Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
4dc85607 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
252b5132 | 36 | |
252b5132 RH |
37 | #ifndef REGISTER_WARNINGS |
38 | #define REGISTER_WARNINGS 1 | |
39 | #endif | |
40 | ||
c3332e24 | 41 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 42 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
43 | #endif |
44 | ||
252b5132 RH |
45 | #ifndef SCALE1_WHEN_NO_INDEX |
46 | /* Specifying a scale factor besides 1 when there is no index is | |
47 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
48 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
49 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
50 | #define SCALE1_WHEN_NO_INDEX 1 | |
51 | #endif | |
52 | ||
29b0f896 AM |
53 | #ifndef DEFAULT_ARCH |
54 | #define DEFAULT_ARCH "i386" | |
246fcdee | 55 | #endif |
252b5132 | 56 | |
edde18a5 AM |
57 | #ifndef INLINE |
58 | #if __GNUC__ >= 2 | |
59 | #define INLINE __inline__ | |
60 | #else | |
61 | #define INLINE | |
62 | #endif | |
63 | #endif | |
64 | ||
e3bb37b5 L |
65 | static void set_code_flag (int); |
66 | static void set_16bit_gcc_code_flag (int); | |
67 | static void set_intel_syntax (int); | |
68 | static void set_cpu_arch (int); | |
6482c264 | 69 | #ifdef TE_PE |
e3bb37b5 | 70 | static void pe_directive_secrel (int); |
6482c264 | 71 | #endif |
e3bb37b5 L |
72 | static void signed_cons (int); |
73 | static char *output_invalid (int c); | |
74 | static int i386_operand (char *); | |
75 | static int i386_intel_operand (char *, int); | |
76 | static const reg_entry *parse_register (char *, char **); | |
77 | static char *parse_insn (char *, char *); | |
78 | static char *parse_operands (char *, const char *); | |
79 | static void swap_operands (void); | |
4d456e3d | 80 | static void swap_2_operands (int, int); |
e3bb37b5 L |
81 | static void optimize_imm (void); |
82 | static void optimize_disp (void); | |
83 | static int match_template (void); | |
84 | static int check_string (void); | |
85 | static int process_suffix (void); | |
86 | static int check_byte_reg (void); | |
87 | static int check_long_reg (void); | |
88 | static int check_qword_reg (void); | |
89 | static int check_word_reg (void); | |
90 | static int finalize_imm (void); | |
91 | static int process_operands (void); | |
92 | static const seg_entry *build_modrm_byte (void); | |
93 | static void output_insn (void); | |
94 | static void output_imm (fragS *, offsetT); | |
95 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 96 | #ifndef I386COFF |
e3bb37b5 | 97 | static void s_bss (int); |
252b5132 | 98 | #endif |
17d4e2a2 L |
99 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
100 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
101 | #endif | |
252b5132 | 102 | |
a847613f | 103 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 104 | |
252b5132 | 105 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 106 | i386_insn. */ |
252b5132 | 107 | |
520dc8e8 AM |
108 | union i386_op |
109 | { | |
110 | expressionS *disps; | |
111 | expressionS *imms; | |
112 | const reg_entry *regs; | |
113 | }; | |
114 | ||
252b5132 RH |
115 | struct _i386_insn |
116 | { | |
47926f60 | 117 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
118 | template tm; |
119 | ||
120 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
121 | (e.g. 'l' for 'movl') */ | |
122 | char suffix; | |
123 | ||
47926f60 | 124 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
125 | unsigned int operands; |
126 | ||
127 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
128 | of given register, displacement, memory operands and immediate | |
47926f60 | 129 | operands. */ |
252b5132 RH |
130 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
131 | ||
132 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 133 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
134 | unsigned int types[MAX_OPERANDS]; |
135 | ||
520dc8e8 AM |
136 | /* Displacement expression, immediate expression, or register for each |
137 | operand. */ | |
138 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 139 | |
3e73aa7c JH |
140 | /* Flags for operands. */ |
141 | unsigned int flags[MAX_OPERANDS]; | |
142 | #define Operand_PCrel 1 | |
143 | ||
252b5132 | 144 | /* Relocation type for operand */ |
f86103b7 | 145 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 146 | |
252b5132 RH |
147 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
148 | the base index byte below. */ | |
149 | const reg_entry *base_reg; | |
150 | const reg_entry *index_reg; | |
151 | unsigned int log2_scale_factor; | |
152 | ||
153 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 154 | explicit segment overrides are given. */ |
ce8a8b2f | 155 | const seg_entry *seg[2]; |
252b5132 RH |
156 | |
157 | /* PREFIX holds all the given prefix opcodes (usually null). | |
158 | PREFIXES is the number of prefix opcodes. */ | |
159 | unsigned int prefixes; | |
160 | unsigned char prefix[MAX_PREFIXES]; | |
161 | ||
162 | /* RM and SIB are the modrm byte and the sib byte where the | |
163 | addressing modes of this insn are encoded. */ | |
164 | ||
165 | modrm_byte rm; | |
3e73aa7c | 166 | rex_byte rex; |
252b5132 RH |
167 | sib_byte sib; |
168 | }; | |
169 | ||
170 | typedef struct _i386_insn i386_insn; | |
171 | ||
172 | /* List of chars besides those in app.c:symbol_chars that can start an | |
173 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 174 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 175 | #ifdef LEX_AT |
32137342 NC |
176 | "@" |
177 | #endif | |
178 | #ifdef LEX_QM | |
179 | "?" | |
252b5132 | 180 | #endif |
32137342 | 181 | ; |
252b5132 | 182 | |
29b0f896 AM |
183 | #if (defined (TE_I386AIX) \ |
184 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 185 | && !defined (TE_GNU) \ |
29b0f896 | 186 | && !defined (TE_LINUX) \ |
32137342 | 187 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
188 | && !defined (TE_FreeBSD) \ |
189 | && !defined (TE_NetBSD))) | |
252b5132 | 190 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
191 | pre-processor is disabled, these aren't very useful. The option |
192 | --divide will remove '/' from this list. */ | |
193 | const char *i386_comment_chars = "#/"; | |
194 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 195 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 196 | |
b3b91714 AM |
197 | #else |
198 | const char *i386_comment_chars = "#"; | |
199 | #define PREFIX_SEPARATOR '/' | |
200 | #endif | |
201 | ||
252b5132 RH |
202 | /* This array holds the chars that only start a comment at the beginning of |
203 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
204 | .line and .file directives will appear in the pre-processed output. |
205 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 206 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
207 | #NO_APP at the beginning of its output. |
208 | Also note that comments started like this one will always work if | |
252b5132 | 209 | '/' isn't otherwise defined. */ |
b3b91714 | 210 | const char line_comment_chars[] = "#/"; |
252b5132 | 211 | |
63a0b638 | 212 | const char line_separator_chars[] = ";"; |
252b5132 | 213 | |
ce8a8b2f AM |
214 | /* Chars that can be used to separate mant from exp in floating point |
215 | nums. */ | |
252b5132 RH |
216 | const char EXP_CHARS[] = "eE"; |
217 | ||
ce8a8b2f AM |
218 | /* Chars that mean this number is a floating point constant |
219 | As in 0f12.456 | |
220 | or 0d1.2345e12. */ | |
252b5132 RH |
221 | const char FLT_CHARS[] = "fFdDxX"; |
222 | ||
ce8a8b2f | 223 | /* Tables for lexical analysis. */ |
252b5132 RH |
224 | static char mnemonic_chars[256]; |
225 | static char register_chars[256]; | |
226 | static char operand_chars[256]; | |
227 | static char identifier_chars[256]; | |
228 | static char digit_chars[256]; | |
229 | ||
ce8a8b2f | 230 | /* Lexical macros. */ |
252b5132 RH |
231 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
232 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
233 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
234 | #define is_space_char(x) ((x) == ' ') | |
235 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
236 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
237 | ||
0234cb7c | 238 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
239 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
240 | ||
241 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
242 | effect this we maintain a stack of saved characters that we've smashed | |
243 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 244 | assembler instruction). */ |
252b5132 | 245 | static char save_stack[32]; |
ce8a8b2f | 246 | static char *save_stack_p; |
252b5132 RH |
247 | #define END_STRING_AND_SAVE(s) \ |
248 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
249 | #define RESTORE_END_STRING(s) \ | |
250 | do { *(s) = *--save_stack_p; } while (0) | |
251 | ||
47926f60 | 252 | /* The instruction we're assembling. */ |
252b5132 RH |
253 | static i386_insn i; |
254 | ||
255 | /* Possible templates for current insn. */ | |
256 | static const templates *current_templates; | |
257 | ||
31b2323c L |
258 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
259 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
260 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 261 | |
47926f60 KH |
262 | /* Current operand we are working on. */ |
263 | static int this_operand; | |
252b5132 | 264 | |
3e73aa7c JH |
265 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
266 | these. */ | |
267 | ||
268 | enum flag_code { | |
269 | CODE_32BIT, | |
270 | CODE_16BIT, | |
271 | CODE_64BIT }; | |
f3c180ae | 272 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
273 | |
274 | static enum flag_code flag_code; | |
4fa24527 | 275 | static unsigned int object_64bit; |
3e73aa7c JH |
276 | static int use_rela_relocations = 0; |
277 | ||
278 | /* The names used to print error messages. */ | |
b77a7acd | 279 | static const char *flag_code_names[] = |
3e73aa7c JH |
280 | { |
281 | "32", | |
282 | "16", | |
283 | "64" | |
284 | }; | |
252b5132 | 285 | |
47926f60 KH |
286 | /* 1 for intel syntax, |
287 | 0 if att syntax. */ | |
288 | static int intel_syntax = 0; | |
252b5132 | 289 | |
47926f60 KH |
290 | /* 1 if register prefix % not required. */ |
291 | static int allow_naked_reg = 0; | |
252b5132 | 292 | |
2ca3ace5 L |
293 | /* Register prefix used for error message. */ |
294 | static const char *register_prefix = "%"; | |
295 | ||
47926f60 KH |
296 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
297 | leave, push, and pop instructions so that gcc has the same stack | |
298 | frame as in 32 bit mode. */ | |
299 | static char stackop_size = '\0'; | |
eecb386c | 300 | |
12b55ccc L |
301 | /* Non-zero to optimize code alignment. */ |
302 | int optimize_align_code = 1; | |
303 | ||
47926f60 KH |
304 | /* Non-zero to quieten some warnings. */ |
305 | static int quiet_warnings = 0; | |
a38cf1db | 306 | |
47926f60 KH |
307 | /* CPU name. */ |
308 | static const char *cpu_arch_name = NULL; | |
5c6af06e | 309 | static const char *cpu_sub_arch_name = NULL; |
a38cf1db | 310 | |
47926f60 | 311 | /* CPU feature flags. */ |
29b0f896 | 312 | static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; |
a38cf1db | 313 | |
ccc9c027 L |
314 | /* If we have selected a cpu we are generating instructions for. */ |
315 | static int cpu_arch_tune_set = 0; | |
316 | ||
9103f4f4 L |
317 | /* Cpu we are generating instructions for. */ |
318 | static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; | |
319 | ||
320 | /* CPU feature flags of cpu we are generating instructions for. */ | |
321 | static unsigned int cpu_arch_tune_flags = 0; | |
322 | ||
ccc9c027 L |
323 | /* CPU instruction set architecture used. */ |
324 | static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; | |
325 | ||
9103f4f4 L |
326 | /* CPU feature flags of instruction set architecture used. */ |
327 | static unsigned int cpu_arch_isa_flags = 0; | |
328 | ||
fddf5b5b AM |
329 | /* If set, conditional jumps are not automatically promoted to handle |
330 | larger than a byte offset. */ | |
331 | static unsigned int no_cond_jump_promotion = 0; | |
332 | ||
29b0f896 | 333 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 334 | static symbolS *GOT_symbol; |
29b0f896 | 335 | |
a4447b93 RH |
336 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
337 | unsigned int x86_dwarf2_return_column; | |
338 | ||
339 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
340 | int x86_cie_data_alignment; | |
341 | ||
252b5132 | 342 | /* Interface to relax_segment. |
fddf5b5b AM |
343 | There are 3 major relax states for 386 jump insns because the |
344 | different types of jumps add different sizes to frags when we're | |
345 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 346 | |
47926f60 | 347 | /* Types. */ |
93c2a809 AM |
348 | #define UNCOND_JUMP 0 |
349 | #define COND_JUMP 1 | |
350 | #define COND_JUMP86 2 | |
fddf5b5b | 351 | |
47926f60 | 352 | /* Sizes. */ |
252b5132 RH |
353 | #define CODE16 1 |
354 | #define SMALL 0 | |
29b0f896 | 355 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 356 | #define BIG 2 |
29b0f896 | 357 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
358 | |
359 | #ifndef INLINE | |
360 | #ifdef __GNUC__ | |
361 | #define INLINE __inline__ | |
362 | #else | |
363 | #define INLINE | |
364 | #endif | |
365 | #endif | |
366 | ||
fddf5b5b AM |
367 | #define ENCODE_RELAX_STATE(type, size) \ |
368 | ((relax_substateT) (((type) << 2) | (size))) | |
369 | #define TYPE_FROM_RELAX_STATE(s) \ | |
370 | ((s) >> 2) | |
371 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
372 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
373 | |
374 | /* This table is used by relax_frag to promote short jumps to long | |
375 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
376 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
377 | don't allow a short jump in a 32 bit code segment to be promoted to | |
378 | a 16 bit offset jump because it's slower (requires data size | |
379 | prefix), and doesn't work, unless the destination is in the bottom | |
380 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
381 | ||
382 | const relax_typeS md_relax_table[] = | |
383 | { | |
24eab124 AM |
384 | /* The fields are: |
385 | 1) most positive reach of this state, | |
386 | 2) most negative reach of this state, | |
93c2a809 | 387 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 388 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 389 | |
fddf5b5b | 390 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
391 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
392 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
393 | /* dword jmp adds 4 bytes to frag: | |
394 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 395 | {0, 0, 4, 0}, |
93c2a809 AM |
396 | /* word jmp adds 2 byte2 to frag: |
397 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
398 | {0, 0, 2, 0}, |
399 | ||
93c2a809 AM |
400 | /* COND_JUMP states. */ |
401 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
402 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
403 | /* dword conditionals adds 5 bytes to frag: | |
404 | 1 extra opcode byte, 4 displacement bytes. */ | |
405 | {0, 0, 5, 0}, | |
fddf5b5b | 406 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
407 | 1 extra opcode byte, 2 displacement bytes. */ |
408 | {0, 0, 3, 0}, | |
409 | ||
410 | /* COND_JUMP86 states. */ | |
411 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
412 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
413 | /* dword conditionals adds 5 bytes to frag: | |
414 | 1 extra opcode byte, 4 displacement bytes. */ | |
415 | {0, 0, 5, 0}, | |
416 | /* word conditionals add 4 bytes to frag: | |
417 | 1 displacement byte and a 3 byte long branch insn. */ | |
418 | {0, 0, 4, 0} | |
252b5132 RH |
419 | }; |
420 | ||
9103f4f4 L |
421 | static const arch_entry cpu_arch[] = |
422 | { | |
423 | {"generic32", PROCESSOR_GENERIC32, | |
d32cad65 | 424 | Cpu186|Cpu286|Cpu386}, |
9103f4f4 | 425 | {"generic64", PROCESSOR_GENERIC64, |
d32cad65 | 426 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX |
9103f4f4 L |
427 | |CpuMMX2|CpuSSE|CpuSSE2}, |
428 | {"i8086", PROCESSOR_UNKNOWN, | |
d32cad65 | 429 | 0}, |
9103f4f4 | 430 | {"i186", PROCESSOR_UNKNOWN, |
d32cad65 | 431 | Cpu186}, |
9103f4f4 | 432 | {"i286", PROCESSOR_UNKNOWN, |
d32cad65 | 433 | Cpu186|Cpu286}, |
9103f4f4 | 434 | {"i386", PROCESSOR_GENERIC32, |
d32cad65 | 435 | Cpu186|Cpu286|Cpu386}, |
9103f4f4 | 436 | {"i486", PROCESSOR_I486, |
d32cad65 | 437 | Cpu186|Cpu286|Cpu386|Cpu486}, |
9103f4f4 | 438 | {"i586", PROCESSOR_PENTIUM, |
d32cad65 | 439 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586}, |
9103f4f4 | 440 | {"i686", PROCESSOR_PENTIUMPRO, |
d32cad65 | 441 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686}, |
9103f4f4 | 442 | {"pentium", PROCESSOR_PENTIUM, |
d32cad65 | 443 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586}, |
9103f4f4 | 444 | {"pentiumpro",PROCESSOR_PENTIUMPRO, |
d32cad65 | 445 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686}, |
9103f4f4 | 446 | {"pentiumii", PROCESSOR_PENTIUMPRO, |
d32cad65 | 447 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX}, |
9103f4f4 | 448 | {"pentiumiii",PROCESSOR_PENTIUMPRO, |
d32cad65 | 449 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE}, |
9103f4f4 | 450 | {"pentium4", PROCESSOR_PENTIUM4, |
d32cad65 | 451 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX |
9103f4f4 L |
452 | |CpuMMX2|CpuSSE|CpuSSE2}, |
453 | {"prescott", PROCESSOR_NOCONA, | |
d32cad65 | 454 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX |
9103f4f4 L |
455 | |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, |
456 | {"nocona", PROCESSOR_NOCONA, | |
d32cad65 | 457 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX |
9103f4f4 | 458 | |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, |
ef05d495 | 459 | {"yonah", PROCESSOR_CORE, |
d32cad65 | 460 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX |
9103f4f4 | 461 | |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, |
ef05d495 | 462 | {"core", PROCESSOR_CORE, |
d32cad65 | 463 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX |
ef05d495 L |
464 | |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, |
465 | {"merom", PROCESSOR_CORE2, | |
466 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX | |
467 | |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3}, | |
468 | {"core2", PROCESSOR_CORE2, | |
469 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX | |
470 | |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3}, | |
9103f4f4 | 471 | {"k6", PROCESSOR_K6, |
d32cad65 | 472 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX}, |
9103f4f4 | 473 | {"k6_2", PROCESSOR_K6, |
d32cad65 | 474 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow}, |
9103f4f4 | 475 | {"athlon", PROCESSOR_ATHLON, |
d32cad65 | 476 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 |
9103f4f4 L |
477 | |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA}, |
478 | {"sledgehammer", PROCESSOR_K8, | |
d32cad65 | 479 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 |
9103f4f4 L |
480 | |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2}, |
481 | {"opteron", PROCESSOR_K8, | |
d32cad65 | 482 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 |
9103f4f4 L |
483 | |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2}, |
484 | {"k8", PROCESSOR_K8, | |
d32cad65 | 485 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 |
9103f4f4 | 486 | |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2}, |
050dfa73 | 487 | {"amdfam10", PROCESSOR_AMDFAM10, |
d32cad65 L |
488 | Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer |
489 | |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a | |
490 | |CpuABM}, | |
9103f4f4 L |
491 | {".mmx", PROCESSOR_UNKNOWN, |
492 | CpuMMX}, | |
493 | {".sse", PROCESSOR_UNKNOWN, | |
494 | CpuMMX|CpuMMX2|CpuSSE}, | |
495 | {".sse2", PROCESSOR_UNKNOWN, | |
496 | CpuMMX|CpuMMX2|CpuSSE|CpuSSE2}, | |
497 | {".sse3", PROCESSOR_UNKNOWN, | |
498 | CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, | |
ef05d495 L |
499 | {".ssse3", PROCESSOR_UNKNOWN, |
500 | CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3}, | |
9103f4f4 L |
501 | {".3dnow", PROCESSOR_UNKNOWN, |
502 | CpuMMX|Cpu3dnow}, | |
503 | {".3dnowa", PROCESSOR_UNKNOWN, | |
504 | CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA}, | |
505 | {".padlock", PROCESSOR_UNKNOWN, | |
506 | CpuPadLock}, | |
507 | {".pacifica", PROCESSOR_UNKNOWN, | |
508 | CpuSVME}, | |
509 | {".svme", PROCESSOR_UNKNOWN, | |
050dfa73 MM |
510 | CpuSVME}, |
511 | {".sse4a", PROCESSOR_UNKNOWN, | |
512 | CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a}, | |
513 | {".abm", PROCESSOR_UNKNOWN, | |
514 | CpuABM} | |
e413e4e9 AM |
515 | }; |
516 | ||
29b0f896 AM |
517 | const pseudo_typeS md_pseudo_table[] = |
518 | { | |
519 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
520 | {"align", s_align_bytes, 0}, | |
521 | #else | |
522 | {"align", s_align_ptwo, 0}, | |
523 | #endif | |
524 | {"arch", set_cpu_arch, 0}, | |
525 | #ifndef I386COFF | |
526 | {"bss", s_bss, 0}, | |
527 | #endif | |
528 | {"ffloat", float_cons, 'f'}, | |
529 | {"dfloat", float_cons, 'd'}, | |
530 | {"tfloat", float_cons, 'x'}, | |
531 | {"value", cons, 2}, | |
d182319b | 532 | {"slong", signed_cons, 4}, |
29b0f896 AM |
533 | {"noopt", s_ignore, 0}, |
534 | {"optim", s_ignore, 0}, | |
535 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
536 | {"code16", set_code_flag, CODE_16BIT}, | |
537 | {"code32", set_code_flag, CODE_32BIT}, | |
538 | {"code64", set_code_flag, CODE_64BIT}, | |
539 | {"intel_syntax", set_intel_syntax, 1}, | |
540 | {"att_syntax", set_intel_syntax, 0}, | |
3b22753a L |
541 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
542 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 543 | #else |
e3bb37b5 | 544 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
545 | {"loc", dwarf2_directive_loc, 0}, |
546 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 547 | #endif |
6482c264 NC |
548 | #ifdef TE_PE |
549 | {"secrel32", pe_directive_secrel, 0}, | |
550 | #endif | |
29b0f896 AM |
551 | {0, 0, 0} |
552 | }; | |
553 | ||
554 | /* For interface with expression (). */ | |
555 | extern char *input_line_pointer; | |
556 | ||
557 | /* Hash table for instruction mnemonic lookup. */ | |
558 | static struct hash_control *op_hash; | |
559 | ||
560 | /* Hash table for register lookup. */ | |
561 | static struct hash_control *reg_hash; | |
562 | \f | |
252b5132 | 563 | void |
e3bb37b5 | 564 | i386_align_code (fragS *fragP, int count) |
252b5132 | 565 | { |
ce8a8b2f AM |
566 | /* Various efficient no-op patterns for aligning code labels. |
567 | Note: Don't try to assemble the instructions in the comments. | |
568 | 0L and 0w are not legal. */ | |
252b5132 RH |
569 | static const char f32_1[] = |
570 | {0x90}; /* nop */ | |
571 | static const char f32_2[] = | |
ccc9c027 | 572 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
573 | static const char f32_3[] = |
574 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
575 | static const char f32_4[] = | |
576 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
577 | static const char f32_5[] = | |
578 | {0x90, /* nop */ | |
579 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
580 | static const char f32_6[] = | |
581 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
582 | static const char f32_7[] = | |
583 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
584 | static const char f32_8[] = | |
585 | {0x90, /* nop */ | |
586 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
587 | static const char f32_9[] = | |
588 | {0x89,0xf6, /* movl %esi,%esi */ | |
589 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
590 | static const char f32_10[] = | |
591 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
592 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
593 | static const char f32_11[] = | |
594 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
595 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
596 | static const char f32_12[] = | |
597 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
598 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
599 | static const char f32_13[] = | |
600 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
601 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
602 | static const char f32_14[] = | |
603 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
604 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
605 | static const char f32_15[] = | |
606 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
607 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
608 | static const char f16_3[] = |
609 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
610 | static const char f16_4[] = |
611 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
612 | static const char f16_5[] = | |
613 | {0x90, /* nop */ | |
614 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
615 | static const char f16_6[] = | |
616 | {0x89,0xf6, /* mov %si,%si */ | |
617 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
618 | static const char f16_7[] = | |
619 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
620 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
621 | static const char f16_8[] = | |
622 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
623 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
624 | static const char *const f32_patt[] = { | |
625 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
626 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
627 | }; | |
628 | static const char *const f16_patt[] = { | |
c3332e24 | 629 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
630 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
631 | }; | |
ccc9c027 L |
632 | /* nopl (%[re]ax) */ |
633 | static const char alt_3[] = | |
634 | {0x0f,0x1f,0x00}; | |
635 | /* nopl 0(%[re]ax) */ | |
636 | static const char alt_4[] = | |
637 | {0x0f,0x1f,0x40,0x00}; | |
638 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
639 | static const char alt_5[] = | |
640 | {0x0f,0x1f,0x44,0x00,0x00}; | |
641 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
642 | static const char alt_6[] = | |
643 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
644 | /* nopl 0L(%[re]ax) */ | |
645 | static const char alt_7[] = | |
646 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
647 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
648 | static const char alt_8[] = | |
649 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
650 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
651 | static const char alt_9[] = | |
652 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
653 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
654 | static const char alt_10[] = | |
655 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
656 | /* data16 | |
657 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
658 | static const char alt_long_11[] = | |
659 | {0x66, | |
660 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
661 | /* data16 | |
662 | data16 | |
663 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
664 | static const char alt_long_12[] = | |
665 | {0x66, | |
666 | 0x66, | |
667 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
668 | /* data16 | |
669 | data16 | |
670 | data16 | |
671 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
672 | static const char alt_long_13[] = | |
673 | {0x66, | |
674 | 0x66, | |
675 | 0x66, | |
676 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
677 | /* data16 | |
678 | data16 | |
679 | data16 | |
680 | data16 | |
681 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
682 | static const char alt_long_14[] = | |
683 | {0x66, | |
684 | 0x66, | |
685 | 0x66, | |
686 | 0x66, | |
687 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
688 | /* data16 | |
689 | data16 | |
690 | data16 | |
691 | data16 | |
692 | data16 | |
693 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
694 | static const char alt_long_15[] = | |
695 | {0x66, | |
696 | 0x66, | |
697 | 0x66, | |
698 | 0x66, | |
699 | 0x66, | |
700 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
701 | /* nopl 0(%[re]ax,%[re]ax,1) | |
702 | nopw 0(%[re]ax,%[re]ax,1) */ | |
703 | static const char alt_short_11[] = | |
704 | {0x0f,0x1f,0x44,0x00,0x00, | |
705 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
706 | /* nopw 0(%[re]ax,%[re]ax,1) | |
707 | nopw 0(%[re]ax,%[re]ax,1) */ | |
708 | static const char alt_short_12[] = | |
709 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
710 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
711 | /* nopw 0(%[re]ax,%[re]ax,1) | |
712 | nopl 0L(%[re]ax) */ | |
713 | static const char alt_short_13[] = | |
714 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
715 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
716 | /* nopl 0L(%[re]ax) | |
717 | nopl 0L(%[re]ax) */ | |
718 | static const char alt_short_14[] = | |
719 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
720 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
721 | /* nopl 0L(%[re]ax) | |
722 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
723 | static const char alt_short_15[] = | |
724 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
725 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
726 | static const char *const alt_short_patt[] = { | |
727 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
728 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
729 | alt_short_14, alt_short_15 | |
730 | }; | |
731 | static const char *const alt_long_patt[] = { | |
732 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
733 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
734 | alt_long_14, alt_long_15 | |
735 | }; | |
252b5132 | 736 | |
33fef721 JH |
737 | if (count <= 0 || count > 15) |
738 | return; | |
3e73aa7c | 739 | |
ccc9c027 L |
740 | /* We need to decide which NOP sequence to use for 32bit and |
741 | 64bit. When -mtune= is used: | |
4eed87de | 742 | |
ccc9c027 L |
743 | 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32, |
744 | f32_patt will be used. | |
4eed87de AM |
745 | 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with |
746 | 0x66 prefix will be used. | |
ef05d495 | 747 | 3. For PROCESSOR_CORE2, alt_long_patt will be used. |
ccc9c027 | 748 | 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, |
ef05d495 | 749 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON |
ccc9c027 L |
750 | and PROCESSOR_GENERIC64, alt_short_patt will be used. |
751 | ||
752 | When -mtune= isn't used, alt_short_patt will be used if | |
753 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used. | |
754 | ||
755 | When -march= or .arch is used, we can't use anything beyond | |
756 | cpu_arch_isa_flags. */ | |
757 | ||
758 | if (flag_code == CODE_16BIT) | |
759 | { | |
760 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
761 | f16_patt[count - 1], count); | |
762 | if (count > 8) | |
763 | /* Adjust jump offset. */ | |
764 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
765 | } | |
766 | else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8) | |
252b5132 | 767 | { |
33fef721 JH |
768 | int i; |
769 | int nnops = (count + 3) / 4; | |
770 | int len = count / nnops; | |
771 | int remains = count - nnops * len; | |
772 | int pos = 0; | |
773 | ||
ccc9c027 | 774 | /* The recommended way to pad 64bit code is to use NOPs preceded |
4eed87de | 775 | by maximally four 0x66 prefixes. Balance the size of nops. */ |
33fef721 | 776 | for (i = 0; i < remains; i++) |
252b5132 | 777 | { |
33fef721 JH |
778 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); |
779 | fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; | |
780 | pos += len + 1; | |
781 | } | |
782 | for (; i < nnops; i++) | |
783 | { | |
784 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); | |
785 | fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; | |
786 | pos += len; | |
252b5132 | 787 | } |
252b5132 | 788 | } |
33fef721 | 789 | else |
ccc9c027 L |
790 | { |
791 | const char *const *patt = NULL; | |
792 | ||
793 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
794 | { | |
795 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
796 | switch (cpu_arch_tune) | |
797 | { | |
798 | case PROCESSOR_UNKNOWN: | |
799 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
800 | optimize for Cpu686. */ | |
801 | if ((cpu_arch_isa_flags & Cpu686) != 0) | |
802 | patt = alt_short_patt; | |
803 | else | |
804 | patt = f32_patt; | |
805 | break; | |
ef05d495 | 806 | case PROCESSOR_CORE2: |
ccc9c027 L |
807 | patt = alt_long_patt; |
808 | break; | |
809 | case PROCESSOR_PENTIUMPRO: | |
810 | case PROCESSOR_PENTIUM4: | |
811 | case PROCESSOR_NOCONA: | |
ef05d495 | 812 | case PROCESSOR_CORE: |
ccc9c027 L |
813 | case PROCESSOR_K6: |
814 | case PROCESSOR_ATHLON: | |
815 | case PROCESSOR_K8: | |
816 | case PROCESSOR_GENERIC64: | |
4eed87de | 817 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
818 | patt = alt_short_patt; |
819 | break; | |
820 | case PROCESSOR_I486: | |
821 | case PROCESSOR_PENTIUM: | |
822 | case PROCESSOR_GENERIC32: | |
823 | patt = f32_patt; | |
824 | break; | |
4eed87de | 825 | } |
ccc9c027 L |
826 | } |
827 | else | |
828 | { | |
829 | switch (cpu_arch_tune) | |
830 | { | |
831 | case PROCESSOR_UNKNOWN: | |
832 | /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be | |
833 | PROCESSOR_UNKNOWN. */ | |
834 | abort (); | |
835 | break; | |
836 | ||
837 | case PROCESSOR_I486: | |
838 | case PROCESSOR_PENTIUM: | |
839 | case PROCESSOR_PENTIUMPRO: | |
840 | case PROCESSOR_PENTIUM4: | |
841 | case PROCESSOR_NOCONA: | |
ef05d495 | 842 | case PROCESSOR_CORE: |
ccc9c027 L |
843 | case PROCESSOR_K6: |
844 | case PROCESSOR_ATHLON: | |
845 | case PROCESSOR_K8: | |
4eed87de | 846 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
847 | case PROCESSOR_GENERIC32: |
848 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
849 | for Cpu686. */ | |
850 | if ((cpu_arch_isa_flags & Cpu686) != 0) | |
851 | patt = alt_short_patt; | |
852 | else | |
853 | patt = f32_patt; | |
854 | break; | |
ef05d495 | 855 | case PROCESSOR_CORE2: |
ccc9c027 L |
856 | if ((cpu_arch_isa_flags & Cpu686) != 0) |
857 | patt = alt_long_patt; | |
858 | else | |
859 | patt = f32_patt; | |
860 | break; | |
861 | case PROCESSOR_GENERIC64: | |
862 | patt = alt_short_patt; | |
863 | break; | |
4eed87de | 864 | } |
ccc9c027 L |
865 | } |
866 | ||
33fef721 | 867 | memcpy (fragP->fr_literal + fragP->fr_fix, |
ccc9c027 L |
868 | patt[count - 1], count); |
869 | } | |
33fef721 | 870 | fragP->fr_var = count; |
252b5132 RH |
871 | } |
872 | ||
252b5132 | 873 | static INLINE unsigned int |
e3bb37b5 | 874 | mode_from_disp_size (unsigned int t) |
252b5132 | 875 | { |
3e73aa7c | 876 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
877 | } |
878 | ||
879 | static INLINE int | |
e3bb37b5 | 880 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
881 | { |
882 | return (num >= -128) && (num <= 127); | |
47926f60 | 883 | } |
252b5132 RH |
884 | |
885 | static INLINE int | |
e3bb37b5 | 886 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
887 | { |
888 | return (num & 0xff) == num; | |
47926f60 | 889 | } |
252b5132 RH |
890 | |
891 | static INLINE int | |
e3bb37b5 | 892 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
893 | { |
894 | return (num & 0xffff) == num; | |
47926f60 | 895 | } |
252b5132 RH |
896 | |
897 | static INLINE int | |
e3bb37b5 | 898 | fits_in_signed_word (offsetT num) |
252b5132 RH |
899 | { |
900 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 901 | } |
2a962e6d | 902 | |
3e73aa7c | 903 | static INLINE int |
e3bb37b5 | 904 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
905 | { |
906 | #ifndef BFD64 | |
907 | return 1; | |
908 | #else | |
909 | return (!(((offsetT) -1 << 31) & num) | |
910 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
911 | #endif | |
912 | } /* fits_in_signed_long() */ | |
2a962e6d | 913 | |
3e73aa7c | 914 | static INLINE int |
e3bb37b5 | 915 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
916 | { |
917 | #ifndef BFD64 | |
918 | return 1; | |
919 | #else | |
920 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
921 | #endif | |
922 | } /* fits_in_unsigned_long() */ | |
252b5132 | 923 | |
1509aa9a | 924 | static unsigned int |
e3bb37b5 | 925 | smallest_imm_type (offsetT num) |
252b5132 | 926 | { |
d32cad65 | 927 | if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) |
e413e4e9 AM |
928 | { |
929 | /* This code is disabled on the 486 because all the Imm1 forms | |
930 | in the opcode table are slower on the i486. They're the | |
931 | versions with the implicitly specified single-position | |
932 | displacement, which has another syntax if you really want to | |
933 | use that form. */ | |
934 | if (num == 1) | |
3e73aa7c | 935 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 936 | } |
252b5132 | 937 | return (fits_in_signed_byte (num) |
3e73aa7c | 938 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 939 | : fits_in_unsigned_byte (num) |
3e73aa7c | 940 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 941 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
942 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
943 | : fits_in_signed_long (num) | |
944 | ? (Imm32 | Imm32S | Imm64) | |
945 | : fits_in_unsigned_long (num) | |
946 | ? (Imm32 | Imm64) | |
947 | : Imm64); | |
47926f60 | 948 | } |
252b5132 | 949 | |
847f7ad4 | 950 | static offsetT |
e3bb37b5 | 951 | offset_in_range (offsetT val, int size) |
847f7ad4 | 952 | { |
508866be | 953 | addressT mask; |
ba2adb93 | 954 | |
847f7ad4 AM |
955 | switch (size) |
956 | { | |
508866be L |
957 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
958 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 959 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
960 | #ifdef BFD64 |
961 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
962 | #endif | |
47926f60 | 963 | default: abort (); |
847f7ad4 AM |
964 | } |
965 | ||
ba2adb93 | 966 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
967 | if (!use_rela_relocations) |
968 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
969 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 970 | |
47926f60 | 971 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
972 | { |
973 | char buf1[40], buf2[40]; | |
974 | ||
975 | sprint_value (buf1, val); | |
976 | sprint_value (buf2, val & mask); | |
977 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
978 | } | |
979 | return val & mask; | |
980 | } | |
981 | ||
252b5132 RH |
982 | /* Returns 0 if attempting to add a prefix where one from the same |
983 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
984 | added. */ | |
985 | static int | |
e3bb37b5 | 986 | add_prefix (unsigned int prefix) |
252b5132 RH |
987 | { |
988 | int ret = 1; | |
b1905489 | 989 | unsigned int q; |
252b5132 | 990 | |
29b0f896 AM |
991 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
992 | && flag_code == CODE_64BIT) | |
b1905489 JB |
993 | { |
994 | if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64) | |
995 | || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ)) | |
996 | && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ)))) | |
997 | ret = 0; | |
998 | q = REX_PREFIX; | |
999 | } | |
3e73aa7c | 1000 | else |
b1905489 JB |
1001 | { |
1002 | switch (prefix) | |
1003 | { | |
1004 | default: | |
1005 | abort (); | |
1006 | ||
1007 | case CS_PREFIX_OPCODE: | |
1008 | case DS_PREFIX_OPCODE: | |
1009 | case ES_PREFIX_OPCODE: | |
1010 | case FS_PREFIX_OPCODE: | |
1011 | case GS_PREFIX_OPCODE: | |
1012 | case SS_PREFIX_OPCODE: | |
1013 | q = SEG_PREFIX; | |
1014 | break; | |
1015 | ||
1016 | case REPNE_PREFIX_OPCODE: | |
1017 | case REPE_PREFIX_OPCODE: | |
1018 | ret = 2; | |
1019 | /* fall thru */ | |
1020 | case LOCK_PREFIX_OPCODE: | |
1021 | q = LOCKREP_PREFIX; | |
1022 | break; | |
1023 | ||
1024 | case FWAIT_OPCODE: | |
1025 | q = WAIT_PREFIX; | |
1026 | break; | |
1027 | ||
1028 | case ADDR_PREFIX_OPCODE: | |
1029 | q = ADDR_PREFIX; | |
1030 | break; | |
1031 | ||
1032 | case DATA_PREFIX_OPCODE: | |
1033 | q = DATA_PREFIX; | |
1034 | break; | |
1035 | } | |
1036 | if (i.prefix[q] != 0) | |
1037 | ret = 0; | |
1038 | } | |
252b5132 | 1039 | |
b1905489 | 1040 | if (ret) |
252b5132 | 1041 | { |
b1905489 JB |
1042 | if (!i.prefix[q]) |
1043 | ++i.prefixes; | |
1044 | i.prefix[q] |= prefix; | |
252b5132 | 1045 | } |
b1905489 JB |
1046 | else |
1047 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1048 | |
252b5132 RH |
1049 | return ret; |
1050 | } | |
1051 | ||
1052 | static void | |
e3bb37b5 | 1053 | set_code_flag (int value) |
eecb386c | 1054 | { |
3e73aa7c JH |
1055 | flag_code = value; |
1056 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
1057 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
1058 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
1059 | { | |
1060 | as_bad (_("64bit mode not supported on this CPU.")); | |
1061 | } | |
1062 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
1063 | { | |
1064 | as_bad (_("32bit mode not supported on this CPU.")); | |
1065 | } | |
eecb386c AM |
1066 | stackop_size = '\0'; |
1067 | } | |
1068 | ||
1069 | static void | |
e3bb37b5 | 1070 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1071 | { |
3e73aa7c JH |
1072 | flag_code = new_code_flag; |
1073 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
1074 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
9306ca4a | 1075 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1076 | } |
1077 | ||
1078 | static void | |
e3bb37b5 | 1079 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1080 | { |
1081 | /* Find out if register prefixing is specified. */ | |
1082 | int ask_naked_reg = 0; | |
1083 | ||
1084 | SKIP_WHITESPACE (); | |
29b0f896 | 1085 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1086 | { |
1087 | char *string = input_line_pointer; | |
1088 | int e = get_symbol_end (); | |
1089 | ||
47926f60 | 1090 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1091 | ask_naked_reg = 1; |
47926f60 | 1092 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1093 | ask_naked_reg = -1; |
1094 | else | |
d0b47220 | 1095 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1096 | *input_line_pointer = e; |
1097 | } | |
1098 | demand_empty_rest_of_line (); | |
c3332e24 | 1099 | |
252b5132 RH |
1100 | intel_syntax = syntax_flag; |
1101 | ||
1102 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1103 | allow_naked_reg = (intel_syntax |
1104 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1105 | else |
1106 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1107 | |
e4a3b5a4 | 1108 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1109 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1110 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1111 | } |
1112 | ||
e413e4e9 | 1113 | static void |
e3bb37b5 | 1114 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1115 | { |
47926f60 | 1116 | SKIP_WHITESPACE (); |
e413e4e9 | 1117 | |
29b0f896 | 1118 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1119 | { |
1120 | char *string = input_line_pointer; | |
1121 | int e = get_symbol_end (); | |
9103f4f4 | 1122 | unsigned int i; |
e413e4e9 | 1123 | |
9103f4f4 | 1124 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
1125 | { |
1126 | if (strcmp (string, cpu_arch[i].name) == 0) | |
1127 | { | |
5c6af06e JB |
1128 | if (*string != '.') |
1129 | { | |
1130 | cpu_arch_name = cpu_arch[i].name; | |
1131 | cpu_sub_arch_name = NULL; | |
1132 | cpu_arch_flags = (cpu_arch[i].flags | |
4eed87de AM |
1133 | | (flag_code == CODE_64BIT |
1134 | ? Cpu64 : CpuNo64)); | |
ccc9c027 | 1135 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 1136 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
1137 | if (!cpu_arch_tune_set) |
1138 | { | |
1139 | cpu_arch_tune = cpu_arch_isa; | |
1140 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
1141 | } | |
5c6af06e JB |
1142 | break; |
1143 | } | |
1144 | if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags) | |
1145 | { | |
1146 | cpu_sub_arch_name = cpu_arch[i].name; | |
1147 | cpu_arch_flags |= cpu_arch[i].flags; | |
1148 | } | |
1149 | *input_line_pointer = e; | |
1150 | demand_empty_rest_of_line (); | |
1151 | return; | |
e413e4e9 AM |
1152 | } |
1153 | } | |
9103f4f4 | 1154 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
1155 | as_bad (_("no such architecture: `%s'"), string); |
1156 | ||
1157 | *input_line_pointer = e; | |
1158 | } | |
1159 | else | |
1160 | as_bad (_("missing cpu architecture")); | |
1161 | ||
fddf5b5b AM |
1162 | no_cond_jump_promotion = 0; |
1163 | if (*input_line_pointer == ',' | |
29b0f896 | 1164 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
1165 | { |
1166 | char *string = ++input_line_pointer; | |
1167 | int e = get_symbol_end (); | |
1168 | ||
1169 | if (strcmp (string, "nojumps") == 0) | |
1170 | no_cond_jump_promotion = 1; | |
1171 | else if (strcmp (string, "jumps") == 0) | |
1172 | ; | |
1173 | else | |
1174 | as_bad (_("no such architecture modifier: `%s'"), string); | |
1175 | ||
1176 | *input_line_pointer = e; | |
1177 | } | |
1178 | ||
e413e4e9 AM |
1179 | demand_empty_rest_of_line (); |
1180 | } | |
1181 | ||
b9d79e03 JH |
1182 | unsigned long |
1183 | i386_mach () | |
1184 | { | |
1185 | if (!strcmp (default_arch, "x86_64")) | |
1186 | return bfd_mach_x86_64; | |
1187 | else if (!strcmp (default_arch, "i386")) | |
1188 | return bfd_mach_i386_i386; | |
1189 | else | |
1190 | as_fatal (_("Unknown architecture")); | |
1191 | } | |
b9d79e03 | 1192 | \f |
252b5132 RH |
1193 | void |
1194 | md_begin () | |
1195 | { | |
1196 | const char *hash_err; | |
1197 | ||
47926f60 | 1198 | /* Initialize op_hash hash table. */ |
252b5132 RH |
1199 | op_hash = hash_new (); |
1200 | ||
1201 | { | |
29b0f896 AM |
1202 | const template *optab; |
1203 | templates *core_optab; | |
252b5132 | 1204 | |
47926f60 KH |
1205 | /* Setup for loop. */ |
1206 | optab = i386_optab; | |
252b5132 RH |
1207 | core_optab = (templates *) xmalloc (sizeof (templates)); |
1208 | core_optab->start = optab; | |
1209 | ||
1210 | while (1) | |
1211 | { | |
1212 | ++optab; | |
1213 | if (optab->name == NULL | |
1214 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
1215 | { | |
1216 | /* different name --> ship out current template list; | |
47926f60 | 1217 | add to hash table; & begin anew. */ |
252b5132 RH |
1218 | core_optab->end = optab; |
1219 | hash_err = hash_insert (op_hash, | |
1220 | (optab - 1)->name, | |
1221 | (PTR) core_optab); | |
1222 | if (hash_err) | |
1223 | { | |
252b5132 RH |
1224 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
1225 | (optab - 1)->name, | |
1226 | hash_err); | |
1227 | } | |
1228 | if (optab->name == NULL) | |
1229 | break; | |
1230 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
1231 | core_optab->start = optab; | |
1232 | } | |
1233 | } | |
1234 | } | |
1235 | ||
47926f60 | 1236 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
1237 | reg_hash = hash_new (); |
1238 | { | |
29b0f896 | 1239 | const reg_entry *regtab; |
c3fe08fa | 1240 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 1241 | |
c3fe08fa | 1242 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 RH |
1243 | { |
1244 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
1245 | if (hash_err) | |
3e73aa7c JH |
1246 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
1247 | regtab->reg_name, | |
1248 | hash_err); | |
252b5132 RH |
1249 | } |
1250 | } | |
1251 | ||
47926f60 | 1252 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 1253 | { |
29b0f896 AM |
1254 | int c; |
1255 | char *p; | |
252b5132 RH |
1256 | |
1257 | for (c = 0; c < 256; c++) | |
1258 | { | |
3882b010 | 1259 | if (ISDIGIT (c)) |
252b5132 RH |
1260 | { |
1261 | digit_chars[c] = c; | |
1262 | mnemonic_chars[c] = c; | |
1263 | register_chars[c] = c; | |
1264 | operand_chars[c] = c; | |
1265 | } | |
3882b010 | 1266 | else if (ISLOWER (c)) |
252b5132 RH |
1267 | { |
1268 | mnemonic_chars[c] = c; | |
1269 | register_chars[c] = c; | |
1270 | operand_chars[c] = c; | |
1271 | } | |
3882b010 | 1272 | else if (ISUPPER (c)) |
252b5132 | 1273 | { |
3882b010 | 1274 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
1275 | register_chars[c] = mnemonic_chars[c]; |
1276 | operand_chars[c] = c; | |
1277 | } | |
1278 | ||
3882b010 | 1279 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
1280 | identifier_chars[c] = c; |
1281 | else if (c >= 128) | |
1282 | { | |
1283 | identifier_chars[c] = c; | |
1284 | operand_chars[c] = c; | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | #ifdef LEX_AT | |
1289 | identifier_chars['@'] = '@'; | |
32137342 NC |
1290 | #endif |
1291 | #ifdef LEX_QM | |
1292 | identifier_chars['?'] = '?'; | |
1293 | operand_chars['?'] = '?'; | |
252b5132 | 1294 | #endif |
252b5132 | 1295 | digit_chars['-'] = '-'; |
791fe849 | 1296 | mnemonic_chars['-'] = '-'; |
252b5132 RH |
1297 | identifier_chars['_'] = '_'; |
1298 | identifier_chars['.'] = '.'; | |
1299 | ||
1300 | for (p = operand_special_chars; *p != '\0'; p++) | |
1301 | operand_chars[(unsigned char) *p] = *p; | |
1302 | } | |
1303 | ||
1304 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 1305 | if (IS_ELF) |
252b5132 RH |
1306 | { |
1307 | record_alignment (text_section, 2); | |
1308 | record_alignment (data_section, 2); | |
1309 | record_alignment (bss_section, 2); | |
1310 | } | |
1311 | #endif | |
a4447b93 RH |
1312 | |
1313 | if (flag_code == CODE_64BIT) | |
1314 | { | |
1315 | x86_dwarf2_return_column = 16; | |
1316 | x86_cie_data_alignment = -8; | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | x86_dwarf2_return_column = 8; | |
1321 | x86_cie_data_alignment = -4; | |
1322 | } | |
252b5132 RH |
1323 | } |
1324 | ||
1325 | void | |
e3bb37b5 | 1326 | i386_print_statistics (FILE *file) |
252b5132 RH |
1327 | { |
1328 | hash_print_statistics (file, "i386 opcode", op_hash); | |
1329 | hash_print_statistics (file, "i386 register", reg_hash); | |
1330 | } | |
1331 | \f | |
252b5132 RH |
1332 | #ifdef DEBUG386 |
1333 | ||
ce8a8b2f | 1334 | /* Debugging routines for md_assemble. */ |
e3bb37b5 L |
1335 | static void pte (template *); |
1336 | static void pt (unsigned int); | |
1337 | static void pe (expressionS *); | |
1338 | static void ps (symbolS *); | |
252b5132 RH |
1339 | |
1340 | static void | |
e3bb37b5 | 1341 | pi (char *line, i386_insn *x) |
252b5132 | 1342 | { |
09f131f2 | 1343 | unsigned int i; |
252b5132 RH |
1344 | |
1345 | fprintf (stdout, "%s: template ", line); | |
1346 | pte (&x->tm); | |
09f131f2 JH |
1347 | fprintf (stdout, " address: base %s index %s scale %x\n", |
1348 | x->base_reg ? x->base_reg->reg_name : "none", | |
1349 | x->index_reg ? x->index_reg->reg_name : "none", | |
1350 | x->log2_scale_factor); | |
1351 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 1352 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
1353 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
1354 | x->sib.base, x->sib.index, x->sib.scale); | |
1355 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
29b0f896 AM |
1356 | (x->rex & REX_MODE64) != 0, |
1357 | (x->rex & REX_EXTX) != 0, | |
1358 | (x->rex & REX_EXTY) != 0, | |
1359 | (x->rex & REX_EXTZ) != 0); | |
252b5132 RH |
1360 | for (i = 0; i < x->operands; i++) |
1361 | { | |
1362 | fprintf (stdout, " #%d: ", i + 1); | |
1363 | pt (x->types[i]); | |
1364 | fprintf (stdout, "\n"); | |
1365 | if (x->types[i] | |
3f4438ab | 1366 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 1367 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 1368 | if (x->types[i] & Imm) |
520dc8e8 | 1369 | pe (x->op[i].imms); |
252b5132 | 1370 | if (x->types[i] & Disp) |
520dc8e8 | 1371 | pe (x->op[i].disps); |
252b5132 RH |
1372 | } |
1373 | } | |
1374 | ||
1375 | static void | |
e3bb37b5 | 1376 | pte (template *t) |
252b5132 | 1377 | { |
09f131f2 | 1378 | unsigned int i; |
252b5132 | 1379 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1380 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1381 | if (t->extension_opcode != None) |
1382 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1383 | if (t->opcode_modifier & D) | |
1384 | fprintf (stdout, "D"); | |
1385 | if (t->opcode_modifier & W) | |
1386 | fprintf (stdout, "W"); | |
1387 | fprintf (stdout, "\n"); | |
1388 | for (i = 0; i < t->operands; i++) | |
1389 | { | |
1390 | fprintf (stdout, " #%d type ", i + 1); | |
1391 | pt (t->operand_types[i]); | |
1392 | fprintf (stdout, "\n"); | |
1393 | } | |
1394 | } | |
1395 | ||
1396 | static void | |
e3bb37b5 | 1397 | pe (expressionS *e) |
252b5132 | 1398 | { |
24eab124 | 1399 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1400 | fprintf (stdout, " add_number %ld (%lx)\n", |
1401 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1402 | if (e->X_add_symbol) |
1403 | { | |
1404 | fprintf (stdout, " add_symbol "); | |
1405 | ps (e->X_add_symbol); | |
1406 | fprintf (stdout, "\n"); | |
1407 | } | |
1408 | if (e->X_op_symbol) | |
1409 | { | |
1410 | fprintf (stdout, " op_symbol "); | |
1411 | ps (e->X_op_symbol); | |
1412 | fprintf (stdout, "\n"); | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | static void | |
e3bb37b5 | 1417 | ps (symbolS *s) |
252b5132 RH |
1418 | { |
1419 | fprintf (stdout, "%s type %s%s", | |
1420 | S_GET_NAME (s), | |
1421 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1422 | segment_name (S_GET_SEGMENT (s))); | |
1423 | } | |
1424 | ||
7b81dfbb | 1425 | static struct type_name |
252b5132 RH |
1426 | { |
1427 | unsigned int mask; | |
1428 | char *tname; | |
1429 | } | |
7b81dfbb | 1430 | const type_names[] = |
252b5132 RH |
1431 | { |
1432 | { Reg8, "r8" }, | |
1433 | { Reg16, "r16" }, | |
1434 | { Reg32, "r32" }, | |
09f131f2 | 1435 | { Reg64, "r64" }, |
252b5132 RH |
1436 | { Imm8, "i8" }, |
1437 | { Imm8S, "i8s" }, | |
1438 | { Imm16, "i16" }, | |
1439 | { Imm32, "i32" }, | |
09f131f2 JH |
1440 | { Imm32S, "i32s" }, |
1441 | { Imm64, "i64" }, | |
252b5132 RH |
1442 | { Imm1, "i1" }, |
1443 | { BaseIndex, "BaseIndex" }, | |
1444 | { Disp8, "d8" }, | |
1445 | { Disp16, "d16" }, | |
1446 | { Disp32, "d32" }, | |
09f131f2 JH |
1447 | { Disp32S, "d32s" }, |
1448 | { Disp64, "d64" }, | |
252b5132 RH |
1449 | { InOutPortReg, "InOutPortReg" }, |
1450 | { ShiftCount, "ShiftCount" }, | |
1451 | { Control, "control reg" }, | |
1452 | { Test, "test reg" }, | |
1453 | { Debug, "debug reg" }, | |
1454 | { FloatReg, "FReg" }, | |
1455 | { FloatAcc, "FAcc" }, | |
1456 | { SReg2, "SReg2" }, | |
1457 | { SReg3, "SReg3" }, | |
1458 | { Acc, "Acc" }, | |
1459 | { JumpAbsolute, "Jump Absolute" }, | |
1460 | { RegMMX, "rMMX" }, | |
3f4438ab | 1461 | { RegXMM, "rXMM" }, |
252b5132 RH |
1462 | { EsSeg, "es" }, |
1463 | { 0, "" } | |
1464 | }; | |
1465 | ||
1466 | static void | |
1467 | pt (t) | |
1468 | unsigned int t; | |
1469 | { | |
29b0f896 | 1470 | const struct type_name *ty; |
252b5132 | 1471 | |
09f131f2 JH |
1472 | for (ty = type_names; ty->mask; ty++) |
1473 | if (t & ty->mask) | |
1474 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1475 | fflush (stdout); |
1476 | } | |
1477 | ||
1478 | #endif /* DEBUG386 */ | |
1479 | \f | |
252b5132 | 1480 | static bfd_reloc_code_real_type |
3956db08 | 1481 | reloc (unsigned int size, |
64e74474 AM |
1482 | int pcrel, |
1483 | int sign, | |
1484 | bfd_reloc_code_real_type other) | |
252b5132 | 1485 | { |
47926f60 | 1486 | if (other != NO_RELOC) |
3956db08 JB |
1487 | { |
1488 | reloc_howto_type *reloc; | |
1489 | ||
1490 | if (size == 8) | |
1491 | switch (other) | |
1492 | { | |
64e74474 AM |
1493 | case BFD_RELOC_X86_64_GOT32: |
1494 | return BFD_RELOC_X86_64_GOT64; | |
1495 | break; | |
1496 | case BFD_RELOC_X86_64_PLTOFF64: | |
1497 | return BFD_RELOC_X86_64_PLTOFF64; | |
1498 | break; | |
1499 | case BFD_RELOC_X86_64_GOTPC32: | |
1500 | other = BFD_RELOC_X86_64_GOTPC64; | |
1501 | break; | |
1502 | case BFD_RELOC_X86_64_GOTPCREL: | |
1503 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
1504 | break; | |
1505 | case BFD_RELOC_X86_64_TPOFF32: | |
1506 | other = BFD_RELOC_X86_64_TPOFF64; | |
1507 | break; | |
1508 | case BFD_RELOC_X86_64_DTPOFF32: | |
1509 | other = BFD_RELOC_X86_64_DTPOFF64; | |
1510 | break; | |
1511 | default: | |
1512 | break; | |
3956db08 | 1513 | } |
e05278af JB |
1514 | |
1515 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
1516 | if (size == 4 && flag_code != CODE_64BIT) | |
1517 | sign = -1; | |
1518 | ||
3956db08 JB |
1519 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
1520 | if (!reloc) | |
1521 | as_bad (_("unknown relocation (%u)"), other); | |
1522 | else if (size != bfd_get_reloc_size (reloc)) | |
1523 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
1524 | bfd_get_reloc_size (reloc), | |
1525 | size); | |
1526 | else if (pcrel && !reloc->pc_relative) | |
1527 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
1528 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
1529 | && !sign) | |
1530 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 1531 | && sign > 0)) |
3956db08 JB |
1532 | as_bad (_("relocated field and relocation type differ in signedness")); |
1533 | else | |
1534 | return other; | |
1535 | return NO_RELOC; | |
1536 | } | |
252b5132 RH |
1537 | |
1538 | if (pcrel) | |
1539 | { | |
3e73aa7c | 1540 | if (!sign) |
3956db08 | 1541 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
1542 | switch (size) |
1543 | { | |
1544 | case 1: return BFD_RELOC_8_PCREL; | |
1545 | case 2: return BFD_RELOC_16_PCREL; | |
1546 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 1547 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 1548 | } |
3956db08 | 1549 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
1550 | } |
1551 | else | |
1552 | { | |
3956db08 | 1553 | if (sign > 0) |
e5cb08ac | 1554 | switch (size) |
3e73aa7c JH |
1555 | { |
1556 | case 4: return BFD_RELOC_X86_64_32S; | |
1557 | } | |
1558 | else | |
1559 | switch (size) | |
1560 | { | |
1561 | case 1: return BFD_RELOC_8; | |
1562 | case 2: return BFD_RELOC_16; | |
1563 | case 4: return BFD_RELOC_32; | |
1564 | case 8: return BFD_RELOC_64; | |
1565 | } | |
3956db08 JB |
1566 | as_bad (_("cannot do %s %u byte relocation"), |
1567 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
1568 | } |
1569 | ||
bfb32b52 | 1570 | abort (); |
252b5132 RH |
1571 | return BFD_RELOC_NONE; |
1572 | } | |
1573 | ||
47926f60 KH |
1574 | /* Here we decide which fixups can be adjusted to make them relative to |
1575 | the beginning of the section instead of the symbol. Basically we need | |
1576 | to make sure that the dynamic relocations are done correctly, so in | |
1577 | some cases we force the original symbol to be used. */ | |
1578 | ||
252b5132 | 1579 | int |
e3bb37b5 | 1580 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 1581 | { |
6d249963 | 1582 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 1583 | if (!IS_ELF) |
31312f95 AM |
1584 | return 1; |
1585 | ||
a161fe53 AM |
1586 | /* Don't adjust pc-relative references to merge sections in 64-bit |
1587 | mode. */ | |
1588 | if (use_rela_relocations | |
1589 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
1590 | && fixP->fx_pcrel) | |
252b5132 | 1591 | return 0; |
31312f95 | 1592 | |
8d01d9a9 AJ |
1593 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
1594 | and changed later by validate_fix. */ | |
1595 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
1596 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
1597 | return 0; | |
1598 | ||
ce8a8b2f | 1599 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1600 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1601 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1602 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
1603 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
1604 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
1605 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
1606 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
1607 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
1608 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
1609 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
1610 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
1611 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
1612 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
1613 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1614 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1615 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
1616 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
1617 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
1618 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 1619 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
1620 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
1621 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
1622 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
1623 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
1624 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
1625 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
1626 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1627 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1628 | return 0; | |
31312f95 | 1629 | #endif |
252b5132 RH |
1630 | return 1; |
1631 | } | |
252b5132 | 1632 | |
b4cac588 | 1633 | static int |
e3bb37b5 | 1634 | intel_float_operand (const char *mnemonic) |
252b5132 | 1635 | { |
9306ca4a JB |
1636 | /* Note that the value returned is meaningful only for opcodes with (memory) |
1637 | operands, hence the code here is free to improperly handle opcodes that | |
1638 | have no operands (for better performance and smaller code). */ | |
1639 | ||
1640 | if (mnemonic[0] != 'f') | |
1641 | return 0; /* non-math */ | |
1642 | ||
1643 | switch (mnemonic[1]) | |
1644 | { | |
1645 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
1646 | the fs segment override prefix not currently handled because no | |
1647 | call path can make opcodes without operands get here */ | |
1648 | case 'i': | |
1649 | return 2 /* integer op */; | |
1650 | case 'l': | |
1651 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
1652 | return 3; /* fldcw/fldenv */ | |
1653 | break; | |
1654 | case 'n': | |
1655 | if (mnemonic[2] != 'o' /* fnop */) | |
1656 | return 3; /* non-waiting control op */ | |
1657 | break; | |
1658 | case 'r': | |
1659 | if (mnemonic[2] == 's') | |
1660 | return 3; /* frstor/frstpm */ | |
1661 | break; | |
1662 | case 's': | |
1663 | if (mnemonic[2] == 'a') | |
1664 | return 3; /* fsave */ | |
1665 | if (mnemonic[2] == 't') | |
1666 | { | |
1667 | switch (mnemonic[3]) | |
1668 | { | |
1669 | case 'c': /* fstcw */ | |
1670 | case 'd': /* fstdw */ | |
1671 | case 'e': /* fstenv */ | |
1672 | case 's': /* fsts[gw] */ | |
1673 | return 3; | |
1674 | } | |
1675 | } | |
1676 | break; | |
1677 | case 'x': | |
1678 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
1679 | return 0; /* fxsave/fxrstor are not really math ops */ | |
1680 | break; | |
1681 | } | |
252b5132 | 1682 | |
9306ca4a | 1683 | return 1; |
252b5132 RH |
1684 | } |
1685 | ||
1686 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1687 | machine dependent instruction. This function is supposed to emit | |
1688 | the frags/bytes it assembles to. */ | |
1689 | ||
1690 | void | |
1691 | md_assemble (line) | |
1692 | char *line; | |
1693 | { | |
252b5132 | 1694 | int j; |
252b5132 RH |
1695 | char mnemonic[MAX_MNEM_SIZE]; |
1696 | ||
47926f60 | 1697 | /* Initialize globals. */ |
252b5132 RH |
1698 | memset (&i, '\0', sizeof (i)); |
1699 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1700 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1701 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1702 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1703 | save_stack_p = save_stack; |
252b5132 RH |
1704 | |
1705 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1706 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1707 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 1708 | |
29b0f896 AM |
1709 | line = parse_insn (line, mnemonic); |
1710 | if (line == NULL) | |
1711 | return; | |
252b5132 | 1712 | |
29b0f896 AM |
1713 | line = parse_operands (line, mnemonic); |
1714 | if (line == NULL) | |
1715 | return; | |
252b5132 | 1716 | |
4eed87de | 1717 | /* The order of the immediates should be reversed |
050dfa73 | 1718 | for 2 immediates extrq and insertq instructions */ |
4d456e3d L |
1719 | if ((i.imm_operands == 2) |
1720 | && ((strcmp (mnemonic, "extrq") == 0) | |
1721 | || (strcmp (mnemonic, "insertq") == 0))) | |
050dfa73 | 1722 | { |
4eed87de AM |
1723 | swap_2_operands (0, 1); |
1724 | /* "extrq" and insertq" are the only two instructions whose operands | |
050dfa73 MM |
1725 | have to be reversed even though they have two immediate operands. |
1726 | */ | |
1727 | if (intel_syntax) | |
1728 | swap_operands (); | |
1729 | } | |
1730 | ||
29b0f896 AM |
1731 | /* Now we've parsed the mnemonic into a set of templates, and have the |
1732 | operands at hand. */ | |
1733 | ||
1734 | /* All intel opcodes have reversed operands except for "bound" and | |
1735 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1736 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 1737 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
1738 | if (intel_syntax |
1739 | && i.operands > 1 | |
29b0f896 | 1740 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 1741 | && (strcmp (mnemonic, "invlpga") != 0) |
29b0f896 AM |
1742 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) |
1743 | swap_operands (); | |
1744 | ||
1745 | if (i.imm_operands) | |
1746 | optimize_imm (); | |
1747 | ||
b300c311 L |
1748 | /* Don't optimize displacement for movabs since it only takes 64bit |
1749 | displacement. */ | |
1750 | if (i.disp_operands | |
1751 | && (flag_code != CODE_64BIT | |
1752 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
1753 | optimize_disp (); |
1754 | ||
1755 | /* Next, we find a template that matches the given insn, | |
1756 | making sure the overlap of the given operands types is consistent | |
1757 | with the template operand types. */ | |
252b5132 | 1758 | |
29b0f896 AM |
1759 | if (!match_template ()) |
1760 | return; | |
252b5132 | 1761 | |
cd61ebfe AM |
1762 | if (intel_syntax) |
1763 | { | |
1764 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ | |
1765 | if (SYSV386_COMPAT | |
1766 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
8a2ed489 | 1767 | i.tm.base_opcode ^= Opcode_FloatR; |
cd61ebfe AM |
1768 | |
1769 | /* Zap movzx and movsx suffix. The suffix may have been set from | |
1770 | "word ptr" or "byte ptr" on the source operand, but we'll use | |
1771 | the suffix later to choose the destination register. */ | |
1772 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
9306ca4a JB |
1773 | { |
1774 | if (i.reg_operands < 2 | |
1775 | && !i.suffix | |
1776 | && (~i.tm.opcode_modifier | |
1777 | & (No_bSuf | |
1778 | | No_wSuf | |
1779 | | No_lSuf | |
1780 | | No_sSuf | |
1781 | | No_xSuf | |
1782 | | No_qSuf))) | |
1783 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
1784 | ||
1785 | i.suffix = 0; | |
1786 | } | |
cd61ebfe | 1787 | } |
24eab124 | 1788 | |
29b0f896 AM |
1789 | if (i.tm.opcode_modifier & FWait) |
1790 | if (!add_prefix (FWAIT_OPCODE)) | |
1791 | return; | |
252b5132 | 1792 | |
29b0f896 AM |
1793 | /* Check string instruction segment overrides. */ |
1794 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1795 | { | |
1796 | if (!check_string ()) | |
5dd0794d | 1797 | return; |
29b0f896 | 1798 | } |
5dd0794d | 1799 | |
29b0f896 AM |
1800 | if (!process_suffix ()) |
1801 | return; | |
e413e4e9 | 1802 | |
29b0f896 AM |
1803 | /* Make still unresolved immediate matches conform to size of immediate |
1804 | given in i.suffix. */ | |
1805 | if (!finalize_imm ()) | |
1806 | return; | |
252b5132 | 1807 | |
29b0f896 AM |
1808 | if (i.types[0] & Imm1) |
1809 | i.imm_operands = 0; /* kludge for shift insns. */ | |
1810 | if (i.types[0] & ImplicitRegister) | |
1811 | i.reg_operands--; | |
1812 | if (i.types[1] & ImplicitRegister) | |
1813 | i.reg_operands--; | |
1814 | if (i.types[2] & ImplicitRegister) | |
1815 | i.reg_operands--; | |
252b5132 | 1816 | |
29b0f896 AM |
1817 | if (i.tm.opcode_modifier & ImmExt) |
1818 | { | |
02fc3089 L |
1819 | expressionS *exp; |
1820 | ||
b7d9ef37 | 1821 | if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0) |
ca164297 | 1822 | { |
b7d9ef37 | 1823 | /* Streaming SIMD extensions 3 Instructions have the fixed |
ca164297 L |
1824 | operands with an opcode suffix which is coded in the same |
1825 | place as an 8-bit immediate field would be. Here we check | |
1826 | those operands and remove them afterwards. */ | |
1827 | unsigned int x; | |
1828 | ||
a4622f40 | 1829 | for (x = 0; x < i.operands; x++) |
ca164297 L |
1830 | if (i.op[x].regs->reg_num != x) |
1831 | as_bad (_("can't use register '%%%s' as operand %d in '%s'."), | |
64e74474 | 1832 | i.op[x].regs->reg_name, x + 1, i.tm.name); |
ca164297 L |
1833 | i.operands = 0; |
1834 | } | |
1835 | ||
29b0f896 AM |
1836 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1837 | opcode suffix which is coded in the same place as an 8-bit | |
1838 | immediate field would be. Here we fake an 8-bit immediate | |
1839 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 | 1840 | |
29b0f896 | 1841 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 | 1842 | |
29b0f896 AM |
1843 | exp = &im_expressions[i.imm_operands++]; |
1844 | i.op[i.operands].imms = exp; | |
1845 | i.types[i.operands++] = Imm8; | |
1846 | exp->X_op = O_constant; | |
1847 | exp->X_add_number = i.tm.extension_opcode; | |
1848 | i.tm.extension_opcode = None; | |
1849 | } | |
252b5132 | 1850 | |
29b0f896 AM |
1851 | /* For insns with operands there are more diddles to do to the opcode. */ |
1852 | if (i.operands) | |
1853 | { | |
1854 | if (!process_operands ()) | |
1855 | return; | |
1856 | } | |
1857 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
1858 | { | |
1859 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
1860 | as_warn (_("translating to `%sp'"), i.tm.name); | |
1861 | } | |
252b5132 | 1862 | |
29b0f896 AM |
1863 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
1864 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
1865 | { | |
1866 | i.tm.base_opcode = INT3_OPCODE; | |
1867 | i.imm_operands = 0; | |
1868 | } | |
252b5132 | 1869 | |
29b0f896 AM |
1870 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
1871 | && i.op[0].disps->X_op == O_constant) | |
1872 | { | |
1873 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
1874 | the absolute address given by the constant. Since ix86 jumps and | |
1875 | calls are pc relative, we need to generate a reloc. */ | |
1876 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
1877 | i.op[0].disps->X_op = O_symbol; | |
1878 | } | |
252b5132 | 1879 | |
29b0f896 AM |
1880 | if ((i.tm.opcode_modifier & Rex64) != 0) |
1881 | i.rex |= REX_MODE64; | |
252b5132 | 1882 | |
29b0f896 AM |
1883 | /* For 8 bit registers we need an empty rex prefix. Also if the |
1884 | instruction already has a prefix, we need to convert old | |
1885 | registers to new ones. */ | |
773f551c | 1886 | |
29b0f896 AM |
1887 | if (((i.types[0] & Reg8) != 0 |
1888 | && (i.op[0].regs->reg_flags & RegRex64) != 0) | |
1889 | || ((i.types[1] & Reg8) != 0 | |
1890 | && (i.op[1].regs->reg_flags & RegRex64) != 0) | |
1891 | || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) | |
1892 | && i.rex != 0)) | |
1893 | { | |
1894 | int x; | |
726c5dcd | 1895 | |
29b0f896 AM |
1896 | i.rex |= REX_OPCODE; |
1897 | for (x = 0; x < 2; x++) | |
1898 | { | |
1899 | /* Look for 8 bit operand that uses old registers. */ | |
1900 | if ((i.types[x] & Reg8) != 0 | |
1901 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
773f551c | 1902 | { |
29b0f896 AM |
1903 | /* In case it is "hi" register, give up. */ |
1904 | if (i.op[x].regs->reg_num > 3) | |
4eed87de AM |
1905 | as_bad (_("can't encode register '%%%s' in an " |
1906 | "instruction requiring REX prefix."), | |
29b0f896 | 1907 | i.op[x].regs->reg_name); |
773f551c | 1908 | |
29b0f896 AM |
1909 | /* Otherwise it is equivalent to the extended register. |
1910 | Since the encoding doesn't change this is merely | |
1911 | cosmetic cleanup for debug output. */ | |
1912 | ||
1913 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 1914 | } |
29b0f896 AM |
1915 | } |
1916 | } | |
773f551c | 1917 | |
29b0f896 AM |
1918 | if (i.rex != 0) |
1919 | add_prefix (REX_OPCODE | i.rex); | |
1920 | ||
1921 | /* We are ready to output the insn. */ | |
1922 | output_insn (); | |
1923 | } | |
1924 | ||
1925 | static char * | |
e3bb37b5 | 1926 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
1927 | { |
1928 | char *l = line; | |
1929 | char *token_start = l; | |
1930 | char *mnem_p; | |
5c6af06e JB |
1931 | int supported; |
1932 | const template *t; | |
29b0f896 AM |
1933 | |
1934 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
1935 | const char *expecting_string_instruction = NULL; | |
45288df1 | 1936 | |
29b0f896 AM |
1937 | while (1) |
1938 | { | |
1939 | mnem_p = mnemonic; | |
1940 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1941 | { | |
1942 | mnem_p++; | |
1943 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 1944 | { |
29b0f896 AM |
1945 | as_bad (_("no such instruction: `%s'"), token_start); |
1946 | return NULL; | |
1947 | } | |
1948 | l++; | |
1949 | } | |
1950 | if (!is_space_char (*l) | |
1951 | && *l != END_OF_INSN | |
e44823cf JB |
1952 | && (intel_syntax |
1953 | || (*l != PREFIX_SEPARATOR | |
1954 | && *l != ','))) | |
29b0f896 AM |
1955 | { |
1956 | as_bad (_("invalid character %s in mnemonic"), | |
1957 | output_invalid (*l)); | |
1958 | return NULL; | |
1959 | } | |
1960 | if (token_start == l) | |
1961 | { | |
e44823cf | 1962 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
1963 | as_bad (_("expecting prefix; got nothing")); |
1964 | else | |
1965 | as_bad (_("expecting mnemonic; got nothing")); | |
1966 | return NULL; | |
1967 | } | |
45288df1 | 1968 | |
29b0f896 AM |
1969 | /* Look up instruction (or prefix) via hash table. */ |
1970 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 1971 | |
29b0f896 AM |
1972 | if (*l != END_OF_INSN |
1973 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
1974 | && current_templates | |
1975 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1976 | { | |
2dd88dca JB |
1977 | if (current_templates->start->cpu_flags |
1978 | & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64)) | |
1979 | { | |
1980 | as_bad ((flag_code != CODE_64BIT | |
1981 | ? _("`%s' is only supported in 64-bit mode") | |
1982 | : _("`%s' is not supported in 64-bit mode")), | |
1983 | current_templates->start->name); | |
1984 | return NULL; | |
1985 | } | |
29b0f896 AM |
1986 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
1987 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1988 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1989 | && flag_code != CODE_64BIT | |
1990 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1991 | ^ (flag_code == CODE_16BIT))) | |
1992 | { | |
1993 | as_bad (_("redundant %s prefix"), | |
1994 | current_templates->start->name); | |
1995 | return NULL; | |
45288df1 | 1996 | } |
29b0f896 AM |
1997 | /* Add prefix, checking for repeated prefixes. */ |
1998 | switch (add_prefix (current_templates->start->base_opcode)) | |
1999 | { | |
2000 | case 0: | |
2001 | return NULL; | |
2002 | case 2: | |
2003 | expecting_string_instruction = current_templates->start->name; | |
2004 | break; | |
2005 | } | |
2006 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
2007 | token_start = ++l; | |
2008 | } | |
2009 | else | |
2010 | break; | |
2011 | } | |
45288df1 | 2012 | |
29b0f896 AM |
2013 | if (!current_templates) |
2014 | { | |
2015 | /* See if we can get a match by trimming off a suffix. */ | |
2016 | switch (mnem_p[-1]) | |
2017 | { | |
2018 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
2019 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
2020 | i.suffix = SHORT_MNEM_SUFFIX; | |
2021 | else | |
29b0f896 AM |
2022 | case BYTE_MNEM_SUFFIX: |
2023 | case QWORD_MNEM_SUFFIX: | |
2024 | i.suffix = mnem_p[-1]; | |
2025 | mnem_p[-1] = '\0'; | |
2026 | current_templates = hash_find (op_hash, mnemonic); | |
2027 | break; | |
2028 | case SHORT_MNEM_SUFFIX: | |
2029 | case LONG_MNEM_SUFFIX: | |
2030 | if (!intel_syntax) | |
2031 | { | |
2032 | i.suffix = mnem_p[-1]; | |
2033 | mnem_p[-1] = '\0'; | |
2034 | current_templates = hash_find (op_hash, mnemonic); | |
2035 | } | |
2036 | break; | |
252b5132 | 2037 | |
29b0f896 AM |
2038 | /* Intel Syntax. */ |
2039 | case 'd': | |
2040 | if (intel_syntax) | |
2041 | { | |
9306ca4a | 2042 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
2043 | i.suffix = SHORT_MNEM_SUFFIX; |
2044 | else | |
2045 | i.suffix = LONG_MNEM_SUFFIX; | |
2046 | mnem_p[-1] = '\0'; | |
2047 | current_templates = hash_find (op_hash, mnemonic); | |
2048 | } | |
2049 | break; | |
2050 | } | |
2051 | if (!current_templates) | |
2052 | { | |
2053 | as_bad (_("no such instruction: `%s'"), token_start); | |
2054 | return NULL; | |
2055 | } | |
2056 | } | |
252b5132 | 2057 | |
29b0f896 AM |
2058 | if (current_templates->start->opcode_modifier & (Jump | JumpByte)) |
2059 | { | |
2060 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
2061 | predict taken and predict not taken respectively. | |
2062 | I'm not sure that branch hints actually do anything on loop | |
2063 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
2064 | may work in the future and it doesn't hurt to accept them | |
2065 | now. */ | |
2066 | if (l[0] == ',' && l[1] == 'p') | |
2067 | { | |
2068 | if (l[2] == 't') | |
2069 | { | |
2070 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
2071 | return NULL; | |
2072 | l += 3; | |
2073 | } | |
2074 | else if (l[2] == 'n') | |
2075 | { | |
2076 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
2077 | return NULL; | |
2078 | l += 3; | |
2079 | } | |
2080 | } | |
2081 | } | |
2082 | /* Any other comma loses. */ | |
2083 | if (*l == ',') | |
2084 | { | |
2085 | as_bad (_("invalid character %s in mnemonic"), | |
2086 | output_invalid (*l)); | |
2087 | return NULL; | |
2088 | } | |
252b5132 | 2089 | |
29b0f896 | 2090 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
2091 | supported = 0; |
2092 | for (t = current_templates->start; t < current_templates->end; ++t) | |
2093 | { | |
2094 | if (!((t->cpu_flags & ~(Cpu64 | CpuNo64)) | |
2095 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))) | |
64e74474 | 2096 | supported |= 1; |
5c6af06e | 2097 | if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64))) |
64e74474 | 2098 | supported |= 2; |
5c6af06e JB |
2099 | } |
2100 | if (!(supported & 2)) | |
2101 | { | |
2102 | as_bad (flag_code == CODE_64BIT | |
2103 | ? _("`%s' is not supported in 64-bit mode") | |
2104 | : _("`%s' is only supported in 64-bit mode"), | |
2105 | current_templates->start->name); | |
2106 | return NULL; | |
2107 | } | |
2108 | if (!(supported & 1)) | |
29b0f896 | 2109 | { |
5c6af06e JB |
2110 | as_warn (_("`%s' is not supported on `%s%s'"), |
2111 | current_templates->start->name, | |
2112 | cpu_arch_name, | |
2113 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
29b0f896 AM |
2114 | } |
2115 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) | |
2116 | { | |
2117 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
2118 | } | |
252b5132 | 2119 | |
29b0f896 | 2120 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 2121 | if (expecting_string_instruction) |
29b0f896 | 2122 | { |
f41bbced JB |
2123 | static templates override; |
2124 | ||
2125 | for (t = current_templates->start; t < current_templates->end; ++t) | |
2126 | if (t->opcode_modifier & IsString) | |
2127 | break; | |
2128 | if (t >= current_templates->end) | |
2129 | { | |
2130 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 2131 | expecting_string_instruction); |
f41bbced JB |
2132 | return NULL; |
2133 | } | |
2134 | for (override.start = t; t < current_templates->end; ++t) | |
2135 | if (!(t->opcode_modifier & IsString)) | |
2136 | break; | |
2137 | override.end = t; | |
2138 | current_templates = &override; | |
29b0f896 | 2139 | } |
252b5132 | 2140 | |
29b0f896 AM |
2141 | return l; |
2142 | } | |
252b5132 | 2143 | |
29b0f896 | 2144 | static char * |
e3bb37b5 | 2145 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
2146 | { |
2147 | char *token_start; | |
3138f287 | 2148 | |
29b0f896 AM |
2149 | /* 1 if operand is pending after ','. */ |
2150 | unsigned int expecting_operand = 0; | |
252b5132 | 2151 | |
29b0f896 AM |
2152 | /* Non-zero if operand parens not balanced. */ |
2153 | unsigned int paren_not_balanced; | |
2154 | ||
2155 | while (*l != END_OF_INSN) | |
2156 | { | |
2157 | /* Skip optional white space before operand. */ | |
2158 | if (is_space_char (*l)) | |
2159 | ++l; | |
2160 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
2161 | { | |
2162 | as_bad (_("invalid character %s before operand %d"), | |
2163 | output_invalid (*l), | |
2164 | i.operands + 1); | |
2165 | return NULL; | |
2166 | } | |
2167 | token_start = l; /* after white space */ | |
2168 | paren_not_balanced = 0; | |
2169 | while (paren_not_balanced || *l != ',') | |
2170 | { | |
2171 | if (*l == END_OF_INSN) | |
2172 | { | |
2173 | if (paren_not_balanced) | |
2174 | { | |
2175 | if (!intel_syntax) | |
2176 | as_bad (_("unbalanced parenthesis in operand %d."), | |
2177 | i.operands + 1); | |
2178 | else | |
2179 | as_bad (_("unbalanced brackets in operand %d."), | |
2180 | i.operands + 1); | |
2181 | return NULL; | |
2182 | } | |
2183 | else | |
2184 | break; /* we are done */ | |
2185 | } | |
2186 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
2187 | { | |
2188 | as_bad (_("invalid character %s in operand %d"), | |
2189 | output_invalid (*l), | |
2190 | i.operands + 1); | |
2191 | return NULL; | |
2192 | } | |
2193 | if (!intel_syntax) | |
2194 | { | |
2195 | if (*l == '(') | |
2196 | ++paren_not_balanced; | |
2197 | if (*l == ')') | |
2198 | --paren_not_balanced; | |
2199 | } | |
2200 | else | |
2201 | { | |
2202 | if (*l == '[') | |
2203 | ++paren_not_balanced; | |
2204 | if (*l == ']') | |
2205 | --paren_not_balanced; | |
2206 | } | |
2207 | l++; | |
2208 | } | |
2209 | if (l != token_start) | |
2210 | { /* Yes, we've read in another operand. */ | |
2211 | unsigned int operand_ok; | |
2212 | this_operand = i.operands++; | |
2213 | if (i.operands > MAX_OPERANDS) | |
2214 | { | |
2215 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
2216 | MAX_OPERANDS); | |
2217 | return NULL; | |
2218 | } | |
2219 | /* Now parse operand adding info to 'i' as we go along. */ | |
2220 | END_STRING_AND_SAVE (l); | |
2221 | ||
2222 | if (intel_syntax) | |
2223 | operand_ok = | |
2224 | i386_intel_operand (token_start, | |
2225 | intel_float_operand (mnemonic)); | |
2226 | else | |
2227 | operand_ok = i386_operand (token_start); | |
2228 | ||
2229 | RESTORE_END_STRING (l); | |
2230 | if (!operand_ok) | |
2231 | return NULL; | |
2232 | } | |
2233 | else | |
2234 | { | |
2235 | if (expecting_operand) | |
2236 | { | |
2237 | expecting_operand_after_comma: | |
2238 | as_bad (_("expecting operand after ','; got nothing")); | |
2239 | return NULL; | |
2240 | } | |
2241 | if (*l == ',') | |
2242 | { | |
2243 | as_bad (_("expecting operand before ','; got nothing")); | |
2244 | return NULL; | |
2245 | } | |
2246 | } | |
7f3f1ea2 | 2247 | |
29b0f896 AM |
2248 | /* Now *l must be either ',' or END_OF_INSN. */ |
2249 | if (*l == ',') | |
2250 | { | |
2251 | if (*++l == END_OF_INSN) | |
2252 | { | |
2253 | /* Just skip it, if it's \n complain. */ | |
2254 | goto expecting_operand_after_comma; | |
2255 | } | |
2256 | expecting_operand = 1; | |
2257 | } | |
2258 | } | |
2259 | return l; | |
2260 | } | |
7f3f1ea2 | 2261 | |
050dfa73 | 2262 | static void |
4d456e3d | 2263 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
2264 | { |
2265 | union i386_op temp_op; | |
2266 | unsigned int temp_type; | |
2267 | enum bfd_reloc_code_real temp_reloc; | |
4eed87de | 2268 | |
050dfa73 MM |
2269 | temp_type = i.types[xchg2]; |
2270 | i.types[xchg2] = i.types[xchg1]; | |
2271 | i.types[xchg1] = temp_type; | |
2272 | temp_op = i.op[xchg2]; | |
2273 | i.op[xchg2] = i.op[xchg1]; | |
2274 | i.op[xchg1] = temp_op; | |
2275 | temp_reloc = i.reloc[xchg2]; | |
2276 | i.reloc[xchg2] = i.reloc[xchg1]; | |
2277 | i.reloc[xchg1] = temp_reloc; | |
2278 | } | |
2279 | ||
29b0f896 | 2280 | static void |
e3bb37b5 | 2281 | swap_operands (void) |
29b0f896 | 2282 | { |
b7c61d9a | 2283 | switch (i.operands) |
050dfa73 | 2284 | { |
b7c61d9a | 2285 | case 4: |
4d456e3d | 2286 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
2287 | case 3: |
2288 | case 2: | |
4d456e3d | 2289 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
2290 | break; |
2291 | default: | |
2292 | abort (); | |
29b0f896 | 2293 | } |
29b0f896 AM |
2294 | |
2295 | if (i.mem_operands == 2) | |
2296 | { | |
2297 | const seg_entry *temp_seg; | |
2298 | temp_seg = i.seg[0]; | |
2299 | i.seg[0] = i.seg[1]; | |
2300 | i.seg[1] = temp_seg; | |
2301 | } | |
2302 | } | |
252b5132 | 2303 | |
29b0f896 AM |
2304 | /* Try to ensure constant immediates are represented in the smallest |
2305 | opcode possible. */ | |
2306 | static void | |
e3bb37b5 | 2307 | optimize_imm (void) |
29b0f896 AM |
2308 | { |
2309 | char guess_suffix = 0; | |
2310 | int op; | |
252b5132 | 2311 | |
29b0f896 AM |
2312 | if (i.suffix) |
2313 | guess_suffix = i.suffix; | |
2314 | else if (i.reg_operands) | |
2315 | { | |
2316 | /* Figure out a suffix from the last register operand specified. | |
2317 | We can't do this properly yet, ie. excluding InOutPortReg, | |
2318 | but the following works for instructions with immediates. | |
2319 | In any case, we can't set i.suffix yet. */ | |
2320 | for (op = i.operands; --op >= 0;) | |
2321 | if (i.types[op] & Reg) | |
252b5132 | 2322 | { |
29b0f896 AM |
2323 | if (i.types[op] & Reg8) |
2324 | guess_suffix = BYTE_MNEM_SUFFIX; | |
2325 | else if (i.types[op] & Reg16) | |
2326 | guess_suffix = WORD_MNEM_SUFFIX; | |
2327 | else if (i.types[op] & Reg32) | |
2328 | guess_suffix = LONG_MNEM_SUFFIX; | |
2329 | else if (i.types[op] & Reg64) | |
2330 | guess_suffix = QWORD_MNEM_SUFFIX; | |
2331 | break; | |
252b5132 | 2332 | } |
29b0f896 AM |
2333 | } |
2334 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
2335 | guess_suffix = WORD_MNEM_SUFFIX; | |
2336 | ||
2337 | for (op = i.operands; --op >= 0;) | |
2338 | if (i.types[op] & Imm) | |
2339 | { | |
2340 | switch (i.op[op].imms->X_op) | |
252b5132 | 2341 | { |
29b0f896 AM |
2342 | case O_constant: |
2343 | /* If a suffix is given, this operand may be shortened. */ | |
2344 | switch (guess_suffix) | |
252b5132 | 2345 | { |
29b0f896 AM |
2346 | case LONG_MNEM_SUFFIX: |
2347 | i.types[op] |= Imm32 | Imm64; | |
2348 | break; | |
2349 | case WORD_MNEM_SUFFIX: | |
2350 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
2351 | break; | |
2352 | case BYTE_MNEM_SUFFIX: | |
2353 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
2354 | break; | |
252b5132 | 2355 | } |
252b5132 | 2356 | |
29b0f896 AM |
2357 | /* If this operand is at most 16 bits, convert it |
2358 | to a signed 16 bit number before trying to see | |
2359 | whether it will fit in an even smaller size. | |
2360 | This allows a 16-bit operand such as $0xffe0 to | |
2361 | be recognised as within Imm8S range. */ | |
2362 | if ((i.types[op] & Imm16) | |
2363 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) | |
252b5132 | 2364 | { |
29b0f896 AM |
2365 | i.op[op].imms->X_add_number = |
2366 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
2367 | } | |
2368 | if ((i.types[op] & Imm32) | |
2369 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) | |
2370 | == 0)) | |
2371 | { | |
2372 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
2373 | ^ ((offsetT) 1 << 31)) | |
2374 | - ((offsetT) 1 << 31)); | |
2375 | } | |
2376 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
252b5132 | 2377 | |
29b0f896 AM |
2378 | /* We must avoid matching of Imm32 templates when 64bit |
2379 | only immediate is available. */ | |
2380 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
2381 | i.types[op] &= ~Imm32; | |
2382 | break; | |
252b5132 | 2383 | |
29b0f896 AM |
2384 | case O_absent: |
2385 | case O_register: | |
2386 | abort (); | |
2387 | ||
2388 | /* Symbols and expressions. */ | |
2389 | default: | |
9cd96992 JB |
2390 | /* Convert symbolic operand to proper sizes for matching, but don't |
2391 | prevent matching a set of insns that only supports sizes other | |
2392 | than those matching the insn suffix. */ | |
2393 | { | |
2394 | unsigned int mask, allowed = 0; | |
2395 | const template *t; | |
2396 | ||
4eed87de AM |
2397 | for (t = current_templates->start; |
2398 | t < current_templates->end; | |
2399 | ++t) | |
2400 | allowed |= t->operand_types[op]; | |
9cd96992 JB |
2401 | switch (guess_suffix) |
2402 | { | |
2403 | case QWORD_MNEM_SUFFIX: | |
2404 | mask = Imm64 | Imm32S; | |
2405 | break; | |
2406 | case LONG_MNEM_SUFFIX: | |
2407 | mask = Imm32; | |
2408 | break; | |
2409 | case WORD_MNEM_SUFFIX: | |
2410 | mask = Imm16; | |
2411 | break; | |
2412 | case BYTE_MNEM_SUFFIX: | |
2413 | mask = Imm8; | |
2414 | break; | |
2415 | default: | |
2416 | mask = 0; | |
2417 | break; | |
2418 | } | |
64e74474 AM |
2419 | if (mask & allowed) |
2420 | i.types[op] &= mask; | |
9cd96992 | 2421 | } |
29b0f896 | 2422 | break; |
252b5132 | 2423 | } |
29b0f896 AM |
2424 | } |
2425 | } | |
47926f60 | 2426 | |
29b0f896 AM |
2427 | /* Try to use the smallest displacement type too. */ |
2428 | static void | |
e3bb37b5 | 2429 | optimize_disp (void) |
29b0f896 AM |
2430 | { |
2431 | int op; | |
3e73aa7c | 2432 | |
29b0f896 | 2433 | for (op = i.operands; --op >= 0;) |
b300c311 | 2434 | if (i.types[op] & Disp) |
252b5132 | 2435 | { |
b300c311 | 2436 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 2437 | { |
b300c311 | 2438 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 2439 | |
b300c311 L |
2440 | if ((i.types[op] & Disp16) |
2441 | && (disp & ~(offsetT) 0xffff) == 0) | |
2442 | { | |
2443 | /* If this operand is at most 16 bits, convert | |
2444 | to a signed 16 bit number and don't use 64bit | |
2445 | displacement. */ | |
2446 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
2447 | i.types[op] &= ~Disp64; | |
2448 | } | |
2449 | if ((i.types[op] & Disp32) | |
2450 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) | |
2451 | { | |
2452 | /* If this operand is at most 32 bits, convert | |
2453 | to a signed 32 bit number and don't use 64bit | |
2454 | displacement. */ | |
2455 | disp &= (((offsetT) 2 << 31) - 1); | |
2456 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
2457 | i.types[op] &= ~Disp64; | |
2458 | } | |
2459 | if (!disp && (i.types[op] & BaseIndex)) | |
2460 | { | |
2461 | i.types[op] &= ~Disp; | |
2462 | i.op[op].disps = 0; | |
2463 | i.disp_operands--; | |
2464 | } | |
2465 | else if (flag_code == CODE_64BIT) | |
2466 | { | |
2467 | if (fits_in_signed_long (disp)) | |
28a9d8f5 L |
2468 | { |
2469 | i.types[op] &= ~Disp64; | |
2470 | i.types[op] |= Disp32S; | |
2471 | } | |
b300c311 L |
2472 | if (fits_in_unsigned_long (disp)) |
2473 | i.types[op] |= Disp32; | |
2474 | } | |
2475 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) | |
2476 | && fits_in_signed_byte (disp)) | |
2477 | i.types[op] |= Disp8; | |
252b5132 | 2478 | } |
67a4f2b7 AO |
2479 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
2480 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
2481 | { | |
2482 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
2483 | i.op[op].disps, 0, i.reloc[op]); | |
2484 | i.types[op] &= ~Disp; | |
2485 | } | |
2486 | else | |
b300c311 L |
2487 | /* We only support 64bit displacement on constants. */ |
2488 | i.types[op] &= ~Disp64; | |
252b5132 | 2489 | } |
29b0f896 AM |
2490 | } |
2491 | ||
2492 | static int | |
e3bb37b5 | 2493 | match_template (void) |
29b0f896 AM |
2494 | { |
2495 | /* Points to template once we've found it. */ | |
2496 | const template *t; | |
f48ff2ae | 2497 | unsigned int overlap0, overlap1, overlap2, overlap3; |
29b0f896 AM |
2498 | unsigned int found_reverse_match; |
2499 | int suffix_check; | |
f48ff2ae | 2500 | unsigned int operand_types [MAX_OPERANDS]; |
539e75ad | 2501 | int addr_prefix_disp; |
a5c311ca | 2502 | unsigned int j; |
29b0f896 | 2503 | |
f48ff2ae L |
2504 | #if MAX_OPERANDS != 4 |
2505 | # error "MAX_OPERANDS must be 4." | |
2506 | #endif | |
2507 | ||
29b0f896 AM |
2508 | #define MATCH(overlap, given, template) \ |
2509 | ((overlap & ~JumpAbsolute) \ | |
2510 | && (((given) & (BaseIndex | JumpAbsolute)) \ | |
2511 | == ((overlap) & (BaseIndex | JumpAbsolute)))) | |
2512 | ||
2513 | /* If given types r0 and r1 are registers they must be of the same type | |
2514 | unless the expected operand type register overlap is null. | |
2515 | Note that Acc in a template matches every size of reg. */ | |
2516 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
2517 | (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ | |
2518 | || ((g0) & Reg) == ((g1) & Reg) \ | |
2519 | || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
2520 | ||
2521 | overlap0 = 0; | |
2522 | overlap1 = 0; | |
2523 | overlap2 = 0; | |
f48ff2ae | 2524 | overlap3 = 0; |
29b0f896 | 2525 | found_reverse_match = 0; |
a5c311ca L |
2526 | for (j = 0; j < MAX_OPERANDS; j++) |
2527 | operand_types [j] = 0; | |
539e75ad | 2528 | addr_prefix_disp = -1; |
29b0f896 AM |
2529 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX |
2530 | ? No_bSuf | |
2531 | : (i.suffix == WORD_MNEM_SUFFIX | |
2532 | ? No_wSuf | |
2533 | : (i.suffix == SHORT_MNEM_SUFFIX | |
2534 | ? No_sSuf | |
2535 | : (i.suffix == LONG_MNEM_SUFFIX | |
2536 | ? No_lSuf | |
2537 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2538 | ? No_qSuf | |
2539 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX | |
2540 | ? No_xSuf : 0)))))); | |
2541 | ||
45aa61fe | 2542 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 2543 | { |
539e75ad L |
2544 | addr_prefix_disp = -1; |
2545 | ||
29b0f896 AM |
2546 | /* Must have right number of operands. */ |
2547 | if (i.operands != t->operands) | |
2548 | continue; | |
2549 | ||
2550 | /* Check the suffix, except for some instructions in intel mode. */ | |
2551 | if ((t->opcode_modifier & suffix_check) | |
2552 | && !(intel_syntax | |
9306ca4a | 2553 | && (t->opcode_modifier & IgnoreSize))) |
29b0f896 AM |
2554 | continue; |
2555 | ||
a5c311ca L |
2556 | for (j = 0; j < MAX_OPERANDS; j++) |
2557 | operand_types [j] = t->operand_types [j]; | |
539e75ad | 2558 | |
45aa61fe AM |
2559 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
2560 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2561 | && flag_code != CODE_64BIT | |
2562 | && (intel_syntax | |
2563 | ? (!(t->opcode_modifier & IgnoreSize) | |
2564 | && !intel_float_operand (t->name)) | |
2565 | : intel_float_operand (t->name) != 2) | |
539e75ad L |
2566 | && (!(operand_types[0] & (RegMMX | RegXMM)) |
2567 | || !(operand_types[t->operands > 1] & (RegMMX | RegXMM))) | |
45aa61fe AM |
2568 | && (t->base_opcode != 0x0fc7 |
2569 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
2570 | continue; | |
2571 | ||
29b0f896 AM |
2572 | /* Do not verify operands when there are none. */ |
2573 | else if (!t->operands) | |
2574 | { | |
2575 | if (t->cpu_flags & ~cpu_arch_flags) | |
2576 | continue; | |
2577 | /* We've found a match; break out of loop. */ | |
2578 | break; | |
2579 | } | |
252b5132 | 2580 | |
539e75ad L |
2581 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
2582 | into Disp32/Disp16/Disp32 operand. */ | |
2583 | if (i.prefix[ADDR_PREFIX] != 0) | |
2584 | { | |
a5c311ca | 2585 | unsigned int DispOn = 0, DispOff = 0; |
539e75ad L |
2586 | |
2587 | switch (flag_code) | |
2588 | { | |
2589 | case CODE_16BIT: | |
2590 | DispOn = Disp32; | |
2591 | DispOff = Disp16; | |
2592 | break; | |
2593 | case CODE_32BIT: | |
2594 | DispOn = Disp16; | |
2595 | DispOff = Disp32; | |
2596 | break; | |
2597 | case CODE_64BIT: | |
2598 | DispOn = Disp32; | |
2599 | DispOff = Disp64; | |
2600 | break; | |
2601 | } | |
2602 | ||
f48ff2ae | 2603 | for (j = 0; j < MAX_OPERANDS; j++) |
539e75ad L |
2604 | { |
2605 | /* There should be only one Disp operand. */ | |
2606 | if ((operand_types[j] & DispOff)) | |
2607 | { | |
2608 | addr_prefix_disp = j; | |
2609 | operand_types[j] |= DispOn; | |
2610 | operand_types[j] &= ~DispOff; | |
2611 | break; | |
2612 | } | |
2613 | } | |
2614 | } | |
2615 | ||
2616 | overlap0 = i.types[0] & operand_types[0]; | |
29b0f896 AM |
2617 | switch (t->operands) |
2618 | { | |
2619 | case 1: | |
539e75ad | 2620 | if (!MATCH (overlap0, i.types[0], operand_types[0])) |
29b0f896 AM |
2621 | continue; |
2622 | break; | |
2623 | case 2: | |
8b38ad71 L |
2624 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
2625 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
2626 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
2627 | zero-extend %eax to %rax. */ | |
2628 | if (flag_code == CODE_64BIT | |
2629 | && t->base_opcode == 0x90 | |
2630 | && i.types [0] == (Acc | Reg32) | |
2631 | && i.types [1] == (Acc | Reg32)) | |
2632 | continue; | |
29b0f896 | 2633 | case 3: |
f48ff2ae | 2634 | case 4: |
539e75ad L |
2635 | overlap1 = i.types[1] & operand_types[1]; |
2636 | if (!MATCH (overlap0, i.types[0], operand_types[0]) | |
2637 | || !MATCH (overlap1, i.types[1], operand_types[1]) | |
cb712a9e | 2638 | /* monitor in SSE3 is a very special case. The first |
708587a4 | 2639 | register and the second register may have different |
cb712a9e L |
2640 | sizes. */ |
2641 | || !((t->base_opcode == 0x0f01 | |
2642 | && t->extension_opcode == 0xc8) | |
2643 | || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
539e75ad | 2644 | operand_types[0], |
cb712a9e | 2645 | overlap1, i.types[1], |
539e75ad | 2646 | operand_types[1]))) |
29b0f896 AM |
2647 | { |
2648 | /* Check if other direction is valid ... */ | |
2649 | if ((t->opcode_modifier & (D | FloatD)) == 0) | |
2650 | continue; | |
2651 | ||
2652 | /* Try reversing direction of operands. */ | |
539e75ad L |
2653 | overlap0 = i.types[0] & operand_types[1]; |
2654 | overlap1 = i.types[1] & operand_types[0]; | |
2655 | if (!MATCH (overlap0, i.types[0], operand_types[1]) | |
2656 | || !MATCH (overlap1, i.types[1], operand_types[0]) | |
29b0f896 | 2657 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], |
539e75ad | 2658 | operand_types[1], |
29b0f896 | 2659 | overlap1, i.types[1], |
539e75ad | 2660 | operand_types[0])) |
29b0f896 AM |
2661 | { |
2662 | /* Does not match either direction. */ | |
2663 | continue; | |
2664 | } | |
2665 | /* found_reverse_match holds which of D or FloatDR | |
2666 | we've found. */ | |
8a2ed489 L |
2667 | if ((t->opcode_modifier & D)) |
2668 | found_reverse_match = Opcode_D; | |
2669 | else if ((t->opcode_modifier & FloatD)) | |
2670 | found_reverse_match = Opcode_FloatD; | |
2671 | else | |
2672 | found_reverse_match = 0; | |
2673 | if ((t->opcode_modifier & FloatR)) | |
2674 | found_reverse_match |= Opcode_FloatR; | |
29b0f896 | 2675 | } |
f48ff2ae | 2676 | else |
29b0f896 | 2677 | { |
f48ff2ae | 2678 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
2679 | switch (t->operands) |
2680 | { | |
2681 | case 4: | |
2682 | overlap3 = i.types[3] & operand_types[3]; | |
2683 | case 3: | |
2684 | overlap2 = i.types[2] & operand_types[2]; | |
2685 | break; | |
2686 | } | |
29b0f896 | 2687 | |
f48ff2ae L |
2688 | switch (t->operands) |
2689 | { | |
2690 | case 4: | |
2691 | if (!MATCH (overlap3, i.types[3], operand_types[3]) | |
2692 | || !CONSISTENT_REGISTER_MATCH (overlap2, | |
2693 | i.types[2], | |
2694 | operand_types[2], | |
2695 | overlap3, | |
2696 | i.types[3], | |
2697 | operand_types[3])) | |
2698 | continue; | |
2699 | case 3: | |
2700 | /* Here we make use of the fact that there are no | |
2701 | reverse match 3 operand instructions, and all 3 | |
2702 | operand instructions only need to be checked for | |
2703 | register consistency between operands 2 and 3. */ | |
2704 | if (!MATCH (overlap2, i.types[2], operand_types[2]) | |
2705 | || !CONSISTENT_REGISTER_MATCH (overlap1, | |
2706 | i.types[1], | |
2707 | operand_types[1], | |
2708 | overlap2, | |
2709 | i.types[2], | |
2710 | operand_types[2])) | |
2711 | continue; | |
2712 | break; | |
2713 | } | |
29b0f896 | 2714 | } |
f48ff2ae | 2715 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
2716 | slip through to break. */ |
2717 | } | |
2718 | if (t->cpu_flags & ~cpu_arch_flags) | |
2719 | { | |
2720 | found_reverse_match = 0; | |
2721 | continue; | |
2722 | } | |
2723 | /* We've found a match; break out of loop. */ | |
2724 | break; | |
2725 | } | |
2726 | ||
2727 | if (t == current_templates->end) | |
2728 | { | |
2729 | /* We found no match. */ | |
2730 | as_bad (_("suffix or operands invalid for `%s'"), | |
2731 | current_templates->start->name); | |
2732 | return 0; | |
2733 | } | |
252b5132 | 2734 | |
29b0f896 AM |
2735 | if (!quiet_warnings) |
2736 | { | |
2737 | if (!intel_syntax | |
2738 | && ((i.types[0] & JumpAbsolute) | |
539e75ad | 2739 | != (operand_types[0] & JumpAbsolute))) |
29b0f896 AM |
2740 | { |
2741 | as_warn (_("indirect %s without `*'"), t->name); | |
2742 | } | |
2743 | ||
2744 | if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) | |
2745 | == (IsPrefix | IgnoreSize)) | |
2746 | { | |
2747 | /* Warn them that a data or address size prefix doesn't | |
2748 | affect assembly of the next line of code. */ | |
2749 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
2750 | } | |
2751 | } | |
2752 | ||
2753 | /* Copy the template we found. */ | |
2754 | i.tm = *t; | |
539e75ad L |
2755 | |
2756 | if (addr_prefix_disp != -1) | |
2757 | i.tm.operand_types[addr_prefix_disp] | |
2758 | = operand_types[addr_prefix_disp]; | |
2759 | ||
29b0f896 AM |
2760 | if (found_reverse_match) |
2761 | { | |
2762 | /* If we found a reverse match we must alter the opcode | |
2763 | direction bit. found_reverse_match holds bits to change | |
2764 | (different for int & float insns). */ | |
2765 | ||
2766 | i.tm.base_opcode ^= found_reverse_match; | |
2767 | ||
539e75ad L |
2768 | i.tm.operand_types[0] = operand_types[1]; |
2769 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
2770 | } |
2771 | ||
2772 | return 1; | |
2773 | } | |
2774 | ||
2775 | static int | |
e3bb37b5 | 2776 | check_string (void) |
29b0f896 AM |
2777 | { |
2778 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
2779 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
2780 | { | |
2781 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
2782 | { | |
2783 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2784 | i.tm.name, | |
2785 | mem_op + 1); | |
2786 | return 0; | |
2787 | } | |
2788 | /* There's only ever one segment override allowed per instruction. | |
2789 | This instruction possibly has a legal segment override on the | |
2790 | second operand, so copy the segment to where non-string | |
2791 | instructions store it, allowing common code. */ | |
2792 | i.seg[0] = i.seg[1]; | |
2793 | } | |
2794 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
2795 | { | |
2796 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
2797 | { | |
2798 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2799 | i.tm.name, | |
2800 | mem_op + 2); | |
2801 | return 0; | |
2802 | } | |
2803 | } | |
2804 | return 1; | |
2805 | } | |
2806 | ||
2807 | static int | |
543613e9 | 2808 | process_suffix (void) |
29b0f896 AM |
2809 | { |
2810 | /* If matched instruction specifies an explicit instruction mnemonic | |
2811 | suffix, use it. */ | |
2812 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) | |
2813 | { | |
2814 | if (i.tm.opcode_modifier & Size16) | |
2815 | i.suffix = WORD_MNEM_SUFFIX; | |
2816 | else if (i.tm.opcode_modifier & Size64) | |
2817 | i.suffix = QWORD_MNEM_SUFFIX; | |
2818 | else | |
2819 | i.suffix = LONG_MNEM_SUFFIX; | |
2820 | } | |
2821 | else if (i.reg_operands) | |
2822 | { | |
2823 | /* If there's no instruction mnemonic suffix we try to invent one | |
2824 | based on register operands. */ | |
2825 | if (!i.suffix) | |
2826 | { | |
2827 | /* We take i.suffix from the last register operand specified, | |
2828 | Destination register type is more significant than source | |
2829 | register type. */ | |
2830 | int op; | |
543613e9 | 2831 | |
29b0f896 AM |
2832 | for (op = i.operands; --op >= 0;) |
2833 | if ((i.types[op] & Reg) | |
2834 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
2835 | { | |
2836 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
2837 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
2838 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : | |
2839 | LONG_MNEM_SUFFIX); | |
2840 | break; | |
2841 | } | |
2842 | } | |
2843 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
2844 | { | |
2845 | if (!check_byte_reg ()) | |
2846 | return 0; | |
2847 | } | |
2848 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
2849 | { | |
2850 | if (!check_long_reg ()) | |
2851 | return 0; | |
2852 | } | |
2853 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2854 | { | |
2855 | if (!check_qword_reg ()) | |
2856 | return 0; | |
2857 | } | |
2858 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2859 | { | |
2860 | if (!check_word_reg ()) | |
2861 | return 0; | |
2862 | } | |
2863 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) | |
2864 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2865 | ; | |
2866 | else | |
2867 | abort (); | |
2868 | } | |
9306ca4a JB |
2869 | else if ((i.tm.opcode_modifier & DefaultSize) |
2870 | && !i.suffix | |
2871 | /* exclude fldenv/frstor/fsave/fstenv */ | |
2872 | && (i.tm.opcode_modifier & No_sSuf)) | |
29b0f896 AM |
2873 | { |
2874 | i.suffix = stackop_size; | |
2875 | } | |
9306ca4a JB |
2876 | else if (intel_syntax |
2877 | && !i.suffix | |
2878 | && ((i.tm.operand_types[0] & JumpAbsolute) | |
64e74474 AM |
2879 | || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment)) |
2880 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ | |
2881 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
2882 | { |
2883 | switch (flag_code) | |
2884 | { | |
2885 | case CODE_64BIT: | |
2886 | if (!(i.tm.opcode_modifier & No_qSuf)) | |
2887 | { | |
2888 | i.suffix = QWORD_MNEM_SUFFIX; | |
2889 | break; | |
2890 | } | |
2891 | case CODE_32BIT: | |
2892 | if (!(i.tm.opcode_modifier & No_lSuf)) | |
2893 | i.suffix = LONG_MNEM_SUFFIX; | |
2894 | break; | |
2895 | case CODE_16BIT: | |
2896 | if (!(i.tm.opcode_modifier & No_wSuf)) | |
2897 | i.suffix = WORD_MNEM_SUFFIX; | |
2898 | break; | |
2899 | } | |
2900 | } | |
252b5132 | 2901 | |
9306ca4a | 2902 | if (!i.suffix) |
29b0f896 | 2903 | { |
9306ca4a JB |
2904 | if (!intel_syntax) |
2905 | { | |
2906 | if (i.tm.opcode_modifier & W) | |
2907 | { | |
4eed87de AM |
2908 | as_bad (_("no instruction mnemonic suffix given and " |
2909 | "no register operands; can't size instruction")); | |
9306ca4a JB |
2910 | return 0; |
2911 | } | |
2912 | } | |
2913 | else | |
2914 | { | |
64e74474 AM |
2915 | unsigned int suffixes = (~i.tm.opcode_modifier |
2916 | & (No_bSuf | |
2917 | | No_wSuf | |
2918 | | No_lSuf | |
2919 | | No_sSuf | |
2920 | | No_xSuf | |
2921 | | No_qSuf)); | |
9306ca4a JB |
2922 | |
2923 | if ((i.tm.opcode_modifier & W) | |
2924 | || ((suffixes & (suffixes - 1)) | |
2925 | && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize)))) | |
2926 | { | |
2927 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
2928 | return 0; | |
2929 | } | |
2930 | } | |
29b0f896 | 2931 | } |
252b5132 | 2932 | |
9306ca4a JB |
2933 | /* Change the opcode based on the operand size given by i.suffix; |
2934 | We don't need to change things for byte insns. */ | |
2935 | ||
29b0f896 AM |
2936 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
2937 | { | |
2938 | /* It's not a byte, select word/dword operation. */ | |
2939 | if (i.tm.opcode_modifier & W) | |
2940 | { | |
2941 | if (i.tm.opcode_modifier & ShortForm) | |
2942 | i.tm.base_opcode |= 8; | |
2943 | else | |
2944 | i.tm.base_opcode |= 1; | |
2945 | } | |
0f3f3d8b | 2946 | |
29b0f896 AM |
2947 | /* Now select between word & dword operations via the operand |
2948 | size prefix, except for instructions that will ignore this | |
2949 | prefix anyway. */ | |
cb712a9e L |
2950 | if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8) |
2951 | { | |
2952 | /* monitor in SSE3 is a very special case. The default size | |
2953 | of AX is the size of mode. The address size override | |
2954 | prefix will change the size of AX. */ | |
2955 | if (i.op->regs[0].reg_type & | |
2956 | (flag_code == CODE_32BIT ? Reg16 : Reg32)) | |
2957 | if (!add_prefix (ADDR_PREFIX_OPCODE)) | |
2958 | return 0; | |
2959 | } | |
2960 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
2961 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
2962 | && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF)) | |
2963 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
2964 | || (flag_code == CODE_64BIT | |
2965 | && (i.tm.opcode_modifier & JumpByte)))) | |
24eab124 AM |
2966 | { |
2967 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 2968 | |
29b0f896 AM |
2969 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
2970 | prefix = ADDR_PREFIX_OPCODE; | |
252b5132 | 2971 | |
29b0f896 AM |
2972 | if (!add_prefix (prefix)) |
2973 | return 0; | |
24eab124 | 2974 | } |
252b5132 | 2975 | |
29b0f896 AM |
2976 | /* Set mode64 for an operand. */ |
2977 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 2978 | && flag_code == CODE_64BIT |
29b0f896 | 2979 | && (i.tm.opcode_modifier & NoRex64) == 0) |
46e883c5 L |
2980 | { |
2981 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
2982 | need rex64. */ | |
2983 | if (i.operands != 2 | |
2984 | || i.types [0] != (Acc | Reg64) | |
2985 | || i.types [1] != (Acc | Reg64) | |
2986 | || strcmp (i.tm.name, "xchg") != 0) | |
2987 | i.rex |= REX_MODE64; | |
2988 | } | |
3e73aa7c | 2989 | |
29b0f896 AM |
2990 | /* Size floating point instruction. */ |
2991 | if (i.suffix == LONG_MNEM_SUFFIX) | |
543613e9 NC |
2992 | if (i.tm.opcode_modifier & FloatMF) |
2993 | i.tm.base_opcode ^= 4; | |
29b0f896 | 2994 | } |
7ecd2f8b | 2995 | |
29b0f896 AM |
2996 | return 1; |
2997 | } | |
3e73aa7c | 2998 | |
29b0f896 | 2999 | static int |
543613e9 | 3000 | check_byte_reg (void) |
29b0f896 AM |
3001 | { |
3002 | int op; | |
543613e9 | 3003 | |
29b0f896 AM |
3004 | for (op = i.operands; --op >= 0;) |
3005 | { | |
3006 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
3007 | 32 bit version of an eight bit register, we will just use the | |
3008 | low portion, and that's OK too. */ | |
3009 | if (i.types[op] & Reg8) | |
3010 | continue; | |
3011 | ||
3012 | /* movzx and movsx should not generate this warning. */ | |
3013 | if (intel_syntax | |
3014 | && (i.tm.base_opcode == 0xfb7 | |
3015 | || i.tm.base_opcode == 0xfb6 | |
3016 | || i.tm.base_opcode == 0x63 | |
3017 | || i.tm.base_opcode == 0xfbe | |
3018 | || i.tm.base_opcode == 0xfbf)) | |
3019 | continue; | |
3020 | ||
65ec77d2 | 3021 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4) |
29b0f896 AM |
3022 | { |
3023 | /* Prohibit these changes in the 64bit mode, since the | |
3024 | lowering is more complicated. */ | |
3025 | if (flag_code == CODE_64BIT | |
3026 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
3027 | { | |
2ca3ace5 L |
3028 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3029 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3030 | i.suffix); |
3031 | return 0; | |
3032 | } | |
3033 | #if REGISTER_WARNINGS | |
3034 | if (!quiet_warnings | |
3035 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
3036 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
3037 | (i.op[op].regs + (i.types[op] & Reg16 | |
3038 | ? REGNAM_AL - REGNAM_AX | |
3039 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
3040 | i.op[op].regs->reg_name, | |
3041 | i.suffix); | |
3042 | #endif | |
3043 | continue; | |
3044 | } | |
3045 | /* Any other register is bad. */ | |
3046 | if (i.types[op] & (Reg | RegMMX | RegXMM | |
3047 | | SReg2 | SReg3 | |
3048 | | Control | Debug | Test | |
3049 | | FloatReg | FloatAcc)) | |
3050 | { | |
3051 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
3052 | i.op[op].regs->reg_name, | |
3053 | i.tm.name, | |
3054 | i.suffix); | |
3055 | return 0; | |
3056 | } | |
3057 | } | |
3058 | return 1; | |
3059 | } | |
3060 | ||
3061 | static int | |
e3bb37b5 | 3062 | check_long_reg (void) |
29b0f896 AM |
3063 | { |
3064 | int op; | |
3065 | ||
3066 | for (op = i.operands; --op >= 0;) | |
3067 | /* Reject eight bit registers, except where the template requires | |
3068 | them. (eg. movzb) */ | |
3069 | if ((i.types[op] & Reg8) != 0 | |
3070 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
3071 | { | |
3072 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
3073 | i.op[op].regs->reg_name, | |
3074 | i.tm.name, | |
3075 | i.suffix); | |
3076 | return 0; | |
3077 | } | |
3078 | /* Warn if the e prefix on a general reg is missing. */ | |
3079 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
3080 | && (i.types[op] & Reg16) != 0 | |
3081 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
3082 | { | |
3083 | /* Prohibit these changes in the 64bit mode, since the | |
3084 | lowering is more complicated. */ | |
3085 | if (flag_code == CODE_64BIT) | |
252b5132 | 3086 | { |
2ca3ace5 L |
3087 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3088 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3089 | i.suffix); |
3090 | return 0; | |
252b5132 | 3091 | } |
29b0f896 AM |
3092 | #if REGISTER_WARNINGS |
3093 | else | |
3094 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
3095 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
3096 | i.op[op].regs->reg_name, | |
3097 | i.suffix); | |
3098 | #endif | |
252b5132 | 3099 | } |
29b0f896 AM |
3100 | /* Warn if the r prefix on a general reg is missing. */ |
3101 | else if ((i.types[op] & Reg64) != 0 | |
3102 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
252b5132 | 3103 | { |
2ca3ace5 L |
3104 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3105 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3106 | i.suffix); |
3107 | return 0; | |
3108 | } | |
3109 | return 1; | |
3110 | } | |
252b5132 | 3111 | |
29b0f896 | 3112 | static int |
e3bb37b5 | 3113 | check_qword_reg (void) |
29b0f896 AM |
3114 | { |
3115 | int op; | |
252b5132 | 3116 | |
29b0f896 AM |
3117 | for (op = i.operands; --op >= 0; ) |
3118 | /* Reject eight bit registers, except where the template requires | |
3119 | them. (eg. movzb) */ | |
3120 | if ((i.types[op] & Reg8) != 0 | |
3121 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
3122 | { | |
3123 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
3124 | i.op[op].regs->reg_name, | |
3125 | i.tm.name, | |
3126 | i.suffix); | |
3127 | return 0; | |
3128 | } | |
3129 | /* Warn if the e prefix on a general reg is missing. */ | |
3130 | else if (((i.types[op] & Reg16) != 0 | |
3131 | || (i.types[op] & Reg32) != 0) | |
3132 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
3133 | { | |
3134 | /* Prohibit these changes in the 64bit mode, since the | |
3135 | lowering is more complicated. */ | |
2ca3ace5 L |
3136 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3137 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3138 | i.suffix); |
3139 | return 0; | |
252b5132 | 3140 | } |
29b0f896 AM |
3141 | return 1; |
3142 | } | |
252b5132 | 3143 | |
29b0f896 | 3144 | static int |
e3bb37b5 | 3145 | check_word_reg (void) |
29b0f896 AM |
3146 | { |
3147 | int op; | |
3148 | for (op = i.operands; --op >= 0;) | |
3149 | /* Reject eight bit registers, except where the template requires | |
3150 | them. (eg. movzb) */ | |
3151 | if ((i.types[op] & Reg8) != 0 | |
3152 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
3153 | { | |
3154 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
3155 | i.op[op].regs->reg_name, | |
3156 | i.tm.name, | |
3157 | i.suffix); | |
3158 | return 0; | |
3159 | } | |
3160 | /* Warn if the e prefix on a general reg is present. */ | |
3161 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
3162 | && (i.types[op] & Reg32) != 0 | |
3163 | && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) | |
252b5132 | 3164 | { |
29b0f896 AM |
3165 | /* Prohibit these changes in the 64bit mode, since the |
3166 | lowering is more complicated. */ | |
3167 | if (flag_code == CODE_64BIT) | |
252b5132 | 3168 | { |
2ca3ace5 L |
3169 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3170 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3171 | i.suffix); |
3172 | return 0; | |
252b5132 | 3173 | } |
29b0f896 AM |
3174 | else |
3175 | #if REGISTER_WARNINGS | |
3176 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
3177 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
3178 | i.op[op].regs->reg_name, | |
3179 | i.suffix); | |
3180 | #endif | |
3181 | } | |
3182 | return 1; | |
3183 | } | |
252b5132 | 3184 | |
29b0f896 | 3185 | static int |
e3bb37b5 | 3186 | finalize_imm (void) |
29b0f896 AM |
3187 | { |
3188 | unsigned int overlap0, overlap1, overlap2; | |
3189 | ||
3190 | overlap0 = i.types[0] & i.tm.operand_types[0]; | |
20f0a1fc | 3191 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) |
29b0f896 AM |
3192 | && overlap0 != Imm8 && overlap0 != Imm8S |
3193 | && overlap0 != Imm16 && overlap0 != Imm32S | |
3194 | && overlap0 != Imm32 && overlap0 != Imm64) | |
3195 | { | |
3196 | if (i.suffix) | |
3197 | { | |
3198 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX | |
3199 | ? Imm8 | Imm8S | |
3200 | : (i.suffix == WORD_MNEM_SUFFIX | |
3201 | ? Imm16 | |
3202 | : (i.suffix == QWORD_MNEM_SUFFIX | |
3203 | ? Imm64 | Imm32S | |
3204 | : Imm32))); | |
3205 | } | |
3206 | else if (overlap0 == (Imm16 | Imm32S | Imm32) | |
3207 | || overlap0 == (Imm16 | Imm32) | |
3208 | || overlap0 == (Imm16 | Imm32S)) | |
3209 | { | |
3210 | overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
3211 | ? Imm16 : Imm32S); | |
3212 | } | |
3213 | if (overlap0 != Imm8 && overlap0 != Imm8S | |
3214 | && overlap0 != Imm16 && overlap0 != Imm32S | |
3215 | && overlap0 != Imm32 && overlap0 != Imm64) | |
3216 | { | |
4eed87de AM |
3217 | as_bad (_("no instruction mnemonic suffix given; " |
3218 | "can't determine immediate size")); | |
29b0f896 AM |
3219 | return 0; |
3220 | } | |
3221 | } | |
3222 | i.types[0] = overlap0; | |
3223 | ||
3224 | overlap1 = i.types[1] & i.tm.operand_types[1]; | |
37edbb65 | 3225 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64)) |
29b0f896 AM |
3226 | && overlap1 != Imm8 && overlap1 != Imm8S |
3227 | && overlap1 != Imm16 && overlap1 != Imm32S | |
3228 | && overlap1 != Imm32 && overlap1 != Imm64) | |
3229 | { | |
3230 | if (i.suffix) | |
3231 | { | |
3232 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX | |
3233 | ? Imm8 | Imm8S | |
3234 | : (i.suffix == WORD_MNEM_SUFFIX | |
3235 | ? Imm16 | |
3236 | : (i.suffix == QWORD_MNEM_SUFFIX | |
3237 | ? Imm64 | Imm32S | |
3238 | : Imm32))); | |
3239 | } | |
3240 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) | |
3241 | || overlap1 == (Imm16 | Imm32) | |
3242 | || overlap1 == (Imm16 | Imm32S)) | |
3243 | { | |
3244 | overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
3245 | ? Imm16 : Imm32S); | |
3246 | } | |
3247 | if (overlap1 != Imm8 && overlap1 != Imm8S | |
3248 | && overlap1 != Imm16 && overlap1 != Imm32S | |
3249 | && overlap1 != Imm32 && overlap1 != Imm64) | |
3250 | { | |
4eed87de AM |
3251 | as_bad (_("no instruction mnemonic suffix given; " |
3252 | "can't determine immediate size %x %c"), | |
3253 | overlap1, i.suffix); | |
29b0f896 AM |
3254 | return 0; |
3255 | } | |
3256 | } | |
3257 | i.types[1] = overlap1; | |
3258 | ||
3259 | overlap2 = i.types[2] & i.tm.operand_types[2]; | |
3260 | assert ((overlap2 & Imm) == 0); | |
3261 | i.types[2] = overlap2; | |
3262 | ||
3263 | return 1; | |
3264 | } | |
3265 | ||
3266 | static int | |
e3bb37b5 | 3267 | process_operands (void) |
29b0f896 AM |
3268 | { |
3269 | /* Default segment register this instruction will use for memory | |
3270 | accesses. 0 means unknown. This is only for optimizing out | |
3271 | unnecessary segment overrides. */ | |
3272 | const seg_entry *default_seg = 0; | |
3273 | ||
3274 | /* The imul $imm, %reg instruction is converted into | |
3275 | imul $imm, %reg, %reg, and the clr %reg instruction | |
3276 | is converted into xor %reg, %reg. */ | |
3277 | if (i.tm.opcode_modifier & regKludge) | |
3278 | { | |
3279 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
3280 | /* Pretend we saw the extra register operand. */ | |
cab737b9 L |
3281 | assert (i.reg_operands == 1 |
3282 | && i.op[first_reg_op + 1].regs == 0); | |
29b0f896 AM |
3283 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
3284 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
cab737b9 L |
3285 | i.operands++; |
3286 | i.reg_operands++; | |
29b0f896 AM |
3287 | } |
3288 | ||
3289 | if (i.tm.opcode_modifier & ShortForm) | |
3290 | { | |
4eed87de | 3291 | if (i.types[0] & (SReg2 | SReg3)) |
29b0f896 | 3292 | { |
4eed87de AM |
3293 | if (i.tm.base_opcode == POP_SEG_SHORT |
3294 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 3295 | { |
4eed87de AM |
3296 | as_bad (_("you can't `pop %%cs'")); |
3297 | return 0; | |
29b0f896 | 3298 | } |
4eed87de AM |
3299 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
3300 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
3301 | i.rex |= REX_EXTZ; | |
3302 | } | |
3303 | else | |
3304 | { | |
3305 | /* The register or float register operand is in operand 0 or 1. */ | |
3306 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; | |
3307 | /* Register goes in low 3 bits of opcode. */ | |
3308 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
3309 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
3310 | i.rex |= REX_EXTZ; | |
3311 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
29b0f896 | 3312 | { |
4eed87de AM |
3313 | /* Warn about some common errors, but press on regardless. |
3314 | The first case can be generated by gcc (<= 2.8.1). */ | |
3315 | if (i.operands == 2) | |
3316 | { | |
3317 | /* Reversed arguments on faddp, fsubp, etc. */ | |
3318 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
3319 | i.op[1].regs->reg_name, | |
3320 | i.op[0].regs->reg_name); | |
3321 | } | |
3322 | else | |
3323 | { | |
3324 | /* Extraneous `l' suffix on fp insn. */ | |
3325 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
3326 | i.op[0].regs->reg_name); | |
3327 | } | |
29b0f896 AM |
3328 | } |
3329 | } | |
3330 | } | |
3331 | else if (i.tm.opcode_modifier & Modrm) | |
3332 | { | |
3333 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
3334 | must be put into the modrm byte). Now, we make the modrm and |
3335 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
3336 | |
3337 | default_seg = build_modrm_byte (); | |
3338 | } | |
8a2ed489 | 3339 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
3340 | { |
3341 | default_seg = &ds; | |
3342 | } | |
3343 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
3344 | { | |
3345 | /* For the string instructions that allow a segment override | |
3346 | on one of their operands, the default segment is ds. */ | |
3347 | default_seg = &ds; | |
3348 | } | |
3349 | ||
30123838 JB |
3350 | if ((i.tm.base_opcode == 0x8d /* lea */ |
3351 | || (i.tm.cpu_flags & CpuSVME)) | |
3352 | && i.seg[0] && !quiet_warnings) | |
3353 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
52271982 AM |
3354 | |
3355 | /* If a segment was explicitly specified, and the specified segment | |
3356 | is not the default, use an opcode prefix to select it. If we | |
3357 | never figured out what the default segment is, then default_seg | |
3358 | will be zero at this point, and the specified segment prefix will | |
3359 | always be used. */ | |
29b0f896 AM |
3360 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
3361 | { | |
3362 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
3363 | return 0; | |
3364 | } | |
3365 | return 1; | |
3366 | } | |
3367 | ||
3368 | static const seg_entry * | |
e3bb37b5 | 3369 | build_modrm_byte (void) |
29b0f896 AM |
3370 | { |
3371 | const seg_entry *default_seg = 0; | |
3372 | ||
3373 | /* i.reg_operands MUST be the number of real register operands; | |
3374 | implicit registers do not count. */ | |
3375 | if (i.reg_operands == 2) | |
3376 | { | |
3377 | unsigned int source, dest; | |
cab737b9 L |
3378 | |
3379 | switch (i.operands) | |
3380 | { | |
3381 | case 2: | |
3382 | source = 0; | |
3383 | break; | |
3384 | case 3: | |
c81128dc L |
3385 | /* When there are 3 operands, one of them may be immediate, |
3386 | which may be the first or the last operand. Otherwise, | |
3387 | the first operand must be shift count register (cl). */ | |
3388 | assert (i.imm_operands == 1 | |
3389 | || (i.imm_operands == 0 | |
3390 | && (i.types[0] & ShiftCount))); | |
3391 | source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0; | |
cab737b9 L |
3392 | break; |
3393 | case 4: | |
3394 | /* When there are 4 operands, the first two must be immediate | |
3395 | operands. The source operand will be the 3rd one. */ | |
3396 | assert (i.imm_operands == 2 | |
3397 | && (i.types[0] & Imm) | |
3398 | && (i.types[1] & Imm)); | |
3399 | source = 2; | |
3400 | break; | |
3401 | default: | |
3402 | abort (); | |
3403 | } | |
3404 | ||
29b0f896 AM |
3405 | dest = source + 1; |
3406 | ||
3407 | i.rm.mode = 3; | |
3408 | /* One of the register operands will be encoded in the i.tm.reg | |
3409 | field, the other in the combined i.tm.mode and i.tm.regmem | |
3410 | fields. If no form of this instruction supports a memory | |
3411 | destination operand, then we assume the source operand may | |
3412 | sometimes be a memory operand and so we need to store the | |
3413 | destination in the i.rm.reg field. */ | |
3414 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
3415 | { | |
3416 | i.rm.reg = i.op[dest].regs->reg_num; | |
3417 | i.rm.regmem = i.op[source].regs->reg_num; | |
3418 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
3419 | i.rex |= REX_EXTX; | |
3420 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
3421 | i.rex |= REX_EXTZ; | |
3422 | } | |
3423 | else | |
3424 | { | |
3425 | i.rm.reg = i.op[source].regs->reg_num; | |
3426 | i.rm.regmem = i.op[dest].regs->reg_num; | |
3427 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
3428 | i.rex |= REX_EXTZ; | |
3429 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
3430 | i.rex |= REX_EXTX; | |
3431 | } | |
c4a530c5 JB |
3432 | if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ))) |
3433 | { | |
3434 | if (!((i.types[0] | i.types[1]) & Control)) | |
3435 | abort (); | |
3436 | i.rex &= ~(REX_EXTX | REX_EXTZ); | |
3437 | add_prefix (LOCK_PREFIX_OPCODE); | |
3438 | } | |
29b0f896 AM |
3439 | } |
3440 | else | |
3441 | { /* If it's not 2 reg operands... */ | |
3442 | if (i.mem_operands) | |
3443 | { | |
3444 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 3445 | unsigned int op; |
4eed87de | 3446 | |
99018f42 L |
3447 | for (op = 0; op < i.operands; op++) |
3448 | if ((i.types[op] & AnyMem)) | |
3449 | break; | |
3450 | assert (op < i.operands); | |
29b0f896 AM |
3451 | |
3452 | default_seg = &ds; | |
3453 | ||
3454 | if (i.base_reg == 0) | |
3455 | { | |
3456 | i.rm.mode = 0; | |
3457 | if (!i.disp_operands) | |
3458 | fake_zero_displacement = 1; | |
3459 | if (i.index_reg == 0) | |
3460 | { | |
3461 | /* Operand is just <disp> */ | |
20f0a1fc | 3462 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
3463 | { |
3464 | /* 64bit mode overwrites the 32bit absolute | |
3465 | addressing by RIP relative addressing and | |
3466 | absolute addressing is encoded by one of the | |
3467 | redundant SIB forms. */ | |
3468 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3469 | i.sib.base = NO_BASE_REGISTER; | |
3470 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 L |
3471 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
3472 | ? Disp32S : Disp32); | |
20f0a1fc | 3473 | } |
fc225355 L |
3474 | else if ((flag_code == CODE_16BIT) |
3475 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
3476 | { |
3477 | i.rm.regmem = NO_BASE_REGISTER_16; | |
3478 | i.types[op] = Disp16; | |
3479 | } | |
3480 | else | |
3481 | { | |
3482 | i.rm.regmem = NO_BASE_REGISTER; | |
3483 | i.types[op] = Disp32; | |
29b0f896 AM |
3484 | } |
3485 | } | |
3486 | else /* !i.base_reg && i.index_reg */ | |
3487 | { | |
3488 | i.sib.index = i.index_reg->reg_num; | |
3489 | i.sib.base = NO_BASE_REGISTER; | |
3490 | i.sib.scale = i.log2_scale_factor; | |
3491 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3492 | i.types[op] &= ~Disp; | |
3493 | if (flag_code != CODE_64BIT) | |
3494 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
3495 | else | |
3496 | i.types[op] |= Disp32S; | |
3497 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
3498 | i.rex |= REX_EXTY; | |
3499 | } | |
3500 | } | |
3501 | /* RIP addressing for 64bit mode. */ | |
3502 | else if (i.base_reg->reg_type == BaseIndex) | |
3503 | { | |
3504 | i.rm.regmem = NO_BASE_REGISTER; | |
20f0a1fc | 3505 | i.types[op] &= ~ Disp; |
29b0f896 | 3506 | i.types[op] |= Disp32S; |
71903a11 | 3507 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
3508 | if (! i.disp_operands) |
3509 | fake_zero_displacement = 1; | |
29b0f896 AM |
3510 | } |
3511 | else if (i.base_reg->reg_type & Reg16) | |
3512 | { | |
3513 | switch (i.base_reg->reg_num) | |
3514 | { | |
3515 | case 3: /* (%bx) */ | |
3516 | if (i.index_reg == 0) | |
3517 | i.rm.regmem = 7; | |
3518 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
3519 | i.rm.regmem = i.index_reg->reg_num - 6; | |
3520 | break; | |
3521 | case 5: /* (%bp) */ | |
3522 | default_seg = &ss; | |
3523 | if (i.index_reg == 0) | |
3524 | { | |
3525 | i.rm.regmem = 6; | |
3526 | if ((i.types[op] & Disp) == 0) | |
3527 | { | |
3528 | /* fake (%bp) into 0(%bp) */ | |
3529 | i.types[op] |= Disp8; | |
252b5132 | 3530 | fake_zero_displacement = 1; |
29b0f896 AM |
3531 | } |
3532 | } | |
3533 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
3534 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
3535 | break; | |
3536 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
3537 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
3538 | } | |
3539 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
3540 | } | |
3541 | else /* i.base_reg and 32/64 bit mode */ | |
3542 | { | |
3543 | if (flag_code == CODE_64BIT | |
3544 | && (i.types[op] & Disp)) | |
fc225355 L |
3545 | i.types[op] = ((i.types[op] & Disp8) |
3546 | | (i.prefix[ADDR_PREFIX] == 0 | |
3547 | ? Disp32S : Disp32)); | |
20f0a1fc | 3548 | |
29b0f896 AM |
3549 | i.rm.regmem = i.base_reg->reg_num; |
3550 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
3551 | i.rex |= REX_EXTZ; | |
3552 | i.sib.base = i.base_reg->reg_num; | |
3553 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
3554 | complications. */ | |
3555 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
3556 | { | |
3557 | default_seg = &ss; | |
3558 | if (i.disp_operands == 0) | |
3559 | { | |
3560 | fake_zero_displacement = 1; | |
3561 | i.types[op] |= Disp8; | |
3562 | } | |
3563 | } | |
3564 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
3565 | { | |
3566 | default_seg = &ss; | |
3567 | } | |
3568 | i.sib.scale = i.log2_scale_factor; | |
3569 | if (i.index_reg == 0) | |
3570 | { | |
3571 | /* <disp>(%esp) becomes two byte modrm with no index | |
3572 | register. We've already stored the code for esp | |
3573 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
3574 | Any base register besides %esp will not use the | |
3575 | extra modrm byte. */ | |
3576 | i.sib.index = NO_INDEX_REGISTER; | |
3577 | #if !SCALE1_WHEN_NO_INDEX | |
3578 | /* Another case where we force the second modrm byte. */ | |
3579 | if (i.log2_scale_factor) | |
3580 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
252b5132 | 3581 | #endif |
29b0f896 AM |
3582 | } |
3583 | else | |
3584 | { | |
3585 | i.sib.index = i.index_reg->reg_num; | |
3586 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3587 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
3588 | i.rex |= REX_EXTY; | |
3589 | } | |
67a4f2b7 AO |
3590 | |
3591 | if (i.disp_operands | |
3592 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
3593 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
3594 | i.rm.mode = 0; | |
3595 | else | |
3596 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 3597 | } |
252b5132 | 3598 | |
29b0f896 AM |
3599 | if (fake_zero_displacement) |
3600 | { | |
3601 | /* Fakes a zero displacement assuming that i.types[op] | |
3602 | holds the correct displacement size. */ | |
3603 | expressionS *exp; | |
3604 | ||
3605 | assert (i.op[op].disps == 0); | |
3606 | exp = &disp_expressions[i.disp_operands++]; | |
3607 | i.op[op].disps = exp; | |
3608 | exp->X_op = O_constant; | |
3609 | exp->X_add_number = 0; | |
3610 | exp->X_add_symbol = (symbolS *) 0; | |
3611 | exp->X_op_symbol = (symbolS *) 0; | |
3612 | } | |
3613 | } | |
252b5132 | 3614 | |
29b0f896 AM |
3615 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
3616 | (if any) based on i.tm.extension_opcode. Again, we must be | |
3617 | careful to make sure that segment/control/debug/test/MMX | |
3618 | registers are coded into the i.rm.reg field. */ | |
3619 | if (i.reg_operands) | |
3620 | { | |
99018f42 L |
3621 | unsigned int op; |
3622 | ||
3623 | for (op = 0; op < i.operands; op++) | |
3624 | if ((i.types[op] & (Reg | RegMMX | RegXMM | |
3625 | | SReg2 | SReg3 | |
3626 | | Control | Debug | Test))) | |
3627 | break; | |
3628 | assert (op < i.operands); | |
3629 | ||
29b0f896 AM |
3630 | /* If there is an extension opcode to put here, the register |
3631 | number must be put into the regmem field. */ | |
3632 | if (i.tm.extension_opcode != None) | |
3633 | { | |
3634 | i.rm.regmem = i.op[op].regs->reg_num; | |
3635 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
3636 | i.rex |= REX_EXTZ; | |
3637 | } | |
3638 | else | |
3639 | { | |
3640 | i.rm.reg = i.op[op].regs->reg_num; | |
3641 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
3642 | i.rex |= REX_EXTX; | |
3643 | } | |
252b5132 | 3644 | |
29b0f896 AM |
3645 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
3646 | must set it to 3 to indicate this is a register operand | |
3647 | in the regmem field. */ | |
3648 | if (!i.mem_operands) | |
3649 | i.rm.mode = 3; | |
3650 | } | |
252b5132 | 3651 | |
29b0f896 AM |
3652 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
3653 | if (i.tm.extension_opcode != None) | |
3654 | i.rm.reg = i.tm.extension_opcode; | |
3655 | } | |
3656 | return default_seg; | |
3657 | } | |
252b5132 | 3658 | |
29b0f896 | 3659 | static void |
e3bb37b5 | 3660 | output_branch (void) |
29b0f896 AM |
3661 | { |
3662 | char *p; | |
3663 | int code16; | |
3664 | int prefix; | |
3665 | relax_substateT subtype; | |
3666 | symbolS *sym; | |
3667 | offsetT off; | |
3668 | ||
3669 | code16 = 0; | |
3670 | if (flag_code == CODE_16BIT) | |
3671 | code16 = CODE16; | |
3672 | ||
3673 | prefix = 0; | |
3674 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 3675 | { |
29b0f896 AM |
3676 | prefix = 1; |
3677 | i.prefixes -= 1; | |
3678 | code16 ^= CODE16; | |
252b5132 | 3679 | } |
29b0f896 AM |
3680 | /* Pentium4 branch hints. */ |
3681 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
3682 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 3683 | { |
29b0f896 AM |
3684 | prefix++; |
3685 | i.prefixes--; | |
3686 | } | |
3687 | if (i.prefix[REX_PREFIX] != 0) | |
3688 | { | |
3689 | prefix++; | |
3690 | i.prefixes--; | |
2f66722d AM |
3691 | } |
3692 | ||
29b0f896 AM |
3693 | if (i.prefixes != 0 && !intel_syntax) |
3694 | as_warn (_("skipping prefixes on this instruction")); | |
3695 | ||
3696 | /* It's always a symbol; End frag & setup for relax. | |
3697 | Make sure there is enough room in this frag for the largest | |
3698 | instruction we may generate in md_convert_frag. This is 2 | |
3699 | bytes for the opcode and room for the prefix and largest | |
3700 | displacement. */ | |
3701 | frag_grow (prefix + 2 + 4); | |
3702 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
3703 | p = frag_more (prefix + 1); | |
3704 | if (i.prefix[DATA_PREFIX] != 0) | |
3705 | *p++ = DATA_PREFIX_OPCODE; | |
3706 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
3707 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
3708 | *p++ = i.prefix[SEG_PREFIX]; | |
3709 | if (i.prefix[REX_PREFIX] != 0) | |
3710 | *p++ = i.prefix[REX_PREFIX]; | |
3711 | *p = i.tm.base_opcode; | |
3712 | ||
3713 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
3714 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
3715 | else if ((cpu_arch_flags & Cpu386) != 0) | |
3716 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); | |
3717 | else | |
3718 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
3719 | subtype |= code16; | |
3e73aa7c | 3720 | |
29b0f896 AM |
3721 | sym = i.op[0].disps->X_add_symbol; |
3722 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 3723 | |
29b0f896 AM |
3724 | if (i.op[0].disps->X_op != O_constant |
3725 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 3726 | { |
29b0f896 AM |
3727 | /* Handle complex expressions. */ |
3728 | sym = make_expr_symbol (i.op[0].disps); | |
3729 | off = 0; | |
3730 | } | |
3e73aa7c | 3731 | |
29b0f896 AM |
3732 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
3733 | Pass reloc in fr_var. */ | |
3734 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
3735 | } | |
3e73aa7c | 3736 | |
29b0f896 | 3737 | static void |
e3bb37b5 | 3738 | output_jump (void) |
29b0f896 AM |
3739 | { |
3740 | char *p; | |
3741 | int size; | |
3e02c1cc | 3742 | fixS *fixP; |
29b0f896 AM |
3743 | |
3744 | if (i.tm.opcode_modifier & JumpByte) | |
3745 | { | |
3746 | /* This is a loop or jecxz type instruction. */ | |
3747 | size = 1; | |
3748 | if (i.prefix[ADDR_PREFIX] != 0) | |
3749 | { | |
3750 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
3751 | i.prefixes -= 1; | |
3752 | } | |
3753 | /* Pentium4 branch hints. */ | |
3754 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
3755 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
3756 | { | |
3757 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
3758 | i.prefixes--; | |
3e73aa7c JH |
3759 | } |
3760 | } | |
29b0f896 AM |
3761 | else |
3762 | { | |
3763 | int code16; | |
3e73aa7c | 3764 | |
29b0f896 AM |
3765 | code16 = 0; |
3766 | if (flag_code == CODE_16BIT) | |
3767 | code16 = CODE16; | |
3e73aa7c | 3768 | |
29b0f896 AM |
3769 | if (i.prefix[DATA_PREFIX] != 0) |
3770 | { | |
3771 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
3772 | i.prefixes -= 1; | |
3773 | code16 ^= CODE16; | |
3774 | } | |
252b5132 | 3775 | |
29b0f896 AM |
3776 | size = 4; |
3777 | if (code16) | |
3778 | size = 2; | |
3779 | } | |
9fcc94b6 | 3780 | |
29b0f896 AM |
3781 | if (i.prefix[REX_PREFIX] != 0) |
3782 | { | |
3783 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
3784 | i.prefixes -= 1; | |
3785 | } | |
252b5132 | 3786 | |
29b0f896 AM |
3787 | if (i.prefixes != 0 && !intel_syntax) |
3788 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 3789 | |
29b0f896 AM |
3790 | p = frag_more (1 + size); |
3791 | *p++ = i.tm.base_opcode; | |
e0890092 | 3792 | |
3e02c1cc AM |
3793 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3794 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
3795 | ||
3796 | /* All jumps handled here are signed, but don't use a signed limit | |
3797 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
3798 | 4G and 64k respectively. */ | |
3799 | if (size == 1) | |
3800 | fixP->fx_signed = 1; | |
29b0f896 | 3801 | } |
e0890092 | 3802 | |
29b0f896 | 3803 | static void |
e3bb37b5 | 3804 | output_interseg_jump (void) |
29b0f896 AM |
3805 | { |
3806 | char *p; | |
3807 | int size; | |
3808 | int prefix; | |
3809 | int code16; | |
252b5132 | 3810 | |
29b0f896 AM |
3811 | code16 = 0; |
3812 | if (flag_code == CODE_16BIT) | |
3813 | code16 = CODE16; | |
a217f122 | 3814 | |
29b0f896 AM |
3815 | prefix = 0; |
3816 | if (i.prefix[DATA_PREFIX] != 0) | |
3817 | { | |
3818 | prefix = 1; | |
3819 | i.prefixes -= 1; | |
3820 | code16 ^= CODE16; | |
3821 | } | |
3822 | if (i.prefix[REX_PREFIX] != 0) | |
3823 | { | |
3824 | prefix++; | |
3825 | i.prefixes -= 1; | |
3826 | } | |
252b5132 | 3827 | |
29b0f896 AM |
3828 | size = 4; |
3829 | if (code16) | |
3830 | size = 2; | |
252b5132 | 3831 | |
29b0f896 AM |
3832 | if (i.prefixes != 0 && !intel_syntax) |
3833 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 3834 | |
29b0f896 AM |
3835 | /* 1 opcode; 2 segment; offset */ |
3836 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 3837 | |
29b0f896 AM |
3838 | if (i.prefix[DATA_PREFIX] != 0) |
3839 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 3840 | |
29b0f896 AM |
3841 | if (i.prefix[REX_PREFIX] != 0) |
3842 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 3843 | |
29b0f896 AM |
3844 | *p++ = i.tm.base_opcode; |
3845 | if (i.op[1].imms->X_op == O_constant) | |
3846 | { | |
3847 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 3848 | |
29b0f896 AM |
3849 | if (size == 2 |
3850 | && !fits_in_unsigned_word (n) | |
3851 | && !fits_in_signed_word (n)) | |
3852 | { | |
3853 | as_bad (_("16-bit jump out of range")); | |
3854 | return; | |
3855 | } | |
3856 | md_number_to_chars (p, n, size); | |
3857 | } | |
3858 | else | |
3859 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3860 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
3861 | if (i.op[0].imms->X_op != O_constant) | |
3862 | as_bad (_("can't handle non absolute segment in `%s'"), | |
3863 | i.tm.name); | |
3864 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
3865 | } | |
a217f122 | 3866 | |
29b0f896 | 3867 | static void |
e3bb37b5 | 3868 | output_insn (void) |
29b0f896 | 3869 | { |
2bbd9c25 JJ |
3870 | fragS *insn_start_frag; |
3871 | offsetT insn_start_off; | |
3872 | ||
29b0f896 AM |
3873 | /* Tie dwarf2 debug info to the address at the start of the insn. |
3874 | We can't do this after the insn has been output as the current | |
3875 | frag may have been closed off. eg. by frag_var. */ | |
3876 | dwarf2_emit_insn (0); | |
3877 | ||
2bbd9c25 JJ |
3878 | insn_start_frag = frag_now; |
3879 | insn_start_off = frag_now_fix (); | |
3880 | ||
29b0f896 AM |
3881 | /* Output jumps. */ |
3882 | if (i.tm.opcode_modifier & Jump) | |
3883 | output_branch (); | |
3884 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
3885 | output_jump (); | |
3886 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
3887 | output_interseg_jump (); | |
3888 | else | |
3889 | { | |
3890 | /* Output normal instructions here. */ | |
3891 | char *p; | |
3892 | unsigned char *q; | |
331d2d0d | 3893 | unsigned int prefix; |
252b5132 | 3894 | |
ef05d495 L |
3895 | /* All opcodes on i386 have either 1 or 2 bytes. Supplemental |
3896 | Streaming SIMD extensions 3 Instructions have 3 bytes. We may | |
3897 | use one more higher byte to specify a prefix the instruction | |
3898 | requires. */ | |
3899 | if ((i.tm.cpu_flags & CpuSSSE3) != 0) | |
bc4bd9ab | 3900 | { |
331d2d0d L |
3901 | if (i.tm.base_opcode & 0xff000000) |
3902 | { | |
3903 | prefix = (i.tm.base_opcode >> 24) & 0xff; | |
3904 | goto check_prefix; | |
3905 | } | |
3906 | } | |
3907 | else if ((i.tm.base_opcode & 0xff0000) != 0) | |
3908 | { | |
3909 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
bc4bd9ab MK |
3910 | if ((i.tm.cpu_flags & CpuPadLock) != 0) |
3911 | { | |
64e74474 | 3912 | check_prefix: |
bc4bd9ab MK |
3913 | if (prefix != REPE_PREFIX_OPCODE |
3914 | || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) | |
3915 | add_prefix (prefix); | |
3916 | } | |
3917 | else | |
331d2d0d | 3918 | add_prefix (prefix); |
0f10071e | 3919 | } |
252b5132 | 3920 | |
29b0f896 AM |
3921 | /* The prefix bytes. */ |
3922 | for (q = i.prefix; | |
3923 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
3924 | q++) | |
3925 | { | |
3926 | if (*q) | |
3927 | { | |
3928 | p = frag_more (1); | |
3929 | md_number_to_chars (p, (valueT) *q, 1); | |
3930 | } | |
3931 | } | |
252b5132 | 3932 | |
29b0f896 AM |
3933 | /* Now the opcode; be careful about word order here! */ |
3934 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
3935 | { | |
3936 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
3937 | } | |
3938 | else | |
3939 | { | |
ef05d495 | 3940 | if ((i.tm.cpu_flags & CpuSSSE3) != 0) |
331d2d0d L |
3941 | { |
3942 | p = frag_more (3); | |
3943 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
3944 | } | |
3945 | else | |
3946 | p = frag_more (2); | |
0f10071e | 3947 | |
29b0f896 AM |
3948 | /* Put out high byte first: can't use md_number_to_chars! */ |
3949 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
3950 | *p = i.tm.base_opcode & 0xff; | |
3951 | } | |
3e73aa7c | 3952 | |
29b0f896 AM |
3953 | /* Now the modrm byte and sib byte (if present). */ |
3954 | if (i.tm.opcode_modifier & Modrm) | |
3955 | { | |
3956 | p = frag_more (1); | |
3957 | md_number_to_chars (p, | |
3958 | (valueT) (i.rm.regmem << 0 | |
3959 | | i.rm.reg << 3 | |
3960 | | i.rm.mode << 6), | |
3961 | 1); | |
3962 | /* If i.rm.regmem == ESP (4) | |
3963 | && i.rm.mode != (Register mode) | |
3964 | && not 16 bit | |
3965 | ==> need second modrm byte. */ | |
3966 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
3967 | && i.rm.mode != 3 | |
3968 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
3969 | { | |
3970 | p = frag_more (1); | |
3971 | md_number_to_chars (p, | |
3972 | (valueT) (i.sib.base << 0 | |
3973 | | i.sib.index << 3 | |
3974 | | i.sib.scale << 6), | |
3975 | 1); | |
3976 | } | |
3977 | } | |
3e73aa7c | 3978 | |
29b0f896 | 3979 | if (i.disp_operands) |
2bbd9c25 | 3980 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 3981 | |
29b0f896 | 3982 | if (i.imm_operands) |
2bbd9c25 | 3983 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 3984 | } |
252b5132 | 3985 | |
29b0f896 AM |
3986 | #ifdef DEBUG386 |
3987 | if (flag_debug) | |
3988 | { | |
7b81dfbb | 3989 | pi ("" /*line*/, &i); |
29b0f896 AM |
3990 | } |
3991 | #endif /* DEBUG386 */ | |
3992 | } | |
252b5132 | 3993 | |
29b0f896 | 3994 | static void |
64e74474 | 3995 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
3996 | { |
3997 | char *p; | |
3998 | unsigned int n; | |
252b5132 | 3999 | |
29b0f896 AM |
4000 | for (n = 0; n < i.operands; n++) |
4001 | { | |
4002 | if (i.types[n] & Disp) | |
4003 | { | |
4004 | if (i.op[n].disps->X_op == O_constant) | |
4005 | { | |
4006 | int size; | |
4007 | offsetT val; | |
252b5132 | 4008 | |
29b0f896 AM |
4009 | size = 4; |
4010 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) | |
4011 | { | |
4012 | size = 2; | |
4013 | if (i.types[n] & Disp8) | |
4014 | size = 1; | |
4015 | if (i.types[n] & Disp64) | |
4016 | size = 8; | |
4017 | } | |
4018 | val = offset_in_range (i.op[n].disps->X_add_number, | |
4019 | size); | |
4020 | p = frag_more (size); | |
4021 | md_number_to_chars (p, val, size); | |
4022 | } | |
4023 | else | |
4024 | { | |
f86103b7 | 4025 | enum bfd_reloc_code_real reloc_type; |
29b0f896 AM |
4026 | int size = 4; |
4027 | int sign = 0; | |
4028 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
4029 | ||
4030 | /* The PC relative address is computed relative | |
4031 | to the instruction boundary, so in case immediate | |
4032 | fields follows, we need to adjust the value. */ | |
4033 | if (pcrel && i.imm_operands) | |
4034 | { | |
4035 | int imm_size = 4; | |
4036 | unsigned int n1; | |
252b5132 | 4037 | |
29b0f896 AM |
4038 | for (n1 = 0; n1 < i.operands; n1++) |
4039 | if (i.types[n1] & Imm) | |
252b5132 | 4040 | { |
29b0f896 | 4041 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 4042 | { |
29b0f896 AM |
4043 | imm_size = 2; |
4044 | if (i.types[n1] & (Imm8 | Imm8S)) | |
4045 | imm_size = 1; | |
4046 | if (i.types[n1] & Imm64) | |
4047 | imm_size = 8; | |
252b5132 | 4048 | } |
29b0f896 | 4049 | break; |
252b5132 | 4050 | } |
29b0f896 AM |
4051 | /* We should find the immediate. */ |
4052 | if (n1 == i.operands) | |
4053 | abort (); | |
4054 | i.op[n].disps->X_add_number -= imm_size; | |
4055 | } | |
520dc8e8 | 4056 | |
29b0f896 AM |
4057 | if (i.types[n] & Disp32S) |
4058 | sign = 1; | |
3e73aa7c | 4059 | |
29b0f896 AM |
4060 | if (i.types[n] & (Disp16 | Disp64)) |
4061 | { | |
4062 | size = 2; | |
4063 | if (i.types[n] & Disp64) | |
4064 | size = 8; | |
4065 | } | |
520dc8e8 | 4066 | |
29b0f896 | 4067 | p = frag_more (size); |
2bbd9c25 | 4068 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 4069 | if (GOT_symbol |
2bbd9c25 | 4070 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 4071 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
4072 | || reloc_type == BFD_RELOC_X86_64_32S |
4073 | || (reloc_type == BFD_RELOC_64 | |
4074 | && object_64bit)) | |
d6ab8113 JB |
4075 | && (i.op[n].disps->X_op == O_symbol |
4076 | || (i.op[n].disps->X_op == O_add | |
4077 | && ((symbol_get_value_expression | |
4078 | (i.op[n].disps->X_op_symbol)->X_op) | |
4079 | == O_subtract)))) | |
4080 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
4081 | { |
4082 | offsetT add; | |
4083 | ||
4084 | if (insn_start_frag == frag_now) | |
4085 | add = (p - frag_now->fr_literal) - insn_start_off; | |
4086 | else | |
4087 | { | |
4088 | fragS *fr; | |
4089 | ||
4090 | add = insn_start_frag->fr_fix - insn_start_off; | |
4091 | for (fr = insn_start_frag->fr_next; | |
4092 | fr && fr != frag_now; fr = fr->fr_next) | |
4093 | add += fr->fr_fix; | |
4094 | add += p - frag_now->fr_literal; | |
4095 | } | |
4096 | ||
4fa24527 | 4097 | if (!object_64bit) |
7b81dfbb AJ |
4098 | { |
4099 | reloc_type = BFD_RELOC_386_GOTPC; | |
4100 | i.op[n].imms->X_add_number += add; | |
4101 | } | |
4102 | else if (reloc_type == BFD_RELOC_64) | |
4103 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 4104 | else |
7b81dfbb AJ |
4105 | /* Don't do the adjustment for x86-64, as there |
4106 | the pcrel addressing is relative to the _next_ | |
4107 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 4108 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 4109 | } |
062cd5e7 | 4110 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 4111 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
4112 | } |
4113 | } | |
4114 | } | |
4115 | } | |
252b5132 | 4116 | |
29b0f896 | 4117 | static void |
64e74474 | 4118 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
4119 | { |
4120 | char *p; | |
4121 | unsigned int n; | |
252b5132 | 4122 | |
29b0f896 AM |
4123 | for (n = 0; n < i.operands; n++) |
4124 | { | |
4125 | if (i.types[n] & Imm) | |
4126 | { | |
4127 | if (i.op[n].imms->X_op == O_constant) | |
4128 | { | |
4129 | int size; | |
4130 | offsetT val; | |
b4cac588 | 4131 | |
29b0f896 AM |
4132 | size = 4; |
4133 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
4134 | { | |
4135 | size = 2; | |
4136 | if (i.types[n] & (Imm8 | Imm8S)) | |
4137 | size = 1; | |
4138 | else if (i.types[n] & Imm64) | |
4139 | size = 8; | |
4140 | } | |
4141 | val = offset_in_range (i.op[n].imms->X_add_number, | |
4142 | size); | |
4143 | p = frag_more (size); | |
4144 | md_number_to_chars (p, val, size); | |
4145 | } | |
4146 | else | |
4147 | { | |
4148 | /* Not absolute_section. | |
4149 | Need a 32-bit fixup (don't support 8bit | |
4150 | non-absolute imms). Try to support other | |
4151 | sizes ... */ | |
f86103b7 | 4152 | enum bfd_reloc_code_real reloc_type; |
29b0f896 AM |
4153 | int size = 4; |
4154 | int sign = 0; | |
4155 | ||
4156 | if ((i.types[n] & (Imm32S)) | |
a7d61044 JB |
4157 | && (i.suffix == QWORD_MNEM_SUFFIX |
4158 | || (!i.suffix && (i.tm.opcode_modifier & No_lSuf)))) | |
29b0f896 AM |
4159 | sign = 1; |
4160 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
4161 | { | |
4162 | size = 2; | |
4163 | if (i.types[n] & (Imm8 | Imm8S)) | |
4164 | size = 1; | |
4165 | if (i.types[n] & Imm64) | |
4166 | size = 8; | |
4167 | } | |
520dc8e8 | 4168 | |
29b0f896 AM |
4169 | p = frag_more (size); |
4170 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 4171 | |
2bbd9c25 JJ |
4172 | /* This is tough to explain. We end up with this one if we |
4173 | * have operands that look like | |
4174 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
4175 | * obtain the absolute address of the GOT, and it is strongly | |
4176 | * preferable from a performance point of view to avoid using | |
4177 | * a runtime relocation for this. The actual sequence of | |
4178 | * instructions often look something like: | |
4179 | * | |
4180 | * call .L66 | |
4181 | * .L66: | |
4182 | * popl %ebx | |
4183 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
4184 | * | |
4185 | * The call and pop essentially return the absolute address | |
4186 | * of the label .L66 and store it in %ebx. The linker itself | |
4187 | * will ultimately change the first operand of the addl so | |
4188 | * that %ebx points to the GOT, but to keep things simple, the | |
4189 | * .o file must have this operand set so that it generates not | |
4190 | * the absolute address of .L66, but the absolute address of | |
4191 | * itself. This allows the linker itself simply treat a GOTPC | |
4192 | * relocation as asking for a pcrel offset to the GOT to be | |
4193 | * added in, and the addend of the relocation is stored in the | |
4194 | * operand field for the instruction itself. | |
4195 | * | |
4196 | * Our job here is to fix the operand so that it would add | |
4197 | * the correct offset so that %ebx would point to itself. The | |
4198 | * thing that is tricky is that .-.L66 will point to the | |
4199 | * beginning of the instruction, so we need to further modify | |
4200 | * the operand so that it will point to itself. There are | |
4201 | * other cases where you have something like: | |
4202 | * | |
4203 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
4204 | * | |
4205 | * and here no correction would be required. Internally in | |
4206 | * the assembler we treat operands of this form as not being | |
4207 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
4208 | * whether it would simplify matters to do it this way. Who | |
4209 | * knows. In earlier versions of the PIC patches, the | |
4210 | * pcrel_adjust field was used to store the correction, but | |
4211 | * since the expression is not pcrel, I felt it would be | |
4212 | * confusing to do it this way. */ | |
4213 | ||
d6ab8113 | 4214 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
4215 | || reloc_type == BFD_RELOC_X86_64_32S |
4216 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
4217 | && GOT_symbol |
4218 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
4219 | && (i.op[n].imms->X_op == O_symbol | |
4220 | || (i.op[n].imms->X_op == O_add | |
4221 | && ((symbol_get_value_expression | |
4222 | (i.op[n].imms->X_op_symbol)->X_op) | |
4223 | == O_subtract)))) | |
4224 | { | |
2bbd9c25 JJ |
4225 | offsetT add; |
4226 | ||
4227 | if (insn_start_frag == frag_now) | |
4228 | add = (p - frag_now->fr_literal) - insn_start_off; | |
4229 | else | |
4230 | { | |
4231 | fragS *fr; | |
4232 | ||
4233 | add = insn_start_frag->fr_fix - insn_start_off; | |
4234 | for (fr = insn_start_frag->fr_next; | |
4235 | fr && fr != frag_now; fr = fr->fr_next) | |
4236 | add += fr->fr_fix; | |
4237 | add += p - frag_now->fr_literal; | |
4238 | } | |
4239 | ||
4fa24527 | 4240 | if (!object_64bit) |
d6ab8113 | 4241 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 4242 | else if (size == 4) |
d6ab8113 | 4243 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
4244 | else if (size == 8) |
4245 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 4246 | i.op[n].imms->X_add_number += add; |
29b0f896 | 4247 | } |
29b0f896 AM |
4248 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
4249 | i.op[n].imms, 0, reloc_type); | |
4250 | } | |
4251 | } | |
4252 | } | |
252b5132 RH |
4253 | } |
4254 | \f | |
d182319b JB |
4255 | /* x86_cons_fix_new is called via the expression parsing code when a |
4256 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
4257 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
4258 | static int cons_sign = -1; | |
4259 | ||
4260 | void | |
e3bb37b5 | 4261 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 4262 | expressionS *exp) |
d182319b JB |
4263 | { |
4264 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
4265 | ||
4266 | got_reloc = NO_RELOC; | |
4267 | ||
4268 | #ifdef TE_PE | |
4269 | if (exp->X_op == O_secrel) | |
4270 | { | |
4271 | exp->X_op = O_symbol; | |
4272 | r = BFD_RELOC_32_SECREL; | |
4273 | } | |
4274 | #endif | |
4275 | ||
4276 | fix_new_exp (frag, off, len, exp, 0, r); | |
4277 | } | |
4278 | ||
718ddfc0 JB |
4279 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
4280 | # define lex_got(reloc, adjust, types) NULL | |
4281 | #else | |
f3c180ae AM |
4282 | /* Parse operands of the form |
4283 | <symbol>@GOTOFF+<nnn> | |
4284 | and similar .plt or .got references. | |
4285 | ||
4286 | If we find one, set up the correct relocation in RELOC and copy the | |
4287 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
4288 | parsing by the calling routine. Return this buffer, and if ADJUST | |
4289 | is non-null set it to the length of the string we removed from the | |
4290 | input line. Otherwise return NULL. */ | |
4291 | static char * | |
3956db08 | 4292 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 AM |
4293 | int *adjust, |
4294 | unsigned int *types) | |
f3c180ae | 4295 | { |
7b81dfbb AJ |
4296 | /* Some of the relocations depend on the size of what field is to |
4297 | be relocated. But in our callers i386_immediate and i386_displacement | |
4298 | we don't yet know the operand size (this will be set by insn | |
4299 | matching). Hence we record the word32 relocation here, | |
4300 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
4301 | static const struct { |
4302 | const char *str; | |
4fa24527 | 4303 | const enum bfd_reloc_code_real rel[2]; |
3956db08 | 4304 | const unsigned int types64; |
f3c180ae | 4305 | } gotrel[] = { |
4eed87de AM |
4306 | { "PLTOFF", { 0, |
4307 | BFD_RELOC_X86_64_PLTOFF64 }, | |
4308 | Imm64 }, | |
4309 | { "PLT", { BFD_RELOC_386_PLT32, | |
4310 | BFD_RELOC_X86_64_PLT32 }, | |
4311 | Imm32 | Imm32S | Disp32 }, | |
4312 | { "GOTPLT", { 0, | |
4313 | BFD_RELOC_X86_64_GOTPLT64 }, | |
4314 | Imm64 | Disp64 }, | |
4315 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, | |
4316 | BFD_RELOC_X86_64_GOTOFF64 }, | |
4317 | Imm64 | Disp64 }, | |
4318 | { "GOTPCREL", { 0, | |
4319 | BFD_RELOC_X86_64_GOTPCREL }, | |
4320 | Imm32 | Imm32S | Disp32 }, | |
4321 | { "TLSGD", { BFD_RELOC_386_TLS_GD, | |
4322 | BFD_RELOC_X86_64_TLSGD }, | |
4323 | Imm32 | Imm32S | Disp32 }, | |
4324 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, | |
4325 | 0 }, | |
4326 | 0 }, | |
4327 | { "TLSLD", { 0, | |
4328 | BFD_RELOC_X86_64_TLSLD }, | |
4329 | Imm32 | Imm32S | Disp32 }, | |
4330 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, | |
4331 | BFD_RELOC_X86_64_GOTTPOFF }, | |
4332 | Imm32 | Imm32S | Disp32 }, | |
4333 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, | |
4334 | BFD_RELOC_X86_64_TPOFF32 }, | |
4335 | Imm32 | Imm32S | Imm64 | Disp32 | Disp64 }, | |
4336 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, | |
4337 | 0 }, | |
4338 | 0 }, | |
4339 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, | |
4340 | BFD_RELOC_X86_64_DTPOFF32 }, | |
4341 | Imm32 | Imm32S | Imm64 | Disp32 | Disp64 }, | |
4342 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, | |
4343 | 0 }, | |
4344 | 0 }, | |
4345 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, | |
4346 | 0 }, | |
4347 | 0 }, | |
4348 | { "GOT", { BFD_RELOC_386_GOT32, | |
4349 | BFD_RELOC_X86_64_GOT32 }, | |
4350 | Imm32 | Imm32S | Disp32 | Imm64 }, | |
4351 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, | |
4352 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
4353 | Imm32 | Imm32S | Disp32 }, | |
4354 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, | |
4355 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
4356 | Imm32 | Imm32S | Disp32 } | |
f3c180ae AM |
4357 | }; |
4358 | char *cp; | |
4359 | unsigned int j; | |
4360 | ||
718ddfc0 JB |
4361 | if (!IS_ELF) |
4362 | return NULL; | |
4363 | ||
f3c180ae AM |
4364 | for (cp = input_line_pointer; *cp != '@'; cp++) |
4365 | if (is_end_of_line[(unsigned char) *cp]) | |
4366 | return NULL; | |
4367 | ||
4368 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
4369 | { | |
4370 | int len; | |
4371 | ||
4372 | len = strlen (gotrel[j].str); | |
28f81592 | 4373 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 4374 | { |
4fa24527 | 4375 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 4376 | { |
28f81592 AM |
4377 | int first, second; |
4378 | char *tmpbuf, *past_reloc; | |
f3c180ae | 4379 | |
4fa24527 | 4380 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
4381 | if (adjust) |
4382 | *adjust = len; | |
f3c180ae | 4383 | |
3956db08 JB |
4384 | if (types) |
4385 | { | |
4386 | if (flag_code != CODE_64BIT) | |
4eed87de | 4387 | *types = Imm32 | Disp32; |
3956db08 JB |
4388 | else |
4389 | *types = gotrel[j].types64; | |
4390 | } | |
4391 | ||
f3c180ae AM |
4392 | if (GOT_symbol == NULL) |
4393 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
4394 | ||
4395 | /* Replace the relocation token with ' ', so that | |
4396 | errors like foo@GOTOFF1 will be detected. */ | |
28f81592 AM |
4397 | |
4398 | /* The length of the first part of our input line. */ | |
f3c180ae | 4399 | first = cp - input_line_pointer; |
28f81592 AM |
4400 | |
4401 | /* The second part goes from after the reloc token until | |
4402 | (and including) an end_of_line char. Don't use strlen | |
4403 | here as the end_of_line char may not be a NUL. */ | |
4404 | past_reloc = cp + 1 + len; | |
4405 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) | |
4406 | ; | |
4407 | second = cp - past_reloc; | |
4408 | ||
4409 | /* Allocate and copy string. The trailing NUL shouldn't | |
4410 | be necessary, but be safe. */ | |
4411 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae AM |
4412 | memcpy (tmpbuf, input_line_pointer, first); |
4413 | tmpbuf[first] = ' '; | |
28f81592 AM |
4414 | memcpy (tmpbuf + first + 1, past_reloc, second); |
4415 | tmpbuf[first + second + 1] = '\0'; | |
f3c180ae AM |
4416 | return tmpbuf; |
4417 | } | |
4418 | ||
4fa24527 JB |
4419 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
4420 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
4421 | return NULL; |
4422 | } | |
4423 | } | |
4424 | ||
4425 | /* Might be a symbol version string. Don't as_bad here. */ | |
4426 | return NULL; | |
4427 | } | |
4428 | ||
f3c180ae | 4429 | void |
e3bb37b5 | 4430 | x86_cons (expressionS *exp, int size) |
f3c180ae | 4431 | { |
4fa24527 | 4432 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
4433 | { |
4434 | /* Handle @GOTOFF and the like in an expression. */ | |
4435 | char *save; | |
4436 | char *gotfree_input_line; | |
4437 | int adjust; | |
4438 | ||
4439 | save = input_line_pointer; | |
3956db08 | 4440 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
4441 | if (gotfree_input_line) |
4442 | input_line_pointer = gotfree_input_line; | |
4443 | ||
4444 | expression (exp); | |
4445 | ||
4446 | if (gotfree_input_line) | |
4447 | { | |
4448 | /* expression () has merrily parsed up to the end of line, | |
4449 | or a comma - in the wrong buffer. Transfer how far | |
4450 | input_line_pointer has moved to the right buffer. */ | |
4451 | input_line_pointer = (save | |
4452 | + (input_line_pointer - gotfree_input_line) | |
4453 | + adjust); | |
4454 | free (gotfree_input_line); | |
4455 | } | |
4456 | } | |
4457 | else | |
4458 | expression (exp); | |
4459 | } | |
4460 | #endif | |
4461 | ||
d182319b | 4462 | static void signed_cons (int size) |
6482c264 | 4463 | { |
d182319b JB |
4464 | if (flag_code == CODE_64BIT) |
4465 | cons_sign = 1; | |
4466 | cons (size); | |
4467 | cons_sign = -1; | |
6482c264 NC |
4468 | } |
4469 | ||
d182319b | 4470 | #ifdef TE_PE |
6482c264 NC |
4471 | static void |
4472 | pe_directive_secrel (dummy) | |
4473 | int dummy ATTRIBUTE_UNUSED; | |
4474 | { | |
4475 | expressionS exp; | |
4476 | ||
4477 | do | |
4478 | { | |
4479 | expression (&exp); | |
4480 | if (exp.X_op == O_symbol) | |
4481 | exp.X_op = O_secrel; | |
4482 | ||
4483 | emit_expr (&exp, 4); | |
4484 | } | |
4485 | while (*input_line_pointer++ == ','); | |
4486 | ||
4487 | input_line_pointer--; | |
4488 | demand_empty_rest_of_line (); | |
4489 | } | |
6482c264 NC |
4490 | #endif |
4491 | ||
252b5132 | 4492 | static int |
70e41ade | 4493 | i386_immediate (char *imm_start) |
252b5132 RH |
4494 | { |
4495 | char *save_input_line_pointer; | |
f3c180ae | 4496 | char *gotfree_input_line; |
252b5132 | 4497 | segT exp_seg = 0; |
47926f60 | 4498 | expressionS *exp; |
3956db08 | 4499 | unsigned int types = ~0U; |
252b5132 RH |
4500 | |
4501 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
4502 | { | |
31b2323c L |
4503 | as_bad (_("at most %d immediate operands are allowed"), |
4504 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
4505 | return 0; |
4506 | } | |
4507 | ||
4508 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 4509 | i.op[this_operand].imms = exp; |
252b5132 RH |
4510 | |
4511 | if (is_space_char (*imm_start)) | |
4512 | ++imm_start; | |
4513 | ||
4514 | save_input_line_pointer = input_line_pointer; | |
4515 | input_line_pointer = imm_start; | |
4516 | ||
3956db08 | 4517 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
4518 | if (gotfree_input_line) |
4519 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
4520 | |
4521 | exp_seg = expression (exp); | |
4522 | ||
83183c0c | 4523 | SKIP_WHITESPACE (); |
252b5132 | 4524 | if (*input_line_pointer) |
f3c180ae | 4525 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
4526 | |
4527 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
4528 | if (gotfree_input_line) |
4529 | free (gotfree_input_line); | |
252b5132 | 4530 | |
2daf4fd8 | 4531 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 4532 | { |
47926f60 | 4533 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 4534 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 4535 | imm_start); |
252b5132 RH |
4536 | exp->X_op = O_constant; |
4537 | exp->X_add_number = 0; | |
4538 | exp->X_add_symbol = (symbolS *) 0; | |
4539 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 4540 | } |
3e73aa7c | 4541 | else if (exp->X_op == O_constant) |
252b5132 | 4542 | { |
47926f60 | 4543 | /* Size it properly later. */ |
3e73aa7c JH |
4544 | i.types[this_operand] |= Imm64; |
4545 | /* If BFD64, sign extend val. */ | |
4eed87de AM |
4546 | if (!use_rela_relocations |
4547 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
4548 | exp->X_add_number | |
4549 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 4550 | } |
4c63da97 | 4551 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 4552 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 4553 | && exp_seg != absolute_section |
47926f60 | 4554 | && exp_seg != text_section |
24eab124 AM |
4555 | && exp_seg != data_section |
4556 | && exp_seg != bss_section | |
4557 | && exp_seg != undefined_section | |
f86103b7 | 4558 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 4559 | { |
d0b47220 | 4560 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
4561 | return 0; |
4562 | } | |
4563 | #endif | |
bb8f5920 L |
4564 | else if (!intel_syntax && exp->X_op == O_register) |
4565 | { | |
4566 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
4567 | return 0; | |
4568 | } | |
252b5132 RH |
4569 | else |
4570 | { | |
4571 | /* This is an address. The size of the address will be | |
24eab124 | 4572 | determined later, depending on destination register, |
3e73aa7c JH |
4573 | suffix, or the default for the section. */ |
4574 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
3956db08 | 4575 | i.types[this_operand] &= types; |
252b5132 RH |
4576 | } |
4577 | ||
4578 | return 1; | |
4579 | } | |
4580 | ||
551c1ca1 | 4581 | static char * |
e3bb37b5 | 4582 | i386_scale (char *scale) |
252b5132 | 4583 | { |
551c1ca1 AM |
4584 | offsetT val; |
4585 | char *save = input_line_pointer; | |
252b5132 | 4586 | |
551c1ca1 AM |
4587 | input_line_pointer = scale; |
4588 | val = get_absolute_expression (); | |
4589 | ||
4590 | switch (val) | |
252b5132 | 4591 | { |
551c1ca1 | 4592 | case 1: |
252b5132 RH |
4593 | i.log2_scale_factor = 0; |
4594 | break; | |
551c1ca1 | 4595 | case 2: |
252b5132 RH |
4596 | i.log2_scale_factor = 1; |
4597 | break; | |
551c1ca1 | 4598 | case 4: |
252b5132 RH |
4599 | i.log2_scale_factor = 2; |
4600 | break; | |
551c1ca1 | 4601 | case 8: |
252b5132 RH |
4602 | i.log2_scale_factor = 3; |
4603 | break; | |
4604 | default: | |
a724f0f4 JB |
4605 | { |
4606 | char sep = *input_line_pointer; | |
4607 | ||
4608 | *input_line_pointer = '\0'; | |
4609 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
4610 | scale); | |
4611 | *input_line_pointer = sep; | |
4612 | input_line_pointer = save; | |
4613 | return NULL; | |
4614 | } | |
252b5132 | 4615 | } |
29b0f896 | 4616 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
4617 | { |
4618 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 4619 | 1 << i.log2_scale_factor); |
252b5132 RH |
4620 | #if SCALE1_WHEN_NO_INDEX |
4621 | i.log2_scale_factor = 0; | |
4622 | #endif | |
4623 | } | |
551c1ca1 AM |
4624 | scale = input_line_pointer; |
4625 | input_line_pointer = save; | |
4626 | return scale; | |
252b5132 RH |
4627 | } |
4628 | ||
252b5132 | 4629 | static int |
e3bb37b5 | 4630 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 4631 | { |
29b0f896 | 4632 | expressionS *exp; |
252b5132 RH |
4633 | segT exp_seg = 0; |
4634 | char *save_input_line_pointer; | |
f3c180ae | 4635 | char *gotfree_input_line; |
e05278af | 4636 | int bigdisp, override; |
3956db08 | 4637 | unsigned int types = Disp; |
252b5132 | 4638 | |
31b2323c L |
4639 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
4640 | { | |
4641 | as_bad (_("at most %d displacement operands are allowed"), | |
4642 | MAX_MEMORY_OPERANDS); | |
4643 | return 0; | |
4644 | } | |
4645 | ||
e05278af JB |
4646 | if ((i.types[this_operand] & JumpAbsolute) |
4647 | || !(current_templates->start->opcode_modifier & (Jump | JumpDword))) | |
4648 | { | |
4649 | bigdisp = Disp32; | |
4650 | override = (i.prefix[ADDR_PREFIX] != 0); | |
4651 | } | |
4652 | else | |
4653 | { | |
4654 | /* For PC-relative branches, the width of the displacement | |
4655 | is dependent upon data size, not address size. */ | |
4656 | bigdisp = 0; | |
4657 | override = (i.prefix[DATA_PREFIX] != 0); | |
4658 | } | |
3e73aa7c | 4659 | if (flag_code == CODE_64BIT) |
7ecd2f8b | 4660 | { |
e05278af | 4661 | if (!bigdisp) |
64e74474 AM |
4662 | bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX) |
4663 | ? Disp16 | |
4664 | : Disp32S | Disp32); | |
e05278af | 4665 | else if (!override) |
3956db08 | 4666 | bigdisp = Disp64 | Disp32S | Disp32; |
7ecd2f8b | 4667 | } |
e05278af JB |
4668 | else |
4669 | { | |
4670 | if (!bigdisp) | |
4671 | { | |
4672 | if (!override) | |
4673 | override = (i.suffix == (flag_code != CODE_16BIT | |
4674 | ? WORD_MNEM_SUFFIX | |
4675 | : LONG_MNEM_SUFFIX)); | |
4676 | bigdisp = Disp32; | |
4677 | } | |
4678 | if ((flag_code == CODE_16BIT) ^ override) | |
4679 | bigdisp = Disp16; | |
4680 | } | |
252b5132 RH |
4681 | i.types[this_operand] |= bigdisp; |
4682 | ||
4683 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 4684 | i.op[this_operand].disps = exp; |
252b5132 RH |
4685 | i.disp_operands++; |
4686 | save_input_line_pointer = input_line_pointer; | |
4687 | input_line_pointer = disp_start; | |
4688 | END_STRING_AND_SAVE (disp_end); | |
4689 | ||
4690 | #ifndef GCC_ASM_O_HACK | |
4691 | #define GCC_ASM_O_HACK 0 | |
4692 | #endif | |
4693 | #if GCC_ASM_O_HACK | |
4694 | END_STRING_AND_SAVE (disp_end + 1); | |
4695 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 4696 | && displacement_string_end[-1] == '+') |
252b5132 RH |
4697 | { |
4698 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
4699 | constraint within gcc asm statements. |
4700 | For instance: | |
4701 | ||
4702 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
4703 | __asm__ __volatile__ ( \ | |
4704 | "movw %w2,%0\n\t" \ | |
4705 | "movw %w1,2+%0\n\t" \ | |
4706 | "rorl $16,%1\n\t" \ | |
4707 | "movb %b1,4+%0\n\t" \ | |
4708 | "movb %4,5+%0\n\t" \ | |
4709 | "movb $0,6+%0\n\t" \ | |
4710 | "movb %h1,7+%0\n\t" \ | |
4711 | "rorl $16,%1" \ | |
4712 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
4713 | ||
4714 | This works great except that the output assembler ends | |
4715 | up looking a bit weird if it turns out that there is | |
4716 | no offset. You end up producing code that looks like: | |
4717 | ||
4718 | #APP | |
4719 | movw $235,(%eax) | |
4720 | movw %dx,2+(%eax) | |
4721 | rorl $16,%edx | |
4722 | movb %dl,4+(%eax) | |
4723 | movb $137,5+(%eax) | |
4724 | movb $0,6+(%eax) | |
4725 | movb %dh,7+(%eax) | |
4726 | rorl $16,%edx | |
4727 | #NO_APP | |
4728 | ||
47926f60 | 4729 | So here we provide the missing zero. */ |
24eab124 AM |
4730 | |
4731 | *displacement_string_end = '0'; | |
252b5132 RH |
4732 | } |
4733 | #endif | |
3956db08 | 4734 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
4735 | if (gotfree_input_line) |
4736 | input_line_pointer = gotfree_input_line; | |
252b5132 | 4737 | |
24eab124 | 4738 | exp_seg = expression (exp); |
252b5132 | 4739 | |
636c26b0 AM |
4740 | SKIP_WHITESPACE (); |
4741 | if (*input_line_pointer) | |
4742 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
4743 | #if GCC_ASM_O_HACK | |
4744 | RESTORE_END_STRING (disp_end + 1); | |
4745 | #endif | |
4746 | RESTORE_END_STRING (disp_end); | |
4747 | input_line_pointer = save_input_line_pointer; | |
636c26b0 AM |
4748 | if (gotfree_input_line) |
4749 | free (gotfree_input_line); | |
636c26b0 | 4750 | |
24eab124 AM |
4751 | /* We do this to make sure that the section symbol is in |
4752 | the symbol table. We will ultimately change the relocation | |
47926f60 | 4753 | to be relative to the beginning of the section. */ |
1ae12ab7 | 4754 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
4755 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
4756 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 4757 | { |
636c26b0 AM |
4758 | if (exp->X_op != O_symbol) |
4759 | { | |
4760 | as_bad (_("bad expression used with @%s"), | |
4761 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
4762 | ? "GOTPCREL" | |
4763 | : "GOTOFF")); | |
4764 | return 0; | |
4765 | } | |
4766 | ||
e5cb08ac | 4767 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
4768 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
4769 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
4770 | exp->X_op = O_subtract; |
4771 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 4772 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 4773 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
4774 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
4775 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 4776 | else |
29b0f896 | 4777 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 4778 | } |
252b5132 | 4779 | |
2daf4fd8 AM |
4780 | if (exp->X_op == O_absent || exp->X_op == O_big) |
4781 | { | |
47926f60 | 4782 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 4783 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
4784 | disp_start); |
4785 | exp->X_op = O_constant; | |
4786 | exp->X_add_number = 0; | |
4787 | exp->X_add_symbol = (symbolS *) 0; | |
4788 | exp->X_op_symbol = (symbolS *) 0; | |
4789 | } | |
4790 | ||
4c63da97 | 4791 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 4792 | if (exp->X_op != O_constant |
45288df1 | 4793 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 4794 | && exp_seg != absolute_section |
45288df1 AM |
4795 | && exp_seg != text_section |
4796 | && exp_seg != data_section | |
4797 | && exp_seg != bss_section | |
31312f95 | 4798 | && exp_seg != undefined_section |
f86103b7 | 4799 | && !bfd_is_com_section (exp_seg)) |
24eab124 | 4800 | { |
d0b47220 | 4801 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
24eab124 AM |
4802 | return 0; |
4803 | } | |
252b5132 | 4804 | #endif |
3956db08 JB |
4805 | |
4806 | if (!(i.types[this_operand] & ~Disp)) | |
4807 | i.types[this_operand] &= types; | |
4808 | ||
252b5132 RH |
4809 | return 1; |
4810 | } | |
4811 | ||
eecb386c | 4812 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
4813 | Return 1 on success, 0 on a failure. */ |
4814 | ||
252b5132 | 4815 | static int |
e3bb37b5 | 4816 | i386_index_check (const char *operand_string) |
252b5132 | 4817 | { |
3e73aa7c | 4818 | int ok; |
24eab124 | 4819 | #if INFER_ADDR_PREFIX |
eecb386c AM |
4820 | int fudged = 0; |
4821 | ||
24eab124 AM |
4822 | tryprefix: |
4823 | #endif | |
3e73aa7c | 4824 | ok = 1; |
30123838 JB |
4825 | if ((current_templates->start->cpu_flags & CpuSVME) |
4826 | && current_templates->end[-1].operand_types[0] == AnyMem) | |
4827 | { | |
4828 | /* Memory operands of SVME insns are special in that they only allow | |
4829 | rAX as their memory address and ignore any segment override. */ | |
4830 | unsigned RegXX; | |
4831 | ||
4832 | /* SKINIT is even more restrictive: it always requires EAX. */ | |
4833 | if (strcmp (current_templates->start->name, "skinit") == 0) | |
4834 | RegXX = Reg32; | |
4835 | else if (flag_code == CODE_64BIT) | |
4836 | RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32; | |
4837 | else | |
64e74474 AM |
4838 | RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) |
4839 | ? Reg16 | |
4840 | : Reg32); | |
30123838 JB |
4841 | if (!i.base_reg |
4842 | || !(i.base_reg->reg_type & Acc) | |
4843 | || !(i.base_reg->reg_type & RegXX) | |
4844 | || i.index_reg | |
4845 | || (i.types[0] & Disp)) | |
4846 | ok = 0; | |
4847 | } | |
4848 | else if (flag_code == CODE_64BIT) | |
64e74474 AM |
4849 | { |
4850 | unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); | |
4851 | ||
4852 | if ((i.base_reg | |
4853 | && ((i.base_reg->reg_type & RegXX) == 0) | |
4854 | && (i.base_reg->reg_type != BaseIndex | |
4855 | || i.index_reg)) | |
4856 | || (i.index_reg | |
4857 | && ((i.index_reg->reg_type & (RegXX | BaseIndex)) | |
4858 | != (RegXX | BaseIndex)))) | |
4859 | ok = 0; | |
3e73aa7c JH |
4860 | } |
4861 | else | |
4862 | { | |
4863 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
4864 | { | |
4865 | /* 16bit checks. */ | |
4866 | if ((i.base_reg | |
29b0f896 AM |
4867 | && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) |
4868 | != (Reg16 | BaseIndex))) | |
3e73aa7c | 4869 | || (i.index_reg |
29b0f896 AM |
4870 | && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) |
4871 | != (Reg16 | BaseIndex)) | |
4872 | || !(i.base_reg | |
4873 | && i.base_reg->reg_num < 6 | |
4874 | && i.index_reg->reg_num >= 6 | |
4875 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
4876 | ok = 0; |
4877 | } | |
4878 | else | |
e5cb08ac | 4879 | { |
3e73aa7c JH |
4880 | /* 32bit checks. */ |
4881 | if ((i.base_reg | |
4882 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
4883 | || (i.index_reg | |
29b0f896 AM |
4884 | && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) |
4885 | != (Reg32 | BaseIndex)))) | |
e5cb08ac | 4886 | ok = 0; |
3e73aa7c JH |
4887 | } |
4888 | } | |
4889 | if (!ok) | |
24eab124 AM |
4890 | { |
4891 | #if INFER_ADDR_PREFIX | |
20f0a1fc | 4892 | if (i.prefix[ADDR_PREFIX] == 0) |
24eab124 AM |
4893 | { |
4894 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
4895 | i.prefixes += 1; | |
b23bac36 AM |
4896 | /* Change the size of any displacement too. At most one of |
4897 | Disp16 or Disp32 is set. | |
4898 | FIXME. There doesn't seem to be any real need for separate | |
4899 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 4900 | Removing them would probably clean up the code quite a lot. */ |
4eed87de AM |
4901 | if (flag_code != CODE_64BIT |
4902 | && (i.types[this_operand] & (Disp16 | Disp32))) | |
64e74474 | 4903 | i.types[this_operand] ^= (Disp16 | Disp32); |
eecb386c | 4904 | fudged = 1; |
24eab124 AM |
4905 | goto tryprefix; |
4906 | } | |
eecb386c AM |
4907 | if (fudged) |
4908 | as_bad (_("`%s' is not a valid base/index expression"), | |
4909 | operand_string); | |
4910 | else | |
c388dee8 | 4911 | #endif |
eecb386c AM |
4912 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
4913 | operand_string, | |
3e73aa7c | 4914 | flag_code_names[flag_code]); |
24eab124 | 4915 | } |
20f0a1fc | 4916 | return ok; |
24eab124 | 4917 | } |
252b5132 | 4918 | |
252b5132 | 4919 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 4920 | on error. */ |
252b5132 | 4921 | |
252b5132 | 4922 | static int |
e3bb37b5 | 4923 | i386_operand (char *operand_string) |
252b5132 | 4924 | { |
af6bdddf AM |
4925 | const reg_entry *r; |
4926 | char *end_op; | |
24eab124 | 4927 | char *op_string = operand_string; |
252b5132 | 4928 | |
24eab124 | 4929 | if (is_space_char (*op_string)) |
252b5132 RH |
4930 | ++op_string; |
4931 | ||
24eab124 | 4932 | /* We check for an absolute prefix (differentiating, |
47926f60 | 4933 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
4934 | if (*op_string == ABSOLUTE_PREFIX) |
4935 | { | |
4936 | ++op_string; | |
4937 | if (is_space_char (*op_string)) | |
4938 | ++op_string; | |
4939 | i.types[this_operand] |= JumpAbsolute; | |
4940 | } | |
252b5132 | 4941 | |
47926f60 | 4942 | /* Check if operand is a register. */ |
4d1bb795 | 4943 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 4944 | { |
24eab124 AM |
4945 | /* Check for a segment override by searching for ':' after a |
4946 | segment register. */ | |
4947 | op_string = end_op; | |
4948 | if (is_space_char (*op_string)) | |
4949 | ++op_string; | |
4950 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
4951 | { | |
4952 | switch (r->reg_num) | |
4953 | { | |
4954 | case 0: | |
4955 | i.seg[i.mem_operands] = &es; | |
4956 | break; | |
4957 | case 1: | |
4958 | i.seg[i.mem_operands] = &cs; | |
4959 | break; | |
4960 | case 2: | |
4961 | i.seg[i.mem_operands] = &ss; | |
4962 | break; | |
4963 | case 3: | |
4964 | i.seg[i.mem_operands] = &ds; | |
4965 | break; | |
4966 | case 4: | |
4967 | i.seg[i.mem_operands] = &fs; | |
4968 | break; | |
4969 | case 5: | |
4970 | i.seg[i.mem_operands] = &gs; | |
4971 | break; | |
4972 | } | |
252b5132 | 4973 | |
24eab124 | 4974 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
4975 | ++op_string; |
4976 | if (is_space_char (*op_string)) | |
24eab124 | 4977 | ++op_string; |
252b5132 | 4978 | |
24eab124 AM |
4979 | if (!is_digit_char (*op_string) |
4980 | && !is_identifier_char (*op_string) | |
4981 | && *op_string != '(' | |
4982 | && *op_string != ABSOLUTE_PREFIX) | |
4983 | { | |
4984 | as_bad (_("bad memory operand `%s'"), op_string); | |
4985 | return 0; | |
4986 | } | |
47926f60 | 4987 | /* Handle case of %es:*foo. */ |
24eab124 AM |
4988 | if (*op_string == ABSOLUTE_PREFIX) |
4989 | { | |
4990 | ++op_string; | |
4991 | if (is_space_char (*op_string)) | |
4992 | ++op_string; | |
4993 | i.types[this_operand] |= JumpAbsolute; | |
4994 | } | |
4995 | goto do_memory_reference; | |
4996 | } | |
4997 | if (*op_string) | |
4998 | { | |
d0b47220 | 4999 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
5000 | return 0; |
5001 | } | |
5002 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 5003 | i.op[this_operand].regs = r; |
24eab124 AM |
5004 | i.reg_operands++; |
5005 | } | |
af6bdddf AM |
5006 | else if (*op_string == REGISTER_PREFIX) |
5007 | { | |
5008 | as_bad (_("bad register name `%s'"), op_string); | |
5009 | return 0; | |
5010 | } | |
24eab124 | 5011 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 5012 | { |
24eab124 AM |
5013 | ++op_string; |
5014 | if (i.types[this_operand] & JumpAbsolute) | |
5015 | { | |
d0b47220 | 5016 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
5017 | return 0; |
5018 | } | |
5019 | if (!i386_immediate (op_string)) | |
5020 | return 0; | |
5021 | } | |
5022 | else if (is_digit_char (*op_string) | |
5023 | || is_identifier_char (*op_string) | |
e5cb08ac | 5024 | || *op_string == '(') |
24eab124 | 5025 | { |
47926f60 | 5026 | /* This is a memory reference of some sort. */ |
af6bdddf | 5027 | char *base_string; |
252b5132 | 5028 | |
47926f60 | 5029 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
5030 | char *displacement_string_start; |
5031 | char *displacement_string_end; | |
252b5132 | 5032 | |
24eab124 | 5033 | do_memory_reference: |
24eab124 AM |
5034 | if ((i.mem_operands == 1 |
5035 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5036 | || i.mem_operands == 2) | |
5037 | { | |
5038 | as_bad (_("too many memory references for `%s'"), | |
5039 | current_templates->start->name); | |
5040 | return 0; | |
5041 | } | |
252b5132 | 5042 | |
24eab124 AM |
5043 | /* Check for base index form. We detect the base index form by |
5044 | looking for an ')' at the end of the operand, searching | |
5045 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
5046 | after the '('. */ | |
af6bdddf | 5047 | base_string = op_string + strlen (op_string); |
c3332e24 | 5048 | |
af6bdddf AM |
5049 | --base_string; |
5050 | if (is_space_char (*base_string)) | |
5051 | --base_string; | |
252b5132 | 5052 | |
47926f60 | 5053 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
5054 | displacement_string_start = op_string; |
5055 | displacement_string_end = base_string + 1; | |
252b5132 | 5056 | |
24eab124 AM |
5057 | if (*base_string == ')') |
5058 | { | |
af6bdddf | 5059 | char *temp_string; |
24eab124 AM |
5060 | unsigned int parens_balanced = 1; |
5061 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 5062 | equal, so this loop will not be infinite. */ |
24eab124 AM |
5063 | do |
5064 | { | |
5065 | base_string--; | |
5066 | if (*base_string == ')') | |
5067 | parens_balanced++; | |
5068 | if (*base_string == '(') | |
5069 | parens_balanced--; | |
5070 | } | |
5071 | while (parens_balanced); | |
c3332e24 | 5072 | |
af6bdddf | 5073 | temp_string = base_string; |
c3332e24 | 5074 | |
24eab124 | 5075 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
5076 | ++base_string; |
5077 | if (is_space_char (*base_string)) | |
24eab124 | 5078 | ++base_string; |
252b5132 | 5079 | |
af6bdddf | 5080 | if (*base_string == ',' |
4eed87de AM |
5081 | || ((i.base_reg = parse_register (base_string, &end_op)) |
5082 | != NULL)) | |
252b5132 | 5083 | { |
af6bdddf | 5084 | displacement_string_end = temp_string; |
252b5132 | 5085 | |
af6bdddf | 5086 | i.types[this_operand] |= BaseIndex; |
252b5132 | 5087 | |
af6bdddf | 5088 | if (i.base_reg) |
24eab124 | 5089 | { |
24eab124 AM |
5090 | base_string = end_op; |
5091 | if (is_space_char (*base_string)) | |
5092 | ++base_string; | |
af6bdddf AM |
5093 | } |
5094 | ||
5095 | /* There may be an index reg or scale factor here. */ | |
5096 | if (*base_string == ',') | |
5097 | { | |
5098 | ++base_string; | |
5099 | if (is_space_char (*base_string)) | |
5100 | ++base_string; | |
5101 | ||
4eed87de AM |
5102 | if ((i.index_reg = parse_register (base_string, &end_op)) |
5103 | != NULL) | |
24eab124 | 5104 | { |
af6bdddf | 5105 | base_string = end_op; |
24eab124 AM |
5106 | if (is_space_char (*base_string)) |
5107 | ++base_string; | |
af6bdddf AM |
5108 | if (*base_string == ',') |
5109 | { | |
5110 | ++base_string; | |
5111 | if (is_space_char (*base_string)) | |
5112 | ++base_string; | |
5113 | } | |
e5cb08ac | 5114 | else if (*base_string != ')') |
af6bdddf | 5115 | { |
4eed87de AM |
5116 | as_bad (_("expecting `,' or `)' " |
5117 | "after index register in `%s'"), | |
af6bdddf AM |
5118 | operand_string); |
5119 | return 0; | |
5120 | } | |
24eab124 | 5121 | } |
af6bdddf | 5122 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 5123 | { |
af6bdddf | 5124 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
5125 | return 0; |
5126 | } | |
252b5132 | 5127 | |
47926f60 | 5128 | /* Check for scale factor. */ |
551c1ca1 | 5129 | if (*base_string != ')') |
af6bdddf | 5130 | { |
551c1ca1 AM |
5131 | char *end_scale = i386_scale (base_string); |
5132 | ||
5133 | if (!end_scale) | |
af6bdddf | 5134 | return 0; |
24eab124 | 5135 | |
551c1ca1 | 5136 | base_string = end_scale; |
af6bdddf AM |
5137 | if (is_space_char (*base_string)) |
5138 | ++base_string; | |
5139 | if (*base_string != ')') | |
5140 | { | |
4eed87de AM |
5141 | as_bad (_("expecting `)' " |
5142 | "after scale factor in `%s'"), | |
af6bdddf AM |
5143 | operand_string); |
5144 | return 0; | |
5145 | } | |
5146 | } | |
5147 | else if (!i.index_reg) | |
24eab124 | 5148 | { |
4eed87de AM |
5149 | as_bad (_("expecting index register or scale factor " |
5150 | "after `,'; got '%c'"), | |
af6bdddf | 5151 | *base_string); |
24eab124 AM |
5152 | return 0; |
5153 | } | |
5154 | } | |
af6bdddf | 5155 | else if (*base_string != ')') |
24eab124 | 5156 | { |
4eed87de AM |
5157 | as_bad (_("expecting `,' or `)' " |
5158 | "after base register in `%s'"), | |
af6bdddf | 5159 | operand_string); |
24eab124 AM |
5160 | return 0; |
5161 | } | |
c3332e24 | 5162 | } |
af6bdddf | 5163 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 5164 | { |
af6bdddf | 5165 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 5166 | return 0; |
c3332e24 | 5167 | } |
24eab124 AM |
5168 | } |
5169 | ||
5170 | /* If there's an expression beginning the operand, parse it, | |
5171 | assuming displacement_string_start and | |
5172 | displacement_string_end are meaningful. */ | |
5173 | if (displacement_string_start != displacement_string_end) | |
5174 | { | |
5175 | if (!i386_displacement (displacement_string_start, | |
5176 | displacement_string_end)) | |
5177 | return 0; | |
5178 | } | |
5179 | ||
5180 | /* Special case for (%dx) while doing input/output op. */ | |
5181 | if (i.base_reg | |
5182 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
5183 | && i.index_reg == 0 | |
5184 | && i.log2_scale_factor == 0 | |
5185 | && i.seg[i.mem_operands] == 0 | |
5186 | && (i.types[this_operand] & Disp) == 0) | |
5187 | { | |
5188 | i.types[this_operand] = InOutPortReg; | |
5189 | return 1; | |
5190 | } | |
5191 | ||
eecb386c AM |
5192 | if (i386_index_check (operand_string) == 0) |
5193 | return 0; | |
24eab124 AM |
5194 | i.mem_operands++; |
5195 | } | |
5196 | else | |
ce8a8b2f AM |
5197 | { |
5198 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
5199 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
5200 | output_invalid (*op_string), | |
5201 | this_operand + 1, | |
5202 | op_string); | |
5203 | return 0; | |
5204 | } | |
47926f60 | 5205 | return 1; /* Normal return. */ |
252b5132 RH |
5206 | } |
5207 | \f | |
ee7fcc42 AM |
5208 | /* md_estimate_size_before_relax() |
5209 | ||
5210 | Called just before relax() for rs_machine_dependent frags. The x86 | |
5211 | assembler uses these frags to handle variable size jump | |
5212 | instructions. | |
5213 | ||
5214 | Any symbol that is now undefined will not become defined. | |
5215 | Return the correct fr_subtype in the frag. | |
5216 | Return the initial "guess for variable size of frag" to caller. | |
5217 | The guess is actually the growth beyond the fixed part. Whatever | |
5218 | we do to grow the fixed or variable part contributes to our | |
5219 | returned value. */ | |
5220 | ||
252b5132 RH |
5221 | int |
5222 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
5223 | fragS *fragP; |
5224 | segT segment; | |
252b5132 | 5225 | { |
252b5132 | 5226 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
5227 | check for un-relaxable symbols. On an ELF system, we can't relax |
5228 | an externally visible symbol, because it may be overridden by a | |
5229 | shared library. */ | |
5230 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 5231 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 5232 | || (IS_ELF |
31312f95 AM |
5233 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
5234 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
5235 | #endif |
5236 | ) | |
252b5132 | 5237 | { |
b98ef147 AM |
5238 | /* Symbol is undefined in this segment, or we need to keep a |
5239 | reloc so that weak symbols can be overridden. */ | |
5240 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 5241 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
5242 | unsigned char *opcode; |
5243 | int old_fr_fix; | |
f6af82bd | 5244 | |
ee7fcc42 AM |
5245 | if (fragP->fr_var != NO_RELOC) |
5246 | reloc_type = fragP->fr_var; | |
b98ef147 | 5247 | else if (size == 2) |
f6af82bd AM |
5248 | reloc_type = BFD_RELOC_16_PCREL; |
5249 | else | |
5250 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 5251 | |
ee7fcc42 AM |
5252 | old_fr_fix = fragP->fr_fix; |
5253 | opcode = (unsigned char *) fragP->fr_opcode; | |
5254 | ||
fddf5b5b | 5255 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 5256 | { |
fddf5b5b AM |
5257 | case UNCOND_JUMP: |
5258 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 5259 | opcode[0] = 0xe9; |
252b5132 | 5260 | fragP->fr_fix += size; |
062cd5e7 AS |
5261 | fix_new (fragP, old_fr_fix, size, |
5262 | fragP->fr_symbol, | |
5263 | fragP->fr_offset, 1, | |
5264 | reloc_type); | |
252b5132 RH |
5265 | break; |
5266 | ||
fddf5b5b | 5267 | case COND_JUMP86: |
412167cb AM |
5268 | if (size == 2 |
5269 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
5270 | { |
5271 | /* Negate the condition, and branch past an | |
5272 | unconditional jump. */ | |
5273 | opcode[0] ^= 1; | |
5274 | opcode[1] = 3; | |
5275 | /* Insert an unconditional jump. */ | |
5276 | opcode[2] = 0xe9; | |
5277 | /* We added two extra opcode bytes, and have a two byte | |
5278 | offset. */ | |
5279 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
5280 | fix_new (fragP, old_fr_fix + 2, 2, |
5281 | fragP->fr_symbol, | |
5282 | fragP->fr_offset, 1, | |
5283 | reloc_type); | |
fddf5b5b AM |
5284 | break; |
5285 | } | |
5286 | /* Fall through. */ | |
5287 | ||
5288 | case COND_JUMP: | |
412167cb AM |
5289 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
5290 | { | |
3e02c1cc AM |
5291 | fixS *fixP; |
5292 | ||
412167cb | 5293 | fragP->fr_fix += 1; |
3e02c1cc AM |
5294 | fixP = fix_new (fragP, old_fr_fix, 1, |
5295 | fragP->fr_symbol, | |
5296 | fragP->fr_offset, 1, | |
5297 | BFD_RELOC_8_PCREL); | |
5298 | fixP->fx_signed = 1; | |
412167cb AM |
5299 | break; |
5300 | } | |
93c2a809 | 5301 | |
24eab124 | 5302 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 5303 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 5304 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 5305 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
5306 | /* We've added an opcode byte. */ |
5307 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
5308 | fix_new (fragP, old_fr_fix + 1, size, |
5309 | fragP->fr_symbol, | |
5310 | fragP->fr_offset, 1, | |
5311 | reloc_type); | |
252b5132 | 5312 | break; |
fddf5b5b AM |
5313 | |
5314 | default: | |
5315 | BAD_CASE (fragP->fr_subtype); | |
5316 | break; | |
252b5132 RH |
5317 | } |
5318 | frag_wane (fragP); | |
ee7fcc42 | 5319 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 5320 | } |
93c2a809 | 5321 | |
93c2a809 AM |
5322 | /* Guess size depending on current relax state. Initially the relax |
5323 | state will correspond to a short jump and we return 1, because | |
5324 | the variable part of the frag (the branch offset) is one byte | |
5325 | long. However, we can relax a section more than once and in that | |
5326 | case we must either set fr_subtype back to the unrelaxed state, | |
5327 | or return the value for the appropriate branch. */ | |
5328 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
5329 | } |
5330 | ||
47926f60 KH |
5331 | /* Called after relax() is finished. |
5332 | ||
5333 | In: Address of frag. | |
5334 | fr_type == rs_machine_dependent. | |
5335 | fr_subtype is what the address relaxed to. | |
5336 | ||
5337 | Out: Any fixSs and constants are set up. | |
5338 | Caller will turn frag into a ".space 0". */ | |
5339 | ||
252b5132 RH |
5340 | void |
5341 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
5342 | bfd *abfd ATTRIBUTE_UNUSED; |
5343 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 5344 | fragS *fragP; |
252b5132 | 5345 | { |
29b0f896 | 5346 | unsigned char *opcode; |
252b5132 | 5347 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
5348 | offsetT target_address; |
5349 | offsetT opcode_address; | |
252b5132 | 5350 | unsigned int extension = 0; |
847f7ad4 | 5351 | offsetT displacement_from_opcode_start; |
252b5132 RH |
5352 | |
5353 | opcode = (unsigned char *) fragP->fr_opcode; | |
5354 | ||
47926f60 | 5355 | /* Address we want to reach in file space. */ |
252b5132 | 5356 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 5357 | |
47926f60 | 5358 | /* Address opcode resides at in file space. */ |
252b5132 RH |
5359 | opcode_address = fragP->fr_address + fragP->fr_fix; |
5360 | ||
47926f60 | 5361 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
5362 | displacement_from_opcode_start = target_address - opcode_address; |
5363 | ||
fddf5b5b | 5364 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 5365 | { |
47926f60 KH |
5366 | /* Don't have to change opcode. */ |
5367 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 5368 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
5369 | } |
5370 | else | |
5371 | { | |
5372 | if (no_cond_jump_promotion | |
5373 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
5374 | as_warn_where (fragP->fr_file, fragP->fr_line, |
5375 | _("long jump required")); | |
252b5132 | 5376 | |
fddf5b5b AM |
5377 | switch (fragP->fr_subtype) |
5378 | { | |
5379 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
5380 | extension = 4; /* 1 opcode + 4 displacement */ | |
5381 | opcode[0] = 0xe9; | |
5382 | where_to_put_displacement = &opcode[1]; | |
5383 | break; | |
252b5132 | 5384 | |
fddf5b5b AM |
5385 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
5386 | extension = 2; /* 1 opcode + 2 displacement */ | |
5387 | opcode[0] = 0xe9; | |
5388 | where_to_put_displacement = &opcode[1]; | |
5389 | break; | |
252b5132 | 5390 | |
fddf5b5b AM |
5391 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
5392 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
5393 | extension = 5; /* 2 opcode + 4 displacement */ | |
5394 | opcode[1] = opcode[0] + 0x10; | |
5395 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
5396 | where_to_put_displacement = &opcode[2]; | |
5397 | break; | |
252b5132 | 5398 | |
fddf5b5b AM |
5399 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
5400 | extension = 3; /* 2 opcode + 2 displacement */ | |
5401 | opcode[1] = opcode[0] + 0x10; | |
5402 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
5403 | where_to_put_displacement = &opcode[2]; | |
5404 | break; | |
252b5132 | 5405 | |
fddf5b5b AM |
5406 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
5407 | extension = 4; | |
5408 | opcode[0] ^= 1; | |
5409 | opcode[1] = 3; | |
5410 | opcode[2] = 0xe9; | |
5411 | where_to_put_displacement = &opcode[3]; | |
5412 | break; | |
5413 | ||
5414 | default: | |
5415 | BAD_CASE (fragP->fr_subtype); | |
5416 | break; | |
5417 | } | |
252b5132 | 5418 | } |
fddf5b5b | 5419 | |
7b81dfbb AJ |
5420 | /* If size if less then four we are sure that the operand fits, |
5421 | but if it's 4, then it could be that the displacement is larger | |
5422 | then -/+ 2GB. */ | |
5423 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
5424 | && object_64bit | |
5425 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
5426 | + ((addressT) 1 << 31)) |
5427 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
5428 | { |
5429 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
5430 | _("jump target out of range")); | |
5431 | /* Make us emit 0. */ | |
5432 | displacement_from_opcode_start = extension; | |
5433 | } | |
47926f60 | 5434 | /* Now put displacement after opcode. */ |
252b5132 RH |
5435 | md_number_to_chars ((char *) where_to_put_displacement, |
5436 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 5437 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
5438 | fragP->fr_fix += extension; |
5439 | } | |
5440 | \f | |
47926f60 KH |
5441 | /* Size of byte displacement jmp. */ |
5442 | int md_short_jump_size = 2; | |
5443 | ||
5444 | /* Size of dword displacement jmp. */ | |
5445 | int md_long_jump_size = 5; | |
252b5132 | 5446 | |
252b5132 RH |
5447 | void |
5448 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
5449 | char *ptr; | |
5450 | addressT from_addr, to_addr; | |
ab9da554 ILT |
5451 | fragS *frag ATTRIBUTE_UNUSED; |
5452 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 5453 | { |
847f7ad4 | 5454 | offsetT offset; |
252b5132 RH |
5455 | |
5456 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
5457 | /* Opcode for byte-disp jump. */ |
5458 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
5459 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
5460 | } | |
5461 | ||
5462 | void | |
5463 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
5464 | char *ptr; | |
5465 | addressT from_addr, to_addr; | |
a38cf1db AM |
5466 | fragS *frag ATTRIBUTE_UNUSED; |
5467 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 5468 | { |
847f7ad4 | 5469 | offsetT offset; |
252b5132 | 5470 | |
a38cf1db AM |
5471 | offset = to_addr - (from_addr + 5); |
5472 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
5473 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
5474 | } |
5475 | \f | |
5476 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
5477 | by our caller that we have all the info we need to fix it up. | |
5478 | ||
5479 | On the 386, immediates, displacements, and data pointers are all in | |
5480 | the same (little-endian) format, so we don't need to care about which | |
5481 | we are handling. */ | |
5482 | ||
94f592af | 5483 | void |
55cf6793 | 5484 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
5485 | /* The fix we're to put in. */ |
5486 | fixS *fixP; | |
47926f60 | 5487 | /* Pointer to the value of the bits. */ |
c6682705 | 5488 | valueT *valP; |
47926f60 KH |
5489 | /* Segment fix is from. */ |
5490 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 5491 | { |
94f592af | 5492 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 5493 | valueT value = *valP; |
252b5132 | 5494 | |
f86103b7 | 5495 | #if !defined (TE_Mach) |
93382f6d AM |
5496 | if (fixP->fx_pcrel) |
5497 | { | |
5498 | switch (fixP->fx_r_type) | |
5499 | { | |
5865bb77 ILT |
5500 | default: |
5501 | break; | |
5502 | ||
d6ab8113 JB |
5503 | case BFD_RELOC_64: |
5504 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
5505 | break; | |
93382f6d | 5506 | case BFD_RELOC_32: |
ae8887b5 | 5507 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
5508 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
5509 | break; | |
5510 | case BFD_RELOC_16: | |
5511 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
5512 | break; | |
5513 | case BFD_RELOC_8: | |
5514 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
5515 | break; | |
5516 | } | |
5517 | } | |
252b5132 | 5518 | |
a161fe53 | 5519 | if (fixP->fx_addsy != NULL |
31312f95 | 5520 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 5521 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
5522 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
5523 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
5524 | && !use_rela_relocations) | |
252b5132 | 5525 | { |
31312f95 AM |
5526 | /* This is a hack. There should be a better way to handle this. |
5527 | This covers for the fact that bfd_install_relocation will | |
5528 | subtract the current location (for partial_inplace, PC relative | |
5529 | relocations); see more below. */ | |
252b5132 | 5530 | #ifndef OBJ_AOUT |
718ddfc0 | 5531 | if (IS_ELF |
252b5132 RH |
5532 | #ifdef TE_PE |
5533 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
5534 | #endif | |
5535 | ) | |
5536 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
5537 | #endif | |
5538 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 5539 | if (IS_ELF) |
252b5132 | 5540 | { |
6539b54b | 5541 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 5542 | |
6539b54b | 5543 | if ((sym_seg == seg |
2f66722d | 5544 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 5545 | && sym_seg != absolute_section)) |
ae6063d4 | 5546 | && !generic_force_reloc (fixP)) |
2f66722d AM |
5547 | { |
5548 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
5549 | bfd_install_relocation subtracts them out again. I think |
5550 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
5551 | it. FIXME. */ |
5552 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
5553 | } | |
252b5132 RH |
5554 | } |
5555 | #endif | |
5556 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
5557 | /* For some reason, the PE format does not store a |
5558 | section address offset for a PC relative symbol. */ | |
5559 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 5560 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
5561 | value += md_pcrel_from (fixP); |
5562 | #endif | |
5563 | } | |
5564 | ||
5565 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 5566 | and we must not disappoint it. */ |
252b5132 | 5567 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 5568 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
5569 | switch (fixP->fx_r_type) |
5570 | { | |
5571 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 5572 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
5573 | /* Make the jump instruction point to the address of the operand. At |
5574 | runtime we merely add the offset to the actual PLT entry. */ | |
5575 | value = -4; | |
5576 | break; | |
31312f95 | 5577 | |
13ae64f3 JJ |
5578 | case BFD_RELOC_386_TLS_GD: |
5579 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 5580 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
5581 | case BFD_RELOC_386_TLS_IE: |
5582 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 5583 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
5584 | case BFD_RELOC_X86_64_TLSGD: |
5585 | case BFD_RELOC_X86_64_TLSLD: | |
5586 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 5587 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
5588 | value = 0; /* Fully resolved at runtime. No addend. */ |
5589 | /* Fallthrough */ | |
5590 | case BFD_RELOC_386_TLS_LE: | |
5591 | case BFD_RELOC_386_TLS_LDO_32: | |
5592 | case BFD_RELOC_386_TLS_LE_32: | |
5593 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 5594 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 5595 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 5596 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
5597 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
5598 | break; | |
5599 | ||
67a4f2b7 AO |
5600 | case BFD_RELOC_386_TLS_DESC_CALL: |
5601 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
5602 | value = 0; /* Fully resolved at runtime. No addend. */ | |
5603 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
5604 | fixP->fx_done = 0; | |
5605 | return; | |
5606 | ||
00f7efb6 JJ |
5607 | case BFD_RELOC_386_GOT32: |
5608 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
5609 | value = 0; /* Fully resolved at runtime. No addend. */ |
5610 | break; | |
47926f60 KH |
5611 | |
5612 | case BFD_RELOC_VTABLE_INHERIT: | |
5613 | case BFD_RELOC_VTABLE_ENTRY: | |
5614 | fixP->fx_done = 0; | |
94f592af | 5615 | return; |
47926f60 KH |
5616 | |
5617 | default: | |
5618 | break; | |
5619 | } | |
5620 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 5621 | *valP = value; |
f86103b7 | 5622 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 5623 | |
3e73aa7c | 5624 | /* Are we finished with this relocation now? */ |
c6682705 | 5625 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
5626 | fixP->fx_done = 1; |
5627 | else if (use_rela_relocations) | |
5628 | { | |
5629 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
5630 | /* Remember value for tc_gen_reloc. */ |
5631 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
5632 | value = 0; |
5633 | } | |
f86103b7 | 5634 | |
94f592af | 5635 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 5636 | } |
252b5132 | 5637 | \f |
252b5132 RH |
5638 | #define MAX_LITTLENUMS 6 |
5639 | ||
47926f60 KH |
5640 | /* Turn the string pointed to by litP into a floating point constant |
5641 | of type TYPE, and emit the appropriate bytes. The number of | |
5642 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
5643 | returned, or NULL on OK. */ | |
5644 | ||
252b5132 RH |
5645 | char * |
5646 | md_atof (type, litP, sizeP) | |
2ab9b79e | 5647 | int type; |
252b5132 RH |
5648 | char *litP; |
5649 | int *sizeP; | |
5650 | { | |
5651 | int prec; | |
5652 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
5653 | LITTLENUM_TYPE *wordP; | |
5654 | char *t; | |
5655 | ||
5656 | switch (type) | |
5657 | { | |
5658 | case 'f': | |
5659 | case 'F': | |
5660 | prec = 2; | |
5661 | break; | |
5662 | ||
5663 | case 'd': | |
5664 | case 'D': | |
5665 | prec = 4; | |
5666 | break; | |
5667 | ||
5668 | case 'x': | |
5669 | case 'X': | |
5670 | prec = 5; | |
5671 | break; | |
5672 | ||
5673 | default: | |
5674 | *sizeP = 0; | |
5675 | return _("Bad call to md_atof ()"); | |
5676 | } | |
5677 | t = atof_ieee (input_line_pointer, type, words); | |
5678 | if (t) | |
5679 | input_line_pointer = t; | |
5680 | ||
5681 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
5682 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
5683 | the bigendian 386. */ | |
5684 | for (wordP = words + prec - 1; prec--;) | |
5685 | { | |
5686 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
5687 | litP += sizeof (LITTLENUM_TYPE); | |
5688 | } | |
5689 | return 0; | |
5690 | } | |
5691 | \f | |
2d545b82 | 5692 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 5693 | |
252b5132 | 5694 | static char * |
e3bb37b5 | 5695 | output_invalid (int c) |
252b5132 | 5696 | { |
3882b010 | 5697 | if (ISPRINT (c)) |
f9f21a03 L |
5698 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
5699 | "'%c'", c); | |
252b5132 | 5700 | else |
f9f21a03 | 5701 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 5702 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
5703 | return output_invalid_buf; |
5704 | } | |
5705 | ||
af6bdddf | 5706 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
5707 | |
5708 | static const reg_entry * | |
4d1bb795 | 5709 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 5710 | { |
af6bdddf AM |
5711 | char *s = reg_string; |
5712 | char *p; | |
252b5132 RH |
5713 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
5714 | const reg_entry *r; | |
5715 | ||
5716 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
5717 | if (*s == REGISTER_PREFIX) | |
5718 | ++s; | |
5719 | ||
5720 | if (is_space_char (*s)) | |
5721 | ++s; | |
5722 | ||
5723 | p = reg_name_given; | |
af6bdddf | 5724 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
5725 | { |
5726 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
5727 | return (const reg_entry *) NULL; |
5728 | s++; | |
252b5132 RH |
5729 | } |
5730 | ||
6588847e DN |
5731 | /* For naked regs, make sure that we are not dealing with an identifier. |
5732 | This prevents confusing an identifier like `eax_var' with register | |
5733 | `eax'. */ | |
5734 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
5735 | return (const reg_entry *) NULL; | |
5736 | ||
af6bdddf | 5737 | *end_op = s; |
252b5132 RH |
5738 | |
5739 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
5740 | ||
5f47d35b | 5741 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 5742 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 5743 | { |
5f47d35b AM |
5744 | if (is_space_char (*s)) |
5745 | ++s; | |
5746 | if (*s == '(') | |
5747 | { | |
af6bdddf | 5748 | ++s; |
5f47d35b AM |
5749 | if (is_space_char (*s)) |
5750 | ++s; | |
5751 | if (*s >= '0' && *s <= '7') | |
5752 | { | |
5753 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 5754 | ++s; |
5f47d35b AM |
5755 | if (is_space_char (*s)) |
5756 | ++s; | |
5757 | if (*s == ')') | |
5758 | { | |
5759 | *end_op = s + 1; | |
5760 | return r; | |
5761 | } | |
5f47d35b | 5762 | } |
47926f60 | 5763 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
5764 | return (const reg_entry *) NULL; |
5765 | } | |
5766 | } | |
5767 | ||
1ae00879 | 5768 | if (r != NULL |
20f0a1fc | 5769 | && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 |
c4a530c5 | 5770 | && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer)) |
1ae00879 | 5771 | && flag_code != CODE_64BIT) |
20f0a1fc | 5772 | return (const reg_entry *) NULL; |
1ae00879 | 5773 | |
252b5132 RH |
5774 | return r; |
5775 | } | |
4d1bb795 JB |
5776 | |
5777 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
5778 | ||
5779 | static const reg_entry * | |
5780 | parse_register (char *reg_string, char **end_op) | |
5781 | { | |
5782 | const reg_entry *r; | |
5783 | ||
5784 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
5785 | r = parse_real_register (reg_string, end_op); | |
5786 | else | |
5787 | r = NULL; | |
5788 | if (!r) | |
5789 | { | |
5790 | char *save = input_line_pointer; | |
5791 | char c; | |
5792 | symbolS *symbolP; | |
5793 | ||
5794 | input_line_pointer = reg_string; | |
5795 | c = get_symbol_end (); | |
5796 | symbolP = symbol_find (reg_string); | |
5797 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
5798 | { | |
5799 | const expressionS *e = symbol_get_value_expression (symbolP); | |
5800 | ||
5801 | know (e->X_op == O_register); | |
4eed87de | 5802 | know (e->X_add_number >= 0 |
c3fe08fa | 5803 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
5804 | r = i386_regtab + e->X_add_number; |
5805 | *end_op = input_line_pointer; | |
5806 | } | |
5807 | *input_line_pointer = c; | |
5808 | input_line_pointer = save; | |
5809 | } | |
5810 | return r; | |
5811 | } | |
5812 | ||
5813 | int | |
5814 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
5815 | { | |
5816 | const reg_entry *r; | |
5817 | char *end = input_line_pointer; | |
5818 | ||
5819 | *end = *nextcharP; | |
5820 | r = parse_register (name, &input_line_pointer); | |
5821 | if (r && end <= input_line_pointer) | |
5822 | { | |
5823 | *nextcharP = *input_line_pointer; | |
5824 | *input_line_pointer = 0; | |
5825 | e->X_op = O_register; | |
5826 | e->X_add_number = r - i386_regtab; | |
5827 | return 1; | |
5828 | } | |
5829 | input_line_pointer = end; | |
5830 | *end = 0; | |
5831 | return 0; | |
5832 | } | |
5833 | ||
5834 | void | |
5835 | md_operand (expressionS *e) | |
5836 | { | |
5837 | if (*input_line_pointer == REGISTER_PREFIX) | |
5838 | { | |
5839 | char *end; | |
5840 | const reg_entry *r = parse_real_register (input_line_pointer, &end); | |
5841 | ||
5842 | if (r) | |
5843 | { | |
5844 | e->X_op = O_register; | |
5845 | e->X_add_number = r - i386_regtab; | |
5846 | input_line_pointer = end; | |
5847 | } | |
5848 | } | |
5849 | } | |
5850 | ||
252b5132 | 5851 | \f |
4cc782b5 | 5852 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 5853 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 5854 | #else |
12b55ccc | 5855 | const char *md_shortopts = "qn"; |
252b5132 | 5856 | #endif |
6e0b89ee | 5857 | |
3e73aa7c | 5858 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
5859 | #define OPTION_64 (OPTION_MD_BASE + 1) |
5860 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
5861 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
5862 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
b3b91714 | 5863 | |
99ad8390 NC |
5864 | struct option md_longopts[] = |
5865 | { | |
3e73aa7c | 5866 | {"32", no_argument, NULL, OPTION_32}, |
99ad8390 | 5867 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
3e73aa7c | 5868 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 5869 | #endif |
b3b91714 | 5870 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
5871 | {"march", required_argument, NULL, OPTION_MARCH}, |
5872 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
252b5132 RH |
5873 | {NULL, no_argument, NULL, 0} |
5874 | }; | |
5875 | size_t md_longopts_size = sizeof (md_longopts); | |
5876 | ||
5877 | int | |
9103f4f4 | 5878 | md_parse_option (int c, char *arg) |
252b5132 | 5879 | { |
9103f4f4 L |
5880 | unsigned int i; |
5881 | ||
252b5132 RH |
5882 | switch (c) |
5883 | { | |
12b55ccc L |
5884 | case 'n': |
5885 | optimize_align_code = 0; | |
5886 | break; | |
5887 | ||
a38cf1db AM |
5888 | case 'q': |
5889 | quiet_warnings = 1; | |
252b5132 RH |
5890 | break; |
5891 | ||
5892 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
5893 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
5894 | should be emitted or not. FIXME: Not implemented. */ | |
5895 | case 'Q': | |
252b5132 RH |
5896 | break; |
5897 | ||
5898 | /* -V: SVR4 argument to print version ID. */ | |
5899 | case 'V': | |
5900 | print_version_id (); | |
5901 | break; | |
5902 | ||
a38cf1db AM |
5903 | /* -k: Ignore for FreeBSD compatibility. */ |
5904 | case 'k': | |
252b5132 | 5905 | break; |
4cc782b5 ILT |
5906 | |
5907 | case 's': | |
5908 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 5909 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 5910 | break; |
99ad8390 NC |
5911 | #endif |
5912 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) | |
3e73aa7c JH |
5913 | case OPTION_64: |
5914 | { | |
5915 | const char **list, **l; | |
5916 | ||
3e73aa7c JH |
5917 | list = bfd_target_list (); |
5918 | for (l = list; *l != NULL; l++) | |
8620418b | 5919 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
5920 | || strcmp (*l, "coff-x86-64") == 0 |
5921 | || strcmp (*l, "pe-x86-64") == 0 | |
5922 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
5923 | { |
5924 | default_arch = "x86_64"; | |
5925 | break; | |
5926 | } | |
3e73aa7c | 5927 | if (*l == NULL) |
6e0b89ee | 5928 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
5929 | free (list); |
5930 | } | |
5931 | break; | |
5932 | #endif | |
252b5132 | 5933 | |
6e0b89ee AM |
5934 | case OPTION_32: |
5935 | default_arch = "i386"; | |
5936 | break; | |
5937 | ||
b3b91714 AM |
5938 | case OPTION_DIVIDE: |
5939 | #ifdef SVR4_COMMENT_CHARS | |
5940 | { | |
5941 | char *n, *t; | |
5942 | const char *s; | |
5943 | ||
5944 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
5945 | t = n; | |
5946 | for (s = i386_comment_chars; *s != '\0'; s++) | |
5947 | if (*s != '/') | |
5948 | *t++ = *s; | |
5949 | *t = '\0'; | |
5950 | i386_comment_chars = n; | |
5951 | } | |
5952 | #endif | |
5953 | break; | |
5954 | ||
9103f4f4 L |
5955 | case OPTION_MARCH: |
5956 | if (*arg == '.') | |
5957 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
5958 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
5959 | { | |
5960 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
5961 | { | |
ccc9c027 | 5962 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 5963 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
5964 | if (!cpu_arch_tune_set) |
5965 | { | |
5966 | cpu_arch_tune = cpu_arch_isa; | |
5967 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
5968 | } | |
9103f4f4 L |
5969 | break; |
5970 | } | |
5971 | } | |
5972 | if (i >= ARRAY_SIZE (cpu_arch)) | |
5973 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
5974 | break; | |
5975 | ||
5976 | case OPTION_MTUNE: | |
5977 | if (*arg == '.') | |
5978 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
5979 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
5980 | { | |
5981 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
5982 | { | |
ccc9c027 | 5983 | cpu_arch_tune_set = 1; |
9103f4f4 L |
5984 | cpu_arch_tune = cpu_arch [i].type; |
5985 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
5986 | break; | |
5987 | } | |
5988 | } | |
5989 | if (i >= ARRAY_SIZE (cpu_arch)) | |
5990 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
5991 | break; | |
5992 | ||
252b5132 RH |
5993 | default: |
5994 | return 0; | |
5995 | } | |
5996 | return 1; | |
5997 | } | |
5998 | ||
5999 | void | |
6000 | md_show_usage (stream) | |
6001 | FILE *stream; | |
6002 | { | |
4cc782b5 ILT |
6003 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
6004 | fprintf (stream, _("\ | |
a38cf1db AM |
6005 | -Q ignored\n\ |
6006 | -V print assembler version number\n\ | |
b3b91714 AM |
6007 | -k ignored\n")); |
6008 | #endif | |
6009 | fprintf (stream, _("\ | |
12b55ccc | 6010 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
6011 | -q quieten some warnings\n")); |
6012 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
6013 | fprintf (stream, _("\ | |
a38cf1db | 6014 | -s ignored\n")); |
b3b91714 | 6015 | #endif |
751d281c L |
6016 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
6017 | fprintf (stream, _("\ | |
6018 | --32/--64 generate 32bit/64bit code\n")); | |
6019 | #endif | |
b3b91714 AM |
6020 | #ifdef SVR4_COMMENT_CHARS |
6021 | fprintf (stream, _("\ | |
6022 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
6023 | #else |
6024 | fprintf (stream, _("\ | |
b3b91714 | 6025 | --divide ignored\n")); |
4cc782b5 | 6026 | #endif |
9103f4f4 L |
6027 | fprintf (stream, _("\ |
6028 | -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\ | |
6029 | i386, i486, pentium, pentiumpro, pentium4, nocona,\n\ | |
4eed87de | 6030 | core, core2, k6, athlon, k8, generic32, generic64\n")); |
9103f4f4 | 6031 | |
252b5132 RH |
6032 | } |
6033 | ||
99ad8390 NC |
6034 | #if defined(TE_PEP) |
6035 | const char * | |
6036 | x86_64_target_format (void) | |
6037 | { | |
6038 | if (strcmp (default_arch, "x86_64") == 0) | |
6039 | { | |
6040 | set_code_flag (CODE_64BIT); | |
6041 | return COFF_TARGET_FORMAT; | |
6042 | } | |
6043 | else if (strcmp (default_arch, "i386") == 0) | |
6044 | { | |
6045 | set_code_flag (CODE_32BIT); | |
6046 | return "coff-i386"; | |
6047 | } | |
6048 | ||
6049 | as_fatal (_("Unknown architecture")); | |
6050 | return NULL; | |
6051 | } | |
6052 | #endif | |
6053 | ||
3e73aa7c JH |
6054 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
6055 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
6056 | |
6057 | /* Pick the target format to use. */ | |
6058 | ||
47926f60 | 6059 | const char * |
e3bb37b5 | 6060 | i386_target_format (void) |
252b5132 | 6061 | { |
3e73aa7c | 6062 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
6063 | { |
6064 | set_code_flag (CODE_64BIT); | |
6065 | if (cpu_arch_isa_flags == 0) | |
d32cad65 | 6066 | cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486 |
9103f4f4 L |
6067 | |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2 |
6068 | |CpuSSE|CpuSSE2; | |
ccc9c027 | 6069 | if (cpu_arch_tune_flags == 0) |
d32cad65 | 6070 | cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486 |
ccc9c027 L |
6071 | |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2 |
6072 | |CpuSSE|CpuSSE2; | |
9103f4f4 | 6073 | } |
3e73aa7c | 6074 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
6075 | { |
6076 | set_code_flag (CODE_32BIT); | |
6077 | if (cpu_arch_isa_flags == 0) | |
d32cad65 | 6078 | cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386; |
ccc9c027 | 6079 | if (cpu_arch_tune_flags == 0) |
d32cad65 | 6080 | cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386; |
9103f4f4 | 6081 | } |
3e73aa7c JH |
6082 | else |
6083 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
6084 | switch (OUTPUT_FLAVOR) |
6085 | { | |
4c63da97 AM |
6086 | #ifdef OBJ_MAYBE_AOUT |
6087 | case bfd_target_aout_flavour: | |
47926f60 | 6088 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
6089 | #endif |
6090 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
6091 | case bfd_target_coff_flavour: |
6092 | return "coff-i386"; | |
4c63da97 | 6093 | #endif |
3e73aa7c | 6094 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 6095 | case bfd_target_elf_flavour: |
3e73aa7c | 6096 | { |
e5cb08ac | 6097 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
6098 | { |
6099 | object_64bit = 1; | |
6100 | use_rela_relocations = 1; | |
6101 | } | |
9d7cbccd | 6102 | return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; |
3e73aa7c | 6103 | } |
4c63da97 | 6104 | #endif |
252b5132 RH |
6105 | default: |
6106 | abort (); | |
6107 | return NULL; | |
6108 | } | |
6109 | } | |
6110 | ||
47926f60 | 6111 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
6112 | |
6113 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
6114 | void |
6115 | i386_elf_emit_arch_note (void) | |
a847613f | 6116 | { |
718ddfc0 | 6117 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
6118 | { |
6119 | char *p; | |
6120 | asection *seg = now_seg; | |
6121 | subsegT subseg = now_subseg; | |
6122 | Elf_Internal_Note i_note; | |
6123 | Elf_External_Note e_note; | |
6124 | asection *note_secp; | |
6125 | int len; | |
6126 | ||
6127 | /* Create the .note section. */ | |
6128 | note_secp = subseg_new (".note", 0); | |
6129 | bfd_set_section_flags (stdoutput, | |
6130 | note_secp, | |
6131 | SEC_HAS_CONTENTS | SEC_READONLY); | |
6132 | ||
6133 | /* Process the arch string. */ | |
6134 | len = strlen (cpu_arch_name); | |
6135 | ||
6136 | i_note.namesz = len + 1; | |
6137 | i_note.descsz = 0; | |
6138 | i_note.type = NT_ARCH; | |
6139 | p = frag_more (sizeof (e_note.namesz)); | |
6140 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
6141 | p = frag_more (sizeof (e_note.descsz)); | |
6142 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
6143 | p = frag_more (sizeof (e_note.type)); | |
6144 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
6145 | p = frag_more (len + 1); | |
6146 | strcpy (p, cpu_arch_name); | |
6147 | ||
6148 | frag_align (2, 0, 0); | |
6149 | ||
6150 | subseg_set (seg, subseg); | |
6151 | } | |
6152 | } | |
6153 | #endif | |
252b5132 | 6154 | \f |
252b5132 RH |
6155 | symbolS * |
6156 | md_undefined_symbol (name) | |
6157 | char *name; | |
6158 | { | |
18dc2407 ILT |
6159 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
6160 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
6161 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
6162 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
6163 | { |
6164 | if (!GOT_symbol) | |
6165 | { | |
6166 | if (symbol_find (name)) | |
6167 | as_bad (_("GOT already in symbol table")); | |
6168 | GOT_symbol = symbol_new (name, undefined_section, | |
6169 | (valueT) 0, &zero_address_frag); | |
6170 | }; | |
6171 | return GOT_symbol; | |
6172 | } | |
252b5132 RH |
6173 | return 0; |
6174 | } | |
6175 | ||
6176 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 6177 | |
252b5132 RH |
6178 | valueT |
6179 | md_section_align (segment, size) | |
ab9da554 | 6180 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
6181 | valueT size; |
6182 | { | |
4c63da97 AM |
6183 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
6184 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
6185 | { | |
6186 | /* For a.out, force the section size to be aligned. If we don't do | |
6187 | this, BFD will align it for us, but it will not write out the | |
6188 | final bytes of the section. This may be a bug in BFD, but it is | |
6189 | easier to fix it here since that is how the other a.out targets | |
6190 | work. */ | |
6191 | int align; | |
6192 | ||
6193 | align = bfd_get_section_alignment (stdoutput, segment); | |
6194 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
6195 | } | |
252b5132 RH |
6196 | #endif |
6197 | ||
6198 | return size; | |
6199 | } | |
6200 | ||
6201 | /* On the i386, PC-relative offsets are relative to the start of the | |
6202 | next instruction. That is, the address of the offset, plus its | |
6203 | size, since the offset is always the last part of the insn. */ | |
6204 | ||
6205 | long | |
e3bb37b5 | 6206 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
6207 | { |
6208 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
6209 | } | |
6210 | ||
6211 | #ifndef I386COFF | |
6212 | ||
6213 | static void | |
e3bb37b5 | 6214 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 6215 | { |
29b0f896 | 6216 | int temp; |
252b5132 | 6217 | |
8a75718c JB |
6218 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
6219 | if (IS_ELF) | |
6220 | obj_elf_section_change_hook (); | |
6221 | #endif | |
252b5132 RH |
6222 | temp = get_absolute_expression (); |
6223 | subseg_set (bss_section, (subsegT) temp); | |
6224 | demand_empty_rest_of_line (); | |
6225 | } | |
6226 | ||
6227 | #endif | |
6228 | ||
252b5132 | 6229 | void |
e3bb37b5 | 6230 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
6231 | { |
6232 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
6233 | { | |
23df1078 JH |
6234 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
6235 | { | |
4fa24527 | 6236 | if (!object_64bit) |
23df1078 JH |
6237 | abort (); |
6238 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
6239 | } | |
6240 | else | |
6241 | { | |
4fa24527 | 6242 | if (!object_64bit) |
d6ab8113 JB |
6243 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
6244 | else | |
6245 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 6246 | } |
252b5132 RH |
6247 | fixp->fx_subsy = 0; |
6248 | } | |
6249 | } | |
6250 | ||
252b5132 RH |
6251 | arelent * |
6252 | tc_gen_reloc (section, fixp) | |
ab9da554 | 6253 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
6254 | fixS *fixp; |
6255 | { | |
6256 | arelent *rel; | |
6257 | bfd_reloc_code_real_type code; | |
6258 | ||
6259 | switch (fixp->fx_r_type) | |
6260 | { | |
3e73aa7c JH |
6261 | case BFD_RELOC_X86_64_PLT32: |
6262 | case BFD_RELOC_X86_64_GOT32: | |
6263 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
6264 | case BFD_RELOC_386_PLT32: |
6265 | case BFD_RELOC_386_GOT32: | |
6266 | case BFD_RELOC_386_GOTOFF: | |
6267 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
6268 | case BFD_RELOC_386_TLS_GD: |
6269 | case BFD_RELOC_386_TLS_LDM: | |
6270 | case BFD_RELOC_386_TLS_LDO_32: | |
6271 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
6272 | case BFD_RELOC_386_TLS_IE: |
6273 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
6274 | case BFD_RELOC_386_TLS_LE_32: |
6275 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
6276 | case BFD_RELOC_386_TLS_GOTDESC: |
6277 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
6278 | case BFD_RELOC_X86_64_TLSGD: |
6279 | case BFD_RELOC_X86_64_TLSLD: | |
6280 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 6281 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
6282 | case BFD_RELOC_X86_64_GOTTPOFF: |
6283 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
6284 | case BFD_RELOC_X86_64_TPOFF64: |
6285 | case BFD_RELOC_X86_64_GOTOFF64: | |
6286 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
6287 | case BFD_RELOC_X86_64_GOT64: |
6288 | case BFD_RELOC_X86_64_GOTPCREL64: | |
6289 | case BFD_RELOC_X86_64_GOTPC64: | |
6290 | case BFD_RELOC_X86_64_GOTPLT64: | |
6291 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
6292 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
6293 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
6294 | case BFD_RELOC_RVA: |
6295 | case BFD_RELOC_VTABLE_ENTRY: | |
6296 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
6297 | #ifdef TE_PE |
6298 | case BFD_RELOC_32_SECREL: | |
6299 | #endif | |
252b5132 RH |
6300 | code = fixp->fx_r_type; |
6301 | break; | |
dbbaec26 L |
6302 | case BFD_RELOC_X86_64_32S: |
6303 | if (!fixp->fx_pcrel) | |
6304 | { | |
6305 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
6306 | code = fixp->fx_r_type; | |
6307 | break; | |
6308 | } | |
252b5132 | 6309 | default: |
93382f6d | 6310 | if (fixp->fx_pcrel) |
252b5132 | 6311 | { |
93382f6d AM |
6312 | switch (fixp->fx_size) |
6313 | { | |
6314 | default: | |
b091f402 AM |
6315 | as_bad_where (fixp->fx_file, fixp->fx_line, |
6316 | _("can not do %d byte pc-relative relocation"), | |
6317 | fixp->fx_size); | |
93382f6d AM |
6318 | code = BFD_RELOC_32_PCREL; |
6319 | break; | |
6320 | case 1: code = BFD_RELOC_8_PCREL; break; | |
6321 | case 2: code = BFD_RELOC_16_PCREL; break; | |
6322 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
6323 | #ifdef BFD64 |
6324 | case 8: code = BFD_RELOC_64_PCREL; break; | |
6325 | #endif | |
93382f6d AM |
6326 | } |
6327 | } | |
6328 | else | |
6329 | { | |
6330 | switch (fixp->fx_size) | |
6331 | { | |
6332 | default: | |
b091f402 AM |
6333 | as_bad_where (fixp->fx_file, fixp->fx_line, |
6334 | _("can not do %d byte relocation"), | |
6335 | fixp->fx_size); | |
93382f6d AM |
6336 | code = BFD_RELOC_32; |
6337 | break; | |
6338 | case 1: code = BFD_RELOC_8; break; | |
6339 | case 2: code = BFD_RELOC_16; break; | |
6340 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 6341 | #ifdef BFD64 |
3e73aa7c | 6342 | case 8: code = BFD_RELOC_64; break; |
937149dd | 6343 | #endif |
93382f6d | 6344 | } |
252b5132 RH |
6345 | } |
6346 | break; | |
6347 | } | |
252b5132 | 6348 | |
d182319b JB |
6349 | if ((code == BFD_RELOC_32 |
6350 | || code == BFD_RELOC_32_PCREL | |
6351 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
6352 | && GOT_symbol |
6353 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 6354 | { |
4fa24527 | 6355 | if (!object_64bit) |
d6ab8113 JB |
6356 | code = BFD_RELOC_386_GOTPC; |
6357 | else | |
6358 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 6359 | } |
7b81dfbb AJ |
6360 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
6361 | && GOT_symbol | |
6362 | && fixp->fx_addsy == GOT_symbol) | |
6363 | { | |
6364 | code = BFD_RELOC_X86_64_GOTPC64; | |
6365 | } | |
252b5132 RH |
6366 | |
6367 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
6368 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
6369 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
6370 | |
6371 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 6372 | |
3e73aa7c JH |
6373 | if (!use_rela_relocations) |
6374 | { | |
6375 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
6376 | vtable entry to be used in the relocation's section offset. */ | |
6377 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
6378 | rel->address = fixp->fx_offset; | |
252b5132 | 6379 | |
c6682705 | 6380 | rel->addend = 0; |
3e73aa7c JH |
6381 | } |
6382 | /* Use the rela in 64bit mode. */ | |
252b5132 | 6383 | else |
3e73aa7c | 6384 | { |
062cd5e7 AS |
6385 | if (!fixp->fx_pcrel) |
6386 | rel->addend = fixp->fx_offset; | |
6387 | else | |
6388 | switch (code) | |
6389 | { | |
6390 | case BFD_RELOC_X86_64_PLT32: | |
6391 | case BFD_RELOC_X86_64_GOT32: | |
6392 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
6393 | case BFD_RELOC_X86_64_TLSGD: |
6394 | case BFD_RELOC_X86_64_TLSLD: | |
6395 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
6396 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
6397 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
6398 | rel->addend = fixp->fx_offset - fixp->fx_size; |
6399 | break; | |
6400 | default: | |
6401 | rel->addend = (section->vma | |
6402 | - fixp->fx_size | |
6403 | + fixp->fx_addnumber | |
6404 | + md_pcrel_from (fixp)); | |
6405 | break; | |
6406 | } | |
3e73aa7c JH |
6407 | } |
6408 | ||
252b5132 RH |
6409 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
6410 | if (rel->howto == NULL) | |
6411 | { | |
6412 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 6413 | _("cannot represent relocation type %s"), |
252b5132 RH |
6414 | bfd_get_reloc_code_name (code)); |
6415 | /* Set howto to a garbage value so that we can keep going. */ | |
6416 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
6417 | assert (rel->howto != NULL); | |
6418 | } | |
6419 | ||
6420 | return rel; | |
6421 | } | |
6422 | ||
64a0c779 DN |
6423 | \f |
6424 | /* Parse operands using Intel syntax. This implements a recursive descent | |
6425 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
6426 | Programmer's Guide. | |
6427 | ||
6428 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
6429 | documentation. In particular, all the structure/union and | |
6430 | high-level macro operands are missing. | |
6431 | ||
6432 | Uppercase words are terminals, lower case words are non-terminals. | |
6433 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
6434 | bars '|' denote choices. Most grammar productions are implemented in | |
6435 | functions called 'intel_<production>'. | |
6436 | ||
6437 | Initial production is 'expr'. | |
6438 | ||
9306ca4a | 6439 | addOp + | - |
64a0c779 DN |
6440 | |
6441 | alpha [a-zA-Z] | |
6442 | ||
9306ca4a JB |
6443 | binOp & | AND | \| | OR | ^ | XOR |
6444 | ||
64a0c779 DN |
6445 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
6446 | ||
6447 | constant digits [[ radixOverride ]] | |
6448 | ||
9306ca4a | 6449 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD |
64a0c779 DN |
6450 | |
6451 | digits decdigit | |
b77a7acd AJ |
6452 | | digits decdigit |
6453 | | digits hexdigit | |
64a0c779 DN |
6454 | |
6455 | decdigit [0-9] | |
6456 | ||
9306ca4a JB |
6457 | e04 e04 addOp e05 |
6458 | | e05 | |
6459 | ||
6460 | e05 e05 binOp e06 | |
b77a7acd | 6461 | | e06 |
64a0c779 DN |
6462 | |
6463 | e06 e06 mulOp e09 | |
b77a7acd | 6464 | | e09 |
64a0c779 DN |
6465 | |
6466 | e09 OFFSET e10 | |
a724f0f4 JB |
6467 | | SHORT e10 |
6468 | | + e10 | |
6469 | | - e10 | |
9306ca4a JB |
6470 | | ~ e10 |
6471 | | NOT e10 | |
64a0c779 DN |
6472 | | e09 PTR e10 |
6473 | | e09 : e10 | |
6474 | | e10 | |
6475 | ||
6476 | e10 e10 [ expr ] | |
b77a7acd | 6477 | | e11 |
64a0c779 DN |
6478 | |
6479 | e11 ( expr ) | |
b77a7acd | 6480 | | [ expr ] |
64a0c779 DN |
6481 | | constant |
6482 | | dataType | |
6483 | | id | |
6484 | | $ | |
6485 | | register | |
6486 | ||
a724f0f4 | 6487 | => expr expr cmpOp e04 |
9306ca4a | 6488 | | e04 |
64a0c779 DN |
6489 | |
6490 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 6491 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
6492 | |
6493 | hexdigit a | b | c | d | e | f | |
b77a7acd | 6494 | | A | B | C | D | E | F |
64a0c779 DN |
6495 | |
6496 | id alpha | |
b77a7acd | 6497 | | id alpha |
64a0c779 DN |
6498 | | id decdigit |
6499 | ||
9306ca4a | 6500 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
64a0c779 DN |
6501 | |
6502 | quote " | ' | |
6503 | ||
6504 | register specialRegister | |
b77a7acd | 6505 | | gpRegister |
64a0c779 DN |
6506 | | byteRegister |
6507 | ||
6508 | segmentRegister CS | DS | ES | FS | GS | SS | |
6509 | ||
9306ca4a | 6510 | specialRegister CR0 | CR2 | CR3 | CR4 |
b77a7acd | 6511 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
6512 | | TR3 | TR4 | TR5 | TR6 | TR7 |
6513 | ||
64a0c779 DN |
6514 | We simplify the grammar in obvious places (e.g., register parsing is |
6515 | done by calling parse_register) and eliminate immediate left recursion | |
6516 | to implement a recursive-descent parser. | |
6517 | ||
a724f0f4 JB |
6518 | expr e04 expr' |
6519 | ||
6520 | expr' cmpOp e04 expr' | |
6521 | | Empty | |
9306ca4a JB |
6522 | |
6523 | e04 e05 e04' | |
6524 | ||
6525 | e04' addOp e05 e04' | |
6526 | | Empty | |
64a0c779 DN |
6527 | |
6528 | e05 e06 e05' | |
6529 | ||
9306ca4a | 6530 | e05' binOp e06 e05' |
b77a7acd | 6531 | | Empty |
64a0c779 DN |
6532 | |
6533 | e06 e09 e06' | |
6534 | ||
6535 | e06' mulOp e09 e06' | |
b77a7acd | 6536 | | Empty |
64a0c779 DN |
6537 | |
6538 | e09 OFFSET e10 e09' | |
a724f0f4 JB |
6539 | | SHORT e10' |
6540 | | + e10' | |
6541 | | - e10' | |
6542 | | ~ e10' | |
6543 | | NOT e10' | |
b77a7acd | 6544 | | e10 e09' |
64a0c779 DN |
6545 | |
6546 | e09' PTR e10 e09' | |
b77a7acd | 6547 | | : e10 e09' |
64a0c779 DN |
6548 | | Empty |
6549 | ||
6550 | e10 e11 e10' | |
6551 | ||
6552 | e10' [ expr ] e10' | |
b77a7acd | 6553 | | Empty |
64a0c779 DN |
6554 | |
6555 | e11 ( expr ) | |
b77a7acd | 6556 | | [ expr ] |
64a0c779 DN |
6557 | | BYTE |
6558 | | WORD | |
6559 | | DWORD | |
9306ca4a | 6560 | | FWORD |
64a0c779 | 6561 | | QWORD |
9306ca4a JB |
6562 | | TBYTE |
6563 | | OWORD | |
6564 | | XMMWORD | |
64a0c779 DN |
6565 | | . |
6566 | | $ | |
6567 | | register | |
6568 | | id | |
6569 | | constant */ | |
6570 | ||
6571 | /* Parsing structure for the intel syntax parser. Used to implement the | |
6572 | semantic actions for the operand grammar. */ | |
6573 | struct intel_parser_s | |
6574 | { | |
6575 | char *op_string; /* The string being parsed. */ | |
6576 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 6577 | int op_modifier; /* Operand modifier. */ |
64a0c779 | 6578 | int is_mem; /* 1 if operand is memory reference. */ |
4eed87de AM |
6579 | int in_offset; /* >=1 if parsing operand of offset. */ |
6580 | int in_bracket; /* >=1 if parsing operand in brackets. */ | |
64a0c779 DN |
6581 | const reg_entry *reg; /* Last register reference found. */ |
6582 | char *disp; /* Displacement string being built. */ | |
a724f0f4 | 6583 | char *next_operand; /* Resume point when splitting operands. */ |
64a0c779 DN |
6584 | }; |
6585 | ||
6586 | static struct intel_parser_s intel_parser; | |
6587 | ||
6588 | /* Token structure for parsing intel syntax. */ | |
6589 | struct intel_token | |
6590 | { | |
6591 | int code; /* Token code. */ | |
6592 | const reg_entry *reg; /* Register entry for register tokens. */ | |
6593 | char *str; /* String representation. */ | |
6594 | }; | |
6595 | ||
6596 | static struct intel_token cur_token, prev_token; | |
6597 | ||
50705ef4 AM |
6598 | /* Token codes for the intel parser. Since T_SHORT is already used |
6599 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
6600 | #define T_NIL -1 |
6601 | #define T_CONST 1 | |
6602 | #define T_REG 2 | |
6603 | #define T_BYTE 3 | |
6604 | #define T_WORD 4 | |
9306ca4a JB |
6605 | #define T_DWORD 5 |
6606 | #define T_FWORD 6 | |
6607 | #define T_QWORD 7 | |
6608 | #define T_TBYTE 8 | |
6609 | #define T_XMMWORD 9 | |
50705ef4 | 6610 | #undef T_SHORT |
9306ca4a JB |
6611 | #define T_SHORT 10 |
6612 | #define T_OFFSET 11 | |
6613 | #define T_PTR 12 | |
6614 | #define T_ID 13 | |
6615 | #define T_SHL 14 | |
6616 | #define T_SHR 15 | |
64a0c779 DN |
6617 | |
6618 | /* Prototypes for intel parser functions. */ | |
e3bb37b5 L |
6619 | static int intel_match_token (int); |
6620 | static void intel_putback_token (void); | |
6621 | static void intel_get_token (void); | |
6622 | static int intel_expr (void); | |
6623 | static int intel_e04 (void); | |
6624 | static int intel_e05 (void); | |
6625 | static int intel_e06 (void); | |
6626 | static int intel_e09 (void); | |
6627 | static int intel_e10 (void); | |
6628 | static int intel_e11 (void); | |
64a0c779 | 6629 | |
64a0c779 | 6630 | static int |
e3bb37b5 | 6631 | i386_intel_operand (char *operand_string, int got_a_float) |
64a0c779 DN |
6632 | { |
6633 | int ret; | |
6634 | char *p; | |
6635 | ||
a724f0f4 JB |
6636 | p = intel_parser.op_string = xstrdup (operand_string); |
6637 | intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); | |
6638 | ||
6639 | for (;;) | |
64a0c779 | 6640 | { |
a724f0f4 JB |
6641 | /* Initialize token holders. */ |
6642 | cur_token.code = prev_token.code = T_NIL; | |
6643 | cur_token.reg = prev_token.reg = NULL; | |
6644 | cur_token.str = prev_token.str = NULL; | |
6645 | ||
6646 | /* Initialize parser structure. */ | |
6647 | intel_parser.got_a_float = got_a_float; | |
6648 | intel_parser.op_modifier = 0; | |
6649 | intel_parser.is_mem = 0; | |
6650 | intel_parser.in_offset = 0; | |
6651 | intel_parser.in_bracket = 0; | |
6652 | intel_parser.reg = NULL; | |
6653 | intel_parser.disp[0] = '\0'; | |
6654 | intel_parser.next_operand = NULL; | |
6655 | ||
6656 | /* Read the first token and start the parser. */ | |
6657 | intel_get_token (); | |
6658 | ret = intel_expr (); | |
6659 | ||
6660 | if (!ret) | |
6661 | break; | |
6662 | ||
9306ca4a JB |
6663 | if (cur_token.code != T_NIL) |
6664 | { | |
6665 | as_bad (_("invalid operand for '%s' ('%s' unexpected)"), | |
6666 | current_templates->start->name, cur_token.str); | |
6667 | ret = 0; | |
6668 | } | |
64a0c779 DN |
6669 | /* If we found a memory reference, hand it over to i386_displacement |
6670 | to fill in the rest of the operand fields. */ | |
9306ca4a | 6671 | else if (intel_parser.is_mem) |
64a0c779 DN |
6672 | { |
6673 | if ((i.mem_operands == 1 | |
6674 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
6675 | || i.mem_operands == 2) | |
6676 | { | |
6677 | as_bad (_("too many memory references for '%s'"), | |
6678 | current_templates->start->name); | |
6679 | ret = 0; | |
6680 | } | |
6681 | else | |
6682 | { | |
6683 | char *s = intel_parser.disp; | |
6684 | i.mem_operands++; | |
6685 | ||
a724f0f4 JB |
6686 | if (!quiet_warnings && intel_parser.is_mem < 0) |
6687 | /* See the comments in intel_bracket_expr. */ | |
6688 | as_warn (_("Treating `%s' as memory reference"), operand_string); | |
6689 | ||
64a0c779 DN |
6690 | /* Add the displacement expression. */ |
6691 | if (*s != '\0') | |
a4622f40 AM |
6692 | ret = i386_displacement (s, s + strlen (s)); |
6693 | if (ret) | |
a724f0f4 JB |
6694 | { |
6695 | /* Swap base and index in 16-bit memory operands like | |
6696 | [si+bx]. Since i386_index_check is also used in AT&T | |
6697 | mode we have to do that here. */ | |
6698 | if (i.base_reg | |
6699 | && i.index_reg | |
6700 | && (i.base_reg->reg_type & Reg16) | |
6701 | && (i.index_reg->reg_type & Reg16) | |
6702 | && i.base_reg->reg_num >= 6 | |
6703 | && i.index_reg->reg_num < 6) | |
6704 | { | |
6705 | const reg_entry *base = i.index_reg; | |
6706 | ||
6707 | i.index_reg = i.base_reg; | |
6708 | i.base_reg = base; | |
6709 | } | |
6710 | ret = i386_index_check (operand_string); | |
6711 | } | |
64a0c779 DN |
6712 | } |
6713 | } | |
6714 | ||
6715 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
a724f0f4 | 6716 | else if ((intel_parser.op_modifier & (1 << T_OFFSET)) |
64a0c779 DN |
6717 | || intel_parser.reg == NULL) |
6718 | ret = i386_immediate (intel_parser.disp); | |
a724f0f4 JB |
6719 | |
6720 | if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) | |
4eed87de | 6721 | ret = 0; |
a724f0f4 JB |
6722 | if (!ret || !intel_parser.next_operand) |
6723 | break; | |
6724 | intel_parser.op_string = intel_parser.next_operand; | |
6725 | this_operand = i.operands++; | |
64a0c779 DN |
6726 | } |
6727 | ||
6728 | free (p); | |
6729 | free (intel_parser.disp); | |
6730 | ||
6731 | return ret; | |
6732 | } | |
6733 | ||
a724f0f4 JB |
6734 | #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) |
6735 | ||
6736 | /* expr e04 expr' | |
6737 | ||
6738 | expr' cmpOp e04 expr' | |
6739 | | Empty */ | |
64a0c779 | 6740 | static int |
e3bb37b5 | 6741 | intel_expr (void) |
64a0c779 | 6742 | { |
a724f0f4 JB |
6743 | /* XXX Implement the comparison operators. */ |
6744 | return intel_e04 (); | |
9306ca4a JB |
6745 | } |
6746 | ||
a724f0f4 | 6747 | /* e04 e05 e04' |
9306ca4a | 6748 | |
a724f0f4 | 6749 | e04' addOp e05 e04' |
9306ca4a JB |
6750 | | Empty */ |
6751 | static int | |
e3bb37b5 | 6752 | intel_e04 (void) |
9306ca4a | 6753 | { |
a724f0f4 | 6754 | int nregs = -1; |
9306ca4a | 6755 | |
a724f0f4 | 6756 | for (;;) |
9306ca4a | 6757 | { |
a724f0f4 JB |
6758 | if (!intel_e05()) |
6759 | return 0; | |
9306ca4a | 6760 | |
a724f0f4 JB |
6761 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
6762 | i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ | |
9306ca4a | 6763 | |
a724f0f4 JB |
6764 | if (cur_token.code == '+') |
6765 | nregs = -1; | |
6766 | else if (cur_token.code == '-') | |
6767 | nregs = NUM_ADDRESS_REGS; | |
6768 | else | |
6769 | return 1; | |
64a0c779 | 6770 | |
a724f0f4 JB |
6771 | strcat (intel_parser.disp, cur_token.str); |
6772 | intel_match_token (cur_token.code); | |
6773 | } | |
64a0c779 DN |
6774 | } |
6775 | ||
64a0c779 DN |
6776 | /* e05 e06 e05' |
6777 | ||
9306ca4a | 6778 | e05' binOp e06 e05' |
64a0c779 DN |
6779 | | Empty */ |
6780 | static int | |
e3bb37b5 | 6781 | intel_e05 (void) |
64a0c779 | 6782 | { |
a724f0f4 | 6783 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 6784 | |
a724f0f4 | 6785 | for (;;) |
64a0c779 | 6786 | { |
a724f0f4 JB |
6787 | if (!intel_e06()) |
6788 | return 0; | |
6789 | ||
4eed87de AM |
6790 | if (cur_token.code == '&' |
6791 | || cur_token.code == '|' | |
6792 | || cur_token.code == '^') | |
a724f0f4 JB |
6793 | { |
6794 | char str[2]; | |
6795 | ||
6796 | str[0] = cur_token.code; | |
6797 | str[1] = 0; | |
6798 | strcat (intel_parser.disp, str); | |
6799 | } | |
6800 | else | |
6801 | break; | |
9306ca4a | 6802 | |
64a0c779 DN |
6803 | intel_match_token (cur_token.code); |
6804 | ||
a724f0f4 JB |
6805 | if (nregs < 0) |
6806 | nregs = ~nregs; | |
64a0c779 | 6807 | } |
a724f0f4 JB |
6808 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
6809 | i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ | |
6810 | return 1; | |
4a1805b1 | 6811 | } |
64a0c779 DN |
6812 | |
6813 | /* e06 e09 e06' | |
6814 | ||
6815 | e06' mulOp e09 e06' | |
b77a7acd | 6816 | | Empty */ |
64a0c779 | 6817 | static int |
e3bb37b5 | 6818 | intel_e06 (void) |
64a0c779 | 6819 | { |
a724f0f4 | 6820 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 6821 | |
a724f0f4 | 6822 | for (;;) |
64a0c779 | 6823 | { |
a724f0f4 JB |
6824 | if (!intel_e09()) |
6825 | return 0; | |
9306ca4a | 6826 | |
4eed87de AM |
6827 | if (cur_token.code == '*' |
6828 | || cur_token.code == '/' | |
6829 | || cur_token.code == '%') | |
a724f0f4 JB |
6830 | { |
6831 | char str[2]; | |
9306ca4a | 6832 | |
a724f0f4 JB |
6833 | str[0] = cur_token.code; |
6834 | str[1] = 0; | |
6835 | strcat (intel_parser.disp, str); | |
6836 | } | |
6837 | else if (cur_token.code == T_SHL) | |
6838 | strcat (intel_parser.disp, "<<"); | |
6839 | else if (cur_token.code == T_SHR) | |
6840 | strcat (intel_parser.disp, ">>"); | |
6841 | else | |
6842 | break; | |
9306ca4a | 6843 | |
64e74474 | 6844 | intel_match_token (cur_token.code); |
64a0c779 | 6845 | |
a724f0f4 JB |
6846 | if (nregs < 0) |
6847 | nregs = ~nregs; | |
64a0c779 | 6848 | } |
a724f0f4 JB |
6849 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
6850 | i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ | |
6851 | return 1; | |
64a0c779 DN |
6852 | } |
6853 | ||
a724f0f4 JB |
6854 | /* e09 OFFSET e09 |
6855 | | SHORT e09 | |
6856 | | + e09 | |
6857 | | - e09 | |
6858 | | ~ e09 | |
6859 | | NOT e09 | |
9306ca4a JB |
6860 | | e10 e09' |
6861 | ||
64a0c779 | 6862 | e09' PTR e10 e09' |
b77a7acd | 6863 | | : e10 e09' |
64a0c779 DN |
6864 | | Empty */ |
6865 | static int | |
e3bb37b5 | 6866 | intel_e09 (void) |
64a0c779 | 6867 | { |
a724f0f4 JB |
6868 | int nregs = ~NUM_ADDRESS_REGS; |
6869 | int in_offset = 0; | |
6870 | ||
6871 | for (;;) | |
64a0c779 | 6872 | { |
a724f0f4 JB |
6873 | /* Don't consume constants here. */ |
6874 | if (cur_token.code == '+' || cur_token.code == '-') | |
6875 | { | |
6876 | /* Need to look one token ahead - if the next token | |
6877 | is a constant, the current token is its sign. */ | |
6878 | int next_code; | |
6879 | ||
6880 | intel_match_token (cur_token.code); | |
6881 | next_code = cur_token.code; | |
6882 | intel_putback_token (); | |
6883 | if (next_code == T_CONST) | |
6884 | break; | |
6885 | } | |
6886 | ||
6887 | /* e09 OFFSET e09 */ | |
6888 | if (cur_token.code == T_OFFSET) | |
6889 | { | |
6890 | if (!in_offset++) | |
6891 | ++intel_parser.in_offset; | |
6892 | } | |
6893 | ||
6894 | /* e09 SHORT e09 */ | |
6895 | else if (cur_token.code == T_SHORT) | |
6896 | intel_parser.op_modifier |= 1 << T_SHORT; | |
6897 | ||
6898 | /* e09 + e09 */ | |
6899 | else if (cur_token.code == '+') | |
6900 | strcat (intel_parser.disp, "+"); | |
6901 | ||
6902 | /* e09 - e09 | |
6903 | | ~ e09 | |
6904 | | NOT e09 */ | |
6905 | else if (cur_token.code == '-' || cur_token.code == '~') | |
6906 | { | |
6907 | char str[2]; | |
64a0c779 | 6908 | |
a724f0f4 JB |
6909 | if (nregs < 0) |
6910 | nregs = ~nregs; | |
6911 | str[0] = cur_token.code; | |
6912 | str[1] = 0; | |
6913 | strcat (intel_parser.disp, str); | |
6914 | } | |
6915 | ||
6916 | /* e09 e10 e09' */ | |
6917 | else | |
6918 | break; | |
6919 | ||
6920 | intel_match_token (cur_token.code); | |
64a0c779 DN |
6921 | } |
6922 | ||
a724f0f4 | 6923 | for (;;) |
9306ca4a | 6924 | { |
a724f0f4 JB |
6925 | if (!intel_e10 ()) |
6926 | return 0; | |
9306ca4a | 6927 | |
a724f0f4 JB |
6928 | /* e09' PTR e10 e09' */ |
6929 | if (cur_token.code == T_PTR) | |
6930 | { | |
6931 | char suffix; | |
9306ca4a | 6932 | |
a724f0f4 JB |
6933 | if (prev_token.code == T_BYTE) |
6934 | suffix = BYTE_MNEM_SUFFIX; | |
9306ca4a | 6935 | |
a724f0f4 JB |
6936 | else if (prev_token.code == T_WORD) |
6937 | { | |
6938 | if (current_templates->start->name[0] == 'l' | |
6939 | && current_templates->start->name[2] == 's' | |
6940 | && current_templates->start->name[3] == 0) | |
6941 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
6942 | else if (intel_parser.got_a_float == 2) /* "fi..." */ | |
6943 | suffix = SHORT_MNEM_SUFFIX; | |
6944 | else | |
6945 | suffix = WORD_MNEM_SUFFIX; | |
6946 | } | |
64a0c779 | 6947 | |
a724f0f4 JB |
6948 | else if (prev_token.code == T_DWORD) |
6949 | { | |
6950 | if (current_templates->start->name[0] == 'l' | |
6951 | && current_templates->start->name[2] == 's' | |
6952 | && current_templates->start->name[3] == 0) | |
6953 | suffix = WORD_MNEM_SUFFIX; | |
6954 | else if (flag_code == CODE_16BIT | |
6955 | && (current_templates->start->opcode_modifier | |
435acd52 | 6956 | & (Jump | JumpDword))) |
a724f0f4 JB |
6957 | suffix = LONG_DOUBLE_MNEM_SUFFIX; |
6958 | else if (intel_parser.got_a_float == 1) /* "f..." */ | |
6959 | suffix = SHORT_MNEM_SUFFIX; | |
6960 | else | |
6961 | suffix = LONG_MNEM_SUFFIX; | |
6962 | } | |
9306ca4a | 6963 | |
a724f0f4 JB |
6964 | else if (prev_token.code == T_FWORD) |
6965 | { | |
6966 | if (current_templates->start->name[0] == 'l' | |
6967 | && current_templates->start->name[2] == 's' | |
6968 | && current_templates->start->name[3] == 0) | |
6969 | suffix = LONG_MNEM_SUFFIX; | |
6970 | else if (!intel_parser.got_a_float) | |
6971 | { | |
6972 | if (flag_code == CODE_16BIT) | |
6973 | add_prefix (DATA_PREFIX_OPCODE); | |
6974 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
6975 | } | |
6976 | else | |
6977 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
6978 | } | |
64a0c779 | 6979 | |
a724f0f4 JB |
6980 | else if (prev_token.code == T_QWORD) |
6981 | { | |
6982 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
6983 | suffix = LONG_MNEM_SUFFIX; | |
6984 | else | |
6985 | suffix = QWORD_MNEM_SUFFIX; | |
6986 | } | |
64a0c779 | 6987 | |
a724f0f4 JB |
6988 | else if (prev_token.code == T_TBYTE) |
6989 | { | |
6990 | if (intel_parser.got_a_float == 1) | |
6991 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
6992 | else | |
6993 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
6994 | } | |
9306ca4a | 6995 | |
a724f0f4 | 6996 | else if (prev_token.code == T_XMMWORD) |
9306ca4a | 6997 | { |
a724f0f4 JB |
6998 | /* XXX ignored for now, but accepted since gcc uses it */ |
6999 | suffix = 0; | |
9306ca4a | 7000 | } |
64a0c779 | 7001 | |
f16b83df | 7002 | else |
a724f0f4 JB |
7003 | { |
7004 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); | |
7005 | return 0; | |
7006 | } | |
7007 | ||
435acd52 JB |
7008 | /* Operands for jump/call using 'ptr' notation denote absolute |
7009 | addresses. */ | |
7010 | if (current_templates->start->opcode_modifier & (Jump | JumpDword)) | |
7011 | i.types[this_operand] |= JumpAbsolute; | |
7012 | ||
a724f0f4 JB |
7013 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
7014 | ; | |
7015 | else if (!i.suffix) | |
7016 | i.suffix = suffix; | |
7017 | else if (i.suffix != suffix) | |
7018 | { | |
7019 | as_bad (_("Conflicting operand modifiers")); | |
7020 | return 0; | |
7021 | } | |
64a0c779 | 7022 | |
9306ca4a JB |
7023 | } |
7024 | ||
a724f0f4 JB |
7025 | /* e09' : e10 e09' */ |
7026 | else if (cur_token.code == ':') | |
9306ca4a | 7027 | { |
a724f0f4 JB |
7028 | if (prev_token.code != T_REG) |
7029 | { | |
7030 | /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a | |
7031 | segment/group identifier (which we don't have), using comma | |
7032 | as the operand separator there is even less consistent, since | |
7033 | there all branches only have a single operand. */ | |
7034 | if (this_operand != 0 | |
7035 | || intel_parser.in_offset | |
7036 | || intel_parser.in_bracket | |
7037 | || (!(current_templates->start->opcode_modifier | |
7038 | & (Jump|JumpDword|JumpInterSegment)) | |
7039 | && !(current_templates->start->operand_types[0] | |
7040 | & JumpAbsolute))) | |
7041 | return intel_match_token (T_NIL); | |
7042 | /* Remember the start of the 2nd operand and terminate 1st | |
7043 | operand here. | |
7044 | XXX This isn't right, yet (when SSSS:OOOO is right operand of | |
7045 | another expression), but it gets at least the simplest case | |
7046 | (a plain number or symbol on the left side) right. */ | |
7047 | intel_parser.next_operand = intel_parser.op_string; | |
7048 | *--intel_parser.op_string = '\0'; | |
7049 | return intel_match_token (':'); | |
7050 | } | |
9306ca4a | 7051 | } |
64a0c779 | 7052 | |
a724f0f4 | 7053 | /* e09' Empty */ |
64a0c779 | 7054 | else |
a724f0f4 | 7055 | break; |
64a0c779 | 7056 | |
a724f0f4 JB |
7057 | intel_match_token (cur_token.code); |
7058 | ||
7059 | } | |
7060 | ||
7061 | if (in_offset) | |
7062 | { | |
7063 | --intel_parser.in_offset; | |
7064 | if (nregs < 0) | |
7065 | nregs = ~nregs; | |
7066 | if (NUM_ADDRESS_REGS > nregs) | |
9306ca4a | 7067 | { |
a724f0f4 | 7068 | as_bad (_("Invalid operand to `OFFSET'")); |
9306ca4a JB |
7069 | return 0; |
7070 | } | |
a724f0f4 JB |
7071 | intel_parser.op_modifier |= 1 << T_OFFSET; |
7072 | } | |
9306ca4a | 7073 | |
a724f0f4 JB |
7074 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
7075 | i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ | |
7076 | return 1; | |
7077 | } | |
64a0c779 | 7078 | |
a724f0f4 | 7079 | static int |
e3bb37b5 | 7080 | intel_bracket_expr (void) |
a724f0f4 JB |
7081 | { |
7082 | int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); | |
7083 | const char *start = intel_parser.op_string; | |
7084 | int len; | |
7085 | ||
7086 | if (i.op[this_operand].regs) | |
7087 | return intel_match_token (T_NIL); | |
7088 | ||
7089 | intel_match_token ('['); | |
7090 | ||
7091 | /* Mark as a memory operand only if it's not already known to be an | |
7092 | offset expression. If it's an offset expression, we need to keep | |
7093 | the brace in. */ | |
7094 | if (!intel_parser.in_offset) | |
7095 | { | |
7096 | ++intel_parser.in_bracket; | |
435acd52 JB |
7097 | |
7098 | /* Operands for jump/call inside brackets denote absolute addresses. */ | |
7099 | if (current_templates->start->opcode_modifier & (Jump | JumpDword)) | |
7100 | i.types[this_operand] |= JumpAbsolute; | |
7101 | ||
a724f0f4 JB |
7102 | /* Unfortunately gas always diverged from MASM in a respect that can't |
7103 | be easily fixed without risking to break code sequences likely to be | |
7104 | encountered (the testsuite even check for this): MASM doesn't consider | |
7105 | an expression inside brackets unconditionally as a memory reference. | |
7106 | When that is e.g. a constant, an offset expression, or the sum of the | |
7107 | two, this is still taken as a constant load. gas, however, always | |
7108 | treated these as memory references. As a compromise, we'll try to make | |
7109 | offset expressions inside brackets work the MASM way (since that's | |
7110 | less likely to be found in real world code), but make constants alone | |
7111 | continue to work the traditional gas way. In either case, issue a | |
7112 | warning. */ | |
7113 | intel_parser.op_modifier &= ~was_offset; | |
64a0c779 | 7114 | } |
a724f0f4 | 7115 | else |
64e74474 | 7116 | strcat (intel_parser.disp, "["); |
a724f0f4 JB |
7117 | |
7118 | /* Add a '+' to the displacement string if necessary. */ | |
7119 | if (*intel_parser.disp != '\0' | |
7120 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
7121 | strcat (intel_parser.disp, "+"); | |
64a0c779 | 7122 | |
a724f0f4 JB |
7123 | if (intel_expr () |
7124 | && (len = intel_parser.op_string - start - 1, | |
7125 | intel_match_token (']'))) | |
64a0c779 | 7126 | { |
a724f0f4 JB |
7127 | /* Preserve brackets when the operand is an offset expression. */ |
7128 | if (intel_parser.in_offset) | |
7129 | strcat (intel_parser.disp, "]"); | |
7130 | else | |
7131 | { | |
7132 | --intel_parser.in_bracket; | |
7133 | if (i.base_reg || i.index_reg) | |
7134 | intel_parser.is_mem = 1; | |
7135 | if (!intel_parser.is_mem) | |
7136 | { | |
7137 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
7138 | /* Defer the warning until all of the operand was parsed. */ | |
7139 | intel_parser.is_mem = -1; | |
7140 | else if (!quiet_warnings) | |
4eed87de AM |
7141 | as_warn (_("`[%.*s]' taken to mean just `%.*s'"), |
7142 | len, start, len, start); | |
a724f0f4 JB |
7143 | } |
7144 | } | |
7145 | intel_parser.op_modifier |= was_offset; | |
64a0c779 | 7146 | |
a724f0f4 | 7147 | return 1; |
64a0c779 | 7148 | } |
a724f0f4 | 7149 | return 0; |
64a0c779 DN |
7150 | } |
7151 | ||
7152 | /* e10 e11 e10' | |
7153 | ||
7154 | e10' [ expr ] e10' | |
b77a7acd | 7155 | | Empty */ |
64a0c779 | 7156 | static int |
e3bb37b5 | 7157 | intel_e10 (void) |
64a0c779 | 7158 | { |
a724f0f4 JB |
7159 | if (!intel_e11 ()) |
7160 | return 0; | |
64a0c779 | 7161 | |
a724f0f4 | 7162 | while (cur_token.code == '[') |
64a0c779 | 7163 | { |
a724f0f4 | 7164 | if (!intel_bracket_expr ()) |
21d6c4af | 7165 | return 0; |
64a0c779 DN |
7166 | } |
7167 | ||
a724f0f4 | 7168 | return 1; |
64a0c779 DN |
7169 | } |
7170 | ||
64a0c779 | 7171 | /* e11 ( expr ) |
b77a7acd | 7172 | | [ expr ] |
64a0c779 DN |
7173 | | BYTE |
7174 | | WORD | |
7175 | | DWORD | |
9306ca4a | 7176 | | FWORD |
64a0c779 | 7177 | | QWORD |
9306ca4a JB |
7178 | | TBYTE |
7179 | | OWORD | |
7180 | | XMMWORD | |
4a1805b1 | 7181 | | $ |
64a0c779 DN |
7182 | | . |
7183 | | register | |
7184 | | id | |
7185 | | constant */ | |
7186 | static int | |
e3bb37b5 | 7187 | intel_e11 (void) |
64a0c779 | 7188 | { |
a724f0f4 | 7189 | switch (cur_token.code) |
64a0c779 | 7190 | { |
a724f0f4 JB |
7191 | /* e11 ( expr ) */ |
7192 | case '(': | |
64a0c779 DN |
7193 | intel_match_token ('('); |
7194 | strcat (intel_parser.disp, "("); | |
7195 | ||
7196 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
7197 | { |
7198 | strcat (intel_parser.disp, ")"); | |
7199 | return 1; | |
7200 | } | |
a724f0f4 | 7201 | return 0; |
4a1805b1 | 7202 | |
a724f0f4 JB |
7203 | /* e11 [ expr ] */ |
7204 | case '[': | |
a724f0f4 | 7205 | return intel_bracket_expr (); |
64a0c779 | 7206 | |
a724f0f4 JB |
7207 | /* e11 $ |
7208 | | . */ | |
7209 | case '.': | |
64a0c779 DN |
7210 | strcat (intel_parser.disp, cur_token.str); |
7211 | intel_match_token (cur_token.code); | |
21d6c4af DN |
7212 | |
7213 | /* Mark as a memory operand only if it's not already known to be an | |
7214 | offset expression. */ | |
a724f0f4 | 7215 | if (!intel_parser.in_offset) |
21d6c4af | 7216 | intel_parser.is_mem = 1; |
64a0c779 DN |
7217 | |
7218 | return 1; | |
64a0c779 | 7219 | |
a724f0f4 JB |
7220 | /* e11 register */ |
7221 | case T_REG: | |
7222 | { | |
7223 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
64a0c779 | 7224 | |
a724f0f4 | 7225 | intel_match_token (T_REG); |
64a0c779 | 7226 | |
a724f0f4 JB |
7227 | /* Check for segment change. */ |
7228 | if (cur_token.code == ':') | |
7229 | { | |
7230 | if (!(reg->reg_type & (SReg2 | SReg3))) | |
7231 | { | |
4eed87de AM |
7232 | as_bad (_("`%s' is not a valid segment register"), |
7233 | reg->reg_name); | |
a724f0f4 JB |
7234 | return 0; |
7235 | } | |
7236 | else if (i.seg[i.mem_operands]) | |
7237 | as_warn (_("Extra segment override ignored")); | |
7238 | else | |
7239 | { | |
7240 | if (!intel_parser.in_offset) | |
7241 | intel_parser.is_mem = 1; | |
7242 | switch (reg->reg_num) | |
7243 | { | |
7244 | case 0: | |
7245 | i.seg[i.mem_operands] = &es; | |
7246 | break; | |
7247 | case 1: | |
7248 | i.seg[i.mem_operands] = &cs; | |
7249 | break; | |
7250 | case 2: | |
7251 | i.seg[i.mem_operands] = &ss; | |
7252 | break; | |
7253 | case 3: | |
7254 | i.seg[i.mem_operands] = &ds; | |
7255 | break; | |
7256 | case 4: | |
7257 | i.seg[i.mem_operands] = &fs; | |
7258 | break; | |
7259 | case 5: | |
7260 | i.seg[i.mem_operands] = &gs; | |
7261 | break; | |
7262 | } | |
7263 | } | |
7264 | } | |
64a0c779 | 7265 | |
a724f0f4 JB |
7266 | /* Not a segment register. Check for register scaling. */ |
7267 | else if (cur_token.code == '*') | |
7268 | { | |
7269 | if (!intel_parser.in_bracket) | |
7270 | { | |
7271 | as_bad (_("Register scaling only allowed in memory operands")); | |
7272 | return 0; | |
7273 | } | |
64a0c779 | 7274 | |
a724f0f4 JB |
7275 | if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */ |
7276 | reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ | |
7277 | else if (i.index_reg) | |
7278 | reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ | |
64a0c779 | 7279 | |
a724f0f4 JB |
7280 | /* What follows must be a valid scale. */ |
7281 | intel_match_token ('*'); | |
7282 | i.index_reg = reg; | |
7283 | i.types[this_operand] |= BaseIndex; | |
64a0c779 | 7284 | |
a724f0f4 JB |
7285 | /* Set the scale after setting the register (otherwise, |
7286 | i386_scale will complain) */ | |
7287 | if (cur_token.code == '+' || cur_token.code == '-') | |
7288 | { | |
7289 | char *str, sign = cur_token.code; | |
7290 | intel_match_token (cur_token.code); | |
7291 | if (cur_token.code != T_CONST) | |
7292 | { | |
7293 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
7294 | cur_token.str); | |
7295 | return 0; | |
7296 | } | |
7297 | str = (char *) xmalloc (strlen (cur_token.str) + 2); | |
7298 | strcpy (str + 1, cur_token.str); | |
7299 | *str = sign; | |
7300 | if (!i386_scale (str)) | |
7301 | return 0; | |
7302 | free (str); | |
7303 | } | |
7304 | else if (!i386_scale (cur_token.str)) | |
64a0c779 | 7305 | return 0; |
a724f0f4 JB |
7306 | intel_match_token (cur_token.code); |
7307 | } | |
64a0c779 | 7308 | |
a724f0f4 JB |
7309 | /* No scaling. If this is a memory operand, the register is either a |
7310 | base register (first occurrence) or an index register (second | |
7311 | occurrence). */ | |
7b0441f6 | 7312 | else if (intel_parser.in_bracket) |
a724f0f4 | 7313 | { |
64a0c779 | 7314 | |
a724f0f4 JB |
7315 | if (!i.base_reg) |
7316 | i.base_reg = reg; | |
7317 | else if (!i.index_reg) | |
7318 | i.index_reg = reg; | |
7319 | else | |
7320 | { | |
7321 | as_bad (_("Too many register references in memory operand")); | |
7322 | return 0; | |
7323 | } | |
64a0c779 | 7324 | |
a724f0f4 JB |
7325 | i.types[this_operand] |= BaseIndex; |
7326 | } | |
4a1805b1 | 7327 | |
4d1bb795 JB |
7328 | /* It's neither base nor index. */ |
7329 | else if (!intel_parser.in_offset && !intel_parser.is_mem) | |
a724f0f4 JB |
7330 | { |
7331 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
7332 | i.op[this_operand].regs = reg; | |
7333 | i.reg_operands++; | |
7334 | } | |
7335 | else | |
7336 | { | |
7337 | as_bad (_("Invalid use of register")); | |
7338 | return 0; | |
7339 | } | |
64a0c779 | 7340 | |
a724f0f4 JB |
7341 | /* Since registers are not part of the displacement string (except |
7342 | when we're parsing offset operands), we may need to remove any | |
7343 | preceding '+' from the displacement string. */ | |
7344 | if (*intel_parser.disp != '\0' | |
7345 | && !intel_parser.in_offset) | |
7346 | { | |
7347 | char *s = intel_parser.disp; | |
7348 | s += strlen (s) - 1; | |
7349 | if (*s == '+') | |
7350 | *s = '\0'; | |
7351 | } | |
4a1805b1 | 7352 | |
a724f0f4 JB |
7353 | return 1; |
7354 | } | |
7355 | ||
7356 | /* e11 BYTE | |
7357 | | WORD | |
7358 | | DWORD | |
7359 | | FWORD | |
7360 | | QWORD | |
7361 | | TBYTE | |
7362 | | OWORD | |
7363 | | XMMWORD */ | |
7364 | case T_BYTE: | |
7365 | case T_WORD: | |
7366 | case T_DWORD: | |
7367 | case T_FWORD: | |
7368 | case T_QWORD: | |
7369 | case T_TBYTE: | |
7370 | case T_XMMWORD: | |
7371 | intel_match_token (cur_token.code); | |
64a0c779 | 7372 | |
a724f0f4 JB |
7373 | if (cur_token.code == T_PTR) |
7374 | return 1; | |
7375 | ||
7376 | /* It must have been an identifier. */ | |
7377 | intel_putback_token (); | |
7378 | cur_token.code = T_ID; | |
7379 | /* FALLTHRU */ | |
7380 | ||
7381 | /* e11 id | |
7382 | | constant */ | |
7383 | case T_ID: | |
7384 | if (!intel_parser.in_offset && intel_parser.is_mem <= 0) | |
9306ca4a JB |
7385 | { |
7386 | symbolS *symbolP; | |
7387 | ||
a724f0f4 JB |
7388 | /* The identifier represents a memory reference only if it's not |
7389 | preceded by an offset modifier and if it's not an equate. */ | |
9306ca4a JB |
7390 | symbolP = symbol_find(cur_token.str); |
7391 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) | |
7392 | intel_parser.is_mem = 1; | |
7393 | } | |
a724f0f4 | 7394 | /* FALLTHRU */ |
64a0c779 | 7395 | |
a724f0f4 JB |
7396 | case T_CONST: |
7397 | case '-': | |
7398 | case '+': | |
7399 | { | |
7400 | char *save_str, sign = 0; | |
64a0c779 | 7401 | |
a724f0f4 JB |
7402 | /* Allow constants that start with `+' or `-'. */ |
7403 | if (cur_token.code == '-' || cur_token.code == '+') | |
7404 | { | |
7405 | sign = cur_token.code; | |
7406 | intel_match_token (cur_token.code); | |
7407 | if (cur_token.code != T_CONST) | |
7408 | { | |
7409 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
7410 | cur_token.str); | |
7411 | return 0; | |
7412 | } | |
7413 | } | |
64a0c779 | 7414 | |
a724f0f4 JB |
7415 | save_str = (char *) xmalloc (strlen (cur_token.str) + 2); |
7416 | strcpy (save_str + !!sign, cur_token.str); | |
7417 | if (sign) | |
7418 | *save_str = sign; | |
64a0c779 | 7419 | |
a724f0f4 JB |
7420 | /* Get the next token to check for register scaling. */ |
7421 | intel_match_token (cur_token.code); | |
64a0c779 | 7422 | |
4eed87de AM |
7423 | /* Check if this constant is a scaling factor for an |
7424 | index register. */ | |
a724f0f4 JB |
7425 | if (cur_token.code == '*') |
7426 | { | |
7427 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
7428 | { | |
7429 | const reg_entry *reg = cur_token.reg; | |
7430 | ||
7431 | if (!intel_parser.in_bracket) | |
7432 | { | |
4eed87de AM |
7433 | as_bad (_("Register scaling only allowed " |
7434 | "in memory operands")); | |
a724f0f4 JB |
7435 | return 0; |
7436 | } | |
7437 | ||
4eed87de AM |
7438 | /* Disallow things like [1*si]. |
7439 | sp and esp are invalid as index. */ | |
7440 | if (reg->reg_type & Reg16) | |
7441 | reg = i386_regtab + REGNAM_AX + 4; | |
a724f0f4 | 7442 | else if (i.index_reg) |
4eed87de | 7443 | reg = i386_regtab + REGNAM_EAX + 4; |
a724f0f4 JB |
7444 | |
7445 | /* The constant is followed by `* reg', so it must be | |
7446 | a valid scale. */ | |
7447 | i.index_reg = reg; | |
7448 | i.types[this_operand] |= BaseIndex; | |
7449 | ||
7450 | /* Set the scale after setting the register (otherwise, | |
7451 | i386_scale will complain) */ | |
7452 | if (!i386_scale (save_str)) | |
64a0c779 | 7453 | return 0; |
a724f0f4 JB |
7454 | intel_match_token (T_REG); |
7455 | ||
7456 | /* Since registers are not part of the displacement | |
7457 | string, we may need to remove any preceding '+' from | |
7458 | the displacement string. */ | |
7459 | if (*intel_parser.disp != '\0') | |
7460 | { | |
7461 | char *s = intel_parser.disp; | |
7462 | s += strlen (s) - 1; | |
7463 | if (*s == '+') | |
7464 | *s = '\0'; | |
7465 | } | |
7466 | ||
7467 | free (save_str); | |
7468 | ||
7469 | return 1; | |
7470 | } | |
64a0c779 | 7471 | |
a724f0f4 JB |
7472 | /* The constant was not used for register scaling. Since we have |
7473 | already consumed the token following `*' we now need to put it | |
7474 | back in the stream. */ | |
64a0c779 | 7475 | intel_putback_token (); |
a724f0f4 | 7476 | } |
64a0c779 | 7477 | |
a724f0f4 JB |
7478 | /* Add the constant to the displacement string. */ |
7479 | strcat (intel_parser.disp, save_str); | |
7480 | free (save_str); | |
64a0c779 | 7481 | |
a724f0f4 JB |
7482 | return 1; |
7483 | } | |
64a0c779 DN |
7484 | } |
7485 | ||
64a0c779 DN |
7486 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
7487 | return 0; | |
7488 | } | |
7489 | ||
64a0c779 DN |
7490 | /* Match the given token against cur_token. If they match, read the next |
7491 | token from the operand string. */ | |
7492 | static int | |
e3bb37b5 | 7493 | intel_match_token (int code) |
64a0c779 DN |
7494 | { |
7495 | if (cur_token.code == code) | |
7496 | { | |
7497 | intel_get_token (); | |
7498 | return 1; | |
7499 | } | |
7500 | else | |
7501 | { | |
0477af35 | 7502 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
7503 | return 0; |
7504 | } | |
7505 | } | |
7506 | ||
64a0c779 DN |
7507 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
7508 | static void | |
e3bb37b5 | 7509 | intel_get_token (void) |
64a0c779 DN |
7510 | { |
7511 | char *end_op; | |
7512 | const reg_entry *reg; | |
7513 | struct intel_token new_token; | |
7514 | ||
7515 | new_token.code = T_NIL; | |
7516 | new_token.reg = NULL; | |
7517 | new_token.str = NULL; | |
7518 | ||
4a1805b1 | 7519 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
7520 | cur_token to prev_token. */ |
7521 | if (prev_token.str) | |
7522 | free (prev_token.str); | |
7523 | ||
7524 | prev_token = cur_token; | |
7525 | ||
7526 | /* Skip whitespace. */ | |
7527 | while (is_space_char (*intel_parser.op_string)) | |
7528 | intel_parser.op_string++; | |
7529 | ||
7530 | /* Return an empty token if we find nothing else on the line. */ | |
7531 | if (*intel_parser.op_string == '\0') | |
7532 | { | |
7533 | cur_token = new_token; | |
7534 | return; | |
7535 | } | |
7536 | ||
7537 | /* The new token cannot be larger than the remainder of the operand | |
7538 | string. */ | |
a724f0f4 | 7539 | new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); |
64a0c779 DN |
7540 | new_token.str[0] = '\0'; |
7541 | ||
7542 | if (strchr ("0123456789", *intel_parser.op_string)) | |
7543 | { | |
7544 | char *p = new_token.str; | |
7545 | char *q = intel_parser.op_string; | |
7546 | new_token.code = T_CONST; | |
7547 | ||
7548 | /* Allow any kind of identifier char to encompass floating point and | |
7549 | hexadecimal numbers. */ | |
7550 | while (is_identifier_char (*q)) | |
7551 | *p++ = *q++; | |
7552 | *p = '\0'; | |
7553 | ||
7554 | /* Recognize special symbol names [0-9][bf]. */ | |
7555 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 7556 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
7557 | || intel_parser.op_string[1] == 'f')) |
7558 | new_token.code = T_ID; | |
7559 | } | |
7560 | ||
4d1bb795 | 7561 | else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) |
64a0c779 | 7562 | { |
4d1bb795 JB |
7563 | size_t len = end_op - intel_parser.op_string; |
7564 | ||
64a0c779 DN |
7565 | new_token.code = T_REG; |
7566 | new_token.reg = reg; | |
7567 | ||
4d1bb795 JB |
7568 | memcpy (new_token.str, intel_parser.op_string, len); |
7569 | new_token.str[len] = '\0'; | |
64a0c779 DN |
7570 | } |
7571 | ||
7572 | else if (is_identifier_char (*intel_parser.op_string)) | |
7573 | { | |
7574 | char *p = new_token.str; | |
7575 | char *q = intel_parser.op_string; | |
7576 | ||
7577 | /* A '.' or '$' followed by an identifier char is an identifier. | |
7578 | Otherwise, it's operator '.' followed by an expression. */ | |
7579 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
7580 | { | |
9306ca4a JB |
7581 | new_token.code = '.'; |
7582 | new_token.str[0] = '.'; | |
64a0c779 DN |
7583 | new_token.str[1] = '\0'; |
7584 | } | |
7585 | else | |
7586 | { | |
7587 | while (is_identifier_char (*q) || *q == '@') | |
7588 | *p++ = *q++; | |
7589 | *p = '\0'; | |
7590 | ||
9306ca4a JB |
7591 | if (strcasecmp (new_token.str, "NOT") == 0) |
7592 | new_token.code = '~'; | |
7593 | ||
7594 | else if (strcasecmp (new_token.str, "MOD") == 0) | |
7595 | new_token.code = '%'; | |
7596 | ||
7597 | else if (strcasecmp (new_token.str, "AND") == 0) | |
7598 | new_token.code = '&'; | |
7599 | ||
7600 | else if (strcasecmp (new_token.str, "OR") == 0) | |
7601 | new_token.code = '|'; | |
7602 | ||
7603 | else if (strcasecmp (new_token.str, "XOR") == 0) | |
7604 | new_token.code = '^'; | |
7605 | ||
7606 | else if (strcasecmp (new_token.str, "SHL") == 0) | |
7607 | new_token.code = T_SHL; | |
7608 | ||
7609 | else if (strcasecmp (new_token.str, "SHR") == 0) | |
7610 | new_token.code = T_SHR; | |
7611 | ||
7612 | else if (strcasecmp (new_token.str, "BYTE") == 0) | |
64a0c779 DN |
7613 | new_token.code = T_BYTE; |
7614 | ||
7615 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
7616 | new_token.code = T_WORD; | |
7617 | ||
7618 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
7619 | new_token.code = T_DWORD; | |
7620 | ||
9306ca4a JB |
7621 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
7622 | new_token.code = T_FWORD; | |
7623 | ||
64a0c779 DN |
7624 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
7625 | new_token.code = T_QWORD; | |
7626 | ||
9306ca4a JB |
7627 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
7628 | /* XXX remove (gcc still uses it) */ | |
7629 | || strcasecmp (new_token.str, "XWORD") == 0) | |
7630 | new_token.code = T_TBYTE; | |
7631 | ||
7632 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 | |
7633 | || strcasecmp (new_token.str, "OWORD") == 0) | |
7634 | new_token.code = T_XMMWORD; | |
64a0c779 DN |
7635 | |
7636 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
7637 | new_token.code = T_PTR; | |
7638 | ||
7639 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
7640 | new_token.code = T_SHORT; | |
7641 | ||
7642 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
7643 | { | |
7644 | new_token.code = T_OFFSET; | |
7645 | ||
7646 | /* ??? This is not mentioned in the MASM grammar but gcc | |
7647 | makes use of it with -mintel-syntax. OFFSET may be | |
7648 | followed by FLAT: */ | |
7649 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
7650 | strcat (new_token.str, " FLAT:"); | |
7651 | } | |
7652 | ||
7653 | /* ??? This is not mentioned in the MASM grammar. */ | |
7654 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
a724f0f4 JB |
7655 | { |
7656 | new_token.code = T_OFFSET; | |
7657 | if (*q == ':') | |
7658 | strcat (new_token.str, ":"); | |
7659 | else | |
7660 | as_bad (_("`:' expected")); | |
7661 | } | |
64a0c779 DN |
7662 | |
7663 | else | |
7664 | new_token.code = T_ID; | |
7665 | } | |
7666 | } | |
7667 | ||
9306ca4a JB |
7668 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
7669 | { | |
7670 | new_token.code = *intel_parser.op_string; | |
7671 | new_token.str[0] = *intel_parser.op_string; | |
7672 | new_token.str[1] = '\0'; | |
7673 | } | |
7674 | ||
7675 | else if (strchr ("<>", *intel_parser.op_string) | |
7676 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
7677 | { | |
7678 | new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; | |
7679 | new_token.str[0] = *intel_parser.op_string; | |
7680 | new_token.str[1] = *intel_parser.op_string; | |
7681 | new_token.str[2] = '\0'; | |
7682 | } | |
7683 | ||
64a0c779 | 7684 | else |
0477af35 | 7685 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
7686 | |
7687 | intel_parser.op_string += strlen (new_token.str); | |
7688 | cur_token = new_token; | |
7689 | } | |
7690 | ||
64a0c779 DN |
7691 | /* Put cur_token back into the token stream and make cur_token point to |
7692 | prev_token. */ | |
7693 | static void | |
e3bb37b5 | 7694 | intel_putback_token (void) |
64a0c779 | 7695 | { |
a724f0f4 JB |
7696 | if (cur_token.code != T_NIL) |
7697 | { | |
7698 | intel_parser.op_string -= strlen (cur_token.str); | |
7699 | free (cur_token.str); | |
7700 | } | |
64a0c779 | 7701 | cur_token = prev_token; |
4a1805b1 | 7702 | |
64a0c779 DN |
7703 | /* Forget prev_token. */ |
7704 | prev_token.code = T_NIL; | |
7705 | prev_token.reg = NULL; | |
7706 | prev_token.str = NULL; | |
7707 | } | |
54cfded0 | 7708 | |
a4447b93 | 7709 | int |
1df69f4f | 7710 | tc_x86_regname_to_dw2regnum (char *regname) |
54cfded0 AM |
7711 | { |
7712 | unsigned int regnum; | |
7713 | unsigned int regnames_count; | |
089dfecd | 7714 | static const char *const regnames_32[] = |
54cfded0 | 7715 | { |
a4447b93 RH |
7716 | "eax", "ecx", "edx", "ebx", |
7717 | "esp", "ebp", "esi", "edi", | |
089dfecd JB |
7718 | "eip", "eflags", NULL, |
7719 | "st0", "st1", "st2", "st3", | |
7720 | "st4", "st5", "st6", "st7", | |
7721 | NULL, NULL, | |
7722 | "xmm0", "xmm1", "xmm2", "xmm3", | |
7723 | "xmm4", "xmm5", "xmm6", "xmm7", | |
7724 | "mm0", "mm1", "mm2", "mm3", | |
43fd16e4 JB |
7725 | "mm4", "mm5", "mm6", "mm7", |
7726 | "fcw", "fsw", "mxcsr", | |
7727 | "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, | |
7728 | "tr", "ldtr" | |
54cfded0 | 7729 | }; |
089dfecd | 7730 | static const char *const regnames_64[] = |
54cfded0 | 7731 | { |
089dfecd JB |
7732 | "rax", "rdx", "rcx", "rbx", |
7733 | "rsi", "rdi", "rbp", "rsp", | |
7734 | "r8", "r9", "r10", "r11", | |
54cfded0 | 7735 | "r12", "r13", "r14", "r15", |
089dfecd JB |
7736 | "rip", |
7737 | "xmm0", "xmm1", "xmm2", "xmm3", | |
7738 | "xmm4", "xmm5", "xmm6", "xmm7", | |
7739 | "xmm8", "xmm9", "xmm10", "xmm11", | |
7740 | "xmm12", "xmm13", "xmm14", "xmm15", | |
7741 | "st0", "st1", "st2", "st3", | |
7742 | "st4", "st5", "st6", "st7", | |
7743 | "mm0", "mm1", "mm2", "mm3", | |
43fd16e4 JB |
7744 | "mm4", "mm5", "mm6", "mm7", |
7745 | "rflags", | |
7746 | "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, | |
7747 | "fs.base", "gs.base", NULL, NULL, | |
7748 | "tr", "ldtr", | |
7749 | "mxcsr", "fcw", "fsw" | |
54cfded0 | 7750 | }; |
089dfecd | 7751 | const char *const *regnames; |
54cfded0 AM |
7752 | |
7753 | if (flag_code == CODE_64BIT) | |
7754 | { | |
7755 | regnames = regnames_64; | |
0cea6190 | 7756 | regnames_count = ARRAY_SIZE (regnames_64); |
54cfded0 AM |
7757 | } |
7758 | else | |
7759 | { | |
7760 | regnames = regnames_32; | |
0cea6190 | 7761 | regnames_count = ARRAY_SIZE (regnames_32); |
54cfded0 AM |
7762 | } |
7763 | ||
7764 | for (regnum = 0; regnum < regnames_count; regnum++) | |
089dfecd JB |
7765 | if (regnames[regnum] != NULL |
7766 | && strcmp (regname, regnames[regnum]) == 0) | |
54cfded0 AM |
7767 | return regnum; |
7768 | ||
54cfded0 AM |
7769 | return -1; |
7770 | } | |
7771 | ||
7772 | void | |
7773 | tc_x86_frame_initial_instructions (void) | |
7774 | { | |
a4447b93 RH |
7775 | static unsigned int sp_regno; |
7776 | ||
7777 | if (!sp_regno) | |
7778 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT | |
7779 | ? "rsp" : "esp"); | |
7780 | ||
7781 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); | |
7782 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 7783 | } |
d2b2c203 DJ |
7784 | |
7785 | int | |
7786 | i386_elf_section_type (const char *str, size_t len) | |
7787 | { | |
7788 | if (flag_code == CODE_64BIT | |
7789 | && len == sizeof ("unwind") - 1 | |
7790 | && strncmp (str, "unwind", 6) == 0) | |
7791 | return SHT_X86_64_UNWIND; | |
7792 | ||
7793 | return -1; | |
7794 | } | |
bb41ade5 AM |
7795 | |
7796 | #ifdef TE_PE | |
7797 | void | |
7798 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
7799 | { | |
7800 | expressionS expr; | |
7801 | ||
7802 | expr.X_op = O_secrel; | |
7803 | expr.X_add_symbol = symbol; | |
7804 | expr.X_add_number = 0; | |
7805 | emit_expr (&expr, size); | |
7806 | } | |
7807 | #endif | |
3b22753a L |
7808 | |
7809 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
7810 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
7811 | ||
7812 | int | |
7813 | x86_64_section_letter (int letter, char **ptr_msg) | |
7814 | { | |
7815 | if (flag_code == CODE_64BIT) | |
7816 | { | |
7817 | if (letter == 'l') | |
7818 | return SHF_X86_64_LARGE; | |
7819 | ||
7820 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 7821 | } |
3b22753a | 7822 | else |
64e74474 | 7823 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
7824 | return -1; |
7825 | } | |
7826 | ||
7827 | int | |
7828 | x86_64_section_word (char *str, size_t len) | |
7829 | { | |
8620418b | 7830 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
7831 | return SHF_X86_64_LARGE; |
7832 | ||
7833 | return -1; | |
7834 | } | |
7835 | ||
7836 | static void | |
7837 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
7838 | { | |
7839 | if (flag_code != CODE_64BIT) | |
7840 | { | |
7841 | s_comm_internal (0, elf_common_parse); | |
7842 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
7843 | } | |
7844 | else | |
7845 | { | |
7846 | static segT lbss_section; | |
7847 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
7848 | asection *saved_bss_section = bss_section; | |
7849 | ||
7850 | if (lbss_section == NULL) | |
7851 | { | |
7852 | flagword applicable; | |
7853 | segT seg = now_seg; | |
7854 | subsegT subseg = now_subseg; | |
7855 | ||
7856 | /* The .lbss section is for local .largecomm symbols. */ | |
7857 | lbss_section = subseg_new (".lbss", 0); | |
7858 | applicable = bfd_applicable_section_flags (stdoutput); | |
7859 | bfd_set_section_flags (stdoutput, lbss_section, | |
7860 | applicable & SEC_ALLOC); | |
7861 | seg_info (lbss_section)->bss = 1; | |
7862 | ||
7863 | subseg_set (seg, subseg); | |
7864 | } | |
7865 | ||
7866 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
7867 | bss_section = lbss_section; | |
7868 | ||
7869 | s_comm_internal (0, elf_common_parse); | |
7870 | ||
7871 | elf_com_section_ptr = saved_com_section_ptr; | |
7872 | bss_section = saved_bss_section; | |
7873 | } | |
7874 | } | |
7875 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |