projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Implement Intel OSPKE instructions
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
8dcea932
L		 521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522/* 1 if generating code for a shared library. */
523static int shared = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
770 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 772 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 774 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 776 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 782 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 784 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 786 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 788 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
790 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
792 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 794 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
796 CPU_BTVER1_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
798 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 800 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 802 CPU_287_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 804 CPU_387_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 806 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 808 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 826 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
830 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
832 CPU_AVX512F_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
834 CPU_AVX512CD_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
836 CPU_AVX512ER_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
838 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
840 CPU_AVX512DQ_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
842 CPU_AVX512BW_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
844 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 846 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 848 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
850 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 856 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
858 CPU_XSAVEC_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
860 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 862 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 864 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 866 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 868 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 870 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 872 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
874 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 876 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 878 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 880 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 882 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 884 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
886 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 888 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
890 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
892 CPU_HLE_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
894 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
896 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 898 CPU_CLFLUSH_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
900 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 902 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 904 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 906 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 908 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 910 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 914 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 916 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 918 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
920 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
922 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
924 CPU_ADX_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
926 CPU_RDSEED_FLAGS, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
928 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
930 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
932 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
934 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
936 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
938 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
940 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
942 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
944 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
946 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
948 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
950 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
952 CPU_MWAITX_FLAGS, 0, 0 },
8eab4136
L		 953 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
954 CPU_OSPKE_FLAGS, 0, 0 },
e413e4e9
AM		 955};
956
704209c0 957#ifdef I386COFF
a6c24e68
NC		 958/* Like s_lcomm_internal in gas/read.c but the alignment string
959 is allowed to be optional. */
960
961static symbolS *
962pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
963{
964 addressT align = 0;
965
966 SKIP_WHITESPACE ();
967
7ab9ffdd 968 if (needs_align
a6c24e68
NC		 969 && *input_line_pointer == ',')
970 {
971 align = parse_align (needs_align - 1);
7ab9ffdd 972
a6c24e68
NC		 973 if (align == (addressT) -1)
974 return NULL;
975 }
976 else
977 {
978 if (size >= 8)
979 align = 3;
980 else if (size >= 4)
981 align = 2;
982 else if (size >= 2)
983 align = 1;
984 else
985 align = 0;
986 }
987
988 bss_alloc (symbolP, size, align);
989 return symbolP;
990}
991
704209c0 992static void
a6c24e68
NC		 993pe_lcomm (int needs_align)
994{
995 s_comm_internal (needs_align * 2, pe_lcomm_internal);
996}
704209c0 997#endif
a6c24e68 998
29b0f896
AM		 999const pseudo_typeS md_pseudo_table[] =
1000{
1001#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1002 {"align", s_align_bytes, 0},
1003#else
1004 {"align", s_align_ptwo, 0},
1005#endif
1006 {"arch", set_cpu_arch, 0},
1007#ifndef I386COFF
1008 {"bss", s_bss, 0},
a6c24e68
NC		 1009#else
1010 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1011#endif
1012 {"ffloat", float_cons, 'f'},
1013 {"dfloat", float_cons, 'd'},
1014 {"tfloat", float_cons, 'x'},
1015 {"value", cons, 2},
d182319b 1016 {"slong", signed_cons, 4},
29b0f896
AM		 1017 {"noopt", s_ignore, 0},
1018 {"optim", s_ignore, 0},
1019 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1020 {"code16", set_code_flag, CODE_16BIT},
1021 {"code32", set_code_flag, CODE_32BIT},
1022 {"code64", set_code_flag, CODE_64BIT},
1023 {"intel_syntax", set_intel_syntax, 1},
1024 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1025 {"intel_mnemonic", set_intel_mnemonic, 1},
1026 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1027 {"allow_index_reg", set_allow_index_reg, 1},
1028 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1029 {"sse_check", set_check, 0},
1030 {"operand_check", set_check, 1},
3b22753a
L		 1031#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1032 {"largecomm", handle_large_common, 0},
07a53e5c 1033#else
e3bb37b5 1034 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1035 {"loc", dwarf2_directive_loc, 0},
1036 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1037#endif
6482c264
NC		 1038#ifdef TE_PE
1039 {"secrel32", pe_directive_secrel, 0},
1040#endif
29b0f896
AM		 1041 {0, 0, 0}
1042};
1043
1044/* For interface with expression (). */
1045extern char *input_line_pointer;
1046
1047/* Hash table for instruction mnemonic lookup. */
1048static struct hash_control *op_hash;
1049
1050/* Hash table for register lookup. */
1051static struct hash_control *reg_hash;
1052\f
252b5132 1053void
e3bb37b5 1054i386_align_code (fragS *fragP, int count)
252b5132 1055{
ce8a8b2f
AM		 1056 /* Various efficient no-op patterns for aligning code labels.
1057 Note: Don't try to assemble the instructions in the comments.
1058 0L and 0w are not legal. */
252b5132
RH		 1059 static const char f32_1[] =
1060 {0x90}; /* nop */
1061 static const char f32_2[] =
ccc9c027 1062 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1063 static const char f32_3[] =
1064 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1065 static const char f32_4[] =
1066 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1067 static const char f32_5[] =
1068 {0x90, /* nop */
1069 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1070 static const char f32_6[] =
1071 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1072 static const char f32_7[] =
1073 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1074 static const char f32_8[] =
1075 {0x90, /* nop */
1076 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1077 static const char f32_9[] =
1078 {0x89,0xf6, /* movl %esi,%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_10[] =
1081 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1082 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1083 static const char f32_11[] =
1084 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1085 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1086 static const char f32_12[] =
1087 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1088 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1089 static const char f32_13[] =
1090 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1092 static const char f32_14[] =
1093 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1094 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1095 static const char f16_3[] =
1096 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1097 static const char f16_4[] =
1098 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1099 static const char f16_5[] =
1100 {0x90, /* nop */
1101 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1102 static const char f16_6[] =
1103 {0x89,0xf6, /* mov %si,%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1105 static const char f16_7[] =
1106 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1107 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1108 static const char f16_8[] =
1109 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1110 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1111 static const char jump_31[] =
1112 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1114 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1115 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1116 static const char *const f32_patt[] = {
1117 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1118 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1119 };
1120 static const char *const f16_patt[] = {
76bc74dc 1121 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1122 };
ccc9c027
L		 1123 /* nopl (%[re]ax) */
1124 static const char alt_3[] =
1125 {0x0f,0x1f,0x00};
1126 /* nopl 0(%[re]ax) */
1127 static const char alt_4[] =
1128 {0x0f,0x1f,0x40,0x00};
1129 /* nopl 0(%[re]ax,%[re]ax,1) */
1130 static const char alt_5[] =
1131 {0x0f,0x1f,0x44,0x00,0x00};
1132 /* nopw 0(%[re]ax,%[re]ax,1) */
1133 static const char alt_6[] =
1134 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1135 /* nopl 0L(%[re]ax) */
1136 static const char alt_7[] =
1137 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1138 /* nopl 0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_8[] =
1140 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 /* nopw 0L(%[re]ax,%[re]ax,1) */
1142 static const char alt_9[] =
1143 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1145 static const char alt_10[] =
1146 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1147 static const char *const alt_patt[] = {
ccc9c027 1148 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1149 alt_9, alt_10
ccc9c027 1150 };
252b5132 1151
76bc74dc
L		 1152 /* Only align for at least a positive non-zero boundary. */
1153 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1154 return;
3e73aa7c 1155
ccc9c027
L		 1156 /* We need to decide which NOP sequence to use for 32bit and
1157 64bit. When -mtune= is used:
4eed87de 1158
76bc74dc
L		 1159 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1160 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1161 2. For the rest, alt_patt will be used.
1162
1163 When -mtune= isn't used, alt_patt will be used if
22109423 1164 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1165 be used.
ccc9c027
L		 1166
1167 When -march= or .arch is used, we can't use anything beyond
1168 cpu_arch_isa_flags. */
1169
1170 if (flag_code == CODE_16BIT)
1171 {
ccc9c027 1172 if (count > 8)
33fef721 1173 {
76bc74dc
L		 1174 memcpy (fragP->fr_literal + fragP->fr_fix,
1175 jump_31, count);
1176 /* Adjust jump offset. */
1177 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1178 }
76bc74dc
L		 1179 else
1180 memcpy (fragP->fr_literal + fragP->fr_fix,
1181 f16_patt[count - 1], count);
252b5132 1182 }
33fef721 1183 else
ccc9c027
L		 1184 {
1185 const char *const *patt = NULL;
1186
fbf3f584 1187 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1188 {
1189 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1190 switch (cpu_arch_tune)
1191 {
1192 case PROCESSOR_UNKNOWN:
1193 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1194 optimize with nops. */
1195 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1196 patt = alt_patt;
ccc9c027
L		 1197 else
1198 patt = f32_patt;
1199 break;
ccc9c027
L		 1200 case PROCESSOR_PENTIUM4:
1201 case PROCESSOR_NOCONA:
ef05d495 1202 case PROCESSOR_CORE:
76bc74dc 1203 case PROCESSOR_CORE2:
bd5295b2 1204 case PROCESSOR_COREI7:
3632d14b 1205 case PROCESSOR_L1OM:
7a9068fe 1206 case PROCESSOR_K1OM:
76bc74dc 1207 case PROCESSOR_GENERIC64:
ccc9c027
L		 1208 case PROCESSOR_K6:
1209 case PROCESSOR_ATHLON:
1210 case PROCESSOR_K8:
4eed87de 1211 case PROCESSOR_AMDFAM10:
8aedb9fe 1212 case PROCESSOR_BD:
029f3522 1213 case PROCESSOR_ZNVER:
7b458c12 1214 case PROCESSOR_BT:
80b8656c 1215 patt = alt_patt;
ccc9c027 1216 break;
76bc74dc 1217 case PROCESSOR_I386:
ccc9c027
L		 1218 case PROCESSOR_I486:
1219 case PROCESSOR_PENTIUM:
2dde1948 1220 case PROCESSOR_PENTIUMPRO:
81486035 1221 case PROCESSOR_IAMCU:
ccc9c027
L		 1222 case PROCESSOR_GENERIC32:
1223 patt = f32_patt;
1224 break;
4eed87de 1225 }
ccc9c027
L		 1226 }
1227 else
1228 {
fbf3f584 1229 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1230 {
1231 case PROCESSOR_UNKNOWN:
e6a14101 1232 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1233 PROCESSOR_UNKNOWN. */
1234 abort ();
1235 break;
1236
76bc74dc 1237 case PROCESSOR_I386:
ccc9c027
L		 1238 case PROCESSOR_I486:
1239 case PROCESSOR_PENTIUM:
81486035 1240 case PROCESSOR_IAMCU:
ccc9c027
L		 1241 case PROCESSOR_K6:
1242 case PROCESSOR_ATHLON:
1243 case PROCESSOR_K8:
4eed87de 1244 case PROCESSOR_AMDFAM10:
8aedb9fe 1245 case PROCESSOR_BD:
029f3522 1246 case PROCESSOR_ZNVER:
7b458c12 1247 case PROCESSOR_BT:
ccc9c027
L		 1248 case PROCESSOR_GENERIC32:
1249 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1250 with nops. */
1251 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1252 patt = alt_patt;
ccc9c027
L		 1253 else
1254 patt = f32_patt;
1255 break;
76bc74dc
L		 1256 case PROCESSOR_PENTIUMPRO:
1257 case PROCESSOR_PENTIUM4:
1258 case PROCESSOR_NOCONA:
1259 case PROCESSOR_CORE:
ef05d495 1260 case PROCESSOR_CORE2:
bd5295b2 1261 case PROCESSOR_COREI7:
3632d14b 1262 case PROCESSOR_L1OM:
7a9068fe 1263 case PROCESSOR_K1OM:
22109423 1264 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1265 patt = alt_patt;
ccc9c027
L		 1266 else
1267 patt = f32_patt;
1268 break;
1269 case PROCESSOR_GENERIC64:
80b8656c 1270 patt = alt_patt;
ccc9c027 1271 break;
4eed87de 1272 }
ccc9c027
L		 1273 }
1274
76bc74dc
L		 1275 if (patt == f32_patt)
1276 {
1277 /* If the padding is less than 15 bytes, we use the normal
1278 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1279 its offset. */
1280 int limit;
76ba9986 1281
711eedef
L		 1282 /* For 64bit, the limit is 3 bytes. */
1283 if (flag_code == CODE_64BIT
1284 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1285 limit = 3;
1286 else
1287 limit = 15;
1288 if (count < limit)
76bc74dc
L		 1289 memcpy (fragP->fr_literal + fragP->fr_fix,
1290 patt[count - 1], count);
1291 else
1292 {
1293 memcpy (fragP->fr_literal + fragP->fr_fix,
1294 jump_31, count);
1295 /* Adjust jump offset. */
1296 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1297 }
1298 }
1299 else
1300 {
80b8656c
L		 1301 /* Maximum length of an instruction is 10 byte. If the
1302 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1303 we have to break it into smaller pieces. */
1304 int padding = count;
80b8656c 1305 while (padding > 10)
76bc74dc 1306 {
80b8656c 1307 padding -= 10;
76bc74dc 1308 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1309 patt [9], 10);
76bc74dc
L		 1310 }
1311
1312 if (padding)
1313 memcpy (fragP->fr_literal + fragP->fr_fix,
1314 patt [padding - 1], padding);
1315 }
ccc9c027 1316 }
33fef721 1317 fragP->fr_var = count;
252b5132
RH		 1318}
1319
c6fb90c8 1320static INLINE int
0dfbf9d7 1321operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1322{
0dfbf9d7 1323 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1324 {
1325 case 3:
0dfbf9d7 1326 if (x->array[2])
c6fb90c8
L		 1327 return 0;
1328 case 2:
0dfbf9d7 1329 if (x->array[1])
c6fb90c8
L		 1330 return 0;
1331 case 1:
0dfbf9d7 1332 return !x->array[0];
c6fb90c8
L		 1333 default:
1334 abort ();
1335 }
40fb9820
L		 1336}
1337
c6fb90c8 1338static INLINE void
0dfbf9d7 1339operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1340{
0dfbf9d7 1341 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1342 {
1343 case 3:
0dfbf9d7 1344 x->array[2] = v;
c6fb90c8 1345 case 2:
0dfbf9d7 1346 x->array[1] = v;
c6fb90c8 1347 case 1:
0dfbf9d7 1348 x->array[0] = v;
c6fb90c8
L		 1349 break;
1350 default:
1351 abort ();
1352 }
1353}
40fb9820 1354
c6fb90c8 1355static INLINE int
0dfbf9d7
L		 1356operand_type_equal (const union i386_operand_type *x,
1357 const union i386_operand_type *y)
c6fb90c8 1358{
0dfbf9d7 1359 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1360 {
1361 case 3:
0dfbf9d7 1362 if (x->array[2] != y->array[2])
c6fb90c8
L		 1363 return 0;
1364 case 2:
0dfbf9d7 1365 if (x->array[1] != y->array[1])
c6fb90c8
L		 1366 return 0;
1367 case 1:
0dfbf9d7 1368 return x->array[0] == y->array[0];
c6fb90c8
L		 1369 break;
1370 default:
1371 abort ();
1372 }
1373}
40fb9820 1374
0dfbf9d7
L		 1375static INLINE int
1376cpu_flags_all_zero (const union i386_cpu_flags *x)
1377{
1378 switch (ARRAY_SIZE(x->array))
1379 {
1380 case 3:
1381 if (x->array[2])
1382 return 0;
1383 case 2:
1384 if (x->array[1])
1385 return 0;
1386 case 1:
1387 return !x->array[0];
1388 default:
1389 abort ();
1390 }
1391}
1392
0dfbf9d7
L		 1393static INLINE int
1394cpu_flags_equal (const union i386_cpu_flags *x,
1395 const union i386_cpu_flags *y)
1396{
1397 switch (ARRAY_SIZE(x->array))
1398 {
1399 case 3:
1400 if (x->array[2] != y->array[2])
1401 return 0;
1402 case 2:
1403 if (x->array[1] != y->array[1])
1404 return 0;
1405 case 1:
1406 return x->array[0] == y->array[0];
1407 break;
1408 default:
1409 abort ();
1410 }
1411}
c6fb90c8
L		 1412
1413static INLINE int
1414cpu_flags_check_cpu64 (i386_cpu_flags f)
1415{
1416 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1417 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1418}
1419
c6fb90c8
L		 1420static INLINE i386_cpu_flags
1421cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1422{
c6fb90c8
L		 1423 switch (ARRAY_SIZE (x.array))
1424 {
1425 case 3:
1426 x.array [2] &= y.array [2];
1427 case 2:
1428 x.array [1] &= y.array [1];
1429 case 1:
1430 x.array [0] &= y.array [0];
1431 break;
1432 default:
1433 abort ();
1434 }
1435 return x;
1436}
40fb9820 1437
c6fb90c8
L		 1438static INLINE i386_cpu_flags
1439cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1440{
c6fb90c8 1441 switch (ARRAY_SIZE (x.array))
40fb9820 1442 {
c6fb90c8
L		 1443 case 3:
1444 x.array [2] |= y.array [2];
1445 case 2:
1446 x.array [1] |= y.array [1];
1447 case 1:
1448 x.array [0] |= y.array [0];
40fb9820
L		 1449 break;
1450 default:
1451 abort ();
1452 }
40fb9820
L		 1453 return x;
1454}
1455
309d3373
JB		 1456static INLINE i386_cpu_flags
1457cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1458{
1459 switch (ARRAY_SIZE (x.array))
1460 {
1461 case 3:
1462 x.array [2] &= ~y.array [2];
1463 case 2:
1464 x.array [1] &= ~y.array [1];
1465 case 1:
1466 x.array [0] &= ~y.array [0];
1467 break;
1468 default:
1469 abort ();
1470 }
1471 return x;
1472}
1473
81486035
L		 1474static int
1475valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1476{
1477 if (cpu_arch_isa == PROCESSOR_IAMCU)
1478 {
1479 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1480 i386_cpu_flags compat_flags;
1481 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1482 return cpu_flags_all_zero (&compat_flags);
1483 }
1484 else
1485 return 1;
1486}
1487
c0f3af97
L		 1488#define CPU_FLAGS_ARCH_MATCH 0x1
1489#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1490#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1491#define CPU_FLAGS_PCLMUL_MATCH 0x8
1492#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1493
a5ff0eb2 1494#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1495 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1496 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1497#define CPU_FLAGS_PERFECT_MATCH \
1498 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1499
1500/* Return CPU flags match bits. */
3629bb00 1501
40fb9820 1502static int
d3ce72d0 1503cpu_flags_match (const insn_template *t)
40fb9820 1504{
c0f3af97
L		 1505 i386_cpu_flags x = t->cpu_flags;
1506 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1507
1508 x.bitfield.cpu64 = 0;
1509 x.bitfield.cpuno64 = 0;
1510
0dfbf9d7 1511 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1512 {
1513 /* This instruction is available on all archs. */
1514 match |= CPU_FLAGS_32BIT_MATCH;
1515 }
3629bb00
L		 1516 else
1517 {
c0f3af97 1518 /* This instruction is available only on some archs. */
3629bb00
L		 1519 i386_cpu_flags cpu = cpu_arch_flags;
1520
1521 cpu.bitfield.cpu64 = 0;
1522 cpu.bitfield.cpuno64 = 0;
1523 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1524 if (!cpu_flags_all_zero (&cpu))
1525 {
a5ff0eb2
L		 1526 if (x.bitfield.cpuavx)
1527 {
ce2f5b3c 1528 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1529 if (cpu.bitfield.cpuavx)
1530 {
1531 /* Check SSE2AVX. */
1532 if (!t->opcode_modifier.sse2avx|| sse2avx)
1533 {
1534 match |= (CPU_FLAGS_ARCH_MATCH
1535 | CPU_FLAGS_AVX_MATCH);
1536 /* Check AES. */
1537 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1538 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1539 /* Check PCLMUL. */
1540 if (!x.bitfield.cpupclmul
1541 || cpu.bitfield.cpupclmul)
1542 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1543 }
1544 }
1545 else
1546 match |= CPU_FLAGS_ARCH_MATCH;
1547 }
1548 else
c0f3af97
L		 1549 match |= CPU_FLAGS_32BIT_MATCH;
1550 }
3629bb00 1551 }
c0f3af97 1552 return match;
40fb9820
L		 1553}
1554
c6fb90c8
L		 1555static INLINE i386_operand_type
1556operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1557{
c6fb90c8
L		 1558 switch (ARRAY_SIZE (x.array))
1559 {
1560 case 3:
1561 x.array [2] &= y.array [2];
1562 case 2:
1563 x.array [1] &= y.array [1];
1564 case 1:
1565 x.array [0] &= y.array [0];
1566 break;
1567 default:
1568 abort ();
1569 }
1570 return x;
40fb9820
L		 1571}
1572
c6fb90c8
L		 1573static INLINE i386_operand_type
1574operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1575{
c6fb90c8 1576 switch (ARRAY_SIZE (x.array))
40fb9820 1577 {
c6fb90c8
L		 1578 case 3:
1579 x.array [2] |= y.array [2];
1580 case 2:
1581 x.array [1] |= y.array [1];
1582 case 1:
1583 x.array [0] |= y.array [0];
40fb9820
L		 1584 break;
1585 default:
1586 abort ();
1587 }
c6fb90c8
L		 1588 return x;
1589}
40fb9820 1590
c6fb90c8
L		 1591static INLINE i386_operand_type
1592operand_type_xor (i386_operand_type x, i386_operand_type y)
1593{
1594 switch (ARRAY_SIZE (x.array))
1595 {
1596 case 3:
1597 x.array [2] ^= y.array [2];
1598 case 2:
1599 x.array [1] ^= y.array [1];
1600 case 1:
1601 x.array [0] ^= y.array [0];
1602 break;
1603 default:
1604 abort ();
1605 }
40fb9820
L		 1606 return x;
1607}
1608
1609static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1610static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1611static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1612static const i386_operand_type inoutportreg
1613 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1614static const i386_operand_type reg16_inoutportreg
1615 = OPERAND_TYPE_REG16_INOUTPORTREG;
1616static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1617static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1618static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1619static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1620static const i386_operand_type anydisp
1621 = OPERAND_TYPE_ANYDISP;
40fb9820 1622static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1623static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1624static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1625static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1626static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1627static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1628static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1629static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1630static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1631static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1632static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1633static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1634static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1635static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1636
1637enum operand_type
1638{
1639 reg,
40fb9820
L		 1640 imm,
1641 disp,
1642 anymem
1643};
1644
c6fb90c8 1645static INLINE int
40fb9820
L		 1646operand_type_check (i386_operand_type t, enum operand_type c)
1647{
1648 switch (c)
1649 {
1650 case reg:
1651 return (t.bitfield.reg8
1652 || t.bitfield.reg16
1653 || t.bitfield.reg32
1654 || t.bitfield.reg64);
1655
40fb9820
L		 1656 case imm:
1657 return (t.bitfield.imm8
1658 || t.bitfield.imm8s
1659 || t.bitfield.imm16
1660 || t.bitfield.imm32
1661 || t.bitfield.imm32s
1662 || t.bitfield.imm64);
1663
1664 case disp:
1665 return (t.bitfield.disp8
1666 || t.bitfield.disp16
1667 || t.bitfield.disp32
1668 || t.bitfield.disp32s
1669 || t.bitfield.disp64);
1670
1671 case anymem:
1672 return (t.bitfield.disp8
1673 || t.bitfield.disp16
1674 || t.bitfield.disp32
1675 || t.bitfield.disp32s
1676 || t.bitfield.disp64
1677 || t.bitfield.baseindex);
1678
1679 default:
1680 abort ();
1681 }
2cfe26b6
AM		 1682
1683 return 0;
40fb9820
L		 1684}
1685
5c07affc
L		 1686/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1687 operand J for instruction template T. */
1688
1689static INLINE int
d3ce72d0 1690match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1691{
1692 return !((i.types[j].bitfield.byte
1693 && !t->operand_types[j].bitfield.byte)
1694 || (i.types[j].bitfield.word
1695 && !t->operand_types[j].bitfield.word)
1696 || (i.types[j].bitfield.dword
1697 && !t->operand_types[j].bitfield.dword)
1698 || (i.types[j].bitfield.qword
1699 && !t->operand_types[j].bitfield.qword));
1700}
1701
1702/* Return 1 if there is no conflict in any size on operand J for
1703 instruction template T. */
1704
1705static INLINE int
d3ce72d0 1706match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1707{
1708 return (match_reg_size (t, j)
1709 && !((i.types[j].bitfield.unspecified
af508cb9 1710 && !i.broadcast
5c07affc
L		 1711 && !t->operand_types[j].bitfield.unspecified)
1712 || (i.types[j].bitfield.fword
1713 && !t->operand_types[j].bitfield.fword)
1714 || (i.types[j].bitfield.tbyte
1715 && !t->operand_types[j].bitfield.tbyte)
1716 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1717 && !t->operand_types[j].bitfield.xmmword)
1718 || (i.types[j].bitfield.ymmword
43234a1e
L		 1719 && !t->operand_types[j].bitfield.ymmword)
1720 || (i.types[j].bitfield.zmmword
1721 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1722}
1723
1724/* Return 1 if there is no size conflict on any operands for
1725 instruction template T. */
1726
1727static INLINE int
d3ce72d0 1728operand_size_match (const insn_template *t)
5c07affc
L		 1729{
1730 unsigned int j;
1731 int match = 1;
1732
1733 /* Don't check jump instructions. */
1734 if (t->opcode_modifier.jump
1735 || t->opcode_modifier.jumpbyte
1736 || t->opcode_modifier.jumpdword
1737 || t->opcode_modifier.jumpintersegment)
1738 return match;
1739
1740 /* Check memory and accumulator operand size. */
1741 for (j = 0; j < i.operands; j++)
1742 {
1743 if (t->operand_types[j].bitfield.anysize)
1744 continue;
1745
1746 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1747 {
1748 match = 0;
1749 break;
1750 }
1751
1752 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1753 {
1754 match = 0;
1755 break;
1756 }
1757 }
1758
891edac4 1759 if (match)
5c07affc 1760 return match;
891edac4
L		 1761 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1762 {
1763mismatch:
86e026a4 1764 i.error = operand_size_mismatch;
891edac4
L		 1765 return 0;
1766 }
5c07affc
L		 1767
1768 /* Check reverse. */
9c2799c2 1769 gas_assert (i.operands == 2);
5c07affc
L		 1770
1771 match = 1;
1772 for (j = 0; j < 2; j++)
1773 {
1774 if (t->operand_types[j].bitfield.acc
1775 && !match_reg_size (t, j ? 0 : 1))
891edac4 1776 goto mismatch;
5c07affc
L		 1777
1778 if (i.types[j].bitfield.mem
1779 && !match_mem_size (t, j ? 0 : 1))
891edac4 1780 goto mismatch;
5c07affc
L		 1781 }
1782
1783 return match;
1784}
1785
c6fb90c8 1786static INLINE int
40fb9820
L		 1787operand_type_match (i386_operand_type overlap,
1788 i386_operand_type given)
1789{
1790 i386_operand_type temp = overlap;
1791
1792 temp.bitfield.jumpabsolute = 0;
7d5e4556 1793 temp.bitfield.unspecified = 0;
5c07affc
L		 1794 temp.bitfield.byte = 0;
1795 temp.bitfield.word = 0;
1796 temp.bitfield.dword = 0;
1797 temp.bitfield.fword = 0;
1798 temp.bitfield.qword = 0;
1799 temp.bitfield.tbyte = 0;
1800 temp.bitfield.xmmword = 0;
c0f3af97 1801 temp.bitfield.ymmword = 0;
43234a1e 1802 temp.bitfield.zmmword = 0;
0dfbf9d7 1803 if (operand_type_all_zero (&temp))
891edac4 1804 goto mismatch;
40fb9820 1805
891edac4
L		 1806 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1807 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1808 return 1;
1809
1810mismatch:
a65babc9 1811 i.error = operand_type_mismatch;
891edac4 1812 return 0;
40fb9820
L		 1813}
1814
7d5e4556 1815/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1816 unless the expected operand type register overlap is null.
1817 Note that Acc in a template matches every size of reg. */
1818
c6fb90c8 1819static INLINE int
40fb9820
L		 1820operand_type_register_match (i386_operand_type m0,
1821 i386_operand_type g0,
1822 i386_operand_type t0,
1823 i386_operand_type m1,
1824 i386_operand_type g1,
1825 i386_operand_type t1)
1826{
1827 if (!operand_type_check (g0, reg))
1828 return 1;
1829
1830 if (!operand_type_check (g1, reg))
1831 return 1;
1832
1833 if (g0.bitfield.reg8 == g1.bitfield.reg8
1834 && g0.bitfield.reg16 == g1.bitfield.reg16
1835 && g0.bitfield.reg32 == g1.bitfield.reg32
1836 && g0.bitfield.reg64 == g1.bitfield.reg64)
1837 return 1;
1838
1839 if (m0.bitfield.acc)
1840 {
1841 t0.bitfield.reg8 = 1;
1842 t0.bitfield.reg16 = 1;
1843 t0.bitfield.reg32 = 1;
1844 t0.bitfield.reg64 = 1;
1845 }
1846
1847 if (m1.bitfield.acc)
1848 {
1849 t1.bitfield.reg8 = 1;
1850 t1.bitfield.reg16 = 1;
1851 t1.bitfield.reg32 = 1;
1852 t1.bitfield.reg64 = 1;
1853 }
1854
891edac4
L		 1855 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1856 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1857 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1858 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1859 return 1;
1860
a65babc9 1861 i.error = register_type_mismatch;
891edac4
L		 1862
1863 return 0;
40fb9820
L		 1864}
1865
4c692bc7
JB		 1866static INLINE unsigned int
1867register_number (const reg_entry *r)
1868{
1869 unsigned int nr = r->reg_num;
1870
1871 if (r->reg_flags & RegRex)
1872 nr += 8;
1873
1874 return nr;
1875}
1876
252b5132 1877static INLINE unsigned int
40fb9820 1878mode_from_disp_size (i386_operand_type t)
252b5132 1879{
43234a1e 1880 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1881 return 1;
1882 else if (t.bitfield.disp16
1883 || t.bitfield.disp32
1884 || t.bitfield.disp32s)
1885 return 2;
1886 else
1887 return 0;
252b5132
RH		 1888}
1889
1890static INLINE int
65879393 1891fits_in_signed_byte (addressT num)
252b5132 1892{
65879393 1893 return num + 0x80 <= 0xff;
47926f60 1894}
252b5132
RH		 1895
1896static INLINE int
65879393 1897fits_in_unsigned_byte (addressT num)
252b5132 1898{
65879393 1899 return num <= 0xff;
47926f60 1900}
252b5132
RH		 1901
1902static INLINE int
65879393 1903fits_in_unsigned_word (addressT num)
252b5132 1904{
65879393 1905 return num <= 0xffff;
47926f60 1906}
252b5132
RH		 1907
1908static INLINE int
65879393 1909fits_in_signed_word (addressT num)
252b5132 1910{
65879393 1911 return num + 0x8000 <= 0xffff;
47926f60 1912}
2a962e6d 1913
3e73aa7c 1914static INLINE int
65879393 1915fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1916{
1917#ifndef BFD64
1918 return 1;
1919#else
65879393 1920 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1921#endif
1922} /* fits_in_signed_long() */
2a962e6d 1923
3e73aa7c 1924static INLINE int
65879393 1925fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1926{
1927#ifndef BFD64
1928 return 1;
1929#else
65879393 1930 return num <= 0xffffffff;
3e73aa7c
JH		 1931#endif
1932} /* fits_in_unsigned_long() */
252b5132 1933
43234a1e
L		 1934static INLINE int
1935fits_in_vec_disp8 (offsetT num)
1936{
1937 int shift = i.memshift;
1938 unsigned int mask;
1939
1940 if (shift == -1)
1941 abort ();
1942
1943 mask = (1 << shift) - 1;
1944
1945 /* Return 0 if NUM isn't properly aligned. */
1946 if ((num & mask))
1947 return 0;
1948
1949 /* Check if NUM will fit in 8bit after shift. */
1950 return fits_in_signed_byte (num >> shift);
1951}
1952
a683cc34
SP		 1953static INLINE int
1954fits_in_imm4 (offsetT num)
1955{
1956 return (num & 0xf) == num;
1957}
1958
40fb9820 1959static i386_operand_type
e3bb37b5 1960smallest_imm_type (offsetT num)
252b5132 1961{
40fb9820 1962 i386_operand_type t;
7ab9ffdd 1963
0dfbf9d7 1964 operand_type_set (&t, 0);
40fb9820
L		 1965 t.bitfield.imm64 = 1;
1966
1967 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1968 {
1969 /* This code is disabled on the 486 because all the Imm1 forms
1970 in the opcode table are slower on the i486. They're the
1971 versions with the implicitly specified single-position
1972 displacement, which has another syntax if you really want to
1973 use that form. */
40fb9820
L		 1974 t.bitfield.imm1 = 1;
1975 t.bitfield.imm8 = 1;
1976 t.bitfield.imm8s = 1;
1977 t.bitfield.imm16 = 1;
1978 t.bitfield.imm32 = 1;
1979 t.bitfield.imm32s = 1;
1980 }
1981 else if (fits_in_signed_byte (num))
1982 {
1983 t.bitfield.imm8 = 1;
1984 t.bitfield.imm8s = 1;
1985 t.bitfield.imm16 = 1;
1986 t.bitfield.imm32 = 1;
1987 t.bitfield.imm32s = 1;
1988 }
1989 else if (fits_in_unsigned_byte (num))
1990 {
1991 t.bitfield.imm8 = 1;
1992 t.bitfield.imm16 = 1;
1993 t.bitfield.imm32 = 1;
1994 t.bitfield.imm32s = 1;
1995 }
1996 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1997 {
1998 t.bitfield.imm16 = 1;
1999 t.bitfield.imm32 = 1;
2000 t.bitfield.imm32s = 1;
2001 }
2002 else if (fits_in_signed_long (num))
2003 {
2004 t.bitfield.imm32 = 1;
2005 t.bitfield.imm32s = 1;
2006 }
2007 else if (fits_in_unsigned_long (num))
2008 t.bitfield.imm32 = 1;
2009
2010 return t;
47926f60 2011}
252b5132 2012
847f7ad4 2013static offsetT
e3bb37b5 2014offset_in_range (offsetT val, int size)
847f7ad4 2015{
508866be 2016 addressT mask;
ba2adb93 2017
847f7ad4
AM		 2018 switch (size)
2019 {
508866be
L		 2020 case 1: mask = ((addressT) 1 << 8) - 1; break;
2021 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2022 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2023#ifdef BFD64
2024 case 8: mask = ((addressT) 2 << 63) - 1; break;
2025#endif
47926f60 2026 default: abort ();
847f7ad4
AM		 2027 }
2028
9de868bf
L		 2029#ifdef BFD64
2030 /* If BFD64, sign extend val for 32bit address mode. */
2031 if (flag_code != CODE_64BIT
2032 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2033 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2034 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2035#endif
ba2adb93 2036
47926f60 2037 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2038 {
2039 char buf1[40], buf2[40];
2040
2041 sprint_value (buf1, val);
2042 sprint_value (buf2, val & mask);
2043 as_warn (_("%s shortened to %s"), buf1, buf2);
2044 }
2045 return val & mask;
2046}
2047
c32fa91d
L		 2048enum PREFIX_GROUP
2049{
2050 PREFIX_EXIST = 0,
2051 PREFIX_LOCK,
2052 PREFIX_REP,
2053 PREFIX_OTHER
2054};
2055
2056/* Returns
2057 a. PREFIX_EXIST if attempting to add a prefix where one from the
2058 same class already exists.
2059 b. PREFIX_LOCK if lock prefix is added.
2060 c. PREFIX_REP if rep/repne prefix is added.
2061 d. PREFIX_OTHER if other prefix is added.
2062 */
2063
2064static enum PREFIX_GROUP
e3bb37b5 2065add_prefix (unsigned int prefix)
252b5132 2066{
c32fa91d 2067 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2068 unsigned int q;
252b5132 2069
29b0f896
AM		 2070 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2071 && flag_code == CODE_64BIT)
b1905489 2072 {
161a04f6
L		 2073 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2074 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2075 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2076 ret = PREFIX_EXIST;
b1905489
JB		 2077 q = REX_PREFIX;
2078 }
3e73aa7c 2079 else
b1905489
JB		 2080 {
2081 switch (prefix)
2082 {
2083 default:
2084 abort ();
2085
2086 case CS_PREFIX_OPCODE:
2087 case DS_PREFIX_OPCODE:
2088 case ES_PREFIX_OPCODE:
2089 case FS_PREFIX_OPCODE:
2090 case GS_PREFIX_OPCODE:
2091 case SS_PREFIX_OPCODE:
2092 q = SEG_PREFIX;
2093 break;
2094
2095 case REPNE_PREFIX_OPCODE:
2096 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2097 q = REP_PREFIX;
2098 ret = PREFIX_REP;
2099 break;
2100
b1905489 2101 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2102 q = LOCK_PREFIX;
2103 ret = PREFIX_LOCK;
b1905489
JB		 2104 break;
2105
2106 case FWAIT_OPCODE:
2107 q = WAIT_PREFIX;
2108 break;
2109
2110 case ADDR_PREFIX_OPCODE:
2111 q = ADDR_PREFIX;
2112 break;
2113
2114 case DATA_PREFIX_OPCODE:
2115 q = DATA_PREFIX;
2116 break;
2117 }
2118 if (i.prefix[q] != 0)
c32fa91d 2119 ret = PREFIX_EXIST;
b1905489 2120 }
252b5132 2121
b1905489 2122 if (ret)
252b5132 2123 {
b1905489
JB		 2124 if (!i.prefix[q])
2125 ++i.prefixes;
2126 i.prefix[q] |= prefix;
252b5132 2127 }
b1905489
JB		 2128 else
2129 as_bad (_("same type of prefix used twice"));
252b5132 2130
252b5132
RH		 2131 return ret;
2132}
2133
2134static void
78f12dd3 2135update_code_flag (int value, int check)
eecb386c 2136{
78f12dd3
L		 2137 PRINTF_LIKE ((*as_error));
2138
1e9cc1c2 2139 flag_code = (enum flag_code) value;
40fb9820
L		 2140 if (flag_code == CODE_64BIT)
2141 {
2142 cpu_arch_flags.bitfield.cpu64 = 1;
2143 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2144 }
2145 else
2146 {
2147 cpu_arch_flags.bitfield.cpu64 = 0;
2148 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2149 }
2150 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2151 {
78f12dd3
L		 2152 if (check)
2153 as_error = as_fatal;
2154 else
2155 as_error = as_bad;
2156 (*as_error) (_("64bit mode not supported on `%s'."),
2157 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2158 }
40fb9820 2159 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2160 {
78f12dd3
L		 2161 if (check)
2162 as_error = as_fatal;
2163 else
2164 as_error = as_bad;
2165 (*as_error) (_("32bit mode not supported on `%s'."),
2166 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2167 }
eecb386c
AM		 2168 stackop_size = '\0';
2169}
2170
78f12dd3
L		 2171static void
2172set_code_flag (int value)
2173{
2174 update_code_flag (value, 0);
2175}
2176
eecb386c 2177static void
e3bb37b5 2178set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2179{
1e9cc1c2 2180 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2181 if (flag_code != CODE_16BIT)
2182 abort ();
2183 cpu_arch_flags.bitfield.cpu64 = 0;
2184 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2185 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2186}
2187
2188static void
e3bb37b5 2189set_intel_syntax (int syntax_flag)
252b5132
RH		 2190{
2191 /* Find out if register prefixing is specified. */
2192 int ask_naked_reg = 0;
2193
2194 SKIP_WHITESPACE ();
29b0f896 2195 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2196 {
d02603dc
NC		 2197 char *string;
2198 int e = get_symbol_name (&string);
252b5132 2199
47926f60 2200 if (strcmp (string, "prefix") == 0)
252b5132 2201 ask_naked_reg = 1;
47926f60 2202 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2203 ask_naked_reg = -1;
2204 else
d0b47220 2205 as_bad (_("bad argument to syntax directive."));
d02603dc 2206 (void) restore_line_pointer (e);
252b5132
RH		 2207 }
2208 demand_empty_rest_of_line ();
c3332e24 2209
252b5132
RH		 2210 intel_syntax = syntax_flag;
2211
2212 if (ask_naked_reg == 0)
f86103b7
AM		 2213 allow_naked_reg = (intel_syntax
2214 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2215 else
2216 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2217
ee86248c 2218 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2219
e4a3b5a4 2220 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2221 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2222 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2223}
2224
1efbbeb4
L		 2225static void
2226set_intel_mnemonic (int mnemonic_flag)
2227{
e1d4d893 2228 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2229}
2230
db51cc60
L		 2231static void
2232set_allow_index_reg (int flag)
2233{
2234 allow_index_reg = flag;
2235}
2236
cb19c032 2237static void
7bab8ab5 2238set_check (int what)
cb19c032 2239{
7bab8ab5
JB		 2240 enum check_kind *kind;
2241 const char *str;
2242
2243 if (what)
2244 {
2245 kind = &operand_check;
2246 str = "operand";
2247 }
2248 else
2249 {
2250 kind = &sse_check;
2251 str = "sse";
2252 }
2253
cb19c032
L		 2254 SKIP_WHITESPACE ();
2255
2256 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2257 {
d02603dc
NC		 2258 char *string;
2259 int e = get_symbol_name (&string);
cb19c032
L		 2260
2261 if (strcmp (string, "none") == 0)
7bab8ab5 2262 *kind = check_none;
cb19c032 2263 else if (strcmp (string, "warning") == 0)
7bab8ab5 2264 *kind = check_warning;
cb19c032 2265 else if (strcmp (string, "error") == 0)
7bab8ab5 2266 *kind = check_error;
cb19c032 2267 else
7bab8ab5 2268 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2269 (void) restore_line_pointer (e);
cb19c032
L		 2270 }
2271 else
7bab8ab5 2272 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2273
2274 demand_empty_rest_of_line ();
2275}
2276
8a9036a4
L		 2277static void
2278check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2279 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2280{
2281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2282 static const char *arch;
2283
2284 /* Intel LIOM is only supported on ELF. */
2285 if (!IS_ELF)
2286 return;
2287
2288 if (!arch)
2289 {
2290 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2291 use default_arch. */
2292 arch = cpu_arch_name;
2293 if (!arch)
2294 arch = default_arch;
2295 }
2296
81486035
L		 2297 /* If we are targeting Intel MCU, we must enable it. */
2298 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2299 || new_flag.bitfield.cpuiamcu)
2300 return;
2301
3632d14b 2302 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2303 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2304 || new_flag.bitfield.cpul1om)
8a9036a4 2305 return;
76ba9986 2306
7a9068fe
L		 2307 /* If we are targeting Intel K1OM, we must enable it. */
2308 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2309 || new_flag.bitfield.cpuk1om)
2310 return;
2311
8a9036a4
L		 2312 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2313#endif
2314}
2315
e413e4e9 2316static void
e3bb37b5 2317set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2318{
47926f60 2319 SKIP_WHITESPACE ();
e413e4e9 2320
29b0f896 2321 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2322 {
d02603dc
NC		 2323 char *string;
2324 int e = get_symbol_name (&string);
91d6fa6a 2325 unsigned int j;
40fb9820 2326 i386_cpu_flags flags;
e413e4e9 2327
91d6fa6a 2328 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2329 {
91d6fa6a 2330 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2331 {
91d6fa6a 2332 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2333
5c6af06e
JB		 2334 if (*string != '.')
2335 {
91d6fa6a 2336 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2337 cpu_sub_arch_name = NULL;
91d6fa6a 2338 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2339 if (flag_code == CODE_64BIT)
2340 {
2341 cpu_arch_flags.bitfield.cpu64 = 1;
2342 cpu_arch_flags.bitfield.cpuno64 = 0;
2343 }
2344 else
2345 {
2346 cpu_arch_flags.bitfield.cpu64 = 0;
2347 cpu_arch_flags.bitfield.cpuno64 = 1;
2348 }
91d6fa6a
NC		 2349 cpu_arch_isa = cpu_arch[j].type;
2350 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2351 if (!cpu_arch_tune_set)
2352 {
2353 cpu_arch_tune = cpu_arch_isa;
2354 cpu_arch_tune_flags = cpu_arch_isa_flags;
2355 }
5c6af06e
JB		 2356 break;
2357 }
40fb9820 2358
22109423 2359 if (!cpu_arch[j].negated)
309d3373 2360 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2361 cpu_arch[j].flags);
309d3373
JB		 2362 else
2363 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2364 cpu_arch[j].flags);
81486035
L		 2365
2366 if (!valid_iamcu_cpu_flags (&flags))
2367 as_fatal (_("`%s' isn't valid for Intel MCU"),
2368 cpu_arch[j].name);
2369 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2370 {
6305a203
L		 2371 if (cpu_sub_arch_name)
2372 {
2373 char *name = cpu_sub_arch_name;
2374 cpu_sub_arch_name = concat (name,
91d6fa6a 2375 cpu_arch[j].name,
1bf57e9f 2376 (const char *) NULL);
6305a203
L		 2377 free (name);
2378 }
2379 else
91d6fa6a 2380 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2381 cpu_arch_flags = flags;
a586129e 2382 cpu_arch_isa_flags = flags;
5c6af06e 2383 }
d02603dc 2384 (void) restore_line_pointer (e);
5c6af06e
JB		 2385 demand_empty_rest_of_line ();
2386 return;
e413e4e9
AM		 2387 }
2388 }
91d6fa6a 2389 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2390 as_bad (_("no such architecture: `%s'"), string);
2391
2392 *input_line_pointer = e;
2393 }
2394 else
2395 as_bad (_("missing cpu architecture"));
2396
fddf5b5b
AM		 2397 no_cond_jump_promotion = 0;
2398 if (*input_line_pointer == ','
29b0f896 2399 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2400 {
d02603dc
NC		 2401 char *string;
2402 char e;
2403
2404 ++input_line_pointer;
2405 e = get_symbol_name (&string);
fddf5b5b
AM		 2406
2407 if (strcmp (string, "nojumps") == 0)
2408 no_cond_jump_promotion = 1;
2409 else if (strcmp (string, "jumps") == 0)
2410 ;
2411 else
2412 as_bad (_("no such architecture modifier: `%s'"), string);
2413
d02603dc 2414 (void) restore_line_pointer (e);
fddf5b5b
AM		 2415 }
2416
e413e4e9
AM		 2417 demand_empty_rest_of_line ();
2418}
2419
8a9036a4
L		 2420enum bfd_architecture
2421i386_arch (void)
2422{
3632d14b 2423 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2424 {
2425 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2426 || flag_code != CODE_64BIT)
2427 as_fatal (_("Intel L1OM is 64bit ELF only"));
2428 return bfd_arch_l1om;
2429 }
7a9068fe
L		 2430 else if (cpu_arch_isa == PROCESSOR_K1OM)
2431 {
2432 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2433 || flag_code != CODE_64BIT)
2434 as_fatal (_("Intel K1OM is 64bit ELF only"));
2435 return bfd_arch_k1om;
2436 }
81486035
L		 2437 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2438 {
2439 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2440 || flag_code == CODE_64BIT)
2441 as_fatal (_("Intel MCU is 32bit ELF only"));
2442 return bfd_arch_iamcu;
2443 }
8a9036a4
L		 2444 else
2445 return bfd_arch_i386;
2446}
2447
b9d79e03 2448unsigned long
7016a5d5 2449i386_mach (void)
b9d79e03 2450{
351f65ca 2451 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2452 {
3632d14b 2453 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2454 {
351f65ca
L		 2455 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2456 || default_arch[6] != '\0')
8a9036a4
L		 2457 as_fatal (_("Intel L1OM is 64bit ELF only"));
2458 return bfd_mach_l1om;
2459 }
7a9068fe
L		 2460 else if (cpu_arch_isa == PROCESSOR_K1OM)
2461 {
2462 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2463 || default_arch[6] != '\0')
2464 as_fatal (_("Intel K1OM is 64bit ELF only"));
2465 return bfd_mach_k1om;
2466 }
351f65ca 2467 else if (default_arch[6] == '\0')
8a9036a4 2468 return bfd_mach_x86_64;
351f65ca
L		 2469 else
2470 return bfd_mach_x64_32;
8a9036a4 2471 }
5197d474
L		 2472 else if (!strcmp (default_arch, "i386")
2473 || !strcmp (default_arch, "iamcu"))
81486035
L		 2474 {
2475 if (cpu_arch_isa == PROCESSOR_IAMCU)
2476 {
2477 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2478 as_fatal (_("Intel MCU is 32bit ELF only"));
2479 return bfd_mach_i386_iamcu;
2480 }
2481 else
2482 return bfd_mach_i386_i386;
2483 }
b9d79e03 2484 else
2b5d6a91 2485 as_fatal (_("unknown architecture"));
b9d79e03 2486}
b9d79e03 2487\f
252b5132 2488void
7016a5d5 2489md_begin (void)
252b5132
RH		 2490{
2491 const char *hash_err;
2492
47926f60 2493 /* Initialize op_hash hash table. */
252b5132
RH		 2494 op_hash = hash_new ();
2495
2496 {
d3ce72d0 2497 const insn_template *optab;
29b0f896 2498 templates *core_optab;
252b5132 2499
47926f60
KH		 2500 /* Setup for loop. */
2501 optab = i386_optab;
252b5132
RH		 2502 core_optab = (templates *) xmalloc (sizeof (templates));
2503 core_optab->start = optab;
2504
2505 while (1)
2506 {
2507 ++optab;
2508 if (optab->name == NULL
2509 || strcmp (optab->name, (optab - 1)->name) != 0)
2510 {
2511 /* different name --> ship out current template list;
47926f60 2512 add to hash table; & begin anew. */
252b5132
RH		 2513 core_optab->end = optab;
2514 hash_err = hash_insert (op_hash,
2515 (optab - 1)->name,
5a49b8ac 2516 (void *) core_optab);
252b5132
RH		 2517 if (hash_err)
2518 {
b37df7c4 2519 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2520 (optab - 1)->name,
2521 hash_err);
2522 }
2523 if (optab->name == NULL)
2524 break;
2525 core_optab = (templates *) xmalloc (sizeof (templates));
2526 core_optab->start = optab;
2527 }
2528 }
2529 }
2530
47926f60 2531 /* Initialize reg_hash hash table. */
252b5132
RH		 2532 reg_hash = hash_new ();
2533 {
29b0f896 2534 const reg_entry *regtab;
c3fe08fa 2535 unsigned int regtab_size = i386_regtab_size;
252b5132 2536
c3fe08fa 2537 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2538 {
5a49b8ac 2539 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2540 if (hash_err)
b37df7c4 2541 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2542 regtab->reg_name,
2543 hash_err);
252b5132
RH		 2544 }
2545 }
2546
47926f60 2547 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2548 {
29b0f896
AM		 2549 int c;
2550 char *p;
252b5132
RH		 2551
2552 for (c = 0; c < 256; c++)
2553 {
3882b010 2554 if (ISDIGIT (c))
252b5132
RH		 2555 {
2556 digit_chars[c] = c;
2557 mnemonic_chars[c] = c;
2558 register_chars[c] = c;
2559 operand_chars[c] = c;
2560 }
3882b010 2561 else if (ISLOWER (c))
252b5132
RH		 2562 {
2563 mnemonic_chars[c] = c;
2564 register_chars[c] = c;
2565 operand_chars[c] = c;
2566 }
3882b010 2567 else if (ISUPPER (c))
252b5132 2568 {
3882b010 2569 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2570 register_chars[c] = mnemonic_chars[c];
2571 operand_chars[c] = c;
2572 }
43234a1e
L		 2573 else if (c == '{' || c == '}')
2574 operand_chars[c] = c;
252b5132 2575
3882b010 2576 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2577 identifier_chars[c] = c;
2578 else if (c >= 128)
2579 {
2580 identifier_chars[c] = c;
2581 operand_chars[c] = c;
2582 }
2583 }
2584
2585#ifdef LEX_AT
2586 identifier_chars['@'] = '@';
32137342
NC		 2587#endif
2588#ifdef LEX_QM
2589 identifier_chars['?'] = '?';
2590 operand_chars['?'] = '?';
252b5132 2591#endif
252b5132 2592 digit_chars['-'] = '-';
c0f3af97 2593 mnemonic_chars['_'] = '_';
791fe849 2594 mnemonic_chars['-'] = '-';
0003779b 2595 mnemonic_chars['.'] = '.';
252b5132
RH		 2596 identifier_chars['_'] = '_';
2597 identifier_chars['.'] = '.';
2598
2599 for (p = operand_special_chars; *p != '\0'; p++)
2600 operand_chars[(unsigned char) *p] = *p;
2601 }
2602
a4447b93
RH		 2603 if (flag_code == CODE_64BIT)
2604 {
ca19b261
KT		 2605#if defined (OBJ_COFF) && defined (TE_PE)
2606 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2607 ? 32 : 16);
2608#else
a4447b93 2609 x86_dwarf2_return_column = 16;
ca19b261 2610#endif
61ff971f 2611 x86_cie_data_alignment = -8;
a4447b93
RH		 2612 }
2613 else
2614 {
2615 x86_dwarf2_return_column = 8;
2616 x86_cie_data_alignment = -4;
2617 }
252b5132
RH		 2618}
2619
2620void
e3bb37b5 2621i386_print_statistics (FILE *file)
252b5132
RH		 2622{
2623 hash_print_statistics (file, "i386 opcode", op_hash);
2624 hash_print_statistics (file, "i386 register", reg_hash);
2625}
2626\f
252b5132
RH		 2627#ifdef DEBUG386
2628
ce8a8b2f 2629/* Debugging routines for md_assemble. */
d3ce72d0 2630static void pte (insn_template *);
40fb9820 2631static void pt (i386_operand_type);
e3bb37b5
L		 2632static void pe (expressionS *);
2633static void ps (symbolS *);
252b5132
RH		 2634
2635static void
e3bb37b5 2636pi (char *line, i386_insn *x)
252b5132 2637{
09137c09 2638 unsigned int j;
252b5132
RH		 2639
2640 fprintf (stdout, "%s: template ", line);
2641 pte (&x->tm);
09f131f2
JH		 2642 fprintf (stdout, " address: base %s index %s scale %x\n",
2643 x->base_reg ? x->base_reg->reg_name : "none",
2644 x->index_reg ? x->index_reg->reg_name : "none",
2645 x->log2_scale_factor);
2646 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2647 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2648 fprintf (stdout, " sib: base %x index %x scale %x\n",
2649 x->sib.base, x->sib.index, x->sib.scale);
2650 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2651 (x->rex & REX_W) != 0,
2652 (x->rex & REX_R) != 0,
2653 (x->rex & REX_X) != 0,
2654 (x->rex & REX_B) != 0);
09137c09 2655 for (j = 0; j < x->operands; j++)
252b5132 2656 {
09137c09
SP		 2657 fprintf (stdout, " #%d: ", j + 1);
2658 pt (x->types[j]);
252b5132 2659 fprintf (stdout, "\n");
09137c09
SP		 2660 if (x->types[j].bitfield.reg8
2661 || x->types[j].bitfield.reg16
2662 || x->types[j].bitfield.reg32
2663 || x->types[j].bitfield.reg64
2664 || x->types[j].bitfield.regmmx
2665 || x->types[j].bitfield.regxmm
2666 || x->types[j].bitfield.regymm
43234a1e 2667 || x->types[j].bitfield.regzmm
09137c09
SP		 2668 || x->types[j].bitfield.sreg2
2669 || x->types[j].bitfield.sreg3
2670 || x->types[j].bitfield.control
2671 || x->types[j].bitfield.debug
2672 || x->types[j].bitfield.test)
2673 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2674 if (operand_type_check (x->types[j], imm))
2675 pe (x->op[j].imms);
2676 if (operand_type_check (x->types[j], disp))
2677 pe (x->op[j].disps);
252b5132
RH		 2678 }
2679}
2680
2681static void
d3ce72d0 2682pte (insn_template *t)
252b5132 2683{
09137c09 2684 unsigned int j;
252b5132 2685 fprintf (stdout, " %d operands ", t->operands);
47926f60 2686 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2687 if (t->extension_opcode != None)
2688 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2689 if (t->opcode_modifier.d)
252b5132 2690 fprintf (stdout, "D");
40fb9820 2691 if (t->opcode_modifier.w)
252b5132
RH		 2692 fprintf (stdout, "W");
2693 fprintf (stdout, "\n");
09137c09 2694 for (j = 0; j < t->operands; j++)
252b5132 2695 {
09137c09
SP		 2696 fprintf (stdout, " #%d type ", j + 1);
2697 pt (t->operand_types[j]);
252b5132
RH		 2698 fprintf (stdout, "\n");
2699 }
2700}
2701
2702static void
e3bb37b5 2703pe (expressionS *e)
252b5132 2704{
24eab124 2705 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2706 fprintf (stdout, " add_number %ld (%lx)\n",
2707 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2708 if (e->X_add_symbol)
2709 {
2710 fprintf (stdout, " add_symbol ");
2711 ps (e->X_add_symbol);
2712 fprintf (stdout, "\n");
2713 }
2714 if (e->X_op_symbol)
2715 {
2716 fprintf (stdout, " op_symbol ");
2717 ps (e->X_op_symbol);
2718 fprintf (stdout, "\n");
2719 }
2720}
2721
2722static void
e3bb37b5 2723ps (symbolS *s)
252b5132
RH		 2724{
2725 fprintf (stdout, "%s type %s%s",
2726 S_GET_NAME (s),
2727 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2728 segment_name (S_GET_SEGMENT (s)));
2729}
2730
7b81dfbb 2731static struct type_name
252b5132 2732 {
40fb9820
L		 2733 i386_operand_type mask;
2734 const char *name;
252b5132 2735 }
7b81dfbb 2736const type_names[] =
252b5132 2737{
40fb9820
L		 2738 { OPERAND_TYPE_REG8, "r8" },
2739 { OPERAND_TYPE_REG16, "r16" },
2740 { OPERAND_TYPE_REG32, "r32" },
2741 { OPERAND_TYPE_REG64, "r64" },
2742 { OPERAND_TYPE_IMM8, "i8" },
2743 { OPERAND_TYPE_IMM8, "i8s" },
2744 { OPERAND_TYPE_IMM16, "i16" },
2745 { OPERAND_TYPE_IMM32, "i32" },
2746 { OPERAND_TYPE_IMM32S, "i32s" },
2747 { OPERAND_TYPE_IMM64, "i64" },
2748 { OPERAND_TYPE_IMM1, "i1" },
2749 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2750 { OPERAND_TYPE_DISP8, "d8" },
2751 { OPERAND_TYPE_DISP16, "d16" },
2752 { OPERAND_TYPE_DISP32, "d32" },
2753 { OPERAND_TYPE_DISP32S, "d32s" },
2754 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2755 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2756 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2757 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2758 { OPERAND_TYPE_CONTROL, "control reg" },
2759 { OPERAND_TYPE_TEST, "test reg" },
2760 { OPERAND_TYPE_DEBUG, "debug reg" },
2761 { OPERAND_TYPE_FLOATREG, "FReg" },
2762 { OPERAND_TYPE_FLOATACC, "FAcc" },
2763 { OPERAND_TYPE_SREG2, "SReg2" },
2764 { OPERAND_TYPE_SREG3, "SReg3" },
2765 { OPERAND_TYPE_ACC, "Acc" },
2766 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2767 { OPERAND_TYPE_REGMMX, "rMMX" },
2768 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2769 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2770 { OPERAND_TYPE_REGZMM, "rZMM" },
2771 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2772 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2773};
2774
2775static void
40fb9820 2776pt (i386_operand_type t)
252b5132 2777{
40fb9820 2778 unsigned int j;
c6fb90c8 2779 i386_operand_type a;
252b5132 2780
40fb9820 2781 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2782 {
2783 a = operand_type_and (t, type_names[j].mask);
0349dc08 2784 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2785 fprintf (stdout, "%s, ", type_names[j].name);
2786 }
252b5132
RH		 2787 fflush (stdout);
2788}
2789
2790#endif /* DEBUG386 */
2791\f
252b5132 2792static bfd_reloc_code_real_type
3956db08 2793reloc (unsigned int size,
64e74474
AM		 2794 int pcrel,
2795 int sign,
2796 bfd_reloc_code_real_type other)
252b5132 2797{
47926f60 2798 if (other != NO_RELOC)
3956db08 2799 {
91d6fa6a 2800 reloc_howto_type *rel;
3956db08
JB		 2801
2802 if (size == 8)
2803 switch (other)
2804 {
64e74474
AM		 2805 case BFD_RELOC_X86_64_GOT32:
2806 return BFD_RELOC_X86_64_GOT64;
2807 break;
553d1284
L		 2808 case BFD_RELOC_X86_64_GOTPLT64:
2809 return BFD_RELOC_X86_64_GOTPLT64;
2810 break;
64e74474
AM		 2811 case BFD_RELOC_X86_64_PLTOFF64:
2812 return BFD_RELOC_X86_64_PLTOFF64;
2813 break;
2814 case BFD_RELOC_X86_64_GOTPC32:
2815 other = BFD_RELOC_X86_64_GOTPC64;
2816 break;
2817 case BFD_RELOC_X86_64_GOTPCREL:
2818 other = BFD_RELOC_X86_64_GOTPCREL64;
2819 break;
2820 case BFD_RELOC_X86_64_TPOFF32:
2821 other = BFD_RELOC_X86_64_TPOFF64;
2822 break;
2823 case BFD_RELOC_X86_64_DTPOFF32:
2824 other = BFD_RELOC_X86_64_DTPOFF64;
2825 break;
2826 default:
2827 break;
3956db08 2828 }
e05278af 2829
8ce3d284 2830#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2831 if (other == BFD_RELOC_SIZE32)
2832 {
2833 if (size == 8)
1ab668bf 2834 other = BFD_RELOC_SIZE64;
8fd4256d 2835 if (pcrel)
1ab668bf
AM		 2836 {
2837 as_bad (_("there are no pc-relative size relocations"));
2838 return NO_RELOC;
2839 }
8fd4256d 2840 }
8ce3d284 2841#endif
8fd4256d 2842
e05278af 2843 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2844 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2845 sign = -1;
2846
91d6fa6a
NC		 2847 rel = bfd_reloc_type_lookup (stdoutput, other);
2848 if (!rel)
3956db08 2849 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2850 else if (size != bfd_get_reloc_size (rel))
3956db08 2851 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2852 bfd_get_reloc_size (rel),
3956db08 2853 size);
91d6fa6a 2854 else if (pcrel && !rel->pc_relative)
3956db08 2855 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2856 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2857 && !sign)
91d6fa6a 2858 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2859 && sign > 0))
3956db08
JB		 2860 as_bad (_("relocated field and relocation type differ in signedness"));
2861 else
2862 return other;
2863 return NO_RELOC;
2864 }
252b5132
RH		 2865
2866 if (pcrel)
2867 {
3e73aa7c 2868 if (!sign)
3956db08 2869 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2870 switch (size)
2871 {
2872 case 1: return BFD_RELOC_8_PCREL;
2873 case 2: return BFD_RELOC_16_PCREL;
d258b828 2874 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2875 case 8: return BFD_RELOC_64_PCREL;
252b5132 2876 }
3956db08 2877 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2878 }
2879 else
2880 {
3956db08 2881 if (sign > 0)
e5cb08ac 2882 switch (size)
3e73aa7c
JH		 2883 {
2884 case 4: return BFD_RELOC_X86_64_32S;
2885 }
2886 else
2887 switch (size)
2888 {
2889 case 1: return BFD_RELOC_8;
2890 case 2: return BFD_RELOC_16;
2891 case 4: return BFD_RELOC_32;
2892 case 8: return BFD_RELOC_64;
2893 }
3956db08
JB		 2894 as_bad (_("cannot do %s %u byte relocation"),
2895 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2896 }
2897
0cc9e1d3 2898 return NO_RELOC;
252b5132
RH		 2899}
2900
47926f60
KH		 2901/* Here we decide which fixups can be adjusted to make them relative to
2902 the beginning of the section instead of the symbol. Basically we need
2903 to make sure that the dynamic relocations are done correctly, so in
2904 some cases we force the original symbol to be used. */
2905
252b5132 2906int
e3bb37b5 2907tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2908{
6d249963 2909#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2910 if (!IS_ELF)
31312f95
AM		 2911 return 1;
2912
a161fe53
AM		 2913 /* Don't adjust pc-relative references to merge sections in 64-bit
2914 mode. */
2915 if (use_rela_relocations
2916 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2917 && fixP->fx_pcrel)
252b5132 2918 return 0;
31312f95 2919
8d01d9a9
AJ		 2920 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2921 and changed later by validate_fix. */
2922 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2923 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2924 return 0;
2925
8fd4256d
L		 2926 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2927 for size relocations. */
2928 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2929 || fixP->fx_r_type == BFD_RELOC_SIZE64
2930 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2931 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2932 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2933 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2945 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2946 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 2949 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2952 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2955 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2958 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2959 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2960 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2961 return 0;
31312f95 2962#endif
252b5132
RH		 2963 return 1;
2964}
252b5132 2965
b4cac588 2966static int
e3bb37b5 2967intel_float_operand (const char *mnemonic)
252b5132 2968{
9306ca4a
JB		 2969 /* Note that the value returned is meaningful only for opcodes with (memory)
2970 operands, hence the code here is free to improperly handle opcodes that
2971 have no operands (for better performance and smaller code). */
2972
2973 if (mnemonic[0] != 'f')
2974 return 0; /* non-math */
2975
2976 switch (mnemonic[1])
2977 {
2978 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2979 the fs segment override prefix not currently handled because no
2980 call path can make opcodes without operands get here */
2981 case 'i':
2982 return 2 /* integer op */;
2983 case 'l':
2984 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2985 return 3; /* fldcw/fldenv */
2986 break;
2987 case 'n':
2988 if (mnemonic[2] != 'o' /* fnop */)
2989 return 3; /* non-waiting control op */
2990 break;
2991 case 'r':
2992 if (mnemonic[2] == 's')
2993 return 3; /* frstor/frstpm */
2994 break;
2995 case 's':
2996 if (mnemonic[2] == 'a')
2997 return 3; /* fsave */
2998 if (mnemonic[2] == 't')
2999 {
3000 switch (mnemonic[3])
3001 {
3002 case 'c': /* fstcw */
3003 case 'd': /* fstdw */
3004 case 'e': /* fstenv */
3005 case 's': /* fsts[gw] */
3006 return 3;
3007 }
3008 }
3009 break;
3010 case 'x':
3011 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3012 return 0; /* fxsave/fxrstor are not really math ops */
3013 break;
3014 }
252b5132 3015
9306ca4a 3016 return 1;
252b5132
RH		 3017}
3018
c0f3af97
L		 3019/* Build the VEX prefix. */
3020
3021static void
d3ce72d0 3022build_vex_prefix (const insn_template *t)
c0f3af97
L		 3023{
3024 unsigned int register_specifier;
3025 unsigned int implied_prefix;
3026 unsigned int vector_length;
3027
3028 /* Check register specifier. */
3029 if (i.vex.register_specifier)
43234a1e
L		 3030 {
3031 register_specifier =
3032 ~register_number (i.vex.register_specifier) & 0xf;
3033 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3034 }
c0f3af97
L		 3035 else
3036 register_specifier = 0xf;
3037
fa99fab2
L		 3038 /* Use 2-byte VEX prefix by swappping destination and source
3039 operand. */
3040 if (!i.swap_operand
3041 && i.operands == i.reg_operands
7f399153 3042 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3043 && i.tm.opcode_modifier.s
3044 && i.rex == REX_B)
3045 {
3046 unsigned int xchg = i.operands - 1;
3047 union i386_op temp_op;
3048 i386_operand_type temp_type;
3049
3050 temp_type = i.types[xchg];
3051 i.types[xchg] = i.types[0];
3052 i.types[0] = temp_type;
3053 temp_op = i.op[xchg];
3054 i.op[xchg] = i.op[0];
3055 i.op[0] = temp_op;
3056
9c2799c2 3057 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3058
3059 i.rex = REX_R;
3060 xchg = i.rm.regmem;
3061 i.rm.regmem = i.rm.reg;
3062 i.rm.reg = xchg;
3063
3064 /* Use the next insn. */
3065 i.tm = t[1];
3066 }
3067
539f890d
L		 3068 if (i.tm.opcode_modifier.vex == VEXScalar)
3069 vector_length = avxscalar;
3070 else
3071 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3072
3073 switch ((i.tm.base_opcode >> 8) & 0xff)
3074 {
3075 case 0:
3076 implied_prefix = 0;
3077 break;
3078 case DATA_PREFIX_OPCODE:
3079 implied_prefix = 1;
3080 break;
3081 case REPE_PREFIX_OPCODE:
3082 implied_prefix = 2;
3083 break;
3084 case REPNE_PREFIX_OPCODE:
3085 implied_prefix = 3;
3086 break;
3087 default:
3088 abort ();
3089 }
3090
3091 /* Use 2-byte VEX prefix if possible. */
7f399153 3092 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3093 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3094 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3095 {
3096 /* 2-byte VEX prefix. */
3097 unsigned int r;
3098
3099 i.vex.length = 2;
3100 i.vex.bytes[0] = 0xc5;
3101
3102 /* Check the REX.R bit. */
3103 r = (i.rex & REX_R) ? 0 : 1;
3104 i.vex.bytes[1] = (r << 7
3105 | register_specifier << 3
3106 | vector_length << 2
3107 | implied_prefix);
3108 }
3109 else
3110 {
3111 /* 3-byte VEX prefix. */
3112 unsigned int m, w;
3113
f88c9eb0 3114 i.vex.length = 3;
f88c9eb0 3115
7f399153 3116 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3117 {
7f399153
L		 3118 case VEX0F:
3119 m = 0x1;
80de6e00 3120 i.vex.bytes[0] = 0xc4;
7f399153
L		 3121 break;
3122 case VEX0F38:
3123 m = 0x2;
80de6e00 3124 i.vex.bytes[0] = 0xc4;
7f399153
L		 3125 break;
3126 case VEX0F3A:
3127 m = 0x3;
80de6e00 3128 i.vex.bytes[0] = 0xc4;
7f399153
L		 3129 break;
3130 case XOP08:
5dd85c99
SP		 3131 m = 0x8;
3132 i.vex.bytes[0] = 0x8f;
7f399153
L		 3133 break;
3134 case XOP09:
f88c9eb0
SP		 3135 m = 0x9;
3136 i.vex.bytes[0] = 0x8f;
7f399153
L		 3137 break;
3138 case XOP0A:
f88c9eb0
SP		 3139 m = 0xa;
3140 i.vex.bytes[0] = 0x8f;
7f399153
L		 3141 break;
3142 default:
3143 abort ();
f88c9eb0 3144 }
c0f3af97 3145
c0f3af97
L		 3146 /* The high 3 bits of the second VEX byte are 1's compliment
3147 of RXB bits from REX. */
3148 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3149
3150 /* Check the REX.W bit. */
3151 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3152 if (i.tm.opcode_modifier.vexw == VEXW1)
3153 w = 1;
c0f3af97
L		 3154
3155 i.vex.bytes[2] = (w << 7
3156 | register_specifier << 3
3157 | vector_length << 2
3158 | implied_prefix);
3159 }
3160}
3161
43234a1e
L		 3162/* Build the EVEX prefix. */
3163
3164static void
3165build_evex_prefix (void)
3166{
3167 unsigned int register_specifier;
3168 unsigned int implied_prefix;
3169 unsigned int m, w;
3170 rex_byte vrex_used = 0;
3171
3172 /* Check register specifier. */
3173 if (i.vex.register_specifier)
3174 {
3175 gas_assert ((i.vrex & REX_X) == 0);
3176
3177 register_specifier = i.vex.register_specifier->reg_num;
3178 if ((i.vex.register_specifier->reg_flags & RegRex))
3179 register_specifier += 8;
3180 /* The upper 16 registers are encoded in the fourth byte of the
3181 EVEX prefix. */
3182 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3183 i.vex.bytes[3] = 0x8;
3184 register_specifier = ~register_specifier & 0xf;
3185 }
3186 else
3187 {
3188 register_specifier = 0xf;
3189
3190 /* Encode upper 16 vector index register in the fourth byte of
3191 the EVEX prefix. */
3192 if (!(i.vrex & REX_X))
3193 i.vex.bytes[3] = 0x8;
3194 else
3195 vrex_used |= REX_X;
3196 }
3197
3198 switch ((i.tm.base_opcode >> 8) & 0xff)
3199 {
3200 case 0:
3201 implied_prefix = 0;
3202 break;
3203 case DATA_PREFIX_OPCODE:
3204 implied_prefix = 1;
3205 break;
3206 case REPE_PREFIX_OPCODE:
3207 implied_prefix = 2;
3208 break;
3209 case REPNE_PREFIX_OPCODE:
3210 implied_prefix = 3;
3211 break;
3212 default:
3213 abort ();
3214 }
3215
3216 /* 4 byte EVEX prefix. */
3217 i.vex.length = 4;
3218 i.vex.bytes[0] = 0x62;
3219
3220 /* mmmm bits. */
3221 switch (i.tm.opcode_modifier.vexopcode)
3222 {
3223 case VEX0F:
3224 m = 1;
3225 break;
3226 case VEX0F38:
3227 m = 2;
3228 break;
3229 case VEX0F3A:
3230 m = 3;
3231 break;
3232 default:
3233 abort ();
3234 break;
3235 }
3236
3237 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3238 bits from REX. */
3239 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3240
3241 /* The fifth bit of the second EVEX byte is 1's compliment of the
3242 REX_R bit in VREX. */
3243 if (!(i.vrex & REX_R))
3244 i.vex.bytes[1] |= 0x10;
3245 else
3246 vrex_used |= REX_R;
3247
3248 if ((i.reg_operands + i.imm_operands) == i.operands)
3249 {
3250 /* When all operands are registers, the REX_X bit in REX is not
3251 used. We reuse it to encode the upper 16 registers, which is
3252 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3253 as 1's compliment. */
3254 if ((i.vrex & REX_B))
3255 {
3256 vrex_used |= REX_B;
3257 i.vex.bytes[1] &= ~0x40;
3258 }
3259 }
3260
3261 /* EVEX instructions shouldn't need the REX prefix. */
3262 i.vrex &= ~vrex_used;
3263 gas_assert (i.vrex == 0);
3264
3265 /* Check the REX.W bit. */
3266 w = (i.rex & REX_W) ? 1 : 0;
3267 if (i.tm.opcode_modifier.vexw)
3268 {
3269 if (i.tm.opcode_modifier.vexw == VEXW1)
3270 w = 1;
3271 }
3272 /* If w is not set it means we are dealing with WIG instruction. */
3273 else if (!w)
3274 {
3275 if (evexwig == evexw1)
3276 w = 1;
3277 }
3278
3279 /* Encode the U bit. */
3280 implied_prefix |= 0x4;
3281
3282 /* The third byte of the EVEX prefix. */
3283 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3284
3285 /* The fourth byte of the EVEX prefix. */
3286 /* The zeroing-masking bit. */
3287 if (i.mask && i.mask->zeroing)
3288 i.vex.bytes[3] |= 0x80;
3289
3290 /* Don't always set the broadcast bit if there is no RC. */
3291 if (!i.rounding)
3292 {
3293 /* Encode the vector length. */
3294 unsigned int vec_length;
3295
3296 switch (i.tm.opcode_modifier.evex)
3297 {
3298 case EVEXLIG: /* LL' is ignored */
3299 vec_length = evexlig << 5;
3300 break;
3301 case EVEX128:
3302 vec_length = 0 << 5;
3303 break;
3304 case EVEX256:
3305 vec_length = 1 << 5;
3306 break;
3307 case EVEX512:
3308 vec_length = 2 << 5;
3309 break;
3310 default:
3311 abort ();
3312 break;
3313 }
3314 i.vex.bytes[3] |= vec_length;
3315 /* Encode the broadcast bit. */
3316 if (i.broadcast)
3317 i.vex.bytes[3] |= 0x10;
3318 }
3319 else
3320 {
3321 if (i.rounding->type != saeonly)
3322 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3323 else
d3d3c6db 3324 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3325 }
3326
3327 if (i.mask && i.mask->mask)
3328 i.vex.bytes[3] |= i.mask->mask->reg_num;
3329}
3330
65da13b5
L		 3331static void
3332process_immext (void)
3333{
3334 expressionS *exp;
3335
4c692bc7
JB		 3336 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3337 && i.operands > 0)
65da13b5 3338 {
4c692bc7
JB		 3339 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3340 with an opcode suffix which is coded in the same place as an
3341 8-bit immediate field would be.
3342 Here we check those operands and remove them afterwards. */
65da13b5
L		 3343 unsigned int x;
3344
3345 for (x = 0; x < i.operands; x++)
4c692bc7 3346 if (register_number (i.op[x].regs) != x)
65da13b5 3347 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3348 register_prefix, i.op[x].regs->reg_name, x + 1,
3349 i.tm.name);
3350
3351 i.operands = 0;
65da13b5
L		 3352 }
3353
9916071f
AP		 3354 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3355 {
3356 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3357 suffix which is coded in the same place as an 8-bit immediate
3358 field would be.
3359 Here we check those operands and remove them afterwards. */
3360 unsigned int x;
3361
3362 if (i.operands != 3)
3363 abort();
3364
3365 for (x = 0; x < 2; x++)
3366 if (register_number (i.op[x].regs) != x)
3367 goto bad_register_operand;
3368
3369 /* Check for third operand for mwaitx/monitorx insn. */
3370 if (register_number (i.op[x].regs)
3371 != (x + (i.tm.extension_opcode == 0xfb)))
3372 {
3373bad_register_operand:
3374 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3375 register_prefix, i.op[x].regs->reg_name, x+1,
3376 i.tm.name);
3377 }
3378
3379 i.operands = 0;
3380 }
3381
c0f3af97 3382 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3383 which is coded in the same place as an 8-bit immediate field
3384 would be. Here we fake an 8-bit immediate operand from the
3385 opcode suffix stored in tm.extension_opcode.
3386
c1e679ec 3387 AVX instructions also use this encoding, for some of
c0f3af97 3388 3 argument instructions. */
65da13b5 3389
43234a1e 3390 gas_assert (i.imm_operands <= 1
7ab9ffdd 3391 && (i.operands <= 2
43234a1e
L		 3392 || ((i.tm.opcode_modifier.vex
3393 || i.tm.opcode_modifier.evex)
7ab9ffdd 3394 && i.operands <= 4)));
65da13b5
L		 3395
3396 exp = &im_expressions[i.imm_operands++];
3397 i.op[i.operands].imms = exp;
3398 i.types[i.operands] = imm8;
3399 i.operands++;
3400 exp->X_op = O_constant;
3401 exp->X_add_number = i.tm.extension_opcode;
3402 i.tm.extension_opcode = None;
3403}
3404
42164a71
L		 3405
3406static int
3407check_hle (void)
3408{
3409 switch (i.tm.opcode_modifier.hleprefixok)
3410 {
3411 default:
3412 abort ();
82c2def5 3413 case HLEPrefixNone:
165de32a
L		 3414 as_bad (_("invalid instruction `%s' after `%s'"),
3415 i.tm.name, i.hle_prefix);
42164a71 3416 return 0;
82c2def5 3417 case HLEPrefixLock:
42164a71
L		 3418 if (i.prefix[LOCK_PREFIX])
3419 return 1;
165de32a 3420 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3421 return 0;
82c2def5 3422 case HLEPrefixAny:
42164a71 3423 return 1;
82c2def5 3424 case HLEPrefixRelease:
42164a71
L		 3425 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3426 {
3427 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3428 i.tm.name);
3429 return 0;
3430 }
3431 if (i.mem_operands == 0
3432 || !operand_type_check (i.types[i.operands - 1], anymem))
3433 {
3434 as_bad (_("memory destination needed for instruction `%s'"
3435 " after `xrelease'"), i.tm.name);
3436 return 0;
3437 }
3438 return 1;
3439 }
3440}
3441
252b5132
RH		 3442/* This is the guts of the machine-dependent assembler. LINE points to a
3443 machine dependent instruction. This function is supposed to emit
3444 the frags/bytes it assembles to. */
3445
3446void
65da13b5 3447md_assemble (char *line)
252b5132 3448{
40fb9820 3449 unsigned int j;
252b5132 3450 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3451 const insn_template *t;
252b5132 3452
47926f60 3453 /* Initialize globals. */
252b5132
RH		 3454 memset (&i, '\0', sizeof (i));
3455 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3456 i.reloc[j] = NO_RELOC;
252b5132
RH		 3457 memset (disp_expressions, '\0', sizeof (disp_expressions));
3458 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3459 save_stack_p = save_stack;
252b5132
RH		 3460
3461 /* First parse an instruction mnemonic & call i386_operand for the operands.
3462 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3463 start of a (possibly prefixed) mnemonic. */
252b5132 3464
29b0f896
AM		 3465 line = parse_insn (line, mnemonic);
3466 if (line == NULL)
3467 return;
252b5132 3468
29b0f896 3469 line = parse_operands (line, mnemonic);
ee86248c 3470 this_operand = -1;
29b0f896
AM		 3471 if (line == NULL)
3472 return;
252b5132 3473
29b0f896
AM		 3474 /* Now we've parsed the mnemonic into a set of templates, and have the
3475 operands at hand. */
3476
3477 /* All intel opcodes have reversed operands except for "bound" and
3478 "enter". We also don't reverse intersegment "jmp" and "call"
3479 instructions with 2 immediate operands so that the immediate segment
050dfa73 3480 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3481 if (intel_syntax
3482 && i.operands > 1
29b0f896 3483 && (strcmp (mnemonic, "bound") != 0)
30123838 3484 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3485 && !(operand_type_check (i.types[0], imm)
3486 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3487 swap_operands ();
3488
ec56d5c0
JB		 3489 /* The order of the immediates should be reversed
3490 for 2 immediates extrq and insertq instructions */
3491 if (i.imm_operands == 2
3492 && (strcmp (mnemonic, "extrq") == 0
3493 || strcmp (mnemonic, "insertq") == 0))
3494 swap_2_operands (0, 1);
3495
29b0f896
AM		 3496 if (i.imm_operands)
3497 optimize_imm ();
3498
b300c311
L		 3499 /* Don't optimize displacement for movabs since it only takes 64bit
3500 displacement. */
3501 if (i.disp_operands
a501d77e 3502 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3503 && (flag_code != CODE_64BIT
3504 || strcmp (mnemonic, "movabs") != 0))
3505 optimize_disp ();
29b0f896
AM		 3506
3507 /* Next, we find a template that matches the given insn,
3508 making sure the overlap of the given operands types is consistent
3509 with the template operand types. */
252b5132 3510
fa99fab2 3511 if (!(t = match_template ()))
29b0f896 3512 return;
252b5132 3513
7bab8ab5 3514 if (sse_check != check_none
81f8a913 3515 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3516 && (i.tm.cpu_flags.bitfield.cpusse
3517 || i.tm.cpu_flags.bitfield.cpusse2
3518 || i.tm.cpu_flags.bitfield.cpusse3
3519 || i.tm.cpu_flags.bitfield.cpussse3
3520 || i.tm.cpu_flags.bitfield.cpusse4_1
3521 || i.tm.cpu_flags.bitfield.cpusse4_2))
3522 {
7bab8ab5 3523 (sse_check == check_warning
daf50ae7
L		 3524 ? as_warn
3525 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3526 }
3527
321fd21e
L		 3528 /* Zap movzx and movsx suffix. The suffix has been set from
3529 "word ptr" or "byte ptr" on the source operand in Intel syntax
3530 or extracted from mnemonic in AT&T syntax. But we'll use
3531 the destination register to choose the suffix for encoding. */
3532 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3533 {
321fd21e
L		 3534 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3535 there is no suffix, the default will be byte extension. */
3536 if (i.reg_operands != 2
3537 && !i.suffix
7ab9ffdd 3538 && intel_syntax)
321fd21e
L		 3539 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3540
3541 i.suffix = 0;
cd61ebfe 3542 }
24eab124 3543
40fb9820 3544 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3545 if (!add_prefix (FWAIT_OPCODE))
3546 return;
252b5132 3547
d5de92cf
L		 3548 /* Check if REP prefix is OK. */
3549 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3550 {
3551 as_bad (_("invalid instruction `%s' after `%s'"),
3552 i.tm.name, i.rep_prefix);
3553 return;
3554 }
3555
c1ba0266
L		 3556 /* Check for lock without a lockable instruction. Destination operand
3557 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3558 if (i.prefix[LOCK_PREFIX]
3559 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3560 || i.mem_operands == 0
3561 || (i.tm.base_opcode != 0x86
3562 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3563 {
3564 as_bad (_("expecting lockable instruction after `lock'"));
3565 return;
3566 }
3567
42164a71 3568 /* Check if HLE prefix is OK. */
165de32a 3569 if (i.hle_prefix && !check_hle ())
42164a71
L		 3570 return;
3571
7e8b059b
L		 3572 /* Check BND prefix. */
3573 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3574 as_bad (_("expecting valid branch instruction after `bnd'"));
3575
3576 if (i.tm.cpu_flags.bitfield.cpumpx
3577 && flag_code == CODE_64BIT
3578 && i.prefix[ADDR_PREFIX])
3579 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3580
3581 /* Insert BND prefix. */
3582 if (add_bnd_prefix
3583 && i.tm.opcode_modifier.bndprefixok
3584 && !i.prefix[BND_PREFIX])
3585 add_prefix (BND_PREFIX_OPCODE);
3586
29b0f896 3587 /* Check string instruction segment overrides. */
40fb9820 3588 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3589 {
3590 if (!check_string ())
5dd0794d 3591 return;
fc0763e6 3592 i.disp_operands = 0;
29b0f896 3593 }
5dd0794d 3594
29b0f896
AM		 3595 if (!process_suffix ())
3596 return;
e413e4e9 3597
bc0844ae
L		 3598 /* Update operand types. */
3599 for (j = 0; j < i.operands; j++)
3600 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3601
29b0f896
AM		 3602 /* Make still unresolved immediate matches conform to size of immediate
3603 given in i.suffix. */
3604 if (!finalize_imm ())
3605 return;
252b5132 3606
40fb9820 3607 if (i.types[0].bitfield.imm1)
29b0f896 3608 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3609
9afe6eb8
L		 3610 /* We only need to check those implicit registers for instructions
3611 with 3 operands or less. */
3612 if (i.operands <= 3)
3613 for (j = 0; j < i.operands; j++)
3614 if (i.types[j].bitfield.inoutportreg
3615 || i.types[j].bitfield.shiftcount
3616 || i.types[j].bitfield.acc
3617 || i.types[j].bitfield.floatacc)
3618 i.reg_operands--;
40fb9820 3619
c0f3af97
L		 3620 /* ImmExt should be processed after SSE2AVX. */
3621 if (!i.tm.opcode_modifier.sse2avx
3622 && i.tm.opcode_modifier.immext)
65da13b5 3623 process_immext ();
252b5132 3624
29b0f896
AM		 3625 /* For insns with operands there are more diddles to do to the opcode. */
3626 if (i.operands)
3627 {
3628 if (!process_operands ())
3629 return;
3630 }
40fb9820 3631 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3632 {
3633 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3634 as_warn (_("translating to `%sp'"), i.tm.name);
3635 }
252b5132 3636
9e5e5283
L		 3637 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3638 {
3639 if (flag_code == CODE_16BIT)
3640 {
3641 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3642 i.tm.name);
3643 return;
3644 }
c0f3af97 3645
9e5e5283
L		 3646 if (i.tm.opcode_modifier.vex)
3647 build_vex_prefix (t);
3648 else
3649 build_evex_prefix ();
3650 }
43234a1e 3651
5dd85c99
SP		 3652 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3653 instructions may define INT_OPCODE as well, so avoid this corner
3654 case for those instructions that use MODRM. */
3655 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3656 && !i.tm.opcode_modifier.modrm
3657 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3658 {
3659 i.tm.base_opcode = INT3_OPCODE;
3660 i.imm_operands = 0;
3661 }
252b5132 3662
40fb9820
L		 3663 if ((i.tm.opcode_modifier.jump
3664 || i.tm.opcode_modifier.jumpbyte
3665 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3666 && i.op[0].disps->X_op == O_constant)
3667 {
3668 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3669 the absolute address given by the constant. Since ix86 jumps and
3670 calls are pc relative, we need to generate a reloc. */
3671 i.op[0].disps->X_add_symbol = &abs_symbol;
3672 i.op[0].disps->X_op = O_symbol;
3673 }
252b5132 3674
40fb9820 3675 if (i.tm.opcode_modifier.rex64)
161a04f6 3676 i.rex |= REX_W;
252b5132 3677
29b0f896
AM		 3678 /* For 8 bit registers we need an empty rex prefix. Also if the
3679 instruction already has a prefix, we need to convert old
3680 registers to new ones. */
773f551c 3681
40fb9820 3682 if ((i.types[0].bitfield.reg8
29b0f896 3683 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3684 || (i.types[1].bitfield.reg8
29b0f896 3685 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3686 || ((i.types[0].bitfield.reg8
3687 || i.types[1].bitfield.reg8)
29b0f896
AM		 3688 && i.rex != 0))
3689 {
3690 int x;
726c5dcd 3691
29b0f896
AM		 3692 i.rex |= REX_OPCODE;
3693 for (x = 0; x < 2; x++)
3694 {
3695 /* Look for 8 bit operand that uses old registers. */
40fb9820 3696 if (i.types[x].bitfield.reg8
29b0f896 3697 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3698 {
29b0f896
AM		 3699 /* In case it is "hi" register, give up. */
3700 if (i.op[x].regs->reg_num > 3)
a540244d 3701 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3702 "instruction requiring REX prefix."),
a540244d 3703 register_prefix, i.op[x].regs->reg_name);
773f551c 3704
29b0f896
AM		 3705 /* Otherwise it is equivalent to the extended register.
3706 Since the encoding doesn't change this is merely
3707 cosmetic cleanup for debug output. */
3708
3709 i.op[x].regs = i.op[x].regs + 8;
773f551c 3710 }
29b0f896
AM		 3711 }
3712 }
773f551c 3713
7ab9ffdd 3714 if (i.rex != 0)
29b0f896
AM		 3715 add_prefix (REX_OPCODE | i.rex);
3716
3717 /* We are ready to output the insn. */
3718 output_insn ();
3719}
3720
3721static char *
e3bb37b5 3722parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3723{
3724 char *l = line;
3725 char *token_start = l;
3726 char *mnem_p;
5c6af06e 3727 int supported;
d3ce72d0 3728 const insn_template *t;
b6169b20 3729 char *dot_p = NULL;
29b0f896 3730
29b0f896
AM		 3731 while (1)
3732 {
3733 mnem_p = mnemonic;
3734 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3735 {
b6169b20
L		 3736 if (*mnem_p == '.')
3737 dot_p = mnem_p;
29b0f896
AM		 3738 mnem_p++;
3739 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3740 {
29b0f896
AM		 3741 as_bad (_("no such instruction: `%s'"), token_start);
3742 return NULL;
3743 }
3744 l++;
3745 }
3746 if (!is_space_char (*l)
3747 && *l != END_OF_INSN
e44823cf
JB		 3748 && (intel_syntax
3749 || (*l != PREFIX_SEPARATOR
3750 && *l != ',')))
29b0f896
AM		 3751 {
3752 as_bad (_("invalid character %s in mnemonic"),
3753 output_invalid (*l));
3754 return NULL;
3755 }
3756 if (token_start == l)
3757 {
e44823cf 3758 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3759 as_bad (_("expecting prefix; got nothing"));
3760 else
3761 as_bad (_("expecting mnemonic; got nothing"));
3762 return NULL;
3763 }
45288df1 3764
29b0f896 3765 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3766 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3767
29b0f896
AM		 3768 if (*l != END_OF_INSN
3769 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3770 && current_templates
40fb9820 3771 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3772 {
c6fb90c8 3773 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3774 {
3775 as_bad ((flag_code != CODE_64BIT
3776 ? _("`%s' is only supported in 64-bit mode")
3777 : _("`%s' is not supported in 64-bit mode")),
3778 current_templates->start->name);
3779 return NULL;
3780 }
29b0f896
AM		 3781 /* If we are in 16-bit mode, do not allow addr16 or data16.
3782 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3783 if ((current_templates->start->opcode_modifier.size16
3784 || current_templates->start->opcode_modifier.size32)
29b0f896 3785 && flag_code != CODE_64BIT
40fb9820 3786 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3787 ^ (flag_code == CODE_16BIT)))
3788 {
3789 as_bad (_("redundant %s prefix"),
3790 current_templates->start->name);
3791 return NULL;
45288df1 3792 }
29b0f896
AM		 3793 /* Add prefix, checking for repeated prefixes. */
3794 switch (add_prefix (current_templates->start->base_opcode))
3795 {
c32fa91d 3796 case PREFIX_EXIST:
29b0f896 3797 return NULL;
c32fa91d 3798 case PREFIX_REP:
42164a71 3799 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3800 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3801 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3802 i.bnd_prefix = current_templates->start->name;
42164a71 3803 else
d5de92cf 3804 i.rep_prefix = current_templates->start->name;
29b0f896 3805 break;
c32fa91d
L		 3806 default:
3807 break;
29b0f896
AM		 3808 }
3809 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3810 token_start = ++l;
3811 }
3812 else
3813 break;
3814 }
45288df1 3815
30a55f88 3816 if (!current_templates)
b6169b20 3817 {
f8a5c266
L		 3818 /* Check if we should swap operand or force 32bit displacement in
3819 encoding. */
30a55f88
L		 3820 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3821 i.swap_operand = 1;
8d63c93e 3822 else if (mnem_p - 3 == dot_p
a501d77e
L		 3823 && dot_p[1] == 'd'
3824 && dot_p[2] == '8')
3825 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3826 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3827 && dot_p[1] == 'd'
3828 && dot_p[2] == '3'
3829 && dot_p[3] == '2')
a501d77e 3830 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3831 else
3832 goto check_suffix;
3833 mnem_p = dot_p;
3834 *dot_p = '\0';
d3ce72d0 3835 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3836 }
3837
29b0f896
AM		 3838 if (!current_templates)
3839 {
b6169b20 3840check_suffix:
29b0f896
AM		 3841 /* See if we can get a match by trimming off a suffix. */
3842 switch (mnem_p[-1])
3843 {
3844 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3845 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3846 i.suffix = SHORT_MNEM_SUFFIX;
3847 else
29b0f896
AM		 3848 case BYTE_MNEM_SUFFIX:
3849 case QWORD_MNEM_SUFFIX:
3850 i.suffix = mnem_p[-1];
3851 mnem_p[-1] = '\0';
d3ce72d0
NC		 3852 current_templates = (const templates *) hash_find (op_hash,
3853 mnemonic);
29b0f896
AM		 3854 break;
3855 case SHORT_MNEM_SUFFIX:
3856 case LONG_MNEM_SUFFIX:
3857 if (!intel_syntax)
3858 {
3859 i.suffix = mnem_p[-1];
3860 mnem_p[-1] = '\0';
d3ce72d0
NC		 3861 current_templates = (const templates *) hash_find (op_hash,
3862 mnemonic);
29b0f896
AM		 3863 }
3864 break;
252b5132 3865
29b0f896
AM		 3866 /* Intel Syntax. */
3867 case 'd':
3868 if (intel_syntax)
3869 {
9306ca4a 3870 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3871 i.suffix = SHORT_MNEM_SUFFIX;
3872 else
3873 i.suffix = LONG_MNEM_SUFFIX;
3874 mnem_p[-1] = '\0';
d3ce72d0
NC		 3875 current_templates = (const templates *) hash_find (op_hash,
3876 mnemonic);
29b0f896
AM		 3877 }
3878 break;
3879 }
3880 if (!current_templates)
3881 {
3882 as_bad (_("no such instruction: `%s'"), token_start);
3883 return NULL;
3884 }
3885 }
252b5132 3886
40fb9820
L		 3887 if (current_templates->start->opcode_modifier.jump
3888 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3889 {
3890 /* Check for a branch hint. We allow ",pt" and ",pn" for
3891 predict taken and predict not taken respectively.
3892 I'm not sure that branch hints actually do anything on loop
3893 and jcxz insns (JumpByte) for current Pentium4 chips. They
3894 may work in the future and it doesn't hurt to accept them
3895 now. */
3896 if (l[0] == ',' && l[1] == 'p')
3897 {
3898 if (l[2] == 't')
3899 {
3900 if (!add_prefix (DS_PREFIX_OPCODE))
3901 return NULL;
3902 l += 3;
3903 }
3904 else if (l[2] == 'n')
3905 {
3906 if (!add_prefix (CS_PREFIX_OPCODE))
3907 return NULL;
3908 l += 3;
3909 }
3910 }
3911 }
3912 /* Any other comma loses. */
3913 if (*l == ',')
3914 {
3915 as_bad (_("invalid character %s in mnemonic"),
3916 output_invalid (*l));
3917 return NULL;
3918 }
252b5132 3919
29b0f896 3920 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3921 supported = 0;
3922 for (t = current_templates->start; t < current_templates->end; ++t)
3923 {
c0f3af97
L		 3924 supported |= cpu_flags_match (t);
3925 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3926 goto skip;
5c6af06e 3927 }
3629bb00 3928
c0f3af97 3929 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3930 {
3931 as_bad (flag_code == CODE_64BIT
3932 ? _("`%s' is not supported in 64-bit mode")
3933 : _("`%s' is only supported in 64-bit mode"),
3934 current_templates->start->name);
3935 return NULL;
3936 }
c0f3af97 3937 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3938 {
3629bb00 3939 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3940 current_templates->start->name,
41aacd83 3941 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3942 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3943 return NULL;
29b0f896 3944 }
3629bb00
L		 3945
3946skip:
3947 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3948 && (flag_code != CODE_16BIT))
29b0f896
AM		 3949 {
3950 as_warn (_("use .code16 to ensure correct addressing mode"));
3951 }
252b5132 3952
29b0f896
AM		 3953 return l;
3954}
252b5132 3955
29b0f896 3956static char *
e3bb37b5 3957parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3958{
3959 char *token_start;
3138f287 3960
29b0f896
AM		 3961 /* 1 if operand is pending after ','. */
3962 unsigned int expecting_operand = 0;
252b5132 3963
29b0f896
AM		 3964 /* Non-zero if operand parens not balanced. */
3965 unsigned int paren_not_balanced;
3966
3967 while (*l != END_OF_INSN)
3968 {
3969 /* Skip optional white space before operand. */
3970 if (is_space_char (*l))
3971 ++l;
d02603dc 3972 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 3973 {
3974 as_bad (_("invalid character %s before operand %d"),
3975 output_invalid (*l),
3976 i.operands + 1);
3977 return NULL;
3978 }
d02603dc 3979 token_start = l; /* After white space. */
29b0f896
AM		 3980 paren_not_balanced = 0;
3981 while (paren_not_balanced || *l != ',')
3982 {
3983 if (*l == END_OF_INSN)
3984 {
3985 if (paren_not_balanced)
3986 {
3987 if (!intel_syntax)
3988 as_bad (_("unbalanced parenthesis in operand %d."),
3989 i.operands + 1);
3990 else
3991 as_bad (_("unbalanced brackets in operand %d."),
3992 i.operands + 1);
3993 return NULL;
3994 }
3995 else
3996 break; /* we are done */
3997 }
d02603dc 3998 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 3999 {
4000 as_bad (_("invalid character %s in operand %d"),
4001 output_invalid (*l),
4002 i.operands + 1);
4003 return NULL;
4004 }
4005 if (!intel_syntax)
4006 {
4007 if (*l == '(')
4008 ++paren_not_balanced;
4009 if (*l == ')')
4010 --paren_not_balanced;
4011 }
4012 else
4013 {
4014 if (*l == '[')
4015 ++paren_not_balanced;
4016 if (*l == ']')
4017 --paren_not_balanced;
4018 }
4019 l++;
4020 }
4021 if (l != token_start)
4022 { /* Yes, we've read in another operand. */
4023 unsigned int operand_ok;
4024 this_operand = i.operands++;
7d5e4556 4025 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4026 if (i.operands > MAX_OPERANDS)
4027 {
4028 as_bad (_("spurious operands; (%d operands/instruction max)"),
4029 MAX_OPERANDS);
4030 return NULL;
4031 }
4032 /* Now parse operand adding info to 'i' as we go along. */
4033 END_STRING_AND_SAVE (l);
4034
4035 if (intel_syntax)
4036 operand_ok =
4037 i386_intel_operand (token_start,
4038 intel_float_operand (mnemonic));
4039 else
a7619375 4040 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4041
4042 RESTORE_END_STRING (l);
4043 if (!operand_ok)
4044 return NULL;
4045 }
4046 else
4047 {
4048 if (expecting_operand)
4049 {
4050 expecting_operand_after_comma:
4051 as_bad (_("expecting operand after ','; got nothing"));
4052 return NULL;
4053 }
4054 if (*l == ',')
4055 {
4056 as_bad (_("expecting operand before ','; got nothing"));
4057 return NULL;
4058 }
4059 }
7f3f1ea2 4060
29b0f896
AM		 4061 /* Now *l must be either ',' or END_OF_INSN. */
4062 if (*l == ',')
4063 {
4064 if (*++l == END_OF_INSN)
4065 {
4066 /* Just skip it, if it's \n complain. */
4067 goto expecting_operand_after_comma;
4068 }
4069 expecting_operand = 1;
4070 }
4071 }
4072 return l;
4073}
7f3f1ea2 4074
050dfa73 4075static void
4d456e3d 4076swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4077{
4078 union i386_op temp_op;
40fb9820 4079 i386_operand_type temp_type;
050dfa73 4080 enum bfd_reloc_code_real temp_reloc;
4eed87de 4081
050dfa73
MM		 4082 temp_type = i.types[xchg2];
4083 i.types[xchg2] = i.types[xchg1];
4084 i.types[xchg1] = temp_type;
4085 temp_op = i.op[xchg2];
4086 i.op[xchg2] = i.op[xchg1];
4087 i.op[xchg1] = temp_op;
4088 temp_reloc = i.reloc[xchg2];
4089 i.reloc[xchg2] = i.reloc[xchg1];
4090 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4091
4092 if (i.mask)
4093 {
4094 if (i.mask->operand == xchg1)
4095 i.mask->operand = xchg2;
4096 else if (i.mask->operand == xchg2)
4097 i.mask->operand = xchg1;
4098 }
4099 if (i.broadcast)
4100 {
4101 if (i.broadcast->operand == xchg1)
4102 i.broadcast->operand = xchg2;
4103 else if (i.broadcast->operand == xchg2)
4104 i.broadcast->operand = xchg1;
4105 }
4106 if (i.rounding)
4107 {
4108 if (i.rounding->operand == xchg1)
4109 i.rounding->operand = xchg2;
4110 else if (i.rounding->operand == xchg2)
4111 i.rounding->operand = xchg1;
4112 }
050dfa73
MM		 4113}
4114
29b0f896 4115static void
e3bb37b5 4116swap_operands (void)
29b0f896 4117{
b7c61d9a 4118 switch (i.operands)
050dfa73 4119 {
c0f3af97 4120 case 5:
b7c61d9a 4121 case 4:
4d456e3d 4122 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4123 case 3:
4124 case 2:
4d456e3d 4125 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4126 break;
4127 default:
4128 abort ();
29b0f896 4129 }
29b0f896
AM		 4130
4131 if (i.mem_operands == 2)
4132 {
4133 const seg_entry *temp_seg;
4134 temp_seg = i.seg[0];
4135 i.seg[0] = i.seg[1];
4136 i.seg[1] = temp_seg;
4137 }
4138}
252b5132 4139
29b0f896
AM		 4140/* Try to ensure constant immediates are represented in the smallest
4141 opcode possible. */
4142static void
e3bb37b5 4143optimize_imm (void)
29b0f896
AM		 4144{
4145 char guess_suffix = 0;
4146 int op;
252b5132 4147
29b0f896
AM		 4148 if (i.suffix)
4149 guess_suffix = i.suffix;
4150 else if (i.reg_operands)
4151 {
4152 /* Figure out a suffix from the last register operand specified.
4153 We can't do this properly yet, ie. excluding InOutPortReg,
4154 but the following works for instructions with immediates.
4155 In any case, we can't set i.suffix yet. */
4156 for (op = i.operands; --op >= 0;)
40fb9820 4157 if (i.types[op].bitfield.reg8)
7ab9ffdd 4158 {
40fb9820
L		 4159 guess_suffix = BYTE_MNEM_SUFFIX;
4160 break;
4161 }
4162 else if (i.types[op].bitfield.reg16)
252b5132 4163 {
40fb9820
L		 4164 guess_suffix = WORD_MNEM_SUFFIX;
4165 break;
4166 }
4167 else if (i.types[op].bitfield.reg32)
4168 {
4169 guess_suffix = LONG_MNEM_SUFFIX;
4170 break;
4171 }
4172 else if (i.types[op].bitfield.reg64)
4173 {
4174 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4175 break;
252b5132 4176 }
29b0f896
AM		 4177 }
4178 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4179 guess_suffix = WORD_MNEM_SUFFIX;
4180
4181 for (op = i.operands; --op >= 0;)
40fb9820 4182 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4183 {
4184 switch (i.op[op].imms->X_op)
252b5132 4185 {
29b0f896
AM		 4186 case O_constant:
4187 /* If a suffix is given, this operand may be shortened. */
4188 switch (guess_suffix)
252b5132 4189 {
29b0f896 4190 case LONG_MNEM_SUFFIX:
40fb9820
L		 4191 i.types[op].bitfield.imm32 = 1;
4192 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4193 break;
4194 case WORD_MNEM_SUFFIX:
40fb9820
L		 4195 i.types[op].bitfield.imm16 = 1;
4196 i.types[op].bitfield.imm32 = 1;
4197 i.types[op].bitfield.imm32s = 1;
4198 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4199 break;
4200 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4201 i.types[op].bitfield.imm8 = 1;
4202 i.types[op].bitfield.imm8s = 1;
4203 i.types[op].bitfield.imm16 = 1;
4204 i.types[op].bitfield.imm32 = 1;
4205 i.types[op].bitfield.imm32s = 1;
4206 i.types[op].bitfield.imm64 = 1;
29b0f896 4207 break;
252b5132 4208 }
252b5132 4209
29b0f896
AM		 4210 /* If this operand is at most 16 bits, convert it
4211 to a signed 16 bit number before trying to see
4212 whether it will fit in an even smaller size.
4213 This allows a 16-bit operand such as $0xffe0 to
4214 be recognised as within Imm8S range. */
40fb9820 4215 if ((i.types[op].bitfield.imm16)
29b0f896 4216 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4217 {
29b0f896
AM		 4218 i.op[op].imms->X_add_number =
4219 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4220 }
40fb9820 4221 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4222 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4223 == 0))
4224 {
4225 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4226 ^ ((offsetT) 1 << 31))
4227 - ((offsetT) 1 << 31));
4228 }
40fb9820 4229 i.types[op]
c6fb90c8
L		 4230 = operand_type_or (i.types[op],
4231 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4232
29b0f896
AM		 4233 /* We must avoid matching of Imm32 templates when 64bit
4234 only immediate is available. */
4235 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4236 i.types[op].bitfield.imm32 = 0;
29b0f896 4237 break;
252b5132 4238
29b0f896
AM		 4239 case O_absent:
4240 case O_register:
4241 abort ();
4242
4243 /* Symbols and expressions. */
4244 default:
9cd96992
JB		 4245 /* Convert symbolic operand to proper sizes for matching, but don't
4246 prevent matching a set of insns that only supports sizes other
4247 than those matching the insn suffix. */
4248 {
40fb9820 4249 i386_operand_type mask, allowed;
d3ce72d0 4250 const insn_template *t;
9cd96992 4251
0dfbf9d7
L		 4252 operand_type_set (&mask, 0);
4253 operand_type_set (&allowed, 0);
40fb9820 4254
4eed87de
AM		 4255 for (t = current_templates->start;
4256 t < current_templates->end;
4257 ++t)
c6fb90c8
L		 4258 allowed = operand_type_or (allowed,
4259 t->operand_types[op]);
9cd96992
JB		 4260 switch (guess_suffix)
4261 {
4262 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4263 mask.bitfield.imm64 = 1;
4264 mask.bitfield.imm32s = 1;
9cd96992
JB		 4265 break;
4266 case LONG_MNEM_SUFFIX:
40fb9820 4267 mask.bitfield.imm32 = 1;
9cd96992
JB		 4268 break;
4269 case WORD_MNEM_SUFFIX:
40fb9820 4270 mask.bitfield.imm16 = 1;
9cd96992
JB		 4271 break;
4272 case BYTE_MNEM_SUFFIX:
40fb9820 4273 mask.bitfield.imm8 = 1;
9cd96992
JB		 4274 break;
4275 default:
9cd96992
JB		 4276 break;
4277 }
c6fb90c8 4278 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4279 if (!operand_type_all_zero (&allowed))
c6fb90c8 4280 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4281 }
29b0f896 4282 break;
252b5132 4283 }
29b0f896
AM		 4284 }
4285}
47926f60 4286
29b0f896
AM		 4287/* Try to use the smallest displacement type too. */
4288static void
e3bb37b5 4289optimize_disp (void)
29b0f896
AM		 4290{
4291 int op;
3e73aa7c 4292
29b0f896 4293 for (op = i.operands; --op >= 0;)
40fb9820 4294 if (operand_type_check (i.types[op], disp))
252b5132 4295 {
b300c311 4296 if (i.op[op].disps->X_op == O_constant)
252b5132 4297 {
91d6fa6a 4298 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4299
40fb9820 4300 if (i.types[op].bitfield.disp16
91d6fa6a 4301 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4302 {
4303 /* If this operand is at most 16 bits, convert
4304 to a signed 16 bit number and don't use 64bit
4305 displacement. */
91d6fa6a 4306 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4307 i.types[op].bitfield.disp64 = 0;
b300c311 4308 }
40fb9820 4309 if (i.types[op].bitfield.disp32
91d6fa6a 4310 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4311 {
4312 /* If this operand is at most 32 bits, convert
4313 to a signed 32 bit number and don't use 64bit
4314 displacement. */
91d6fa6a
NC		 4315 op_disp &= (((offsetT) 2 << 31) - 1);
4316 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4317 i.types[op].bitfield.disp64 = 0;
b300c311 4318 }
91d6fa6a 4319 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4320 {
40fb9820
L		 4321 i.types[op].bitfield.disp8 = 0;
4322 i.types[op].bitfield.disp16 = 0;
4323 i.types[op].bitfield.disp32 = 0;
4324 i.types[op].bitfield.disp32s = 0;
4325 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4326 i.op[op].disps = 0;
4327 i.disp_operands--;
4328 }
4329 else if (flag_code == CODE_64BIT)
4330 {
91d6fa6a 4331 if (fits_in_signed_long (op_disp))
28a9d8f5 4332 {
40fb9820
L		 4333 i.types[op].bitfield.disp64 = 0;
4334 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4335 }
0e1147d9 4336 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4337 && fits_in_unsigned_long (op_disp))
40fb9820 4338 i.types[op].bitfield.disp32 = 1;
b300c311 4339 }
40fb9820
L		 4340 if ((i.types[op].bitfield.disp32
4341 || i.types[op].bitfield.disp32s
4342 || i.types[op].bitfield.disp16)
91d6fa6a 4343 && fits_in_signed_byte (op_disp))
40fb9820 4344 i.types[op].bitfield.disp8 = 1;
252b5132 4345 }
67a4f2b7
AO		 4346 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4347 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4348 {
4349 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4350 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4351 i.types[op].bitfield.disp8 = 0;
4352 i.types[op].bitfield.disp16 = 0;
4353 i.types[op].bitfield.disp32 = 0;
4354 i.types[op].bitfield.disp32s = 0;
4355 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4356 }
4357 else
b300c311 4358 /* We only support 64bit displacement on constants. */
40fb9820 4359 i.types[op].bitfield.disp64 = 0;
252b5132 4360 }
29b0f896
AM		 4361}
4362
6c30d220
L		 4363/* Check if operands are valid for the instruction. */
4364
4365static int
4366check_VecOperands (const insn_template *t)
4367{
43234a1e
L		 4368 unsigned int op;
4369
6c30d220
L		 4370 /* Without VSIB byte, we can't have a vector register for index. */
4371 if (!t->opcode_modifier.vecsib
4372 && i.index_reg
4373 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4374 || i.index_reg->reg_type.bitfield.regymm
4375 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4376 {
4377 i.error = unsupported_vector_index_register;
4378 return 1;
4379 }
4380
ad8ecc81
MZ		 4381 /* Check if default mask is allowed. */
4382 if (t->opcode_modifier.nodefmask
4383 && (!i.mask || i.mask->mask->reg_num == 0))
4384 {
4385 i.error = no_default_mask;
4386 return 1;
4387 }
4388
7bab8ab5
JB		 4389 /* For VSIB byte, we need a vector register for index, and all vector
4390 registers must be distinct. */
4391 if (t->opcode_modifier.vecsib)
4392 {
4393 if (!i.index_reg
6c30d220
L		 4394 || !((t->opcode_modifier.vecsib == VecSIB128
4395 && i.index_reg->reg_type.bitfield.regxmm)
4396 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4397 && i.index_reg->reg_type.bitfield.regymm)
4398 || (t->opcode_modifier.vecsib == VecSIB512
4399 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4400 {
4401 i.error = invalid_vsib_address;
4402 return 1;
4403 }
4404
43234a1e
L		 4405 gas_assert (i.reg_operands == 2 || i.mask);
4406 if (i.reg_operands == 2 && !i.mask)
4407 {
4408 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4409 || i.types[0].bitfield.regymm);
43234a1e 4410 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4411 || i.types[2].bitfield.regymm);
43234a1e
L		 4412 if (operand_check == check_none)
4413 return 0;
4414 if (register_number (i.op[0].regs)
4415 != register_number (i.index_reg)
4416 && register_number (i.op[2].regs)
4417 != register_number (i.index_reg)
4418 && register_number (i.op[0].regs)
4419 != register_number (i.op[2].regs))
4420 return 0;
4421 if (operand_check == check_error)
4422 {
4423 i.error = invalid_vector_register_set;
4424 return 1;
4425 }
4426 as_warn (_("mask, index, and destination registers should be distinct"));
4427 }
8444f82a
MZ		 4428 else if (i.reg_operands == 1 && i.mask)
4429 {
4430 if ((i.types[1].bitfield.regymm
4431 || i.types[1].bitfield.regzmm)
4432 && (register_number (i.op[1].regs)
4433 == register_number (i.index_reg)))
4434 {
4435 if (operand_check == check_error)
4436 {
4437 i.error = invalid_vector_register_set;
4438 return 1;
4439 }
4440 if (operand_check != check_none)
4441 as_warn (_("index and destination registers should be distinct"));
4442 }
4443 }
43234a1e 4444 }
7bab8ab5 4445
43234a1e
L		 4446 /* Check if broadcast is supported by the instruction and is applied
4447 to the memory operand. */
4448 if (i.broadcast)
4449 {
4450 int broadcasted_opnd_size;
4451
4452 /* Check if specified broadcast is supported in this instruction,
4453 and it's applied to memory operand of DWORD or QWORD type,
4454 depending on VecESize. */
4455 if (i.broadcast->type != t->opcode_modifier.broadcast
4456 || !i.types[i.broadcast->operand].bitfield.mem
4457 || (t->opcode_modifier.vecesize == 0
4458 && !i.types[i.broadcast->operand].bitfield.dword
4459 && !i.types[i.broadcast->operand].bitfield.unspecified)
4460 || (t->opcode_modifier.vecesize == 1
4461 && !i.types[i.broadcast->operand].bitfield.qword
4462 && !i.types[i.broadcast->operand].bitfield.unspecified))
4463 goto bad_broadcast;
4464
4465 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4466 if (i.broadcast->type == BROADCAST_1TO16)
4467 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4468 else if (i.broadcast->type == BROADCAST_1TO8)
4469 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4470 else if (i.broadcast->type == BROADCAST_1TO4)
4471 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4472 else if (i.broadcast->type == BROADCAST_1TO2)
4473 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4474 else
4475 goto bad_broadcast;
4476
4477 if ((broadcasted_opnd_size == 256
4478 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4479 || (broadcasted_opnd_size == 512
4480 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4481 {
4482 bad_broadcast:
4483 i.error = unsupported_broadcast;
4484 return 1;
4485 }
4486 }
4487 /* If broadcast is supported in this instruction, we need to check if
4488 operand of one-element size isn't specified without broadcast. */
4489 else if (t->opcode_modifier.broadcast && i.mem_operands)
4490 {
4491 /* Find memory operand. */
4492 for (op = 0; op < i.operands; op++)
4493 if (operand_type_check (i.types[op], anymem))
4494 break;
4495 gas_assert (op < i.operands);
4496 /* Check size of the memory operand. */
4497 if ((t->opcode_modifier.vecesize == 0
4498 && i.types[op].bitfield.dword)
4499 || (t->opcode_modifier.vecesize == 1
4500 && i.types[op].bitfield.qword))
4501 {
4502 i.error = broadcast_needed;
4503 return 1;
4504 }
4505 }
4506
4507 /* Check if requested masking is supported. */
4508 if (i.mask
4509 && (!t->opcode_modifier.masking
4510 || (i.mask->zeroing
4511 && t->opcode_modifier.masking == MERGING_MASKING)))
4512 {
4513 i.error = unsupported_masking;
4514 return 1;
4515 }
4516
4517 /* Check if masking is applied to dest operand. */
4518 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4519 {
4520 i.error = mask_not_on_destination;
4521 return 1;
4522 }
4523
43234a1e
L		 4524 /* Check RC/SAE. */
4525 if (i.rounding)
4526 {
4527 if ((i.rounding->type != saeonly
4528 && !t->opcode_modifier.staticrounding)
4529 || (i.rounding->type == saeonly
4530 && (t->opcode_modifier.staticrounding
4531 || !t->opcode_modifier.sae)))
4532 {
4533 i.error = unsupported_rc_sae;
4534 return 1;
4535 }
4536 /* If the instruction has several immediate operands and one of
4537 them is rounding, the rounding operand should be the last
4538 immediate operand. */
4539 if (i.imm_operands > 1
4540 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4541 {
43234a1e 4542 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4543 return 1;
4544 }
6c30d220
L		 4545 }
4546
43234a1e
L		 4547 /* Check vector Disp8 operand. */
4548 if (t->opcode_modifier.disp8memshift)
4549 {
4550 if (i.broadcast)
4551 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4552 else
4553 i.memshift = t->opcode_modifier.disp8memshift;
4554
4555 for (op = 0; op < i.operands; op++)
4556 if (operand_type_check (i.types[op], disp)
4557 && i.op[op].disps->X_op == O_constant)
4558 {
4559 offsetT value = i.op[op].disps->X_add_number;
4560 int vec_disp8_ok = fits_in_vec_disp8 (value);
4561 if (t->operand_types [op].bitfield.vec_disp8)
4562 {
4563 if (vec_disp8_ok)
4564 i.types[op].bitfield.vec_disp8 = 1;
4565 else
4566 {
4567 /* Vector insn can only have Vec_Disp8/Disp32 in
4568 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4569 mode. */
4570 i.types[op].bitfield.disp8 = 0;
4571 if (flag_code != CODE_16BIT)
4572 i.types[op].bitfield.disp16 = 0;
4573 }
4574 }
4575 else if (flag_code != CODE_16BIT)
4576 {
4577 /* One form of this instruction supports vector Disp8.
4578 Try vector Disp8 if we need to use Disp32. */
4579 if (vec_disp8_ok && !fits_in_signed_byte (value))
4580 {
4581 i.error = try_vector_disp8;
4582 return 1;
4583 }
4584 }
4585 }
4586 }
4587 else
4588 i.memshift = -1;
4589
6c30d220
L		 4590 return 0;
4591}
4592
43f3e2ee 4593/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4594 operand types. */
4595
4596static int
4597VEX_check_operands (const insn_template *t)
4598{
43234a1e
L		 4599 /* VREX is only valid with EVEX prefix. */
4600 if (i.need_vrex && !t->opcode_modifier.evex)
4601 {
4602 i.error = invalid_register_operand;
4603 return 1;
4604 }
4605
a683cc34
SP		 4606 if (!t->opcode_modifier.vex)
4607 return 0;
4608
4609 /* Only check VEX_Imm4, which must be the first operand. */
4610 if (t->operand_types[0].bitfield.vec_imm4)
4611 {
4612 if (i.op[0].imms->X_op != O_constant
4613 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4614 {
a65babc9 4615 i.error = bad_imm4;
891edac4
L		 4616 return 1;
4617 }
a683cc34
SP		 4618
4619 /* Turn off Imm8 so that update_imm won't complain. */
4620 i.types[0] = vec_imm4;
4621 }
4622
4623 return 0;
4624}
4625
d3ce72d0 4626static const insn_template *
e3bb37b5 4627match_template (void)
29b0f896
AM		 4628{
4629 /* Points to template once we've found it. */
d3ce72d0 4630 const insn_template *t;
40fb9820 4631 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4632 i386_operand_type overlap4;
29b0f896 4633 unsigned int found_reverse_match;
40fb9820
L		 4634 i386_opcode_modifier suffix_check;
4635 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4636 int addr_prefix_disp;
a5c311ca 4637 unsigned int j;
3629bb00 4638 unsigned int found_cpu_match;
45664ddb 4639 unsigned int check_register;
5614d22c 4640 enum i386_error specific_error = 0;
29b0f896 4641
c0f3af97
L		 4642#if MAX_OPERANDS != 5
4643# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4644#endif
4645
29b0f896 4646 found_reverse_match = 0;
539e75ad 4647 addr_prefix_disp = -1;
40fb9820
L		 4648
4649 memset (&suffix_check, 0, sizeof (suffix_check));
4650 if (i.suffix == BYTE_MNEM_SUFFIX)
4651 suffix_check.no_bsuf = 1;
4652 else if (i.suffix == WORD_MNEM_SUFFIX)
4653 suffix_check.no_wsuf = 1;
4654 else if (i.suffix == SHORT_MNEM_SUFFIX)
4655 suffix_check.no_ssuf = 1;
4656 else if (i.suffix == LONG_MNEM_SUFFIX)
4657 suffix_check.no_lsuf = 1;
4658 else if (i.suffix == QWORD_MNEM_SUFFIX)
4659 suffix_check.no_qsuf = 1;
4660 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4661 suffix_check.no_ldsuf = 1;
29b0f896 4662
01559ecc
L		 4663 /* Must have right number of operands. */
4664 i.error = number_of_operands_mismatch;
4665
45aa61fe 4666 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4667 {
539e75ad
L		 4668 addr_prefix_disp = -1;
4669
29b0f896
AM		 4670 if (i.operands != t->operands)
4671 continue;
4672
50aecf8c 4673 /* Check processor support. */
a65babc9 4674 i.error = unsupported;
c0f3af97
L		 4675 found_cpu_match = (cpu_flags_match (t)
4676 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4677 if (!found_cpu_match)
4678 continue;
4679
e1d4d893 4680 /* Check old gcc support. */
a65babc9 4681 i.error = old_gcc_only;
e1d4d893
L		 4682 if (!old_gcc && t->opcode_modifier.oldgcc)
4683 continue;
4684
4685 /* Check AT&T mnemonic. */
a65babc9 4686 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4687 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4688 continue;
4689
891edac4 4690 /* Check AT&T/Intel syntax. */
a65babc9 4691 i.error = unsupported_syntax;
5c07affc
L		 4692 if ((intel_syntax && t->opcode_modifier.attsyntax)
4693 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4694 continue;
4695
20592a94 4696 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4697 i.error = invalid_instruction_suffix;
567e4e96
L		 4698 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4699 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4700 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4701 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4702 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4703 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4704 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4705 continue;
4706
5c07affc 4707 if (!operand_size_match (t))
7d5e4556 4708 continue;
539e75ad 4709
5c07affc
L		 4710 for (j = 0; j < MAX_OPERANDS; j++)
4711 operand_types[j] = t->operand_types[j];
4712
45aa61fe
AM		 4713 /* In general, don't allow 64-bit operands in 32-bit mode. */
4714 if (i.suffix == QWORD_MNEM_SUFFIX
4715 && flag_code != CODE_64BIT
4716 && (intel_syntax
40fb9820 4717 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4718 && !intel_float_operand (t->name))
4719 : intel_float_operand (t->name) != 2)
40fb9820 4720 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4721 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4722 && !operand_types[0].bitfield.regymm
4723 && !operand_types[0].bitfield.regzmm)
40fb9820 4724 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4725 && operand_types[t->operands > 1].bitfield.regxmm
4726 && operand_types[t->operands > 1].bitfield.regymm
4727 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4728 && (t->base_opcode != 0x0fc7
4729 || t->extension_opcode != 1 /* cmpxchg8b */))
4730 continue;
4731
192dc9c6
JB		 4732 /* In general, don't allow 32-bit operands on pre-386. */
4733 else if (i.suffix == LONG_MNEM_SUFFIX
4734 && !cpu_arch_flags.bitfield.cpui386
4735 && (intel_syntax
4736 ? (!t->opcode_modifier.ignoresize
4737 && !intel_float_operand (t->name))
4738 : intel_float_operand (t->name) != 2)
4739 && ((!operand_types[0].bitfield.regmmx
4740 && !operand_types[0].bitfield.regxmm)
4741 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4742 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4743 continue;
4744
29b0f896 4745 /* Do not verify operands when there are none. */
50aecf8c 4746 else
29b0f896 4747 {
c6fb90c8 4748 if (!t->operands)
2dbab7d5
L		 4749 /* We've found a match; break out of loop. */
4750 break;
29b0f896 4751 }
252b5132 4752
539e75ad
L		 4753 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4754 into Disp32/Disp16/Disp32 operand. */
4755 if (i.prefix[ADDR_PREFIX] != 0)
4756 {
40fb9820 4757 /* There should be only one Disp operand. */
539e75ad
L		 4758 switch (flag_code)
4759 {
4760 case CODE_16BIT:
40fb9820
L		 4761 for (j = 0; j < MAX_OPERANDS; j++)
4762 {
4763 if (operand_types[j].bitfield.disp16)
4764 {
4765 addr_prefix_disp = j;
4766 operand_types[j].bitfield.disp32 = 1;
4767 operand_types[j].bitfield.disp16 = 0;
4768 break;
4769 }
4770 }
539e75ad
L		 4771 break;
4772 case CODE_32BIT:
40fb9820
L		 4773 for (j = 0; j < MAX_OPERANDS; j++)
4774 {
4775 if (operand_types[j].bitfield.disp32)
4776 {
4777 addr_prefix_disp = j;
4778 operand_types[j].bitfield.disp32 = 0;
4779 operand_types[j].bitfield.disp16 = 1;
4780 break;
4781 }
4782 }
539e75ad
L		 4783 break;
4784 case CODE_64BIT:
40fb9820
L		 4785 for (j = 0; j < MAX_OPERANDS; j++)
4786 {
4787 if (operand_types[j].bitfield.disp64)
4788 {
4789 addr_prefix_disp = j;
4790 operand_types[j].bitfield.disp64 = 0;
4791 operand_types[j].bitfield.disp32 = 1;
4792 break;
4793 }
4794 }
539e75ad
L		 4795 break;
4796 }
539e75ad
L		 4797 }
4798
02a86693
L		 4799 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4800 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4801 continue;
4802
56ffb741
L		 4803 /* We check register size if needed. */
4804 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4805 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4806 switch (t->operands)
4807 {
4808 case 1:
40fb9820 4809 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4810 continue;
4811 break;
4812 case 2:
8b38ad71
L		 4813 /* xchg %eax, %eax is a special case. It is an aliase for nop
4814 only in 32bit mode and we can use opcode 0x90. In 64bit
4815 mode, we can't use 0x90 for xchg %eax, %eax since it should
4816 zero-extend %eax to %rax. */
4817 if (flag_code == CODE_64BIT
4818 && t->base_opcode == 0x90
0dfbf9d7
L		 4819 && operand_type_equal (&i.types [0], &acc32)
4820 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4821 continue;
b6169b20
L		 4822 if (i.swap_operand)
4823 {
4824 /* If we swap operand in encoding, we either match
4825 the next one or reverse direction of operands. */
4826 if (t->opcode_modifier.s)
4827 continue;
4828 else if (t->opcode_modifier.d)
4829 goto check_reverse;
4830 }
4831
29b0f896 4832 case 3:
fa99fab2
L		 4833 /* If we swap operand in encoding, we match the next one. */
4834 if (i.swap_operand && t->opcode_modifier.s)
4835 continue;
f48ff2ae 4836 case 4:
c0f3af97 4837 case 5:
c6fb90c8 4838 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4839 if (!operand_type_match (overlap0, i.types[0])
4840 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4841 || (check_register
4842 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4843 operand_types[0],
4844 overlap1, i.types[1],
4845 operand_types[1])))
29b0f896
AM		 4846 {
4847 /* Check if other direction is valid ... */
40fb9820 4848 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4849 continue;
4850
b6169b20 4851check_reverse:
29b0f896 4852 /* Try reversing direction of operands. */
c6fb90c8
L		 4853 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4854 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4855 if (!operand_type_match (overlap0, i.types[0])
4856 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4857 || (check_register
4858 && !operand_type_register_match (overlap0,
4859 i.types[0],
4860 operand_types[1],
4861 overlap1,
4862 i.types[1],
4863 operand_types[0])))
29b0f896
AM		 4864 {
4865 /* Does not match either direction. */
4866 continue;
4867 }
4868 /* found_reverse_match holds which of D or FloatDR
4869 we've found. */
40fb9820 4870 if (t->opcode_modifier.d)
8a2ed489 4871 found_reverse_match = Opcode_D;
40fb9820 4872 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4873 found_reverse_match = Opcode_FloatD;
4874 else
4875 found_reverse_match = 0;
40fb9820 4876 if (t->opcode_modifier.floatr)
8a2ed489 4877 found_reverse_match |= Opcode_FloatR;
29b0f896 4878 }
f48ff2ae 4879 else
29b0f896 4880 {
f48ff2ae 4881 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4882 switch (t->operands)
4883 {
c0f3af97
L		 4884 case 5:
4885 overlap4 = operand_type_and (i.types[4],
4886 operand_types[4]);
d1cbb4db 4887 case 4:
c6fb90c8
L		 4888 overlap3 = operand_type_and (i.types[3],
4889 operand_types[3]);
d1cbb4db 4890 case 3:
c6fb90c8
L		 4891 overlap2 = operand_type_and (i.types[2],
4892 operand_types[2]);
d1cbb4db
L		 4893 break;
4894 }
29b0f896 4895
f48ff2ae
L		 4896 switch (t->operands)
4897 {
c0f3af97
L		 4898 case 5:
4899 if (!operand_type_match (overlap4, i.types[4])
4900 || !operand_type_register_match (overlap3,
4901 i.types[3],
4902 operand_types[3],
4903 overlap4,
4904 i.types[4],
4905 operand_types[4]))
4906 continue;
f48ff2ae 4907 case 4:
40fb9820 4908 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4909 || (check_register
4910 && !operand_type_register_match (overlap2,
4911 i.types[2],
4912 operand_types[2],
4913 overlap3,
4914 i.types[3],
4915 operand_types[3])))
f48ff2ae
L		 4916 continue;
4917 case 3:
4918 /* Here we make use of the fact that there are no
4919 reverse match 3 operand instructions, and all 3
4920 operand instructions only need to be checked for
4921 register consistency between operands 2 and 3. */
40fb9820 4922 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4923 || (check_register
4924 && !operand_type_register_match (overlap1,
4925 i.types[1],
4926 operand_types[1],
4927 overlap2,
4928 i.types[2],
4929 operand_types[2])))
f48ff2ae
L		 4930 continue;
4931 break;
4932 }
29b0f896 4933 }
f48ff2ae 4934 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4935 slip through to break. */
4936 }
3629bb00 4937 if (!found_cpu_match)
29b0f896
AM		 4938 {
4939 found_reverse_match = 0;
4940 continue;
4941 }
c0f3af97 4942
5614d22c
JB		 4943 /* Check if vector and VEX operands are valid. */
4944 if (check_VecOperands (t) || VEX_check_operands (t))
4945 {
4946 specific_error = i.error;
4947 continue;
4948 }
a683cc34 4949
29b0f896
AM		 4950 /* We've found a match; break out of loop. */
4951 break;
4952 }
4953
4954 if (t == current_templates->end)
4955 {
4956 /* We found no match. */
a65babc9 4957 const char *err_msg;
5614d22c 4958 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4959 {
4960 default:
4961 abort ();
86e026a4 4962 case operand_size_mismatch:
a65babc9
L		 4963 err_msg = _("operand size mismatch");
4964 break;
4965 case operand_type_mismatch:
4966 err_msg = _("operand type mismatch");
4967 break;
4968 case register_type_mismatch:
4969 err_msg = _("register type mismatch");
4970 break;
4971 case number_of_operands_mismatch:
4972 err_msg = _("number of operands mismatch");
4973 break;
4974 case invalid_instruction_suffix:
4975 err_msg = _("invalid instruction suffix");
4976 break;
4977 case bad_imm4:
4a2608e3 4978 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4979 break;
4980 case old_gcc_only:
4981 err_msg = _("only supported with old gcc");
4982 break;
4983 case unsupported_with_intel_mnemonic:
4984 err_msg = _("unsupported with Intel mnemonic");
4985 break;
4986 case unsupported_syntax:
4987 err_msg = _("unsupported syntax");
4988 break;
4989 case unsupported:
35262a23 4990 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4991 current_templates->start->name);
4992 return NULL;
6c30d220
L		 4993 case invalid_vsib_address:
4994 err_msg = _("invalid VSIB address");
4995 break;
7bab8ab5
JB		 4996 case invalid_vector_register_set:
4997 err_msg = _("mask, index, and destination registers must be distinct");
4998 break;
6c30d220
L		 4999 case unsupported_vector_index_register:
5000 err_msg = _("unsupported vector index register");
5001 break;
43234a1e
L		 5002 case unsupported_broadcast:
5003 err_msg = _("unsupported broadcast");
5004 break;
5005 case broadcast_not_on_src_operand:
5006 err_msg = _("broadcast not on source memory operand");
5007 break;
5008 case broadcast_needed:
5009 err_msg = _("broadcast is needed for operand of such type");
5010 break;
5011 case unsupported_masking:
5012 err_msg = _("unsupported masking");
5013 break;
5014 case mask_not_on_destination:
5015 err_msg = _("mask not on destination operand");
5016 break;
5017 case no_default_mask:
5018 err_msg = _("default mask isn't allowed");
5019 break;
5020 case unsupported_rc_sae:
5021 err_msg = _("unsupported static rounding/sae");
5022 break;
5023 case rc_sae_operand_not_last_imm:
5024 if (intel_syntax)
5025 err_msg = _("RC/SAE operand must precede immediate operands");
5026 else
5027 err_msg = _("RC/SAE operand must follow immediate operands");
5028 break;
5029 case invalid_register_operand:
5030 err_msg = _("invalid register operand");
5031 break;
a65babc9
L		 5032 }
5033 as_bad (_("%s for `%s'"), err_msg,
891edac4 5034 current_templates->start->name);
fa99fab2 5035 return NULL;
29b0f896 5036 }
252b5132 5037
29b0f896
AM		 5038 if (!quiet_warnings)
5039 {
5040 if (!intel_syntax
40fb9820
L		 5041 && (i.types[0].bitfield.jumpabsolute
5042 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5043 {
5044 as_warn (_("indirect %s without `*'"), t->name);
5045 }
5046
40fb9820
L		 5047 if (t->opcode_modifier.isprefix
5048 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5049 {
5050 /* Warn them that a data or address size prefix doesn't
5051 affect assembly of the next line of code. */
5052 as_warn (_("stand-alone `%s' prefix"), t->name);
5053 }
5054 }
5055
5056 /* Copy the template we found. */
5057 i.tm = *t;
539e75ad
L		 5058
5059 if (addr_prefix_disp != -1)
5060 i.tm.operand_types[addr_prefix_disp]
5061 = operand_types[addr_prefix_disp];
5062
29b0f896
AM		 5063 if (found_reverse_match)
5064 {
5065 /* If we found a reverse match we must alter the opcode
5066 direction bit. found_reverse_match holds bits to change
5067 (different for int & float insns). */
5068
5069 i.tm.base_opcode ^= found_reverse_match;
5070
539e75ad
L		 5071 i.tm.operand_types[0] = operand_types[1];
5072 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5073 }
5074
fa99fab2 5075 return t;
29b0f896
AM		 5076}
5077
5078static int
e3bb37b5 5079check_string (void)
29b0f896 5080{
40fb9820
L		 5081 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5082 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5083 {
5084 if (i.seg[0] != NULL && i.seg[0] != &es)
5085 {
a87af027 5086 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5087 i.tm.name,
a87af027
JB		 5088 mem_op + 1,
5089 register_prefix);
29b0f896
AM		 5090 return 0;
5091 }
5092 /* There's only ever one segment override allowed per instruction.
5093 This instruction possibly has a legal segment override on the
5094 second operand, so copy the segment to where non-string
5095 instructions store it, allowing common code. */
5096 i.seg[0] = i.seg[1];
5097 }
40fb9820 5098 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5099 {
5100 if (i.seg[1] != NULL && i.seg[1] != &es)
5101 {
a87af027 5102 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5103 i.tm.name,
a87af027
JB		 5104 mem_op + 2,
5105 register_prefix);
29b0f896
AM		 5106 return 0;
5107 }
5108 }
5109 return 1;
5110}
5111
5112static int
543613e9 5113process_suffix (void)
29b0f896
AM		 5114{
5115 /* If matched instruction specifies an explicit instruction mnemonic
5116 suffix, use it. */
40fb9820
L		 5117 if (i.tm.opcode_modifier.size16)
5118 i.suffix = WORD_MNEM_SUFFIX;
5119 else if (i.tm.opcode_modifier.size32)
5120 i.suffix = LONG_MNEM_SUFFIX;
5121 else if (i.tm.opcode_modifier.size64)
5122 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5123 else if (i.reg_operands)
5124 {
5125 /* If there's no instruction mnemonic suffix we try to invent one
5126 based on register operands. */
5127 if (!i.suffix)
5128 {
5129 /* We take i.suffix from the last register operand specified,
5130 Destination register type is more significant than source
381d071f
L		 5131 register type. crc32 in SSE4.2 prefers source register
5132 type. */
5133 if (i.tm.base_opcode == 0xf20f38f1)
5134 {
40fb9820
L		 5135 if (i.types[0].bitfield.reg16)
5136 i.suffix = WORD_MNEM_SUFFIX;
5137 else if (i.types[0].bitfield.reg32)
5138 i.suffix = LONG_MNEM_SUFFIX;
5139 else if (i.types[0].bitfield.reg64)
5140 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5141 }
9344ff29 5142 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5143 {
40fb9820 5144 if (i.types[0].bitfield.reg8)
20592a94
L		 5145 i.suffix = BYTE_MNEM_SUFFIX;
5146 }
381d071f
L		 5147
5148 if (!i.suffix)
5149 {
5150 int op;
5151
20592a94
L		 5152 if (i.tm.base_opcode == 0xf20f38f1
5153 || i.tm.base_opcode == 0xf20f38f0)
5154 {
5155 /* We have to know the operand size for crc32. */
5156 as_bad (_("ambiguous memory operand size for `%s`"),
5157 i.tm.name);
5158 return 0;
5159 }
5160
381d071f 5161 for (op = i.operands; --op >= 0;)
40fb9820 5162 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5163 {
40fb9820
L		 5164 if (i.types[op].bitfield.reg8)
5165 {
5166 i.suffix = BYTE_MNEM_SUFFIX;
5167 break;
5168 }
5169 else if (i.types[op].bitfield.reg16)
5170 {
5171 i.suffix = WORD_MNEM_SUFFIX;
5172 break;
5173 }
5174 else if (i.types[op].bitfield.reg32)
5175 {
5176 i.suffix = LONG_MNEM_SUFFIX;
5177 break;
5178 }
5179 else if (i.types[op].bitfield.reg64)
5180 {
5181 i.suffix = QWORD_MNEM_SUFFIX;
5182 break;
5183 }
381d071f
L		 5184 }
5185 }
29b0f896
AM		 5186 }
5187 else if (i.suffix == BYTE_MNEM_SUFFIX)
5188 {
2eb952a4
L		 5189 if (intel_syntax
5190 && i.tm.opcode_modifier.ignoresize
5191 && i.tm.opcode_modifier.no_bsuf)
5192 i.suffix = 0;
5193 else if (!check_byte_reg ())
29b0f896
AM		 5194 return 0;
5195 }
5196 else if (i.suffix == LONG_MNEM_SUFFIX)
5197 {
2eb952a4
L		 5198 if (intel_syntax
5199 && i.tm.opcode_modifier.ignoresize
5200 && i.tm.opcode_modifier.no_lsuf)
5201 i.suffix = 0;
5202 else if (!check_long_reg ())
29b0f896
AM		 5203 return 0;
5204 }
5205 else if (i.suffix == QWORD_MNEM_SUFFIX)
5206 {
955e1e6a
L		 5207 if (intel_syntax
5208 && i.tm.opcode_modifier.ignoresize
5209 && i.tm.opcode_modifier.no_qsuf)
5210 i.suffix = 0;
5211 else if (!check_qword_reg ())
29b0f896
AM		 5212 return 0;
5213 }
5214 else if (i.suffix == WORD_MNEM_SUFFIX)
5215 {
2eb952a4
L		 5216 if (intel_syntax
5217 && i.tm.opcode_modifier.ignoresize
5218 && i.tm.opcode_modifier.no_wsuf)
5219 i.suffix = 0;
5220 else if (!check_word_reg ())
29b0f896
AM		 5221 return 0;
5222 }
c0f3af97 5223 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5224 || i.suffix == YMMWORD_MNEM_SUFFIX
5225 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5226 {
43234a1e 5227 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5228 should check if it is a valid suffix. */
5229 }
40fb9820 5230 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5231 /* Do nothing if the instruction is going to ignore the prefix. */
5232 ;
5233 else
5234 abort ();
5235 }
40fb9820 5236 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5237 && !i.suffix
5238 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5239 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5240 {
5241 i.suffix = stackop_size;
5242 }
9306ca4a
JB		 5243 else if (intel_syntax
5244 && !i.suffix
40fb9820
L		 5245 && (i.tm.operand_types[0].bitfield.jumpabsolute
5246 || i.tm.opcode_modifier.jumpbyte
5247 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5248 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5249 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5250 {
5251 switch (flag_code)
5252 {
5253 case CODE_64BIT:
40fb9820 5254 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5255 {
5256 i.suffix = QWORD_MNEM_SUFFIX;
5257 break;
5258 }
5259 case CODE_32BIT:
40fb9820 5260 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5261 i.suffix = LONG_MNEM_SUFFIX;
5262 break;
5263 case CODE_16BIT:
40fb9820 5264 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5265 i.suffix = WORD_MNEM_SUFFIX;
5266 break;
5267 }
5268 }
252b5132 5269
9306ca4a 5270 if (!i.suffix)
29b0f896 5271 {
9306ca4a
JB		 5272 if (!intel_syntax)
5273 {
40fb9820 5274 if (i.tm.opcode_modifier.w)
9306ca4a 5275 {
4eed87de
AM		 5276 as_bad (_("no instruction mnemonic suffix given and "
5277 "no register operands; can't size instruction"));
9306ca4a
JB		 5278 return 0;
5279 }
5280 }
5281 else
5282 {
40fb9820 5283 unsigned int suffixes;
7ab9ffdd 5284
40fb9820
L		 5285 suffixes = !i.tm.opcode_modifier.no_bsuf;
5286 if (!i.tm.opcode_modifier.no_wsuf)
5287 suffixes |= 1 << 1;
5288 if (!i.tm.opcode_modifier.no_lsuf)
5289 suffixes |= 1 << 2;
fc4adea1 5290 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5291 suffixes |= 1 << 3;
5292 if (!i.tm.opcode_modifier.no_ssuf)
5293 suffixes |= 1 << 4;
5294 if (!i.tm.opcode_modifier.no_qsuf)
5295 suffixes |= 1 << 5;
5296
5297 /* There are more than suffix matches. */
5298 if (i.tm.opcode_modifier.w
9306ca4a 5299 || ((suffixes & (suffixes - 1))
40fb9820
L		 5300 && !i.tm.opcode_modifier.defaultsize
5301 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5302 {
5303 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5304 return 0;
5305 }
5306 }
29b0f896 5307 }
252b5132 5308
9306ca4a
JB		 5309 /* Change the opcode based on the operand size given by i.suffix;
5310 We don't need to change things for byte insns. */
5311
582d5edd
L		 5312 if (i.suffix
5313 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5314 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5315 && i.suffix != YMMWORD_MNEM_SUFFIX
5316 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5317 {
5318 /* It's not a byte, select word/dword operation. */
40fb9820 5319 if (i.tm.opcode_modifier.w)
29b0f896 5320 {
40fb9820 5321 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5322 i.tm.base_opcode |= 8;
5323 else
5324 i.tm.base_opcode |= 1;
5325 }
0f3f3d8b 5326
29b0f896
AM		 5327 /* Now select between word & dword operations via the operand
5328 size prefix, except for instructions that will ignore this
5329 prefix anyway. */
ca61edf2 5330 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5331 {
ca61edf2
L		 5332 /* The address size override prefix changes the size of the
5333 first operand. */
40fb9820
L		 5334 if ((flag_code == CODE_32BIT
5335 && i.op->regs[0].reg_type.bitfield.reg16)
5336 || (flag_code != CODE_32BIT
5337 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5338 if (!add_prefix (ADDR_PREFIX_OPCODE))
5339 return 0;
5340 }
5341 else if (i.suffix != QWORD_MNEM_SUFFIX
5342 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5343 && !i.tm.opcode_modifier.ignoresize
5344 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5345 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5346 || (flag_code == CODE_64BIT
40fb9820 5347 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5348 {
5349 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5350
40fb9820 5351 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5352 prefix = ADDR_PREFIX_OPCODE;
252b5132 5353
29b0f896
AM		 5354 if (!add_prefix (prefix))
5355 return 0;
24eab124 5356 }
252b5132 5357
29b0f896
AM		 5358 /* Set mode64 for an operand. */
5359 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5360 && flag_code == CODE_64BIT
40fb9820 5361 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5362 {
5363 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5364 need rex64. cmpxchg8b is also a special case. */
5365 if (! (i.operands == 2
5366 && i.tm.base_opcode == 0x90
5367 && i.tm.extension_opcode == None
0dfbf9d7
L		 5368 && operand_type_equal (&i.types [0], &acc64)
5369 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5370 && ! (i.operands == 1
5371 && i.tm.base_opcode == 0xfc7
5372 && i.tm.extension_opcode == 1
40fb9820
L		 5373 && !operand_type_check (i.types [0], reg)
5374 && operand_type_check (i.types [0], anymem)))
f6bee062 5375 i.rex |= REX_W;
46e883c5 5376 }
3e73aa7c 5377
29b0f896
AM		 5378 /* Size floating point instruction. */
5379 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5380 if (i.tm.opcode_modifier.floatmf)
543613e9 5381 i.tm.base_opcode ^= 4;
29b0f896 5382 }
7ecd2f8b 5383
29b0f896
AM		 5384 return 1;
5385}
3e73aa7c 5386
29b0f896 5387static int
543613e9 5388check_byte_reg (void)
29b0f896
AM		 5389{
5390 int op;
543613e9 5391
29b0f896
AM		 5392 for (op = i.operands; --op >= 0;)
5393 {
5394 /* If this is an eight bit register, it's OK. If it's the 16 or
5395 32 bit version of an eight bit register, we will just use the
5396 low portion, and that's OK too. */
40fb9820 5397 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5398 continue;
5399
5a819eb9
JB		 5400 /* I/O port address operands are OK too. */
5401 if (i.tm.operand_types[op].bitfield.inoutportreg)
5402 continue;
5403
9344ff29
L		 5404 /* crc32 doesn't generate this warning. */
5405 if (i.tm.base_opcode == 0xf20f38f0)
5406 continue;
5407
40fb9820
L		 5408 if ((i.types[op].bitfield.reg16
5409 || i.types[op].bitfield.reg32
5410 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5411 && i.op[op].regs->reg_num < 4
5412 /* Prohibit these changes in 64bit mode, since the lowering
5413 would be more complicated. */
5414 && flag_code != CODE_64BIT)
29b0f896 5415 {
29b0f896 5416#if REGISTER_WARNINGS
5a819eb9 5417 if (!quiet_warnings)
a540244d
L		 5418 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5419 register_prefix,
40fb9820 5420 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5421 ? REGNAM_AL - REGNAM_AX
5422 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5423 register_prefix,
29b0f896
AM		 5424 i.op[op].regs->reg_name,
5425 i.suffix);
5426#endif
5427 continue;
5428 }
5429 /* Any other register is bad. */
40fb9820
L		 5430 if (i.types[op].bitfield.reg16
5431 || i.types[op].bitfield.reg32
5432 || i.types[op].bitfield.reg64
5433 || i.types[op].bitfield.regmmx
5434 || i.types[op].bitfield.regxmm
c0f3af97 5435 || i.types[op].bitfield.regymm
43234a1e 5436 || i.types[op].bitfield.regzmm
40fb9820
L		 5437 || i.types[op].bitfield.sreg2
5438 || i.types[op].bitfield.sreg3
5439 || i.types[op].bitfield.control
5440 || i.types[op].bitfield.debug
5441 || i.types[op].bitfield.test
5442 || i.types[op].bitfield.floatreg
5443 || i.types[op].bitfield.floatacc)
29b0f896 5444 {
a540244d
L		 5445 as_bad (_("`%s%s' not allowed with `%s%c'"),
5446 register_prefix,
29b0f896
AM		 5447 i.op[op].regs->reg_name,
5448 i.tm.name,
5449 i.suffix);
5450 return 0;
5451 }
5452 }
5453 return 1;
5454}
5455
5456static int
e3bb37b5 5457check_long_reg (void)
29b0f896
AM		 5458{
5459 int op;
5460
5461 for (op = i.operands; --op >= 0;)
5462 /* Reject eight bit registers, except where the template requires
5463 them. (eg. movzb) */
40fb9820
L		 5464 if (i.types[op].bitfield.reg8
5465 && (i.tm.operand_types[op].bitfield.reg16
5466 || i.tm.operand_types[op].bitfield.reg32
5467 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5468 {
a540244d
L		 5469 as_bad (_("`%s%s' not allowed with `%s%c'"),
5470 register_prefix,
29b0f896
AM		 5471 i.op[op].regs->reg_name,
5472 i.tm.name,
5473 i.suffix);
5474 return 0;
5475 }
e4630f71 5476 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5477 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5478 && i.types[op].bitfield.reg16
5479 && (i.tm.operand_types[op].bitfield.reg32
5480 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5481 {
5482 /* Prohibit these changes in the 64bit mode, since the
5483 lowering is more complicated. */
5484 if (flag_code == CODE_64BIT)
252b5132 5485 {
2b5d6a91 5486 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5487 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5488 i.suffix);
5489 return 0;
252b5132 5490 }
29b0f896 5491#if REGISTER_WARNINGS
cecf1424
JB		 5492 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5493 register_prefix,
5494 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5495 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5496#endif
252b5132 5497 }
e4630f71 5498 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5499 else if (i.types[op].bitfield.reg64
5500 && (i.tm.operand_types[op].bitfield.reg32
5501 || i.tm.operand_types[op].bitfield.acc))
252b5132 5502 {
34828aad 5503 if (intel_syntax
ca61edf2 5504 && i.tm.opcode_modifier.toqword
40fb9820 5505 && !i.types[0].bitfield.regxmm)
34828aad 5506 {
ca61edf2 5507 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5508 i.suffix = QWORD_MNEM_SUFFIX;
5509 }
5510 else
5511 {
2b5d6a91 5512 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5513 register_prefix, i.op[op].regs->reg_name,
5514 i.suffix);
5515 return 0;
5516 }
29b0f896
AM		 5517 }
5518 return 1;
5519}
252b5132 5520
29b0f896 5521static int
e3bb37b5 5522check_qword_reg (void)
29b0f896
AM		 5523{
5524 int op;
252b5132 5525
29b0f896
AM		 5526 for (op = i.operands; --op >= 0; )
5527 /* Reject eight bit registers, except where the template requires
5528 them. (eg. movzb) */
40fb9820
L		 5529 if (i.types[op].bitfield.reg8
5530 && (i.tm.operand_types[op].bitfield.reg16
5531 || i.tm.operand_types[op].bitfield.reg32
5532 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5533 {
a540244d
L		 5534 as_bad (_("`%s%s' not allowed with `%s%c'"),
5535 register_prefix,
29b0f896
AM		 5536 i.op[op].regs->reg_name,
5537 i.tm.name,
5538 i.suffix);
5539 return 0;
5540 }
e4630f71 5541 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5542 else if ((i.types[op].bitfield.reg16
5543 || i.types[op].bitfield.reg32)
5544 && (i.tm.operand_types[op].bitfield.reg32
5545 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5546 {
5547 /* Prohibit these changes in the 64bit mode, since the
5548 lowering is more complicated. */
34828aad 5549 if (intel_syntax
ca61edf2 5550 && i.tm.opcode_modifier.todword
40fb9820 5551 && !i.types[0].bitfield.regxmm)
34828aad 5552 {
ca61edf2 5553 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5554 i.suffix = LONG_MNEM_SUFFIX;
5555 }
5556 else
5557 {
2b5d6a91 5558 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5559 register_prefix, i.op[op].regs->reg_name,
5560 i.suffix);
5561 return 0;
5562 }
252b5132 5563 }
29b0f896
AM		 5564 return 1;
5565}
252b5132 5566
29b0f896 5567static int
e3bb37b5 5568check_word_reg (void)
29b0f896
AM		 5569{
5570 int op;
5571 for (op = i.operands; --op >= 0;)
5572 /* Reject eight bit registers, except where the template requires
5573 them. (eg. movzb) */
40fb9820
L		 5574 if (i.types[op].bitfield.reg8
5575 && (i.tm.operand_types[op].bitfield.reg16
5576 || i.tm.operand_types[op].bitfield.reg32
5577 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5578 {
a540244d
L		 5579 as_bad (_("`%s%s' not allowed with `%s%c'"),
5580 register_prefix,
29b0f896
AM		 5581 i.op[op].regs->reg_name,
5582 i.tm.name,
5583 i.suffix);
5584 return 0;
5585 }
e4630f71 5586 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5587 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5588 && (i.types[op].bitfield.reg32
5589 || i.types[op].bitfield.reg64)
40fb9820
L		 5590 && (i.tm.operand_types[op].bitfield.reg16
5591 || i.tm.operand_types[op].bitfield.acc))
252b5132 5592 {
29b0f896
AM		 5593 /* Prohibit these changes in the 64bit mode, since the
5594 lowering is more complicated. */
5595 if (flag_code == CODE_64BIT)
252b5132 5596 {
2b5d6a91 5597 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5598 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5599 i.suffix);
5600 return 0;
252b5132 5601 }
29b0f896 5602#if REGISTER_WARNINGS
cecf1424
JB		 5603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5604 register_prefix,
5605 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5606 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5607#endif
5608 }
5609 return 1;
5610}
252b5132 5611
29b0f896 5612static int
40fb9820 5613update_imm (unsigned int j)
29b0f896 5614{
bc0844ae 5615 i386_operand_type overlap = i.types[j];
40fb9820
L		 5616 if ((overlap.bitfield.imm8
5617 || overlap.bitfield.imm8s
5618 || overlap.bitfield.imm16
5619 || overlap.bitfield.imm32
5620 || overlap.bitfield.imm32s
5621 || overlap.bitfield.imm64)
0dfbf9d7
L		 5622 && !operand_type_equal (&overlap, &imm8)
5623 && !operand_type_equal (&overlap, &imm8s)
5624 && !operand_type_equal (&overlap, &imm16)
5625 && !operand_type_equal (&overlap, &imm32)
5626 && !operand_type_equal (&overlap, &imm32s)
5627 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5628 {
5629 if (i.suffix)
5630 {
40fb9820
L		 5631 i386_operand_type temp;
5632
0dfbf9d7 5633 operand_type_set (&temp, 0);
7ab9ffdd 5634 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5635 {
5636 temp.bitfield.imm8 = overlap.bitfield.imm8;
5637 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5638 }
5639 else if (i.suffix == WORD_MNEM_SUFFIX)
5640 temp.bitfield.imm16 = overlap.bitfield.imm16;
5641 else if (i.suffix == QWORD_MNEM_SUFFIX)
5642 {
5643 temp.bitfield.imm64 = overlap.bitfield.imm64;
5644 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5645 }
5646 else
5647 temp.bitfield.imm32 = overlap.bitfield.imm32;
5648 overlap = temp;
29b0f896 5649 }
0dfbf9d7
L		 5650 else if (operand_type_equal (&overlap, &imm16_32_32s)
5651 || operand_type_equal (&overlap, &imm16_32)
5652 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5653 {
40fb9820 5654 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5655 overlap = imm16;
40fb9820 5656 else
65da13b5 5657 overlap = imm32s;
29b0f896 5658 }
0dfbf9d7
L		 5659 if (!operand_type_equal (&overlap, &imm8)
5660 && !operand_type_equal (&overlap, &imm8s)
5661 && !operand_type_equal (&overlap, &imm16)
5662 && !operand_type_equal (&overlap, &imm32)
5663 && !operand_type_equal (&overlap, &imm32s)
5664 && !operand_type_equal (&overlap, &imm64))
29b0f896 5665 {
4eed87de
AM		 5666 as_bad (_("no instruction mnemonic suffix given; "
5667 "can't determine immediate size"));
29b0f896
AM		 5668 return 0;
5669 }
5670 }
40fb9820 5671 i.types[j] = overlap;
29b0f896 5672
40fb9820
L		 5673 return 1;
5674}
5675
5676static int
5677finalize_imm (void)
5678{
bc0844ae 5679 unsigned int j, n;
29b0f896 5680
bc0844ae
L		 5681 /* Update the first 2 immediate operands. */
5682 n = i.operands > 2 ? 2 : i.operands;
5683 if (n)
5684 {
5685 for (j = 0; j < n; j++)
5686 if (update_imm (j) == 0)
5687 return 0;
40fb9820 5688
bc0844ae
L		 5689 /* The 3rd operand can't be immediate operand. */
5690 gas_assert (operand_type_check (i.types[2], imm) == 0);
5691 }
29b0f896
AM		 5692
5693 return 1;
5694}
5695
c0f3af97
L		 5696static int
5697bad_implicit_operand (int xmm)
5698{
91d6fa6a
NC		 5699 const char *ireg = xmm ? "xmm0" : "ymm0";
5700
c0f3af97
L		 5701 if (intel_syntax)
5702 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5703 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5704 else
5705 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5706 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5707 return 0;
5708}
5709
29b0f896 5710static int
e3bb37b5 5711process_operands (void)
29b0f896
AM		 5712{
5713 /* Default segment register this instruction will use for memory
5714 accesses. 0 means unknown. This is only for optimizing out
5715 unnecessary segment overrides. */
5716 const seg_entry *default_seg = 0;
5717
2426c15f 5718 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5719 {
91d6fa6a
NC		 5720 unsigned int dupl = i.operands;
5721 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5722 unsigned int j;
5723
c0f3af97 5724 /* The destination must be an xmm register. */
9c2799c2 5725 gas_assert (i.reg_operands
91d6fa6a 5726 && MAX_OPERANDS > dupl
7ab9ffdd 5727 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5728
5729 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5730 {
c0f3af97 5731 /* The first operand is implicit and must be xmm0. */
9c2799c2 5732 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5733 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5734 return bad_implicit_operand (1);
5735
8cd7925b 5736 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5737 {
5738 /* Keep xmm0 for instructions with VEX prefix and 3
5739 sources. */
5740 goto duplicate;
5741 }
e2ec9d29 5742 else
c0f3af97
L		 5743 {
5744 /* We remove the first xmm0 and keep the number of
5745 operands unchanged, which in fact duplicates the
5746 destination. */
5747 for (j = 1; j < i.operands; j++)
5748 {
5749 i.op[j - 1] = i.op[j];
5750 i.types[j - 1] = i.types[j];
5751 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5752 }
5753 }
5754 }
5755 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5756 {
91d6fa6a 5757 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5758 && (i.tm.opcode_modifier.vexsources
5759 == VEX3SOURCES));
c0f3af97
L		 5760
5761 /* Add the implicit xmm0 for instructions with VEX prefix
5762 and 3 sources. */
5763 for (j = i.operands; j > 0; j--)
5764 {
5765 i.op[j] = i.op[j - 1];
5766 i.types[j] = i.types[j - 1];
5767 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5768 }
5769 i.op[0].regs
5770 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5771 i.types[0] = regxmm;
c0f3af97
L		 5772 i.tm.operand_types[0] = regxmm;
5773
5774 i.operands += 2;
5775 i.reg_operands += 2;
5776 i.tm.operands += 2;
5777
91d6fa6a 5778 dupl++;
c0f3af97 5779 dest++;
91d6fa6a
NC		 5780 i.op[dupl] = i.op[dest];
5781 i.types[dupl] = i.types[dest];
5782 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5783 }
c0f3af97
L		 5784 else
5785 {
5786duplicate:
5787 i.operands++;
5788 i.reg_operands++;
5789 i.tm.operands++;
5790
91d6fa6a
NC		 5791 i.op[dupl] = i.op[dest];
5792 i.types[dupl] = i.types[dest];
5793 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5794 }
5795
5796 if (i.tm.opcode_modifier.immext)
5797 process_immext ();
5798 }
5799 else if (i.tm.opcode_modifier.firstxmm0)
5800 {
5801 unsigned int j;
5802
43234a1e 5803 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5804 gas_assert (i.reg_operands
7ab9ffdd 5805 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5806 || operand_type_equal (&i.types[0], &regymm)
5807 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5808 if (register_number (i.op[0].regs) != 0)
c0f3af97 5809 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5810
5811 for (j = 1; j < i.operands; j++)
5812 {
5813 i.op[j - 1] = i.op[j];
5814 i.types[j - 1] = i.types[j];
5815
5816 /* We need to adjust fields in i.tm since they are used by
5817 build_modrm_byte. */
5818 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5819 }
5820
e2ec9d29
L		 5821 i.operands--;
5822 i.reg_operands--;
e2ec9d29
L		 5823 i.tm.operands--;
5824 }
5825 else if (i.tm.opcode_modifier.regkludge)
5826 {
5827 /* The imul $imm, %reg instruction is converted into
5828 imul $imm, %reg, %reg, and the clr %reg instruction
5829 is converted into xor %reg, %reg. */
5830
5831 unsigned int first_reg_op;
5832
5833 if (operand_type_check (i.types[0], reg))
5834 first_reg_op = 0;
5835 else
5836 first_reg_op = 1;
5837 /* Pretend we saw the extra register operand. */
9c2799c2 5838 gas_assert (i.reg_operands == 1
7ab9ffdd 5839 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5840 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5841 i.types[first_reg_op + 1] = i.types[first_reg_op];
5842 i.operands++;
5843 i.reg_operands++;
29b0f896
AM		 5844 }
5845
40fb9820 5846 if (i.tm.opcode_modifier.shortform)
29b0f896 5847 {
40fb9820
L		 5848 if (i.types[0].bitfield.sreg2
5849 || i.types[0].bitfield.sreg3)
29b0f896 5850 {
4eed87de
AM		 5851 if (i.tm.base_opcode == POP_SEG_SHORT
5852 && i.op[0].regs->reg_num == 1)
29b0f896 5853 {
a87af027 5854 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5855 return 0;
29b0f896 5856 }
4eed87de
AM		 5857 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5858 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5859 i.rex |= REX_B;
4eed87de
AM		 5860 }
5861 else
5862 {
7ab9ffdd 5863 /* The register or float register operand is in operand
85f10a01 5864 0 or 1. */
40fb9820 5865 unsigned int op;
7ab9ffdd
L		 5866
5867 if (i.types[0].bitfield.floatreg
5868 || operand_type_check (i.types[0], reg))
5869 op = 0;
5870 else
5871 op = 1;
4eed87de
AM		 5872 /* Register goes in low 3 bits of opcode. */
5873 i.tm.base_opcode |= i.op[op].regs->reg_num;
5874 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5875 i.rex |= REX_B;
40fb9820 5876 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5877 {
4eed87de
AM		 5878 /* Warn about some common errors, but press on regardless.
5879 The first case can be generated by gcc (<= 2.8.1). */
5880 if (i.operands == 2)
5881 {
5882 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5883 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5884 register_prefix, i.op[!intel_syntax].regs->reg_name,
5885 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5886 }
5887 else
5888 {
5889 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5890 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5891 register_prefix, i.op[0].regs->reg_name);
4eed87de 5892 }
29b0f896
AM		 5893 }
5894 }
5895 }
40fb9820 5896 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5897 {
5898 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5899 must be put into the modrm byte). Now, we make the modrm and
5900 index base bytes based on all the info we've collected. */
29b0f896
AM		 5901
5902 default_seg = build_modrm_byte ();
5903 }
8a2ed489 5904 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5905 {
5906 default_seg = &ds;
5907 }
40fb9820 5908 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5909 {
5910 /* For the string instructions that allow a segment override
5911 on one of their operands, the default segment is ds. */
5912 default_seg = &ds;
5913 }
5914
75178d9d
L		 5915 if (i.tm.base_opcode == 0x8d /* lea */
5916 && i.seg[0]
5917 && !quiet_warnings)
30123838 5918 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5919
5920 /* If a segment was explicitly specified, and the specified segment
5921 is not the default, use an opcode prefix to select it. If we
5922 never figured out what the default segment is, then default_seg
5923 will be zero at this point, and the specified segment prefix will
5924 always be used. */
29b0f896
AM		 5925 if ((i.seg[0]) && (i.seg[0] != default_seg))
5926 {
5927 if (!add_prefix (i.seg[0]->seg_prefix))
5928 return 0;
5929 }
5930 return 1;
5931}
5932
5933static const seg_entry *
e3bb37b5 5934build_modrm_byte (void)
29b0f896
AM		 5935{
5936 const seg_entry *default_seg = 0;
c0f3af97 5937 unsigned int source, dest;
8cd7925b 5938 int vex_3_sources;
c0f3af97
L		 5939
5940 /* The first operand of instructions with VEX prefix and 3 sources
5941 must be VEX_Imm4. */
8cd7925b 5942 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5943 if (vex_3_sources)
5944 {
91d6fa6a 5945 unsigned int nds, reg_slot;
4c2c6516 5946 expressionS *exp;
c0f3af97 5947
922d8de8 5948 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5949 && i.tm.opcode_modifier.immext)
5950 {
5951 dest = i.operands - 2;
5952 gas_assert (dest == 3);
5953 }
922d8de8 5954 else
a683cc34 5955 dest = i.operands - 1;
c0f3af97 5956 nds = dest - 1;
922d8de8 5957
a683cc34
SP		 5958 /* There are 2 kinds of instructions:
5959 1. 5 operands: 4 register operands or 3 register operands
5960 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5961 VexW0 or VexW1. The destination must be either XMM, YMM or
5962 ZMM register.
a683cc34
SP		 5963 2. 4 operands: 4 register operands or 3 register operands
5964 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5965 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5966 || (i.reg_operands == 3 && i.mem_operands == 1))
5967 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5968 && (i.tm.opcode_modifier.veximmext
5969 || (i.imm_operands == 1
5970 && i.types[0].bitfield.vec_imm4
5971 && (i.tm.opcode_modifier.vexw == VEXW0
5972 || i.tm.opcode_modifier.vexw == VEXW1)
5973 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5974 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5975 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5976
5977 if (i.imm_operands == 0)
5978 {
5979 /* When there is no immediate operand, generate an 8bit
5980 immediate operand to encode the first operand. */
5981 exp = &im_expressions[i.imm_operands++];
5982 i.op[i.operands].imms = exp;
5983 i.types[i.operands] = imm8;
5984 i.operands++;
5985 /* If VexW1 is set, the first operand is the source and
5986 the second operand is encoded in the immediate operand. */
5987 if (i.tm.opcode_modifier.vexw == VEXW1)
5988 {
5989 source = 0;
5990 reg_slot = 1;
5991 }
5992 else
5993 {
5994 source = 1;
5995 reg_slot = 0;
5996 }
5997
5998 /* FMA swaps REG and NDS. */
5999 if (i.tm.cpu_flags.bitfield.cpufma)
6000 {
6001 unsigned int tmp;
6002 tmp = reg_slot;
6003 reg_slot = nds;
6004 nds = tmp;
6005 }
6006
24981e7b
L		 6007 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6008 &regxmm)
a683cc34 6009 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6010 &regymm)
6011 || operand_type_equal (&i.tm.operand_types[reg_slot],
6012 &regzmm));
a683cc34 6013 exp->X_op = O_constant;
4c692bc7 6014 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6015 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6016 }
922d8de8 6017 else
a683cc34
SP		 6018 {
6019 unsigned int imm_slot;
6020
6021 if (i.tm.opcode_modifier.vexw == VEXW0)
6022 {
6023 /* If VexW0 is set, the third operand is the source and
6024 the second operand is encoded in the immediate
6025 operand. */
6026 source = 2;
6027 reg_slot = 1;
6028 }
6029 else
6030 {
6031 /* VexW1 is set, the second operand is the source and
6032 the third operand is encoded in the immediate
6033 operand. */
6034 source = 1;
6035 reg_slot = 2;
6036 }
6037
6038 if (i.tm.opcode_modifier.immext)
6039 {
6040 /* When ImmExt is set, the immdiate byte is the last
6041 operand. */
6042 imm_slot = i.operands - 1;
6043 source--;
6044 reg_slot--;
6045 }
6046 else
6047 {
6048 imm_slot = 0;
6049
6050 /* Turn on Imm8 so that output_imm will generate it. */
6051 i.types[imm_slot].bitfield.imm8 = 1;
6052 }
6053
24981e7b
L		 6054 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6055 &regxmm)
6056 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6057 &regymm)
6058 || operand_type_equal (&i.tm.operand_types[reg_slot],
6059 &regzmm));
a683cc34 6060 i.op[imm_slot].imms->X_add_number
4c692bc7 6061 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6062 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6063 }
6064
6065 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6066 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6067 &regymm)
6068 || operand_type_equal (&i.tm.operand_types[nds],
6069 &regzmm));
dae39acc 6070 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6071 }
6072 else
6073 source = dest = 0;
29b0f896
AM		 6074
6075 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6076 implicit registers do not count. If there are 3 register
6077 operands, it must be a instruction with VexNDS. For a
6078 instruction with VexNDD, the destination register is encoded
6079 in VEX prefix. If there are 4 register operands, it must be
6080 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6081 if (i.mem_operands == 0
6082 && ((i.reg_operands == 2
2426c15f 6083 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6084 || (i.reg_operands == 3
2426c15f 6085 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6086 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6087 {
cab737b9
L		 6088 switch (i.operands)
6089 {
6090 case 2:
6091 source = 0;
6092 break;
6093 case 3:
c81128dc
L		 6094 /* When there are 3 operands, one of them may be immediate,
6095 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6096 the first operand must be shift count register (cl) or it
6097 is an instruction with VexNDS. */
9c2799c2 6098 gas_assert (i.imm_operands == 1
7ab9ffdd 6099 || (i.imm_operands == 0
2426c15f 6100 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6101 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6102 if (operand_type_check (i.types[0], imm)
6103 || i.types[0].bitfield.shiftcount)
6104 source = 1;
6105 else
6106 source = 0;
cab737b9
L		 6107 break;
6108 case 4:
368d64cc
L		 6109 /* When there are 4 operands, the first two must be 8bit
6110 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6111 one.
6112
6113 For instructions with VexNDS, if the first operand
6114 an imm8, the source operand is the 2nd one. If the last
6115 operand is imm8, the source operand is the first one. */
9c2799c2 6116 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6117 && i.types[0].bitfield.imm8
6118 && i.types[1].bitfield.imm8)
2426c15f 6119 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6120 && i.imm_operands == 1
6121 && (i.types[0].bitfield.imm8
43234a1e
L		 6122 || i.types[i.operands - 1].bitfield.imm8
6123 || i.rounding)));
9f2670f2
L		 6124 if (i.imm_operands == 2)
6125 source = 2;
6126 else
c0f3af97
L		 6127 {
6128 if (i.types[0].bitfield.imm8)
6129 source = 1;
6130 else
6131 source = 0;
6132 }
c0f3af97
L		 6133 break;
6134 case 5:
43234a1e
L		 6135 if (i.tm.opcode_modifier.evex)
6136 {
6137 /* For EVEX instructions, when there are 5 operands, the
6138 first one must be immediate operand. If the second one
6139 is immediate operand, the source operand is the 3th
6140 one. If the last one is immediate operand, the source
6141 operand is the 2nd one. */
6142 gas_assert (i.imm_operands == 2
6143 && i.tm.opcode_modifier.sae
6144 && operand_type_check (i.types[0], imm));
6145 if (operand_type_check (i.types[1], imm))
6146 source = 2;
6147 else if (operand_type_check (i.types[4], imm))
6148 source = 1;
6149 else
6150 abort ();
6151 }
cab737b9
L		 6152 break;
6153 default:
6154 abort ();
6155 }
6156
c0f3af97
L		 6157 if (!vex_3_sources)
6158 {
6159 dest = source + 1;
6160
43234a1e
L		 6161 /* RC/SAE operand could be between DEST and SRC. That happens
6162 when one operand is GPR and the other one is XMM/YMM/ZMM
6163 register. */
6164 if (i.rounding && i.rounding->operand == (int) dest)
6165 dest++;
6166
2426c15f 6167 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6168 {
43234a1e
L		 6169 /* For instructions with VexNDS, the register-only source
6170 operand must be 32/64bit integer, XMM, YMM or ZMM
6171 register. It is encoded in VEX prefix. We need to
6172 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6173
6174 i386_operand_type op;
6175 unsigned int vvvv;
6176
6177 /* Check register-only source operand when two source
6178 operands are swapped. */
6179 if (!i.tm.operand_types[source].bitfield.baseindex
6180 && i.tm.operand_types[dest].bitfield.baseindex)
6181 {
6182 vvvv = source;
6183 source = dest;
6184 }
6185 else
6186 vvvv = dest;
6187
6188 op = i.tm.operand_types[vvvv];
fa99fab2 6189 op.bitfield.regmem = 0;
c0f3af97 6190 if ((dest + 1) >= i.operands
ac4eb736
AM		 6191 || (!op.bitfield.reg32
6192 && op.bitfield.reg64
f12dc422 6193 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6194 && !operand_type_equal (&op, &regymm)
6195 && !operand_type_equal (&op, &regzmm)
6196 && !operand_type_equal (&op, &regmask)))
c0f3af97 6197 abort ();
f12dc422 6198 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6199 dest++;
6200 }
6201 }
29b0f896
AM		 6202
6203 i.rm.mode = 3;
6204 /* One of the register operands will be encoded in the i.tm.reg
6205 field, the other in the combined i.tm.mode and i.tm.regmem
6206 fields. If no form of this instruction supports a memory
6207 destination operand, then we assume the source operand may
6208 sometimes be a memory operand and so we need to store the
6209 destination in the i.rm.reg field. */
40fb9820
L		 6210 if (!i.tm.operand_types[dest].bitfield.regmem
6211 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6212 {
6213 i.rm.reg = i.op[dest].regs->reg_num;
6214 i.rm.regmem = i.op[source].regs->reg_num;
6215 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6216 i.rex |= REX_R;
43234a1e
L		 6217 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6218 i.vrex |= REX_R;
29b0f896 6219 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6220 i.rex |= REX_B;
43234a1e
L		 6221 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6222 i.vrex |= REX_B;
29b0f896
AM		 6223 }
6224 else
6225 {
6226 i.rm.reg = i.op[source].regs->reg_num;
6227 i.rm.regmem = i.op[dest].regs->reg_num;
6228 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6229 i.rex |= REX_B;
43234a1e
L		 6230 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6231 i.vrex |= REX_B;
29b0f896 6232 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6233 i.rex |= REX_R;
43234a1e
L		 6234 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6235 i.vrex |= REX_R;
29b0f896 6236 }
161a04f6 6237 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6238 {
40fb9820
L		 6239 if (!i.types[0].bitfield.control
6240 && !i.types[1].bitfield.control)
c4a530c5 6241 abort ();
161a04f6 6242 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6243 add_prefix (LOCK_PREFIX_OPCODE);
6244 }
29b0f896
AM		 6245 }
6246 else
6247 { /* If it's not 2 reg operands... */
c0f3af97
L		 6248 unsigned int mem;
6249
29b0f896
AM		 6250 if (i.mem_operands)
6251 {
6252 unsigned int fake_zero_displacement = 0;
99018f42 6253 unsigned int op;
4eed87de 6254
7ab9ffdd
L		 6255 for (op = 0; op < i.operands; op++)
6256 if (operand_type_check (i.types[op], anymem))
6257 break;
7ab9ffdd 6258 gas_assert (op < i.operands);
29b0f896 6259
6c30d220
L		 6260 if (i.tm.opcode_modifier.vecsib)
6261 {
6262 if (i.index_reg->reg_num == RegEiz
6263 || i.index_reg->reg_num == RegRiz)
6264 abort ();
6265
6266 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6267 if (!i.base_reg)
6268 {
6269 i.sib.base = NO_BASE_REGISTER;
6270 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6271 /* No Vec_Disp8 if there is no base. */
6272 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6273 i.types[op].bitfield.disp8 = 0;
6274 i.types[op].bitfield.disp16 = 0;
6275 i.types[op].bitfield.disp64 = 0;
6276 if (flag_code != CODE_64BIT)
6277 {
6278 /* Must be 32 bit */
6279 i.types[op].bitfield.disp32 = 1;
6280 i.types[op].bitfield.disp32s = 0;
6281 }
6282 else
6283 {
6284 i.types[op].bitfield.disp32 = 0;
6285 i.types[op].bitfield.disp32s = 1;
6286 }
6287 }
6288 i.sib.index = i.index_reg->reg_num;
6289 if ((i.index_reg->reg_flags & RegRex) != 0)
6290 i.rex |= REX_X;
43234a1e
L		 6291 if ((i.index_reg->reg_flags & RegVRex) != 0)
6292 i.vrex |= REX_X;
6c30d220
L		 6293 }
6294
29b0f896
AM		 6295 default_seg = &ds;
6296
6297 if (i.base_reg == 0)
6298 {
6299 i.rm.mode = 0;
6300 if (!i.disp_operands)
6c30d220
L		 6301 {
6302 fake_zero_displacement = 1;
6303 /* Instructions with VSIB byte need 32bit displacement
6304 if there is no base register. */
6305 if (i.tm.opcode_modifier.vecsib)
6306 i.types[op].bitfield.disp32 = 1;
6307 }
29b0f896
AM		 6308 if (i.index_reg == 0)
6309 {
6c30d220 6310 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6311 /* Operand is just <disp> */
20f0a1fc 6312 if (flag_code == CODE_64BIT)
29b0f896
AM		 6313 {
6314 /* 64bit mode overwrites the 32bit absolute
6315 addressing by RIP relative addressing and
6316 absolute addressing is encoded by one of the
6317 redundant SIB forms. */
6318 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6319 i.sib.base = NO_BASE_REGISTER;
6320 i.sib.index = NO_INDEX_REGISTER;
fc225355 6321 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6322 ? disp32s : disp32);
20f0a1fc 6323 }
fc225355
L		 6324 else if ((flag_code == CODE_16BIT)
6325 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6326 {
6327 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6328 i.types[op] = disp16;
20f0a1fc
NC		 6329 }
6330 else
6331 {
6332 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6333 i.types[op] = disp32;
29b0f896
AM		 6334 }
6335 }
6c30d220 6336 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6337 {
6c30d220 6338 /* !i.base_reg && i.index_reg */
db51cc60
L		 6339 if (i.index_reg->reg_num == RegEiz
6340 || i.index_reg->reg_num == RegRiz)
6341 i.sib.index = NO_INDEX_REGISTER;
6342 else
6343 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6344 i.sib.base = NO_BASE_REGISTER;
6345 i.sib.scale = i.log2_scale_factor;
6346 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6347 /* No Vec_Disp8 if there is no base. */
6348 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6349 i.types[op].bitfield.disp8 = 0;
6350 i.types[op].bitfield.disp16 = 0;
6351 i.types[op].bitfield.disp64 = 0;
29b0f896 6352 if (flag_code != CODE_64BIT)
40fb9820
L		 6353 {
6354 /* Must be 32 bit */
6355 i.types[op].bitfield.disp32 = 1;
6356 i.types[op].bitfield.disp32s = 0;
6357 }
29b0f896 6358 else
40fb9820
L		 6359 {
6360 i.types[op].bitfield.disp32 = 0;
6361 i.types[op].bitfield.disp32s = 1;
6362 }
29b0f896 6363 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6364 i.rex |= REX_X;
29b0f896
AM		 6365 }
6366 }
6367 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6368 else if (i.base_reg->reg_num == RegRip ||
6369 i.base_reg->reg_num == RegEip)
29b0f896 6370 {
6c30d220 6371 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6372 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6373 i.types[op].bitfield.disp8 = 0;
6374 i.types[op].bitfield.disp16 = 0;
6375 i.types[op].bitfield.disp32 = 0;
6376 i.types[op].bitfield.disp32s = 1;
6377 i.types[op].bitfield.disp64 = 0;
43234a1e 6378 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6379 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6380 if (! i.disp_operands)
6381 fake_zero_displacement = 1;
29b0f896 6382 }
40fb9820 6383 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6384 {
6c30d220 6385 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6386 switch (i.base_reg->reg_num)
6387 {
6388 case 3: /* (%bx) */
6389 if (i.index_reg == 0)
6390 i.rm.regmem = 7;
6391 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6392 i.rm.regmem = i.index_reg->reg_num - 6;
6393 break;
6394 case 5: /* (%bp) */
6395 default_seg = &ss;
6396 if (i.index_reg == 0)
6397 {
6398 i.rm.regmem = 6;
40fb9820 6399 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6400 {
6401 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6402 if (i.tm.operand_types[op].bitfield.vec_disp8)
6403 i.types[op].bitfield.vec_disp8 = 1;
6404 else
6405 i.types[op].bitfield.disp8 = 1;
252b5132 6406 fake_zero_displacement = 1;
29b0f896
AM		 6407 }
6408 }
6409 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6410 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6411 break;
6412 default: /* (%si) -> 4 or (%di) -> 5 */
6413 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6414 }
6415 i.rm.mode = mode_from_disp_size (i.types[op]);
6416 }
6417 else /* i.base_reg and 32/64 bit mode */
6418 {
6419 if (flag_code == CODE_64BIT
40fb9820
L		 6420 && operand_type_check (i.types[op], disp))
6421 {
6422 i386_operand_type temp;
0dfbf9d7 6423 operand_type_set (&temp, 0);
40fb9820 6424 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6425 temp.bitfield.vec_disp8
6426 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6427 i.types[op] = temp;
6428 if (i.prefix[ADDR_PREFIX] == 0)
6429 i.types[op].bitfield.disp32s = 1;
6430 else
6431 i.types[op].bitfield.disp32 = 1;
6432 }
20f0a1fc 6433
6c30d220
L		 6434 if (!i.tm.opcode_modifier.vecsib)
6435 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6436 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6437 i.rex |= REX_B;
29b0f896
AM		 6438 i.sib.base = i.base_reg->reg_num;
6439 /* x86-64 ignores REX prefix bit here to avoid decoder
6440 complications. */
848930b2
JB		 6441 if (!(i.base_reg->reg_flags & RegRex)
6442 && (i.base_reg->reg_num == EBP_REG_NUM
6443 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6444 default_seg = &ss;
848930b2 6445 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6446 {
848930b2 6447 fake_zero_displacement = 1;
43234a1e
L		 6448 if (i.tm.operand_types [op].bitfield.vec_disp8)
6449 i.types[op].bitfield.vec_disp8 = 1;
6450 else
6451 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6452 }
6453 i.sib.scale = i.log2_scale_factor;
6454 if (i.index_reg == 0)
6455 {
6c30d220 6456 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6457 /* <disp>(%esp) becomes two byte modrm with no index
6458 register. We've already stored the code for esp
6459 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6460 Any base register besides %esp will not use the
6461 extra modrm byte. */
6462 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6463 }
6c30d220 6464 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6465 {
db51cc60
L		 6466 if (i.index_reg->reg_num == RegEiz
6467 || i.index_reg->reg_num == RegRiz)
6468 i.sib.index = NO_INDEX_REGISTER;
6469 else
6470 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6471 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6472 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6473 i.rex |= REX_X;
29b0f896 6474 }
67a4f2b7
AO		 6475
6476 if (i.disp_operands
6477 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6478 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6479 i.rm.mode = 0;
6480 else
a501d77e
L		 6481 {
6482 if (!fake_zero_displacement
6483 && !i.disp_operands
6484 && i.disp_encoding)
6485 {
6486 fake_zero_displacement = 1;
6487 if (i.disp_encoding == disp_encoding_8bit)
6488 i.types[op].bitfield.disp8 = 1;
6489 else
6490 i.types[op].bitfield.disp32 = 1;
6491 }
6492 i.rm.mode = mode_from_disp_size (i.types[op]);
6493 }
29b0f896 6494 }
252b5132 6495
29b0f896
AM		 6496 if (fake_zero_displacement)
6497 {
6498 /* Fakes a zero displacement assuming that i.types[op]
6499 holds the correct displacement size. */
6500 expressionS *exp;
6501
9c2799c2 6502 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6503 exp = &disp_expressions[i.disp_operands++];
6504 i.op[op].disps = exp;
6505 exp->X_op = O_constant;
6506 exp->X_add_number = 0;
6507 exp->X_add_symbol = (symbolS *) 0;
6508 exp->X_op_symbol = (symbolS *) 0;
6509 }
c0f3af97
L		 6510
6511 mem = op;
29b0f896 6512 }
c0f3af97
L		 6513 else
6514 mem = ~0;
252b5132 6515
8c43a48b 6516 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6517 {
6518 if (operand_type_check (i.types[0], imm))
6519 i.vex.register_specifier = NULL;
6520 else
6521 {
6522 /* VEX.vvvv encodes one of the sources when the first
6523 operand is not an immediate. */
1ef99a7b 6524 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6525 i.vex.register_specifier = i.op[0].regs;
6526 else
6527 i.vex.register_specifier = i.op[1].regs;
6528 }
6529
6530 /* Destination is a XMM register encoded in the ModRM.reg
6531 and VEX.R bit. */
6532 i.rm.reg = i.op[2].regs->reg_num;
6533 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6534 i.rex |= REX_R;
6535
6536 /* ModRM.rm and VEX.B encodes the other source. */
6537 if (!i.mem_operands)
6538 {
6539 i.rm.mode = 3;
6540
1ef99a7b 6541 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6542 i.rm.regmem = i.op[1].regs->reg_num;
6543 else
6544 i.rm.regmem = i.op[0].regs->reg_num;
6545
6546 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6547 i.rex |= REX_B;
6548 }
6549 }
2426c15f 6550 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6551 {
6552 i.vex.register_specifier = i.op[2].regs;
6553 if (!i.mem_operands)
6554 {
6555 i.rm.mode = 3;
6556 i.rm.regmem = i.op[1].regs->reg_num;
6557 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6558 i.rex |= REX_B;
6559 }
6560 }
29b0f896
AM		 6561 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6562 (if any) based on i.tm.extension_opcode. Again, we must be
6563 careful to make sure that segment/control/debug/test/MMX
6564 registers are coded into the i.rm.reg field. */
f88c9eb0 6565 else if (i.reg_operands)
29b0f896 6566 {
99018f42 6567 unsigned int op;
7ab9ffdd
L		 6568 unsigned int vex_reg = ~0;
6569
6570 for (op = 0; op < i.operands; op++)
6571 if (i.types[op].bitfield.reg8
6572 || i.types[op].bitfield.reg16
6573 || i.types[op].bitfield.reg32
6574 || i.types[op].bitfield.reg64
6575 || i.types[op].bitfield.regmmx
6576 || i.types[op].bitfield.regxmm
6577 || i.types[op].bitfield.regymm
7e8b059b 6578 || i.types[op].bitfield.regbnd
43234a1e
L		 6579 || i.types[op].bitfield.regzmm
6580 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6581 || i.types[op].bitfield.sreg2
6582 || i.types[op].bitfield.sreg3
6583 || i.types[op].bitfield.control
6584 || i.types[op].bitfield.debug
6585 || i.types[op].bitfield.test)
6586 break;
c0209578 6587
7ab9ffdd
L		 6588 if (vex_3_sources)
6589 op = dest;
2426c15f 6590 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6591 {
6592 /* For instructions with VexNDS, the register-only
6593 source operand is encoded in VEX prefix. */
6594 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6595
7ab9ffdd 6596 if (op > mem)
c0f3af97 6597 {
7ab9ffdd
L		 6598 vex_reg = op++;
6599 gas_assert (op < i.operands);
c0f3af97
L		 6600 }
6601 else
c0f3af97 6602 {
f12dc422
L		 6603 /* Check register-only source operand when two source
6604 operands are swapped. */
6605 if (!i.tm.operand_types[op].bitfield.baseindex
6606 && i.tm.operand_types[op + 1].bitfield.baseindex)
6607 {
6608 vex_reg = op;
6609 op += 2;
6610 gas_assert (mem == (vex_reg + 1)
6611 && op < i.operands);
6612 }
6613 else
6614 {
6615 vex_reg = op + 1;
6616 gas_assert (vex_reg < i.operands);
6617 }
c0f3af97 6618 }
7ab9ffdd 6619 }
2426c15f 6620 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6621 {
f12dc422 6622 /* For instructions with VexNDD, the register destination
7ab9ffdd 6623 is encoded in VEX prefix. */
f12dc422
L		 6624 if (i.mem_operands == 0)
6625 {
6626 /* There is no memory operand. */
6627 gas_assert ((op + 2) == i.operands);
6628 vex_reg = op + 1;
6629 }
6630 else
8d63c93e 6631 {
f12dc422
L		 6632 /* There are only 2 operands. */
6633 gas_assert (op < 2 && i.operands == 2);
6634 vex_reg = 1;
6635 }
7ab9ffdd
L		 6636 }
6637 else
6638 gas_assert (op < i.operands);
99018f42 6639
7ab9ffdd
L		 6640 if (vex_reg != (unsigned int) ~0)
6641 {
f12dc422 6642 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6643
f12dc422
L		 6644 if (type->bitfield.reg32 != 1
6645 && type->bitfield.reg64 != 1
6646 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6647 && !operand_type_equal (type, &regymm)
6648 && !operand_type_equal (type, &regzmm)
6649 && !operand_type_equal (type, &regmask))
7ab9ffdd 6650 abort ();
f88c9eb0 6651
7ab9ffdd
L		 6652 i.vex.register_specifier = i.op[vex_reg].regs;
6653 }
6654
1b9f0c97
L		 6655 /* Don't set OP operand twice. */
6656 if (vex_reg != op)
7ab9ffdd 6657 {
1b9f0c97
L		 6658 /* If there is an extension opcode to put here, the
6659 register number must be put into the regmem field. */
6660 if (i.tm.extension_opcode != None)
6661 {
6662 i.rm.regmem = i.op[op].regs->reg_num;
6663 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6664 i.rex |= REX_B;
43234a1e
L		 6665 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6666 i.vrex |= REX_B;
1b9f0c97
L		 6667 }
6668 else
6669 {
6670 i.rm.reg = i.op[op].regs->reg_num;
6671 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6672 i.rex |= REX_R;
43234a1e
L		 6673 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6674 i.vrex |= REX_R;
1b9f0c97 6675 }
7ab9ffdd 6676 }
252b5132 6677
29b0f896
AM		 6678 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6679 must set it to 3 to indicate this is a register operand
6680 in the regmem field. */
6681 if (!i.mem_operands)
6682 i.rm.mode = 3;
6683 }
252b5132 6684
29b0f896 6685 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6686 if (i.tm.extension_opcode != None)
29b0f896
AM		 6687 i.rm.reg = i.tm.extension_opcode;
6688 }
6689 return default_seg;
6690}
252b5132 6691
29b0f896 6692static void
e3bb37b5 6693output_branch (void)
29b0f896
AM		 6694{
6695 char *p;
f8a5c266 6696 int size;
29b0f896
AM		 6697 int code16;
6698 int prefix;
6699 relax_substateT subtype;
6700 symbolS *sym;
6701 offsetT off;
6702
f8a5c266 6703 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6704 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6705
6706 prefix = 0;
6707 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6708 {
29b0f896
AM		 6709 prefix = 1;
6710 i.prefixes -= 1;
6711 code16 ^= CODE16;
252b5132 6712 }
29b0f896
AM		 6713 /* Pentium4 branch hints. */
6714 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6715 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6716 {
29b0f896
AM		 6717 prefix++;
6718 i.prefixes--;
6719 }
6720 if (i.prefix[REX_PREFIX] != 0)
6721 {
6722 prefix++;
6723 i.prefixes--;
2f66722d
AM		 6724 }
6725
7e8b059b
L		 6726 /* BND prefixed jump. */
6727 if (i.prefix[BND_PREFIX] != 0)
6728 {
6729 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6730 i.prefixes -= 1;
6731 }
6732
29b0f896
AM		 6733 if (i.prefixes != 0 && !intel_syntax)
6734 as_warn (_("skipping prefixes on this instruction"));
6735
6736 /* It's always a symbol; End frag & setup for relax.
6737 Make sure there is enough room in this frag for the largest
6738 instruction we may generate in md_convert_frag. This is 2
6739 bytes for the opcode and room for the prefix and largest
6740 displacement. */
6741 frag_grow (prefix + 2 + 4);
6742 /* Prefix and 1 opcode byte go in fr_fix. */
6743 p = frag_more (prefix + 1);
6744 if (i.prefix[DATA_PREFIX] != 0)
6745 *p++ = DATA_PREFIX_OPCODE;
6746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6748 *p++ = i.prefix[SEG_PREFIX];
6749 if (i.prefix[REX_PREFIX] != 0)
6750 *p++ = i.prefix[REX_PREFIX];
6751 *p = i.tm.base_opcode;
6752
6753 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6754 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6755 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6756 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6757 else
f8a5c266 6758 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6759 subtype |= code16;
3e73aa7c 6760
29b0f896
AM		 6761 sym = i.op[0].disps->X_add_symbol;
6762 off = i.op[0].disps->X_add_number;
3e73aa7c 6763
29b0f896
AM		 6764 if (i.op[0].disps->X_op != O_constant
6765 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6766 {
29b0f896
AM		 6767 /* Handle complex expressions. */
6768 sym = make_expr_symbol (i.op[0].disps);
6769 off = 0;
6770 }
3e73aa7c 6771
29b0f896
AM		 6772 /* 1 possible extra opcode + 4 byte displacement go in var part.
6773 Pass reloc in fr_var. */
d258b828 6774 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6775}
3e73aa7c 6776
29b0f896 6777static void
e3bb37b5 6778output_jump (void)
29b0f896
AM		 6779{
6780 char *p;
6781 int size;
3e02c1cc 6782 fixS *fixP;
29b0f896 6783
40fb9820 6784 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6785 {
6786 /* This is a loop or jecxz type instruction. */
6787 size = 1;
6788 if (i.prefix[ADDR_PREFIX] != 0)
6789 {
6790 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6791 i.prefixes -= 1;
6792 }
6793 /* Pentium4 branch hints. */
6794 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6795 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6796 {
6797 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6798 i.prefixes--;
3e73aa7c
JH		 6799 }
6800 }
29b0f896
AM		 6801 else
6802 {
6803 int code16;
3e73aa7c 6804
29b0f896
AM		 6805 code16 = 0;
6806 if (flag_code == CODE_16BIT)
6807 code16 = CODE16;
3e73aa7c 6808
29b0f896
AM		 6809 if (i.prefix[DATA_PREFIX] != 0)
6810 {
6811 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6812 i.prefixes -= 1;
6813 code16 ^= CODE16;
6814 }
252b5132 6815
29b0f896
AM		 6816 size = 4;
6817 if (code16)
6818 size = 2;
6819 }
9fcc94b6 6820
29b0f896
AM		 6821 if (i.prefix[REX_PREFIX] != 0)
6822 {
6823 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6824 i.prefixes -= 1;
6825 }
252b5132 6826
7e8b059b
L		 6827 /* BND prefixed jump. */
6828 if (i.prefix[BND_PREFIX] != 0)
6829 {
6830 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6831 i.prefixes -= 1;
6832 }
6833
29b0f896
AM		 6834 if (i.prefixes != 0 && !intel_syntax)
6835 as_warn (_("skipping prefixes on this instruction"));
e0890092 6836
42164a71
L		 6837 p = frag_more (i.tm.opcode_length + size);
6838 switch (i.tm.opcode_length)
6839 {
6840 case 2:
6841 *p++ = i.tm.base_opcode >> 8;
6842 case 1:
6843 *p++ = i.tm.base_opcode;
6844 break;
6845 default:
6846 abort ();
6847 }
e0890092 6848
3e02c1cc 6849 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6850 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6851
6852 /* All jumps handled here are signed, but don't use a signed limit
6853 check for 32 and 16 bit jumps as we want to allow wrap around at
6854 4G and 64k respectively. */
6855 if (size == 1)
6856 fixP->fx_signed = 1;
29b0f896 6857}
e0890092 6858
29b0f896 6859static void
e3bb37b5 6860output_interseg_jump (void)
29b0f896
AM		 6861{
6862 char *p;
6863 int size;
6864 int prefix;
6865 int code16;
252b5132 6866
29b0f896
AM		 6867 code16 = 0;
6868 if (flag_code == CODE_16BIT)
6869 code16 = CODE16;
a217f122 6870
29b0f896
AM		 6871 prefix = 0;
6872 if (i.prefix[DATA_PREFIX] != 0)
6873 {
6874 prefix = 1;
6875 i.prefixes -= 1;
6876 code16 ^= CODE16;
6877 }
6878 if (i.prefix[REX_PREFIX] != 0)
6879 {
6880 prefix++;
6881 i.prefixes -= 1;
6882 }
252b5132 6883
29b0f896
AM		 6884 size = 4;
6885 if (code16)
6886 size = 2;
252b5132 6887
29b0f896
AM		 6888 if (i.prefixes != 0 && !intel_syntax)
6889 as_warn (_("skipping prefixes on this instruction"));
252b5132 6890
29b0f896
AM		 6891 /* 1 opcode; 2 segment; offset */
6892 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6893
29b0f896
AM		 6894 if (i.prefix[DATA_PREFIX] != 0)
6895 *p++ = DATA_PREFIX_OPCODE;
252b5132 6896
29b0f896
AM		 6897 if (i.prefix[REX_PREFIX] != 0)
6898 *p++ = i.prefix[REX_PREFIX];
252b5132 6899
29b0f896
AM		 6900 *p++ = i.tm.base_opcode;
6901 if (i.op[1].imms->X_op == O_constant)
6902 {
6903 offsetT n = i.op[1].imms->X_add_number;
252b5132 6904
29b0f896
AM		 6905 if (size == 2
6906 && !fits_in_unsigned_word (n)
6907 && !fits_in_signed_word (n))
6908 {
6909 as_bad (_("16-bit jump out of range"));
6910 return;
6911 }
6912 md_number_to_chars (p, n, size);
6913 }
6914 else
6915 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6916 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6917 if (i.op[0].imms->X_op != O_constant)
6918 as_bad (_("can't handle non absolute segment in `%s'"),
6919 i.tm.name);
6920 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6921}
a217f122 6922
29b0f896 6923static void
e3bb37b5 6924output_insn (void)
29b0f896 6925{
2bbd9c25
JJ		 6926 fragS *insn_start_frag;
6927 offsetT insn_start_off;
6928
29b0f896
AM		 6929 /* Tie dwarf2 debug info to the address at the start of the insn.
6930 We can't do this after the insn has been output as the current
6931 frag may have been closed off. eg. by frag_var. */
6932 dwarf2_emit_insn (0);
6933
2bbd9c25
JJ		 6934 insn_start_frag = frag_now;
6935 insn_start_off = frag_now_fix ();
6936
29b0f896 6937 /* Output jumps. */
40fb9820 6938 if (i.tm.opcode_modifier.jump)
29b0f896 6939 output_branch ();
40fb9820
L		 6940 else if (i.tm.opcode_modifier.jumpbyte
6941 || i.tm.opcode_modifier.jumpdword)
29b0f896 6942 output_jump ();
40fb9820 6943 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6944 output_interseg_jump ();
6945 else
6946 {
6947 /* Output normal instructions here. */
6948 char *p;
6949 unsigned char *q;
47465058 6950 unsigned int j;
331d2d0d 6951 unsigned int prefix;
4dffcebc 6952
d022bddd
IT		 6953 /* Some processors fail on LOCK prefix. This options makes
6954 assembler ignore LOCK prefix and serves as a workaround. */
6955 if (omit_lock_prefix)
6956 {
6957 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6958 return;
6959 i.prefix[LOCK_PREFIX] = 0;
6960 }
6961
43234a1e
L		 6962 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6963 don't need the explicit prefix. */
6964 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6965 {
c0f3af97 6966 switch (i.tm.opcode_length)
bc4bd9ab 6967 {
c0f3af97
L		 6968 case 3:
6969 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6970 {
c0f3af97
L		 6971 prefix = (i.tm.base_opcode >> 24) & 0xff;
6972 goto check_prefix;
6973 }
6974 break;
6975 case 2:
6976 if ((i.tm.base_opcode & 0xff0000) != 0)
6977 {
6978 prefix = (i.tm.base_opcode >> 16) & 0xff;
6979 if (i.tm.cpu_flags.bitfield.cpupadlock)
6980 {
4dffcebc 6981check_prefix:
c0f3af97 6982 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6983 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6984 != REPE_PREFIX_OPCODE))
6985 add_prefix (prefix);
6986 }
6987 else
4dffcebc
L		 6988 add_prefix (prefix);
6989 }
c0f3af97
L		 6990 break;
6991 case 1:
6992 break;
6993 default:
6994 abort ();
bc4bd9ab 6995 }
c0f3af97 6996
6d19a37a 6997#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6998 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6999 R_X86_64_GOTTPOFF relocation so that linker can safely
7000 perform IE->LE optimization. */
7001 if (x86_elf_abi == X86_64_X32_ABI
7002 && i.operands == 2
7003 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7004 && i.prefix[REX_PREFIX] == 0)
7005 add_prefix (REX_OPCODE);
6d19a37a 7006#endif
cf61b747 7007
c0f3af97
L		 7008 /* The prefix bytes. */
7009 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7010 if (*q)
7011 FRAG_APPEND_1_CHAR (*q);
0f10071e 7012 }
ae5c1c7b 7013 else
c0f3af97
L		 7014 {
7015 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7016 if (*q)
7017 switch (j)
7018 {
7019 case REX_PREFIX:
7020 /* REX byte is encoded in VEX prefix. */
7021 break;
7022 case SEG_PREFIX:
7023 case ADDR_PREFIX:
7024 FRAG_APPEND_1_CHAR (*q);
7025 break;
7026 default:
7027 /* There should be no other prefixes for instructions
7028 with VEX prefix. */
7029 abort ();
7030 }
7031
43234a1e
L		 7032 /* For EVEX instructions i.vrex should become 0 after
7033 build_evex_prefix. For VEX instructions upper 16 registers
7034 aren't available, so VREX should be 0. */
7035 if (i.vrex)
7036 abort ();
c0f3af97
L		 7037 /* Now the VEX prefix. */
7038 p = frag_more (i.vex.length);
7039 for (j = 0; j < i.vex.length; j++)
7040 p[j] = i.vex.bytes[j];
7041 }
252b5132 7042
29b0f896 7043 /* Now the opcode; be careful about word order here! */
4dffcebc 7044 if (i.tm.opcode_length == 1)
29b0f896
AM		 7045 {
7046 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7047 }
7048 else
7049 {
4dffcebc 7050 switch (i.tm.opcode_length)
331d2d0d 7051 {
43234a1e
L		 7052 case 4:
7053 p = frag_more (4);
7054 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7055 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7056 break;
4dffcebc 7057 case 3:
331d2d0d
L		 7058 p = frag_more (3);
7059 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7060 break;
7061 case 2:
7062 p = frag_more (2);
7063 break;
7064 default:
7065 abort ();
7066 break;
331d2d0d 7067 }
0f10071e 7068
29b0f896
AM		 7069 /* Put out high byte first: can't use md_number_to_chars! */
7070 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7071 *p = i.tm.base_opcode & 0xff;
7072 }
3e73aa7c 7073
29b0f896 7074 /* Now the modrm byte and sib byte (if present). */
40fb9820 7075 if (i.tm.opcode_modifier.modrm)
29b0f896 7076 {
4a3523fa
L		 7077 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7078 | i.rm.reg << 3
7079 | i.rm.mode << 6));
29b0f896
AM		 7080 /* If i.rm.regmem == ESP (4)
7081 && i.rm.mode != (Register mode)
7082 && not 16 bit
7083 ==> need second modrm byte. */
7084 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7085 && i.rm.mode != 3
40fb9820 7086 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7087 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7088 | i.sib.index << 3
7089 | i.sib.scale << 6));
29b0f896 7090 }
3e73aa7c 7091
29b0f896 7092 if (i.disp_operands)
2bbd9c25 7093 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7094
29b0f896 7095 if (i.imm_operands)
2bbd9c25 7096 output_imm (insn_start_frag, insn_start_off);
29b0f896 7097 }
252b5132 7098
29b0f896
AM		 7099#ifdef DEBUG386
7100 if (flag_debug)
7101 {
7b81dfbb 7102 pi ("" /*line*/, &i);
29b0f896
AM		 7103 }
7104#endif /* DEBUG386 */
7105}
252b5132 7106
e205caa7
L		 7107/* Return the size of the displacement operand N. */
7108
7109static int
7110disp_size (unsigned int n)
7111{
7112 int size = 4;
43234a1e
L		 7113
7114 /* Vec_Disp8 has to be 8bit. */
7115 if (i.types[n].bitfield.vec_disp8)
7116 size = 1;
7117 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7118 size = 8;
7119 else if (i.types[n].bitfield.disp8)
7120 size = 1;
7121 else if (i.types[n].bitfield.disp16)
7122 size = 2;
e205caa7
L		 7123 return size;
7124}
7125
7126/* Return the size of the immediate operand N. */
7127
7128static int
7129imm_size (unsigned int n)
7130{
7131 int size = 4;
40fb9820
L		 7132 if (i.types[n].bitfield.imm64)
7133 size = 8;
7134 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7135 size = 1;
7136 else if (i.types[n].bitfield.imm16)
7137 size = 2;
e205caa7
L		 7138 return size;
7139}
7140
29b0f896 7141static void
64e74474 7142output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7143{
7144 char *p;
7145 unsigned int n;
252b5132 7146
29b0f896
AM		 7147 for (n = 0; n < i.operands; n++)
7148 {
43234a1e
L		 7149 if (i.types[n].bitfield.vec_disp8
7150 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7151 {
7152 if (i.op[n].disps->X_op == O_constant)
7153 {
e205caa7 7154 int size = disp_size (n);
43234a1e 7155 offsetT val = i.op[n].disps->X_add_number;
252b5132 7156
43234a1e
L		 7157 if (i.types[n].bitfield.vec_disp8)
7158 val >>= i.memshift;
7159 val = offset_in_range (val, size);
29b0f896
AM		 7160 p = frag_more (size);
7161 md_number_to_chars (p, val, size);
7162 }
7163 else
7164 {
f86103b7 7165 enum bfd_reloc_code_real reloc_type;
e205caa7 7166 int size = disp_size (n);
40fb9820 7167 int sign = i.types[n].bitfield.disp32s;
29b0f896 7168 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7169 fixS *fixP;
29b0f896 7170
e205caa7 7171 /* We can't have 8 bit displacement here. */
9c2799c2 7172 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7173
29b0f896
AM		 7174 /* The PC relative address is computed relative
7175 to the instruction boundary, so in case immediate
7176 fields follows, we need to adjust the value. */
7177 if (pcrel && i.imm_operands)
7178 {
29b0f896 7179 unsigned int n1;
e205caa7 7180 int sz = 0;
252b5132 7181
29b0f896 7182 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7183 if (operand_type_check (i.types[n1], imm))
252b5132 7184 {
e205caa7
L		 7185 /* Only one immediate is allowed for PC
7186 relative address. */
9c2799c2 7187 gas_assert (sz == 0);
e205caa7
L		 7188 sz = imm_size (n1);
7189 i.op[n].disps->X_add_number -= sz;
252b5132 7190 }
29b0f896 7191 /* We should find the immediate. */
9c2799c2 7192 gas_assert (sz != 0);
29b0f896 7193 }
520dc8e8 7194
29b0f896 7195 p = frag_more (size);
d258b828 7196 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7197 if (GOT_symbol
2bbd9c25 7198 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7199 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7200 || reloc_type == BFD_RELOC_X86_64_32S
7201 || (reloc_type == BFD_RELOC_64
7202 && object_64bit))
d6ab8113
JB		 7203 && (i.op[n].disps->X_op == O_symbol
7204 || (i.op[n].disps->X_op == O_add
7205 && ((symbol_get_value_expression
7206 (i.op[n].disps->X_op_symbol)->X_op)
7207 == O_subtract))))
7208 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7209 {
7210 offsetT add;
7211
7212 if (insn_start_frag == frag_now)
7213 add = (p - frag_now->fr_literal) - insn_start_off;
7214 else
7215 {
7216 fragS *fr;
7217
7218 add = insn_start_frag->fr_fix - insn_start_off;
7219 for (fr = insn_start_frag->fr_next;
7220 fr && fr != frag_now; fr = fr->fr_next)
7221 add += fr->fr_fix;
7222 add += p - frag_now->fr_literal;
7223 }
7224
4fa24527 7225 if (!object_64bit)
7b81dfbb
AJ		 7226 {
7227 reloc_type = BFD_RELOC_386_GOTPC;
7228 i.op[n].imms->X_add_number += add;
7229 }
7230 else if (reloc_type == BFD_RELOC_64)
7231 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7232 else
7b81dfbb
AJ		 7233 /* Don't do the adjustment for x86-64, as there
7234 the pcrel addressing is relative to the _next_
7235 insn, and that is taken care of in other code. */
d6ab8113 7236 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7237 }
02a86693
L		 7238 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7239 size, i.op[n].disps, pcrel,
7240 reloc_type);
7241 /* Check for "call/jmp *mem", "mov mem, %reg",
7242 "test %reg, mem" and "binop mem, %reg" where binop
7243 is one of adc, add, and, cmp, or, sbb, sub, xor
7244 instructions. */
7245 if ((i.rm.mode == 2
7246 || (i.rm.mode == 0 && i.rm.regmem == 5))
7247 && ((i.operands == 1
7248 && i.tm.base_opcode == 0xff
7249 && (i.rm.reg == 2 || i.rm.reg == 4))
7250 || (i.operands == 2
7251 && (i.tm.base_opcode == 0x8b
7252 || i.tm.base_opcode == 0x85
7253 || (i.tm.base_opcode & 0xc7) == 0x03))))
7254 {
7255 if (object_64bit)
7256 {
7257 fixP->fx_tcbit = i.rex != 0;
7258 if (i.base_reg
7259 && (i.base_reg->reg_num == RegRip
7260 || i.base_reg->reg_num == RegEip))
7261 fixP->fx_tcbit2 = 1;
7262 }
7263 else
7264 fixP->fx_tcbit2 = 1;
7265 }
29b0f896
AM		 7266 }
7267 }
7268 }
7269}
252b5132 7270
29b0f896 7271static void
64e74474 7272output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7273{
7274 char *p;
7275 unsigned int n;
252b5132 7276
29b0f896
AM		 7277 for (n = 0; n < i.operands; n++)
7278 {
43234a1e
L		 7279 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7280 if (i.rounding && (int) n == i.rounding->operand)
7281 continue;
7282
40fb9820 7283 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7284 {
7285 if (i.op[n].imms->X_op == O_constant)
7286 {
e205caa7 7287 int size = imm_size (n);
29b0f896 7288 offsetT val;
b4cac588 7289
29b0f896
AM		 7290 val = offset_in_range (i.op[n].imms->X_add_number,
7291 size);
7292 p = frag_more (size);
7293 md_number_to_chars (p, val, size);
7294 }
7295 else
7296 {
7297 /* Not absolute_section.
7298 Need a 32-bit fixup (don't support 8bit
7299 non-absolute imms). Try to support other
7300 sizes ... */
f86103b7 7301 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7302 int size = imm_size (n);
7303 int sign;
29b0f896 7304
40fb9820 7305 if (i.types[n].bitfield.imm32s
a7d61044 7306 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7307 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7308 sign = 1;
e205caa7
L		 7309 else
7310 sign = 0;
520dc8e8 7311
29b0f896 7312 p = frag_more (size);
d258b828 7313 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7314
2bbd9c25
JJ		 7315 /* This is tough to explain. We end up with this one if we
7316 * have operands that look like
7317 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7318 * obtain the absolute address of the GOT, and it is strongly
7319 * preferable from a performance point of view to avoid using
7320 * a runtime relocation for this. The actual sequence of
7321 * instructions often look something like:
7322 *
7323 * call .L66
7324 * .L66:
7325 * popl %ebx
7326 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7327 *
7328 * The call and pop essentially return the absolute address
7329 * of the label .L66 and store it in %ebx. The linker itself
7330 * will ultimately change the first operand of the addl so
7331 * that %ebx points to the GOT, but to keep things simple, the
7332 * .o file must have this operand set so that it generates not
7333 * the absolute address of .L66, but the absolute address of
7334 * itself. This allows the linker itself simply treat a GOTPC
7335 * relocation as asking for a pcrel offset to the GOT to be
7336 * added in, and the addend of the relocation is stored in the
7337 * operand field for the instruction itself.
7338 *
7339 * Our job here is to fix the operand so that it would add
7340 * the correct offset so that %ebx would point to itself. The
7341 * thing that is tricky is that .-.L66 will point to the
7342 * beginning of the instruction, so we need to further modify
7343 * the operand so that it will point to itself. There are
7344 * other cases where you have something like:
7345 *
7346 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7347 *
7348 * and here no correction would be required. Internally in
7349 * the assembler we treat operands of this form as not being
7350 * pcrel since the '.' is explicitly mentioned, and I wonder
7351 * whether it would simplify matters to do it this way. Who
7352 * knows. In earlier versions of the PIC patches, the
7353 * pcrel_adjust field was used to store the correction, but
7354 * since the expression is not pcrel, I felt it would be
7355 * confusing to do it this way. */
7356
d6ab8113 7357 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7358 || reloc_type == BFD_RELOC_X86_64_32S
7359 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7360 && GOT_symbol
7361 && GOT_symbol == i.op[n].imms->X_add_symbol
7362 && (i.op[n].imms->X_op == O_symbol
7363 || (i.op[n].imms->X_op == O_add
7364 && ((symbol_get_value_expression
7365 (i.op[n].imms->X_op_symbol)->X_op)
7366 == O_subtract))))
7367 {
2bbd9c25
JJ		 7368 offsetT add;
7369
7370 if (insn_start_frag == frag_now)
7371 add = (p - frag_now->fr_literal) - insn_start_off;
7372 else
7373 {
7374 fragS *fr;
7375
7376 add = insn_start_frag->fr_fix - insn_start_off;
7377 for (fr = insn_start_frag->fr_next;
7378 fr && fr != frag_now; fr = fr->fr_next)
7379 add += fr->fr_fix;
7380 add += p - frag_now->fr_literal;
7381 }
7382
4fa24527 7383 if (!object_64bit)
d6ab8113 7384 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7385 else if (size == 4)
d6ab8113 7386 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7387 else if (size == 8)
7388 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7389 i.op[n].imms->X_add_number += add;
29b0f896 7390 }
29b0f896
AM		 7391 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7392 i.op[n].imms, 0, reloc_type);
7393 }
7394 }
7395 }
252b5132
RH		 7396}
7397\f
d182319b
JB		 7398/* x86_cons_fix_new is called via the expression parsing code when a
7399 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7400static int cons_sign = -1;
7401
7402void
e3bb37b5 7403x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7404 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7405{
d258b828 7406 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7407
7408#ifdef TE_PE
7409 if (exp->X_op == O_secrel)
7410 {
7411 exp->X_op = O_symbol;
7412 r = BFD_RELOC_32_SECREL;
7413 }
7414#endif
7415
7416 fix_new_exp (frag, off, len, exp, 0, r);
7417}
7418
357d1bd8
L		 7419/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7420 purpose of the `.dc.a' internal pseudo-op. */
7421
7422int
7423x86_address_bytes (void)
7424{
7425 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7426 return 4;
7427 return stdoutput->arch_info->bits_per_address / 8;
7428}
7429
d382c579
TG		 7430#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7431 || defined (LEX_AT)
d258b828 7432# define lex_got(reloc, adjust, types) NULL
718ddfc0 7433#else
f3c180ae
AM		 7434/* Parse operands of the form
7435 <symbol>@GOTOFF+<nnn>
7436 and similar .plt or .got references.
7437
7438 If we find one, set up the correct relocation in RELOC and copy the
7439 input string, minus the `@GOTOFF' into a malloc'd buffer for
7440 parsing by the calling routine. Return this buffer, and if ADJUST
7441 is non-null set it to the length of the string we removed from the
7442 input line. Otherwise return NULL. */
7443static char *
91d6fa6a 7444lex_got (enum bfd_reloc_code_real *rel,
64e74474 7445 int *adjust,
d258b828 7446 i386_operand_type *types)
f3c180ae 7447{
7b81dfbb
AJ		 7448 /* Some of the relocations depend on the size of what field is to
7449 be relocated. But in our callers i386_immediate and i386_displacement
7450 we don't yet know the operand size (this will be set by insn
7451 matching). Hence we record the word32 relocation here,
7452 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7453 static const struct {
7454 const char *str;
cff8d58a 7455 int len;
4fa24527 7456 const enum bfd_reloc_code_real rel[2];
40fb9820 7457 const i386_operand_type types64;
f3c180ae 7458 } gotrel[] = {
8ce3d284 7459#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7460 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7461 BFD_RELOC_SIZE32 },
7462 OPERAND_TYPE_IMM32_64 },
8ce3d284 7463#endif
cff8d58a
L		 7464 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7465 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7466 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7467 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7468 BFD_RELOC_X86_64_PLT32 },
40fb9820 7469 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7470 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7471 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7472 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7473 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7474 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7475 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7476 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7477 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7478 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7479 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7480 BFD_RELOC_X86_64_TLSGD },
40fb9820 7481 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7482 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7483 _dummy_first_bfd_reloc_code_real },
40fb9820 7484 OPERAND_TYPE_NONE },
cff8d58a
L		 7485 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7486 BFD_RELOC_X86_64_TLSLD },
40fb9820 7487 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7488 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7489 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7490 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7491 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7492 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7493 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7494 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7495 _dummy_first_bfd_reloc_code_real },
40fb9820 7496 OPERAND_TYPE_NONE },
cff8d58a
L		 7497 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7498 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7499 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7500 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7501 _dummy_first_bfd_reloc_code_real },
40fb9820 7502 OPERAND_TYPE_NONE },
cff8d58a
L		 7503 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7504 _dummy_first_bfd_reloc_code_real },
40fb9820 7505 OPERAND_TYPE_NONE },
cff8d58a
L		 7506 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7507 BFD_RELOC_X86_64_GOT32 },
40fb9820 7508 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7509 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7510 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7511 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7512 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7513 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7514 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7515 };
7516 char *cp;
7517 unsigned int j;
7518
d382c579 7519#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7520 if (!IS_ELF)
7521 return NULL;
d382c579 7522#endif
718ddfc0 7523
f3c180ae 7524 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7525 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7526 return NULL;
7527
47465058 7528 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7529 {
cff8d58a 7530 int len = gotrel[j].len;
28f81592 7531 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7532 {
4fa24527 7533 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7534 {
28f81592
AM		 7535 int first, second;
7536 char *tmpbuf, *past_reloc;
f3c180ae 7537
91d6fa6a 7538 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7539
3956db08
JB		 7540 if (types)
7541 {
7542 if (flag_code != CODE_64BIT)
40fb9820
L		 7543 {
7544 types->bitfield.imm32 = 1;
7545 types->bitfield.disp32 = 1;
7546 }
3956db08
JB		 7547 else
7548 *types = gotrel[j].types64;
7549 }
7550
8fd4256d 7551 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7552 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7553
28f81592 7554 /* The length of the first part of our input line. */
f3c180ae 7555 first = cp - input_line_pointer;
28f81592
AM		 7556
7557 /* The second part goes from after the reloc token until
67c11a9b 7558 (and including) an end_of_line char or comma. */
28f81592 7559 past_reloc = cp + 1 + len;
67c11a9b
AM		 7560 cp = past_reloc;
7561 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7562 ++cp;
7563 second = cp + 1 - past_reloc;
28f81592
AM		 7564
7565 /* Allocate and copy string. The trailing NUL shouldn't
7566 be necessary, but be safe. */
1e9cc1c2 7567 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7568 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7569 if (second != 0 && *past_reloc != ' ')
7570 /* Replace the relocation token with ' ', so that
7571 errors like foo@GOTOFF1 will be detected. */
7572 tmpbuf[first++] = ' ';
af89796a
L		 7573 else
7574 /* Increment length by 1 if the relocation token is
7575 removed. */
7576 len++;
7577 if (adjust)
7578 *adjust = len;
0787a12d
AM		 7579 memcpy (tmpbuf + first, past_reloc, second);
7580 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7581 return tmpbuf;
7582 }
7583
4fa24527
JB		 7584 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7585 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7586 return NULL;
7587 }
7588 }
7589
7590 /* Might be a symbol version string. Don't as_bad here. */
7591 return NULL;
7592}
4e4f7c87 7593#endif
f3c180ae 7594
a988325c
NC		 7595#ifdef TE_PE
7596#ifdef lex_got
7597#undef lex_got
7598#endif
7599/* Parse operands of the form
7600 <symbol>@SECREL32+<nnn>
7601
7602 If we find one, set up the correct relocation in RELOC and copy the
7603 input string, minus the `@SECREL32' into a malloc'd buffer for
7604 parsing by the calling routine. Return this buffer, and if ADJUST
7605 is non-null set it to the length of the string we removed from the
34bca508
L		 7606 input line. Otherwise return NULL.
7607
a988325c
NC		 7608 This function is copied from the ELF version above adjusted for PE targets. */
7609
7610static char *
7611lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7612 int *adjust ATTRIBUTE_UNUSED,
d258b828 7613 i386_operand_type *types)
a988325c
NC		 7614{
7615 static const struct
7616 {
7617 const char *str;
7618 int len;
7619 const enum bfd_reloc_code_real rel[2];
7620 const i386_operand_type types64;
7621 }
7622 gotrel[] =
7623 {
7624 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7625 BFD_RELOC_32_SECREL },
7626 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7627 };
7628
7629 char *cp;
7630 unsigned j;
7631
7632 for (cp = input_line_pointer; *cp != '@'; cp++)
7633 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7634 return NULL;
7635
7636 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7637 {
7638 int len = gotrel[j].len;
7639
7640 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7641 {
7642 if (gotrel[j].rel[object_64bit] != 0)
7643 {
7644 int first, second;
7645 char *tmpbuf, *past_reloc;
7646
7647 *rel = gotrel[j].rel[object_64bit];
7648 if (adjust)
7649 *adjust = len;
7650
7651 if (types)
7652 {
7653 if (flag_code != CODE_64BIT)
7654 {
7655 types->bitfield.imm32 = 1;
7656 types->bitfield.disp32 = 1;
7657 }
7658 else
7659 *types = gotrel[j].types64;
7660 }
7661
7662 /* The length of the first part of our input line. */
7663 first = cp - input_line_pointer;
7664
7665 /* The second part goes from after the reloc token until
7666 (and including) an end_of_line char or comma. */
7667 past_reloc = cp + 1 + len;
7668 cp = past_reloc;
7669 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7670 ++cp;
7671 second = cp + 1 - past_reloc;
7672
7673 /* Allocate and copy string. The trailing NUL shouldn't
7674 be necessary, but be safe. */
7675 tmpbuf = (char *) xmalloc (first + second + 2);
7676 memcpy (tmpbuf, input_line_pointer, first);
7677 if (second != 0 && *past_reloc != ' ')
7678 /* Replace the relocation token with ' ', so that
7679 errors like foo@SECLREL321 will be detected. */
7680 tmpbuf[first++] = ' ';
7681 memcpy (tmpbuf + first, past_reloc, second);
7682 tmpbuf[first + second] = '\0';
7683 return tmpbuf;
7684 }
7685
7686 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7687 gotrel[j].str, 1 << (5 + object_64bit));
7688 return NULL;
7689 }
7690 }
7691
7692 /* Might be a symbol version string. Don't as_bad here. */
7693 return NULL;
7694}
7695
7696#endif /* TE_PE */
7697
62ebcb5c 7698bfd_reloc_code_real_type
e3bb37b5 7699x86_cons (expressionS *exp, int size)
f3c180ae 7700{
62ebcb5c
AM		 7701 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7702
ee86248c
JB		 7703 intel_syntax = -intel_syntax;
7704
3c7b9c2c 7705 exp->X_md = 0;
4fa24527 7706 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7707 {
7708 /* Handle @GOTOFF and the like in an expression. */
7709 char *save;
7710 char *gotfree_input_line;
4a57f2cf 7711 int adjust = 0;
f3c180ae
AM		 7712
7713 save = input_line_pointer;
d258b828 7714 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7715 if (gotfree_input_line)
7716 input_line_pointer = gotfree_input_line;
7717
7718 expression (exp);
7719
7720 if (gotfree_input_line)
7721 {
7722 /* expression () has merrily parsed up to the end of line,
7723 or a comma - in the wrong buffer. Transfer how far
7724 input_line_pointer has moved to the right buffer. */
7725 input_line_pointer = (save
7726 + (input_line_pointer - gotfree_input_line)
7727 + adjust);
7728 free (gotfree_input_line);
3992d3b7
AM		 7729 if (exp->X_op == O_constant
7730 || exp->X_op == O_absent
7731 || exp->X_op == O_illegal
0398aac5 7732 || exp->X_op == O_register
3992d3b7
AM		 7733 || exp->X_op == O_big)
7734 {
7735 char c = *input_line_pointer;
7736 *input_line_pointer = 0;
7737 as_bad (_("missing or invalid expression `%s'"), save);
7738 *input_line_pointer = c;
7739 }
f3c180ae
AM		 7740 }
7741 }
7742 else
7743 expression (exp);
ee86248c
JB		 7744
7745 intel_syntax = -intel_syntax;
7746
7747 if (intel_syntax)
7748 i386_intel_simplify (exp);
62ebcb5c
AM		 7749
7750 return got_reloc;
f3c180ae 7751}
f3c180ae 7752
9f32dd5b
L		 7753static void
7754signed_cons (int size)
6482c264 7755{
d182319b
JB		 7756 if (flag_code == CODE_64BIT)
7757 cons_sign = 1;
7758 cons (size);
7759 cons_sign = -1;
6482c264
NC		 7760}
7761
d182319b 7762#ifdef TE_PE
6482c264 7763static void
7016a5d5 7764pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7765{
7766 expressionS exp;
7767
7768 do
7769 {
7770 expression (&exp);
7771 if (exp.X_op == O_symbol)
7772 exp.X_op = O_secrel;
7773
7774 emit_expr (&exp, 4);
7775 }
7776 while (*input_line_pointer++ == ',');
7777
7778 input_line_pointer--;
7779 demand_empty_rest_of_line ();
7780}
6482c264
NC		 7781#endif
7782
43234a1e
L		 7783/* Handle Vector operations. */
7784
7785static char *
7786check_VecOperations (char *op_string, char *op_end)
7787{
7788 const reg_entry *mask;
7789 const char *saved;
7790 char *end_op;
7791
7792 while (*op_string
7793 && (op_end == NULL || op_string < op_end))
7794 {
7795 saved = op_string;
7796 if (*op_string == '{')
7797 {
7798 op_string++;
7799
7800 /* Check broadcasts. */
7801 if (strncmp (op_string, "1to", 3) == 0)
7802 {
7803 int bcst_type;
7804
7805 if (i.broadcast)
7806 goto duplicated_vec_op;
7807
7808 op_string += 3;
7809 if (*op_string == '8')
7810 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7811 else if (*op_string == '4')
7812 bcst_type = BROADCAST_1TO4;
7813 else if (*op_string == '2')
7814 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7815 else if (*op_string == '1'
7816 && *(op_string+1) == '6')
7817 {
7818 bcst_type = BROADCAST_1TO16;
7819 op_string++;
7820 }
7821 else
7822 {
7823 as_bad (_("Unsupported broadcast: `%s'"), saved);
7824 return NULL;
7825 }
7826 op_string++;
7827
7828 broadcast_op.type = bcst_type;
7829 broadcast_op.operand = this_operand;
7830 i.broadcast = &broadcast_op;
7831 }
7832 /* Check masking operation. */
7833 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7834 {
7835 /* k0 can't be used for write mask. */
7836 if (mask->reg_num == 0)
7837 {
7838 as_bad (_("`%s' can't be used for write mask"),
7839 op_string);
7840 return NULL;
7841 }
7842
7843 if (!i.mask)
7844 {
7845 mask_op.mask = mask;
7846 mask_op.zeroing = 0;
7847 mask_op.operand = this_operand;
7848 i.mask = &mask_op;
7849 }
7850 else
7851 {
7852 if (i.mask->mask)
7853 goto duplicated_vec_op;
7854
7855 i.mask->mask = mask;
7856
7857 /* Only "{z}" is allowed here. No need to check
7858 zeroing mask explicitly. */
7859 if (i.mask->operand != this_operand)
7860 {
7861 as_bad (_("invalid write mask `%s'"), saved);
7862 return NULL;
7863 }
7864 }
7865
7866 op_string = end_op;
7867 }
7868 /* Check zeroing-flag for masking operation. */
7869 else if (*op_string == 'z')
7870 {
7871 if (!i.mask)
7872 {
7873 mask_op.mask = NULL;
7874 mask_op.zeroing = 1;
7875 mask_op.operand = this_operand;
7876 i.mask = &mask_op;
7877 }
7878 else
7879 {
7880 if (i.mask->zeroing)
7881 {
7882 duplicated_vec_op:
7883 as_bad (_("duplicated `%s'"), saved);
7884 return NULL;
7885 }
7886
7887 i.mask->zeroing = 1;
7888
7889 /* Only "{%k}" is allowed here. No need to check mask
7890 register explicitly. */
7891 if (i.mask->operand != this_operand)
7892 {
7893 as_bad (_("invalid zeroing-masking `%s'"),
7894 saved);
7895 return NULL;
7896 }
7897 }
7898
7899 op_string++;
7900 }
7901 else
7902 goto unknown_vec_op;
7903
7904 if (*op_string != '}')
7905 {
7906 as_bad (_("missing `}' in `%s'"), saved);
7907 return NULL;
7908 }
7909 op_string++;
7910 continue;
7911 }
7912 unknown_vec_op:
7913 /* We don't know this one. */
7914 as_bad (_("unknown vector operation: `%s'"), saved);
7915 return NULL;
7916 }
7917
7918 return op_string;
7919}
7920
252b5132 7921static int
70e41ade 7922i386_immediate (char *imm_start)
252b5132
RH		 7923{
7924 char *save_input_line_pointer;
f3c180ae 7925 char *gotfree_input_line;
252b5132 7926 segT exp_seg = 0;
47926f60 7927 expressionS *exp;
40fb9820
L		 7928 i386_operand_type types;
7929
0dfbf9d7 7930 operand_type_set (&types, ~0);
252b5132
RH		 7931
7932 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7933 {
31b2323c
L		 7934 as_bad (_("at most %d immediate operands are allowed"),
7935 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7936 return 0;
7937 }
7938
7939 exp = &im_expressions[i.imm_operands++];
520dc8e8 7940 i.op[this_operand].imms = exp;
252b5132
RH		 7941
7942 if (is_space_char (*imm_start))
7943 ++imm_start;
7944
7945 save_input_line_pointer = input_line_pointer;
7946 input_line_pointer = imm_start;
7947
d258b828 7948 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7949 if (gotfree_input_line)
7950 input_line_pointer = gotfree_input_line;
252b5132
RH		 7951
7952 exp_seg = expression (exp);
7953
83183c0c 7954 SKIP_WHITESPACE ();
43234a1e
L		 7955
7956 /* Handle vector operations. */
7957 if (*input_line_pointer == '{')
7958 {
7959 input_line_pointer = check_VecOperations (input_line_pointer,
7960 NULL);
7961 if (input_line_pointer == NULL)
7962 return 0;
7963 }
7964
252b5132 7965 if (*input_line_pointer)
f3c180ae 7966 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7967
7968 input_line_pointer = save_input_line_pointer;
f3c180ae 7969 if (gotfree_input_line)
ee86248c
JB		 7970 {
7971 free (gotfree_input_line);
7972
7973 if (exp->X_op == O_constant || exp->X_op == O_register)
7974 exp->X_op = O_illegal;
7975 }
7976
7977 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7978}
252b5132 7979
ee86248c
JB		 7980static int
7981i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7982 i386_operand_type types, const char *imm_start)
7983{
7984 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7985 {
313c53d1
L		 7986 if (imm_start)
7987 as_bad (_("missing or invalid immediate expression `%s'"),
7988 imm_start);
3992d3b7 7989 return 0;
252b5132 7990 }
3e73aa7c 7991 else if (exp->X_op == O_constant)
252b5132 7992 {
47926f60 7993 /* Size it properly later. */
40fb9820 7994 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7995 /* If not 64bit, sign extend val. */
7996 if (flag_code != CODE_64BIT
4eed87de
AM		 7997 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7998 exp->X_add_number
7999 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8000 }
4c63da97 8001#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8002 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8003 && exp_seg != absolute_section
47926f60 8004 && exp_seg != text_section
24eab124
AM		 8005 && exp_seg != data_section
8006 && exp_seg != bss_section
8007 && exp_seg != undefined_section
f86103b7 8008 && !bfd_is_com_section (exp_seg))
252b5132 8009 {
d0b47220 8010 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8011 return 0;
8012 }
8013#endif
a841bdf5 8014 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8015 {
313c53d1
L		 8016 if (imm_start)
8017 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8018 return 0;
8019 }
252b5132
RH		 8020 else
8021 {
8022 /* This is an address. The size of the address will be
24eab124 8023 determined later, depending on destination register,
3e73aa7c 8024 suffix, or the default for the section. */
40fb9820
L		 8025 i.types[this_operand].bitfield.imm8 = 1;
8026 i.types[this_operand].bitfield.imm16 = 1;
8027 i.types[this_operand].bitfield.imm32 = 1;
8028 i.types[this_operand].bitfield.imm32s = 1;
8029 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8030 i.types[this_operand] = operand_type_and (i.types[this_operand],
8031 types);
252b5132
RH		 8032 }
8033
8034 return 1;
8035}
8036
551c1ca1 8037static char *
e3bb37b5 8038i386_scale (char *scale)
252b5132 8039{
551c1ca1
AM		 8040 offsetT val;
8041 char *save = input_line_pointer;
252b5132 8042
551c1ca1
AM		 8043 input_line_pointer = scale;
8044 val = get_absolute_expression ();
8045
8046 switch (val)
252b5132 8047 {
551c1ca1 8048 case 1:
252b5132
RH		 8049 i.log2_scale_factor = 0;
8050 break;
551c1ca1 8051 case 2:
252b5132
RH		 8052 i.log2_scale_factor = 1;
8053 break;
551c1ca1 8054 case 4:
252b5132
RH		 8055 i.log2_scale_factor = 2;
8056 break;
551c1ca1 8057 case 8:
252b5132
RH		 8058 i.log2_scale_factor = 3;
8059 break;
8060 default:
a724f0f4
JB		 8061 {
8062 char sep = *input_line_pointer;
8063
8064 *input_line_pointer = '\0';
8065 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8066 scale);
8067 *input_line_pointer = sep;
8068 input_line_pointer = save;
8069 return NULL;
8070 }
252b5132 8071 }
29b0f896 8072 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8073 {
8074 as_warn (_("scale factor of %d without an index register"),
24eab124 8075 1 << i.log2_scale_factor);
252b5132 8076 i.log2_scale_factor = 0;
252b5132 8077 }
551c1ca1
AM		 8078 scale = input_line_pointer;
8079 input_line_pointer = save;
8080 return scale;
252b5132
RH		 8081}
8082
252b5132 8083static int
e3bb37b5 8084i386_displacement (char *disp_start, char *disp_end)
252b5132 8085{
29b0f896 8086 expressionS *exp;
252b5132
RH		 8087 segT exp_seg = 0;
8088 char *save_input_line_pointer;
f3c180ae 8089 char *gotfree_input_line;
40fb9820
L		 8090 int override;
8091 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8092 int ret;
252b5132 8093
31b2323c
L		 8094 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8095 {
8096 as_bad (_("at most %d displacement operands are allowed"),
8097 MAX_MEMORY_OPERANDS);
8098 return 0;
8099 }
8100
0dfbf9d7 8101 operand_type_set (&bigdisp, 0);
40fb9820
L		 8102 if ((i.types[this_operand].bitfield.jumpabsolute)
8103 || (!current_templates->start->opcode_modifier.jump
8104 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8105 {
40fb9820 8106 bigdisp.bitfield.disp32 = 1;
e05278af 8107 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8108 if (flag_code == CODE_64BIT)
8109 {
8110 if (!override)
8111 {
8112 bigdisp.bitfield.disp32s = 1;
8113 bigdisp.bitfield.disp64 = 1;
8114 }
8115 }
8116 else if ((flag_code == CODE_16BIT) ^ override)
8117 {
8118 bigdisp.bitfield.disp32 = 0;
8119 bigdisp.bitfield.disp16 = 1;
8120 }
e05278af
JB		 8121 }
8122 else
8123 {
8124 /* For PC-relative branches, the width of the displacement
8125 is dependent upon data size, not address size. */
e05278af 8126 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8127 if (flag_code == CODE_64BIT)
8128 {
8129 if (override || i.suffix == WORD_MNEM_SUFFIX)
8130 bigdisp.bitfield.disp16 = 1;
8131 else
8132 {
8133 bigdisp.bitfield.disp32 = 1;
8134 bigdisp.bitfield.disp32s = 1;
8135 }
8136 }
8137 else
e05278af
JB		 8138 {
8139 if (!override)
8140 override = (i.suffix == (flag_code != CODE_16BIT
8141 ? WORD_MNEM_SUFFIX
8142 : LONG_MNEM_SUFFIX));
40fb9820
L		 8143 bigdisp.bitfield.disp32 = 1;
8144 if ((flag_code == CODE_16BIT) ^ override)
8145 {
8146 bigdisp.bitfield.disp32 = 0;
8147 bigdisp.bitfield.disp16 = 1;
8148 }
e05278af 8149 }
e05278af 8150 }
c6fb90c8
L		 8151 i.types[this_operand] = operand_type_or (i.types[this_operand],
8152 bigdisp);
252b5132
RH		 8153
8154 exp = &disp_expressions[i.disp_operands];
520dc8e8 8155 i.op[this_operand].disps = exp;
252b5132
RH		 8156 i.disp_operands++;
8157 save_input_line_pointer = input_line_pointer;
8158 input_line_pointer = disp_start;
8159 END_STRING_AND_SAVE (disp_end);
8160
8161#ifndef GCC_ASM_O_HACK
8162#define GCC_ASM_O_HACK 0
8163#endif
8164#if GCC_ASM_O_HACK
8165 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8166 if (i.types[this_operand].bitfield.baseIndex
24eab124 8167 && displacement_string_end[-1] == '+')
252b5132
RH		 8168 {
8169 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8170 constraint within gcc asm statements.
8171 For instance:
8172
8173 #define _set_tssldt_desc(n,addr,limit,type) \
8174 __asm__ __volatile__ ( \
8175 "movw %w2,%0\n\t" \
8176 "movw %w1,2+%0\n\t" \
8177 "rorl $16,%1\n\t" \
8178 "movb %b1,4+%0\n\t" \
8179 "movb %4,5+%0\n\t" \
8180 "movb $0,6+%0\n\t" \
8181 "movb %h1,7+%0\n\t" \
8182 "rorl $16,%1" \
8183 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8184
8185 This works great except that the output assembler ends
8186 up looking a bit weird if it turns out that there is
8187 no offset. You end up producing code that looks like:
8188
8189 #APP
8190 movw $235,(%eax)
8191 movw %dx,2+(%eax)
8192 rorl $16,%edx
8193 movb %dl,4+(%eax)
8194 movb $137,5+(%eax)
8195 movb $0,6+(%eax)
8196 movb %dh,7+(%eax)
8197 rorl $16,%edx
8198 #NO_APP
8199
47926f60 8200 So here we provide the missing zero. */
24eab124
AM		 8201
8202 *displacement_string_end = '0';
252b5132
RH		 8203 }
8204#endif
d258b828 8205 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8206 if (gotfree_input_line)
8207 input_line_pointer = gotfree_input_line;
252b5132 8208
24eab124 8209 exp_seg = expression (exp);
252b5132 8210
636c26b0
AM		 8211 SKIP_WHITESPACE ();
8212 if (*input_line_pointer)
8213 as_bad (_("junk `%s' after expression"), input_line_pointer);
8214#if GCC_ASM_O_HACK
8215 RESTORE_END_STRING (disp_end + 1);
8216#endif
636c26b0 8217 input_line_pointer = save_input_line_pointer;
636c26b0 8218 if (gotfree_input_line)
ee86248c
JB		 8219 {
8220 free (gotfree_input_line);
8221
8222 if (exp->X_op == O_constant || exp->X_op == O_register)
8223 exp->X_op = O_illegal;
8224 }
8225
8226 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8227
8228 RESTORE_END_STRING (disp_end);
8229
8230 return ret;
8231}
8232
8233static int
8234i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8235 i386_operand_type types, const char *disp_start)
8236{
8237 i386_operand_type bigdisp;
8238 int ret = 1;
636c26b0 8239
24eab124
AM		 8240 /* We do this to make sure that the section symbol is in
8241 the symbol table. We will ultimately change the relocation
47926f60 8242 to be relative to the beginning of the section. */
1ae12ab7 8243 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8244 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8245 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8246 {
636c26b0 8247 if (exp->X_op != O_symbol)
3992d3b7 8248 goto inv_disp;
636c26b0 8249
e5cb08ac 8250 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8251 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8252 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8253 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8254 exp->X_op = O_subtract;
8255 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8256 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8257 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8258 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8259 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8260 else
29b0f896 8261 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8262 }
252b5132 8263
3992d3b7
AM		 8264 else if (exp->X_op == O_absent
8265 || exp->X_op == O_illegal
ee86248c 8266 || exp->X_op == O_big)
2daf4fd8 8267 {
3992d3b7
AM		 8268 inv_disp:
8269 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8270 disp_start);
3992d3b7 8271 ret = 0;
2daf4fd8
AM		 8272 }
8273
0e1147d9
L		 8274 else if (flag_code == CODE_64BIT
8275 && !i.prefix[ADDR_PREFIX]
8276 && exp->X_op == O_constant)
8277 {
8278 /* Since displacement is signed extended to 64bit, don't allow
8279 disp32 and turn off disp32s if they are out of range. */
8280 i.types[this_operand].bitfield.disp32 = 0;
8281 if (!fits_in_signed_long (exp->X_add_number))
8282 {
8283 i.types[this_operand].bitfield.disp32s = 0;
8284 if (i.types[this_operand].bitfield.baseindex)
8285 {
8286 as_bad (_("0x%lx out range of signed 32bit displacement"),
8287 (long) exp->X_add_number);
8288 ret = 0;
8289 }
8290 }
8291 }
8292
4c63da97 8293#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8294 else if (exp->X_op != O_constant
8295 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8296 && exp_seg != absolute_section
8297 && exp_seg != text_section
8298 && exp_seg != data_section
8299 && exp_seg != bss_section
8300 && exp_seg != undefined_section
8301 && !bfd_is_com_section (exp_seg))
24eab124 8302 {
d0b47220 8303 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8304 ret = 0;
24eab124 8305 }
252b5132 8306#endif
3956db08 8307
40fb9820
L		 8308 /* Check if this is a displacement only operand. */
8309 bigdisp = i.types[this_operand];
8310 bigdisp.bitfield.disp8 = 0;
8311 bigdisp.bitfield.disp16 = 0;
8312 bigdisp.bitfield.disp32 = 0;
8313 bigdisp.bitfield.disp32s = 0;
8314 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8315 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8316 i.types[this_operand] = operand_type_and (i.types[this_operand],
8317 types);
3956db08 8318
3992d3b7 8319 return ret;
252b5132
RH		 8320}
8321
eecb386c 8322/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8323 Return 1 on success, 0 on a failure. */
8324
252b5132 8325static int
e3bb37b5 8326i386_index_check (const char *operand_string)
252b5132 8327{
fc0763e6 8328 const char *kind = "base/index";
be05d201
L		 8329 enum flag_code addr_mode;
8330
8331 if (i.prefix[ADDR_PREFIX])
8332 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8333 else
8334 {
8335 addr_mode = flag_code;
8336
24eab124 8337#if INFER_ADDR_PREFIX
be05d201
L		 8338 if (i.mem_operands == 0)
8339 {
8340 /* Infer address prefix from the first memory operand. */
8341 const reg_entry *addr_reg = i.base_reg;
8342
8343 if (addr_reg == NULL)
8344 addr_reg = i.index_reg;
eecb386c 8345
be05d201
L		 8346 if (addr_reg)
8347 {
8348 if (addr_reg->reg_num == RegEip
8349 || addr_reg->reg_num == RegEiz
8350 || addr_reg->reg_type.bitfield.reg32)
8351 addr_mode = CODE_32BIT;
8352 else if (flag_code != CODE_64BIT
8353 && addr_reg->reg_type.bitfield.reg16)
8354 addr_mode = CODE_16BIT;
8355
8356 if (addr_mode != flag_code)
8357 {
8358 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8359 i.prefixes += 1;
8360 /* Change the size of any displacement too. At most one
8361 of Disp16 or Disp32 is set.
8362 FIXME. There doesn't seem to be any real need for
8363 separate Disp16 and Disp32 flags. The same goes for
8364 Imm16 and Imm32. Removing them would probably clean
8365 up the code quite a lot. */
8366 if (flag_code != CODE_64BIT
8367 && (i.types[this_operand].bitfield.disp16
8368 || i.types[this_operand].bitfield.disp32))
8369 i.types[this_operand]
8370 = operand_type_xor (i.types[this_operand], disp16_32);
8371 }
8372 }
8373 }
24eab124 8374#endif
be05d201
L		 8375 }
8376
fc0763e6
JB		 8377 if (current_templates->start->opcode_modifier.isstring
8378 && !current_templates->start->opcode_modifier.immext
8379 && (current_templates->end[-1].opcode_modifier.isstring
8380 || i.mem_operands))
8381 {
8382 /* Memory operands of string insns are special in that they only allow
8383 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8384 const reg_entry *expected_reg;
8385 static const char *di_si[][2] =
8386 {
8387 { "esi", "edi" },
8388 { "si", "di" },
8389 { "rsi", "rdi" }
8390 };
8391 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8392
8393 kind = "string address";
8394
8395 if (current_templates->start->opcode_modifier.w)
8396 {
8397 i386_operand_type type = current_templates->end[-1].operand_types[0];
8398
8399 if (!type.bitfield.baseindex
8400 || ((!i.mem_operands != !intel_syntax)
8401 && current_templates->end[-1].operand_types[1]
8402 .bitfield.baseindex))
8403 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8404 expected_reg = hash_find (reg_hash,
8405 di_si[addr_mode][type.bitfield.esseg]);
8406
fc0763e6
JB		 8407 }
8408 else
be05d201 8409 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8410
be05d201
L		 8411 if (i.base_reg != expected_reg
8412 || i.index_reg
fc0763e6 8413 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8414 {
be05d201
L		 8415 /* The second memory operand must have the same size as
8416 the first one. */
8417 if (i.mem_operands
8418 && i.base_reg
8419 && !((addr_mode == CODE_64BIT
8420 && i.base_reg->reg_type.bitfield.reg64)
8421 || (addr_mode == CODE_32BIT
8422 ? i.base_reg->reg_type.bitfield.reg32
8423 : i.base_reg->reg_type.bitfield.reg16)))
8424 goto bad_address;
8425
fc0763e6
JB		 8426 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8427 operand_string,
8428 intel_syntax ? '[' : '(',
8429 register_prefix,
be05d201 8430 expected_reg->reg_name,
fc0763e6 8431 intel_syntax ? ']' : ')');
be05d201 8432 return 1;
fc0763e6 8433 }
be05d201
L		 8434 else
8435 return 1;
8436
8437bad_address:
8438 as_bad (_("`%s' is not a valid %s expression"),
8439 operand_string, kind);
8440 return 0;
3e73aa7c
JH		 8441 }
8442 else
8443 {
be05d201
L		 8444 if (addr_mode != CODE_16BIT)
8445 {
8446 /* 32-bit/64-bit checks. */
8447 if ((i.base_reg
8448 && (addr_mode == CODE_64BIT
8449 ? !i.base_reg->reg_type.bitfield.reg64
8450 : !i.base_reg->reg_type.bitfield.reg32)
8451 && (i.index_reg
8452 || (i.base_reg->reg_num
8453 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8454 || (i.index_reg
8455 && !i.index_reg->reg_type.bitfield.regxmm
8456 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8457 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8458 && ((addr_mode == CODE_64BIT
8459 ? !(i.index_reg->reg_type.bitfield.reg64
8460 || i.index_reg->reg_num == RegRiz)
8461 : !(i.index_reg->reg_type.bitfield.reg32
8462 || i.index_reg->reg_num == RegEiz))
8463 || !i.index_reg->reg_type.bitfield.baseindex)))
8464 goto bad_address;
8465 }
8466 else
3e73aa7c 8467 {
be05d201 8468 /* 16-bit checks. */
3e73aa7c 8469 if ((i.base_reg
40fb9820
L		 8470 && (!i.base_reg->reg_type.bitfield.reg16
8471 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8472 || (i.index_reg
40fb9820
L		 8473 && (!i.index_reg->reg_type.bitfield.reg16
8474 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8475 || !(i.base_reg
8476 && i.base_reg->reg_num < 6
8477 && i.index_reg->reg_num >= 6
8478 && i.log2_scale_factor == 0))))
be05d201 8479 goto bad_address;
3e73aa7c
JH		 8480 }
8481 }
be05d201 8482 return 1;
24eab124 8483}
252b5132 8484
43234a1e
L		 8485/* Handle vector immediates. */
8486
8487static int
8488RC_SAE_immediate (const char *imm_start)
8489{
8490 unsigned int match_found, j;
8491 const char *pstr = imm_start;
8492 expressionS *exp;
8493
8494 if (*pstr != '{')
8495 return 0;
8496
8497 pstr++;
8498 match_found = 0;
8499 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8500 {
8501 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8502 {
8503 if (!i.rounding)
8504 {
8505 rc_op.type = RC_NamesTable[j].type;
8506 rc_op.operand = this_operand;
8507 i.rounding = &rc_op;
8508 }
8509 else
8510 {
8511 as_bad (_("duplicated `%s'"), imm_start);
8512 return 0;
8513 }
8514 pstr += RC_NamesTable[j].len;
8515 match_found = 1;
8516 break;
8517 }
8518 }
8519 if (!match_found)
8520 return 0;
8521
8522 if (*pstr++ != '}')
8523 {
8524 as_bad (_("Missing '}': '%s'"), imm_start);
8525 return 0;
8526 }
8527 /* RC/SAE immediate string should contain nothing more. */;
8528 if (*pstr != 0)
8529 {
8530 as_bad (_("Junk after '}': '%s'"), imm_start);
8531 return 0;
8532 }
8533
8534 exp = &im_expressions[i.imm_operands++];
8535 i.op[this_operand].imms = exp;
8536
8537 exp->X_op = O_constant;
8538 exp->X_add_number = 0;
8539 exp->X_add_symbol = (symbolS *) 0;
8540 exp->X_op_symbol = (symbolS *) 0;
8541
8542 i.types[this_operand].bitfield.imm8 = 1;
8543 return 1;
8544}
8545
fc0763e6 8546/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8547 on error. */
252b5132 8548
252b5132 8549static int
a7619375 8550i386_att_operand (char *operand_string)
252b5132 8551{
af6bdddf
AM		 8552 const reg_entry *r;
8553 char *end_op;
24eab124 8554 char *op_string = operand_string;
252b5132 8555
24eab124 8556 if (is_space_char (*op_string))
252b5132
RH		 8557 ++op_string;
8558
24eab124 8559 /* We check for an absolute prefix (differentiating,
47926f60 8560 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8561 if (*op_string == ABSOLUTE_PREFIX)
8562 {
8563 ++op_string;
8564 if (is_space_char (*op_string))
8565 ++op_string;
40fb9820 8566 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8567 }
252b5132 8568
47926f60 8569 /* Check if operand is a register. */
4d1bb795 8570 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8571 {
40fb9820
L		 8572 i386_operand_type temp;
8573
24eab124
AM		 8574 /* Check for a segment override by searching for ':' after a
8575 segment register. */
8576 op_string = end_op;
8577 if (is_space_char (*op_string))
8578 ++op_string;
40fb9820
L		 8579 if (*op_string == ':'
8580 && (r->reg_type.bitfield.sreg2
8581 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8582 {
8583 switch (r->reg_num)
8584 {
8585 case 0:
8586 i.seg[i.mem_operands] = &es;
8587 break;
8588 case 1:
8589 i.seg[i.mem_operands] = &cs;
8590 break;
8591 case 2:
8592 i.seg[i.mem_operands] = &ss;
8593 break;
8594 case 3:
8595 i.seg[i.mem_operands] = &ds;
8596 break;
8597 case 4:
8598 i.seg[i.mem_operands] = &fs;
8599 break;
8600 case 5:
8601 i.seg[i.mem_operands] = &gs;
8602 break;
8603 }
252b5132 8604
24eab124 8605 /* Skip the ':' and whitespace. */
252b5132
RH		 8606 ++op_string;
8607 if (is_space_char (*op_string))
24eab124 8608 ++op_string;
252b5132 8609
24eab124
AM		 8610 if (!is_digit_char (*op_string)
8611 && !is_identifier_char (*op_string)
8612 && *op_string != '('
8613 && *op_string != ABSOLUTE_PREFIX)
8614 {
8615 as_bad (_("bad memory operand `%s'"), op_string);
8616 return 0;
8617 }
47926f60 8618 /* Handle case of %es:*foo. */
24eab124
AM		 8619 if (*op_string == ABSOLUTE_PREFIX)
8620 {
8621 ++op_string;
8622 if (is_space_char (*op_string))
8623 ++op_string;
40fb9820 8624 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8625 }
8626 goto do_memory_reference;
8627 }
43234a1e
L		 8628
8629 /* Handle vector operations. */
8630 if (*op_string == '{')
8631 {
8632 op_string = check_VecOperations (op_string, NULL);
8633 if (op_string == NULL)
8634 return 0;
8635 }
8636
24eab124
AM		 8637 if (*op_string)
8638 {
d0b47220 8639 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8640 return 0;
8641 }
40fb9820
L		 8642 temp = r->reg_type;
8643 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8644 i.types[this_operand] = operand_type_or (i.types[this_operand],
8645 temp);
7d5e4556 8646 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8647 i.op[this_operand].regs = r;
24eab124
AM		 8648 i.reg_operands++;
8649 }
af6bdddf
AM		 8650 else if (*op_string == REGISTER_PREFIX)
8651 {
8652 as_bad (_("bad register name `%s'"), op_string);
8653 return 0;
8654 }
24eab124 8655 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8656 {
24eab124 8657 ++op_string;
40fb9820 8658 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8659 {
d0b47220 8660 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8661 return 0;
8662 }
8663 if (!i386_immediate (op_string))
8664 return 0;
8665 }
43234a1e
L		 8666 else if (RC_SAE_immediate (operand_string))
8667 {
8668 /* If it is a RC or SAE immediate, do nothing. */
8669 ;
8670 }
24eab124
AM		 8671 else if (is_digit_char (*op_string)
8672 || is_identifier_char (*op_string)
d02603dc 8673 || *op_string == '"'
e5cb08ac 8674 || *op_string == '(')
24eab124 8675 {
47926f60 8676 /* This is a memory reference of some sort. */
af6bdddf 8677 char *base_string;
252b5132 8678
47926f60 8679 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8680 char *displacement_string_start;
8681 char *displacement_string_end;
43234a1e 8682 char *vop_start;
252b5132 8683
24eab124 8684 do_memory_reference:
24eab124 8685 if ((i.mem_operands == 1
40fb9820 8686 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8687 || i.mem_operands == 2)
8688 {
8689 as_bad (_("too many memory references for `%s'"),
8690 current_templates->start->name);
8691 return 0;
8692 }
252b5132 8693
24eab124
AM		 8694 /* Check for base index form. We detect the base index form by
8695 looking for an ')' at the end of the operand, searching
8696 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8697 after the '('. */
af6bdddf 8698 base_string = op_string + strlen (op_string);
c3332e24 8699
43234a1e
L		 8700 /* Handle vector operations. */
8701 vop_start = strchr (op_string, '{');
8702 if (vop_start && vop_start < base_string)
8703 {
8704 if (check_VecOperations (vop_start, base_string) == NULL)
8705 return 0;
8706 base_string = vop_start;
8707 }
8708
af6bdddf
AM		 8709 --base_string;
8710 if (is_space_char (*base_string))
8711 --base_string;
252b5132 8712
47926f60 8713 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8714 displacement_string_start = op_string;
8715 displacement_string_end = base_string + 1;
252b5132 8716
24eab124
AM		 8717 if (*base_string == ')')
8718 {
af6bdddf 8719 char *temp_string;
24eab124
AM		 8720 unsigned int parens_balanced = 1;
8721 /* We've already checked that the number of left & right ()'s are
47926f60 8722 equal, so this loop will not be infinite. */
24eab124
AM		 8723 do
8724 {
8725 base_string--;
8726 if (*base_string == ')')
8727 parens_balanced++;
8728 if (*base_string == '(')
8729 parens_balanced--;
8730 }
8731 while (parens_balanced);
c3332e24 8732
af6bdddf 8733 temp_string = base_string;
c3332e24 8734
24eab124 8735 /* Skip past '(' and whitespace. */
252b5132
RH		 8736 ++base_string;
8737 if (is_space_char (*base_string))
24eab124 8738 ++base_string;
252b5132 8739
af6bdddf 8740 if (*base_string == ','
4eed87de
AM		 8741 || ((i.base_reg = parse_register (base_string, &end_op))
8742 != NULL))
252b5132 8743 {
af6bdddf 8744 displacement_string_end = temp_string;
252b5132 8745
40fb9820 8746 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8747
af6bdddf 8748 if (i.base_reg)
24eab124 8749 {
24eab124
AM		 8750 base_string = end_op;
8751 if (is_space_char (*base_string))
8752 ++base_string;
af6bdddf
AM		 8753 }
8754
8755 /* There may be an index reg or scale factor here. */
8756 if (*base_string == ',')
8757 {
8758 ++base_string;
8759 if (is_space_char (*base_string))
8760 ++base_string;
8761
4eed87de
AM		 8762 if ((i.index_reg = parse_register (base_string, &end_op))
8763 != NULL)
24eab124 8764 {
af6bdddf 8765 base_string = end_op;
24eab124
AM		 8766 if (is_space_char (*base_string))
8767 ++base_string;
af6bdddf
AM		 8768 if (*base_string == ',')
8769 {
8770 ++base_string;
8771 if (is_space_char (*base_string))
8772 ++base_string;
8773 }
e5cb08ac 8774 else if (*base_string != ')')
af6bdddf 8775 {
4eed87de
AM		 8776 as_bad (_("expecting `,' or `)' "
8777 "after index register in `%s'"),
af6bdddf
AM		 8778 operand_string);
8779 return 0;
8780 }
24eab124 8781 }
af6bdddf 8782 else if (*base_string == REGISTER_PREFIX)
24eab124 8783 {
f76bf5e0
L		 8784 end_op = strchr (base_string, ',');
8785 if (end_op)
8786 *end_op = '\0';
af6bdddf 8787 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8788 return 0;
8789 }
252b5132 8790
47926f60 8791 /* Check for scale factor. */
551c1ca1 8792 if (*base_string != ')')
af6bdddf 8793 {
551c1ca1
AM		 8794 char *end_scale = i386_scale (base_string);
8795
8796 if (!end_scale)
af6bdddf 8797 return 0;
24eab124 8798
551c1ca1 8799 base_string = end_scale;
af6bdddf
AM		 8800 if (is_space_char (*base_string))
8801 ++base_string;
8802 if (*base_string != ')')
8803 {
4eed87de
AM		 8804 as_bad (_("expecting `)' "
8805 "after scale factor in `%s'"),
af6bdddf
AM		 8806 operand_string);
8807 return 0;
8808 }
8809 }
8810 else if (!i.index_reg)
24eab124 8811 {
4eed87de
AM		 8812 as_bad (_("expecting index register or scale factor "
8813 "after `,'; got '%c'"),
af6bdddf 8814 *base_string);
24eab124
AM		 8815 return 0;
8816 }
8817 }
af6bdddf 8818 else if (*base_string != ')')
24eab124 8819 {
4eed87de
AM		 8820 as_bad (_("expecting `,' or `)' "
8821 "after base register in `%s'"),
af6bdddf 8822 operand_string);
24eab124
AM		 8823 return 0;
8824 }
c3332e24 8825 }
af6bdddf 8826 else if (*base_string == REGISTER_PREFIX)
c3332e24 8827 {
f76bf5e0
L		 8828 end_op = strchr (base_string, ',');
8829 if (end_op)
8830 *end_op = '\0';
af6bdddf 8831 as_bad (_("bad register name `%s'"), base_string);
24eab124 8832 return 0;
c3332e24 8833 }
24eab124
AM		 8834 }
8835
8836 /* If there's an expression beginning the operand, parse it,
8837 assuming displacement_string_start and
8838 displacement_string_end are meaningful. */
8839 if (displacement_string_start != displacement_string_end)
8840 {
8841 if (!i386_displacement (displacement_string_start,
8842 displacement_string_end))
8843 return 0;
8844 }
8845
8846 /* Special case for (%dx) while doing input/output op. */
8847 if (i.base_reg
0dfbf9d7
L		 8848 && operand_type_equal (&i.base_reg->reg_type,
8849 &reg16_inoutportreg)
24eab124
AM		 8850 && i.index_reg == 0
8851 && i.log2_scale_factor == 0
8852 && i.seg[i.mem_operands] == 0
40fb9820 8853 && !operand_type_check (i.types[this_operand], disp))
24eab124 8854 {
65da13b5 8855 i.types[this_operand] = inoutportreg;
24eab124
AM		 8856 return 1;
8857 }
8858
eecb386c
AM		 8859 if (i386_index_check (operand_string) == 0)
8860 return 0;
5c07affc 8861 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8862 i.mem_operands++;
8863 }
8864 else
ce8a8b2f
AM		 8865 {
8866 /* It's not a memory operand; argh! */
24eab124
AM		 8867 as_bad (_("invalid char %s beginning operand %d `%s'"),
8868 output_invalid (*op_string),
8869 this_operand + 1,
8870 op_string);
8871 return 0;
8872 }
47926f60 8873 return 1; /* Normal return. */
252b5132
RH		 8874}
8875\f
fa94de6b
RM		 8876/* Calculate the maximum variable size (i.e., excluding fr_fix)
8877 that an rs_machine_dependent frag may reach. */
8878
8879unsigned int
8880i386_frag_max_var (fragS *frag)
8881{
8882 /* The only relaxable frags are for jumps.
8883 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8884 gas_assert (frag->fr_type == rs_machine_dependent);
8885 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8886}
8887
b084df0b
L		 8888#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8889static int
8dcea932 8890elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8891{
8892 /* STT_GNU_IFUNC symbol must go through PLT. */
8893 if ((symbol_get_bfdsym (fr_symbol)->flags
8894 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8895 return 0;
8896
8897 if (!S_IS_EXTERNAL (fr_symbol))
8898 /* Symbol may be weak or local. */
8899 return !S_IS_WEAK (fr_symbol);
8900
8dcea932
L		 8901 /* Global symbols with non-default visibility can't be preempted. */
8902 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8903 return 1;
8904
8905 if (fr_var != NO_RELOC)
8906 switch ((enum bfd_reloc_code_real) fr_var)
8907 {
8908 case BFD_RELOC_386_PLT32:
8909 case BFD_RELOC_X86_64_PLT32:
8910 /* Symbol with PLT relocatin may be preempted. */
8911 return 0;
8912 default:
8913 abort ();
8914 }
8915
b084df0b
L		 8916 /* Global symbols with default visibility in a shared library may be
8917 preempted by another definition. */
8dcea932 8918 return !shared;
b084df0b
L		 8919}
8920#endif
8921
ee7fcc42
AM		 8922/* md_estimate_size_before_relax()
8923
8924 Called just before relax() for rs_machine_dependent frags. The x86
8925 assembler uses these frags to handle variable size jump
8926 instructions.
8927
8928 Any symbol that is now undefined will not become defined.
8929 Return the correct fr_subtype in the frag.
8930 Return the initial "guess for variable size of frag" to caller.
8931 The guess is actually the growth beyond the fixed part. Whatever
8932 we do to grow the fixed or variable part contributes to our
8933 returned value. */
8934
252b5132 8935int
7016a5d5 8936md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8937{
252b5132 8938 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8939 check for un-relaxable symbols. On an ELF system, we can't relax
8940 an externally visible symbol, because it may be overridden by a
8941 shared library. */
8942 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8943#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8944 || (IS_ELF
8dcea932
L		 8945 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8946 fragP->fr_var))
fbeb56a4
DK		 8947#endif
8948#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8949 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8950 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8951#endif
8952 )
252b5132 8953 {
b98ef147
AM		 8954 /* Symbol is undefined in this segment, or we need to keep a
8955 reloc so that weak symbols can be overridden. */
8956 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8957 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8958 unsigned char *opcode;
8959 int old_fr_fix;
f6af82bd 8960
ee7fcc42 8961 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8962 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8963 else if (size == 2)
f6af82bd
AM		 8964 reloc_type = BFD_RELOC_16_PCREL;
8965 else
8966 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8967
ee7fcc42
AM		 8968 old_fr_fix = fragP->fr_fix;
8969 opcode = (unsigned char *) fragP->fr_opcode;
8970
fddf5b5b 8971 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8972 {
fddf5b5b
AM		 8973 case UNCOND_JUMP:
8974 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8975 opcode[0] = 0xe9;
252b5132 8976 fragP->fr_fix += size;
062cd5e7
AS		 8977 fix_new (fragP, old_fr_fix, size,
8978 fragP->fr_symbol,
8979 fragP->fr_offset, 1,
8980 reloc_type);
252b5132
RH		 8981 break;
8982
fddf5b5b 8983 case COND_JUMP86:
412167cb
AM		 8984 if (size == 2
8985 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8986 {
8987 /* Negate the condition, and branch past an
8988 unconditional jump. */
8989 opcode[0] ^= 1;
8990 opcode[1] = 3;
8991 /* Insert an unconditional jump. */
8992 opcode[2] = 0xe9;
8993 /* We added two extra opcode bytes, and have a two byte
8994 offset. */
8995 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8996 fix_new (fragP, old_fr_fix + 2, 2,
8997 fragP->fr_symbol,
8998 fragP->fr_offset, 1,
8999 reloc_type);
fddf5b5b
AM		 9000 break;
9001 }
9002 /* Fall through. */
9003
9004 case COND_JUMP:
412167cb
AM		 9005 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9006 {
3e02c1cc
AM		 9007 fixS *fixP;
9008
412167cb 9009 fragP->fr_fix += 1;
3e02c1cc
AM		 9010 fixP = fix_new (fragP, old_fr_fix, 1,
9011 fragP->fr_symbol,
9012 fragP->fr_offset, 1,
9013 BFD_RELOC_8_PCREL);
9014 fixP->fx_signed = 1;
412167cb
AM		 9015 break;
9016 }
93c2a809 9017
24eab124 9018 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9019 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9020 opcode[1] = opcode[0] + 0x10;
f6af82bd 9021 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9022 /* We've added an opcode byte. */
9023 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9024 fix_new (fragP, old_fr_fix + 1, size,
9025 fragP->fr_symbol,
9026 fragP->fr_offset, 1,
9027 reloc_type);
252b5132 9028 break;
fddf5b5b
AM		 9029
9030 default:
9031 BAD_CASE (fragP->fr_subtype);
9032 break;
252b5132
RH		 9033 }
9034 frag_wane (fragP);
ee7fcc42 9035 return fragP->fr_fix - old_fr_fix;
252b5132 9036 }
93c2a809 9037
93c2a809
AM		 9038 /* Guess size depending on current relax state. Initially the relax
9039 state will correspond to a short jump and we return 1, because
9040 the variable part of the frag (the branch offset) is one byte
9041 long. However, we can relax a section more than once and in that
9042 case we must either set fr_subtype back to the unrelaxed state,
9043 or return the value for the appropriate branch. */
9044 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9045}
9046
47926f60
KH		 9047/* Called after relax() is finished.
9048
9049 In: Address of frag.
9050 fr_type == rs_machine_dependent.
9051 fr_subtype is what the address relaxed to.
9052
9053 Out: Any fixSs and constants are set up.
9054 Caller will turn frag into a ".space 0". */
9055
252b5132 9056void
7016a5d5
TG		 9057md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9058 fragS *fragP)
252b5132 9059{
29b0f896 9060 unsigned char *opcode;
252b5132 9061 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9062 offsetT target_address;
9063 offsetT opcode_address;
252b5132 9064 unsigned int extension = 0;
847f7ad4 9065 offsetT displacement_from_opcode_start;
252b5132
RH		 9066
9067 opcode = (unsigned char *) fragP->fr_opcode;
9068
47926f60 9069 /* Address we want to reach in file space. */
252b5132 9070 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9071
47926f60 9072 /* Address opcode resides at in file space. */
252b5132
RH		 9073 opcode_address = fragP->fr_address + fragP->fr_fix;
9074
47926f60 9075 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9076 displacement_from_opcode_start = target_address - opcode_address;
9077
fddf5b5b 9078 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9079 {
47926f60
KH		 9080 /* Don't have to change opcode. */
9081 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9082 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9083 }
9084 else
9085 {
9086 if (no_cond_jump_promotion
9087 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9088 as_warn_where (fragP->fr_file, fragP->fr_line,
9089 _("long jump required"));
252b5132 9090
fddf5b5b
AM		 9091 switch (fragP->fr_subtype)
9092 {
9093 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9094 extension = 4; /* 1 opcode + 4 displacement */
9095 opcode[0] = 0xe9;
9096 where_to_put_displacement = &opcode[1];
9097 break;
252b5132 9098
fddf5b5b
AM		 9099 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9100 extension = 2; /* 1 opcode + 2 displacement */
9101 opcode[0] = 0xe9;
9102 where_to_put_displacement = &opcode[1];
9103 break;
252b5132 9104
fddf5b5b
AM		 9105 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9106 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9107 extension = 5; /* 2 opcode + 4 displacement */
9108 opcode[1] = opcode[0] + 0x10;
9109 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9110 where_to_put_displacement = &opcode[2];
9111 break;
252b5132 9112
fddf5b5b
AM		 9113 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9114 extension = 3; /* 2 opcode + 2 displacement */
9115 opcode[1] = opcode[0] + 0x10;
9116 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9117 where_to_put_displacement = &opcode[2];
9118 break;
252b5132 9119
fddf5b5b
AM		 9120 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9121 extension = 4;
9122 opcode[0] ^= 1;
9123 opcode[1] = 3;
9124 opcode[2] = 0xe9;
9125 where_to_put_displacement = &opcode[3];
9126 break;
9127
9128 default:
9129 BAD_CASE (fragP->fr_subtype);
9130 break;
9131 }
252b5132 9132 }
fddf5b5b 9133
7b81dfbb
AJ		 9134 /* If size if less then four we are sure that the operand fits,
9135 but if it's 4, then it could be that the displacement is larger
9136 then -/+ 2GB. */
9137 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9138 && object_64bit
9139 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9140 + ((addressT) 1 << 31))
9141 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9142 {
9143 as_bad_where (fragP->fr_file, fragP->fr_line,
9144 _("jump target out of range"));
9145 /* Make us emit 0. */
9146 displacement_from_opcode_start = extension;
9147 }
47926f60 9148 /* Now put displacement after opcode. */
252b5132
RH		 9149 md_number_to_chars ((char *) where_to_put_displacement,
9150 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9151 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9152 fragP->fr_fix += extension;
9153}
9154\f
7016a5d5 9155/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9156 by our caller that we have all the info we need to fix it up.
9157
7016a5d5
TG		 9158 Parameter valP is the pointer to the value of the bits.
9159
252b5132
RH		 9160 On the 386, immediates, displacements, and data pointers are all in
9161 the same (little-endian) format, so we don't need to care about which
9162 we are handling. */
9163
94f592af 9164void
7016a5d5 9165md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9166{
94f592af 9167 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9168 valueT value = *valP;
252b5132 9169
f86103b7 9170#if !defined (TE_Mach)
93382f6d
AM		 9171 if (fixP->fx_pcrel)
9172 {
9173 switch (fixP->fx_r_type)
9174 {
5865bb77
ILT		 9175 default:
9176 break;
9177
d6ab8113
JB		 9178 case BFD_RELOC_64:
9179 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9180 break;
93382f6d 9181 case BFD_RELOC_32:
ae8887b5 9182 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9183 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9184 break;
9185 case BFD_RELOC_16:
9186 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9187 break;
9188 case BFD_RELOC_8:
9189 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9190 break;
9191 }
9192 }
252b5132 9193
a161fe53 9194 if (fixP->fx_addsy != NULL
31312f95 9195 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9196 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9197 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9198 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9199 && !use_rela_relocations)
252b5132 9200 {
31312f95
AM		 9201 /* This is a hack. There should be a better way to handle this.
9202 This covers for the fact that bfd_install_relocation will
9203 subtract the current location (for partial_inplace, PC relative
9204 relocations); see more below. */
252b5132 9205#ifndef OBJ_AOUT
718ddfc0 9206 if (IS_ELF
252b5132
RH		 9207#ifdef TE_PE
9208 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9209#endif
9210 )
9211 value += fixP->fx_where + fixP->fx_frag->fr_address;
9212#endif
9213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9214 if (IS_ELF)
252b5132 9215 {
6539b54b 9216 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9217
6539b54b 9218 if ((sym_seg == seg
2f66722d 9219 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9220 && sym_seg != absolute_section))
af65af87 9221 && !generic_force_reloc (fixP))
2f66722d
AM		 9222 {
9223 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9224 bfd_install_relocation subtracts them out again. I think
9225 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9226 it. FIXME. */
9227 value += fixP->fx_where + fixP->fx_frag->fr_address;
9228 }
252b5132
RH		 9229 }
9230#endif
9231#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9232 /* For some reason, the PE format does not store a
9233 section address offset for a PC relative symbol. */
9234 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9235 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9236 value += md_pcrel_from (fixP);
9237#endif
9238 }
fbeb56a4 9239#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9240 if (fixP->fx_addsy != NULL
9241 && S_IS_WEAK (fixP->fx_addsy)
9242 /* PR 16858: Do not modify weak function references. */
9243 && ! fixP->fx_pcrel)
fbeb56a4 9244 {
296a8689
NC		 9245#if !defined (TE_PEP)
9246 /* For x86 PE weak function symbols are neither PC-relative
9247 nor do they set S_IS_FUNCTION. So the only reliable way
9248 to detect them is to check the flags of their containing
9249 section. */
9250 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9251 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9252 ;
9253 else
9254#endif
fbeb56a4
DK		 9255 value -= S_GET_VALUE (fixP->fx_addsy);
9256 }
9257#endif
252b5132
RH		 9258
9259 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9260 and we must not disappoint it. */
252b5132 9261#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9262 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9263 switch (fixP->fx_r_type)
9264 {
9265 case BFD_RELOC_386_PLT32:
3e73aa7c 9266 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9267 /* Make the jump instruction point to the address of the operand. At
9268 runtime we merely add the offset to the actual PLT entry. */
9269 value = -4;
9270 break;
31312f95 9271
13ae64f3
JJ		 9272 case BFD_RELOC_386_TLS_GD:
9273 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9274 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9275 case BFD_RELOC_386_TLS_IE:
9276 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9277 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9278 case BFD_RELOC_X86_64_TLSGD:
9279 case BFD_RELOC_X86_64_TLSLD:
9280 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9281 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9282 value = 0; /* Fully resolved at runtime. No addend. */
9283 /* Fallthrough */
9284 case BFD_RELOC_386_TLS_LE:
9285 case BFD_RELOC_386_TLS_LDO_32:
9286 case BFD_RELOC_386_TLS_LE_32:
9287 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9288 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9289 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9290 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9291 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9292 break;
9293
67a4f2b7
AO		 9294 case BFD_RELOC_386_TLS_DESC_CALL:
9295 case BFD_RELOC_X86_64_TLSDESC_CALL:
9296 value = 0; /* Fully resolved at runtime. No addend. */
9297 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9298 fixP->fx_done = 0;
9299 return;
9300
00f7efb6
JJ		 9301 case BFD_RELOC_386_GOT32:
9302 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9303 value = 0; /* Fully resolved at runtime. No addend. */
9304 break;
47926f60
KH		 9305
9306 case BFD_RELOC_VTABLE_INHERIT:
9307 case BFD_RELOC_VTABLE_ENTRY:
9308 fixP->fx_done = 0;
94f592af 9309 return;
47926f60
KH		 9310
9311 default:
9312 break;
9313 }
9314#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9315 *valP = value;
f86103b7 9316#endif /* !defined (TE_Mach) */
3e73aa7c 9317
3e73aa7c 9318 /* Are we finished with this relocation now? */
c6682705 9319 if (fixP->fx_addsy == NULL)
3e73aa7c 9320 fixP->fx_done = 1;
fbeb56a4
DK		 9321#if defined (OBJ_COFF) && defined (TE_PE)
9322 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9323 {
9324 fixP->fx_done = 0;
9325 /* Remember value for tc_gen_reloc. */
9326 fixP->fx_addnumber = value;
9327 /* Clear out the frag for now. */
9328 value = 0;
9329 }
9330#endif
3e73aa7c
JH		 9331 else if (use_rela_relocations)
9332 {
9333 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9334 /* Remember value for tc_gen_reloc. */
9335 fixP->fx_addnumber = value;
3e73aa7c
JH		 9336 value = 0;
9337 }
f86103b7 9338
94f592af 9339 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9340}
252b5132 9341\f
252b5132 9342char *
499ac353 9343md_atof (int type, char *litP, int *sizeP)
252b5132 9344{
499ac353
NC		 9345 /* This outputs the LITTLENUMs in REVERSE order;
9346 in accord with the bigendian 386. */
9347 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9348}
9349\f
2d545b82 9350static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9351
252b5132 9352static char *
e3bb37b5 9353output_invalid (int c)
252b5132 9354{
3882b010 9355 if (ISPRINT (c))
f9f21a03
L		 9356 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9357 "'%c'", c);
252b5132 9358 else
f9f21a03 9359 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9360 "(0x%x)", (unsigned char) c);
252b5132
RH		 9361 return output_invalid_buf;
9362}
9363
af6bdddf 9364/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9365
9366static const reg_entry *
4d1bb795 9367parse_real_register (char *reg_string, char **end_op)
252b5132 9368{
af6bdddf
AM		 9369 char *s = reg_string;
9370 char *p;
252b5132
RH		 9371 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9372 const reg_entry *r;
9373
9374 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9375 if (*s == REGISTER_PREFIX)
9376 ++s;
9377
9378 if (is_space_char (*s))
9379 ++s;
9380
9381 p = reg_name_given;
af6bdddf 9382 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9383 {
9384 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9385 return (const reg_entry *) NULL;
9386 s++;
252b5132
RH		 9387 }
9388
6588847e
DN		 9389 /* For naked regs, make sure that we are not dealing with an identifier.
9390 This prevents confusing an identifier like `eax_var' with register
9391 `eax'. */
9392 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9393 return (const reg_entry *) NULL;
9394
af6bdddf 9395 *end_op = s;
252b5132
RH		 9396
9397 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9398
5f47d35b 9399 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9400 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9401 {
5f47d35b
AM		 9402 if (is_space_char (*s))
9403 ++s;
9404 if (*s == '(')
9405 {
af6bdddf 9406 ++s;
5f47d35b
AM		 9407 if (is_space_char (*s))
9408 ++s;
9409 if (*s >= '0' && *s <= '7')
9410 {
db557034 9411 int fpr = *s - '0';
af6bdddf 9412 ++s;
5f47d35b
AM		 9413 if (is_space_char (*s))
9414 ++s;
9415 if (*s == ')')
9416 {
9417 *end_op = s + 1;
1e9cc1c2 9418 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9419 know (r);
9420 return r + fpr;
5f47d35b 9421 }
5f47d35b 9422 }
47926f60 9423 /* We have "%st(" then garbage. */
5f47d35b
AM		 9424 return (const reg_entry *) NULL;
9425 }
9426 }
9427
a60de03c
JB		 9428 if (r == NULL || allow_pseudo_reg)
9429 return r;
9430
0dfbf9d7 9431 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9432 return (const reg_entry *) NULL;
9433
192dc9c6
JB		 9434 if ((r->reg_type.bitfield.reg32
9435 || r->reg_type.bitfield.sreg3
9436 || r->reg_type.bitfield.control
9437 || r->reg_type.bitfield.debug
9438 || r->reg_type.bitfield.test)
9439 && !cpu_arch_flags.bitfield.cpui386)
9440 return (const reg_entry *) NULL;
9441
309d3373
JB		 9442 if (r->reg_type.bitfield.floatreg
9443 && !cpu_arch_flags.bitfield.cpu8087
9444 && !cpu_arch_flags.bitfield.cpu287
9445 && !cpu_arch_flags.bitfield.cpu387)
9446 return (const reg_entry *) NULL;
9447
192dc9c6
JB		 9448 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9449 return (const reg_entry *) NULL;
9450
9451 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9452 return (const reg_entry *) NULL;
9453
40f12533
L		 9454 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9455 return (const reg_entry *) NULL;
9456
43234a1e
L		 9457 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9458 && !cpu_arch_flags.bitfield.cpuavx512f)
9459 return (const reg_entry *) NULL;
9460
db51cc60 9461 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9462 if (!allow_index_reg
db51cc60
L		 9463 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9464 return (const reg_entry *) NULL;
9465
43234a1e
L		 9466 /* Upper 16 vector register is only available with VREX in 64bit
9467 mode. */
9468 if ((r->reg_flags & RegVRex))
9469 {
9470 if (!cpu_arch_flags.bitfield.cpuvrex
9471 || flag_code != CODE_64BIT)
9472 return (const reg_entry *) NULL;
9473
9474 i.need_vrex = 1;
9475 }
9476
a60de03c
JB		 9477 if (((r->reg_flags & (RegRex64 | RegRex))
9478 || r->reg_type.bitfield.reg64)
40fb9820 9479 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9480 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9481 && flag_code != CODE_64BIT)
20f0a1fc 9482 return (const reg_entry *) NULL;
1ae00879 9483
b7240065
JB		 9484 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9485 return (const reg_entry *) NULL;
9486
252b5132
RH		 9487 return r;
9488}
4d1bb795
JB		 9489
9490/* REG_STRING starts *before* REGISTER_PREFIX. */
9491
9492static const reg_entry *
9493parse_register (char *reg_string, char **end_op)
9494{
9495 const reg_entry *r;
9496
9497 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9498 r = parse_real_register (reg_string, end_op);
9499 else
9500 r = NULL;
9501 if (!r)
9502 {
9503 char *save = input_line_pointer;
9504 char c;
9505 symbolS *symbolP;
9506
9507 input_line_pointer = reg_string;
d02603dc 9508 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9509 symbolP = symbol_find (reg_string);
9510 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9511 {
9512 const expressionS *e = symbol_get_value_expression (symbolP);
9513
0398aac5 9514 know (e->X_op == O_register);
4eed87de 9515 know (e->X_add_number >= 0
c3fe08fa 9516 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9517 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9518 if ((r->reg_flags & RegVRex))
9519 i.need_vrex = 1;
4d1bb795
JB		 9520 *end_op = input_line_pointer;
9521 }
9522 *input_line_pointer = c;
9523 input_line_pointer = save;
9524 }
9525 return r;
9526}
9527
9528int
9529i386_parse_name (char *name, expressionS *e, char *nextcharP)
9530{
9531 const reg_entry *r;
9532 char *end = input_line_pointer;
9533
9534 *end = *nextcharP;
9535 r = parse_register (name, &input_line_pointer);
9536 if (r && end <= input_line_pointer)
9537 {
9538 *nextcharP = *input_line_pointer;
9539 *input_line_pointer = 0;
9540 e->X_op = O_register;
9541 e->X_add_number = r - i386_regtab;
9542 return 1;
9543 }
9544 input_line_pointer = end;
9545 *end = 0;
ee86248c 9546 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9547}
9548
9549void
9550md_operand (expressionS *e)
9551{
ee86248c
JB		 9552 char *end;
9553 const reg_entry *r;
4d1bb795 9554
ee86248c
JB		 9555 switch (*input_line_pointer)
9556 {
9557 case REGISTER_PREFIX:
9558 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9559 if (r)
9560 {
9561 e->X_op = O_register;
9562 e->X_add_number = r - i386_regtab;
9563 input_line_pointer = end;
9564 }
ee86248c
JB		 9565 break;
9566
9567 case '[':
9c2799c2 9568 gas_assert (intel_syntax);
ee86248c
JB		 9569 end = input_line_pointer++;
9570 expression (e);
9571 if (*input_line_pointer == ']')
9572 {
9573 ++input_line_pointer;
9574 e->X_op_symbol = make_expr_symbol (e);
9575 e->X_add_symbol = NULL;
9576 e->X_add_number = 0;
9577 e->X_op = O_index;
9578 }
9579 else
9580 {
9581 e->X_op = O_absent;
9582 input_line_pointer = end;
9583 }
9584 break;
4d1bb795
JB		 9585 }
9586}
9587
252b5132 9588\f
4cc782b5 9589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9590const char *md_shortopts = "kVQ:sqn";
252b5132 9591#else
12b55ccc 9592const char *md_shortopts = "qn";
252b5132 9593#endif
6e0b89ee 9594
3e73aa7c 9595#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9596#define OPTION_64 (OPTION_MD_BASE + 1)
9597#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9598#define OPTION_MARCH (OPTION_MD_BASE + 3)
9599#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9600#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9601#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9602#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9603#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9604#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9605#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9606#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9607#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9608#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9609#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9610#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9611#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9612#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9613#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9614#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9615#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9616#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9617#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9618#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
b3b91714 9619
99ad8390
NC		 9620struct option md_longopts[] =
9621{
3e73aa7c 9622 {"32", no_argument, NULL, OPTION_32},
321098a5 9623#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9624 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9625 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9626#endif
9627#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9628 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9629 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9630#endif
b3b91714 9631 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9632 {"march", required_argument, NULL, OPTION_MARCH},
9633 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9634 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9635 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9636 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9637 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9638 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9639 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9640 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9641 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9642 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9643 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9644 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9645 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9646# if defined (TE_PE) || defined (TE_PEP)
9647 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9648#endif
a5094208 9649 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9650 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9651 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9652 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9653 {NULL, no_argument, NULL, 0}
9654};
9655size_t md_longopts_size = sizeof (md_longopts);
9656
9657int
9103f4f4 9658md_parse_option (int c, char *arg)
252b5132 9659{
91d6fa6a 9660 unsigned int j;
6305a203 9661 char *arch, *next;
9103f4f4 9662
252b5132
RH		 9663 switch (c)
9664 {
12b55ccc
L		 9665 case 'n':
9666 optimize_align_code = 0;
9667 break;
9668
a38cf1db
AM		 9669 case 'q':
9670 quiet_warnings = 1;
252b5132
RH		 9671 break;
9672
9673#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9674 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9675 should be emitted or not. FIXME: Not implemented. */
9676 case 'Q':
252b5132
RH		 9677 break;
9678
9679 /* -V: SVR4 argument to print version ID. */
9680 case 'V':
9681 print_version_id ();
9682 break;
9683
a38cf1db
AM		 9684 /* -k: Ignore for FreeBSD compatibility. */
9685 case 'k':
252b5132 9686 break;
4cc782b5
ILT		 9687
9688 case 's':
9689 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9690 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9691 break;
8dcea932
L		 9692
9693 case OPTION_MSHARED:
9694 shared = 1;
9695 break;
99ad8390 9696#endif
321098a5 9697#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9698 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9699 case OPTION_64:
9700 {
9701 const char **list, **l;
9702
3e73aa7c
JH		 9703 list = bfd_target_list ();
9704 for (l = list; *l != NULL; l++)
8620418b 9705 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9706 || strcmp (*l, "coff-x86-64") == 0
9707 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9708 || strcmp (*l, "pei-x86-64") == 0
9709 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9710 {
9711 default_arch = "x86_64";
9712 break;
9713 }
3e73aa7c 9714 if (*l == NULL)
2b5d6a91 9715 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9716 free (list);
9717 }
9718 break;
9719#endif
252b5132 9720
351f65ca 9721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9722 case OPTION_X32:
351f65ca
L		 9723 if (IS_ELF)
9724 {
9725 const char **list, **l;
9726
9727 list = bfd_target_list ();
9728 for (l = list; *l != NULL; l++)
9729 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9730 {
9731 default_arch = "x86_64:32";
9732 break;
9733 }
9734 if (*l == NULL)
2b5d6a91 9735 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9736 free (list);
9737 }
9738 else
9739 as_fatal (_("32bit x86_64 is only supported for ELF"));
9740 break;
9741#endif
9742
6e0b89ee
AM		 9743 case OPTION_32:
9744 default_arch = "i386";
9745 break;
9746
b3b91714
AM		 9747 case OPTION_DIVIDE:
9748#ifdef SVR4_COMMENT_CHARS
9749 {
9750 char *n, *t;
9751 const char *s;
9752
9753 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9754 t = n;
9755 for (s = i386_comment_chars; *s != '\0'; s++)
9756 if (*s != '/')
9757 *t++ = *s;
9758 *t = '\0';
9759 i386_comment_chars = n;
9760 }
9761#endif
9762 break;
9763
9103f4f4 9764 case OPTION_MARCH:
6305a203
L		 9765 arch = xstrdup (arg);
9766 do
9103f4f4 9767 {
6305a203 9768 if (*arch == '.')
2b5d6a91 9769 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9770 next = strchr (arch, '+');
9771 if (next)
9772 *next++ = '\0';
91d6fa6a 9773 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9774 {
91d6fa6a 9775 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9776 {
6305a203 9777 /* Processor. */
1ded5609
JB		 9778 if (! cpu_arch[j].flags.bitfield.cpui386)
9779 continue;
9780
91d6fa6a 9781 cpu_arch_name = cpu_arch[j].name;
6305a203 9782 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9783 cpu_arch_flags = cpu_arch[j].flags;
9784 cpu_arch_isa = cpu_arch[j].type;
9785 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9786 if (!cpu_arch_tune_set)
9787 {
9788 cpu_arch_tune = cpu_arch_isa;
9789 cpu_arch_tune_flags = cpu_arch_isa_flags;
9790 }
9791 break;
9792 }
91d6fa6a
NC		 9793 else if (*cpu_arch [j].name == '.'
9794 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9795 {
9796 /* ISA entension. */
9797 i386_cpu_flags flags;
309d3373 9798
49021df2 9799 if (!cpu_arch[j].negated)
309d3373 9800 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9801 cpu_arch[j].flags);
309d3373
JB		 9802 else
9803 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9804 cpu_arch[j].flags);
81486035
L		 9805
9806 if (!valid_iamcu_cpu_flags (&flags))
9807 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9808 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9809 {
9810 if (cpu_sub_arch_name)
9811 {
9812 char *name = cpu_sub_arch_name;
9813 cpu_sub_arch_name = concat (name,
91d6fa6a 9814 cpu_arch[j].name,
1bf57e9f 9815 (const char *) NULL);
6305a203
L		 9816 free (name);
9817 }
9818 else
91d6fa6a 9819 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9820 cpu_arch_flags = flags;
a586129e 9821 cpu_arch_isa_flags = flags;
6305a203
L		 9822 }
9823 break;
ccc9c027 9824 }
9103f4f4 9825 }
6305a203 9826
91d6fa6a 9827 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9828 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9829
9830 arch = next;
9103f4f4 9831 }
6305a203 9832 while (next != NULL );
9103f4f4
L		 9833 break;
9834
9835 case OPTION_MTUNE:
9836 if (*arg == '.')
2b5d6a91 9837 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9838 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9839 {
91d6fa6a 9840 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9841 {
ccc9c027 9842 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9843 cpu_arch_tune = cpu_arch [j].type;
9844 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9845 break;
9846 }
9847 }
91d6fa6a 9848 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9849 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9850 break;
9851
1efbbeb4
L		 9852 case OPTION_MMNEMONIC:
9853 if (strcasecmp (arg, "att") == 0)
9854 intel_mnemonic = 0;
9855 else if (strcasecmp (arg, "intel") == 0)
9856 intel_mnemonic = 1;
9857 else
2b5d6a91 9858 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9859 break;
9860
9861 case OPTION_MSYNTAX:
9862 if (strcasecmp (arg, "att") == 0)
9863 intel_syntax = 0;
9864 else if (strcasecmp (arg, "intel") == 0)
9865 intel_syntax = 1;
9866 else
2b5d6a91 9867 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9868 break;
9869
9870 case OPTION_MINDEX_REG:
9871 allow_index_reg = 1;
9872 break;
9873
9874 case OPTION_MNAKED_REG:
9875 allow_naked_reg = 1;
9876 break;
9877
9878 case OPTION_MOLD_GCC:
9879 old_gcc = 1;
1efbbeb4
L		 9880 break;
9881
c0f3af97
L		 9882 case OPTION_MSSE2AVX:
9883 sse2avx = 1;
9884 break;
9885
daf50ae7
L		 9886 case OPTION_MSSE_CHECK:
9887 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9888 sse_check = check_error;
daf50ae7 9889 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9890 sse_check = check_warning;
daf50ae7 9891 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9892 sse_check = check_none;
daf50ae7 9893 else
2b5d6a91 9894 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9895 break;
9896
7bab8ab5
JB		 9897 case OPTION_MOPERAND_CHECK:
9898 if (strcasecmp (arg, "error") == 0)
9899 operand_check = check_error;
9900 else if (strcasecmp (arg, "warning") == 0)
9901 operand_check = check_warning;
9902 else if (strcasecmp (arg, "none") == 0)
9903 operand_check = check_none;
9904 else
9905 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9906 break;
9907
539f890d
L		 9908 case OPTION_MAVXSCALAR:
9909 if (strcasecmp (arg, "128") == 0)
9910 avxscalar = vex128;
9911 else if (strcasecmp (arg, "256") == 0)
9912 avxscalar = vex256;
9913 else
2b5d6a91 9914 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9915 break;
9916
7e8b059b
L		 9917 case OPTION_MADD_BND_PREFIX:
9918 add_bnd_prefix = 1;
9919 break;
9920
43234a1e
L		 9921 case OPTION_MEVEXLIG:
9922 if (strcmp (arg, "128") == 0)
9923 evexlig = evexl128;
9924 else if (strcmp (arg, "256") == 0)
9925 evexlig = evexl256;
9926 else if (strcmp (arg, "512") == 0)
9927 evexlig = evexl512;
9928 else
9929 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9930 break;
9931
d3d3c6db
IT		 9932 case OPTION_MEVEXRCIG:
9933 if (strcmp (arg, "rne") == 0)
9934 evexrcig = rne;
9935 else if (strcmp (arg, "rd") == 0)
9936 evexrcig = rd;
9937 else if (strcmp (arg, "ru") == 0)
9938 evexrcig = ru;
9939 else if (strcmp (arg, "rz") == 0)
9940 evexrcig = rz;
9941 else
9942 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9943 break;
9944
43234a1e
L		 9945 case OPTION_MEVEXWIG:
9946 if (strcmp (arg, "0") == 0)
9947 evexwig = evexw0;
9948 else if (strcmp (arg, "1") == 0)
9949 evexwig = evexw1;
9950 else
9951 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9952 break;
9953
167ad85b
TG		 9954# if defined (TE_PE) || defined (TE_PEP)
9955 case OPTION_MBIG_OBJ:
9956 use_big_obj = 1;
9957 break;
9958#endif
9959
a5094208 9960 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9961 if (strcasecmp (arg, "yes") == 0)
9962 omit_lock_prefix = 1;
9963 else if (strcasecmp (arg, "no") == 0)
9964 omit_lock_prefix = 0;
9965 else
9966 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9967 break;
9968
5db04b09
L		 9969 case OPTION_MAMD64:
9970 cpu_arch_flags.bitfield.cpuamd64 = 1;
9971 cpu_arch_flags.bitfield.cpuintel64 = 0;
9972 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9973 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9974 break;
9975
9976 case OPTION_MINTEL64:
9977 cpu_arch_flags.bitfield.cpuamd64 = 0;
9978 cpu_arch_flags.bitfield.cpuintel64 = 1;
9979 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9980 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9981 break;
9982
252b5132
RH		 9983 default:
9984 return 0;
9985 }
9986 return 1;
9987}
9988
8a2c8fef
L		 9989#define MESSAGE_TEMPLATE \
9990" "
9991
9992static void
1ded5609 9993show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9994{
9995 static char message[] = MESSAGE_TEMPLATE;
9996 char *start = message + 27;
9997 char *p;
9998 int size = sizeof (MESSAGE_TEMPLATE);
9999 int left;
10000 const char *name;
10001 int len;
10002 unsigned int j;
10003
10004 p = start;
10005 left = size - (start - message);
10006 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10007 {
10008 /* Should it be skipped? */
10009 if (cpu_arch [j].skip)
10010 continue;
10011
10012 name = cpu_arch [j].name;
10013 len = cpu_arch [j].len;
10014 if (*name == '.')
10015 {
10016 /* It is an extension. Skip if we aren't asked to show it. */
10017 if (ext)
10018 {
10019 name++;
10020 len--;
10021 }
10022 else
10023 continue;
10024 }
10025 else if (ext)
10026 {
10027 /* It is an processor. Skip if we show only extension. */
10028 continue;
10029 }
1ded5609
JB		 10030 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10031 {
10032 /* It is an impossible processor - skip. */
10033 continue;
10034 }
8a2c8fef
L		 10035
10036 /* Reserve 2 spaces for ", " or ",\0" */
10037 left -= len + 2;
10038
10039 /* Check if there is any room. */
10040 if (left >= 0)
10041 {
10042 if (p != start)
10043 {
10044 *p++ = ',';
10045 *p++ = ' ';
10046 }
10047 p = mempcpy (p, name, len);
10048 }
10049 else
10050 {
10051 /* Output the current message now and start a new one. */
10052 *p++ = ',';
10053 *p = '\0';
10054 fprintf (stream, "%s\n", message);
10055 p = start;
10056 left = size - (start - message) - len - 2;
8d63c93e 10057
8a2c8fef
L		 10058 gas_assert (left >= 0);
10059
10060 p = mempcpy (p, name, len);
10061 }
10062 }
10063
10064 *p = '\0';
10065 fprintf (stream, "%s\n", message);
10066}
10067
252b5132 10068void
8a2c8fef 10069md_show_usage (FILE *stream)
252b5132 10070{
4cc782b5
ILT		 10071#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10072 fprintf (stream, _("\
a38cf1db
AM		 10073 -Q ignored\n\
10074 -V print assembler version number\n\
b3b91714
AM		 10075 -k ignored\n"));
10076#endif
10077 fprintf (stream, _("\
12b55ccc 10078 -n Do not optimize code alignment\n\
b3b91714
AM		 10079 -q quieten some warnings\n"));
10080#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10081 fprintf (stream, _("\
a38cf1db 10082 -s ignored\n"));
b3b91714 10083#endif
321098a5
L		 10084#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10085 || defined (TE_PE) || defined (TE_PEP))
751d281c 10086 fprintf (stream, _("\
570561f7 10087 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10088#endif
b3b91714
AM		 10089#ifdef SVR4_COMMENT_CHARS
10090 fprintf (stream, _("\
10091 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10092#else
10093 fprintf (stream, _("\
b3b91714 10094 --divide ignored\n"));
4cc782b5 10095#endif
9103f4f4 10096 fprintf (stream, _("\
6305a203 10097 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10098 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10099 show_arch (stream, 0, 1);
8a2c8fef
L		 10100 fprintf (stream, _("\
10101 EXTENSION is combination of:\n"));
1ded5609 10102 show_arch (stream, 1, 0);
6305a203 10103 fprintf (stream, _("\
8a2c8fef 10104 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10105 show_arch (stream, 0, 0);
ba104c83 10106 fprintf (stream, _("\
c0f3af97
L		 10107 -msse2avx encode SSE instructions with VEX prefix\n"));
10108 fprintf (stream, _("\
daf50ae7
L		 10109 -msse-check=[none|error|warning]\n\
10110 check SSE instructions\n"));
10111 fprintf (stream, _("\
7bab8ab5
JB		 10112 -moperand-check=[none|error|warning]\n\
10113 check operand combinations for validity\n"));
10114 fprintf (stream, _("\
539f890d
L		 10115 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10116 length\n"));
10117 fprintf (stream, _("\
43234a1e
L		 10118 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10119 length\n"));
10120 fprintf (stream, _("\
10121 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10122 for EVEX.W bit ignored instructions\n"));
10123 fprintf (stream, _("\
d3d3c6db
IT		 10124 -mevexrcig=[rne|rd|ru|rz]\n\
10125 encode EVEX instructions with specific EVEX.RC value\n\
10126 for SAE-only ignored instructions\n"));
10127 fprintf (stream, _("\
ba104c83
L		 10128 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10129 fprintf (stream, _("\
10130 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10131 fprintf (stream, _("\
10132 -mindex-reg support pseudo index registers\n"));
10133 fprintf (stream, _("\
10134 -mnaked-reg don't require `%%' prefix for registers\n"));
10135 fprintf (stream, _("\
10136 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10137 fprintf (stream, _("\
10138 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10139 fprintf (stream, _("\
10140 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10141# if defined (TE_PE) || defined (TE_PEP)
10142 fprintf (stream, _("\
10143 -mbig-obj generate big object files\n"));
10144#endif
d022bddd
IT		 10145 fprintf (stream, _("\
10146 -momit-lock-prefix=[no|yes]\n\
10147 strip all lock prefixes\n"));
5db04b09
L		 10148 fprintf (stream, _("\
10149 -mamd64 accept only AMD64 ISA\n"));
10150 fprintf (stream, _("\
10151 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10152}
10153
3e73aa7c 10154#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10155 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10156 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10157
10158/* Pick the target format to use. */
10159
47926f60 10160const char *
e3bb37b5 10161i386_target_format (void)
252b5132 10162{
351f65ca
L		 10163 if (!strncmp (default_arch, "x86_64", 6))
10164 {
10165 update_code_flag (CODE_64BIT, 1);
10166 if (default_arch[6] == '\0')
7f56bc95 10167 x86_elf_abi = X86_64_ABI;
351f65ca 10168 else
7f56bc95 10169 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10170 }
3e73aa7c 10171 else if (!strcmp (default_arch, "i386"))
78f12dd3 10172 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10173 else if (!strcmp (default_arch, "iamcu"))
10174 {
10175 update_code_flag (CODE_32BIT, 1);
10176 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10177 {
10178 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10179 cpu_arch_name = "iamcu";
10180 cpu_sub_arch_name = NULL;
10181 cpu_arch_flags = iamcu_flags;
10182 cpu_arch_isa = PROCESSOR_IAMCU;
10183 cpu_arch_isa_flags = iamcu_flags;
10184 if (!cpu_arch_tune_set)
10185 {
10186 cpu_arch_tune = cpu_arch_isa;
10187 cpu_arch_tune_flags = cpu_arch_isa_flags;
10188 }
10189 }
10190 else
10191 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10192 cpu_arch_name);
10193 }
3e73aa7c 10194 else
2b5d6a91 10195 as_fatal (_("unknown architecture"));
89507696
JB		 10196
10197 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10198 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10199 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10200 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10201
252b5132
RH		 10202 switch (OUTPUT_FLAVOR)
10203 {
9384f2ff 10204#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10205 case bfd_target_aout_flavour:
47926f60 10206 return AOUT_TARGET_FORMAT;
4c63da97 10207#endif
9384f2ff
AM		 10208#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10209# if defined (TE_PE) || defined (TE_PEP)
10210 case bfd_target_coff_flavour:
167ad85b
TG		 10211 if (flag_code == CODE_64BIT)
10212 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10213 else
10214 return "pe-i386";
9384f2ff 10215# elif defined (TE_GO32)
0561d57c
JK		 10216 case bfd_target_coff_flavour:
10217 return "coff-go32";
9384f2ff 10218# else
252b5132
RH		 10219 case bfd_target_coff_flavour:
10220 return "coff-i386";
9384f2ff 10221# endif
4c63da97 10222#endif
3e73aa7c 10223#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10224 case bfd_target_elf_flavour:
3e73aa7c 10225 {
351f65ca
L		 10226 const char *format;
10227
10228 switch (x86_elf_abi)
4fa24527 10229 {
351f65ca
L		 10230 default:
10231 format = ELF_TARGET_FORMAT;
10232 break;
7f56bc95 10233 case X86_64_ABI:
351f65ca 10234 use_rela_relocations = 1;
4fa24527 10235 object_64bit = 1;
351f65ca
L		 10236 format = ELF_TARGET_FORMAT64;
10237 break;
7f56bc95 10238 case X86_64_X32_ABI:
4fa24527 10239 use_rela_relocations = 1;
351f65ca 10240 object_64bit = 1;
862be3fb 10241 disallow_64bit_reloc = 1;
351f65ca
L		 10242 format = ELF_TARGET_FORMAT32;
10243 break;
4fa24527 10244 }
3632d14b 10245 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10246 {
7f56bc95 10247 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10248 as_fatal (_("Intel L1OM is 64bit only"));
10249 return ELF_TARGET_L1OM_FORMAT;
10250 }
b49f93f6 10251 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10252 {
10253 if (x86_elf_abi != X86_64_ABI)
10254 as_fatal (_("Intel K1OM is 64bit only"));
10255 return ELF_TARGET_K1OM_FORMAT;
10256 }
81486035
L		 10257 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10258 {
10259 if (x86_elf_abi != I386_ABI)
10260 as_fatal (_("Intel MCU is 32bit only"));
10261 return ELF_TARGET_IAMCU_FORMAT;
10262 }
8a9036a4 10263 else
351f65ca 10264 return format;
3e73aa7c 10265 }
e57f8c65
TG		 10266#endif
10267#if defined (OBJ_MACH_O)
10268 case bfd_target_mach_o_flavour:
d382c579
TG		 10269 if (flag_code == CODE_64BIT)
10270 {
10271 use_rela_relocations = 1;
10272 object_64bit = 1;
10273 return "mach-o-x86-64";
10274 }
10275 else
10276 return "mach-o-i386";
4c63da97 10277#endif
252b5132
RH		 10278 default:
10279 abort ();
10280 return NULL;
10281 }
10282}
10283
47926f60 10284#endif /* OBJ_MAYBE_ more than one */
252b5132 10285\f
252b5132 10286symbolS *
7016a5d5 10287md_undefined_symbol (char *name)
252b5132 10288{
18dc2407
ILT		 10289 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10290 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10291 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10292 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10293 {
10294 if (!GOT_symbol)
10295 {
10296 if (symbol_find (name))
10297 as_bad (_("GOT already in symbol table"));
10298 GOT_symbol = symbol_new (name, undefined_section,
10299 (valueT) 0, &zero_address_frag);
10300 };
10301 return GOT_symbol;
10302 }
252b5132
RH		 10303 return 0;
10304}
10305
10306/* Round up a section size to the appropriate boundary. */
47926f60 10307
252b5132 10308valueT
7016a5d5 10309md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10310{
4c63da97
AM		 10311#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10312 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10313 {
10314 /* For a.out, force the section size to be aligned. If we don't do
10315 this, BFD will align it for us, but it will not write out the
10316 final bytes of the section. This may be a bug in BFD, but it is
10317 easier to fix it here since that is how the other a.out targets
10318 work. */
10319 int align;
10320
10321 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10322 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10323 }
252b5132
RH		 10324#endif
10325
10326 return size;
10327}
10328
10329/* On the i386, PC-relative offsets are relative to the start of the
10330 next instruction. That is, the address of the offset, plus its
10331 size, since the offset is always the last part of the insn. */
10332
10333long
e3bb37b5 10334md_pcrel_from (fixS *fixP)
252b5132
RH		 10335{
10336 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10337}
10338
10339#ifndef I386COFF
10340
10341static void
e3bb37b5 10342s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10343{
29b0f896 10344 int temp;
252b5132 10345
8a75718c
JB		 10346#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10347 if (IS_ELF)
10348 obj_elf_section_change_hook ();
10349#endif
252b5132
RH		 10350 temp = get_absolute_expression ();
10351 subseg_set (bss_section, (subsegT) temp);
10352 demand_empty_rest_of_line ();
10353}
10354
10355#endif
10356
252b5132 10357void
e3bb37b5 10358i386_validate_fix (fixS *fixp)
252b5132 10359{
02a86693 10360 if (fixp->fx_subsy)
252b5132 10361 {
02a86693 10362 if (fixp->fx_subsy == GOT_symbol)
23df1078 10363 {
02a86693
L		 10364 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10365 {
10366 if (!object_64bit)
10367 abort ();
10368#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10369 if (fixp->fx_tcbit2)
56ceb5b5
L		 10370 fixp->fx_r_type = (fixp->fx_tcbit
10371 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10372 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10373 else
10374#endif
10375 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10376 }
d6ab8113 10377 else
02a86693
L		 10378 {
10379 if (!object_64bit)
10380 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10381 else
10382 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10383 }
10384 fixp->fx_subsy = 0;
23df1078 10385 }
252b5132 10386 }
02a86693
L		 10387#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10388 else if (!object_64bit)
10389 {
10390 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10391 && fixp->fx_tcbit2)
10392 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10393 }
10394#endif
252b5132
RH		 10395}
10396
252b5132 10397arelent *
7016a5d5 10398tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10399{
10400 arelent *rel;
10401 bfd_reloc_code_real_type code;
10402
10403 switch (fixp->fx_r_type)
10404 {
8ce3d284 10405#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10406 case BFD_RELOC_SIZE32:
10407 case BFD_RELOC_SIZE64:
10408 if (S_IS_DEFINED (fixp->fx_addsy)
10409 && !S_IS_EXTERNAL (fixp->fx_addsy))
10410 {
10411 /* Resolve size relocation against local symbol to size of
10412 the symbol plus addend. */
10413 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10414 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10415 && !fits_in_unsigned_long (value))
10416 as_bad_where (fixp->fx_file, fixp->fx_line,
10417 _("symbol size computation overflow"));
10418 fixp->fx_addsy = NULL;
10419 fixp->fx_subsy = NULL;
10420 md_apply_fix (fixp, (valueT *) &value, NULL);
10421 return NULL;
10422 }
8ce3d284 10423#endif
8fd4256d 10424
3e73aa7c
JH		 10425 case BFD_RELOC_X86_64_PLT32:
10426 case BFD_RELOC_X86_64_GOT32:
10427 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10428 case BFD_RELOC_X86_64_GOTPCRELX:
10429 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10430 case BFD_RELOC_386_PLT32:
10431 case BFD_RELOC_386_GOT32:
02a86693 10432 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10433 case BFD_RELOC_386_GOTOFF:
10434 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10435 case BFD_RELOC_386_TLS_GD:
10436 case BFD_RELOC_386_TLS_LDM:
10437 case BFD_RELOC_386_TLS_LDO_32:
10438 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10439 case BFD_RELOC_386_TLS_IE:
10440 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10441 case BFD_RELOC_386_TLS_LE_32:
10442 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10443 case BFD_RELOC_386_TLS_GOTDESC:
10444 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10445 case BFD_RELOC_X86_64_TLSGD:
10446 case BFD_RELOC_X86_64_TLSLD:
10447 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10448 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10449 case BFD_RELOC_X86_64_GOTTPOFF:
10450 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10451 case BFD_RELOC_X86_64_TPOFF64:
10452 case BFD_RELOC_X86_64_GOTOFF64:
10453 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10454 case BFD_RELOC_X86_64_GOT64:
10455 case BFD_RELOC_X86_64_GOTPCREL64:
10456 case BFD_RELOC_X86_64_GOTPC64:
10457 case BFD_RELOC_X86_64_GOTPLT64:
10458 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10459 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10460 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10461 case BFD_RELOC_RVA:
10462 case BFD_RELOC_VTABLE_ENTRY:
10463 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10464#ifdef TE_PE
10465 case BFD_RELOC_32_SECREL:
10466#endif
252b5132
RH		 10467 code = fixp->fx_r_type;
10468 break;
dbbaec26
L		 10469 case BFD_RELOC_X86_64_32S:
10470 if (!fixp->fx_pcrel)
10471 {
10472 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10473 code = fixp->fx_r_type;
10474 break;
10475 }
252b5132 10476 default:
93382f6d 10477 if (fixp->fx_pcrel)
252b5132 10478 {
93382f6d
AM		 10479 switch (fixp->fx_size)
10480 {
10481 default:
b091f402
AM		 10482 as_bad_where (fixp->fx_file, fixp->fx_line,
10483 _("can not do %d byte pc-relative relocation"),
10484 fixp->fx_size);
93382f6d
AM		 10485 code = BFD_RELOC_32_PCREL;
10486 break;
10487 case 1: code = BFD_RELOC_8_PCREL; break;
10488 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10489 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10490#ifdef BFD64
10491 case 8: code = BFD_RELOC_64_PCREL; break;
10492#endif
93382f6d
AM		 10493 }
10494 }
10495 else
10496 {
10497 switch (fixp->fx_size)
10498 {
10499 default:
b091f402
AM		 10500 as_bad_where (fixp->fx_file, fixp->fx_line,
10501 _("can not do %d byte relocation"),
10502 fixp->fx_size);
93382f6d
AM		 10503 code = BFD_RELOC_32;
10504 break;
10505 case 1: code = BFD_RELOC_8; break;
10506 case 2: code = BFD_RELOC_16; break;
10507 case 4: code = BFD_RELOC_32; break;
937149dd 10508#ifdef BFD64
3e73aa7c 10509 case 8: code = BFD_RELOC_64; break;
937149dd 10510#endif
93382f6d 10511 }
252b5132
RH		 10512 }
10513 break;
10514 }
252b5132 10515
d182319b
JB		 10516 if ((code == BFD_RELOC_32
10517 || code == BFD_RELOC_32_PCREL
10518 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10519 && GOT_symbol
10520 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10521 {
4fa24527 10522 if (!object_64bit)
d6ab8113
JB		 10523 code = BFD_RELOC_386_GOTPC;
10524 else
10525 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10526 }
7b81dfbb
AJ		 10527 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10528 && GOT_symbol
10529 && fixp->fx_addsy == GOT_symbol)
10530 {
10531 code = BFD_RELOC_X86_64_GOTPC64;
10532 }
252b5132
RH		 10533
10534 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10535 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10536 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10537
10538 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10539
3e73aa7c
JH		 10540 if (!use_rela_relocations)
10541 {
10542 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10543 vtable entry to be used in the relocation's section offset. */
10544 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10545 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10546#if defined (OBJ_COFF) && defined (TE_PE)
10547 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10548 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10549 else
10550#endif
c6682705 10551 rel->addend = 0;
3e73aa7c
JH		 10552 }
10553 /* Use the rela in 64bit mode. */
252b5132 10554 else
3e73aa7c 10555 {
862be3fb
L		 10556 if (disallow_64bit_reloc)
10557 switch (code)
10558 {
862be3fb
L		 10559 case BFD_RELOC_X86_64_DTPOFF64:
10560 case BFD_RELOC_X86_64_TPOFF64:
10561 case BFD_RELOC_64_PCREL:
10562 case BFD_RELOC_X86_64_GOTOFF64:
10563 case BFD_RELOC_X86_64_GOT64:
10564 case BFD_RELOC_X86_64_GOTPCREL64:
10565 case BFD_RELOC_X86_64_GOTPC64:
10566 case BFD_RELOC_X86_64_GOTPLT64:
10567 case BFD_RELOC_X86_64_PLTOFF64:
10568 as_bad_where (fixp->fx_file, fixp->fx_line,
10569 _("cannot represent relocation type %s in x32 mode"),
10570 bfd_get_reloc_code_name (code));
10571 break;
10572 default:
10573 break;
10574 }
10575
062cd5e7
AS		 10576 if (!fixp->fx_pcrel)
10577 rel->addend = fixp->fx_offset;
10578 else
10579 switch (code)
10580 {
10581 case BFD_RELOC_X86_64_PLT32:
10582 case BFD_RELOC_X86_64_GOT32:
10583 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10584 case BFD_RELOC_X86_64_GOTPCRELX:
10585 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10586 case BFD_RELOC_X86_64_TLSGD:
10587 case BFD_RELOC_X86_64_TLSLD:
10588 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10589 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10590 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10591 rel->addend = fixp->fx_offset - fixp->fx_size;
10592 break;
10593 default:
10594 rel->addend = (section->vma
10595 - fixp->fx_size
10596 + fixp->fx_addnumber
10597 + md_pcrel_from (fixp));
10598 break;
10599 }
3e73aa7c
JH		 10600 }
10601
252b5132
RH		 10602 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10603 if (rel->howto == NULL)
10604 {
10605 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10606 _("cannot represent relocation type %s"),
252b5132
RH		 10607 bfd_get_reloc_code_name (code));
10608 /* Set howto to a garbage value so that we can keep going. */
10609 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10610 gas_assert (rel->howto != NULL);
252b5132
RH		 10611 }
10612
10613 return rel;
10614}
10615
ee86248c 10616#include "tc-i386-intel.c"
54cfded0 10617
a60de03c
JB		 10618void
10619tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10620{
a60de03c
JB		 10621 int saved_naked_reg;
10622 char saved_register_dot;
54cfded0 10623
a60de03c
JB		 10624 saved_naked_reg = allow_naked_reg;
10625 allow_naked_reg = 1;
10626 saved_register_dot = register_chars['.'];
10627 register_chars['.'] = '.';
10628 allow_pseudo_reg = 1;
10629 expression_and_evaluate (exp);
10630 allow_pseudo_reg = 0;
10631 register_chars['.'] = saved_register_dot;
10632 allow_naked_reg = saved_naked_reg;
10633
e96d56a1 10634 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10635 {
a60de03c
JB		 10636 if ((addressT) exp->X_add_number < i386_regtab_size)
10637 {
10638 exp->X_op = O_constant;
10639 exp->X_add_number = i386_regtab[exp->X_add_number]
10640 .dw2_regnum[flag_code >> 1];
10641 }
10642 else
10643 exp->X_op = O_illegal;
54cfded0 10644 }
54cfded0
AM		 10645}
10646
10647void
10648tc_x86_frame_initial_instructions (void)
10649{
a60de03c
JB		 10650 static unsigned int sp_regno[2];
10651
10652 if (!sp_regno[flag_code >> 1])
10653 {
10654 char *saved_input = input_line_pointer;
10655 char sp[][4] = {"esp", "rsp"};
10656 expressionS exp;
a4447b93 10657
a60de03c
JB		 10658 input_line_pointer = sp[flag_code >> 1];
10659 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10660 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10661 sp_regno[flag_code >> 1] = exp.X_add_number;
10662 input_line_pointer = saved_input;
10663 }
a4447b93 10664
61ff971f
L		 10665 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10666 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10667}
d2b2c203 10668
d7921315
L		 10669int
10670x86_dwarf2_addr_size (void)
10671{
10672#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10673 if (x86_elf_abi == X86_64_X32_ABI)
10674 return 4;
10675#endif
10676 return bfd_arch_bits_per_address (stdoutput) / 8;
10677}
10678
d2b2c203
DJ		 10679int
10680i386_elf_section_type (const char *str, size_t len)
10681{
10682 if (flag_code == CODE_64BIT
10683 && len == sizeof ("unwind") - 1
10684 && strncmp (str, "unwind", 6) == 0)
10685 return SHT_X86_64_UNWIND;
10686
10687 return -1;
10688}
bb41ade5 10689
ad5fec3b
EB		 10690#ifdef TE_SOLARIS
10691void
10692i386_solaris_fix_up_eh_frame (segT sec)
10693{
10694 if (flag_code == CODE_64BIT)
10695 elf_section_type (sec) = SHT_X86_64_UNWIND;
10696}
10697#endif
10698
bb41ade5
AM		 10699#ifdef TE_PE
10700void
10701tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10702{
91d6fa6a 10703 expressionS exp;
bb41ade5 10704
91d6fa6a
NC		 10705 exp.X_op = O_secrel;
10706 exp.X_add_symbol = symbol;
10707 exp.X_add_number = 0;
10708 emit_expr (&exp, size);
bb41ade5
AM		 10709}
10710#endif
3b22753a
L		 10711
10712#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10713/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10714
01e1a5bc 10715bfd_vma
3b22753a
L		 10716x86_64_section_letter (int letter, char **ptr_msg)
10717{
10718 if (flag_code == CODE_64BIT)
10719 {
10720 if (letter == 'l')
10721 return SHF_X86_64_LARGE;
10722
8f3bae45 10723 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10724 }
3b22753a 10725 else
8f3bae45 10726 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10727 return -1;
10728}
10729
01e1a5bc 10730bfd_vma
3b22753a
L		 10731x86_64_section_word (char *str, size_t len)
10732{
8620418b 10733 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10734 return SHF_X86_64_LARGE;
10735
10736 return -1;
10737}
10738
10739static void
10740handle_large_common (int small ATTRIBUTE_UNUSED)
10741{
10742 if (flag_code != CODE_64BIT)
10743 {
10744 s_comm_internal (0, elf_common_parse);
10745 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10746 }
10747 else
10748 {
10749 static segT lbss_section;
10750 asection *saved_com_section_ptr = elf_com_section_ptr;
10751 asection *saved_bss_section = bss_section;
10752
10753 if (lbss_section == NULL)
10754 {
10755 flagword applicable;
10756 segT seg = now_seg;
10757 subsegT subseg = now_subseg;
10758
10759 /* The .lbss section is for local .largecomm symbols. */
10760 lbss_section = subseg_new (".lbss", 0);
10761 applicable = bfd_applicable_section_flags (stdoutput);
10762 bfd_set_section_flags (stdoutput, lbss_section,
10763 applicable & SEC_ALLOC);
10764 seg_info (lbss_section)->bss = 1;
10765
10766 subseg_set (seg, subseg);
10767 }
10768
10769 elf_com_section_ptr = &_bfd_elf_large_com_section;
10770 bss_section = lbss_section;
10771
10772 s_comm_internal (0, elf_common_parse);
10773
10774 elf_com_section_ptr = saved_com_section_ptr;
10775 bss_section = saved_bss_section;
10776 }
10777}
10778#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.773498 seconds and 4 git commands to generate.