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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
4d456e3d 81static void swap_2_operands (int, int);
e3bb37b5
L		 82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
252b5132
RH		 135 unsigned int types[MAX_OPERANDS];
136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
2ca3ace5
L		 294/* Register prefix used for error message. */
295static const char *register_prefix = "%";
296
47926f60
KH		 297/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300static char stackop_size = '\0';
eecb386c 301
12b55ccc
L		 302/* Non-zero to optimize code alignment. */
303int optimize_align_code = 1;
304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
5c6af06e 310static const char *cpu_sub_arch_name = NULL;
a38cf1db 311
47926f60 312/* CPU feature flags. */
29b0f896 313static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 314
ccc9c027
L		 315/* If we have selected a cpu we are generating instructions for. */
316static int cpu_arch_tune_set = 0;
317
9103f4f4
L		 318/* Cpu we are generating instructions for. */
319static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
320
321/* CPU feature flags of cpu we are generating instructions for. */
322static unsigned int cpu_arch_tune_flags = 0;
323
ccc9c027
L		 324/* CPU instruction set architecture used. */
325static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
326
9103f4f4
L		 327/* CPU feature flags of instruction set architecture used. */
328static unsigned int cpu_arch_isa_flags = 0;
329
fddf5b5b
AM		 330/* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332static unsigned int no_cond_jump_promotion = 0;
333
29b0f896 334/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 335static symbolS *GOT_symbol;
29b0f896 336
a4447b93
RH		 337/* The dwarf2 return column, adjusted for 32 or 64 bit. */
338unsigned int x86_dwarf2_return_column;
339
340/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341int x86_cie_data_alignment;
342
252b5132 343/* Interface to relax_segment.
fddf5b5b
AM		 344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
252b5132 347
47926f60 348/* Types. */
93c2a809
AM		 349#define UNCOND_JUMP 0
350#define COND_JUMP 1
351#define COND_JUMP86 2
fddf5b5b 352
47926f60 353/* Sizes. */
252b5132
RH		 354#define CODE16 1
355#define SMALL 0
29b0f896 356#define SMALL16 (SMALL | CODE16)
252b5132 357#define BIG 2
29b0f896 358#define BIG16 (BIG | CODE16)
252b5132
RH		 359
360#ifndef INLINE
361#ifdef __GNUC__
362#define INLINE __inline__
363#else
364#define INLINE
365#endif
366#endif
367
fddf5b5b
AM		 368#define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370#define TYPE_FROM_RELAX_STATE(s) \
371 ((s) >> 2)
372#define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 374
375/* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
382
383const relax_typeS md_relax_table[] =
384{
24eab124
AM		 385 /* The fields are:
386 1) most positive reach of this state,
387 2) most negative reach of this state,
93c2a809 388 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 389 4) which index into the table to try if we can't fit into this one. */
252b5132 390
fddf5b5b 391 /* UNCOND_JUMP states. */
93c2a809
AM		 392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
252b5132 396 {0, 0, 4, 0},
93c2a809
AM		 397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 399 {0, 0, 2, 0},
400
93c2a809
AM		 401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
406 {0, 0, 5, 0},
fddf5b5b 407 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 408 1 extra opcode byte, 2 displacement bytes. */
409 {0, 0, 3, 0},
410
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
416 {0, 0, 5, 0},
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
419 {0, 0, 4, 0}
252b5132
RH		 420};
421
9103f4f4
L		 422static const arch_entry cpu_arch[] =
423{
424 {"generic32", PROCESSOR_GENERIC32,
d32cad65 425 Cpu186|Cpu286|Cpu386},
9103f4f4 426 {"generic64", PROCESSOR_GENERIC64,
d32cad65 427 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 428 |CpuMMX2|CpuSSE|CpuSSE2},
429 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 430 0},
9103f4f4 431 {"i186", PROCESSOR_UNKNOWN,
d32cad65 432 Cpu186},
9103f4f4 433 {"i286", PROCESSOR_UNKNOWN,
d32cad65 434 Cpu186|Cpu286},
9103f4f4 435 {"i386", PROCESSOR_GENERIC32,
d32cad65 436 Cpu186|Cpu286|Cpu386},
9103f4f4 437 {"i486", PROCESSOR_I486,
d32cad65 438 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 439 {"i586", PROCESSOR_PENTIUM,
d32cad65 440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 441 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 442 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 443 {"pentium", PROCESSOR_PENTIUM,
d32cad65 444 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 446 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 447 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 448 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 451 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 453 |CpuMMX2|CpuSSE|CpuSSE2},
454 {"prescott", PROCESSOR_NOCONA,
d32cad65 455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
457 {"nocona", PROCESSOR_NOCONA,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 460 {"yonah", PROCESSOR_CORE,
d32cad65 461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 463 {"core", PROCESSOR_CORE,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"merom", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
469 {"core2", PROCESSOR_CORE2,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 472 {"k6", PROCESSOR_K6,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 474 {"k6_2", PROCESSOR_K6,
d32cad65 475 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 476 {"athlon", PROCESSOR_ATHLON,
d32cad65 477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
d32cad65 480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
d32cad65 483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
485 {"k8", PROCESSOR_K8,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 488 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
491 |CpuABM},
9103f4f4
L		 492 {".mmx", PROCESSOR_UNKNOWN,
493 CpuMMX},
494 {".sse", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE},
496 {".sse2", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
498 {".sse3", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 500 {".ssse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 502 {".3dnow", PROCESSOR_UNKNOWN,
503 CpuMMX|Cpu3dnow},
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
507 CpuPadLock},
508 {".pacifica", PROCESSOR_UNKNOWN,
509 CpuSVME},
510 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 511 CpuSVME},
512 {".sse4a", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
514 {".abm", PROCESSOR_UNKNOWN,
515 CpuABM}
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
07a53e5c 544#else
e3bb37b5 545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 548#endif
6482c264
NC		 549#ifdef TE_PE
550 {"secrel32", pe_directive_secrel, 0},
551#endif
29b0f896
AM		 552 {0, 0, 0}
553};
554
555/* For interface with expression (). */
556extern char *input_line_pointer;
557
558/* Hash table for instruction mnemonic lookup. */
559static struct hash_control *op_hash;
560
561/* Hash table for register lookup. */
562static struct hash_control *reg_hash;
563\f
252b5132 564void
e3bb37b5 565i386_align_code (fragS *fragP, int count)
252b5132 566{
ce8a8b2f
AM		 567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
252b5132
RH		 570 static const char f32_1[] =
571 {0x90}; /* nop */
572 static const char f32_2[] =
ccc9c027 573 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
579 {0x90, /* nop */
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
586 {0x90, /* nop */
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 609 static const char f16_3[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 611 static const char f16_4[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5[] =
614 {0x90, /* nop */
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
628 };
629 static const char *const f16_patt[] = {
c3332e24 630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 631 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
632 };
ccc9c027
L		 633 /* nopl (%[re]ax) */
634 static const char alt_3[] =
635 {0x0f,0x1f,0x00};
636 /* nopl 0(%[re]ax) */
637 static const char alt_4[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* data16
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11[] =
660 {0x66,
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12[] =
666 {0x66,
667 0x66,
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 /* data16
670 data16
671 data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13[] =
674 {0x66,
675 0x66,
676 0x66,
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 /* data16
679 data16
680 data16
681 data16
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14[] =
684 {0x66,
685 0x66,
686 0x66,
687 0x66,
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
689 /* data16
690 data16
691 data16
692 data16
693 data16
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15[] =
696 {0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopl 0L(%[re]ax) */
714 static const char alt_short_13[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
717 /* nopl 0L(%[re]ax)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_14[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt[] = {
728 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
729 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
730 alt_short_14, alt_short_15
731 };
732 static const char *const alt_long_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
735 alt_long_14, alt_long_15
736 };
252b5132 737
33fef721
JH		 738 if (count <= 0 || count > 15)
739 return;
3e73aa7c 740
ccc9c027
L		 741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
743
744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
050dfa73 746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
751
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
762 if (count > 8)
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
765 }
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 767 {
33fef721
JH		 768 int i;
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
772 int pos = 0;
773
ccc9c027
L		 774 /* The recommended way to pad 64bit code is to use NOPs preceded
775 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 776 for (i = 0; i < remains; i++)
252b5132 777 {
33fef721
JH		 778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
780 pos += len + 1;
781 }
782 for (; i < nnops; i++)
783 {
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
786 pos += len;
252b5132 787 }
252b5132 788 }
33fef721 789 else
ccc9c027
L		 790 {
791 const char *const *patt = NULL;
792
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
794 {
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
797 {
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
803 else
804 patt = f32_patt;
805 break;
ef05d495 806 case PROCESSOR_CORE2:
ccc9c027
L		 807 patt = alt_long_patt;
808 break;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
ef05d495 812 case PROCESSOR_CORE:
ccc9c027
L		 813 case PROCESSOR_K6:
814 case PROCESSOR_ATHLON:
815 case PROCESSOR_K8:
816 case PROCESSOR_GENERIC64:
050dfa73 817 case PROCESSOR_AMDFAM10:
ccc9c027
L		 818 patt = alt_short_patt;
819 break;
820 case PROCESSOR_I486:
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
823 patt = f32_patt;
824 break;
825 }
826 }
827 else
828 {
829 switch (cpu_arch_tune)
830 {
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
834 abort ();
835 break;
836
837 case PROCESSOR_I486:
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
ef05d495 842 case PROCESSOR_CORE:
ccc9c027
L		 843 case PROCESSOR_K6:
844 case PROCESSOR_ATHLON:
845 case PROCESSOR_K8:
050dfa73 846 case PROCESSOR_AMDFAM10:
ccc9c027
L		 847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
849 for Cpu686. */
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
852 else
853 patt = f32_patt;
854 break;
ef05d495 855 case PROCESSOR_CORE2:
ccc9c027
L		 856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
863 break;
864 }
865 }
866
33fef721 867 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 868 patt[count - 1], count);
869 }
33fef721 870 fragP->fr_var = count;
252b5132
RH		 871}
872
252b5132 873static INLINE unsigned int
e3bb37b5 874mode_from_disp_size (unsigned int t)
252b5132 875{
3e73aa7c 876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 877}
878
879static INLINE int
e3bb37b5 880fits_in_signed_byte (offsetT num)
252b5132
RH		 881{
882 return (num >= -128) && (num <= 127);
47926f60 883}
252b5132
RH		 884
885static INLINE int
e3bb37b5 886fits_in_unsigned_byte (offsetT num)
252b5132
RH		 887{
888 return (num & 0xff) == num;
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_word (offsetT num)
252b5132
RH		 893{
894 return (num & 0xffff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_signed_word (offsetT num)
252b5132
RH		 899{
900 return (-32768 <= num) && (num <= 32767);
47926f60 901}
2a962e6d 902
3e73aa7c 903static INLINE int
e3bb37b5 904fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 905{
906#ifndef BFD64
907 return 1;
908#else
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
911#endif
912} /* fits_in_signed_long() */
2a962e6d 913
3e73aa7c 914static INLINE int
e3bb37b5 915fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 916{
917#ifndef BFD64
918 return 1;
919#else
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
921#endif
922} /* fits_in_unsigned_long() */
252b5132 923
1509aa9a 924static unsigned int
e3bb37b5 925smallest_imm_type (offsetT num)
252b5132 926{
d32cad65 927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 928 {
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
933 use that form. */
934 if (num == 1)
3e73aa7c 935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 936 }
252b5132 937 return (fits_in_signed_byte (num)
3e73aa7c 938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 939 : fits_in_unsigned_byte (num)
3e73aa7c 940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
946 ? (Imm32 | Imm64)
947 : Imm64);
47926f60 948}
252b5132 949
847f7ad4 950static offsetT
e3bb37b5 951offset_in_range (offsetT val, int size)
847f7ad4 952{
508866be 953 addressT mask;
ba2adb93 954
847f7ad4
AM		 955 switch (size)
956 {
508866be
L		 957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 959 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 960#ifdef BFD64
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
962#endif
47926f60 963 default: abort ();
847f7ad4
AM		 964 }
965
ba2adb93 966 /* If BFD64, sign extend val. */
3e73aa7c
JH		 967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 970
47926f60 971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 972 {
973 char buf1[40], buf2[40];
974
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
978 }
979 return val & mask;
980}
981
252b5132
RH		 982/* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
984 added. */
985static int
e3bb37b5 986add_prefix (unsigned int prefix)
252b5132
RH		 987{
988 int ret = 1;
b1905489 989 unsigned int q;
252b5132 990
29b0f896
AM		 991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
b1905489
JB		 993 {
994 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
995 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
996 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
997 ret = 0;
998 q = REX_PREFIX;
999 }
3e73aa7c 1000 else
b1905489
JB		 1001 {
1002 switch (prefix)
1003 {
1004 default:
1005 abort ();
1006
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1013 q = SEG_PREFIX;
1014 break;
1015
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1018 ret = 2;
1019 /* fall thru */
1020 case LOCK_PREFIX_OPCODE:
1021 q = LOCKREP_PREFIX;
1022 break;
1023
1024 case FWAIT_OPCODE:
1025 q = WAIT_PREFIX;
1026 break;
1027
1028 case ADDR_PREFIX_OPCODE:
1029 q = ADDR_PREFIX;
1030 break;
1031
1032 case DATA_PREFIX_OPCODE:
1033 q = DATA_PREFIX;
1034 break;
1035 }
1036 if (i.prefix[q] != 0)
1037 ret = 0;
1038 }
252b5132 1039
b1905489 1040 if (ret)
252b5132 1041 {
b1905489
JB		 1042 if (!i.prefix[q])
1043 ++i.prefixes;
1044 i.prefix[q] |= prefix;
252b5132 1045 }
b1905489
JB		 1046 else
1047 as_bad (_("same type of prefix used twice"));
252b5132 1048
252b5132
RH		 1049 return ret;
1050}
1051
1052static void
e3bb37b5 1053set_code_flag (int value)
eecb386c 1054{
3e73aa7c
JH		 1055 flag_code = value;
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1059 {
1060 as_bad (_("64bit mode not supported on this CPU."));
1061 }
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1063 {
1064 as_bad (_("32bit mode not supported on this CPU."));
1065 }
eecb386c
AM		 1066 stackop_size = '\0';
1067}
1068
1069static void
e3bb37b5 1070set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1071{
3e73aa7c
JH		 1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1075 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1076}
1077
1078static void
e3bb37b5 1079set_intel_syntax (int syntax_flag)
252b5132
RH		 1080{
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1083
1084 SKIP_WHITESPACE ();
29b0f896 1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1086 {
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1089
47926f60 1090 if (strcmp (string, "prefix") == 0)
252b5132 1091 ask_naked_reg = 1;
47926f60 1092 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1093 ask_naked_reg = -1;
1094 else
d0b47220 1095 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1096 *input_line_pointer = e;
1097 }
1098 demand_empty_rest_of_line ();
c3332e24 1099
252b5132
RH		 1100 intel_syntax = syntax_flag;
1101
1102 if (ask_naked_reg == 0)
f86103b7
AM		 1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1105 else
1106 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1107
e4a3b5a4 1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1110 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1111}
1112
e413e4e9 1113static void
e3bb37b5 1114set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1115{
47926f60 1116 SKIP_WHITESPACE ();
e413e4e9 1117
29b0f896 1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1119 {
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
9103f4f4 1122 unsigned int i;
e413e4e9 1123
9103f4f4 1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1125 {
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1127 {
5c6af06e
JB		 1128 if (*string != '.')
1129 {
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
1133 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1134 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1135 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1136 if (!cpu_arch_tune_set)
1137 {
1138 cpu_arch_tune = cpu_arch_isa;
1139 cpu_arch_tune_flags = cpu_arch_isa_flags;
1140 }
5c6af06e
JB		 1141 break;
1142 }
1143 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1144 {
1145 cpu_sub_arch_name = cpu_arch[i].name;
1146 cpu_arch_flags |= cpu_arch[i].flags;
1147 }
1148 *input_line_pointer = e;
1149 demand_empty_rest_of_line ();
1150 return;
e413e4e9
AM		 1151 }
1152 }
9103f4f4 1153 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1154 as_bad (_("no such architecture: `%s'"), string);
1155
1156 *input_line_pointer = e;
1157 }
1158 else
1159 as_bad (_("missing cpu architecture"));
1160
fddf5b5b
AM		 1161 no_cond_jump_promotion = 0;
1162 if (*input_line_pointer == ','
29b0f896 1163 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1164 {
1165 char *string = ++input_line_pointer;
1166 int e = get_symbol_end ();
1167
1168 if (strcmp (string, "nojumps") == 0)
1169 no_cond_jump_promotion = 1;
1170 else if (strcmp (string, "jumps") == 0)
1171 ;
1172 else
1173 as_bad (_("no such architecture modifier: `%s'"), string);
1174
1175 *input_line_pointer = e;
1176 }
1177
e413e4e9
AM		 1178 demand_empty_rest_of_line ();
1179}
1180
b9d79e03
JH		 1181unsigned long
1182i386_mach ()
1183{
1184 if (!strcmp (default_arch, "x86_64"))
1185 return bfd_mach_x86_64;
1186 else if (!strcmp (default_arch, "i386"))
1187 return bfd_mach_i386_i386;
1188 else
1189 as_fatal (_("Unknown architecture"));
1190}
b9d79e03 1191\f
252b5132
RH		 1192void
1193md_begin ()
1194{
1195 const char *hash_err;
1196
47926f60 1197 /* Initialize op_hash hash table. */
252b5132
RH		 1198 op_hash = hash_new ();
1199
1200 {
29b0f896
AM		 1201 const template *optab;
1202 templates *core_optab;
252b5132 1203
47926f60
KH		 1204 /* Setup for loop. */
1205 optab = i386_optab;
252b5132
RH		 1206 core_optab = (templates *) xmalloc (sizeof (templates));
1207 core_optab->start = optab;
1208
1209 while (1)
1210 {
1211 ++optab;
1212 if (optab->name == NULL
1213 || strcmp (optab->name, (optab - 1)->name) != 0)
1214 {
1215 /* different name --> ship out current template list;
47926f60 1216 add to hash table; & begin anew. */
252b5132
RH		 1217 core_optab->end = optab;
1218 hash_err = hash_insert (op_hash,
1219 (optab - 1)->name,
1220 (PTR) core_optab);
1221 if (hash_err)
1222 {
252b5132
RH		 1223 as_fatal (_("Internal Error: Can't hash %s: %s"),
1224 (optab - 1)->name,
1225 hash_err);
1226 }
1227 if (optab->name == NULL)
1228 break;
1229 core_optab = (templates *) xmalloc (sizeof (templates));
1230 core_optab->start = optab;
1231 }
1232 }
1233 }
1234
47926f60 1235 /* Initialize reg_hash hash table. */
252b5132
RH		 1236 reg_hash = hash_new ();
1237 {
29b0f896 1238 const reg_entry *regtab;
252b5132
RH		 1239
1240 for (regtab = i386_regtab;
1241 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1242 regtab++)
1243 {
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1245 if (hash_err)
3e73aa7c
JH		 1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1247 regtab->reg_name,
1248 hash_err);
252b5132
RH		 1249 }
1250 }
1251
47926f60 1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1253 {
29b0f896
AM		 1254 int c;
1255 char *p;
252b5132
RH		 1256
1257 for (c = 0; c < 256; c++)
1258 {
3882b010 1259 if (ISDIGIT (c))
252b5132
RH		 1260 {
1261 digit_chars[c] = c;
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1265 }
3882b010 1266 else if (ISLOWER (c))
252b5132
RH		 1267 {
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISUPPER (c))
252b5132 1273 {
3882b010 1274 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1277 }
1278
3882b010 1279 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1280 identifier_chars[c] = c;
1281 else if (c >= 128)
1282 {
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1285 }
1286 }
1287
1288#ifdef LEX_AT
1289 identifier_chars['@'] = '@';
32137342
NC		 1290#endif
1291#ifdef LEX_QM
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
252b5132 1294#endif
252b5132 1295 digit_chars['-'] = '-';
791fe849 1296 mnemonic_chars['-'] = '-';
252b5132
RH		 1297 identifier_chars['_'] = '_';
1298 identifier_chars['.'] = '.';
1299
1300 for (p = operand_special_chars; *p != '\0'; p++)
1301 operand_chars[(unsigned char) *p] = *p;
1302 }
1303
1304#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1305 if (IS_ELF)
252b5132
RH		 1306 {
1307 record_alignment (text_section, 2);
1308 record_alignment (data_section, 2);
1309 record_alignment (bss_section, 2);
1310 }
1311#endif
a4447b93
RH		 1312
1313 if (flag_code == CODE_64BIT)
1314 {
1315 x86_dwarf2_return_column = 16;
1316 x86_cie_data_alignment = -8;
1317 }
1318 else
1319 {
1320 x86_dwarf2_return_column = 8;
1321 x86_cie_data_alignment = -4;
1322 }
252b5132
RH		 1323}
1324
1325void
e3bb37b5 1326i386_print_statistics (FILE *file)
252b5132
RH		 1327{
1328 hash_print_statistics (file, "i386 opcode", op_hash);
1329 hash_print_statistics (file, "i386 register", reg_hash);
1330}
1331\f
252b5132
RH		 1332#ifdef DEBUG386
1333
ce8a8b2f 1334/* Debugging routines for md_assemble. */
e3bb37b5
L		 1335static void pte (template *);
1336static void pt (unsigned int);
1337static void pe (expressionS *);
1338static void ps (symbolS *);
252b5132
RH		 1339
1340static void
e3bb37b5 1341pi (char *line, i386_insn *x)
252b5132 1342{
09f131f2 1343 unsigned int i;
252b5132
RH		 1344
1345 fprintf (stdout, "%s: template ", line);
1346 pte (&x->tm);
09f131f2
JH		 1347 fprintf (stdout, " address: base %s index %s scale %x\n",
1348 x->base_reg ? x->base_reg->reg_name : "none",
1349 x->index_reg ? x->index_reg->reg_name : "none",
1350 x->log2_scale_factor);
1351 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1352 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1353 fprintf (stdout, " sib: base %x index %x scale %x\n",
1354 x->sib.base, x->sib.index, x->sib.scale);
1355 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1356 (x->rex & REX_MODE64) != 0,
1357 (x->rex & REX_EXTX) != 0,
1358 (x->rex & REX_EXTY) != 0,
1359 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1360 for (i = 0; i < x->operands; i++)
1361 {
1362 fprintf (stdout, " #%d: ", i + 1);
1363 pt (x->types[i]);
1364 fprintf (stdout, "\n");
1365 if (x->types[i]
3f4438ab 1366 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1367 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1368 if (x->types[i] & Imm)
520dc8e8 1369 pe (x->op[i].imms);
252b5132 1370 if (x->types[i] & Disp)
520dc8e8 1371 pe (x->op[i].disps);
252b5132
RH		 1372 }
1373}
1374
1375static void
e3bb37b5 1376pte (template *t)
252b5132 1377{
09f131f2 1378 unsigned int i;
252b5132 1379 fprintf (stdout, " %d operands ", t->operands);
47926f60 1380 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1381 if (t->extension_opcode != None)
1382 fprintf (stdout, "ext %x ", t->extension_opcode);
1383 if (t->opcode_modifier & D)
1384 fprintf (stdout, "D");
1385 if (t->opcode_modifier & W)
1386 fprintf (stdout, "W");
1387 fprintf (stdout, "\n");
1388 for (i = 0; i < t->operands; i++)
1389 {
1390 fprintf (stdout, " #%d type ", i + 1);
1391 pt (t->operand_types[i]);
1392 fprintf (stdout, "\n");
1393 }
1394}
1395
1396static void
e3bb37b5 1397pe (expressionS *e)
252b5132 1398{
24eab124 1399 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1400 fprintf (stdout, " add_number %ld (%lx)\n",
1401 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1402 if (e->X_add_symbol)
1403 {
1404 fprintf (stdout, " add_symbol ");
1405 ps (e->X_add_symbol);
1406 fprintf (stdout, "\n");
1407 }
1408 if (e->X_op_symbol)
1409 {
1410 fprintf (stdout, " op_symbol ");
1411 ps (e->X_op_symbol);
1412 fprintf (stdout, "\n");
1413 }
1414}
1415
1416static void
e3bb37b5 1417ps (symbolS *s)
252b5132
RH		 1418{
1419 fprintf (stdout, "%s type %s%s",
1420 S_GET_NAME (s),
1421 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1422 segment_name (S_GET_SEGMENT (s)));
1423}
1424
7b81dfbb 1425static struct type_name
252b5132
RH		 1426 {
1427 unsigned int mask;
1428 char *tname;
1429 }
7b81dfbb 1430const type_names[] =
252b5132
RH		 1431{
1432 { Reg8, "r8" },
1433 { Reg16, "r16" },
1434 { Reg32, "r32" },
09f131f2 1435 { Reg64, "r64" },
252b5132
RH		 1436 { Imm8, "i8" },
1437 { Imm8S, "i8s" },
1438 { Imm16, "i16" },
1439 { Imm32, "i32" },
09f131f2
JH		 1440 { Imm32S, "i32s" },
1441 { Imm64, "i64" },
252b5132
RH		 1442 { Imm1, "i1" },
1443 { BaseIndex, "BaseIndex" },
1444 { Disp8, "d8" },
1445 { Disp16, "d16" },
1446 { Disp32, "d32" },
09f131f2
JH		 1447 { Disp32S, "d32s" },
1448 { Disp64, "d64" },
252b5132
RH		 1449 { InOutPortReg, "InOutPortReg" },
1450 { ShiftCount, "ShiftCount" },
1451 { Control, "control reg" },
1452 { Test, "test reg" },
1453 { Debug, "debug reg" },
1454 { FloatReg, "FReg" },
1455 { FloatAcc, "FAcc" },
1456 { SReg2, "SReg2" },
1457 { SReg3, "SReg3" },
1458 { Acc, "Acc" },
1459 { JumpAbsolute, "Jump Absolute" },
1460 { RegMMX, "rMMX" },
3f4438ab 1461 { RegXMM, "rXMM" },
252b5132
RH		 1462 { EsSeg, "es" },
1463 { 0, "" }
1464};
1465
1466static void
1467pt (t)
1468 unsigned int t;
1469{
29b0f896 1470 const struct type_name *ty;
252b5132 1471
09f131f2
JH		 1472 for (ty = type_names; ty->mask; ty++)
1473 if (t & ty->mask)
1474 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1475 fflush (stdout);
1476}
1477
1478#endif /* DEBUG386 */
1479\f
252b5132 1480static bfd_reloc_code_real_type
3956db08 1481reloc (unsigned int size,
64e74474
AM		 1482 int pcrel,
1483 int sign,
1484 bfd_reloc_code_real_type other)
252b5132 1485{
47926f60 1486 if (other != NO_RELOC)
3956db08
JB		 1487 {
1488 reloc_howto_type *reloc;
1489
1490 if (size == 8)
1491 switch (other)
1492 {
64e74474
AM		 1493 case BFD_RELOC_X86_64_GOT32:
1494 return BFD_RELOC_X86_64_GOT64;
1495 break;
1496 case BFD_RELOC_X86_64_PLTOFF64:
1497 return BFD_RELOC_X86_64_PLTOFF64;
1498 break;
1499 case BFD_RELOC_X86_64_GOTPC32:
1500 other = BFD_RELOC_X86_64_GOTPC64;
1501 break;
1502 case BFD_RELOC_X86_64_GOTPCREL:
1503 other = BFD_RELOC_X86_64_GOTPCREL64;
1504 break;
1505 case BFD_RELOC_X86_64_TPOFF32:
1506 other = BFD_RELOC_X86_64_TPOFF64;
1507 break;
1508 case BFD_RELOC_X86_64_DTPOFF32:
1509 other = BFD_RELOC_X86_64_DTPOFF64;
1510 break;
1511 default:
1512 break;
3956db08 1513 }
e05278af
JB		 1514
1515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1516 if (size == 4 && flag_code != CODE_64BIT)
1517 sign = -1;
1518
3956db08
JB		 1519 reloc = bfd_reloc_type_lookup (stdoutput, other);
1520 if (!reloc)
1521 as_bad (_("unknown relocation (%u)"), other);
1522 else if (size != bfd_get_reloc_size (reloc))
1523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1524 bfd_get_reloc_size (reloc),
1525 size);
1526 else if (pcrel && !reloc->pc_relative)
1527 as_bad (_("non-pc-relative relocation for pc-relative field"));
1528 else if ((reloc->complain_on_overflow == complain_overflow_signed
1529 && !sign)
1530 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1531 && sign > 0))
3956db08
JB		 1532 as_bad (_("relocated field and relocation type differ in signedness"));
1533 else
1534 return other;
1535 return NO_RELOC;
1536 }
252b5132
RH		 1537
1538 if (pcrel)
1539 {
3e73aa7c 1540 if (!sign)
3956db08 1541 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1542 switch (size)
1543 {
1544 case 1: return BFD_RELOC_8_PCREL;
1545 case 2: return BFD_RELOC_16_PCREL;
1546 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1547 case 8: return BFD_RELOC_64_PCREL;
252b5132 1548 }
3956db08 1549 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1550 }
1551 else
1552 {
3956db08 1553 if (sign > 0)
e5cb08ac 1554 switch (size)
3e73aa7c
JH		 1555 {
1556 case 4: return BFD_RELOC_X86_64_32S;
1557 }
1558 else
1559 switch (size)
1560 {
1561 case 1: return BFD_RELOC_8;
1562 case 2: return BFD_RELOC_16;
1563 case 4: return BFD_RELOC_32;
1564 case 8: return BFD_RELOC_64;
1565 }
3956db08
JB		 1566 as_bad (_("cannot do %s %u byte relocation"),
1567 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1568 }
1569
bfb32b52 1570 abort ();
252b5132
RH		 1571 return BFD_RELOC_NONE;
1572}
1573
47926f60
KH		 1574/* Here we decide which fixups can be adjusted to make them relative to
1575 the beginning of the section instead of the symbol. Basically we need
1576 to make sure that the dynamic relocations are done correctly, so in
1577 some cases we force the original symbol to be used. */
1578
252b5132 1579int
e3bb37b5 1580tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1581{
6d249963 1582#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1583 if (!IS_ELF)
31312f95
AM		 1584 return 1;
1585
a161fe53
AM		 1586 /* Don't adjust pc-relative references to merge sections in 64-bit
1587 mode. */
1588 if (use_rela_relocations
1589 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1590 && fixP->fx_pcrel)
252b5132 1591 return 0;
31312f95 1592
8d01d9a9
AJ		 1593 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1594 and changed later by validate_fix. */
1595 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1596 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1597 return 0;
1598
ce8a8b2f 1599 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1600 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1601 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1602 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1613 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1626 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1628 return 0;
31312f95 1629#endif
252b5132
RH		 1630 return 1;
1631}
252b5132 1632
b4cac588 1633static int
e3bb37b5 1634intel_float_operand (const char *mnemonic)
252b5132 1635{
9306ca4a
JB		 1636 /* Note that the value returned is meaningful only for opcodes with (memory)
1637 operands, hence the code here is free to improperly handle opcodes that
1638 have no operands (for better performance and smaller code). */
1639
1640 if (mnemonic[0] != 'f')
1641 return 0; /* non-math */
1642
1643 switch (mnemonic[1])
1644 {
1645 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1646 the fs segment override prefix not currently handled because no
1647 call path can make opcodes without operands get here */
1648 case 'i':
1649 return 2 /* integer op */;
1650 case 'l':
1651 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1652 return 3; /* fldcw/fldenv */
1653 break;
1654 case 'n':
1655 if (mnemonic[2] != 'o' /* fnop */)
1656 return 3; /* non-waiting control op */
1657 break;
1658 case 'r':
1659 if (mnemonic[2] == 's')
1660 return 3; /* frstor/frstpm */
1661 break;
1662 case 's':
1663 if (mnemonic[2] == 'a')
1664 return 3; /* fsave */
1665 if (mnemonic[2] == 't')
1666 {
1667 switch (mnemonic[3])
1668 {
1669 case 'c': /* fstcw */
1670 case 'd': /* fstdw */
1671 case 'e': /* fstenv */
1672 case 's': /* fsts[gw] */
1673 return 3;
1674 }
1675 }
1676 break;
1677 case 'x':
1678 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1679 return 0; /* fxsave/fxrstor are not really math ops */
1680 break;
1681 }
252b5132 1682
9306ca4a 1683 return 1;
252b5132
RH		 1684}
1685
1686/* This is the guts of the machine-dependent assembler. LINE points to a
1687 machine dependent instruction. This function is supposed to emit
1688 the frags/bytes it assembles to. */
1689
1690void
1691md_assemble (line)
1692 char *line;
1693{
252b5132 1694 int j;
252b5132
RH		 1695 char mnemonic[MAX_MNEM_SIZE];
1696
47926f60 1697 /* Initialize globals. */
252b5132
RH		 1698 memset (&i, '\0', sizeof (i));
1699 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1700 i.reloc[j] = NO_RELOC;
252b5132
RH		 1701 memset (disp_expressions, '\0', sizeof (disp_expressions));
1702 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1703 save_stack_p = save_stack;
252b5132
RH		 1704
1705 /* First parse an instruction mnemonic & call i386_operand for the operands.
1706 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1707 start of a (possibly prefixed) mnemonic. */
252b5132 1708
29b0f896
AM		 1709 line = parse_insn (line, mnemonic);
1710 if (line == NULL)
1711 return;
252b5132 1712
29b0f896
AM		 1713 line = parse_operands (line, mnemonic);
1714 if (line == NULL)
1715 return;
252b5132 1716
050dfa73
MM		 1717 /* The order of the immediates should be reversed
1718 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1719 if ((i.imm_operands == 2)
1720 && ((strcmp (mnemonic, "extrq") == 0)
1721 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1722 {
4d456e3d 1723 swap_2_operands (0, 1);
050dfa73
MM		 1724 /* "extrq" and insertq" are the only two instructions whose operands
1725 have to be reversed even though they have two immediate operands.
1726 */
1727 if (intel_syntax)
1728 swap_operands ();
1729 }
1730
29b0f896
AM		 1731 /* Now we've parsed the mnemonic into a set of templates, and have the
1732 operands at hand. */
1733
1734 /* All intel opcodes have reversed operands except for "bound" and
1735 "enter". We also don't reverse intersegment "jmp" and "call"
1736 instructions with 2 immediate operands so that the immediate segment
050dfa73 1737 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1738 if (intel_syntax
1739 && i.operands > 1
29b0f896 1740 && (strcmp (mnemonic, "bound") != 0)
30123838 1741 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1742 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1743 swap_operands ();
1744
1745 if (i.imm_operands)
1746 optimize_imm ();
1747
b300c311
L		 1748 /* Don't optimize displacement for movabs since it only takes 64bit
1749 displacement. */
1750 if (i.disp_operands
1751 && (flag_code != CODE_64BIT
1752 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1753 optimize_disp ();
1754
1755 /* Next, we find a template that matches the given insn,
1756 making sure the overlap of the given operands types is consistent
1757 with the template operand types. */
252b5132 1758
29b0f896
AM		 1759 if (!match_template ())
1760 return;
252b5132 1761
cd61ebfe
AM		 1762 if (intel_syntax)
1763 {
1764 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1765 if (SYSV386_COMPAT
1766 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1767 i.tm.base_opcode ^= FloatR;
1768
1769 /* Zap movzx and movsx suffix. The suffix may have been set from
1770 "word ptr" or "byte ptr" on the source operand, but we'll use
1771 the suffix later to choose the destination register. */
1772 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1773 {
1774 if (i.reg_operands < 2
1775 && !i.suffix
1776 && (~i.tm.opcode_modifier
1777 & (No_bSuf
1778 | No_wSuf
1779 | No_lSuf
1780 | No_sSuf
1781 | No_xSuf
1782 | No_qSuf)))
1783 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1784
1785 i.suffix = 0;
1786 }
cd61ebfe 1787 }
24eab124 1788
29b0f896
AM		 1789 if (i.tm.opcode_modifier & FWait)
1790 if (!add_prefix (FWAIT_OPCODE))
1791 return;
252b5132 1792
29b0f896
AM		 1793 /* Check string instruction segment overrides. */
1794 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1795 {
1796 if (!check_string ())
5dd0794d 1797 return;
29b0f896 1798 }
5dd0794d 1799
29b0f896
AM		 1800 if (!process_suffix ())
1801 return;
e413e4e9 1802
29b0f896
AM		 1803 /* Make still unresolved immediate matches conform to size of immediate
1804 given in i.suffix. */
1805 if (!finalize_imm ())
1806 return;
252b5132 1807
29b0f896
AM		 1808 if (i.types[0] & Imm1)
1809 i.imm_operands = 0; /* kludge for shift insns. */
1810 if (i.types[0] & ImplicitRegister)
1811 i.reg_operands--;
1812 if (i.types[1] & ImplicitRegister)
1813 i.reg_operands--;
1814 if (i.types[2] & ImplicitRegister)
1815 i.reg_operands--;
252b5132 1816
29b0f896
AM		 1817 if (i.tm.opcode_modifier & ImmExt)
1818 {
02fc3089
L		 1819 expressionS *exp;
1820
b7d9ef37 1821 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1822 {
b7d9ef37 1823 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1824 operands with an opcode suffix which is coded in the same
1825 place as an 8-bit immediate field would be. Here we check
1826 those operands and remove them afterwards. */
1827 unsigned int x;
1828
a4622f40 1829 for (x = 0; x < i.operands; x++)
ca164297
L		 1830 if (i.op[x].regs->reg_num != x)
1831 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1832 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1833 i.operands = 0;
1834 }
1835
29b0f896
AM		 1836 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1837 opcode suffix which is coded in the same place as an 8-bit
1838 immediate field would be. Here we fake an 8-bit immediate
1839 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1840
29b0f896 1841 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1842
29b0f896
AM		 1843 exp = &im_expressions[i.imm_operands++];
1844 i.op[i.operands].imms = exp;
1845 i.types[i.operands++] = Imm8;
1846 exp->X_op = O_constant;
1847 exp->X_add_number = i.tm.extension_opcode;
1848 i.tm.extension_opcode = None;
1849 }
252b5132 1850
29b0f896
AM		 1851 /* For insns with operands there are more diddles to do to the opcode. */
1852 if (i.operands)
1853 {
1854 if (!process_operands ())
1855 return;
1856 }
1857 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1858 {
1859 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1860 as_warn (_("translating to `%sp'"), i.tm.name);
1861 }
252b5132 1862
29b0f896
AM		 1863 /* Handle conversion of 'int $3' --> special int3 insn. */
1864 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1865 {
1866 i.tm.base_opcode = INT3_OPCODE;
1867 i.imm_operands = 0;
1868 }
252b5132 1869
29b0f896
AM		 1870 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1871 && i.op[0].disps->X_op == O_constant)
1872 {
1873 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1874 the absolute address given by the constant. Since ix86 jumps and
1875 calls are pc relative, we need to generate a reloc. */
1876 i.op[0].disps->X_add_symbol = &abs_symbol;
1877 i.op[0].disps->X_op = O_symbol;
1878 }
252b5132 1879
29b0f896
AM		 1880 if ((i.tm.opcode_modifier & Rex64) != 0)
1881 i.rex |= REX_MODE64;
252b5132 1882
29b0f896
AM		 1883 /* For 8 bit registers we need an empty rex prefix. Also if the
1884 instruction already has a prefix, we need to convert old
1885 registers to new ones. */
773f551c 1886
29b0f896
AM		 1887 if (((i.types[0] & Reg8) != 0
1888 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1889 || ((i.types[1] & Reg8) != 0
1890 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1891 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1892 && i.rex != 0))
1893 {
1894 int x;
726c5dcd 1895
29b0f896
AM		 1896 i.rex |= REX_OPCODE;
1897 for (x = 0; x < 2; x++)
1898 {
1899 /* Look for 8 bit operand that uses old registers. */
1900 if ((i.types[x] & Reg8) != 0
1901 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1902 {
29b0f896
AM		 1903 /* In case it is "hi" register, give up. */
1904 if (i.op[x].regs->reg_num > 3)
0477af35 1905 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1906 i.op[x].regs->reg_name);
773f551c 1907
29b0f896
AM		 1908 /* Otherwise it is equivalent to the extended register.
1909 Since the encoding doesn't change this is merely
1910 cosmetic cleanup for debug output. */
1911
1912 i.op[x].regs = i.op[x].regs + 8;
773f551c 1913 }
29b0f896
AM		 1914 }
1915 }
773f551c 1916
29b0f896
AM		 1917 if (i.rex != 0)
1918 add_prefix (REX_OPCODE | i.rex);
1919
1920 /* We are ready to output the insn. */
1921 output_insn ();
1922}
1923
1924static char *
e3bb37b5 1925parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1926{
1927 char *l = line;
1928 char *token_start = l;
1929 char *mnem_p;
5c6af06e
JB		 1930 int supported;
1931 const template *t;
29b0f896
AM		 1932
1933 /* Non-zero if we found a prefix only acceptable with string insns. */
1934 const char *expecting_string_instruction = NULL;
45288df1 1935
29b0f896
AM		 1936 while (1)
1937 {
1938 mnem_p = mnemonic;
1939 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1940 {
1941 mnem_p++;
1942 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1943 {
29b0f896
AM		 1944 as_bad (_("no such instruction: `%s'"), token_start);
1945 return NULL;
1946 }
1947 l++;
1948 }
1949 if (!is_space_char (*l)
1950 && *l != END_OF_INSN
e44823cf
JB		 1951 && (intel_syntax
1952 || (*l != PREFIX_SEPARATOR
1953 && *l != ',')))
29b0f896
AM		 1954 {
1955 as_bad (_("invalid character %s in mnemonic"),
1956 output_invalid (*l));
1957 return NULL;
1958 }
1959 if (token_start == l)
1960 {
e44823cf 1961 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1962 as_bad (_("expecting prefix; got nothing"));
1963 else
1964 as_bad (_("expecting mnemonic; got nothing"));
1965 return NULL;
1966 }
45288df1 1967
29b0f896
AM		 1968 /* Look up instruction (or prefix) via hash table. */
1969 current_templates = hash_find (op_hash, mnemonic);
47926f60 1970
29b0f896
AM		 1971 if (*l != END_OF_INSN
1972 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1973 && current_templates
1974 && (current_templates->start->opcode_modifier & IsPrefix))
1975 {
2dd88dca
JB		 1976 if (current_templates->start->cpu_flags
1977 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1978 {
1979 as_bad ((flag_code != CODE_64BIT
1980 ? _("`%s' is only supported in 64-bit mode")
1981 : _("`%s' is not supported in 64-bit mode")),
1982 current_templates->start->name);
1983 return NULL;
1984 }
29b0f896
AM		 1985 /* If we are in 16-bit mode, do not allow addr16 or data16.
1986 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1987 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1988 && flag_code != CODE_64BIT
1989 && (((current_templates->start->opcode_modifier & Size32) != 0)
1990 ^ (flag_code == CODE_16BIT)))
1991 {
1992 as_bad (_("redundant %s prefix"),
1993 current_templates->start->name);
1994 return NULL;
45288df1 1995 }
29b0f896
AM		 1996 /* Add prefix, checking for repeated prefixes. */
1997 switch (add_prefix (current_templates->start->base_opcode))
1998 {
1999 case 0:
2000 return NULL;
2001 case 2:
2002 expecting_string_instruction = current_templates->start->name;
2003 break;
2004 }
2005 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2006 token_start = ++l;
2007 }
2008 else
2009 break;
2010 }
45288df1 2011
29b0f896
AM		 2012 if (!current_templates)
2013 {
2014 /* See if we can get a match by trimming off a suffix. */
2015 switch (mnem_p[-1])
2016 {
2017 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2018 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2019 i.suffix = SHORT_MNEM_SUFFIX;
2020 else
29b0f896
AM		 2021 case BYTE_MNEM_SUFFIX:
2022 case QWORD_MNEM_SUFFIX:
2023 i.suffix = mnem_p[-1];
2024 mnem_p[-1] = '\0';
2025 current_templates = hash_find (op_hash, mnemonic);
2026 break;
2027 case SHORT_MNEM_SUFFIX:
2028 case LONG_MNEM_SUFFIX:
2029 if (!intel_syntax)
2030 {
2031 i.suffix = mnem_p[-1];
2032 mnem_p[-1] = '\0';
2033 current_templates = hash_find (op_hash, mnemonic);
2034 }
2035 break;
252b5132 2036
29b0f896
AM		 2037 /* Intel Syntax. */
2038 case 'd':
2039 if (intel_syntax)
2040 {
9306ca4a 2041 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2042 i.suffix = SHORT_MNEM_SUFFIX;
2043 else
2044 i.suffix = LONG_MNEM_SUFFIX;
2045 mnem_p[-1] = '\0';
2046 current_templates = hash_find (op_hash, mnemonic);
2047 }
2048 break;
2049 }
2050 if (!current_templates)
2051 {
2052 as_bad (_("no such instruction: `%s'"), token_start);
2053 return NULL;
2054 }
2055 }
252b5132 2056
29b0f896
AM		 2057 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2058 {
2059 /* Check for a branch hint. We allow ",pt" and ",pn" for
2060 predict taken and predict not taken respectively.
2061 I'm not sure that branch hints actually do anything on loop
2062 and jcxz insns (JumpByte) for current Pentium4 chips. They
2063 may work in the future and it doesn't hurt to accept them
2064 now. */
2065 if (l[0] == ',' && l[1] == 'p')
2066 {
2067 if (l[2] == 't')
2068 {
2069 if (!add_prefix (DS_PREFIX_OPCODE))
2070 return NULL;
2071 l += 3;
2072 }
2073 else if (l[2] == 'n')
2074 {
2075 if (!add_prefix (CS_PREFIX_OPCODE))
2076 return NULL;
2077 l += 3;
2078 }
2079 }
2080 }
2081 /* Any other comma loses. */
2082 if (*l == ',')
2083 {
2084 as_bad (_("invalid character %s in mnemonic"),
2085 output_invalid (*l));
2086 return NULL;
2087 }
252b5132 2088
29b0f896 2089 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2090 supported = 0;
2091 for (t = current_templates->start; t < current_templates->end; ++t)
2092 {
2093 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2094 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2095 supported |= 1;
5c6af06e 2096 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2097 supported |= 2;
5c6af06e
JB		 2098 }
2099 if (!(supported & 2))
2100 {
2101 as_bad (flag_code == CODE_64BIT
2102 ? _("`%s' is not supported in 64-bit mode")
2103 : _("`%s' is only supported in 64-bit mode"),
2104 current_templates->start->name);
2105 return NULL;
2106 }
2107 if (!(supported & 1))
29b0f896 2108 {
5c6af06e
JB		 2109 as_warn (_("`%s' is not supported on `%s%s'"),
2110 current_templates->start->name,
2111 cpu_arch_name,
2112 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2113 }
2114 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2115 {
2116 as_warn (_("use .code16 to ensure correct addressing mode"));
2117 }
252b5132 2118
29b0f896 2119 /* Check for rep/repne without a string instruction. */
f41bbced 2120 if (expecting_string_instruction)
29b0f896 2121 {
f41bbced
JB		 2122 static templates override;
2123
2124 for (t = current_templates->start; t < current_templates->end; ++t)
2125 if (t->opcode_modifier & IsString)
2126 break;
2127 if (t >= current_templates->end)
2128 {
2129 as_bad (_("expecting string instruction after `%s'"),
64e74474 2130 expecting_string_instruction);
f41bbced
JB		 2131 return NULL;
2132 }
2133 for (override.start = t; t < current_templates->end; ++t)
2134 if (!(t->opcode_modifier & IsString))
2135 break;
2136 override.end = t;
2137 current_templates = &override;
29b0f896 2138 }
252b5132 2139
29b0f896
AM		 2140 return l;
2141}
252b5132 2142
29b0f896 2143static char *
e3bb37b5 2144parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2145{
2146 char *token_start;
3138f287 2147
29b0f896
AM		 2148 /* 1 if operand is pending after ','. */
2149 unsigned int expecting_operand = 0;
252b5132 2150
29b0f896
AM		 2151 /* Non-zero if operand parens not balanced. */
2152 unsigned int paren_not_balanced;
2153
2154 while (*l != END_OF_INSN)
2155 {
2156 /* Skip optional white space before operand. */
2157 if (is_space_char (*l))
2158 ++l;
2159 if (!is_operand_char (*l) && *l != END_OF_INSN)
2160 {
2161 as_bad (_("invalid character %s before operand %d"),
2162 output_invalid (*l),
2163 i.operands + 1);
2164 return NULL;
2165 }
2166 token_start = l; /* after white space */
2167 paren_not_balanced = 0;
2168 while (paren_not_balanced || *l != ',')
2169 {
2170 if (*l == END_OF_INSN)
2171 {
2172 if (paren_not_balanced)
2173 {
2174 if (!intel_syntax)
2175 as_bad (_("unbalanced parenthesis in operand %d."),
2176 i.operands + 1);
2177 else
2178 as_bad (_("unbalanced brackets in operand %d."),
2179 i.operands + 1);
2180 return NULL;
2181 }
2182 else
2183 break; /* we are done */
2184 }
2185 else if (!is_operand_char (*l) && !is_space_char (*l))
2186 {
2187 as_bad (_("invalid character %s in operand %d"),
2188 output_invalid (*l),
2189 i.operands + 1);
2190 return NULL;
2191 }
2192 if (!intel_syntax)
2193 {
2194 if (*l == '(')
2195 ++paren_not_balanced;
2196 if (*l == ')')
2197 --paren_not_balanced;
2198 }
2199 else
2200 {
2201 if (*l == '[')
2202 ++paren_not_balanced;
2203 if (*l == ']')
2204 --paren_not_balanced;
2205 }
2206 l++;
2207 }
2208 if (l != token_start)
2209 { /* Yes, we've read in another operand. */
2210 unsigned int operand_ok;
2211 this_operand = i.operands++;
2212 if (i.operands > MAX_OPERANDS)
2213 {
2214 as_bad (_("spurious operands; (%d operands/instruction max)"),
2215 MAX_OPERANDS);
2216 return NULL;
2217 }
2218 /* Now parse operand adding info to 'i' as we go along. */
2219 END_STRING_AND_SAVE (l);
2220
2221 if (intel_syntax)
2222 operand_ok =
2223 i386_intel_operand (token_start,
2224 intel_float_operand (mnemonic));
2225 else
2226 operand_ok = i386_operand (token_start);
2227
2228 RESTORE_END_STRING (l);
2229 if (!operand_ok)
2230 return NULL;
2231 }
2232 else
2233 {
2234 if (expecting_operand)
2235 {
2236 expecting_operand_after_comma:
2237 as_bad (_("expecting operand after ','; got nothing"));
2238 return NULL;
2239 }
2240 if (*l == ',')
2241 {
2242 as_bad (_("expecting operand before ','; got nothing"));
2243 return NULL;
2244 }
2245 }
7f3f1ea2 2246
29b0f896
AM		 2247 /* Now *l must be either ',' or END_OF_INSN. */
2248 if (*l == ',')
2249 {
2250 if (*++l == END_OF_INSN)
2251 {
2252 /* Just skip it, if it's \n complain. */
2253 goto expecting_operand_after_comma;
2254 }
2255 expecting_operand = 1;
2256 }
2257 }
2258 return l;
2259}
7f3f1ea2 2260
050dfa73 2261static void
4d456e3d 2262swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2263{
2264 union i386_op temp_op;
2265 unsigned int temp_type;
2266 enum bfd_reloc_code_real temp_reloc;
050dfa73
MM		 2267
2268 temp_type = i.types[xchg2];
2269 i.types[xchg2] = i.types[xchg1];
2270 i.types[xchg1] = temp_type;
2271 temp_op = i.op[xchg2];
2272 i.op[xchg2] = i.op[xchg1];
2273 i.op[xchg1] = temp_op;
2274 temp_reloc = i.reloc[xchg2];
2275 i.reloc[xchg2] = i.reloc[xchg1];
2276 i.reloc[xchg1] = temp_reloc;
2277}
2278
29b0f896 2279static void
e3bb37b5 2280swap_operands (void)
29b0f896 2281{
b7c61d9a 2282 switch (i.operands)
050dfa73 2283 {
b7c61d9a 2284 case 4:
4d456e3d 2285 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2286 case 3:
2287 case 2:
4d456e3d 2288 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2289 break;
2290 default:
2291 abort ();
29b0f896 2292 }
29b0f896
AM		 2293
2294 if (i.mem_operands == 2)
2295 {
2296 const seg_entry *temp_seg;
2297 temp_seg = i.seg[0];
2298 i.seg[0] = i.seg[1];
2299 i.seg[1] = temp_seg;
2300 }
2301}
252b5132 2302
29b0f896
AM		 2303/* Try to ensure constant immediates are represented in the smallest
2304 opcode possible. */
2305static void
e3bb37b5 2306optimize_imm (void)
29b0f896
AM		 2307{
2308 char guess_suffix = 0;
2309 int op;
252b5132 2310
29b0f896
AM		 2311 if (i.suffix)
2312 guess_suffix = i.suffix;
2313 else if (i.reg_operands)
2314 {
2315 /* Figure out a suffix from the last register operand specified.
2316 We can't do this properly yet, ie. excluding InOutPortReg,
2317 but the following works for instructions with immediates.
2318 In any case, we can't set i.suffix yet. */
2319 for (op = i.operands; --op >= 0;)
2320 if (i.types[op] & Reg)
252b5132 2321 {
29b0f896
AM		 2322 if (i.types[op] & Reg8)
2323 guess_suffix = BYTE_MNEM_SUFFIX;
2324 else if (i.types[op] & Reg16)
2325 guess_suffix = WORD_MNEM_SUFFIX;
2326 else if (i.types[op] & Reg32)
2327 guess_suffix = LONG_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg64)
2329 guess_suffix = QWORD_MNEM_SUFFIX;
2330 break;
252b5132 2331 }
29b0f896
AM		 2332 }
2333 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2334 guess_suffix = WORD_MNEM_SUFFIX;
2335
2336 for (op = i.operands; --op >= 0;)
2337 if (i.types[op] & Imm)
2338 {
2339 switch (i.op[op].imms->X_op)
252b5132 2340 {
29b0f896
AM		 2341 case O_constant:
2342 /* If a suffix is given, this operand may be shortened. */
2343 switch (guess_suffix)
252b5132 2344 {
29b0f896
AM		 2345 case LONG_MNEM_SUFFIX:
2346 i.types[op] |= Imm32 | Imm64;
2347 break;
2348 case WORD_MNEM_SUFFIX:
2349 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2350 break;
2351 case BYTE_MNEM_SUFFIX:
2352 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2353 break;
252b5132 2354 }
252b5132 2355
29b0f896
AM		 2356 /* If this operand is at most 16 bits, convert it
2357 to a signed 16 bit number before trying to see
2358 whether it will fit in an even smaller size.
2359 This allows a 16-bit operand such as $0xffe0 to
2360 be recognised as within Imm8S range. */
2361 if ((i.types[op] & Imm16)
2362 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2363 {
29b0f896
AM		 2364 i.op[op].imms->X_add_number =
2365 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2366 }
2367 if ((i.types[op] & Imm32)
2368 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2369 == 0))
2370 {
2371 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2372 ^ ((offsetT) 1 << 31))
2373 - ((offsetT) 1 << 31));
2374 }
2375 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2376
29b0f896
AM		 2377 /* We must avoid matching of Imm32 templates when 64bit
2378 only immediate is available. */
2379 if (guess_suffix == QWORD_MNEM_SUFFIX)
2380 i.types[op] &= ~Imm32;
2381 break;
252b5132 2382
29b0f896
AM		 2383 case O_absent:
2384 case O_register:
2385 abort ();
2386
2387 /* Symbols and expressions. */
2388 default:
9cd96992
JB		 2389 /* Convert symbolic operand to proper sizes for matching, but don't
2390 prevent matching a set of insns that only supports sizes other
2391 than those matching the insn suffix. */
2392 {
2393 unsigned int mask, allowed = 0;
2394 const template *t;
2395
2396 for (t = current_templates->start; t < current_templates->end; ++t)
2397 allowed |= t->operand_types[op];
2398 switch (guess_suffix)
2399 {
2400 case QWORD_MNEM_SUFFIX:
2401 mask = Imm64 | Imm32S;
2402 break;
2403 case LONG_MNEM_SUFFIX:
2404 mask = Imm32;
2405 break;
2406 case WORD_MNEM_SUFFIX:
2407 mask = Imm16;
2408 break;
2409 case BYTE_MNEM_SUFFIX:
2410 mask = Imm8;
2411 break;
2412 default:
2413 mask = 0;
2414 break;
2415 }
64e74474
AM		 2416 if (mask & allowed)
2417 i.types[op] &= mask;
9cd96992 2418 }
29b0f896 2419 break;
252b5132 2420 }
29b0f896
AM		 2421 }
2422}
47926f60 2423
29b0f896
AM		 2424/* Try to use the smallest displacement type too. */
2425static void
e3bb37b5 2426optimize_disp (void)
29b0f896
AM		 2427{
2428 int op;
3e73aa7c 2429
29b0f896 2430 for (op = i.operands; --op >= 0;)
b300c311 2431 if (i.types[op] & Disp)
252b5132 2432 {
b300c311 2433 if (i.op[op].disps->X_op == O_constant)
252b5132 2434 {
b300c311 2435 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2436
b300c311
L		 2437 if ((i.types[op] & Disp16)
2438 && (disp & ~(offsetT) 0xffff) == 0)
2439 {
2440 /* If this operand is at most 16 bits, convert
2441 to a signed 16 bit number and don't use 64bit
2442 displacement. */
2443 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2444 i.types[op] &= ~Disp64;
2445 }
2446 if ((i.types[op] & Disp32)
2447 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2448 {
2449 /* If this operand is at most 32 bits, convert
2450 to a signed 32 bit number and don't use 64bit
2451 displacement. */
2452 disp &= (((offsetT) 2 << 31) - 1);
2453 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2454 i.types[op] &= ~Disp64;
2455 }
2456 if (!disp && (i.types[op] & BaseIndex))
2457 {
2458 i.types[op] &= ~Disp;
2459 i.op[op].disps = 0;
2460 i.disp_operands--;
2461 }
2462 else if (flag_code == CODE_64BIT)
2463 {
2464 if (fits_in_signed_long (disp))
28a9d8f5
L		 2465 {
2466 i.types[op] &= ~Disp64;
2467 i.types[op] |= Disp32S;
2468 }
b300c311
L		 2469 if (fits_in_unsigned_long (disp))
2470 i.types[op] |= Disp32;
2471 }
2472 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2473 && fits_in_signed_byte (disp))
2474 i.types[op] |= Disp8;
252b5132 2475 }
67a4f2b7
AO		 2476 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2477 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2478 {
2479 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2480 i.op[op].disps, 0, i.reloc[op]);
2481 i.types[op] &= ~Disp;
2482 }
2483 else
b300c311
L		 2484 /* We only support 64bit displacement on constants. */
2485 i.types[op] &= ~Disp64;
252b5132 2486 }
29b0f896
AM		 2487}
2488
2489static int
e3bb37b5 2490match_template (void)
29b0f896
AM		 2491{
2492 /* Points to template once we've found it. */
2493 const template *t;
f48ff2ae 2494 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2495 unsigned int found_reverse_match;
2496 int suffix_check;
f48ff2ae 2497 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2498 int addr_prefix_disp;
a5c311ca 2499 unsigned int j;
29b0f896 2500
f48ff2ae
L		 2501#if MAX_OPERANDS != 4
2502# error "MAX_OPERANDS must be 4."
2503#endif
2504
29b0f896
AM		 2505#define MATCH(overlap, given, template) \
2506 ((overlap & ~JumpAbsolute) \
2507 && (((given) & (BaseIndex | JumpAbsolute)) \
2508 == ((overlap) & (BaseIndex | JumpAbsolute))))
2509
2510 /* If given types r0 and r1 are registers they must be of the same type
2511 unless the expected operand type register overlap is null.
2512 Note that Acc in a template matches every size of reg. */
2513#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2514 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2515 || ((g0) & Reg) == ((g1) & Reg) \
2516 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2517
2518 overlap0 = 0;
2519 overlap1 = 0;
2520 overlap2 = 0;
f48ff2ae 2521 overlap3 = 0;
29b0f896 2522 found_reverse_match = 0;
a5c311ca
L		 2523 for (j = 0; j < MAX_OPERANDS; j++)
2524 operand_types [j] = 0;
539e75ad 2525 addr_prefix_disp = -1;
29b0f896
AM		 2526 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2527 ? No_bSuf
2528 : (i.suffix == WORD_MNEM_SUFFIX
2529 ? No_wSuf
2530 : (i.suffix == SHORT_MNEM_SUFFIX
2531 ? No_sSuf
2532 : (i.suffix == LONG_MNEM_SUFFIX
2533 ? No_lSuf
2534 : (i.suffix == QWORD_MNEM_SUFFIX
2535 ? No_qSuf
2536 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2537 ? No_xSuf : 0))))));
2538
45aa61fe 2539 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2540 {
539e75ad
L		 2541 addr_prefix_disp = -1;
2542
29b0f896
AM		 2543 /* Must have right number of operands. */
2544 if (i.operands != t->operands)
2545 continue;
2546
2547 /* Check the suffix, except for some instructions in intel mode. */
2548 if ((t->opcode_modifier & suffix_check)
2549 && !(intel_syntax
9306ca4a 2550 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2551 continue;
2552
a5c311ca
L		 2553 for (j = 0; j < MAX_OPERANDS; j++)
2554 operand_types [j] = t->operand_types [j];
539e75ad 2555
45aa61fe
AM		 2556 /* In general, don't allow 64-bit operands in 32-bit mode. */
2557 if (i.suffix == QWORD_MNEM_SUFFIX
2558 && flag_code != CODE_64BIT
2559 && (intel_syntax
2560 ? (!(t->opcode_modifier & IgnoreSize)
2561 && !intel_float_operand (t->name))
2562 : intel_float_operand (t->name) != 2)
539e75ad
L		 2563 && (!(operand_types[0] & (RegMMX | RegXMM))
2564 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2565 && (t->base_opcode != 0x0fc7
2566 || t->extension_opcode != 1 /* cmpxchg8b */))
2567 continue;
2568
29b0f896
AM		 2569 /* Do not verify operands when there are none. */
2570 else if (!t->operands)
2571 {
2572 if (t->cpu_flags & ~cpu_arch_flags)
2573 continue;
2574 /* We've found a match; break out of loop. */
2575 break;
2576 }
252b5132 2577
539e75ad
L		 2578 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2579 into Disp32/Disp16/Disp32 operand. */
2580 if (i.prefix[ADDR_PREFIX] != 0)
2581 {
a5c311ca 2582 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2583
2584 switch (flag_code)
2585 {
2586 case CODE_16BIT:
2587 DispOn = Disp32;
2588 DispOff = Disp16;
2589 break;
2590 case CODE_32BIT:
2591 DispOn = Disp16;
2592 DispOff = Disp32;
2593 break;
2594 case CODE_64BIT:
2595 DispOn = Disp32;
2596 DispOff = Disp64;
2597 break;
2598 }
2599
f48ff2ae 2600 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2601 {
2602 /* There should be only one Disp operand. */
2603 if ((operand_types[j] & DispOff))
2604 {
2605 addr_prefix_disp = j;
2606 operand_types[j] |= DispOn;
2607 operand_types[j] &= ~DispOff;
2608 break;
2609 }
2610 }
2611 }
2612
2613 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2614 switch (t->operands)
2615 {
2616 case 1:
539e75ad 2617 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2618 continue;
2619 break;
2620 case 2:
2621 case 3:
f48ff2ae 2622 case 4:
539e75ad
L		 2623 overlap1 = i.types[1] & operand_types[1];
2624 if (!MATCH (overlap0, i.types[0], operand_types[0])
2625 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2626 /* monitor in SSE3 is a very special case. The first
708587a4 2627 register and the second register may have different
cb712a9e
L		 2628 sizes. */
2629 || !((t->base_opcode == 0x0f01
2630 && t->extension_opcode == 0xc8)
2631 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2632 operand_types[0],
cb712a9e 2633 overlap1, i.types[1],
539e75ad 2634 operand_types[1])))
29b0f896
AM		 2635 {
2636 /* Check if other direction is valid ... */
2637 if ((t->opcode_modifier & (D | FloatD)) == 0)
2638 continue;
2639
2640 /* Try reversing direction of operands. */
539e75ad
L		 2641 overlap0 = i.types[0] & operand_types[1];
2642 overlap1 = i.types[1] & operand_types[0];
2643 if (!MATCH (overlap0, i.types[0], operand_types[1])
2644 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2645 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2646 operand_types[1],
29b0f896 2647 overlap1, i.types[1],
539e75ad 2648 operand_types[0]))
29b0f896
AM		 2649 {
2650 /* Does not match either direction. */
2651 continue;
2652 }
2653 /* found_reverse_match holds which of D or FloatDR
2654 we've found. */
2655 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2656 }
f48ff2ae 2657 else
29b0f896 2658 {
f48ff2ae 2659 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2660 switch (t->operands)
2661 {
2662 case 4:
2663 overlap3 = i.types[3] & operand_types[3];
2664 case 3:
2665 overlap2 = i.types[2] & operand_types[2];
2666 break;
2667 }
29b0f896 2668
f48ff2ae
L		 2669 switch (t->operands)
2670 {
2671 case 4:
2672 if (!MATCH (overlap3, i.types[3], operand_types[3])
2673 || !CONSISTENT_REGISTER_MATCH (overlap2,
2674 i.types[2],
2675 operand_types[2],
2676 overlap3,
2677 i.types[3],
2678 operand_types[3]))
2679 continue;
2680 case 3:
2681 /* Here we make use of the fact that there are no
2682 reverse match 3 operand instructions, and all 3
2683 operand instructions only need to be checked for
2684 register consistency between operands 2 and 3. */
2685 if (!MATCH (overlap2, i.types[2], operand_types[2])
2686 || !CONSISTENT_REGISTER_MATCH (overlap1,
2687 i.types[1],
2688 operand_types[1],
2689 overlap2,
2690 i.types[2],
2691 operand_types[2]))
2692 continue;
2693 break;
2694 }
29b0f896 2695 }
f48ff2ae 2696 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2697 slip through to break. */
2698 }
2699 if (t->cpu_flags & ~cpu_arch_flags)
2700 {
2701 found_reverse_match = 0;
2702 continue;
2703 }
2704 /* We've found a match; break out of loop. */
2705 break;
2706 }
2707
2708 if (t == current_templates->end)
2709 {
2710 /* We found no match. */
2711 as_bad (_("suffix or operands invalid for `%s'"),
2712 current_templates->start->name);
2713 return 0;
2714 }
252b5132 2715
29b0f896
AM		 2716 if (!quiet_warnings)
2717 {
2718 if (!intel_syntax
2719 && ((i.types[0] & JumpAbsolute)
539e75ad 2720 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2721 {
2722 as_warn (_("indirect %s without `*'"), t->name);
2723 }
2724
2725 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2726 == (IsPrefix | IgnoreSize))
2727 {
2728 /* Warn them that a data or address size prefix doesn't
2729 affect assembly of the next line of code. */
2730 as_warn (_("stand-alone `%s' prefix"), t->name);
2731 }
2732 }
2733
2734 /* Copy the template we found. */
2735 i.tm = *t;
539e75ad
L		 2736
2737 if (addr_prefix_disp != -1)
2738 i.tm.operand_types[addr_prefix_disp]
2739 = operand_types[addr_prefix_disp];
2740
29b0f896
AM		 2741 if (found_reverse_match)
2742 {
2743 /* If we found a reverse match we must alter the opcode
2744 direction bit. found_reverse_match holds bits to change
2745 (different for int & float insns). */
2746
2747 i.tm.base_opcode ^= found_reverse_match;
2748
539e75ad
L		 2749 i.tm.operand_types[0] = operand_types[1];
2750 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2751 }
2752
2753 return 1;
2754}
2755
2756static int
e3bb37b5 2757check_string (void)
29b0f896
AM		 2758{
2759 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2760 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2761 {
2762 if (i.seg[0] != NULL && i.seg[0] != &es)
2763 {
2764 as_bad (_("`%s' operand %d must use `%%es' segment"),
2765 i.tm.name,
2766 mem_op + 1);
2767 return 0;
2768 }
2769 /* There's only ever one segment override allowed per instruction.
2770 This instruction possibly has a legal segment override on the
2771 second operand, so copy the segment to where non-string
2772 instructions store it, allowing common code. */
2773 i.seg[0] = i.seg[1];
2774 }
2775 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2776 {
2777 if (i.seg[1] != NULL && i.seg[1] != &es)
2778 {
2779 as_bad (_("`%s' operand %d must use `%%es' segment"),
2780 i.tm.name,
2781 mem_op + 2);
2782 return 0;
2783 }
2784 }
2785 return 1;
2786}
2787
2788static int
543613e9 2789process_suffix (void)
29b0f896
AM		 2790{
2791 /* If matched instruction specifies an explicit instruction mnemonic
2792 suffix, use it. */
2793 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2794 {
2795 if (i.tm.opcode_modifier & Size16)
2796 i.suffix = WORD_MNEM_SUFFIX;
2797 else if (i.tm.opcode_modifier & Size64)
2798 i.suffix = QWORD_MNEM_SUFFIX;
2799 else
2800 i.suffix = LONG_MNEM_SUFFIX;
2801 }
2802 else if (i.reg_operands)
2803 {
2804 /* If there's no instruction mnemonic suffix we try to invent one
2805 based on register operands. */
2806 if (!i.suffix)
2807 {
2808 /* We take i.suffix from the last register operand specified,
2809 Destination register type is more significant than source
2810 register type. */
2811 int op;
543613e9 2812
29b0f896
AM		 2813 for (op = i.operands; --op >= 0;)
2814 if ((i.types[op] & Reg)
2815 && !(i.tm.operand_types[op] & InOutPortReg))
2816 {
2817 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2818 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2819 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2820 LONG_MNEM_SUFFIX);
2821 break;
2822 }
2823 }
2824 else if (i.suffix == BYTE_MNEM_SUFFIX)
2825 {
2826 if (!check_byte_reg ())
2827 return 0;
2828 }
2829 else if (i.suffix == LONG_MNEM_SUFFIX)
2830 {
2831 if (!check_long_reg ())
2832 return 0;
2833 }
2834 else if (i.suffix == QWORD_MNEM_SUFFIX)
2835 {
2836 if (!check_qword_reg ())
2837 return 0;
2838 }
2839 else if (i.suffix == WORD_MNEM_SUFFIX)
2840 {
2841 if (!check_word_reg ())
2842 return 0;
2843 }
2844 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2845 /* Do nothing if the instruction is going to ignore the prefix. */
2846 ;
2847 else
2848 abort ();
2849 }
9306ca4a
JB		 2850 else if ((i.tm.opcode_modifier & DefaultSize)
2851 && !i.suffix
2852 /* exclude fldenv/frstor/fsave/fstenv */
2853 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2854 {
2855 i.suffix = stackop_size;
2856 }
9306ca4a
JB		 2857 else if (intel_syntax
2858 && !i.suffix
2859 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2860 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2861 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2862 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2863 {
2864 switch (flag_code)
2865 {
2866 case CODE_64BIT:
2867 if (!(i.tm.opcode_modifier & No_qSuf))
2868 {
2869 i.suffix = QWORD_MNEM_SUFFIX;
2870 break;
2871 }
2872 case CODE_32BIT:
2873 if (!(i.tm.opcode_modifier & No_lSuf))
2874 i.suffix = LONG_MNEM_SUFFIX;
2875 break;
2876 case CODE_16BIT:
2877 if (!(i.tm.opcode_modifier & No_wSuf))
2878 i.suffix = WORD_MNEM_SUFFIX;
2879 break;
2880 }
2881 }
252b5132 2882
9306ca4a 2883 if (!i.suffix)
29b0f896 2884 {
9306ca4a
JB		 2885 if (!intel_syntax)
2886 {
2887 if (i.tm.opcode_modifier & W)
2888 {
2889 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2890 return 0;
2891 }
2892 }
2893 else
2894 {
64e74474
AM		 2895 unsigned int suffixes = (~i.tm.opcode_modifier
2896 & (No_bSuf
2897 | No_wSuf
2898 | No_lSuf
2899 | No_sSuf
2900 | No_xSuf
2901 | No_qSuf));
9306ca4a
JB		 2902
2903 if ((i.tm.opcode_modifier & W)
2904 || ((suffixes & (suffixes - 1))
2905 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2906 {
2907 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2908 return 0;
2909 }
2910 }
29b0f896 2911 }
252b5132 2912
9306ca4a
JB		 2913 /* Change the opcode based on the operand size given by i.suffix;
2914 We don't need to change things for byte insns. */
2915
29b0f896
AM		 2916 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2917 {
2918 /* It's not a byte, select word/dword operation. */
2919 if (i.tm.opcode_modifier & W)
2920 {
2921 if (i.tm.opcode_modifier & ShortForm)
2922 i.tm.base_opcode |= 8;
2923 else
2924 i.tm.base_opcode |= 1;
2925 }
0f3f3d8b 2926
29b0f896
AM		 2927 /* Now select between word & dword operations via the operand
2928 size prefix, except for instructions that will ignore this
2929 prefix anyway. */
cb712a9e
L		 2930 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2931 {
2932 /* monitor in SSE3 is a very special case. The default size
2933 of AX is the size of mode. The address size override
2934 prefix will change the size of AX. */
2935 if (i.op->regs[0].reg_type &
2936 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2937 if (!add_prefix (ADDR_PREFIX_OPCODE))
2938 return 0;
2939 }
2940 else if (i.suffix != QWORD_MNEM_SUFFIX
2941 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2942 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2943 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2944 || (flag_code == CODE_64BIT
2945 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2946 {
2947 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2948
29b0f896
AM		 2949 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2950 prefix = ADDR_PREFIX_OPCODE;
252b5132 2951
29b0f896
AM		 2952 if (!add_prefix (prefix))
2953 return 0;
24eab124 2954 }
252b5132 2955
29b0f896
AM		 2956 /* Set mode64 for an operand. */
2957 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2958 && flag_code == CODE_64BIT
29b0f896 2959 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2960 {
2961 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2962 need rex64. */
2963 if (i.operands != 2
2964 || i.types [0] != (Acc | Reg64)
2965 || i.types [1] != (Acc | Reg64)
2966 || strcmp (i.tm.name, "xchg") != 0)
2967 i.rex |= REX_MODE64;
2968 }
3e73aa7c 2969
29b0f896
AM		 2970 /* Size floating point instruction. */
2971 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2972 if (i.tm.opcode_modifier & FloatMF)
2973 i.tm.base_opcode ^= 4;
29b0f896 2974 }
7ecd2f8b 2975
29b0f896
AM		 2976 return 1;
2977}
3e73aa7c 2978
29b0f896 2979static int
543613e9 2980check_byte_reg (void)
29b0f896
AM		 2981{
2982 int op;
543613e9 2983
29b0f896
AM		 2984 for (op = i.operands; --op >= 0;)
2985 {
2986 /* If this is an eight bit register, it's OK. If it's the 16 or
2987 32 bit version of an eight bit register, we will just use the
2988 low portion, and that's OK too. */
2989 if (i.types[op] & Reg8)
2990 continue;
2991
2992 /* movzx and movsx should not generate this warning. */
2993 if (intel_syntax
2994 && (i.tm.base_opcode == 0xfb7
2995 || i.tm.base_opcode == 0xfb6
2996 || i.tm.base_opcode == 0x63
2997 || i.tm.base_opcode == 0xfbe
2998 || i.tm.base_opcode == 0xfbf))
2999 continue;
3000
65ec77d2 3001 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3002 {
3003 /* Prohibit these changes in the 64bit mode, since the
3004 lowering is more complicated. */
3005 if (flag_code == CODE_64BIT
3006 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3007 {
2ca3ace5
L		 3008 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3009 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3010 i.suffix);
3011 return 0;
3012 }
3013#if REGISTER_WARNINGS
3014 if (!quiet_warnings
3015 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3016 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3017 (i.op[op].regs + (i.types[op] & Reg16
3018 ? REGNAM_AL - REGNAM_AX
3019 : REGNAM_AL - REGNAM_EAX))->reg_name,
3020 i.op[op].regs->reg_name,
3021 i.suffix);
3022#endif
3023 continue;
3024 }
3025 /* Any other register is bad. */
3026 if (i.types[op] & (Reg | RegMMX | RegXMM
3027 | SReg2 | SReg3
3028 | Control | Debug | Test
3029 | FloatReg | FloatAcc))
3030 {
3031 as_bad (_("`%%%s' not allowed with `%s%c'"),
3032 i.op[op].regs->reg_name,
3033 i.tm.name,
3034 i.suffix);
3035 return 0;
3036 }
3037 }
3038 return 1;
3039}
3040
3041static int
e3bb37b5 3042check_long_reg (void)
29b0f896
AM		 3043{
3044 int op;
3045
3046 for (op = i.operands; --op >= 0;)
3047 /* Reject eight bit registers, except where the template requires
3048 them. (eg. movzb) */
3049 if ((i.types[op] & Reg8) != 0
3050 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3051 {
3052 as_bad (_("`%%%s' not allowed with `%s%c'"),
3053 i.op[op].regs->reg_name,
3054 i.tm.name,
3055 i.suffix);
3056 return 0;
3057 }
3058 /* Warn if the e prefix on a general reg is missing. */
3059 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3060 && (i.types[op] & Reg16) != 0
3061 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3062 {
3063 /* Prohibit these changes in the 64bit mode, since the
3064 lowering is more complicated. */
3065 if (flag_code == CODE_64BIT)
252b5132 3066 {
2ca3ace5
L		 3067 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3068 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3069 i.suffix);
3070 return 0;
252b5132 3071 }
29b0f896
AM		 3072#if REGISTER_WARNINGS
3073 else
3074 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3075 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3076 i.op[op].regs->reg_name,
3077 i.suffix);
3078#endif
252b5132 3079 }
29b0f896
AM		 3080 /* Warn if the r prefix on a general reg is missing. */
3081 else if ((i.types[op] & Reg64) != 0
3082 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3083 {
2ca3ace5
L		 3084 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3085 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3086 i.suffix);
3087 return 0;
3088 }
3089 return 1;
3090}
252b5132 3091
29b0f896 3092static int
e3bb37b5 3093check_qword_reg (void)
29b0f896
AM		 3094{
3095 int op;
252b5132 3096
29b0f896
AM		 3097 for (op = i.operands; --op >= 0; )
3098 /* Reject eight bit registers, except where the template requires
3099 them. (eg. movzb) */
3100 if ((i.types[op] & Reg8) != 0
3101 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3102 {
3103 as_bad (_("`%%%s' not allowed with `%s%c'"),
3104 i.op[op].regs->reg_name,
3105 i.tm.name,
3106 i.suffix);
3107 return 0;
3108 }
3109 /* Warn if the e prefix on a general reg is missing. */
3110 else if (((i.types[op] & Reg16) != 0
3111 || (i.types[op] & Reg32) != 0)
3112 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3113 {
3114 /* Prohibit these changes in the 64bit mode, since the
3115 lowering is more complicated. */
2ca3ace5
L		 3116 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3117 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3118 i.suffix);
3119 return 0;
252b5132 3120 }
29b0f896
AM		 3121 return 1;
3122}
252b5132 3123
29b0f896 3124static int
e3bb37b5 3125check_word_reg (void)
29b0f896
AM		 3126{
3127 int op;
3128 for (op = i.operands; --op >= 0;)
3129 /* Reject eight bit registers, except where the template requires
3130 them. (eg. movzb) */
3131 if ((i.types[op] & Reg8) != 0
3132 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3133 {
3134 as_bad (_("`%%%s' not allowed with `%s%c'"),
3135 i.op[op].regs->reg_name,
3136 i.tm.name,
3137 i.suffix);
3138 return 0;
3139 }
3140 /* Warn if the e prefix on a general reg is present. */
3141 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3142 && (i.types[op] & Reg32) != 0
3143 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3144 {
29b0f896
AM		 3145 /* Prohibit these changes in the 64bit mode, since the
3146 lowering is more complicated. */
3147 if (flag_code == CODE_64BIT)
252b5132 3148 {
2ca3ace5
L		 3149 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3150 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3151 i.suffix);
3152 return 0;
252b5132 3153 }
29b0f896
AM		 3154 else
3155#if REGISTER_WARNINGS
3156 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3157 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3158 i.op[op].regs->reg_name,
3159 i.suffix);
3160#endif
3161 }
3162 return 1;
3163}
252b5132 3164
29b0f896 3165static int
e3bb37b5 3166finalize_imm (void)
29b0f896
AM		 3167{
3168 unsigned int overlap0, overlap1, overlap2;
3169
3170 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3171 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3172 && overlap0 != Imm8 && overlap0 != Imm8S
3173 && overlap0 != Imm16 && overlap0 != Imm32S
3174 && overlap0 != Imm32 && overlap0 != Imm64)
3175 {
3176 if (i.suffix)
3177 {
3178 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3179 ? Imm8 | Imm8S
3180 : (i.suffix == WORD_MNEM_SUFFIX
3181 ? Imm16
3182 : (i.suffix == QWORD_MNEM_SUFFIX
3183 ? Imm64 | Imm32S
3184 : Imm32)));
3185 }
3186 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3187 || overlap0 == (Imm16 | Imm32)
3188 || overlap0 == (Imm16 | Imm32S))
3189 {
3190 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3191 ? Imm16 : Imm32S);
3192 }
3193 if (overlap0 != Imm8 && overlap0 != Imm8S
3194 && overlap0 != Imm16 && overlap0 != Imm32S
3195 && overlap0 != Imm32 && overlap0 != Imm64)
3196 {
3197 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3198 return 0;
3199 }
3200 }
3201 i.types[0] = overlap0;
3202
3203 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3204 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3205 && overlap1 != Imm8 && overlap1 != Imm8S
3206 && overlap1 != Imm16 && overlap1 != Imm32S
3207 && overlap1 != Imm32 && overlap1 != Imm64)
3208 {
3209 if (i.suffix)
3210 {
3211 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3212 ? Imm8 | Imm8S
3213 : (i.suffix == WORD_MNEM_SUFFIX
3214 ? Imm16
3215 : (i.suffix == QWORD_MNEM_SUFFIX
3216 ? Imm64 | Imm32S
3217 : Imm32)));
3218 }
3219 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3220 || overlap1 == (Imm16 | Imm32)
3221 || overlap1 == (Imm16 | Imm32S))
3222 {
3223 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3224 ? Imm16 : Imm32S);
3225 }
3226 if (overlap1 != Imm8 && overlap1 != Imm8S
3227 && overlap1 != Imm16 && overlap1 != Imm32S
3228 && overlap1 != Imm32 && overlap1 != Imm64)
3229 {
3230 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3231 return 0;
3232 }
3233 }
3234 i.types[1] = overlap1;
3235
3236 overlap2 = i.types[2] & i.tm.operand_types[2];
3237 assert ((overlap2 & Imm) == 0);
3238 i.types[2] = overlap2;
3239
3240 return 1;
3241}
3242
3243static int
e3bb37b5 3244process_operands (void)
29b0f896
AM		 3245{
3246 /* Default segment register this instruction will use for memory
3247 accesses. 0 means unknown. This is only for optimizing out
3248 unnecessary segment overrides. */
3249 const seg_entry *default_seg = 0;
3250
3251 /* The imul $imm, %reg instruction is converted into
3252 imul $imm, %reg, %reg, and the clr %reg instruction
3253 is converted into xor %reg, %reg. */
3254 if (i.tm.opcode_modifier & regKludge)
3255 {
3256 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3257 /* Pretend we saw the extra register operand. */
cab737b9
L		 3258 assert (i.reg_operands == 1
3259 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM		 3260 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3261 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L		 3262 i.operands++;
3263 i.reg_operands++;
29b0f896
AM		 3264 }
3265
3266 if (i.tm.opcode_modifier & ShortForm)
3267 {
3268 /* The register or float register operand is in operand 0 or 1. */
3269 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3270 /* Register goes in low 3 bits of opcode. */
3271 i.tm.base_opcode |= i.op[op].regs->reg_num;
3272 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3273 i.rex |= REX_EXTZ;
3274 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3275 {
3276 /* Warn about some common errors, but press on regardless.
3277 The first case can be generated by gcc (<= 2.8.1). */
3278 if (i.operands == 2)
3279 {
3280 /* Reversed arguments on faddp, fsubp, etc. */
3281 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3282 i.op[1].regs->reg_name,
3283 i.op[0].regs->reg_name);
3284 }
3285 else
3286 {
3287 /* Extraneous `l' suffix on fp insn. */
3288 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3289 i.op[0].regs->reg_name);
3290 }
3291 }
3292 }
3293 else if (i.tm.opcode_modifier & Modrm)
3294 {
3295 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3296 must be put into the modrm byte). Now, we make the modrm and
3297 index base bytes based on all the info we've collected. */
29b0f896
AM		 3298
3299 default_seg = build_modrm_byte ();
3300 }
3301 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3302 {
3303 if (i.tm.base_opcode == POP_SEG_SHORT
3304 && i.op[0].regs->reg_num == 1)
3305 {
3306 as_bad (_("you can't `pop %%cs'"));
3307 return 0;
3308 }
3309 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3310 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3311 i.rex |= REX_EXTZ;
3312 }
3313 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3314 {
3315 default_seg = &ds;
3316 }
3317 else if ((i.tm.opcode_modifier & IsString) != 0)
3318 {
3319 /* For the string instructions that allow a segment override
3320 on one of their operands, the default segment is ds. */
3321 default_seg = &ds;
3322 }
3323
30123838
JB		 3324 if ((i.tm.base_opcode == 0x8d /* lea */
3325 || (i.tm.cpu_flags & CpuSVME))
3326 && i.seg[0] && !quiet_warnings)
3327 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3328
3329 /* If a segment was explicitly specified, and the specified segment
3330 is not the default, use an opcode prefix to select it. If we
3331 never figured out what the default segment is, then default_seg
3332 will be zero at this point, and the specified segment prefix will
3333 always be used. */
29b0f896
AM		 3334 if ((i.seg[0]) && (i.seg[0] != default_seg))
3335 {
3336 if (!add_prefix (i.seg[0]->seg_prefix))
3337 return 0;
3338 }
3339 return 1;
3340}
3341
3342static const seg_entry *
e3bb37b5 3343build_modrm_byte (void)
29b0f896
AM		 3344{
3345 const seg_entry *default_seg = 0;
3346
3347 /* i.reg_operands MUST be the number of real register operands;
3348 implicit registers do not count. */
3349 if (i.reg_operands == 2)
3350 {
3351 unsigned int source, dest;
cab737b9
L		 3352
3353 switch (i.operands)
3354 {
3355 case 2:
3356 source = 0;
3357 break;
3358 case 3:
c81128dc
L		 3359 /* When there are 3 operands, one of them may be immediate,
3360 which may be the first or the last operand. Otherwise,
3361 the first operand must be shift count register (cl). */
3362 assert (i.imm_operands == 1
3363 || (i.imm_operands == 0
3364 && (i.types[0] & ShiftCount)));
3365 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3366 break;
3367 case 4:
3368 /* When there are 4 operands, the first two must be immediate
3369 operands. The source operand will be the 3rd one. */
3370 assert (i.imm_operands == 2
3371 && (i.types[0] & Imm)
3372 && (i.types[1] & Imm));
3373 source = 2;
3374 break;
3375 default:
3376 abort ();
3377 }
3378
29b0f896
AM		 3379 dest = source + 1;
3380
3381 i.rm.mode = 3;
3382 /* One of the register operands will be encoded in the i.tm.reg
3383 field, the other in the combined i.tm.mode and i.tm.regmem
3384 fields. If no form of this instruction supports a memory
3385 destination operand, then we assume the source operand may
3386 sometimes be a memory operand and so we need to store the
3387 destination in the i.rm.reg field. */
3388 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3389 {
3390 i.rm.reg = i.op[dest].regs->reg_num;
3391 i.rm.regmem = i.op[source].regs->reg_num;
3392 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3393 i.rex |= REX_EXTX;
3394 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3395 i.rex |= REX_EXTZ;
3396 }
3397 else
3398 {
3399 i.rm.reg = i.op[source].regs->reg_num;
3400 i.rm.regmem = i.op[dest].regs->reg_num;
3401 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3402 i.rex |= REX_EXTZ;
3403 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3404 i.rex |= REX_EXTX;
3405 }
c4a530c5
JB		 3406 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3407 {
3408 if (!((i.types[0] | i.types[1]) & Control))
3409 abort ();
3410 i.rex &= ~(REX_EXTX | REX_EXTZ);
3411 add_prefix (LOCK_PREFIX_OPCODE);
3412 }
29b0f896
AM		 3413 }
3414 else
3415 { /* If it's not 2 reg operands... */
3416 if (i.mem_operands)
3417 {
3418 unsigned int fake_zero_displacement = 0;
99018f42
L		 3419 unsigned int op;
3420
3421 for (op = 0; op < i.operands; op++)
3422 if ((i.types[op] & AnyMem))
3423 break;
3424 assert (op < i.operands);
29b0f896
AM		 3425
3426 default_seg = &ds;
3427
3428 if (i.base_reg == 0)
3429 {
3430 i.rm.mode = 0;
3431 if (!i.disp_operands)
3432 fake_zero_displacement = 1;
3433 if (i.index_reg == 0)
3434 {
3435 /* Operand is just <disp> */
20f0a1fc 3436 if (flag_code == CODE_64BIT)
29b0f896
AM		 3437 {
3438 /* 64bit mode overwrites the 32bit absolute
3439 addressing by RIP relative addressing and
3440 absolute addressing is encoded by one of the
3441 redundant SIB forms. */
3442 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3443 i.sib.base = NO_BASE_REGISTER;
3444 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3445 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3446 ? Disp32S : Disp32);
20f0a1fc 3447 }
fc225355
L		 3448 else if ((flag_code == CODE_16BIT)
3449 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3450 {
3451 i.rm.regmem = NO_BASE_REGISTER_16;
3452 i.types[op] = Disp16;
3453 }
3454 else
3455 {
3456 i.rm.regmem = NO_BASE_REGISTER;
3457 i.types[op] = Disp32;
29b0f896
AM		 3458 }
3459 }
3460 else /* !i.base_reg && i.index_reg */
3461 {
3462 i.sib.index = i.index_reg->reg_num;
3463 i.sib.base = NO_BASE_REGISTER;
3464 i.sib.scale = i.log2_scale_factor;
3465 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3466 i.types[op] &= ~Disp;
3467 if (flag_code != CODE_64BIT)
3468 i.types[op] |= Disp32; /* Must be 32 bit */
3469 else
3470 i.types[op] |= Disp32S;
3471 if ((i.index_reg->reg_flags & RegRex) != 0)
3472 i.rex |= REX_EXTY;
3473 }
3474 }
3475 /* RIP addressing for 64bit mode. */
3476 else if (i.base_reg->reg_type == BaseIndex)
3477 {
3478 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3479 i.types[op] &= ~ Disp;
29b0f896 3480 i.types[op] |= Disp32S;
71903a11 3481 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3482 if (! i.disp_operands)
3483 fake_zero_displacement = 1;
29b0f896
AM		 3484 }
3485 else if (i.base_reg->reg_type & Reg16)
3486 {
3487 switch (i.base_reg->reg_num)
3488 {
3489 case 3: /* (%bx) */
3490 if (i.index_reg == 0)
3491 i.rm.regmem = 7;
3492 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3493 i.rm.regmem = i.index_reg->reg_num - 6;
3494 break;
3495 case 5: /* (%bp) */
3496 default_seg = &ss;
3497 if (i.index_reg == 0)
3498 {
3499 i.rm.regmem = 6;
3500 if ((i.types[op] & Disp) == 0)
3501 {
3502 /* fake (%bp) into 0(%bp) */
3503 i.types[op] |= Disp8;
252b5132 3504 fake_zero_displacement = 1;
29b0f896
AM		 3505 }
3506 }
3507 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3508 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3509 break;
3510 default: /* (%si) -> 4 or (%di) -> 5 */
3511 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3512 }
3513 i.rm.mode = mode_from_disp_size (i.types[op]);
3514 }
3515 else /* i.base_reg and 32/64 bit mode */
3516 {
3517 if (flag_code == CODE_64BIT
3518 && (i.types[op] & Disp))
fc225355
L		 3519 i.types[op] = ((i.types[op] & Disp8)
3520 | (i.prefix[ADDR_PREFIX] == 0
3521 ? Disp32S : Disp32));
20f0a1fc 3522
29b0f896
AM		 3523 i.rm.regmem = i.base_reg->reg_num;
3524 if ((i.base_reg->reg_flags & RegRex) != 0)
3525 i.rex |= REX_EXTZ;
3526 i.sib.base = i.base_reg->reg_num;
3527 /* x86-64 ignores REX prefix bit here to avoid decoder
3528 complications. */
3529 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3530 {
3531 default_seg = &ss;
3532 if (i.disp_operands == 0)
3533 {
3534 fake_zero_displacement = 1;
3535 i.types[op] |= Disp8;
3536 }
3537 }
3538 else if (i.base_reg->reg_num == ESP_REG_NUM)
3539 {
3540 default_seg = &ss;
3541 }
3542 i.sib.scale = i.log2_scale_factor;
3543 if (i.index_reg == 0)
3544 {
3545 /* <disp>(%esp) becomes two byte modrm with no index
3546 register. We've already stored the code for esp
3547 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3548 Any base register besides %esp will not use the
3549 extra modrm byte. */
3550 i.sib.index = NO_INDEX_REGISTER;
3551#if !SCALE1_WHEN_NO_INDEX
3552 /* Another case where we force the second modrm byte. */
3553 if (i.log2_scale_factor)
3554 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3555#endif
29b0f896
AM		 3556 }
3557 else
3558 {
3559 i.sib.index = i.index_reg->reg_num;
3560 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3561 if ((i.index_reg->reg_flags & RegRex) != 0)
3562 i.rex |= REX_EXTY;
3563 }
67a4f2b7
AO		 3564
3565 if (i.disp_operands
3566 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3567 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3568 i.rm.mode = 0;
3569 else
3570 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3571 }
252b5132 3572
29b0f896
AM		 3573 if (fake_zero_displacement)
3574 {
3575 /* Fakes a zero displacement assuming that i.types[op]
3576 holds the correct displacement size. */
3577 expressionS *exp;
3578
3579 assert (i.op[op].disps == 0);
3580 exp = &disp_expressions[i.disp_operands++];
3581 i.op[op].disps = exp;
3582 exp->X_op = O_constant;
3583 exp->X_add_number = 0;
3584 exp->X_add_symbol = (symbolS *) 0;
3585 exp->X_op_symbol = (symbolS *) 0;
3586 }
3587 }
252b5132 3588
29b0f896
AM		 3589 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3590 (if any) based on i.tm.extension_opcode. Again, we must be
3591 careful to make sure that segment/control/debug/test/MMX
3592 registers are coded into the i.rm.reg field. */
3593 if (i.reg_operands)
3594 {
99018f42
L		 3595 unsigned int op;
3596
3597 for (op = 0; op < i.operands; op++)
3598 if ((i.types[op] & (Reg | RegMMX | RegXMM
3599 | SReg2 | SReg3
3600 | Control | Debug | Test)))
3601 break;
3602 assert (op < i.operands);
3603
29b0f896
AM		 3604 /* If there is an extension opcode to put here, the register
3605 number must be put into the regmem field. */
3606 if (i.tm.extension_opcode != None)
3607 {
3608 i.rm.regmem = i.op[op].regs->reg_num;
3609 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3610 i.rex |= REX_EXTZ;
3611 }
3612 else
3613 {
3614 i.rm.reg = i.op[op].regs->reg_num;
3615 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3616 i.rex |= REX_EXTX;
3617 }
252b5132 3618
29b0f896
AM		 3619 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3620 must set it to 3 to indicate this is a register operand
3621 in the regmem field. */
3622 if (!i.mem_operands)
3623 i.rm.mode = 3;
3624 }
252b5132 3625
29b0f896
AM		 3626 /* Fill in i.rm.reg field with extension opcode (if any). */
3627 if (i.tm.extension_opcode != None)
3628 i.rm.reg = i.tm.extension_opcode;
3629 }
3630 return default_seg;
3631}
252b5132 3632
29b0f896 3633static void
e3bb37b5 3634output_branch (void)
29b0f896
AM		 3635{
3636 char *p;
3637 int code16;
3638 int prefix;
3639 relax_substateT subtype;
3640 symbolS *sym;
3641 offsetT off;
3642
3643 code16 = 0;
3644 if (flag_code == CODE_16BIT)
3645 code16 = CODE16;
3646
3647 prefix = 0;
3648 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3649 {
29b0f896
AM		 3650 prefix = 1;
3651 i.prefixes -= 1;
3652 code16 ^= CODE16;
252b5132 3653 }
29b0f896
AM		 3654 /* Pentium4 branch hints. */
3655 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3656 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3657 {
29b0f896
AM		 3658 prefix++;
3659 i.prefixes--;
3660 }
3661 if (i.prefix[REX_PREFIX] != 0)
3662 {
3663 prefix++;
3664 i.prefixes--;
2f66722d
AM		 3665 }
3666
29b0f896
AM		 3667 if (i.prefixes != 0 && !intel_syntax)
3668 as_warn (_("skipping prefixes on this instruction"));
3669
3670 /* It's always a symbol; End frag & setup for relax.
3671 Make sure there is enough room in this frag for the largest
3672 instruction we may generate in md_convert_frag. This is 2
3673 bytes for the opcode and room for the prefix and largest
3674 displacement. */
3675 frag_grow (prefix + 2 + 4);
3676 /* Prefix and 1 opcode byte go in fr_fix. */
3677 p = frag_more (prefix + 1);
3678 if (i.prefix[DATA_PREFIX] != 0)
3679 *p++ = DATA_PREFIX_OPCODE;
3680 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3681 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3682 *p++ = i.prefix[SEG_PREFIX];
3683 if (i.prefix[REX_PREFIX] != 0)
3684 *p++ = i.prefix[REX_PREFIX];
3685 *p = i.tm.base_opcode;
3686
3687 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3688 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3689 else if ((cpu_arch_flags & Cpu386) != 0)
3690 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3691 else
3692 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3693 subtype |= code16;
3e73aa7c 3694
29b0f896
AM		 3695 sym = i.op[0].disps->X_add_symbol;
3696 off = i.op[0].disps->X_add_number;
3e73aa7c 3697
29b0f896
AM		 3698 if (i.op[0].disps->X_op != O_constant
3699 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3700 {
29b0f896
AM		 3701 /* Handle complex expressions. */
3702 sym = make_expr_symbol (i.op[0].disps);
3703 off = 0;
3704 }
3e73aa7c 3705
29b0f896
AM		 3706 /* 1 possible extra opcode + 4 byte displacement go in var part.
3707 Pass reloc in fr_var. */
3708 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3709}
3e73aa7c 3710
29b0f896 3711static void
e3bb37b5 3712output_jump (void)
29b0f896
AM		 3713{
3714 char *p;
3715 int size;
3e02c1cc 3716 fixS *fixP;
29b0f896
AM		 3717
3718 if (i.tm.opcode_modifier & JumpByte)
3719 {
3720 /* This is a loop or jecxz type instruction. */
3721 size = 1;
3722 if (i.prefix[ADDR_PREFIX] != 0)
3723 {
3724 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3725 i.prefixes -= 1;
3726 }
3727 /* Pentium4 branch hints. */
3728 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3729 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3730 {
3731 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3732 i.prefixes--;
3e73aa7c
JH		 3733 }
3734 }
29b0f896
AM		 3735 else
3736 {
3737 int code16;
3e73aa7c 3738
29b0f896
AM		 3739 code16 = 0;
3740 if (flag_code == CODE_16BIT)
3741 code16 = CODE16;
3e73aa7c 3742
29b0f896
AM		 3743 if (i.prefix[DATA_PREFIX] != 0)
3744 {
3745 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3746 i.prefixes -= 1;
3747 code16 ^= CODE16;
3748 }
252b5132 3749
29b0f896
AM		 3750 size = 4;
3751 if (code16)
3752 size = 2;
3753 }
9fcc94b6 3754
29b0f896
AM		 3755 if (i.prefix[REX_PREFIX] != 0)
3756 {
3757 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3758 i.prefixes -= 1;
3759 }
252b5132 3760
29b0f896
AM		 3761 if (i.prefixes != 0 && !intel_syntax)
3762 as_warn (_("skipping prefixes on this instruction"));
e0890092 3763
29b0f896
AM		 3764 p = frag_more (1 + size);
3765 *p++ = i.tm.base_opcode;
e0890092 3766
3e02c1cc
AM		 3767 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3768 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3769
3770 /* All jumps handled here are signed, but don't use a signed limit
3771 check for 32 and 16 bit jumps as we want to allow wrap around at
3772 4G and 64k respectively. */
3773 if (size == 1)
3774 fixP->fx_signed = 1;
29b0f896 3775}
e0890092 3776
29b0f896 3777static void
e3bb37b5 3778output_interseg_jump (void)
29b0f896
AM		 3779{
3780 char *p;
3781 int size;
3782 int prefix;
3783 int code16;
252b5132 3784
29b0f896
AM		 3785 code16 = 0;
3786 if (flag_code == CODE_16BIT)
3787 code16 = CODE16;
a217f122 3788
29b0f896
AM		 3789 prefix = 0;
3790 if (i.prefix[DATA_PREFIX] != 0)
3791 {
3792 prefix = 1;
3793 i.prefixes -= 1;
3794 code16 ^= CODE16;
3795 }
3796 if (i.prefix[REX_PREFIX] != 0)
3797 {
3798 prefix++;
3799 i.prefixes -= 1;
3800 }
252b5132 3801
29b0f896
AM		 3802 size = 4;
3803 if (code16)
3804 size = 2;
252b5132 3805
29b0f896
AM		 3806 if (i.prefixes != 0 && !intel_syntax)
3807 as_warn (_("skipping prefixes on this instruction"));
252b5132 3808
29b0f896
AM		 3809 /* 1 opcode; 2 segment; offset */
3810 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3811
29b0f896
AM		 3812 if (i.prefix[DATA_PREFIX] != 0)
3813 *p++ = DATA_PREFIX_OPCODE;
252b5132 3814
29b0f896
AM		 3815 if (i.prefix[REX_PREFIX] != 0)
3816 *p++ = i.prefix[REX_PREFIX];
252b5132 3817
29b0f896
AM		 3818 *p++ = i.tm.base_opcode;
3819 if (i.op[1].imms->X_op == O_constant)
3820 {
3821 offsetT n = i.op[1].imms->X_add_number;
252b5132 3822
29b0f896
AM		 3823 if (size == 2
3824 && !fits_in_unsigned_word (n)
3825 && !fits_in_signed_word (n))
3826 {
3827 as_bad (_("16-bit jump out of range"));
3828 return;
3829 }
3830 md_number_to_chars (p, n, size);
3831 }
3832 else
3833 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3834 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3835 if (i.op[0].imms->X_op != O_constant)
3836 as_bad (_("can't handle non absolute segment in `%s'"),
3837 i.tm.name);
3838 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3839}
a217f122 3840
29b0f896 3841static void
e3bb37b5 3842output_insn (void)
29b0f896 3843{
2bbd9c25
JJ		 3844 fragS *insn_start_frag;
3845 offsetT insn_start_off;
3846
29b0f896
AM		 3847 /* Tie dwarf2 debug info to the address at the start of the insn.
3848 We can't do this after the insn has been output as the current
3849 frag may have been closed off. eg. by frag_var. */
3850 dwarf2_emit_insn (0);
3851
2bbd9c25
JJ		 3852 insn_start_frag = frag_now;
3853 insn_start_off = frag_now_fix ();
3854
29b0f896
AM		 3855 /* Output jumps. */
3856 if (i.tm.opcode_modifier & Jump)
3857 output_branch ();
3858 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3859 output_jump ();
3860 else if (i.tm.opcode_modifier & JumpInterSegment)
3861 output_interseg_jump ();
3862 else
3863 {
3864 /* Output normal instructions here. */
3865 char *p;
3866 unsigned char *q;
331d2d0d 3867 unsigned int prefix;
252b5132 3868
ef05d495
L		 3869 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3870 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3871 use one more higher byte to specify a prefix the instruction
3872 requires. */
3873 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3874 {
331d2d0d
L		 3875 if (i.tm.base_opcode & 0xff000000)
3876 {
3877 prefix = (i.tm.base_opcode >> 24) & 0xff;
3878 goto check_prefix;
3879 }
3880 }
3881 else if ((i.tm.base_opcode & 0xff0000) != 0)
3882 {
3883 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3884 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3885 {
64e74474 3886 check_prefix:
bc4bd9ab
MK		 3887 if (prefix != REPE_PREFIX_OPCODE
3888 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3889 add_prefix (prefix);
3890 }
3891 else
331d2d0d 3892 add_prefix (prefix);
0f10071e 3893 }
252b5132 3894
29b0f896
AM		 3895 /* The prefix bytes. */
3896 for (q = i.prefix;
3897 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3898 q++)
3899 {
3900 if (*q)
3901 {
3902 p = frag_more (1);
3903 md_number_to_chars (p, (valueT) *q, 1);
3904 }
3905 }
252b5132 3906
29b0f896
AM		 3907 /* Now the opcode; be careful about word order here! */
3908 if (fits_in_unsigned_byte (i.tm.base_opcode))
3909 {
3910 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3911 }
3912 else
3913 {
ef05d495 3914 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3915 {
3916 p = frag_more (3);
3917 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3918 }
3919 else
3920 p = frag_more (2);
0f10071e 3921
29b0f896
AM		 3922 /* Put out high byte first: can't use md_number_to_chars! */
3923 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3924 *p = i.tm.base_opcode & 0xff;
3925 }
3e73aa7c 3926
29b0f896
AM		 3927 /* Now the modrm byte and sib byte (if present). */
3928 if (i.tm.opcode_modifier & Modrm)
3929 {
3930 p = frag_more (1);
3931 md_number_to_chars (p,
3932 (valueT) (i.rm.regmem << 0
3933 | i.rm.reg << 3
3934 | i.rm.mode << 6),
3935 1);
3936 /* If i.rm.regmem == ESP (4)
3937 && i.rm.mode != (Register mode)
3938 && not 16 bit
3939 ==> need second modrm byte. */
3940 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3941 && i.rm.mode != 3
3942 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3943 {
3944 p = frag_more (1);
3945 md_number_to_chars (p,
3946 (valueT) (i.sib.base << 0
3947 | i.sib.index << 3
3948 | i.sib.scale << 6),
3949 1);
3950 }
3951 }
3e73aa7c 3952
29b0f896 3953 if (i.disp_operands)
2bbd9c25 3954 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3955
29b0f896 3956 if (i.imm_operands)
2bbd9c25 3957 output_imm (insn_start_frag, insn_start_off);
29b0f896 3958 }
252b5132 3959
29b0f896
AM		 3960#ifdef DEBUG386
3961 if (flag_debug)
3962 {
7b81dfbb 3963 pi ("" /*line*/, &i);
29b0f896
AM		 3964 }
3965#endif /* DEBUG386 */
3966}
252b5132 3967
29b0f896 3968static void
64e74474 3969output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3970{
3971 char *p;
3972 unsigned int n;
252b5132 3973
29b0f896
AM		 3974 for (n = 0; n < i.operands; n++)
3975 {
3976 if (i.types[n] & Disp)
3977 {
3978 if (i.op[n].disps->X_op == O_constant)
3979 {
3980 int size;
3981 offsetT val;
252b5132 3982
29b0f896
AM		 3983 size = 4;
3984 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3985 {
3986 size = 2;
3987 if (i.types[n] & Disp8)
3988 size = 1;
3989 if (i.types[n] & Disp64)
3990 size = 8;
3991 }
3992 val = offset_in_range (i.op[n].disps->X_add_number,
3993 size);
3994 p = frag_more (size);
3995 md_number_to_chars (p, val, size);
3996 }
3997 else
3998 {
f86103b7 3999 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4000 int size = 4;
4001 int sign = 0;
4002 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4003
4004 /* The PC relative address is computed relative
4005 to the instruction boundary, so in case immediate
4006 fields follows, we need to adjust the value. */
4007 if (pcrel && i.imm_operands)
4008 {
4009 int imm_size = 4;
4010 unsigned int n1;
252b5132 4011
29b0f896
AM		 4012 for (n1 = 0; n1 < i.operands; n1++)
4013 if (i.types[n1] & Imm)
252b5132 4014 {
29b0f896 4015 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4016 {
29b0f896
AM		 4017 imm_size = 2;
4018 if (i.types[n1] & (Imm8 | Imm8S))
4019 imm_size = 1;
4020 if (i.types[n1] & Imm64)
4021 imm_size = 8;
252b5132 4022 }
29b0f896 4023 break;
252b5132 4024 }
29b0f896
AM		 4025 /* We should find the immediate. */
4026 if (n1 == i.operands)
4027 abort ();
4028 i.op[n].disps->X_add_number -= imm_size;
4029 }
520dc8e8 4030
29b0f896
AM		 4031 if (i.types[n] & Disp32S)
4032 sign = 1;
3e73aa7c 4033
29b0f896
AM		 4034 if (i.types[n] & (Disp16 | Disp64))
4035 {
4036 size = 2;
4037 if (i.types[n] & Disp64)
4038 size = 8;
4039 }
520dc8e8 4040
29b0f896 4041 p = frag_more (size);
2bbd9c25 4042 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4043 if (GOT_symbol
2bbd9c25 4044 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4045 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4046 || reloc_type == BFD_RELOC_X86_64_32S
4047 || (reloc_type == BFD_RELOC_64
4048 && object_64bit))
d6ab8113
JB		 4049 && (i.op[n].disps->X_op == O_symbol
4050 || (i.op[n].disps->X_op == O_add
4051 && ((symbol_get_value_expression
4052 (i.op[n].disps->X_op_symbol)->X_op)
4053 == O_subtract))))
4054 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4055 {
4056 offsetT add;
4057
4058 if (insn_start_frag == frag_now)
4059 add = (p - frag_now->fr_literal) - insn_start_off;
4060 else
4061 {
4062 fragS *fr;
4063
4064 add = insn_start_frag->fr_fix - insn_start_off;
4065 for (fr = insn_start_frag->fr_next;
4066 fr && fr != frag_now; fr = fr->fr_next)
4067 add += fr->fr_fix;
4068 add += p - frag_now->fr_literal;
4069 }
4070
4fa24527 4071 if (!object_64bit)
7b81dfbb
AJ		 4072 {
4073 reloc_type = BFD_RELOC_386_GOTPC;
4074 i.op[n].imms->X_add_number += add;
4075 }
4076 else if (reloc_type == BFD_RELOC_64)
4077 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4078 else
7b81dfbb
AJ		 4079 /* Don't do the adjustment for x86-64, as there
4080 the pcrel addressing is relative to the _next_
4081 insn, and that is taken care of in other code. */
d6ab8113 4082 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4083 }
062cd5e7 4084 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4085 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4086 }
4087 }
4088 }
4089}
252b5132 4090
29b0f896 4091static void
64e74474 4092output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4093{
4094 char *p;
4095 unsigned int n;
252b5132 4096
29b0f896
AM		 4097 for (n = 0; n < i.operands; n++)
4098 {
4099 if (i.types[n] & Imm)
4100 {
4101 if (i.op[n].imms->X_op == O_constant)
4102 {
4103 int size;
4104 offsetT val;
b4cac588 4105
29b0f896
AM		 4106 size = 4;
4107 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4108 {
4109 size = 2;
4110 if (i.types[n] & (Imm8 | Imm8S))
4111 size = 1;
4112 else if (i.types[n] & Imm64)
4113 size = 8;
4114 }
4115 val = offset_in_range (i.op[n].imms->X_add_number,
4116 size);
4117 p = frag_more (size);
4118 md_number_to_chars (p, val, size);
4119 }
4120 else
4121 {
4122 /* Not absolute_section.
4123 Need a 32-bit fixup (don't support 8bit
4124 non-absolute imms). Try to support other
4125 sizes ... */
f86103b7 4126 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4127 int size = 4;
4128 int sign = 0;
4129
4130 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4131 && (i.suffix == QWORD_MNEM_SUFFIX
4132 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4133 sign = 1;
4134 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4135 {
4136 size = 2;
4137 if (i.types[n] & (Imm8 | Imm8S))
4138 size = 1;
4139 if (i.types[n] & Imm64)
4140 size = 8;
4141 }
520dc8e8 4142
29b0f896
AM		 4143 p = frag_more (size);
4144 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4145
2bbd9c25
JJ		 4146 /* This is tough to explain. We end up with this one if we
4147 * have operands that look like
4148 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4149 * obtain the absolute address of the GOT, and it is strongly
4150 * preferable from a performance point of view to avoid using
4151 * a runtime relocation for this. The actual sequence of
4152 * instructions often look something like:
4153 *
4154 * call .L66
4155 * .L66:
4156 * popl %ebx
4157 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4158 *
4159 * The call and pop essentially return the absolute address
4160 * of the label .L66 and store it in %ebx. The linker itself
4161 * will ultimately change the first operand of the addl so
4162 * that %ebx points to the GOT, but to keep things simple, the
4163 * .o file must have this operand set so that it generates not
4164 * the absolute address of .L66, but the absolute address of
4165 * itself. This allows the linker itself simply treat a GOTPC
4166 * relocation as asking for a pcrel offset to the GOT to be
4167 * added in, and the addend of the relocation is stored in the
4168 * operand field for the instruction itself.
4169 *
4170 * Our job here is to fix the operand so that it would add
4171 * the correct offset so that %ebx would point to itself. The
4172 * thing that is tricky is that .-.L66 will point to the
4173 * beginning of the instruction, so we need to further modify
4174 * the operand so that it will point to itself. There are
4175 * other cases where you have something like:
4176 *
4177 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4178 *
4179 * and here no correction would be required. Internally in
4180 * the assembler we treat operands of this form as not being
4181 * pcrel since the '.' is explicitly mentioned, and I wonder
4182 * whether it would simplify matters to do it this way. Who
4183 * knows. In earlier versions of the PIC patches, the
4184 * pcrel_adjust field was used to store the correction, but
4185 * since the expression is not pcrel, I felt it would be
4186 * confusing to do it this way. */
4187
d6ab8113 4188 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4189 || reloc_type == BFD_RELOC_X86_64_32S
4190 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4191 && GOT_symbol
4192 && GOT_symbol == i.op[n].imms->X_add_symbol
4193 && (i.op[n].imms->X_op == O_symbol
4194 || (i.op[n].imms->X_op == O_add
4195 && ((symbol_get_value_expression
4196 (i.op[n].imms->X_op_symbol)->X_op)
4197 == O_subtract))))
4198 {
2bbd9c25
JJ		 4199 offsetT add;
4200
4201 if (insn_start_frag == frag_now)
4202 add = (p - frag_now->fr_literal) - insn_start_off;
4203 else
4204 {
4205 fragS *fr;
4206
4207 add = insn_start_frag->fr_fix - insn_start_off;
4208 for (fr = insn_start_frag->fr_next;
4209 fr && fr != frag_now; fr = fr->fr_next)
4210 add += fr->fr_fix;
4211 add += p - frag_now->fr_literal;
4212 }
4213
4fa24527 4214 if (!object_64bit)
d6ab8113 4215 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4216 else if (size == 4)
d6ab8113 4217 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4218 else if (size == 8)
4219 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4220 i.op[n].imms->X_add_number += add;
29b0f896 4221 }
29b0f896
AM		 4222 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4223 i.op[n].imms, 0, reloc_type);
4224 }
4225 }
4226 }
252b5132
RH		 4227}
4228\f
d182319b
JB		 4229/* x86_cons_fix_new is called via the expression parsing code when a
4230 reloc is needed. We use this hook to get the correct .got reloc. */
4231static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4232static int cons_sign = -1;
4233
4234void
e3bb37b5 4235x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4236 expressionS *exp)
d182319b
JB		 4237{
4238 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4239
4240 got_reloc = NO_RELOC;
4241
4242#ifdef TE_PE
4243 if (exp->X_op == O_secrel)
4244 {
4245 exp->X_op = O_symbol;
4246 r = BFD_RELOC_32_SECREL;
4247 }
4248#endif
4249
4250 fix_new_exp (frag, off, len, exp, 0, r);
4251}
4252
718ddfc0
JB		 4253#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4254# define lex_got(reloc, adjust, types) NULL
4255#else
f3c180ae
AM		 4256/* Parse operands of the form
4257 <symbol>@GOTOFF+<nnn>
4258 and similar .plt or .got references.
4259
4260 If we find one, set up the correct relocation in RELOC and copy the
4261 input string, minus the `@GOTOFF' into a malloc'd buffer for
4262 parsing by the calling routine. Return this buffer, and if ADJUST
4263 is non-null set it to the length of the string we removed from the
4264 input line. Otherwise return NULL. */
4265static char *
3956db08 4266lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4267 int *adjust,
4268 unsigned int *types)
f3c180ae 4269{
7b81dfbb
AJ		 4270 /* Some of the relocations depend on the size of what field is to
4271 be relocated. But in our callers i386_immediate and i386_displacement
4272 we don't yet know the operand size (this will be set by insn
4273 matching). Hence we record the word32 relocation here,
4274 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4275 static const struct {
4276 const char *str;
4fa24527 4277 const enum bfd_reloc_code_real rel[2];
3956db08 4278 const unsigned int types64;
f3c180ae 4279 } gotrel[] = {
7b81dfbb 4280 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4281 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4282 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4283 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4284 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4285 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4286 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4287 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4288 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4289 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4290 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4291 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4292 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4293 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4294 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4295 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4296 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4297 };
4298 char *cp;
4299 unsigned int j;
4300
718ddfc0
JB		 4301 if (!IS_ELF)
4302 return NULL;
4303
f3c180ae
AM		 4304 for (cp = input_line_pointer; *cp != '@'; cp++)
4305 if (is_end_of_line[(unsigned char) *cp])
4306 return NULL;
4307
4308 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4309 {
4310 int len;
4311
4312 len = strlen (gotrel[j].str);
28f81592 4313 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4314 {
4fa24527 4315 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4316 {
28f81592
AM		 4317 int first, second;
4318 char *tmpbuf, *past_reloc;
f3c180ae 4319
4fa24527 4320 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4321 if (adjust)
4322 *adjust = len;
f3c180ae 4323
3956db08
JB		 4324 if (types)
4325 {
4326 if (flag_code != CODE_64BIT)
4327 *types = Imm32|Disp32;
4328 else
4329 *types = gotrel[j].types64;
4330 }
4331
f3c180ae
AM		 4332 if (GOT_symbol == NULL)
4333 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4334
4335 /* Replace the relocation token with ' ', so that
4336 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4337
4338 /* The length of the first part of our input line. */
f3c180ae 4339 first = cp - input_line_pointer;
28f81592
AM		 4340
4341 /* The second part goes from after the reloc token until
4342 (and including) an end_of_line char. Don't use strlen
4343 here as the end_of_line char may not be a NUL. */
4344 past_reloc = cp + 1 + len;
4345 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4346 ;
4347 second = cp - past_reloc;
4348
4349 /* Allocate and copy string. The trailing NUL shouldn't
4350 be necessary, but be safe. */
4351 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4352 memcpy (tmpbuf, input_line_pointer, first);
4353 tmpbuf[first] = ' ';
28f81592
AM		 4354 memcpy (tmpbuf + first + 1, past_reloc, second);
4355 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4356 return tmpbuf;
4357 }
4358
4fa24527
JB		 4359 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4360 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4361 return NULL;
4362 }
4363 }
4364
4365 /* Might be a symbol version string. Don't as_bad here. */
4366 return NULL;
4367}
4368
f3c180ae 4369void
e3bb37b5 4370x86_cons (expressionS *exp, int size)
f3c180ae 4371{
4fa24527 4372 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4373 {
4374 /* Handle @GOTOFF and the like in an expression. */
4375 char *save;
4376 char *gotfree_input_line;
4377 int adjust;
4378
4379 save = input_line_pointer;
3956db08 4380 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4381 if (gotfree_input_line)
4382 input_line_pointer = gotfree_input_line;
4383
4384 expression (exp);
4385
4386 if (gotfree_input_line)
4387 {
4388 /* expression () has merrily parsed up to the end of line,
4389 or a comma - in the wrong buffer. Transfer how far
4390 input_line_pointer has moved to the right buffer. */
4391 input_line_pointer = (save
4392 + (input_line_pointer - gotfree_input_line)
4393 + adjust);
4394 free (gotfree_input_line);
4395 }
4396 }
4397 else
4398 expression (exp);
4399}
4400#endif
4401
d182319b 4402static void signed_cons (int size)
6482c264 4403{
d182319b
JB		 4404 if (flag_code == CODE_64BIT)
4405 cons_sign = 1;
4406 cons (size);
4407 cons_sign = -1;
6482c264
NC		 4408}
4409
d182319b 4410#ifdef TE_PE
6482c264
NC		 4411static void
4412pe_directive_secrel (dummy)
4413 int dummy ATTRIBUTE_UNUSED;
4414{
4415 expressionS exp;
4416
4417 do
4418 {
4419 expression (&exp);
4420 if (exp.X_op == O_symbol)
4421 exp.X_op = O_secrel;
4422
4423 emit_expr (&exp, 4);
4424 }
4425 while (*input_line_pointer++ == ',');
4426
4427 input_line_pointer--;
4428 demand_empty_rest_of_line ();
4429}
6482c264
NC		 4430#endif
4431
252b5132 4432static int
70e41ade 4433i386_immediate (char *imm_start)
252b5132
RH		 4434{
4435 char *save_input_line_pointer;
f3c180ae 4436 char *gotfree_input_line;
252b5132 4437 segT exp_seg = 0;
47926f60 4438 expressionS *exp;
3956db08 4439 unsigned int types = ~0U;
252b5132
RH		 4440
4441 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4442 {
31b2323c
L		 4443 as_bad (_("at most %d immediate operands are allowed"),
4444 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4445 return 0;
4446 }
4447
4448 exp = &im_expressions[i.imm_operands++];
520dc8e8 4449 i.op[this_operand].imms = exp;
252b5132
RH		 4450
4451 if (is_space_char (*imm_start))
4452 ++imm_start;
4453
4454 save_input_line_pointer = input_line_pointer;
4455 input_line_pointer = imm_start;
4456
3956db08 4457 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4458 if (gotfree_input_line)
4459 input_line_pointer = gotfree_input_line;
252b5132
RH		 4460
4461 exp_seg = expression (exp);
4462
83183c0c 4463 SKIP_WHITESPACE ();
252b5132 4464 if (*input_line_pointer)
f3c180ae 4465 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4466
4467 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4468 if (gotfree_input_line)
4469 free (gotfree_input_line);
252b5132 4470
2daf4fd8 4471 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4472 {
47926f60 4473 /* Missing or bad expr becomes absolute 0. */
d0b47220 4474 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4475 imm_start);
252b5132
RH		 4476 exp->X_op = O_constant;
4477 exp->X_add_number = 0;
4478 exp->X_add_symbol = (symbolS *) 0;
4479 exp->X_op_symbol = (symbolS *) 0;
252b5132 4480 }
3e73aa7c 4481 else if (exp->X_op == O_constant)
252b5132 4482 {
47926f60 4483 /* Size it properly later. */
3e73aa7c
JH		 4484 i.types[this_operand] |= Imm64;
4485 /* If BFD64, sign extend val. */
4486 if (!use_rela_relocations)
4487 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4488 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4489 }
4c63da97 4490#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4491 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4492 && exp_seg != absolute_section
47926f60 4493 && exp_seg != text_section
24eab124
AM		 4494 && exp_seg != data_section
4495 && exp_seg != bss_section
4496 && exp_seg != undefined_section
f86103b7 4497 && !bfd_is_com_section (exp_seg))
252b5132 4498 {
d0b47220 4499 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4500 return 0;
4501 }
4502#endif
bb8f5920
L		 4503 else if (!intel_syntax && exp->X_op == O_register)
4504 {
4505 as_bad (_("illegal immediate register operand %s"), imm_start);
4506 return 0;
4507 }
252b5132
RH		 4508 else
4509 {
4510 /* This is an address. The size of the address will be
24eab124 4511 determined later, depending on destination register,
3e73aa7c
JH		 4512 suffix, or the default for the section. */
4513 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4514 i.types[this_operand] &= types;
252b5132
RH		 4515 }
4516
4517 return 1;
4518}
4519
551c1ca1 4520static char *
e3bb37b5 4521i386_scale (char *scale)
252b5132 4522{
551c1ca1
AM		 4523 offsetT val;
4524 char *save = input_line_pointer;
252b5132 4525
551c1ca1
AM		 4526 input_line_pointer = scale;
4527 val = get_absolute_expression ();
4528
4529 switch (val)
252b5132 4530 {
551c1ca1 4531 case 1:
252b5132
RH		 4532 i.log2_scale_factor = 0;
4533 break;
551c1ca1 4534 case 2:
252b5132
RH		 4535 i.log2_scale_factor = 1;
4536 break;
551c1ca1 4537 case 4:
252b5132
RH		 4538 i.log2_scale_factor = 2;
4539 break;
551c1ca1 4540 case 8:
252b5132
RH		 4541 i.log2_scale_factor = 3;
4542 break;
4543 default:
a724f0f4
JB		 4544 {
4545 char sep = *input_line_pointer;
4546
4547 *input_line_pointer = '\0';
4548 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4549 scale);
4550 *input_line_pointer = sep;
4551 input_line_pointer = save;
4552 return NULL;
4553 }
252b5132 4554 }
29b0f896 4555 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4556 {
4557 as_warn (_("scale factor of %d without an index register"),
24eab124 4558 1 << i.log2_scale_factor);
252b5132
RH		 4559#if SCALE1_WHEN_NO_INDEX
4560 i.log2_scale_factor = 0;
4561#endif
4562 }
551c1ca1
AM		 4563 scale = input_line_pointer;
4564 input_line_pointer = save;
4565 return scale;
252b5132
RH		 4566}
4567
252b5132 4568static int
e3bb37b5 4569i386_displacement (char *disp_start, char *disp_end)
252b5132 4570{
29b0f896 4571 expressionS *exp;
252b5132
RH		 4572 segT exp_seg = 0;
4573 char *save_input_line_pointer;
f3c180ae 4574 char *gotfree_input_line;
e05278af 4575 int bigdisp, override;
3956db08 4576 unsigned int types = Disp;
252b5132 4577
31b2323c
L		 4578 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4579 {
4580 as_bad (_("at most %d displacement operands are allowed"),
4581 MAX_MEMORY_OPERANDS);
4582 return 0;
4583 }
4584
e05278af
JB		 4585 if ((i.types[this_operand] & JumpAbsolute)
4586 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4587 {
4588 bigdisp = Disp32;
4589 override = (i.prefix[ADDR_PREFIX] != 0);
4590 }
4591 else
4592 {
4593 /* For PC-relative branches, the width of the displacement
4594 is dependent upon data size, not address size. */
4595 bigdisp = 0;
4596 override = (i.prefix[DATA_PREFIX] != 0);
4597 }
3e73aa7c 4598 if (flag_code == CODE_64BIT)
7ecd2f8b 4599 {
e05278af 4600 if (!bigdisp)
64e74474
AM		 4601 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4602 ? Disp16
4603 : Disp32S | Disp32);
e05278af 4604 else if (!override)
3956db08 4605 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4606 }
e05278af
JB		 4607 else
4608 {
4609 if (!bigdisp)
4610 {
4611 if (!override)
4612 override = (i.suffix == (flag_code != CODE_16BIT
4613 ? WORD_MNEM_SUFFIX
4614 : LONG_MNEM_SUFFIX));
4615 bigdisp = Disp32;
4616 }
4617 if ((flag_code == CODE_16BIT) ^ override)
4618 bigdisp = Disp16;
4619 }
252b5132
RH		 4620 i.types[this_operand] |= bigdisp;
4621
4622 exp = &disp_expressions[i.disp_operands];
520dc8e8 4623 i.op[this_operand].disps = exp;
252b5132
RH		 4624 i.disp_operands++;
4625 save_input_line_pointer = input_line_pointer;
4626 input_line_pointer = disp_start;
4627 END_STRING_AND_SAVE (disp_end);
4628
4629#ifndef GCC_ASM_O_HACK
4630#define GCC_ASM_O_HACK 0
4631#endif
4632#if GCC_ASM_O_HACK
4633 END_STRING_AND_SAVE (disp_end + 1);
4634 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4635 && displacement_string_end[-1] == '+')
252b5132
RH		 4636 {
4637 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4638 constraint within gcc asm statements.
4639 For instance:
4640
4641 #define _set_tssldt_desc(n,addr,limit,type) \
4642 __asm__ __volatile__ ( \
4643 "movw %w2,%0\n\t" \
4644 "movw %w1,2+%0\n\t" \
4645 "rorl $16,%1\n\t" \
4646 "movb %b1,4+%0\n\t" \
4647 "movb %4,5+%0\n\t" \
4648 "movb $0,6+%0\n\t" \
4649 "movb %h1,7+%0\n\t" \
4650 "rorl $16,%1" \
4651 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4652
4653 This works great except that the output assembler ends
4654 up looking a bit weird if it turns out that there is
4655 no offset. You end up producing code that looks like:
4656
4657 #APP
4658 movw $235,(%eax)
4659 movw %dx,2+(%eax)
4660 rorl $16,%edx
4661 movb %dl,4+(%eax)
4662 movb $137,5+(%eax)
4663 movb $0,6+(%eax)
4664 movb %dh,7+(%eax)
4665 rorl $16,%edx
4666 #NO_APP
4667
47926f60 4668 So here we provide the missing zero. */
24eab124
AM		 4669
4670 *displacement_string_end = '0';
252b5132
RH		 4671 }
4672#endif
3956db08 4673 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4674 if (gotfree_input_line)
4675 input_line_pointer = gotfree_input_line;
252b5132 4676
24eab124 4677 exp_seg = expression (exp);
252b5132 4678
636c26b0
AM		 4679 SKIP_WHITESPACE ();
4680 if (*input_line_pointer)
4681 as_bad (_("junk `%s' after expression"), input_line_pointer);
4682#if GCC_ASM_O_HACK
4683 RESTORE_END_STRING (disp_end + 1);
4684#endif
4685 RESTORE_END_STRING (disp_end);
4686 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4687 if (gotfree_input_line)
4688 free (gotfree_input_line);
636c26b0 4689
24eab124
AM		 4690 /* We do this to make sure that the section symbol is in
4691 the symbol table. We will ultimately change the relocation
47926f60 4692 to be relative to the beginning of the section. */
1ae12ab7 4693 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4694 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4695 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4696 {
636c26b0
AM		 4697 if (exp->X_op != O_symbol)
4698 {
4699 as_bad (_("bad expression used with @%s"),
4700 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4701 ? "GOTPCREL"
4702 : "GOTOFF"));
4703 return 0;
4704 }
4705
e5cb08ac 4706 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4707 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4708 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4709 exp->X_op = O_subtract;
4710 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4711 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4712 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4713 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4714 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4715 else
29b0f896 4716 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4717 }
252b5132 4718
2daf4fd8
AM		 4719 if (exp->X_op == O_absent || exp->X_op == O_big)
4720 {
47926f60 4721 /* Missing or bad expr becomes absolute 0. */
d0b47220 4722 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4723 disp_start);
4724 exp->X_op = O_constant;
4725 exp->X_add_number = 0;
4726 exp->X_add_symbol = (symbolS *) 0;
4727 exp->X_op_symbol = (symbolS *) 0;
4728 }
4729
4c63da97 4730#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4731 if (exp->X_op != O_constant
45288df1 4732 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4733 && exp_seg != absolute_section
45288df1
AM		 4734 && exp_seg != text_section
4735 && exp_seg != data_section
4736 && exp_seg != bss_section
31312f95 4737 && exp_seg != undefined_section
f86103b7 4738 && !bfd_is_com_section (exp_seg))
24eab124 4739 {
d0b47220 4740 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4741 return 0;
4742 }
252b5132 4743#endif
3956db08
JB		 4744
4745 if (!(i.types[this_operand] & ~Disp))
4746 i.types[this_operand] &= types;
4747
252b5132
RH		 4748 return 1;
4749}
4750
eecb386c 4751/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4752 Return 1 on success, 0 on a failure. */
4753
252b5132 4754static int
e3bb37b5 4755i386_index_check (const char *operand_string)
252b5132 4756{
3e73aa7c 4757 int ok;
24eab124 4758#if INFER_ADDR_PREFIX
eecb386c
AM		 4759 int fudged = 0;
4760
24eab124
AM		 4761 tryprefix:
4762#endif
3e73aa7c 4763 ok = 1;
30123838
JB		 4764 if ((current_templates->start->cpu_flags & CpuSVME)
4765 && current_templates->end[-1].operand_types[0] == AnyMem)
4766 {
4767 /* Memory operands of SVME insns are special in that they only allow
4768 rAX as their memory address and ignore any segment override. */
4769 unsigned RegXX;
4770
4771 /* SKINIT is even more restrictive: it always requires EAX. */
4772 if (strcmp (current_templates->start->name, "skinit") == 0)
4773 RegXX = Reg32;
4774 else if (flag_code == CODE_64BIT)
4775 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4776 else
64e74474
AM		 4777 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4778 ? Reg16
4779 : Reg32);
30123838
JB		 4780 if (!i.base_reg
4781 || !(i.base_reg->reg_type & Acc)
4782 || !(i.base_reg->reg_type & RegXX)
4783 || i.index_reg
4784 || (i.types[0] & Disp))
4785 ok = 0;
4786 }
4787 else if (flag_code == CODE_64BIT)
64e74474
AM		 4788 {
4789 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4790
4791 if ((i.base_reg
4792 && ((i.base_reg->reg_type & RegXX) == 0)
4793 && (i.base_reg->reg_type != BaseIndex
4794 || i.index_reg))
4795 || (i.index_reg
4796 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4797 != (RegXX | BaseIndex))))
4798 ok = 0;
3e73aa7c
JH		 4799 }
4800 else
4801 {
4802 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4803 {
4804 /* 16bit checks. */
4805 if ((i.base_reg
29b0f896
AM		 4806 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4807 != (Reg16 | BaseIndex)))
3e73aa7c 4808 || (i.index_reg
29b0f896
AM		 4809 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4810 != (Reg16 | BaseIndex))
4811 || !(i.base_reg
4812 && i.base_reg->reg_num < 6
4813 && i.index_reg->reg_num >= 6
4814 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4815 ok = 0;
4816 }
4817 else
e5cb08ac 4818 {
3e73aa7c
JH		 4819 /* 32bit checks. */
4820 if ((i.base_reg
4821 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4822 || (i.index_reg
29b0f896
AM		 4823 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4824 != (Reg32 | BaseIndex))))
e5cb08ac 4825 ok = 0;
3e73aa7c
JH		 4826 }
4827 }
4828 if (!ok)
24eab124
AM		 4829 {
4830#if INFER_ADDR_PREFIX
20f0a1fc 4831 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4832 {
4833 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4834 i.prefixes += 1;
b23bac36
AM		 4835 /* Change the size of any displacement too. At most one of
4836 Disp16 or Disp32 is set.
4837 FIXME. There doesn't seem to be any real need for separate
4838 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4839 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4840 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4841 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4842 fudged = 1;
24eab124
AM		 4843 goto tryprefix;
4844 }
eecb386c
AM		 4845 if (fudged)
4846 as_bad (_("`%s' is not a valid base/index expression"),
4847 operand_string);
4848 else
c388dee8 4849#endif
eecb386c
AM		 4850 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4851 operand_string,
3e73aa7c 4852 flag_code_names[flag_code]);
24eab124 4853 }
20f0a1fc 4854 return ok;
24eab124 4855}
252b5132 4856
252b5132 4857/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4858 on error. */
252b5132 4859
252b5132 4860static int
e3bb37b5 4861i386_operand (char *operand_string)
252b5132 4862{
af6bdddf
AM		 4863 const reg_entry *r;
4864 char *end_op;
24eab124 4865 char *op_string = operand_string;
252b5132 4866
24eab124 4867 if (is_space_char (*op_string))
252b5132
RH		 4868 ++op_string;
4869
24eab124 4870 /* We check for an absolute prefix (differentiating,
47926f60 4871 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4872 if (*op_string == ABSOLUTE_PREFIX)
4873 {
4874 ++op_string;
4875 if (is_space_char (*op_string))
4876 ++op_string;
4877 i.types[this_operand] |= JumpAbsolute;
4878 }
252b5132 4879
47926f60 4880 /* Check if operand is a register. */
4d1bb795 4881 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4882 {
24eab124
AM		 4883 /* Check for a segment override by searching for ':' after a
4884 segment register. */
4885 op_string = end_op;
4886 if (is_space_char (*op_string))
4887 ++op_string;
4888 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4889 {
4890 switch (r->reg_num)
4891 {
4892 case 0:
4893 i.seg[i.mem_operands] = &es;
4894 break;
4895 case 1:
4896 i.seg[i.mem_operands] = &cs;
4897 break;
4898 case 2:
4899 i.seg[i.mem_operands] = &ss;
4900 break;
4901 case 3:
4902 i.seg[i.mem_operands] = &ds;
4903 break;
4904 case 4:
4905 i.seg[i.mem_operands] = &fs;
4906 break;
4907 case 5:
4908 i.seg[i.mem_operands] = &gs;
4909 break;
4910 }
252b5132 4911
24eab124 4912 /* Skip the ':' and whitespace. */
252b5132
RH		 4913 ++op_string;
4914 if (is_space_char (*op_string))
24eab124 4915 ++op_string;
252b5132 4916
24eab124
AM		 4917 if (!is_digit_char (*op_string)
4918 && !is_identifier_char (*op_string)
4919 && *op_string != '('
4920 && *op_string != ABSOLUTE_PREFIX)
4921 {
4922 as_bad (_("bad memory operand `%s'"), op_string);
4923 return 0;
4924 }
47926f60 4925 /* Handle case of %es:*foo. */
24eab124
AM		 4926 if (*op_string == ABSOLUTE_PREFIX)
4927 {
4928 ++op_string;
4929 if (is_space_char (*op_string))
4930 ++op_string;
4931 i.types[this_operand] |= JumpAbsolute;
4932 }
4933 goto do_memory_reference;
4934 }
4935 if (*op_string)
4936 {
d0b47220 4937 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4938 return 0;
4939 }
4940 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4941 i.op[this_operand].regs = r;
24eab124
AM		 4942 i.reg_operands++;
4943 }
af6bdddf
AM		 4944 else if (*op_string == REGISTER_PREFIX)
4945 {
4946 as_bad (_("bad register name `%s'"), op_string);
4947 return 0;
4948 }
24eab124 4949 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4950 {
24eab124
AM		 4951 ++op_string;
4952 if (i.types[this_operand] & JumpAbsolute)
4953 {
d0b47220 4954 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4955 return 0;
4956 }
4957 if (!i386_immediate (op_string))
4958 return 0;
4959 }
4960 else if (is_digit_char (*op_string)
4961 || is_identifier_char (*op_string)
e5cb08ac 4962 || *op_string == '(')
24eab124 4963 {
47926f60 4964 /* This is a memory reference of some sort. */
af6bdddf 4965 char *base_string;
252b5132 4966
47926f60 4967 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4968 char *displacement_string_start;
4969 char *displacement_string_end;
252b5132 4970
24eab124 4971 do_memory_reference:
24eab124
AM		 4972 if ((i.mem_operands == 1
4973 && (current_templates->start->opcode_modifier & IsString) == 0)
4974 || i.mem_operands == 2)
4975 {
4976 as_bad (_("too many memory references for `%s'"),
4977 current_templates->start->name);
4978 return 0;
4979 }
252b5132 4980
24eab124
AM		 4981 /* Check for base index form. We detect the base index form by
4982 looking for an ')' at the end of the operand, searching
4983 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4984 after the '('. */
af6bdddf 4985 base_string = op_string + strlen (op_string);
c3332e24 4986
af6bdddf
AM		 4987 --base_string;
4988 if (is_space_char (*base_string))
4989 --base_string;
252b5132 4990
47926f60 4991 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4992 displacement_string_start = op_string;
4993 displacement_string_end = base_string + 1;
252b5132 4994
24eab124
AM		 4995 if (*base_string == ')')
4996 {
af6bdddf 4997 char *temp_string;
24eab124
AM		 4998 unsigned int parens_balanced = 1;
4999 /* We've already checked that the number of left & right ()'s are
47926f60 5000 equal, so this loop will not be infinite. */
24eab124
AM		 5001 do
5002 {
5003 base_string--;
5004 if (*base_string == ')')
5005 parens_balanced++;
5006 if (*base_string == '(')
5007 parens_balanced--;
5008 }
5009 while (parens_balanced);
c3332e24 5010
af6bdddf 5011 temp_string = base_string;
c3332e24 5012
24eab124 5013 /* Skip past '(' and whitespace. */
252b5132
RH		 5014 ++base_string;
5015 if (is_space_char (*base_string))
24eab124 5016 ++base_string;
252b5132 5017
af6bdddf 5018 if (*base_string == ','
4d1bb795 5019 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5020 {
af6bdddf 5021 displacement_string_end = temp_string;
252b5132 5022
af6bdddf 5023 i.types[this_operand] |= BaseIndex;
252b5132 5024
af6bdddf 5025 if (i.base_reg)
24eab124 5026 {
24eab124
AM		 5027 base_string = end_op;
5028 if (is_space_char (*base_string))
5029 ++base_string;
af6bdddf
AM		 5030 }
5031
5032 /* There may be an index reg or scale factor here. */
5033 if (*base_string == ',')
5034 {
5035 ++base_string;
5036 if (is_space_char (*base_string))
5037 ++base_string;
5038
4d1bb795 5039 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5040 {
af6bdddf 5041 base_string = end_op;
24eab124
AM		 5042 if (is_space_char (*base_string))
5043 ++base_string;
af6bdddf
AM		 5044 if (*base_string == ',')
5045 {
5046 ++base_string;
5047 if (is_space_char (*base_string))
5048 ++base_string;
5049 }
e5cb08ac 5050 else if (*base_string != ')')
af6bdddf
AM		 5051 {
5052 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5053 operand_string);
5054 return 0;
5055 }
24eab124 5056 }
af6bdddf 5057 else if (*base_string == REGISTER_PREFIX)
24eab124 5058 {
af6bdddf 5059 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5060 return 0;
5061 }
252b5132 5062
47926f60 5063 /* Check for scale factor. */
551c1ca1 5064 if (*base_string != ')')
af6bdddf 5065 {
551c1ca1
AM		 5066 char *end_scale = i386_scale (base_string);
5067
5068 if (!end_scale)
af6bdddf 5069 return 0;
24eab124 5070
551c1ca1 5071 base_string = end_scale;
af6bdddf
AM		 5072 if (is_space_char (*base_string))
5073 ++base_string;
5074 if (*base_string != ')')
5075 {
5076 as_bad (_("expecting `)' after scale factor in `%s'"),
5077 operand_string);
5078 return 0;
5079 }
5080 }
5081 else if (!i.index_reg)
24eab124 5082 {
af6bdddf
AM		 5083 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5084 *base_string);
24eab124
AM		 5085 return 0;
5086 }
5087 }
af6bdddf 5088 else if (*base_string != ')')
24eab124 5089 {
af6bdddf
AM		 5090 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5091 operand_string);
24eab124
AM		 5092 return 0;
5093 }
c3332e24 5094 }
af6bdddf 5095 else if (*base_string == REGISTER_PREFIX)
c3332e24 5096 {
af6bdddf 5097 as_bad (_("bad register name `%s'"), base_string);
24eab124 5098 return 0;
c3332e24 5099 }
24eab124
AM		 5100 }
5101
5102 /* If there's an expression beginning the operand, parse it,
5103 assuming displacement_string_start and
5104 displacement_string_end are meaningful. */
5105 if (displacement_string_start != displacement_string_end)
5106 {
5107 if (!i386_displacement (displacement_string_start,
5108 displacement_string_end))
5109 return 0;
5110 }
5111
5112 /* Special case for (%dx) while doing input/output op. */
5113 if (i.base_reg
5114 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5115 && i.index_reg == 0
5116 && i.log2_scale_factor == 0
5117 && i.seg[i.mem_operands] == 0
5118 && (i.types[this_operand] & Disp) == 0)
5119 {
5120 i.types[this_operand] = InOutPortReg;
5121 return 1;
5122 }
5123
eecb386c
AM		 5124 if (i386_index_check (operand_string) == 0)
5125 return 0;
24eab124
AM		 5126 i.mem_operands++;
5127 }
5128 else
ce8a8b2f
AM		 5129 {
5130 /* It's not a memory operand; argh! */
24eab124
AM		 5131 as_bad (_("invalid char %s beginning operand %d `%s'"),
5132 output_invalid (*op_string),
5133 this_operand + 1,
5134 op_string);
5135 return 0;
5136 }
47926f60 5137 return 1; /* Normal return. */
252b5132
RH		 5138}
5139\f
ee7fcc42
AM		 5140/* md_estimate_size_before_relax()
5141
5142 Called just before relax() for rs_machine_dependent frags. The x86
5143 assembler uses these frags to handle variable size jump
5144 instructions.
5145
5146 Any symbol that is now undefined will not become defined.
5147 Return the correct fr_subtype in the frag.
5148 Return the initial "guess for variable size of frag" to caller.
5149 The guess is actually the growth beyond the fixed part. Whatever
5150 we do to grow the fixed or variable part contributes to our
5151 returned value. */
5152
252b5132
RH		 5153int
5154md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5155 fragS *fragP;
5156 segT segment;
252b5132 5157{
252b5132 5158 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5159 check for un-relaxable symbols. On an ELF system, we can't relax
5160 an externally visible symbol, because it may be overridden by a
5161 shared library. */
5162 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5163#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5164 || (IS_ELF
31312f95
AM		 5165 && (S_IS_EXTERNAL (fragP->fr_symbol)
5166 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5167#endif
5168 )
252b5132 5169 {
b98ef147
AM		 5170 /* Symbol is undefined in this segment, or we need to keep a
5171 reloc so that weak symbols can be overridden. */
5172 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5173 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5174 unsigned char *opcode;
5175 int old_fr_fix;
f6af82bd 5176
ee7fcc42
AM		 5177 if (fragP->fr_var != NO_RELOC)
5178 reloc_type = fragP->fr_var;
b98ef147 5179 else if (size == 2)
f6af82bd
AM		 5180 reloc_type = BFD_RELOC_16_PCREL;
5181 else
5182 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5183
ee7fcc42
AM		 5184 old_fr_fix = fragP->fr_fix;
5185 opcode = (unsigned char *) fragP->fr_opcode;
5186
fddf5b5b 5187 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5188 {
fddf5b5b
AM		 5189 case UNCOND_JUMP:
5190 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5191 opcode[0] = 0xe9;
252b5132 5192 fragP->fr_fix += size;
062cd5e7
AS		 5193 fix_new (fragP, old_fr_fix, size,
5194 fragP->fr_symbol,
5195 fragP->fr_offset, 1,
5196 reloc_type);
252b5132
RH		 5197 break;
5198
fddf5b5b 5199 case COND_JUMP86:
412167cb
AM		 5200 if (size == 2
5201 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5202 {
5203 /* Negate the condition, and branch past an
5204 unconditional jump. */
5205 opcode[0] ^= 1;
5206 opcode[1] = 3;
5207 /* Insert an unconditional jump. */
5208 opcode[2] = 0xe9;
5209 /* We added two extra opcode bytes, and have a two byte
5210 offset. */
5211 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5212 fix_new (fragP, old_fr_fix + 2, 2,
5213 fragP->fr_symbol,
5214 fragP->fr_offset, 1,
5215 reloc_type);
fddf5b5b
AM		 5216 break;
5217 }
5218 /* Fall through. */
5219
5220 case COND_JUMP:
412167cb
AM		 5221 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5222 {
3e02c1cc
AM		 5223 fixS *fixP;
5224
412167cb 5225 fragP->fr_fix += 1;
3e02c1cc
AM		 5226 fixP = fix_new (fragP, old_fr_fix, 1,
5227 fragP->fr_symbol,
5228 fragP->fr_offset, 1,
5229 BFD_RELOC_8_PCREL);
5230 fixP->fx_signed = 1;
412167cb
AM		 5231 break;
5232 }
93c2a809 5233
24eab124 5234 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5235 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5236 opcode[1] = opcode[0] + 0x10;
f6af82bd 5237 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5238 /* We've added an opcode byte. */
5239 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5240 fix_new (fragP, old_fr_fix + 1, size,
5241 fragP->fr_symbol,
5242 fragP->fr_offset, 1,
5243 reloc_type);
252b5132 5244 break;
fddf5b5b
AM		 5245
5246 default:
5247 BAD_CASE (fragP->fr_subtype);
5248 break;
252b5132
RH		 5249 }
5250 frag_wane (fragP);
ee7fcc42 5251 return fragP->fr_fix - old_fr_fix;
252b5132 5252 }
93c2a809 5253
93c2a809
AM		 5254 /* Guess size depending on current relax state. Initially the relax
5255 state will correspond to a short jump and we return 1, because
5256 the variable part of the frag (the branch offset) is one byte
5257 long. However, we can relax a section more than once and in that
5258 case we must either set fr_subtype back to the unrelaxed state,
5259 or return the value for the appropriate branch. */
5260 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5261}
5262
47926f60
KH		 5263/* Called after relax() is finished.
5264
5265 In: Address of frag.
5266 fr_type == rs_machine_dependent.
5267 fr_subtype is what the address relaxed to.
5268
5269 Out: Any fixSs and constants are set up.
5270 Caller will turn frag into a ".space 0". */
5271
252b5132
RH		 5272void
5273md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5274 bfd *abfd ATTRIBUTE_UNUSED;
5275 segT sec ATTRIBUTE_UNUSED;
29b0f896 5276 fragS *fragP;
252b5132 5277{
29b0f896 5278 unsigned char *opcode;
252b5132 5279 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5280 offsetT target_address;
5281 offsetT opcode_address;
252b5132 5282 unsigned int extension = 0;
847f7ad4 5283 offsetT displacement_from_opcode_start;
252b5132
RH		 5284
5285 opcode = (unsigned char *) fragP->fr_opcode;
5286
47926f60 5287 /* Address we want to reach in file space. */
252b5132 5288 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5289
47926f60 5290 /* Address opcode resides at in file space. */
252b5132
RH		 5291 opcode_address = fragP->fr_address + fragP->fr_fix;
5292
47926f60 5293 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5294 displacement_from_opcode_start = target_address - opcode_address;
5295
fddf5b5b 5296 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5297 {
47926f60
KH		 5298 /* Don't have to change opcode. */
5299 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5300 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5301 }
5302 else
5303 {
5304 if (no_cond_jump_promotion
5305 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5306 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5307
fddf5b5b
AM		 5308 switch (fragP->fr_subtype)
5309 {
5310 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5311 extension = 4; /* 1 opcode + 4 displacement */
5312 opcode[0] = 0xe9;
5313 where_to_put_displacement = &opcode[1];
5314 break;
252b5132 5315
fddf5b5b
AM		 5316 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5317 extension = 2; /* 1 opcode + 2 displacement */
5318 opcode[0] = 0xe9;
5319 where_to_put_displacement = &opcode[1];
5320 break;
252b5132 5321
fddf5b5b
AM		 5322 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5323 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5324 extension = 5; /* 2 opcode + 4 displacement */
5325 opcode[1] = opcode[0] + 0x10;
5326 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5327 where_to_put_displacement = &opcode[2];
5328 break;
252b5132 5329
fddf5b5b
AM		 5330 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5331 extension = 3; /* 2 opcode + 2 displacement */
5332 opcode[1] = opcode[0] + 0x10;
5333 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5334 where_to_put_displacement = &opcode[2];
5335 break;
252b5132 5336
fddf5b5b
AM		 5337 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5338 extension = 4;
5339 opcode[0] ^= 1;
5340 opcode[1] = 3;
5341 opcode[2] = 0xe9;
5342 where_to_put_displacement = &opcode[3];
5343 break;
5344
5345 default:
5346 BAD_CASE (fragP->fr_subtype);
5347 break;
5348 }
252b5132 5349 }
fddf5b5b 5350
7b81dfbb
AJ		 5351 /* If size if less then four we are sure that the operand fits,
5352 but if it's 4, then it could be that the displacement is larger
5353 then -/+ 2GB. */
5354 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5355 && object_64bit
5356 && ((addressT) (displacement_from_opcode_start - extension
5357 + ((addressT) 1 << 31))
5358 > (((addressT) 2 << 31) - 1)))
5359 {
5360 as_bad_where (fragP->fr_file, fragP->fr_line,
5361 _("jump target out of range"));
5362 /* Make us emit 0. */
5363 displacement_from_opcode_start = extension;
5364 }
47926f60 5365 /* Now put displacement after opcode. */
252b5132
RH		 5366 md_number_to_chars ((char *) where_to_put_displacement,
5367 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5368 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5369 fragP->fr_fix += extension;
5370}
5371\f
47926f60
KH		 5372/* Size of byte displacement jmp. */
5373int md_short_jump_size = 2;
5374
5375/* Size of dword displacement jmp. */
5376int md_long_jump_size = 5;
252b5132 5377
252b5132
RH		 5378void
5379md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5380 char *ptr;
5381 addressT from_addr, to_addr;
ab9da554
ILT		 5382 fragS *frag ATTRIBUTE_UNUSED;
5383 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5384{
847f7ad4 5385 offsetT offset;
252b5132
RH		 5386
5387 offset = to_addr - (from_addr + 2);
47926f60
KH		 5388 /* Opcode for byte-disp jump. */
5389 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5390 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5391}
5392
5393void
5394md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5395 char *ptr;
5396 addressT from_addr, to_addr;
a38cf1db
AM		 5397 fragS *frag ATTRIBUTE_UNUSED;
5398 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5399{
847f7ad4 5400 offsetT offset;
252b5132 5401
a38cf1db
AM		 5402 offset = to_addr - (from_addr + 5);
5403 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5404 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5405}
5406\f
5407/* Apply a fixup (fixS) to segment data, once it has been determined
5408 by our caller that we have all the info we need to fix it up.
5409
5410 On the 386, immediates, displacements, and data pointers are all in
5411 the same (little-endian) format, so we don't need to care about which
5412 we are handling. */
5413
94f592af 5414void
55cf6793 5415md_apply_fix (fixP, valP, seg)
47926f60
KH		 5416 /* The fix we're to put in. */
5417 fixS *fixP;
47926f60 5418 /* Pointer to the value of the bits. */
c6682705 5419 valueT *valP;
47926f60
KH		 5420 /* Segment fix is from. */
5421 segT seg ATTRIBUTE_UNUSED;
252b5132 5422{
94f592af 5423 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5424 valueT value = *valP;
252b5132 5425
f86103b7 5426#if !defined (TE_Mach)
93382f6d
AM		 5427 if (fixP->fx_pcrel)
5428 {
5429 switch (fixP->fx_r_type)
5430 {
5865bb77
ILT		 5431 default:
5432 break;
5433
d6ab8113
JB		 5434 case BFD_RELOC_64:
5435 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5436 break;
93382f6d 5437 case BFD_RELOC_32:
ae8887b5 5438 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5439 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5440 break;
5441 case BFD_RELOC_16:
5442 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5443 break;
5444 case BFD_RELOC_8:
5445 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5446 break;
5447 }
5448 }
252b5132 5449
a161fe53 5450 if (fixP->fx_addsy != NULL
31312f95 5451 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5452 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5453 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5454 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5455 && !use_rela_relocations)
252b5132 5456 {
31312f95
AM		 5457 /* This is a hack. There should be a better way to handle this.
5458 This covers for the fact that bfd_install_relocation will
5459 subtract the current location (for partial_inplace, PC relative
5460 relocations); see more below. */
252b5132 5461#ifndef OBJ_AOUT
718ddfc0 5462 if (IS_ELF
252b5132
RH		 5463#ifdef TE_PE
5464 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5465#endif
5466 )
5467 value += fixP->fx_where + fixP->fx_frag->fr_address;
5468#endif
5469#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5470 if (IS_ELF)
252b5132 5471 {
6539b54b 5472 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5473
6539b54b 5474 if ((sym_seg == seg
2f66722d 5475 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5476 && sym_seg != absolute_section))
ae6063d4 5477 && !generic_force_reloc (fixP))
2f66722d
AM		 5478 {
5479 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5480 bfd_install_relocation subtracts them out again. I think
5481 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5482 it. FIXME. */
5483 value += fixP->fx_where + fixP->fx_frag->fr_address;
5484 }
252b5132
RH		 5485 }
5486#endif
5487#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5488 /* For some reason, the PE format does not store a
5489 section address offset for a PC relative symbol. */
5490 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5491 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5492 value += md_pcrel_from (fixP);
5493#endif
5494 }
5495
5496 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5497 and we must not disappoint it. */
252b5132 5498#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5499 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5500 switch (fixP->fx_r_type)
5501 {
5502 case BFD_RELOC_386_PLT32:
3e73aa7c 5503 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5504 /* Make the jump instruction point to the address of the operand. At
5505 runtime we merely add the offset to the actual PLT entry. */
5506 value = -4;
5507 break;
31312f95 5508
13ae64f3
JJ		 5509 case BFD_RELOC_386_TLS_GD:
5510 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5511 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5512 case BFD_RELOC_386_TLS_IE:
5513 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5514 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5515 case BFD_RELOC_X86_64_TLSGD:
5516 case BFD_RELOC_X86_64_TLSLD:
5517 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5518 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5519 value = 0; /* Fully resolved at runtime. No addend. */
5520 /* Fallthrough */
5521 case BFD_RELOC_386_TLS_LE:
5522 case BFD_RELOC_386_TLS_LDO_32:
5523 case BFD_RELOC_386_TLS_LE_32:
5524 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5525 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5526 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5527 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5528 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5529 break;
5530
67a4f2b7
AO		 5531 case BFD_RELOC_386_TLS_DESC_CALL:
5532 case BFD_RELOC_X86_64_TLSDESC_CALL:
5533 value = 0; /* Fully resolved at runtime. No addend. */
5534 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5535 fixP->fx_done = 0;
5536 return;
5537
00f7efb6
JJ		 5538 case BFD_RELOC_386_GOT32:
5539 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5540 value = 0; /* Fully resolved at runtime. No addend. */
5541 break;
47926f60
KH		 5542
5543 case BFD_RELOC_VTABLE_INHERIT:
5544 case BFD_RELOC_VTABLE_ENTRY:
5545 fixP->fx_done = 0;
94f592af 5546 return;
47926f60
KH		 5547
5548 default:
5549 break;
5550 }
5551#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5552 *valP = value;
f86103b7 5553#endif /* !defined (TE_Mach) */
3e73aa7c 5554
3e73aa7c 5555 /* Are we finished with this relocation now? */
c6682705 5556 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5557 fixP->fx_done = 1;
5558 else if (use_rela_relocations)
5559 {
5560 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5561 /* Remember value for tc_gen_reloc. */
5562 fixP->fx_addnumber = value;
3e73aa7c
JH		 5563 value = 0;
5564 }
f86103b7 5565
94f592af 5566 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5567}
252b5132 5568\f
252b5132
RH		 5569#define MAX_LITTLENUMS 6
5570
47926f60
KH		 5571/* Turn the string pointed to by litP into a floating point constant
5572 of type TYPE, and emit the appropriate bytes. The number of
5573 LITTLENUMS emitted is stored in *SIZEP. An error message is
5574 returned, or NULL on OK. */
5575
252b5132
RH		 5576char *
5577md_atof (type, litP, sizeP)
2ab9b79e 5578 int type;
252b5132
RH		 5579 char *litP;
5580 int *sizeP;
5581{
5582 int prec;
5583 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5584 LITTLENUM_TYPE *wordP;
5585 char *t;
5586
5587 switch (type)
5588 {
5589 case 'f':
5590 case 'F':
5591 prec = 2;
5592 break;
5593
5594 case 'd':
5595 case 'D':
5596 prec = 4;
5597 break;
5598
5599 case 'x':
5600 case 'X':
5601 prec = 5;
5602 break;
5603
5604 default:
5605 *sizeP = 0;
5606 return _("Bad call to md_atof ()");
5607 }
5608 t = atof_ieee (input_line_pointer, type, words);
5609 if (t)
5610 input_line_pointer = t;
5611
5612 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5613 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5614 the bigendian 386. */
5615 for (wordP = words + prec - 1; prec--;)
5616 {
5617 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5618 litP += sizeof (LITTLENUM_TYPE);
5619 }
5620 return 0;
5621}
5622\f
2d545b82 5623static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5624
252b5132 5625static char *
e3bb37b5 5626output_invalid (int c)
252b5132 5627{
3882b010 5628 if (ISPRINT (c))
f9f21a03
L		 5629 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5630 "'%c'", c);
252b5132 5631 else
f9f21a03 5632 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5633 "(0x%x)", (unsigned char) c);
252b5132
RH		 5634 return output_invalid_buf;
5635}
5636
af6bdddf 5637/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5638
5639static const reg_entry *
4d1bb795 5640parse_real_register (char *reg_string, char **end_op)
252b5132 5641{
af6bdddf
AM		 5642 char *s = reg_string;
5643 char *p;
252b5132
RH		 5644 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5645 const reg_entry *r;
5646
5647 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5648 if (*s == REGISTER_PREFIX)
5649 ++s;
5650
5651 if (is_space_char (*s))
5652 ++s;
5653
5654 p = reg_name_given;
af6bdddf 5655 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5656 {
5657 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5658 return (const reg_entry *) NULL;
5659 s++;
252b5132
RH		 5660 }
5661
6588847e
DN		 5662 /* For naked regs, make sure that we are not dealing with an identifier.
5663 This prevents confusing an identifier like `eax_var' with register
5664 `eax'. */
5665 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5666 return (const reg_entry *) NULL;
5667
af6bdddf 5668 *end_op = s;
252b5132
RH		 5669
5670 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5671
5f47d35b 5672 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5673 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5674 {
5f47d35b
AM		 5675 if (is_space_char (*s))
5676 ++s;
5677 if (*s == '(')
5678 {
af6bdddf 5679 ++s;
5f47d35b
AM		 5680 if (is_space_char (*s))
5681 ++s;
5682 if (*s >= '0' && *s <= '7')
5683 {
5684 r = &i386_float_regtab[*s - '0'];
af6bdddf 5685 ++s;
5f47d35b
AM		 5686 if (is_space_char (*s))
5687 ++s;
5688 if (*s == ')')
5689 {
5690 *end_op = s + 1;
5691 return r;
5692 }
5f47d35b 5693 }
47926f60 5694 /* We have "%st(" then garbage. */
5f47d35b
AM		 5695 return (const reg_entry *) NULL;
5696 }
5697 }
5698
1ae00879 5699 if (r != NULL
20f0a1fc 5700 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5701 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5702 && flag_code != CODE_64BIT)
20f0a1fc 5703 return (const reg_entry *) NULL;
1ae00879 5704
252b5132
RH		 5705 return r;
5706}
4d1bb795
JB		 5707
5708/* REG_STRING starts *before* REGISTER_PREFIX. */
5709
5710static const reg_entry *
5711parse_register (char *reg_string, char **end_op)
5712{
5713 const reg_entry *r;
5714
5715 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5716 r = parse_real_register (reg_string, end_op);
5717 else
5718 r = NULL;
5719 if (!r)
5720 {
5721 char *save = input_line_pointer;
5722 char c;
5723 symbolS *symbolP;
5724
5725 input_line_pointer = reg_string;
5726 c = get_symbol_end ();
5727 symbolP = symbol_find (reg_string);
5728 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5729 {
5730 const expressionS *e = symbol_get_value_expression (symbolP);
5731
5732 know (e->X_op == O_register);
5733 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5734 r = i386_regtab + e->X_add_number;
5735 *end_op = input_line_pointer;
5736 }
5737 *input_line_pointer = c;
5738 input_line_pointer = save;
5739 }
5740 return r;
5741}
5742
5743int
5744i386_parse_name (char *name, expressionS *e, char *nextcharP)
5745{
5746 const reg_entry *r;
5747 char *end = input_line_pointer;
5748
5749 *end = *nextcharP;
5750 r = parse_register (name, &input_line_pointer);
5751 if (r && end <= input_line_pointer)
5752 {
5753 *nextcharP = *input_line_pointer;
5754 *input_line_pointer = 0;
5755 e->X_op = O_register;
5756 e->X_add_number = r - i386_regtab;
5757 return 1;
5758 }
5759 input_line_pointer = end;
5760 *end = 0;
5761 return 0;
5762}
5763
5764void
5765md_operand (expressionS *e)
5766{
5767 if (*input_line_pointer == REGISTER_PREFIX)
5768 {
5769 char *end;
5770 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5771
5772 if (r)
5773 {
5774 e->X_op = O_register;
5775 e->X_add_number = r - i386_regtab;
5776 input_line_pointer = end;
5777 }
5778 }
5779}
5780
252b5132 5781\f
4cc782b5 5782#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5783const char *md_shortopts = "kVQ:sqn";
252b5132 5784#else
12b55ccc 5785const char *md_shortopts = "qn";
252b5132 5786#endif
6e0b89ee 5787
3e73aa7c 5788#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5789#define OPTION_64 (OPTION_MD_BASE + 1)
5790#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5791#define OPTION_MARCH (OPTION_MD_BASE + 3)
5792#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5793
99ad8390
NC		 5794struct option md_longopts[] =
5795{
3e73aa7c 5796 {"32", no_argument, NULL, OPTION_32},
99ad8390 5797#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5798 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5799#endif
b3b91714 5800 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5801 {"march", required_argument, NULL, OPTION_MARCH},
5802 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5803 {NULL, no_argument, NULL, 0}
5804};
5805size_t md_longopts_size = sizeof (md_longopts);
5806
5807int
9103f4f4 5808md_parse_option (int c, char *arg)
252b5132 5809{
9103f4f4
L		 5810 unsigned int i;
5811
252b5132
RH		 5812 switch (c)
5813 {
12b55ccc
L		 5814 case 'n':
5815 optimize_align_code = 0;
5816 break;
5817
a38cf1db
AM		 5818 case 'q':
5819 quiet_warnings = 1;
252b5132
RH		 5820 break;
5821
5822#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5823 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5824 should be emitted or not. FIXME: Not implemented. */
5825 case 'Q':
252b5132
RH		 5826 break;
5827
5828 /* -V: SVR4 argument to print version ID. */
5829 case 'V':
5830 print_version_id ();
5831 break;
5832
a38cf1db
AM		 5833 /* -k: Ignore for FreeBSD compatibility. */
5834 case 'k':
252b5132 5835 break;
4cc782b5
ILT		 5836
5837 case 's':
5838 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5839 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5840 break;
99ad8390
NC		 5841#endif
5842#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5843 case OPTION_64:
5844 {
5845 const char **list, **l;
5846
3e73aa7c
JH		 5847 list = bfd_target_list ();
5848 for (l = list; *l != NULL; l++)
8620418b 5849 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5850 || strcmp (*l, "coff-x86-64") == 0
5851 || strcmp (*l, "pe-x86-64") == 0
5852 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5853 {
5854 default_arch = "x86_64";
5855 break;
5856 }
3e73aa7c 5857 if (*l == NULL)
6e0b89ee 5858 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5859 free (list);
5860 }
5861 break;
5862#endif
252b5132 5863
6e0b89ee
AM		 5864 case OPTION_32:
5865 default_arch = "i386";
5866 break;
5867
b3b91714
AM		 5868 case OPTION_DIVIDE:
5869#ifdef SVR4_COMMENT_CHARS
5870 {
5871 char *n, *t;
5872 const char *s;
5873
5874 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5875 t = n;
5876 for (s = i386_comment_chars; *s != '\0'; s++)
5877 if (*s != '/')
5878 *t++ = *s;
5879 *t = '\0';
5880 i386_comment_chars = n;
5881 }
5882#endif
5883 break;
5884
9103f4f4
L		 5885 case OPTION_MARCH:
5886 if (*arg == '.')
5887 as_fatal (_("Invalid -march= option: `%s'"), arg);
5888 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5889 {
5890 if (strcmp (arg, cpu_arch [i].name) == 0)
5891 {
ccc9c027 5892 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5893 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5894 if (!cpu_arch_tune_set)
5895 {
5896 cpu_arch_tune = cpu_arch_isa;
5897 cpu_arch_tune_flags = cpu_arch_isa_flags;
5898 }
9103f4f4
L		 5899 break;
5900 }
5901 }
5902 if (i >= ARRAY_SIZE (cpu_arch))
5903 as_fatal (_("Invalid -march= option: `%s'"), arg);
5904 break;
5905
5906 case OPTION_MTUNE:
5907 if (*arg == '.')
5908 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5909 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5910 {
5911 if (strcmp (arg, cpu_arch [i].name) == 0)
5912 {
ccc9c027 5913 cpu_arch_tune_set = 1;
9103f4f4
L		 5914 cpu_arch_tune = cpu_arch [i].type;
5915 cpu_arch_tune_flags = cpu_arch[i].flags;
5916 break;
5917 }
5918 }
5919 if (i >= ARRAY_SIZE (cpu_arch))
5920 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5921 break;
5922
252b5132
RH		 5923 default:
5924 return 0;
5925 }
5926 return 1;
5927}
5928
5929void
5930md_show_usage (stream)
5931 FILE *stream;
5932{
4cc782b5
ILT		 5933#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5934 fprintf (stream, _("\
a38cf1db
AM		 5935 -Q ignored\n\
5936 -V print assembler version number\n\
b3b91714
AM		 5937 -k ignored\n"));
5938#endif
5939 fprintf (stream, _("\
12b55ccc 5940 -n Do not optimize code alignment\n\
b3b91714
AM		 5941 -q quieten some warnings\n"));
5942#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5943 fprintf (stream, _("\
a38cf1db 5944 -s ignored\n"));
b3b91714 5945#endif
751d281c
L		 5946#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5947 fprintf (stream, _("\
5948 --32/--64 generate 32bit/64bit code\n"));
5949#endif
b3b91714
AM		 5950#ifdef SVR4_COMMENT_CHARS
5951 fprintf (stream, _("\
5952 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5953#else
5954 fprintf (stream, _("\
b3b91714 5955 --divide ignored\n"));
4cc782b5 5956#endif
9103f4f4
L		 5957 fprintf (stream, _("\
5958 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5959 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 5960 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 5961
252b5132
RH		 5962}
5963
99ad8390
NC		 5964#if defined(TE_PEP)
5965const char *
5966x86_64_target_format (void)
5967{
5968 if (strcmp (default_arch, "x86_64") == 0)
5969 {
5970 set_code_flag (CODE_64BIT);
5971 return COFF_TARGET_FORMAT;
5972 }
5973 else if (strcmp (default_arch, "i386") == 0)
5974 {
5975 set_code_flag (CODE_32BIT);
5976 return "coff-i386";
5977 }
5978
5979 as_fatal (_("Unknown architecture"));
5980 return NULL;
5981}
5982#endif
5983
3e73aa7c
JH		 5984#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5985 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5986
5987/* Pick the target format to use. */
5988
47926f60 5989const char *
e3bb37b5 5990i386_target_format (void)
252b5132 5991{
3e73aa7c 5992 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 5993 {
5994 set_code_flag (CODE_64BIT);
5995 if (cpu_arch_isa_flags == 0)
d32cad65 5996 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 5997 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5998 |CpuSSE|CpuSSE2;
ccc9c027 5999 if (cpu_arch_tune_flags == 0)
d32cad65 6000 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6001 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6002 |CpuSSE|CpuSSE2;
9103f4f4 6003 }
3e73aa7c 6004 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6005 {
6006 set_code_flag (CODE_32BIT);
6007 if (cpu_arch_isa_flags == 0)
d32cad65 6008 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6009 if (cpu_arch_tune_flags == 0)
d32cad65 6010 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6011 }
3e73aa7c
JH		 6012 else
6013 as_fatal (_("Unknown architecture"));
252b5132
RH		 6014 switch (OUTPUT_FLAVOR)
6015 {
4c63da97
AM		 6016#ifdef OBJ_MAYBE_AOUT
6017 case bfd_target_aout_flavour:
47926f60 6018 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6019#endif
6020#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6021 case bfd_target_coff_flavour:
6022 return "coff-i386";
4c63da97 6023#endif
3e73aa7c 6024#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6025 case bfd_target_elf_flavour:
3e73aa7c 6026 {
e5cb08ac 6027 if (flag_code == CODE_64BIT)
4fa24527
JB		 6028 {
6029 object_64bit = 1;
6030 use_rela_relocations = 1;
6031 }
9d7cbccd 6032 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6033 }
4c63da97 6034#endif
252b5132
RH		 6035 default:
6036 abort ();
6037 return NULL;
6038 }
6039}
6040
47926f60 6041#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6042
6043#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6044void
6045i386_elf_emit_arch_note (void)
a847613f 6046{
718ddfc0 6047 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6048 {
6049 char *p;
6050 asection *seg = now_seg;
6051 subsegT subseg = now_subseg;
6052 Elf_Internal_Note i_note;
6053 Elf_External_Note e_note;
6054 asection *note_secp;
6055 int len;
6056
6057 /* Create the .note section. */
6058 note_secp = subseg_new (".note", 0);
6059 bfd_set_section_flags (stdoutput,
6060 note_secp,
6061 SEC_HAS_CONTENTS | SEC_READONLY);
6062
6063 /* Process the arch string. */
6064 len = strlen (cpu_arch_name);
6065
6066 i_note.namesz = len + 1;
6067 i_note.descsz = 0;
6068 i_note.type = NT_ARCH;
6069 p = frag_more (sizeof (e_note.namesz));
6070 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6071 p = frag_more (sizeof (e_note.descsz));
6072 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6073 p = frag_more (sizeof (e_note.type));
6074 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6075 p = frag_more (len + 1);
6076 strcpy (p, cpu_arch_name);
6077
6078 frag_align (2, 0, 0);
6079
6080 subseg_set (seg, subseg);
6081 }
6082}
6083#endif
252b5132 6084\f
252b5132
RH		 6085symbolS *
6086md_undefined_symbol (name)
6087 char *name;
6088{
18dc2407
ILT		 6089 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6090 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6091 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6092 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6093 {
6094 if (!GOT_symbol)
6095 {
6096 if (symbol_find (name))
6097 as_bad (_("GOT already in symbol table"));
6098 GOT_symbol = symbol_new (name, undefined_section,
6099 (valueT) 0, &zero_address_frag);
6100 };
6101 return GOT_symbol;
6102 }
252b5132
RH		 6103 return 0;
6104}
6105
6106/* Round up a section size to the appropriate boundary. */
47926f60 6107
252b5132
RH		 6108valueT
6109md_section_align (segment, size)
ab9da554 6110 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6111 valueT size;
6112{
4c63da97
AM		 6113#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6114 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6115 {
6116 /* For a.out, force the section size to be aligned. If we don't do
6117 this, BFD will align it for us, but it will not write out the
6118 final bytes of the section. This may be a bug in BFD, but it is
6119 easier to fix it here since that is how the other a.out targets
6120 work. */
6121 int align;
6122
6123 align = bfd_get_section_alignment (stdoutput, segment);
6124 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6125 }
252b5132
RH		 6126#endif
6127
6128 return size;
6129}
6130
6131/* On the i386, PC-relative offsets are relative to the start of the
6132 next instruction. That is, the address of the offset, plus its
6133 size, since the offset is always the last part of the insn. */
6134
6135long
e3bb37b5 6136md_pcrel_from (fixS *fixP)
252b5132
RH		 6137{
6138 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6139}
6140
6141#ifndef I386COFF
6142
6143static void
e3bb37b5 6144s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6145{
29b0f896 6146 int temp;
252b5132 6147
8a75718c
JB		 6148#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6149 if (IS_ELF)
6150 obj_elf_section_change_hook ();
6151#endif
252b5132
RH		 6152 temp = get_absolute_expression ();
6153 subseg_set (bss_section, (subsegT) temp);
6154 demand_empty_rest_of_line ();
6155}
6156
6157#endif
6158
252b5132 6159void
e3bb37b5 6160i386_validate_fix (fixS *fixp)
252b5132
RH		 6161{
6162 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6163 {
23df1078
JH		 6164 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6165 {
4fa24527 6166 if (!object_64bit)
23df1078
JH		 6167 abort ();
6168 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6169 }
6170 else
6171 {
4fa24527 6172 if (!object_64bit)
d6ab8113
JB		 6173 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6174 else
6175 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6176 }
252b5132
RH		 6177 fixp->fx_subsy = 0;
6178 }
6179}
6180
252b5132
RH		 6181arelent *
6182tc_gen_reloc (section, fixp)
ab9da554 6183 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6184 fixS *fixp;
6185{
6186 arelent *rel;
6187 bfd_reloc_code_real_type code;
6188
6189 switch (fixp->fx_r_type)
6190 {
3e73aa7c
JH		 6191 case BFD_RELOC_X86_64_PLT32:
6192 case BFD_RELOC_X86_64_GOT32:
6193 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6194 case BFD_RELOC_386_PLT32:
6195 case BFD_RELOC_386_GOT32:
6196 case BFD_RELOC_386_GOTOFF:
6197 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6198 case BFD_RELOC_386_TLS_GD:
6199 case BFD_RELOC_386_TLS_LDM:
6200 case BFD_RELOC_386_TLS_LDO_32:
6201 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6202 case BFD_RELOC_386_TLS_IE:
6203 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6204 case BFD_RELOC_386_TLS_LE_32:
6205 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6206 case BFD_RELOC_386_TLS_GOTDESC:
6207 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6208 case BFD_RELOC_X86_64_TLSGD:
6209 case BFD_RELOC_X86_64_TLSLD:
6210 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6211 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6212 case BFD_RELOC_X86_64_GOTTPOFF:
6213 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6214 case BFD_RELOC_X86_64_TPOFF64:
6215 case BFD_RELOC_X86_64_GOTOFF64:
6216 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6217 case BFD_RELOC_X86_64_GOT64:
6218 case BFD_RELOC_X86_64_GOTPCREL64:
6219 case BFD_RELOC_X86_64_GOTPC64:
6220 case BFD_RELOC_X86_64_GOTPLT64:
6221 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6222 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6223 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6224 case BFD_RELOC_RVA:
6225 case BFD_RELOC_VTABLE_ENTRY:
6226 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6227#ifdef TE_PE
6228 case BFD_RELOC_32_SECREL:
6229#endif
252b5132
RH		 6230 code = fixp->fx_r_type;
6231 break;
dbbaec26
L		 6232 case BFD_RELOC_X86_64_32S:
6233 if (!fixp->fx_pcrel)
6234 {
6235 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6236 code = fixp->fx_r_type;
6237 break;
6238 }
252b5132 6239 default:
93382f6d 6240 if (fixp->fx_pcrel)
252b5132 6241 {
93382f6d
AM		 6242 switch (fixp->fx_size)
6243 {
6244 default:
b091f402
AM		 6245 as_bad_where (fixp->fx_file, fixp->fx_line,
6246 _("can not do %d byte pc-relative relocation"),
6247 fixp->fx_size);
93382f6d
AM		 6248 code = BFD_RELOC_32_PCREL;
6249 break;
6250 case 1: code = BFD_RELOC_8_PCREL; break;
6251 case 2: code = BFD_RELOC_16_PCREL; break;
6252 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6253#ifdef BFD64
6254 case 8: code = BFD_RELOC_64_PCREL; break;
6255#endif
93382f6d
AM		 6256 }
6257 }
6258 else
6259 {
6260 switch (fixp->fx_size)
6261 {
6262 default:
b091f402
AM		 6263 as_bad_where (fixp->fx_file, fixp->fx_line,
6264 _("can not do %d byte relocation"),
6265 fixp->fx_size);
93382f6d
AM		 6266 code = BFD_RELOC_32;
6267 break;
6268 case 1: code = BFD_RELOC_8; break;
6269 case 2: code = BFD_RELOC_16; break;
6270 case 4: code = BFD_RELOC_32; break;
937149dd 6271#ifdef BFD64
3e73aa7c 6272 case 8: code = BFD_RELOC_64; break;
937149dd 6273#endif
93382f6d 6274 }
252b5132
RH		 6275 }
6276 break;
6277 }
252b5132 6278
d182319b
JB		 6279 if ((code == BFD_RELOC_32
6280 || code == BFD_RELOC_32_PCREL
6281 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6282 && GOT_symbol
6283 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6284 {
4fa24527 6285 if (!object_64bit)
d6ab8113
JB		 6286 code = BFD_RELOC_386_GOTPC;
6287 else
6288 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6289 }
7b81dfbb
AJ		 6290 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6291 && GOT_symbol
6292 && fixp->fx_addsy == GOT_symbol)
6293 {
6294 code = BFD_RELOC_X86_64_GOTPC64;
6295 }
252b5132
RH		 6296
6297 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6298 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6299 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6300
6301 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6302
3e73aa7c
JH		 6303 if (!use_rela_relocations)
6304 {
6305 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6306 vtable entry to be used in the relocation's section offset. */
6307 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6308 rel->address = fixp->fx_offset;
252b5132 6309
c6682705 6310 rel->addend = 0;
3e73aa7c
JH		 6311 }
6312 /* Use the rela in 64bit mode. */
252b5132 6313 else
3e73aa7c 6314 {
062cd5e7
AS		 6315 if (!fixp->fx_pcrel)
6316 rel->addend = fixp->fx_offset;
6317 else
6318 switch (code)
6319 {
6320 case BFD_RELOC_X86_64_PLT32:
6321 case BFD_RELOC_X86_64_GOT32:
6322 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6323 case BFD_RELOC_X86_64_TLSGD:
6324 case BFD_RELOC_X86_64_TLSLD:
6325 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6326 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6327 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6328 rel->addend = fixp->fx_offset - fixp->fx_size;
6329 break;
6330 default:
6331 rel->addend = (section->vma
6332 - fixp->fx_size
6333 + fixp->fx_addnumber
6334 + md_pcrel_from (fixp));
6335 break;
6336 }
3e73aa7c
JH		 6337 }
6338
252b5132
RH		 6339 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6340 if (rel->howto == NULL)
6341 {
6342 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6343 _("cannot represent relocation type %s"),
252b5132
RH		 6344 bfd_get_reloc_code_name (code));
6345 /* Set howto to a garbage value so that we can keep going. */
6346 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6347 assert (rel->howto != NULL);
6348 }
6349
6350 return rel;
6351}
6352
64a0c779
DN		 6353\f
6354/* Parse operands using Intel syntax. This implements a recursive descent
6355 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6356 Programmer's Guide.
6357
6358 FIXME: We do not recognize the full operand grammar defined in the MASM
6359 documentation. In particular, all the structure/union and
6360 high-level macro operands are missing.
6361
6362 Uppercase words are terminals, lower case words are non-terminals.
6363 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6364 bars '|' denote choices. Most grammar productions are implemented in
6365 functions called 'intel_<production>'.
6366
6367 Initial production is 'expr'.
6368
9306ca4a 6369 addOp + | -
64a0c779
DN		 6370
6371 alpha [a-zA-Z]
6372
9306ca4a
JB		 6373 binOp & | AND | \| | OR | ^ | XOR
6374
64a0c779
DN		 6375 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6376
6377 constant digits [[ radixOverride ]]
6378
9306ca4a 6379 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6380
6381 digits decdigit
b77a7acd
AJ		 6382 | digits decdigit
6383 | digits hexdigit
64a0c779
DN		 6384
6385 decdigit [0-9]
6386
9306ca4a
JB		 6387 e04 e04 addOp e05
6388 | e05
6389
6390 e05 e05 binOp e06
b77a7acd 6391 | e06
64a0c779
DN		 6392
6393 e06 e06 mulOp e09
b77a7acd 6394 | e09
64a0c779
DN		 6395
6396 e09 OFFSET e10
a724f0f4
JB		 6397 | SHORT e10
6398 | + e10
6399 | - e10
9306ca4a
JB		 6400 | ~ e10
6401 | NOT e10
64a0c779
DN		 6402 | e09 PTR e10
6403 | e09 : e10
6404 | e10
6405
6406 e10 e10 [ expr ]
b77a7acd 6407 | e11
64a0c779
DN		 6408
6409 e11 ( expr )
b77a7acd 6410 | [ expr ]
64a0c779
DN		 6411 | constant
6412 | dataType
6413 | id
6414 | $
6415 | register
6416
a724f0f4 6417 => expr expr cmpOp e04
9306ca4a 6418 | e04
64a0c779
DN		 6419
6420 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6421 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6422
6423 hexdigit a | b | c | d | e | f
b77a7acd 6424 | A | B | C | D | E | F
64a0c779
DN		 6425
6426 id alpha
b77a7acd 6427 | id alpha
64a0c779
DN		 6428 | id decdigit
6429
9306ca4a 6430 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6431
6432 quote " | '
6433
6434 register specialRegister
b77a7acd 6435 | gpRegister
64a0c779
DN		 6436 | byteRegister
6437
6438 segmentRegister CS | DS | ES | FS | GS | SS
6439
9306ca4a 6440 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6441 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6442 | TR3 | TR4 | TR5 | TR6 | TR7
6443
64a0c779
DN		 6444 We simplify the grammar in obvious places (e.g., register parsing is
6445 done by calling parse_register) and eliminate immediate left recursion
6446 to implement a recursive-descent parser.
6447
a724f0f4
JB		 6448 expr e04 expr'
6449
6450 expr' cmpOp e04 expr'
6451 | Empty
9306ca4a
JB		 6452
6453 e04 e05 e04'
6454
6455 e04' addOp e05 e04'
6456 | Empty
64a0c779
DN		 6457
6458 e05 e06 e05'
6459
9306ca4a 6460 e05' binOp e06 e05'
b77a7acd 6461 | Empty
64a0c779
DN		 6462
6463 e06 e09 e06'
6464
6465 e06' mulOp e09 e06'
b77a7acd 6466 | Empty
64a0c779
DN		 6467
6468 e09 OFFSET e10 e09'
a724f0f4
JB		 6469 | SHORT e10'
6470 | + e10'
6471 | - e10'
6472 | ~ e10'
6473 | NOT e10'
b77a7acd 6474 | e10 e09'
64a0c779
DN		 6475
6476 e09' PTR e10 e09'
b77a7acd 6477 | : e10 e09'
64a0c779
DN		 6478 | Empty
6479
6480 e10 e11 e10'
6481
6482 e10' [ expr ] e10'
b77a7acd 6483 | Empty
64a0c779
DN		 6484
6485 e11 ( expr )
b77a7acd 6486 | [ expr ]
64a0c779
DN		 6487 | BYTE
6488 | WORD
6489 | DWORD
9306ca4a 6490 | FWORD
64a0c779 6491 | QWORD
9306ca4a
JB		 6492 | TBYTE
6493 | OWORD
6494 | XMMWORD
64a0c779
DN		 6495 | .
6496 | $
6497 | register
6498 | id
6499 | constant */
6500
6501/* Parsing structure for the intel syntax parser. Used to implement the
6502 semantic actions for the operand grammar. */
6503struct intel_parser_s
6504 {
6505 char *op_string; /* The string being parsed. */
6506 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6507 int op_modifier; /* Operand modifier. */
64a0c779 6508 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6509 int in_offset; /* >=1 if parsing operand of offset. */
6510 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6511 const reg_entry *reg; /* Last register reference found. */
6512 char *disp; /* Displacement string being built. */
a724f0f4 6513 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6514 };
6515
6516static struct intel_parser_s intel_parser;
6517
6518/* Token structure for parsing intel syntax. */
6519struct intel_token
6520 {
6521 int code; /* Token code. */
6522 const reg_entry *reg; /* Register entry for register tokens. */
6523 char *str; /* String representation. */
6524 };
6525
6526static struct intel_token cur_token, prev_token;
6527
50705ef4
AM		 6528/* Token codes for the intel parser. Since T_SHORT is already used
6529 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6530#define T_NIL -1
6531#define T_CONST 1
6532#define T_REG 2
6533#define T_BYTE 3
6534#define T_WORD 4
9306ca4a
JB		 6535#define T_DWORD 5
6536#define T_FWORD 6
6537#define T_QWORD 7
6538#define T_TBYTE 8
6539#define T_XMMWORD 9
50705ef4 6540#undef T_SHORT
9306ca4a
JB		 6541#define T_SHORT 10
6542#define T_OFFSET 11
6543#define T_PTR 12
6544#define T_ID 13
6545#define T_SHL 14
6546#define T_SHR 15
64a0c779
DN		 6547
6548/* Prototypes for intel parser functions. */
e3bb37b5
L		 6549static int intel_match_token (int);
6550static void intel_putback_token (void);
6551static void intel_get_token (void);
6552static int intel_expr (void);
6553static int intel_e04 (void);
6554static int intel_e05 (void);
6555static int intel_e06 (void);
6556static int intel_e09 (void);
6557static int intel_e10 (void);
6558static int intel_e11 (void);
64a0c779 6559
64a0c779 6560static int
e3bb37b5 6561i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6562{
6563 int ret;
6564 char *p;
6565
a724f0f4
JB		 6566 p = intel_parser.op_string = xstrdup (operand_string);
6567 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6568
6569 for (;;)
64a0c779 6570 {
a724f0f4
JB		 6571 /* Initialize token holders. */
6572 cur_token.code = prev_token.code = T_NIL;
6573 cur_token.reg = prev_token.reg = NULL;
6574 cur_token.str = prev_token.str = NULL;
6575
6576 /* Initialize parser structure. */
6577 intel_parser.got_a_float = got_a_float;
6578 intel_parser.op_modifier = 0;
6579 intel_parser.is_mem = 0;
6580 intel_parser.in_offset = 0;
6581 intel_parser.in_bracket = 0;
6582 intel_parser.reg = NULL;
6583 intel_parser.disp[0] = '\0';
6584 intel_parser.next_operand = NULL;
6585
6586 /* Read the first token and start the parser. */
6587 intel_get_token ();
6588 ret = intel_expr ();
6589
6590 if (!ret)
6591 break;
6592
9306ca4a
JB		 6593 if (cur_token.code != T_NIL)
6594 {
6595 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6596 current_templates->start->name, cur_token.str);
6597 ret = 0;
6598 }
64a0c779
DN		 6599 /* If we found a memory reference, hand it over to i386_displacement
6600 to fill in the rest of the operand fields. */
9306ca4a 6601 else if (intel_parser.is_mem)
64a0c779
DN		 6602 {
6603 if ((i.mem_operands == 1
6604 && (current_templates->start->opcode_modifier & IsString) == 0)
6605 || i.mem_operands == 2)
6606 {
6607 as_bad (_("too many memory references for '%s'"),
6608 current_templates->start->name);
6609 ret = 0;
6610 }
6611 else
6612 {
6613 char *s = intel_parser.disp;
6614 i.mem_operands++;
6615
a724f0f4
JB		 6616 if (!quiet_warnings && intel_parser.is_mem < 0)
6617 /* See the comments in intel_bracket_expr. */
6618 as_warn (_("Treating `%s' as memory reference"), operand_string);
6619
64a0c779
DN		 6620 /* Add the displacement expression. */
6621 if (*s != '\0')
a4622f40
AM		 6622 ret = i386_displacement (s, s + strlen (s));
6623 if (ret)
a724f0f4
JB		 6624 {
6625 /* Swap base and index in 16-bit memory operands like
6626 [si+bx]. Since i386_index_check is also used in AT&T
6627 mode we have to do that here. */
6628 if (i.base_reg
6629 && i.index_reg
6630 && (i.base_reg->reg_type & Reg16)
6631 && (i.index_reg->reg_type & Reg16)
6632 && i.base_reg->reg_num >= 6
6633 && i.index_reg->reg_num < 6)
6634 {
6635 const reg_entry *base = i.index_reg;
6636
6637 i.index_reg = i.base_reg;
6638 i.base_reg = base;
6639 }
6640 ret = i386_index_check (operand_string);
6641 }
64a0c779
DN		 6642 }
6643 }
6644
6645 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6646 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6647 || intel_parser.reg == NULL)
6648 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6649
6650 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6651 ret = 0;
6652 if (!ret || !intel_parser.next_operand)
6653 break;
6654 intel_parser.op_string = intel_parser.next_operand;
6655 this_operand = i.operands++;
64a0c779
DN		 6656 }
6657
6658 free (p);
6659 free (intel_parser.disp);
6660
6661 return ret;
6662}
6663
a724f0f4
JB		 6664#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6665
6666/* expr e04 expr'
6667
6668 expr' cmpOp e04 expr'
6669 | Empty */
64a0c779 6670static int
e3bb37b5 6671intel_expr (void)
64a0c779 6672{
a724f0f4
JB		 6673 /* XXX Implement the comparison operators. */
6674 return intel_e04 ();
9306ca4a
JB		 6675}
6676
a724f0f4 6677/* e04 e05 e04'
9306ca4a 6678
a724f0f4 6679 e04' addOp e05 e04'
9306ca4a
JB		 6680 | Empty */
6681static int
e3bb37b5 6682intel_e04 (void)
9306ca4a 6683{
a724f0f4 6684 int nregs = -1;
9306ca4a 6685
a724f0f4 6686 for (;;)
9306ca4a 6687 {
a724f0f4
JB		 6688 if (!intel_e05())
6689 return 0;
9306ca4a 6690
a724f0f4
JB		 6691 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6692 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6693
a724f0f4
JB		 6694 if (cur_token.code == '+')
6695 nregs = -1;
6696 else if (cur_token.code == '-')
6697 nregs = NUM_ADDRESS_REGS;
6698 else
6699 return 1;
64a0c779 6700
a724f0f4
JB		 6701 strcat (intel_parser.disp, cur_token.str);
6702 intel_match_token (cur_token.code);
6703 }
64a0c779
DN		 6704}
6705
64a0c779
DN		 6706/* e05 e06 e05'
6707
9306ca4a 6708 e05' binOp e06 e05'
64a0c779
DN		 6709 | Empty */
6710static int
e3bb37b5 6711intel_e05 (void)
64a0c779 6712{
a724f0f4 6713 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6714
a724f0f4 6715 for (;;)
64a0c779 6716 {
a724f0f4
JB		 6717 if (!intel_e06())
6718 return 0;
6719
6720 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6721 {
6722 char str[2];
6723
6724 str[0] = cur_token.code;
6725 str[1] = 0;
6726 strcat (intel_parser.disp, str);
6727 }
6728 else
6729 break;
9306ca4a 6730
64a0c779
DN		 6731 intel_match_token (cur_token.code);
6732
a724f0f4
JB		 6733 if (nregs < 0)
6734 nregs = ~nregs;
64a0c779 6735 }
a724f0f4
JB		 6736 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6737 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6738 return 1;
4a1805b1 6739}
64a0c779
DN		 6740
6741/* e06 e09 e06'
6742
6743 e06' mulOp e09 e06'
b77a7acd 6744 | Empty */
64a0c779 6745static int
e3bb37b5 6746intel_e06 (void)
64a0c779 6747{
a724f0f4 6748 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6749
a724f0f4 6750 for (;;)
64a0c779 6751 {
a724f0f4
JB		 6752 if (!intel_e09())
6753 return 0;
9306ca4a 6754
a724f0f4
JB		 6755 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6756 {
6757 char str[2];
9306ca4a 6758
a724f0f4
JB		 6759 str[0] = cur_token.code;
6760 str[1] = 0;
6761 strcat (intel_parser.disp, str);
6762 }
6763 else if (cur_token.code == T_SHL)
6764 strcat (intel_parser.disp, "<<");
6765 else if (cur_token.code == T_SHR)
6766 strcat (intel_parser.disp, ">>");
6767 else
6768 break;
9306ca4a 6769
64e74474 6770 intel_match_token (cur_token.code);
64a0c779 6771
a724f0f4
JB		 6772 if (nregs < 0)
6773 nregs = ~nregs;
64a0c779 6774 }
a724f0f4
JB		 6775 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6776 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6777 return 1;
64a0c779
DN		 6778}
6779
a724f0f4
JB		 6780/* e09 OFFSET e09
6781 | SHORT e09
6782 | + e09
6783 | - e09
6784 | ~ e09
6785 | NOT e09
9306ca4a
JB		 6786 | e10 e09'
6787
64a0c779 6788 e09' PTR e10 e09'
b77a7acd 6789 | : e10 e09'
64a0c779
DN		 6790 | Empty */
6791static int
e3bb37b5 6792intel_e09 (void)
64a0c779 6793{
a724f0f4
JB		 6794 int nregs = ~NUM_ADDRESS_REGS;
6795 int in_offset = 0;
6796
6797 for (;;)
64a0c779 6798 {
a724f0f4
JB		 6799 /* Don't consume constants here. */
6800 if (cur_token.code == '+' || cur_token.code == '-')
6801 {
6802 /* Need to look one token ahead - if the next token
6803 is a constant, the current token is its sign. */
6804 int next_code;
6805
6806 intel_match_token (cur_token.code);
6807 next_code = cur_token.code;
6808 intel_putback_token ();
6809 if (next_code == T_CONST)
6810 break;
6811 }
6812
6813 /* e09 OFFSET e09 */
6814 if (cur_token.code == T_OFFSET)
6815 {
6816 if (!in_offset++)
6817 ++intel_parser.in_offset;
6818 }
6819
6820 /* e09 SHORT e09 */
6821 else if (cur_token.code == T_SHORT)
6822 intel_parser.op_modifier |= 1 << T_SHORT;
6823
6824 /* e09 + e09 */
6825 else if (cur_token.code == '+')
6826 strcat (intel_parser.disp, "+");
6827
6828 /* e09 - e09
6829 | ~ e09
6830 | NOT e09 */
6831 else if (cur_token.code == '-' || cur_token.code == '~')
6832 {
6833 char str[2];
64a0c779 6834
a724f0f4
JB		 6835 if (nregs < 0)
6836 nregs = ~nregs;
6837 str[0] = cur_token.code;
6838 str[1] = 0;
6839 strcat (intel_parser.disp, str);
6840 }
6841
6842 /* e09 e10 e09' */
6843 else
6844 break;
6845
6846 intel_match_token (cur_token.code);
64a0c779
DN		 6847 }
6848
a724f0f4 6849 for (;;)
9306ca4a 6850 {
a724f0f4
JB		 6851 if (!intel_e10 ())
6852 return 0;
9306ca4a 6853
a724f0f4
JB		 6854 /* e09' PTR e10 e09' */
6855 if (cur_token.code == T_PTR)
6856 {
6857 char suffix;
9306ca4a 6858
a724f0f4
JB		 6859 if (prev_token.code == T_BYTE)
6860 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6861
a724f0f4
JB		 6862 else if (prev_token.code == T_WORD)
6863 {
6864 if (current_templates->start->name[0] == 'l'
6865 && current_templates->start->name[2] == 's'
6866 && current_templates->start->name[3] == 0)
6867 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6868 else if (intel_parser.got_a_float == 2) /* "fi..." */
6869 suffix = SHORT_MNEM_SUFFIX;
6870 else
6871 suffix = WORD_MNEM_SUFFIX;
6872 }
64a0c779 6873
a724f0f4
JB		 6874 else if (prev_token.code == T_DWORD)
6875 {
6876 if (current_templates->start->name[0] == 'l'
6877 && current_templates->start->name[2] == 's'
6878 && current_templates->start->name[3] == 0)
6879 suffix = WORD_MNEM_SUFFIX;
6880 else if (flag_code == CODE_16BIT
6881 && (current_templates->start->opcode_modifier
435acd52 6882 & (Jump | JumpDword)))
a724f0f4
JB		 6883 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6884 else if (intel_parser.got_a_float == 1) /* "f..." */
6885 suffix = SHORT_MNEM_SUFFIX;
6886 else
6887 suffix = LONG_MNEM_SUFFIX;
6888 }
9306ca4a 6889
a724f0f4
JB		 6890 else if (prev_token.code == T_FWORD)
6891 {
6892 if (current_templates->start->name[0] == 'l'
6893 && current_templates->start->name[2] == 's'
6894 && current_templates->start->name[3] == 0)
6895 suffix = LONG_MNEM_SUFFIX;
6896 else if (!intel_parser.got_a_float)
6897 {
6898 if (flag_code == CODE_16BIT)
6899 add_prefix (DATA_PREFIX_OPCODE);
6900 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6901 }
6902 else
6903 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6904 }
64a0c779 6905
a724f0f4
JB		 6906 else if (prev_token.code == T_QWORD)
6907 {
6908 if (intel_parser.got_a_float == 1) /* "f..." */
6909 suffix = LONG_MNEM_SUFFIX;
6910 else
6911 suffix = QWORD_MNEM_SUFFIX;
6912 }
64a0c779 6913
a724f0f4
JB		 6914 else if (prev_token.code == T_TBYTE)
6915 {
6916 if (intel_parser.got_a_float == 1)
6917 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6918 else
6919 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6920 }
9306ca4a 6921
a724f0f4 6922 else if (prev_token.code == T_XMMWORD)
9306ca4a 6923 {
a724f0f4
JB		 6924 /* XXX ignored for now, but accepted since gcc uses it */
6925 suffix = 0;
9306ca4a 6926 }
64a0c779 6927
f16b83df 6928 else
a724f0f4
JB		 6929 {
6930 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6931 return 0;
6932 }
6933
435acd52
JB		 6934 /* Operands for jump/call using 'ptr' notation denote absolute
6935 addresses. */
6936 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6937 i.types[this_operand] |= JumpAbsolute;
6938
a724f0f4
JB		 6939 if (current_templates->start->base_opcode == 0x8d /* lea */)
6940 ;
6941 else if (!i.suffix)
6942 i.suffix = suffix;
6943 else if (i.suffix != suffix)
6944 {
6945 as_bad (_("Conflicting operand modifiers"));
6946 return 0;
6947 }
64a0c779 6948
9306ca4a
JB		 6949 }
6950
a724f0f4
JB		 6951 /* e09' : e10 e09' */
6952 else if (cur_token.code == ':')
9306ca4a 6953 {
a724f0f4
JB		 6954 if (prev_token.code != T_REG)
6955 {
6956 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6957 segment/group identifier (which we don't have), using comma
6958 as the operand separator there is even less consistent, since
6959 there all branches only have a single operand. */
6960 if (this_operand != 0
6961 || intel_parser.in_offset
6962 || intel_parser.in_bracket
6963 || (!(current_templates->start->opcode_modifier
6964 & (Jump|JumpDword|JumpInterSegment))
6965 && !(current_templates->start->operand_types[0]
6966 & JumpAbsolute)))
6967 return intel_match_token (T_NIL);
6968 /* Remember the start of the 2nd operand and terminate 1st
6969 operand here.
6970 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6971 another expression), but it gets at least the simplest case
6972 (a plain number or symbol on the left side) right. */
6973 intel_parser.next_operand = intel_parser.op_string;
6974 *--intel_parser.op_string = '\0';
6975 return intel_match_token (':');
6976 }
9306ca4a 6977 }
64a0c779 6978
a724f0f4 6979 /* e09' Empty */
64a0c779 6980 else
a724f0f4 6981 break;
64a0c779 6982
a724f0f4
JB		 6983 intel_match_token (cur_token.code);
6984
6985 }
6986
6987 if (in_offset)
6988 {
6989 --intel_parser.in_offset;
6990 if (nregs < 0)
6991 nregs = ~nregs;
6992 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6993 {
a724f0f4 6994 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6995 return 0;
6996 }
a724f0f4
JB		 6997 intel_parser.op_modifier |= 1 << T_OFFSET;
6998 }
9306ca4a 6999
a724f0f4
JB		 7000 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7001 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7002 return 1;
7003}
64a0c779 7004
a724f0f4 7005static int
e3bb37b5 7006intel_bracket_expr (void)
a724f0f4
JB		 7007{
7008 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7009 const char *start = intel_parser.op_string;
7010 int len;
7011
7012 if (i.op[this_operand].regs)
7013 return intel_match_token (T_NIL);
7014
7015 intel_match_token ('[');
7016
7017 /* Mark as a memory operand only if it's not already known to be an
7018 offset expression. If it's an offset expression, we need to keep
7019 the brace in. */
7020 if (!intel_parser.in_offset)
7021 {
7022 ++intel_parser.in_bracket;
435acd52
JB		 7023
7024 /* Operands for jump/call inside brackets denote absolute addresses. */
7025 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7026 i.types[this_operand] |= JumpAbsolute;
7027
a724f0f4
JB		 7028 /* Unfortunately gas always diverged from MASM in a respect that can't
7029 be easily fixed without risking to break code sequences likely to be
7030 encountered (the testsuite even check for this): MASM doesn't consider
7031 an expression inside brackets unconditionally as a memory reference.
7032 When that is e.g. a constant, an offset expression, or the sum of the
7033 two, this is still taken as a constant load. gas, however, always
7034 treated these as memory references. As a compromise, we'll try to make
7035 offset expressions inside brackets work the MASM way (since that's
7036 less likely to be found in real world code), but make constants alone
7037 continue to work the traditional gas way. In either case, issue a
7038 warning. */
7039 intel_parser.op_modifier &= ~was_offset;
64a0c779 7040 }
a724f0f4 7041 else
64e74474 7042 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7043
7044 /* Add a '+' to the displacement string if necessary. */
7045 if (*intel_parser.disp != '\0'
7046 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7047 strcat (intel_parser.disp, "+");
64a0c779 7048
a724f0f4
JB		 7049 if (intel_expr ()
7050 && (len = intel_parser.op_string - start - 1,
7051 intel_match_token (']')))
64a0c779 7052 {
a724f0f4
JB		 7053 /* Preserve brackets when the operand is an offset expression. */
7054 if (intel_parser.in_offset)
7055 strcat (intel_parser.disp, "]");
7056 else
7057 {
7058 --intel_parser.in_bracket;
7059 if (i.base_reg || i.index_reg)
7060 intel_parser.is_mem = 1;
7061 if (!intel_parser.is_mem)
7062 {
7063 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7064 /* Defer the warning until all of the operand was parsed. */
7065 intel_parser.is_mem = -1;
7066 else if (!quiet_warnings)
7067 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7068 }
7069 }
7070 intel_parser.op_modifier |= was_offset;
64a0c779 7071
a724f0f4 7072 return 1;
64a0c779 7073 }
a724f0f4 7074 return 0;
64a0c779
DN		 7075}
7076
7077/* e10 e11 e10'
7078
7079 e10' [ expr ] e10'
b77a7acd 7080 | Empty */
64a0c779 7081static int
e3bb37b5 7082intel_e10 (void)
64a0c779 7083{
a724f0f4
JB		 7084 if (!intel_e11 ())
7085 return 0;
64a0c779 7086
a724f0f4 7087 while (cur_token.code == '[')
64a0c779 7088 {
a724f0f4 7089 if (!intel_bracket_expr ())
21d6c4af 7090 return 0;
64a0c779
DN		 7091 }
7092
a724f0f4 7093 return 1;
64a0c779
DN		 7094}
7095
64a0c779 7096/* e11 ( expr )
b77a7acd 7097 | [ expr ]
64a0c779
DN		 7098 | BYTE
7099 | WORD
7100 | DWORD
9306ca4a 7101 | FWORD
64a0c779 7102 | QWORD
9306ca4a
JB		 7103 | TBYTE
7104 | OWORD
7105 | XMMWORD
4a1805b1 7106 | $
64a0c779
DN		 7107 | .
7108 | register
7109 | id
7110 | constant */
7111static int
e3bb37b5 7112intel_e11 (void)
64a0c779 7113{
a724f0f4 7114 switch (cur_token.code)
64a0c779 7115 {
a724f0f4
JB		 7116 /* e11 ( expr ) */
7117 case '(':
64a0c779
DN		 7118 intel_match_token ('(');
7119 strcat (intel_parser.disp, "(");
7120
7121 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7122 {
7123 strcat (intel_parser.disp, ")");
7124 return 1;
7125 }
a724f0f4 7126 return 0;
4a1805b1 7127
a724f0f4
JB		 7128 /* e11 [ expr ] */
7129 case '[':
a724f0f4 7130 return intel_bracket_expr ();
64a0c779 7131
a724f0f4
JB		 7132 /* e11 $
7133 | . */
7134 case '.':
64a0c779
DN		 7135 strcat (intel_parser.disp, cur_token.str);
7136 intel_match_token (cur_token.code);
21d6c4af
DN		 7137
7138 /* Mark as a memory operand only if it's not already known to be an
7139 offset expression. */
a724f0f4 7140 if (!intel_parser.in_offset)
21d6c4af 7141 intel_parser.is_mem = 1;
64a0c779
DN		 7142
7143 return 1;
64a0c779 7144
a724f0f4
JB		 7145 /* e11 register */
7146 case T_REG:
7147 {
7148 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7149
a724f0f4 7150 intel_match_token (T_REG);
64a0c779 7151
a724f0f4
JB		 7152 /* Check for segment change. */
7153 if (cur_token.code == ':')
7154 {
7155 if (!(reg->reg_type & (SReg2 | SReg3)))
7156 {
7157 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7158 return 0;
7159 }
7160 else if (i.seg[i.mem_operands])
7161 as_warn (_("Extra segment override ignored"));
7162 else
7163 {
7164 if (!intel_parser.in_offset)
7165 intel_parser.is_mem = 1;
7166 switch (reg->reg_num)
7167 {
7168 case 0:
7169 i.seg[i.mem_operands] = &es;
7170 break;
7171 case 1:
7172 i.seg[i.mem_operands] = &cs;
7173 break;
7174 case 2:
7175 i.seg[i.mem_operands] = &ss;
7176 break;
7177 case 3:
7178 i.seg[i.mem_operands] = &ds;
7179 break;
7180 case 4:
7181 i.seg[i.mem_operands] = &fs;
7182 break;
7183 case 5:
7184 i.seg[i.mem_operands] = &gs;
7185 break;
7186 }
7187 }
7188 }
64a0c779 7189
a724f0f4
JB		 7190 /* Not a segment register. Check for register scaling. */
7191 else if (cur_token.code == '*')
7192 {
7193 if (!intel_parser.in_bracket)
7194 {
7195 as_bad (_("Register scaling only allowed in memory operands"));
7196 return 0;
7197 }
64a0c779 7198
a724f0f4
JB		 7199 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7200 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7201 else if (i.index_reg)
7202 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7203
a724f0f4
JB		 7204 /* What follows must be a valid scale. */
7205 intel_match_token ('*');
7206 i.index_reg = reg;
7207 i.types[this_operand] |= BaseIndex;
64a0c779 7208
a724f0f4
JB		 7209 /* Set the scale after setting the register (otherwise,
7210 i386_scale will complain) */
7211 if (cur_token.code == '+' || cur_token.code == '-')
7212 {
7213 char *str, sign = cur_token.code;
7214 intel_match_token (cur_token.code);
7215 if (cur_token.code != T_CONST)
7216 {
7217 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7218 cur_token.str);
7219 return 0;
7220 }
7221 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7222 strcpy (str + 1, cur_token.str);
7223 *str = sign;
7224 if (!i386_scale (str))
7225 return 0;
7226 free (str);
7227 }
7228 else if (!i386_scale (cur_token.str))
64a0c779 7229 return 0;
a724f0f4
JB		 7230 intel_match_token (cur_token.code);
7231 }
64a0c779 7232
a724f0f4
JB		 7233 /* No scaling. If this is a memory operand, the register is either a
7234 base register (first occurrence) or an index register (second
7235 occurrence). */
7b0441f6 7236 else if (intel_parser.in_bracket)
a724f0f4 7237 {
64a0c779 7238
a724f0f4
JB		 7239 if (!i.base_reg)
7240 i.base_reg = reg;
7241 else if (!i.index_reg)
7242 i.index_reg = reg;
7243 else
7244 {
7245 as_bad (_("Too many register references in memory operand"));
7246 return 0;
7247 }
64a0c779 7248
a724f0f4
JB		 7249 i.types[this_operand] |= BaseIndex;
7250 }
4a1805b1 7251
4d1bb795
JB		 7252 /* It's neither base nor index. */
7253 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7254 {
7255 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7256 i.op[this_operand].regs = reg;
7257 i.reg_operands++;
7258 }
7259 else
7260 {
7261 as_bad (_("Invalid use of register"));
7262 return 0;
7263 }
64a0c779 7264
a724f0f4
JB		 7265 /* Since registers are not part of the displacement string (except
7266 when we're parsing offset operands), we may need to remove any
7267 preceding '+' from the displacement string. */
7268 if (*intel_parser.disp != '\0'
7269 && !intel_parser.in_offset)
7270 {
7271 char *s = intel_parser.disp;
7272 s += strlen (s) - 1;
7273 if (*s == '+')
7274 *s = '\0';
7275 }
4a1805b1 7276
a724f0f4
JB		 7277 return 1;
7278 }
7279
7280 /* e11 BYTE
7281 | WORD
7282 | DWORD
7283 | FWORD
7284 | QWORD
7285 | TBYTE
7286 | OWORD
7287 | XMMWORD */
7288 case T_BYTE:
7289 case T_WORD:
7290 case T_DWORD:
7291 case T_FWORD:
7292 case T_QWORD:
7293 case T_TBYTE:
7294 case T_XMMWORD:
7295 intel_match_token (cur_token.code);
64a0c779 7296
a724f0f4
JB		 7297 if (cur_token.code == T_PTR)
7298 return 1;
7299
7300 /* It must have been an identifier. */
7301 intel_putback_token ();
7302 cur_token.code = T_ID;
7303 /* FALLTHRU */
7304
7305 /* e11 id
7306 | constant */
7307 case T_ID:
7308 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7309 {
7310 symbolS *symbolP;
7311
a724f0f4
JB		 7312 /* The identifier represents a memory reference only if it's not
7313 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7314 symbolP = symbol_find(cur_token.str);
7315 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7316 intel_parser.is_mem = 1;
7317 }
a724f0f4 7318 /* FALLTHRU */
64a0c779 7319
a724f0f4
JB		 7320 case T_CONST:
7321 case '-':
7322 case '+':
7323 {
7324 char *save_str, sign = 0;
64a0c779 7325
a724f0f4
JB		 7326 /* Allow constants that start with `+' or `-'. */
7327 if (cur_token.code == '-' || cur_token.code == '+')
7328 {
7329 sign = cur_token.code;
7330 intel_match_token (cur_token.code);
7331 if (cur_token.code != T_CONST)
7332 {
7333 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7334 cur_token.str);
7335 return 0;
7336 }
7337 }
64a0c779 7338
a724f0f4
JB		 7339 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7340 strcpy (save_str + !!sign, cur_token.str);
7341 if (sign)
7342 *save_str = sign;
64a0c779 7343
a724f0f4
JB		 7344 /* Get the next token to check for register scaling. */
7345 intel_match_token (cur_token.code);
64a0c779 7346
a724f0f4
JB		 7347 /* Check if this constant is a scaling factor for an index register. */
7348 if (cur_token.code == '*')
7349 {
7350 if (intel_match_token ('*') && cur_token.code == T_REG)
7351 {
7352 const reg_entry *reg = cur_token.reg;
7353
7354 if (!intel_parser.in_bracket)
7355 {
7356 as_bad (_("Register scaling only allowed in memory operands"));
7357 return 0;
7358 }
7359
7360 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7361 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7362 else if (i.index_reg)
7363 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7364
7365 /* The constant is followed by `* reg', so it must be
7366 a valid scale. */
7367 i.index_reg = reg;
7368 i.types[this_operand] |= BaseIndex;
7369
7370 /* Set the scale after setting the register (otherwise,
7371 i386_scale will complain) */
7372 if (!i386_scale (save_str))
64a0c779 7373 return 0;
a724f0f4
JB		 7374 intel_match_token (T_REG);
7375
7376 /* Since registers are not part of the displacement
7377 string, we may need to remove any preceding '+' from
7378 the displacement string. */
7379 if (*intel_parser.disp != '\0')
7380 {
7381 char *s = intel_parser.disp;
7382 s += strlen (s) - 1;
7383 if (*s == '+')
7384 *s = '\0';
7385 }
7386
7387 free (save_str);
7388
7389 return 1;
7390 }
64a0c779 7391
a724f0f4
JB		 7392 /* The constant was not used for register scaling. Since we have
7393 already consumed the token following `*' we now need to put it
7394 back in the stream. */
64a0c779 7395 intel_putback_token ();
a724f0f4 7396 }
64a0c779 7397
a724f0f4
JB		 7398 /* Add the constant to the displacement string. */
7399 strcat (intel_parser.disp, save_str);
7400 free (save_str);
64a0c779 7401
a724f0f4
JB		 7402 return 1;
7403 }
64a0c779
DN		 7404 }
7405
64a0c779
DN		 7406 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7407 return 0;
7408}
7409
64a0c779
DN		 7410/* Match the given token against cur_token. If they match, read the next
7411 token from the operand string. */
7412static int
e3bb37b5 7413intel_match_token (int code)
64a0c779
DN		 7414{
7415 if (cur_token.code == code)
7416 {
7417 intel_get_token ();
7418 return 1;
7419 }
7420 else
7421 {
0477af35 7422 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7423 return 0;
7424 }
7425}
7426
64a0c779
DN		 7427/* Read a new token from intel_parser.op_string and store it in cur_token. */
7428static void
e3bb37b5 7429intel_get_token (void)
64a0c779
DN		 7430{
7431 char *end_op;
7432 const reg_entry *reg;
7433 struct intel_token new_token;
7434
7435 new_token.code = T_NIL;
7436 new_token.reg = NULL;
7437 new_token.str = NULL;
7438
4a1805b1 7439 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7440 cur_token to prev_token. */
7441 if (prev_token.str)
7442 free (prev_token.str);
7443
7444 prev_token = cur_token;
7445
7446 /* Skip whitespace. */
7447 while (is_space_char (*intel_parser.op_string))
7448 intel_parser.op_string++;
7449
7450 /* Return an empty token if we find nothing else on the line. */
7451 if (*intel_parser.op_string == '\0')
7452 {
7453 cur_token = new_token;
7454 return;
7455 }
7456
7457 /* The new token cannot be larger than the remainder of the operand
7458 string. */
a724f0f4 7459 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7460 new_token.str[0] = '\0';
7461
7462 if (strchr ("0123456789", *intel_parser.op_string))
7463 {
7464 char *p = new_token.str;
7465 char *q = intel_parser.op_string;
7466 new_token.code = T_CONST;
7467
7468 /* Allow any kind of identifier char to encompass floating point and
7469 hexadecimal numbers. */
7470 while (is_identifier_char (*q))
7471 *p++ = *q++;
7472 *p = '\0';
7473
7474 /* Recognize special symbol names [0-9][bf]. */
7475 if (strlen (intel_parser.op_string) == 2
4a1805b1 7476 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7477 || intel_parser.op_string[1] == 'f'))
7478 new_token.code = T_ID;
7479 }
7480
4d1bb795 7481 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7482 {
4d1bb795
JB		 7483 size_t len = end_op - intel_parser.op_string;
7484
64a0c779
DN		 7485 new_token.code = T_REG;
7486 new_token.reg = reg;
7487
4d1bb795
JB		 7488 memcpy (new_token.str, intel_parser.op_string, len);
7489 new_token.str[len] = '\0';
64a0c779
DN		 7490 }
7491
7492 else if (is_identifier_char (*intel_parser.op_string))
7493 {
7494 char *p = new_token.str;
7495 char *q = intel_parser.op_string;
7496
7497 /* A '.' or '$' followed by an identifier char is an identifier.
7498 Otherwise, it's operator '.' followed by an expression. */
7499 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7500 {
9306ca4a
JB		 7501 new_token.code = '.';
7502 new_token.str[0] = '.';
64a0c779
DN		 7503 new_token.str[1] = '\0';
7504 }
7505 else
7506 {
7507 while (is_identifier_char (*q) || *q == '@')
7508 *p++ = *q++;
7509 *p = '\0';
7510
9306ca4a
JB		 7511 if (strcasecmp (new_token.str, "NOT") == 0)
7512 new_token.code = '~';
7513
7514 else if (strcasecmp (new_token.str, "MOD") == 0)
7515 new_token.code = '%';
7516
7517 else if (strcasecmp (new_token.str, "AND") == 0)
7518 new_token.code = '&';
7519
7520 else if (strcasecmp (new_token.str, "OR") == 0)
7521 new_token.code = '|';
7522
7523 else if (strcasecmp (new_token.str, "XOR") == 0)
7524 new_token.code = '^';
7525
7526 else if (strcasecmp (new_token.str, "SHL") == 0)
7527 new_token.code = T_SHL;
7528
7529 else if (strcasecmp (new_token.str, "SHR") == 0)
7530 new_token.code = T_SHR;
7531
7532 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7533 new_token.code = T_BYTE;
7534
7535 else if (strcasecmp (new_token.str, "WORD") == 0)
7536 new_token.code = T_WORD;
7537
7538 else if (strcasecmp (new_token.str, "DWORD") == 0)
7539 new_token.code = T_DWORD;
7540
9306ca4a
JB		 7541 else if (strcasecmp (new_token.str, "FWORD") == 0)
7542 new_token.code = T_FWORD;
7543
64a0c779
DN		 7544 else if (strcasecmp (new_token.str, "QWORD") == 0)
7545 new_token.code = T_QWORD;
7546
9306ca4a
JB		 7547 else if (strcasecmp (new_token.str, "TBYTE") == 0
7548 /* XXX remove (gcc still uses it) */
7549 || strcasecmp (new_token.str, "XWORD") == 0)
7550 new_token.code = T_TBYTE;
7551
7552 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7553 || strcasecmp (new_token.str, "OWORD") == 0)
7554 new_token.code = T_XMMWORD;
64a0c779
DN		 7555
7556 else if (strcasecmp (new_token.str, "PTR") == 0)
7557 new_token.code = T_PTR;
7558
7559 else if (strcasecmp (new_token.str, "SHORT") == 0)
7560 new_token.code = T_SHORT;
7561
7562 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7563 {
7564 new_token.code = T_OFFSET;
7565
7566 /* ??? This is not mentioned in the MASM grammar but gcc
7567 makes use of it with -mintel-syntax. OFFSET may be
7568 followed by FLAT: */
7569 if (strncasecmp (q, " FLAT:", 6) == 0)
7570 strcat (new_token.str, " FLAT:");
7571 }
7572
7573 /* ??? This is not mentioned in the MASM grammar. */
7574 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7575 {
7576 new_token.code = T_OFFSET;
7577 if (*q == ':')
7578 strcat (new_token.str, ":");
7579 else
7580 as_bad (_("`:' expected"));
7581 }
64a0c779
DN		 7582
7583 else
7584 new_token.code = T_ID;
7585 }
7586 }
7587
9306ca4a
JB		 7588 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7589 {
7590 new_token.code = *intel_parser.op_string;
7591 new_token.str[0] = *intel_parser.op_string;
7592 new_token.str[1] = '\0';
7593 }
7594
7595 else if (strchr ("<>", *intel_parser.op_string)
7596 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7597 {
7598 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7599 new_token.str[0] = *intel_parser.op_string;
7600 new_token.str[1] = *intel_parser.op_string;
7601 new_token.str[2] = '\0';
7602 }
7603
64a0c779 7604 else
0477af35 7605 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7606
7607 intel_parser.op_string += strlen (new_token.str);
7608 cur_token = new_token;
7609}
7610
64a0c779
DN		 7611/* Put cur_token back into the token stream and make cur_token point to
7612 prev_token. */
7613static void
e3bb37b5 7614intel_putback_token (void)
64a0c779 7615{
a724f0f4
JB		 7616 if (cur_token.code != T_NIL)
7617 {
7618 intel_parser.op_string -= strlen (cur_token.str);
7619 free (cur_token.str);
7620 }
64a0c779 7621 cur_token = prev_token;
4a1805b1 7622
64a0c779
DN		 7623 /* Forget prev_token. */
7624 prev_token.code = T_NIL;
7625 prev_token.reg = NULL;
7626 prev_token.str = NULL;
7627}
54cfded0 7628
a4447b93 7629int
1df69f4f 7630tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7631{
7632 unsigned int regnum;
7633 unsigned int regnames_count;
089dfecd 7634 static const char *const regnames_32[] =
54cfded0 7635 {
a4447b93
RH		 7636 "eax", "ecx", "edx", "ebx",
7637 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7638 "eip", "eflags", NULL,
7639 "st0", "st1", "st2", "st3",
7640 "st4", "st5", "st6", "st7",
7641 NULL, NULL,
7642 "xmm0", "xmm1", "xmm2", "xmm3",
7643 "xmm4", "xmm5", "xmm6", "xmm7",
7644 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7645 "mm4", "mm5", "mm6", "mm7",
7646 "fcw", "fsw", "mxcsr",
7647 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7648 "tr", "ldtr"
54cfded0 7649 };
089dfecd 7650 static const char *const regnames_64[] =
54cfded0 7651 {
089dfecd
JB		 7652 "rax", "rdx", "rcx", "rbx",
7653 "rsi", "rdi", "rbp", "rsp",
7654 "r8", "r9", "r10", "r11",
54cfded0 7655 "r12", "r13", "r14", "r15",
089dfecd
JB		 7656 "rip",
7657 "xmm0", "xmm1", "xmm2", "xmm3",
7658 "xmm4", "xmm5", "xmm6", "xmm7",
7659 "xmm8", "xmm9", "xmm10", "xmm11",
7660 "xmm12", "xmm13", "xmm14", "xmm15",
7661 "st0", "st1", "st2", "st3",
7662 "st4", "st5", "st6", "st7",
7663 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7664 "mm4", "mm5", "mm6", "mm7",
7665 "rflags",
7666 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7667 "fs.base", "gs.base", NULL, NULL,
7668 "tr", "ldtr",
7669 "mxcsr", "fcw", "fsw"
54cfded0 7670 };
089dfecd 7671 const char *const *regnames;
54cfded0
AM		 7672
7673 if (flag_code == CODE_64BIT)
7674 {
7675 regnames = regnames_64;
0cea6190 7676 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7677 }
7678 else
7679 {
7680 regnames = regnames_32;
0cea6190 7681 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7682 }
7683
7684 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7685 if (regnames[regnum] != NULL
7686 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7687 return regnum;
7688
54cfded0
AM		 7689 return -1;
7690}
7691
7692void
7693tc_x86_frame_initial_instructions (void)
7694{
a4447b93
RH		 7695 static unsigned int sp_regno;
7696
7697 if (!sp_regno)
7698 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7699 ? "rsp" : "esp");
7700
7701 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7702 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7703}
d2b2c203
DJ		 7704
7705int
7706i386_elf_section_type (const char *str, size_t len)
7707{
7708 if (flag_code == CODE_64BIT
7709 && len == sizeof ("unwind") - 1
7710 && strncmp (str, "unwind", 6) == 0)
7711 return SHT_X86_64_UNWIND;
7712
7713 return -1;
7714}
bb41ade5
AM		 7715
7716#ifdef TE_PE
7717void
7718tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7719{
7720 expressionS expr;
7721
7722 expr.X_op = O_secrel;
7723 expr.X_add_symbol = symbol;
7724 expr.X_add_number = 0;
7725 emit_expr (&expr, size);
7726}
7727#endif
3b22753a
L		 7728
7729#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7730/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7731
7732int
7733x86_64_section_letter (int letter, char **ptr_msg)
7734{
7735 if (flag_code == CODE_64BIT)
7736 {
7737 if (letter == 'l')
7738 return SHF_X86_64_LARGE;
7739
7740 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7741 }
3b22753a 7742 else
64e74474 7743 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7744 return -1;
7745}
7746
7747int
7748x86_64_section_word (char *str, size_t len)
7749{
8620418b 7750 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7751 return SHF_X86_64_LARGE;
7752
7753 return -1;
7754}
7755
7756static void
7757handle_large_common (int small ATTRIBUTE_UNUSED)
7758{
7759 if (flag_code != CODE_64BIT)
7760 {
7761 s_comm_internal (0, elf_common_parse);
7762 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7763 }
7764 else
7765 {
7766 static segT lbss_section;
7767 asection *saved_com_section_ptr = elf_com_section_ptr;
7768 asection *saved_bss_section = bss_section;
7769
7770 if (lbss_section == NULL)
7771 {
7772 flagword applicable;
7773 segT seg = now_seg;
7774 subsegT subseg = now_subseg;
7775
7776 /* The .lbss section is for local .largecomm symbols. */
7777 lbss_section = subseg_new (".lbss", 0);
7778 applicable = bfd_applicable_section_flags (stdoutput);
7779 bfd_set_section_flags (stdoutput, lbss_section,
7780 applicable & SEC_ALLOC);
7781 seg_info (lbss_section)->bss = 1;
7782
7783 subseg_set (seg, subseg);
7784 }
7785
7786 elf_com_section_ptr = &_bfd_elf_large_com_section;
7787 bss_section = lbss_section;
7788
7789 s_comm_internal (0, elf_common_parse);
7790
7791 elf_com_section_ptr = saved_com_section_ptr;
7792 bss_section = saved_bss_section;
7793 }
7794}
7795#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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