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PR 10980
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
252b5132
RH		 207struct _i386_insn
208 {
47926f60 209 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 210 insn_template tm;
252b5132 211
7d5e4556
L		 212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
252b5132
RH		 214 char suffix;
215
47926f60 216 /* OPERANDS gives the number of given operands. */
252b5132
RH		 217 unsigned int operands;
218
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
47926f60 221 operands. */
252b5132
RH		 222 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
223
224 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 225 use OP[i] for the corresponding operand. */
40fb9820 226 i386_operand_type types[MAX_OPERANDS];
252b5132 227
520dc8e8
AM		 228 /* Displacement expression, immediate expression, or register for each
229 operand. */
230 union i386_op op[MAX_OPERANDS];
252b5132 231
3e73aa7c
JH		 232 /* Flags for operands. */
233 unsigned int flags[MAX_OPERANDS];
234#define Operand_PCrel 1
235
252b5132 236 /* Relocation type for operand */
f86103b7 237 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 238
252b5132
RH		 239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry *base_reg;
242 const reg_entry *index_reg;
243 unsigned int log2_scale_factor;
244
245 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 246 explicit segment overrides are given. */
ce8a8b2f 247 const seg_entry *seg[2];
252b5132
RH		 248
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes;
252 unsigned char prefix[MAX_PREFIXES];
253
254 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 255 addressing modes of this insn are encoded. */
252b5132 256 modrm_byte rm;
3e73aa7c 257 rex_byte rex;
252b5132 258 sib_byte sib;
c0f3af97 259 vex_prefix vex;
b6169b20
L		 260
261 /* Swap operand in encoding. */
4473e004 262 unsigned int swap_operand;
252b5132
RH		 263 };
264
265typedef struct _i386_insn i386_insn;
266
267/* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
32137342 269const char extra_symbol_chars[] = "*%-(["
252b5132 270#ifdef LEX_AT
32137342
NC		 271 "@"
272#endif
273#ifdef LEX_QM
274 "?"
252b5132 275#endif
32137342 276 ;
252b5132 277
29b0f896
AM		 278#if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 280 && !defined (TE_GNU) \
29b0f896 281 && !defined (TE_LINUX) \
32137342 282 && !defined (TE_NETWARE) \
29b0f896
AM		 283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
252b5132 285/* This array holds the chars that always start a comment. If the
b3b91714
AM		 286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288const char *i386_comment_chars = "#/";
289#define SVR4_COMMENT_CHARS 1
252b5132 290#define PREFIX_SEPARATOR '\\'
252b5132 291
b3b91714
AM		 292#else
293const char *i386_comment_chars = "#";
294#define PREFIX_SEPARATOR '/'
295#endif
296
252b5132
RH		 297/* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 301 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
252b5132 304 '/' isn't otherwise defined. */
b3b91714 305const char line_comment_chars[] = "#/";
252b5132 306
63a0b638 307const char line_separator_chars[] = ";";
252b5132 308
ce8a8b2f
AM		 309/* Chars that can be used to separate mant from exp in floating point
310 nums. */
252b5132
RH		 311const char EXP_CHARS[] = "eE";
312
ce8a8b2f
AM		 313/* Chars that mean this number is a floating point constant
314 As in 0f12.456
315 or 0d1.2345e12. */
252b5132
RH		 316const char FLT_CHARS[] = "fFdDxX";
317
ce8a8b2f 318/* Tables for lexical analysis. */
252b5132
RH		 319static char mnemonic_chars[256];
320static char register_chars[256];
321static char operand_chars[256];
322static char identifier_chars[256];
323static char digit_chars[256];
324
ce8a8b2f 325/* Lexical macros. */
252b5132
RH		 326#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327#define is_operand_char(x) (operand_chars[(unsigned char) x])
328#define is_register_char(x) (register_chars[(unsigned char) x])
329#define is_space_char(x) ((x) == ' ')
330#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331#define is_digit_char(x) (digit_chars[(unsigned char) x])
332
0234cb7c 333/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 334static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
335
336/* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
47926f60 339 assembler instruction). */
252b5132 340static char save_stack[32];
ce8a8b2f 341static char *save_stack_p;
252b5132
RH		 342#define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344#define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
346
47926f60 347/* The instruction we're assembling. */
252b5132
RH		 348static i386_insn i;
349
350/* Possible templates for current insn. */
351static const templates *current_templates;
352
31b2323c
L		 353/* Per instruction expressionS buffers: max displacements & immediates. */
354static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
355static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 356
47926f60 357/* Current operand we are working on. */
ee86248c 358static int this_operand = -1;
252b5132 359
3e73aa7c
JH		 360/* We support four different modes. FLAG_CODE variable is used to distinguish
361 these. */
362
363enum flag_code {
364 CODE_32BIT,
365 CODE_16BIT,
366 CODE_64BIT };
367
368static enum flag_code flag_code;
4fa24527 369static unsigned int object_64bit;
3e73aa7c
JH		 370static int use_rela_relocations = 0;
371
372/* The names used to print error messages. */
b77a7acd 373static const char *flag_code_names[] =
3e73aa7c
JH		 374 {
375 "32",
376 "16",
377 "64"
378 };
252b5132 379
47926f60
KH		 380/* 1 for intel syntax,
381 0 if att syntax. */
382static int intel_syntax = 0;
252b5132 383
1efbbeb4
L		 384/* 1 for intel mnemonic,
385 0 if att mnemonic. */
386static int intel_mnemonic = !SYSV386_COMPAT;
387
5209009a 388/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 389static int old_gcc = OLDGCC_COMPAT;
390
a60de03c
JB		 391/* 1 if pseudo registers are permitted. */
392static int allow_pseudo_reg = 0;
393
47926f60
KH		 394/* 1 if register prefix % not required. */
395static int allow_naked_reg = 0;
252b5132 396
ba104c83 397/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 398static int allow_index_reg = 0;
399
daf50ae7
L		 400static enum
401 {
402 sse_check_none = 0,
403 sse_check_warning,
404 sse_check_error
405 }
406sse_check;
407
2ca3ace5
L		 408/* Register prefix used for error message. */
409static const char *register_prefix = "%";
410
47926f60
KH		 411/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414static char stackop_size = '\0';
eecb386c 415
12b55ccc
L		 416/* Non-zero to optimize code alignment. */
417int optimize_align_code = 1;
418
47926f60
KH		 419/* Non-zero to quieten some warnings. */
420static int quiet_warnings = 0;
a38cf1db 421
47926f60
KH		 422/* CPU name. */
423static const char *cpu_arch_name = NULL;
6305a203 424static char *cpu_sub_arch_name = NULL;
a38cf1db 425
47926f60 426/* CPU feature flags. */
40fb9820
L		 427static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
428
ccc9c027
L		 429/* If we have selected a cpu we are generating instructions for. */
430static int cpu_arch_tune_set = 0;
431
9103f4f4 432/* Cpu we are generating instructions for. */
fbf3f584 433enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 434
435/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 436static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 437
ccc9c027 438/* CPU instruction set architecture used. */
fbf3f584 439enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 440
9103f4f4 441/* CPU feature flags of instruction set architecture used. */
fbf3f584 442i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 443
fddf5b5b
AM		 444/* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446static unsigned int no_cond_jump_promotion = 0;
447
c0f3af97
L		 448/* Encode SSE instructions with VEX prefix. */
449static unsigned int sse2avx;
450
29b0f896 451/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 452static symbolS *GOT_symbol;
29b0f896 453
a4447b93
RH		 454/* The dwarf2 return column, adjusted for 32 or 64 bit. */
455unsigned int x86_dwarf2_return_column;
456
457/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458int x86_cie_data_alignment;
459
252b5132 460/* Interface to relax_segment.
fddf5b5b
AM		 461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
252b5132 464
47926f60 465/* Types. */
93c2a809
AM		 466#define UNCOND_JUMP 0
467#define COND_JUMP 1
468#define COND_JUMP86 2
fddf5b5b 469
47926f60 470/* Sizes. */
252b5132
RH		 471#define CODE16 1
472#define SMALL 0
29b0f896 473#define SMALL16 (SMALL | CODE16)
252b5132 474#define BIG 2
29b0f896 475#define BIG16 (BIG | CODE16)
252b5132
RH		 476
477#ifndef INLINE
478#ifdef __GNUC__
479#define INLINE __inline__
480#else
481#define INLINE
482#endif
483#endif
484
fddf5b5b
AM		 485#define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487#define TYPE_FROM_RELAX_STATE(s) \
488 ((s) >> 2)
489#define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 491
492/* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
499
500const relax_typeS md_relax_table[] =
501{
24eab124
AM		 502 /* The fields are:
503 1) most positive reach of this state,
504 2) most negative reach of this state,
93c2a809 505 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 506 4) which index into the table to try if we can't fit into this one. */
252b5132 507
fddf5b5b 508 /* UNCOND_JUMP states. */
93c2a809
AM		 509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
252b5132 513 {0, 0, 4, 0},
93c2a809
AM		 514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 516 {0, 0, 2, 0},
517
93c2a809
AM		 518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
523 {0, 0, 5, 0},
fddf5b5b 524 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 525 1 extra opcode byte, 2 displacement bytes. */
526 {0, 0, 3, 0},
527
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
533 {0, 0, 5, 0},
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
536 {0, 0, 4, 0}
252b5132
RH		 537};
538
9103f4f4
L		 539static const arch_entry cpu_arch[] =
540{
8a2c8fef
L		 541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
542 CPU_GENERIC32_FLAGS, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
544 CPU_GENERIC64_FLAGS, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
546 CPU_NONE_FLAGS, 0 },
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
548 CPU_I186_FLAGS, 0 },
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
550 CPU_I286_FLAGS, 0 },
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
552 CPU_I386_FLAGS, 0 },
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
554 CPU_I486_FLAGS, 0 },
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
556 CPU_I586_FLAGS, 0 },
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
558 CPU_I686_FLAGS, 0 },
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
560 CPU_I586_FLAGS, 0 },
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
562 CPU_I686_FLAGS, 0 },
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
564 CPU_P2_FLAGS, 0 },
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
566 CPU_P3_FLAGS, 0 },
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
568 CPU_P4_FLAGS, 0 },
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
570 CPU_CORE_FLAGS, 0 },
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
572 CPU_NOCONA_FLAGS, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
574 CPU_CORE_FLAGS, 1 },
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
576 CPU_CORE_FLAGS, 0 },
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
578 CPU_CORE2_FLAGS, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
580 CPU_CORE2_FLAGS, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
582 CPU_COREI7_FLAGS, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
584 CPU_L1OM_FLAGS, 0 },
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
586 CPU_K6_FLAGS, 0 },
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
588 CPU_K6_2_FLAGS, 0 },
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
590 CPU_ATHLON_FLAGS, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
592 CPU_K8_FLAGS, 1 },
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
594 CPU_K8_FLAGS, 0 },
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
596 CPU_K8_FLAGS, 0 },
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
598 CPU_AMDFAM10_FLAGS, 0 },
599 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
600 CPU_8087_FLAGS, 0 },
601 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
602 CPU_287_FLAGS, 0 },
603 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
604 CPU_387_FLAGS, 0 },
605 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
606 CPU_ANY87_FLAGS, 0 },
607 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
608 CPU_MMX_FLAGS, 0 },
609 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
610 CPU_3DNOWA_FLAGS, 0 },
611 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS, 0 },
613 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS, 0 },
615 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS, 0 },
617 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS, 0 },
619 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS, 0 },
621 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS, 0 },
623 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS, 0 },
625 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
626 CPU_ANY_SSE_FLAGS, 0 },
627 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
628 CPU_AVX_FLAGS, 0 },
629 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
630 CPU_ANY_AVX_FLAGS, 0 },
631 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
632 CPU_VMX_FLAGS, 0 },
633 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
634 CPU_SMX_FLAGS, 0 },
635 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
636 CPU_XSAVE_FLAGS, 0 },
637 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
638 CPU_AES_FLAGS, 0 },
639 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
640 CPU_PCLMUL_FLAGS, 0 },
641 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
642 CPU_PCLMUL_FLAGS, 1 },
643 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
644 CPU_FMA_FLAGS, 0 },
645 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
646 CPU_FMA4_FLAGS, 0 },
647 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
648 CPU_XOP_FLAGS, 0 },
649 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
650 CPU_LWP_FLAGS, 0 },
651 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS, 0 },
653 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS, 0 },
655 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS, 0 },
657 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS, 0 },
659 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS, 0 },
661 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS, 0 },
663 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS, 0 },
665 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS, 0 },
667 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS, 1 },
669 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS, 0 },
671 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS, 0 },
673 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 675};
676
704209c0 677#ifdef I386COFF
a6c24e68
NC		 678/* Like s_lcomm_internal in gas/read.c but the alignment string
679 is allowed to be optional. */
680
681static symbolS *
682pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
683{
684 addressT align = 0;
685
686 SKIP_WHITESPACE ();
687
7ab9ffdd 688 if (needs_align
a6c24e68
NC		 689 && *input_line_pointer == ',')
690 {
691 align = parse_align (needs_align - 1);
7ab9ffdd 692
a6c24e68
NC		 693 if (align == (addressT) -1)
694 return NULL;
695 }
696 else
697 {
698 if (size >= 8)
699 align = 3;
700 else if (size >= 4)
701 align = 2;
702 else if (size >= 2)
703 align = 1;
704 else
705 align = 0;
706 }
707
708 bss_alloc (symbolP, size, align);
709 return symbolP;
710}
711
704209c0 712static void
a6c24e68
NC		 713pe_lcomm (int needs_align)
714{
715 s_comm_internal (needs_align * 2, pe_lcomm_internal);
716}
704209c0 717#endif
a6c24e68 718
29b0f896
AM		 719const pseudo_typeS md_pseudo_table[] =
720{
721#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
722 {"align", s_align_bytes, 0},
723#else
724 {"align", s_align_ptwo, 0},
725#endif
726 {"arch", set_cpu_arch, 0},
727#ifndef I386COFF
728 {"bss", s_bss, 0},
a6c24e68
NC		 729#else
730 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 731#endif
732 {"ffloat", float_cons, 'f'},
733 {"dfloat", float_cons, 'd'},
734 {"tfloat", float_cons, 'x'},
735 {"value", cons, 2},
d182319b 736 {"slong", signed_cons, 4},
29b0f896
AM		 737 {"noopt", s_ignore, 0},
738 {"optim", s_ignore, 0},
739 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
740 {"code16", set_code_flag, CODE_16BIT},
741 {"code32", set_code_flag, CODE_32BIT},
742 {"code64", set_code_flag, CODE_64BIT},
743 {"intel_syntax", set_intel_syntax, 1},
744 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 745 {"intel_mnemonic", set_intel_mnemonic, 1},
746 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 747 {"allow_index_reg", set_allow_index_reg, 1},
748 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 749 {"sse_check", set_sse_check, 0},
3b22753a
L		 750#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
751 {"largecomm", handle_large_common, 0},
07a53e5c 752#else
e3bb37b5 753 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 754 {"loc", dwarf2_directive_loc, 0},
755 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 756#endif
6482c264
NC		 757#ifdef TE_PE
758 {"secrel32", pe_directive_secrel, 0},
759#endif
29b0f896
AM		 760 {0, 0, 0}
761};
762
763/* For interface with expression (). */
764extern char *input_line_pointer;
765
766/* Hash table for instruction mnemonic lookup. */
767static struct hash_control *op_hash;
768
769/* Hash table for register lookup. */
770static struct hash_control *reg_hash;
771\f
252b5132 772void
e3bb37b5 773i386_align_code (fragS *fragP, int count)
252b5132 774{
ce8a8b2f
AM		 775 /* Various efficient no-op patterns for aligning code labels.
776 Note: Don't try to assemble the instructions in the comments.
777 0L and 0w are not legal. */
252b5132
RH		 778 static const char f32_1[] =
779 {0x90}; /* nop */
780 static const char f32_2[] =
ccc9c027 781 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 782 static const char f32_3[] =
783 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
784 static const char f32_4[] =
785 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
786 static const char f32_5[] =
787 {0x90, /* nop */
788 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
789 static const char f32_6[] =
790 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
791 static const char f32_7[] =
792 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
793 static const char f32_8[] =
794 {0x90, /* nop */
795 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
796 static const char f32_9[] =
797 {0x89,0xf6, /* movl %esi,%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_10[] =
800 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_11[] =
803 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_12[] =
806 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
807 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
808 static const char f32_13[] =
809 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_14[] =
812 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 814 static const char f16_3[] =
815 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 816 static const char f16_4[] =
817 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
818 static const char f16_5[] =
819 {0x90, /* nop */
820 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
821 static const char f16_6[] =
822 {0x89,0xf6, /* mov %si,%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char f16_7[] =
825 {0x8d,0x74,0x00, /* lea 0(%si),%si */
826 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
827 static const char f16_8[] =
828 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
829 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 830 static const char jump_31[] =
831 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
833 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 835 static const char *const f32_patt[] = {
836 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 837 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 838 };
839 static const char *const f16_patt[] = {
76bc74dc 840 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 841 };
ccc9c027
L		 842 /* nopl (%[re]ax) */
843 static const char alt_3[] =
844 {0x0f,0x1f,0x00};
845 /* nopl 0(%[re]ax) */
846 static const char alt_4[] =
847 {0x0f,0x1f,0x40,0x00};
848 /* nopl 0(%[re]ax,%[re]ax,1) */
849 static const char alt_5[] =
850 {0x0f,0x1f,0x44,0x00,0x00};
851 /* nopw 0(%[re]ax,%[re]ax,1) */
852 static const char alt_6[] =
853 {0x66,0x0f,0x1f,0x44,0x00,0x00};
854 /* nopl 0L(%[re]ax) */
855 static const char alt_7[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
857 /* nopl 0L(%[re]ax,%[re]ax,1) */
858 static const char alt_8[] =
859 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* nopw 0L(%[re]ax,%[re]ax,1) */
861 static const char alt_9[] =
862 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_10[] =
865 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 /* data16
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_11[] =
869 {0x66,
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* data16
872 data16
873 nopw %cs:0L(%[re]ax,%[re]ax,1) */
874 static const char alt_long_12[] =
875 {0x66,
876 0x66,
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
878 /* data16
879 data16
880 data16
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_13[] =
883 {0x66,
884 0x66,
885 0x66,
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
887 /* data16
888 data16
889 data16
890 data16
891 nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_long_14[] =
893 {0x66,
894 0x66,
895 0x66,
896 0x66,
897 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
898 /* data16
899 data16
900 data16
901 data16
902 data16
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_15[] =
905 {0x66,
906 0x66,
907 0x66,
908 0x66,
909 0x66,
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* nopl 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_11[] =
914 {0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_short_12[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x66,0x0f,0x1f,0x44,0x00,0x00};
921 /* nopw 0(%[re]ax,%[re]ax,1)
922 nopl 0L(%[re]ax) */
923 static const char alt_short_13[] =
924 {0x66,0x0f,0x1f,0x44,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 /* nopl 0L(%[re]ax)
927 nopl 0L(%[re]ax) */
928 static const char alt_short_14[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
931 /* nopl 0L(%[re]ax)
932 nopl 0L(%[re]ax,%[re]ax,1) */
933 static const char alt_short_15[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
935 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
936 static const char *const alt_short_patt[] = {
937 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
938 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
939 alt_short_14, alt_short_15
940 };
941 static const char *const alt_long_patt[] = {
942 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
943 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
944 alt_long_14, alt_long_15
945 };
252b5132 946
76bc74dc
L		 947 /* Only align for at least a positive non-zero boundary. */
948 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 949 return;
3e73aa7c 950
ccc9c027
L		 951 /* We need to decide which NOP sequence to use for 32bit and
952 64bit. When -mtune= is used:
4eed87de 953
76bc74dc
L		 954 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
955 PROCESSOR_GENERIC32, f32_patt will be used.
956 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 957 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
958 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 959 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
960 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 961
76bc74dc
L		 962 When -mtune= isn't used, alt_long_patt will be used if
963 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
964 be used.
ccc9c027
L		 965
966 When -march= or .arch is used, we can't use anything beyond
967 cpu_arch_isa_flags. */
968
969 if (flag_code == CODE_16BIT)
970 {
ccc9c027 971 if (count > 8)
33fef721 972 {
76bc74dc
L		 973 memcpy (fragP->fr_literal + fragP->fr_fix,
974 jump_31, count);
975 /* Adjust jump offset. */
976 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 977 }
76bc74dc
L		 978 else
979 memcpy (fragP->fr_literal + fragP->fr_fix,
980 f16_patt[count - 1], count);
252b5132 981 }
33fef721 982 else
ccc9c027
L		 983 {
984 const char *const *patt = NULL;
985
fbf3f584 986 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 987 {
988 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
989 switch (cpu_arch_tune)
990 {
991 case PROCESSOR_UNKNOWN:
992 /* We use cpu_arch_isa_flags to check if we SHOULD
993 optimize for Cpu686. */
fbf3f584 994 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 995 patt = alt_long_patt;
ccc9c027
L		 996 else
997 patt = f32_patt;
998 break;
ccc9c027
L		 999 case PROCESSOR_PENTIUMPRO:
1000 case PROCESSOR_PENTIUM4:
1001 case PROCESSOR_NOCONA:
ef05d495 1002 case PROCESSOR_CORE:
76bc74dc 1003 case PROCESSOR_CORE2:
bd5295b2 1004 case PROCESSOR_COREI7:
3632d14b 1005 case PROCESSOR_L1OM:
76bc74dc
L		 1006 case PROCESSOR_GENERIC64:
1007 patt = alt_long_patt;
1008 break;
ccc9c027
L		 1009 case PROCESSOR_K6:
1010 case PROCESSOR_ATHLON:
1011 case PROCESSOR_K8:
4eed87de 1012 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1013 patt = alt_short_patt;
1014 break;
76bc74dc 1015 case PROCESSOR_I386:
ccc9c027
L		 1016 case PROCESSOR_I486:
1017 case PROCESSOR_PENTIUM:
1018 case PROCESSOR_GENERIC32:
1019 patt = f32_patt;
1020 break;
4eed87de 1021 }
ccc9c027
L		 1022 }
1023 else
1024 {
fbf3f584 1025 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1026 {
1027 case PROCESSOR_UNKNOWN:
e6a14101 1028 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1029 PROCESSOR_UNKNOWN. */
1030 abort ();
1031 break;
1032
76bc74dc 1033 case PROCESSOR_I386:
ccc9c027
L		 1034 case PROCESSOR_I486:
1035 case PROCESSOR_PENTIUM:
ccc9c027
L		 1036 case PROCESSOR_K6:
1037 case PROCESSOR_ATHLON:
1038 case PROCESSOR_K8:
4eed87de 1039 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1040 case PROCESSOR_GENERIC32:
1041 /* We use cpu_arch_isa_flags to check if we CAN optimize
1042 for Cpu686. */
fbf3f584 1043 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1044 patt = alt_short_patt;
1045 else
1046 patt = f32_patt;
1047 break;
76bc74dc
L		 1048 case PROCESSOR_PENTIUMPRO:
1049 case PROCESSOR_PENTIUM4:
1050 case PROCESSOR_NOCONA:
1051 case PROCESSOR_CORE:
ef05d495 1052 case PROCESSOR_CORE2:
bd5295b2 1053 case PROCESSOR_COREI7:
3632d14b 1054 case PROCESSOR_L1OM:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1070 its offset. */
1071 int limit;
76ba9986 1072
711eedef
L		 1073 /* For 64bit, the limit is 3 bytes. */
1074 if (flag_code == CODE_64BIT
1075 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1076 limit = 3;
1077 else
1078 limit = 15;
1079 if (count < limit)
76bc74dc
L		 1080 memcpy (fragP->fr_literal + fragP->fr_fix,
1081 patt[count - 1], count);
1082 else
1083 {
1084 memcpy (fragP->fr_literal + fragP->fr_fix,
1085 jump_31, count);
1086 /* Adjust jump offset. */
1087 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1088 }
1089 }
1090 else
1091 {
1092 /* Maximum length of an instruction is 15 byte. If the
1093 padding is greater than 15 bytes and we don't use jump,
1094 we have to break it into smaller pieces. */
1095 int padding = count;
1096 while (padding > 15)
1097 {
1098 padding -= 15;
1099 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1100 patt [14], 15);
1101 }
1102
1103 if (padding)
1104 memcpy (fragP->fr_literal + fragP->fr_fix,
1105 patt [padding - 1], padding);
1106 }
ccc9c027 1107 }
33fef721 1108 fragP->fr_var = count;
252b5132
RH		 1109}
1110
c6fb90c8 1111static INLINE int
0dfbf9d7 1112operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1113{
0dfbf9d7 1114 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1115 {
1116 case 3:
0dfbf9d7 1117 if (x->array[2])
c6fb90c8
L		 1118 return 0;
1119 case 2:
0dfbf9d7 1120 if (x->array[1])
c6fb90c8
L		 1121 return 0;
1122 case 1:
0dfbf9d7 1123 return !x->array[0];
c6fb90c8
L		 1124 default:
1125 abort ();
1126 }
40fb9820
L		 1127}
1128
c6fb90c8 1129static INLINE void
0dfbf9d7 1130operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1131{
0dfbf9d7 1132 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1133 {
1134 case 3:
0dfbf9d7 1135 x->array[2] = v;
c6fb90c8 1136 case 2:
0dfbf9d7 1137 x->array[1] = v;
c6fb90c8 1138 case 1:
0dfbf9d7 1139 x->array[0] = v;
c6fb90c8
L		 1140 break;
1141 default:
1142 abort ();
1143 }
1144}
40fb9820 1145
c6fb90c8 1146static INLINE int
0dfbf9d7
L		 1147operand_type_equal (const union i386_operand_type *x,
1148 const union i386_operand_type *y)
c6fb90c8 1149{
0dfbf9d7 1150 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1151 {
1152 case 3:
0dfbf9d7 1153 if (x->array[2] != y->array[2])
c6fb90c8
L		 1154 return 0;
1155 case 2:
0dfbf9d7 1156 if (x->array[1] != y->array[1])
c6fb90c8
L		 1157 return 0;
1158 case 1:
0dfbf9d7 1159 return x->array[0] == y->array[0];
c6fb90c8
L		 1160 break;
1161 default:
1162 abort ();
1163 }
1164}
40fb9820 1165
0dfbf9d7
L		 1166static INLINE int
1167cpu_flags_all_zero (const union i386_cpu_flags *x)
1168{
1169 switch (ARRAY_SIZE(x->array))
1170 {
1171 case 3:
1172 if (x->array[2])
1173 return 0;
1174 case 2:
1175 if (x->array[1])
1176 return 0;
1177 case 1:
1178 return !x->array[0];
1179 default:
1180 abort ();
1181 }
1182}
1183
1184static INLINE void
1185cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1186{
1187 switch (ARRAY_SIZE(x->array))
1188 {
1189 case 3:
1190 x->array[2] = v;
1191 case 2:
1192 x->array[1] = v;
1193 case 1:
1194 x->array[0] = v;
1195 break;
1196 default:
1197 abort ();
1198 }
1199}
1200
1201static INLINE int
1202cpu_flags_equal (const union i386_cpu_flags *x,
1203 const union i386_cpu_flags *y)
1204{
1205 switch (ARRAY_SIZE(x->array))
1206 {
1207 case 3:
1208 if (x->array[2] != y->array[2])
1209 return 0;
1210 case 2:
1211 if (x->array[1] != y->array[1])
1212 return 0;
1213 case 1:
1214 return x->array[0] == y->array[0];
1215 break;
1216 default:
1217 abort ();
1218 }
1219}
c6fb90c8
L		 1220
1221static INLINE int
1222cpu_flags_check_cpu64 (i386_cpu_flags f)
1223{
1224 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1225 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1226}
1227
c6fb90c8
L		 1228static INLINE i386_cpu_flags
1229cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1230{
c6fb90c8
L		 1231 switch (ARRAY_SIZE (x.array))
1232 {
1233 case 3:
1234 x.array [2] &= y.array [2];
1235 case 2:
1236 x.array [1] &= y.array [1];
1237 case 1:
1238 x.array [0] &= y.array [0];
1239 break;
1240 default:
1241 abort ();
1242 }
1243 return x;
1244}
40fb9820 1245
c6fb90c8
L		 1246static INLINE i386_cpu_flags
1247cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1248{
c6fb90c8 1249 switch (ARRAY_SIZE (x.array))
40fb9820 1250 {
c6fb90c8
L		 1251 case 3:
1252 x.array [2] |= y.array [2];
1253 case 2:
1254 x.array [1] |= y.array [1];
1255 case 1:
1256 x.array [0] |= y.array [0];
40fb9820
L		 1257 break;
1258 default:
1259 abort ();
1260 }
40fb9820
L		 1261 return x;
1262}
1263
309d3373
JB		 1264static INLINE i386_cpu_flags
1265cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1266{
1267 switch (ARRAY_SIZE (x.array))
1268 {
1269 case 3:
1270 x.array [2] &= ~y.array [2];
1271 case 2:
1272 x.array [1] &= ~y.array [1];
1273 case 1:
1274 x.array [0] &= ~y.array [0];
1275 break;
1276 default:
1277 abort ();
1278 }
1279 return x;
1280}
1281
c0f3af97
L		 1282#define CPU_FLAGS_ARCH_MATCH 0x1
1283#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1284#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1285#define CPU_FLAGS_PCLMUL_MATCH 0x8
1286#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1287
a5ff0eb2 1288#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1289 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1290 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1291#define CPU_FLAGS_PERFECT_MATCH \
1292 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1293
1294/* Return CPU flags match bits. */
3629bb00 1295
40fb9820 1296static int
d3ce72d0 1297cpu_flags_match (const insn_template *t)
40fb9820 1298{
c0f3af97
L		 1299 i386_cpu_flags x = t->cpu_flags;
1300 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1301
1302 x.bitfield.cpu64 = 0;
1303 x.bitfield.cpuno64 = 0;
1304
0dfbf9d7 1305 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1306 {
1307 /* This instruction is available on all archs. */
1308 match |= CPU_FLAGS_32BIT_MATCH;
1309 }
3629bb00
L		 1310 else
1311 {
c0f3af97 1312 /* This instruction is available only on some archs. */
3629bb00
L		 1313 i386_cpu_flags cpu = cpu_arch_flags;
1314
1315 cpu.bitfield.cpu64 = 0;
1316 cpu.bitfield.cpuno64 = 0;
1317 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1318 if (!cpu_flags_all_zero (&cpu))
1319 {
a5ff0eb2
L		 1320 if (x.bitfield.cpuavx)
1321 {
ce2f5b3c 1322 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1323 if (cpu.bitfield.cpuavx)
1324 {
1325 /* Check SSE2AVX. */
1326 if (!t->opcode_modifier.sse2avx|| sse2avx)
1327 {
1328 match |= (CPU_FLAGS_ARCH_MATCH
1329 | CPU_FLAGS_AVX_MATCH);
1330 /* Check AES. */
1331 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1332 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1333 /* Check PCLMUL. */
1334 if (!x.bitfield.cpupclmul
1335 || cpu.bitfield.cpupclmul)
1336 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1337 }
1338 }
1339 else
1340 match |= CPU_FLAGS_ARCH_MATCH;
1341 }
1342 else
c0f3af97
L		 1343 match |= CPU_FLAGS_32BIT_MATCH;
1344 }
3629bb00 1345 }
c0f3af97 1346 return match;
40fb9820
L		 1347}
1348
c6fb90c8
L		 1349static INLINE i386_operand_type
1350operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1351{
c6fb90c8
L		 1352 switch (ARRAY_SIZE (x.array))
1353 {
1354 case 3:
1355 x.array [2] &= y.array [2];
1356 case 2:
1357 x.array [1] &= y.array [1];
1358 case 1:
1359 x.array [0] &= y.array [0];
1360 break;
1361 default:
1362 abort ();
1363 }
1364 return x;
40fb9820
L		 1365}
1366
c6fb90c8
L		 1367static INLINE i386_operand_type
1368operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1369{
c6fb90c8 1370 switch (ARRAY_SIZE (x.array))
40fb9820 1371 {
c6fb90c8
L		 1372 case 3:
1373 x.array [2] |= y.array [2];
1374 case 2:
1375 x.array [1] |= y.array [1];
1376 case 1:
1377 x.array [0] |= y.array [0];
40fb9820
L		 1378 break;
1379 default:
1380 abort ();
1381 }
c6fb90c8
L		 1382 return x;
1383}
40fb9820 1384
c6fb90c8
L		 1385static INLINE i386_operand_type
1386operand_type_xor (i386_operand_type x, i386_operand_type y)
1387{
1388 switch (ARRAY_SIZE (x.array))
1389 {
1390 case 3:
1391 x.array [2] ^= y.array [2];
1392 case 2:
1393 x.array [1] ^= y.array [1];
1394 case 1:
1395 x.array [0] ^= y.array [0];
1396 break;
1397 default:
1398 abort ();
1399 }
40fb9820
L		 1400 return x;
1401}
1402
1403static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1404static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1405static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1406static const i386_operand_type inoutportreg
1407 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1408static const i386_operand_type reg16_inoutportreg
1409 = OPERAND_TYPE_REG16_INOUTPORTREG;
1410static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1411static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1412static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1413static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1414static const i386_operand_type anydisp
1415 = OPERAND_TYPE_ANYDISP;
40fb9820 1416static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1417static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1418static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1419static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1420static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1421static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1422static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1423static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1424static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1425static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1426static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1427
1428enum operand_type
1429{
1430 reg,
40fb9820
L		 1431 imm,
1432 disp,
1433 anymem
1434};
1435
c6fb90c8 1436static INLINE int
40fb9820
L		 1437operand_type_check (i386_operand_type t, enum operand_type c)
1438{
1439 switch (c)
1440 {
1441 case reg:
1442 return (t.bitfield.reg8
1443 || t.bitfield.reg16
1444 || t.bitfield.reg32
1445 || t.bitfield.reg64);
1446
40fb9820
L		 1447 case imm:
1448 return (t.bitfield.imm8
1449 || t.bitfield.imm8s
1450 || t.bitfield.imm16
1451 || t.bitfield.imm32
1452 || t.bitfield.imm32s
1453 || t.bitfield.imm64);
1454
1455 case disp:
1456 return (t.bitfield.disp8
1457 || t.bitfield.disp16
1458 || t.bitfield.disp32
1459 || t.bitfield.disp32s
1460 || t.bitfield.disp64);
1461
1462 case anymem:
1463 return (t.bitfield.disp8
1464 || t.bitfield.disp16
1465 || t.bitfield.disp32
1466 || t.bitfield.disp32s
1467 || t.bitfield.disp64
1468 || t.bitfield.baseindex);
1469
1470 default:
1471 abort ();
1472 }
2cfe26b6
AM		 1473
1474 return 0;
40fb9820
L		 1475}
1476
5c07affc
L		 1477/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1478 operand J for instruction template T. */
1479
1480static INLINE int
d3ce72d0 1481match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1482{
1483 return !((i.types[j].bitfield.byte
1484 && !t->operand_types[j].bitfield.byte)
1485 || (i.types[j].bitfield.word
1486 && !t->operand_types[j].bitfield.word)
1487 || (i.types[j].bitfield.dword
1488 && !t->operand_types[j].bitfield.dword)
1489 || (i.types[j].bitfield.qword
1490 && !t->operand_types[j].bitfield.qword));
1491}
1492
1493/* Return 1 if there is no conflict in any size on operand J for
1494 instruction template T. */
1495
1496static INLINE int
d3ce72d0 1497match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1498{
1499 return (match_reg_size (t, j)
1500 && !((i.types[j].bitfield.unspecified
1501 && !t->operand_types[j].bitfield.unspecified)
1502 || (i.types[j].bitfield.fword
1503 && !t->operand_types[j].bitfield.fword)
1504 || (i.types[j].bitfield.tbyte
1505 && !t->operand_types[j].bitfield.tbyte)
1506 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1507 && !t->operand_types[j].bitfield.xmmword)
1508 || (i.types[j].bitfield.ymmword
1509 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1510}
1511
1512/* Return 1 if there is no size conflict on any operands for
1513 instruction template T. */
1514
1515static INLINE int
d3ce72d0 1516operand_size_match (const insn_template *t)
5c07affc
L		 1517{
1518 unsigned int j;
1519 int match = 1;
1520
1521 /* Don't check jump instructions. */
1522 if (t->opcode_modifier.jump
1523 || t->opcode_modifier.jumpbyte
1524 || t->opcode_modifier.jumpdword
1525 || t->opcode_modifier.jumpintersegment)
1526 return match;
1527
1528 /* Check memory and accumulator operand size. */
1529 for (j = 0; j < i.operands; j++)
1530 {
1531 if (t->operand_types[j].bitfield.anysize)
1532 continue;
1533
1534 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1535 {
1536 match = 0;
1537 break;
1538 }
1539
1540 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1541 {
1542 match = 0;
1543 break;
1544 }
1545 }
1546
1547 if (match
1548 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1549 return match;
1550
1551 /* Check reverse. */
9c2799c2 1552 gas_assert (i.operands == 2);
5c07affc
L		 1553
1554 match = 1;
1555 for (j = 0; j < 2; j++)
1556 {
1557 if (t->operand_types[j].bitfield.acc
1558 && !match_reg_size (t, j ? 0 : 1))
1559 {
1560 match = 0;
1561 break;
1562 }
1563
1564 if (i.types[j].bitfield.mem
1565 && !match_mem_size (t, j ? 0 : 1))
1566 {
1567 match = 0;
1568 break;
1569 }
1570 }
1571
1572 return match;
1573}
1574
c6fb90c8 1575static INLINE int
40fb9820
L		 1576operand_type_match (i386_operand_type overlap,
1577 i386_operand_type given)
1578{
1579 i386_operand_type temp = overlap;
1580
1581 temp.bitfield.jumpabsolute = 0;
7d5e4556 1582 temp.bitfield.unspecified = 0;
5c07affc
L		 1583 temp.bitfield.byte = 0;
1584 temp.bitfield.word = 0;
1585 temp.bitfield.dword = 0;
1586 temp.bitfield.fword = 0;
1587 temp.bitfield.qword = 0;
1588 temp.bitfield.tbyte = 0;
1589 temp.bitfield.xmmword = 0;
c0f3af97 1590 temp.bitfield.ymmword = 0;
0dfbf9d7 1591 if (operand_type_all_zero (&temp))
40fb9820
L		 1592 return 0;
1593
1594 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1595 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1596}
1597
7d5e4556 1598/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1599 unless the expected operand type register overlap is null.
1600 Note that Acc in a template matches every size of reg. */
1601
c6fb90c8 1602static INLINE int
40fb9820
L		 1603operand_type_register_match (i386_operand_type m0,
1604 i386_operand_type g0,
1605 i386_operand_type t0,
1606 i386_operand_type m1,
1607 i386_operand_type g1,
1608 i386_operand_type t1)
1609{
1610 if (!operand_type_check (g0, reg))
1611 return 1;
1612
1613 if (!operand_type_check (g1, reg))
1614 return 1;
1615
1616 if (g0.bitfield.reg8 == g1.bitfield.reg8
1617 && g0.bitfield.reg16 == g1.bitfield.reg16
1618 && g0.bitfield.reg32 == g1.bitfield.reg32
1619 && g0.bitfield.reg64 == g1.bitfield.reg64)
1620 return 1;
1621
1622 if (m0.bitfield.acc)
1623 {
1624 t0.bitfield.reg8 = 1;
1625 t0.bitfield.reg16 = 1;
1626 t0.bitfield.reg32 = 1;
1627 t0.bitfield.reg64 = 1;
1628 }
1629
1630 if (m1.bitfield.acc)
1631 {
1632 t1.bitfield.reg8 = 1;
1633 t1.bitfield.reg16 = 1;
1634 t1.bitfield.reg32 = 1;
1635 t1.bitfield.reg64 = 1;
1636 }
1637
1638 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1639 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1640 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1641 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1642}
1643
252b5132 1644static INLINE unsigned int
40fb9820 1645mode_from_disp_size (i386_operand_type t)
252b5132 1646{
40fb9820
L		 1647 if (t.bitfield.disp8)
1648 return 1;
1649 else if (t.bitfield.disp16
1650 || t.bitfield.disp32
1651 || t.bitfield.disp32s)
1652 return 2;
1653 else
1654 return 0;
252b5132
RH		 1655}
1656
1657static INLINE int
e3bb37b5 1658fits_in_signed_byte (offsetT num)
252b5132
RH		 1659{
1660 return (num >= -128) && (num <= 127);
47926f60 1661}
252b5132
RH		 1662
1663static INLINE int
e3bb37b5 1664fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1665{
1666 return (num & 0xff) == num;
47926f60 1667}
252b5132
RH		 1668
1669static INLINE int
e3bb37b5 1670fits_in_unsigned_word (offsetT num)
252b5132
RH		 1671{
1672 return (num & 0xffff) == num;
47926f60 1673}
252b5132
RH		 1674
1675static INLINE int
e3bb37b5 1676fits_in_signed_word (offsetT num)
252b5132
RH		 1677{
1678 return (-32768 <= num) && (num <= 32767);
47926f60 1679}
2a962e6d 1680
3e73aa7c 1681static INLINE int
e3bb37b5 1682fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1683{
1684#ifndef BFD64
1685 return 1;
1686#else
1687 return (!(((offsetT) -1 << 31) & num)
1688 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1689#endif
1690} /* fits_in_signed_long() */
2a962e6d 1691
3e73aa7c 1692static INLINE int
e3bb37b5 1693fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1694{
1695#ifndef BFD64
1696 return 1;
1697#else
1698 return (num & (((offsetT) 2 << 31) - 1)) == num;
1699#endif
1700} /* fits_in_unsigned_long() */
252b5132 1701
40fb9820 1702static i386_operand_type
e3bb37b5 1703smallest_imm_type (offsetT num)
252b5132 1704{
40fb9820 1705 i386_operand_type t;
7ab9ffdd 1706
0dfbf9d7 1707 operand_type_set (&t, 0);
40fb9820
L		 1708 t.bitfield.imm64 = 1;
1709
1710 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1711 {
1712 /* This code is disabled on the 486 because all the Imm1 forms
1713 in the opcode table are slower on the i486. They're the
1714 versions with the implicitly specified single-position
1715 displacement, which has another syntax if you really want to
1716 use that form. */
40fb9820
L		 1717 t.bitfield.imm1 = 1;
1718 t.bitfield.imm8 = 1;
1719 t.bitfield.imm8s = 1;
1720 t.bitfield.imm16 = 1;
1721 t.bitfield.imm32 = 1;
1722 t.bitfield.imm32s = 1;
1723 }
1724 else if (fits_in_signed_byte (num))
1725 {
1726 t.bitfield.imm8 = 1;
1727 t.bitfield.imm8s = 1;
1728 t.bitfield.imm16 = 1;
1729 t.bitfield.imm32 = 1;
1730 t.bitfield.imm32s = 1;
1731 }
1732 else if (fits_in_unsigned_byte (num))
1733 {
1734 t.bitfield.imm8 = 1;
1735 t.bitfield.imm16 = 1;
1736 t.bitfield.imm32 = 1;
1737 t.bitfield.imm32s = 1;
1738 }
1739 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1740 {
1741 t.bitfield.imm16 = 1;
1742 t.bitfield.imm32 = 1;
1743 t.bitfield.imm32s = 1;
1744 }
1745 else if (fits_in_signed_long (num))
1746 {
1747 t.bitfield.imm32 = 1;
1748 t.bitfield.imm32s = 1;
1749 }
1750 else if (fits_in_unsigned_long (num))
1751 t.bitfield.imm32 = 1;
1752
1753 return t;
47926f60 1754}
252b5132 1755
847f7ad4 1756static offsetT
e3bb37b5 1757offset_in_range (offsetT val, int size)
847f7ad4 1758{
508866be 1759 addressT mask;
ba2adb93 1760
847f7ad4
AM		 1761 switch (size)
1762 {
508866be
L		 1763 case 1: mask = ((addressT) 1 << 8) - 1; break;
1764 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1765 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1766#ifdef BFD64
1767 case 8: mask = ((addressT) 2 << 63) - 1; break;
1768#endif
47926f60 1769 default: abort ();
847f7ad4
AM		 1770 }
1771
9de868bf
L		 1772#ifdef BFD64
1773 /* If BFD64, sign extend val for 32bit address mode. */
1774 if (flag_code != CODE_64BIT
1775 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1776 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1777 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1778#endif
ba2adb93 1779
47926f60 1780 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1781 {
1782 char buf1[40], buf2[40];
1783
1784 sprint_value (buf1, val);
1785 sprint_value (buf2, val & mask);
1786 as_warn (_("%s shortened to %s"), buf1, buf2);
1787 }
1788 return val & mask;
1789}
1790
c32fa91d
L		 1791enum PREFIX_GROUP
1792{
1793 PREFIX_EXIST = 0,
1794 PREFIX_LOCK,
1795 PREFIX_REP,
1796 PREFIX_OTHER
1797};
1798
1799/* Returns
1800 a. PREFIX_EXIST if attempting to add a prefix where one from the
1801 same class already exists.
1802 b. PREFIX_LOCK if lock prefix is added.
1803 c. PREFIX_REP if rep/repne prefix is added.
1804 d. PREFIX_OTHER if other prefix is added.
1805 */
1806
1807static enum PREFIX_GROUP
e3bb37b5 1808add_prefix (unsigned int prefix)
252b5132 1809{
c32fa91d 1810 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1811 unsigned int q;
252b5132 1812
29b0f896
AM		 1813 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1814 && flag_code == CODE_64BIT)
b1905489 1815 {
161a04f6
L		 1816 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1817 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1818 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1819 ret = PREFIX_EXIST;
b1905489
JB		 1820 q = REX_PREFIX;
1821 }
3e73aa7c 1822 else
b1905489
JB		 1823 {
1824 switch (prefix)
1825 {
1826 default:
1827 abort ();
1828
1829 case CS_PREFIX_OPCODE:
1830 case DS_PREFIX_OPCODE:
1831 case ES_PREFIX_OPCODE:
1832 case FS_PREFIX_OPCODE:
1833 case GS_PREFIX_OPCODE:
1834 case SS_PREFIX_OPCODE:
1835 q = SEG_PREFIX;
1836 break;
1837
1838 case REPNE_PREFIX_OPCODE:
1839 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1840 q = REP_PREFIX;
1841 ret = PREFIX_REP;
1842 break;
1843
b1905489 1844 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1845 q = LOCK_PREFIX;
1846 ret = PREFIX_LOCK;
b1905489
JB		 1847 break;
1848
1849 case FWAIT_OPCODE:
1850 q = WAIT_PREFIX;
1851 break;
1852
1853 case ADDR_PREFIX_OPCODE:
1854 q = ADDR_PREFIX;
1855 break;
1856
1857 case DATA_PREFIX_OPCODE:
1858 q = DATA_PREFIX;
1859 break;
1860 }
1861 if (i.prefix[q] != 0)
c32fa91d 1862 ret = PREFIX_EXIST;
b1905489 1863 }
252b5132 1864
b1905489 1865 if (ret)
252b5132 1866 {
b1905489
JB		 1867 if (!i.prefix[q])
1868 ++i.prefixes;
1869 i.prefix[q] |= prefix;
252b5132 1870 }
b1905489
JB		 1871 else
1872 as_bad (_("same type of prefix used twice"));
252b5132 1873
252b5132
RH		 1874 return ret;
1875}
1876
1877static void
e3bb37b5 1878set_code_flag (int value)
eecb386c 1879{
1e9cc1c2 1880 flag_code = (enum flag_code) value;
40fb9820
L		 1881 if (flag_code == CODE_64BIT)
1882 {
1883 cpu_arch_flags.bitfield.cpu64 = 1;
1884 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1885 }
1886 else
1887 {
1888 cpu_arch_flags.bitfield.cpu64 = 0;
1889 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1890 }
1891 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1892 {
1893 as_bad (_("64bit mode not supported on this CPU."));
1894 }
40fb9820 1895 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1896 {
1897 as_bad (_("32bit mode not supported on this CPU."));
1898 }
eecb386c
AM		 1899 stackop_size = '\0';
1900}
1901
1902static void
e3bb37b5 1903set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1904{
1e9cc1c2 1905 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1906 if (flag_code != CODE_16BIT)
1907 abort ();
1908 cpu_arch_flags.bitfield.cpu64 = 0;
1909 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1910 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1911}
1912
1913static void
e3bb37b5 1914set_intel_syntax (int syntax_flag)
252b5132
RH		 1915{
1916 /* Find out if register prefixing is specified. */
1917 int ask_naked_reg = 0;
1918
1919 SKIP_WHITESPACE ();
29b0f896 1920 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1921 {
1922 char *string = input_line_pointer;
1923 int e = get_symbol_end ();
1924
47926f60 1925 if (strcmp (string, "prefix") == 0)
252b5132 1926 ask_naked_reg = 1;
47926f60 1927 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1928 ask_naked_reg = -1;
1929 else
d0b47220 1930 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1931 *input_line_pointer = e;
1932 }
1933 demand_empty_rest_of_line ();
c3332e24 1934
252b5132
RH		 1935 intel_syntax = syntax_flag;
1936
1937 if (ask_naked_reg == 0)
f86103b7
AM		 1938 allow_naked_reg = (intel_syntax
1939 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1940 else
1941 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1942
ee86248c 1943 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1944
e4a3b5a4 1945 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1946 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1947 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1948}
1949
1efbbeb4
L		 1950static void
1951set_intel_mnemonic (int mnemonic_flag)
1952{
e1d4d893 1953 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1954}
1955
db51cc60
L		 1956static void
1957set_allow_index_reg (int flag)
1958{
1959 allow_index_reg = flag;
1960}
1961
cb19c032
L		 1962static void
1963set_sse_check (int dummy ATTRIBUTE_UNUSED)
1964{
1965 SKIP_WHITESPACE ();
1966
1967 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1968 {
1969 char *string = input_line_pointer;
1970 int e = get_symbol_end ();
1971
1972 if (strcmp (string, "none") == 0)
1973 sse_check = sse_check_none;
1974 else if (strcmp (string, "warning") == 0)
1975 sse_check = sse_check_warning;
1976 else if (strcmp (string, "error") == 0)
1977 sse_check = sse_check_error;
1978 else
1979 as_bad (_("bad argument to sse_check directive."));
1980 *input_line_pointer = e;
1981 }
1982 else
1983 as_bad (_("missing argument for sse_check directive"));
1984
1985 demand_empty_rest_of_line ();
1986}
1987
8a9036a4
L		 1988static void
1989check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1990 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1991{
1992#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1993 static const char *arch;
1994
1995 /* Intel LIOM is only supported on ELF. */
1996 if (!IS_ELF)
1997 return;
1998
1999 if (!arch)
2000 {
2001 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2002 use default_arch. */
2003 arch = cpu_arch_name;
2004 if (!arch)
2005 arch = default_arch;
2006 }
2007
3632d14b 2008 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2009 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2010 || new_flag.bitfield.cpul1om)
8a9036a4 2011 return;
76ba9986 2012
8a9036a4
L		 2013 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2014#endif
2015}
2016
e413e4e9 2017static void
e3bb37b5 2018set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2019{
47926f60 2020 SKIP_WHITESPACE ();
e413e4e9 2021
29b0f896 2022 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2023 {
2024 char *string = input_line_pointer;
2025 int e = get_symbol_end ();
91d6fa6a 2026 unsigned int j;
40fb9820 2027 i386_cpu_flags flags;
e413e4e9 2028
91d6fa6a 2029 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2030 {
91d6fa6a 2031 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2032 {
91d6fa6a 2033 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2034
5c6af06e
JB		 2035 if (*string != '.')
2036 {
91d6fa6a 2037 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2038 cpu_sub_arch_name = NULL;
91d6fa6a 2039 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2040 if (flag_code == CODE_64BIT)
2041 {
2042 cpu_arch_flags.bitfield.cpu64 = 1;
2043 cpu_arch_flags.bitfield.cpuno64 = 0;
2044 }
2045 else
2046 {
2047 cpu_arch_flags.bitfield.cpu64 = 0;
2048 cpu_arch_flags.bitfield.cpuno64 = 1;
2049 }
91d6fa6a
NC		 2050 cpu_arch_isa = cpu_arch[j].type;
2051 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2052 if (!cpu_arch_tune_set)
2053 {
2054 cpu_arch_tune = cpu_arch_isa;
2055 cpu_arch_tune_flags = cpu_arch_isa_flags;
2056 }
5c6af06e
JB		 2057 break;
2058 }
40fb9820 2059
309d3373
JB		 2060 if (strncmp (string + 1, "no", 2))
2061 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2062 cpu_arch[j].flags);
309d3373
JB		 2063 else
2064 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2065 cpu_arch[j].flags);
0dfbf9d7 2066 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2067 {
6305a203
L		 2068 if (cpu_sub_arch_name)
2069 {
2070 char *name = cpu_sub_arch_name;
2071 cpu_sub_arch_name = concat (name,
91d6fa6a 2072 cpu_arch[j].name,
1bf57e9f 2073 (const char *) NULL);
6305a203
L		 2074 free (name);
2075 }
2076 else
91d6fa6a 2077 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2078 cpu_arch_flags = flags;
5c6af06e
JB		 2079 }
2080 *input_line_pointer = e;
2081 demand_empty_rest_of_line ();
2082 return;
e413e4e9
AM		 2083 }
2084 }
91d6fa6a 2085 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2086 as_bad (_("no such architecture: `%s'"), string);
2087
2088 *input_line_pointer = e;
2089 }
2090 else
2091 as_bad (_("missing cpu architecture"));
2092
fddf5b5b
AM		 2093 no_cond_jump_promotion = 0;
2094 if (*input_line_pointer == ','
29b0f896 2095 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2096 {
2097 char *string = ++input_line_pointer;
2098 int e = get_symbol_end ();
2099
2100 if (strcmp (string, "nojumps") == 0)
2101 no_cond_jump_promotion = 1;
2102 else if (strcmp (string, "jumps") == 0)
2103 ;
2104 else
2105 as_bad (_("no such architecture modifier: `%s'"), string);
2106
2107 *input_line_pointer = e;
2108 }
2109
e413e4e9
AM		 2110 demand_empty_rest_of_line ();
2111}
2112
8a9036a4
L		 2113enum bfd_architecture
2114i386_arch (void)
2115{
3632d14b 2116 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2117 {
2118 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2119 || flag_code != CODE_64BIT)
2120 as_fatal (_("Intel L1OM is 64bit ELF only"));
2121 return bfd_arch_l1om;
2122 }
2123 else
2124 return bfd_arch_i386;
2125}
2126
b9d79e03
JH		 2127unsigned long
2128i386_mach ()
2129{
2130 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2131 {
3632d14b 2132 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2133 {
2134 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2135 as_fatal (_("Intel L1OM is 64bit ELF only"));
2136 return bfd_mach_l1om;
2137 }
2138 else
2139 return bfd_mach_x86_64;
2140 }
b9d79e03
JH		 2141 else if (!strcmp (default_arch, "i386"))
2142 return bfd_mach_i386_i386;
2143 else
2144 as_fatal (_("Unknown architecture"));
2145}
b9d79e03 2146\f
252b5132
RH		 2147void
2148md_begin ()
2149{
2150 const char *hash_err;
2151
47926f60 2152 /* Initialize op_hash hash table. */
252b5132
RH		 2153 op_hash = hash_new ();
2154
2155 {
d3ce72d0 2156 const insn_template *optab;
29b0f896 2157 templates *core_optab;
252b5132 2158
47926f60
KH		 2159 /* Setup for loop. */
2160 optab = i386_optab;
252b5132
RH		 2161 core_optab = (templates *) xmalloc (sizeof (templates));
2162 core_optab->start = optab;
2163
2164 while (1)
2165 {
2166 ++optab;
2167 if (optab->name == NULL
2168 || strcmp (optab->name, (optab - 1)->name) != 0)
2169 {
2170 /* different name --> ship out current template list;
47926f60 2171 add to hash table; & begin anew. */
252b5132
RH		 2172 core_optab->end = optab;
2173 hash_err = hash_insert (op_hash,
2174 (optab - 1)->name,
5a49b8ac 2175 (void *) core_optab);
252b5132
RH		 2176 if (hash_err)
2177 {
252b5132
RH		 2178 as_fatal (_("Internal Error: Can't hash %s: %s"),
2179 (optab - 1)->name,
2180 hash_err);
2181 }
2182 if (optab->name == NULL)
2183 break;
2184 core_optab = (templates *) xmalloc (sizeof (templates));
2185 core_optab->start = optab;
2186 }
2187 }
2188 }
2189
47926f60 2190 /* Initialize reg_hash hash table. */
252b5132
RH		 2191 reg_hash = hash_new ();
2192 {
29b0f896 2193 const reg_entry *regtab;
c3fe08fa 2194 unsigned int regtab_size = i386_regtab_size;
252b5132 2195
c3fe08fa 2196 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2197 {
5a49b8ac 2198 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2199 if (hash_err)
3e73aa7c
JH		 2200 as_fatal (_("Internal Error: Can't hash %s: %s"),
2201 regtab->reg_name,
2202 hash_err);
252b5132
RH		 2203 }
2204 }
2205
47926f60 2206 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2207 {
29b0f896
AM		 2208 int c;
2209 char *p;
252b5132
RH		 2210
2211 for (c = 0; c < 256; c++)
2212 {
3882b010 2213 if (ISDIGIT (c))
252b5132
RH		 2214 {
2215 digit_chars[c] = c;
2216 mnemonic_chars[c] = c;
2217 register_chars[c] = c;
2218 operand_chars[c] = c;
2219 }
3882b010 2220 else if (ISLOWER (c))
252b5132
RH		 2221 {
2222 mnemonic_chars[c] = c;
2223 register_chars[c] = c;
2224 operand_chars[c] = c;
2225 }
3882b010 2226 else if (ISUPPER (c))
252b5132 2227 {
3882b010 2228 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2229 register_chars[c] = mnemonic_chars[c];
2230 operand_chars[c] = c;
2231 }
2232
3882b010 2233 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2234 identifier_chars[c] = c;
2235 else if (c >= 128)
2236 {
2237 identifier_chars[c] = c;
2238 operand_chars[c] = c;
2239 }
2240 }
2241
2242#ifdef LEX_AT
2243 identifier_chars['@'] = '@';
32137342
NC		 2244#endif
2245#ifdef LEX_QM
2246 identifier_chars['?'] = '?';
2247 operand_chars['?'] = '?';
252b5132 2248#endif
252b5132 2249 digit_chars['-'] = '-';
c0f3af97 2250 mnemonic_chars['_'] = '_';
791fe849 2251 mnemonic_chars['-'] = '-';
0003779b 2252 mnemonic_chars['.'] = '.';
252b5132
RH		 2253 identifier_chars['_'] = '_';
2254 identifier_chars['.'] = '.';
2255
2256 for (p = operand_special_chars; *p != '\0'; p++)
2257 operand_chars[(unsigned char) *p] = *p;
2258 }
2259
2260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2261 if (IS_ELF)
252b5132
RH		 2262 {
2263 record_alignment (text_section, 2);
2264 record_alignment (data_section, 2);
2265 record_alignment (bss_section, 2);
2266 }
2267#endif
a4447b93
RH		 2268
2269 if (flag_code == CODE_64BIT)
2270 {
2271 x86_dwarf2_return_column = 16;
2272 x86_cie_data_alignment = -8;
2273 }
2274 else
2275 {
2276 x86_dwarf2_return_column = 8;
2277 x86_cie_data_alignment = -4;
2278 }
252b5132
RH		 2279}
2280
2281void
e3bb37b5 2282i386_print_statistics (FILE *file)
252b5132
RH		 2283{
2284 hash_print_statistics (file, "i386 opcode", op_hash);
2285 hash_print_statistics (file, "i386 register", reg_hash);
2286}
2287\f
252b5132
RH		 2288#ifdef DEBUG386
2289
ce8a8b2f 2290/* Debugging routines for md_assemble. */
d3ce72d0 2291static void pte (insn_template *);
40fb9820 2292static void pt (i386_operand_type);
e3bb37b5
L		 2293static void pe (expressionS *);
2294static void ps (symbolS *);
252b5132
RH		 2295
2296static void
e3bb37b5 2297pi (char *line, i386_insn *x)
252b5132 2298{
09f131f2 2299 unsigned int i;
252b5132
RH		 2300
2301 fprintf (stdout, "%s: template ", line);
2302 pte (&x->tm);
09f131f2
JH		 2303 fprintf (stdout, " address: base %s index %s scale %x\n",
2304 x->base_reg ? x->base_reg->reg_name : "none",
2305 x->index_reg ? x->index_reg->reg_name : "none",
2306 x->log2_scale_factor);
2307 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2308 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2309 fprintf (stdout, " sib: base %x index %x scale %x\n",
2310 x->sib.base, x->sib.index, x->sib.scale);
2311 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2312 (x->rex & REX_W) != 0,
2313 (x->rex & REX_R) != 0,
2314 (x->rex & REX_X) != 0,
2315 (x->rex & REX_B) != 0);
252b5132
RH		 2316 for (i = 0; i < x->operands; i++)
2317 {
2318 fprintf (stdout, " #%d: ", i + 1);
2319 pt (x->types[i]);
2320 fprintf (stdout, "\n");
40fb9820
L		 2321 if (x->types[i].bitfield.reg8
2322 || x->types[i].bitfield.reg16
2323 || x->types[i].bitfield.reg32
2324 || x->types[i].bitfield.reg64
2325 || x->types[i].bitfield.regmmx
2326 || x->types[i].bitfield.regxmm
c0f3af97 2327 || x->types[i].bitfield.regymm
40fb9820
L		 2328 || x->types[i].bitfield.sreg2
2329 || x->types[i].bitfield.sreg3
2330 || x->types[i].bitfield.control
2331 || x->types[i].bitfield.debug
2332 || x->types[i].bitfield.test)
520dc8e8 2333 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2334 if (operand_type_check (x->types[i], imm))
520dc8e8 2335 pe (x->op[i].imms);
40fb9820 2336 if (operand_type_check (x->types[i], disp))
520dc8e8 2337 pe (x->op[i].disps);
252b5132
RH		 2338 }
2339}
2340
2341static void
d3ce72d0 2342pte (insn_template *t)
252b5132 2343{
09f131f2 2344 unsigned int i;
252b5132 2345 fprintf (stdout, " %d operands ", t->operands);
47926f60 2346 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2347 if (t->extension_opcode != None)
2348 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2349 if (t->opcode_modifier.d)
252b5132 2350 fprintf (stdout, "D");
40fb9820 2351 if (t->opcode_modifier.w)
252b5132
RH		 2352 fprintf (stdout, "W");
2353 fprintf (stdout, "\n");
2354 for (i = 0; i < t->operands; i++)
2355 {
2356 fprintf (stdout, " #%d type ", i + 1);
2357 pt (t->operand_types[i]);
2358 fprintf (stdout, "\n");
2359 }
2360}
2361
2362static void
e3bb37b5 2363pe (expressionS *e)
252b5132 2364{
24eab124 2365 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2366 fprintf (stdout, " add_number %ld (%lx)\n",
2367 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2368 if (e->X_add_symbol)
2369 {
2370 fprintf (stdout, " add_symbol ");
2371 ps (e->X_add_symbol);
2372 fprintf (stdout, "\n");
2373 }
2374 if (e->X_op_symbol)
2375 {
2376 fprintf (stdout, " op_symbol ");
2377 ps (e->X_op_symbol);
2378 fprintf (stdout, "\n");
2379 }
2380}
2381
2382static void
e3bb37b5 2383ps (symbolS *s)
252b5132
RH		 2384{
2385 fprintf (stdout, "%s type %s%s",
2386 S_GET_NAME (s),
2387 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2388 segment_name (S_GET_SEGMENT (s)));
2389}
2390
7b81dfbb 2391static struct type_name
252b5132 2392 {
40fb9820
L		 2393 i386_operand_type mask;
2394 const char *name;
252b5132 2395 }
7b81dfbb 2396const type_names[] =
252b5132 2397{
40fb9820
L		 2398 { OPERAND_TYPE_REG8, "r8" },
2399 { OPERAND_TYPE_REG16, "r16" },
2400 { OPERAND_TYPE_REG32, "r32" },
2401 { OPERAND_TYPE_REG64, "r64" },
2402 { OPERAND_TYPE_IMM8, "i8" },
2403 { OPERAND_TYPE_IMM8, "i8s" },
2404 { OPERAND_TYPE_IMM16, "i16" },
2405 { OPERAND_TYPE_IMM32, "i32" },
2406 { OPERAND_TYPE_IMM32S, "i32s" },
2407 { OPERAND_TYPE_IMM64, "i64" },
2408 { OPERAND_TYPE_IMM1, "i1" },
2409 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2410 { OPERAND_TYPE_DISP8, "d8" },
2411 { OPERAND_TYPE_DISP16, "d16" },
2412 { OPERAND_TYPE_DISP32, "d32" },
2413 { OPERAND_TYPE_DISP32S, "d32s" },
2414 { OPERAND_TYPE_DISP64, "d64" },
2415 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2416 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2417 { OPERAND_TYPE_CONTROL, "control reg" },
2418 { OPERAND_TYPE_TEST, "test reg" },
2419 { OPERAND_TYPE_DEBUG, "debug reg" },
2420 { OPERAND_TYPE_FLOATREG, "FReg" },
2421 { OPERAND_TYPE_FLOATACC, "FAcc" },
2422 { OPERAND_TYPE_SREG2, "SReg2" },
2423 { OPERAND_TYPE_SREG3, "SReg3" },
2424 { OPERAND_TYPE_ACC, "Acc" },
2425 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2426 { OPERAND_TYPE_REGMMX, "rMMX" },
2427 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2428 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2429 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2430};
2431
2432static void
40fb9820 2433pt (i386_operand_type t)
252b5132 2434{
40fb9820 2435 unsigned int j;
c6fb90c8 2436 i386_operand_type a;
252b5132 2437
40fb9820 2438 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2439 {
2440 a = operand_type_and (t, type_names[j].mask);
0349dc08 2441 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2442 fprintf (stdout, "%s, ", type_names[j].name);
2443 }
252b5132
RH		 2444 fflush (stdout);
2445}
2446
2447#endif /* DEBUG386 */
2448\f
252b5132 2449static bfd_reloc_code_real_type
3956db08 2450reloc (unsigned int size,
64e74474
AM		 2451 int pcrel,
2452 int sign,
2453 bfd_reloc_code_real_type other)
252b5132 2454{
47926f60 2455 if (other != NO_RELOC)
3956db08 2456 {
91d6fa6a 2457 reloc_howto_type *rel;
3956db08
JB		 2458
2459 if (size == 8)
2460 switch (other)
2461 {
64e74474
AM		 2462 case BFD_RELOC_X86_64_GOT32:
2463 return BFD_RELOC_X86_64_GOT64;
2464 break;
2465 case BFD_RELOC_X86_64_PLTOFF64:
2466 return BFD_RELOC_X86_64_PLTOFF64;
2467 break;
2468 case BFD_RELOC_X86_64_GOTPC32:
2469 other = BFD_RELOC_X86_64_GOTPC64;
2470 break;
2471 case BFD_RELOC_X86_64_GOTPCREL:
2472 other = BFD_RELOC_X86_64_GOTPCREL64;
2473 break;
2474 case BFD_RELOC_X86_64_TPOFF32:
2475 other = BFD_RELOC_X86_64_TPOFF64;
2476 break;
2477 case BFD_RELOC_X86_64_DTPOFF32:
2478 other = BFD_RELOC_X86_64_DTPOFF64;
2479 break;
2480 default:
2481 break;
3956db08 2482 }
e05278af
JB		 2483
2484 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2485 if (size == 4 && flag_code != CODE_64BIT)
2486 sign = -1;
2487
91d6fa6a
NC		 2488 rel = bfd_reloc_type_lookup (stdoutput, other);
2489 if (!rel)
3956db08 2490 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2491 else if (size != bfd_get_reloc_size (rel))
3956db08 2492 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2493 bfd_get_reloc_size (rel),
3956db08 2494 size);
91d6fa6a 2495 else if (pcrel && !rel->pc_relative)
3956db08 2496 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2497 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2498 && !sign)
91d6fa6a 2499 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2500 && sign > 0))
3956db08
JB		 2501 as_bad (_("relocated field and relocation type differ in signedness"));
2502 else
2503 return other;
2504 return NO_RELOC;
2505 }
252b5132
RH		 2506
2507 if (pcrel)
2508 {
3e73aa7c 2509 if (!sign)
3956db08 2510 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2511 switch (size)
2512 {
2513 case 1: return BFD_RELOC_8_PCREL;
2514 case 2: return BFD_RELOC_16_PCREL;
2515 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2516 case 8: return BFD_RELOC_64_PCREL;
252b5132 2517 }
3956db08 2518 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2519 }
2520 else
2521 {
3956db08 2522 if (sign > 0)
e5cb08ac 2523 switch (size)
3e73aa7c
JH		 2524 {
2525 case 4: return BFD_RELOC_X86_64_32S;
2526 }
2527 else
2528 switch (size)
2529 {
2530 case 1: return BFD_RELOC_8;
2531 case 2: return BFD_RELOC_16;
2532 case 4: return BFD_RELOC_32;
2533 case 8: return BFD_RELOC_64;
2534 }
3956db08
JB		 2535 as_bad (_("cannot do %s %u byte relocation"),
2536 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2537 }
2538
0cc9e1d3 2539 return NO_RELOC;
252b5132
RH		 2540}
2541
47926f60
KH		 2542/* Here we decide which fixups can be adjusted to make them relative to
2543 the beginning of the section instead of the symbol. Basically we need
2544 to make sure that the dynamic relocations are done correctly, so in
2545 some cases we force the original symbol to be used. */
2546
252b5132 2547int
e3bb37b5 2548tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2549{
6d249963 2550#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2551 if (!IS_ELF)
31312f95
AM		 2552 return 1;
2553
a161fe53
AM		 2554 /* Don't adjust pc-relative references to merge sections in 64-bit
2555 mode. */
2556 if (use_rela_relocations
2557 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2558 && fixP->fx_pcrel)
252b5132 2559 return 0;
31312f95 2560
8d01d9a9
AJ		 2561 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2562 and changed later by validate_fix. */
2563 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2564 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2565 return 0;
2566
ce8a8b2f 2567 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2568 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2569 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2570 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2571 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2572 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2573 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2574 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2575 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2576 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2577 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2578 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2579 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2580 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2581 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2582 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2583 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2584 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2585 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2586 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2587 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2588 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2589 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2590 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2591 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2592 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2593 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2594 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2595 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2596 return 0;
31312f95 2597#endif
252b5132
RH		 2598 return 1;
2599}
252b5132 2600
b4cac588 2601static int
e3bb37b5 2602intel_float_operand (const char *mnemonic)
252b5132 2603{
9306ca4a
JB		 2604 /* Note that the value returned is meaningful only for opcodes with (memory)
2605 operands, hence the code here is free to improperly handle opcodes that
2606 have no operands (for better performance and smaller code). */
2607
2608 if (mnemonic[0] != 'f')
2609 return 0; /* non-math */
2610
2611 switch (mnemonic[1])
2612 {
2613 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2614 the fs segment override prefix not currently handled because no
2615 call path can make opcodes without operands get here */
2616 case 'i':
2617 return 2 /* integer op */;
2618 case 'l':
2619 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2620 return 3; /* fldcw/fldenv */
2621 break;
2622 case 'n':
2623 if (mnemonic[2] != 'o' /* fnop */)
2624 return 3; /* non-waiting control op */
2625 break;
2626 case 'r':
2627 if (mnemonic[2] == 's')
2628 return 3; /* frstor/frstpm */
2629 break;
2630 case 's':
2631 if (mnemonic[2] == 'a')
2632 return 3; /* fsave */
2633 if (mnemonic[2] == 't')
2634 {
2635 switch (mnemonic[3])
2636 {
2637 case 'c': /* fstcw */
2638 case 'd': /* fstdw */
2639 case 'e': /* fstenv */
2640 case 's': /* fsts[gw] */
2641 return 3;
2642 }
2643 }
2644 break;
2645 case 'x':
2646 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2647 return 0; /* fxsave/fxrstor are not really math ops */
2648 break;
2649 }
252b5132 2650
9306ca4a 2651 return 1;
252b5132
RH		 2652}
2653
c0f3af97
L		 2654/* Build the VEX prefix. */
2655
2656static void
d3ce72d0 2657build_vex_prefix (const insn_template *t)
c0f3af97
L		 2658{
2659 unsigned int register_specifier;
2660 unsigned int implied_prefix;
2661 unsigned int vector_length;
2662
2663 /* Check register specifier. */
2664 if (i.vex.register_specifier)
2665 {
2666 register_specifier = i.vex.register_specifier->reg_num;
2667 if ((i.vex.register_specifier->reg_flags & RegRex))
2668 register_specifier += 8;
2669 register_specifier = ~register_specifier & 0xf;
2670 }
2671 else
2672 register_specifier = 0xf;
2673
fa99fab2
L		 2674 /* Use 2-byte VEX prefix by swappping destination and source
2675 operand. */
2676 if (!i.swap_operand
2677 && i.operands == i.reg_operands
7f399153 2678 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2679 && i.tm.opcode_modifier.s
2680 && i.rex == REX_B)
2681 {
2682 unsigned int xchg = i.operands - 1;
2683 union i386_op temp_op;
2684 i386_operand_type temp_type;
2685
2686 temp_type = i.types[xchg];
2687 i.types[xchg] = i.types[0];
2688 i.types[0] = temp_type;
2689 temp_op = i.op[xchg];
2690 i.op[xchg] = i.op[0];
2691 i.op[0] = temp_op;
2692
9c2799c2 2693 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2694
2695 i.rex = REX_R;
2696 xchg = i.rm.regmem;
2697 i.rm.regmem = i.rm.reg;
2698 i.rm.reg = xchg;
2699
2700 /* Use the next insn. */
2701 i.tm = t[1];
2702 }
2703
e3c58833 2704 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2705
2706 switch ((i.tm.base_opcode >> 8) & 0xff)
2707 {
2708 case 0:
2709 implied_prefix = 0;
2710 break;
2711 case DATA_PREFIX_OPCODE:
2712 implied_prefix = 1;
2713 break;
2714 case REPE_PREFIX_OPCODE:
2715 implied_prefix = 2;
2716 break;
2717 case REPNE_PREFIX_OPCODE:
2718 implied_prefix = 3;
2719 break;
2720 default:
2721 abort ();
2722 }
2723
2724 /* Use 2-byte VEX prefix if possible. */
7f399153 2725 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2726 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2727 {
2728 /* 2-byte VEX prefix. */
2729 unsigned int r;
2730
2731 i.vex.length = 2;
2732 i.vex.bytes[0] = 0xc5;
2733
2734 /* Check the REX.R bit. */
2735 r = (i.rex & REX_R) ? 0 : 1;
2736 i.vex.bytes[1] = (r << 7
2737 | register_specifier << 3
2738 | vector_length << 2
2739 | implied_prefix);
2740 }
2741 else
2742 {
2743 /* 3-byte VEX prefix. */
2744 unsigned int m, w;
2745
f88c9eb0
SP		 2746 i.vex.length = 3;
2747 i.vex.bytes[0] = 0xc4;
2748
7f399153 2749 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2750 {
7f399153
L		 2751 case VEX0F:
2752 m = 0x1;
2753 break;
2754 case VEX0F38:
2755 m = 0x2;
2756 break;
2757 case VEX0F3A:
2758 m = 0x3;
2759 break;
2760 case XOP08:
5dd85c99
SP		 2761 m = 0x8;
2762 i.vex.bytes[0] = 0x8f;
7f399153
L		 2763 break;
2764 case XOP09:
f88c9eb0
SP		 2765 m = 0x9;
2766 i.vex.bytes[0] = 0x8f;
7f399153
L		 2767 break;
2768 case XOP0A:
f88c9eb0
SP		 2769 m = 0xa;
2770 i.vex.bytes[0] = 0x8f;
7f399153
L		 2771 break;
2772 default:
2773 abort ();
f88c9eb0 2774 }
c0f3af97 2775
c0f3af97
L		 2776 /* The high 3 bits of the second VEX byte are 1's compliment
2777 of RXB bits from REX. */
2778 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2779
2780 /* Check the REX.W bit. */
2781 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2782 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2783 {
2784 if (w)
2785 abort ();
2786
1ef99a7b 2787 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2788 w = 1;
2789 }
2790
2791 i.vex.bytes[2] = (w << 7
2792 | register_specifier << 3
2793 | vector_length << 2
2794 | implied_prefix);
2795 }
2796}
2797
65da13b5
L		 2798static void
2799process_immext (void)
2800{
2801 expressionS *exp;
2802
2803 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2804 {
1fed0ba1
L		 2805 /* SSE3 Instructions have the fixed operands with an opcode
2806 suffix which is coded in the same place as an 8-bit immediate
2807 field would be. Here we check those operands and remove them
2808 afterwards. */
65da13b5
L		 2809 unsigned int x;
2810
2811 for (x = 0; x < i.operands; x++)
2812 if (i.op[x].regs->reg_num != x)
2813 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2814 register_prefix, i.op[x].regs->reg_name, x + 1,
2815 i.tm.name);
2816
2817 i.operands = 0;
65da13b5
L		 2818 }
2819
c0f3af97 2820 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2821 which is coded in the same place as an 8-bit immediate field
2822 would be. Here we fake an 8-bit immediate operand from the
2823 opcode suffix stored in tm.extension_opcode.
2824
c1e679ec 2825 AVX instructions also use this encoding, for some of
c0f3af97 2826 3 argument instructions. */
65da13b5 2827
9c2799c2 2828 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2829 && (i.operands <= 2
2830 || (i.tm.opcode_modifier.vex
2831 && i.operands <= 4)));
65da13b5
L		 2832
2833 exp = &im_expressions[i.imm_operands++];
2834 i.op[i.operands].imms = exp;
2835 i.types[i.operands] = imm8;
2836 i.operands++;
2837 exp->X_op = O_constant;
2838 exp->X_add_number = i.tm.extension_opcode;
2839 i.tm.extension_opcode = None;
2840}
2841
252b5132
RH		 2842/* This is the guts of the machine-dependent assembler. LINE points to a
2843 machine dependent instruction. This function is supposed to emit
2844 the frags/bytes it assembles to. */
2845
2846void
65da13b5 2847md_assemble (char *line)
252b5132 2848{
40fb9820 2849 unsigned int j;
252b5132 2850 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2851 const insn_template *t;
252b5132 2852
47926f60 2853 /* Initialize globals. */
252b5132
RH		 2854 memset (&i, '\0', sizeof (i));
2855 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2856 i.reloc[j] = NO_RELOC;
252b5132
RH		 2857 memset (disp_expressions, '\0', sizeof (disp_expressions));
2858 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2859 save_stack_p = save_stack;
252b5132
RH		 2860
2861 /* First parse an instruction mnemonic & call i386_operand for the operands.
2862 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2863 start of a (possibly prefixed) mnemonic. */
252b5132 2864
29b0f896
AM		 2865 line = parse_insn (line, mnemonic);
2866 if (line == NULL)
2867 return;
252b5132 2868
29b0f896 2869 line = parse_operands (line, mnemonic);
ee86248c 2870 this_operand = -1;
29b0f896
AM		 2871 if (line == NULL)
2872 return;
252b5132 2873
29b0f896
AM		 2874 /* Now we've parsed the mnemonic into a set of templates, and have the
2875 operands at hand. */
2876
2877 /* All intel opcodes have reversed operands except for "bound" and
2878 "enter". We also don't reverse intersegment "jmp" and "call"
2879 instructions with 2 immediate operands so that the immediate segment
050dfa73 2880 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2881 if (intel_syntax
2882 && i.operands > 1
29b0f896 2883 && (strcmp (mnemonic, "bound") != 0)
30123838 2884 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2885 && !(operand_type_check (i.types[0], imm)
2886 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2887 swap_operands ();
2888
ec56d5c0
JB		 2889 /* The order of the immediates should be reversed
2890 for 2 immediates extrq and insertq instructions */
2891 if (i.imm_operands == 2
2892 && (strcmp (mnemonic, "extrq") == 0
2893 || strcmp (mnemonic, "insertq") == 0))
2894 swap_2_operands (0, 1);
2895
29b0f896
AM		 2896 if (i.imm_operands)
2897 optimize_imm ();
2898
b300c311
L		 2899 /* Don't optimize displacement for movabs since it only takes 64bit
2900 displacement. */
2901 if (i.disp_operands
2902 && (flag_code != CODE_64BIT
2903 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2904 optimize_disp ();
2905
2906 /* Next, we find a template that matches the given insn,
2907 making sure the overlap of the given operands types is consistent
2908 with the template operand types. */
252b5132 2909
fa99fab2 2910 if (!(t = match_template ()))
29b0f896 2911 return;
252b5132 2912
daf50ae7 2913 if (sse_check != sse_check_none
81f8a913 2914 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2915 && (i.tm.cpu_flags.bitfield.cpusse
2916 || i.tm.cpu_flags.bitfield.cpusse2
2917 || i.tm.cpu_flags.bitfield.cpusse3
2918 || i.tm.cpu_flags.bitfield.cpussse3
2919 || i.tm.cpu_flags.bitfield.cpusse4_1
2920 || i.tm.cpu_flags.bitfield.cpusse4_2))
2921 {
2922 (sse_check == sse_check_warning
2923 ? as_warn
2924 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2925 }
2926
321fd21e
L		 2927 /* Zap movzx and movsx suffix. The suffix has been set from
2928 "word ptr" or "byte ptr" on the source operand in Intel syntax
2929 or extracted from mnemonic in AT&T syntax. But we'll use
2930 the destination register to choose the suffix for encoding. */
2931 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2932 {
321fd21e
L		 2933 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2934 there is no suffix, the default will be byte extension. */
2935 if (i.reg_operands != 2
2936 && !i.suffix
7ab9ffdd 2937 && intel_syntax)
321fd21e
L		 2938 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2939
2940 i.suffix = 0;
cd61ebfe 2941 }
24eab124 2942
40fb9820 2943 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2944 if (!add_prefix (FWAIT_OPCODE))
2945 return;
252b5132 2946
c1ba0266
L		 2947 /* Check for lock without a lockable instruction. Destination operand
2948 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2949 if (i.prefix[LOCK_PREFIX]
2950 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2951 || i.mem_operands == 0
2952 || (i.tm.base_opcode != 0x86
2953 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2954 {
2955 as_bad (_("expecting lockable instruction after `lock'"));
2956 return;
2957 }
2958
29b0f896 2959 /* Check string instruction segment overrides. */
40fb9820 2960 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2961 {
2962 if (!check_string ())
5dd0794d 2963 return;
fc0763e6 2964 i.disp_operands = 0;
29b0f896 2965 }
5dd0794d 2966
29b0f896
AM		 2967 if (!process_suffix ())
2968 return;
e413e4e9 2969
bc0844ae
L		 2970 /* Update operand types. */
2971 for (j = 0; j < i.operands; j++)
2972 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2973
29b0f896
AM		 2974 /* Make still unresolved immediate matches conform to size of immediate
2975 given in i.suffix. */
2976 if (!finalize_imm ())
2977 return;
252b5132 2978
40fb9820 2979 if (i.types[0].bitfield.imm1)
29b0f896 2980 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2981
9afe6eb8
L		 2982 /* We only need to check those implicit registers for instructions
2983 with 3 operands or less. */
2984 if (i.operands <= 3)
2985 for (j = 0; j < i.operands; j++)
2986 if (i.types[j].bitfield.inoutportreg
2987 || i.types[j].bitfield.shiftcount
2988 || i.types[j].bitfield.acc
2989 || i.types[j].bitfield.floatacc)
2990 i.reg_operands--;
40fb9820 2991
c0f3af97
L		 2992 /* ImmExt should be processed after SSE2AVX. */
2993 if (!i.tm.opcode_modifier.sse2avx
2994 && i.tm.opcode_modifier.immext)
65da13b5 2995 process_immext ();
252b5132 2996
29b0f896
AM		 2997 /* For insns with operands there are more diddles to do to the opcode. */
2998 if (i.operands)
2999 {
3000 if (!process_operands ())
3001 return;
3002 }
40fb9820 3003 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3004 {
3005 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3006 as_warn (_("translating to `%sp'"), i.tm.name);
3007 }
252b5132 3008
c0f3af97 3009 if (i.tm.opcode_modifier.vex)
fa99fab2 3010 build_vex_prefix (t);
c0f3af97 3011
5dd85c99
SP		 3012 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3013 instructions may define INT_OPCODE as well, so avoid this corner
3014 case for those instructions that use MODRM. */
3015 if (i.tm.base_opcode == INT_OPCODE
3016 && i.op[0].imms->X_add_number == 3
3017 && !i.tm.opcode_modifier.modrm)
29b0f896
AM		 3018 {
3019 i.tm.base_opcode = INT3_OPCODE;
3020 i.imm_operands = 0;
3021 }
252b5132 3022
40fb9820
L		 3023 if ((i.tm.opcode_modifier.jump
3024 || i.tm.opcode_modifier.jumpbyte
3025 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3026 && i.op[0].disps->X_op == O_constant)
3027 {
3028 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3029 the absolute address given by the constant. Since ix86 jumps and
3030 calls are pc relative, we need to generate a reloc. */
3031 i.op[0].disps->X_add_symbol = &abs_symbol;
3032 i.op[0].disps->X_op = O_symbol;
3033 }
252b5132 3034
40fb9820 3035 if (i.tm.opcode_modifier.rex64)
161a04f6 3036 i.rex |= REX_W;
252b5132 3037
29b0f896
AM		 3038 /* For 8 bit registers we need an empty rex prefix. Also if the
3039 instruction already has a prefix, we need to convert old
3040 registers to new ones. */
773f551c 3041
40fb9820 3042 if ((i.types[0].bitfield.reg8
29b0f896 3043 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3044 || (i.types[1].bitfield.reg8
29b0f896 3045 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3046 || ((i.types[0].bitfield.reg8
3047 || i.types[1].bitfield.reg8)
29b0f896
AM		 3048 && i.rex != 0))
3049 {
3050 int x;
726c5dcd 3051
29b0f896
AM		 3052 i.rex |= REX_OPCODE;
3053 for (x = 0; x < 2; x++)
3054 {
3055 /* Look for 8 bit operand that uses old registers. */
40fb9820 3056 if (i.types[x].bitfield.reg8
29b0f896 3057 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3058 {
29b0f896
AM		 3059 /* In case it is "hi" register, give up. */
3060 if (i.op[x].regs->reg_num > 3)
a540244d 3061 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3062 "instruction requiring REX prefix."),
a540244d 3063 register_prefix, i.op[x].regs->reg_name);
773f551c 3064
29b0f896
AM		 3065 /* Otherwise it is equivalent to the extended register.
3066 Since the encoding doesn't change this is merely
3067 cosmetic cleanup for debug output. */
3068
3069 i.op[x].regs = i.op[x].regs + 8;
773f551c 3070 }
29b0f896
AM		 3071 }
3072 }
773f551c 3073
7ab9ffdd 3074 if (i.rex != 0)
29b0f896
AM		 3075 add_prefix (REX_OPCODE | i.rex);
3076
3077 /* We are ready to output the insn. */
3078 output_insn ();
3079}
3080
3081static char *
e3bb37b5 3082parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3083{
3084 char *l = line;
3085 char *token_start = l;
3086 char *mnem_p;
5c6af06e 3087 int supported;
d3ce72d0 3088 const insn_template *t;
b6169b20 3089 char *dot_p = NULL;
29b0f896
AM		 3090
3091 /* Non-zero if we found a prefix only acceptable with string insns. */
3092 const char *expecting_string_instruction = NULL;
45288df1 3093
29b0f896
AM		 3094 while (1)
3095 {
3096 mnem_p = mnemonic;
3097 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3098 {
b6169b20
L		 3099 if (*mnem_p == '.')
3100 dot_p = mnem_p;
29b0f896
AM		 3101 mnem_p++;
3102 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3103 {
29b0f896
AM		 3104 as_bad (_("no such instruction: `%s'"), token_start);
3105 return NULL;
3106 }
3107 l++;
3108 }
3109 if (!is_space_char (*l)
3110 && *l != END_OF_INSN
e44823cf
JB		 3111 && (intel_syntax
3112 || (*l != PREFIX_SEPARATOR
3113 && *l != ',')))
29b0f896
AM		 3114 {
3115 as_bad (_("invalid character %s in mnemonic"),
3116 output_invalid (*l));
3117 return NULL;
3118 }
3119 if (token_start == l)
3120 {
e44823cf 3121 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3122 as_bad (_("expecting prefix; got nothing"));
3123 else
3124 as_bad (_("expecting mnemonic; got nothing"));
3125 return NULL;
3126 }
45288df1 3127
29b0f896 3128 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3129 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3130
29b0f896
AM		 3131 if (*l != END_OF_INSN
3132 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3133 && current_templates
40fb9820 3134 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3135 {
c6fb90c8 3136 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3137 {
3138 as_bad ((flag_code != CODE_64BIT
3139 ? _("`%s' is only supported in 64-bit mode")
3140 : _("`%s' is not supported in 64-bit mode")),
3141 current_templates->start->name);
3142 return NULL;
3143 }
29b0f896
AM		 3144 /* If we are in 16-bit mode, do not allow addr16 or data16.
3145 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3146 if ((current_templates->start->opcode_modifier.size16
3147 || current_templates->start->opcode_modifier.size32)
29b0f896 3148 && flag_code != CODE_64BIT
40fb9820 3149 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3150 ^ (flag_code == CODE_16BIT)))
3151 {
3152 as_bad (_("redundant %s prefix"),
3153 current_templates->start->name);
3154 return NULL;
45288df1 3155 }
29b0f896
AM		 3156 /* Add prefix, checking for repeated prefixes. */
3157 switch (add_prefix (current_templates->start->base_opcode))
3158 {
c32fa91d 3159 case PREFIX_EXIST:
29b0f896 3160 return NULL;
c32fa91d 3161 case PREFIX_REP:
29b0f896
AM		 3162 expecting_string_instruction = current_templates->start->name;
3163 break;
c32fa91d
L		 3164 default:
3165 break;
29b0f896
AM		 3166 }
3167 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3168 token_start = ++l;
3169 }
3170 else
3171 break;
3172 }
45288df1 3173
30a55f88 3174 if (!current_templates)
b6169b20 3175 {
30a55f88
L		 3176 /* Check if we should swap operand in encoding. */
3177 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3178 i.swap_operand = 1;
3179 else
3180 goto check_suffix;
3181 mnem_p = dot_p;
3182 *dot_p = '\0';
d3ce72d0 3183 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3184 }
3185
29b0f896
AM		 3186 if (!current_templates)
3187 {
b6169b20 3188check_suffix:
29b0f896
AM		 3189 /* See if we can get a match by trimming off a suffix. */
3190 switch (mnem_p[-1])
3191 {
3192 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3193 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3194 i.suffix = SHORT_MNEM_SUFFIX;
3195 else
29b0f896
AM		 3196 case BYTE_MNEM_SUFFIX:
3197 case QWORD_MNEM_SUFFIX:
3198 i.suffix = mnem_p[-1];
3199 mnem_p[-1] = '\0';
d3ce72d0
NC		 3200 current_templates = (const templates *) hash_find (op_hash,
3201 mnemonic);
29b0f896
AM		 3202 break;
3203 case SHORT_MNEM_SUFFIX:
3204 case LONG_MNEM_SUFFIX:
3205 if (!intel_syntax)
3206 {
3207 i.suffix = mnem_p[-1];
3208 mnem_p[-1] = '\0';
d3ce72d0
NC		 3209 current_templates = (const templates *) hash_find (op_hash,
3210 mnemonic);
29b0f896
AM		 3211 }
3212 break;
252b5132 3213
29b0f896
AM		 3214 /* Intel Syntax. */
3215 case 'd':
3216 if (intel_syntax)
3217 {
9306ca4a 3218 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3219 i.suffix = SHORT_MNEM_SUFFIX;
3220 else
3221 i.suffix = LONG_MNEM_SUFFIX;
3222 mnem_p[-1] = '\0';
d3ce72d0
NC		 3223 current_templates = (const templates *) hash_find (op_hash,
3224 mnemonic);
29b0f896
AM		 3225 }
3226 break;
3227 }
3228 if (!current_templates)
3229 {
3230 as_bad (_("no such instruction: `%s'"), token_start);
3231 return NULL;
3232 }
3233 }
252b5132 3234
40fb9820
L		 3235 if (current_templates->start->opcode_modifier.jump
3236 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3237 {
3238 /* Check for a branch hint. We allow ",pt" and ",pn" for
3239 predict taken and predict not taken respectively.
3240 I'm not sure that branch hints actually do anything on loop
3241 and jcxz insns (JumpByte) for current Pentium4 chips. They
3242 may work in the future and it doesn't hurt to accept them
3243 now. */
3244 if (l[0] == ',' && l[1] == 'p')
3245 {
3246 if (l[2] == 't')
3247 {
3248 if (!add_prefix (DS_PREFIX_OPCODE))
3249 return NULL;
3250 l += 3;
3251 }
3252 else if (l[2] == 'n')
3253 {
3254 if (!add_prefix (CS_PREFIX_OPCODE))
3255 return NULL;
3256 l += 3;
3257 }
3258 }
3259 }
3260 /* Any other comma loses. */
3261 if (*l == ',')
3262 {
3263 as_bad (_("invalid character %s in mnemonic"),
3264 output_invalid (*l));
3265 return NULL;
3266 }
252b5132 3267
29b0f896 3268 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3269 supported = 0;
3270 for (t = current_templates->start; t < current_templates->end; ++t)
3271 {
c0f3af97
L		 3272 supported |= cpu_flags_match (t);
3273 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3274 goto skip;
5c6af06e 3275 }
3629bb00 3276
c0f3af97 3277 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3278 {
3279 as_bad (flag_code == CODE_64BIT
3280 ? _("`%s' is not supported in 64-bit mode")
3281 : _("`%s' is only supported in 64-bit mode"),
3282 current_templates->start->name);
3283 return NULL;
3284 }
c0f3af97 3285 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3286 {
3629bb00 3287 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3288 current_templates->start->name,
41aacd83 3289 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3290 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3291 return NULL;
29b0f896 3292 }
3629bb00
L		 3293
3294skip:
3295 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3296 && (flag_code != CODE_16BIT))
29b0f896
AM		 3297 {
3298 as_warn (_("use .code16 to ensure correct addressing mode"));
3299 }
252b5132 3300
29b0f896 3301 /* Check for rep/repne without a string instruction. */
f41bbced 3302 if (expecting_string_instruction)
29b0f896 3303 {
f41bbced
JB		 3304 static templates override;
3305
3306 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3307 if (t->opcode_modifier.isstring)
f41bbced
JB		 3308 break;
3309 if (t >= current_templates->end)
3310 {
3311 as_bad (_("expecting string instruction after `%s'"),
64e74474 3312 expecting_string_instruction);
f41bbced
JB		 3313 return NULL;
3314 }
3315 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3316 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3317 break;
3318 override.end = t;
3319 current_templates = &override;
29b0f896 3320 }
252b5132 3321
29b0f896
AM		 3322 return l;
3323}
252b5132 3324
29b0f896 3325static char *
e3bb37b5 3326parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3327{
3328 char *token_start;
3138f287 3329
29b0f896
AM		 3330 /* 1 if operand is pending after ','. */
3331 unsigned int expecting_operand = 0;
252b5132 3332
29b0f896
AM		 3333 /* Non-zero if operand parens not balanced. */
3334 unsigned int paren_not_balanced;
3335
3336 while (*l != END_OF_INSN)
3337 {
3338 /* Skip optional white space before operand. */
3339 if (is_space_char (*l))
3340 ++l;
3341 if (!is_operand_char (*l) && *l != END_OF_INSN)
3342 {
3343 as_bad (_("invalid character %s before operand %d"),
3344 output_invalid (*l),
3345 i.operands + 1);
3346 return NULL;
3347 }
3348 token_start = l; /* after white space */
3349 paren_not_balanced = 0;
3350 while (paren_not_balanced || *l != ',')
3351 {
3352 if (*l == END_OF_INSN)
3353 {
3354 if (paren_not_balanced)
3355 {
3356 if (!intel_syntax)
3357 as_bad (_("unbalanced parenthesis in operand %d."),
3358 i.operands + 1);
3359 else
3360 as_bad (_("unbalanced brackets in operand %d."),
3361 i.operands + 1);
3362 return NULL;
3363 }
3364 else
3365 break; /* we are done */
3366 }
3367 else if (!is_operand_char (*l) && !is_space_char (*l))
3368 {
3369 as_bad (_("invalid character %s in operand %d"),
3370 output_invalid (*l),
3371 i.operands + 1);
3372 return NULL;
3373 }
3374 if (!intel_syntax)
3375 {
3376 if (*l == '(')
3377 ++paren_not_balanced;
3378 if (*l == ')')
3379 --paren_not_balanced;
3380 }
3381 else
3382 {
3383 if (*l == '[')
3384 ++paren_not_balanced;
3385 if (*l == ']')
3386 --paren_not_balanced;
3387 }
3388 l++;
3389 }
3390 if (l != token_start)
3391 { /* Yes, we've read in another operand. */
3392 unsigned int operand_ok;
3393 this_operand = i.operands++;
7d5e4556 3394 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3395 if (i.operands > MAX_OPERANDS)
3396 {
3397 as_bad (_("spurious operands; (%d operands/instruction max)"),
3398 MAX_OPERANDS);
3399 return NULL;
3400 }
3401 /* Now parse operand adding info to 'i' as we go along. */
3402 END_STRING_AND_SAVE (l);
3403
3404 if (intel_syntax)
3405 operand_ok =
3406 i386_intel_operand (token_start,
3407 intel_float_operand (mnemonic));
3408 else
a7619375 3409 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3410
3411 RESTORE_END_STRING (l);
3412 if (!operand_ok)
3413 return NULL;
3414 }
3415 else
3416 {
3417 if (expecting_operand)
3418 {
3419 expecting_operand_after_comma:
3420 as_bad (_("expecting operand after ','; got nothing"));
3421 return NULL;
3422 }
3423 if (*l == ',')
3424 {
3425 as_bad (_("expecting operand before ','; got nothing"));
3426 return NULL;
3427 }
3428 }
7f3f1ea2 3429
29b0f896
AM		 3430 /* Now *l must be either ',' or END_OF_INSN. */
3431 if (*l == ',')
3432 {
3433 if (*++l == END_OF_INSN)
3434 {
3435 /* Just skip it, if it's \n complain. */
3436 goto expecting_operand_after_comma;
3437 }
3438 expecting_operand = 1;
3439 }
3440 }
3441 return l;
3442}
7f3f1ea2 3443
050dfa73 3444static void
4d456e3d 3445swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3446{
3447 union i386_op temp_op;
40fb9820 3448 i386_operand_type temp_type;
050dfa73 3449 enum bfd_reloc_code_real temp_reloc;
4eed87de 3450
050dfa73
MM		 3451 temp_type = i.types[xchg2];
3452 i.types[xchg2] = i.types[xchg1];
3453 i.types[xchg1] = temp_type;
3454 temp_op = i.op[xchg2];
3455 i.op[xchg2] = i.op[xchg1];
3456 i.op[xchg1] = temp_op;
3457 temp_reloc = i.reloc[xchg2];
3458 i.reloc[xchg2] = i.reloc[xchg1];
3459 i.reloc[xchg1] = temp_reloc;
3460}
3461
29b0f896 3462static void
e3bb37b5 3463swap_operands (void)
29b0f896 3464{
b7c61d9a 3465 switch (i.operands)
050dfa73 3466 {
c0f3af97 3467 case 5:
b7c61d9a 3468 case 4:
4d456e3d 3469 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3470 case 3:
3471 case 2:
4d456e3d 3472 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3473 break;
3474 default:
3475 abort ();
29b0f896 3476 }
29b0f896
AM		 3477
3478 if (i.mem_operands == 2)
3479 {
3480 const seg_entry *temp_seg;
3481 temp_seg = i.seg[0];
3482 i.seg[0] = i.seg[1];
3483 i.seg[1] = temp_seg;
3484 }
3485}
252b5132 3486
29b0f896
AM		 3487/* Try to ensure constant immediates are represented in the smallest
3488 opcode possible. */
3489static void
e3bb37b5 3490optimize_imm (void)
29b0f896
AM		 3491{
3492 char guess_suffix = 0;
3493 int op;
252b5132 3494
29b0f896
AM		 3495 if (i.suffix)
3496 guess_suffix = i.suffix;
3497 else if (i.reg_operands)
3498 {
3499 /* Figure out a suffix from the last register operand specified.
3500 We can't do this properly yet, ie. excluding InOutPortReg,
3501 but the following works for instructions with immediates.
3502 In any case, we can't set i.suffix yet. */
3503 for (op = i.operands; --op >= 0;)
40fb9820 3504 if (i.types[op].bitfield.reg8)
7ab9ffdd 3505 {
40fb9820
L		 3506 guess_suffix = BYTE_MNEM_SUFFIX;
3507 break;
3508 }
3509 else if (i.types[op].bitfield.reg16)
252b5132 3510 {
40fb9820
L		 3511 guess_suffix = WORD_MNEM_SUFFIX;
3512 break;
3513 }
3514 else if (i.types[op].bitfield.reg32)
3515 {
3516 guess_suffix = LONG_MNEM_SUFFIX;
3517 break;
3518 }
3519 else if (i.types[op].bitfield.reg64)
3520 {
3521 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3522 break;
252b5132 3523 }
29b0f896
AM		 3524 }
3525 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3526 guess_suffix = WORD_MNEM_SUFFIX;
3527
3528 for (op = i.operands; --op >= 0;)
40fb9820 3529 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3530 {
3531 switch (i.op[op].imms->X_op)
252b5132 3532 {
29b0f896
AM		 3533 case O_constant:
3534 /* If a suffix is given, this operand may be shortened. */
3535 switch (guess_suffix)
252b5132 3536 {
29b0f896 3537 case LONG_MNEM_SUFFIX:
40fb9820
L		 3538 i.types[op].bitfield.imm32 = 1;
3539 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3540 break;
3541 case WORD_MNEM_SUFFIX:
40fb9820
L		 3542 i.types[op].bitfield.imm16 = 1;
3543 i.types[op].bitfield.imm32 = 1;
3544 i.types[op].bitfield.imm32s = 1;
3545 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3546 break;
3547 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3548 i.types[op].bitfield.imm8 = 1;
3549 i.types[op].bitfield.imm8s = 1;
3550 i.types[op].bitfield.imm16 = 1;
3551 i.types[op].bitfield.imm32 = 1;
3552 i.types[op].bitfield.imm32s = 1;
3553 i.types[op].bitfield.imm64 = 1;
29b0f896 3554 break;
252b5132 3555 }
252b5132 3556
29b0f896
AM		 3557 /* If this operand is at most 16 bits, convert it
3558 to a signed 16 bit number before trying to see
3559 whether it will fit in an even smaller size.
3560 This allows a 16-bit operand such as $0xffe0 to
3561 be recognised as within Imm8S range. */
40fb9820 3562 if ((i.types[op].bitfield.imm16)
29b0f896 3563 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3564 {
29b0f896
AM		 3565 i.op[op].imms->X_add_number =
3566 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3567 }
40fb9820 3568 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3569 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3570 == 0))
3571 {
3572 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3573 ^ ((offsetT) 1 << 31))
3574 - ((offsetT) 1 << 31));
3575 }
40fb9820 3576 i.types[op]
c6fb90c8
L		 3577 = operand_type_or (i.types[op],
3578 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3579
29b0f896
AM		 3580 /* We must avoid matching of Imm32 templates when 64bit
3581 only immediate is available. */
3582 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3583 i.types[op].bitfield.imm32 = 0;
29b0f896 3584 break;
252b5132 3585
29b0f896
AM		 3586 case O_absent:
3587 case O_register:
3588 abort ();
3589
3590 /* Symbols and expressions. */
3591 default:
9cd96992
JB		 3592 /* Convert symbolic operand to proper sizes for matching, but don't
3593 prevent matching a set of insns that only supports sizes other
3594 than those matching the insn suffix. */
3595 {
40fb9820 3596 i386_operand_type mask, allowed;
d3ce72d0 3597 const insn_template *t;
9cd96992 3598
0dfbf9d7
L		 3599 operand_type_set (&mask, 0);
3600 operand_type_set (&allowed, 0);
40fb9820 3601
4eed87de
AM		 3602 for (t = current_templates->start;
3603 t < current_templates->end;
3604 ++t)
c6fb90c8
L		 3605 allowed = operand_type_or (allowed,
3606 t->operand_types[op]);
9cd96992
JB		 3607 switch (guess_suffix)
3608 {
3609 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3610 mask.bitfield.imm64 = 1;
3611 mask.bitfield.imm32s = 1;
9cd96992
JB		 3612 break;
3613 case LONG_MNEM_SUFFIX:
40fb9820 3614 mask.bitfield.imm32 = 1;
9cd96992
JB		 3615 break;
3616 case WORD_MNEM_SUFFIX:
40fb9820 3617 mask.bitfield.imm16 = 1;
9cd96992
JB		 3618 break;
3619 case BYTE_MNEM_SUFFIX:
40fb9820 3620 mask.bitfield.imm8 = 1;
9cd96992
JB		 3621 break;
3622 default:
9cd96992
JB		 3623 break;
3624 }
c6fb90c8 3625 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3626 if (!operand_type_all_zero (&allowed))
c6fb90c8 3627 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3628 }
29b0f896 3629 break;
252b5132 3630 }
29b0f896
AM		 3631 }
3632}
47926f60 3633
29b0f896
AM		 3634/* Try to use the smallest displacement type too. */
3635static void
e3bb37b5 3636optimize_disp (void)
29b0f896
AM		 3637{
3638 int op;
3e73aa7c 3639
29b0f896 3640 for (op = i.operands; --op >= 0;)
40fb9820 3641 if (operand_type_check (i.types[op], disp))
252b5132 3642 {
b300c311 3643 if (i.op[op].disps->X_op == O_constant)
252b5132 3644 {
91d6fa6a 3645 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3646
40fb9820 3647 if (i.types[op].bitfield.disp16
91d6fa6a 3648 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3649 {
3650 /* If this operand is at most 16 bits, convert
3651 to a signed 16 bit number and don't use 64bit
3652 displacement. */
91d6fa6a 3653 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3654 i.types[op].bitfield.disp64 = 0;
b300c311 3655 }
40fb9820 3656 if (i.types[op].bitfield.disp32
91d6fa6a 3657 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3658 {
3659 /* If this operand is at most 32 bits, convert
3660 to a signed 32 bit number and don't use 64bit
3661 displacement. */
91d6fa6a
NC		 3662 op_disp &= (((offsetT) 2 << 31) - 1);
3663 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3664 i.types[op].bitfield.disp64 = 0;
b300c311 3665 }
91d6fa6a 3666 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3667 {
40fb9820
L		 3668 i.types[op].bitfield.disp8 = 0;
3669 i.types[op].bitfield.disp16 = 0;
3670 i.types[op].bitfield.disp32 = 0;
3671 i.types[op].bitfield.disp32s = 0;
3672 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3673 i.op[op].disps = 0;
3674 i.disp_operands--;
3675 }
3676 else if (flag_code == CODE_64BIT)
3677 {
91d6fa6a 3678 if (fits_in_signed_long (op_disp))
28a9d8f5 3679 {
40fb9820
L		 3680 i.types[op].bitfield.disp64 = 0;
3681 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3682 }
0e1147d9 3683 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3684 && fits_in_unsigned_long (op_disp))
40fb9820 3685 i.types[op].bitfield.disp32 = 1;
b300c311 3686 }
40fb9820
L		 3687 if ((i.types[op].bitfield.disp32
3688 || i.types[op].bitfield.disp32s
3689 || i.types[op].bitfield.disp16)
91d6fa6a 3690 && fits_in_signed_byte (op_disp))
40fb9820 3691 i.types[op].bitfield.disp8 = 1;
252b5132 3692 }
67a4f2b7
AO		 3693 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3694 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3695 {
3696 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3697 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3698 i.types[op].bitfield.disp8 = 0;
3699 i.types[op].bitfield.disp16 = 0;
3700 i.types[op].bitfield.disp32 = 0;
3701 i.types[op].bitfield.disp32s = 0;
3702 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3703 }
3704 else
b300c311 3705 /* We only support 64bit displacement on constants. */
40fb9820 3706 i.types[op].bitfield.disp64 = 0;
252b5132 3707 }
29b0f896
AM		 3708}
3709
d3ce72d0 3710static const insn_template *
e3bb37b5 3711match_template (void)
29b0f896
AM		 3712{
3713 /* Points to template once we've found it. */
d3ce72d0 3714 const insn_template *t;
40fb9820 3715 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3716 i386_operand_type overlap4;
29b0f896 3717 unsigned int found_reverse_match;
40fb9820
L		 3718 i386_opcode_modifier suffix_check;
3719 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3720 int addr_prefix_disp;
a5c311ca 3721 unsigned int j;
3629bb00 3722 unsigned int found_cpu_match;
45664ddb 3723 unsigned int check_register;
29b0f896 3724
c0f3af97
L		 3725#if MAX_OPERANDS != 5
3726# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3727#endif
3728
29b0f896 3729 found_reverse_match = 0;
539e75ad 3730 addr_prefix_disp = -1;
40fb9820
L		 3731
3732 memset (&suffix_check, 0, sizeof (suffix_check));
3733 if (i.suffix == BYTE_MNEM_SUFFIX)
3734 suffix_check.no_bsuf = 1;
3735 else if (i.suffix == WORD_MNEM_SUFFIX)
3736 suffix_check.no_wsuf = 1;
3737 else if (i.suffix == SHORT_MNEM_SUFFIX)
3738 suffix_check.no_ssuf = 1;
3739 else if (i.suffix == LONG_MNEM_SUFFIX)
3740 suffix_check.no_lsuf = 1;
3741 else if (i.suffix == QWORD_MNEM_SUFFIX)
3742 suffix_check.no_qsuf = 1;
3743 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3744 suffix_check.no_ldsuf = 1;
29b0f896 3745
45aa61fe 3746 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3747 {
539e75ad
L		 3748 addr_prefix_disp = -1;
3749
29b0f896
AM		 3750 /* Must have right number of operands. */
3751 if (i.operands != t->operands)
3752 continue;
3753
50aecf8c 3754 /* Check processor support. */
c0f3af97
L		 3755 found_cpu_match = (cpu_flags_match (t)
3756 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3757 if (!found_cpu_match)
3758 continue;
3759
e1d4d893
L		 3760 /* Check old gcc support. */
3761 if (!old_gcc && t->opcode_modifier.oldgcc)
3762 continue;
3763
3764 /* Check AT&T mnemonic. */
3765 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3766 continue;
3767
5c07affc
L		 3768 /* Check AT&T syntax Intel syntax. */
3769 if ((intel_syntax && t->opcode_modifier.attsyntax)
3770 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3771 continue;
3772
20592a94 3773 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3774 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3775 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3776 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3777 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3778 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3779 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3780 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3781 continue;
3782
5c07affc 3783 if (!operand_size_match (t))
7d5e4556 3784 continue;
539e75ad 3785
5c07affc
L		 3786 for (j = 0; j < MAX_OPERANDS; j++)
3787 operand_types[j] = t->operand_types[j];
3788
45aa61fe
AM		 3789 /* In general, don't allow 64-bit operands in 32-bit mode. */
3790 if (i.suffix == QWORD_MNEM_SUFFIX
3791 && flag_code != CODE_64BIT
3792 && (intel_syntax
40fb9820 3793 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3794 && !intel_float_operand (t->name))
3795 : intel_float_operand (t->name) != 2)
40fb9820 3796 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3797 && !operand_types[0].bitfield.regxmm
3798 && !operand_types[0].bitfield.regymm)
40fb9820 3799 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3800 && !!operand_types[t->operands > 1].bitfield.regxmm
3801 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3802 && (t->base_opcode != 0x0fc7
3803 || t->extension_opcode != 1 /* cmpxchg8b */))
3804 continue;
3805
192dc9c6
JB		 3806 /* In general, don't allow 32-bit operands on pre-386. */
3807 else if (i.suffix == LONG_MNEM_SUFFIX
3808 && !cpu_arch_flags.bitfield.cpui386
3809 && (intel_syntax
3810 ? (!t->opcode_modifier.ignoresize
3811 && !intel_float_operand (t->name))
3812 : intel_float_operand (t->name) != 2)
3813 && ((!operand_types[0].bitfield.regmmx
3814 && !operand_types[0].bitfield.regxmm)
3815 || (!operand_types[t->operands > 1].bitfield.regmmx
3816 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3817 continue;
3818
29b0f896 3819 /* Do not verify operands when there are none. */
50aecf8c 3820 else
29b0f896 3821 {
c6fb90c8 3822 if (!t->operands)
2dbab7d5
L		 3823 /* We've found a match; break out of loop. */
3824 break;
29b0f896 3825 }
252b5132 3826
539e75ad
L		 3827 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3828 into Disp32/Disp16/Disp32 operand. */
3829 if (i.prefix[ADDR_PREFIX] != 0)
3830 {
40fb9820 3831 /* There should be only one Disp operand. */
539e75ad
L		 3832 switch (flag_code)
3833 {
3834 case CODE_16BIT:
40fb9820
L		 3835 for (j = 0; j < MAX_OPERANDS; j++)
3836 {
3837 if (operand_types[j].bitfield.disp16)
3838 {
3839 addr_prefix_disp = j;
3840 operand_types[j].bitfield.disp32 = 1;
3841 operand_types[j].bitfield.disp16 = 0;
3842 break;
3843 }
3844 }
539e75ad
L		 3845 break;
3846 case CODE_32BIT:
40fb9820
L		 3847 for (j = 0; j < MAX_OPERANDS; j++)
3848 {
3849 if (operand_types[j].bitfield.disp32)
3850 {
3851 addr_prefix_disp = j;
3852 operand_types[j].bitfield.disp32 = 0;
3853 operand_types[j].bitfield.disp16 = 1;
3854 break;
3855 }
3856 }
539e75ad
L		 3857 break;
3858 case CODE_64BIT:
40fb9820
L		 3859 for (j = 0; j < MAX_OPERANDS; j++)
3860 {
3861 if (operand_types[j].bitfield.disp64)
3862 {
3863 addr_prefix_disp = j;
3864 operand_types[j].bitfield.disp64 = 0;
3865 operand_types[j].bitfield.disp32 = 1;
3866 break;
3867 }
3868 }
539e75ad
L		 3869 break;
3870 }
539e75ad
L		 3871 }
3872
45664ddb
L		 3873 /* We check register size only if size of operands can be
3874 encoded the canonical way. */
3875 check_register = t->opcode_modifier.w;
c6fb90c8 3876 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3877 switch (t->operands)
3878 {
3879 case 1:
40fb9820 3880 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3881 continue;
3882 break;
3883 case 2:
8b38ad71
L		 3884 /* xchg %eax, %eax is a special case. It is an aliase for nop
3885 only in 32bit mode and we can use opcode 0x90. In 64bit
3886 mode, we can't use 0x90 for xchg %eax, %eax since it should
3887 zero-extend %eax to %rax. */
3888 if (flag_code == CODE_64BIT
3889 && t->base_opcode == 0x90
0dfbf9d7
L		 3890 && operand_type_equal (&i.types [0], &acc32)
3891 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3892 continue;
b6169b20
L		 3893 if (i.swap_operand)
3894 {
3895 /* If we swap operand in encoding, we either match
3896 the next one or reverse direction of operands. */
3897 if (t->opcode_modifier.s)
3898 continue;
3899 else if (t->opcode_modifier.d)
3900 goto check_reverse;
3901 }
3902
29b0f896 3903 case 3:
fa99fab2
L		 3904 /* If we swap operand in encoding, we match the next one. */
3905 if (i.swap_operand && t->opcode_modifier.s)
3906 continue;
f48ff2ae 3907 case 4:
c0f3af97 3908 case 5:
c6fb90c8 3909 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3910 if (!operand_type_match (overlap0, i.types[0])
3911 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3912 || (check_register
3913 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3914 operand_types[0],
3915 overlap1, i.types[1],
3916 operand_types[1])))
29b0f896
AM		 3917 {
3918 /* Check if other direction is valid ... */
40fb9820 3919 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3920 continue;
3921
b6169b20 3922check_reverse:
29b0f896 3923 /* Try reversing direction of operands. */
c6fb90c8
L		 3924 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3925 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3926 if (!operand_type_match (overlap0, i.types[0])
3927 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3928 || (check_register
3929 && !operand_type_register_match (overlap0,
3930 i.types[0],
3931 operand_types[1],
3932 overlap1,
3933 i.types[1],
3934 operand_types[0])))
29b0f896
AM		 3935 {
3936 /* Does not match either direction. */
3937 continue;
3938 }
3939 /* found_reverse_match holds which of D or FloatDR
3940 we've found. */
40fb9820 3941 if (t->opcode_modifier.d)
8a2ed489 3942 found_reverse_match = Opcode_D;
40fb9820 3943 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3944 found_reverse_match = Opcode_FloatD;
3945 else
3946 found_reverse_match = 0;
40fb9820 3947 if (t->opcode_modifier.floatr)
8a2ed489 3948 found_reverse_match |= Opcode_FloatR;
29b0f896 3949 }
f48ff2ae 3950 else
29b0f896 3951 {
f48ff2ae 3952 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3953 switch (t->operands)
3954 {
c0f3af97
L		 3955 case 5:
3956 overlap4 = operand_type_and (i.types[4],
3957 operand_types[4]);
d1cbb4db 3958 case 4:
c6fb90c8
L		 3959 overlap3 = operand_type_and (i.types[3],
3960 operand_types[3]);
d1cbb4db 3961 case 3:
c6fb90c8
L		 3962 overlap2 = operand_type_and (i.types[2],
3963 operand_types[2]);
d1cbb4db
L		 3964 break;
3965 }
29b0f896 3966
f48ff2ae
L		 3967 switch (t->operands)
3968 {
c0f3af97
L		 3969 case 5:
3970 if (!operand_type_match (overlap4, i.types[4])
3971 || !operand_type_register_match (overlap3,
3972 i.types[3],
3973 operand_types[3],
3974 overlap4,
3975 i.types[4],
3976 operand_types[4]))
3977 continue;
f48ff2ae 3978 case 4:
40fb9820 3979 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3980 || (check_register
3981 && !operand_type_register_match (overlap2,
3982 i.types[2],
3983 operand_types[2],
3984 overlap3,
3985 i.types[3],
3986 operand_types[3])))
f48ff2ae
L		 3987 continue;
3988 case 3:
3989 /* Here we make use of the fact that there are no
3990 reverse match 3 operand instructions, and all 3
3991 operand instructions only need to be checked for
3992 register consistency between operands 2 and 3. */
40fb9820 3993 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3994 || (check_register
3995 && !operand_type_register_match (overlap1,
3996 i.types[1],
3997 operand_types[1],
3998 overlap2,
3999 i.types[2],
4000 operand_types[2])))
f48ff2ae
L		 4001 continue;
4002 break;
4003 }
29b0f896 4004 }
f48ff2ae 4005 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4006 slip through to break. */
4007 }
3629bb00 4008 if (!found_cpu_match)
29b0f896
AM		 4009 {
4010 found_reverse_match = 0;
4011 continue;
4012 }
c0f3af97 4013
29b0f896
AM		 4014 /* We've found a match; break out of loop. */
4015 break;
4016 }
4017
4018 if (t == current_templates->end)
4019 {
4020 /* We found no match. */
95f283e8
L		 4021 if (intel_syntax)
4022 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4023 current_templates->start->name);
4024 else
4025 as_bad (_("suffix or operands invalid for `%s'"),
4026 current_templates->start->name);
fa99fab2 4027 return NULL;
29b0f896 4028 }
252b5132 4029
29b0f896
AM		 4030 if (!quiet_warnings)
4031 {
4032 if (!intel_syntax
40fb9820
L		 4033 && (i.types[0].bitfield.jumpabsolute
4034 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4035 {
4036 as_warn (_("indirect %s without `*'"), t->name);
4037 }
4038
40fb9820
L		 4039 if (t->opcode_modifier.isprefix
4040 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4041 {
4042 /* Warn them that a data or address size prefix doesn't
4043 affect assembly of the next line of code. */
4044 as_warn (_("stand-alone `%s' prefix"), t->name);
4045 }
4046 }
4047
4048 /* Copy the template we found. */
4049 i.tm = *t;
539e75ad
L		 4050
4051 if (addr_prefix_disp != -1)
4052 i.tm.operand_types[addr_prefix_disp]
4053 = operand_types[addr_prefix_disp];
4054
29b0f896
AM		 4055 if (found_reverse_match)
4056 {
4057 /* If we found a reverse match we must alter the opcode
4058 direction bit. found_reverse_match holds bits to change
4059 (different for int & float insns). */
4060
4061 i.tm.base_opcode ^= found_reverse_match;
4062
539e75ad
L		 4063 i.tm.operand_types[0] = operand_types[1];
4064 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4065 }
4066
fa99fab2 4067 return t;
29b0f896
AM		 4068}
4069
4070static int
e3bb37b5 4071check_string (void)
29b0f896 4072{
40fb9820
L		 4073 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4074 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4075 {
4076 if (i.seg[0] != NULL && i.seg[0] != &es)
4077 {
a87af027 4078 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4079 i.tm.name,
a87af027
JB		 4080 mem_op + 1,
4081 register_prefix);
29b0f896
AM		 4082 return 0;
4083 }
4084 /* There's only ever one segment override allowed per instruction.
4085 This instruction possibly has a legal segment override on the
4086 second operand, so copy the segment to where non-string
4087 instructions store it, allowing common code. */
4088 i.seg[0] = i.seg[1];
4089 }
40fb9820 4090 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4091 {
4092 if (i.seg[1] != NULL && i.seg[1] != &es)
4093 {
a87af027 4094 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4095 i.tm.name,
a87af027
JB		 4096 mem_op + 2,
4097 register_prefix);
29b0f896
AM		 4098 return 0;
4099 }
4100 }
4101 return 1;
4102}
4103
4104static int
543613e9 4105process_suffix (void)
29b0f896
AM		 4106{
4107 /* If matched instruction specifies an explicit instruction mnemonic
4108 suffix, use it. */
40fb9820
L		 4109 if (i.tm.opcode_modifier.size16)
4110 i.suffix = WORD_MNEM_SUFFIX;
4111 else if (i.tm.opcode_modifier.size32)
4112 i.suffix = LONG_MNEM_SUFFIX;
4113 else if (i.tm.opcode_modifier.size64)
4114 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4115 else if (i.reg_operands)
4116 {
4117 /* If there's no instruction mnemonic suffix we try to invent one
4118 based on register operands. */
4119 if (!i.suffix)
4120 {
4121 /* We take i.suffix from the last register operand specified,
4122 Destination register type is more significant than source
381d071f
L		 4123 register type. crc32 in SSE4.2 prefers source register
4124 type. */
4125 if (i.tm.base_opcode == 0xf20f38f1)
4126 {
40fb9820
L		 4127 if (i.types[0].bitfield.reg16)
4128 i.suffix = WORD_MNEM_SUFFIX;
4129 else if (i.types[0].bitfield.reg32)
4130 i.suffix = LONG_MNEM_SUFFIX;
4131 else if (i.types[0].bitfield.reg64)
4132 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4133 }
9344ff29 4134 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4135 {
40fb9820 4136 if (i.types[0].bitfield.reg8)
20592a94
L		 4137 i.suffix = BYTE_MNEM_SUFFIX;
4138 }
381d071f
L		 4139
4140 if (!i.suffix)
4141 {
4142 int op;
4143
20592a94
L		 4144 if (i.tm.base_opcode == 0xf20f38f1
4145 || i.tm.base_opcode == 0xf20f38f0)
4146 {
4147 /* We have to know the operand size for crc32. */
4148 as_bad (_("ambiguous memory operand size for `%s`"),
4149 i.tm.name);
4150 return 0;
4151 }
4152
381d071f 4153 for (op = i.operands; --op >= 0;)
40fb9820 4154 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4155 {
40fb9820
L		 4156 if (i.types[op].bitfield.reg8)
4157 {
4158 i.suffix = BYTE_MNEM_SUFFIX;
4159 break;
4160 }
4161 else if (i.types[op].bitfield.reg16)
4162 {
4163 i.suffix = WORD_MNEM_SUFFIX;
4164 break;
4165 }
4166 else if (i.types[op].bitfield.reg32)
4167 {
4168 i.suffix = LONG_MNEM_SUFFIX;
4169 break;
4170 }
4171 else if (i.types[op].bitfield.reg64)
4172 {
4173 i.suffix = QWORD_MNEM_SUFFIX;
4174 break;
4175 }
381d071f
L		 4176 }
4177 }
29b0f896
AM		 4178 }
4179 else if (i.suffix == BYTE_MNEM_SUFFIX)
4180 {
2eb952a4
L		 4181 if (intel_syntax
4182 && i.tm.opcode_modifier.ignoresize
4183 && i.tm.opcode_modifier.no_bsuf)
4184 i.suffix = 0;
4185 else if (!check_byte_reg ())
29b0f896
AM		 4186 return 0;
4187 }
4188 else if (i.suffix == LONG_MNEM_SUFFIX)
4189 {
2eb952a4
L		 4190 if (intel_syntax
4191 && i.tm.opcode_modifier.ignoresize
4192 && i.tm.opcode_modifier.no_lsuf)
4193 i.suffix = 0;
4194 else if (!check_long_reg ())
29b0f896
AM		 4195 return 0;
4196 }
4197 else if (i.suffix == QWORD_MNEM_SUFFIX)
4198 {
955e1e6a
L		 4199 if (intel_syntax
4200 && i.tm.opcode_modifier.ignoresize
4201 && i.tm.opcode_modifier.no_qsuf)
4202 i.suffix = 0;
4203 else if (!check_qword_reg ())
29b0f896
AM		 4204 return 0;
4205 }
4206 else if (i.suffix == WORD_MNEM_SUFFIX)
4207 {
2eb952a4
L		 4208 if (intel_syntax
4209 && i.tm.opcode_modifier.ignoresize
4210 && i.tm.opcode_modifier.no_wsuf)
4211 i.suffix = 0;
4212 else if (!check_word_reg ())
29b0f896
AM		 4213 return 0;
4214 }
c0f3af97
L		 4215 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4216 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4217 {
c0f3af97 4218 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4219 should check if it is a valid suffix. */
4220 }
40fb9820 4221 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4222 /* Do nothing if the instruction is going to ignore the prefix. */
4223 ;
4224 else
4225 abort ();
4226 }
40fb9820 4227 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4228 && !i.suffix
4229 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4230 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4231 {
4232 i.suffix = stackop_size;
4233 }
9306ca4a
JB		 4234 else if (intel_syntax
4235 && !i.suffix
40fb9820
L		 4236 && (i.tm.operand_types[0].bitfield.jumpabsolute
4237 || i.tm.opcode_modifier.jumpbyte
4238 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4239 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4240 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4241 {
4242 switch (flag_code)
4243 {
4244 case CODE_64BIT:
40fb9820 4245 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4246 {
4247 i.suffix = QWORD_MNEM_SUFFIX;
4248 break;
4249 }
4250 case CODE_32BIT:
40fb9820 4251 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4252 i.suffix = LONG_MNEM_SUFFIX;
4253 break;
4254 case CODE_16BIT:
40fb9820 4255 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4256 i.suffix = WORD_MNEM_SUFFIX;
4257 break;
4258 }
4259 }
252b5132 4260
9306ca4a 4261 if (!i.suffix)
29b0f896 4262 {
9306ca4a
JB		 4263 if (!intel_syntax)
4264 {
40fb9820 4265 if (i.tm.opcode_modifier.w)
9306ca4a 4266 {
4eed87de
AM		 4267 as_bad (_("no instruction mnemonic suffix given and "
4268 "no register operands; can't size instruction"));
9306ca4a
JB		 4269 return 0;
4270 }
4271 }
4272 else
4273 {
40fb9820 4274 unsigned int suffixes;
7ab9ffdd 4275
40fb9820
L		 4276 suffixes = !i.tm.opcode_modifier.no_bsuf;
4277 if (!i.tm.opcode_modifier.no_wsuf)
4278 suffixes |= 1 << 1;
4279 if (!i.tm.opcode_modifier.no_lsuf)
4280 suffixes |= 1 << 2;
fc4adea1 4281 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4282 suffixes |= 1 << 3;
4283 if (!i.tm.opcode_modifier.no_ssuf)
4284 suffixes |= 1 << 4;
4285 if (!i.tm.opcode_modifier.no_qsuf)
4286 suffixes |= 1 << 5;
4287
4288 /* There are more than suffix matches. */
4289 if (i.tm.opcode_modifier.w
9306ca4a 4290 || ((suffixes & (suffixes - 1))
40fb9820
L		 4291 && !i.tm.opcode_modifier.defaultsize
4292 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4293 {
4294 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4295 return 0;
4296 }
4297 }
29b0f896 4298 }
252b5132 4299
9306ca4a
JB		 4300 /* Change the opcode based on the operand size given by i.suffix;
4301 We don't need to change things for byte insns. */
4302
582d5edd
L		 4303 if (i.suffix
4304 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4305 && i.suffix != XMMWORD_MNEM_SUFFIX
4306 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4307 {
4308 /* It's not a byte, select word/dword operation. */
40fb9820 4309 if (i.tm.opcode_modifier.w)
29b0f896 4310 {
40fb9820 4311 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4312 i.tm.base_opcode |= 8;
4313 else
4314 i.tm.base_opcode |= 1;
4315 }
0f3f3d8b 4316
29b0f896
AM		 4317 /* Now select between word & dword operations via the operand
4318 size prefix, except for instructions that will ignore this
4319 prefix anyway. */
ca61edf2 4320 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4321 {
ca61edf2
L		 4322 /* The address size override prefix changes the size of the
4323 first operand. */
40fb9820
L		 4324 if ((flag_code == CODE_32BIT
4325 && i.op->regs[0].reg_type.bitfield.reg16)
4326 || (flag_code != CODE_32BIT
4327 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4328 if (!add_prefix (ADDR_PREFIX_OPCODE))
4329 return 0;
4330 }
4331 else if (i.suffix != QWORD_MNEM_SUFFIX
4332 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4333 && !i.tm.opcode_modifier.ignoresize
4334 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4335 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4336 || (flag_code == CODE_64BIT
40fb9820 4337 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4338 {
4339 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4340
40fb9820 4341 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4342 prefix = ADDR_PREFIX_OPCODE;
252b5132 4343
29b0f896
AM		 4344 if (!add_prefix (prefix))
4345 return 0;
24eab124 4346 }
252b5132 4347
29b0f896
AM		 4348 /* Set mode64 for an operand. */
4349 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4350 && flag_code == CODE_64BIT
40fb9820 4351 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4352 {
4353 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4354 need rex64. cmpxchg8b is also a special case. */
4355 if (! (i.operands == 2
4356 && i.tm.base_opcode == 0x90
4357 && i.tm.extension_opcode == None
0dfbf9d7
L		 4358 && operand_type_equal (&i.types [0], &acc64)
4359 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4360 && ! (i.operands == 1
4361 && i.tm.base_opcode == 0xfc7
4362 && i.tm.extension_opcode == 1
40fb9820
L		 4363 && !operand_type_check (i.types [0], reg)
4364 && operand_type_check (i.types [0], anymem)))
f6bee062 4365 i.rex |= REX_W;
46e883c5 4366 }
3e73aa7c 4367
29b0f896
AM		 4368 /* Size floating point instruction. */
4369 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4370 if (i.tm.opcode_modifier.floatmf)
543613e9 4371 i.tm.base_opcode ^= 4;
29b0f896 4372 }
7ecd2f8b 4373
29b0f896
AM		 4374 return 1;
4375}
3e73aa7c 4376
29b0f896 4377static int
543613e9 4378check_byte_reg (void)
29b0f896
AM		 4379{
4380 int op;
543613e9 4381
29b0f896
AM		 4382 for (op = i.operands; --op >= 0;)
4383 {
4384 /* If this is an eight bit register, it's OK. If it's the 16 or
4385 32 bit version of an eight bit register, we will just use the
4386 low portion, and that's OK too. */
40fb9820 4387 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4388 continue;
4389
9344ff29
L		 4390 /* crc32 doesn't generate this warning. */
4391 if (i.tm.base_opcode == 0xf20f38f0)
4392 continue;
4393
40fb9820
L		 4394 if ((i.types[op].bitfield.reg16
4395 || i.types[op].bitfield.reg32
4396 || i.types[op].bitfield.reg64)
4397 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4398 {
4399 /* Prohibit these changes in the 64bit mode, since the
4400 lowering is more complicated. */
4401 if (flag_code == CODE_64BIT
40fb9820 4402 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4403 {
2ca3ace5
L		 4404 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4405 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4406 i.suffix);
4407 return 0;
4408 }
4409#if REGISTER_WARNINGS
4410 if (!quiet_warnings
40fb9820 4411 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4413 register_prefix,
40fb9820 4414 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4415 ? REGNAM_AL - REGNAM_AX
4416 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4417 register_prefix,
29b0f896
AM		 4418 i.op[op].regs->reg_name,
4419 i.suffix);
4420#endif
4421 continue;
4422 }
4423 /* Any other register is bad. */
40fb9820
L		 4424 if (i.types[op].bitfield.reg16
4425 || i.types[op].bitfield.reg32
4426 || i.types[op].bitfield.reg64
4427 || i.types[op].bitfield.regmmx
4428 || i.types[op].bitfield.regxmm
c0f3af97 4429 || i.types[op].bitfield.regymm
40fb9820
L		 4430 || i.types[op].bitfield.sreg2
4431 || i.types[op].bitfield.sreg3
4432 || i.types[op].bitfield.control
4433 || i.types[op].bitfield.debug
4434 || i.types[op].bitfield.test
4435 || i.types[op].bitfield.floatreg
4436 || i.types[op].bitfield.floatacc)
29b0f896 4437 {
a540244d
L		 4438 as_bad (_("`%s%s' not allowed with `%s%c'"),
4439 register_prefix,
29b0f896
AM		 4440 i.op[op].regs->reg_name,
4441 i.tm.name,
4442 i.suffix);
4443 return 0;
4444 }
4445 }
4446 return 1;
4447}
4448
4449static int
e3bb37b5 4450check_long_reg (void)
29b0f896
AM		 4451{
4452 int op;
4453
4454 for (op = i.operands; --op >= 0;)
4455 /* Reject eight bit registers, except where the template requires
4456 them. (eg. movzb) */
40fb9820
L		 4457 if (i.types[op].bitfield.reg8
4458 && (i.tm.operand_types[op].bitfield.reg16
4459 || i.tm.operand_types[op].bitfield.reg32
4460 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4461 {
a540244d
L		 4462 as_bad (_("`%s%s' not allowed with `%s%c'"),
4463 register_prefix,
29b0f896
AM		 4464 i.op[op].regs->reg_name,
4465 i.tm.name,
4466 i.suffix);
4467 return 0;
4468 }
4469 /* Warn if the e prefix on a general reg is missing. */
4470 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4471 && i.types[op].bitfield.reg16
4472 && (i.tm.operand_types[op].bitfield.reg32
4473 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4474 {
4475 /* Prohibit these changes in the 64bit mode, since the
4476 lowering is more complicated. */
4477 if (flag_code == CODE_64BIT)
252b5132 4478 {
2ca3ace5
L		 4479 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4480 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4481 i.suffix);
4482 return 0;
252b5132 4483 }
29b0f896
AM		 4484#if REGISTER_WARNINGS
4485 else
a540244d
L		 4486 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4487 register_prefix,
29b0f896 4488 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4489 register_prefix,
29b0f896
AM		 4490 i.op[op].regs->reg_name,
4491 i.suffix);
4492#endif
252b5132 4493 }
29b0f896 4494 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4495 else if (i.types[op].bitfield.reg64
4496 && (i.tm.operand_types[op].bitfield.reg32
4497 || i.tm.operand_types[op].bitfield.acc))
252b5132 4498 {
34828aad 4499 if (intel_syntax
ca61edf2 4500 && i.tm.opcode_modifier.toqword
40fb9820 4501 && !i.types[0].bitfield.regxmm)
34828aad 4502 {
ca61edf2 4503 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4504 i.suffix = QWORD_MNEM_SUFFIX;
4505 }
4506 else
4507 {
4508 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4509 register_prefix, i.op[op].regs->reg_name,
4510 i.suffix);
4511 return 0;
4512 }
29b0f896
AM		 4513 }
4514 return 1;
4515}
252b5132 4516
29b0f896 4517static int
e3bb37b5 4518check_qword_reg (void)
29b0f896
AM		 4519{
4520 int op;
252b5132 4521
29b0f896
AM		 4522 for (op = i.operands; --op >= 0; )
4523 /* Reject eight bit registers, except where the template requires
4524 them. (eg. movzb) */
40fb9820
L		 4525 if (i.types[op].bitfield.reg8
4526 && (i.tm.operand_types[op].bitfield.reg16
4527 || i.tm.operand_types[op].bitfield.reg32
4528 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4529 {
a540244d
L		 4530 as_bad (_("`%s%s' not allowed with `%s%c'"),
4531 register_prefix,
29b0f896
AM		 4532 i.op[op].regs->reg_name,
4533 i.tm.name,
4534 i.suffix);
4535 return 0;
4536 }
4537 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4538 else if ((i.types[op].bitfield.reg16
4539 || i.types[op].bitfield.reg32)
4540 && (i.tm.operand_types[op].bitfield.reg32
4541 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4542 {
4543 /* Prohibit these changes in the 64bit mode, since the
4544 lowering is more complicated. */
34828aad 4545 if (intel_syntax
ca61edf2 4546 && i.tm.opcode_modifier.todword
40fb9820 4547 && !i.types[0].bitfield.regxmm)
34828aad 4548 {
ca61edf2 4549 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4550 i.suffix = LONG_MNEM_SUFFIX;
4551 }
4552 else
4553 {
4554 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4555 register_prefix, i.op[op].regs->reg_name,
4556 i.suffix);
4557 return 0;
4558 }
252b5132 4559 }
29b0f896
AM		 4560 return 1;
4561}
252b5132 4562
29b0f896 4563static int
e3bb37b5 4564check_word_reg (void)
29b0f896
AM		 4565{
4566 int op;
4567 for (op = i.operands; --op >= 0;)
4568 /* Reject eight bit registers, except where the template requires
4569 them. (eg. movzb) */
40fb9820
L		 4570 if (i.types[op].bitfield.reg8
4571 && (i.tm.operand_types[op].bitfield.reg16
4572 || i.tm.operand_types[op].bitfield.reg32
4573 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4574 {
a540244d
L		 4575 as_bad (_("`%s%s' not allowed with `%s%c'"),
4576 register_prefix,
29b0f896
AM		 4577 i.op[op].regs->reg_name,
4578 i.tm.name,
4579 i.suffix);
4580 return 0;
4581 }
4582 /* Warn if the e prefix on a general reg is present. */
4583 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4584 && i.types[op].bitfield.reg32
4585 && (i.tm.operand_types[op].bitfield.reg16
4586 || i.tm.operand_types[op].bitfield.acc))
252b5132 4587 {
29b0f896
AM		 4588 /* Prohibit these changes in the 64bit mode, since the
4589 lowering is more complicated. */
4590 if (flag_code == CODE_64BIT)
252b5132 4591 {
2ca3ace5
L		 4592 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4593 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4594 i.suffix);
4595 return 0;
252b5132 4596 }
29b0f896
AM		 4597 else
4598#if REGISTER_WARNINGS
a540244d
L		 4599 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4600 register_prefix,
29b0f896 4601 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4602 register_prefix,
29b0f896
AM		 4603 i.op[op].regs->reg_name,
4604 i.suffix);
4605#endif
4606 }
4607 return 1;
4608}
252b5132 4609
29b0f896 4610static int
40fb9820 4611update_imm (unsigned int j)
29b0f896 4612{
bc0844ae 4613 i386_operand_type overlap = i.types[j];
40fb9820
L		 4614 if ((overlap.bitfield.imm8
4615 || overlap.bitfield.imm8s
4616 || overlap.bitfield.imm16
4617 || overlap.bitfield.imm32
4618 || overlap.bitfield.imm32s
4619 || overlap.bitfield.imm64)
0dfbf9d7
L		 4620 && !operand_type_equal (&overlap, &imm8)
4621 && !operand_type_equal (&overlap, &imm8s)
4622 && !operand_type_equal (&overlap, &imm16)
4623 && !operand_type_equal (&overlap, &imm32)
4624 && !operand_type_equal (&overlap, &imm32s)
4625 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4626 {
4627 if (i.suffix)
4628 {
40fb9820
L		 4629 i386_operand_type temp;
4630
0dfbf9d7 4631 operand_type_set (&temp, 0);
7ab9ffdd 4632 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4633 {
4634 temp.bitfield.imm8 = overlap.bitfield.imm8;
4635 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4636 }
4637 else if (i.suffix == WORD_MNEM_SUFFIX)
4638 temp.bitfield.imm16 = overlap.bitfield.imm16;
4639 else if (i.suffix == QWORD_MNEM_SUFFIX)
4640 {
4641 temp.bitfield.imm64 = overlap.bitfield.imm64;
4642 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4643 }
4644 else
4645 temp.bitfield.imm32 = overlap.bitfield.imm32;
4646 overlap = temp;
29b0f896 4647 }
0dfbf9d7
L		 4648 else if (operand_type_equal (&overlap, &imm16_32_32s)
4649 || operand_type_equal (&overlap, &imm16_32)
4650 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4651 {
40fb9820 4652 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4653 overlap = imm16;
40fb9820 4654 else
65da13b5 4655 overlap = imm32s;
29b0f896 4656 }
0dfbf9d7
L		 4657 if (!operand_type_equal (&overlap, &imm8)
4658 && !operand_type_equal (&overlap, &imm8s)
4659 && !operand_type_equal (&overlap, &imm16)
4660 && !operand_type_equal (&overlap, &imm32)
4661 && !operand_type_equal (&overlap, &imm32s)
4662 && !operand_type_equal (&overlap, &imm64))
29b0f896 4663 {
4eed87de
AM		 4664 as_bad (_("no instruction mnemonic suffix given; "
4665 "can't determine immediate size"));
29b0f896
AM		 4666 return 0;
4667 }
4668 }
40fb9820 4669 i.types[j] = overlap;
29b0f896 4670
40fb9820
L		 4671 return 1;
4672}
4673
4674static int
4675finalize_imm (void)
4676{
bc0844ae 4677 unsigned int j, n;
29b0f896 4678
bc0844ae
L		 4679 /* Update the first 2 immediate operands. */
4680 n = i.operands > 2 ? 2 : i.operands;
4681 if (n)
4682 {
4683 for (j = 0; j < n; j++)
4684 if (update_imm (j) == 0)
4685 return 0;
40fb9820 4686
bc0844ae
L		 4687 /* The 3rd operand can't be immediate operand. */
4688 gas_assert (operand_type_check (i.types[2], imm) == 0);
4689 }
29b0f896
AM		 4690
4691 return 1;
4692}
4693
c0f3af97
L		 4694static int
4695bad_implicit_operand (int xmm)
4696{
91d6fa6a
NC		 4697 const char *ireg = xmm ? "xmm0" : "ymm0";
4698
c0f3af97
L		 4699 if (intel_syntax)
4700 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4701 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4702 else
4703 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4704 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4705 return 0;
4706}
4707
29b0f896 4708static int
e3bb37b5 4709process_operands (void)
29b0f896
AM		 4710{
4711 /* Default segment register this instruction will use for memory
4712 accesses. 0 means unknown. This is only for optimizing out
4713 unnecessary segment overrides. */
4714 const seg_entry *default_seg = 0;
4715
2426c15f 4716 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4717 {
91d6fa6a
NC		 4718 unsigned int dupl = i.operands;
4719 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4720 unsigned int j;
4721
c0f3af97 4722 /* The destination must be an xmm register. */
9c2799c2 4723 gas_assert (i.reg_operands
91d6fa6a 4724 && MAX_OPERANDS > dupl
7ab9ffdd 4725 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4726
4727 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4728 {
c0f3af97 4729 /* The first operand is implicit and must be xmm0. */
9c2799c2 4730 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4731 if (i.op[0].regs->reg_num != 0)
4732 return bad_implicit_operand (1);
4733
8cd7925b 4734 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4735 {
4736 /* Keep xmm0 for instructions with VEX prefix and 3
4737 sources. */
4738 goto duplicate;
4739 }
e2ec9d29 4740 else
c0f3af97
L		 4741 {
4742 /* We remove the first xmm0 and keep the number of
4743 operands unchanged, which in fact duplicates the
4744 destination. */
4745 for (j = 1; j < i.operands; j++)
4746 {
4747 i.op[j - 1] = i.op[j];
4748 i.types[j - 1] = i.types[j];
4749 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4750 }
4751 }
4752 }
4753 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4754 {
91d6fa6a 4755 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4756 && (i.tm.opcode_modifier.vexsources
4757 == VEX3SOURCES));
c0f3af97
L		 4758
4759 /* Add the implicit xmm0 for instructions with VEX prefix
4760 and 3 sources. */
4761 for (j = i.operands; j > 0; j--)
4762 {
4763 i.op[j] = i.op[j - 1];
4764 i.types[j] = i.types[j - 1];
4765 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4766 }
4767 i.op[0].regs
4768 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4769 i.types[0] = regxmm;
c0f3af97
L		 4770 i.tm.operand_types[0] = regxmm;
4771
4772 i.operands += 2;
4773 i.reg_operands += 2;
4774 i.tm.operands += 2;
4775
91d6fa6a 4776 dupl++;
c0f3af97 4777 dest++;
91d6fa6a
NC		 4778 i.op[dupl] = i.op[dest];
4779 i.types[dupl] = i.types[dest];
4780 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4781 }
c0f3af97
L		 4782 else
4783 {
4784duplicate:
4785 i.operands++;
4786 i.reg_operands++;
4787 i.tm.operands++;
4788
91d6fa6a
NC		 4789 i.op[dupl] = i.op[dest];
4790 i.types[dupl] = i.types[dest];
4791 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4792 }
4793
4794 if (i.tm.opcode_modifier.immext)
4795 process_immext ();
4796 }
4797 else if (i.tm.opcode_modifier.firstxmm0)
4798 {
4799 unsigned int j;
4800
4801 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4802 gas_assert (i.reg_operands
7ab9ffdd
L		 4803 && (operand_type_equal (&i.types[0], &regxmm)
4804 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4805 if (i.op[0].regs->reg_num != 0)
4806 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4807
4808 for (j = 1; j < i.operands; j++)
4809 {
4810 i.op[j - 1] = i.op[j];
4811 i.types[j - 1] = i.types[j];
4812
4813 /* We need to adjust fields in i.tm since they are used by
4814 build_modrm_byte. */
4815 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4816 }
4817
e2ec9d29
L		 4818 i.operands--;
4819 i.reg_operands--;
e2ec9d29
L		 4820 i.tm.operands--;
4821 }
4822 else if (i.tm.opcode_modifier.regkludge)
4823 {
4824 /* The imul $imm, %reg instruction is converted into
4825 imul $imm, %reg, %reg, and the clr %reg instruction
4826 is converted into xor %reg, %reg. */
4827
4828 unsigned int first_reg_op;
4829
4830 if (operand_type_check (i.types[0], reg))
4831 first_reg_op = 0;
4832 else
4833 first_reg_op = 1;
4834 /* Pretend we saw the extra register operand. */
9c2799c2 4835 gas_assert (i.reg_operands == 1
7ab9ffdd 4836 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4837 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4838 i.types[first_reg_op + 1] = i.types[first_reg_op];
4839 i.operands++;
4840 i.reg_operands++;
29b0f896
AM		 4841 }
4842
40fb9820 4843 if (i.tm.opcode_modifier.shortform)
29b0f896 4844 {
40fb9820
L		 4845 if (i.types[0].bitfield.sreg2
4846 || i.types[0].bitfield.sreg3)
29b0f896 4847 {
4eed87de
AM		 4848 if (i.tm.base_opcode == POP_SEG_SHORT
4849 && i.op[0].regs->reg_num == 1)
29b0f896 4850 {
a87af027 4851 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4852 return 0;
29b0f896 4853 }
4eed87de
AM		 4854 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4855 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4856 i.rex |= REX_B;
4eed87de
AM		 4857 }
4858 else
4859 {
7ab9ffdd 4860 /* The register or float register operand is in operand
85f10a01 4861 0 or 1. */
40fb9820 4862 unsigned int op;
7ab9ffdd
L		 4863
4864 if (i.types[0].bitfield.floatreg
4865 || operand_type_check (i.types[0], reg))
4866 op = 0;
4867 else
4868 op = 1;
4eed87de
AM		 4869 /* Register goes in low 3 bits of opcode. */
4870 i.tm.base_opcode |= i.op[op].regs->reg_num;
4871 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4872 i.rex |= REX_B;
40fb9820 4873 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4874 {
4eed87de
AM		 4875 /* Warn about some common errors, but press on regardless.
4876 The first case can be generated by gcc (<= 2.8.1). */
4877 if (i.operands == 2)
4878 {
4879 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4880 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4881 register_prefix, i.op[!intel_syntax].regs->reg_name,
4882 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4883 }
4884 else
4885 {
4886 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4887 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4888 register_prefix, i.op[0].regs->reg_name);
4eed87de 4889 }
29b0f896
AM		 4890 }
4891 }
4892 }
40fb9820 4893 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4894 {
4895 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4896 must be put into the modrm byte). Now, we make the modrm and
4897 index base bytes based on all the info we've collected. */
29b0f896
AM		 4898
4899 default_seg = build_modrm_byte ();
4900 }
8a2ed489 4901 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4902 {
4903 default_seg = &ds;
4904 }
40fb9820 4905 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4906 {
4907 /* For the string instructions that allow a segment override
4908 on one of their operands, the default segment is ds. */
4909 default_seg = &ds;
4910 }
4911
75178d9d
L		 4912 if (i.tm.base_opcode == 0x8d /* lea */
4913 && i.seg[0]
4914 && !quiet_warnings)
30123838 4915 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4916
4917 /* If a segment was explicitly specified, and the specified segment
4918 is not the default, use an opcode prefix to select it. If we
4919 never figured out what the default segment is, then default_seg
4920 will be zero at this point, and the specified segment prefix will
4921 always be used. */
29b0f896
AM		 4922 if ((i.seg[0]) && (i.seg[0] != default_seg))
4923 {
4924 if (!add_prefix (i.seg[0]->seg_prefix))
4925 return 0;
4926 }
4927 return 1;
4928}
4929
4930static const seg_entry *
e3bb37b5 4931build_modrm_byte (void)
29b0f896
AM		 4932{
4933 const seg_entry *default_seg = 0;
c0f3af97 4934 unsigned int source, dest;
8cd7925b 4935 int vex_3_sources;
c0f3af97
L		 4936
4937 /* The first operand of instructions with VEX prefix and 3 sources
4938 must be VEX_Imm4. */
8cd7925b 4939 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 4940 if (vex_3_sources)
4941 {
91d6fa6a 4942 unsigned int nds, reg_slot;
4c2c6516 4943 expressionS *exp;
c0f3af97 4944
922d8de8
DR		 4945 if (i.tm.opcode_modifier.veximmext
4946 && i.tm.opcode_modifier.immext)
4947 {
4948 dest = i.operands - 2;
4949 gas_assert (dest == 3);
4950 }
4951 else
91d6fa6a 4952 dest = i.operands - 1;
c0f3af97 4953 nds = dest - 1;
922d8de8 4954
76ba9986
L		 4955 /* This instruction must have 4 register operands
4956 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4957 It must have VexNDS and VexImmExt. */
4958 gas_assert ((i.reg_operands == 4
7ab9ffdd 4959 || (i.reg_operands == 3 && i.mem_operands == 1))
2426c15f 4960 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 4961 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4962 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4963 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4964
0bfee649
L		 4965 /* Generate an 8bit immediate operand to encode the register
4966 operand. */
4c2c6516 4967 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4968 i.op[i.operands].imms = exp;
4969 i.types[i.operands] = imm8;
4970 i.operands++;
922d8de8
DR		 4971 /* If VexW1 is set, the first operand is the source and
4972 the second operand is encoded in the immediate operand. */
1ef99a7b 4973 if (i.tm.opcode_modifier.vexw == VEXW1)
922d8de8
DR		 4974 {
4975 source = 0;
91d6fa6a 4976 reg_slot = 1;
922d8de8
DR		 4977 }
4978 else
4979 {
4980 source = 1;
91d6fa6a 4981 reg_slot = 0;
76ba9986 4982 }
91d6fa6a
NC		 4983 gas_assert ((operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
4984 || operand_type_equal (&i.tm.operand_types[reg_slot],
76ba9986 4985 &regymm))
922d8de8 4986 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4987 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4988 &regymm)));
0bfee649
L		 4989 exp->X_op = O_constant;
4990 exp->X_add_number
91d6fa6a
NC		 4991 = ((i.op[reg_slot].regs->reg_num
4992 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4993 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4994 }
4995 else
4996 source = dest = 0;
29b0f896
AM		 4997
4998 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4999 implicit registers do not count. If there are 3 register
5000 operands, it must be a instruction with VexNDS. For a
5001 instruction with VexNDD, the destination register is encoded
5002 in VEX prefix. If there are 4 register operands, it must be
5003 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5004 if (i.mem_operands == 0
5005 && ((i.reg_operands == 2
2426c15f 5006 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5007 || (i.reg_operands == 3
2426c15f 5008 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5009 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5010 {
cab737b9
L		 5011 switch (i.operands)
5012 {
5013 case 2:
5014 source = 0;
5015 break;
5016 case 3:
c81128dc
L		 5017 /* When there are 3 operands, one of them may be immediate,
5018 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5019 the first operand must be shift count register (cl) or it
5020 is an instruction with VexNDS. */
9c2799c2 5021 gas_assert (i.imm_operands == 1
7ab9ffdd 5022 || (i.imm_operands == 0
2426c15f 5023 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5024 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5025 if (operand_type_check (i.types[0], imm)
5026 || i.types[0].bitfield.shiftcount)
5027 source = 1;
5028 else
5029 source = 0;
cab737b9
L		 5030 break;
5031 case 4:
368d64cc
L		 5032 /* When there are 4 operands, the first two must be 8bit
5033 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5034 one.
5035
5036 For instructions with VexNDS, if the first operand
5037 an imm8, the source operand is the 2nd one. If the last
5038 operand is imm8, the source operand is the first one. */
9c2799c2 5039 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5040 && i.types[0].bitfield.imm8
5041 && i.types[1].bitfield.imm8)
2426c15f 5042 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5043 && i.imm_operands == 1
5044 && (i.types[0].bitfield.imm8
5045 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5046 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5047 {
5048 if (i.types[0].bitfield.imm8)
5049 source = 1;
5050 else
5051 source = 0;
5052 }
5053 else
5054 source = 2;
5055 break;
5056 case 5:
cab737b9
L		 5057 break;
5058 default:
5059 abort ();
5060 }
5061
c0f3af97
L		 5062 if (!vex_3_sources)
5063 {
5064 dest = source + 1;
5065
2426c15f 5066 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5067 {
5068 /* For instructions with VexNDS, the register-only
5069 source operand must be XMM or YMM register. It is
fa99fab2
L		 5070 encoded in VEX prefix. We need to clear RegMem bit
5071 before calling operand_type_equal. */
5072 i386_operand_type op = i.tm.operand_types[dest];
5073 op.bitfield.regmem = 0;
c0f3af97 5074 if ((dest + 1) >= i.operands
fa99fab2
L		 5075 || (!operand_type_equal (&op, &regxmm)
5076 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5077 abort ();
5078 i.vex.register_specifier = i.op[dest].regs;
5079 dest++;
5080 }
5081 }
29b0f896
AM		 5082
5083 i.rm.mode = 3;
5084 /* One of the register operands will be encoded in the i.tm.reg
5085 field, the other in the combined i.tm.mode and i.tm.regmem
5086 fields. If no form of this instruction supports a memory
5087 destination operand, then we assume the source operand may
5088 sometimes be a memory operand and so we need to store the
5089 destination in the i.rm.reg field. */
40fb9820
L		 5090 if (!i.tm.operand_types[dest].bitfield.regmem
5091 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5092 {
5093 i.rm.reg = i.op[dest].regs->reg_num;
5094 i.rm.regmem = i.op[source].regs->reg_num;
5095 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5096 i.rex |= REX_R;
29b0f896 5097 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5098 i.rex |= REX_B;
29b0f896
AM		 5099 }
5100 else
5101 {
5102 i.rm.reg = i.op[source].regs->reg_num;
5103 i.rm.regmem = i.op[dest].regs->reg_num;
5104 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5105 i.rex |= REX_B;
29b0f896 5106 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5107 i.rex |= REX_R;
29b0f896 5108 }
161a04f6 5109 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5110 {
40fb9820
L		 5111 if (!i.types[0].bitfield.control
5112 && !i.types[1].bitfield.control)
c4a530c5 5113 abort ();
161a04f6 5114 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5115 add_prefix (LOCK_PREFIX_OPCODE);
5116 }
29b0f896
AM		 5117 }
5118 else
5119 { /* If it's not 2 reg operands... */
c0f3af97
L		 5120 unsigned int mem;
5121
29b0f896
AM		 5122 if (i.mem_operands)
5123 {
5124 unsigned int fake_zero_displacement = 0;
99018f42 5125 unsigned int op;
4eed87de 5126
7ab9ffdd
L		 5127 for (op = 0; op < i.operands; op++)
5128 if (operand_type_check (i.types[op], anymem))
5129 break;
7ab9ffdd 5130 gas_assert (op < i.operands);
29b0f896
AM		 5131
5132 default_seg = &ds;
5133
5134 if (i.base_reg == 0)
5135 {
5136 i.rm.mode = 0;
5137 if (!i.disp_operands)
5138 fake_zero_displacement = 1;
5139 if (i.index_reg == 0)
5140 {
5141 /* Operand is just <disp> */
20f0a1fc 5142 if (flag_code == CODE_64BIT)
29b0f896
AM		 5143 {
5144 /* 64bit mode overwrites the 32bit absolute
5145 addressing by RIP relative addressing and
5146 absolute addressing is encoded by one of the
5147 redundant SIB forms. */
5148 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5149 i.sib.base = NO_BASE_REGISTER;
5150 i.sib.index = NO_INDEX_REGISTER;
fc225355 5151 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5152 ? disp32s : disp32);
20f0a1fc 5153 }
fc225355
L		 5154 else if ((flag_code == CODE_16BIT)
5155 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5156 {
5157 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5158 i.types[op] = disp16;
20f0a1fc
NC		 5159 }
5160 else
5161 {
5162 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5163 i.types[op] = disp32;
29b0f896
AM		 5164 }
5165 }
5166 else /* !i.base_reg && i.index_reg */
5167 {
db51cc60
L		 5168 if (i.index_reg->reg_num == RegEiz
5169 || i.index_reg->reg_num == RegRiz)
5170 i.sib.index = NO_INDEX_REGISTER;
5171 else
5172 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5173 i.sib.base = NO_BASE_REGISTER;
5174 i.sib.scale = i.log2_scale_factor;
5175 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5176 i.types[op].bitfield.disp8 = 0;
5177 i.types[op].bitfield.disp16 = 0;
5178 i.types[op].bitfield.disp64 = 0;
29b0f896 5179 if (flag_code != CODE_64BIT)
40fb9820
L		 5180 {
5181 /* Must be 32 bit */
5182 i.types[op].bitfield.disp32 = 1;
5183 i.types[op].bitfield.disp32s = 0;
5184 }
29b0f896 5185 else
40fb9820
L		 5186 {
5187 i.types[op].bitfield.disp32 = 0;
5188 i.types[op].bitfield.disp32s = 1;
5189 }
29b0f896 5190 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5191 i.rex |= REX_X;
29b0f896
AM		 5192 }
5193 }
5194 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5195 else if (i.base_reg->reg_num == RegRip ||
5196 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5197 {
5198 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5199 i.types[op].bitfield.disp8 = 0;
5200 i.types[op].bitfield.disp16 = 0;
5201 i.types[op].bitfield.disp32 = 0;
5202 i.types[op].bitfield.disp32s = 1;
5203 i.types[op].bitfield.disp64 = 0;
71903a11 5204 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5205 if (! i.disp_operands)
5206 fake_zero_displacement = 1;
29b0f896 5207 }
40fb9820 5208 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5209 {
5210 switch (i.base_reg->reg_num)
5211 {
5212 case 3: /* (%bx) */
5213 if (i.index_reg == 0)
5214 i.rm.regmem = 7;
5215 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5216 i.rm.regmem = i.index_reg->reg_num - 6;
5217 break;
5218 case 5: /* (%bp) */
5219 default_seg = &ss;
5220 if (i.index_reg == 0)
5221 {
5222 i.rm.regmem = 6;
40fb9820 5223 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5224 {
5225 /* fake (%bp) into 0(%bp) */
40fb9820 5226 i.types[op].bitfield.disp8 = 1;
252b5132 5227 fake_zero_displacement = 1;
29b0f896
AM		 5228 }
5229 }
5230 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5231 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5232 break;
5233 default: /* (%si) -> 4 or (%di) -> 5 */
5234 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5235 }
5236 i.rm.mode = mode_from_disp_size (i.types[op]);
5237 }
5238 else /* i.base_reg and 32/64 bit mode */
5239 {
5240 if (flag_code == CODE_64BIT
40fb9820
L		 5241 && operand_type_check (i.types[op], disp))
5242 {
5243 i386_operand_type temp;
0dfbf9d7 5244 operand_type_set (&temp, 0);
40fb9820
L		 5245 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5246 i.types[op] = temp;
5247 if (i.prefix[ADDR_PREFIX] == 0)
5248 i.types[op].bitfield.disp32s = 1;
5249 else
5250 i.types[op].bitfield.disp32 = 1;
5251 }
20f0a1fc 5252
29b0f896
AM		 5253 i.rm.regmem = i.base_reg->reg_num;
5254 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5255 i.rex |= REX_B;
29b0f896
AM		 5256 i.sib.base = i.base_reg->reg_num;
5257 /* x86-64 ignores REX prefix bit here to avoid decoder
5258 complications. */
5259 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5260 {
5261 default_seg = &ss;
5262 if (i.disp_operands == 0)
5263 {
5264 fake_zero_displacement = 1;
40fb9820 5265 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5266 }
5267 }
5268 else if (i.base_reg->reg_num == ESP_REG_NUM)
5269 {
5270 default_seg = &ss;
5271 }
5272 i.sib.scale = i.log2_scale_factor;
5273 if (i.index_reg == 0)
5274 {
5275 /* <disp>(%esp) becomes two byte modrm with no index
5276 register. We've already stored the code for esp
5277 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5278 Any base register besides %esp will not use the
5279 extra modrm byte. */
5280 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5281 }
5282 else
5283 {
db51cc60
L		 5284 if (i.index_reg->reg_num == RegEiz
5285 || i.index_reg->reg_num == RegRiz)
5286 i.sib.index = NO_INDEX_REGISTER;
5287 else
5288 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5289 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5290 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5291 i.rex |= REX_X;
29b0f896 5292 }
67a4f2b7
AO		 5293
5294 if (i.disp_operands
5295 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5296 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5297 i.rm.mode = 0;
5298 else
5299 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5300 }
252b5132 5301
29b0f896
AM		 5302 if (fake_zero_displacement)
5303 {
5304 /* Fakes a zero displacement assuming that i.types[op]
5305 holds the correct displacement size. */
5306 expressionS *exp;
5307
9c2799c2 5308 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5309 exp = &disp_expressions[i.disp_operands++];
5310 i.op[op].disps = exp;
5311 exp->X_op = O_constant;
5312 exp->X_add_number = 0;
5313 exp->X_add_symbol = (symbolS *) 0;
5314 exp->X_op_symbol = (symbolS *) 0;
5315 }
c0f3af97
L		 5316
5317 mem = op;
29b0f896 5318 }
c0f3af97
L		 5319 else
5320 mem = ~0;
252b5132 5321
8c43a48b 5322 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5323 {
5324 if (operand_type_check (i.types[0], imm))
5325 i.vex.register_specifier = NULL;
5326 else
5327 {
5328 /* VEX.vvvv encodes one of the sources when the first
5329 operand is not an immediate. */
1ef99a7b 5330 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5331 i.vex.register_specifier = i.op[0].regs;
5332 else
5333 i.vex.register_specifier = i.op[1].regs;
5334 }
5335
5336 /* Destination is a XMM register encoded in the ModRM.reg
5337 and VEX.R bit. */
5338 i.rm.reg = i.op[2].regs->reg_num;
5339 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5340 i.rex |= REX_R;
5341
5342 /* ModRM.rm and VEX.B encodes the other source. */
5343 if (!i.mem_operands)
5344 {
5345 i.rm.mode = 3;
5346
1ef99a7b 5347 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5348 i.rm.regmem = i.op[1].regs->reg_num;
5349 else
5350 i.rm.regmem = i.op[0].regs->reg_num;
5351
5352 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5353 i.rex |= REX_B;
5354 }
5355 }
2426c15f 5356 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5357 {
5358 i.vex.register_specifier = i.op[2].regs;
5359 if (!i.mem_operands)
5360 {
5361 i.rm.mode = 3;
5362 i.rm.regmem = i.op[1].regs->reg_num;
5363 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5364 i.rex |= REX_B;
5365 }
5366 }
29b0f896
AM		 5367 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5368 (if any) based on i.tm.extension_opcode. Again, we must be
5369 careful to make sure that segment/control/debug/test/MMX
5370 registers are coded into the i.rm.reg field. */
f88c9eb0 5371 else if (i.reg_operands)
29b0f896 5372 {
99018f42 5373 unsigned int op;
7ab9ffdd
L		 5374 unsigned int vex_reg = ~0;
5375
5376 for (op = 0; op < i.operands; op++)
5377 if (i.types[op].bitfield.reg8
5378 || i.types[op].bitfield.reg16
5379 || i.types[op].bitfield.reg32
5380 || i.types[op].bitfield.reg64
5381 || i.types[op].bitfield.regmmx
5382 || i.types[op].bitfield.regxmm
5383 || i.types[op].bitfield.regymm
5384 || i.types[op].bitfield.sreg2
5385 || i.types[op].bitfield.sreg3
5386 || i.types[op].bitfield.control
5387 || i.types[op].bitfield.debug
5388 || i.types[op].bitfield.test)
5389 break;
c0209578 5390
7ab9ffdd
L		 5391 if (vex_3_sources)
5392 op = dest;
2426c15f 5393 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5394 {
5395 /* For instructions with VexNDS, the register-only
5396 source operand is encoded in VEX prefix. */
5397 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5398
7ab9ffdd 5399 if (op > mem)
c0f3af97 5400 {
7ab9ffdd
L		 5401 vex_reg = op++;
5402 gas_assert (op < i.operands);
c0f3af97
L		 5403 }
5404 else
c0f3af97 5405 {
7ab9ffdd
L		 5406 vex_reg = op + 1;
5407 gas_assert (vex_reg < i.operands);
c0f3af97 5408 }
7ab9ffdd 5409 }
2426c15f 5410 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5411 {
5412 /* For instructions with VexNDD, there should be
5413 no memory operand and the register destination
5414 is encoded in VEX prefix. */
5415 gas_assert (i.mem_operands == 0
5416 && (op + 2) == i.operands);
5417 vex_reg = op + 1;
5418 }
5419 else
5420 gas_assert (op < i.operands);
99018f42 5421
7ab9ffdd
L		 5422 if (vex_reg != (unsigned int) ~0)
5423 {
5424 gas_assert (i.reg_operands == 2);
5425
5426 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5427 &regxmm)
7ab9ffdd
L		 5428 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5429 &regymm))
5430 abort ();
f88c9eb0 5431
7ab9ffdd
L		 5432 i.vex.register_specifier = i.op[vex_reg].regs;
5433 }
5434
1b9f0c97
L		 5435 /* Don't set OP operand twice. */
5436 if (vex_reg != op)
7ab9ffdd 5437 {
1b9f0c97
L		 5438 /* If there is an extension opcode to put here, the
5439 register number must be put into the regmem field. */
5440 if (i.tm.extension_opcode != None)
5441 {
5442 i.rm.regmem = i.op[op].regs->reg_num;
5443 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5444 i.rex |= REX_B;
5445 }
5446 else
5447 {
5448 i.rm.reg = i.op[op].regs->reg_num;
5449 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5450 i.rex |= REX_R;
5451 }
7ab9ffdd 5452 }
252b5132 5453
29b0f896
AM		 5454 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5455 must set it to 3 to indicate this is a register operand
5456 in the regmem field. */
5457 if (!i.mem_operands)
5458 i.rm.mode = 3;
5459 }
252b5132 5460
29b0f896 5461 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5462 if (i.tm.extension_opcode != None)
29b0f896
AM		 5463 i.rm.reg = i.tm.extension_opcode;
5464 }
5465 return default_seg;
5466}
252b5132 5467
29b0f896 5468static void
e3bb37b5 5469output_branch (void)
29b0f896
AM		 5470{
5471 char *p;
5472 int code16;
5473 int prefix;
5474 relax_substateT subtype;
5475 symbolS *sym;
5476 offsetT off;
5477
5478 code16 = 0;
5479 if (flag_code == CODE_16BIT)
5480 code16 = CODE16;
5481
5482 prefix = 0;
5483 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5484 {
29b0f896
AM		 5485 prefix = 1;
5486 i.prefixes -= 1;
5487 code16 ^= CODE16;
252b5132 5488 }
29b0f896
AM		 5489 /* Pentium4 branch hints. */
5490 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5491 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5492 {
29b0f896
AM		 5493 prefix++;
5494 i.prefixes--;
5495 }
5496 if (i.prefix[REX_PREFIX] != 0)
5497 {
5498 prefix++;
5499 i.prefixes--;
2f66722d
AM		 5500 }
5501
29b0f896
AM		 5502 if (i.prefixes != 0 && !intel_syntax)
5503 as_warn (_("skipping prefixes on this instruction"));
5504
5505 /* It's always a symbol; End frag & setup for relax.
5506 Make sure there is enough room in this frag for the largest
5507 instruction we may generate in md_convert_frag. This is 2
5508 bytes for the opcode and room for the prefix and largest
5509 displacement. */
5510 frag_grow (prefix + 2 + 4);
5511 /* Prefix and 1 opcode byte go in fr_fix. */
5512 p = frag_more (prefix + 1);
5513 if (i.prefix[DATA_PREFIX] != 0)
5514 *p++ = DATA_PREFIX_OPCODE;
5515 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5516 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5517 *p++ = i.prefix[SEG_PREFIX];
5518 if (i.prefix[REX_PREFIX] != 0)
5519 *p++ = i.prefix[REX_PREFIX];
5520 *p = i.tm.base_opcode;
5521
5522 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5523 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5524 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5525 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5526 else
5527 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5528 subtype |= code16;
3e73aa7c 5529
29b0f896
AM		 5530 sym = i.op[0].disps->X_add_symbol;
5531 off = i.op[0].disps->X_add_number;
3e73aa7c 5532
29b0f896
AM		 5533 if (i.op[0].disps->X_op != O_constant
5534 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5535 {
29b0f896
AM		 5536 /* Handle complex expressions. */
5537 sym = make_expr_symbol (i.op[0].disps);
5538 off = 0;
5539 }
3e73aa7c 5540
29b0f896
AM		 5541 /* 1 possible extra opcode + 4 byte displacement go in var part.
5542 Pass reloc in fr_var. */
5543 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5544}
3e73aa7c 5545
29b0f896 5546static void
e3bb37b5 5547output_jump (void)
29b0f896
AM		 5548{
5549 char *p;
5550 int size;
3e02c1cc 5551 fixS *fixP;
29b0f896 5552
40fb9820 5553 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5554 {
5555 /* This is a loop or jecxz type instruction. */
5556 size = 1;
5557 if (i.prefix[ADDR_PREFIX] != 0)
5558 {
5559 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5560 i.prefixes -= 1;
5561 }
5562 /* Pentium4 branch hints. */
5563 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5564 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5565 {
5566 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5567 i.prefixes--;
3e73aa7c
JH		 5568 }
5569 }
29b0f896
AM		 5570 else
5571 {
5572 int code16;
3e73aa7c 5573
29b0f896
AM		 5574 code16 = 0;
5575 if (flag_code == CODE_16BIT)
5576 code16 = CODE16;
3e73aa7c 5577
29b0f896
AM		 5578 if (i.prefix[DATA_PREFIX] != 0)
5579 {
5580 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5581 i.prefixes -= 1;
5582 code16 ^= CODE16;
5583 }
252b5132 5584
29b0f896
AM		 5585 size = 4;
5586 if (code16)
5587 size = 2;
5588 }
9fcc94b6 5589
29b0f896
AM		 5590 if (i.prefix[REX_PREFIX] != 0)
5591 {
5592 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5593 i.prefixes -= 1;
5594 }
252b5132 5595
29b0f896
AM		 5596 if (i.prefixes != 0 && !intel_syntax)
5597 as_warn (_("skipping prefixes on this instruction"));
e0890092 5598
29b0f896
AM		 5599 p = frag_more (1 + size);
5600 *p++ = i.tm.base_opcode;
e0890092 5601
3e02c1cc
AM		 5602 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5603 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5604
5605 /* All jumps handled here are signed, but don't use a signed limit
5606 check for 32 and 16 bit jumps as we want to allow wrap around at
5607 4G and 64k respectively. */
5608 if (size == 1)
5609 fixP->fx_signed = 1;
29b0f896 5610}
e0890092 5611
29b0f896 5612static void
e3bb37b5 5613output_interseg_jump (void)
29b0f896
AM		 5614{
5615 char *p;
5616 int size;
5617 int prefix;
5618 int code16;
252b5132 5619
29b0f896
AM		 5620 code16 = 0;
5621 if (flag_code == CODE_16BIT)
5622 code16 = CODE16;
a217f122 5623
29b0f896
AM		 5624 prefix = 0;
5625 if (i.prefix[DATA_PREFIX] != 0)
5626 {
5627 prefix = 1;
5628 i.prefixes -= 1;
5629 code16 ^= CODE16;
5630 }
5631 if (i.prefix[REX_PREFIX] != 0)
5632 {
5633 prefix++;
5634 i.prefixes -= 1;
5635 }
252b5132 5636
29b0f896
AM		 5637 size = 4;
5638 if (code16)
5639 size = 2;
252b5132 5640
29b0f896
AM		 5641 if (i.prefixes != 0 && !intel_syntax)
5642 as_warn (_("skipping prefixes on this instruction"));
252b5132 5643
29b0f896
AM		 5644 /* 1 opcode; 2 segment; offset */
5645 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5646
29b0f896
AM		 5647 if (i.prefix[DATA_PREFIX] != 0)
5648 *p++ = DATA_PREFIX_OPCODE;
252b5132 5649
29b0f896
AM		 5650 if (i.prefix[REX_PREFIX] != 0)
5651 *p++ = i.prefix[REX_PREFIX];
252b5132 5652
29b0f896
AM		 5653 *p++ = i.tm.base_opcode;
5654 if (i.op[1].imms->X_op == O_constant)
5655 {
5656 offsetT n = i.op[1].imms->X_add_number;
252b5132 5657
29b0f896
AM		 5658 if (size == 2
5659 && !fits_in_unsigned_word (n)
5660 && !fits_in_signed_word (n))
5661 {
5662 as_bad (_("16-bit jump out of range"));
5663 return;
5664 }
5665 md_number_to_chars (p, n, size);
5666 }
5667 else
5668 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5669 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5670 if (i.op[0].imms->X_op != O_constant)
5671 as_bad (_("can't handle non absolute segment in `%s'"),
5672 i.tm.name);
5673 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5674}
a217f122 5675
29b0f896 5676static void
e3bb37b5 5677output_insn (void)
29b0f896 5678{
2bbd9c25
JJ		 5679 fragS *insn_start_frag;
5680 offsetT insn_start_off;
5681
29b0f896
AM		 5682 /* Tie dwarf2 debug info to the address at the start of the insn.
5683 We can't do this after the insn has been output as the current
5684 frag may have been closed off. eg. by frag_var. */
5685 dwarf2_emit_insn (0);
5686
2bbd9c25
JJ		 5687 insn_start_frag = frag_now;
5688 insn_start_off = frag_now_fix ();
5689
29b0f896 5690 /* Output jumps. */
40fb9820 5691 if (i.tm.opcode_modifier.jump)
29b0f896 5692 output_branch ();
40fb9820
L		 5693 else if (i.tm.opcode_modifier.jumpbyte
5694 || i.tm.opcode_modifier.jumpdword)
29b0f896 5695 output_jump ();
40fb9820 5696 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5697 output_interseg_jump ();
5698 else
5699 {
5700 /* Output normal instructions here. */
5701 char *p;
5702 unsigned char *q;
47465058 5703 unsigned int j;
331d2d0d 5704 unsigned int prefix;
4dffcebc 5705
c0f3af97
L		 5706 /* Since the VEX prefix contains the implicit prefix, we don't
5707 need the explicit prefix. */
5708 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5709 {
c0f3af97 5710 switch (i.tm.opcode_length)
bc4bd9ab 5711 {
c0f3af97
L		 5712 case 3:
5713 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5714 {
c0f3af97
L		 5715 prefix = (i.tm.base_opcode >> 24) & 0xff;
5716 goto check_prefix;
5717 }
5718 break;
5719 case 2:
5720 if ((i.tm.base_opcode & 0xff0000) != 0)
5721 {
5722 prefix = (i.tm.base_opcode >> 16) & 0xff;
5723 if (i.tm.cpu_flags.bitfield.cpupadlock)
5724 {
4dffcebc 5725check_prefix:
c0f3af97 5726 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5727 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5728 != REPE_PREFIX_OPCODE))
5729 add_prefix (prefix);
5730 }
5731 else
4dffcebc
L		 5732 add_prefix (prefix);
5733 }
c0f3af97
L		 5734 break;
5735 case 1:
5736 break;
5737 default:
5738 abort ();
bc4bd9ab 5739 }
c0f3af97
L		 5740
5741 /* The prefix bytes. */
5742 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5743 if (*q)
5744 FRAG_APPEND_1_CHAR (*q);
0f10071e 5745 }
252b5132 5746
c0f3af97
L		 5747 if (i.tm.opcode_modifier.vex)
5748 {
5749 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5750 if (*q)
5751 switch (j)
5752 {
5753 case REX_PREFIX:
5754 /* REX byte is encoded in VEX prefix. */
5755 break;
5756 case SEG_PREFIX:
5757 case ADDR_PREFIX:
5758 FRAG_APPEND_1_CHAR (*q);
5759 break;
5760 default:
5761 /* There should be no other prefixes for instructions
5762 with VEX prefix. */
5763 abort ();
5764 }
5765
5766 /* Now the VEX prefix. */
5767 p = frag_more (i.vex.length);
5768 for (j = 0; j < i.vex.length; j++)
5769 p[j] = i.vex.bytes[j];
5770 }
252b5132 5771
29b0f896 5772 /* Now the opcode; be careful about word order here! */
4dffcebc 5773 if (i.tm.opcode_length == 1)
29b0f896
AM		 5774 {
5775 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5776 }
5777 else
5778 {
4dffcebc 5779 switch (i.tm.opcode_length)
331d2d0d 5780 {
4dffcebc 5781 case 3:
331d2d0d
L		 5782 p = frag_more (3);
5783 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5784 break;
5785 case 2:
5786 p = frag_more (2);
5787 break;
5788 default:
5789 abort ();
5790 break;
331d2d0d 5791 }
0f10071e 5792
29b0f896
AM		 5793 /* Put out high byte first: can't use md_number_to_chars! */
5794 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5795 *p = i.tm.base_opcode & 0xff;
5796 }
3e73aa7c 5797
29b0f896 5798 /* Now the modrm byte and sib byte (if present). */
40fb9820 5799 if (i.tm.opcode_modifier.modrm)
29b0f896 5800 {
4a3523fa
L		 5801 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5802 | i.rm.reg << 3
5803 | i.rm.mode << 6));
29b0f896
AM		 5804 /* If i.rm.regmem == ESP (4)
5805 && i.rm.mode != (Register mode)
5806 && not 16 bit
5807 ==> need second modrm byte. */
5808 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5809 && i.rm.mode != 3
40fb9820 5810 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5811 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5812 | i.sib.index << 3
5813 | i.sib.scale << 6));
29b0f896 5814 }
3e73aa7c 5815
29b0f896 5816 if (i.disp_operands)
2bbd9c25 5817 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5818
29b0f896 5819 if (i.imm_operands)
2bbd9c25 5820 output_imm (insn_start_frag, insn_start_off);
29b0f896 5821 }
252b5132 5822
29b0f896
AM		 5823#ifdef DEBUG386
5824 if (flag_debug)
5825 {
7b81dfbb 5826 pi ("" /*line*/, &i);
29b0f896
AM		 5827 }
5828#endif /* DEBUG386 */
5829}
252b5132 5830
e205caa7
L		 5831/* Return the size of the displacement operand N. */
5832
5833static int
5834disp_size (unsigned int n)
5835{
5836 int size = 4;
40fb9820
L		 5837 if (i.types[n].bitfield.disp64)
5838 size = 8;
5839 else if (i.types[n].bitfield.disp8)
5840 size = 1;
5841 else if (i.types[n].bitfield.disp16)
5842 size = 2;
e205caa7
L		 5843 return size;
5844}
5845
5846/* Return the size of the immediate operand N. */
5847
5848static int
5849imm_size (unsigned int n)
5850{
5851 int size = 4;
40fb9820
L		 5852 if (i.types[n].bitfield.imm64)
5853 size = 8;
5854 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5855 size = 1;
5856 else if (i.types[n].bitfield.imm16)
5857 size = 2;
e205caa7
L		 5858 return size;
5859}
5860
29b0f896 5861static void
64e74474 5862output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5863{
5864 char *p;
5865 unsigned int n;
252b5132 5866
29b0f896
AM		 5867 for (n = 0; n < i.operands; n++)
5868 {
40fb9820 5869 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5870 {
5871 if (i.op[n].disps->X_op == O_constant)
5872 {
e205caa7 5873 int size = disp_size (n);
29b0f896 5874 offsetT val;
252b5132 5875
29b0f896
AM		 5876 val = offset_in_range (i.op[n].disps->X_add_number,
5877 size);
5878 p = frag_more (size);
5879 md_number_to_chars (p, val, size);
5880 }
5881 else
5882 {
f86103b7 5883 enum bfd_reloc_code_real reloc_type;
e205caa7 5884 int size = disp_size (n);
40fb9820 5885 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5886 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5887
e205caa7 5888 /* We can't have 8 bit displacement here. */
9c2799c2 5889 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5890
29b0f896
AM		 5891 /* The PC relative address is computed relative
5892 to the instruction boundary, so in case immediate
5893 fields follows, we need to adjust the value. */
5894 if (pcrel && i.imm_operands)
5895 {
29b0f896 5896 unsigned int n1;
e205caa7 5897 int sz = 0;
252b5132 5898
29b0f896 5899 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5900 if (operand_type_check (i.types[n1], imm))
252b5132 5901 {
e205caa7
L		 5902 /* Only one immediate is allowed for PC
5903 relative address. */
9c2799c2 5904 gas_assert (sz == 0);
e205caa7
L		 5905 sz = imm_size (n1);
5906 i.op[n].disps->X_add_number -= sz;
252b5132 5907 }
29b0f896 5908 /* We should find the immediate. */
9c2799c2 5909 gas_assert (sz != 0);
29b0f896 5910 }
520dc8e8 5911
29b0f896 5912 p = frag_more (size);
2bbd9c25 5913 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5914 if (GOT_symbol
2bbd9c25 5915 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5916 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5917 || reloc_type == BFD_RELOC_X86_64_32S
5918 || (reloc_type == BFD_RELOC_64
5919 && object_64bit))
d6ab8113
JB		 5920 && (i.op[n].disps->X_op == O_symbol
5921 || (i.op[n].disps->X_op == O_add
5922 && ((symbol_get_value_expression
5923 (i.op[n].disps->X_op_symbol)->X_op)
5924 == O_subtract))))
5925 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5926 {
5927 offsetT add;
5928
5929 if (insn_start_frag == frag_now)
5930 add = (p - frag_now->fr_literal) - insn_start_off;
5931 else
5932 {
5933 fragS *fr;
5934
5935 add = insn_start_frag->fr_fix - insn_start_off;
5936 for (fr = insn_start_frag->fr_next;
5937 fr && fr != frag_now; fr = fr->fr_next)
5938 add += fr->fr_fix;
5939 add += p - frag_now->fr_literal;
5940 }
5941
4fa24527 5942 if (!object_64bit)
7b81dfbb
AJ		 5943 {
5944 reloc_type = BFD_RELOC_386_GOTPC;
5945 i.op[n].imms->X_add_number += add;
5946 }
5947 else if (reloc_type == BFD_RELOC_64)
5948 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5949 else
7b81dfbb
AJ		 5950 /* Don't do the adjustment for x86-64, as there
5951 the pcrel addressing is relative to the _next_
5952 insn, and that is taken care of in other code. */
d6ab8113 5953 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5954 }
062cd5e7 5955 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5956 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5957 }
5958 }
5959 }
5960}
252b5132 5961
29b0f896 5962static void
64e74474 5963output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5964{
5965 char *p;
5966 unsigned int n;
252b5132 5967
29b0f896
AM		 5968 for (n = 0; n < i.operands; n++)
5969 {
40fb9820 5970 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5971 {
5972 if (i.op[n].imms->X_op == O_constant)
5973 {
e205caa7 5974 int size = imm_size (n);
29b0f896 5975 offsetT val;
b4cac588 5976
29b0f896
AM		 5977 val = offset_in_range (i.op[n].imms->X_add_number,
5978 size);
5979 p = frag_more (size);
5980 md_number_to_chars (p, val, size);
5981 }
5982 else
5983 {
5984 /* Not absolute_section.
5985 Need a 32-bit fixup (don't support 8bit
5986 non-absolute imms). Try to support other
5987 sizes ... */
f86103b7 5988 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5989 int size = imm_size (n);
5990 int sign;
29b0f896 5991
40fb9820 5992 if (i.types[n].bitfield.imm32s
a7d61044 5993 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5994 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5995 sign = 1;
e205caa7
L		 5996 else
5997 sign = 0;
520dc8e8 5998
29b0f896
AM		 5999 p = frag_more (size);
6000 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6001
2bbd9c25
JJ		 6002 /* This is tough to explain. We end up with this one if we
6003 * have operands that look like
6004 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6005 * obtain the absolute address of the GOT, and it is strongly
6006 * preferable from a performance point of view to avoid using
6007 * a runtime relocation for this. The actual sequence of
6008 * instructions often look something like:
6009 *
6010 * call .L66
6011 * .L66:
6012 * popl %ebx
6013 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6014 *
6015 * The call and pop essentially return the absolute address
6016 * of the label .L66 and store it in %ebx. The linker itself
6017 * will ultimately change the first operand of the addl so
6018 * that %ebx points to the GOT, but to keep things simple, the
6019 * .o file must have this operand set so that it generates not
6020 * the absolute address of .L66, but the absolute address of
6021 * itself. This allows the linker itself simply treat a GOTPC
6022 * relocation as asking for a pcrel offset to the GOT to be
6023 * added in, and the addend of the relocation is stored in the
6024 * operand field for the instruction itself.
6025 *
6026 * Our job here is to fix the operand so that it would add
6027 * the correct offset so that %ebx would point to itself. The
6028 * thing that is tricky is that .-.L66 will point to the
6029 * beginning of the instruction, so we need to further modify
6030 * the operand so that it will point to itself. There are
6031 * other cases where you have something like:
6032 *
6033 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6034 *
6035 * and here no correction would be required. Internally in
6036 * the assembler we treat operands of this form as not being
6037 * pcrel since the '.' is explicitly mentioned, and I wonder
6038 * whether it would simplify matters to do it this way. Who
6039 * knows. In earlier versions of the PIC patches, the
6040 * pcrel_adjust field was used to store the correction, but
6041 * since the expression is not pcrel, I felt it would be
6042 * confusing to do it this way. */
6043
d6ab8113 6044 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6045 || reloc_type == BFD_RELOC_X86_64_32S
6046 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6047 && GOT_symbol
6048 && GOT_symbol == i.op[n].imms->X_add_symbol
6049 && (i.op[n].imms->X_op == O_symbol
6050 || (i.op[n].imms->X_op == O_add
6051 && ((symbol_get_value_expression
6052 (i.op[n].imms->X_op_symbol)->X_op)
6053 == O_subtract))))
6054 {
2bbd9c25
JJ		 6055 offsetT add;
6056
6057 if (insn_start_frag == frag_now)
6058 add = (p - frag_now->fr_literal) - insn_start_off;
6059 else
6060 {
6061 fragS *fr;
6062
6063 add = insn_start_frag->fr_fix - insn_start_off;
6064 for (fr = insn_start_frag->fr_next;
6065 fr && fr != frag_now; fr = fr->fr_next)
6066 add += fr->fr_fix;
6067 add += p - frag_now->fr_literal;
6068 }
6069
4fa24527 6070 if (!object_64bit)
d6ab8113 6071 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6072 else if (size == 4)
d6ab8113 6073 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6074 else if (size == 8)
6075 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6076 i.op[n].imms->X_add_number += add;
29b0f896 6077 }
29b0f896
AM		 6078 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6079 i.op[n].imms, 0, reloc_type);
6080 }
6081 }
6082 }
252b5132
RH		 6083}
6084\f
d182319b
JB		 6085/* x86_cons_fix_new is called via the expression parsing code when a
6086 reloc is needed. We use this hook to get the correct .got reloc. */
6087static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6088static int cons_sign = -1;
6089
6090void
e3bb37b5 6091x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6092 expressionS *exp)
d182319b
JB		 6093{
6094 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6095
6096 got_reloc = NO_RELOC;
6097
6098#ifdef TE_PE
6099 if (exp->X_op == O_secrel)
6100 {
6101 exp->X_op = O_symbol;
6102 r = BFD_RELOC_32_SECREL;
6103 }
6104#endif
6105
6106 fix_new_exp (frag, off, len, exp, 0, r);
6107}
6108
718ddfc0
JB		 6109#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6110# define lex_got(reloc, adjust, types) NULL
6111#else
f3c180ae
AM		 6112/* Parse operands of the form
6113 <symbol>@GOTOFF+<nnn>
6114 and similar .plt or .got references.
6115
6116 If we find one, set up the correct relocation in RELOC and copy the
6117 input string, minus the `@GOTOFF' into a malloc'd buffer for
6118 parsing by the calling routine. Return this buffer, and if ADJUST
6119 is non-null set it to the length of the string we removed from the
6120 input line. Otherwise return NULL. */
6121static char *
91d6fa6a 6122lex_got (enum bfd_reloc_code_real *rel,
64e74474 6123 int *adjust,
40fb9820 6124 i386_operand_type *types)
f3c180ae 6125{
7b81dfbb
AJ		 6126 /* Some of the relocations depend on the size of what field is to
6127 be relocated. But in our callers i386_immediate and i386_displacement
6128 we don't yet know the operand size (this will be set by insn
6129 matching). Hence we record the word32 relocation here,
6130 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6131 static const struct {
6132 const char *str;
4fa24527 6133 const enum bfd_reloc_code_real rel[2];
40fb9820 6134 const i386_operand_type types64;
f3c180ae 6135 } gotrel[] = {
1e9cc1c2 6136 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6137 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6138 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6139 { "PLT", { BFD_RELOC_386_PLT32,
6140 BFD_RELOC_X86_64_PLT32 },
40fb9820 6141 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6142 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6143 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6144 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6145 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6146 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6147 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6148 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6149 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6150 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6151 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6152 BFD_RELOC_X86_64_TLSGD },
40fb9820 6153 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6154 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6155 _dummy_first_bfd_reloc_code_real },
40fb9820 6156 OPERAND_TYPE_NONE },
1e9cc1c2 6157 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6158 BFD_RELOC_X86_64_TLSLD },
40fb9820 6159 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6160 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6161 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6162 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6163 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6164 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6165 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6166 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6167 _dummy_first_bfd_reloc_code_real },
40fb9820 6168 OPERAND_TYPE_NONE },
4eed87de
AM		 6169 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6170 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6171
40fb9820 6172 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6173 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6174 _dummy_first_bfd_reloc_code_real },
40fb9820 6175 OPERAND_TYPE_NONE },
4eed87de 6176 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6177 _dummy_first_bfd_reloc_code_real },
40fb9820 6178 OPERAND_TYPE_NONE },
4eed87de
AM		 6179 { "GOT", { BFD_RELOC_386_GOT32,
6180 BFD_RELOC_X86_64_GOT32 },
40fb9820 6181 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6182 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6183 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6184 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6185 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6186 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6187 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6188 };
6189 char *cp;
6190 unsigned int j;
6191
718ddfc0
JB		 6192 if (!IS_ELF)
6193 return NULL;
6194
f3c180ae 6195 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6196 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6197 return NULL;
6198
47465058 6199 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6200 {
6201 int len;
6202
6203 len = strlen (gotrel[j].str);
28f81592 6204 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6205 {
4fa24527 6206 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6207 {
28f81592
AM		 6208 int first, second;
6209 char *tmpbuf, *past_reloc;
f3c180ae 6210
91d6fa6a 6211 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6212 if (adjust)
6213 *adjust = len;
f3c180ae 6214
3956db08
JB		 6215 if (types)
6216 {
6217 if (flag_code != CODE_64BIT)
40fb9820
L		 6218 {
6219 types->bitfield.imm32 = 1;
6220 types->bitfield.disp32 = 1;
6221 }
3956db08
JB		 6222 else
6223 *types = gotrel[j].types64;
6224 }
6225
f3c180ae
AM		 6226 if (GOT_symbol == NULL)
6227 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6228
28f81592 6229 /* The length of the first part of our input line. */
f3c180ae 6230 first = cp - input_line_pointer;
28f81592
AM		 6231
6232 /* The second part goes from after the reloc token until
67c11a9b 6233 (and including) an end_of_line char or comma. */
28f81592 6234 past_reloc = cp + 1 + len;
67c11a9b
AM		 6235 cp = past_reloc;
6236 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6237 ++cp;
6238 second = cp + 1 - past_reloc;
28f81592
AM		 6239
6240 /* Allocate and copy string. The trailing NUL shouldn't
6241 be necessary, but be safe. */
1e9cc1c2 6242 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6243 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6244 if (second != 0 && *past_reloc != ' ')
6245 /* Replace the relocation token with ' ', so that
6246 errors like foo@GOTOFF1 will be detected. */
6247 tmpbuf[first++] = ' ';
6248 memcpy (tmpbuf + first, past_reloc, second);
6249 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6250 return tmpbuf;
6251 }
6252
4fa24527
JB		 6253 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6254 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6255 return NULL;
6256 }
6257 }
6258
6259 /* Might be a symbol version string. Don't as_bad here. */
6260 return NULL;
6261}
6262
f3c180ae 6263void
e3bb37b5 6264x86_cons (expressionS *exp, int size)
f3c180ae 6265{
ee86248c
JB		 6266 intel_syntax = -intel_syntax;
6267
4fa24527 6268 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6269 {
6270 /* Handle @GOTOFF and the like in an expression. */
6271 char *save;
6272 char *gotfree_input_line;
6273 int adjust;
6274
6275 save = input_line_pointer;
3956db08 6276 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6277 if (gotfree_input_line)
6278 input_line_pointer = gotfree_input_line;
6279
6280 expression (exp);
6281
6282 if (gotfree_input_line)
6283 {
6284 /* expression () has merrily parsed up to the end of line,
6285 or a comma - in the wrong buffer. Transfer how far
6286 input_line_pointer has moved to the right buffer. */
6287 input_line_pointer = (save
6288 + (input_line_pointer - gotfree_input_line)
6289 + adjust);
6290 free (gotfree_input_line);
3992d3b7
AM		 6291 if (exp->X_op == O_constant
6292 || exp->X_op == O_absent
6293 || exp->X_op == O_illegal
6294 || exp->X_op == O_register
6295 || exp->X_op == O_big)
6296 {
6297 char c = *input_line_pointer;
6298 *input_line_pointer = 0;
6299 as_bad (_("missing or invalid expression `%s'"), save);
6300 *input_line_pointer = c;
6301 }
f3c180ae
AM		 6302 }
6303 }
6304 else
6305 expression (exp);
ee86248c
JB		 6306
6307 intel_syntax = -intel_syntax;
6308
6309 if (intel_syntax)
6310 i386_intel_simplify (exp);
f3c180ae
AM		 6311}
6312#endif
6313
9f32dd5b
L		 6314static void
6315signed_cons (int size)
6482c264 6316{
d182319b
JB		 6317 if (flag_code == CODE_64BIT)
6318 cons_sign = 1;
6319 cons (size);
6320 cons_sign = -1;
6482c264
NC		 6321}
6322
d182319b 6323#ifdef TE_PE
6482c264
NC		 6324static void
6325pe_directive_secrel (dummy)
6326 int dummy ATTRIBUTE_UNUSED;
6327{
6328 expressionS exp;
6329
6330 do
6331 {
6332 expression (&exp);
6333 if (exp.X_op == O_symbol)
6334 exp.X_op = O_secrel;
6335
6336 emit_expr (&exp, 4);
6337 }
6338 while (*input_line_pointer++ == ',');
6339
6340 input_line_pointer--;
6341 demand_empty_rest_of_line ();
6342}
6482c264
NC		 6343#endif
6344
252b5132 6345static int
70e41ade 6346i386_immediate (char *imm_start)
252b5132
RH		 6347{
6348 char *save_input_line_pointer;
f3c180ae 6349 char *gotfree_input_line;
252b5132 6350 segT exp_seg = 0;
47926f60 6351 expressionS *exp;
40fb9820
L		 6352 i386_operand_type types;
6353
0dfbf9d7 6354 operand_type_set (&types, ~0);
252b5132
RH		 6355
6356 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6357 {
31b2323c
L		 6358 as_bad (_("at most %d immediate operands are allowed"),
6359 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6360 return 0;
6361 }
6362
6363 exp = &im_expressions[i.imm_operands++];
520dc8e8 6364 i.op[this_operand].imms = exp;
252b5132
RH		 6365
6366 if (is_space_char (*imm_start))
6367 ++imm_start;
6368
6369 save_input_line_pointer = input_line_pointer;
6370 input_line_pointer = imm_start;
6371
3956db08 6372 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6373 if (gotfree_input_line)
6374 input_line_pointer = gotfree_input_line;
252b5132
RH		 6375
6376 exp_seg = expression (exp);
6377
83183c0c 6378 SKIP_WHITESPACE ();
252b5132 6379 if (*input_line_pointer)
f3c180ae 6380 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6381
6382 input_line_pointer = save_input_line_pointer;
f3c180ae 6383 if (gotfree_input_line)
ee86248c
JB		 6384 {
6385 free (gotfree_input_line);
6386
6387 if (exp->X_op == O_constant || exp->X_op == O_register)
6388 exp->X_op = O_illegal;
6389 }
6390
6391 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6392}
252b5132 6393
ee86248c
JB		 6394static int
6395i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6396 i386_operand_type types, const char *imm_start)
6397{
6398 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6399 {
313c53d1
L		 6400 if (imm_start)
6401 as_bad (_("missing or invalid immediate expression `%s'"),
6402 imm_start);
3992d3b7 6403 return 0;
252b5132 6404 }
3e73aa7c 6405 else if (exp->X_op == O_constant)
252b5132 6406 {
47926f60 6407 /* Size it properly later. */
40fb9820 6408 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6409 /* If BFD64, sign extend val. */
4eed87de
AM		 6410 if (!use_rela_relocations
6411 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6412 exp->X_add_number
6413 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6414 }
4c63da97 6415#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6416 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6417 && exp_seg != absolute_section
47926f60 6418 && exp_seg != text_section
24eab124
AM		 6419 && exp_seg != data_section
6420 && exp_seg != bss_section
6421 && exp_seg != undefined_section
f86103b7 6422 && !bfd_is_com_section (exp_seg))
252b5132 6423 {
d0b47220 6424 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6425 return 0;
6426 }
6427#endif
bb8f5920
L		 6428 else if (!intel_syntax && exp->X_op == O_register)
6429 {
313c53d1
L		 6430 if (imm_start)
6431 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6432 return 0;
6433 }
252b5132
RH		 6434 else
6435 {
6436 /* This is an address. The size of the address will be
24eab124 6437 determined later, depending on destination register,
3e73aa7c 6438 suffix, or the default for the section. */
40fb9820
L		 6439 i.types[this_operand].bitfield.imm8 = 1;
6440 i.types[this_operand].bitfield.imm16 = 1;
6441 i.types[this_operand].bitfield.imm32 = 1;
6442 i.types[this_operand].bitfield.imm32s = 1;
6443 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6444 i.types[this_operand] = operand_type_and (i.types[this_operand],
6445 types);
252b5132
RH		 6446 }
6447
6448 return 1;
6449}
6450
551c1ca1 6451static char *
e3bb37b5 6452i386_scale (char *scale)
252b5132 6453{
551c1ca1
AM		 6454 offsetT val;
6455 char *save = input_line_pointer;
252b5132 6456
551c1ca1
AM		 6457 input_line_pointer = scale;
6458 val = get_absolute_expression ();
6459
6460 switch (val)
252b5132 6461 {
551c1ca1 6462 case 1:
252b5132
RH		 6463 i.log2_scale_factor = 0;
6464 break;
551c1ca1 6465 case 2:
252b5132
RH		 6466 i.log2_scale_factor = 1;
6467 break;
551c1ca1 6468 case 4:
252b5132
RH		 6469 i.log2_scale_factor = 2;
6470 break;
551c1ca1 6471 case 8:
252b5132
RH		 6472 i.log2_scale_factor = 3;
6473 break;
6474 default:
a724f0f4
JB		 6475 {
6476 char sep = *input_line_pointer;
6477
6478 *input_line_pointer = '\0';
6479 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6480 scale);
6481 *input_line_pointer = sep;
6482 input_line_pointer = save;
6483 return NULL;
6484 }
252b5132 6485 }
29b0f896 6486 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6487 {
6488 as_warn (_("scale factor of %d without an index register"),
24eab124 6489 1 << i.log2_scale_factor);
252b5132 6490 i.log2_scale_factor = 0;
252b5132 6491 }
551c1ca1
AM		 6492 scale = input_line_pointer;
6493 input_line_pointer = save;
6494 return scale;
252b5132
RH		 6495}
6496
252b5132 6497static int
e3bb37b5 6498i386_displacement (char *disp_start, char *disp_end)
252b5132 6499{
29b0f896 6500 expressionS *exp;
252b5132
RH		 6501 segT exp_seg = 0;
6502 char *save_input_line_pointer;
f3c180ae 6503 char *gotfree_input_line;
40fb9820
L		 6504 int override;
6505 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6506 int ret;
252b5132 6507
31b2323c
L		 6508 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6509 {
6510 as_bad (_("at most %d displacement operands are allowed"),
6511 MAX_MEMORY_OPERANDS);
6512 return 0;
6513 }
6514
0dfbf9d7 6515 operand_type_set (&bigdisp, 0);
40fb9820
L		 6516 if ((i.types[this_operand].bitfield.jumpabsolute)
6517 || (!current_templates->start->opcode_modifier.jump
6518 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6519 {
40fb9820 6520 bigdisp.bitfield.disp32 = 1;
e05278af 6521 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6522 if (flag_code == CODE_64BIT)
6523 {
6524 if (!override)
6525 {
6526 bigdisp.bitfield.disp32s = 1;
6527 bigdisp.bitfield.disp64 = 1;
6528 }
6529 }
6530 else if ((flag_code == CODE_16BIT) ^ override)
6531 {
6532 bigdisp.bitfield.disp32 = 0;
6533 bigdisp.bitfield.disp16 = 1;
6534 }
e05278af
JB		 6535 }
6536 else
6537 {
6538 /* For PC-relative branches, the width of the displacement
6539 is dependent upon data size, not address size. */
e05278af 6540 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6541 if (flag_code == CODE_64BIT)
6542 {
6543 if (override || i.suffix == WORD_MNEM_SUFFIX)
6544 bigdisp.bitfield.disp16 = 1;
6545 else
6546 {
6547 bigdisp.bitfield.disp32 = 1;
6548 bigdisp.bitfield.disp32s = 1;
6549 }
6550 }
6551 else
e05278af
JB		 6552 {
6553 if (!override)
6554 override = (i.suffix == (flag_code != CODE_16BIT
6555 ? WORD_MNEM_SUFFIX
6556 : LONG_MNEM_SUFFIX));
40fb9820
L		 6557 bigdisp.bitfield.disp32 = 1;
6558 if ((flag_code == CODE_16BIT) ^ override)
6559 {
6560 bigdisp.bitfield.disp32 = 0;
6561 bigdisp.bitfield.disp16 = 1;
6562 }
e05278af 6563 }
e05278af 6564 }
c6fb90c8
L		 6565 i.types[this_operand] = operand_type_or (i.types[this_operand],
6566 bigdisp);
252b5132
RH		 6567
6568 exp = &disp_expressions[i.disp_operands];
520dc8e8 6569 i.op[this_operand].disps = exp;
252b5132
RH		 6570 i.disp_operands++;
6571 save_input_line_pointer = input_line_pointer;
6572 input_line_pointer = disp_start;
6573 END_STRING_AND_SAVE (disp_end);
6574
6575#ifndef GCC_ASM_O_HACK
6576#define GCC_ASM_O_HACK 0
6577#endif
6578#if GCC_ASM_O_HACK
6579 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6580 if (i.types[this_operand].bitfield.baseIndex
24eab124 6581 && displacement_string_end[-1] == '+')
252b5132
RH		 6582 {
6583 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6584 constraint within gcc asm statements.
6585 For instance:
6586
6587 #define _set_tssldt_desc(n,addr,limit,type) \
6588 __asm__ __volatile__ ( \
6589 "movw %w2,%0\n\t" \
6590 "movw %w1,2+%0\n\t" \
6591 "rorl $16,%1\n\t" \
6592 "movb %b1,4+%0\n\t" \
6593 "movb %4,5+%0\n\t" \
6594 "movb $0,6+%0\n\t" \
6595 "movb %h1,7+%0\n\t" \
6596 "rorl $16,%1" \
6597 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6598
6599 This works great except that the output assembler ends
6600 up looking a bit weird if it turns out that there is
6601 no offset. You end up producing code that looks like:
6602
6603 #APP
6604 movw $235,(%eax)
6605 movw %dx,2+(%eax)
6606 rorl $16,%edx
6607 movb %dl,4+(%eax)
6608 movb $137,5+(%eax)
6609 movb $0,6+(%eax)
6610 movb %dh,7+(%eax)
6611 rorl $16,%edx
6612 #NO_APP
6613
47926f60 6614 So here we provide the missing zero. */
24eab124
AM		 6615
6616 *displacement_string_end = '0';
252b5132
RH		 6617 }
6618#endif
3956db08 6619 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6620 if (gotfree_input_line)
6621 input_line_pointer = gotfree_input_line;
252b5132 6622
24eab124 6623 exp_seg = expression (exp);
252b5132 6624
636c26b0
AM		 6625 SKIP_WHITESPACE ();
6626 if (*input_line_pointer)
6627 as_bad (_("junk `%s' after expression"), input_line_pointer);
6628#if GCC_ASM_O_HACK
6629 RESTORE_END_STRING (disp_end + 1);
6630#endif
636c26b0 6631 input_line_pointer = save_input_line_pointer;
636c26b0 6632 if (gotfree_input_line)
ee86248c
JB		 6633 {
6634 free (gotfree_input_line);
6635
6636 if (exp->X_op == O_constant || exp->X_op == O_register)
6637 exp->X_op = O_illegal;
6638 }
6639
6640 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6641
6642 RESTORE_END_STRING (disp_end);
6643
6644 return ret;
6645}
6646
6647static int
6648i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6649 i386_operand_type types, const char *disp_start)
6650{
6651 i386_operand_type bigdisp;
6652 int ret = 1;
636c26b0 6653
24eab124
AM		 6654 /* We do this to make sure that the section symbol is in
6655 the symbol table. We will ultimately change the relocation
47926f60 6656 to be relative to the beginning of the section. */
1ae12ab7 6657 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6658 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6659 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6660 {
636c26b0 6661 if (exp->X_op != O_symbol)
3992d3b7 6662 goto inv_disp;
636c26b0 6663
e5cb08ac 6664 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6665 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6666 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6667 exp->X_op = O_subtract;
6668 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6669 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6670 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6671 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6672 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6673 else
29b0f896 6674 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6675 }
252b5132 6676
3992d3b7
AM		 6677 else if (exp->X_op == O_absent
6678 || exp->X_op == O_illegal
ee86248c 6679 || exp->X_op == O_big)
2daf4fd8 6680 {
3992d3b7
AM		 6681 inv_disp:
6682 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6683 disp_start);
3992d3b7 6684 ret = 0;
2daf4fd8
AM		 6685 }
6686
0e1147d9
L		 6687 else if (flag_code == CODE_64BIT
6688 && !i.prefix[ADDR_PREFIX]
6689 && exp->X_op == O_constant)
6690 {
6691 /* Since displacement is signed extended to 64bit, don't allow
6692 disp32 and turn off disp32s if they are out of range. */
6693 i.types[this_operand].bitfield.disp32 = 0;
6694 if (!fits_in_signed_long (exp->X_add_number))
6695 {
6696 i.types[this_operand].bitfield.disp32s = 0;
6697 if (i.types[this_operand].bitfield.baseindex)
6698 {
6699 as_bad (_("0x%lx out range of signed 32bit displacement"),
6700 (long) exp->X_add_number);
6701 ret = 0;
6702 }
6703 }
6704 }
6705
4c63da97 6706#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6707 else if (exp->X_op != O_constant
6708 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6709 && exp_seg != absolute_section
6710 && exp_seg != text_section
6711 && exp_seg != data_section
6712 && exp_seg != bss_section
6713 && exp_seg != undefined_section
6714 && !bfd_is_com_section (exp_seg))
24eab124 6715 {
d0b47220 6716 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6717 ret = 0;
24eab124 6718 }
252b5132 6719#endif
3956db08 6720
40fb9820
L		 6721 /* Check if this is a displacement only operand. */
6722 bigdisp = i.types[this_operand];
6723 bigdisp.bitfield.disp8 = 0;
6724 bigdisp.bitfield.disp16 = 0;
6725 bigdisp.bitfield.disp32 = 0;
6726 bigdisp.bitfield.disp32s = 0;
6727 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6728 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6729 i.types[this_operand] = operand_type_and (i.types[this_operand],
6730 types);
3956db08 6731
3992d3b7 6732 return ret;
252b5132
RH		 6733}
6734
eecb386c 6735/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6736 Return 1 on success, 0 on a failure. */
6737
252b5132 6738static int
e3bb37b5 6739i386_index_check (const char *operand_string)
252b5132 6740{
3e73aa7c 6741 int ok;
fc0763e6 6742 const char *kind = "base/index";
24eab124 6743#if INFER_ADDR_PREFIX
eecb386c
AM		 6744 int fudged = 0;
6745
24eab124
AM		 6746 tryprefix:
6747#endif
3e73aa7c 6748 ok = 1;
fc0763e6
JB		 6749 if (current_templates->start->opcode_modifier.isstring
6750 && !current_templates->start->opcode_modifier.immext
6751 && (current_templates->end[-1].opcode_modifier.isstring
6752 || i.mem_operands))
6753 {
6754 /* Memory operands of string insns are special in that they only allow
6755 a single register (rDI, rSI, or rBX) as their memory address. */
6756 unsigned int expected;
6757
6758 kind = "string address";
6759
6760 if (current_templates->start->opcode_modifier.w)
6761 {
6762 i386_operand_type type = current_templates->end[-1].operand_types[0];
6763
6764 if (!type.bitfield.baseindex
6765 || ((!i.mem_operands != !intel_syntax)
6766 && current_templates->end[-1].operand_types[1]
6767 .bitfield.baseindex))
6768 type = current_templates->end[-1].operand_types[1];
6769 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6770 }
6771 else
6772 expected = 3 /* rBX */;
6773
6774 if (!i.base_reg || i.index_reg
6775 || operand_type_check (i.types[this_operand], disp))
6776 ok = -1;
6777 else if (!(flag_code == CODE_64BIT
6778 ? i.prefix[ADDR_PREFIX]
6779 ? i.base_reg->reg_type.bitfield.reg32
6780 : i.base_reg->reg_type.bitfield.reg64
6781 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6782 ? i.base_reg->reg_type.bitfield.reg32
6783 : i.base_reg->reg_type.bitfield.reg16))
6784 ok = 0;
6785 else if (i.base_reg->reg_num != expected)
6786 ok = -1;
6787
6788 if (ok < 0)
6789 {
6790 unsigned int j;
6791
6792 for (j = 0; j < i386_regtab_size; ++j)
6793 if ((flag_code == CODE_64BIT
6794 ? i.prefix[ADDR_PREFIX]
6795 ? i386_regtab[j].reg_type.bitfield.reg32
6796 : i386_regtab[j].reg_type.bitfield.reg64
6797 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6798 ? i386_regtab[j].reg_type.bitfield.reg32
6799 : i386_regtab[j].reg_type.bitfield.reg16)
6800 && i386_regtab[j].reg_num == expected)
6801 break;
9c2799c2 6802 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6803 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6804 operand_string,
6805 intel_syntax ? '[' : '(',
6806 register_prefix,
6807 i386_regtab[j].reg_name,
6808 intel_syntax ? ']' : ')');
6809 ok = 1;
6810 }
6811 }
6812 else if (flag_code == CODE_64BIT)
64e74474 6813 {
64e74474 6814 if ((i.base_reg
40fb9820
L		 6815 && ((i.prefix[ADDR_PREFIX] == 0
6816 && !i.base_reg->reg_type.bitfield.reg64)
6817 || (i.prefix[ADDR_PREFIX]
6818 && !i.base_reg->reg_type.bitfield.reg32))
6819 && (i.index_reg
9a04903e
JB		 6820 || i.base_reg->reg_num !=
6821 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6822 || (i.index_reg
40fb9820
L		 6823 && (!i.index_reg->reg_type.bitfield.baseindex
6824 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6825 && i.index_reg->reg_num != RegRiz
6826 && !i.index_reg->reg_type.bitfield.reg64
6827 )
40fb9820 6828 || (i.prefix[ADDR_PREFIX]
db51cc60 6829 && i.index_reg->reg_num != RegEiz
40fb9820 6830 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6831 ok = 0;
3e73aa7c
JH		 6832 }
6833 else
6834 {
6835 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6836 {
6837 /* 16bit checks. */
6838 if ((i.base_reg
40fb9820
L		 6839 && (!i.base_reg->reg_type.bitfield.reg16
6840 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6841 || (i.index_reg
40fb9820
L		 6842 && (!i.index_reg->reg_type.bitfield.reg16
6843 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6844 || !(i.base_reg
6845 && i.base_reg->reg_num < 6
6846 && i.index_reg->reg_num >= 6
6847 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6848 ok = 0;
6849 }
6850 else
e5cb08ac 6851 {
3e73aa7c
JH		 6852 /* 32bit checks. */
6853 if ((i.base_reg
40fb9820 6854 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6855 || (i.index_reg
db51cc60
L		 6856 && ((!i.index_reg->reg_type.bitfield.reg32
6857 && i.index_reg->reg_num != RegEiz)
40fb9820 6858 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6859 ok = 0;
3e73aa7c
JH		 6860 }
6861 }
6862 if (!ok)
24eab124
AM		 6863 {
6864#if INFER_ADDR_PREFIX
fc0763e6 6865 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6866 {
6867 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6868 i.prefixes += 1;
b23bac36
AM		 6869 /* Change the size of any displacement too. At most one of
6870 Disp16 or Disp32 is set.
6871 FIXME. There doesn't seem to be any real need for separate
6872 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6873 Removing them would probably clean up the code quite a lot. */
4eed87de 6874 if (flag_code != CODE_64BIT
40fb9820
L		 6875 && (i.types[this_operand].bitfield.disp16
6876 || i.types[this_operand].bitfield.disp32))
6877 i.types[this_operand]
c6fb90c8 6878 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6879 fudged = 1;
24eab124
AM		 6880 goto tryprefix;
6881 }
eecb386c 6882 if (fudged)
fc0763e6
JB		 6883 as_bad (_("`%s' is not a valid %s expression"),
6884 operand_string,
6885 kind);
eecb386c 6886 else
c388dee8 6887#endif
fc0763e6 6888 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6889 operand_string,
fc0763e6
JB		 6890 flag_code_names[i.prefix[ADDR_PREFIX]
6891 ? flag_code == CODE_32BIT
6892 ? CODE_16BIT
6893 : CODE_32BIT
6894 : flag_code],
6895 kind);
24eab124 6896 }
20f0a1fc 6897 return ok;
24eab124 6898}
252b5132 6899
fc0763e6 6900/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6901 on error. */
252b5132 6902
252b5132 6903static int
a7619375 6904i386_att_operand (char *operand_string)
252b5132 6905{
af6bdddf
AM		 6906 const reg_entry *r;
6907 char *end_op;
24eab124 6908 char *op_string = operand_string;
252b5132 6909
24eab124 6910 if (is_space_char (*op_string))
252b5132
RH		 6911 ++op_string;
6912
24eab124 6913 /* We check for an absolute prefix (differentiating,
47926f60 6914 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6915 if (*op_string == ABSOLUTE_PREFIX)
6916 {
6917 ++op_string;
6918 if (is_space_char (*op_string))
6919 ++op_string;
40fb9820 6920 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6921 }
252b5132 6922
47926f60 6923 /* Check if operand is a register. */
4d1bb795 6924 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6925 {
40fb9820
L		 6926 i386_operand_type temp;
6927
24eab124
AM		 6928 /* Check for a segment override by searching for ':' after a
6929 segment register. */
6930 op_string = end_op;
6931 if (is_space_char (*op_string))
6932 ++op_string;
40fb9820
L		 6933 if (*op_string == ':'
6934 && (r->reg_type.bitfield.sreg2
6935 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6936 {
6937 switch (r->reg_num)
6938 {
6939 case 0:
6940 i.seg[i.mem_operands] = &es;
6941 break;
6942 case 1:
6943 i.seg[i.mem_operands] = &cs;
6944 break;
6945 case 2:
6946 i.seg[i.mem_operands] = &ss;
6947 break;
6948 case 3:
6949 i.seg[i.mem_operands] = &ds;
6950 break;
6951 case 4:
6952 i.seg[i.mem_operands] = &fs;
6953 break;
6954 case 5:
6955 i.seg[i.mem_operands] = &gs;
6956 break;
6957 }
252b5132 6958
24eab124 6959 /* Skip the ':' and whitespace. */
252b5132
RH		 6960 ++op_string;
6961 if (is_space_char (*op_string))
24eab124 6962 ++op_string;
252b5132 6963
24eab124
AM		 6964 if (!is_digit_char (*op_string)
6965 && !is_identifier_char (*op_string)
6966 && *op_string != '('
6967 && *op_string != ABSOLUTE_PREFIX)
6968 {
6969 as_bad (_("bad memory operand `%s'"), op_string);
6970 return 0;
6971 }
47926f60 6972 /* Handle case of %es:*foo. */
24eab124
AM		 6973 if (*op_string == ABSOLUTE_PREFIX)
6974 {
6975 ++op_string;
6976 if (is_space_char (*op_string))
6977 ++op_string;
40fb9820 6978 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6979 }
6980 goto do_memory_reference;
6981 }
6982 if (*op_string)
6983 {
d0b47220 6984 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6985 return 0;
6986 }
40fb9820
L		 6987 temp = r->reg_type;
6988 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6989 i.types[this_operand] = operand_type_or (i.types[this_operand],
6990 temp);
7d5e4556 6991 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6992 i.op[this_operand].regs = r;
24eab124
AM		 6993 i.reg_operands++;
6994 }
af6bdddf
AM		 6995 else if (*op_string == REGISTER_PREFIX)
6996 {
6997 as_bad (_("bad register name `%s'"), op_string);
6998 return 0;
6999 }
24eab124 7000 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7001 {
24eab124 7002 ++op_string;
40fb9820 7003 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7004 {
d0b47220 7005 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7006 return 0;
7007 }
7008 if (!i386_immediate (op_string))
7009 return 0;
7010 }
7011 else if (is_digit_char (*op_string)
7012 || is_identifier_char (*op_string)
e5cb08ac 7013 || *op_string == '(')
24eab124 7014 {
47926f60 7015 /* This is a memory reference of some sort. */
af6bdddf 7016 char *base_string;
252b5132 7017
47926f60 7018 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7019 char *displacement_string_start;
7020 char *displacement_string_end;
252b5132 7021
24eab124 7022 do_memory_reference:
24eab124 7023 if ((i.mem_operands == 1
40fb9820 7024 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7025 || i.mem_operands == 2)
7026 {
7027 as_bad (_("too many memory references for `%s'"),
7028 current_templates->start->name);
7029 return 0;
7030 }
252b5132 7031
24eab124
AM		 7032 /* Check for base index form. We detect the base index form by
7033 looking for an ')' at the end of the operand, searching
7034 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7035 after the '('. */
af6bdddf 7036 base_string = op_string + strlen (op_string);
c3332e24 7037
af6bdddf
AM		 7038 --base_string;
7039 if (is_space_char (*base_string))
7040 --base_string;
252b5132 7041
47926f60 7042 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7043 displacement_string_start = op_string;
7044 displacement_string_end = base_string + 1;
252b5132 7045
24eab124
AM		 7046 if (*base_string == ')')
7047 {
af6bdddf 7048 char *temp_string;
24eab124
AM		 7049 unsigned int parens_balanced = 1;
7050 /* We've already checked that the number of left & right ()'s are
47926f60 7051 equal, so this loop will not be infinite. */
24eab124
AM		 7052 do
7053 {
7054 base_string--;
7055 if (*base_string == ')')
7056 parens_balanced++;
7057 if (*base_string == '(')
7058 parens_balanced--;
7059 }
7060 while (parens_balanced);
c3332e24 7061
af6bdddf 7062 temp_string = base_string;
c3332e24 7063
24eab124 7064 /* Skip past '(' and whitespace. */
252b5132
RH		 7065 ++base_string;
7066 if (is_space_char (*base_string))
24eab124 7067 ++base_string;
252b5132 7068
af6bdddf 7069 if (*base_string == ','
4eed87de
AM		 7070 || ((i.base_reg = parse_register (base_string, &end_op))
7071 != NULL))
252b5132 7072 {
af6bdddf 7073 displacement_string_end = temp_string;
252b5132 7074
40fb9820 7075 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7076
af6bdddf 7077 if (i.base_reg)
24eab124 7078 {
24eab124
AM		 7079 base_string = end_op;
7080 if (is_space_char (*base_string))
7081 ++base_string;
af6bdddf
AM		 7082 }
7083
7084 /* There may be an index reg or scale factor here. */
7085 if (*base_string == ',')
7086 {
7087 ++base_string;
7088 if (is_space_char (*base_string))
7089 ++base_string;
7090
4eed87de
AM		 7091 if ((i.index_reg = parse_register (base_string, &end_op))
7092 != NULL)
24eab124 7093 {
af6bdddf 7094 base_string = end_op;
24eab124
AM		 7095 if (is_space_char (*base_string))
7096 ++base_string;
af6bdddf
AM		 7097 if (*base_string == ',')
7098 {
7099 ++base_string;
7100 if (is_space_char (*base_string))
7101 ++base_string;
7102 }
e5cb08ac 7103 else if (*base_string != ')')
af6bdddf 7104 {
4eed87de
AM		 7105 as_bad (_("expecting `,' or `)' "
7106 "after index register in `%s'"),
af6bdddf
AM		 7107 operand_string);
7108 return 0;
7109 }
24eab124 7110 }
af6bdddf 7111 else if (*base_string == REGISTER_PREFIX)
24eab124 7112 {
af6bdddf 7113 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7114 return 0;
7115 }
252b5132 7116
47926f60 7117 /* Check for scale factor. */
551c1ca1 7118 if (*base_string != ')')
af6bdddf 7119 {
551c1ca1
AM		 7120 char *end_scale = i386_scale (base_string);
7121
7122 if (!end_scale)
af6bdddf 7123 return 0;
24eab124 7124
551c1ca1 7125 base_string = end_scale;
af6bdddf
AM		 7126 if (is_space_char (*base_string))
7127 ++base_string;
7128 if (*base_string != ')')
7129 {
4eed87de
AM		 7130 as_bad (_("expecting `)' "
7131 "after scale factor in `%s'"),
af6bdddf
AM		 7132 operand_string);
7133 return 0;
7134 }
7135 }
7136 else if (!i.index_reg)
24eab124 7137 {
4eed87de
AM		 7138 as_bad (_("expecting index register or scale factor "
7139 "after `,'; got '%c'"),
af6bdddf 7140 *base_string);
24eab124
AM		 7141 return 0;
7142 }
7143 }
af6bdddf 7144 else if (*base_string != ')')
24eab124 7145 {
4eed87de
AM		 7146 as_bad (_("expecting `,' or `)' "
7147 "after base register in `%s'"),
af6bdddf 7148 operand_string);
24eab124
AM		 7149 return 0;
7150 }
c3332e24 7151 }
af6bdddf 7152 else if (*base_string == REGISTER_PREFIX)
c3332e24 7153 {
af6bdddf 7154 as_bad (_("bad register name `%s'"), base_string);
24eab124 7155 return 0;
c3332e24 7156 }
24eab124
AM		 7157 }
7158
7159 /* If there's an expression beginning the operand, parse it,
7160 assuming displacement_string_start and
7161 displacement_string_end are meaningful. */
7162 if (displacement_string_start != displacement_string_end)
7163 {
7164 if (!i386_displacement (displacement_string_start,
7165 displacement_string_end))
7166 return 0;
7167 }
7168
7169 /* Special case for (%dx) while doing input/output op. */
7170 if (i.base_reg
0dfbf9d7
L		 7171 && operand_type_equal (&i.base_reg->reg_type,
7172 &reg16_inoutportreg)
24eab124
AM		 7173 && i.index_reg == 0
7174 && i.log2_scale_factor == 0
7175 && i.seg[i.mem_operands] == 0
40fb9820 7176 && !operand_type_check (i.types[this_operand], disp))
24eab124 7177 {
65da13b5 7178 i.types[this_operand] = inoutportreg;
24eab124
AM		 7179 return 1;
7180 }
7181
eecb386c
AM		 7182 if (i386_index_check (operand_string) == 0)
7183 return 0;
5c07affc 7184 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7185 i.mem_operands++;
7186 }
7187 else
ce8a8b2f
AM		 7188 {
7189 /* It's not a memory operand; argh! */
24eab124
AM		 7190 as_bad (_("invalid char %s beginning operand %d `%s'"),
7191 output_invalid (*op_string),
7192 this_operand + 1,
7193 op_string);
7194 return 0;
7195 }
47926f60 7196 return 1; /* Normal return. */
252b5132
RH		 7197}
7198\f
ee7fcc42
AM		 7199/* md_estimate_size_before_relax()
7200
7201 Called just before relax() for rs_machine_dependent frags. The x86
7202 assembler uses these frags to handle variable size jump
7203 instructions.
7204
7205 Any symbol that is now undefined will not become defined.
7206 Return the correct fr_subtype in the frag.
7207 Return the initial "guess for variable size of frag" to caller.
7208 The guess is actually the growth beyond the fixed part. Whatever
7209 we do to grow the fixed or variable part contributes to our
7210 returned value. */
7211
252b5132
RH		 7212int
7213md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7214 fragS *fragP;
7215 segT segment;
252b5132 7216{
252b5132 7217 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7218 check for un-relaxable symbols. On an ELF system, we can't relax
7219 an externally visible symbol, because it may be overridden by a
7220 shared library. */
7221 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7223 || (IS_ELF
31312f95 7224 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7225 || S_IS_WEAK (fragP->fr_symbol)
7226 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7227 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7228#endif
7229#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7230 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7231 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7232#endif
7233 )
252b5132 7234 {
b98ef147
AM		 7235 /* Symbol is undefined in this segment, or we need to keep a
7236 reloc so that weak symbols can be overridden. */
7237 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7238 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7239 unsigned char *opcode;
7240 int old_fr_fix;
f6af82bd 7241
ee7fcc42 7242 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7243 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7244 else if (size == 2)
f6af82bd
AM		 7245 reloc_type = BFD_RELOC_16_PCREL;
7246 else
7247 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7248
ee7fcc42
AM		 7249 old_fr_fix = fragP->fr_fix;
7250 opcode = (unsigned char *) fragP->fr_opcode;
7251
fddf5b5b 7252 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7253 {
fddf5b5b
AM		 7254 case UNCOND_JUMP:
7255 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7256 opcode[0] = 0xe9;
252b5132 7257 fragP->fr_fix += size;
062cd5e7
AS		 7258 fix_new (fragP, old_fr_fix, size,
7259 fragP->fr_symbol,
7260 fragP->fr_offset, 1,
7261 reloc_type);
252b5132
RH		 7262 break;
7263
fddf5b5b 7264 case COND_JUMP86:
412167cb
AM		 7265 if (size == 2
7266 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7267 {
7268 /* Negate the condition, and branch past an
7269 unconditional jump. */
7270 opcode[0] ^= 1;
7271 opcode[1] = 3;
7272 /* Insert an unconditional jump. */
7273 opcode[2] = 0xe9;
7274 /* We added two extra opcode bytes, and have a two byte
7275 offset. */
7276 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7277 fix_new (fragP, old_fr_fix + 2, 2,
7278 fragP->fr_symbol,
7279 fragP->fr_offset, 1,
7280 reloc_type);
fddf5b5b
AM		 7281 break;
7282 }
7283 /* Fall through. */
7284
7285 case COND_JUMP:
412167cb
AM		 7286 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7287 {
3e02c1cc
AM		 7288 fixS *fixP;
7289
412167cb 7290 fragP->fr_fix += 1;
3e02c1cc
AM		 7291 fixP = fix_new (fragP, old_fr_fix, 1,
7292 fragP->fr_symbol,
7293 fragP->fr_offset, 1,
7294 BFD_RELOC_8_PCREL);
7295 fixP->fx_signed = 1;
412167cb
AM		 7296 break;
7297 }
93c2a809 7298
24eab124 7299 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7300 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7301 opcode[1] = opcode[0] + 0x10;
f6af82bd 7302 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7303 /* We've added an opcode byte. */
7304 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7305 fix_new (fragP, old_fr_fix + 1, size,
7306 fragP->fr_symbol,
7307 fragP->fr_offset, 1,
7308 reloc_type);
252b5132 7309 break;
fddf5b5b
AM		 7310
7311 default:
7312 BAD_CASE (fragP->fr_subtype);
7313 break;
252b5132
RH		 7314 }
7315 frag_wane (fragP);
ee7fcc42 7316 return fragP->fr_fix - old_fr_fix;
252b5132 7317 }
93c2a809 7318
93c2a809
AM		 7319 /* Guess size depending on current relax state. Initially the relax
7320 state will correspond to a short jump and we return 1, because
7321 the variable part of the frag (the branch offset) is one byte
7322 long. However, we can relax a section more than once and in that
7323 case we must either set fr_subtype back to the unrelaxed state,
7324 or return the value for the appropriate branch. */
7325 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7326}
7327
47926f60
KH		 7328/* Called after relax() is finished.
7329
7330 In: Address of frag.
7331 fr_type == rs_machine_dependent.
7332 fr_subtype is what the address relaxed to.
7333
7334 Out: Any fixSs and constants are set up.
7335 Caller will turn frag into a ".space 0". */
7336
252b5132
RH		 7337void
7338md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7339 bfd *abfd ATTRIBUTE_UNUSED;
7340 segT sec ATTRIBUTE_UNUSED;
29b0f896 7341 fragS *fragP;
252b5132 7342{
29b0f896 7343 unsigned char *opcode;
252b5132 7344 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7345 offsetT target_address;
7346 offsetT opcode_address;
252b5132 7347 unsigned int extension = 0;
847f7ad4 7348 offsetT displacement_from_opcode_start;
252b5132
RH		 7349
7350 opcode = (unsigned char *) fragP->fr_opcode;
7351
47926f60 7352 /* Address we want to reach in file space. */
252b5132 7353 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7354
47926f60 7355 /* Address opcode resides at in file space. */
252b5132
RH		 7356 opcode_address = fragP->fr_address + fragP->fr_fix;
7357
47926f60 7358 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7359 displacement_from_opcode_start = target_address - opcode_address;
7360
fddf5b5b 7361 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7362 {
47926f60
KH		 7363 /* Don't have to change opcode. */
7364 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7365 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7366 }
7367 else
7368 {
7369 if (no_cond_jump_promotion
7370 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7371 as_warn_where (fragP->fr_file, fragP->fr_line,
7372 _("long jump required"));
252b5132 7373
fddf5b5b
AM		 7374 switch (fragP->fr_subtype)
7375 {
7376 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7377 extension = 4; /* 1 opcode + 4 displacement */
7378 opcode[0] = 0xe9;
7379 where_to_put_displacement = &opcode[1];
7380 break;
252b5132 7381
fddf5b5b
AM		 7382 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7383 extension = 2; /* 1 opcode + 2 displacement */
7384 opcode[0] = 0xe9;
7385 where_to_put_displacement = &opcode[1];
7386 break;
252b5132 7387
fddf5b5b
AM		 7388 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7389 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7390 extension = 5; /* 2 opcode + 4 displacement */
7391 opcode[1] = opcode[0] + 0x10;
7392 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7393 where_to_put_displacement = &opcode[2];
7394 break;
252b5132 7395
fddf5b5b
AM		 7396 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7397 extension = 3; /* 2 opcode + 2 displacement */
7398 opcode[1] = opcode[0] + 0x10;
7399 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7400 where_to_put_displacement = &opcode[2];
7401 break;
252b5132 7402
fddf5b5b
AM		 7403 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7404 extension = 4;
7405 opcode[0] ^= 1;
7406 opcode[1] = 3;
7407 opcode[2] = 0xe9;
7408 where_to_put_displacement = &opcode[3];
7409 break;
7410
7411 default:
7412 BAD_CASE (fragP->fr_subtype);
7413 break;
7414 }
252b5132 7415 }
fddf5b5b 7416
7b81dfbb
AJ		 7417 /* If size if less then four we are sure that the operand fits,
7418 but if it's 4, then it could be that the displacement is larger
7419 then -/+ 2GB. */
7420 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7421 && object_64bit
7422 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7423 + ((addressT) 1 << 31))
7424 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7425 {
7426 as_bad_where (fragP->fr_file, fragP->fr_line,
7427 _("jump target out of range"));
7428 /* Make us emit 0. */
7429 displacement_from_opcode_start = extension;
7430 }
47926f60 7431 /* Now put displacement after opcode. */
252b5132
RH		 7432 md_number_to_chars ((char *) where_to_put_displacement,
7433 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7434 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7435 fragP->fr_fix += extension;
7436}
7437\f
252b5132
RH		 7438/* Apply a fixup (fixS) to segment data, once it has been determined
7439 by our caller that we have all the info we need to fix it up.
7440
7441 On the 386, immediates, displacements, and data pointers are all in
7442 the same (little-endian) format, so we don't need to care about which
7443 we are handling. */
7444
94f592af 7445void
55cf6793 7446md_apply_fix (fixP, valP, seg)
47926f60
KH		 7447 /* The fix we're to put in. */
7448 fixS *fixP;
47926f60 7449 /* Pointer to the value of the bits. */
c6682705 7450 valueT *valP;
47926f60
KH		 7451 /* Segment fix is from. */
7452 segT seg ATTRIBUTE_UNUSED;
252b5132 7453{
94f592af 7454 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7455 valueT value = *valP;
252b5132 7456
f86103b7 7457#if !defined (TE_Mach)
93382f6d
AM		 7458 if (fixP->fx_pcrel)
7459 {
7460 switch (fixP->fx_r_type)
7461 {
5865bb77
ILT		 7462 default:
7463 break;
7464
d6ab8113
JB		 7465 case BFD_RELOC_64:
7466 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7467 break;
93382f6d 7468 case BFD_RELOC_32:
ae8887b5 7469 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7470 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7471 break;
7472 case BFD_RELOC_16:
7473 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7474 break;
7475 case BFD_RELOC_8:
7476 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7477 break;
7478 }
7479 }
252b5132 7480
a161fe53 7481 if (fixP->fx_addsy != NULL
31312f95 7482 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7483 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7484 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7485 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7486 && !use_rela_relocations)
252b5132 7487 {
31312f95
AM		 7488 /* This is a hack. There should be a better way to handle this.
7489 This covers for the fact that bfd_install_relocation will
7490 subtract the current location (for partial_inplace, PC relative
7491 relocations); see more below. */
252b5132 7492#ifndef OBJ_AOUT
718ddfc0 7493 if (IS_ELF
252b5132
RH		 7494#ifdef TE_PE
7495 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7496#endif
7497 )
7498 value += fixP->fx_where + fixP->fx_frag->fr_address;
7499#endif
7500#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7501 if (IS_ELF)
252b5132 7502 {
6539b54b 7503 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7504
6539b54b 7505 if ((sym_seg == seg
2f66722d 7506 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7507 && sym_seg != absolute_section))
af65af87 7508 && !generic_force_reloc (fixP))
2f66722d
AM		 7509 {
7510 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7511 bfd_install_relocation subtracts them out again. I think
7512 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7513 it. FIXME. */
7514 value += fixP->fx_where + fixP->fx_frag->fr_address;
7515 }
252b5132
RH		 7516 }
7517#endif
7518#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7519 /* For some reason, the PE format does not store a
7520 section address offset for a PC relative symbol. */
7521 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7522 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7523 value += md_pcrel_from (fixP);
7524#endif
7525 }
fbeb56a4
DK		 7526#if defined (OBJ_COFF) && defined (TE_PE)
7527 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7528 {
7529 value -= S_GET_VALUE (fixP->fx_addsy);
7530 }
7531#endif
252b5132
RH		 7532
7533 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7534 and we must not disappoint it. */
252b5132 7535#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7536 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7537 switch (fixP->fx_r_type)
7538 {
7539 case BFD_RELOC_386_PLT32:
3e73aa7c 7540 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7541 /* Make the jump instruction point to the address of the operand. At
7542 runtime we merely add the offset to the actual PLT entry. */
7543 value = -4;
7544 break;
31312f95 7545
13ae64f3
JJ		 7546 case BFD_RELOC_386_TLS_GD:
7547 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7548 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7549 case BFD_RELOC_386_TLS_IE:
7550 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7551 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7552 case BFD_RELOC_X86_64_TLSGD:
7553 case BFD_RELOC_X86_64_TLSLD:
7554 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7555 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7556 value = 0; /* Fully resolved at runtime. No addend. */
7557 /* Fallthrough */
7558 case BFD_RELOC_386_TLS_LE:
7559 case BFD_RELOC_386_TLS_LDO_32:
7560 case BFD_RELOC_386_TLS_LE_32:
7561 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7562 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7563 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7564 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7565 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7566 break;
7567
67a4f2b7
AO		 7568 case BFD_RELOC_386_TLS_DESC_CALL:
7569 case BFD_RELOC_X86_64_TLSDESC_CALL:
7570 value = 0; /* Fully resolved at runtime. No addend. */
7571 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7572 fixP->fx_done = 0;
7573 return;
7574
00f7efb6
JJ		 7575 case BFD_RELOC_386_GOT32:
7576 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7577 value = 0; /* Fully resolved at runtime. No addend. */
7578 break;
47926f60
KH		 7579
7580 case BFD_RELOC_VTABLE_INHERIT:
7581 case BFD_RELOC_VTABLE_ENTRY:
7582 fixP->fx_done = 0;
94f592af 7583 return;
47926f60
KH		 7584
7585 default:
7586 break;
7587 }
7588#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7589 *valP = value;
f86103b7 7590#endif /* !defined (TE_Mach) */
3e73aa7c 7591
3e73aa7c 7592 /* Are we finished with this relocation now? */
c6682705 7593 if (fixP->fx_addsy == NULL)
3e73aa7c 7594 fixP->fx_done = 1;
fbeb56a4
DK		 7595#if defined (OBJ_COFF) && defined (TE_PE)
7596 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7597 {
7598 fixP->fx_done = 0;
7599 /* Remember value for tc_gen_reloc. */
7600 fixP->fx_addnumber = value;
7601 /* Clear out the frag for now. */
7602 value = 0;
7603 }
7604#endif
3e73aa7c
JH		 7605 else if (use_rela_relocations)
7606 {
7607 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7608 /* Remember value for tc_gen_reloc. */
7609 fixP->fx_addnumber = value;
3e73aa7c
JH		 7610 value = 0;
7611 }
f86103b7 7612
94f592af 7613 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7614}
252b5132 7615\f
252b5132 7616char *
499ac353 7617md_atof (int type, char *litP, int *sizeP)
252b5132 7618{
499ac353
NC		 7619 /* This outputs the LITTLENUMs in REVERSE order;
7620 in accord with the bigendian 386. */
7621 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7622}
7623\f
2d545b82 7624static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7625
252b5132 7626static char *
e3bb37b5 7627output_invalid (int c)
252b5132 7628{
3882b010 7629 if (ISPRINT (c))
f9f21a03
L		 7630 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7631 "'%c'", c);
252b5132 7632 else
f9f21a03 7633 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7634 "(0x%x)", (unsigned char) c);
252b5132
RH		 7635 return output_invalid_buf;
7636}
7637
af6bdddf 7638/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7639
7640static const reg_entry *
4d1bb795 7641parse_real_register (char *reg_string, char **end_op)
252b5132 7642{
af6bdddf
AM		 7643 char *s = reg_string;
7644 char *p;
252b5132
RH		 7645 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7646 const reg_entry *r;
7647
7648 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7649 if (*s == REGISTER_PREFIX)
7650 ++s;
7651
7652 if (is_space_char (*s))
7653 ++s;
7654
7655 p = reg_name_given;
af6bdddf 7656 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7657 {
7658 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7659 return (const reg_entry *) NULL;
7660 s++;
252b5132
RH		 7661 }
7662
6588847e
DN		 7663 /* For naked regs, make sure that we are not dealing with an identifier.
7664 This prevents confusing an identifier like `eax_var' with register
7665 `eax'. */
7666 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7667 return (const reg_entry *) NULL;
7668
af6bdddf 7669 *end_op = s;
252b5132
RH		 7670
7671 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7672
5f47d35b 7673 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7674 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7675 {
5f47d35b
AM		 7676 if (is_space_char (*s))
7677 ++s;
7678 if (*s == '(')
7679 {
af6bdddf 7680 ++s;
5f47d35b
AM		 7681 if (is_space_char (*s))
7682 ++s;
7683 if (*s >= '0' && *s <= '7')
7684 {
db557034 7685 int fpr = *s - '0';
af6bdddf 7686 ++s;
5f47d35b
AM		 7687 if (is_space_char (*s))
7688 ++s;
7689 if (*s == ')')
7690 {
7691 *end_op = s + 1;
1e9cc1c2 7692 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7693 know (r);
7694 return r + fpr;
5f47d35b 7695 }
5f47d35b 7696 }
47926f60 7697 /* We have "%st(" then garbage. */
5f47d35b
AM		 7698 return (const reg_entry *) NULL;
7699 }
7700 }
7701
a60de03c
JB		 7702 if (r == NULL || allow_pseudo_reg)
7703 return r;
7704
0dfbf9d7 7705 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7706 return (const reg_entry *) NULL;
7707
192dc9c6
JB		 7708 if ((r->reg_type.bitfield.reg32
7709 || r->reg_type.bitfield.sreg3
7710 || r->reg_type.bitfield.control
7711 || r->reg_type.bitfield.debug
7712 || r->reg_type.bitfield.test)
7713 && !cpu_arch_flags.bitfield.cpui386)
7714 return (const reg_entry *) NULL;
7715
309d3373
JB		 7716 if (r->reg_type.bitfield.floatreg
7717 && !cpu_arch_flags.bitfield.cpu8087
7718 && !cpu_arch_flags.bitfield.cpu287
7719 && !cpu_arch_flags.bitfield.cpu387)
7720 return (const reg_entry *) NULL;
7721
192dc9c6
JB		 7722 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7723 return (const reg_entry *) NULL;
7724
7725 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7726 return (const reg_entry *) NULL;
7727
40f12533
L		 7728 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7729 return (const reg_entry *) NULL;
7730
db51cc60 7731 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7732 if (!allow_index_reg
db51cc60
L		 7733 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7734 return (const reg_entry *) NULL;
7735
a60de03c
JB		 7736 if (((r->reg_flags & (RegRex64 | RegRex))
7737 || r->reg_type.bitfield.reg64)
40fb9820 7738 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7739 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7740 && flag_code != CODE_64BIT)
20f0a1fc 7741 return (const reg_entry *) NULL;
1ae00879 7742
b7240065
JB		 7743 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7744 return (const reg_entry *) NULL;
7745
252b5132
RH		 7746 return r;
7747}
4d1bb795
JB		 7748
7749/* REG_STRING starts *before* REGISTER_PREFIX. */
7750
7751static const reg_entry *
7752parse_register (char *reg_string, char **end_op)
7753{
7754 const reg_entry *r;
7755
7756 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7757 r = parse_real_register (reg_string, end_op);
7758 else
7759 r = NULL;
7760 if (!r)
7761 {
7762 char *save = input_line_pointer;
7763 char c;
7764 symbolS *symbolP;
7765
7766 input_line_pointer = reg_string;
7767 c = get_symbol_end ();
7768 symbolP = symbol_find (reg_string);
7769 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7770 {
7771 const expressionS *e = symbol_get_value_expression (symbolP);
7772
7773 know (e->X_op == O_register);
4eed87de 7774 know (e->X_add_number >= 0
c3fe08fa 7775 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7776 r = i386_regtab + e->X_add_number;
7777 *end_op = input_line_pointer;
7778 }
7779 *input_line_pointer = c;
7780 input_line_pointer = save;
7781 }
7782 return r;
7783}
7784
7785int
7786i386_parse_name (char *name, expressionS *e, char *nextcharP)
7787{
7788 const reg_entry *r;
7789 char *end = input_line_pointer;
7790
7791 *end = *nextcharP;
7792 r = parse_register (name, &input_line_pointer);
7793 if (r && end <= input_line_pointer)
7794 {
7795 *nextcharP = *input_line_pointer;
7796 *input_line_pointer = 0;
7797 e->X_op = O_register;
7798 e->X_add_number = r - i386_regtab;
7799 return 1;
7800 }
7801 input_line_pointer = end;
7802 *end = 0;
ee86248c 7803 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7804}
7805
7806void
7807md_operand (expressionS *e)
7808{
ee86248c
JB		 7809 char *end;
7810 const reg_entry *r;
4d1bb795 7811
ee86248c
JB		 7812 switch (*input_line_pointer)
7813 {
7814 case REGISTER_PREFIX:
7815 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7816 if (r)
7817 {
7818 e->X_op = O_register;
7819 e->X_add_number = r - i386_regtab;
7820 input_line_pointer = end;
7821 }
ee86248c
JB		 7822 break;
7823
7824 case '[':
9c2799c2 7825 gas_assert (intel_syntax);
ee86248c
JB		 7826 end = input_line_pointer++;
7827 expression (e);
7828 if (*input_line_pointer == ']')
7829 {
7830 ++input_line_pointer;
7831 e->X_op_symbol = make_expr_symbol (e);
7832 e->X_add_symbol = NULL;
7833 e->X_add_number = 0;
7834 e->X_op = O_index;
7835 }
7836 else
7837 {
7838 e->X_op = O_absent;
7839 input_line_pointer = end;
7840 }
7841 break;
4d1bb795
JB		 7842 }
7843}
7844
252b5132 7845\f
4cc782b5 7846#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7847const char *md_shortopts = "kVQ:sqn";
252b5132 7848#else
12b55ccc 7849const char *md_shortopts = "qn";
252b5132 7850#endif
6e0b89ee 7851
3e73aa7c 7852#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7853#define OPTION_64 (OPTION_MD_BASE + 1)
7854#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7855#define OPTION_MARCH (OPTION_MD_BASE + 3)
7856#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7857#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7858#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7859#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7860#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7861#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7862#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7863#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7864
99ad8390
NC		 7865struct option md_longopts[] =
7866{
3e73aa7c 7867 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7868#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7869 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7870 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7871#endif
b3b91714 7872 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7873 {"march", required_argument, NULL, OPTION_MARCH},
7874 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7875 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7876 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7877 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7878 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7879 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7880 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7881 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7882 {NULL, no_argument, NULL, 0}
7883};
7884size_t md_longopts_size = sizeof (md_longopts);
7885
7886int
9103f4f4 7887md_parse_option (int c, char *arg)
252b5132 7888{
91d6fa6a 7889 unsigned int j;
6305a203 7890 char *arch, *next;
9103f4f4 7891
252b5132
RH		 7892 switch (c)
7893 {
12b55ccc
L		 7894 case 'n':
7895 optimize_align_code = 0;
7896 break;
7897
a38cf1db
AM		 7898 case 'q':
7899 quiet_warnings = 1;
252b5132
RH		 7900 break;
7901
7902#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7903 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7904 should be emitted or not. FIXME: Not implemented. */
7905 case 'Q':
252b5132
RH		 7906 break;
7907
7908 /* -V: SVR4 argument to print version ID. */
7909 case 'V':
7910 print_version_id ();
7911 break;
7912
a38cf1db
AM		 7913 /* -k: Ignore for FreeBSD compatibility. */
7914 case 'k':
252b5132 7915 break;
4cc782b5
ILT		 7916
7917 case 's':
7918 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7919 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7920 break;
99ad8390 7921#endif
321098a5
L		 7922#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7923 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7924 case OPTION_64:
7925 {
7926 const char **list, **l;
7927
3e73aa7c
JH		 7928 list = bfd_target_list ();
7929 for (l = list; *l != NULL; l++)
8620418b 7930 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7931 || strcmp (*l, "coff-x86-64") == 0
7932 || strcmp (*l, "pe-x86-64") == 0
7933 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7934 {
7935 default_arch = "x86_64";
7936 break;
7937 }
3e73aa7c 7938 if (*l == NULL)
6e0b89ee 7939 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7940 free (list);
7941 }
7942 break;
7943#endif
252b5132 7944
6e0b89ee
AM		 7945 case OPTION_32:
7946 default_arch = "i386";
7947 break;
7948
b3b91714
AM		 7949 case OPTION_DIVIDE:
7950#ifdef SVR4_COMMENT_CHARS
7951 {
7952 char *n, *t;
7953 const char *s;
7954
7955 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7956 t = n;
7957 for (s = i386_comment_chars; *s != '\0'; s++)
7958 if (*s != '/')
7959 *t++ = *s;
7960 *t = '\0';
7961 i386_comment_chars = n;
7962 }
7963#endif
7964 break;
7965
9103f4f4 7966 case OPTION_MARCH:
6305a203
L		 7967 arch = xstrdup (arg);
7968 do
9103f4f4 7969 {
6305a203
L		 7970 if (*arch == '.')
7971 as_fatal (_("Invalid -march= option: `%s'"), arg);
7972 next = strchr (arch, '+');
7973 if (next)
7974 *next++ = '\0';
91d6fa6a 7975 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 7976 {
91d6fa6a 7977 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 7978 {
6305a203 7979 /* Processor. */
91d6fa6a 7980 cpu_arch_name = cpu_arch[j].name;
6305a203 7981 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 7982 cpu_arch_flags = cpu_arch[j].flags;
7983 cpu_arch_isa = cpu_arch[j].type;
7984 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 7985 if (!cpu_arch_tune_set)
7986 {
7987 cpu_arch_tune = cpu_arch_isa;
7988 cpu_arch_tune_flags = cpu_arch_isa_flags;
7989 }
7990 break;
7991 }
91d6fa6a
NC		 7992 else if (*cpu_arch [j].name == '.'
7993 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 7994 {
7995 /* ISA entension. */
7996 i386_cpu_flags flags;
309d3373
JB		 7997
7998 if (strncmp (arch, "no", 2))
7999 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8000 cpu_arch[j].flags);
309d3373
JB		 8001 else
8002 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8003 cpu_arch[j].flags);
0dfbf9d7 8004 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8005 {
8006 if (cpu_sub_arch_name)
8007 {
8008 char *name = cpu_sub_arch_name;
8009 cpu_sub_arch_name = concat (name,
91d6fa6a 8010 cpu_arch[j].name,
1bf57e9f 8011 (const char *) NULL);
6305a203
L		 8012 free (name);
8013 }
8014 else
91d6fa6a 8015 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8016 cpu_arch_flags = flags;
8017 }
8018 break;
ccc9c027 8019 }
9103f4f4 8020 }
6305a203 8021
91d6fa6a 8022 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8023 as_fatal (_("Invalid -march= option: `%s'"), arg);
8024
8025 arch = next;
9103f4f4 8026 }
6305a203 8027 while (next != NULL );
9103f4f4
L		 8028 break;
8029
8030 case OPTION_MTUNE:
8031 if (*arg == '.')
8032 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8033 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8034 {
91d6fa6a 8035 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8036 {
ccc9c027 8037 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8038 cpu_arch_tune = cpu_arch [j].type;
8039 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8040 break;
8041 }
8042 }
91d6fa6a 8043 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8044 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8045 break;
8046
1efbbeb4
L		 8047 case OPTION_MMNEMONIC:
8048 if (strcasecmp (arg, "att") == 0)
8049 intel_mnemonic = 0;
8050 else if (strcasecmp (arg, "intel") == 0)
8051 intel_mnemonic = 1;
8052 else
8053 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8054 break;
8055
8056 case OPTION_MSYNTAX:
8057 if (strcasecmp (arg, "att") == 0)
8058 intel_syntax = 0;
8059 else if (strcasecmp (arg, "intel") == 0)
8060 intel_syntax = 1;
8061 else
8062 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8063 break;
8064
8065 case OPTION_MINDEX_REG:
8066 allow_index_reg = 1;
8067 break;
8068
8069 case OPTION_MNAKED_REG:
8070 allow_naked_reg = 1;
8071 break;
8072
8073 case OPTION_MOLD_GCC:
8074 old_gcc = 1;
1efbbeb4
L		 8075 break;
8076
c0f3af97
L		 8077 case OPTION_MSSE2AVX:
8078 sse2avx = 1;
8079 break;
8080
daf50ae7
L		 8081 case OPTION_MSSE_CHECK:
8082 if (strcasecmp (arg, "error") == 0)
8083 sse_check = sse_check_error;
8084 else if (strcasecmp (arg, "warning") == 0)
8085 sse_check = sse_check_warning;
8086 else if (strcasecmp (arg, "none") == 0)
8087 sse_check = sse_check_none;
8088 else
8089 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8090 break;
8091
252b5132
RH		 8092 default:
8093 return 0;
8094 }
8095 return 1;
8096}
8097
8a2c8fef
L		 8098#define MESSAGE_TEMPLATE \
8099" "
8100
8101static void
8102show_arch (FILE *stream, int ext)
8103{
8104 static char message[] = MESSAGE_TEMPLATE;
8105 char *start = message + 27;
8106 char *p;
8107 int size = sizeof (MESSAGE_TEMPLATE);
8108 int left;
8109 const char *name;
8110 int len;
8111 unsigned int j;
8112
8113 p = start;
8114 left = size - (start - message);
8115 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8116 {
8117 /* Should it be skipped? */
8118 if (cpu_arch [j].skip)
8119 continue;
8120
8121 name = cpu_arch [j].name;
8122 len = cpu_arch [j].len;
8123 if (*name == '.')
8124 {
8125 /* It is an extension. Skip if we aren't asked to show it. */
8126 if (ext)
8127 {
8128 name++;
8129 len--;
8130 }
8131 else
8132 continue;
8133 }
8134 else if (ext)
8135 {
8136 /* It is an processor. Skip if we show only extension. */
8137 continue;
8138 }
8139
8140 /* Reserve 2 spaces for ", " or ",\0" */
8141 left -= len + 2;
8142
8143 /* Check if there is any room. */
8144 if (left >= 0)
8145 {
8146 if (p != start)
8147 {
8148 *p++ = ',';
8149 *p++ = ' ';
8150 }
8151 p = mempcpy (p, name, len);
8152 }
8153 else
8154 {
8155 /* Output the current message now and start a new one. */
8156 *p++ = ',';
8157 *p = '\0';
8158 fprintf (stream, "%s\n", message);
8159 p = start;
8160 left = size - (start - message) - len - 2;
8161
8162 gas_assert (left >= 0);
8163
8164 p = mempcpy (p, name, len);
8165 }
8166 }
8167
8168 *p = '\0';
8169 fprintf (stream, "%s\n", message);
8170}
8171
252b5132 8172void
8a2c8fef 8173md_show_usage (FILE *stream)
252b5132 8174{
4cc782b5
ILT		 8175#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8176 fprintf (stream, _("\
a38cf1db
AM		 8177 -Q ignored\n\
8178 -V print assembler version number\n\
b3b91714
AM		 8179 -k ignored\n"));
8180#endif
8181 fprintf (stream, _("\
12b55ccc 8182 -n Do not optimize code alignment\n\
b3b91714
AM		 8183 -q quieten some warnings\n"));
8184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8185 fprintf (stream, _("\
a38cf1db 8186 -s ignored\n"));
b3b91714 8187#endif
321098a5
L		 8188#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8189 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8190 fprintf (stream, _("\
8191 --32/--64 generate 32bit/64bit code\n"));
8192#endif
b3b91714
AM		 8193#ifdef SVR4_COMMENT_CHARS
8194 fprintf (stream, _("\
8195 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8196#else
8197 fprintf (stream, _("\
b3b91714 8198 --divide ignored\n"));
4cc782b5 8199#endif
9103f4f4 8200 fprintf (stream, _("\
6305a203 8201 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8202 generate code for CPU and EXTENSION, CPU is one of:\n"));
8203 show_arch (stream, 0);
8204 fprintf (stream, _("\
8205 EXTENSION is combination of:\n"));
8206 show_arch (stream, 1);
6305a203 8207 fprintf (stream, _("\
8a2c8fef
L		 8208 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8209 show_arch (stream, 0);
ba104c83 8210 fprintf (stream, _("\
c0f3af97
L		 8211 -msse2avx encode SSE instructions with VEX prefix\n"));
8212 fprintf (stream, _("\
daf50ae7
L		 8213 -msse-check=[none|error|warning]\n\
8214 check SSE instructions\n"));
8215 fprintf (stream, _("\
ba104c83
L		 8216 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8217 fprintf (stream, _("\
8218 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8219 fprintf (stream, _("\
8220 -mindex-reg support pseudo index registers\n"));
8221 fprintf (stream, _("\
8222 -mnaked-reg don't require `%%' prefix for registers\n"));
8223 fprintf (stream, _("\
8224 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8225}
8226
3e73aa7c 8227#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8228 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8229 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8230
8231/* Pick the target format to use. */
8232
47926f60 8233const char *
e3bb37b5 8234i386_target_format (void)
252b5132 8235{
3e73aa7c 8236 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8237 {
8238 set_code_flag (CODE_64BIT);
0dfbf9d7 8239 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8240 {
8241 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8242 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8243 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8244 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8245 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8246 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8247 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8248 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8249 cpu_arch_isa_flags.bitfield.cpusse = 1;
8250 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8251 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8252 }
0dfbf9d7 8253 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8254 {
8255 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8256 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8257 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8258 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8259 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8260 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8261 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8262 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8263 cpu_arch_tune_flags.bitfield.cpusse = 1;
8264 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8265 }
9103f4f4 8266 }
3e73aa7c 8267 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8268 {
8269 set_code_flag (CODE_32BIT);
0dfbf9d7 8270 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8271 {
8272 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8273 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8274 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8275 }
0dfbf9d7 8276 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8277 {
8278 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8279 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8280 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8281 }
9103f4f4 8282 }
3e73aa7c
JH		 8283 else
8284 as_fatal (_("Unknown architecture"));
252b5132
RH		 8285 switch (OUTPUT_FLAVOR)
8286 {
9384f2ff 8287#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8288 case bfd_target_aout_flavour:
47926f60 8289 return AOUT_TARGET_FORMAT;
4c63da97 8290#endif
9384f2ff
AM		 8291#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8292# if defined (TE_PE) || defined (TE_PEP)
8293 case bfd_target_coff_flavour:
8294 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8295# elif defined (TE_GO32)
0561d57c
JK		 8296 case bfd_target_coff_flavour:
8297 return "coff-go32";
9384f2ff 8298# else
252b5132
RH		 8299 case bfd_target_coff_flavour:
8300 return "coff-i386";
9384f2ff 8301# endif
4c63da97 8302#endif
3e73aa7c 8303#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8304 case bfd_target_elf_flavour:
3e73aa7c 8305 {
e5cb08ac 8306 if (flag_code == CODE_64BIT)
4fa24527
JB		 8307 {
8308 object_64bit = 1;
8309 use_rela_relocations = 1;
8310 }
3632d14b 8311 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8312 {
8313 if (flag_code != CODE_64BIT)
8314 as_fatal (_("Intel L1OM is 64bit only"));
8315 return ELF_TARGET_L1OM_FORMAT;
8316 }
8317 else
8318 return (flag_code == CODE_64BIT
8319 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8320 }
e57f8c65
TG		 8321#endif
8322#if defined (OBJ_MACH_O)
8323 case bfd_target_mach_o_flavour:
8324 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8325#endif
252b5132
RH		 8326 default:
8327 abort ();
8328 return NULL;
8329 }
8330}
8331
47926f60 8332#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8333
8334#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8335void
8336i386_elf_emit_arch_note (void)
a847613f 8337{
718ddfc0 8338 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8339 {
8340 char *p;
8341 asection *seg = now_seg;
8342 subsegT subseg = now_subseg;
8343 Elf_Internal_Note i_note;
8344 Elf_External_Note e_note;
8345 asection *note_secp;
8346 int len;
8347
8348 /* Create the .note section. */
8349 note_secp = subseg_new (".note", 0);
8350 bfd_set_section_flags (stdoutput,
8351 note_secp,
8352 SEC_HAS_CONTENTS | SEC_READONLY);
8353
8354 /* Process the arch string. */
8355 len = strlen (cpu_arch_name);
8356
8357 i_note.namesz = len + 1;
8358 i_note.descsz = 0;
8359 i_note.type = NT_ARCH;
8360 p = frag_more (sizeof (e_note.namesz));
8361 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8362 p = frag_more (sizeof (e_note.descsz));
8363 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8364 p = frag_more (sizeof (e_note.type));
8365 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8366 p = frag_more (len + 1);
8367 strcpy (p, cpu_arch_name);
8368
8369 frag_align (2, 0, 0);
8370
8371 subseg_set (seg, subseg);
8372 }
8373}
8374#endif
252b5132 8375\f
252b5132
RH		 8376symbolS *
8377md_undefined_symbol (name)
8378 char *name;
8379{
18dc2407
ILT		 8380 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8381 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8382 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8383 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8384 {
8385 if (!GOT_symbol)
8386 {
8387 if (symbol_find (name))
8388 as_bad (_("GOT already in symbol table"));
8389 GOT_symbol = symbol_new (name, undefined_section,
8390 (valueT) 0, &zero_address_frag);
8391 };
8392 return GOT_symbol;
8393 }
252b5132
RH		 8394 return 0;
8395}
8396
8397/* Round up a section size to the appropriate boundary. */
47926f60 8398
252b5132
RH		 8399valueT
8400md_section_align (segment, size)
ab9da554 8401 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8402 valueT size;
8403{
4c63da97
AM		 8404#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8405 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8406 {
8407 /* For a.out, force the section size to be aligned. If we don't do
8408 this, BFD will align it for us, but it will not write out the
8409 final bytes of the section. This may be a bug in BFD, but it is
8410 easier to fix it here since that is how the other a.out targets
8411 work. */
8412 int align;
8413
8414 align = bfd_get_section_alignment (stdoutput, segment);
8415 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8416 }
252b5132
RH		 8417#endif
8418
8419 return size;
8420}
8421
8422/* On the i386, PC-relative offsets are relative to the start of the
8423 next instruction. That is, the address of the offset, plus its
8424 size, since the offset is always the last part of the insn. */
8425
8426long
e3bb37b5 8427md_pcrel_from (fixS *fixP)
252b5132
RH		 8428{
8429 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8430}
8431
8432#ifndef I386COFF
8433
8434static void
e3bb37b5 8435s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8436{
29b0f896 8437 int temp;
252b5132 8438
8a75718c
JB		 8439#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8440 if (IS_ELF)
8441 obj_elf_section_change_hook ();
8442#endif
252b5132
RH		 8443 temp = get_absolute_expression ();
8444 subseg_set (bss_section, (subsegT) temp);
8445 demand_empty_rest_of_line ();
8446}
8447
8448#endif
8449
252b5132 8450void
e3bb37b5 8451i386_validate_fix (fixS *fixp)
252b5132
RH		 8452{
8453 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8454 {
23df1078
JH		 8455 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8456 {
4fa24527 8457 if (!object_64bit)
23df1078
JH		 8458 abort ();
8459 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8460 }
8461 else
8462 {
4fa24527 8463 if (!object_64bit)
d6ab8113
JB		 8464 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8465 else
8466 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8467 }
252b5132
RH		 8468 fixp->fx_subsy = 0;
8469 }
8470}
8471
252b5132
RH		 8472arelent *
8473tc_gen_reloc (section, fixp)
ab9da554 8474 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8475 fixS *fixp;
8476{
8477 arelent *rel;
8478 bfd_reloc_code_real_type code;
8479
8480 switch (fixp->fx_r_type)
8481 {
3e73aa7c
JH		 8482 case BFD_RELOC_X86_64_PLT32:
8483 case BFD_RELOC_X86_64_GOT32:
8484 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8485 case BFD_RELOC_386_PLT32:
8486 case BFD_RELOC_386_GOT32:
8487 case BFD_RELOC_386_GOTOFF:
8488 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8489 case BFD_RELOC_386_TLS_GD:
8490 case BFD_RELOC_386_TLS_LDM:
8491 case BFD_RELOC_386_TLS_LDO_32:
8492 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8493 case BFD_RELOC_386_TLS_IE:
8494 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8495 case BFD_RELOC_386_TLS_LE_32:
8496 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8497 case BFD_RELOC_386_TLS_GOTDESC:
8498 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8499 case BFD_RELOC_X86_64_TLSGD:
8500 case BFD_RELOC_X86_64_TLSLD:
8501 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8502 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8503 case BFD_RELOC_X86_64_GOTTPOFF:
8504 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8505 case BFD_RELOC_X86_64_TPOFF64:
8506 case BFD_RELOC_X86_64_GOTOFF64:
8507 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8508 case BFD_RELOC_X86_64_GOT64:
8509 case BFD_RELOC_X86_64_GOTPCREL64:
8510 case BFD_RELOC_X86_64_GOTPC64:
8511 case BFD_RELOC_X86_64_GOTPLT64:
8512 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8513 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8514 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8515 case BFD_RELOC_RVA:
8516 case BFD_RELOC_VTABLE_ENTRY:
8517 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8518#ifdef TE_PE
8519 case BFD_RELOC_32_SECREL:
8520#endif
252b5132
RH		 8521 code = fixp->fx_r_type;
8522 break;
dbbaec26
L		 8523 case BFD_RELOC_X86_64_32S:
8524 if (!fixp->fx_pcrel)
8525 {
8526 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8527 code = fixp->fx_r_type;
8528 break;
8529 }
252b5132 8530 default:
93382f6d 8531 if (fixp->fx_pcrel)
252b5132 8532 {
93382f6d
AM		 8533 switch (fixp->fx_size)
8534 {
8535 default:
b091f402
AM		 8536 as_bad_where (fixp->fx_file, fixp->fx_line,
8537 _("can not do %d byte pc-relative relocation"),
8538 fixp->fx_size);
93382f6d
AM		 8539 code = BFD_RELOC_32_PCREL;
8540 break;
8541 case 1: code = BFD_RELOC_8_PCREL; break;
8542 case 2: code = BFD_RELOC_16_PCREL; break;
8543 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8544#ifdef BFD64
8545 case 8: code = BFD_RELOC_64_PCREL; break;
8546#endif
93382f6d
AM		 8547 }
8548 }
8549 else
8550 {
8551 switch (fixp->fx_size)
8552 {
8553 default:
b091f402
AM		 8554 as_bad_where (fixp->fx_file, fixp->fx_line,
8555 _("can not do %d byte relocation"),
8556 fixp->fx_size);
93382f6d
AM		 8557 code = BFD_RELOC_32;
8558 break;
8559 case 1: code = BFD_RELOC_8; break;
8560 case 2: code = BFD_RELOC_16; break;
8561 case 4: code = BFD_RELOC_32; break;
937149dd 8562#ifdef BFD64
3e73aa7c 8563 case 8: code = BFD_RELOC_64; break;
937149dd 8564#endif
93382f6d 8565 }
252b5132
RH		 8566 }
8567 break;
8568 }
252b5132 8569
d182319b
JB		 8570 if ((code == BFD_RELOC_32
8571 || code == BFD_RELOC_32_PCREL
8572 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8573 && GOT_symbol
8574 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8575 {
4fa24527 8576 if (!object_64bit)
d6ab8113
JB		 8577 code = BFD_RELOC_386_GOTPC;
8578 else
8579 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8580 }
7b81dfbb
AJ		 8581 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8582 && GOT_symbol
8583 && fixp->fx_addsy == GOT_symbol)
8584 {
8585 code = BFD_RELOC_X86_64_GOTPC64;
8586 }
252b5132
RH		 8587
8588 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8589 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8590 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8591
8592 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8593
3e73aa7c
JH		 8594 if (!use_rela_relocations)
8595 {
8596 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8597 vtable entry to be used in the relocation's section offset. */
8598 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8599 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8600#if defined (OBJ_COFF) && defined (TE_PE)
8601 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8602 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8603 else
8604#endif
c6682705 8605 rel->addend = 0;
3e73aa7c
JH		 8606 }
8607 /* Use the rela in 64bit mode. */
252b5132 8608 else
3e73aa7c 8609 {
062cd5e7
AS		 8610 if (!fixp->fx_pcrel)
8611 rel->addend = fixp->fx_offset;
8612 else
8613 switch (code)
8614 {
8615 case BFD_RELOC_X86_64_PLT32:
8616 case BFD_RELOC_X86_64_GOT32:
8617 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8618 case BFD_RELOC_X86_64_TLSGD:
8619 case BFD_RELOC_X86_64_TLSLD:
8620 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8621 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8622 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8623 rel->addend = fixp->fx_offset - fixp->fx_size;
8624 break;
8625 default:
8626 rel->addend = (section->vma
8627 - fixp->fx_size
8628 + fixp->fx_addnumber
8629 + md_pcrel_from (fixp));
8630 break;
8631 }
3e73aa7c
JH		 8632 }
8633
252b5132
RH		 8634 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8635 if (rel->howto == NULL)
8636 {
8637 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8638 _("cannot represent relocation type %s"),
252b5132
RH		 8639 bfd_get_reloc_code_name (code));
8640 /* Set howto to a garbage value so that we can keep going. */
8641 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8642 gas_assert (rel->howto != NULL);
252b5132
RH		 8643 }
8644
8645 return rel;
8646}
8647
ee86248c 8648#include "tc-i386-intel.c"
54cfded0 8649
a60de03c
JB		 8650void
8651tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8652{
a60de03c
JB		 8653 int saved_naked_reg;
8654 char saved_register_dot;
54cfded0 8655
a60de03c
JB		 8656 saved_naked_reg = allow_naked_reg;
8657 allow_naked_reg = 1;
8658 saved_register_dot = register_chars['.'];
8659 register_chars['.'] = '.';
8660 allow_pseudo_reg = 1;
8661 expression_and_evaluate (exp);
8662 allow_pseudo_reg = 0;
8663 register_chars['.'] = saved_register_dot;
8664 allow_naked_reg = saved_naked_reg;
8665
8666 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8667 {
a60de03c
JB		 8668 if ((addressT) exp->X_add_number < i386_regtab_size)
8669 {
8670 exp->X_op = O_constant;
8671 exp->X_add_number = i386_regtab[exp->X_add_number]
8672 .dw2_regnum[flag_code >> 1];
8673 }
8674 else
8675 exp->X_op = O_illegal;
54cfded0 8676 }
54cfded0
AM		 8677}
8678
8679void
8680tc_x86_frame_initial_instructions (void)
8681{
a60de03c
JB		 8682 static unsigned int sp_regno[2];
8683
8684 if (!sp_regno[flag_code >> 1])
8685 {
8686 char *saved_input = input_line_pointer;
8687 char sp[][4] = {"esp", "rsp"};
8688 expressionS exp;
a4447b93 8689
a60de03c
JB		 8690 input_line_pointer = sp[flag_code >> 1];
8691 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8692 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8693 sp_regno[flag_code >> 1] = exp.X_add_number;
8694 input_line_pointer = saved_input;
8695 }
a4447b93 8696
a60de03c 8697 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8698 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8699}
d2b2c203
DJ		 8700
8701int
8702i386_elf_section_type (const char *str, size_t len)
8703{
8704 if (flag_code == CODE_64BIT
8705 && len == sizeof ("unwind") - 1
8706 && strncmp (str, "unwind", 6) == 0)
8707 return SHT_X86_64_UNWIND;
8708
8709 return -1;
8710}
bb41ade5 8711
ad5fec3b
EB		 8712#ifdef TE_SOLARIS
8713void
8714i386_solaris_fix_up_eh_frame (segT sec)
8715{
8716 if (flag_code == CODE_64BIT)
8717 elf_section_type (sec) = SHT_X86_64_UNWIND;
8718}
8719#endif
8720
bb41ade5
AM		 8721#ifdef TE_PE
8722void
8723tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8724{
91d6fa6a 8725 expressionS exp;
bb41ade5 8726
91d6fa6a
NC		 8727 exp.X_op = O_secrel;
8728 exp.X_add_symbol = symbol;
8729 exp.X_add_number = 0;
8730 emit_expr (&exp, size);
bb41ade5
AM		 8731}
8732#endif
3b22753a
L		 8733
8734#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8735/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8736
01e1a5bc 8737bfd_vma
3b22753a
L		 8738x86_64_section_letter (int letter, char **ptr_msg)
8739{
8740 if (flag_code == CODE_64BIT)
8741 {
8742 if (letter == 'l')
8743 return SHF_X86_64_LARGE;
8744
8745 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8746 }
3b22753a 8747 else
64e74474 8748 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8749 return -1;
8750}
8751
01e1a5bc 8752bfd_vma
3b22753a
L		 8753x86_64_section_word (char *str, size_t len)
8754{
8620418b 8755 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8756 return SHF_X86_64_LARGE;
8757
8758 return -1;
8759}
8760
8761static void
8762handle_large_common (int small ATTRIBUTE_UNUSED)
8763{
8764 if (flag_code != CODE_64BIT)
8765 {
8766 s_comm_internal (0, elf_common_parse);
8767 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8768 }
8769 else
8770 {
8771 static segT lbss_section;
8772 asection *saved_com_section_ptr = elf_com_section_ptr;
8773 asection *saved_bss_section = bss_section;
8774
8775 if (lbss_section == NULL)
8776 {
8777 flagword applicable;
8778 segT seg = now_seg;
8779 subsegT subseg = now_subseg;
8780
8781 /* The .lbss section is for local .largecomm symbols. */
8782 lbss_section = subseg_new (".lbss", 0);
8783 applicable = bfd_applicable_section_flags (stdoutput);
8784 bfd_set_section_flags (stdoutput, lbss_section,
8785 applicable & SEC_ALLOC);
8786 seg_info (lbss_section)->bss = 1;
8787
8788 subseg_set (seg, subseg);
8789 }
8790
8791 elf_com_section_ptr = &_bfd_elf_large_com_section;
8792 bss_section = lbss_section;
8793
8794 s_comm_internal (0, elf_common_parse);
8795
8796 elf_com_section_ptr = saved_com_section_ptr;
8797 bss_section = saved_bss_section;
8798 }
8799}
8800#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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