Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
4c63da97 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
252b5132 RH |
3 | Free Software Foundation. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
27 | */ | |
28 | ||
29 | #include <ctype.h> | |
30 | ||
31 | #include "as.h" | |
32 | #include "subsegs.h" | |
33 | #include "opcode/i386.h" | |
34 | ||
252b5132 RH |
35 | #ifndef REGISTER_WARNINGS |
36 | #define REGISTER_WARNINGS 1 | |
37 | #endif | |
38 | ||
c3332e24 | 39 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 40 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
41 | #endif |
42 | ||
252b5132 RH |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
51 | #define true 1 | |
52 | #define false 0 | |
53 | ||
54 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
55 | static int fits_in_signed_byte PARAMS ((offsetT)); |
56 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
57 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
58 | static int fits_in_signed_word PARAMS ((offsetT)); | |
59 | static int smallest_imm_type PARAMS ((offsetT)); | |
60 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 RH |
61 | static int add_prefix PARAMS ((unsigned int)); |
62 | static void set_16bit_code_flag PARAMS ((int)); | |
eecb386c | 63 | static void set_16bit_gcc_code_flag PARAMS((int)); |
252b5132 | 64 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 65 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
66 | |
67 | #ifdef BFD_ASSEMBLER | |
68 | static bfd_reloc_code_real_type reloc | |
69 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
70 | #endif | |
71 | ||
72 | /* 'md_assemble ()' gathers together information and puts it into a | |
73 | i386_insn. */ | |
74 | ||
520dc8e8 AM |
75 | union i386_op |
76 | { | |
77 | expressionS *disps; | |
78 | expressionS *imms; | |
79 | const reg_entry *regs; | |
80 | }; | |
81 | ||
252b5132 RH |
82 | struct _i386_insn |
83 | { | |
84 | /* TM holds the template for the insn were currently assembling. */ | |
85 | template tm; | |
86 | ||
87 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
88 | (e.g. 'l' for 'movl') */ | |
89 | char suffix; | |
90 | ||
252b5132 RH |
91 | /* OPERANDS gives the number of given operands. */ |
92 | unsigned int operands; | |
93 | ||
94 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
95 | of given register, displacement, memory operands and immediate | |
96 | operands. */ | |
97 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; | |
98 | ||
99 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 100 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
101 | unsigned int types[MAX_OPERANDS]; |
102 | ||
520dc8e8 AM |
103 | /* Displacement expression, immediate expression, or register for each |
104 | operand. */ | |
105 | union i386_op op[MAX_OPERANDS]; | |
252b5132 RH |
106 | |
107 | /* Relocation type for operand */ | |
108 | #ifdef BFD_ASSEMBLER | |
109 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
110 | #else | |
111 | int disp_reloc[MAX_OPERANDS]; | |
112 | #endif | |
113 | ||
252b5132 RH |
114 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
115 | the base index byte below. */ | |
116 | const reg_entry *base_reg; | |
117 | const reg_entry *index_reg; | |
118 | unsigned int log2_scale_factor; | |
119 | ||
120 | /* SEG gives the seg_entries of this insn. They are zero unless | |
121 | explicit segment overrides are given. */ | |
122 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
123 | ||
124 | /* PREFIX holds all the given prefix opcodes (usually null). | |
125 | PREFIXES is the number of prefix opcodes. */ | |
126 | unsigned int prefixes; | |
127 | unsigned char prefix[MAX_PREFIXES]; | |
128 | ||
129 | /* RM and SIB are the modrm byte and the sib byte where the | |
130 | addressing modes of this insn are encoded. */ | |
131 | ||
132 | modrm_byte rm; | |
133 | sib_byte sib; | |
134 | }; | |
135 | ||
136 | typedef struct _i386_insn i386_insn; | |
137 | ||
138 | /* List of chars besides those in app.c:symbol_chars that can start an | |
139 | operand. Used to prevent the scrubber eating vital white-space. */ | |
140 | #ifdef LEX_AT | |
141 | const char extra_symbol_chars[] = "*%-(@"; | |
142 | #else | |
143 | const char extra_symbol_chars[] = "*%-("; | |
144 | #endif | |
145 | ||
146 | /* This array holds the chars that always start a comment. If the | |
147 | pre-processor is disabled, these aren't very useful */ | |
d9b7d820 | 148 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
149 | /* Putting '/' here makes it impossible to use the divide operator. |
150 | However, we need it for compatibility with SVR4 systems. */ | |
151 | const char comment_chars[] = "#/"; | |
152 | #define PREFIX_SEPARATOR '\\' | |
153 | #else | |
154 | const char comment_chars[] = "#"; | |
155 | #define PREFIX_SEPARATOR '/' | |
156 | #endif | |
157 | ||
158 | /* This array holds the chars that only start a comment at the beginning of | |
159 | a line. If the line seems to have the form '# 123 filename' | |
160 | .line and .file directives will appear in the pre-processed output */ | |
161 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
162 | first line of the input file. This is because the compiler outputs | |
163 | #NO_APP at the beginning of its output. */ | |
164 | /* Also note that comments started like this one will always work if | |
165 | '/' isn't otherwise defined. */ | |
d9b7d820 | 166 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
167 | const char line_comment_chars[] = ""; |
168 | #else | |
169 | const char line_comment_chars[] = "/"; | |
170 | #endif | |
171 | ||
172 | const char line_separator_chars[] = ""; | |
173 | ||
174 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
175 | const char EXP_CHARS[] = "eE"; | |
176 | ||
177 | /* Chars that mean this number is a floating point constant */ | |
178 | /* As in 0f12.456 */ | |
179 | /* or 0d1.2345e12 */ | |
180 | const char FLT_CHARS[] = "fFdDxX"; | |
181 | ||
182 | /* tables for lexical analysis */ | |
183 | static char mnemonic_chars[256]; | |
184 | static char register_chars[256]; | |
185 | static char operand_chars[256]; | |
186 | static char identifier_chars[256]; | |
187 | static char digit_chars[256]; | |
188 | ||
189 | /* lexical macros */ | |
190 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) | |
191 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
192 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
193 | #define is_space_char(x) ((x) == ' ') | |
194 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
195 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
196 | ||
197 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
198 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; | |
199 | ||
200 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
201 | effect this we maintain a stack of saved characters that we've smashed | |
202 | with '\0's (indicating end of strings for various sub-fields of the | |
203 | assembler instruction). */ | |
204 | static char save_stack[32]; | |
205 | static char *save_stack_p; /* stack pointer */ | |
206 | #define END_STRING_AND_SAVE(s) \ | |
207 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
208 | #define RESTORE_END_STRING(s) \ | |
209 | do { *(s) = *--save_stack_p; } while (0) | |
210 | ||
211 | /* The instruction we're assembling. */ | |
212 | static i386_insn i; | |
213 | ||
214 | /* Possible templates for current insn. */ | |
215 | static const templates *current_templates; | |
216 | ||
217 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ | |
218 | static expressionS disp_expressions[2], im_expressions[2]; | |
219 | ||
e413e4e9 | 220 | static int this_operand; /* Current operand we are working on. */ |
252b5132 | 221 | |
e413e4e9 AM |
222 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, |
223 | 0 if 32-bit. */ | |
252b5132 | 224 | |
e413e4e9 | 225 | static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax. */ |
252b5132 | 226 | |
e413e4e9 | 227 | static int allow_naked_reg = 0; /* 1 if register prefix % not required */ |
252b5132 | 228 | |
eecb386c AM |
229 | static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l |
230 | suffix to call, ret, enter, leave, push, | |
add0c677 AM |
231 | and pop instructions so that gcc has the |
232 | same stack frame as in 32 bit mode. */ | |
eecb386c | 233 | |
a38cf1db AM |
234 | static int quiet_warnings = 0; /* Non-zero to quieten some warnings. */ |
235 | ||
236 | static const char *cpu_arch_name = NULL; /* cpu name */ | |
237 | ||
238 | static unsigned int cpu_arch_flags = 0; /* cpu feature flags */ | |
239 | ||
252b5132 RH |
240 | /* Interface to relax_segment. |
241 | There are 2 relax states for 386 jump insns: one for conditional & | |
a217f122 AM |
242 | one for unconditional jumps. This is because these two types of |
243 | jumps add different sizes to frags when we're figuring out what | |
252b5132 RH |
244 | sort of jump to choose to reach a given label. */ |
245 | ||
246 | /* types */ | |
247 | #define COND_JUMP 1 /* conditional jump */ | |
248 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
249 | /* sizes */ | |
250 | #define CODE16 1 | |
251 | #define SMALL 0 | |
252 | #define SMALL16 (SMALL|CODE16) | |
253 | #define BIG 2 | |
254 | #define BIG16 (BIG|CODE16) | |
255 | ||
256 | #ifndef INLINE | |
257 | #ifdef __GNUC__ | |
258 | #define INLINE __inline__ | |
259 | #else | |
260 | #define INLINE | |
261 | #endif | |
262 | #endif | |
263 | ||
264 | #define ENCODE_RELAX_STATE(type,size) \ | |
265 | ((relax_substateT)((type<<2) | (size))) | |
266 | #define SIZE_FROM_RELAX_STATE(s) \ | |
267 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) | |
268 | ||
269 | /* This table is used by relax_frag to promote short jumps to long | |
270 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
271 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
272 | don't allow a short jump in a 32 bit code segment to be promoted to | |
273 | a 16 bit offset jump because it's slower (requires data size | |
274 | prefix), and doesn't work, unless the destination is in the bottom | |
275 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
276 | ||
277 | const relax_typeS md_relax_table[] = | |
278 | { | |
24eab124 AM |
279 | /* The fields are: |
280 | 1) most positive reach of this state, | |
281 | 2) most negative reach of this state, | |
282 | 3) how many bytes this mode will add to the size of the current frag | |
283 | 4) which index into the table to try if we can't fit into this one. | |
284 | */ | |
252b5132 RH |
285 | {1, 1, 0, 0}, |
286 | {1, 1, 0, 0}, | |
287 | {1, 1, 0, 0}, | |
288 | {1, 1, 0, 0}, | |
289 | ||
290 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
291 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
292 | /* dword conditionals adds 4 bytes to frag: | |
293 | 1 extra opcode byte, 3 extra displacement bytes. */ | |
294 | {0, 0, 4, 0}, | |
295 | /* word conditionals add 2 bytes to frag: | |
296 | 1 extra opcode byte, 1 extra displacement byte. */ | |
297 | {0, 0, 2, 0}, | |
298 | ||
299 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, | |
300 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
301 | /* dword jmp adds 3 bytes to frag: | |
302 | 0 extra opcode bytes, 3 extra displacement bytes. */ | |
303 | {0, 0, 3, 0}, | |
304 | /* word jmp adds 1 byte to frag: | |
305 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
306 | {0, 0, 1, 0} | |
307 | ||
308 | }; | |
309 | ||
e413e4e9 AM |
310 | static const arch_entry cpu_arch[] = { |
311 | {"i8086", Cpu086 }, | |
312 | {"i186", Cpu086|Cpu186 }, | |
313 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
314 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
315 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
316 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
317 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
318 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
319 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
320 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, | |
321 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, | |
322 | {NULL, 0 } | |
323 | }; | |
324 | ||
252b5132 RH |
325 | |
326 | void | |
327 | i386_align_code (fragP, count) | |
328 | fragS *fragP; | |
329 | int count; | |
330 | { | |
331 | /* Various efficient no-op patterns for aligning code labels. */ | |
332 | /* Note: Don't try to assemble the instructions in the comments. */ | |
333 | /* 0L and 0w are not legal */ | |
334 | static const char f32_1[] = | |
335 | {0x90}; /* nop */ | |
336 | static const char f32_2[] = | |
337 | {0x89,0xf6}; /* movl %esi,%esi */ | |
338 | static const char f32_3[] = | |
339 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
340 | static const char f32_4[] = | |
341 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
342 | static const char f32_5[] = | |
343 | {0x90, /* nop */ | |
344 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
345 | static const char f32_6[] = | |
346 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
347 | static const char f32_7[] = | |
348 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
349 | static const char f32_8[] = | |
350 | {0x90, /* nop */ | |
351 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
352 | static const char f32_9[] = | |
353 | {0x89,0xf6, /* movl %esi,%esi */ | |
354 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
355 | static const char f32_10[] = | |
356 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
357 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
358 | static const char f32_11[] = | |
359 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
360 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
361 | static const char f32_12[] = | |
362 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
363 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
364 | static const char f32_13[] = | |
365 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
366 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
367 | static const char f32_14[] = | |
368 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
369 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
370 | static const char f32_15[] = | |
371 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
372 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
373 | static const char f16_3[] = |
374 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
375 | static const char f16_4[] = |
376 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
377 | static const char f16_5[] = | |
378 | {0x90, /* nop */ | |
379 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
380 | static const char f16_6[] = | |
381 | {0x89,0xf6, /* mov %si,%si */ | |
382 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
383 | static const char f16_7[] = | |
384 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
385 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
386 | static const char f16_8[] = | |
387 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
388 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
389 | static const char *const f32_patt[] = { | |
390 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
391 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
392 | }; | |
393 | static const char *const f16_patt[] = { | |
c3332e24 | 394 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
395 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
396 | }; | |
397 | ||
398 | if (count > 0 && count <= 15) | |
399 | { | |
400 | if (flag_16bit_code) | |
401 | { | |
402 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
403 | f16_patt[count - 1], count); | |
404 | if (count > 8) /* adjust jump offset */ | |
405 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
406 | } | |
407 | else | |
408 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
409 | f32_patt[count - 1], count); | |
410 | fragP->fr_var = count; | |
411 | } | |
412 | } | |
413 | ||
414 | static char *output_invalid PARAMS ((int c)); | |
415 | static int i386_operand PARAMS ((char *operand_string)); | |
416 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
417 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
418 | char **end_op)); | |
419 | ||
420 | #ifndef I386COFF | |
421 | static void s_bss PARAMS ((int)); | |
422 | #endif | |
423 | ||
424 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
425 | ||
426 | static INLINE unsigned int | |
427 | mode_from_disp_size (t) | |
428 | unsigned int t; | |
429 | { | |
430 | return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0; | |
431 | } | |
432 | ||
433 | static INLINE int | |
434 | fits_in_signed_byte (num) | |
847f7ad4 | 435 | offsetT num; |
252b5132 RH |
436 | { |
437 | return (num >= -128) && (num <= 127); | |
438 | } /* fits_in_signed_byte() */ | |
439 | ||
440 | static INLINE int | |
441 | fits_in_unsigned_byte (num) | |
847f7ad4 | 442 | offsetT num; |
252b5132 RH |
443 | { |
444 | return (num & 0xff) == num; | |
445 | } /* fits_in_unsigned_byte() */ | |
446 | ||
447 | static INLINE int | |
448 | fits_in_unsigned_word (num) | |
847f7ad4 | 449 | offsetT num; |
252b5132 RH |
450 | { |
451 | return (num & 0xffff) == num; | |
452 | } /* fits_in_unsigned_word() */ | |
453 | ||
454 | static INLINE int | |
455 | fits_in_signed_word (num) | |
847f7ad4 | 456 | offsetT num; |
252b5132 RH |
457 | { |
458 | return (-32768 <= num) && (num <= 32767); | |
459 | } /* fits_in_signed_word() */ | |
460 | ||
461 | static int | |
462 | smallest_imm_type (num) | |
847f7ad4 | 463 | offsetT num; |
252b5132 | 464 | { |
e413e4e9 AM |
465 | if (cpu_arch_flags != 0 |
466 | && cpu_arch_flags != (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486)) | |
467 | { | |
468 | /* This code is disabled on the 486 because all the Imm1 forms | |
469 | in the opcode table are slower on the i486. They're the | |
470 | versions with the implicitly specified single-position | |
471 | displacement, which has another syntax if you really want to | |
472 | use that form. */ | |
473 | if (num == 1) | |
474 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
475 | } | |
252b5132 RH |
476 | return (fits_in_signed_byte (num) |
477 | ? (Imm8S | Imm8 | Imm16 | Imm32) | |
478 | : fits_in_unsigned_byte (num) | |
479 | ? (Imm8 | Imm16 | Imm32) | |
480 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
481 | ? (Imm16 | Imm32) | |
482 | : (Imm32)); | |
483 | } /* smallest_imm_type() */ | |
484 | ||
847f7ad4 AM |
485 | static offsetT |
486 | offset_in_range (val, size) | |
487 | offsetT val; | |
488 | int size; | |
489 | { | |
508866be | 490 | addressT mask; |
ba2adb93 | 491 | |
847f7ad4 AM |
492 | switch (size) |
493 | { | |
508866be L |
494 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
495 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 496 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
847f7ad4 AM |
497 | default: abort(); |
498 | } | |
499 | ||
ba2adb93 | 500 | /* If BFD64, sign extend val. */ |
3b0ec529 | 501 | if ((val & ~ (((addressT) 2 << 31) - 1)) == 0) |
508866be | 502 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
ba2adb93 | 503 | |
847f7ad4 AM |
504 | if ((val & ~ mask) != 0 && (val & ~ mask) != ~ mask) |
505 | { | |
506 | char buf1[40], buf2[40]; | |
507 | ||
508 | sprint_value (buf1, val); | |
509 | sprint_value (buf2, val & mask); | |
510 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
511 | } | |
512 | return val & mask; | |
513 | } | |
514 | ||
252b5132 RH |
515 | /* Returns 0 if attempting to add a prefix where one from the same |
516 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
517 | added. */ | |
518 | static int | |
519 | add_prefix (prefix) | |
520 | unsigned int prefix; | |
521 | { | |
522 | int ret = 1; | |
523 | int q; | |
524 | ||
525 | switch (prefix) | |
526 | { | |
527 | default: | |
528 | abort (); | |
529 | ||
530 | case CS_PREFIX_OPCODE: | |
531 | case DS_PREFIX_OPCODE: | |
532 | case ES_PREFIX_OPCODE: | |
533 | case FS_PREFIX_OPCODE: | |
534 | case GS_PREFIX_OPCODE: | |
535 | case SS_PREFIX_OPCODE: | |
536 | q = SEG_PREFIX; | |
537 | break; | |
538 | ||
539 | case REPNE_PREFIX_OPCODE: | |
540 | case REPE_PREFIX_OPCODE: | |
541 | ret = 2; | |
542 | /* fall thru */ | |
543 | case LOCK_PREFIX_OPCODE: | |
544 | q = LOCKREP_PREFIX; | |
545 | break; | |
546 | ||
547 | case FWAIT_OPCODE: | |
548 | q = WAIT_PREFIX; | |
549 | break; | |
550 | ||
551 | case ADDR_PREFIX_OPCODE: | |
552 | q = ADDR_PREFIX; | |
553 | break; | |
554 | ||
555 | case DATA_PREFIX_OPCODE: | |
556 | q = DATA_PREFIX; | |
557 | break; | |
558 | } | |
559 | ||
560 | if (i.prefix[q]) | |
561 | { | |
562 | as_bad (_("same type of prefix used twice")); | |
563 | return 0; | |
564 | } | |
565 | ||
566 | i.prefixes += 1; | |
567 | i.prefix[q] = prefix; | |
568 | return ret; | |
569 | } | |
570 | ||
571 | static void | |
572 | set_16bit_code_flag (new_16bit_code_flag) | |
eecb386c AM |
573 | int new_16bit_code_flag; |
574 | { | |
575 | flag_16bit_code = new_16bit_code_flag; | |
576 | stackop_size = '\0'; | |
577 | } | |
578 | ||
579 | static void | |
580 | set_16bit_gcc_code_flag (new_16bit_code_flag) | |
581 | int new_16bit_code_flag; | |
252b5132 RH |
582 | { |
583 | flag_16bit_code = new_16bit_code_flag; | |
eecb386c | 584 | stackop_size = new_16bit_code_flag ? 'l' : '\0'; |
252b5132 RH |
585 | } |
586 | ||
587 | static void | |
588 | set_intel_syntax (syntax_flag) | |
eecb386c | 589 | int syntax_flag; |
252b5132 RH |
590 | { |
591 | /* Find out if register prefixing is specified. */ | |
592 | int ask_naked_reg = 0; | |
593 | ||
594 | SKIP_WHITESPACE (); | |
595 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
596 | { | |
597 | char *string = input_line_pointer; | |
598 | int e = get_symbol_end (); | |
599 | ||
600 | if (strcmp(string, "prefix") == 0) | |
601 | ask_naked_reg = 1; | |
602 | else if (strcmp(string, "noprefix") == 0) | |
603 | ask_naked_reg = -1; | |
604 | else | |
d0b47220 | 605 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
606 | *input_line_pointer = e; |
607 | } | |
608 | demand_empty_rest_of_line (); | |
c3332e24 | 609 | |
252b5132 RH |
610 | intel_syntax = syntax_flag; |
611 | ||
612 | if (ask_naked_reg == 0) | |
613 | { | |
614 | #ifdef BFD_ASSEMBLER | |
615 | allow_naked_reg = (intel_syntax | |
24eab124 | 616 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 RH |
617 | #else |
618 | allow_naked_reg = 0; /* conservative default */ | |
619 | #endif | |
620 | } | |
621 | else | |
622 | allow_naked_reg = (ask_naked_reg < 0); | |
623 | } | |
624 | ||
e413e4e9 AM |
625 | static void |
626 | set_cpu_arch (dummy) | |
627 | int dummy ATTRIBUTE_UNUSED; | |
628 | { | |
629 | SKIP_WHITESPACE(); | |
630 | ||
631 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
632 | { | |
633 | char *string = input_line_pointer; | |
634 | int e = get_symbol_end (); | |
635 | int i; | |
636 | ||
637 | for (i = 0; cpu_arch[i].name; i++) | |
638 | { | |
639 | if (strcmp (string, cpu_arch[i].name) == 0) | |
640 | { | |
641 | cpu_arch_name = cpu_arch[i].name; | |
642 | cpu_arch_flags = cpu_arch[i].flags; | |
643 | break; | |
644 | } | |
645 | } | |
646 | if (!cpu_arch[i].name) | |
647 | as_bad (_("no such architecture: `%s'"), string); | |
648 | ||
649 | *input_line_pointer = e; | |
650 | } | |
651 | else | |
652 | as_bad (_("missing cpu architecture")); | |
653 | ||
654 | demand_empty_rest_of_line (); | |
655 | } | |
656 | ||
252b5132 RH |
657 | const pseudo_typeS md_pseudo_table[] = |
658 | { | |
252b5132 RH |
659 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
660 | {"align", s_align_bytes, 0}, | |
661 | #else | |
662 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
663 | #endif |
664 | {"arch", set_cpu_arch, 0}, | |
665 | #ifndef I386COFF | |
666 | {"bss", s_bss, 0}, | |
252b5132 RH |
667 | #endif |
668 | {"ffloat", float_cons, 'f'}, | |
669 | {"dfloat", float_cons, 'd'}, | |
670 | {"tfloat", float_cons, 'x'}, | |
671 | {"value", cons, 2}, | |
672 | {"noopt", s_ignore, 0}, | |
673 | {"optim", s_ignore, 0}, | |
eecb386c | 674 | {"code16gcc", set_16bit_gcc_code_flag, 1}, |
252b5132 RH |
675 | {"code16", set_16bit_code_flag, 1}, |
676 | {"code32", set_16bit_code_flag, 0}, | |
677 | {"intel_syntax", set_intel_syntax, 1}, | |
678 | {"att_syntax", set_intel_syntax, 0}, | |
679 | {0, 0, 0} | |
680 | }; | |
681 | ||
682 | /* for interface with expression () */ | |
683 | extern char *input_line_pointer; | |
684 | ||
685 | /* hash table for instruction mnemonic lookup */ | |
686 | static struct hash_control *op_hash; | |
687 | /* hash table for register lookup */ | |
688 | static struct hash_control *reg_hash; | |
689 | \f | |
690 | ||
691 | void | |
692 | md_begin () | |
693 | { | |
694 | const char *hash_err; | |
695 | ||
696 | /* initialize op_hash hash table */ | |
697 | op_hash = hash_new (); | |
698 | ||
699 | { | |
700 | register const template *optab; | |
701 | register templates *core_optab; | |
702 | ||
703 | optab = i386_optab; /* setup for loop */ | |
704 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
705 | core_optab->start = optab; | |
706 | ||
707 | while (1) | |
708 | { | |
709 | ++optab; | |
710 | if (optab->name == NULL | |
711 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
712 | { | |
713 | /* different name --> ship out current template list; | |
714 | add to hash table; & begin anew */ | |
715 | core_optab->end = optab; | |
716 | hash_err = hash_insert (op_hash, | |
717 | (optab - 1)->name, | |
718 | (PTR) core_optab); | |
719 | if (hash_err) | |
720 | { | |
721 | hash_error: | |
722 | as_fatal (_("Internal Error: Can't hash %s: %s"), | |
723 | (optab - 1)->name, | |
724 | hash_err); | |
725 | } | |
726 | if (optab->name == NULL) | |
727 | break; | |
728 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
729 | core_optab->start = optab; | |
730 | } | |
731 | } | |
732 | } | |
733 | ||
734 | /* initialize reg_hash hash table */ | |
735 | reg_hash = hash_new (); | |
736 | { | |
737 | register const reg_entry *regtab; | |
738 | ||
739 | for (regtab = i386_regtab; | |
740 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
741 | regtab++) | |
742 | { | |
743 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
744 | if (hash_err) | |
745 | goto hash_error; | |
746 | } | |
747 | } | |
748 | ||
749 | /* fill in lexical tables: mnemonic_chars, operand_chars. */ | |
750 | { | |
751 | register int c; | |
752 | register char *p; | |
753 | ||
754 | for (c = 0; c < 256; c++) | |
755 | { | |
756 | if (isdigit (c)) | |
757 | { | |
758 | digit_chars[c] = c; | |
759 | mnemonic_chars[c] = c; | |
760 | register_chars[c] = c; | |
761 | operand_chars[c] = c; | |
762 | } | |
763 | else if (islower (c)) | |
764 | { | |
765 | mnemonic_chars[c] = c; | |
766 | register_chars[c] = c; | |
767 | operand_chars[c] = c; | |
768 | } | |
769 | else if (isupper (c)) | |
770 | { | |
771 | mnemonic_chars[c] = tolower (c); | |
772 | register_chars[c] = mnemonic_chars[c]; | |
773 | operand_chars[c] = c; | |
774 | } | |
775 | ||
776 | if (isalpha (c) || isdigit (c)) | |
777 | identifier_chars[c] = c; | |
778 | else if (c >= 128) | |
779 | { | |
780 | identifier_chars[c] = c; | |
781 | operand_chars[c] = c; | |
782 | } | |
783 | } | |
784 | ||
785 | #ifdef LEX_AT | |
786 | identifier_chars['@'] = '@'; | |
787 | #endif | |
252b5132 RH |
788 | digit_chars['-'] = '-'; |
789 | identifier_chars['_'] = '_'; | |
790 | identifier_chars['.'] = '.'; | |
791 | ||
792 | for (p = operand_special_chars; *p != '\0'; p++) | |
793 | operand_chars[(unsigned char) *p] = *p; | |
794 | } | |
795 | ||
796 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
797 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
798 | { | |
799 | record_alignment (text_section, 2); | |
800 | record_alignment (data_section, 2); | |
801 | record_alignment (bss_section, 2); | |
802 | } | |
803 | #endif | |
804 | } | |
805 | ||
806 | void | |
807 | i386_print_statistics (file) | |
808 | FILE *file; | |
809 | { | |
810 | hash_print_statistics (file, "i386 opcode", op_hash); | |
811 | hash_print_statistics (file, "i386 register", reg_hash); | |
812 | } | |
813 | \f | |
814 | ||
815 | #ifdef DEBUG386 | |
816 | ||
817 | /* debugging routines for md_assemble */ | |
818 | static void pi PARAMS ((char *, i386_insn *)); | |
819 | static void pte PARAMS ((template *)); | |
820 | static void pt PARAMS ((unsigned int)); | |
821 | static void pe PARAMS ((expressionS *)); | |
822 | static void ps PARAMS ((symbolS *)); | |
823 | ||
824 | static void | |
825 | pi (line, x) | |
826 | char *line; | |
827 | i386_insn *x; | |
828 | { | |
829 | register template *p; | |
830 | int i; | |
831 | ||
832 | fprintf (stdout, "%s: template ", line); | |
833 | pte (&x->tm); | |
834 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
835 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
836 | fprintf (stdout, " base %x index %x scale %x\n", | |
837 | x->bi.base, x->bi.index, x->bi.scale); | |
838 | for (i = 0; i < x->operands; i++) | |
839 | { | |
840 | fprintf (stdout, " #%d: ", i + 1); | |
841 | pt (x->types[i]); | |
842 | fprintf (stdout, "\n"); | |
843 | if (x->types[i] | |
3f4438ab | 844 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 845 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 846 | if (x->types[i] & Imm) |
520dc8e8 | 847 | pe (x->op[i].imms); |
252b5132 | 848 | if (x->types[i] & Disp) |
520dc8e8 | 849 | pe (x->op[i].disps); |
252b5132 RH |
850 | } |
851 | } | |
852 | ||
853 | static void | |
854 | pte (t) | |
855 | template *t; | |
856 | { | |
857 | int i; | |
858 | fprintf (stdout, " %d operands ", t->operands); | |
859 | fprintf (stdout, "opcode %x ", | |
860 | t->base_opcode); | |
861 | if (t->extension_opcode != None) | |
862 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
863 | if (t->opcode_modifier & D) | |
864 | fprintf (stdout, "D"); | |
865 | if (t->opcode_modifier & W) | |
866 | fprintf (stdout, "W"); | |
867 | fprintf (stdout, "\n"); | |
868 | for (i = 0; i < t->operands; i++) | |
869 | { | |
870 | fprintf (stdout, " #%d type ", i + 1); | |
871 | pt (t->operand_types[i]); | |
872 | fprintf (stdout, "\n"); | |
873 | } | |
874 | } | |
875 | ||
876 | static void | |
877 | pe (e) | |
878 | expressionS *e; | |
879 | { | |
24eab124 | 880 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
881 | fprintf (stdout, " add_number %ld (%lx)\n", |
882 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
883 | if (e->X_add_symbol) |
884 | { | |
885 | fprintf (stdout, " add_symbol "); | |
886 | ps (e->X_add_symbol); | |
887 | fprintf (stdout, "\n"); | |
888 | } | |
889 | if (e->X_op_symbol) | |
890 | { | |
891 | fprintf (stdout, " op_symbol "); | |
892 | ps (e->X_op_symbol); | |
893 | fprintf (stdout, "\n"); | |
894 | } | |
895 | } | |
896 | ||
897 | static void | |
898 | ps (s) | |
899 | symbolS *s; | |
900 | { | |
901 | fprintf (stdout, "%s type %s%s", | |
902 | S_GET_NAME (s), | |
903 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
904 | segment_name (S_GET_SEGMENT (s))); | |
905 | } | |
906 | ||
907 | struct type_name | |
908 | { | |
909 | unsigned int mask; | |
910 | char *tname; | |
911 | } | |
912 | ||
913 | type_names[] = | |
914 | { | |
915 | { Reg8, "r8" }, | |
916 | { Reg16, "r16" }, | |
917 | { Reg32, "r32" }, | |
918 | { Imm8, "i8" }, | |
919 | { Imm8S, "i8s" }, | |
920 | { Imm16, "i16" }, | |
921 | { Imm32, "i32" }, | |
922 | { Imm1, "i1" }, | |
923 | { BaseIndex, "BaseIndex" }, | |
924 | { Disp8, "d8" }, | |
925 | { Disp16, "d16" }, | |
926 | { Disp32, "d32" }, | |
927 | { InOutPortReg, "InOutPortReg" }, | |
928 | { ShiftCount, "ShiftCount" }, | |
929 | { Control, "control reg" }, | |
930 | { Test, "test reg" }, | |
931 | { Debug, "debug reg" }, | |
932 | { FloatReg, "FReg" }, | |
933 | { FloatAcc, "FAcc" }, | |
934 | { SReg2, "SReg2" }, | |
935 | { SReg3, "SReg3" }, | |
936 | { Acc, "Acc" }, | |
937 | { JumpAbsolute, "Jump Absolute" }, | |
938 | { RegMMX, "rMMX" }, | |
3f4438ab | 939 | { RegXMM, "rXMM" }, |
252b5132 RH |
940 | { EsSeg, "es" }, |
941 | { 0, "" } | |
942 | }; | |
943 | ||
944 | static void | |
945 | pt (t) | |
946 | unsigned int t; | |
947 | { | |
948 | register struct type_name *ty; | |
949 | ||
950 | if (t == Unknown) | |
951 | { | |
952 | fprintf (stdout, _("Unknown")); | |
953 | } | |
954 | else | |
955 | { | |
956 | for (ty = type_names; ty->mask; ty++) | |
957 | if (t & ty->mask) | |
958 | fprintf (stdout, "%s, ", ty->tname); | |
959 | } | |
960 | fflush (stdout); | |
961 | } | |
962 | ||
963 | #endif /* DEBUG386 */ | |
964 | \f | |
965 | int | |
966 | tc_i386_force_relocation (fixp) | |
967 | struct fix *fixp; | |
968 | { | |
969 | #ifdef BFD_ASSEMBLER | |
970 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
971 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
972 | return 1; | |
973 | return 0; | |
974 | #else | |
975 | /* For COFF */ | |
f6af82bd | 976 | return fixp->fx_r_type == 7; |
252b5132 RH |
977 | #endif |
978 | } | |
979 | ||
980 | #ifdef BFD_ASSEMBLER | |
981 | static bfd_reloc_code_real_type reloc | |
982 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
983 | ||
984 | static bfd_reloc_code_real_type | |
985 | reloc (size, pcrel, other) | |
986 | int size; | |
987 | int pcrel; | |
988 | bfd_reloc_code_real_type other; | |
989 | { | |
990 | if (other != NO_RELOC) return other; | |
991 | ||
992 | if (pcrel) | |
993 | { | |
994 | switch (size) | |
995 | { | |
996 | case 1: return BFD_RELOC_8_PCREL; | |
997 | case 2: return BFD_RELOC_16_PCREL; | |
998 | case 4: return BFD_RELOC_32_PCREL; | |
999 | } | |
d0b47220 | 1000 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1001 | } |
1002 | else | |
1003 | { | |
1004 | switch (size) | |
1005 | { | |
1006 | case 1: return BFD_RELOC_8; | |
1007 | case 2: return BFD_RELOC_16; | |
1008 | case 4: return BFD_RELOC_32; | |
1009 | } | |
d0b47220 | 1010 | as_bad (_("can not do %d byte relocation"), size); |
252b5132 RH |
1011 | } |
1012 | ||
1013 | return BFD_RELOC_NONE; | |
1014 | } | |
1015 | ||
1016 | /* | |
1017 | * Here we decide which fixups can be adjusted to make them relative to | |
1018 | * the beginning of the section instead of the symbol. Basically we need | |
1019 | * to make sure that the dynamic relocations are done correctly, so in | |
1020 | * some cases we force the original symbol to be used. | |
1021 | */ | |
1022 | int | |
c0c949c7 ILT |
1023 | tc_i386_fix_adjustable (fixP) |
1024 | fixS *fixP; | |
252b5132 | 1025 | { |
79d292aa ILT |
1026 | #if defined (OBJ_ELF) || defined (TE_PE) |
1027 | /* Prevent all adjustments to global symbols, or else dynamic | |
1028 | linking will not work correctly. */ | |
252b5132 RH |
1029 | if (S_IS_EXTERN (fixP->fx_addsy)) |
1030 | return 0; | |
1031 | if (S_IS_WEAK (fixP->fx_addsy)) | |
1032 | return 0; | |
1033 | #endif | |
1034 | /* adjust_reloc_syms doesn't know about the GOT */ | |
1035 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
1036 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1037 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
d33e1d24 | 1038 | || fixP->fx_r_type == BFD_RELOC_RVA |
252b5132 RH |
1039 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1040 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1041 | return 0; | |
1042 | return 1; | |
1043 | } | |
1044 | #else | |
1045 | #define reloc(SIZE,PCREL,OTHER) 0 | |
1046 | #define BFD_RELOC_16 0 | |
1047 | #define BFD_RELOC_32 0 | |
1048 | #define BFD_RELOC_16_PCREL 0 | |
1049 | #define BFD_RELOC_32_PCREL 0 | |
1050 | #define BFD_RELOC_386_PLT32 0 | |
1051 | #define BFD_RELOC_386_GOT32 0 | |
1052 | #define BFD_RELOC_386_GOTOFF 0 | |
1053 | #endif | |
1054 | ||
b4cac588 AM |
1055 | static int |
1056 | intel_float_operand PARAMS ((char *mnemonic)); | |
1057 | ||
1058 | static int | |
252b5132 RH |
1059 | intel_float_operand (mnemonic) |
1060 | char *mnemonic; | |
1061 | { | |
1062 | if (mnemonic[0] == 'f' && mnemonic[1] =='i') | |
cc5ca5ce | 1063 | return 2; |
252b5132 RH |
1064 | |
1065 | if (mnemonic[0] == 'f') | |
1066 | return 1; | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1072 | machine dependent instruction. This function is supposed to emit | |
1073 | the frags/bytes it assembles to. */ | |
1074 | ||
1075 | void | |
1076 | md_assemble (line) | |
1077 | char *line; | |
1078 | { | |
1079 | /* Points to template once we've found it. */ | |
1080 | const template *t; | |
1081 | ||
1082 | /* Count the size of the instruction generated. */ | |
1083 | int insn_size = 0; | |
1084 | ||
1085 | int j; | |
1086 | ||
1087 | char mnemonic[MAX_MNEM_SIZE]; | |
1088 | ||
1089 | /* Initialize globals. */ | |
1090 | memset (&i, '\0', sizeof (i)); | |
1091 | for (j = 0; j < MAX_OPERANDS; j++) | |
1092 | i.disp_reloc[j] = NO_RELOC; | |
1093 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
1094 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
1095 | save_stack_p = save_stack; /* reset stack pointer */ | |
1096 | ||
1097 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1098 | We assume that the scrubber has arranged it so that line[0] is the valid | |
1099 | start of a (possibly prefixed) mnemonic. */ | |
1100 | { | |
1101 | char *l = line; | |
1102 | char *token_start = l; | |
1103 | char *mnem_p; | |
1104 | ||
1105 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
1106 | const char *expecting_string_instruction = NULL; | |
1107 | ||
1108 | while (1) | |
1109 | { | |
1110 | mnem_p = mnemonic; | |
1111 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1112 | { | |
1113 | mnem_p++; | |
1114 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1115 | { | |
e413e4e9 | 1116 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1117 | return; |
1118 | } | |
1119 | l++; | |
1120 | } | |
1121 | if (!is_space_char (*l) | |
1122 | && *l != END_OF_INSN | |
1123 | && *l != PREFIX_SEPARATOR) | |
1124 | { | |
1125 | as_bad (_("invalid character %s in mnemonic"), | |
1126 | output_invalid (*l)); | |
1127 | return; | |
1128 | } | |
1129 | if (token_start == l) | |
1130 | { | |
1131 | if (*l == PREFIX_SEPARATOR) | |
1132 | as_bad (_("expecting prefix; got nothing")); | |
1133 | else | |
1134 | as_bad (_("expecting mnemonic; got nothing")); | |
1135 | return; | |
1136 | } | |
1137 | ||
1138 | /* Look up instruction (or prefix) via hash table. */ | |
1139 | current_templates = hash_find (op_hash, mnemonic); | |
1140 | ||
1141 | if (*l != END_OF_INSN | |
1142 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1143 | && current_templates | |
1144 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1145 | { | |
1146 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1147 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1148 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1149 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1150 | ^ flag_16bit_code)) | |
1151 | { | |
1152 | as_bad (_("redundant %s prefix"), | |
1153 | current_templates->start->name); | |
1154 | return; | |
1155 | } | |
1156 | /* Add prefix, checking for repeated prefixes. */ | |
1157 | switch (add_prefix (current_templates->start->base_opcode)) | |
1158 | { | |
1159 | case 0: | |
1160 | return; | |
1161 | case 2: | |
1162 | expecting_string_instruction = | |
1163 | current_templates->start->name; | |
1164 | break; | |
1165 | } | |
1166 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1167 | token_start = ++l; | |
1168 | } | |
1169 | else | |
1170 | break; | |
1171 | } | |
1172 | ||
1173 | if (!current_templates) | |
1174 | { | |
24eab124 | 1175 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1176 | switch (mnem_p[-1]) |
1177 | { | |
252b5132 RH |
1178 | case WORD_MNEM_SUFFIX: |
1179 | case BYTE_MNEM_SUFFIX: | |
1180 | case SHORT_MNEM_SUFFIX: | |
252b5132 | 1181 | case LONG_MNEM_SUFFIX: |
252b5132 RH |
1182 | i.suffix = mnem_p[-1]; |
1183 | mnem_p[-1] = '\0'; | |
1184 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 AM |
1185 | break; |
1186 | ||
1187 | /* Intel Syntax */ | |
add0c677 | 1188 | case DWORD_MNEM_SUFFIX: |
24eab124 AM |
1189 | if (intel_syntax) |
1190 | { | |
1191 | i.suffix = mnem_p[-1]; | |
1192 | mnem_p[-1] = '\0'; | |
1193 | current_templates = hash_find (op_hash, mnemonic); | |
1194 | break; | |
1195 | } | |
252b5132 RH |
1196 | } |
1197 | if (!current_templates) | |
1198 | { | |
e413e4e9 | 1199 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1200 | return; |
1201 | } | |
1202 | } | |
1203 | ||
e413e4e9 AM |
1204 | /* Check if instruction is supported on specified architecture. */ |
1205 | if (cpu_arch_flags != 0) | |
1206 | { | |
1207 | if (current_templates->start->cpu_flags & ~ cpu_arch_flags) | |
1208 | { | |
1209 | as_warn (_("`%s' is not supported on `%s'"), | |
1210 | current_templates->start->name, cpu_arch_name); | |
1211 | } | |
1212 | else if ((Cpu386 & ~ cpu_arch_flags) && !flag_16bit_code) | |
1213 | { | |
1214 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1215 | } | |
1216 | } | |
1217 | ||
252b5132 RH |
1218 | /* check for rep/repne without a string instruction */ |
1219 | if (expecting_string_instruction | |
1220 | && !(current_templates->start->opcode_modifier & IsString)) | |
1221 | { | |
1222 | as_bad (_("expecting string instruction after `%s'"), | |
1223 | expecting_string_instruction); | |
1224 | return; | |
1225 | } | |
1226 | ||
1227 | /* There may be operands to parse. */ | |
1228 | if (*l != END_OF_INSN) | |
1229 | { | |
1230 | /* parse operands */ | |
1231 | ||
1232 | /* 1 if operand is pending after ','. */ | |
1233 | unsigned int expecting_operand = 0; | |
1234 | ||
1235 | /* Non-zero if operand parens not balanced. */ | |
1236 | unsigned int paren_not_balanced; | |
1237 | ||
1238 | do | |
1239 | { | |
1240 | /* skip optional white space before operand */ | |
1241 | if (is_space_char (*l)) | |
1242 | ++l; | |
1243 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1244 | { | |
1245 | as_bad (_("invalid character %s before operand %d"), | |
1246 | output_invalid (*l), | |
1247 | i.operands + 1); | |
1248 | return; | |
1249 | } | |
1250 | token_start = l; /* after white space */ | |
1251 | paren_not_balanced = 0; | |
1252 | while (paren_not_balanced || *l != ',') | |
1253 | { | |
1254 | if (*l == END_OF_INSN) | |
1255 | { | |
1256 | if (paren_not_balanced) | |
1257 | { | |
24eab124 | 1258 | if (!intel_syntax) |
252b5132 RH |
1259 | as_bad (_("unbalanced parenthesis in operand %d."), |
1260 | i.operands + 1); | |
24eab124 | 1261 | else |
252b5132 RH |
1262 | as_bad (_("unbalanced brackets in operand %d."), |
1263 | i.operands + 1); | |
1264 | return; | |
1265 | } | |
1266 | else | |
1267 | break; /* we are done */ | |
1268 | } | |
1269 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1270 | { | |
1271 | as_bad (_("invalid character %s in operand %d"), | |
1272 | output_invalid (*l), | |
1273 | i.operands + 1); | |
1274 | return; | |
1275 | } | |
24eab124 AM |
1276 | if (!intel_syntax) |
1277 | { | |
252b5132 RH |
1278 | if (*l == '(') |
1279 | ++paren_not_balanced; | |
1280 | if (*l == ')') | |
1281 | --paren_not_balanced; | |
24eab124 AM |
1282 | } |
1283 | else | |
1284 | { | |
252b5132 RH |
1285 | if (*l == '[') |
1286 | ++paren_not_balanced; | |
1287 | if (*l == ']') | |
1288 | --paren_not_balanced; | |
24eab124 | 1289 | } |
252b5132 RH |
1290 | l++; |
1291 | } | |
1292 | if (l != token_start) | |
1293 | { /* yes, we've read in another operand */ | |
1294 | unsigned int operand_ok; | |
1295 | this_operand = i.operands++; | |
1296 | if (i.operands > MAX_OPERANDS) | |
1297 | { | |
1298 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1299 | MAX_OPERANDS); | |
1300 | return; | |
1301 | } | |
1302 | /* now parse operand adding info to 'i' as we go along */ | |
1303 | END_STRING_AND_SAVE (l); | |
1304 | ||
24eab124 AM |
1305 | if (intel_syntax) |
1306 | operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic)); | |
1307 | else | |
1308 | operand_ok = i386_operand (token_start); | |
252b5132 RH |
1309 | |
1310 | RESTORE_END_STRING (l); /* restore old contents */ | |
1311 | if (!operand_ok) | |
1312 | return; | |
1313 | } | |
1314 | else | |
1315 | { | |
1316 | if (expecting_operand) | |
1317 | { | |
1318 | expecting_operand_after_comma: | |
1319 | as_bad (_("expecting operand after ','; got nothing")); | |
1320 | return; | |
1321 | } | |
1322 | if (*l == ',') | |
1323 | { | |
1324 | as_bad (_("expecting operand before ','; got nothing")); | |
1325 | return; | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | /* now *l must be either ',' or END_OF_INSN */ | |
1330 | if (*l == ',') | |
1331 | { | |
1332 | if (*++l == END_OF_INSN) | |
1333 | { /* just skip it, if it's \n complain */ | |
1334 | goto expecting_operand_after_comma; | |
1335 | } | |
1336 | expecting_operand = 1; | |
1337 | } | |
1338 | } | |
1339 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1344 | operands at hand. | |
1345 | ||
1346 | Next, we find a template that matches the given insn, | |
1347 | making sure the overlap of the given operands types is consistent | |
1348 | with the template operand types. */ | |
1349 | ||
1350 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1351 | ((overlap & ~JumpAbsolute) \ |
1352 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1353 | |
1354 | /* If given types r0 and r1 are registers they must be of the same type | |
1355 | unless the expected operand type register overlap is null. | |
1356 | Note that Acc in a template matches every size of reg. */ | |
1357 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1358 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1359 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1360 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1361 | ||
1362 | { | |
1363 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1364 | unsigned int overlap2; |
1365 | unsigned int found_reverse_match; | |
1366 | int suffix_check; | |
1367 | ||
cc5ca5ce AM |
1368 | /* All intel opcodes have reversed operands except for "bound" and |
1369 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1370 | instructions with 2 immediate operands so that the immediate segment | |
1371 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1372 | intersegment "jmp" and "call" instructions are the only ones that | |
1373 | have two immediate operands. */ | |
520dc8e8 | 1374 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1375 | && (strcmp (mnemonic, "bound") != 0) |
1376 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1377 | { |
520dc8e8 | 1378 | union i386_op temp_op; |
24eab124 AM |
1379 | unsigned int temp_type; |
1380 | int xchg1 = 0; | |
ab9da554 | 1381 | int xchg2 = 0; |
252b5132 | 1382 | |
24eab124 AM |
1383 | if (i.operands == 2) |
1384 | { | |
1385 | xchg1 = 0; | |
1386 | xchg2 = 1; | |
1387 | } | |
1388 | else if (i.operands == 3) | |
1389 | { | |
1390 | xchg1 = 0; | |
1391 | xchg2 = 2; | |
1392 | } | |
520dc8e8 AM |
1393 | temp_type = i.types[xchg2]; |
1394 | i.types[xchg2] = i.types[xchg1]; | |
1395 | i.types[xchg1] = temp_type; | |
1396 | temp_op = i.op[xchg2]; | |
1397 | i.op[xchg2] = i.op[xchg1]; | |
1398 | i.op[xchg1] = temp_op; | |
36bf8ab9 AM |
1399 | |
1400 | if (i.mem_operands == 2) | |
1401 | { | |
1402 | const seg_entry *temp_seg; | |
1403 | temp_seg = i.seg[0]; | |
1404 | i.seg[0] = i.seg[1]; | |
1405 | i.seg[1] = temp_seg; | |
1406 | } | |
24eab124 | 1407 | } |
773f551c AM |
1408 | |
1409 | if (i.imm_operands) | |
1410 | { | |
1411 | /* Try to ensure constant immediates are represented in the smallest | |
1412 | opcode possible. */ | |
1413 | char guess_suffix = 0; | |
1414 | int op; | |
1415 | ||
1416 | if (i.suffix) | |
1417 | guess_suffix = i.suffix; | |
1418 | else if (i.reg_operands) | |
1419 | { | |
1420 | /* Figure out a suffix from the last register operand specified. | |
1421 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1422 | but the following works for instructions with immediates. | |
1423 | In any case, we can't set i.suffix yet. */ | |
1424 | for (op = i.operands; --op >= 0; ) | |
1425 | if (i.types[op] & Reg) | |
1426 | { | |
1427 | if (i.types[op] & Reg8) | |
1428 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1429 | else if (i.types[op] & Reg16) | |
1430 | guess_suffix = WORD_MNEM_SUFFIX; | |
1431 | break; | |
1432 | } | |
1433 | } | |
726c5dcd AM |
1434 | else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) |
1435 | guess_suffix = WORD_MNEM_SUFFIX; | |
1436 | ||
773f551c AM |
1437 | for (op = i.operands; --op >= 0; ) |
1438 | if ((i.types[op] & Imm) | |
1439 | && i.op[op].imms->X_op == O_constant) | |
1440 | { | |
1441 | /* If a suffix is given, this operand may be shortened. */ | |
1442 | switch (guess_suffix) | |
1443 | { | |
1444 | case WORD_MNEM_SUFFIX: | |
1445 | i.types[op] |= Imm16; | |
1446 | break; | |
1447 | case BYTE_MNEM_SUFFIX: | |
1448 | i.types[op] |= Imm16 | Imm8 | Imm8S; | |
1449 | break; | |
1450 | } | |
1451 | ||
1452 | /* If this operand is at most 16 bits, convert it to a | |
1453 | signed 16 bit number before trying to see whether it will | |
1454 | fit in an even smaller size. This allows a 16-bit operand | |
1455 | such as $0xffe0 to be recognised as within Imm8S range. */ | |
1456 | if ((i.types[op] & Imm16) | |
1457 | && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) | |
1458 | { | |
1459 | i.op[op].imms->X_add_number = | |
1460 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1461 | } | |
1462 | i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); | |
1463 | } | |
1464 | } | |
1465 | ||
252b5132 RH |
1466 | overlap0 = 0; |
1467 | overlap1 = 0; | |
1468 | overlap2 = 0; | |
1469 | found_reverse_match = 0; | |
1470 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1471 | ? No_bSuf | |
1472 | : (i.suffix == WORD_MNEM_SUFFIX | |
1473 | ? No_wSuf | |
1474 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1475 | ? No_sSuf | |
1476 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1477 | ? No_lSuf |
add0c677 | 1478 | : (i.suffix == DWORD_MNEM_SUFFIX |
24eab124 AM |
1479 | ? No_dSuf |
1480 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1481 | |
1482 | for (t = current_templates->start; | |
1483 | t < current_templates->end; | |
1484 | t++) | |
1485 | { | |
1486 | /* Must have right number of operands. */ | |
1487 | if (i.operands != t->operands) | |
1488 | continue; | |
1489 | ||
7f3f1ea2 AM |
1490 | /* Check the suffix, except for some instructions in intel mode. */ |
1491 | if ((t->opcode_modifier & suffix_check) | |
1492 | && !(intel_syntax | |
1493 | && t->base_opcode == 0xd9 | |
1494 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ | |
1495 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1496 | continue; |
252b5132 RH |
1497 | |
1498 | else if (!t->operands) | |
1499 | break; /* 0 operands always matches */ | |
1500 | ||
1501 | overlap0 = i.types[0] & t->operand_types[0]; | |
1502 | switch (t->operands) | |
1503 | { | |
1504 | case 1: | |
1505 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1506 | continue; | |
1507 | break; | |
1508 | case 2: | |
1509 | case 3: | |
1510 | overlap1 = i.types[1] & t->operand_types[1]; | |
1511 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1512 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1513 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1514 | t->operand_types[0], | |
1515 | overlap1, i.types[1], | |
1516 | t->operand_types[1])) | |
1517 | { | |
1518 | ||
1519 | /* check if other direction is valid ... */ | |
1520 | if ((t->opcode_modifier & (D|FloatD)) == 0) | |
1521 | continue; | |
1522 | ||
1523 | /* try reversing direction of operands */ | |
1524 | overlap0 = i.types[0] & t->operand_types[1]; | |
1525 | overlap1 = i.types[1] & t->operand_types[0]; | |
1526 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1527 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1528 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1529 | t->operand_types[1], | |
1530 | overlap1, i.types[1], | |
1531 | t->operand_types[0])) | |
1532 | { | |
1533 | /* does not match either direction */ | |
1534 | continue; | |
1535 | } | |
1536 | /* found_reverse_match holds which of D or FloatDR | |
1537 | we've found. */ | |
1538 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1539 | break; | |
1540 | } | |
1541 | /* found a forward 2 operand match here */ | |
1542 | if (t->operands == 3) | |
1543 | { | |
1544 | /* Here we make use of the fact that there are no | |
1545 | reverse match 3 operand instructions, and all 3 | |
1546 | operand instructions only need to be checked for | |
1547 | register consistency between operands 2 and 3. */ | |
1548 | overlap2 = i.types[2] & t->operand_types[2]; | |
1549 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1550 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1551 | t->operand_types[1], | |
1552 | overlap2, i.types[2], | |
24eab124 | 1553 | t->operand_types[2])) |
252b5132 | 1554 | |
24eab124 | 1555 | continue; |
252b5132 RH |
1556 | } |
1557 | /* found either forward/reverse 2 or 3 operand match here: | |
1558 | slip through to break */ | |
1559 | } | |
1560 | break; /* we've found a match; break out of loop */ | |
1561 | } /* for (t = ... */ | |
1562 | if (t == current_templates->end) | |
1563 | { /* we found no match */ | |
1564 | as_bad (_("suffix or operands invalid for `%s'"), | |
1565 | current_templates->start->name); | |
1566 | return; | |
1567 | } | |
1568 | ||
a38cf1db | 1569 | if (!quiet_warnings) |
3138f287 | 1570 | { |
a38cf1db AM |
1571 | if (!intel_syntax |
1572 | && ((i.types[0] & JumpAbsolute) | |
1573 | != (t->operand_types[0] & JumpAbsolute))) | |
1574 | { | |
1575 | as_warn (_("indirect %s without `*'"), t->name); | |
1576 | } | |
3138f287 | 1577 | |
a38cf1db AM |
1578 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1579 | == (IsPrefix|IgnoreSize)) | |
1580 | { | |
1581 | /* Warn them that a data or address size prefix doesn't | |
1582 | affect assembly of the next line of code. */ | |
1583 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1584 | } | |
252b5132 RH |
1585 | } |
1586 | ||
1587 | /* Copy the template we found. */ | |
1588 | i.tm = *t; | |
1589 | if (found_reverse_match) | |
1590 | { | |
7f3f1ea2 AM |
1591 | /* If we found a reverse match we must alter the opcode |
1592 | direction bit. found_reverse_match holds bits to change | |
1593 | (different for int & float insns). */ | |
1594 | ||
1595 | i.tm.base_opcode ^= found_reverse_match; | |
1596 | ||
252b5132 RH |
1597 | i.tm.operand_types[0] = t->operand_types[1]; |
1598 | i.tm.operand_types[1] = t->operand_types[0]; | |
1599 | } | |
1600 | ||
d0b47220 AM |
1601 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
1602 | if (SYSV386_COMPAT | |
7f3f1ea2 AM |
1603 | && intel_syntax |
1604 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1605 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1606 | |
1607 | if (i.tm.opcode_modifier & FWait) | |
1608 | if (! add_prefix (FWAIT_OPCODE)) | |
1609 | return; | |
1610 | ||
1611 | /* Check string instruction segment overrides */ | |
1612 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1613 | { | |
1614 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1615 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1616 | { | |
1617 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1618 | { | |
1619 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1620 | i.tm.name, | |
1621 | mem_op + 1); | |
1622 | return; | |
1623 | } | |
1624 | /* There's only ever one segment override allowed per instruction. | |
1625 | This instruction possibly has a legal segment override on the | |
1626 | second operand, so copy the segment to where non-string | |
1627 | instructions store it, allowing common code. */ | |
1628 | i.seg[0] = i.seg[1]; | |
1629 | } | |
1630 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1631 | { | |
1632 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1633 | { | |
1634 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1635 | i.tm.name, | |
1636 | mem_op + 2); | |
1637 | return; | |
1638 | } | |
1639 | } | |
1640 | } | |
1641 | ||
1642 | /* If matched instruction specifies an explicit instruction mnemonic | |
1643 | suffix, use it. */ | |
1644 | if (i.tm.opcode_modifier & (Size16 | Size32)) | |
1645 | { | |
1646 | if (i.tm.opcode_modifier & Size16) | |
1647 | i.suffix = WORD_MNEM_SUFFIX; | |
1648 | else | |
add0c677 | 1649 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1650 | } |
1651 | else if (i.reg_operands) | |
1652 | { | |
1653 | /* If there's no instruction mnemonic suffix we try to invent one | |
1654 | based on register operands. */ | |
1655 | if (!i.suffix) | |
1656 | { | |
1657 | /* We take i.suffix from the last register operand specified, | |
1658 | Destination register type is more significant than source | |
1659 | register type. */ | |
1660 | int op; | |
1661 | for (op = i.operands; --op >= 0; ) | |
cc5ca5ce AM |
1662 | if ((i.types[op] & Reg) |
1663 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1664 | { |
1665 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1666 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
add0c677 | 1667 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1668 | break; |
1669 | } | |
1670 | } | |
1671 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1672 | { | |
1673 | int op; | |
1674 | for (op = i.operands; --op >= 0; ) | |
1675 | { | |
1676 | /* If this is an eight bit register, it's OK. If it's | |
1677 | the 16 or 32 bit version of an eight bit register, | |
1678 | we will just use the low portion, and that's OK too. */ | |
1679 | if (i.types[op] & Reg8) | |
1680 | continue; | |
1681 | ||
24eab124 AM |
1682 | /* movzx and movsx should not generate this warning. */ |
1683 | if (intel_syntax | |
1684 | && (i.tm.base_opcode == 0xfb7 | |
1685 | || i.tm.base_opcode == 0xfb6 | |
1686 | || i.tm.base_opcode == 0xfbe | |
1687 | || i.tm.base_opcode == 0xfbf)) | |
1688 | continue; | |
252b5132 | 1689 | |
520dc8e8 | 1690 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1691 | #if 0 |
1692 | /* Check that the template allows eight bit regs | |
1693 | This kills insns such as `orb $1,%edx', which | |
1694 | maybe should be allowed. */ | |
1695 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1696 | #endif | |
1697 | ) | |
1698 | { | |
1699 | #if REGISTER_WARNINGS | |
a38cf1db AM |
1700 | if (!quiet_warnings |
1701 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1702 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
520dc8e8 AM |
1703 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
1704 | i.op[op].regs->reg_name, | |
252b5132 RH |
1705 | i.suffix); |
1706 | #endif | |
1707 | continue; | |
1708 | } | |
1709 | /* Any other register is bad */ | |
3f4438ab AM |
1710 | if (i.types[op] & (Reg | RegMMX | RegXMM |
1711 | | SReg2 | SReg3 | |
1712 | | Control | Debug | Test | |
1713 | | FloatReg | FloatAcc)) | |
252b5132 RH |
1714 | { |
1715 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1716 | i.op[op].regs->reg_name, |
252b5132 RH |
1717 | i.tm.name, |
1718 | i.suffix); | |
1719 | return; | |
1720 | } | |
1721 | } | |
1722 | } | |
add0c677 | 1723 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1724 | { |
1725 | int op; | |
1726 | for (op = i.operands; --op >= 0; ) | |
1727 | /* Reject eight bit registers, except where the template | |
1728 | requires them. (eg. movzb) */ | |
1729 | if ((i.types[op] & Reg8) != 0 | |
1730 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1731 | { | |
1732 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1733 | i.op[op].regs->reg_name, |
252b5132 RH |
1734 | i.tm.name, |
1735 | i.suffix); | |
1736 | return; | |
1737 | } | |
1738 | #if REGISTER_WARNINGS | |
1739 | /* Warn if the e prefix on a general reg is missing. */ | |
a38cf1db AM |
1740 | else if (!quiet_warnings |
1741 | && (i.types[op] & Reg16) != 0 | |
252b5132 RH |
1742 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
1743 | { | |
1744 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1745 | (i.op[op].regs + 8)->reg_name, |
1746 | i.op[op].regs->reg_name, | |
252b5132 RH |
1747 | i.suffix); |
1748 | } | |
1749 | #endif | |
1750 | } | |
1751 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
1752 | { | |
1753 | int op; | |
1754 | for (op = i.operands; --op >= 0; ) | |
1755 | /* Reject eight bit registers, except where the template | |
1756 | requires them. (eg. movzb) */ | |
1757 | if ((i.types[op] & Reg8) != 0 | |
1758 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1759 | { | |
1760 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1761 | i.op[op].regs->reg_name, |
252b5132 RH |
1762 | i.tm.name, |
1763 | i.suffix); | |
1764 | return; | |
1765 | } | |
1766 | #if REGISTER_WARNINGS | |
1767 | /* Warn if the e prefix on a general reg is present. */ | |
a38cf1db AM |
1768 | else if (!quiet_warnings |
1769 | && (i.types[op] & Reg32) != 0 | |
252b5132 RH |
1770 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
1771 | { | |
1772 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1773 | (i.op[op].regs - 8)->reg_name, |
1774 | i.op[op].regs->reg_name, | |
252b5132 RH |
1775 | i.suffix); |
1776 | } | |
1777 | #endif | |
1778 | } | |
1779 | else | |
1780 | abort(); | |
1781 | } | |
eecb386c AM |
1782 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
1783 | { | |
1784 | i.suffix = stackop_size; | |
1785 | } | |
252b5132 RH |
1786 | |
1787 | /* Make still unresolved immediate matches conform to size of immediate | |
1788 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
1789 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1790 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1791 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1792 | { | |
1793 | if (i.suffix) | |
1794 | { | |
24eab124 AM |
1795 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1796 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1797 | } |
1798 | else if (overlap0 == (Imm16 | Imm32)) | |
1799 | { | |
24eab124 | 1800 | overlap0 = |
252b5132 RH |
1801 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1802 | } | |
1803 | else | |
1804 | { | |
1805 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1806 | return; | |
1807 | } | |
1808 | } | |
1809 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1810 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1811 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1812 | { | |
1813 | if (i.suffix) | |
1814 | { | |
24eab124 AM |
1815 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1816 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1817 | } |
1818 | else if (overlap1 == (Imm16 | Imm32)) | |
1819 | { | |
24eab124 | 1820 | overlap1 = |
252b5132 RH |
1821 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1822 | } | |
1823 | else | |
1824 | { | |
1825 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1826 | return; | |
1827 | } | |
1828 | } | |
1829 | assert ((overlap2 & Imm) == 0); | |
1830 | ||
1831 | i.types[0] = overlap0; | |
1832 | if (overlap0 & ImplicitRegister) | |
1833 | i.reg_operands--; | |
1834 | if (overlap0 & Imm1) | |
1835 | i.imm_operands = 0; /* kludge for shift insns */ | |
1836 | ||
1837 | i.types[1] = overlap1; | |
1838 | if (overlap1 & ImplicitRegister) | |
1839 | i.reg_operands--; | |
1840 | ||
1841 | i.types[2] = overlap2; | |
1842 | if (overlap2 & ImplicitRegister) | |
1843 | i.reg_operands--; | |
1844 | ||
1845 | /* Finalize opcode. First, we change the opcode based on the operand | |
1846 | size given by i.suffix: We need not change things for byte insns. */ | |
1847 | ||
1848 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
1849 | { | |
1850 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
1851 | return; | |
1852 | } | |
1853 | ||
1854 | /* For movzx and movsx, need to check the register type */ | |
1855 | if (intel_syntax | |
24eab124 | 1856 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 1857 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
1858 | { |
1859 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 1860 | |
520dc8e8 | 1861 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
1862 | if (!add_prefix (prefix)) |
1863 | return; | |
1864 | } | |
252b5132 RH |
1865 | |
1866 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
1867 | { | |
1868 | /* It's not a byte, select word/dword operation. */ | |
1869 | if (i.tm.opcode_modifier & W) | |
1870 | { | |
1871 | if (i.tm.opcode_modifier & ShortForm) | |
1872 | i.tm.base_opcode |= 8; | |
1873 | else | |
1874 | i.tm.base_opcode |= 1; | |
1875 | } | |
1876 | /* Now select between word & dword operations via the operand | |
1877 | size prefix, except for instructions that will ignore this | |
1878 | prefix anyway. */ | |
add0c677 | 1879 | if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1880 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
1881 | && !(i.tm.opcode_modifier & IgnoreSize)) | |
1882 | { | |
1883 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
1884 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
1885 | prefix = ADDR_PREFIX_OPCODE; | |
1886 | ||
1887 | if (! add_prefix (prefix)) | |
1888 | return; | |
1889 | } | |
1890 | /* Size floating point instruction. */ | |
1891 | if (i.suffix == LONG_MNEM_SUFFIX | |
add0c677 | 1892 | || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1893 | { |
1894 | if (i.tm.opcode_modifier & FloatMF) | |
1895 | i.tm.base_opcode ^= 4; | |
1896 | } | |
252b5132 RH |
1897 | } |
1898 | ||
3f4438ab | 1899 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 1900 | { |
3f4438ab AM |
1901 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1902 | opcode suffix which is coded in the same place as an 8-bit | |
1903 | immediate field would be. Here we fake an 8-bit immediate | |
1904 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
1905 | |
1906 | expressionS *exp; | |
1907 | ||
520dc8e8 | 1908 | assert(i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
1909 | |
1910 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 1911 | i.op[i.operands].imms = exp; |
252b5132 RH |
1912 | i.types[i.operands++] = Imm8; |
1913 | exp->X_op = O_constant; | |
1914 | exp->X_add_number = i.tm.extension_opcode; | |
1915 | i.tm.extension_opcode = None; | |
1916 | } | |
1917 | ||
1918 | /* For insns with operands there are more diddles to do to the opcode. */ | |
1919 | if (i.operands) | |
1920 | { | |
24eab124 | 1921 | /* Default segment register this instruction will use |
252b5132 RH |
1922 | for memory accesses. 0 means unknown. |
1923 | This is only for optimizing out unnecessary segment overrides. */ | |
1924 | const seg_entry *default_seg = 0; | |
1925 | ||
252b5132 RH |
1926 | /* The imul $imm, %reg instruction is converted into |
1927 | imul $imm, %reg, %reg, and the clr %reg instruction | |
1928 | is converted into xor %reg, %reg. */ | |
1929 | if (i.tm.opcode_modifier & regKludge) | |
1930 | { | |
1931 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
1932 | /* Pretend we saw the extra register operand. */ | |
520dc8e8 AM |
1933 | assert (i.op[first_reg_op+1].regs == 0); |
1934 | i.op[first_reg_op+1].regs = i.op[first_reg_op].regs; | |
1935 | i.types[first_reg_op+1] = i.types[first_reg_op]; | |
252b5132 RH |
1936 | i.reg_operands = 2; |
1937 | } | |
1938 | ||
1939 | if (i.tm.opcode_modifier & ShortForm) | |
1940 | { | |
1941 | /* The register or float register operand is in operand 0 or 1. */ | |
1942 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; | |
1943 | /* Register goes in low 3 bits of opcode. */ | |
520dc8e8 | 1944 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
a38cf1db | 1945 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
1946 | { |
1947 | /* Warn about some common errors, but press on regardless. | |
1948 | The first case can be generated by gcc (<= 2.8.1). */ | |
1949 | if (i.operands == 2) | |
1950 | { | |
1951 | /* reversed arguments on faddp, fsubp, etc. */ | |
1952 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
520dc8e8 AM |
1953 | i.op[1].regs->reg_name, |
1954 | i.op[0].regs->reg_name); | |
252b5132 RH |
1955 | } |
1956 | else | |
1957 | { | |
1958 | /* extraneous `l' suffix on fp insn */ | |
1959 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
520dc8e8 | 1960 | i.op[0].regs->reg_name); |
252b5132 RH |
1961 | } |
1962 | } | |
1963 | } | |
1964 | else if (i.tm.opcode_modifier & Modrm) | |
1965 | { | |
1966 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
1967 | must be put into the modrm byte). | |
1968 | Now, we make the modrm & index base bytes based on all the | |
1969 | info we've collected. */ | |
1970 | ||
1971 | /* i.reg_operands MUST be the number of real register operands; | |
1972 | implicit registers do not count. */ | |
1973 | if (i.reg_operands == 2) | |
1974 | { | |
1975 | unsigned int source, dest; | |
1976 | source = ((i.types[0] | |
3f4438ab AM |
1977 | & (Reg | RegMMX | RegXMM |
1978 | | SReg2 | SReg3 | |
1979 | | Control | Debug | Test)) | |
252b5132 RH |
1980 | ? 0 : 1); |
1981 | dest = source + 1; | |
1982 | ||
252b5132 | 1983 | i.rm.mode = 3; |
3f4438ab AM |
1984 | /* One of the register operands will be encoded in the |
1985 | i.tm.reg field, the other in the combined i.tm.mode | |
1986 | and i.tm.regmem fields. If no form of this | |
1987 | instruction supports a memory destination operand, | |
1988 | then we assume the source operand may sometimes be | |
1989 | a memory operand and so we need to store the | |
1990 | destination in the i.rm.reg field. */ | |
1991 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 1992 | { |
520dc8e8 AM |
1993 | i.rm.reg = i.op[dest].regs->reg_num; |
1994 | i.rm.regmem = i.op[source].regs->reg_num; | |
252b5132 RH |
1995 | } |
1996 | else | |
1997 | { | |
520dc8e8 AM |
1998 | i.rm.reg = i.op[source].regs->reg_num; |
1999 | i.rm.regmem = i.op[dest].regs->reg_num; | |
252b5132 RH |
2000 | } |
2001 | } | |
2002 | else | |
2003 | { /* if it's not 2 reg operands... */ | |
2004 | if (i.mem_operands) | |
2005 | { | |
2006 | unsigned int fake_zero_displacement = 0; | |
2007 | unsigned int op = ((i.types[0] & AnyMem) | |
2008 | ? 0 | |
2009 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2010 | ||
2011 | default_seg = &ds; | |
2012 | ||
2013 | if (! i.base_reg) | |
2014 | { | |
2015 | i.rm.mode = 0; | |
2016 | if (! i.disp_operands) | |
2017 | fake_zero_displacement = 1; | |
2018 | if (! i.index_reg) | |
2019 | { | |
2020 | /* Operand is just <disp> */ | |
2021 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2022 | { | |
2023 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2024 | i.types[op] &= ~Disp; | |
2025 | i.types[op] |= Disp16; | |
2026 | } | |
2027 | else | |
2028 | { | |
2029 | i.rm.regmem = NO_BASE_REGISTER; | |
2030 | i.types[op] &= ~Disp; | |
2031 | i.types[op] |= Disp32; | |
2032 | } | |
2033 | } | |
2034 | else /* ! i.base_reg && i.index_reg */ | |
2035 | { | |
2036 | i.sib.index = i.index_reg->reg_num; | |
2037 | i.sib.base = NO_BASE_REGISTER; | |
2038 | i.sib.scale = i.log2_scale_factor; | |
2039 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2040 | i.types[op] &= ~Disp; | |
2041 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2042 | } | |
2043 | } | |
2044 | else if (i.base_reg->reg_type & Reg16) | |
2045 | { | |
2046 | switch (i.base_reg->reg_num) | |
2047 | { | |
2048 | case 3: /* (%bx) */ | |
2049 | if (! i.index_reg) | |
2050 | i.rm.regmem = 7; | |
2051 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
2052 | i.rm.regmem = i.index_reg->reg_num - 6; | |
2053 | break; | |
2054 | case 5: /* (%bp) */ | |
2055 | default_seg = &ss; | |
2056 | if (! i.index_reg) | |
2057 | { | |
2058 | i.rm.regmem = 6; | |
2059 | if ((i.types[op] & Disp) == 0) | |
2060 | { | |
2061 | /* fake (%bp) into 0(%bp) */ | |
2062 | i.types[op] |= Disp8; | |
2063 | fake_zero_displacement = 1; | |
2064 | } | |
2065 | } | |
2066 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
2067 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
2068 | break; | |
2069 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
2070 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
2071 | } | |
2072 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2073 | } | |
2074 | else /* i.base_reg and 32 bit mode */ | |
2075 | { | |
2076 | i.rm.regmem = i.base_reg->reg_num; | |
2077 | i.sib.base = i.base_reg->reg_num; | |
2078 | if (i.base_reg->reg_num == EBP_REG_NUM) | |
2079 | { | |
2080 | default_seg = &ss; | |
2081 | if (i.disp_operands == 0) | |
2082 | { | |
2083 | fake_zero_displacement = 1; | |
2084 | i.types[op] |= Disp8; | |
2085 | } | |
2086 | } | |
2087 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2088 | { | |
2089 | default_seg = &ss; | |
2090 | } | |
2091 | i.sib.scale = i.log2_scale_factor; | |
2092 | if (! i.index_reg) | |
2093 | { | |
2094 | /* <disp>(%esp) becomes two byte modrm | |
2095 | with no index register. We've already | |
2096 | stored the code for esp in i.rm.regmem | |
2097 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2098 | base register besides %esp will not use | |
2099 | the extra modrm byte. */ | |
2100 | i.sib.index = NO_INDEX_REGISTER; | |
2101 | #if ! SCALE1_WHEN_NO_INDEX | |
2102 | /* Another case where we force the second | |
2103 | modrm byte. */ | |
2104 | if (i.log2_scale_factor) | |
2105 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2106 | #endif | |
2107 | } | |
2108 | else | |
2109 | { | |
2110 | i.sib.index = i.index_reg->reg_num; | |
2111 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2112 | } | |
2113 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2114 | } | |
2115 | ||
2116 | if (fake_zero_displacement) | |
2117 | { | |
2118 | /* Fakes a zero displacement assuming that i.types[op] | |
2119 | holds the correct displacement size. */ | |
b4cac588 AM |
2120 | expressionS *exp; |
2121 | ||
520dc8e8 | 2122 | assert (i.op[op].disps == 0); |
252b5132 | 2123 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2124 | i.op[op].disps = exp; |
252b5132 RH |
2125 | exp->X_op = O_constant; |
2126 | exp->X_add_number = 0; | |
2127 | exp->X_add_symbol = (symbolS *) 0; | |
2128 | exp->X_op_symbol = (symbolS *) 0; | |
2129 | } | |
2130 | } | |
2131 | ||
2132 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2133 | operand (if any) based on i.tm.extension_opcode. | |
2134 | Again, we must be careful to make sure that | |
2135 | segment/control/debug/test/MMX registers are coded | |
2136 | into the i.rm.reg field. */ | |
2137 | if (i.reg_operands) | |
2138 | { | |
2139 | unsigned int op = | |
2140 | ((i.types[0] | |
3f4438ab AM |
2141 | & (Reg | RegMMX | RegXMM |
2142 | | SReg2 | SReg3 | |
2143 | | Control | Debug | Test)) | |
252b5132 RH |
2144 | ? 0 |
2145 | : ((i.types[1] | |
3f4438ab AM |
2146 | & (Reg | RegMMX | RegXMM |
2147 | | SReg2 | SReg3 | |
2148 | | Control | Debug | Test)) | |
252b5132 RH |
2149 | ? 1 |
2150 | : 2)); | |
2151 | /* If there is an extension opcode to put here, the | |
2152 | register number must be put into the regmem field. */ | |
2153 | if (i.tm.extension_opcode != None) | |
520dc8e8 | 2154 | i.rm.regmem = i.op[op].regs->reg_num; |
252b5132 | 2155 | else |
520dc8e8 | 2156 | i.rm.reg = i.op[op].regs->reg_num; |
252b5132 RH |
2157 | |
2158 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2159 | we must set it to 3 to indicate this is a register | |
2160 | operand in the regmem field. */ | |
2161 | if (!i.mem_operands) | |
2162 | i.rm.mode = 3; | |
2163 | } | |
2164 | ||
2165 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
2166 | if (i.tm.extension_opcode != None) | |
2167 | i.rm.reg = i.tm.extension_opcode; | |
2168 | } | |
2169 | } | |
2170 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2171 | { | |
520dc8e8 | 2172 | if (i.tm.base_opcode == POP_SEG_SHORT && i.op[0].regs->reg_num == 1) |
252b5132 RH |
2173 | { |
2174 | as_bad (_("you can't `pop %%cs'")); | |
2175 | return; | |
2176 | } | |
520dc8e8 | 2177 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
252b5132 RH |
2178 | } |
2179 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2180 | { | |
2181 | default_seg = &ds; | |
2182 | } | |
2183 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2184 | { | |
2185 | /* For the string instructions that allow a segment override | |
2186 | on one of their operands, the default segment is ds. */ | |
2187 | default_seg = &ds; | |
2188 | } | |
2189 | ||
2190 | /* If a segment was explicitly specified, | |
2191 | and the specified segment is not the default, | |
2192 | use an opcode prefix to select it. | |
2193 | If we never figured out what the default segment is, | |
2194 | then default_seg will be zero at this point, | |
2195 | and the specified segment prefix will always be used. */ | |
2196 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2197 | { | |
2198 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2199 | return; | |
2200 | } | |
2201 | } | |
a38cf1db | 2202 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2203 | { |
24eab124 AM |
2204 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2205 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2206 | } |
2207 | } | |
2208 | ||
2209 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
520dc8e8 | 2210 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2211 | { |
2212 | i.tm.base_opcode = INT3_OPCODE; | |
2213 | i.imm_operands = 0; | |
2214 | } | |
2215 | ||
2f66722d | 2216 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2217 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2218 | { |
2219 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2220 | the absolute address given by the constant. Since ix86 jumps and | |
2221 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2222 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2223 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2224 | } |
2225 | ||
252b5132 RH |
2226 | /* We are ready to output the insn. */ |
2227 | { | |
2228 | register char *p; | |
2229 | ||
2230 | /* Output jumps. */ | |
2231 | if (i.tm.opcode_modifier & Jump) | |
2232 | { | |
a217f122 AM |
2233 | int size; |
2234 | int code16; | |
2235 | int prefix; | |
252b5132 | 2236 | |
a217f122 AM |
2237 | code16 = 0; |
2238 | if (flag_16bit_code) | |
2239 | code16 = CODE16; | |
2240 | ||
2241 | prefix = 0; | |
2242 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2243 | { |
a217f122 | 2244 | prefix = 1; |
252b5132 | 2245 | i.prefixes -= 1; |
a217f122 | 2246 | code16 ^= CODE16; |
252b5132 | 2247 | } |
252b5132 | 2248 | |
a217f122 AM |
2249 | size = 4; |
2250 | if (code16) | |
2251 | size = 2; | |
2252 | ||
2253 | if (i.prefixes != 0 && !intel_syntax) | |
252b5132 RH |
2254 | as_warn (_("skipping prefixes on this instruction")); |
2255 | ||
2f66722d AM |
2256 | /* It's always a symbol; End frag & setup for relax. |
2257 | Make sure there is enough room in this frag for the largest | |
2258 | instruction we may generate in md_convert_frag. This is 2 | |
2259 | bytes for the opcode and room for the prefix and largest | |
2260 | displacement. */ | |
2261 | frag_grow (prefix + 2 + size); | |
2262 | insn_size += prefix + 1; | |
2263 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2264 | p = frag_more (prefix + 1); | |
2265 | if (prefix) | |
2266 | *p++ = DATA_PREFIX_OPCODE; | |
2267 | *p = i.tm.base_opcode; | |
2268 | /* 1 possible extra opcode + displacement go in fr_var. */ | |
2269 | frag_var (rs_machine_dependent, | |
2270 | 1 + size, | |
2271 | 1, | |
2272 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
2273 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
2274 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
520dc8e8 AM |
2275 | i.op[0].disps->X_add_symbol, |
2276 | i.op[0].disps->X_add_number, | |
2f66722d | 2277 | p); |
252b5132 RH |
2278 | } |
2279 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2280 | { | |
a217f122 | 2281 | int size; |
252b5132 | 2282 | |
a217f122 | 2283 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2284 | { |
a217f122 AM |
2285 | /* This is a loop or jecxz type instruction. */ |
2286 | size = 1; | |
252b5132 RH |
2287 | if (i.prefix[ADDR_PREFIX]) |
2288 | { | |
2289 | insn_size += 1; | |
2290 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2291 | i.prefixes -= 1; | |
2292 | } | |
2293 | } | |
2294 | else | |
2295 | { | |
a217f122 AM |
2296 | int code16; |
2297 | ||
2298 | code16 = 0; | |
2299 | if (flag_16bit_code) | |
2300 | code16 = CODE16; | |
252b5132 RH |
2301 | |
2302 | if (i.prefix[DATA_PREFIX]) | |
2303 | { | |
2304 | insn_size += 1; | |
2305 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2306 | i.prefixes -= 1; | |
a217f122 | 2307 | code16 ^= CODE16; |
252b5132 | 2308 | } |
252b5132 | 2309 | |
a217f122 | 2310 | size = 4; |
252b5132 RH |
2311 | if (code16) |
2312 | size = 2; | |
2313 | } | |
2314 | ||
a217f122 | 2315 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2316 | as_warn (_("skipping prefixes on this instruction")); |
2317 | ||
2318 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2319 | { | |
2320 | insn_size += 1 + size; | |
2321 | p = frag_more (1 + size); | |
2322 | } | |
2323 | else | |
2324 | { | |
a217f122 AM |
2325 | /* opcode can be at most two bytes */ |
2326 | insn_size += 2 + size; | |
252b5132 RH |
2327 | p = frag_more (2 + size); |
2328 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2329 | } | |
2330 | *p++ = i.tm.base_opcode & 0xff; | |
2331 | ||
2f66722d | 2332 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
520dc8e8 | 2333 | i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); |
252b5132 RH |
2334 | } |
2335 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2336 | { | |
2337 | int size; | |
a217f122 AM |
2338 | int prefix; |
2339 | int code16; | |
252b5132 | 2340 | |
a217f122 AM |
2341 | code16 = 0; |
2342 | if (flag_16bit_code) | |
2343 | code16 = CODE16; | |
2344 | ||
2345 | prefix = 0; | |
2346 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2347 | { |
a217f122 | 2348 | prefix = 1; |
252b5132 | 2349 | i.prefixes -= 1; |
a217f122 | 2350 | code16 ^= CODE16; |
252b5132 | 2351 | } |
252b5132 RH |
2352 | |
2353 | size = 4; | |
252b5132 | 2354 | if (code16) |
f6af82bd | 2355 | size = 2; |
252b5132 | 2356 | |
a217f122 | 2357 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2358 | as_warn (_("skipping prefixes on this instruction")); |
2359 | ||
2360 | insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */ | |
2361 | p = frag_more (prefix + 1 + 2 + size); | |
2362 | if (prefix) | |
2363 | *p++ = DATA_PREFIX_OPCODE; | |
2364 | *p++ = i.tm.base_opcode; | |
520dc8e8 | 2365 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2366 | { |
847f7ad4 | 2367 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2368 | |
773f551c AM |
2369 | if (size == 2 |
2370 | && !fits_in_unsigned_word (n) | |
2371 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2372 | { |
2373 | as_bad (_("16-bit jump out of range")); | |
2374 | return; | |
2375 | } | |
847f7ad4 | 2376 | md_number_to_chars (p, n, size); |
252b5132 RH |
2377 | } |
2378 | else | |
2379 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 AM |
2380 | i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); |
2381 | if (i.op[0].imms->X_op != O_constant) | |
252b5132 RH |
2382 | as_bad (_("can't handle non absolute segment in `%s'"), |
2383 | i.tm.name); | |
520dc8e8 | 2384 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2385 | } |
2386 | else | |
2387 | { | |
2388 | /* Output normal instructions here. */ | |
2389 | unsigned char *q; | |
2390 | ||
2391 | /* The prefix bytes. */ | |
2392 | for (q = i.prefix; | |
2393 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2394 | q++) | |
2395 | { | |
2396 | if (*q) | |
2397 | { | |
2398 | insn_size += 1; | |
2399 | p = frag_more (1); | |
2400 | md_number_to_chars (p, (valueT) *q, 1); | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | /* Now the opcode; be careful about word order here! */ | |
2405 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2406 | { | |
2407 | insn_size += 1; | |
2408 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2409 | } | |
2410 | else if (fits_in_unsigned_word (i.tm.base_opcode)) | |
2411 | { | |
2412 | insn_size += 2; | |
2413 | p = frag_more (2); | |
2414 | /* put out high byte first: can't use md_number_to_chars! */ | |
2415 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2416 | *p = i.tm.base_opcode & 0xff; | |
2417 | } | |
2418 | else | |
2419 | { /* opcode is either 3 or 4 bytes */ | |
2420 | if (i.tm.base_opcode & 0xff000000) | |
2421 | { | |
2422 | insn_size += 4; | |
2423 | p = frag_more (4); | |
2424 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
2425 | } | |
2426 | else | |
2427 | { | |
2428 | insn_size += 3; | |
2429 | p = frag_more (3); | |
2430 | } | |
2431 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
2432 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2433 | *p = (i.tm.base_opcode) & 0xff; | |
2434 | } | |
2435 | ||
2436 | /* Now the modrm byte and sib byte (if present). */ | |
2437 | if (i.tm.opcode_modifier & Modrm) | |
2438 | { | |
2439 | insn_size += 1; | |
2440 | p = frag_more (1); | |
2441 | md_number_to_chars (p, | |
2442 | (valueT) (i.rm.regmem << 0 | |
2443 | | i.rm.reg << 3 | |
2444 | | i.rm.mode << 6), | |
2445 | 1); | |
2446 | /* If i.rm.regmem == ESP (4) | |
2447 | && i.rm.mode != (Register mode) | |
2448 | && not 16 bit | |
2449 | ==> need second modrm byte. */ | |
2450 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2451 | && i.rm.mode != 3 | |
2452 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2453 | { | |
2454 | insn_size += 1; | |
2455 | p = frag_more (1); | |
2456 | md_number_to_chars (p, | |
2457 | (valueT) (i.sib.base << 0 | |
2458 | | i.sib.index << 3 | |
2459 | | i.sib.scale << 6), | |
2460 | 1); | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | if (i.disp_operands) | |
2465 | { | |
2466 | register unsigned int n; | |
2467 | ||
2468 | for (n = 0; n < i.operands; n++) | |
2469 | { | |
520dc8e8 | 2470 | if (i.types[n] & Disp) |
252b5132 | 2471 | { |
520dc8e8 | 2472 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2473 | { |
847f7ad4 AM |
2474 | int size; |
2475 | offsetT val; | |
b4cac588 | 2476 | |
847f7ad4 | 2477 | size = 4; |
b4cac588 | 2478 | if (i.types[n] & (Disp8 | Disp16)) |
252b5132 | 2479 | { |
b4cac588 | 2480 | size = 2; |
b4cac588 | 2481 | if (i.types[n] & Disp8) |
847f7ad4 | 2482 | size = 1; |
252b5132 | 2483 | } |
847f7ad4 AM |
2484 | val = offset_in_range (i.op[n].disps->X_add_number, |
2485 | size); | |
b4cac588 AM |
2486 | insn_size += size; |
2487 | p = frag_more (size); | |
847f7ad4 | 2488 | md_number_to_chars (p, val, size); |
252b5132 | 2489 | } |
252b5132 | 2490 | else |
520dc8e8 AM |
2491 | { |
2492 | int size = 4; | |
2493 | ||
2494 | if (i.types[n] & Disp16) | |
2495 | size = 2; | |
2496 | ||
2497 | insn_size += size; | |
2498 | p = frag_more (size); | |
2499 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
2500 | i.op[n].disps, 0, | |
2501 | reloc (size, 0, i.disp_reloc[n])); | |
252b5132 RH |
2502 | } |
2503 | } | |
2504 | } | |
2505 | } /* end displacement output */ | |
2506 | ||
2507 | /* output immediate */ | |
2508 | if (i.imm_operands) | |
2509 | { | |
2510 | register unsigned int n; | |
2511 | ||
2512 | for (n = 0; n < i.operands; n++) | |
2513 | { | |
520dc8e8 | 2514 | if (i.types[n] & Imm) |
252b5132 | 2515 | { |
520dc8e8 | 2516 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 2517 | { |
847f7ad4 AM |
2518 | int size; |
2519 | offsetT val; | |
b4cac588 | 2520 | |
847f7ad4 | 2521 | size = 4; |
b4cac588 | 2522 | if (i.types[n] & (Imm8 | Imm8S | Imm16)) |
252b5132 | 2523 | { |
b4cac588 | 2524 | size = 2; |
b4cac588 | 2525 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 2526 | size = 1; |
252b5132 | 2527 | } |
847f7ad4 AM |
2528 | val = offset_in_range (i.op[n].imms->X_add_number, |
2529 | size); | |
b4cac588 AM |
2530 | insn_size += size; |
2531 | p = frag_more (size); | |
847f7ad4 | 2532 | md_number_to_chars (p, val, size); |
252b5132 RH |
2533 | } |
2534 | else | |
2535 | { /* not absolute_section */ | |
2536 | /* Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 2537 | non-absolute imms). Try to support other |
252b5132 | 2538 | sizes ... */ |
f6af82bd AM |
2539 | #ifdef BFD_ASSEMBLER |
2540 | enum bfd_reloc_code_real reloc_type; | |
2541 | #else | |
2542 | int reloc_type; | |
2543 | #endif | |
520dc8e8 | 2544 | int size = 4; |
252b5132 | 2545 | |
520dc8e8 | 2546 | if (i.types[n] & Imm16) |
252b5132 | 2547 | size = 2; |
520dc8e8 AM |
2548 | else if (i.types[n] & (Imm8 | Imm8S)) |
2549 | size = 1; | |
2550 | ||
252b5132 RH |
2551 | insn_size += size; |
2552 | p = frag_more (size); | |
f6af82bd | 2553 | reloc_type = reloc (size, 0, i.disp_reloc[0]); |
252b5132 | 2554 | #ifdef BFD_ASSEMBLER |
f6af82bd | 2555 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 2556 | && GOT_symbol |
520dc8e8 AM |
2557 | && GOT_symbol == i.op[n].imms->X_add_symbol |
2558 | && (i.op[n].imms->X_op == O_symbol | |
2559 | || (i.op[n].imms->X_op == O_add | |
49309057 | 2560 | && ((symbol_get_value_expression |
520dc8e8 | 2561 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
2562 | == O_subtract)))) |
2563 | { | |
f6af82bd | 2564 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 2565 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
2566 | } |
2567 | #endif | |
2568 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 2569 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
2570 | } |
2571 | } | |
2572 | } | |
2573 | } /* end immediate output */ | |
2574 | } | |
2575 | ||
2576 | #ifdef DEBUG386 | |
2577 | if (flag_debug) | |
2578 | { | |
2579 | pi (line, &i); | |
2580 | } | |
2581 | #endif /* DEBUG386 */ | |
2582 | } | |
2583 | } | |
2584 | \f | |
252b5132 RH |
2585 | static int i386_immediate PARAMS ((char *)); |
2586 | ||
2587 | static int | |
2588 | i386_immediate (imm_start) | |
2589 | char *imm_start; | |
2590 | { | |
2591 | char *save_input_line_pointer; | |
2592 | segT exp_seg = 0; | |
2593 | expressionS * exp; | |
2594 | ||
2595 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2596 | { | |
d0b47220 | 2597 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
2598 | return 0; |
2599 | } | |
2600 | ||
2601 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2602 | i.op[this_operand].imms = exp; |
252b5132 RH |
2603 | |
2604 | if (is_space_char (*imm_start)) | |
2605 | ++imm_start; | |
2606 | ||
2607 | save_input_line_pointer = input_line_pointer; | |
2608 | input_line_pointer = imm_start; | |
2609 | ||
2610 | #ifndef LEX_AT | |
24eab124 AM |
2611 | { |
2612 | /* | |
2613 | * We can have operands of the form | |
2614 | * <symbol>@GOTOFF+<nnn> | |
2615 | * Take the easy way out here and copy everything | |
2616 | * into a temporary buffer... | |
2617 | */ | |
2618 | register char *cp; | |
2619 | ||
2620 | cp = strchr (input_line_pointer, '@'); | |
2621 | if (cp != NULL) | |
2622 | { | |
2623 | char *tmpbuf; | |
2624 | int len = 0; | |
2625 | int first; | |
2626 | ||
2627 | /* GOT relocations are not supported in 16 bit mode */ | |
2628 | if (flag_16bit_code) | |
2629 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2630 | ||
2631 | if (GOT_symbol == NULL) | |
2632 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2633 | ||
2634 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2635 | { | |
2636 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2637 | len = 3; | |
2638 | } | |
2639 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2640 | { | |
2641 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2642 | len = 6; | |
2643 | } | |
2644 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2645 | { | |
2646 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2647 | len = 3; | |
2648 | } | |
2649 | else | |
d0b47220 | 2650 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2651 | |
2652 | /* Replace the relocation token with ' ', so that errors like | |
2653 | foo@GOTOFF1 will be detected. */ | |
2654 | first = cp - input_line_pointer; | |
2655 | tmpbuf = (char *) alloca (strlen(input_line_pointer)); | |
2656 | memcpy (tmpbuf, input_line_pointer, first); | |
2657 | tmpbuf[first] = ' '; | |
2658 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2659 | input_line_pointer = tmpbuf; | |
2660 | } | |
2661 | } | |
252b5132 RH |
2662 | #endif |
2663 | ||
2664 | exp_seg = expression (exp); | |
2665 | ||
83183c0c | 2666 | SKIP_WHITESPACE (); |
252b5132 | 2667 | if (*input_line_pointer) |
d0b47220 | 2668 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
2669 | |
2670 | input_line_pointer = save_input_line_pointer; | |
2671 | ||
2daf4fd8 | 2672 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 RH |
2673 | { |
2674 | /* missing or bad expr becomes absolute 0 */ | |
d0b47220 | 2675 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 2676 | imm_start); |
252b5132 RH |
2677 | exp->X_op = O_constant; |
2678 | exp->X_add_number = 0; | |
2679 | exp->X_add_symbol = (symbolS *) 0; | |
2680 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 2681 | } |
2daf4fd8 AM |
2682 | |
2683 | if (exp->X_op == O_constant) | |
252b5132 | 2684 | { |
726c5dcd | 2685 | i.types[this_operand] |= Imm32; /* Size it properly later. */ |
252b5132 | 2686 | } |
4c63da97 AM |
2687 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
2688 | else if ( | |
2689 | #ifdef BFD_ASSEMBLER | |
2690 | OUTPUT_FLAVOR == bfd_target_aout_flavour && | |
2691 | #endif | |
2692 | exp_seg != text_section | |
24eab124 AM |
2693 | && exp_seg != data_section |
2694 | && exp_seg != bss_section | |
2695 | && exp_seg != undefined_section | |
252b5132 | 2696 | #ifdef BFD_ASSEMBLER |
24eab124 | 2697 | && !bfd_is_com_section (exp_seg) |
252b5132 | 2698 | #endif |
24eab124 | 2699 | ) |
252b5132 | 2700 | { |
4c63da97 | 2701 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2702 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2703 | #else |
d0b47220 | 2704 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2705 | #endif |
252b5132 RH |
2706 | return 0; |
2707 | } | |
2708 | #endif | |
2709 | else | |
2710 | { | |
2711 | /* This is an address. The size of the address will be | |
24eab124 AM |
2712 | determined later, depending on destination register, |
2713 | suffix, or the default for the section. We exclude | |
2714 | Imm8S here so that `push $foo' and other instructions | |
2715 | with an Imm8S form will use Imm16 or Imm32. */ | |
252b5132 RH |
2716 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); |
2717 | } | |
2718 | ||
2719 | return 1; | |
2720 | } | |
2721 | ||
2722 | static int i386_scale PARAMS ((char *)); | |
2723 | ||
2724 | static int | |
2725 | i386_scale (scale) | |
2726 | char *scale; | |
2727 | { | |
2728 | if (!isdigit (*scale)) | |
2729 | goto bad_scale; | |
2730 | ||
2731 | switch (*scale) | |
2732 | { | |
2733 | case '0': | |
2734 | case '1': | |
2735 | i.log2_scale_factor = 0; | |
2736 | break; | |
2737 | case '2': | |
2738 | i.log2_scale_factor = 1; | |
2739 | break; | |
2740 | case '4': | |
2741 | i.log2_scale_factor = 2; | |
2742 | break; | |
2743 | case '8': | |
2744 | i.log2_scale_factor = 3; | |
2745 | break; | |
2746 | default: | |
2747 | bad_scale: | |
2748 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
24eab124 | 2749 | scale); |
252b5132 RH |
2750 | return 0; |
2751 | } | |
2752 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2753 | { | |
2754 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 2755 | 1 << i.log2_scale_factor); |
252b5132 RH |
2756 | #if SCALE1_WHEN_NO_INDEX |
2757 | i.log2_scale_factor = 0; | |
2758 | #endif | |
2759 | } | |
2760 | return 1; | |
2761 | } | |
2762 | ||
2763 | static int i386_displacement PARAMS ((char *, char *)); | |
2764 | ||
2765 | static int | |
2766 | i386_displacement (disp_start, disp_end) | |
2767 | char *disp_start; | |
2768 | char *disp_end; | |
2769 | { | |
2770 | register expressionS *exp; | |
2771 | segT exp_seg = 0; | |
2772 | char *save_input_line_pointer; | |
2773 | int bigdisp = Disp32; | |
2774 | ||
252b5132 RH |
2775 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2776 | bigdisp = Disp16; | |
2777 | i.types[this_operand] |= bigdisp; | |
2778 | ||
2779 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 2780 | i.op[this_operand].disps = exp; |
252b5132 RH |
2781 | i.disp_operands++; |
2782 | save_input_line_pointer = input_line_pointer; | |
2783 | input_line_pointer = disp_start; | |
2784 | END_STRING_AND_SAVE (disp_end); | |
2785 | ||
2786 | #ifndef GCC_ASM_O_HACK | |
2787 | #define GCC_ASM_O_HACK 0 | |
2788 | #endif | |
2789 | #if GCC_ASM_O_HACK | |
2790 | END_STRING_AND_SAVE (disp_end + 1); | |
2791 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 2792 | && displacement_string_end[-1] == '+') |
252b5132 RH |
2793 | { |
2794 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
2795 | constraint within gcc asm statements. |
2796 | For instance: | |
2797 | ||
2798 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2799 | __asm__ __volatile__ ( \ | |
2800 | "movw %w2,%0\n\t" \ | |
2801 | "movw %w1,2+%0\n\t" \ | |
2802 | "rorl $16,%1\n\t" \ | |
2803 | "movb %b1,4+%0\n\t" \ | |
2804 | "movb %4,5+%0\n\t" \ | |
2805 | "movb $0,6+%0\n\t" \ | |
2806 | "movb %h1,7+%0\n\t" \ | |
2807 | "rorl $16,%1" \ | |
2808 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2809 | ||
2810 | This works great except that the output assembler ends | |
2811 | up looking a bit weird if it turns out that there is | |
2812 | no offset. You end up producing code that looks like: | |
2813 | ||
2814 | #APP | |
2815 | movw $235,(%eax) | |
2816 | movw %dx,2+(%eax) | |
2817 | rorl $16,%edx | |
2818 | movb %dl,4+(%eax) | |
2819 | movb $137,5+(%eax) | |
2820 | movb $0,6+(%eax) | |
2821 | movb %dh,7+(%eax) | |
2822 | rorl $16,%edx | |
2823 | #NO_APP | |
2824 | ||
2825 | So here we provide the missing zero. | |
2826 | */ | |
2827 | ||
2828 | *displacement_string_end = '0'; | |
252b5132 RH |
2829 | } |
2830 | #endif | |
2831 | #ifndef LEX_AT | |
24eab124 AM |
2832 | { |
2833 | /* | |
2834 | * We can have operands of the form | |
2835 | * <symbol>@GOTOFF+<nnn> | |
2836 | * Take the easy way out here and copy everything | |
2837 | * into a temporary buffer... | |
2838 | */ | |
2839 | register char *cp; | |
2840 | ||
2841 | cp = strchr (input_line_pointer, '@'); | |
2842 | if (cp != NULL) | |
2843 | { | |
2844 | char *tmpbuf; | |
2845 | int len = 0; | |
2846 | int first; | |
2847 | ||
2848 | /* GOT relocations are not supported in 16 bit mode */ | |
2849 | if (flag_16bit_code) | |
2850 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2851 | ||
2852 | if (GOT_symbol == NULL) | |
2853 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2854 | ||
2855 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2856 | { | |
2857 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2858 | len = 3; | |
2859 | } | |
2860 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2861 | { | |
2862 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2863 | len = 6; | |
2864 | } | |
2865 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2866 | { | |
2867 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2868 | len = 3; | |
2869 | } | |
2870 | else | |
d0b47220 | 2871 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2872 | |
2873 | /* Replace the relocation token with ' ', so that errors like | |
2874 | foo@GOTOFF1 will be detected. */ | |
2875 | first = cp - input_line_pointer; | |
2876 | tmpbuf = (char *) alloca (strlen(input_line_pointer)); | |
2877 | memcpy (tmpbuf, input_line_pointer, first); | |
2878 | tmpbuf[first] = ' '; | |
2879 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2880 | input_line_pointer = tmpbuf; | |
2881 | } | |
2882 | } | |
252b5132 RH |
2883 | #endif |
2884 | ||
24eab124 | 2885 | exp_seg = expression (exp); |
252b5132 RH |
2886 | |
2887 | #ifdef BFD_ASSEMBLER | |
24eab124 AM |
2888 | /* We do this to make sure that the section symbol is in |
2889 | the symbol table. We will ultimately change the relocation | |
2890 | to be relative to the beginning of the section */ | |
2891 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) | |
2892 | { | |
2893 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2894 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2895 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
2896 | assert (exp->X_op == O_symbol); | |
2897 | exp->X_op = O_subtract; | |
2898 | exp->X_op_symbol = GOT_symbol; | |
2899 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2900 | } | |
252b5132 RH |
2901 | #endif |
2902 | ||
24eab124 AM |
2903 | SKIP_WHITESPACE (); |
2904 | if (*input_line_pointer) | |
d0b47220 | 2905 | as_bad (_("ignoring junk `%s' after expression"), |
24eab124 | 2906 | input_line_pointer); |
252b5132 | 2907 | #if GCC_ASM_O_HACK |
24eab124 | 2908 | RESTORE_END_STRING (disp_end + 1); |
252b5132 | 2909 | #endif |
24eab124 AM |
2910 | RESTORE_END_STRING (disp_end); |
2911 | input_line_pointer = save_input_line_pointer; | |
2912 | ||
2daf4fd8 AM |
2913 | if (exp->X_op == O_absent || exp->X_op == O_big) |
2914 | { | |
2915 | /* missing or bad expr becomes absolute 0 */ | |
d0b47220 | 2916 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
2917 | disp_start); |
2918 | exp->X_op = O_constant; | |
2919 | exp->X_add_number = 0; | |
2920 | exp->X_add_symbol = (symbolS *) 0; | |
2921 | exp->X_op_symbol = (symbolS *) 0; | |
2922 | } | |
2923 | ||
24eab124 AM |
2924 | if (exp->X_op == O_constant) |
2925 | { | |
773f551c AM |
2926 | if (i.types[this_operand] & Disp16) |
2927 | { | |
2928 | /* We know this operand is at most 16 bits, so convert to a | |
2929 | signed 16 bit number before trying to see whether it will | |
2930 | fit in an even smaller size. */ | |
2931 | exp->X_add_number = | |
2932 | (((exp->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
2933 | } | |
24eab124 AM |
2934 | if (fits_in_signed_byte (exp->X_add_number)) |
2935 | i.types[this_operand] |= Disp8; | |
2936 | } | |
4c63da97 AM |
2937 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
2938 | else if ( | |
2939 | #ifdef BFD_ASSEMBLER | |
2940 | OUTPUT_FLAVOR == bfd_target_aout_flavour && | |
2941 | #endif | |
2942 | exp_seg != text_section | |
24eab124 AM |
2943 | && exp_seg != data_section |
2944 | && exp_seg != bss_section | |
2945 | && exp_seg != undefined_section) | |
2946 | { | |
4c63da97 | 2947 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2948 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2949 | #else |
d0b47220 | 2950 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2951 | #endif |
24eab124 AM |
2952 | return 0; |
2953 | } | |
252b5132 RH |
2954 | #endif |
2955 | return 1; | |
2956 | } | |
2957 | ||
2958 | static int i386_operand_modifier PARAMS ((char **, int)); | |
2959 | ||
2960 | static int | |
2961 | i386_operand_modifier (op_string, got_a_float) | |
2962 | char **op_string; | |
2963 | int got_a_float; | |
2964 | { | |
24eab124 AM |
2965 | if (!strncasecmp (*op_string, "BYTE PTR", 8)) |
2966 | { | |
2967 | i.suffix = BYTE_MNEM_SUFFIX; | |
2968 | *op_string += 8; | |
2969 | return BYTE_PTR; | |
252b5132 | 2970 | |
24eab124 AM |
2971 | } |
2972 | else if (!strncasecmp (*op_string, "WORD PTR", 8)) | |
2973 | { | |
cc5ca5ce AM |
2974 | if (got_a_float == 2) /* "fi..." */ |
2975 | i.suffix = SHORT_MNEM_SUFFIX; | |
2976 | else | |
2977 | i.suffix = WORD_MNEM_SUFFIX; | |
24eab124 AM |
2978 | *op_string += 8; |
2979 | return WORD_PTR; | |
2980 | } | |
252b5132 | 2981 | |
24eab124 AM |
2982 | else if (!strncasecmp (*op_string, "DWORD PTR", 9)) |
2983 | { | |
cc5ca5ce | 2984 | if (got_a_float == 1) /* "f..." */ |
24eab124 AM |
2985 | i.suffix = SHORT_MNEM_SUFFIX; |
2986 | else | |
add0c677 | 2987 | i.suffix = LONG_MNEM_SUFFIX; |
24eab124 AM |
2988 | *op_string += 9; |
2989 | return DWORD_PTR; | |
2990 | } | |
252b5132 | 2991 | |
24eab124 AM |
2992 | else if (!strncasecmp (*op_string, "QWORD PTR", 9)) |
2993 | { | |
add0c677 | 2994 | i.suffix = DWORD_MNEM_SUFFIX; |
24eab124 AM |
2995 | *op_string += 9; |
2996 | return QWORD_PTR; | |
2997 | } | |
252b5132 | 2998 | |
24eab124 AM |
2999 | else if (!strncasecmp (*op_string, "XWORD PTR", 9)) |
3000 | { | |
3001 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
3002 | *op_string += 9; | |
3003 | return XWORD_PTR; | |
3004 | } | |
252b5132 | 3005 | |
24eab124 AM |
3006 | else if (!strncasecmp (*op_string, "SHORT", 5)) |
3007 | { | |
3008 | *op_string += 5; | |
3009 | return SHORT; | |
3010 | } | |
252b5132 | 3011 | |
24eab124 AM |
3012 | else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12)) |
3013 | { | |
3014 | *op_string += 12; | |
3015 | return OFFSET_FLAT; | |
3016 | } | |
252b5132 | 3017 | |
24eab124 AM |
3018 | else if (!strncasecmp (*op_string, "FLAT", 4)) |
3019 | { | |
3020 | *op_string += 4; | |
3021 | return FLAT; | |
3022 | } | |
252b5132 | 3023 | |
24eab124 | 3024 | else return NONE_FOUND; |
c3332e24 | 3025 | } |
252b5132 RH |
3026 | |
3027 | static char * build_displacement_string PARAMS ((int, char *)); | |
3028 | ||
3029 | static char * | |
3030 | build_displacement_string (initial_disp, op_string) | |
3031 | int initial_disp; | |
3032 | char *op_string; | |
3033 | { | |
3034 | char *temp_string = (char *) malloc (strlen (op_string) + 1); | |
3035 | char *end_of_operand_string; | |
3036 | char *tc; | |
3037 | char *temp_disp; | |
3038 | ||
3039 | temp_string[0] = '\0'; | |
3040 | tc = end_of_operand_string = strchr (op_string, '['); | |
36bf8ab9 | 3041 | if (initial_disp && !end_of_operand_string) |
252b5132 RH |
3042 | { |
3043 | strcpy (temp_string, op_string); | |
36bf8ab9 | 3044 | return temp_string; |
252b5132 RH |
3045 | } |
3046 | ||
3047 | /* Build the whole displacement string */ | |
3048 | if (initial_disp) | |
3049 | { | |
3050 | strncpy (temp_string, op_string, end_of_operand_string - op_string); | |
3051 | temp_string[end_of_operand_string - op_string] = '\0'; | |
3052 | temp_disp = tc; | |
3053 | } | |
c3332e24 | 3054 | else |
252b5132 RH |
3055 | temp_disp = op_string; |
3056 | ||
3057 | while (*temp_disp != '\0') | |
3058 | { | |
af6bdddf | 3059 | char *end_op; |
252b5132 RH |
3060 | int add_minus = (*temp_disp == '-'); |
3061 | ||
3062 | if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[') | |
24eab124 | 3063 | temp_disp++; |
252b5132 RH |
3064 | |
3065 | if (is_space_char (*temp_disp)) | |
24eab124 | 3066 | temp_disp++; |
252b5132 RH |
3067 | |
3068 | /* Don't consider registers */ | |
af6bdddf AM |
3069 | if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg) |
3070 | && parse_register (temp_disp, &end_op)) ) | |
24eab124 AM |
3071 | { |
3072 | char *string_start = temp_disp; | |
3073 | ||
3074 | while (*temp_disp != ']' | |
3075 | && *temp_disp != '+' | |
3076 | && *temp_disp != '-' | |
3077 | && *temp_disp != '*') | |
3078 | ++temp_disp; | |
3079 | ||
3080 | if (add_minus) | |
3081 | strcat (temp_string, "-"); | |
3082 | else | |
3083 | strcat (temp_string, "+"); | |
3084 | ||
3085 | strncat (temp_string, string_start, temp_disp - string_start); | |
3086 | if (*temp_disp == '+' || *temp_disp == '-') | |
3087 | --temp_disp; | |
3088 | } | |
252b5132 RH |
3089 | |
3090 | while (*temp_disp != '\0' | |
24eab124 AM |
3091 | && *temp_disp != '+' |
3092 | && *temp_disp != '-') | |
3093 | ++temp_disp; | |
252b5132 RH |
3094 | } |
3095 | ||
3096 | return temp_string; | |
3097 | } | |
3098 | ||
3099 | static int i386_parse_seg PARAMS ((char *)); | |
3100 | ||
3101 | static int | |
3102 | i386_parse_seg (op_string) | |
3103 | char *op_string; | |
3104 | { | |
3105 | if (is_space_char (*op_string)) | |
3106 | ++op_string; | |
3107 | ||
3108 | /* Should be one of es, cs, ss, ds fs or gs */ | |
3109 | switch (*op_string++) | |
3110 | { | |
3111 | case 'e': | |
3112 | i.seg[i.mem_operands] = &es; | |
3113 | break; | |
3114 | case 'c': | |
3115 | i.seg[i.mem_operands] = &cs; | |
3116 | break; | |
3117 | case 's': | |
3118 | i.seg[i.mem_operands] = &ss; | |
3119 | break; | |
3120 | case 'd': | |
3121 | i.seg[i.mem_operands] = &ds; | |
3122 | break; | |
3123 | case 'f': | |
3124 | i.seg[i.mem_operands] = &fs; | |
3125 | break; | |
3126 | case 'g': | |
3127 | i.seg[i.mem_operands] = &gs; | |
3128 | break; | |
3129 | default: | |
3130 | as_bad (_("bad segment name `%s'"), op_string); | |
3131 | return 0; | |
3132 | } | |
3133 | ||
3134 | if (*op_string++ != 's') | |
3135 | { | |
24eab124 AM |
3136 | as_bad (_("bad segment name `%s'"), op_string); |
3137 | return 0; | |
252b5132 RH |
3138 | } |
3139 | ||
3140 | if (is_space_char (*op_string)) | |
3141 | ++op_string; | |
3142 | ||
3143 | if (*op_string != ':') | |
3144 | { | |
24eab124 AM |
3145 | as_bad (_("bad segment name `%s'"), op_string); |
3146 | return 0; | |
252b5132 RH |
3147 | } |
3148 | ||
c3332e24 AM |
3149 | return 1; |
3150 | ||
252b5132 RH |
3151 | } |
3152 | ||
eecb386c | 3153 | static int i386_index_check PARAMS((const char *)); |
252b5132 | 3154 | |
eecb386c AM |
3155 | /* Make sure the memory operand we've been dealt is valid. |
3156 | Returns 1 on success, 0 on a failure. | |
3157 | */ | |
252b5132 | 3158 | static int |
eecb386c AM |
3159 | i386_index_check (operand_string) |
3160 | const char *operand_string; | |
252b5132 | 3161 | { |
24eab124 | 3162 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3163 | int fudged = 0; |
3164 | ||
24eab124 AM |
3165 | tryprefix: |
3166 | #endif | |
d0b47220 | 3167 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) |
24eab124 | 3168 | /* 16 bit mode checks */ |
d0b47220 AM |
3169 | ? ((i.base_reg |
3170 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3171 | != (Reg16|BaseIndex))) | |
3172 | || (i.index_reg | |
3173 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3174 | != (Reg16|BaseIndex)) | |
3175 | || ! (i.base_reg | |
3176 | && i.base_reg->reg_num < 6 | |
3177 | && i.index_reg->reg_num >= 6 | |
3178 | && i.log2_scale_factor == 0)))) | |
24eab124 | 3179 | /* 32 bit mode checks */ |
d0b47220 AM |
3180 | : ((i.base_reg |
3181 | && (i.base_reg->reg_type & Reg32) == 0) | |
3182 | || (i.index_reg | |
3183 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3184 | != (Reg32|BaseIndex))))) | |
24eab124 AM |
3185 | { |
3186 | #if INFER_ADDR_PREFIX | |
eecb386c | 3187 | if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') |
24eab124 AM |
3188 | { |
3189 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3190 | i.prefixes += 1; | |
b23bac36 AM |
3191 | /* Change the size of any displacement too. At most one of |
3192 | Disp16 or Disp32 is set. | |
3193 | FIXME. There doesn't seem to be any real need for separate | |
3194 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
3195 | Removing them would probably clean up the code quite a lot. | |
3196 | */ | |
3197 | if (i.types[this_operand] & (Disp16|Disp32)) | |
3198 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3199 | fudged = 1; |
24eab124 AM |
3200 | goto tryprefix; |
3201 | } | |
eecb386c AM |
3202 | if (fudged) |
3203 | as_bad (_("`%s' is not a valid base/index expression"), | |
3204 | operand_string); | |
3205 | else | |
c388dee8 | 3206 | #endif |
eecb386c AM |
3207 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3208 | operand_string, | |
3209 | flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); | |
3210 | return 0; | |
24eab124 AM |
3211 | } |
3212 | return 1; | |
3213 | } | |
252b5132 | 3214 | |
24eab124 AM |
3215 | static int i386_intel_memory_operand PARAMS ((char *)); |
3216 | ||
3217 | static int | |
3218 | i386_intel_memory_operand (operand_string) | |
3219 | char *operand_string; | |
3220 | { | |
3221 | char *op_string = operand_string; | |
252b5132 RH |
3222 | char *end_of_operand_string; |
3223 | ||
24eab124 AM |
3224 | if ((i.mem_operands == 1 |
3225 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3226 | || i.mem_operands == 2) | |
252b5132 | 3227 | { |
24eab124 AM |
3228 | as_bad (_("too many memory references for `%s'"), |
3229 | current_templates->start->name); | |
3230 | return 0; | |
252b5132 RH |
3231 | } |
3232 | ||
36bf8ab9 | 3233 | /* First check for a segment override. */ |
252b5132 RH |
3234 | if (*op_string != '[') |
3235 | { | |
3236 | char *end_seg; | |
252b5132 RH |
3237 | |
3238 | end_seg = strchr (op_string, ':'); | |
3239 | if (end_seg) | |
24eab124 AM |
3240 | { |
3241 | if (!i386_parse_seg (op_string)) | |
3242 | return 0; | |
3243 | op_string = end_seg + 1; | |
3244 | } | |
36bf8ab9 | 3245 | } |
252b5132 | 3246 | |
36bf8ab9 AM |
3247 | /* Look for displacement preceding open bracket */ |
3248 | if (*op_string != '[') | |
3249 | { | |
3250 | char *temp_string; | |
24eab124 | 3251 | |
36bf8ab9 | 3252 | if (i.disp_operands) |
24eab124 | 3253 | return 0; |
252b5132 | 3254 | |
36bf8ab9 AM |
3255 | temp_string = build_displacement_string (true, op_string); |
3256 | ||
3257 | if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) | |
3258 | { | |
3259 | free (temp_string); | |
3260 | return 0; | |
3261 | } | |
3262 | free (temp_string); | |
3263 | ||
252b5132 RH |
3264 | end_of_operand_string = strchr (op_string, '['); |
3265 | if (!end_of_operand_string) | |
24eab124 | 3266 | end_of_operand_string = op_string + strlen (op_string); |
252b5132 RH |
3267 | |
3268 | if (is_space_char (*end_of_operand_string)) | |
24eab124 | 3269 | --end_of_operand_string; |
252b5132 RH |
3270 | |
3271 | op_string = end_of_operand_string; | |
24eab124 | 3272 | } |
252b5132 RH |
3273 | |
3274 | if (*op_string == '[') | |
3275 | { | |
3276 | ++op_string; | |
3277 | ||
3278 | /* Pick off each component and figure out where it belongs */ | |
3279 | ||
3280 | end_of_operand_string = op_string; | |
3281 | ||
3282 | while (*op_string != ']') | |
24eab124 | 3283 | { |
af6bdddf AM |
3284 | const reg_entry *temp_reg; |
3285 | char *end_op; | |
3286 | char *temp_string; | |
24eab124 AM |
3287 | |
3288 | while (*end_of_operand_string != '+' | |
3289 | && *end_of_operand_string != '-' | |
3290 | && *end_of_operand_string != '*' | |
3291 | && *end_of_operand_string != ']') | |
3292 | end_of_operand_string++; | |
3293 | ||
af6bdddf AM |
3294 | temp_string = op_string; |
3295 | if (*temp_string == '+') | |
24eab124 | 3296 | { |
af6bdddf | 3297 | ++temp_string; |
24eab124 AM |
3298 | if (is_space_char (*temp_string)) |
3299 | ++temp_string; | |
24eab124 AM |
3300 | } |
3301 | ||
af6bdddf AM |
3302 | if ((*temp_string == REGISTER_PREFIX || allow_naked_reg) |
3303 | && (temp_reg = parse_register (temp_string, &end_op)) != NULL) | |
24eab124 | 3304 | { |
24eab124 AM |
3305 | if (i.base_reg == NULL) |
3306 | i.base_reg = temp_reg; | |
3307 | else | |
3308 | i.index_reg = temp_reg; | |
3309 | ||
3310 | i.types[this_operand] |= BaseIndex; | |
24eab124 | 3311 | } |
af6bdddf | 3312 | else if (*temp_string == REGISTER_PREFIX) |
24eab124 | 3313 | { |
af6bdddf AM |
3314 | as_bad (_("bad register name `%s'"), temp_string); |
3315 | return 0; | |
3316 | } | |
3317 | else if (is_digit_char (*op_string) | |
3318 | || *op_string == '+' || *op_string == '-') | |
3319 | { | |
36bf8ab9 AM |
3320 | char *temp_str; |
3321 | ||
3322 | if (i.disp_operands != 0) | |
3323 | return 0; | |
3324 | ||
af6bdddf | 3325 | temp_string = build_displacement_string (false, op_string); |
24eab124 | 3326 | |
36bf8ab9 AM |
3327 | temp_str = temp_string; |
3328 | if (*temp_str == '+') | |
3329 | ++temp_str; | |
24eab124 | 3330 | |
36bf8ab9 AM |
3331 | if (!i386_displacement (temp_str, temp_str + strlen (temp_str))) |
3332 | { | |
3333 | free (temp_string); | |
3334 | return 0; | |
3335 | } | |
3336 | free (temp_string); | |
24eab124 AM |
3337 | |
3338 | ++op_string; | |
3339 | end_of_operand_string = op_string; | |
3340 | while (*end_of_operand_string != ']' | |
3341 | && *end_of_operand_string != '+' | |
3342 | && *end_of_operand_string != '-' | |
3343 | && *end_of_operand_string != '*') | |
3344 | ++end_of_operand_string; | |
3345 | } | |
3346 | else if (*op_string == '*') | |
3347 | { | |
3348 | ++op_string; | |
3349 | ||
3350 | if (i.base_reg && !i.index_reg) | |
3351 | { | |
3352 | i.index_reg = i.base_reg; | |
3353 | i.base_reg = 0; | |
3354 | } | |
3355 | ||
3356 | if (!i386_scale (op_string)) | |
3357 | return 0; | |
3358 | } | |
3359 | op_string = end_of_operand_string; | |
3360 | ++end_of_operand_string; | |
3361 | } | |
3362 | } | |
3363 | ||
eecb386c AM |
3364 | if (i386_index_check (operand_string) == 0) |
3365 | return 0; | |
252b5132 | 3366 | |
24eab124 | 3367 | i.mem_operands++; |
252b5132 RH |
3368 | return 1; |
3369 | } | |
3370 | ||
252b5132 RH |
3371 | static int |
3372 | i386_intel_operand (operand_string, got_a_float) | |
3373 | char *operand_string; | |
3374 | int got_a_float; | |
3375 | { | |
af6bdddf AM |
3376 | const reg_entry * r; |
3377 | char *end_op; | |
252b5132 RH |
3378 | char *op_string = operand_string; |
3379 | ||
3380 | int operand_modifier = i386_operand_modifier (&op_string, got_a_float); | |
3381 | if (is_space_char (*op_string)) | |
3382 | ++op_string; | |
3383 | ||
3384 | switch (operand_modifier) | |
3385 | { | |
3386 | case BYTE_PTR: | |
3387 | case WORD_PTR: | |
3388 | case DWORD_PTR: | |
3389 | case QWORD_PTR: | |
3390 | case XWORD_PTR: | |
252b5132 | 3391 | if (!i386_intel_memory_operand (op_string)) |
24eab124 | 3392 | return 0; |
252b5132 RH |
3393 | break; |
3394 | ||
3395 | case FLAT: | |
252b5132 RH |
3396 | case OFFSET_FLAT: |
3397 | if (!i386_immediate (op_string)) | |
24eab124 | 3398 | return 0; |
252b5132 RH |
3399 | break; |
3400 | ||
3401 | case SHORT: | |
252b5132 | 3402 | case NONE_FOUND: |
c3332e24 AM |
3403 | /* Should be register or immediate */ |
3404 | if (is_digit_char (*op_string) | |
3405 | && strchr (op_string, '[') == 0) | |
3406 | { | |
3407 | if (!i386_immediate (op_string)) | |
3408 | return 0; | |
3409 | } | |
af6bdddf AM |
3410 | else if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3411 | && (r = parse_register (op_string, &end_op)) != NULL) | |
c3332e24 | 3412 | { |
c3332e24 AM |
3413 | /* Check for a segment override by searching for ':' after a |
3414 | segment register. */ | |
3415 | op_string = end_op; | |
3416 | if (is_space_char (*op_string)) | |
3417 | ++op_string; | |
3418 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3419 | { | |
3420 | switch (r->reg_num) | |
3421 | { | |
3422 | case 0: | |
3423 | i.seg[i.mem_operands] = &es; | |
3424 | break; | |
3425 | case 1: | |
3426 | i.seg[i.mem_operands] = &cs; | |
3427 | break; | |
3428 | case 2: | |
3429 | i.seg[i.mem_operands] = &ss; | |
3430 | break; | |
3431 | case 3: | |
3432 | i.seg[i.mem_operands] = &ds; | |
3433 | break; | |
3434 | case 4: | |
3435 | i.seg[i.mem_operands] = &fs; | |
3436 | break; | |
3437 | case 5: | |
3438 | i.seg[i.mem_operands] = &gs; | |
3439 | break; | |
3440 | } | |
252b5132 | 3441 | |
c3332e24 AM |
3442 | } |
3443 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3444 | i.op[this_operand].regs = r; |
c3332e24 AM |
3445 | i.reg_operands++; |
3446 | } | |
af6bdddf | 3447 | else if (*op_string == REGISTER_PREFIX) |
c3332e24 | 3448 | { |
af6bdddf AM |
3449 | as_bad (_("bad register name `%s'"), op_string); |
3450 | return 0; | |
c3332e24 | 3451 | } |
af6bdddf AM |
3452 | else if (!i386_intel_memory_operand (op_string)) |
3453 | return 0; | |
3454 | ||
c3332e24 | 3455 | break; |
c3332e24 | 3456 | } /* end switch */ |
24eab124 | 3457 | |
252b5132 RH |
3458 | return 1; |
3459 | } | |
3460 | ||
3461 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
3462 | on error. */ | |
3463 | ||
252b5132 RH |
3464 | static int |
3465 | i386_operand (operand_string) | |
3466 | char *operand_string; | |
3467 | { | |
af6bdddf AM |
3468 | const reg_entry *r; |
3469 | char *end_op; | |
24eab124 | 3470 | char *op_string = operand_string; |
252b5132 | 3471 | |
24eab124 | 3472 | if (is_space_char (*op_string)) |
252b5132 RH |
3473 | ++op_string; |
3474 | ||
24eab124 AM |
3475 | /* We check for an absolute prefix (differentiating, |
3476 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ | |
3477 | if (*op_string == ABSOLUTE_PREFIX) | |
3478 | { | |
3479 | ++op_string; | |
3480 | if (is_space_char (*op_string)) | |
3481 | ++op_string; | |
3482 | i.types[this_operand] |= JumpAbsolute; | |
3483 | } | |
252b5132 | 3484 | |
24eab124 | 3485 | /* Check if operand is a register. */ |
af6bdddf AM |
3486 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3487 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3488 | { |
24eab124 AM |
3489 | /* Check for a segment override by searching for ':' after a |
3490 | segment register. */ | |
3491 | op_string = end_op; | |
3492 | if (is_space_char (*op_string)) | |
3493 | ++op_string; | |
3494 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3495 | { | |
3496 | switch (r->reg_num) | |
3497 | { | |
3498 | case 0: | |
3499 | i.seg[i.mem_operands] = &es; | |
3500 | break; | |
3501 | case 1: | |
3502 | i.seg[i.mem_operands] = &cs; | |
3503 | break; | |
3504 | case 2: | |
3505 | i.seg[i.mem_operands] = &ss; | |
3506 | break; | |
3507 | case 3: | |
3508 | i.seg[i.mem_operands] = &ds; | |
3509 | break; | |
3510 | case 4: | |
3511 | i.seg[i.mem_operands] = &fs; | |
3512 | break; | |
3513 | case 5: | |
3514 | i.seg[i.mem_operands] = &gs; | |
3515 | break; | |
3516 | } | |
252b5132 | 3517 | |
24eab124 | 3518 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3519 | ++op_string; |
3520 | if (is_space_char (*op_string)) | |
24eab124 | 3521 | ++op_string; |
252b5132 | 3522 | |
24eab124 AM |
3523 | if (!is_digit_char (*op_string) |
3524 | && !is_identifier_char (*op_string) | |
3525 | && *op_string != '(' | |
3526 | && *op_string != ABSOLUTE_PREFIX) | |
3527 | { | |
3528 | as_bad (_("bad memory operand `%s'"), op_string); | |
3529 | return 0; | |
3530 | } | |
3531 | /* Handle case of %es:*foo. */ | |
3532 | if (*op_string == ABSOLUTE_PREFIX) | |
3533 | { | |
3534 | ++op_string; | |
3535 | if (is_space_char (*op_string)) | |
3536 | ++op_string; | |
3537 | i.types[this_operand] |= JumpAbsolute; | |
3538 | } | |
3539 | goto do_memory_reference; | |
3540 | } | |
3541 | if (*op_string) | |
3542 | { | |
d0b47220 | 3543 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3544 | return 0; |
3545 | } | |
3546 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3547 | i.op[this_operand].regs = r; |
24eab124 AM |
3548 | i.reg_operands++; |
3549 | } | |
af6bdddf AM |
3550 | else if (*op_string == REGISTER_PREFIX) |
3551 | { | |
3552 | as_bad (_("bad register name `%s'"), op_string); | |
3553 | return 0; | |
3554 | } | |
24eab124 AM |
3555 | else if (*op_string == IMMEDIATE_PREFIX) |
3556 | { /* ... or an immediate */ | |
3557 | ++op_string; | |
3558 | if (i.types[this_operand] & JumpAbsolute) | |
3559 | { | |
d0b47220 | 3560 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3561 | return 0; |
3562 | } | |
3563 | if (!i386_immediate (op_string)) | |
3564 | return 0; | |
3565 | } | |
3566 | else if (is_digit_char (*op_string) | |
3567 | || is_identifier_char (*op_string) | |
3568 | || *op_string == '(' ) | |
3569 | { | |
3570 | /* This is a memory reference of some sort. */ | |
af6bdddf | 3571 | char *base_string; |
252b5132 | 3572 | |
24eab124 | 3573 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3574 | char *displacement_string_start; |
3575 | char *displacement_string_end; | |
252b5132 | 3576 | |
24eab124 | 3577 | do_memory_reference: |
24eab124 AM |
3578 | if ((i.mem_operands == 1 |
3579 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3580 | || i.mem_operands == 2) | |
3581 | { | |
3582 | as_bad (_("too many memory references for `%s'"), | |
3583 | current_templates->start->name); | |
3584 | return 0; | |
3585 | } | |
252b5132 | 3586 | |
24eab124 AM |
3587 | /* Check for base index form. We detect the base index form by |
3588 | looking for an ')' at the end of the operand, searching | |
3589 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3590 | after the '('. */ | |
af6bdddf | 3591 | base_string = op_string + strlen (op_string); |
c3332e24 | 3592 | |
af6bdddf AM |
3593 | --base_string; |
3594 | if (is_space_char (*base_string)) | |
3595 | --base_string; | |
252b5132 | 3596 | |
af6bdddf AM |
3597 | /* If we only have a displacement, set-up for it to be parsed later. */ |
3598 | displacement_string_start = op_string; | |
3599 | displacement_string_end = base_string + 1; | |
252b5132 | 3600 | |
24eab124 AM |
3601 | if (*base_string == ')') |
3602 | { | |
af6bdddf | 3603 | char *temp_string; |
24eab124 AM |
3604 | unsigned int parens_balanced = 1; |
3605 | /* We've already checked that the number of left & right ()'s are | |
3606 | equal, so this loop will not be infinite. */ | |
3607 | do | |
3608 | { | |
3609 | base_string--; | |
3610 | if (*base_string == ')') | |
3611 | parens_balanced++; | |
3612 | if (*base_string == '(') | |
3613 | parens_balanced--; | |
3614 | } | |
3615 | while (parens_balanced); | |
c3332e24 | 3616 | |
af6bdddf | 3617 | temp_string = base_string; |
c3332e24 | 3618 | |
24eab124 | 3619 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3620 | ++base_string; |
3621 | if (is_space_char (*base_string)) | |
24eab124 | 3622 | ++base_string; |
252b5132 | 3623 | |
af6bdddf AM |
3624 | if (*base_string == ',' |
3625 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3626 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3627 | { |
af6bdddf | 3628 | displacement_string_end = temp_string; |
252b5132 | 3629 | |
af6bdddf | 3630 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3631 | |
af6bdddf | 3632 | if (i.base_reg) |
24eab124 | 3633 | { |
24eab124 AM |
3634 | base_string = end_op; |
3635 | if (is_space_char (*base_string)) | |
3636 | ++base_string; | |
af6bdddf AM |
3637 | } |
3638 | ||
3639 | /* There may be an index reg or scale factor here. */ | |
3640 | if (*base_string == ',') | |
3641 | { | |
3642 | ++base_string; | |
3643 | if (is_space_char (*base_string)) | |
3644 | ++base_string; | |
3645 | ||
3646 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3647 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3648 | { |
af6bdddf | 3649 | base_string = end_op; |
24eab124 AM |
3650 | if (is_space_char (*base_string)) |
3651 | ++base_string; | |
af6bdddf AM |
3652 | if (*base_string == ',') |
3653 | { | |
3654 | ++base_string; | |
3655 | if (is_space_char (*base_string)) | |
3656 | ++base_string; | |
3657 | } | |
3658 | else if (*base_string != ')' ) | |
3659 | { | |
3660 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3661 | operand_string); | |
3662 | return 0; | |
3663 | } | |
24eab124 | 3664 | } |
af6bdddf | 3665 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3666 | { |
af6bdddf | 3667 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3668 | return 0; |
3669 | } | |
252b5132 | 3670 | |
af6bdddf AM |
3671 | /* Check for scale factor. */ |
3672 | if (isdigit ((unsigned char) *base_string)) | |
3673 | { | |
3674 | if (!i386_scale (base_string)) | |
3675 | return 0; | |
24eab124 | 3676 | |
af6bdddf AM |
3677 | ++base_string; |
3678 | if (is_space_char (*base_string)) | |
3679 | ++base_string; | |
3680 | if (*base_string != ')') | |
3681 | { | |
3682 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3683 | operand_string); | |
3684 | return 0; | |
3685 | } | |
3686 | } | |
3687 | else if (!i.index_reg) | |
24eab124 | 3688 | { |
af6bdddf AM |
3689 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3690 | *base_string); | |
24eab124 AM |
3691 | return 0; |
3692 | } | |
3693 | } | |
af6bdddf | 3694 | else if (*base_string != ')') |
24eab124 | 3695 | { |
af6bdddf AM |
3696 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3697 | operand_string); | |
24eab124 AM |
3698 | return 0; |
3699 | } | |
c3332e24 | 3700 | } |
af6bdddf | 3701 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3702 | { |
af6bdddf | 3703 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3704 | return 0; |
c3332e24 | 3705 | } |
24eab124 AM |
3706 | } |
3707 | ||
3708 | /* If there's an expression beginning the operand, parse it, | |
3709 | assuming displacement_string_start and | |
3710 | displacement_string_end are meaningful. */ | |
3711 | if (displacement_string_start != displacement_string_end) | |
3712 | { | |
3713 | if (!i386_displacement (displacement_string_start, | |
3714 | displacement_string_end)) | |
3715 | return 0; | |
3716 | } | |
3717 | ||
3718 | /* Special case for (%dx) while doing input/output op. */ | |
3719 | if (i.base_reg | |
3720 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3721 | && i.index_reg == 0 | |
3722 | && i.log2_scale_factor == 0 | |
3723 | && i.seg[i.mem_operands] == 0 | |
3724 | && (i.types[this_operand] & Disp) == 0) | |
3725 | { | |
3726 | i.types[this_operand] = InOutPortReg; | |
3727 | return 1; | |
3728 | } | |
3729 | ||
eecb386c AM |
3730 | if (i386_index_check (operand_string) == 0) |
3731 | return 0; | |
24eab124 AM |
3732 | i.mem_operands++; |
3733 | } | |
3734 | else | |
3735 | { /* it's not a memory operand; argh! */ | |
3736 | as_bad (_("invalid char %s beginning operand %d `%s'"), | |
3737 | output_invalid (*op_string), | |
3738 | this_operand + 1, | |
3739 | op_string); | |
3740 | return 0; | |
3741 | } | |
3742 | return 1; /* normal return */ | |
252b5132 RH |
3743 | } |
3744 | \f | |
3745 | /* | |
24eab124 | 3746 | * md_estimate_size_before_relax() |
252b5132 RH |
3747 | * |
3748 | * Called just before relax(). | |
3749 | * Any symbol that is now undefined will not become defined. | |
3750 | * Return the correct fr_subtype in the frag. | |
3751 | * Return the initial "guess for fr_var" to caller. | |
3752 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
3753 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
3754 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
3755 | * 0 value. | |
3756 | */ | |
3757 | int | |
3758 | md_estimate_size_before_relax (fragP, segment) | |
3759 | register fragS *fragP; | |
3760 | register segT segment; | |
3761 | { | |
3762 | register unsigned char *opcode; | |
3763 | register int old_fr_fix; | |
3764 | ||
3765 | old_fr_fix = fragP->fr_fix; | |
3766 | opcode = (unsigned char *) fragP->fr_opcode; | |
3767 | /* We've already got fragP->fr_subtype right; all we have to do is | |
3768 | check for un-relaxable symbols. */ | |
3769 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
3770 | { | |
3771 | /* symbol is undefined in this segment */ | |
3772 | int code16 = fragP->fr_subtype & CODE16; | |
3773 | int size = code16 ? 2 : 4; | |
f6af82bd AM |
3774 | #ifdef BFD_ASSEMBLER |
3775 | enum bfd_reloc_code_real reloc_type; | |
3776 | #else | |
3777 | int reloc_type; | |
3778 | #endif | |
3779 | ||
3780 | if (GOT_symbol /* Not quite right - we should switch on presence of | |
3781 | @PLT, but I cannot see how to get to that from | |
3782 | here. We should have done this in md_assemble to | |
3783 | really get it right all of the time, but I think it | |
3784 | does not matter that much, as this will be right | |
3785 | most of the time. ERY */ | |
3786 | && S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) | |
3787 | reloc_type = BFD_RELOC_386_PLT32; | |
3788 | else if (code16) | |
3789 | reloc_type = BFD_RELOC_16_PCREL; | |
3790 | else | |
3791 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 RH |
3792 | |
3793 | switch (opcode[0]) | |
3794 | { | |
3795 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
3796 | opcode[0] = 0xe9; /* dword disp jmp */ | |
3797 | fragP->fr_fix += size; | |
3798 | fix_new (fragP, old_fr_fix, size, | |
3799 | fragP->fr_symbol, | |
3800 | fragP->fr_offset, 1, | |
f6af82bd | 3801 | reloc_type); |
252b5132 RH |
3802 | break; |
3803 | ||
3804 | default: | |
24eab124 | 3805 | /* This changes the byte-displacement jump 0x7N |
f6af82bd | 3806 | to the dword-displacement jump 0x0f,0x8N. */ |
252b5132 | 3807 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 3808 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
252b5132 RH |
3809 | fragP->fr_fix += 1 + size; /* we've added an opcode byte */ |
3810 | fix_new (fragP, old_fr_fix + 1, size, | |
3811 | fragP->fr_symbol, | |
3812 | fragP->fr_offset, 1, | |
f6af82bd | 3813 | reloc_type); |
252b5132 RH |
3814 | break; |
3815 | } | |
3816 | frag_wane (fragP); | |
3817 | } | |
3818 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
3819 | } /* md_estimate_size_before_relax() */ | |
3820 | \f | |
3821 | /* | |
3822 | * md_convert_frag(); | |
3823 | * | |
3824 | * Called after relax() is finished. | |
3825 | * In: Address of frag. | |
3826 | * fr_type == rs_machine_dependent. | |
3827 | * fr_subtype is what the address relaxed to. | |
3828 | * | |
3829 | * Out: Any fixSs and constants are set up. | |
3830 | * Caller will turn frag into a ".space 0". | |
3831 | */ | |
3832 | #ifndef BFD_ASSEMBLER | |
3833 | void | |
3834 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
3835 | object_headers *headers ATTRIBUTE_UNUSED; |
3836 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3837 | register fragS *fragP; |
3838 | #else | |
3839 | void | |
3840 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
3841 | bfd *abfd ATTRIBUTE_UNUSED; |
3842 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3843 | register fragS *fragP; |
3844 | #endif | |
3845 | { | |
3846 | register unsigned char *opcode; | |
3847 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
3848 | offsetT target_address; |
3849 | offsetT opcode_address; | |
252b5132 | 3850 | unsigned int extension = 0; |
847f7ad4 | 3851 | offsetT displacement_from_opcode_start; |
252b5132 RH |
3852 | |
3853 | opcode = (unsigned char *) fragP->fr_opcode; | |
3854 | ||
3855 | /* Address we want to reach in file space. */ | |
3856 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
3857 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ | |
49309057 | 3858 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
3859 | #endif |
3860 | ||
3861 | /* Address opcode resides at in file space. */ | |
3862 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
3863 | ||
3864 | /* Displacement from opcode start to fill into instruction. */ | |
3865 | displacement_from_opcode_start = target_address - opcode_address; | |
3866 | ||
3867 | switch (fragP->fr_subtype) | |
3868 | { | |
3869 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): | |
3870 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3871 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3872 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
3873 | /* don't have to change opcode */ | |
3874 | extension = 1; /* 1 opcode + 1 displacement */ | |
3875 | where_to_put_displacement = &opcode[1]; | |
3876 | break; | |
3877 | ||
3878 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): | |
3879 | extension = 5; /* 2 opcode + 4 displacement */ | |
3880 | opcode[1] = opcode[0] + 0x10; | |
3881 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3882 | where_to_put_displacement = &opcode[2]; | |
3883 | break; | |
3884 | ||
3885 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
3886 | extension = 4; /* 1 opcode + 4 displacement */ | |
3887 | opcode[0] = 0xe9; | |
3888 | where_to_put_displacement = &opcode[1]; | |
3889 | break; | |
3890 | ||
3891 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): | |
3892 | extension = 3; /* 2 opcode + 2 displacement */ | |
3893 | opcode[1] = opcode[0] + 0x10; | |
3894 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3895 | where_to_put_displacement = &opcode[2]; | |
3896 | break; | |
3897 | ||
3898 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): | |
3899 | extension = 2; /* 1 opcode + 2 displacement */ | |
3900 | opcode[0] = 0xe9; | |
3901 | where_to_put_displacement = &opcode[1]; | |
3902 | break; | |
3903 | ||
3904 | default: | |
3905 | BAD_CASE (fragP->fr_subtype); | |
3906 | break; | |
3907 | } | |
3908 | /* now put displacement after opcode */ | |
3909 | md_number_to_chars ((char *) where_to_put_displacement, | |
3910 | (valueT) (displacement_from_opcode_start - extension), | |
3911 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
3912 | fragP->fr_fix += extension; | |
3913 | } | |
3914 | \f | |
3915 | ||
3916 | int md_short_jump_size = 2; /* size of byte displacement jmp */ | |
3917 | int md_long_jump_size = 5; /* size of dword displacement jmp */ | |
3918 | const int md_reloc_size = 8; /* Size of relocation record */ | |
3919 | ||
3920 | void | |
3921 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3922 | char *ptr; | |
3923 | addressT from_addr, to_addr; | |
ab9da554 ILT |
3924 | fragS *frag ATTRIBUTE_UNUSED; |
3925 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3926 | { |
847f7ad4 | 3927 | offsetT offset; |
252b5132 RH |
3928 | |
3929 | offset = to_addr - (from_addr + 2); | |
3930 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ | |
3931 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
3932 | } | |
3933 | ||
3934 | void | |
3935 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3936 | char *ptr; | |
3937 | addressT from_addr, to_addr; | |
a38cf1db AM |
3938 | fragS *frag ATTRIBUTE_UNUSED; |
3939 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3940 | { |
847f7ad4 | 3941 | offsetT offset; |
252b5132 | 3942 | |
a38cf1db AM |
3943 | offset = to_addr - (from_addr + 5); |
3944 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
3945 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
3946 | } |
3947 | \f | |
3948 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
3949 | by our caller that we have all the info we need to fix it up. | |
3950 | ||
3951 | On the 386, immediates, displacements, and data pointers are all in | |
3952 | the same (little-endian) format, so we don't need to care about which | |
3953 | we are handling. */ | |
3954 | ||
3955 | int | |
3956 | md_apply_fix3 (fixP, valp, seg) | |
3957 | fixS *fixP; /* The fix we're to put in. */ | |
3958 | valueT *valp; /* Pointer to the value of the bits. */ | |
a04b544b | 3959 | segT seg ATTRIBUTE_UNUSED; /* Segment fix is from. */ |
252b5132 RH |
3960 | { |
3961 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
3962 | valueT value = *valp; | |
3963 | ||
e1b283bb | 3964 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
3965 | if (fixP->fx_pcrel) |
3966 | { | |
3967 | switch (fixP->fx_r_type) | |
3968 | { | |
5865bb77 ILT |
3969 | default: |
3970 | break; | |
3971 | ||
93382f6d AM |
3972 | case BFD_RELOC_32: |
3973 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
3974 | break; | |
3975 | case BFD_RELOC_16: | |
3976 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
3977 | break; | |
3978 | case BFD_RELOC_8: | |
3979 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
3980 | break; | |
3981 | } | |
3982 | } | |
252b5132 | 3983 | |
0723899b ILT |
3984 | /* This is a hack. There should be a better way to handle this. |
3985 | This covers for the fact that bfd_install_relocation will | |
3986 | subtract the current location (for partial_inplace, PC relative | |
3987 | relocations); see more below. */ | |
93382f6d AM |
3988 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
3989 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
3990 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
3991 | && fixP->fx_addsy) | |
252b5132 RH |
3992 | { |
3993 | #ifndef OBJ_AOUT | |
3994 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3995 | #ifdef TE_PE | |
3996 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3997 | #endif | |
3998 | ) | |
3999 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4000 | #endif | |
4001 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4002 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4003 | { |
2f66722d AM |
4004 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4005 | ||
4006 | if ((fseg == seg | |
4007 | || (symbol_section_p (fixP->fx_addsy) | |
4008 | && fseg != absolute_section)) | |
4009 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4010 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4011 | && S_IS_DEFINED (fixP->fx_addsy) | |
4012 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4013 | { | |
4014 | /* Yes, we add the values in twice. This is because | |
4015 | bfd_perform_relocation subtracts them out again. I think | |
4016 | bfd_perform_relocation is broken, but I don't dare change | |
4017 | it. FIXME. */ | |
4018 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4019 | } | |
252b5132 RH |
4020 | } |
4021 | #endif | |
4022 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4023 | /* For some reason, the PE format does not store a section | |
24eab124 | 4024 | address offset for a PC relative symbol. */ |
252b5132 RH |
4025 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4026 | value += md_pcrel_from (fixP); | |
c0c949c7 ILT |
4027 | else if (S_IS_EXTERNAL (fixP->fx_addsy) |
4028 | || S_IS_WEAK (fixP->fx_addsy)) | |
4029 | { | |
4030 | /* We are generating an external relocation for this defined | |
4031 | symbol. We add the address, because | |
4032 | bfd_install_relocation will subtract it. VALUE already | |
4033 | holds the symbol value, because fixup_segment added it | |
4034 | in. We subtract it out, and then we subtract it out | |
4035 | again because bfd_install_relocation will add it in | |
4036 | again. */ | |
4037 | value += md_pcrel_from (fixP); | |
4038 | value -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
4039 | } | |
252b5132 RH |
4040 | #endif |
4041 | } | |
c0c949c7 ILT |
4042 | #ifdef TE_PE |
4043 | else if (fixP->fx_addsy != NULL | |
4044 | && S_IS_DEFINED (fixP->fx_addsy) | |
4045 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
4046 | || S_IS_WEAK (fixP->fx_addsy))) | |
4047 | { | |
4048 | /* We are generating an external relocation for this defined | |
4049 | symbol. VALUE already holds the symbol value, and | |
4050 | bfd_install_relocation will add it in again. We don't want | |
4051 | either addition. */ | |
4052 | value -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
4053 | } | |
4054 | #endif | |
252b5132 RH |
4055 | |
4056 | /* Fix a few things - the dynamic linker expects certain values here, | |
4057 | and we must not dissappoint it. */ | |
4058 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
4059 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4060 | && fixP->fx_addsy) | |
4061 | switch (fixP->fx_r_type) { | |
4062 | case BFD_RELOC_386_PLT32: | |
4063 | /* Make the jump instruction point to the address of the operand. At | |
4064 | runtime we merely add the offset to the actual PLT entry. */ | |
847f7ad4 | 4065 | value = -4; |
252b5132 RH |
4066 | break; |
4067 | case BFD_RELOC_386_GOTPC: | |
4068 | /* | |
24eab124 | 4069 | * This is tough to explain. We end up with this one if we have |
252b5132 RH |
4070 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4071 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4072 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4073 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4074 | * something like: |
c3332e24 | 4075 | * |
24eab124 | 4076 | * call .L66 |
252b5132 | 4077 | * .L66: |
24eab124 AM |
4078 | * popl %ebx |
4079 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4080 | * |
24eab124 | 4081 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4082 | * the label .L66 and store it in %ebx. The linker itself will |
4083 | * ultimately change the first operand of the addl so that %ebx points to | |
4084 | * the GOT, but to keep things simple, the .o file must have this operand | |
4085 | * set so that it generates not the absolute address of .L66, but the | |
4086 | * absolute address of itself. This allows the linker itself simply | |
4087 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4088 | * added in, and the addend of the relocation is stored in the operand | |
4089 | * field for the instruction itself. | |
c3332e24 | 4090 | * |
24eab124 | 4091 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4092 | * offset so that %ebx would point to itself. The thing that is tricky is |
4093 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4094 | * to further modify the operand so that it will point to itself. | |
4095 | * There are other cases where you have something like: | |
c3332e24 | 4096 | * |
24eab124 | 4097 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4098 | * |
252b5132 | 4099 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4100 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4101 | * explicitly mentioned, and I wonder whether it would simplify matters |
4102 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4103 | * the pcrel_adjust field was used to store the correction, but since the | |
4104 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
4105 | */ | |
4106 | value -= 1; | |
4107 | break; | |
4108 | case BFD_RELOC_386_GOT32: | |
24eab124 | 4109 | value = 0; /* Fully resolved at runtime. No addend. */ |
252b5132 RH |
4110 | break; |
4111 | case BFD_RELOC_386_GOTOFF: | |
4112 | break; | |
4113 | ||
4114 | case BFD_RELOC_VTABLE_INHERIT: | |
4115 | case BFD_RELOC_VTABLE_ENTRY: | |
4116 | fixP->fx_done = 0; | |
4117 | return 1; | |
4118 | ||
4119 | default: | |
4120 | break; | |
4121 | } | |
93382f6d AM |
4122 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
4123 | *valp = value; | |
4124 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ | |
252b5132 RH |
4125 | md_number_to_chars (p, value, fixP->fx_size); |
4126 | ||
4127 | return 1; | |
4128 | } | |
252b5132 RH |
4129 | \f |
4130 | ||
4131 | #define MAX_LITTLENUMS 6 | |
4132 | ||
4133 | /* Turn the string pointed to by litP into a floating point constant of type | |
4134 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
4135 | is stored in *sizeP . An error message is returned, or NULL on OK. */ | |
4136 | char * | |
4137 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4138 | int type; |
252b5132 RH |
4139 | char *litP; |
4140 | int *sizeP; | |
4141 | { | |
4142 | int prec; | |
4143 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4144 | LITTLENUM_TYPE *wordP; | |
4145 | char *t; | |
4146 | ||
4147 | switch (type) | |
4148 | { | |
4149 | case 'f': | |
4150 | case 'F': | |
4151 | prec = 2; | |
4152 | break; | |
4153 | ||
4154 | case 'd': | |
4155 | case 'D': | |
4156 | prec = 4; | |
4157 | break; | |
4158 | ||
4159 | case 'x': | |
4160 | case 'X': | |
4161 | prec = 5; | |
4162 | break; | |
4163 | ||
4164 | default: | |
4165 | *sizeP = 0; | |
4166 | return _("Bad call to md_atof ()"); | |
4167 | } | |
4168 | t = atof_ieee (input_line_pointer, type, words); | |
4169 | if (t) | |
4170 | input_line_pointer = t; | |
4171 | ||
4172 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4173 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4174 | the bigendian 386. */ | |
4175 | for (wordP = words + prec - 1; prec--;) | |
4176 | { | |
4177 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4178 | litP += sizeof (LITTLENUM_TYPE); | |
4179 | } | |
4180 | return 0; | |
4181 | } | |
4182 | \f | |
4183 | char output_invalid_buf[8]; | |
4184 | ||
252b5132 RH |
4185 | static char * |
4186 | output_invalid (c) | |
4187 | int c; | |
4188 | { | |
4189 | if (isprint (c)) | |
4190 | sprintf (output_invalid_buf, "'%c'", c); | |
4191 | else | |
4192 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4193 | return output_invalid_buf; | |
4194 | } | |
4195 | ||
252b5132 | 4196 | |
af6bdddf | 4197 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4198 | |
4199 | static const reg_entry * | |
4200 | parse_register (reg_string, end_op) | |
4201 | char *reg_string; | |
4202 | char **end_op; | |
4203 | { | |
af6bdddf AM |
4204 | char *s = reg_string; |
4205 | char *p; | |
252b5132 RH |
4206 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4207 | const reg_entry *r; | |
4208 | ||
4209 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4210 | if (*s == REGISTER_PREFIX) | |
4211 | ++s; | |
4212 | ||
4213 | if (is_space_char (*s)) | |
4214 | ++s; | |
4215 | ||
4216 | p = reg_name_given; | |
af6bdddf | 4217 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4218 | { |
4219 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4220 | return (const reg_entry *) NULL; |
4221 | s++; | |
252b5132 RH |
4222 | } |
4223 | ||
af6bdddf | 4224 | *end_op = s; |
252b5132 RH |
4225 | |
4226 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4227 | ||
5f47d35b AM |
4228 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
4229 | if (r == i386_regtab /* %st is first entry of table */) | |
4230 | { | |
5f47d35b AM |
4231 | if (is_space_char (*s)) |
4232 | ++s; | |
4233 | if (*s == '(') | |
4234 | { | |
af6bdddf | 4235 | ++s; |
5f47d35b AM |
4236 | if (is_space_char (*s)) |
4237 | ++s; | |
4238 | if (*s >= '0' && *s <= '7') | |
4239 | { | |
4240 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4241 | ++s; |
5f47d35b AM |
4242 | if (is_space_char (*s)) |
4243 | ++s; | |
4244 | if (*s == ')') | |
4245 | { | |
4246 | *end_op = s + 1; | |
4247 | return r; | |
4248 | } | |
5f47d35b | 4249 | } |
af6bdddf | 4250 | /* We have "%st(" then garbage */ |
5f47d35b AM |
4251 | return (const reg_entry *) NULL; |
4252 | } | |
4253 | } | |
4254 | ||
252b5132 RH |
4255 | return r; |
4256 | } | |
4257 | \f | |
4cc782b5 ILT |
4258 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4259 | CONST char *md_shortopts = "kmVQ:sq"; | |
252b5132 RH |
4260 | #else |
4261 | CONST char *md_shortopts = "m"; | |
4262 | #endif | |
4263 | struct option md_longopts[] = { | |
4264 | {NULL, no_argument, NULL, 0} | |
4265 | }; | |
4266 | size_t md_longopts_size = sizeof (md_longopts); | |
4267 | ||
4268 | int | |
4269 | md_parse_option (c, arg) | |
4270 | int c; | |
ab9da554 | 4271 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4272 | { |
4273 | switch (c) | |
4274 | { | |
a38cf1db AM |
4275 | case 'q': |
4276 | quiet_warnings = 1; | |
252b5132 RH |
4277 | break; |
4278 | ||
4279 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4280 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4281 | should be emitted or not. FIXME: Not implemented. */ | |
4282 | case 'Q': | |
252b5132 RH |
4283 | break; |
4284 | ||
4285 | /* -V: SVR4 argument to print version ID. */ | |
4286 | case 'V': | |
4287 | print_version_id (); | |
4288 | break; | |
4289 | ||
a38cf1db AM |
4290 | /* -k: Ignore for FreeBSD compatibility. */ |
4291 | case 'k': | |
252b5132 | 4292 | break; |
4cc782b5 ILT |
4293 | |
4294 | case 's': | |
4295 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4296 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4297 | break; | |
252b5132 RH |
4298 | #endif |
4299 | ||
4300 | default: | |
4301 | return 0; | |
4302 | } | |
4303 | return 1; | |
4304 | } | |
4305 | ||
4306 | void | |
4307 | md_show_usage (stream) | |
4308 | FILE *stream; | |
4309 | { | |
4cc782b5 ILT |
4310 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4311 | fprintf (stream, _("\ | |
a38cf1db AM |
4312 | -Q ignored\n\ |
4313 | -V print assembler version number\n\ | |
4314 | -k ignored\n\ | |
4315 | -q quieten some warnings\n\ | |
4316 | -s ignored\n")); | |
4317 | #else | |
4318 | fprintf (stream, _("\ | |
4319 | -q quieten some warnings\n")); | |
4cc782b5 | 4320 | #endif |
252b5132 RH |
4321 | } |
4322 | ||
4323 | #ifdef BFD_ASSEMBLER | |
4c63da97 AM |
4324 | #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ |
4325 | || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ | |
4326 | || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) | |
252b5132 RH |
4327 | |
4328 | /* Pick the target format to use. */ | |
4329 | ||
4330 | const char * | |
4331 | i386_target_format () | |
4332 | { | |
4333 | switch (OUTPUT_FLAVOR) | |
4334 | { | |
4c63da97 AM |
4335 | #ifdef OBJ_MAYBE_AOUT |
4336 | case bfd_target_aout_flavour: | |
4337 | return AOUT_TARGET_FORMAT; | |
4338 | #endif | |
4339 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4340 | case bfd_target_coff_flavour: |
4341 | return "coff-i386"; | |
4c63da97 AM |
4342 | #endif |
4343 | #ifdef OBJ_MAYBE_ELF | |
252b5132 RH |
4344 | case bfd_target_elf_flavour: |
4345 | return "elf32-i386"; | |
4c63da97 | 4346 | #endif |
252b5132 RH |
4347 | default: |
4348 | abort (); | |
4349 | return NULL; | |
4350 | } | |
4351 | } | |
4352 | ||
4c63da97 | 4353 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 RH |
4354 | #endif /* BFD_ASSEMBLER */ |
4355 | \f | |
252b5132 RH |
4356 | symbolS * |
4357 | md_undefined_symbol (name) | |
4358 | char *name; | |
4359 | { | |
18dc2407 ILT |
4360 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4361 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4362 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4363 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4364 | { |
4365 | if (!GOT_symbol) | |
4366 | { | |
4367 | if (symbol_find (name)) | |
4368 | as_bad (_("GOT already in symbol table")); | |
4369 | GOT_symbol = symbol_new (name, undefined_section, | |
4370 | (valueT) 0, &zero_address_frag); | |
4371 | }; | |
4372 | return GOT_symbol; | |
4373 | } | |
252b5132 RH |
4374 | return 0; |
4375 | } | |
4376 | ||
4377 | /* Round up a section size to the appropriate boundary. */ | |
4378 | valueT | |
4379 | md_section_align (segment, size) | |
ab9da554 | 4380 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4381 | valueT size; |
4382 | { | |
252b5132 | 4383 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4384 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4385 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4386 | { | |
4387 | /* For a.out, force the section size to be aligned. If we don't do | |
4388 | this, BFD will align it for us, but it will not write out the | |
4389 | final bytes of the section. This may be a bug in BFD, but it is | |
4390 | easier to fix it here since that is how the other a.out targets | |
4391 | work. */ | |
4392 | int align; | |
4393 | ||
4394 | align = bfd_get_section_alignment (stdoutput, segment); | |
4395 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4396 | } | |
252b5132 RH |
4397 | #endif |
4398 | #endif | |
4399 | ||
4400 | return size; | |
4401 | } | |
4402 | ||
4403 | /* On the i386, PC-relative offsets are relative to the start of the | |
4404 | next instruction. That is, the address of the offset, plus its | |
4405 | size, since the offset is always the last part of the insn. */ | |
4406 | ||
4407 | long | |
4408 | md_pcrel_from (fixP) | |
4409 | fixS *fixP; | |
4410 | { | |
4411 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4412 | } | |
4413 | ||
4414 | #ifndef I386COFF | |
4415 | ||
4416 | static void | |
4417 | s_bss (ignore) | |
ab9da554 | 4418 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4419 | { |
4420 | register int temp; | |
4421 | ||
4422 | temp = get_absolute_expression (); | |
4423 | subseg_set (bss_section, (subsegT) temp); | |
4424 | demand_empty_rest_of_line (); | |
4425 | } | |
4426 | ||
4427 | #endif | |
4428 | ||
4429 | ||
4430 | #ifdef BFD_ASSEMBLER | |
4431 | ||
4432 | void | |
4433 | i386_validate_fix (fixp) | |
4434 | fixS *fixp; | |
4435 | { | |
4436 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4437 | { | |
4438 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4439 | fixp->fx_subsy = 0; | |
4440 | } | |
4441 | } | |
4442 | ||
252b5132 RH |
4443 | arelent * |
4444 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4445 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4446 | fixS *fixp; |
4447 | { | |
4448 | arelent *rel; | |
4449 | bfd_reloc_code_real_type code; | |
4450 | ||
4451 | switch (fixp->fx_r_type) | |
4452 | { | |
4453 | case BFD_RELOC_386_PLT32: | |
4454 | case BFD_RELOC_386_GOT32: | |
4455 | case BFD_RELOC_386_GOTOFF: | |
4456 | case BFD_RELOC_386_GOTPC: | |
4457 | case BFD_RELOC_RVA: | |
4458 | case BFD_RELOC_VTABLE_ENTRY: | |
4459 | case BFD_RELOC_VTABLE_INHERIT: | |
4460 | code = fixp->fx_r_type; | |
4461 | break; | |
4462 | default: | |
93382f6d | 4463 | if (fixp->fx_pcrel) |
252b5132 | 4464 | { |
93382f6d AM |
4465 | switch (fixp->fx_size) |
4466 | { | |
4467 | default: | |
d0b47220 | 4468 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4469 | fixp->fx_size); |
4470 | code = BFD_RELOC_32_PCREL; | |
4471 | break; | |
4472 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4473 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4474 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4475 | } | |
4476 | } | |
4477 | else | |
4478 | { | |
4479 | switch (fixp->fx_size) | |
4480 | { | |
4481 | default: | |
d0b47220 | 4482 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4483 | code = BFD_RELOC_32; |
4484 | break; | |
4485 | case 1: code = BFD_RELOC_8; break; | |
4486 | case 2: code = BFD_RELOC_16; break; | |
4487 | case 4: code = BFD_RELOC_32; break; | |
4488 | } | |
252b5132 RH |
4489 | } |
4490 | break; | |
4491 | } | |
252b5132 RH |
4492 | |
4493 | if (code == BFD_RELOC_32 | |
4494 | && GOT_symbol | |
4495 | && fixp->fx_addsy == GOT_symbol) | |
4496 | code = BFD_RELOC_386_GOTPC; | |
4497 | ||
4498 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4499 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4500 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4501 | |
4502 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4503 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4504 | vtable entry to be used in the relocation's section offset. */ | |
4505 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4506 | rel->address = fixp->fx_offset; | |
4507 | ||
4508 | if (fixp->fx_pcrel) | |
4509 | rel->addend = fixp->fx_addnumber; | |
4510 | else | |
4511 | rel->addend = 0; | |
4512 | ||
4513 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); | |
4514 | if (rel->howto == NULL) | |
4515 | { | |
4516 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4517 | _("cannot represent relocation type %s"), |
252b5132 RH |
4518 | bfd_get_reloc_code_name (code)); |
4519 | /* Set howto to a garbage value so that we can keep going. */ | |
4520 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4521 | assert (rel->howto != NULL); | |
4522 | } | |
4523 | ||
4524 | return rel; | |
4525 | } | |
4526 | ||
4527 | #else /* ! BFD_ASSEMBLER */ | |
4528 | ||
4529 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4530 | void | |
4531 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4532 | char *where; | |
4533 | fixS *fixP; | |
4534 | relax_addressT segment_address_in_file; | |
4535 | { | |
4536 | /* | |
4537 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
4538 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
4539 | */ | |
4540 | ||
4541 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; | |
4542 | long r_symbolnum; | |
4543 | ||
4544 | know (fixP->fx_addsy != NULL); | |
4545 | ||
4546 | md_number_to_chars (where, | |
4547 | (valueT) (fixP->fx_frag->fr_address | |
4548 | + fixP->fx_where - segment_address_in_file), | |
4549 | 4); | |
4550 | ||
4551 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4552 | ? S_GET_TYPE (fixP->fx_addsy) | |
4553 | : fixP->fx_addsy->sy_number); | |
4554 | ||
4555 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4556 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4557 | where[4] = r_symbolnum & 0x0ff; | |
4558 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4559 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4560 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4561 | } | |
4562 | ||
4563 | #endif /* OBJ_AOUT or OBJ_BOUT */ | |
4564 | ||
4565 | #if defined (I386COFF) | |
4566 | ||
4567 | short | |
4568 | tc_coff_fix2rtype (fixP) | |
4569 | fixS *fixP; | |
4570 | { | |
4571 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4572 | return R_IMAGEBASE; | |
4573 | ||
4574 | return (fixP->fx_pcrel ? | |
4575 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4576 | fixP->fx_size == 2 ? R_PCRWORD : | |
4577 | R_PCRLONG) : | |
4578 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4579 | fixP->fx_size == 2 ? R_RELWORD : | |
4580 | R_DIR32)); | |
4581 | } | |
4582 | ||
4583 | int | |
4584 | tc_coff_sizemachdep (frag) | |
4585 | fragS *frag; | |
4586 | { | |
4587 | if (frag->fr_next) | |
4588 | return (frag->fr_next->fr_address - frag->fr_address); | |
4589 | else | |
4590 | return 0; | |
4591 | } | |
4592 | ||
4593 | #endif /* I386COFF */ | |
4594 | ||
93382f6d | 4595 | #endif /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4596 | \f |
4597 | /* end of tc-i386.c */ |