Commit | Line | Data |
---|---|---|
fecd2382 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
dddc8a82 ILT |
2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998 |
3 | Free Software Foundation. | |
355afbcd | 4 | |
a39116f1 | 5 | This file is part of GAS, the GNU Assembler. |
355afbcd | 6 | |
a39116f1 RP |
7 | GAS is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
355afbcd | 11 | |
a39116f1 RP |
12 | GAS is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
355afbcd | 16 | |
a39116f1 | 17 | You should have received a copy of the GNU General Public License |
e592f0e6 ILT |
18 | along with GAS; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
fecd2382 | 21 | |
fecd2382 RP |
22 | /* |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
a39116f1 | 27 | */ |
fecd2382 | 28 | |
4b77b129 ILT |
29 | #include <ctype.h> |
30 | ||
fecd2382 | 31 | #include "as.h" |
0877841d | 32 | #include "subsegs.h" |
fecd2382 RP |
33 | |
34 | #include "obstack.h" | |
a39116f1 | 35 | #include "opcode/i386.h" |
fecd2382 | 36 | |
f0b37b4a KR |
37 | #ifndef TC_RELOC |
38 | #define TC_RELOC(X,Y) (Y) | |
39 | #endif | |
40 | ||
ec1e6bb8 ILT |
41 | #ifndef SCALE1_WHEN_NO_INDEX |
42 | /* Specifying a scale factor besides 1 when there is no index is | |
43 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
44 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
45 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
46 | #define SCALE1_WHEN_NO_INDEX 1 | |
47 | #endif | |
48 | ||
f59fb6ca ILT |
49 | static unsigned long mode_from_disp_size PARAMS ((unsigned long)); |
50 | static int fits_in_signed_byte PARAMS ((long)); | |
51 | static int fits_in_unsigned_byte PARAMS ((long)); | |
52 | static int fits_in_unsigned_word PARAMS ((long)); | |
53 | static int fits_in_signed_word PARAMS ((long)); | |
54 | static int smallest_imm_type PARAMS ((long)); | |
aa56747a | 55 | static int add_prefix PARAMS ((unsigned char)); |
f59fb6ca ILT |
56 | static void set_16bit_code_flag PARAMS ((int)); |
57 | #ifdef BFD_ASSEMBLER | |
58 | static bfd_reloc_code_real_type reloc | |
59 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
60 | #endif | |
61 | ||
fecd2382 RP |
62 | /* 'md_assemble ()' gathers together information and puts it into a |
63 | i386_insn. */ | |
64 | ||
3c8df4ba | 65 | struct _i386_insn |
355afbcd KR |
66 | { |
67 | /* TM holds the template for the insn were currently assembling. */ | |
68 | template tm; | |
69 | /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */ | |
70 | char suffix; | |
71 | /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */ | |
72 | ||
73 | /* OPERANDS gives the number of given operands. */ | |
74 | unsigned int operands; | |
75 | ||
49864cfa KR |
76 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
77 | of given register, displacement, memory operands and immediate | |
78 | operands. */ | |
355afbcd KR |
79 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
80 | ||
81 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
49864cfa KR |
82 | search through DISPS [i] & IMMS [i] & REGS [i] for the required |
83 | operand. */ | |
355afbcd KR |
84 | unsigned int types[MAX_OPERANDS]; |
85 | ||
86 | /* Displacements (if given) for each operand. */ | |
87 | expressionS *disps[MAX_OPERANDS]; | |
88 | ||
f0b37b4a KR |
89 | /* Relocation type for operand */ |
90 | #ifdef BFD_ASSEMBLER | |
91 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
92 | #else | |
93 | int disp_reloc[MAX_OPERANDS]; | |
94 | #endif | |
95 | ||
355afbcd KR |
96 | /* Immediate operands (if given) for each operand. */ |
97 | expressionS *imms[MAX_OPERANDS]; | |
98 | ||
99 | /* Register operands (if given) for each operand. */ | |
100 | reg_entry *regs[MAX_OPERANDS]; | |
101 | ||
102 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode | |
49864cfa | 103 | the base index byte below. */ |
355afbcd KR |
104 | reg_entry *base_reg; |
105 | reg_entry *index_reg; | |
106 | unsigned int log2_scale_factor; | |
107 | ||
4498e3d6 ILT |
108 | /* SEG gives the seg_entries of this insn. They are zero unless |
109 | explicit segment overrides are given. */ | |
110 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
355afbcd KR |
111 | |
112 | /* PREFIX holds all the given prefix opcodes (usually null). | |
ec1e6bb8 | 113 | PREFIXES is the number of prefix opcodes. */ |
355afbcd | 114 | unsigned int prefixes; |
ec1e6bb8 | 115 | unsigned char prefix[MAX_PREFIXES]; |
355afbcd | 116 | |
4498e3d6 | 117 | /* RM and BI are the modrm byte and the base index byte where the |
49864cfa | 118 | addressing modes of this insn are encoded. */ |
355afbcd KR |
119 | |
120 | modrm_byte rm; | |
121 | base_index_byte bi; | |
3c8df4ba | 122 | }; |
355afbcd | 123 | |
3c8df4ba | 124 | typedef struct _i386_insn i386_insn; |
fecd2382 | 125 | |
a39116f1 RP |
126 | /* This array holds the chars that always start a comment. If the |
127 | pre-processor is disabled, these aren't very useful */ | |
590c50d8 | 128 | #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
49864cfa KR |
129 | const char comment_chars[] = "#/"; |
130 | #else | |
a39116f1 | 131 | const char comment_chars[] = "#"; |
49864cfa | 132 | #endif |
fecd2382 | 133 | |
a39116f1 RP |
134 | /* This array holds the chars that only start a comment at the beginning of |
135 | a line. If the line seems to have the form '# 123 filename' | |
136 | .line and .file directives will appear in the pre-processed output */ | |
137 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
138 | first line of the input file. This is because the compiler outputs | |
139 | #NO_APP at the beginning of its output. */ | |
140 | /* Also note that comments started like this one will always work if | |
f3d817d8 | 141 | '/' isn't otherwise defined. */ |
590c50d8 | 142 | #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
ad660eb1 | 143 | const char line_comment_chars[] = ""; |
7b23213f KR |
144 | #else |
145 | const char line_comment_chars[] = "/"; | |
146 | #endif | |
355afbcd | 147 | const char line_separator_chars[] = ""; |
fecd2382 | 148 | |
a39116f1 RP |
149 | /* Chars that can be used to separate mant from exp in floating point nums */ |
150 | const char EXP_CHARS[] = "eE"; | |
fecd2382 | 151 | |
a39116f1 RP |
152 | /* Chars that mean this number is a floating point constant */ |
153 | /* As in 0f12.456 */ | |
154 | /* or 0d1.2345e12 */ | |
155 | const char FLT_CHARS[] = "fFdDxX"; | |
fecd2382 RP |
156 | |
157 | /* tables for lexical analysis */ | |
158 | static char opcode_chars[256]; | |
159 | static char register_chars[256]; | |
160 | static char operand_chars[256]; | |
161 | static char space_chars[256]; | |
162 | static char identifier_chars[256]; | |
163 | static char digit_chars[256]; | |
164 | ||
165 | /* lexical macros */ | |
166 | #define is_opcode_char(x) (opcode_chars[(unsigned char) x]) | |
167 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
168 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
169 | #define is_space_char(x) (space_chars[(unsigned char) x]) | |
170 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
171 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
172 | ||
173 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
f0b37b4a | 174 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
fecd2382 | 175 | |
fecd2382 RP |
176 | /* md_assemble() always leaves the strings it's passed unaltered. To |
177 | effect this we maintain a stack of saved characters that we've smashed | |
178 | with '\0's (indicating end of strings for various sub-fields of the | |
179 | assembler instruction). */ | |
180 | static char save_stack[32]; | |
181 | static char *save_stack_p; /* stack pointer */ | |
aa56747a ILT |
182 | #define END_STRING_AND_SAVE(s) \ |
183 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
184 | #define RESTORE_END_STRING(s) \ | |
185 | do { *(s) = *--save_stack_p; } while (0) | |
355afbcd KR |
186 | |
187 | /* The instruction we're assembling. */ | |
188 | static i386_insn i; | |
fecd2382 | 189 | |
4498e3d6 ILT |
190 | /* Possible templates for current insn. */ |
191 | static templates *current_templates; | |
192 | ||
fecd2382 RP |
193 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
194 | static expressionS disp_expressions[2], im_expressions[2]; | |
195 | ||
fecd2382 RP |
196 | static int this_operand; /* current operand we are working on */ |
197 | ||
ade614d5 KR |
198 | static int flag_do_long_jump; /* FIXME what does this do? */ |
199 | ||
c54c7aac KR |
200 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ |
201 | ||
3c8df4ba KR |
202 | /* Interface to relax_segment. |
203 | There are 2 relax states for 386 jump insns: one for conditional & | |
204 | one for unconditional jumps. This is because the these two types | |
205 | of jumps add different sizes to frags when we're figuring out what | |
206 | sort of jump to choose to reach a given label. */ | |
fecd2382 RP |
207 | |
208 | /* types */ | |
209 | #define COND_JUMP 1 /* conditional jump */ | |
210 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
211 | /* sizes */ | |
212 | #define BYTE 0 | |
213 | #define WORD 1 | |
214 | #define DWORD 2 | |
215 | #define UNKNOWN_SIZE 3 | |
216 | ||
3c8df4ba KR |
217 | #ifndef INLINE |
218 | #ifdef __GNUC__ | |
219 | #define INLINE __inline__ | |
220 | #else | |
221 | #define INLINE | |
222 | #endif | |
223 | #endif | |
224 | ||
ad660eb1 ILT |
225 | #define ENCODE_RELAX_STATE(type,size) \ |
226 | ((relax_substateT)((type<<2) | (size))) | |
fecd2382 | 227 | #define SIZE_FROM_RELAX_STATE(s) \ |
a39116f1 | 228 | ( (((s) & 0x3) == BYTE ? 1 : (((s) & 0x3) == WORD ? 2 : 4)) ) |
fecd2382 | 229 | |
355afbcd KR |
230 | const relax_typeS md_relax_table[] = |
231 | { | |
49864cfa KR |
232 | /* The fields are: |
233 | 1) most positive reach of this state, | |
234 | 2) most negative reach of this state, | |
235 | 3) how many bytes this mode will add to the size of the current frag | |
236 | 4) which index into the table to try if we can't fit into this one. | |
237 | */ | |
355afbcd KR |
238 | {1, 1, 0, 0}, |
239 | {1, 1, 0, 0}, | |
240 | {1, 1, 0, 0}, | |
241 | {1, 1, 0, 0}, | |
242 | ||
4498e3d6 ILT |
243 | /* For now we don't use word displacement jumps; they will not work |
244 | for destination addresses > 0xFFFF, since they clear the upper 16 | |
245 | bits of %eip. */ | |
355afbcd | 246 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, DWORD)}, |
3c8df4ba KR |
247 | /* word conditionals add 3 bytes to frag: |
248 | 2 opcode prefix; 1 displacement bytes */ | |
355afbcd | 249 | {32767 + 2, -32768 + 2, 3, ENCODE_RELAX_STATE (COND_JUMP, DWORD)}, |
3c8df4ba KR |
250 | /* dword conditionals adds 4 bytes to frag: |
251 | 1 opcode prefix; 3 displacement bytes */ | |
355afbcd KR |
252 | {0, 0, 4, 0}, |
253 | {1, 1, 0, 0}, | |
254 | ||
255 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)}, | |
3c8df4ba KR |
256 | /* word jmp adds 2 bytes to frag: |
257 | 1 opcode prefix; 1 displacement bytes */ | |
355afbcd | 258 | {32767 + 2, -32768 + 2, 2, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)}, |
3c8df4ba KR |
259 | /* dword jmp adds 3 bytes to frag: |
260 | 0 opcode prefix; 3 displacement bytes */ | |
355afbcd KR |
261 | {0, 0, 3, 0}, |
262 | {1, 1, 0, 0}, | |
263 | ||
fecd2382 RP |
264 | }; |
265 | ||
3ea36b53 ILT |
266 | |
267 | void | |
268 | i386_align_code (fragP, count) | |
269 | fragS *fragP; | |
270 | int count; | |
271 | { | |
272 | /* Various efficient no-op patterns for aligning code labels. */ | |
fb50cd4e ILT |
273 | /* Note: Don't try to assemble the instructions in the comments. */ |
274 | /* 0L and 0w are not legal */ | |
275 | static const char f32_1[] = | |
276 | {0x90}; /* nop */ | |
277 | static const char f32_2[] = | |
278 | {0x89,0xf6}; /* movl %esi,%esi */ | |
279 | static const char f32_3[] = | |
280 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
281 | static const char f32_4[] = | |
282 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
283 | static const char f32_5[] = | |
284 | {0x90, /* nop */ | |
285 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
286 | static const char f32_6[] = | |
287 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
288 | static const char f32_7[] = | |
289 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
290 | static const char f32_8[] = | |
291 | {0x90, /* nop */ | |
292 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
293 | static const char f32_9[] = | |
294 | {0x89,0xf6, /* movl %esi,%esi */ | |
295 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
296 | static const char f32_10[] = | |
297 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
298 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
299 | static const char f32_11[] = | |
300 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
301 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
302 | static const char f32_12[] = | |
303 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
304 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
305 | static const char f32_13[] = | |
306 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
307 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
308 | static const char f32_14[] = | |
309 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
310 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
311 | static const char f32_15[] = | |
312 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
313 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
314 | static const char f16_4[] = | |
388fa5c6 | 315 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
316 | static const char f16_5[] = |
317 | {0x90, /* nop */ | |
388fa5c6 | 318 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
319 | static const char f16_6[] = |
320 | {0x89,0xf6, /* mov %si,%si */ | |
321 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
322 | static const char f16_7[] = | |
388fa5c6 | 323 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
fb50cd4e ILT |
324 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
325 | static const char f16_8[] = | |
388fa5c6 | 326 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
fb50cd4e | 327 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
3ea36b53 ILT |
328 | static const char *const f32_patt[] = { |
329 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
330 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
331 | }; | |
332 | static const char *const f16_patt[] = { | |
333 | f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, | |
334 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 | |
335 | }; | |
336 | ||
337 | if (count > 0 && count <= 15) | |
338 | { | |
339 | if (flag_16bit_code) | |
340 | { | |
341 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
342 | f16_patt[count - 1], count); | |
343 | if (count > 8) /* adjust jump offset */ | |
344 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
345 | } | |
346 | else | |
347 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
348 | f32_patt[count - 1], count); | |
349 | fragP->fr_var = count; | |
350 | } | |
351 | } | |
352 | ||
49864cfa KR |
353 | static char *output_invalid PARAMS ((int c)); |
354 | static int i386_operand PARAMS ((char *operand_string)); | |
355 | static reg_entry *parse_register PARAMS ((char *reg_string)); | |
356 | #ifndef I386COFF | |
ad660eb1 | 357 | static void s_bss PARAMS ((int)); |
49864cfa | 358 | #endif |
fecd2382 | 359 | |
4498e3d6 | 360 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
f0b37b4a | 361 | |
3c8df4ba | 362 | static INLINE unsigned long |
49864cfa KR |
363 | mode_from_disp_size (t) |
364 | unsigned long t; | |
365 | { | |
3c8df4ba KR |
366 | return (t & Disp8) ? 1 : (t & Disp32) ? 2 : 0; |
367 | } | |
49864cfa | 368 | |
ad660eb1 ILT |
369 | #if 0 |
370 | /* Not used. */ | |
3c8df4ba | 371 | /* convert opcode suffix ('b' 'w' 'l' typically) into type specifier */ |
49864cfa | 372 | |
3c8df4ba | 373 | static INLINE unsigned long |
49864cfa KR |
374 | opcode_suffix_to_type (s) |
375 | unsigned long s; | |
376 | { | |
377 | return (s == BYTE_OPCODE_SUFFIX | |
378 | ? Byte : (s == WORD_OPCODE_SUFFIX | |
379 | ? Word : DWord)); | |
380 | } /* opcode_suffix_to_type() */ | |
ad660eb1 | 381 | #endif |
49864cfa | 382 | |
3c8df4ba | 383 | static INLINE int |
49864cfa KR |
384 | fits_in_signed_byte (num) |
385 | long num; | |
386 | { | |
3c8df4ba | 387 | return (num >= -128) && (num <= 127); |
49864cfa KR |
388 | } /* fits_in_signed_byte() */ |
389 | ||
3c8df4ba | 390 | static INLINE int |
49864cfa KR |
391 | fits_in_unsigned_byte (num) |
392 | long num; | |
393 | { | |
3c8df4ba | 394 | return (num & 0xff) == num; |
49864cfa KR |
395 | } /* fits_in_unsigned_byte() */ |
396 | ||
3c8df4ba | 397 | static INLINE int |
49864cfa KR |
398 | fits_in_unsigned_word (num) |
399 | long num; | |
400 | { | |
3c8df4ba | 401 | return (num & 0xffff) == num; |
49864cfa KR |
402 | } /* fits_in_unsigned_word() */ |
403 | ||
3c8df4ba | 404 | static INLINE int |
49864cfa KR |
405 | fits_in_signed_word (num) |
406 | long num; | |
407 | { | |
3c8df4ba | 408 | return (-32768 <= num) && (num <= 32767); |
49864cfa KR |
409 | } /* fits_in_signed_word() */ |
410 | ||
411 | static int | |
412 | smallest_imm_type (num) | |
413 | long num; | |
414 | { | |
f3d817d8 DM |
415 | #if 0 |
416 | /* This code is disabled because all the Imm1 forms in the opcode table | |
417 | are slower on the i486, and they're the versions with the implicitly | |
418 | specified single-position displacement, which has another syntax if | |
419 | you really want to use that form. If you really prefer to have the | |
420 | one-byte-shorter Imm1 form despite these problems, re-enable this | |
421 | code. */ | |
422 | if (num == 1) | |
423 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
424 | #endif | |
425 | return (fits_in_signed_byte (num) | |
3c8df4ba KR |
426 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
427 | : fits_in_unsigned_byte (num) | |
428 | ? (Imm8 | Imm16 | Imm32) | |
429 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
430 | ? (Imm16 | Imm32) | |
431 | : (Imm32)); | |
49864cfa | 432 | } /* smallest_imm_type() */ |
fecd2382 | 433 | |
aa56747a ILT |
434 | /* Returns 0 if attempting to add a prefix where one from the same |
435 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
436 | added. */ | |
4498e3d6 | 437 | static int |
aa56747a ILT |
438 | add_prefix (prefix) |
439 | unsigned char prefix; | |
4498e3d6 | 440 | { |
aa56747a | 441 | int ret = 1; |
4498e3d6 ILT |
442 | int q; |
443 | ||
aa56747a | 444 | switch (prefix) |
4498e3d6 | 445 | { |
aa56747a ILT |
446 | case CS_PREFIX_OPCODE: |
447 | case DS_PREFIX_OPCODE: | |
448 | case ES_PREFIX_OPCODE: | |
449 | case FS_PREFIX_OPCODE: | |
450 | case GS_PREFIX_OPCODE: | |
451 | case SS_PREFIX_OPCODE: | |
452 | q = SEG_PREFIX; | |
453 | break; | |
4498e3d6 | 454 | |
aa56747a ILT |
455 | case REPNE: |
456 | case REPE: | |
457 | ret = 2; | |
458 | /* fall thru */ | |
459 | case LOCK_PREFIX_OPCODE: | |
460 | q = LOCKREP_PREFIX; | |
461 | break; | |
4498e3d6 | 462 | |
aa56747a ILT |
463 | case FWAIT_OPCODE: |
464 | q = WAIT_PREFIX; | |
465 | break; | |
4498e3d6 | 466 | |
aa56747a ILT |
467 | case ADDR_PREFIX_OPCODE: |
468 | q = ADDR_PREFIX; | |
469 | break; | |
470 | ||
471 | case WORD_PREFIX_OPCODE: | |
472 | q = DATA_PREFIX; | |
4498e3d6 ILT |
473 | } |
474 | ||
aa56747a | 475 | if (i.prefix[q]) |
4498e3d6 | 476 | { |
aa56747a | 477 | as_bad (_("same type of prefix used twice")); |
4498e3d6 ILT |
478 | return 0; |
479 | } | |
480 | ||
aa56747a ILT |
481 | i.prefixes += 1; |
482 | i.prefix[q] = prefix; | |
483 | return ret; | |
4498e3d6 ILT |
484 | } |
485 | ||
f59fb6ca ILT |
486 | static void |
487 | set_16bit_code_flag (new_16bit_code_flag) | |
c54c7aac KR |
488 | int new_16bit_code_flag; |
489 | { | |
490 | flag_16bit_code = new_16bit_code_flag; | |
491 | } | |
492 | ||
355afbcd KR |
493 | const pseudo_typeS md_pseudo_table[] = |
494 | { | |
49864cfa | 495 | #ifndef I386COFF |
355afbcd | 496 | {"bss", s_bss, 0}, |
49864cfa | 497 | #endif |
02bdbd8b | 498 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
355afbcd | 499 | {"align", s_align_bytes, 0}, |
49864cfa KR |
500 | #else |
501 | {"align", s_align_ptwo, 0}, | |
502 | #endif | |
355afbcd KR |
503 | {"ffloat", float_cons, 'f'}, |
504 | {"dfloat", float_cons, 'd'}, | |
505 | {"tfloat", float_cons, 'x'}, | |
506 | {"value", cons, 2}, | |
49864cfa KR |
507 | {"noopt", s_ignore, 0}, |
508 | {"optim", s_ignore, 0}, | |
c54c7aac KR |
509 | {"code16", set_16bit_code_flag, 1}, |
510 | {"code32", set_16bit_code_flag, 0}, | |
355afbcd | 511 | {0, 0, 0} |
fecd2382 RP |
512 | }; |
513 | ||
514 | /* for interface with expression () */ | |
355afbcd | 515 | extern char *input_line_pointer; |
fecd2382 RP |
516 | |
517 | /* obstack for constructing various things in md_begin */ | |
518 | struct obstack o; | |
519 | ||
520 | /* hash table for opcode lookup */ | |
f3d817d8 | 521 | static struct hash_control *op_hash; |
fecd2382 | 522 | /* hash table for register lookup */ |
f3d817d8 | 523 | static struct hash_control *reg_hash; |
fecd2382 | 524 | /* hash table for prefix lookup */ |
f3d817d8 | 525 | static struct hash_control *prefix_hash; |
fecd2382 | 526 | \f |
355afbcd KR |
527 | |
528 | void | |
529 | md_begin () | |
fecd2382 | 530 | { |
ad660eb1 | 531 | const char *hash_err; |
355afbcd KR |
532 | |
533 | obstack_begin (&o, 4096); | |
534 | ||
535 | /* initialize op_hash hash table */ | |
f3d817d8 | 536 | op_hash = hash_new (); |
355afbcd KR |
537 | |
538 | { | |
539 | register const template *optab; | |
540 | register templates *core_optab; | |
541 | char *prev_name; | |
542 | ||
543 | optab = i386_optab; /* setup for loop */ | |
544 | prev_name = optab->name; | |
545 | obstack_grow (&o, optab, sizeof (template)); | |
546 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
547 | ||
548 | for (optab++; optab < i386_optab_end; optab++) | |
549 | { | |
550 | if (!strcmp (optab->name, prev_name)) | |
551 | { | |
552 | /* same name as before --> append to current template list */ | |
553 | obstack_grow (&o, optab, sizeof (template)); | |
554 | } | |
555 | else | |
556 | { | |
557 | /* different name --> ship out current template list; | |
49864cfa KR |
558 | add to hash table; & begin anew */ |
559 | /* Note: end must be set before start! since obstack_next_free | |
560 | changes upon opstack_finish */ | |
355afbcd KR |
561 | core_optab->end = (template *) obstack_next_free (&o); |
562 | core_optab->start = (template *) obstack_finish (&o); | |
563 | hash_err = hash_insert (op_hash, prev_name, (char *) core_optab); | |
ad660eb1 | 564 | if (hash_err) |
355afbcd KR |
565 | { |
566 | hash_error: | |
48401fcf | 567 | as_fatal (_("Internal Error: Can't hash %s: %s"), prev_name, |
3c8df4ba | 568 | hash_err); |
355afbcd KR |
569 | } |
570 | prev_name = optab->name; | |
571 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
572 | obstack_grow (&o, optab, sizeof (template)); | |
573 | } | |
574 | } | |
575 | } | |
576 | ||
577 | /* initialize reg_hash hash table */ | |
578 | reg_hash = hash_new (); | |
579 | { | |
580 | register const reg_entry *regtab; | |
581 | ||
582 | for (regtab = i386_regtab; regtab < i386_regtab_end; regtab++) | |
583 | { | |
ad660eb1 ILT |
584 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
585 | if (hash_err) | |
355afbcd KR |
586 | goto hash_error; |
587 | } | |
588 | } | |
589 | ||
355afbcd KR |
590 | /* initialize reg_hash hash table */ |
591 | prefix_hash = hash_new (); | |
592 | { | |
593 | register const prefix_entry *prefixtab; | |
594 | ||
595 | for (prefixtab = i386_prefixtab; | |
596 | prefixtab < i386_prefixtab_end; prefixtab++) | |
597 | { | |
ad660eb1 ILT |
598 | hash_err = hash_insert (prefix_hash, prefixtab->prefix_name, |
599 | (PTR) prefixtab); | |
600 | if (hash_err) | |
355afbcd KR |
601 | goto hash_error; |
602 | } | |
603 | } | |
604 | ||
605 | /* fill in lexical tables: opcode_chars, operand_chars, space_chars */ | |
606 | { | |
ad660eb1 ILT |
607 | register int c; |
608 | register char *p; | |
355afbcd KR |
609 | |
610 | for (c = 0; c < 256; c++) | |
611 | { | |
612 | if (islower (c) || isdigit (c)) | |
613 | { | |
614 | opcode_chars[c] = c; | |
615 | register_chars[c] = c; | |
616 | } | |
617 | else if (isupper (c)) | |
618 | { | |
619 | opcode_chars[c] = tolower (c); | |
620 | register_chars[c] = opcode_chars[c]; | |
621 | } | |
622 | else if (c == PREFIX_SEPERATOR) | |
623 | { | |
624 | opcode_chars[c] = c; | |
625 | } | |
626 | else if (c == ')' || c == '(') | |
627 | { | |
628 | register_chars[c] = c; | |
629 | } | |
630 | ||
631 | if (isupper (c) || islower (c) || isdigit (c)) | |
632 | operand_chars[c] = c; | |
355afbcd KR |
633 | |
634 | if (isdigit (c) || c == '-') | |
635 | digit_chars[c] = c; | |
636 | ||
637 | if (isalpha (c) || c == '_' || c == '.' || isdigit (c)) | |
638 | identifier_chars[c] = c; | |
639 | ||
30355216 SC |
640 | #ifdef LEX_AT |
641 | identifier_chars['@'] = '@'; | |
642 | #endif | |
643 | ||
355afbcd KR |
644 | if (c == ' ' || c == '\t') |
645 | space_chars[c] = c; | |
646 | } | |
ad660eb1 ILT |
647 | |
648 | for (p = operand_special_chars; *p != '\0'; p++) | |
649 | operand_chars[(unsigned char) *p] = *p; | |
355afbcd | 650 | } |
ad660eb1 | 651 | |
590c50d8 ILT |
652 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
653 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
654 | { | |
655 | record_alignment (text_section, 2); | |
656 | record_alignment (data_section, 2); | |
657 | record_alignment (bss_section, 2); | |
658 | } | |
ad660eb1 | 659 | #endif |
fecd2382 | 660 | } |
3ea36b53 ILT |
661 | |
662 | void | |
663 | i386_print_statistics (file) | |
664 | FILE *file; | |
665 | { | |
666 | hash_print_statistics (file, "i386 opcode", op_hash); | |
667 | hash_print_statistics (file, "i386 register", reg_hash); | |
668 | hash_print_statistics (file, "i386 prefix", prefix_hash); | |
669 | } | |
fecd2382 | 670 | \f |
355afbcd | 671 | |
fecd2382 RP |
672 | #ifdef DEBUG386 |
673 | ||
674 | /* debugging routines for md_assemble */ | |
ad660eb1 ILT |
675 | static void pi PARAMS ((char *, i386_insn *)); |
676 | static void pte PARAMS ((template *)); | |
677 | static void pt PARAMS ((unsigned int)); | |
678 | static void pe PARAMS ((expressionS *)); | |
679 | static void ps PARAMS ((symbolS *)); | |
fecd2382 | 680 | |
355afbcd KR |
681 | static void |
682 | pi (line, x) | |
683 | char *line; | |
684 | i386_insn *x; | |
fecd2382 | 685 | { |
355afbcd KR |
686 | register template *p; |
687 | int i; | |
688 | ||
689 | fprintf (stdout, "%s: template ", line); | |
690 | pte (&x->tm); | |
691 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
692 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
693 | fprintf (stdout, " base %x index %x scale %x\n", | |
694 | x->bi.base, x->bi.index, x->bi.scale); | |
695 | for (i = 0; i < x->operands; i++) | |
696 | { | |
697 | fprintf (stdout, " #%d: ", i + 1); | |
698 | pt (x->types[i]); | |
699 | fprintf (stdout, "\n"); | |
a52f90a4 ILT |
700 | if (x->types[i] |
701 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
702 | fprintf (stdout, "%s\n", x->regs[i]->reg_name); |
703 | if (x->types[i] & Imm) | |
704 | pe (x->imms[i]); | |
705 | if (x->types[i] & (Disp | Abs)) | |
706 | pe (x->disps[i]); | |
707 | } | |
fecd2382 RP |
708 | } |
709 | ||
355afbcd KR |
710 | static void |
711 | pte (t) | |
712 | template *t; | |
fecd2382 | 713 | { |
355afbcd KR |
714 | int i; |
715 | fprintf (stdout, " %d operands ", t->operands); | |
716 | fprintf (stdout, "opcode %x ", | |
717 | t->base_opcode); | |
718 | if (t->extension_opcode != None) | |
719 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
720 | if (t->opcode_modifier & D) | |
721 | fprintf (stdout, "D"); | |
722 | if (t->opcode_modifier & W) | |
723 | fprintf (stdout, "W"); | |
724 | fprintf (stdout, "\n"); | |
725 | for (i = 0; i < t->operands; i++) | |
726 | { | |
727 | fprintf (stdout, " #%d type ", i + 1); | |
728 | pt (t->operand_types[i]); | |
729 | fprintf (stdout, "\n"); | |
730 | } | |
fecd2382 RP |
731 | } |
732 | ||
355afbcd KR |
733 | static void |
734 | pe (e) | |
735 | expressionS *e; | |
fecd2382 | 736 | { |
5ac34ac3 | 737 | fprintf (stdout, " operation %d\n", e->X_op); |
355afbcd KR |
738 | fprintf (stdout, " add_number %d (%x)\n", |
739 | e->X_add_number, e->X_add_number); | |
740 | if (e->X_add_symbol) | |
741 | { | |
742 | fprintf (stdout, " add_symbol "); | |
743 | ps (e->X_add_symbol); | |
744 | fprintf (stdout, "\n"); | |
745 | } | |
5ac34ac3 | 746 | if (e->X_op_symbol) |
355afbcd | 747 | { |
5ac34ac3 ILT |
748 | fprintf (stdout, " op_symbol "); |
749 | ps (e->X_op_symbol); | |
355afbcd KR |
750 | fprintf (stdout, "\n"); |
751 | } | |
fecd2382 RP |
752 | } |
753 | ||
355afbcd KR |
754 | static void |
755 | ps (s) | |
756 | symbolS *s; | |
fecd2382 | 757 | { |
355afbcd KR |
758 | fprintf (stdout, "%s type %s%s", |
759 | S_GET_NAME (s), | |
760 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
761 | segment_name (S_GET_SEGMENT (s))); | |
fecd2382 RP |
762 | } |
763 | ||
355afbcd KR |
764 | struct type_name |
765 | { | |
766 | unsigned int mask; | |
767 | char *tname; | |
768 | } | |
769 | ||
770 | type_names[] = | |
771 | { | |
772 | { Reg8, "r8" }, | |
773 | { Reg16, "r16" }, | |
774 | { Reg32, "r32" }, | |
775 | { Imm8, "i8" }, | |
776 | { Imm8S, "i8s" }, | |
777 | { Imm16, "i16" }, | |
778 | { Imm32, "i32" }, | |
779 | { Mem8, "Mem8" }, | |
780 | { Mem16, "Mem16" }, | |
781 | { Mem32, "Mem32" }, | |
782 | { BaseIndex, "BaseIndex" }, | |
783 | { Abs8, "Abs8" }, | |
784 | { Abs16, "Abs16" }, | |
785 | { Abs32, "Abs32" }, | |
786 | { Disp8, "d8" }, | |
787 | { Disp16, "d16" }, | |
788 | { Disp32, "d32" }, | |
789 | { SReg2, "SReg2" }, | |
790 | { SReg3, "SReg3" }, | |
791 | { Acc, "Acc" }, | |
792 | { InOutPortReg, "InOutPortReg" }, | |
793 | { ShiftCount, "ShiftCount" }, | |
794 | { Imm1, "i1" }, | |
795 | { Control, "control reg" }, | |
796 | { Test, "test reg" }, | |
4498e3d6 | 797 | { Debug, "debug reg" }, |
355afbcd KR |
798 | { FloatReg, "FReg" }, |
799 | { FloatAcc, "FAcc" }, | |
800 | { JumpAbsolute, "Jump Absolute" }, | |
454b0ccd | 801 | { RegMMX, "rMMX" }, |
4498e3d6 | 802 | { EsSeg, "es" }, |
355afbcd | 803 | { 0, "" } |
fecd2382 RP |
804 | }; |
805 | ||
355afbcd KR |
806 | static void |
807 | pt (t) | |
808 | unsigned int t; | |
fecd2382 | 809 | { |
355afbcd KR |
810 | register struct type_name *ty; |
811 | ||
812 | if (t == Unknown) | |
813 | { | |
48401fcf | 814 | fprintf (stdout, _("Unknown")); |
355afbcd KR |
815 | } |
816 | else | |
817 | { | |
818 | for (ty = type_names; ty->mask; ty++) | |
819 | if (t & ty->mask) | |
820 | fprintf (stdout, "%s, ", ty->tname); | |
821 | } | |
822 | fflush (stdout); | |
fecd2382 RP |
823 | } |
824 | ||
825 | #endif /* DEBUG386 */ | |
826 | \f | |
49864cfa KR |
827 | #ifdef BFD_ASSEMBLER |
828 | static bfd_reloc_code_real_type | |
f0b37b4a | 829 | reloc (size, pcrel, other) |
49864cfa KR |
830 | int size; |
831 | int pcrel; | |
f0b37b4a | 832 | bfd_reloc_code_real_type other; |
49864cfa | 833 | { |
f0b37b4a KR |
834 | if (other != NO_RELOC) return other; |
835 | ||
49864cfa KR |
836 | if (pcrel) |
837 | switch (size) | |
838 | { | |
839 | case 1: return BFD_RELOC_8_PCREL; | |
840 | case 2: return BFD_RELOC_16_PCREL; | |
841 | case 4: return BFD_RELOC_32_PCREL; | |
842 | } | |
843 | else | |
844 | switch (size) | |
845 | { | |
846 | case 1: return BFD_RELOC_8; | |
847 | case 2: return BFD_RELOC_16; | |
848 | case 4: return BFD_RELOC_32; | |
849 | } | |
ad660eb1 | 850 | |
48401fcf TT |
851 | if (pcrel) |
852 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
853 | else | |
854 | as_bad (_("Can not do %d byte relocation"), size); | |
855 | ||
ad660eb1 | 856 | return BFD_RELOC_NONE; |
49864cfa | 857 | } |
49864cfa | 858 | |
f0b37b4a KR |
859 | /* |
860 | * Here we decide which fixups can be adjusted to make them relative to | |
861 | * the beginning of the section instead of the symbol. Basically we need | |
862 | * to make sure that the dynamic relocations are done correctly, so in | |
863 | * some cases we force the original symbol to be used. | |
864 | */ | |
0877841d | 865 | int |
f0b37b4a KR |
866 | tc_i386_fix_adjustable(fixP) |
867 | fixS * fixP; | |
868 | { | |
76fb6d2f | 869 | #ifdef OBJ_ELF |
c54c7aac | 870 | /* Prevent all adjustments to global symbols. */ |
0877841d | 871 | if (S_IS_EXTERN (fixP->fx_addsy)) |
c54c7aac | 872 | return 0; |
0b476c53 ILT |
873 | if (S_IS_WEAK (fixP->fx_addsy)) |
874 | return 0; | |
0b476c53 | 875 | #endif /* ! defined (OBJ_AOUT) */ |
c54c7aac | 876 | /* adjust_reloc_syms doesn't know about the GOT */ |
0877841d ILT |
877 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
878 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
879 | || fixP->fx_r_type == BFD_RELOC_386_GOT32) | |
c54c7aac | 880 | return 0; |
c54c7aac | 881 | return 1; |
f0b37b4a | 882 | } |
454b0ccd ILT |
883 | #else |
884 | #define reloc(SIZE,PCREL,OTHER) 0 | |
885 | #define BFD_RELOC_32 0 | |
886 | #define BFD_RELOC_32_PCREL 0 | |
887 | #define BFD_RELOC_386_PLT32 0 | |
888 | #define BFD_RELOC_386_GOT32 0 | |
889 | #define BFD_RELOC_386_GOTOFF 0 | |
890 | #endif | |
f0b37b4a | 891 | |
49864cfa | 892 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3c8df4ba | 893 | machine dependent instruction. This function is supposed to emit |
49864cfa | 894 | the frags/bytes it assembles to. */ |
f0b37b4a | 895 | |
355afbcd KR |
896 | void |
897 | md_assemble (line) | |
898 | char *line; | |
fecd2382 | 899 | { |
227b6b55 ILT |
900 | /* Points to template once we've found it. */ |
901 | const template *t; | |
355afbcd | 902 | |
ad660eb1 ILT |
903 | /* Count the size of the instruction generated. */ |
904 | int insn_size = 0; | |
905 | ||
f0b37b4a KR |
906 | int j; |
907 | ||
355afbcd KR |
908 | /* Initialize globals. */ |
909 | memset (&i, '\0', sizeof (i)); | |
f0b37b4a KR |
910 | for (j = 0; j < MAX_OPERANDS; j++) |
911 | i.disp_reloc[j] = NO_RELOC; | |
355afbcd KR |
912 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
913 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
914 | save_stack_p = save_stack; /* reset stack pointer */ | |
915 | ||
227b6b55 | 916 | /* First parse an opcode & call i386_operand for the operands. |
49864cfa KR |
917 | We assume that the scrubber has arranged it so that line[0] is the valid |
918 | start of a (possibly prefixed) opcode. */ | |
355afbcd | 919 | { |
f3d817d8 | 920 | char *l = line; |
355afbcd KR |
921 | |
922 | /* 1 if operand is pending after ','. */ | |
923 | unsigned int expecting_operand = 0; | |
4498e3d6 ILT |
924 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
925 | const char *expecting_string_instruction = NULL; | |
0b476c53 ILT |
926 | /* Non-zero if operand parens not balanced. */ |
927 | unsigned int paren_not_balanced; | |
355afbcd KR |
928 | char *token_start = l; |
929 | ||
930 | while (!is_space_char (*l) && *l != END_OF_INSN) | |
931 | { | |
932 | if (!is_opcode_char (*l)) | |
933 | { | |
48401fcf | 934 | as_bad (_("invalid character %s in opcode"), output_invalid (*l)); |
355afbcd KR |
935 | return; |
936 | } | |
937 | else if (*l != PREFIX_SEPERATOR) | |
938 | { | |
939 | *l = opcode_chars[(unsigned char) *l]; /* fold case of opcodes */ | |
940 | l++; | |
941 | } | |
942 | else | |
f3d817d8 DM |
943 | { |
944 | /* This opcode's got a prefix. */ | |
f3d817d8 | 945 | prefix_entry *prefix; |
355afbcd KR |
946 | |
947 | if (l == token_start) | |
948 | { | |
48401fcf | 949 | as_bad (_("expecting prefix; got nothing")); |
355afbcd KR |
950 | return; |
951 | } | |
952 | END_STRING_AND_SAVE (l); | |
953 | prefix = (prefix_entry *) hash_find (prefix_hash, token_start); | |
954 | if (!prefix) | |
955 | { | |
48401fcf | 956 | as_bad (_("no such opcode prefix `%s'"), token_start); |
4498e3d6 | 957 | RESTORE_END_STRING (l); |
355afbcd KR |
958 | return; |
959 | } | |
960 | RESTORE_END_STRING (l); | |
aa56747a ILT |
961 | /* add prefix, checking for repeated prefixes */ |
962 | switch (add_prefix (prefix->prefix_code)) | |
4498e3d6 | 963 | { |
aa56747a ILT |
964 | case 0: return; |
965 | case 2: | |
966 | expecting_string_instruction = prefix->prefix_name; | |
967 | break; | |
355afbcd | 968 | } |
4498e3d6 | 969 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
355afbcd KR |
970 | token_start = ++l; |
971 | } | |
972 | } | |
973 | END_STRING_AND_SAVE (l); | |
974 | if (token_start == l) | |
975 | { | |
48401fcf | 976 | as_bad (_("expecting opcode; got nothing")); |
4498e3d6 | 977 | RESTORE_END_STRING (l); |
355afbcd KR |
978 | return; |
979 | } | |
980 | ||
981 | /* Lookup insn in hash; try intel & att naming conventions if appropriate; | |
49864cfa | 982 | that is: we only use the opcode suffix 'b' 'w' or 'l' if we need to. */ |
355afbcd KR |
983 | current_templates = (templates *) hash_find (op_hash, token_start); |
984 | if (!current_templates) | |
985 | { | |
986 | int last_index = strlen (token_start) - 1; | |
987 | char last_char = token_start[last_index]; | |
988 | switch (last_char) | |
989 | { | |
990 | case DWORD_OPCODE_SUFFIX: | |
991 | case WORD_OPCODE_SUFFIX: | |
992 | case BYTE_OPCODE_SUFFIX: | |
993 | token_start[last_index] = '\0'; | |
994 | current_templates = (templates *) hash_find (op_hash, token_start); | |
995 | token_start[last_index] = last_char; | |
996 | i.suffix = last_char; | |
997 | } | |
998 | if (!current_templates) | |
999 | { | |
48401fcf | 1000 | as_bad (_("no such 386 instruction: `%s'"), token_start); |
4498e3d6 | 1001 | RESTORE_END_STRING (l); |
355afbcd KR |
1002 | return; |
1003 | } | |
1004 | } | |
1005 | RESTORE_END_STRING (l); | |
1006 | ||
1007 | /* check for rep/repne without a string instruction */ | |
1008 | if (expecting_string_instruction && | |
4498e3d6 | 1009 | !(current_templates->start->opcode_modifier & IsString)) |
355afbcd | 1010 | { |
48401fcf | 1011 | as_bad (_("expecting string instruction after `%s'"), |
4498e3d6 | 1012 | expecting_string_instruction); |
355afbcd KR |
1013 | return; |
1014 | } | |
1015 | ||
1016 | /* There may be operands to parse. */ | |
4498e3d6 | 1017 | if (*l != END_OF_INSN) |
355afbcd KR |
1018 | { |
1019 | /* parse operands */ | |
1020 | do | |
1021 | { | |
1022 | /* skip optional white space before operand */ | |
1023 | while (!is_operand_char (*l) && *l != END_OF_INSN) | |
1024 | { | |
1025 | if (!is_space_char (*l)) | |
1026 | { | |
48401fcf | 1027 | as_bad (_("invalid character %s before operand %d"), |
aa56747a ILT |
1028 | output_invalid (*l), |
1029 | i.operands + 1); | |
355afbcd KR |
1030 | return; |
1031 | } | |
1032 | l++; | |
1033 | } | |
1034 | token_start = l; /* after white space */ | |
0b476c53 ILT |
1035 | paren_not_balanced = 0; |
1036 | while (paren_not_balanced || *l != ',') | |
355afbcd KR |
1037 | { |
1038 | if (*l == END_OF_INSN) | |
1039 | { | |
0b476c53 | 1040 | if (paren_not_balanced) |
355afbcd | 1041 | { |
48401fcf | 1042 | as_bad (_("unbalanced parenthesis in operand %d."), |
aa56747a | 1043 | i.operands + 1); |
355afbcd KR |
1044 | return; |
1045 | } | |
1046 | else | |
1047 | break; /* we are done */ | |
1048 | } | |
ad660eb1 | 1049 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
355afbcd | 1050 | { |
48401fcf | 1051 | as_bad (_("invalid character %s in operand %d"), |
aa56747a ILT |
1052 | output_invalid (*l), |
1053 | i.operands + 1); | |
355afbcd KR |
1054 | return; |
1055 | } | |
1056 | if (*l == '(') | |
0b476c53 | 1057 | ++paren_not_balanced; |
355afbcd | 1058 | if (*l == ')') |
0b476c53 | 1059 | --paren_not_balanced; |
355afbcd KR |
1060 | l++; |
1061 | } | |
1062 | if (l != token_start) | |
1063 | { /* yes, we've read in another operand */ | |
1064 | unsigned int operand_ok; | |
1065 | this_operand = i.operands++; | |
1066 | if (i.operands > MAX_OPERANDS) | |
1067 | { | |
48401fcf | 1068 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
355afbcd KR |
1069 | MAX_OPERANDS); |
1070 | return; | |
1071 | } | |
1072 | /* now parse operand adding info to 'i' as we go along */ | |
1073 | END_STRING_AND_SAVE (l); | |
1074 | operand_ok = i386_operand (token_start); | |
1075 | RESTORE_END_STRING (l); /* restore old contents */ | |
1076 | if (!operand_ok) | |
1077 | return; | |
1078 | } | |
1079 | else | |
1080 | { | |
1081 | if (expecting_operand) | |
1082 | { | |
1083 | expecting_operand_after_comma: | |
48401fcf | 1084 | as_bad (_("expecting operand after ','; got nothing")); |
355afbcd KR |
1085 | return; |
1086 | } | |
1087 | if (*l == ',') | |
1088 | { | |
48401fcf | 1089 | as_bad (_("expecting operand before ','; got nothing")); |
355afbcd KR |
1090 | return; |
1091 | } | |
1092 | } | |
1093 | ||
1094 | /* now *l must be either ',' or END_OF_INSN */ | |
1095 | if (*l == ',') | |
1096 | { | |
1097 | if (*++l == END_OF_INSN) | |
1098 | { /* just skip it, if it's \n complain */ | |
1099 | goto expecting_operand_after_comma; | |
1100 | } | |
1101 | expecting_operand = 1; | |
1102 | } | |
1103 | } | |
1104 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | /* Now we've parsed the opcode into a set of templates, and have the | |
c5dd66a1 KR |
1109 | operands at hand. |
1110 | ||
1111 | Next, we find a template that matches the given insn, | |
1112 | making sure the overlap of the given operands types is consistent | |
1113 | with the template operand types. */ | |
355afbcd | 1114 | |
fecd2382 | 1115 | #define MATCH(overlap,given_type) \ |
ec1e6bb8 ILT |
1116 | (overlap \ |
1117 | && ((overlap & (JumpAbsolute|BaseIndex|Mem8)) \ | |
1118 | == (given_type & (JumpAbsolute|BaseIndex|Mem8)))) | |
355afbcd KR |
1119 | |
1120 | /* If m0 and m1 are register matches they must be consistent | |
c5dd66a1 KR |
1121 | with the expected operand types t0 and t1. |
1122 | That is, if both m0 & m1 are register matches | |
1123 | i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ? | |
1124 | then, either 1. or 2. must be true: | |
1125 | 1. the expected operand type register overlap is null: | |
1126 | (t0 & t1 & Reg) == 0 | |
1127 | AND | |
1128 | the given register overlap is null: | |
1129 | (m0 & m1 & Reg) == 0 | |
1130 | 2. the expected operand type register overlap == the given | |
1131 | operand type overlap: (t0 & t1 & m0 & m1 & Reg). | |
1132 | */ | |
a39116f1 RP |
1133 | #define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \ |
1134 | ( ((m0 & (Reg)) && (m1 & (Reg))) ? \ | |
1135 | ( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \ | |
1136 | ((t0 & t1) & (m0 & m1) & (Reg)) \ | |
1137 | ) : 1) | |
355afbcd KR |
1138 | { |
1139 | register unsigned int overlap0, overlap1; | |
1140 | expressionS *exp; | |
1141 | unsigned int overlap2; | |
1142 | unsigned int found_reverse_match; | |
1143 | ||
1144 | overlap0 = overlap1 = overlap2 = found_reverse_match = 0; | |
1145 | for (t = current_templates->start; | |
1146 | t < current_templates->end; | |
1147 | t++) | |
1148 | { | |
355afbcd KR |
1149 | /* must have right number of operands */ |
1150 | if (i.operands != t->operands) | |
1151 | continue; | |
1152 | else if (!t->operands) | |
1153 | break; /* 0 operands always matches */ | |
1154 | ||
1155 | overlap0 = i.types[0] & t->operand_types[0]; | |
1156 | switch (t->operands) | |
1157 | { | |
1158 | case 1: | |
1159 | if (!MATCH (overlap0, i.types[0])) | |
1160 | continue; | |
1161 | break; | |
1162 | case 2: | |
1163 | case 3: | |
1164 | overlap1 = i.types[1] & t->operand_types[1]; | |
1165 | if (!MATCH (overlap0, i.types[0]) || | |
1166 | !MATCH (overlap1, i.types[1]) || | |
1167 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap1, | |
1168 | t->operand_types[0], | |
1169 | t->operand_types[1])) | |
542e1629 | 1170 | { |
355afbcd KR |
1171 | |
1172 | /* check if other direction is valid ... */ | |
1173 | if (!(t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS)) | |
1174 | continue; | |
1175 | ||
1176 | /* try reversing direction of operands */ | |
1177 | overlap0 = i.types[0] & t->operand_types[1]; | |
1178 | overlap1 = i.types[1] & t->operand_types[0]; | |
1179 | if (!MATCH (overlap0, i.types[0]) || | |
1180 | !MATCH (overlap1, i.types[1]) || | |
1181 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap1, | |
227b6b55 ILT |
1182 | t->operand_types[1], |
1183 | t->operand_types[0])) | |
355afbcd KR |
1184 | { |
1185 | /* does not match either direction */ | |
1186 | continue; | |
1187 | } | |
1188 | /* found a reverse match here -- slip through */ | |
1189 | /* found_reverse_match holds which of D or FloatD we've found */ | |
1190 | found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS; | |
1191 | } /* endif: not forward match */ | |
1192 | /* found either forward/reverse 2 operand match here */ | |
1193 | if (t->operands == 3) | |
1194 | { | |
1195 | overlap2 = i.types[2] & t->operand_types[2]; | |
1196 | if (!MATCH (overlap2, i.types[2]) || | |
1197 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap2, | |
1198 | t->operand_types[0], | |
1199 | t->operand_types[2]) || | |
1200 | !CONSISTENT_REGISTER_MATCH (overlap1, overlap2, | |
1201 | t->operand_types[1], | |
1202 | t->operand_types[2])) | |
1203 | continue; | |
1204 | } | |
1205 | /* found either forward/reverse 2 or 3 operand match here: | |
c5dd66a1 | 1206 | slip through to break */ |
355afbcd KR |
1207 | } |
1208 | break; /* we've found a match; break out of loop */ | |
1209 | } /* for (t = ... */ | |
1210 | if (t == current_templates->end) | |
1211 | { /* we found no match */ | |
48401fcf | 1212 | as_bad (_("suffix or operands invalid for `%s'"), |
4498e3d6 | 1213 | current_templates->start->name); |
355afbcd KR |
1214 | return; |
1215 | } | |
1216 | ||
4498e3d6 | 1217 | /* Copy the template we found. */ |
f3d817d8 | 1218 | i.tm = *t; |
aa56747a ILT |
1219 | if (i.tm.opcode_modifier & FWait) |
1220 | if (! add_prefix (FWAIT_OPCODE)) | |
1221 | return; | |
227b6b55 ILT |
1222 | |
1223 | if (found_reverse_match) | |
1224 | { | |
1225 | i.tm.operand_types[0] = t->operand_types[1]; | |
1226 | i.tm.operand_types[1] = t->operand_types[0]; | |
1227 | } | |
355afbcd | 1228 | |
4498e3d6 ILT |
1229 | /* Check string instruction segment overrides */ |
1230 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1231 | { | |
1232 | int mem_op = (i.types[0] & Mem) ? 0 : 1; | |
8081c2be | 1233 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) |
4498e3d6 ILT |
1234 | { |
1235 | if (i.seg[0] != (seg_entry *) 0 && i.seg[0] != (seg_entry *) &es) | |
1236 | { | |
aa56747a ILT |
1237 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1238 | i.tm.name, | |
1239 | mem_op + 1); | |
4498e3d6 ILT |
1240 | return; |
1241 | } | |
1242 | /* There's only ever one segment override allowed per instruction. | |
1243 | This instruction possibly has a legal segment override on the | |
1244 | second operand, so copy the segment to where non-string | |
1245 | instructions store it, allowing common code. */ | |
1246 | i.seg[0] = i.seg[1]; | |
1247 | } | |
8081c2be | 1248 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) |
4498e3d6 ILT |
1249 | { |
1250 | if (i.seg[1] != (seg_entry *) 0 && i.seg[1] != (seg_entry *) &es) | |
1251 | { | |
aa56747a ILT |
1252 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1253 | i.tm.name, | |
1254 | mem_op + 2); | |
4498e3d6 ILT |
1255 | return; |
1256 | } | |
1257 | } | |
1258 | } | |
1259 | ||
c54c7aac KR |
1260 | /* If the matched instruction specifies an explicit opcode suffix, |
1261 | use it - and make sure none has already been specified. */ | |
227b6b55 | 1262 | if (i.tm.opcode_modifier & (Data16|Data32)) |
c54c7aac KR |
1263 | { |
1264 | if (i.suffix) | |
1265 | { | |
48401fcf | 1266 | as_bad (_("extraneous opcode suffix given")); |
c54c7aac KR |
1267 | return; |
1268 | } | |
227b6b55 | 1269 | if (i.tm.opcode_modifier & Data16) |
c54c7aac KR |
1270 | i.suffix = WORD_OPCODE_SUFFIX; |
1271 | else | |
1272 | i.suffix = DWORD_OPCODE_SUFFIX; | |
1273 | } | |
1274 | ||
355afbcd | 1275 | /* If there's no opcode suffix we try to invent one based on register |
c5dd66a1 | 1276 | operands. */ |
355afbcd KR |
1277 | if (!i.suffix && i.reg_operands) |
1278 | { | |
1279 | /* We take i.suffix from the LAST register operand specified. This | |
c5dd66a1 KR |
1280 | assumes that the last register operands is the destination register |
1281 | operand. */ | |
ad660eb1 ILT |
1282 | int op; |
1283 | for (op = 0; op < MAX_OPERANDS; op++) | |
1284 | if (i.types[op] & Reg) | |
355afbcd | 1285 | { |
e592f0e6 ILT |
1286 | i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX : |
1287 | (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX : | |
ad660eb1 | 1288 | DWORD_OPCODE_SUFFIX); |
355afbcd KR |
1289 | } |
1290 | } | |
3ea36b53 ILT |
1291 | else if (i.suffix != 0 |
1292 | && i.reg_operands != 0 | |
1293 | && (i.types[i.operands - 1] & Reg) != 0) | |
1294 | { | |
e592f0e6 | 1295 | int bad; |
3ea36b53 ILT |
1296 | |
1297 | /* If the last operand is a register, make sure it is | |
1298 | compatible with the suffix. */ | |
1299 | ||
e592f0e6 | 1300 | bad = 0; |
3ea36b53 ILT |
1301 | switch (i.suffix) |
1302 | { | |
1303 | default: | |
1304 | abort (); | |
1305 | case BYTE_OPCODE_SUFFIX: | |
e592f0e6 ILT |
1306 | /* If this is an eight bit register, it's OK. If it's the |
1307 | 16 or 32 bit version of an eight bit register, we will | |
1308 | just use the low portion, and that's OK too. */ | |
1309 | if ((i.types[i.operands - 1] & Reg8) == 0 | |
1310 | && i.regs[i.operands - 1]->reg_num >= 4) | |
1311 | bad = 1; | |
3ea36b53 ILT |
1312 | break; |
1313 | case WORD_OPCODE_SUFFIX: | |
3ea36b53 | 1314 | case DWORD_OPCODE_SUFFIX: |
e592f0e6 ILT |
1315 | /* We don't insist on the presence or absence of the e |
1316 | prefix on the register, but we reject eight bit | |
1317 | registers. */ | |
1318 | if ((i.types[i.operands - 1] & Reg8) != 0) | |
1319 | bad = 1; | |
3ea36b53 | 1320 | } |
e592f0e6 | 1321 | if (bad) |
48401fcf | 1322 | as_bad (_("register does not match opcode suffix")); |
3ea36b53 | 1323 | } |
355afbcd KR |
1324 | |
1325 | /* Make still unresolved immediate matches conform to size of immediate | |
c5dd66a1 KR |
1326 | given in i.suffix. Note: overlap2 cannot be an immediate! |
1327 | We assume this. */ | |
355afbcd KR |
1328 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
1329 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1330 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1331 | { | |
1332 | if (!i.suffix) | |
1333 | { | |
48401fcf | 1334 | as_bad (_("no opcode suffix given; can't determine immediate size")); |
355afbcd KR |
1335 | return; |
1336 | } | |
1337 | overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1338 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1339 | } | |
1340 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1341 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1342 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1343 | { | |
1344 | if (!i.suffix) | |
1345 | { | |
48401fcf | 1346 | as_bad (_("no opcode suffix given; can't determine immediate size")); |
355afbcd KR |
1347 | return; |
1348 | } | |
1349 | overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1350 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1351 | } | |
1352 | ||
1353 | i.types[0] = overlap0; | |
1354 | i.types[1] = overlap1; | |
1355 | i.types[2] = overlap2; | |
1356 | ||
1357 | if (overlap0 & ImplicitRegister) | |
1358 | i.reg_operands--; | |
1359 | if (overlap1 & ImplicitRegister) | |
1360 | i.reg_operands--; | |
1361 | if (overlap2 & ImplicitRegister) | |
1362 | i.reg_operands--; | |
1363 | if (overlap0 & Imm1) | |
1364 | i.imm_operands = 0; /* kludge for shift insns */ | |
1365 | ||
355afbcd | 1366 | /* Finalize opcode. First, we change the opcode based on the operand |
c5dd66a1 KR |
1367 | size given by i.suffix: we never have to change things for byte insns, |
1368 | or when no opcode suffix is need to size the operands. */ | |
355afbcd | 1369 | |
227b6b55 | 1370 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
355afbcd | 1371 | { |
48401fcf | 1372 | as_bad (_("no opcode suffix given and no register operands; can't size instruction")); |
355afbcd KR |
1373 | return; |
1374 | } | |
1375 | ||
1376 | if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX) | |
1377 | { | |
1378 | /* Select between byte and word/dword operations. */ | |
227b6b55 ILT |
1379 | if (i.tm.opcode_modifier & W) |
1380 | i.tm.base_opcode |= W; | |
8c927202 ILT |
1381 | /* Now select between word & dword operations via the operand |
1382 | size prefix. */ | |
c54c7aac | 1383 | if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code) |
355afbcd | 1384 | { |
aa56747a ILT |
1385 | unsigned char prefix = WORD_PREFIX_OPCODE; |
1386 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
1387 | prefix = ADDR_PREFIX_OPCODE; | |
1388 | ||
1389 | if (! add_prefix (prefix)) | |
4498e3d6 | 1390 | return; |
355afbcd KR |
1391 | } |
1392 | } | |
1393 | ||
1394 | /* For insns with operands there are more diddles to do to the opcode. */ | |
1395 | if (i.operands) | |
1396 | { | |
c54c7aac KR |
1397 | /* Default segment register this instruction will use |
1398 | for memory accesses. 0 means unknown. | |
1399 | This is only for optimizing out unnecessary segment overrides. */ | |
1400 | const seg_entry *default_seg = 0; | |
1401 | ||
1402 | /* True if this instruction uses a memory addressing mode, | |
1403 | and therefore may need an address-size prefix. */ | |
1404 | int uses_mem_addrmode = 0; | |
1405 | ||
1406 | ||
aa56747a ILT |
1407 | /* If we found a reverse match we must alter the opcode |
1408 | direction bit. found_reverse_match holds bits to change | |
1409 | (different for int & float insns). */ | |
355afbcd | 1410 | |
4498e3d6 | 1411 | i.tm.base_opcode ^= found_reverse_match; |
355afbcd | 1412 | |
c5dd66a1 | 1413 | /* The imul $imm, %reg instruction is converted into |
4498e3d6 ILT |
1414 | imul $imm, %reg, %reg, and the clr %reg instruction |
1415 | is converted into xor %reg, %reg. */ | |
1416 | if (i.tm.opcode_modifier & regKludge) | |
2fb44892 | 1417 | { |
4498e3d6 ILT |
1418 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; |
1419 | /* Pretend we saw the extra register operand. */ | |
1420 | i.regs[first_reg_op+1] = i.regs[first_reg_op]; | |
2fb44892 ILT |
1421 | i.reg_operands = 2; |
1422 | } | |
1423 | ||
227b6b55 | 1424 | if (i.tm.opcode_modifier & ShortForm) |
355afbcd KR |
1425 | { |
1426 | /* The register or float register operand is in operand 0 or 1. */ | |
ad660eb1 | 1427 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
355afbcd | 1428 | /* Register goes in low 3 bits of opcode. */ |
227b6b55 | 1429 | i.tm.base_opcode |= i.regs[op]->reg_num; |
355afbcd | 1430 | } |
227b6b55 | 1431 | else if (i.tm.opcode_modifier & ShortFormW) |
355afbcd KR |
1432 | { |
1433 | /* Short form with 0x8 width bit. Register is always dest. operand */ | |
227b6b55 | 1434 | i.tm.base_opcode |= i.regs[1]->reg_num; |
355afbcd KR |
1435 | if (i.suffix == WORD_OPCODE_SUFFIX || |
1436 | i.suffix == DWORD_OPCODE_SUFFIX) | |
227b6b55 | 1437 | i.tm.base_opcode |= 0x8; |
355afbcd | 1438 | } |
227b6b55 | 1439 | else if (i.tm.opcode_modifier & Modrm) |
355afbcd | 1440 | { |
227b6b55 ILT |
1441 | /* The opcode is completed (modulo i.tm.extension_opcode which |
1442 | must be put into the modrm byte). | |
1443 | Now, we make the modrm & index base bytes based on all the | |
1444 | info we've collected. */ | |
355afbcd KR |
1445 | |
1446 | /* i.reg_operands MUST be the number of real register operands; | |
c5dd66a1 | 1447 | implicit registers do not count. */ |
355afbcd KR |
1448 | if (i.reg_operands == 2) |
1449 | { | |
1450 | unsigned int source, dest; | |
454b0ccd ILT |
1451 | source = ((i.types[0] |
1452 | & (Reg | |
1453 | | SReg2 | |
1454 | | SReg3 | |
1455 | | Control | |
1456 | | Debug | |
1457 | | Test | |
1458 | | RegMMX)) | |
1459 | ? 0 : 1); | |
355afbcd | 1460 | dest = source + 1; |
4498e3d6 ILT |
1461 | |
1462 | /* Certain instructions expect the destination to be | |
1463 | in the i.rm.reg field. This is by far the | |
1464 | exceptional case. For these instructions, if the | |
1465 | source operand is a register, we must reverse the | |
1466 | i.rm.reg and i.rm.regmem fields. We accomplish | |
1467 | this by pretending that the two register operands | |
1468 | were given in the reverse order. */ | |
1469 | if (i.tm.opcode_modifier & ReverseRegRegmem) | |
1470 | { | |
1471 | reg_entry *tmp = i.regs[source]; | |
1472 | i.regs[source] = i.regs[dest]; | |
1473 | i.regs[dest] = tmp; | |
1474 | } | |
1475 | ||
355afbcd | 1476 | i.rm.mode = 3; |
c5dd66a1 | 1477 | /* We must be careful to make sure that all |
454b0ccd | 1478 | segment/control/test/debug/MMX registers go into |
4498e3d6 | 1479 | the i.rm.reg field (despite whether they are |
454b0ccd ILT |
1480 | source or destination operands). */ |
1481 | if (i.regs[dest]->reg_type | |
1482 | & (SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
1483 | { |
1484 | i.rm.reg = i.regs[dest]->reg_num; | |
1485 | i.rm.regmem = i.regs[source]->reg_num; | |
1486 | } | |
1487 | else | |
1488 | { | |
1489 | i.rm.reg = i.regs[source]->reg_num; | |
1490 | i.rm.regmem = i.regs[dest]->reg_num; | |
1491 | } | |
1492 | } | |
1493 | else | |
1494 | { /* if it's not 2 reg operands... */ | |
1495 | if (i.mem_operands) | |
1496 | { | |
1497 | unsigned int fake_zero_displacement = 0; | |
4498e3d6 ILT |
1498 | unsigned int op = ((i.types[0] & Mem) |
1499 | ? 0 | |
1500 | : (i.types[1] & Mem) ? 1 : 2); | |
355afbcd | 1501 | |
ec1e6bb8 | 1502 | default_seg = &ds; |
355afbcd | 1503 | |
ec1e6bb8 | 1504 | if (! i.base_reg) |
355afbcd | 1505 | { |
ec1e6bb8 ILT |
1506 | i.rm.mode = 0; |
1507 | if (! i.disp_operands) | |
1508 | fake_zero_displacement = 1; | |
1509 | if (! i.index_reg) | |
355afbcd | 1510 | { |
ec1e6bb8 ILT |
1511 | /* Operand is just <disp> */ |
1512 | i.rm.regmem = NO_BASE_REGISTER; | |
1513 | i.types[op] &= ~Disp; | |
1514 | i.types[op] |= Disp32; | |
355afbcd KR |
1515 | } |
1516 | else | |
1517 | { | |
ec1e6bb8 ILT |
1518 | i.bi.index = i.index_reg->reg_num; |
1519 | i.bi.base = NO_BASE_REGISTER; | |
1520 | i.bi.scale = i.log2_scale_factor; | |
1521 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1522 | i.types[op] &= ~Disp; | |
1523 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
355afbcd KR |
1524 | } |
1525 | } | |
ec1e6bb8 | 1526 | else /* i.base_reg */ |
355afbcd | 1527 | { |
355afbcd | 1528 | i.rm.regmem = i.base_reg->reg_num; |
ec1e6bb8 ILT |
1529 | i.bi.base = i.base_reg->reg_num; |
1530 | if (i.base_reg->reg_num == EBP_REG_NUM) | |
355afbcd | 1531 | { |
ec1e6bb8 ILT |
1532 | default_seg = &ss; |
1533 | if (i.disp_operands == 0) | |
1534 | { | |
355afbcd | 1535 | fake_zero_displacement = 1; |
ad660eb1 | 1536 | i.types[op] |= Disp8; |
355afbcd KR |
1537 | } |
1538 | } | |
ec1e6bb8 ILT |
1539 | else if (i.base_reg->reg_num == ESP_REG_NUM) |
1540 | { | |
1541 | default_seg = &ss; | |
1542 | } | |
1543 | i.bi.scale = i.log2_scale_factor; | |
1544 | if (! i.index_reg) | |
1545 | { | |
1546 | /* <disp>(%esp) becomes two byte modrm | |
1547 | with no index register. We've already | |
1548 | stored the code for esp in i.rm.regmem | |
1549 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
1550 | base register besides %esp will not use | |
1551 | the extra modrm byte. */ | |
1552 | i.bi.index = NO_INDEX_REGISTER; | |
1553 | #if ! SCALE1_WHEN_NO_INDEX | |
1554 | /* Another case where we force the second | |
1555 | modrm byte. */ | |
1556 | if (i.log2_scale_factor) | |
1557 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1558 | #endif | |
1559 | } | |
1560 | else | |
1561 | { | |
1562 | i.bi.index = i.index_reg->reg_num; | |
1563 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1564 | } | |
1565 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
355afbcd | 1566 | } |
ec1e6bb8 | 1567 | |
355afbcd KR |
1568 | if (fake_zero_displacement) |
1569 | { | |
ad660eb1 | 1570 | /* Fakes a zero displacement assuming that i.types[op] |
c5dd66a1 | 1571 | holds the correct displacement size. */ |
355afbcd | 1572 | exp = &disp_expressions[i.disp_operands++]; |
ad660eb1 | 1573 | i.disps[op] = exp; |
5ac34ac3 | 1574 | exp->X_op = O_constant; |
355afbcd KR |
1575 | exp->X_add_number = 0; |
1576 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 1577 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 1578 | } |
355afbcd KR |
1579 | } |
1580 | ||
454b0ccd | 1581 | /* Fill in i.rm.reg or i.rm.regmem field with register |
227b6b55 ILT |
1582 | operand (if any) based on i.tm.extension_opcode. |
1583 | Again, we must be careful to make sure that | |
1584 | segment/control/debug/test/MMX registers are coded | |
1585 | into the i.rm.reg field. */ | |
355afbcd KR |
1586 | if (i.reg_operands) |
1587 | { | |
ad660eb1 | 1588 | unsigned int op = |
454b0ccd ILT |
1589 | ((i.types[0] |
1590 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1591 | | Test | RegMMX)) | |
1592 | ? 0 | |
1593 | : ((i.types[1] | |
1594 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1595 | | Test | RegMMX)) | |
1596 | ? 1 | |
1597 | : 2)); | |
c5dd66a1 KR |
1598 | /* If there is an extension opcode to put here, the |
1599 | register number must be put into the regmem field. */ | |
227b6b55 | 1600 | if (i.tm.extension_opcode != None) |
ad660eb1 | 1601 | i.rm.regmem = i.regs[op]->reg_num; |
355afbcd | 1602 | else |
ad660eb1 | 1603 | i.rm.reg = i.regs[op]->reg_num; |
355afbcd KR |
1604 | |
1605 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
c5dd66a1 | 1606 | we must set it to 3 to indicate this is a register |
4498e3d6 | 1607 | operand in the regmem field. */ |
355afbcd KR |
1608 | if (!i.mem_operands) |
1609 | i.rm.mode = 3; | |
1610 | } | |
1611 | ||
1612 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
227b6b55 ILT |
1613 | if (i.tm.extension_opcode != None) |
1614 | i.rm.reg = i.tm.extension_opcode; | |
355afbcd | 1615 | } |
c54c7aac KR |
1616 | |
1617 | if (i.rm.mode != 3) | |
1618 | uses_mem_addrmode = 1; | |
1619 | } | |
4498e3d6 ILT |
1620 | else if (i.tm.opcode_modifier & Seg2ShortForm) |
1621 | { | |
1622 | if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) | |
1623 | { | |
aa56747a | 1624 | as_bad (_("you can't `pop %%cs' on the 386.")); |
4498e3d6 ILT |
1625 | return; |
1626 | } | |
1627 | i.tm.base_opcode |= (i.regs[0]->reg_num << 3); | |
1628 | } | |
1629 | else if (i.tm.opcode_modifier & Seg3ShortForm) | |
1630 | { | |
1631 | /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1. | |
1632 | 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9. | |
1633 | So, only if i.regs[0]->reg_num == 5 (%gs) do we need | |
1634 | to change the opcode. */ | |
1635 | if (i.regs[0]->reg_num == 5) | |
1636 | i.tm.base_opcode |= 0x08; | |
1637 | } | |
1638 | else if ((i.tm.base_opcode & ~DW) == MOV_AX_DISP32) | |
1639 | { | |
1640 | /* This is a special non-modrm instruction | |
1641 | that addresses memory with a 32-bit displacement mode anyway, | |
1642 | and thus requires an address-size prefix if in 16-bit mode. */ | |
1643 | uses_mem_addrmode = 1; | |
1644 | default_seg = &ds; | |
1645 | } | |
1646 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
1647 | { | |
1648 | /* For the string instructions that allow a segment override | |
1649 | on one of their operands, the default segment is ds. */ | |
1650 | default_seg = &ds; | |
1651 | } | |
c54c7aac KR |
1652 | |
1653 | /* GAS currently doesn't support 16-bit memory addressing modes at all, | |
1654 | so if we're writing 16-bit code and using a memory addressing mode, | |
1655 | always spew out an address size prefix. */ | |
1656 | if (uses_mem_addrmode && flag_16bit_code) | |
1657 | { | |
aa56747a | 1658 | if (! add_prefix (ADDR_PREFIX_OPCODE)) |
4498e3d6 | 1659 | return; |
c54c7aac KR |
1660 | } |
1661 | ||
1662 | /* If a segment was explicitly specified, | |
1663 | and the specified segment is not the default, | |
1664 | use an opcode prefix to select it. | |
1665 | If we never figured out what the default segment is, | |
1666 | then default_seg will be zero at this point, | |
1667 | and the specified segment prefix will always be used. */ | |
4498e3d6 | 1668 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
c54c7aac | 1669 | { |
aa56747a | 1670 | if (! add_prefix (i.seg[0]->seg_prefix)) |
4498e3d6 | 1671 | return; |
355afbcd KR |
1672 | } |
1673 | } | |
1674 | } | |
1675 | ||
1676 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
227b6b55 | 1677 | if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) |
355afbcd | 1678 | { |
227b6b55 | 1679 | i.tm.base_opcode = INT3_OPCODE; |
355afbcd KR |
1680 | i.imm_operands = 0; |
1681 | } | |
1682 | ||
1683 | /* We are ready to output the insn. */ | |
1684 | { | |
1685 | register char *p; | |
1686 | ||
1687 | /* Output jumps. */ | |
227b6b55 | 1688 | if (i.tm.opcode_modifier & Jump) |
355afbcd | 1689 | { |
ad660eb1 | 1690 | unsigned long n = i.disps[0]->X_add_number; |
355afbcd | 1691 | |
4498e3d6 | 1692 | if (i.prefixes != 0) |
aa56747a | 1693 | as_warn (_("skipping prefixes on this instruction")); |
4498e3d6 | 1694 | |
5ac34ac3 | 1695 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1696 | { |
355afbcd KR |
1697 | if (fits_in_signed_byte (n)) |
1698 | { | |
1699 | p = frag_more (2); | |
ad660eb1 | 1700 | insn_size += 2; |
227b6b55 | 1701 | p[0] = i.tm.base_opcode; |
355afbcd | 1702 | p[1] = n; |
355afbcd | 1703 | } |
355afbcd | 1704 | else |
c54c7aac KR |
1705 | { /* It's an absolute word/dword displacement. */ |
1706 | ||
4498e3d6 | 1707 | /* Use 16-bit jumps only for 16-bit code, |
c54c7aac | 1708 | because text segments are limited to 64K anyway; |
4498e3d6 ILT |
1709 | Use 32-bit jumps for 32-bit code, because they're faster, |
1710 | and a 16-bit jump will clear the top 16 bits of %eip. */ | |
c54c7aac KR |
1711 | int jmp_size = flag_16bit_code ? 2 : 4; |
1712 | if (flag_16bit_code && !fits_in_signed_word (n)) | |
1713 | { | |
48401fcf | 1714 | as_bad (_("16-bit jump out of range")); |
c54c7aac KR |
1715 | return; |
1716 | } | |
1717 | ||
227b6b55 | 1718 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) |
355afbcd KR |
1719 | { /* pace */ |
1720 | /* unconditional jump */ | |
c54c7aac KR |
1721 | p = frag_more (1 + jmp_size); |
1722 | insn_size += 1 + jmp_size; | |
7b23213f | 1723 | p[0] = (char) 0xe9; |
c54c7aac | 1724 | md_number_to_chars (&p[1], (valueT) n, jmp_size); |
355afbcd KR |
1725 | } |
1726 | else | |
1727 | { | |
1728 | /* conditional jump */ | |
c54c7aac KR |
1729 | p = frag_more (2 + jmp_size); |
1730 | insn_size += 2 + jmp_size; | |
355afbcd | 1731 | p[0] = TWO_BYTE_OPCODE_ESCAPE; |
227b6b55 | 1732 | p[1] = i.tm.base_opcode + 0x10; |
c54c7aac | 1733 | md_number_to_chars (&p[2], (valueT) n, jmp_size); |
355afbcd KR |
1734 | } |
1735 | } | |
49864cfa KR |
1736 | } |
1737 | else | |
1738 | { | |
c54c7aac KR |
1739 | if (flag_16bit_code) |
1740 | { | |
1741 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1742 | insn_size += 1; | |
1743 | } | |
1744 | ||
355afbcd | 1745 | /* It's a symbol; end frag & setup for relax. |
49864cfa KR |
1746 | Make sure there are more than 6 chars left in the current frag; |
1747 | if not we'll have to start a new one. */ | |
3ea36b53 | 1748 | frag_grow (7); |
355afbcd | 1749 | p = frag_more (1); |
ad660eb1 | 1750 | insn_size += 1; |
227b6b55 | 1751 | p[0] = i.tm.base_opcode; |
355afbcd KR |
1752 | frag_var (rs_machine_dependent, |
1753 | 6, /* 2 opcode/prefix + 4 displacement */ | |
1754 | 1, | |
1755 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
1756 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE) | |
1757 | : ENCODE_RELAX_STATE (COND_JUMP, BYTE)), | |
1758 | i.disps[0]->X_add_symbol, | |
f59fb6ca | 1759 | (offsetT) n, p); |
355afbcd KR |
1760 | } |
1761 | } | |
227b6b55 | 1762 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) |
355afbcd | 1763 | { |
227b6b55 | 1764 | int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4; |
ad660eb1 | 1765 | unsigned long n = i.disps[0]->X_add_number; |
c54c7aac KR |
1766 | unsigned char *q; |
1767 | ||
aa56747a | 1768 | if (size == 1) /* then this is a loop or jecxz type instruction */ |
c54c7aac | 1769 | { |
aa56747a | 1770 | if (i.prefix[ADDR_PREFIX]) |
c54c7aac | 1771 | { |
aa56747a ILT |
1772 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
1773 | i.prefixes -= 1; | |
1774 | insn_size += 1; | |
c54c7aac KR |
1775 | } |
1776 | } | |
1777 | ||
aa56747a ILT |
1778 | if (i.prefixes != 0) |
1779 | as_warn (_("skipping prefixes on this instruction")); | |
1780 | ||
c54c7aac KR |
1781 | if ((size == 4) && (flag_16bit_code)) |
1782 | { | |
1783 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1784 | insn_size += 1; | |
1785 | } | |
355afbcd | 1786 | |
227b6b55 | 1787 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 1788 | { |
227b6b55 | 1789 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
ad660eb1 | 1790 | insn_size += 1; |
355afbcd KR |
1791 | } |
1792 | else | |
1793 | { | |
1794 | p = frag_more (2); /* opcode can be at most two bytes */ | |
ad660eb1 | 1795 | insn_size += 2; |
355afbcd | 1796 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
1797 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
1798 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
1799 | } |
1800 | ||
1801 | p = frag_more (size); | |
ad660eb1 | 1802 | insn_size += size; |
5ac34ac3 | 1803 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1804 | { |
ad660eb1 | 1805 | md_number_to_chars (p, (valueT) n, size); |
355afbcd KR |
1806 | if (size == 1 && !fits_in_signed_byte (n)) |
1807 | { | |
48401fcf | 1808 | as_bad (_("loop/jecx only takes byte displacement; %lu shortened to %d"), |
355afbcd KR |
1809 | n, *p); |
1810 | } | |
49864cfa KR |
1811 | } |
1812 | else | |
1813 | { | |
5ac34ac3 | 1814 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a KR |
1815 | i.disps[0], 1, reloc (size, 1, i.disp_reloc[0])); |
1816 | ||
355afbcd KR |
1817 | } |
1818 | } | |
227b6b55 | 1819 | else if (i.tm.opcode_modifier & JumpInterSegment) |
355afbcd | 1820 | { |
4498e3d6 | 1821 | if (i.prefixes != 0) |
aa56747a | 1822 | as_warn (_("skipping prefixes on this instruction")); |
4498e3d6 | 1823 | |
c54c7aac KR |
1824 | if (flag_16bit_code) |
1825 | { | |
1826 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1827 | insn_size += 1; | |
1828 | } | |
1829 | ||
355afbcd | 1830 | p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */ |
ad660eb1 | 1831 | insn_size += 1 + 2 + 4; |
227b6b55 | 1832 | p[0] = i.tm.base_opcode; |
5ac34ac3 | 1833 | if (i.imms[1]->X_op == O_constant) |
ad660eb1 | 1834 | md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4); |
355afbcd | 1835 | else |
5ac34ac3 | 1836 | fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4, |
7b23213f | 1837 | i.imms[1], 0, BFD_RELOC_32); |
5ac34ac3 | 1838 | if (i.imms[0]->X_op != O_constant) |
48401fcf | 1839 | as_bad (_("can't handle non absolute segment in long call/jmp")); |
ad660eb1 | 1840 | md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2); |
355afbcd KR |
1841 | } |
1842 | else | |
1843 | { | |
1844 | /* Output normal instructions here. */ | |
1845 | unsigned char *q; | |
1846 | ||
4498e3d6 | 1847 | /* The prefix bytes. */ |
aa56747a ILT |
1848 | for (q = i.prefix; |
1849 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
1850 | q++) | |
355afbcd | 1851 | { |
aa56747a ILT |
1852 | if (*q) |
1853 | { | |
1854 | p = frag_more (1); | |
1855 | insn_size += 1; | |
1856 | md_number_to_chars (p, (valueT) *q, 1); | |
1857 | } | |
355afbcd KR |
1858 | } |
1859 | ||
1860 | /* Now the opcode; be careful about word order here! */ | |
227b6b55 | 1861 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 1862 | { |
227b6b55 | 1863 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
ad660eb1 | 1864 | insn_size += 1; |
355afbcd | 1865 | } |
227b6b55 | 1866 | else if (fits_in_unsigned_word (i.tm.base_opcode)) |
355afbcd KR |
1867 | { |
1868 | p = frag_more (2); | |
ad660eb1 | 1869 | insn_size += 2; |
355afbcd | 1870 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
1871 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
1872 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
1873 | } |
1874 | else | |
1875 | { /* opcode is either 3 or 4 bytes */ | |
227b6b55 | 1876 | if (i.tm.base_opcode & 0xff000000) |
355afbcd KR |
1877 | { |
1878 | p = frag_more (4); | |
ad660eb1 | 1879 | insn_size += 4; |
227b6b55 | 1880 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
355afbcd KR |
1881 | } |
1882 | else | |
ad660eb1 ILT |
1883 | { |
1884 | p = frag_more (3); | |
1885 | insn_size += 3; | |
1886 | } | |
227b6b55 ILT |
1887 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
1888 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
1889 | *p = (i.tm.base_opcode) & 0xff; | |
355afbcd KR |
1890 | } |
1891 | ||
1892 | /* Now the modrm byte and base index byte (if present). */ | |
227b6b55 | 1893 | if (i.tm.opcode_modifier & Modrm) |
355afbcd KR |
1894 | { |
1895 | p = frag_more (1); | |
ad660eb1 | 1896 | insn_size += 1; |
355afbcd | 1897 | /* md_number_to_chars (p, i.rm, 1); */ |
ad660eb1 ILT |
1898 | md_number_to_chars (p, |
1899 | (valueT) (i.rm.regmem << 0 | |
1900 | | i.rm.reg << 3 | |
1901 | | i.rm.mode << 6), | |
1902 | 1); | |
355afbcd | 1903 | /* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode) |
a39116f1 | 1904 | ==> need second modrm byte. */ |
ec1e6bb8 ILT |
1905 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
1906 | && i.rm.mode != 3) | |
355afbcd KR |
1907 | { |
1908 | p = frag_more (1); | |
ad660eb1 | 1909 | insn_size += 1; |
355afbcd | 1910 | /* md_number_to_chars (p, i.bi, 1); */ |
ad660eb1 ILT |
1911 | md_number_to_chars (p, (valueT) (i.bi.base << 0 |
1912 | | i.bi.index << 3 | |
1913 | | i.bi.scale << 6), | |
1914 | 1); | |
355afbcd KR |
1915 | } |
1916 | } | |
1917 | ||
1918 | if (i.disp_operands) | |
1919 | { | |
1920 | register unsigned int n; | |
1921 | ||
1922 | for (n = 0; n < i.operands; n++) | |
1923 | { | |
1924 | if (i.disps[n]) | |
1925 | { | |
5ac34ac3 | 1926 | if (i.disps[n]->X_op == O_constant) |
355afbcd KR |
1927 | { |
1928 | if (i.types[n] & (Disp8 | Abs8)) | |
1929 | { | |
1930 | p = frag_more (1); | |
ad660eb1 ILT |
1931 | insn_size += 1; |
1932 | md_number_to_chars (p, | |
1933 | (valueT) i.disps[n]->X_add_number, | |
1934 | 1); | |
355afbcd KR |
1935 | } |
1936 | else if (i.types[n] & (Disp16 | Abs16)) | |
1937 | { | |
1938 | p = frag_more (2); | |
ad660eb1 ILT |
1939 | insn_size += 2; |
1940 | md_number_to_chars (p, | |
1941 | (valueT) i.disps[n]->X_add_number, | |
1942 | 2); | |
355afbcd KR |
1943 | } |
1944 | else | |
1945 | { /* Disp32|Abs32 */ | |
1946 | p = frag_more (4); | |
ad660eb1 ILT |
1947 | insn_size += 4; |
1948 | md_number_to_chars (p, | |
1949 | (valueT) i.disps[n]->X_add_number, | |
1950 | 4); | |
355afbcd KR |
1951 | } |
1952 | } | |
1953 | else | |
49864cfa | 1954 | { /* not absolute_section */ |
355afbcd KR |
1955 | /* need a 32-bit fixup (don't support 8bit non-absolute disps) */ |
1956 | p = frag_more (4); | |
ad660eb1 | 1957 | insn_size += 4; |
5ac34ac3 | 1958 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, |
f0b37b4a KR |
1959 | i.disps[n], 0, |
1960 | TC_RELOC(i.disp_reloc[n], BFD_RELOC_32)); | |
355afbcd KR |
1961 | } |
1962 | } | |
1963 | } | |
1964 | } /* end displacement output */ | |
1965 | ||
1966 | /* output immediate */ | |
1967 | if (i.imm_operands) | |
1968 | { | |
1969 | register unsigned int n; | |
1970 | ||
1971 | for (n = 0; n < i.operands; n++) | |
1972 | { | |
1973 | if (i.imms[n]) | |
1974 | { | |
5ac34ac3 | 1975 | if (i.imms[n]->X_op == O_constant) |
355afbcd KR |
1976 | { |
1977 | if (i.types[n] & (Imm8 | Imm8S)) | |
1978 | { | |
1979 | p = frag_more (1); | |
ad660eb1 ILT |
1980 | insn_size += 1; |
1981 | md_number_to_chars (p, | |
1982 | (valueT) i.imms[n]->X_add_number, | |
1983 | 1); | |
355afbcd KR |
1984 | } |
1985 | else if (i.types[n] & Imm16) | |
1986 | { | |
1987 | p = frag_more (2); | |
ad660eb1 ILT |
1988 | insn_size += 2; |
1989 | md_number_to_chars (p, | |
1990 | (valueT) i.imms[n]->X_add_number, | |
1991 | 2); | |
355afbcd KR |
1992 | } |
1993 | else | |
1994 | { | |
1995 | p = frag_more (4); | |
ad660eb1 ILT |
1996 | insn_size += 4; |
1997 | md_number_to_chars (p, | |
1998 | (valueT) i.imms[n]->X_add_number, | |
1999 | 4); | |
355afbcd KR |
2000 | } |
2001 | } | |
2002 | else | |
49864cfa | 2003 | { /* not absolute_section */ |
f0b37b4a KR |
2004 | /* Need a 32-bit fixup (don't support 8bit |
2005 | non-absolute ims). Try to support other | |
2006 | sizes ... */ | |
2007 | int r_type; | |
355afbcd | 2008 | int size; |
f0b37b4a KR |
2009 | int pcrel = 0; |
2010 | ||
355afbcd KR |
2011 | if (i.types[n] & (Imm8 | Imm8S)) |
2012 | size = 1; | |
2013 | else if (i.types[n] & Imm16) | |
2014 | size = 2; | |
2015 | else | |
2016 | size = 4; | |
f0b37b4a | 2017 | r_type = reloc (size, 0, i.disp_reloc[0]); |
355afbcd | 2018 | p = frag_more (size); |
ad660eb1 | 2019 | insn_size += size; |
f0b37b4a | 2020 | #ifdef BFD_ASSEMBLER |
c54c7aac | 2021 | if (r_type == BFD_RELOC_32 |
f0b37b4a | 2022 | && GOT_symbol |
0877841d ILT |
2023 | && GOT_symbol == i.imms[n]->X_add_symbol |
2024 | && (i.imms[n]->X_op == O_symbol | |
2025 | || (i.imms[n]->X_op == O_add | |
2026 | && (i.imms[n]->X_op_symbol->sy_value.X_op | |
2027 | == O_subtract)))) | |
f0b37b4a KR |
2028 | { |
2029 | r_type = BFD_RELOC_386_GOTPC; | |
2030 | i.imms[n]->X_add_number += 3; | |
2031 | } | |
2032 | #endif | |
5ac34ac3 | 2033 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a | 2034 | i.imms[n], pcrel, r_type); |
355afbcd KR |
2035 | } |
2036 | } | |
2037 | } | |
2038 | } /* end immediate output */ | |
2039 | } | |
2040 | ||
fecd2382 | 2041 | #ifdef DEBUG386 |
ade614d5 | 2042 | if (flag_debug) |
355afbcd KR |
2043 | { |
2044 | pi (line, &i); | |
2045 | } | |
fecd2382 | 2046 | #endif /* DEBUG386 */ |
355afbcd | 2047 | } |
fecd2382 RP |
2048 | } |
2049 | \f | |
2050 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
2051 | on error. */ | |
2052 | ||
355afbcd KR |
2053 | static int |
2054 | i386_operand (operand_string) | |
2055 | char *operand_string; | |
fecd2382 | 2056 | { |
355afbcd KR |
2057 | register char *op_string = operand_string; |
2058 | ||
2059 | /* Address of '\0' at end of operand_string. */ | |
2060 | char *end_of_operand_string = operand_string + strlen (operand_string); | |
2061 | ||
2062 | /* Start and end of displacement string expression (if found). */ | |
2063 | char *displacement_string_start = NULL; | |
2064 | char *displacement_string_end = NULL; | |
2065 | ||
2066 | /* We check for an absolute prefix (differentiating, | |
3c8df4ba | 2067 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
355afbcd KR |
2068 | if (*op_string == ABSOLUTE_PREFIX) |
2069 | { | |
2070 | op_string++; | |
2071 | i.types[this_operand] |= JumpAbsolute; | |
2072 | } | |
2073 | ||
2074 | /* Check if operand is a register. */ | |
2075 | if (*op_string == REGISTER_PREFIX) | |
2076 | { | |
2077 | register reg_entry *r; | |
2078 | if (!(r = parse_register (op_string))) | |
2079 | { | |
48401fcf | 2080 | as_bad (_("bad register name `%s'"), op_string); |
355afbcd | 2081 | return 0; |
fecd2382 | 2082 | } |
355afbcd | 2083 | /* Check for segment override, rather than segment register by |
3c8df4ba | 2084 | searching for ':' after %<x>s where <x> = s, c, d, e, f, g. */ |
355afbcd KR |
2085 | if ((r->reg_type & (SReg2 | SReg3)) && op_string[3] == ':') |
2086 | { | |
2087 | switch (r->reg_num) | |
2088 | { | |
2089 | case 0: | |
4498e3d6 | 2090 | i.seg[i.mem_operands] = (seg_entry *) & es; |
355afbcd KR |
2091 | break; |
2092 | case 1: | |
4498e3d6 | 2093 | i.seg[i.mem_operands] = (seg_entry *) & cs; |
355afbcd KR |
2094 | break; |
2095 | case 2: | |
4498e3d6 | 2096 | i.seg[i.mem_operands] = (seg_entry *) & ss; |
355afbcd KR |
2097 | break; |
2098 | case 3: | |
4498e3d6 | 2099 | i.seg[i.mem_operands] = (seg_entry *) & ds; |
355afbcd KR |
2100 | break; |
2101 | case 4: | |
4498e3d6 | 2102 | i.seg[i.mem_operands] = (seg_entry *) & fs; |
355afbcd KR |
2103 | break; |
2104 | case 5: | |
4498e3d6 | 2105 | i.seg[i.mem_operands] = (seg_entry *) & gs; |
355afbcd KR |
2106 | break; |
2107 | } | |
2108 | op_string += 4; /* skip % <x> s : */ | |
2109 | operand_string = op_string; /* Pretend given string starts here. */ | |
2110 | if (!is_digit_char (*op_string) && !is_identifier_char (*op_string) | |
2111 | && *op_string != '(' && *op_string != ABSOLUTE_PREFIX) | |
2112 | { | |
48401fcf | 2113 | as_bad (_("bad memory operand `%s'"), op_string); |
355afbcd KR |
2114 | return 0; |
2115 | } | |
2116 | /* Handle case of %es:*foo. */ | |
2117 | if (*op_string == ABSOLUTE_PREFIX) | |
2118 | { | |
2119 | op_string++; | |
2120 | i.types[this_operand] |= JumpAbsolute; | |
2121 | } | |
2122 | goto do_memory_reference; | |
2123 | } | |
ec1e6bb8 | 2124 | i.types[this_operand] |= r->reg_type & ~BaseIndex; |
355afbcd KR |
2125 | i.regs[this_operand] = r; |
2126 | i.reg_operands++; | |
2127 | } | |
2128 | else if (*op_string == IMMEDIATE_PREFIX) | |
2129 | { /* ... or an immediate */ | |
2130 | char *save_input_line_pointer; | |
49864cfa | 2131 | segT exp_seg = 0; |
355afbcd KR |
2132 | expressionS *exp; |
2133 | ||
2134 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2135 | { | |
48401fcf | 2136 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
355afbcd KR |
2137 | return 0; |
2138 | } | |
542e1629 | 2139 | |
355afbcd KR |
2140 | exp = &im_expressions[i.imm_operands++]; |
2141 | i.imms[this_operand] = exp; | |
2142 | save_input_line_pointer = input_line_pointer; | |
2143 | input_line_pointer = ++op_string; /* must advance op_string! */ | |
ad660eb1 | 2144 | SKIP_WHITESPACE (); |
355afbcd | 2145 | exp_seg = expression (exp); |
388fa5c6 | 2146 | if (*input_line_pointer != '\0') |
dddc8a82 ILT |
2147 | { |
2148 | /* This should be as_bad, but some versions of gcc, up to | |
2149 | about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx) | |
2150 | in certain cases. Oddly, the code in question turns out | |
2151 | to work correctly anyhow, so we make this just a warning | |
2152 | until those versions of gcc are obsolete. */ | |
48401fcf | 2153 | as_warn (_("unrecognized characters `%s' in expression"), |
dddc8a82 ILT |
2154 | input_line_pointer); |
2155 | } | |
355afbcd KR |
2156 | input_line_pointer = save_input_line_pointer; |
2157 | ||
7b23213f | 2158 | if (exp->X_op == O_absent) |
355afbcd | 2159 | { |
49864cfa | 2160 | /* missing or bad expr becomes absolute 0 */ |
48401fcf | 2161 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
355afbcd | 2162 | operand_string); |
5ac34ac3 | 2163 | exp->X_op = O_constant; |
355afbcd KR |
2164 | exp->X_add_number = 0; |
2165 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2166 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 2167 | i.types[this_operand] |= Imm; |
49864cfa | 2168 | } |
7b23213f | 2169 | else if (exp->X_op == O_constant) |
49864cfa | 2170 | { |
ad660eb1 ILT |
2171 | i.types[this_operand] |= |
2172 | smallest_imm_type ((unsigned long) exp->X_add_number); | |
49864cfa | 2173 | } |
7b23213f | 2174 | #ifdef OBJ_AOUT |
49864cfa KR |
2175 | else if (exp_seg != text_section |
2176 | && exp_seg != data_section | |
2177 | && exp_seg != bss_section | |
2178 | && exp_seg != undefined_section | |
2179 | #ifdef BFD_ASSEMBLER | |
2180 | && ! bfd_is_com_section (exp_seg) | |
2181 | #endif | |
2182 | ) | |
2183 | { | |
355afbcd | 2184 | seg_unimplemented: |
48401fcf | 2185 | as_bad (_("Unimplemented segment type %d in parse_operand"), exp_seg); |
355afbcd KR |
2186 | return 0; |
2187 | } | |
49864cfa KR |
2188 | #endif |
2189 | else | |
2190 | { | |
2191 | /* this is an address ==> 32bit */ | |
2192 | i.types[this_operand] |= Imm32; | |
2193 | } | |
355afbcd | 2194 | /* shorten this type of this operand if the instruction wants |
49864cfa KR |
2195 | * fewer bits than are present in the immediate. The bit field |
2196 | * code can put out 'andb $0xffffff, %al', for example. pace | |
2197 | * also 'movw $foo,(%eax)' | |
2198 | */ | |
355afbcd KR |
2199 | switch (i.suffix) |
2200 | { | |
2201 | case WORD_OPCODE_SUFFIX: | |
2202 | i.types[this_operand] |= Imm16; | |
2203 | break; | |
2204 | case BYTE_OPCODE_SUFFIX: | |
2205 | i.types[this_operand] |= Imm16 | Imm8 | Imm8S; | |
2206 | break; | |
2207 | } | |
2208 | } | |
2209 | else if (is_digit_char (*op_string) || is_identifier_char (*op_string) | |
2210 | || *op_string == '(') | |
2211 | { | |
2212 | /* This is a memory reference of some sort. */ | |
2213 | register char *base_string; | |
ec1e6bb8 | 2214 | int found_base_index_form; |
355afbcd KR |
2215 | |
2216 | do_memory_reference: | |
4498e3d6 ILT |
2217 | if ((i.mem_operands == 1 |
2218 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
2219 | || i.mem_operands == 2) | |
355afbcd | 2220 | { |
48401fcf | 2221 | as_bad (_("too many memory references for `%s'"), |
4498e3d6 | 2222 | current_templates->start->name); |
355afbcd KR |
2223 | return 0; |
2224 | } | |
355afbcd KR |
2225 | |
2226 | /* Determine type of memory operand from opcode_suffix; | |
227b6b55 | 2227 | no opcode suffix implies general memory references. */ |
355afbcd KR |
2228 | switch (i.suffix) |
2229 | { | |
2230 | case BYTE_OPCODE_SUFFIX: | |
2231 | i.types[this_operand] |= Mem8; | |
2232 | break; | |
2233 | case WORD_OPCODE_SUFFIX: | |
2234 | i.types[this_operand] |= Mem16; | |
2235 | break; | |
2236 | case DWORD_OPCODE_SUFFIX: | |
2237 | default: | |
2238 | i.types[this_operand] |= Mem32; | |
2239 | } | |
2240 | ||
49864cfa KR |
2241 | /* Check for base index form. We detect the base index form by |
2242 | looking for an ')' at the end of the operand, searching | |
2243 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
2244 | after it. */ | |
355afbcd KR |
2245 | base_string = end_of_operand_string - 1; |
2246 | found_base_index_form = 0; | |
2247 | if (*base_string == ')') | |
2248 | { | |
0b476c53 | 2249 | unsigned int parens_balanced = 1; |
49864cfa KR |
2250 | /* We've already checked that the number of left & right ()'s are |
2251 | equal, so this loop will not be infinite. */ | |
355afbcd KR |
2252 | do |
2253 | { | |
2254 | base_string--; | |
2255 | if (*base_string == ')') | |
0b476c53 | 2256 | parens_balanced++; |
355afbcd | 2257 | if (*base_string == '(') |
0b476c53 | 2258 | parens_balanced--; |
355afbcd | 2259 | } |
0b476c53 | 2260 | while (parens_balanced); |
355afbcd KR |
2261 | base_string++; /* Skip past '('. */ |
2262 | if (*base_string == REGISTER_PREFIX || *base_string == ',') | |
2263 | found_base_index_form = 1; | |
2264 | } | |
2265 | ||
2266 | /* If we can't parse a base index register expression, we've found | |
49864cfa KR |
2267 | a pure displacement expression. We set up displacement_string_start |
2268 | and displacement_string_end for the code below. */ | |
355afbcd KR |
2269 | if (!found_base_index_form) |
2270 | { | |
2271 | displacement_string_start = op_string; | |
2272 | displacement_string_end = end_of_operand_string; | |
2273 | } | |
2274 | else | |
2275 | { | |
2276 | char *base_reg_name, *index_reg_name, *num_string; | |
2277 | int num; | |
2278 | ||
2279 | i.types[this_operand] |= BaseIndex; | |
2280 | ||
2281 | /* If there is a displacement set-up for it to be parsed later. */ | |
2282 | if (base_string != op_string + 1) | |
2283 | { | |
2284 | displacement_string_start = op_string; | |
2285 | displacement_string_end = base_string - 1; | |
2286 | } | |
2287 | ||
2288 | /* Find base register (if any). */ | |
2289 | if (*base_string != ',') | |
2290 | { | |
2291 | base_reg_name = base_string++; | |
2292 | /* skip past register name & parse it */ | |
2293 | while (isalpha (*base_string)) | |
2294 | base_string++; | |
2295 | if (base_string == base_reg_name + 1) | |
2296 | { | |
48401fcf | 2297 | as_bad (_("can't find base register name after `(%c'"), |
355afbcd KR |
2298 | REGISTER_PREFIX); |
2299 | return 0; | |
2300 | } | |
2301 | END_STRING_AND_SAVE (base_string); | |
2302 | if (!(i.base_reg = parse_register (base_reg_name))) | |
2303 | { | |
48401fcf | 2304 | as_bad (_("bad base register name `%s'"), base_reg_name); |
4498e3d6 | 2305 | RESTORE_END_STRING (base_string); |
355afbcd KR |
2306 | return 0; |
2307 | } | |
2308 | RESTORE_END_STRING (base_string); | |
2309 | } | |
2310 | ||
2311 | /* Now check seperator; must be ',' ==> index reg | |
a39116f1 RP |
2312 | OR num ==> no index reg. just scale factor |
2313 | OR ')' ==> end. (scale factor = 1) */ | |
355afbcd KR |
2314 | if (*base_string != ',' && *base_string != ')') |
2315 | { | |
48401fcf | 2316 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
355afbcd KR |
2317 | operand_string); |
2318 | return 0; | |
2319 | } | |
2320 | ||
2321 | /* There may index reg here; and there may be a scale factor. */ | |
2322 | if (*base_string == ',' && *(base_string + 1) == REGISTER_PREFIX) | |
2323 | { | |
2324 | index_reg_name = ++base_string; | |
2325 | while (isalpha (*++base_string)); | |
2326 | END_STRING_AND_SAVE (base_string); | |
2327 | if (!(i.index_reg = parse_register (index_reg_name))) | |
2328 | { | |
48401fcf | 2329 | as_bad (_("bad index register name `%s'"), index_reg_name); |
4498e3d6 | 2330 | RESTORE_END_STRING (base_string); |
355afbcd | 2331 | return 0; |
a39116f1 | 2332 | } |
355afbcd KR |
2333 | RESTORE_END_STRING (base_string); |
2334 | } | |
2335 | ||
2336 | /* Check for scale factor. */ | |
2337 | if (*base_string == ',' && isdigit (*(base_string + 1))) | |
2338 | { | |
2339 | num_string = ++base_string; | |
2340 | while (is_digit_char (*base_string)) | |
2341 | base_string++; | |
2342 | if (base_string == num_string) | |
2343 | { | |
48401fcf | 2344 | as_bad (_("can't find a scale factor after `,'")); |
355afbcd | 2345 | return 0; |
a39116f1 | 2346 | } |
355afbcd KR |
2347 | END_STRING_AND_SAVE (base_string); |
2348 | /* We've got a scale factor. */ | |
2349 | if (!sscanf (num_string, "%d", &num)) | |
2350 | { | |
48401fcf | 2351 | as_bad (_("can't parse scale factor from `%s'"), num_string); |
4498e3d6 | 2352 | RESTORE_END_STRING (base_string); |
355afbcd | 2353 | return 0; |
a39116f1 | 2354 | } |
355afbcd KR |
2355 | RESTORE_END_STRING (base_string); |
2356 | switch (num) | |
2357 | { /* must be 1 digit scale */ | |
2358 | case 1: | |
2359 | i.log2_scale_factor = 0; | |
2360 | break; | |
2361 | case 2: | |
2362 | i.log2_scale_factor = 1; | |
2363 | break; | |
2364 | case 4: | |
2365 | i.log2_scale_factor = 2; | |
2366 | break; | |
2367 | case 8: | |
2368 | i.log2_scale_factor = 3; | |
2369 | break; | |
2370 | default: | |
48401fcf | 2371 | as_bad (_("expecting scale factor of 1, 2, 4, 8; got %d"), num); |
355afbcd | 2372 | return 0; |
a39116f1 | 2373 | } |
ec1e6bb8 ILT |
2374 | if (num != 1 && ! i.index_reg) |
2375 | { | |
2376 | as_warn (_("scale factor of %d without an index register"), | |
2377 | num); | |
2378 | #if SCALE1_WHEN_NO_INDEX | |
2379 | i.log2_scale_factor = 0; | |
2380 | #endif | |
2381 | } | |
355afbcd KR |
2382 | } |
2383 | else | |
2384 | { | |
2385 | if (!i.index_reg && *base_string == ',') | |
2386 | { | |
48401fcf | 2387 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
355afbcd KR |
2388 | *(base_string + 1)); |
2389 | return 0; | |
a39116f1 | 2390 | } |
355afbcd KR |
2391 | } |
2392 | } | |
2393 | ||
2394 | /* If there's an expression begining the operand, parse it, | |
49864cfa KR |
2395 | assuming displacement_string_start and displacement_string_end |
2396 | are meaningful. */ | |
355afbcd KR |
2397 | if (displacement_string_start) |
2398 | { | |
2399 | register expressionS *exp; | |
49864cfa | 2400 | segT exp_seg = 0; |
355afbcd | 2401 | char *save_input_line_pointer; |
aa56747a | 2402 | |
355afbcd KR |
2403 | exp = &disp_expressions[i.disp_operands]; |
2404 | i.disps[this_operand] = exp; | |
f0b37b4a | 2405 | i.disp_reloc[this_operand] = NO_RELOC; |
355afbcd KR |
2406 | i.disp_operands++; |
2407 | save_input_line_pointer = input_line_pointer; | |
2408 | input_line_pointer = displacement_string_start; | |
2409 | END_STRING_AND_SAVE (displacement_string_end); | |
a52f90a4 | 2410 | |
30355216 | 2411 | #ifndef LEX_AT |
f0b37b4a KR |
2412 | { |
2413 | /* | |
2414 | * We can have operands of the form | |
2415 | * <symbol>@GOTOFF+<nnn> | |
2416 | * Take the easy way out here and copy everything | |
2417 | * into a temporary buffer... | |
2418 | */ | |
2419 | register char *cp; | |
a52f90a4 ILT |
2420 | |
2421 | cp = strchr (input_line_pointer, '@'); | |
2422 | if (cp != NULL) | |
2423 | { | |
2424 | char *tmpbuf; | |
2425 | ||
2426 | if (GOT_symbol == NULL) | |
2427 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2428 | ||
2429 | tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20); | |
2430 | ||
2431 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2432 | { | |
2433 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2434 | *cp = '\0'; | |
2435 | strcpy (tmpbuf, input_line_pointer); | |
2436 | strcat (tmpbuf, cp + 1 + 3); | |
2437 | *cp = '@'; | |
2438 | } | |
2439 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2440 | { | |
2441 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2442 | *cp = '\0'; | |
2443 | strcpy (tmpbuf, input_line_pointer); | |
2444 | strcat (tmpbuf, cp + 1 + 6); | |
2445 | *cp = '@'; | |
2446 | } | |
2447 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2448 | { | |
2449 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2450 | *cp = '\0'; | |
2451 | strcpy (tmpbuf, input_line_pointer); | |
2452 | strcat (tmpbuf, cp + 1 + 3); | |
2453 | *cp = '@'; | |
2454 | } | |
2455 | else | |
48401fcf | 2456 | as_bad (_("Bad reloc specifier `%s' in expression"), cp + 1); |
a52f90a4 ILT |
2457 | |
2458 | input_line_pointer = tmpbuf; | |
2459 | } | |
f0b37b4a | 2460 | } |
30355216 | 2461 | #endif |
a52f90a4 | 2462 | |
355afbcd | 2463 | exp_seg = expression (exp); |
f0b37b4a KR |
2464 | |
2465 | #ifdef BFD_ASSEMBLER | |
2466 | /* We do this to make sure that the section symbol is in | |
2467 | the symbol table. We will ultimately change the relocation | |
2468 | to be relative to the beginning of the section */ | |
c54c7aac KR |
2469 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2470 | { | |
2471 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2472 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2473 | section_symbol(exp->X_add_symbol->bsym->section); | |
2474 | assert (exp->X_op == O_symbol); | |
2475 | exp->X_op = O_subtract; | |
2476 | exp->X_op_symbol = GOT_symbol; | |
2477 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2478 | } | |
f0b37b4a KR |
2479 | #endif |
2480 | ||
355afbcd | 2481 | if (*input_line_pointer) |
48401fcf TT |
2482 | as_bad (_("Ignoring junk `%s' after expression"), |
2483 | input_line_pointer); | |
355afbcd KR |
2484 | RESTORE_END_STRING (displacement_string_end); |
2485 | input_line_pointer = save_input_line_pointer; | |
aa56747a | 2486 | #if 0 /* this is handled in expr */ |
7b23213f | 2487 | if (exp->X_op == O_absent) |
355afbcd | 2488 | { |
355afbcd | 2489 | /* missing expr becomes absolute 0 */ |
48401fcf | 2490 | as_bad (_("missing or invalid displacement `%s' taken as 0"), |
355afbcd KR |
2491 | operand_string); |
2492 | i.types[this_operand] |= (Disp | Abs); | |
5ac34ac3 | 2493 | exp->X_op = O_constant; |
355afbcd KR |
2494 | exp->X_add_number = 0; |
2495 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2496 | exp->X_op_symbol = (symbolS *) 0; |
49864cfa | 2497 | } |
aa56747a ILT |
2498 | else |
2499 | #endif | |
2500 | if (exp->X_op == O_constant) | |
49864cfa | 2501 | { |
355afbcd | 2502 | i.types[this_operand] |= SMALLEST_DISP_TYPE (exp->X_add_number); |
49864cfa KR |
2503 | } |
2504 | else if (exp_seg == text_section | |
2505 | || exp_seg == data_section | |
2506 | || exp_seg == bss_section | |
2507 | || exp_seg == undefined_section) | |
2508 | { | |
355afbcd | 2509 | i.types[this_operand] |= Disp32; |
49864cfa KR |
2510 | } |
2511 | else | |
2512 | { | |
7b23213f | 2513 | #ifndef OBJ_AOUT |
49864cfa KR |
2514 | i.types[this_operand] |= Disp32; |
2515 | #else | |
355afbcd | 2516 | goto seg_unimplemented; |
49864cfa | 2517 | #endif |
355afbcd KR |
2518 | } |
2519 | } | |
2520 | ||
ec1e6bb8 ILT |
2521 | /* Special case for (%dx) while doing input/output op. */ |
2522 | if (i.base_reg && | |
2523 | i.base_reg->reg_type == (Reg16 | InOutPortReg) && | |
2524 | i.index_reg == 0 && | |
2525 | i.log2_scale_factor == 0 && | |
2526 | i.seg[i.mem_operands] == 0) | |
355afbcd | 2527 | { |
ec1e6bb8 | 2528 | i.types[this_operand] = InOutPortReg; |
49864cfa KR |
2529 | return 1; |
2530 | } | |
ec1e6bb8 ILT |
2531 | /* Make sure the memory operand we've been dealt is valid. */ |
2532 | if ((i.base_reg && (i.base_reg->reg_type & BaseIndex) == 0) | |
2533 | || (i.index_reg && ((i.index_reg->reg_type & BaseIndex) == 0 | |
2534 | || i.index_reg->reg_num == ESP_REG_NUM)) | |
2535 | || (i.base_reg && i.index_reg | |
2536 | && (i.base_reg->reg_type & i.index_reg->reg_type & Reg) == 0)) | |
355afbcd | 2537 | { |
ec1e6bb8 ILT |
2538 | as_bad (_("`%s' is not a valid base/index expression"), |
2539 | operand_string); | |
355afbcd | 2540 | return 0; |
fecd2382 | 2541 | } |
ec1e6bb8 | 2542 | i.mem_operands++; |
355afbcd KR |
2543 | } |
2544 | else | |
2545 | { /* it's not a memory operand; argh! */ | |
8081c2be | 2546 | as_bad (_("invalid char %s begining operand %d `%s'"), |
aa56747a ILT |
2547 | output_invalid (*op_string), |
2548 | this_operand + 1, | |
355afbcd KR |
2549 | op_string); |
2550 | return 0; | |
2551 | } | |
2552 | return 1; /* normal return */ | |
fecd2382 RP |
2553 | } |
2554 | \f | |
2555 | /* | |
2556 | * md_estimate_size_before_relax() | |
2557 | * | |
2558 | * Called just before relax(). | |
2559 | * Any symbol that is now undefined will not become defined. | |
2560 | * Return the correct fr_subtype in the frag. | |
2561 | * Return the initial "guess for fr_var" to caller. | |
2562 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
2563 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
2564 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
2565 | * 0 value. | |
2566 | */ | |
2567 | int | |
355afbcd KR |
2568 | md_estimate_size_before_relax (fragP, segment) |
2569 | register fragS *fragP; | |
2570 | register segT segment; | |
fecd2382 | 2571 | { |
355afbcd KR |
2572 | register unsigned char *opcode; |
2573 | register int old_fr_fix; | |
2574 | ||
2575 | old_fr_fix = fragP->fr_fix; | |
2576 | opcode = (unsigned char *) fragP->fr_opcode; | |
2577 | /* We've already got fragP->fr_subtype right; all we have to do is check | |
a39116f1 | 2578 | for un-relaxable symbols. */ |
355afbcd KR |
2579 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
2580 | { | |
2581 | /* symbol is undefined in this segment */ | |
2582 | switch (opcode[0]) | |
2583 | { | |
2584 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
2585 | opcode[0] = 0xe9; /* dword disp jmp */ | |
2586 | fragP->fr_fix += 4; | |
2587 | fix_new (fragP, old_fr_fix, 4, | |
f0b37b4a KR |
2588 | fragP->fr_symbol, |
2589 | fragP->fr_offset, 1, | |
2590 | (GOT_symbol && /* Not quite right - we should switch on | |
2591 | presence of @PLT, but I cannot see how | |
2592 | to get to that from here. We should have | |
2593 | done this in md_assemble to really | |
2594 | get it right all of the time, but I | |
2595 | think it does not matter that much, as | |
2596 | this will be right most of the time. ERY*/ | |
2597 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)? | |
2598 | BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL); | |
355afbcd KR |
2599 | break; |
2600 | ||
2601 | default: | |
2602 | /* This changes the byte-displacement jump 0x7N --> | |
a39116f1 | 2603 | the dword-displacement jump 0x0f8N */ |
355afbcd KR |
2604 | opcode[1] = opcode[0] + 0x10; |
2605 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */ | |
2606 | fragP->fr_fix += 1 + 4; /* we've added an opcode byte */ | |
2607 | fix_new (fragP, old_fr_fix + 1, 4, | |
2608 | fragP->fr_symbol, | |
f0b37b4a KR |
2609 | fragP->fr_offset, 1, |
2610 | (GOT_symbol && /* Not quite right - we should switch on | |
2611 | presence of @PLT, but I cannot see how | |
2612 | to get to that from here. ERY */ | |
2613 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)? | |
2614 | BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL); | |
355afbcd | 2615 | break; |
a39116f1 | 2616 | } |
355afbcd KR |
2617 | frag_wane (fragP); |
2618 | } | |
2619 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
fecd2382 RP |
2620 | } /* md_estimate_size_before_relax() */ |
2621 | \f | |
2622 | /* | |
2623 | * md_convert_frag(); | |
2624 | * | |
2625 | * Called after relax() is finished. | |
2626 | * In: Address of frag. | |
2627 | * fr_type == rs_machine_dependent. | |
2628 | * fr_subtype is what the address relaxed to. | |
2629 | * | |
2630 | * Out: Any fixSs and constants are set up. | |
2631 | * Caller will turn frag into a ".space 0". | |
2632 | */ | |
49864cfa | 2633 | #ifndef BFD_ASSEMBLER |
fecd2382 | 2634 | void |
3ea36b53 | 2635 | md_convert_frag (headers, sec, fragP) |
355afbcd | 2636 | object_headers *headers; |
3ea36b53 | 2637 | segT sec; |
355afbcd | 2638 | register fragS *fragP; |
49864cfa KR |
2639 | #else |
2640 | void | |
2641 | md_convert_frag (abfd, sec, fragP) | |
2642 | bfd *abfd; | |
2643 | segT sec; | |
2644 | register fragS *fragP; | |
2645 | #endif | |
fecd2382 | 2646 | { |
355afbcd KR |
2647 | register unsigned char *opcode; |
2648 | unsigned char *where_to_put_displacement = NULL; | |
2649 | unsigned int target_address; | |
2650 | unsigned int opcode_address; | |
2651 | unsigned int extension = 0; | |
2652 | int displacement_from_opcode_start; | |
2653 | ||
2654 | opcode = (unsigned char *) fragP->fr_opcode; | |
2655 | ||
2656 | /* Address we want to reach in file space. */ | |
2657 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
7b23213f KR |
2658 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ |
2659 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
2660 | #endif | |
355afbcd KR |
2661 | |
2662 | /* Address opcode resides at in file space. */ | |
2663 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
2664 | ||
2665 | /* Displacement from opcode start to fill into instruction. */ | |
2666 | displacement_from_opcode_start = target_address - opcode_address; | |
2667 | ||
2668 | switch (fragP->fr_subtype) | |
2669 | { | |
2670 | case ENCODE_RELAX_STATE (COND_JUMP, BYTE): | |
a39116f1 | 2671 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE): |
355afbcd KR |
2672 | /* don't have to change opcode */ |
2673 | extension = 1; /* 1 opcode + 1 displacement */ | |
2674 | where_to_put_displacement = &opcode[1]; | |
2675 | break; | |
2676 | ||
2677 | case ENCODE_RELAX_STATE (COND_JUMP, WORD): | |
2678 | opcode[1] = TWO_BYTE_OPCODE_ESCAPE; | |
2679 | opcode[2] = opcode[0] + 0x10; | |
2680 | opcode[0] = WORD_PREFIX_OPCODE; | |
2681 | extension = 4; /* 3 opcode + 2 displacement */ | |
2682 | where_to_put_displacement = &opcode[3]; | |
2683 | break; | |
2684 | ||
2685 | case ENCODE_RELAX_STATE (UNCOND_JUMP, WORD): | |
2686 | opcode[1] = 0xe9; | |
2687 | opcode[0] = WORD_PREFIX_OPCODE; | |
2688 | extension = 3; /* 2 opcode + 2 displacement */ | |
2689 | where_to_put_displacement = &opcode[2]; | |
2690 | break; | |
2691 | ||
2692 | case ENCODE_RELAX_STATE (COND_JUMP, DWORD): | |
2693 | opcode[1] = opcode[0] + 0x10; | |
2694 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
2695 | extension = 5; /* 2 opcode + 4 displacement */ | |
2696 | where_to_put_displacement = &opcode[2]; | |
2697 | break; | |
2698 | ||
2699 | case ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD): | |
2700 | opcode[0] = 0xe9; | |
2701 | extension = 4; /* 1 opcode + 4 displacement */ | |
2702 | where_to_put_displacement = &opcode[1]; | |
2703 | break; | |
2704 | ||
2705 | default: | |
2706 | BAD_CASE (fragP->fr_subtype); | |
2707 | break; | |
2708 | } | |
2709 | /* now put displacement after opcode */ | |
2710 | md_number_to_chars ((char *) where_to_put_displacement, | |
ad660eb1 | 2711 | (valueT) (displacement_from_opcode_start - extension), |
355afbcd KR |
2712 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
2713 | fragP->fr_fix += extension; | |
fecd2382 | 2714 | } |
fecd2382 | 2715 | \f |
355afbcd | 2716 | |
fecd2382 | 2717 | int md_short_jump_size = 2; /* size of byte displacement jmp */ |
355afbcd | 2718 | int md_long_jump_size = 5; /* size of dword displacement jmp */ |
49864cfa | 2719 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 2720 | |
355afbcd KR |
2721 | void |
2722 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
2723 | char *ptr; | |
025b0302 | 2724 | addressT from_addr, to_addr; |
355afbcd KR |
2725 | fragS *frag; |
2726 | symbolS *to_symbol; | |
fecd2382 | 2727 | { |
355afbcd KR |
2728 | long offset; |
2729 | ||
2730 | offset = to_addr - (from_addr + 2); | |
ad660eb1 ILT |
2731 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ |
2732 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
fecd2382 RP |
2733 | } |
2734 | ||
355afbcd KR |
2735 | void |
2736 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
2737 | char *ptr; | |
025b0302 | 2738 | addressT from_addr, to_addr; |
355afbcd KR |
2739 | fragS *frag; |
2740 | symbolS *to_symbol; | |
fecd2382 | 2741 | { |
355afbcd KR |
2742 | long offset; |
2743 | ||
ade614d5 | 2744 | if (flag_do_long_jump) |
355afbcd KR |
2745 | { |
2746 | offset = to_addr - S_GET_VALUE (to_symbol); | |
ad660eb1 ILT |
2747 | md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ |
2748 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 2749 | fix_new (frag, (ptr + 1) - frag->fr_literal, 4, |
7b23213f | 2750 | to_symbol, (offsetT) 0, 0, BFD_RELOC_32); |
355afbcd KR |
2751 | } |
2752 | else | |
2753 | { | |
2754 | offset = to_addr - (from_addr + 5); | |
ad660eb1 ILT |
2755 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
2756 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 2757 | } |
fecd2382 RP |
2758 | } |
2759 | \f | |
fecd2382 | 2760 | /* Apply a fixup (fixS) to segment data, once it has been determined |
355afbcd KR |
2761 | by our caller that we have all the info we need to fix it up. |
2762 | ||
fecd2382 RP |
2763 | On the 386, immediates, displacements, and data pointers are all in |
2764 | the same (little-endian) format, so we don't need to care about which | |
2765 | we are handling. */ | |
2766 | ||
3ea36b53 ILT |
2767 | int |
2768 | md_apply_fix3 (fixP, valp, seg) | |
2769 | fixS *fixP; /* The fix we're to put in. */ | |
2770 | valueT *valp; /* Pointer to the value of the bits. */ | |
2771 | segT seg; /* Segment fix is from. */ | |
fecd2382 | 2772 | { |
355afbcd | 2773 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
3ea36b53 | 2774 | valueT value = *valp; |
355afbcd | 2775 | |
388fa5c6 ILT |
2776 | if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel) |
2777 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
2778 | ||
f3d817d8 | 2779 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
7b23213f KR |
2780 | /* |
2781 | * This is a hack. There should be a better way to | |
2782 | * handle this. | |
2783 | */ | |
2784 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy) | |
2785 | { | |
0b476c53 | 2786 | #ifndef OBJ_AOUT |
76fb6d2f ILT |
2787 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
2788 | || OUTPUT_FLAVOR == bfd_target_coff_flavour) | |
590c50d8 | 2789 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
0b476c53 | 2790 | #endif |
590c50d8 ILT |
2791 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2792 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
2793 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg | |
ec1e6bb8 ILT |
2794 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) |
2795 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
2796 | && ! S_IS_WEAK (fixP->fx_addsy) | |
2797 | && S_IS_DEFINED (fixP->fx_addsy) | |
2798 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
f3d817d8 DM |
2799 | { |
2800 | /* Yes, we add the values in twice. This is because | |
2801 | bfd_perform_relocation subtracts them out again. I think | |
2802 | bfd_perform_relocation is broken, but I don't dare change | |
2803 | it. FIXME. */ | |
2804 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
2805 | } | |
76fb6d2f ILT |
2806 | #endif |
2807 | #if defined (OBJ_COFF) && defined (TE_PE) | |
2808 | /* For some reason, the PE format does not store a section | |
2809 | address offset for a PC relative symbol. */ | |
2810 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
2811 | value += md_pcrel_from (fixP); | |
7b23213f | 2812 | #endif |
355afbcd | 2813 | } |
f0b37b4a KR |
2814 | |
2815 | /* Fix a few things - the dynamic linker expects certain values here, | |
2816 | and we must not dissappoint it. */ | |
590c50d8 ILT |
2817 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2818 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
2819 | && fixP->fx_addsy) | |
f0b37b4a KR |
2820 | switch(fixP->fx_r_type) { |
2821 | case BFD_RELOC_386_PLT32: | |
2822 | /* Make the jump instruction point to the address of the operand. At | |
2823 | runtime we merely add the offset to the actual PLT entry. */ | |
2824 | value = 0xfffffffc; | |
2825 | break; | |
2826 | case BFD_RELOC_386_GOTPC: | |
2827 | /* | |
2828 | * This is tough to explain. We end up with this one if we have | |
2829 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal | |
2830 | * here is to obtain the absolute address of the GOT, and it is strongly | |
2831 | * preferable from a performance point of view to avoid using a runtime | |
2832 | * relocation for this. The actual sequence of instructions often look | |
2833 | * something like: | |
2834 | * | |
2835 | * call .L66 | |
2836 | * .L66: | |
2837 | * popl %ebx | |
2838 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
2839 | * | |
2840 | * The call and pop essentially return the absolute address of | |
2841 | * the label .L66 and store it in %ebx. The linker itself will | |
2842 | * ultimately change the first operand of the addl so that %ebx points to | |
2843 | * the GOT, but to keep things simple, the .o file must have this operand | |
2844 | * set so that it generates not the absolute address of .L66, but the | |
2845 | * absolute address of itself. This allows the linker itself simply | |
2846 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
2847 | * added in, and the addend of the relocation is stored in the operand | |
2848 | * field for the instruction itself. | |
2849 | * | |
2850 | * Our job here is to fix the operand so that it would add the correct | |
2851 | * offset so that %ebx would point to itself. The thing that is tricky is | |
2852 | * that .-.L66 will point to the beginning of the instruction, so we need | |
2853 | * to further modify the operand so that it will point to itself. | |
2854 | * There are other cases where you have something like: | |
2855 | * | |
2856 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
2857 | * | |
2858 | * and here no correction would be required. Internally in the assembler | |
2859 | * we treat operands of this form as not being pcrel since the '.' is | |
2860 | * explicitly mentioned, and I wonder whether it would simplify matters | |
2861 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
2862 | * the pcrel_adjust field was used to store the correction, but since the | |
2863 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
2864 | */ | |
c54c7aac | 2865 | value -= 1; |
f0b37b4a KR |
2866 | break; |
2867 | case BFD_RELOC_386_GOT32: | |
2868 | value = 0; /* Fully resolved at runtime. No addend. */ | |
c54c7aac | 2869 | break; |
f0b37b4a | 2870 | case BFD_RELOC_386_GOTOFF: |
c54c7aac KR |
2871 | break; |
2872 | ||
f0b37b4a KR |
2873 | default: |
2874 | break; | |
2875 | } | |
2876 | #endif | |
2877 | ||
f3d817d8 DM |
2878 | #endif |
2879 | md_number_to_chars (p, value, fixP->fx_size); | |
fecd2382 | 2880 | |
49864cfa KR |
2881 | return 1; |
2882 | } | |
49864cfa | 2883 | |
ad660eb1 ILT |
2884 | #if 0 |
2885 | /* This is never used. */ | |
355afbcd KR |
2886 | long /* Knows about the byte order in a word. */ |
2887 | md_chars_to_number (con, nbytes) | |
2888 | unsigned char con[]; /* Low order byte 1st. */ | |
2889 | int nbytes; /* Number of bytes in the input. */ | |
fecd2382 | 2890 | { |
355afbcd KR |
2891 | long retval; |
2892 | for (retval = 0, con += nbytes - 1; nbytes--; con--) | |
2893 | { | |
2894 | retval <<= BITS_PER_CHAR; | |
2895 | retval |= *con; | |
2896 | } | |
2897 | return retval; | |
fecd2382 | 2898 | } |
ad660eb1 | 2899 | #endif /* 0 */ |
fecd2382 | 2900 | \f |
355afbcd | 2901 | |
fecd2382 RP |
2902 | #define MAX_LITTLENUMS 6 |
2903 | ||
2904 | /* Turn the string pointed to by litP into a floating point constant of type | |
2905 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
3c8df4ba | 2906 | is stored in *sizeP . An error message is returned, or NULL on OK. */ |
fecd2382 | 2907 | char * |
355afbcd KR |
2908 | md_atof (type, litP, sizeP) |
2909 | char type; | |
2910 | char *litP; | |
2911 | int *sizeP; | |
fecd2382 | 2912 | { |
355afbcd KR |
2913 | int prec; |
2914 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2915 | LITTLENUM_TYPE *wordP; | |
2916 | char *t; | |
2917 | ||
2918 | switch (type) | |
2919 | { | |
2920 | case 'f': | |
2921 | case 'F': | |
2922 | prec = 2; | |
2923 | break; | |
2924 | ||
2925 | case 'd': | |
2926 | case 'D': | |
2927 | prec = 4; | |
2928 | break; | |
2929 | ||
2930 | case 'x': | |
2931 | case 'X': | |
2932 | prec = 5; | |
2933 | break; | |
2934 | ||
2935 | default: | |
2936 | *sizeP = 0; | |
48401fcf | 2937 | return _("Bad call to md_atof ()"); |
355afbcd KR |
2938 | } |
2939 | t = atof_ieee (input_line_pointer, type, words); | |
2940 | if (t) | |
2941 | input_line_pointer = t; | |
2942 | ||
2943 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3c8df4ba KR |
2944 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
2945 | the bigendian 386. */ | |
355afbcd KR |
2946 | for (wordP = words + prec - 1; prec--;) |
2947 | { | |
ad660eb1 | 2948 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
355afbcd KR |
2949 | litP += sizeof (LITTLENUM_TYPE); |
2950 | } | |
49864cfa | 2951 | return 0; |
fecd2382 RP |
2952 | } |
2953 | \f | |
2954 | char output_invalid_buf[8]; | |
2955 | ||
355afbcd KR |
2956 | static char * |
2957 | output_invalid (c) | |
2958 | char c; | |
fecd2382 | 2959 | { |
355afbcd KR |
2960 | if (isprint (c)) |
2961 | sprintf (output_invalid_buf, "'%c'", c); | |
2962 | else | |
2963 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
2964 | return output_invalid_buf; | |
fecd2382 RP |
2965 | } |
2966 | ||
7b23213f | 2967 | /* reg_string starts *before* REGISTER_PREFIX */ |
355afbcd KR |
2968 | static reg_entry * |
2969 | parse_register (reg_string) | |
3c8df4ba | 2970 | char *reg_string; |
fecd2382 | 2971 | { |
355afbcd KR |
2972 | register char *s = reg_string; |
2973 | register char *p; | |
2974 | char reg_name_given[MAX_REG_NAME_SIZE]; | |
2975 | ||
2976 | s++; /* skip REGISTER_PREFIX */ | |
2977 | for (p = reg_name_given; is_register_char (*s); p++, s++) | |
2978 | { | |
58d4951d | 2979 | *p = register_chars[(unsigned char) *s]; |
355afbcd KR |
2980 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
2981 | return (reg_entry *) 0; | |
2982 | } | |
2983 | *p = '\0'; | |
2984 | return (reg_entry *) hash_find (reg_hash, reg_name_given); | |
fecd2382 | 2985 | } |
f3d817d8 | 2986 | \f |
ade614d5 | 2987 | #ifdef OBJ_ELF |
3ea36b53 | 2988 | CONST char *md_shortopts = "kmVQ:"; |
ade614d5 KR |
2989 | #else |
2990 | CONST char *md_shortopts = "m"; | |
2991 | #endif | |
f3d817d8 DM |
2992 | struct option md_longopts[] = { |
2993 | {NULL, no_argument, NULL, 0} | |
2994 | }; | |
2995 | size_t md_longopts_size = sizeof(md_longopts); | |
fecd2382 | 2996 | |
f3d817d8 DM |
2997 | int |
2998 | md_parse_option (c, arg) | |
2999 | int c; | |
3000 | char *arg; | |
3001 | { | |
ade614d5 KR |
3002 | switch (c) |
3003 | { | |
3004 | case 'm': | |
3005 | flag_do_long_jump = 1; | |
3006 | break; | |
3007 | ||
590c50d8 | 3008 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3ea36b53 ILT |
3009 | /* -k: Ignore for FreeBSD compatibility. */ |
3010 | case 'k': | |
3011 | break; | |
3012 | ||
ade614d5 KR |
3013 | /* -V: SVR4 argument to print version ID. */ |
3014 | case 'V': | |
3015 | print_version_id (); | |
3016 | break; | |
3017 | ||
3018 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
3019 | should be emitted or not. FIXME: Not implemented. */ | |
3020 | case 'Q': | |
3021 | break; | |
3022 | #endif | |
3023 | ||
3024 | default: | |
3025 | return 0; | |
3026 | } | |
3027 | return 1; | |
f3d817d8 | 3028 | } |
fecd2382 | 3029 | |
f3d817d8 DM |
3030 | void |
3031 | md_show_usage (stream) | |
3032 | FILE *stream; | |
3033 | { | |
48401fcf TT |
3034 | fprintf (stream, _("\ |
3035 | -m do long jump\n")); | |
f3d817d8 | 3036 | } |
fecd2382 | 3037 | |
590c50d8 ILT |
3038 | #ifdef BFD_ASSEMBLER |
3039 | #ifdef OBJ_MAYBE_ELF | |
3040 | #ifdef OBJ_MAYBE_COFF | |
3041 | ||
3042 | /* Pick the target format to use. */ | |
3043 | ||
3044 | const char * | |
3045 | i386_target_format () | |
3046 | { | |
3047 | switch (OUTPUT_FLAVOR) | |
3048 | { | |
3049 | case bfd_target_coff_flavour: | |
3050 | return "coff-i386"; | |
3051 | case bfd_target_elf_flavour: | |
3052 | return "elf32-i386"; | |
3053 | default: | |
3054 | abort (); | |
3055 | return NULL; | |
3056 | } | |
3057 | } | |
3058 | ||
3059 | #endif /* OBJ_MAYBE_COFF */ | |
3060 | #endif /* OBJ_MAYBE_ELF */ | |
3061 | #endif /* BFD_ASSEMBLER */ | |
3062 | \f | |
fecd2382 RP |
3063 | /* ARGSUSED */ |
3064 | symbolS * | |
355afbcd KR |
3065 | md_undefined_symbol (name) |
3066 | char *name; | |
fecd2382 | 3067 | { |
f0b37b4a KR |
3068 | if (*name == '_' && *(name+1) == 'G' |
3069 | && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
3070 | { | |
3071 | if(!GOT_symbol) | |
3072 | { | |
3073 | if(symbol_find(name)) | |
aa56747a | 3074 | as_bad (_("GOT already in symbol table")); |
f0b37b4a KR |
3075 | GOT_symbol = symbol_new (name, undefined_section, |
3076 | (valueT) 0, &zero_address_frag); | |
3077 | }; | |
3078 | return GOT_symbol; | |
3079 | } | |
355afbcd | 3080 | return 0; |
fecd2382 RP |
3081 | } |
3082 | ||
fecd2382 | 3083 | /* Round up a section size to the appropriate boundary. */ |
3c8df4ba | 3084 | valueT |
355afbcd KR |
3085 | md_section_align (segment, size) |
3086 | segT segment; | |
3c8df4ba | 3087 | valueT size; |
fecd2382 | 3088 | { |
91951af6 ILT |
3089 | #ifdef OBJ_AOUT |
3090 | #ifdef BFD_ASSEMBLER | |
3091 | /* For a.out, force the section size to be aligned. If we don't do | |
3092 | this, BFD will align it for us, but it will not write out the | |
3093 | final bytes of the section. This may be a bug in BFD, but it is | |
3094 | easier to fix it here since that is how the other a.out targets | |
3095 | work. */ | |
3096 | int align; | |
3097 | ||
3098 | align = bfd_get_section_alignment (stdoutput, segment); | |
3099 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
3100 | #endif | |
3101 | #endif | |
3102 | ||
3103 | return size; | |
fecd2382 RP |
3104 | } |
3105 | ||
7b23213f KR |
3106 | /* Exactly what point is a PC-relative offset relative TO? On the |
3107 | i386, they're relative to the address of the offset, plus its | |
3108 | size. (??? Is this right? FIXME-SOON!) */ | |
fecd2382 | 3109 | long |
355afbcd KR |
3110 | md_pcrel_from (fixP) |
3111 | fixS *fixP; | |
fecd2382 | 3112 | { |
355afbcd | 3113 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
3114 | } |
3115 | ||
49864cfa | 3116 | #ifndef I386COFF |
542e1629 | 3117 | |
49864cfa | 3118 | static void |
ad660eb1 ILT |
3119 | s_bss (ignore) |
3120 | int ignore; | |
542e1629 | 3121 | { |
49864cfa | 3122 | register int temp; |
542e1629 | 3123 | |
49864cfa | 3124 | temp = get_absolute_expression (); |
49864cfa | 3125 | subseg_set (bss_section, (subsegT) temp); |
49864cfa KR |
3126 | demand_empty_rest_of_line (); |
3127 | } | |
542e1629 | 3128 | |
49864cfa | 3129 | #endif |
355afbcd | 3130 | |
542e1629 | 3131 | |
49864cfa | 3132 | #ifdef BFD_ASSEMBLER |
c54c7aac KR |
3133 | |
3134 | void | |
3135 | i386_validate_fix (fixp) | |
3136 | fixS *fixp; | |
3137 | { | |
3138 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
3139 | { | |
3140 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
3141 | fixp->fx_subsy = 0; | |
3142 | } | |
3143 | } | |
3144 | ||
f0b37b4a KR |
3145 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
3146 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
542e1629 | 3147 | |
49864cfa KR |
3148 | arelent * |
3149 | tc_gen_reloc (section, fixp) | |
3150 | asection *section; | |
3151 | fixS *fixp; | |
542e1629 | 3152 | { |
ad660eb1 | 3153 | arelent *rel; |
49864cfa | 3154 | bfd_reloc_code_real_type code; |
542e1629 | 3155 | |
f0b37b4a | 3156 | switch(fixp->fx_r_type) |
49864cfa | 3157 | { |
f0b37b4a KR |
3158 | case BFD_RELOC_386_PLT32: |
3159 | case BFD_RELOC_386_GOT32: | |
3160 | case BFD_RELOC_386_GOTOFF: | |
3161 | case BFD_RELOC_386_GOTPC: | |
a52f90a4 | 3162 | case BFD_RELOC_RVA: |
f0b37b4a KR |
3163 | code = fixp->fx_r_type; |
3164 | break; | |
3165 | default: | |
3166 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
3167 | { | |
f0b37b4a KR |
3168 | MAP (1, 0, BFD_RELOC_8); |
3169 | MAP (2, 0, BFD_RELOC_16); | |
f0b37b4a | 3170 | MAP (4, 0, BFD_RELOC_32); |
f0b37b4a KR |
3171 | MAP (1, 1, BFD_RELOC_8_PCREL); |
3172 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
f0b37b4a KR |
3173 | MAP (4, 1, BFD_RELOC_32_PCREL); |
3174 | default: | |
48401fcf TT |
3175 | if (fixp->fx_pcrel) |
3176 | as_bad (_("Can not do %d byte pc-relative relocation"), | |
3177 | fixp->fx_size); | |
3178 | else | |
3179 | as_bad (_("Can not do %d byte relocation"), fixp->fx_size); | |
f0b37b4a | 3180 | } |
49864cfa | 3181 | } |
3c8df4ba KR |
3182 | #undef MAP |
3183 | #undef F | |
542e1629 | 3184 | |
f0b37b4a KR |
3185 | if (code == BFD_RELOC_32 |
3186 | && GOT_symbol | |
3187 | && fixp->fx_addsy == GOT_symbol) | |
3188 | code = BFD_RELOC_386_GOTPC; | |
3189 | ||
590c50d8 | 3190 | rel = (arelent *) xmalloc (sizeof (arelent)); |
ad660eb1 ILT |
3191 | rel->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
3192 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
49864cfa | 3193 | if (fixp->fx_pcrel) |
ad660eb1 | 3194 | rel->addend = fixp->fx_addnumber; |
49864cfa | 3195 | else |
ad660eb1 | 3196 | rel->addend = 0; |
355afbcd | 3197 | |
ad660eb1 | 3198 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
e592f0e6 | 3199 | if (rel->howto == NULL) |
ad660eb1 | 3200 | { |
e592f0e6 | 3201 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 3202 | _("Cannot represent relocation type %s"), |
e592f0e6 ILT |
3203 | bfd_get_reloc_code_name (code)); |
3204 | /* Set howto to a garbage value so that we can keep going. */ | |
3205 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
3206 | assert (rel->howto != NULL); | |
ad660eb1 | 3207 | } |
49864cfa | 3208 | |
ad660eb1 | 3209 | return rel; |
49864cfa KR |
3210 | } |
3211 | ||
3212 | #else /* ! BFD_ASSEMBLER */ | |
3213 | ||
3214 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
3215 | void | |
3216 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
3217 | char *where; | |
3218 | fixS *fixP; | |
3219 | relax_addressT segment_address_in_file; | |
4b77b129 | 3220 | { |
49864cfa KR |
3221 | /* |
3222 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3223 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3224 | */ | |
4b77b129 | 3225 | |
3c8df4ba | 3226 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
49864cfa KR |
3227 | long r_symbolnum; |
3228 | ||
3229 | know (fixP->fx_addsy != NULL); | |
3230 | ||
3231 | md_number_to_chars (where, | |
ad660eb1 ILT |
3232 | (valueT) (fixP->fx_frag->fr_address |
3233 | + fixP->fx_where - segment_address_in_file), | |
49864cfa KR |
3234 | 4); |
3235 | ||
3236 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
3237 | ? S_GET_TYPE (fixP->fx_addsy) | |
3238 | : fixP->fx_addsy->sy_number); | |
3239 | ||
3240 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
3241 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3242 | where[4] = r_symbolnum & 0x0ff; | |
3243 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
3244 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
3245 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4b77b129 | 3246 | } |
355afbcd | 3247 | |
49864cfa | 3248 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4b77b129 | 3249 | |
49864cfa | 3250 | #if defined (I386COFF) |
4b77b129 | 3251 | |
355afbcd KR |
3252 | short |
3253 | tc_coff_fix2rtype (fixP) | |
3254 | fixS *fixP; | |
4b77b129 | 3255 | { |
3ea36b53 ILT |
3256 | if (fixP->fx_r_type == R_IMAGEBASE) |
3257 | return R_IMAGEBASE; | |
3258 | ||
355afbcd KR |
3259 | return (fixP->fx_pcrel ? |
3260 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
3261 | fixP->fx_size == 2 ? R_PCRWORD : | |
3262 | R_PCRLONG) : | |
3263 | (fixP->fx_size == 1 ? R_RELBYTE : | |
3264 | fixP->fx_size == 2 ? R_RELWORD : | |
3265 | R_DIR32)); | |
4b77b129 ILT |
3266 | } |
3267 | ||
49864cfa KR |
3268 | int |
3269 | tc_coff_sizemachdep (frag) | |
3270 | fragS *frag; | |
3271 | { | |
3272 | if (frag->fr_next) | |
3273 | return (frag->fr_next->fr_address - frag->fr_address); | |
3274 | else | |
3275 | return 0; | |
3276 | } | |
3277 | ||
3278 | #endif /* I386COFF */ | |
3279 | ||
3280 | #endif /* BFD_ASSEMBLER? */ | |
3ea36b53 | 3281 | \f |
fecd2382 | 3282 | /* end of tc-i386.c */ |