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Improve documentation of general query packets
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
d3ce72d0 176static const insn_template *match_template (void);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132
RH		 328
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
333
334 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 335 addressing modes of this insn are encoded. */
252b5132 336 modrm_byte rm;
3e73aa7c 337 rex_byte rex;
43234a1e 338 rex_byte vrex;
252b5132 339 sib_byte sib;
c0f3af97 340 vex_prefix vex;
b6169b20 341
43234a1e
L		 342 /* Masking attributes. */
343 struct Mask_Operation *mask;
344
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
347
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
350
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
353
b6169b20 354 /* Swap operand in encoding. */
4473e004 355 unsigned int swap_operand;
891edac4 356
a501d77e
L		 357 /* Prefer 8bit or 32bit displacement in encoding. */
358 enum
359 {
360 disp_encoding_default = 0,
361 disp_encoding_8bit,
362 disp_encoding_32bit
363 } disp_encoding;
f8a5c266 364
d5de92cf
L		 365 /* REP prefix. */
366 const char *rep_prefix;
367
165de32a
L		 368 /* HLE prefix. */
369 const char *hle_prefix;
42164a71 370
7e8b059b
L		 371 /* Have BND prefix. */
372 const char *bnd_prefix;
373
43234a1e
L		 374 /* Need VREX to support upper 16 registers. */
375 int need_vrex;
376
891edac4 377 /* Error message. */
a65babc9 378 enum i386_error error;
252b5132
RH		 379 };
380
381typedef struct _i386_insn i386_insn;
382
43234a1e
L		 383/* Link RC type with corresponding string, that'll be looked for in
384 asm. */
385struct RC_name
386{
387 enum rc_type type;
388 const char *name;
389 unsigned int len;
390};
391
392static const struct RC_name RC_NamesTable[] =
393{
394 { rne, STRING_COMMA_LEN ("rn-sae") },
395 { rd, STRING_COMMA_LEN ("rd-sae") },
396 { ru, STRING_COMMA_LEN ("ru-sae") },
397 { rz, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly, STRING_COMMA_LEN ("sae") },
399};
400
252b5132
RH		 401/* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 403const char extra_symbol_chars[] = "*%-([{"
252b5132 404#ifdef LEX_AT
32137342
NC		 405 "@"
406#endif
407#ifdef LEX_QM
408 "?"
252b5132 409#endif
32137342 410 ;
252b5132 411
29b0f896
AM		 412#if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 414 && !defined (TE_GNU) \
29b0f896 415 && !defined (TE_LINUX) \
8d63c93e
RM		 416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
29b0f896 418 && !defined (TE_FreeBSD) \
5b806d27 419 && !defined (TE_DragonFly) \
29b0f896 420 && !defined (TE_NetBSD)))
252b5132 421/* This array holds the chars that always start a comment. If the
b3b91714
AM		 422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424const char *i386_comment_chars = "#/";
425#define SVR4_COMMENT_CHARS 1
252b5132 426#define PREFIX_SEPARATOR '\\'
252b5132 427
b3b91714
AM		 428#else
429const char *i386_comment_chars = "#";
430#define PREFIX_SEPARATOR '/'
431#endif
432
252b5132
RH		 433/* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 437 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
252b5132 440 '/' isn't otherwise defined. */
b3b91714 441const char line_comment_chars[] = "#/";
252b5132 442
63a0b638 443const char line_separator_chars[] = ";";
252b5132 444
ce8a8b2f
AM		 445/* Chars that can be used to separate mant from exp in floating point
446 nums. */
252b5132
RH		 447const char EXP_CHARS[] = "eE";
448
ce8a8b2f
AM		 449/* Chars that mean this number is a floating point constant
450 As in 0f12.456
451 or 0d1.2345e12. */
252b5132
RH		 452const char FLT_CHARS[] = "fFdDxX";
453
ce8a8b2f 454/* Tables for lexical analysis. */
252b5132
RH		 455static char mnemonic_chars[256];
456static char register_chars[256];
457static char operand_chars[256];
458static char identifier_chars[256];
459static char digit_chars[256];
460
ce8a8b2f 461/* Lexical macros. */
252b5132
RH		 462#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463#define is_operand_char(x) (operand_chars[(unsigned char) x])
464#define is_register_char(x) (register_chars[(unsigned char) x])
465#define is_space_char(x) ((x) == ' ')
466#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467#define is_digit_char(x) (digit_chars[(unsigned char) x])
468
0234cb7c 469/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 470static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
471
472/* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
47926f60 475 assembler instruction). */
252b5132 476static char save_stack[32];
ce8a8b2f 477static char *save_stack_p;
252b5132
RH		 478#define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480#define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
482
47926f60 483/* The instruction we're assembling. */
252b5132
RH		 484static i386_insn i;
485
486/* Possible templates for current insn. */
487static const templates *current_templates;
488
31b2323c
L		 489/* Per instruction expressionS buffers: max displacements & immediates. */
490static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
491static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 492
47926f60 493/* Current operand we are working on. */
ee86248c 494static int this_operand = -1;
252b5132 495
3e73aa7c
JH		 496/* We support four different modes. FLAG_CODE variable is used to distinguish
497 these. */
498
499enum flag_code {
500 CODE_32BIT,
501 CODE_16BIT,
502 CODE_64BIT };
503
504static enum flag_code flag_code;
4fa24527 505static unsigned int object_64bit;
862be3fb 506static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 507static int use_rela_relocations = 0;
508
7af8ed2d
NC		 509#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
512
351f65ca
L		 513/* The ELF ABI to use. */
514enum x86_elf_abi
515{
516 I386_ABI,
7f56bc95
L		 517 X86_64_ABI,
518 X86_64_X32_ABI
351f65ca
L		 519};
520
521static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 522#endif
351f65ca 523
167ad85b
TG		 524#if defined (TE_PE) || defined (TE_PEP)
525/* Use big object file format. */
526static int use_big_obj = 0;
527#endif
528
8dcea932
L		 529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530/* 1 if generating code for a shared library. */
531static int shared = 0;
532#endif
533
47926f60
KH		 534/* 1 for intel syntax,
535 0 if att syntax. */
536static int intel_syntax = 0;
252b5132 537
e89c5eaa
L		 538/* 1 for Intel64 ISA,
539 0 if AMD64 ISA. */
540static int intel64;
541
1efbbeb4
L		 542/* 1 for intel mnemonic,
543 0 if att mnemonic. */
544static int intel_mnemonic = !SYSV386_COMPAT;
545
5209009a 546/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 547static int old_gcc = OLDGCC_COMPAT;
548
a60de03c
JB		 549/* 1 if pseudo registers are permitted. */
550static int allow_pseudo_reg = 0;
551
47926f60
KH		 552/* 1 if register prefix % not required. */
553static int allow_naked_reg = 0;
252b5132 554
7e8b059b
L		 555/* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
557 explicitly. */
558static int add_bnd_prefix = 0;
559
ba104c83 560/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 561static int allow_index_reg = 0;
562
d022bddd
IT		 563/* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565static int omit_lock_prefix = 0;
566
e4e00185
AS		 567/* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569static int avoid_fence = 0;
570
0cb4071e
L		 571/* 1 if the assembler should generate relax relocations. */
572
573static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
575
7bab8ab5 576static enum check_kind
daf50ae7 577 {
7bab8ab5
JB		 578 check_none = 0,
579 check_warning,
580 check_error
daf50ae7 581 }
7bab8ab5 582sse_check, operand_check = check_warning;
daf50ae7 583
2ca3ace5
L		 584/* Register prefix used for error message. */
585static const char *register_prefix = "%";
586
47926f60
KH		 587/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590static char stackop_size = '\0';
eecb386c 591
12b55ccc
L		 592/* Non-zero to optimize code alignment. */
593int optimize_align_code = 1;
594
47926f60
KH		 595/* Non-zero to quieten some warnings. */
596static int quiet_warnings = 0;
a38cf1db 597
47926f60
KH		 598/* CPU name. */
599static const char *cpu_arch_name = NULL;
6305a203 600static char *cpu_sub_arch_name = NULL;
a38cf1db 601
47926f60 602/* CPU feature flags. */
40fb9820
L		 603static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
604
ccc9c027
L		 605/* If we have selected a cpu we are generating instructions for. */
606static int cpu_arch_tune_set = 0;
607
9103f4f4 608/* Cpu we are generating instructions for. */
fbf3f584 609enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 610
611/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 612static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 613
ccc9c027 614/* CPU instruction set architecture used. */
fbf3f584 615enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 616
9103f4f4 617/* CPU feature flags of instruction set architecture used. */
fbf3f584 618i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 619
fddf5b5b
AM		 620/* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622static unsigned int no_cond_jump_promotion = 0;
623
c0f3af97
L		 624/* Encode SSE instructions with VEX prefix. */
625static unsigned int sse2avx;
626
539f890d
L		 627/* Encode scalar AVX instructions with specific vector length. */
628static enum
629 {
630 vex128 = 0,
631 vex256
632 } avxscalar;
633
43234a1e
L		 634/* Encode scalar EVEX LIG instructions with specific vector length. */
635static enum
636 {
637 evexl128 = 0,
638 evexl256,
639 evexl512
640 } evexlig;
641
642/* Encode EVEX WIG instructions with specific evex.w. */
643static enum
644 {
645 evexw0 = 0,
646 evexw1
647 } evexwig;
648
d3d3c6db
IT		 649/* Value to encode in EVEX RC bits, for SAE-only instructions. */
650static enum rc_type evexrcig = rne;
651
29b0f896 652/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 653static symbolS *GOT_symbol;
29b0f896 654
a4447b93
RH		 655/* The dwarf2 return column, adjusted for 32 or 64 bit. */
656unsigned int x86_dwarf2_return_column;
657
658/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659int x86_cie_data_alignment;
660
252b5132 661/* Interface to relax_segment.
fddf5b5b
AM		 662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
252b5132 665
47926f60 666/* Types. */
93c2a809
AM		 667#define UNCOND_JUMP 0
668#define COND_JUMP 1
669#define COND_JUMP86 2
fddf5b5b 670
47926f60 671/* Sizes. */
252b5132
RH		 672#define CODE16 1
673#define SMALL 0
29b0f896 674#define SMALL16 (SMALL | CODE16)
252b5132 675#define BIG 2
29b0f896 676#define BIG16 (BIG | CODE16)
252b5132
RH		 677
678#ifndef INLINE
679#ifdef __GNUC__
680#define INLINE __inline__
681#else
682#define INLINE
683#endif
684#endif
685
fddf5b5b
AM		 686#define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688#define TYPE_FROM_RELAX_STATE(s) \
689 ((s) >> 2)
690#define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 692
693/* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
700
701const relax_typeS md_relax_table[] =
702{
24eab124
AM		 703 /* The fields are:
704 1) most positive reach of this state,
705 2) most negative reach of this state,
93c2a809 706 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 707 4) which index into the table to try if we can't fit into this one. */
252b5132 708
fddf5b5b 709 /* UNCOND_JUMP states. */
93c2a809
AM		 710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
252b5132 714 {0, 0, 4, 0},
93c2a809
AM		 715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 717 {0, 0, 2, 0},
718
93c2a809
AM		 719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
724 {0, 0, 5, 0},
fddf5b5b 725 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 726 1 extra opcode byte, 2 displacement bytes. */
727 {0, 0, 3, 0},
728
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
734 {0, 0, 5, 0},
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
737 {0, 0, 4, 0}
252b5132
RH		 738};
739
9103f4f4
L		 740static const arch_entry cpu_arch[] =
741{
89507696
JB		 742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
8a2c8fef 744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 745 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 747 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 749 CPU_NONE_FLAGS, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 751 CPU_I186_FLAGS, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 753 CPU_I286_FLAGS, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 755 CPU_I386_FLAGS, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 757 CPU_I486_FLAGS, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 759 CPU_I586_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 761 CPU_I686_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 763 CPU_I586_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 765 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 767 CPU_P2_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 769 CPU_P3_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 771 CPU_P4_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 773 CPU_CORE_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 775 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 777 CPU_CORE_FLAGS, 1 },
8a2c8fef 778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 779 CPU_CORE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 781 CPU_CORE2_FLAGS, 1 },
8a2c8fef 782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 783 CPU_CORE2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 785 CPU_COREI7_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 787 CPU_L1OM_FLAGS, 0 },
7a9068fe 788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 789 CPU_K1OM_FLAGS, 0 },
81486035 790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 791 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 793 CPU_K6_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 795 CPU_K6_2_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 797 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 799 CPU_K8_FLAGS, 1 },
8a2c8fef 800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 801 CPU_K8_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 803 CPU_K8_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 805 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 807 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 809 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 811 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 813 CPU_BDVER4_FLAGS, 0 },
029f3522 814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 815 CPU_ZNVER1_FLAGS, 0 },
7b458c12 816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 817 CPU_BTVER1_FLAGS, 0 },
7b458c12 818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 819 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 821 CPU_8087_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 823 CPU_287_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 825 CPU_387_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 827 CPU_MMX_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 829 CPU_SSE_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 831 CPU_SSE2_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 833 CPU_SSE3_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_AVX_FLAGS, 0 },
6c30d220 844 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_AVX2_FLAGS, 0 },
43234a1e 846 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_AVX512F_FLAGS, 0 },
43234a1e 848 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_AVX512CD_FLAGS, 0 },
43234a1e 850 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_AVX512ER_FLAGS, 0 },
43234a1e 852 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 854 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 856 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 858 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_VMX_FLAGS, 0 },
8729a6f6 862 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SMX_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 868 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 870 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AES_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 880 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 882 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 884 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_F16C_FLAGS, 0 },
6c30d220 886 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_BMI2_FLAGS, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_FMA_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_FMA4_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_XOP_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_LWP_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_MOVBE_FLAGS, 0 },
60aa667e 898 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_CX16_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_EPT_FLAGS, 0 },
6c30d220 902 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_LZCNT_FLAGS, 0 },
42164a71 904 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_HLE_FLAGS, 0 },
42164a71 906 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_RTM_FLAGS, 0 },
6c30d220 908 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_CLFLUSH_FLAGS, 0 },
22109423 912 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_NOP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_SVME_FLAGS, 1 },
8a2c8fef 926 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_SVME_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_ABM_FLAGS, 0 },
87973e9f 932 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_BMI_FLAGS, 0 },
2a2a0f38 934 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_TBM_FLAGS, 0 },
e2e1fcde 936 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_ADX_FLAGS, 0 },
e2e1fcde 938 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 940 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_PRFCHW_FLAGS, 0 },
5c111e37 942 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SMAP_FLAGS, 0 },
7e8b059b 944 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_MPX_FLAGS, 0 },
a0046408 946 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SHA_FLAGS, 0 },
963f3586 948 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 950 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 952 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_SE1_FLAGS, 0 },
c5e7287a 954 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_CLWB_FLAGS, 0 },
9d8596f0 956 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 958 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 960 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 962 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_CLZERO_FLAGS, 0 },
9916071f 964 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_MWAITX_FLAGS, 0 },
8eab4136 966 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_OSPKE_FLAGS, 0 },
8bc52696 968 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 969 CPU_RDPID_FLAGS, 0 },
970};
971
972static const noarch_entry cpu_noarch[] =
973{
974 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
975 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
976 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
977 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
e413e4e9
AM		 978};
979
704209c0 980#ifdef I386COFF
a6c24e68
NC		 981/* Like s_lcomm_internal in gas/read.c but the alignment string
982 is allowed to be optional. */
983
984static symbolS *
985pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
986{
987 addressT align = 0;
988
989 SKIP_WHITESPACE ();
990
7ab9ffdd 991 if (needs_align
a6c24e68
NC		 992 && *input_line_pointer == ',')
993 {
994 align = parse_align (needs_align - 1);
7ab9ffdd 995
a6c24e68
NC		 996 if (align == (addressT) -1)
997 return NULL;
998 }
999 else
1000 {
1001 if (size >= 8)
1002 align = 3;
1003 else if (size >= 4)
1004 align = 2;
1005 else if (size >= 2)
1006 align = 1;
1007 else
1008 align = 0;
1009 }
1010
1011 bss_alloc (symbolP, size, align);
1012 return symbolP;
1013}
1014
704209c0 1015static void
a6c24e68
NC		 1016pe_lcomm (int needs_align)
1017{
1018 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1019}
704209c0 1020#endif
a6c24e68 1021
29b0f896
AM		 1022const pseudo_typeS md_pseudo_table[] =
1023{
1024#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1025 {"align", s_align_bytes, 0},
1026#else
1027 {"align", s_align_ptwo, 0},
1028#endif
1029 {"arch", set_cpu_arch, 0},
1030#ifndef I386COFF
1031 {"bss", s_bss, 0},
a6c24e68
NC		 1032#else
1033 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1034#endif
1035 {"ffloat", float_cons, 'f'},
1036 {"dfloat", float_cons, 'd'},
1037 {"tfloat", float_cons, 'x'},
1038 {"value", cons, 2},
d182319b 1039 {"slong", signed_cons, 4},
29b0f896
AM		 1040 {"noopt", s_ignore, 0},
1041 {"optim", s_ignore, 0},
1042 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1043 {"code16", set_code_flag, CODE_16BIT},
1044 {"code32", set_code_flag, CODE_32BIT},
1045 {"code64", set_code_flag, CODE_64BIT},
1046 {"intel_syntax", set_intel_syntax, 1},
1047 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1048 {"intel_mnemonic", set_intel_mnemonic, 1},
1049 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1050 {"allow_index_reg", set_allow_index_reg, 1},
1051 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1052 {"sse_check", set_check, 0},
1053 {"operand_check", set_check, 1},
3b22753a
L		 1054#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1055 {"largecomm", handle_large_common, 0},
07a53e5c 1056#else
e3bb37b5 1057 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1058 {"loc", dwarf2_directive_loc, 0},
1059 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1060#endif
6482c264
NC		 1061#ifdef TE_PE
1062 {"secrel32", pe_directive_secrel, 0},
1063#endif
29b0f896
AM		 1064 {0, 0, 0}
1065};
1066
1067/* For interface with expression (). */
1068extern char *input_line_pointer;
1069
1070/* Hash table for instruction mnemonic lookup. */
1071static struct hash_control *op_hash;
1072
1073/* Hash table for register lookup. */
1074static struct hash_control *reg_hash;
1075\f
252b5132 1076void
e3bb37b5 1077i386_align_code (fragS *fragP, int count)
252b5132 1078{
ce8a8b2f
AM		 1079 /* Various efficient no-op patterns for aligning code labels.
1080 Note: Don't try to assemble the instructions in the comments.
1081 0L and 0w are not legal. */
bad6e36d 1082 static const unsigned char f32_1[] =
252b5132 1083 {0x90}; /* nop */
bad6e36d 1084 static const unsigned char f32_2[] =
ccc9c027 1085 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1086 static const unsigned char f32_3[] =
252b5132 1087 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1088 static const unsigned char f32_4[] =
252b5132 1089 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1090 static const unsigned char f32_5[] =
252b5132
RH		 1091 {0x90, /* nop */
1092 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1093 static const unsigned char f32_6[] =
252b5132 1094 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1095 static const unsigned char f32_7[] =
252b5132 1096 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1097 static const unsigned char f32_8[] =
252b5132
RH		 1098 {0x90, /* nop */
1099 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1100 static const unsigned char f32_9[] =
252b5132
RH		 1101 {0x89,0xf6, /* movl %esi,%esi */
1102 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1103 static const unsigned char f32_10[] =
252b5132
RH		 1104 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1105 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1106 static const unsigned char f32_11[] =
252b5132
RH		 1107 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1108 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1109 static const unsigned char f32_12[] =
252b5132
RH		 1110 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1111 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1112 static const unsigned char f32_13[] =
252b5132
RH		 1113 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1114 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1115 static const unsigned char f32_14[] =
252b5132
RH		 1116 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1117 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1118 static const unsigned char f16_3[] =
c3332e24 1119 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1120 static const unsigned char f16_4[] =
252b5132 1121 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1122 static const unsigned char f16_5[] =
252b5132
RH		 1123 {0x90, /* nop */
1124 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1125 static const unsigned char f16_6[] =
252b5132
RH		 1126 {0x89,0xf6, /* mov %si,%si */
1127 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1128 static const unsigned char f16_7[] =
252b5132
RH		 1129 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1130 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1131 static const unsigned char f16_8[] =
252b5132
RH		 1132 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1133 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1134 static const unsigned char jump_31[] =
76bc74dc
L		 1135 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1136 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1137 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1138 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1139 static const unsigned char *const f32_patt[] = {
252b5132 1140 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1141 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1142 };
bad6e36d 1143 static const unsigned char *const f16_patt[] = {
76bc74dc 1144 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1145 };
ccc9c027 1146 /* nopl (%[re]ax) */
bad6e36d 1147 static const unsigned char alt_3[] =
ccc9c027
L		 1148 {0x0f,0x1f,0x00};
1149 /* nopl 0(%[re]ax) */
bad6e36d 1150 static const unsigned char alt_4[] =
ccc9c027
L		 1151 {0x0f,0x1f,0x40,0x00};
1152 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1153 static const unsigned char alt_5[] =
ccc9c027
L		 1154 {0x0f,0x1f,0x44,0x00,0x00};
1155 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1156 static const unsigned char alt_6[] =
ccc9c027
L		 1157 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1158 /* nopl 0L(%[re]ax) */
bad6e36d 1159 static const unsigned char alt_7[] =
ccc9c027
L		 1160 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1161 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1162 static const unsigned char alt_8[] =
ccc9c027
L		 1163 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1164 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1165 static const unsigned char alt_9[] =
ccc9c027
L		 1166 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1167 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1168 static const unsigned char alt_10[] =
ccc9c027 1169 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1170 static const unsigned char *const alt_patt[] = {
ccc9c027 1171 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1172 alt_9, alt_10
ccc9c027 1173 };
252b5132 1174
76bc74dc
L		 1175 /* Only align for at least a positive non-zero boundary. */
1176 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1177 return;
3e73aa7c 1178
ccc9c027
L		 1179 /* We need to decide which NOP sequence to use for 32bit and
1180 64bit. When -mtune= is used:
4eed87de 1181
76bc74dc
L		 1182 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1183 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1184 2. For the rest, alt_patt will be used.
1185
1186 When -mtune= isn't used, alt_patt will be used if
22109423 1187 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1188 be used.
ccc9c027
L		 1189
1190 When -march= or .arch is used, we can't use anything beyond
1191 cpu_arch_isa_flags. */
1192
1193 if (flag_code == CODE_16BIT)
1194 {
ccc9c027 1195 if (count > 8)
33fef721 1196 {
76bc74dc
L		 1197 memcpy (fragP->fr_literal + fragP->fr_fix,
1198 jump_31, count);
1199 /* Adjust jump offset. */
1200 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1201 }
76bc74dc
L		 1202 else
1203 memcpy (fragP->fr_literal + fragP->fr_fix,
1204 f16_patt[count - 1], count);
252b5132 1205 }
33fef721 1206 else
ccc9c027 1207 {
bad6e36d 1208 const unsigned char *const *patt = NULL;
ccc9c027 1209
fbf3f584 1210 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1211 {
1212 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1213 switch (cpu_arch_tune)
1214 {
1215 case PROCESSOR_UNKNOWN:
1216 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1217 optimize with nops. */
1218 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1219 patt = alt_patt;
ccc9c027
L		 1220 else
1221 patt = f32_patt;
1222 break;
ccc9c027
L		 1223 case PROCESSOR_PENTIUM4:
1224 case PROCESSOR_NOCONA:
ef05d495 1225 case PROCESSOR_CORE:
76bc74dc 1226 case PROCESSOR_CORE2:
bd5295b2 1227 case PROCESSOR_COREI7:
3632d14b 1228 case PROCESSOR_L1OM:
7a9068fe 1229 case PROCESSOR_K1OM:
76bc74dc 1230 case PROCESSOR_GENERIC64:
ccc9c027
L		 1231 case PROCESSOR_K6:
1232 case PROCESSOR_ATHLON:
1233 case PROCESSOR_K8:
4eed87de 1234 case PROCESSOR_AMDFAM10:
8aedb9fe 1235 case PROCESSOR_BD:
029f3522 1236 case PROCESSOR_ZNVER:
7b458c12 1237 case PROCESSOR_BT:
80b8656c 1238 patt = alt_patt;
ccc9c027 1239 break;
76bc74dc 1240 case PROCESSOR_I386:
ccc9c027
L		 1241 case PROCESSOR_I486:
1242 case PROCESSOR_PENTIUM:
2dde1948 1243 case PROCESSOR_PENTIUMPRO:
81486035 1244 case PROCESSOR_IAMCU:
ccc9c027
L		 1245 case PROCESSOR_GENERIC32:
1246 patt = f32_patt;
1247 break;
4eed87de 1248 }
ccc9c027
L		 1249 }
1250 else
1251 {
fbf3f584 1252 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1253 {
1254 case PROCESSOR_UNKNOWN:
e6a14101 1255 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1256 PROCESSOR_UNKNOWN. */
1257 abort ();
1258 break;
1259
76bc74dc 1260 case PROCESSOR_I386:
ccc9c027
L		 1261 case PROCESSOR_I486:
1262 case PROCESSOR_PENTIUM:
81486035 1263 case PROCESSOR_IAMCU:
ccc9c027
L		 1264 case PROCESSOR_K6:
1265 case PROCESSOR_ATHLON:
1266 case PROCESSOR_K8:
4eed87de 1267 case PROCESSOR_AMDFAM10:
8aedb9fe 1268 case PROCESSOR_BD:
029f3522 1269 case PROCESSOR_ZNVER:
7b458c12 1270 case PROCESSOR_BT:
ccc9c027
L		 1271 case PROCESSOR_GENERIC32:
1272 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1273 with nops. */
1274 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1275 patt = alt_patt;
ccc9c027
L		 1276 else
1277 patt = f32_patt;
1278 break;
76bc74dc
L		 1279 case PROCESSOR_PENTIUMPRO:
1280 case PROCESSOR_PENTIUM4:
1281 case PROCESSOR_NOCONA:
1282 case PROCESSOR_CORE:
ef05d495 1283 case PROCESSOR_CORE2:
bd5295b2 1284 case PROCESSOR_COREI7:
3632d14b 1285 case PROCESSOR_L1OM:
7a9068fe 1286 case PROCESSOR_K1OM:
22109423 1287 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1288 patt = alt_patt;
ccc9c027
L		 1289 else
1290 patt = f32_patt;
1291 break;
1292 case PROCESSOR_GENERIC64:
80b8656c 1293 patt = alt_patt;
ccc9c027 1294 break;
4eed87de 1295 }
ccc9c027
L		 1296 }
1297
76bc74dc
L		 1298 if (patt == f32_patt)
1299 {
1300 /* If the padding is less than 15 bytes, we use the normal
1301 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1302 its offset. */
1303 int limit;
76ba9986 1304
711eedef
L		 1305 /* For 64bit, the limit is 3 bytes. */
1306 if (flag_code == CODE_64BIT
1307 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1308 limit = 3;
1309 else
1310 limit = 15;
1311 if (count < limit)
76bc74dc
L		 1312 memcpy (fragP->fr_literal + fragP->fr_fix,
1313 patt[count - 1], count);
1314 else
1315 {
1316 memcpy (fragP->fr_literal + fragP->fr_fix,
1317 jump_31, count);
1318 /* Adjust jump offset. */
1319 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1320 }
1321 }
1322 else
1323 {
80b8656c
L		 1324 /* Maximum length of an instruction is 10 byte. If the
1325 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1326 we have to break it into smaller pieces. */
1327 int padding = count;
80b8656c 1328 while (padding > 10)
76bc74dc 1329 {
80b8656c 1330 padding -= 10;
76bc74dc 1331 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1332 patt [9], 10);
76bc74dc
L		 1333 }
1334
1335 if (padding)
1336 memcpy (fragP->fr_literal + fragP->fr_fix,
1337 patt [padding - 1], padding);
1338 }
ccc9c027 1339 }
33fef721 1340 fragP->fr_var = count;
252b5132
RH		 1341}
1342
c6fb90c8 1343static INLINE int
0dfbf9d7 1344operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1345{
0dfbf9d7 1346 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1347 {
1348 case 3:
0dfbf9d7 1349 if (x->array[2])
c6fb90c8
L		 1350 return 0;
1351 case 2:
0dfbf9d7 1352 if (x->array[1])
c6fb90c8
L		 1353 return 0;
1354 case 1:
0dfbf9d7 1355 return !x->array[0];
c6fb90c8
L		 1356 default:
1357 abort ();
1358 }
40fb9820
L		 1359}
1360
c6fb90c8 1361static INLINE void
0dfbf9d7 1362operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1363{
0dfbf9d7 1364 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1365 {
1366 case 3:
0dfbf9d7 1367 x->array[2] = v;
c6fb90c8 1368 case 2:
0dfbf9d7 1369 x->array[1] = v;
c6fb90c8 1370 case 1:
0dfbf9d7 1371 x->array[0] = v;
c6fb90c8
L		 1372 break;
1373 default:
1374 abort ();
1375 }
1376}
40fb9820 1377
c6fb90c8 1378static INLINE int
0dfbf9d7
L		 1379operand_type_equal (const union i386_operand_type *x,
1380 const union i386_operand_type *y)
c6fb90c8 1381{
0dfbf9d7 1382 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1383 {
1384 case 3:
0dfbf9d7 1385 if (x->array[2] != y->array[2])
c6fb90c8
L		 1386 return 0;
1387 case 2:
0dfbf9d7 1388 if (x->array[1] != y->array[1])
c6fb90c8
L		 1389 return 0;
1390 case 1:
0dfbf9d7 1391 return x->array[0] == y->array[0];
c6fb90c8
L		 1392 break;
1393 default:
1394 abort ();
1395 }
1396}
40fb9820 1397
0dfbf9d7
L		 1398static INLINE int
1399cpu_flags_all_zero (const union i386_cpu_flags *x)
1400{
1401 switch (ARRAY_SIZE(x->array))
1402 {
1403 case 3:
1404 if (x->array[2])
1405 return 0;
1406 case 2:
1407 if (x->array[1])
1408 return 0;
1409 case 1:
1410 return !x->array[0];
1411 default:
1412 abort ();
1413 }
1414}
1415
0dfbf9d7
L		 1416static INLINE int
1417cpu_flags_equal (const union i386_cpu_flags *x,
1418 const union i386_cpu_flags *y)
1419{
1420 switch (ARRAY_SIZE(x->array))
1421 {
1422 case 3:
1423 if (x->array[2] != y->array[2])
1424 return 0;
1425 case 2:
1426 if (x->array[1] != y->array[1])
1427 return 0;
1428 case 1:
1429 return x->array[0] == y->array[0];
1430 break;
1431 default:
1432 abort ();
1433 }
1434}
c6fb90c8
L		 1435
1436static INLINE int
1437cpu_flags_check_cpu64 (i386_cpu_flags f)
1438{
1439 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1440 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1441}
1442
c6fb90c8
L		 1443static INLINE i386_cpu_flags
1444cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1445{
c6fb90c8
L		 1446 switch (ARRAY_SIZE (x.array))
1447 {
1448 case 3:
1449 x.array [2] &= y.array [2];
1450 case 2:
1451 x.array [1] &= y.array [1];
1452 case 1:
1453 x.array [0] &= y.array [0];
1454 break;
1455 default:
1456 abort ();
1457 }
1458 return x;
1459}
40fb9820 1460
c6fb90c8
L		 1461static INLINE i386_cpu_flags
1462cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1463{
c6fb90c8 1464 switch (ARRAY_SIZE (x.array))
40fb9820 1465 {
c6fb90c8
L		 1466 case 3:
1467 x.array [2] |= y.array [2];
1468 case 2:
1469 x.array [1] |= y.array [1];
1470 case 1:
1471 x.array [0] |= y.array [0];
40fb9820
L		 1472 break;
1473 default:
1474 abort ();
1475 }
40fb9820
L		 1476 return x;
1477}
1478
309d3373
JB		 1479static INLINE i386_cpu_flags
1480cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1481{
1482 switch (ARRAY_SIZE (x.array))
1483 {
1484 case 3:
1485 x.array [2] &= ~y.array [2];
1486 case 2:
1487 x.array [1] &= ~y.array [1];
1488 case 1:
1489 x.array [0] &= ~y.array [0];
1490 break;
1491 default:
1492 abort ();
1493 }
1494 return x;
1495}
1496
81486035
L		 1497static int
1498valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1499{
1500 if (cpu_arch_isa == PROCESSOR_IAMCU)
1501 {
1502 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1503 i386_cpu_flags compat_flags;
1504 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1505 return cpu_flags_all_zero (&compat_flags);
1506 }
1507 else
1508 return 1;
1509}
1510
c0f3af97
L		 1511#define CPU_FLAGS_ARCH_MATCH 0x1
1512#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1513#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1514#define CPU_FLAGS_PCLMUL_MATCH 0x8
1515#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1516
a5ff0eb2 1517#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1518 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1519 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1520#define CPU_FLAGS_PERFECT_MATCH \
1521 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1522
1523/* Return CPU flags match bits. */
3629bb00 1524
40fb9820 1525static int
d3ce72d0 1526cpu_flags_match (const insn_template *t)
40fb9820 1527{
c0f3af97
L		 1528 i386_cpu_flags x = t->cpu_flags;
1529 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1530
1531 x.bitfield.cpu64 = 0;
1532 x.bitfield.cpuno64 = 0;
1533
0dfbf9d7 1534 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1535 {
1536 /* This instruction is available on all archs. */
1537 match |= CPU_FLAGS_32BIT_MATCH;
1538 }
3629bb00
L		 1539 else
1540 {
c0f3af97 1541 /* This instruction is available only on some archs. */
3629bb00
L		 1542 i386_cpu_flags cpu = cpu_arch_flags;
1543
e89c5eaa
L		 1544 /* Set cpuamd64 and cpuintel64 here since they may be changed by
1545 set_cpu_arch. */
1546 cpu_arch_flags.bitfield.cpuamd64 = !intel64;
1547 cpu_arch_flags.bitfield.cpuintel64 = intel64;
1548
3629bb00 1549 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1550 if (!cpu_flags_all_zero (&cpu))
1551 {
a5ff0eb2
L		 1552 if (x.bitfield.cpuavx)
1553 {
ce2f5b3c 1554 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1555 if (cpu.bitfield.cpuavx)
1556 {
1557 /* Check SSE2AVX. */
1558 if (!t->opcode_modifier.sse2avx|| sse2avx)
1559 {
1560 match |= (CPU_FLAGS_ARCH_MATCH
1561 | CPU_FLAGS_AVX_MATCH);
1562 /* Check AES. */
1563 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1564 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1565 /* Check PCLMUL. */
1566 if (!x.bitfield.cpupclmul
1567 || cpu.bitfield.cpupclmul)
1568 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1569 }
1570 }
1571 else
1572 match |= CPU_FLAGS_ARCH_MATCH;
1573 }
73b090a9
L		 1574 else if (x.bitfield.cpuavx512vl)
1575 {
1576 /* Match AVX512VL. */
1577 if (cpu.bitfield.cpuavx512vl)
1578 {
1579 /* Need another match. */
1580 cpu.bitfield.cpuavx512vl = 0;
1581 if (!cpu_flags_all_zero (&cpu))
1582 match |= CPU_FLAGS_32BIT_MATCH;
1583 else
1584 match |= CPU_FLAGS_ARCH_MATCH;
1585 }
1586 else
1587 match |= CPU_FLAGS_ARCH_MATCH;
1588 }
a5ff0eb2 1589 else
c0f3af97
L		 1590 match |= CPU_FLAGS_32BIT_MATCH;
1591 }
3629bb00 1592 }
c0f3af97 1593 return match;
40fb9820
L		 1594}
1595
c6fb90c8
L		 1596static INLINE i386_operand_type
1597operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1598{
c6fb90c8
L		 1599 switch (ARRAY_SIZE (x.array))
1600 {
1601 case 3:
1602 x.array [2] &= y.array [2];
1603 case 2:
1604 x.array [1] &= y.array [1];
1605 case 1:
1606 x.array [0] &= y.array [0];
1607 break;
1608 default:
1609 abort ();
1610 }
1611 return x;
40fb9820
L		 1612}
1613
c6fb90c8
L		 1614static INLINE i386_operand_type
1615operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1616{
c6fb90c8 1617 switch (ARRAY_SIZE (x.array))
40fb9820 1618 {
c6fb90c8
L		 1619 case 3:
1620 x.array [2] |= y.array [2];
1621 case 2:
1622 x.array [1] |= y.array [1];
1623 case 1:
1624 x.array [0] |= y.array [0];
40fb9820
L		 1625 break;
1626 default:
1627 abort ();
1628 }
c6fb90c8
L		 1629 return x;
1630}
40fb9820 1631
c6fb90c8
L		 1632static INLINE i386_operand_type
1633operand_type_xor (i386_operand_type x, i386_operand_type y)
1634{
1635 switch (ARRAY_SIZE (x.array))
1636 {
1637 case 3:
1638 x.array [2] ^= y.array [2];
1639 case 2:
1640 x.array [1] ^= y.array [1];
1641 case 1:
1642 x.array [0] ^= y.array [0];
1643 break;
1644 default:
1645 abort ();
1646 }
40fb9820
L		 1647 return x;
1648}
1649
1650static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1651static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1652static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1653static const i386_operand_type inoutportreg
1654 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1655static const i386_operand_type reg16_inoutportreg
1656 = OPERAND_TYPE_REG16_INOUTPORTREG;
1657static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1658static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1659static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1660static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1661static const i386_operand_type anydisp
1662 = OPERAND_TYPE_ANYDISP;
40fb9820 1663static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1664static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1665static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1666static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1667static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1668static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1669static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1670static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1671static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1672static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1673static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1674static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1675static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1676static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1677
1678enum operand_type
1679{
1680 reg,
40fb9820
L		 1681 imm,
1682 disp,
1683 anymem
1684};
1685
c6fb90c8 1686static INLINE int
40fb9820
L		 1687operand_type_check (i386_operand_type t, enum operand_type c)
1688{
1689 switch (c)
1690 {
1691 case reg:
1692 return (t.bitfield.reg8
1693 || t.bitfield.reg16
1694 || t.bitfield.reg32
1695 || t.bitfield.reg64);
1696
40fb9820
L		 1697 case imm:
1698 return (t.bitfield.imm8
1699 || t.bitfield.imm8s
1700 || t.bitfield.imm16
1701 || t.bitfield.imm32
1702 || t.bitfield.imm32s
1703 || t.bitfield.imm64);
1704
1705 case disp:
1706 return (t.bitfield.disp8
1707 || t.bitfield.disp16
1708 || t.bitfield.disp32
1709 || t.bitfield.disp32s
1710 || t.bitfield.disp64);
1711
1712 case anymem:
1713 return (t.bitfield.disp8
1714 || t.bitfield.disp16
1715 || t.bitfield.disp32
1716 || t.bitfield.disp32s
1717 || t.bitfield.disp64
1718 || t.bitfield.baseindex);
1719
1720 default:
1721 abort ();
1722 }
2cfe26b6
AM		 1723
1724 return 0;
40fb9820
L		 1725}
1726
5c07affc
L		 1727/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1728 operand J for instruction template T. */
1729
1730static INLINE int
d3ce72d0 1731match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1732{
1733 return !((i.types[j].bitfield.byte
1734 && !t->operand_types[j].bitfield.byte)
1735 || (i.types[j].bitfield.word
1736 && !t->operand_types[j].bitfield.word)
1737 || (i.types[j].bitfield.dword
1738 && !t->operand_types[j].bitfield.dword)
1739 || (i.types[j].bitfield.qword
1740 && !t->operand_types[j].bitfield.qword));
1741}
1742
1743/* Return 1 if there is no conflict in any size on operand J for
1744 instruction template T. */
1745
1746static INLINE int
d3ce72d0 1747match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1748{
1749 return (match_reg_size (t, j)
1750 && !((i.types[j].bitfield.unspecified
af508cb9 1751 && !i.broadcast
5c07affc
L		 1752 && !t->operand_types[j].bitfield.unspecified)
1753 || (i.types[j].bitfield.fword
1754 && !t->operand_types[j].bitfield.fword)
1755 || (i.types[j].bitfield.tbyte
1756 && !t->operand_types[j].bitfield.tbyte)
1757 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1758 && !t->operand_types[j].bitfield.xmmword)
1759 || (i.types[j].bitfield.ymmword
43234a1e
L		 1760 && !t->operand_types[j].bitfield.ymmword)
1761 || (i.types[j].bitfield.zmmword
1762 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1763}
1764
1765/* Return 1 if there is no size conflict on any operands for
1766 instruction template T. */
1767
1768static INLINE int
d3ce72d0 1769operand_size_match (const insn_template *t)
5c07affc
L		 1770{
1771 unsigned int j;
1772 int match = 1;
1773
1774 /* Don't check jump instructions. */
1775 if (t->opcode_modifier.jump
1776 || t->opcode_modifier.jumpbyte
1777 || t->opcode_modifier.jumpdword
1778 || t->opcode_modifier.jumpintersegment)
1779 return match;
1780
1781 /* Check memory and accumulator operand size. */
1782 for (j = 0; j < i.operands; j++)
1783 {
1784 if (t->operand_types[j].bitfield.anysize)
1785 continue;
1786
1787 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1788 {
1789 match = 0;
1790 break;
1791 }
1792
1793 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1794 {
1795 match = 0;
1796 break;
1797 }
1798 }
1799
891edac4 1800 if (match)
5c07affc 1801 return match;
891edac4
L		 1802 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1803 {
1804mismatch:
86e026a4 1805 i.error = operand_size_mismatch;
891edac4
L		 1806 return 0;
1807 }
5c07affc
L		 1808
1809 /* Check reverse. */
9c2799c2 1810 gas_assert (i.operands == 2);
5c07affc
L		 1811
1812 match = 1;
1813 for (j = 0; j < 2; j++)
1814 {
1815 if (t->operand_types[j].bitfield.acc
1816 && !match_reg_size (t, j ? 0 : 1))
891edac4 1817 goto mismatch;
5c07affc
L		 1818
1819 if (i.types[j].bitfield.mem
1820 && !match_mem_size (t, j ? 0 : 1))
891edac4 1821 goto mismatch;
5c07affc
L		 1822 }
1823
1824 return match;
1825}
1826
c6fb90c8 1827static INLINE int
40fb9820
L		 1828operand_type_match (i386_operand_type overlap,
1829 i386_operand_type given)
1830{
1831 i386_operand_type temp = overlap;
1832
1833 temp.bitfield.jumpabsolute = 0;
7d5e4556 1834 temp.bitfield.unspecified = 0;
5c07affc
L		 1835 temp.bitfield.byte = 0;
1836 temp.bitfield.word = 0;
1837 temp.bitfield.dword = 0;
1838 temp.bitfield.fword = 0;
1839 temp.bitfield.qword = 0;
1840 temp.bitfield.tbyte = 0;
1841 temp.bitfield.xmmword = 0;
c0f3af97 1842 temp.bitfield.ymmword = 0;
43234a1e 1843 temp.bitfield.zmmword = 0;
0dfbf9d7 1844 if (operand_type_all_zero (&temp))
891edac4 1845 goto mismatch;
40fb9820 1846
891edac4
L		 1847 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1848 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1849 return 1;
1850
1851mismatch:
a65babc9 1852 i.error = operand_type_mismatch;
891edac4 1853 return 0;
40fb9820
L		 1854}
1855
7d5e4556 1856/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1857 unless the expected operand type register overlap is null.
1858 Note that Acc in a template matches every size of reg. */
1859
c6fb90c8 1860static INLINE int
40fb9820
L		 1861operand_type_register_match (i386_operand_type m0,
1862 i386_operand_type g0,
1863 i386_operand_type t0,
1864 i386_operand_type m1,
1865 i386_operand_type g1,
1866 i386_operand_type t1)
1867{
1868 if (!operand_type_check (g0, reg))
1869 return 1;
1870
1871 if (!operand_type_check (g1, reg))
1872 return 1;
1873
1874 if (g0.bitfield.reg8 == g1.bitfield.reg8
1875 && g0.bitfield.reg16 == g1.bitfield.reg16
1876 && g0.bitfield.reg32 == g1.bitfield.reg32
1877 && g0.bitfield.reg64 == g1.bitfield.reg64)
1878 return 1;
1879
1880 if (m0.bitfield.acc)
1881 {
1882 t0.bitfield.reg8 = 1;
1883 t0.bitfield.reg16 = 1;
1884 t0.bitfield.reg32 = 1;
1885 t0.bitfield.reg64 = 1;
1886 }
1887
1888 if (m1.bitfield.acc)
1889 {
1890 t1.bitfield.reg8 = 1;
1891 t1.bitfield.reg16 = 1;
1892 t1.bitfield.reg32 = 1;
1893 t1.bitfield.reg64 = 1;
1894 }
1895
891edac4
L		 1896 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1897 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1898 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1899 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1900 return 1;
1901
a65babc9 1902 i.error = register_type_mismatch;
891edac4
L		 1903
1904 return 0;
40fb9820
L		 1905}
1906
4c692bc7
JB		 1907static INLINE unsigned int
1908register_number (const reg_entry *r)
1909{
1910 unsigned int nr = r->reg_num;
1911
1912 if (r->reg_flags & RegRex)
1913 nr += 8;
1914
200cbe0f
L		 1915 if (r->reg_flags & RegVRex)
1916 nr += 16;
1917
4c692bc7
JB		 1918 return nr;
1919}
1920
252b5132 1921static INLINE unsigned int
40fb9820 1922mode_from_disp_size (i386_operand_type t)
252b5132 1923{
43234a1e 1924 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1925 return 1;
1926 else if (t.bitfield.disp16
1927 || t.bitfield.disp32
1928 || t.bitfield.disp32s)
1929 return 2;
1930 else
1931 return 0;
252b5132
RH		 1932}
1933
1934static INLINE int
65879393 1935fits_in_signed_byte (addressT num)
252b5132 1936{
65879393 1937 return num + 0x80 <= 0xff;
47926f60 1938}
252b5132
RH		 1939
1940static INLINE int
65879393 1941fits_in_unsigned_byte (addressT num)
252b5132 1942{
65879393 1943 return num <= 0xff;
47926f60 1944}
252b5132
RH		 1945
1946static INLINE int
65879393 1947fits_in_unsigned_word (addressT num)
252b5132 1948{
65879393 1949 return num <= 0xffff;
47926f60 1950}
252b5132
RH		 1951
1952static INLINE int
65879393 1953fits_in_signed_word (addressT num)
252b5132 1954{
65879393 1955 return num + 0x8000 <= 0xffff;
47926f60 1956}
2a962e6d 1957
3e73aa7c 1958static INLINE int
65879393 1959fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1960{
1961#ifndef BFD64
1962 return 1;
1963#else
65879393 1964 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1965#endif
1966} /* fits_in_signed_long() */
2a962e6d 1967
3e73aa7c 1968static INLINE int
65879393 1969fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1970{
1971#ifndef BFD64
1972 return 1;
1973#else
65879393 1974 return num <= 0xffffffff;
3e73aa7c
JH		 1975#endif
1976} /* fits_in_unsigned_long() */
252b5132 1977
43234a1e
L		 1978static INLINE int
1979fits_in_vec_disp8 (offsetT num)
1980{
1981 int shift = i.memshift;
1982 unsigned int mask;
1983
1984 if (shift == -1)
1985 abort ();
1986
1987 mask = (1 << shift) - 1;
1988
1989 /* Return 0 if NUM isn't properly aligned. */
1990 if ((num & mask))
1991 return 0;
1992
1993 /* Check if NUM will fit in 8bit after shift. */
1994 return fits_in_signed_byte (num >> shift);
1995}
1996
a683cc34
SP		 1997static INLINE int
1998fits_in_imm4 (offsetT num)
1999{
2000 return (num & 0xf) == num;
2001}
2002
40fb9820 2003static i386_operand_type
e3bb37b5 2004smallest_imm_type (offsetT num)
252b5132 2005{
40fb9820 2006 i386_operand_type t;
7ab9ffdd 2007
0dfbf9d7 2008 operand_type_set (&t, 0);
40fb9820
L		 2009 t.bitfield.imm64 = 1;
2010
2011 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2012 {
2013 /* This code is disabled on the 486 because all the Imm1 forms
2014 in the opcode table are slower on the i486. They're the
2015 versions with the implicitly specified single-position
2016 displacement, which has another syntax if you really want to
2017 use that form. */
40fb9820
L		 2018 t.bitfield.imm1 = 1;
2019 t.bitfield.imm8 = 1;
2020 t.bitfield.imm8s = 1;
2021 t.bitfield.imm16 = 1;
2022 t.bitfield.imm32 = 1;
2023 t.bitfield.imm32s = 1;
2024 }
2025 else if (fits_in_signed_byte (num))
2026 {
2027 t.bitfield.imm8 = 1;
2028 t.bitfield.imm8s = 1;
2029 t.bitfield.imm16 = 1;
2030 t.bitfield.imm32 = 1;
2031 t.bitfield.imm32s = 1;
2032 }
2033 else if (fits_in_unsigned_byte (num))
2034 {
2035 t.bitfield.imm8 = 1;
2036 t.bitfield.imm16 = 1;
2037 t.bitfield.imm32 = 1;
2038 t.bitfield.imm32s = 1;
2039 }
2040 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2041 {
2042 t.bitfield.imm16 = 1;
2043 t.bitfield.imm32 = 1;
2044 t.bitfield.imm32s = 1;
2045 }
2046 else if (fits_in_signed_long (num))
2047 {
2048 t.bitfield.imm32 = 1;
2049 t.bitfield.imm32s = 1;
2050 }
2051 else if (fits_in_unsigned_long (num))
2052 t.bitfield.imm32 = 1;
2053
2054 return t;
47926f60 2055}
252b5132 2056
847f7ad4 2057static offsetT
e3bb37b5 2058offset_in_range (offsetT val, int size)
847f7ad4 2059{
508866be 2060 addressT mask;
ba2adb93 2061
847f7ad4
AM		 2062 switch (size)
2063 {
508866be
L		 2064 case 1: mask = ((addressT) 1 << 8) - 1; break;
2065 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2066 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2067#ifdef BFD64
2068 case 8: mask = ((addressT) 2 << 63) - 1; break;
2069#endif
47926f60 2070 default: abort ();
847f7ad4
AM		 2071 }
2072
9de868bf
L		 2073#ifdef BFD64
2074 /* If BFD64, sign extend val for 32bit address mode. */
2075 if (flag_code != CODE_64BIT
2076 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2077 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2078 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2079#endif
ba2adb93 2080
47926f60 2081 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2082 {
2083 char buf1[40], buf2[40];
2084
2085 sprint_value (buf1, val);
2086 sprint_value (buf2, val & mask);
2087 as_warn (_("%s shortened to %s"), buf1, buf2);
2088 }
2089 return val & mask;
2090}
2091
c32fa91d
L		 2092enum PREFIX_GROUP
2093{
2094 PREFIX_EXIST = 0,
2095 PREFIX_LOCK,
2096 PREFIX_REP,
2097 PREFIX_OTHER
2098};
2099
2100/* Returns
2101 a. PREFIX_EXIST if attempting to add a prefix where one from the
2102 same class already exists.
2103 b. PREFIX_LOCK if lock prefix is added.
2104 c. PREFIX_REP if rep/repne prefix is added.
2105 d. PREFIX_OTHER if other prefix is added.
2106 */
2107
2108static enum PREFIX_GROUP
e3bb37b5 2109add_prefix (unsigned int prefix)
252b5132 2110{
c32fa91d 2111 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2112 unsigned int q;
252b5132 2113
29b0f896
AM		 2114 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2115 && flag_code == CODE_64BIT)
b1905489 2116 {
161a04f6
L		 2117 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2118 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2119 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2120 ret = PREFIX_EXIST;
b1905489
JB		 2121 q = REX_PREFIX;
2122 }
3e73aa7c 2123 else
b1905489
JB		 2124 {
2125 switch (prefix)
2126 {
2127 default:
2128 abort ();
2129
2130 case CS_PREFIX_OPCODE:
2131 case DS_PREFIX_OPCODE:
2132 case ES_PREFIX_OPCODE:
2133 case FS_PREFIX_OPCODE:
2134 case GS_PREFIX_OPCODE:
2135 case SS_PREFIX_OPCODE:
2136 q = SEG_PREFIX;
2137 break;
2138
2139 case REPNE_PREFIX_OPCODE:
2140 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2141 q = REP_PREFIX;
2142 ret = PREFIX_REP;
2143 break;
2144
b1905489 2145 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2146 q = LOCK_PREFIX;
2147 ret = PREFIX_LOCK;
b1905489
JB		 2148 break;
2149
2150 case FWAIT_OPCODE:
2151 q = WAIT_PREFIX;
2152 break;
2153
2154 case ADDR_PREFIX_OPCODE:
2155 q = ADDR_PREFIX;
2156 break;
2157
2158 case DATA_PREFIX_OPCODE:
2159 q = DATA_PREFIX;
2160 break;
2161 }
2162 if (i.prefix[q] != 0)
c32fa91d 2163 ret = PREFIX_EXIST;
b1905489 2164 }
252b5132 2165
b1905489 2166 if (ret)
252b5132 2167 {
b1905489
JB		 2168 if (!i.prefix[q])
2169 ++i.prefixes;
2170 i.prefix[q] |= prefix;
252b5132 2171 }
b1905489
JB		 2172 else
2173 as_bad (_("same type of prefix used twice"));
252b5132 2174
252b5132
RH		 2175 return ret;
2176}
2177
2178static void
78f12dd3 2179update_code_flag (int value, int check)
eecb386c 2180{
78f12dd3
L		 2181 PRINTF_LIKE ((*as_error));
2182
1e9cc1c2 2183 flag_code = (enum flag_code) value;
40fb9820
L		 2184 if (flag_code == CODE_64BIT)
2185 {
2186 cpu_arch_flags.bitfield.cpu64 = 1;
2187 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2188 }
2189 else
2190 {
2191 cpu_arch_flags.bitfield.cpu64 = 0;
2192 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2193 }
2194 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2195 {
78f12dd3
L		 2196 if (check)
2197 as_error = as_fatal;
2198 else
2199 as_error = as_bad;
2200 (*as_error) (_("64bit mode not supported on `%s'."),
2201 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2202 }
40fb9820 2203 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2204 {
78f12dd3
L		 2205 if (check)
2206 as_error = as_fatal;
2207 else
2208 as_error = as_bad;
2209 (*as_error) (_("32bit mode not supported on `%s'."),
2210 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2211 }
eecb386c
AM		 2212 stackop_size = '\0';
2213}
2214
78f12dd3
L		 2215static void
2216set_code_flag (int value)
2217{
2218 update_code_flag (value, 0);
2219}
2220
eecb386c 2221static void
e3bb37b5 2222set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2223{
1e9cc1c2 2224 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2225 if (flag_code != CODE_16BIT)
2226 abort ();
2227 cpu_arch_flags.bitfield.cpu64 = 0;
2228 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2229 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2230}
2231
2232static void
e3bb37b5 2233set_intel_syntax (int syntax_flag)
252b5132
RH		 2234{
2235 /* Find out if register prefixing is specified. */
2236 int ask_naked_reg = 0;
2237
2238 SKIP_WHITESPACE ();
29b0f896 2239 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2240 {
d02603dc
NC		 2241 char *string;
2242 int e = get_symbol_name (&string);
252b5132 2243
47926f60 2244 if (strcmp (string, "prefix") == 0)
252b5132 2245 ask_naked_reg = 1;
47926f60 2246 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2247 ask_naked_reg = -1;
2248 else
d0b47220 2249 as_bad (_("bad argument to syntax directive."));
d02603dc 2250 (void) restore_line_pointer (e);
252b5132
RH		 2251 }
2252 demand_empty_rest_of_line ();
c3332e24 2253
252b5132
RH		 2254 intel_syntax = syntax_flag;
2255
2256 if (ask_naked_reg == 0)
f86103b7
AM		 2257 allow_naked_reg = (intel_syntax
2258 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2259 else
2260 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2261
ee86248c 2262 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2263
e4a3b5a4 2264 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2265 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2266 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2267}
2268
1efbbeb4
L		 2269static void
2270set_intel_mnemonic (int mnemonic_flag)
2271{
e1d4d893 2272 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2273}
2274
db51cc60
L		 2275static void
2276set_allow_index_reg (int flag)
2277{
2278 allow_index_reg = flag;
2279}
2280
cb19c032 2281static void
7bab8ab5 2282set_check (int what)
cb19c032 2283{
7bab8ab5
JB		 2284 enum check_kind *kind;
2285 const char *str;
2286
2287 if (what)
2288 {
2289 kind = &operand_check;
2290 str = "operand";
2291 }
2292 else
2293 {
2294 kind = &sse_check;
2295 str = "sse";
2296 }
2297
cb19c032
L		 2298 SKIP_WHITESPACE ();
2299
2300 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2301 {
d02603dc
NC		 2302 char *string;
2303 int e = get_symbol_name (&string);
cb19c032
L		 2304
2305 if (strcmp (string, "none") == 0)
7bab8ab5 2306 *kind = check_none;
cb19c032 2307 else if (strcmp (string, "warning") == 0)
7bab8ab5 2308 *kind = check_warning;
cb19c032 2309 else if (strcmp (string, "error") == 0)
7bab8ab5 2310 *kind = check_error;
cb19c032 2311 else
7bab8ab5 2312 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2313 (void) restore_line_pointer (e);
cb19c032
L		 2314 }
2315 else
7bab8ab5 2316 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2317
2318 demand_empty_rest_of_line ();
2319}
2320
8a9036a4
L		 2321static void
2322check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2323 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2324{
2325#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2326 static const char *arch;
2327
2328 /* Intel LIOM is only supported on ELF. */
2329 if (!IS_ELF)
2330 return;
2331
2332 if (!arch)
2333 {
2334 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2335 use default_arch. */
2336 arch = cpu_arch_name;
2337 if (!arch)
2338 arch = default_arch;
2339 }
2340
81486035
L		 2341 /* If we are targeting Intel MCU, we must enable it. */
2342 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2343 || new_flag.bitfield.cpuiamcu)
2344 return;
2345
3632d14b 2346 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2347 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2348 || new_flag.bitfield.cpul1om)
8a9036a4 2349 return;
76ba9986 2350
7a9068fe
L		 2351 /* If we are targeting Intel K1OM, we must enable it. */
2352 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2353 || new_flag.bitfield.cpuk1om)
2354 return;
2355
8a9036a4
L		 2356 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2357#endif
2358}
2359
e413e4e9 2360static void
e3bb37b5 2361set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2362{
47926f60 2363 SKIP_WHITESPACE ();
e413e4e9 2364
29b0f896 2365 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2366 {
d02603dc
NC		 2367 char *string;
2368 int e = get_symbol_name (&string);
91d6fa6a 2369 unsigned int j;
40fb9820 2370 i386_cpu_flags flags;
e413e4e9 2371
91d6fa6a 2372 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2373 {
91d6fa6a 2374 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2375 {
91d6fa6a 2376 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2377
5c6af06e
JB		 2378 if (*string != '.')
2379 {
91d6fa6a 2380 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2381 cpu_sub_arch_name = NULL;
91d6fa6a 2382 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2383 if (flag_code == CODE_64BIT)
2384 {
2385 cpu_arch_flags.bitfield.cpu64 = 1;
2386 cpu_arch_flags.bitfield.cpuno64 = 0;
2387 }
2388 else
2389 {
2390 cpu_arch_flags.bitfield.cpu64 = 0;
2391 cpu_arch_flags.bitfield.cpuno64 = 1;
2392 }
91d6fa6a
NC		 2393 cpu_arch_isa = cpu_arch[j].type;
2394 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2395 if (!cpu_arch_tune_set)
2396 {
2397 cpu_arch_tune = cpu_arch_isa;
2398 cpu_arch_tune_flags = cpu_arch_isa_flags;
2399 }
5c6af06e
JB		 2400 break;
2401 }
40fb9820 2402
293f5f65
L		 2403 flags = cpu_flags_or (cpu_arch_flags,
2404 cpu_arch[j].flags);
81486035
L		 2405
2406 if (!valid_iamcu_cpu_flags (&flags))
2407 as_fatal (_("`%s' isn't valid for Intel MCU"),
2408 cpu_arch[j].name);
2409 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2410 {
6305a203
L		 2411 if (cpu_sub_arch_name)
2412 {
2413 char *name = cpu_sub_arch_name;
2414 cpu_sub_arch_name = concat (name,
91d6fa6a 2415 cpu_arch[j].name,
1bf57e9f 2416 (const char *) NULL);
6305a203
L		 2417 free (name);
2418 }
2419 else
91d6fa6a 2420 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2421 cpu_arch_flags = flags;
a586129e 2422 cpu_arch_isa_flags = flags;
5c6af06e 2423 }
d02603dc 2424 (void) restore_line_pointer (e);
5c6af06e
JB		 2425 demand_empty_rest_of_line ();
2426 return;
e413e4e9
AM		 2427 }
2428 }
293f5f65
L		 2429
2430 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2431 {
2432 /* Disable an ISA entension. */
2433 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2434 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2435 {
2436 flags = cpu_flags_and_not (cpu_arch_flags,
2437 cpu_noarch[j].flags);
2438 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2439 {
2440 if (cpu_sub_arch_name)
2441 {
2442 char *name = cpu_sub_arch_name;
2443 cpu_sub_arch_name = concat (name, string,
2444 (const char *) NULL);
2445 free (name);
2446 }
2447 else
2448 cpu_sub_arch_name = xstrdup (string);
2449 cpu_arch_flags = flags;
2450 cpu_arch_isa_flags = flags;
2451 }
2452 (void) restore_line_pointer (e);
2453 demand_empty_rest_of_line ();
2454 return;
2455 }
2456
2457 j = ARRAY_SIZE (cpu_arch);
2458 }
2459
91d6fa6a 2460 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2461 as_bad (_("no such architecture: `%s'"), string);
2462
2463 *input_line_pointer = e;
2464 }
2465 else
2466 as_bad (_("missing cpu architecture"));
2467
fddf5b5b
AM		 2468 no_cond_jump_promotion = 0;
2469 if (*input_line_pointer == ','
29b0f896 2470 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2471 {
d02603dc
NC		 2472 char *string;
2473 char e;
2474
2475 ++input_line_pointer;
2476 e = get_symbol_name (&string);
fddf5b5b
AM		 2477
2478 if (strcmp (string, "nojumps") == 0)
2479 no_cond_jump_promotion = 1;
2480 else if (strcmp (string, "jumps") == 0)
2481 ;
2482 else
2483 as_bad (_("no such architecture modifier: `%s'"), string);
2484
d02603dc 2485 (void) restore_line_pointer (e);
fddf5b5b
AM		 2486 }
2487
e413e4e9
AM		 2488 demand_empty_rest_of_line ();
2489}
2490
8a9036a4
L		 2491enum bfd_architecture
2492i386_arch (void)
2493{
3632d14b 2494 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2495 {
2496 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2497 || flag_code != CODE_64BIT)
2498 as_fatal (_("Intel L1OM is 64bit ELF only"));
2499 return bfd_arch_l1om;
2500 }
7a9068fe
L		 2501 else if (cpu_arch_isa == PROCESSOR_K1OM)
2502 {
2503 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2504 || flag_code != CODE_64BIT)
2505 as_fatal (_("Intel K1OM is 64bit ELF only"));
2506 return bfd_arch_k1om;
2507 }
81486035
L		 2508 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2509 {
2510 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2511 || flag_code == CODE_64BIT)
2512 as_fatal (_("Intel MCU is 32bit ELF only"));
2513 return bfd_arch_iamcu;
2514 }
8a9036a4
L		 2515 else
2516 return bfd_arch_i386;
2517}
2518
b9d79e03 2519unsigned long
7016a5d5 2520i386_mach (void)
b9d79e03 2521{
351f65ca 2522 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2523 {
3632d14b 2524 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2525 {
351f65ca
L		 2526 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2527 || default_arch[6] != '\0')
8a9036a4
L		 2528 as_fatal (_("Intel L1OM is 64bit ELF only"));
2529 return bfd_mach_l1om;
2530 }
7a9068fe
L		 2531 else if (cpu_arch_isa == PROCESSOR_K1OM)
2532 {
2533 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2534 || default_arch[6] != '\0')
2535 as_fatal (_("Intel K1OM is 64bit ELF only"));
2536 return bfd_mach_k1om;
2537 }
351f65ca 2538 else if (default_arch[6] == '\0')
8a9036a4 2539 return bfd_mach_x86_64;
351f65ca
L		 2540 else
2541 return bfd_mach_x64_32;
8a9036a4 2542 }
5197d474
L		 2543 else if (!strcmp (default_arch, "i386")
2544 || !strcmp (default_arch, "iamcu"))
81486035
L		 2545 {
2546 if (cpu_arch_isa == PROCESSOR_IAMCU)
2547 {
2548 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2549 as_fatal (_("Intel MCU is 32bit ELF only"));
2550 return bfd_mach_i386_iamcu;
2551 }
2552 else
2553 return bfd_mach_i386_i386;
2554 }
b9d79e03 2555 else
2b5d6a91 2556 as_fatal (_("unknown architecture"));
b9d79e03 2557}
b9d79e03 2558\f
252b5132 2559void
7016a5d5 2560md_begin (void)
252b5132
RH		 2561{
2562 const char *hash_err;
2563
47926f60 2564 /* Initialize op_hash hash table. */
252b5132
RH		 2565 op_hash = hash_new ();
2566
2567 {
d3ce72d0 2568 const insn_template *optab;
29b0f896 2569 templates *core_optab;
252b5132 2570
47926f60
KH		 2571 /* Setup for loop. */
2572 optab = i386_optab;
add39d23 2573 core_optab = XNEW (templates);
252b5132
RH		 2574 core_optab->start = optab;
2575
2576 while (1)
2577 {
2578 ++optab;
2579 if (optab->name == NULL
2580 || strcmp (optab->name, (optab - 1)->name) != 0)
2581 {
2582 /* different name --> ship out current template list;
47926f60 2583 add to hash table; & begin anew. */
252b5132
RH		 2584 core_optab->end = optab;
2585 hash_err = hash_insert (op_hash,
2586 (optab - 1)->name,
5a49b8ac 2587 (void *) core_optab);
252b5132
RH		 2588 if (hash_err)
2589 {
b37df7c4 2590 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2591 (optab - 1)->name,
2592 hash_err);
2593 }
2594 if (optab->name == NULL)
2595 break;
add39d23 2596 core_optab = XNEW (templates);
252b5132
RH		 2597 core_optab->start = optab;
2598 }
2599 }
2600 }
2601
47926f60 2602 /* Initialize reg_hash hash table. */
252b5132
RH		 2603 reg_hash = hash_new ();
2604 {
29b0f896 2605 const reg_entry *regtab;
c3fe08fa 2606 unsigned int regtab_size = i386_regtab_size;
252b5132 2607
c3fe08fa 2608 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2609 {
5a49b8ac 2610 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2611 if (hash_err)
b37df7c4 2612 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2613 regtab->reg_name,
2614 hash_err);
252b5132
RH		 2615 }
2616 }
2617
47926f60 2618 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2619 {
29b0f896
AM		 2620 int c;
2621 char *p;
252b5132
RH		 2622
2623 for (c = 0; c < 256; c++)
2624 {
3882b010 2625 if (ISDIGIT (c))
252b5132
RH		 2626 {
2627 digit_chars[c] = c;
2628 mnemonic_chars[c] = c;
2629 register_chars[c] = c;
2630 operand_chars[c] = c;
2631 }
3882b010 2632 else if (ISLOWER (c))
252b5132
RH		 2633 {
2634 mnemonic_chars[c] = c;
2635 register_chars[c] = c;
2636 operand_chars[c] = c;
2637 }
3882b010 2638 else if (ISUPPER (c))
252b5132 2639 {
3882b010 2640 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2641 register_chars[c] = mnemonic_chars[c];
2642 operand_chars[c] = c;
2643 }
43234a1e
L		 2644 else if (c == '{' || c == '}')
2645 operand_chars[c] = c;
252b5132 2646
3882b010 2647 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2648 identifier_chars[c] = c;
2649 else if (c >= 128)
2650 {
2651 identifier_chars[c] = c;
2652 operand_chars[c] = c;
2653 }
2654 }
2655
2656#ifdef LEX_AT
2657 identifier_chars['@'] = '@';
32137342
NC		 2658#endif
2659#ifdef LEX_QM
2660 identifier_chars['?'] = '?';
2661 operand_chars['?'] = '?';
252b5132 2662#endif
252b5132 2663 digit_chars['-'] = '-';
c0f3af97 2664 mnemonic_chars['_'] = '_';
791fe849 2665 mnemonic_chars['-'] = '-';
0003779b 2666 mnemonic_chars['.'] = '.';
252b5132
RH		 2667 identifier_chars['_'] = '_';
2668 identifier_chars['.'] = '.';
2669
2670 for (p = operand_special_chars; *p != '\0'; p++)
2671 operand_chars[(unsigned char) *p] = *p;
2672 }
2673
a4447b93
RH		 2674 if (flag_code == CODE_64BIT)
2675 {
ca19b261
KT		 2676#if defined (OBJ_COFF) && defined (TE_PE)
2677 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2678 ? 32 : 16);
2679#else
a4447b93 2680 x86_dwarf2_return_column = 16;
ca19b261 2681#endif
61ff971f 2682 x86_cie_data_alignment = -8;
a4447b93
RH		 2683 }
2684 else
2685 {
2686 x86_dwarf2_return_column = 8;
2687 x86_cie_data_alignment = -4;
2688 }
252b5132
RH		 2689}
2690
2691void
e3bb37b5 2692i386_print_statistics (FILE *file)
252b5132
RH		 2693{
2694 hash_print_statistics (file, "i386 opcode", op_hash);
2695 hash_print_statistics (file, "i386 register", reg_hash);
2696}
2697\f
252b5132
RH		 2698#ifdef DEBUG386
2699
ce8a8b2f 2700/* Debugging routines for md_assemble. */
d3ce72d0 2701static void pte (insn_template *);
40fb9820 2702static void pt (i386_operand_type);
e3bb37b5
L		 2703static void pe (expressionS *);
2704static void ps (symbolS *);
252b5132
RH		 2705
2706static void
e3bb37b5 2707pi (char *line, i386_insn *x)
252b5132 2708{
09137c09 2709 unsigned int j;
252b5132
RH		 2710
2711 fprintf (stdout, "%s: template ", line);
2712 pte (&x->tm);
09f131f2
JH		 2713 fprintf (stdout, " address: base %s index %s scale %x\n",
2714 x->base_reg ? x->base_reg->reg_name : "none",
2715 x->index_reg ? x->index_reg->reg_name : "none",
2716 x->log2_scale_factor);
2717 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2718 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2719 fprintf (stdout, " sib: base %x index %x scale %x\n",
2720 x->sib.base, x->sib.index, x->sib.scale);
2721 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2722 (x->rex & REX_W) != 0,
2723 (x->rex & REX_R) != 0,
2724 (x->rex & REX_X) != 0,
2725 (x->rex & REX_B) != 0);
09137c09 2726 for (j = 0; j < x->operands; j++)
252b5132 2727 {
09137c09
SP		 2728 fprintf (stdout, " #%d: ", j + 1);
2729 pt (x->types[j]);
252b5132 2730 fprintf (stdout, "\n");
09137c09
SP		 2731 if (x->types[j].bitfield.reg8
2732 || x->types[j].bitfield.reg16
2733 || x->types[j].bitfield.reg32
2734 || x->types[j].bitfield.reg64
2735 || x->types[j].bitfield.regmmx
2736 || x->types[j].bitfield.regxmm
2737 || x->types[j].bitfield.regymm
43234a1e 2738 || x->types[j].bitfield.regzmm
09137c09
SP		 2739 || x->types[j].bitfield.sreg2
2740 || x->types[j].bitfield.sreg3
2741 || x->types[j].bitfield.control
2742 || x->types[j].bitfield.debug
2743 || x->types[j].bitfield.test)
2744 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2745 if (operand_type_check (x->types[j], imm))
2746 pe (x->op[j].imms);
2747 if (operand_type_check (x->types[j], disp))
2748 pe (x->op[j].disps);
252b5132
RH		 2749 }
2750}
2751
2752static void
d3ce72d0 2753pte (insn_template *t)
252b5132 2754{
09137c09 2755 unsigned int j;
252b5132 2756 fprintf (stdout, " %d operands ", t->operands);
47926f60 2757 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2758 if (t->extension_opcode != None)
2759 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2760 if (t->opcode_modifier.d)
252b5132 2761 fprintf (stdout, "D");
40fb9820 2762 if (t->opcode_modifier.w)
252b5132
RH		 2763 fprintf (stdout, "W");
2764 fprintf (stdout, "\n");
09137c09 2765 for (j = 0; j < t->operands; j++)
252b5132 2766 {
09137c09
SP		 2767 fprintf (stdout, " #%d type ", j + 1);
2768 pt (t->operand_types[j]);
252b5132
RH		 2769 fprintf (stdout, "\n");
2770 }
2771}
2772
2773static void
e3bb37b5 2774pe (expressionS *e)
252b5132 2775{
24eab124 2776 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2777 fprintf (stdout, " add_number %ld (%lx)\n",
2778 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2779 if (e->X_add_symbol)
2780 {
2781 fprintf (stdout, " add_symbol ");
2782 ps (e->X_add_symbol);
2783 fprintf (stdout, "\n");
2784 }
2785 if (e->X_op_symbol)
2786 {
2787 fprintf (stdout, " op_symbol ");
2788 ps (e->X_op_symbol);
2789 fprintf (stdout, "\n");
2790 }
2791}
2792
2793static void
e3bb37b5 2794ps (symbolS *s)
252b5132
RH		 2795{
2796 fprintf (stdout, "%s type %s%s",
2797 S_GET_NAME (s),
2798 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2799 segment_name (S_GET_SEGMENT (s)));
2800}
2801
7b81dfbb 2802static struct type_name
252b5132 2803 {
40fb9820
L		 2804 i386_operand_type mask;
2805 const char *name;
252b5132 2806 }
7b81dfbb 2807const type_names[] =
252b5132 2808{
40fb9820
L		 2809 { OPERAND_TYPE_REG8, "r8" },
2810 { OPERAND_TYPE_REG16, "r16" },
2811 { OPERAND_TYPE_REG32, "r32" },
2812 { OPERAND_TYPE_REG64, "r64" },
2813 { OPERAND_TYPE_IMM8, "i8" },
2814 { OPERAND_TYPE_IMM8, "i8s" },
2815 { OPERAND_TYPE_IMM16, "i16" },
2816 { OPERAND_TYPE_IMM32, "i32" },
2817 { OPERAND_TYPE_IMM32S, "i32s" },
2818 { OPERAND_TYPE_IMM64, "i64" },
2819 { OPERAND_TYPE_IMM1, "i1" },
2820 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2821 { OPERAND_TYPE_DISP8, "d8" },
2822 { OPERAND_TYPE_DISP16, "d16" },
2823 { OPERAND_TYPE_DISP32, "d32" },
2824 { OPERAND_TYPE_DISP32S, "d32s" },
2825 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2826 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2827 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2828 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2829 { OPERAND_TYPE_CONTROL, "control reg" },
2830 { OPERAND_TYPE_TEST, "test reg" },
2831 { OPERAND_TYPE_DEBUG, "debug reg" },
2832 { OPERAND_TYPE_FLOATREG, "FReg" },
2833 { OPERAND_TYPE_FLOATACC, "FAcc" },
2834 { OPERAND_TYPE_SREG2, "SReg2" },
2835 { OPERAND_TYPE_SREG3, "SReg3" },
2836 { OPERAND_TYPE_ACC, "Acc" },
2837 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2838 { OPERAND_TYPE_REGMMX, "rMMX" },
2839 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2840 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2841 { OPERAND_TYPE_REGZMM, "rZMM" },
2842 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2843 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2844};
2845
2846static void
40fb9820 2847pt (i386_operand_type t)
252b5132 2848{
40fb9820 2849 unsigned int j;
c6fb90c8 2850 i386_operand_type a;
252b5132 2851
40fb9820 2852 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2853 {
2854 a = operand_type_and (t, type_names[j].mask);
0349dc08 2855 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2856 fprintf (stdout, "%s, ", type_names[j].name);
2857 }
252b5132
RH		 2858 fflush (stdout);
2859}
2860
2861#endif /* DEBUG386 */
2862\f
252b5132 2863static bfd_reloc_code_real_type
3956db08 2864reloc (unsigned int size,
64e74474
AM		 2865 int pcrel,
2866 int sign,
2867 bfd_reloc_code_real_type other)
252b5132 2868{
47926f60 2869 if (other != NO_RELOC)
3956db08 2870 {
91d6fa6a 2871 reloc_howto_type *rel;
3956db08
JB		 2872
2873 if (size == 8)
2874 switch (other)
2875 {
64e74474
AM		 2876 case BFD_RELOC_X86_64_GOT32:
2877 return BFD_RELOC_X86_64_GOT64;
2878 break;
553d1284
L		 2879 case BFD_RELOC_X86_64_GOTPLT64:
2880 return BFD_RELOC_X86_64_GOTPLT64;
2881 break;
64e74474
AM		 2882 case BFD_RELOC_X86_64_PLTOFF64:
2883 return BFD_RELOC_X86_64_PLTOFF64;
2884 break;
2885 case BFD_RELOC_X86_64_GOTPC32:
2886 other = BFD_RELOC_X86_64_GOTPC64;
2887 break;
2888 case BFD_RELOC_X86_64_GOTPCREL:
2889 other = BFD_RELOC_X86_64_GOTPCREL64;
2890 break;
2891 case BFD_RELOC_X86_64_TPOFF32:
2892 other = BFD_RELOC_X86_64_TPOFF64;
2893 break;
2894 case BFD_RELOC_X86_64_DTPOFF32:
2895 other = BFD_RELOC_X86_64_DTPOFF64;
2896 break;
2897 default:
2898 break;
3956db08 2899 }
e05278af 2900
8ce3d284 2901#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2902 if (other == BFD_RELOC_SIZE32)
2903 {
2904 if (size == 8)
1ab668bf 2905 other = BFD_RELOC_SIZE64;
8fd4256d 2906 if (pcrel)
1ab668bf
AM		 2907 {
2908 as_bad (_("there are no pc-relative size relocations"));
2909 return NO_RELOC;
2910 }
8fd4256d 2911 }
8ce3d284 2912#endif
8fd4256d 2913
e05278af 2914 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2915 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2916 sign = -1;
2917
91d6fa6a
NC		 2918 rel = bfd_reloc_type_lookup (stdoutput, other);
2919 if (!rel)
3956db08 2920 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2921 else if (size != bfd_get_reloc_size (rel))
3956db08 2922 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2923 bfd_get_reloc_size (rel),
3956db08 2924 size);
91d6fa6a 2925 else if (pcrel && !rel->pc_relative)
3956db08 2926 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2927 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2928 && !sign)
91d6fa6a 2929 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2930 && sign > 0))
3956db08
JB		 2931 as_bad (_("relocated field and relocation type differ in signedness"));
2932 else
2933 return other;
2934 return NO_RELOC;
2935 }
252b5132
RH		 2936
2937 if (pcrel)
2938 {
3e73aa7c 2939 if (!sign)
3956db08 2940 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2941 switch (size)
2942 {
2943 case 1: return BFD_RELOC_8_PCREL;
2944 case 2: return BFD_RELOC_16_PCREL;
d258b828 2945 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2946 case 8: return BFD_RELOC_64_PCREL;
252b5132 2947 }
3956db08 2948 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2949 }
2950 else
2951 {
3956db08 2952 if (sign > 0)
e5cb08ac 2953 switch (size)
3e73aa7c
JH		 2954 {
2955 case 4: return BFD_RELOC_X86_64_32S;
2956 }
2957 else
2958 switch (size)
2959 {
2960 case 1: return BFD_RELOC_8;
2961 case 2: return BFD_RELOC_16;
2962 case 4: return BFD_RELOC_32;
2963 case 8: return BFD_RELOC_64;
2964 }
3956db08
JB		 2965 as_bad (_("cannot do %s %u byte relocation"),
2966 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2967 }
2968
0cc9e1d3 2969 return NO_RELOC;
252b5132
RH		 2970}
2971
47926f60
KH		 2972/* Here we decide which fixups can be adjusted to make them relative to
2973 the beginning of the section instead of the symbol. Basically we need
2974 to make sure that the dynamic relocations are done correctly, so in
2975 some cases we force the original symbol to be used. */
2976
252b5132 2977int
e3bb37b5 2978tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2979{
6d249963 2980#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2981 if (!IS_ELF)
31312f95
AM		 2982 return 1;
2983
a161fe53
AM		 2984 /* Don't adjust pc-relative references to merge sections in 64-bit
2985 mode. */
2986 if (use_rela_relocations
2987 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2988 && fixP->fx_pcrel)
252b5132 2989 return 0;
31312f95 2990
8d01d9a9
AJ		 2991 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2992 and changed later by validate_fix. */
2993 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2994 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2995 return 0;
2996
8fd4256d
L		 2997 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2998 for size relocations. */
2999 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3000 || fixP->fx_r_type == BFD_RELOC_SIZE64
3001 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3002 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3003 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3004 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3005 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3006 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3007 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3008 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3009 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3010 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3011 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3012 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3013 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3014 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3015 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3016 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3017 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3018 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3019 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3020 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3021 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3022 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3023 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3024 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3025 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3026 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3027 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3028 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3029 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3030 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3031 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3032 return 0;
31312f95 3033#endif
252b5132
RH		 3034 return 1;
3035}
252b5132 3036
b4cac588 3037static int
e3bb37b5 3038intel_float_operand (const char *mnemonic)
252b5132 3039{
9306ca4a
JB		 3040 /* Note that the value returned is meaningful only for opcodes with (memory)
3041 operands, hence the code here is free to improperly handle opcodes that
3042 have no operands (for better performance and smaller code). */
3043
3044 if (mnemonic[0] != 'f')
3045 return 0; /* non-math */
3046
3047 switch (mnemonic[1])
3048 {
3049 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3050 the fs segment override prefix not currently handled because no
3051 call path can make opcodes without operands get here */
3052 case 'i':
3053 return 2 /* integer op */;
3054 case 'l':
3055 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3056 return 3; /* fldcw/fldenv */
3057 break;
3058 case 'n':
3059 if (mnemonic[2] != 'o' /* fnop */)
3060 return 3; /* non-waiting control op */
3061 break;
3062 case 'r':
3063 if (mnemonic[2] == 's')
3064 return 3; /* frstor/frstpm */
3065 break;
3066 case 's':
3067 if (mnemonic[2] == 'a')
3068 return 3; /* fsave */
3069 if (mnemonic[2] == 't')
3070 {
3071 switch (mnemonic[3])
3072 {
3073 case 'c': /* fstcw */
3074 case 'd': /* fstdw */
3075 case 'e': /* fstenv */
3076 case 's': /* fsts[gw] */
3077 return 3;
3078 }
3079 }
3080 break;
3081 case 'x':
3082 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3083 return 0; /* fxsave/fxrstor are not really math ops */
3084 break;
3085 }
252b5132 3086
9306ca4a 3087 return 1;
252b5132
RH		 3088}
3089
c0f3af97
L		 3090/* Build the VEX prefix. */
3091
3092static void
d3ce72d0 3093build_vex_prefix (const insn_template *t)
c0f3af97
L		 3094{
3095 unsigned int register_specifier;
3096 unsigned int implied_prefix;
3097 unsigned int vector_length;
3098
3099 /* Check register specifier. */
3100 if (i.vex.register_specifier)
43234a1e
L		 3101 {
3102 register_specifier =
3103 ~register_number (i.vex.register_specifier) & 0xf;
3104 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3105 }
c0f3af97
L		 3106 else
3107 register_specifier = 0xf;
3108
fa99fab2
L		 3109 /* Use 2-byte VEX prefix by swappping destination and source
3110 operand. */
3111 if (!i.swap_operand
3112 && i.operands == i.reg_operands
7f399153 3113 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3114 && i.tm.opcode_modifier.s
3115 && i.rex == REX_B)
3116 {
3117 unsigned int xchg = i.operands - 1;
3118 union i386_op temp_op;
3119 i386_operand_type temp_type;
3120
3121 temp_type = i.types[xchg];
3122 i.types[xchg] = i.types[0];
3123 i.types[0] = temp_type;
3124 temp_op = i.op[xchg];
3125 i.op[xchg] = i.op[0];
3126 i.op[0] = temp_op;
3127
9c2799c2 3128 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3129
3130 i.rex = REX_R;
3131 xchg = i.rm.regmem;
3132 i.rm.regmem = i.rm.reg;
3133 i.rm.reg = xchg;
3134
3135 /* Use the next insn. */
3136 i.tm = t[1];
3137 }
3138
539f890d
L		 3139 if (i.tm.opcode_modifier.vex == VEXScalar)
3140 vector_length = avxscalar;
3141 else
3142 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3143
3144 switch ((i.tm.base_opcode >> 8) & 0xff)
3145 {
3146 case 0:
3147 implied_prefix = 0;
3148 break;
3149 case DATA_PREFIX_OPCODE:
3150 implied_prefix = 1;
3151 break;
3152 case REPE_PREFIX_OPCODE:
3153 implied_prefix = 2;
3154 break;
3155 case REPNE_PREFIX_OPCODE:
3156 implied_prefix = 3;
3157 break;
3158 default:
3159 abort ();
3160 }
3161
3162 /* Use 2-byte VEX prefix if possible. */
7f399153 3163 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3164 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3165 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3166 {
3167 /* 2-byte VEX prefix. */
3168 unsigned int r;
3169
3170 i.vex.length = 2;
3171 i.vex.bytes[0] = 0xc5;
3172
3173 /* Check the REX.R bit. */
3174 r = (i.rex & REX_R) ? 0 : 1;
3175 i.vex.bytes[1] = (r << 7
3176 | register_specifier << 3
3177 | vector_length << 2
3178 | implied_prefix);
3179 }
3180 else
3181 {
3182 /* 3-byte VEX prefix. */
3183 unsigned int m, w;
3184
f88c9eb0 3185 i.vex.length = 3;
f88c9eb0 3186
7f399153 3187 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3188 {
7f399153
L		 3189 case VEX0F:
3190 m = 0x1;
80de6e00 3191 i.vex.bytes[0] = 0xc4;
7f399153
L		 3192 break;
3193 case VEX0F38:
3194 m = 0x2;
80de6e00 3195 i.vex.bytes[0] = 0xc4;
7f399153
L		 3196 break;
3197 case VEX0F3A:
3198 m = 0x3;
80de6e00 3199 i.vex.bytes[0] = 0xc4;
7f399153
L		 3200 break;
3201 case XOP08:
5dd85c99
SP		 3202 m = 0x8;
3203 i.vex.bytes[0] = 0x8f;
7f399153
L		 3204 break;
3205 case XOP09:
f88c9eb0
SP		 3206 m = 0x9;
3207 i.vex.bytes[0] = 0x8f;
7f399153
L		 3208 break;
3209 case XOP0A:
f88c9eb0
SP		 3210 m = 0xa;
3211 i.vex.bytes[0] = 0x8f;
7f399153
L		 3212 break;
3213 default:
3214 abort ();
f88c9eb0 3215 }
c0f3af97 3216
c0f3af97
L		 3217 /* The high 3 bits of the second VEX byte are 1's compliment
3218 of RXB bits from REX. */
3219 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3220
3221 /* Check the REX.W bit. */
3222 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3223 if (i.tm.opcode_modifier.vexw == VEXW1)
3224 w = 1;
c0f3af97
L		 3225
3226 i.vex.bytes[2] = (w << 7
3227 | register_specifier << 3
3228 | vector_length << 2
3229 | implied_prefix);
3230 }
3231}
3232
43234a1e
L		 3233/* Build the EVEX prefix. */
3234
3235static void
3236build_evex_prefix (void)
3237{
3238 unsigned int register_specifier;
3239 unsigned int implied_prefix;
3240 unsigned int m, w;
3241 rex_byte vrex_used = 0;
3242
3243 /* Check register specifier. */
3244 if (i.vex.register_specifier)
3245 {
3246 gas_assert ((i.vrex & REX_X) == 0);
3247
3248 register_specifier = i.vex.register_specifier->reg_num;
3249 if ((i.vex.register_specifier->reg_flags & RegRex))
3250 register_specifier += 8;
3251 /* The upper 16 registers are encoded in the fourth byte of the
3252 EVEX prefix. */
3253 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3254 i.vex.bytes[3] = 0x8;
3255 register_specifier = ~register_specifier & 0xf;
3256 }
3257 else
3258 {
3259 register_specifier = 0xf;
3260
3261 /* Encode upper 16 vector index register in the fourth byte of
3262 the EVEX prefix. */
3263 if (!(i.vrex & REX_X))
3264 i.vex.bytes[3] = 0x8;
3265 else
3266 vrex_used |= REX_X;
3267 }
3268
3269 switch ((i.tm.base_opcode >> 8) & 0xff)
3270 {
3271 case 0:
3272 implied_prefix = 0;
3273 break;
3274 case DATA_PREFIX_OPCODE:
3275 implied_prefix = 1;
3276 break;
3277 case REPE_PREFIX_OPCODE:
3278 implied_prefix = 2;
3279 break;
3280 case REPNE_PREFIX_OPCODE:
3281 implied_prefix = 3;
3282 break;
3283 default:
3284 abort ();
3285 }
3286
3287 /* 4 byte EVEX prefix. */
3288 i.vex.length = 4;
3289 i.vex.bytes[0] = 0x62;
3290
3291 /* mmmm bits. */
3292 switch (i.tm.opcode_modifier.vexopcode)
3293 {
3294 case VEX0F:
3295 m = 1;
3296 break;
3297 case VEX0F38:
3298 m = 2;
3299 break;
3300 case VEX0F3A:
3301 m = 3;
3302 break;
3303 default:
3304 abort ();
3305 break;
3306 }
3307
3308 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3309 bits from REX. */
3310 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3311
3312 /* The fifth bit of the second EVEX byte is 1's compliment of the
3313 REX_R bit in VREX. */
3314 if (!(i.vrex & REX_R))
3315 i.vex.bytes[1] |= 0x10;
3316 else
3317 vrex_used |= REX_R;
3318
3319 if ((i.reg_operands + i.imm_operands) == i.operands)
3320 {
3321 /* When all operands are registers, the REX_X bit in REX is not
3322 used. We reuse it to encode the upper 16 registers, which is
3323 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3324 as 1's compliment. */
3325 if ((i.vrex & REX_B))
3326 {
3327 vrex_used |= REX_B;
3328 i.vex.bytes[1] &= ~0x40;
3329 }
3330 }
3331
3332 /* EVEX instructions shouldn't need the REX prefix. */
3333 i.vrex &= ~vrex_used;
3334 gas_assert (i.vrex == 0);
3335
3336 /* Check the REX.W bit. */
3337 w = (i.rex & REX_W) ? 1 : 0;
3338 if (i.tm.opcode_modifier.vexw)
3339 {
3340 if (i.tm.opcode_modifier.vexw == VEXW1)
3341 w = 1;
3342 }
3343 /* If w is not set it means we are dealing with WIG instruction. */
3344 else if (!w)
3345 {
3346 if (evexwig == evexw1)
3347 w = 1;
3348 }
3349
3350 /* Encode the U bit. */
3351 implied_prefix |= 0x4;
3352
3353 /* The third byte of the EVEX prefix. */
3354 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3355
3356 /* The fourth byte of the EVEX prefix. */
3357 /* The zeroing-masking bit. */
3358 if (i.mask && i.mask->zeroing)
3359 i.vex.bytes[3] |= 0x80;
3360
3361 /* Don't always set the broadcast bit if there is no RC. */
3362 if (!i.rounding)
3363 {
3364 /* Encode the vector length. */
3365 unsigned int vec_length;
3366
3367 switch (i.tm.opcode_modifier.evex)
3368 {
3369 case EVEXLIG: /* LL' is ignored */
3370 vec_length = evexlig << 5;
3371 break;
3372 case EVEX128:
3373 vec_length = 0 << 5;
3374 break;
3375 case EVEX256:
3376 vec_length = 1 << 5;
3377 break;
3378 case EVEX512:
3379 vec_length = 2 << 5;
3380 break;
3381 default:
3382 abort ();
3383 break;
3384 }
3385 i.vex.bytes[3] |= vec_length;
3386 /* Encode the broadcast bit. */
3387 if (i.broadcast)
3388 i.vex.bytes[3] |= 0x10;
3389 }
3390 else
3391 {
3392 if (i.rounding->type != saeonly)
3393 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3394 else
d3d3c6db 3395 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3396 }
3397
3398 if (i.mask && i.mask->mask)
3399 i.vex.bytes[3] |= i.mask->mask->reg_num;
3400}
3401
65da13b5
L		 3402static void
3403process_immext (void)
3404{
3405 expressionS *exp;
3406
4c692bc7
JB		 3407 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3408 && i.operands > 0)
65da13b5 3409 {
4c692bc7
JB		 3410 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3411 with an opcode suffix which is coded in the same place as an
3412 8-bit immediate field would be.
3413 Here we check those operands and remove them afterwards. */
65da13b5
L		 3414 unsigned int x;
3415
3416 for (x = 0; x < i.operands; x++)
4c692bc7 3417 if (register_number (i.op[x].regs) != x)
65da13b5 3418 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3419 register_prefix, i.op[x].regs->reg_name, x + 1,
3420 i.tm.name);
3421
3422 i.operands = 0;
65da13b5
L		 3423 }
3424
9916071f
AP		 3425 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3426 {
3427 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3428 suffix which is coded in the same place as an 8-bit immediate
3429 field would be.
3430 Here we check those operands and remove them afterwards. */
3431 unsigned int x;
3432
3433 if (i.operands != 3)
3434 abort();
3435
3436 for (x = 0; x < 2; x++)
3437 if (register_number (i.op[x].regs) != x)
3438 goto bad_register_operand;
3439
3440 /* Check for third operand for mwaitx/monitorx insn. */
3441 if (register_number (i.op[x].regs)
3442 != (x + (i.tm.extension_opcode == 0xfb)))
3443 {
3444bad_register_operand:
3445 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3446 register_prefix, i.op[x].regs->reg_name, x+1,
3447 i.tm.name);
3448 }
3449
3450 i.operands = 0;
3451 }
3452
c0f3af97 3453 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3454 which is coded in the same place as an 8-bit immediate field
3455 would be. Here we fake an 8-bit immediate operand from the
3456 opcode suffix stored in tm.extension_opcode.
3457
c1e679ec 3458 AVX instructions also use this encoding, for some of
c0f3af97 3459 3 argument instructions. */
65da13b5 3460
43234a1e 3461 gas_assert (i.imm_operands <= 1
7ab9ffdd 3462 && (i.operands <= 2
43234a1e
L		 3463 || ((i.tm.opcode_modifier.vex
3464 || i.tm.opcode_modifier.evex)
7ab9ffdd 3465 && i.operands <= 4)));
65da13b5
L		 3466
3467 exp = &im_expressions[i.imm_operands++];
3468 i.op[i.operands].imms = exp;
3469 i.types[i.operands] = imm8;
3470 i.operands++;
3471 exp->X_op = O_constant;
3472 exp->X_add_number = i.tm.extension_opcode;
3473 i.tm.extension_opcode = None;
3474}
3475
42164a71
L		 3476
3477static int
3478check_hle (void)
3479{
3480 switch (i.tm.opcode_modifier.hleprefixok)
3481 {
3482 default:
3483 abort ();
82c2def5 3484 case HLEPrefixNone:
165de32a
L		 3485 as_bad (_("invalid instruction `%s' after `%s'"),
3486 i.tm.name, i.hle_prefix);
42164a71 3487 return 0;
82c2def5 3488 case HLEPrefixLock:
42164a71
L		 3489 if (i.prefix[LOCK_PREFIX])
3490 return 1;
165de32a 3491 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3492 return 0;
82c2def5 3493 case HLEPrefixAny:
42164a71 3494 return 1;
82c2def5 3495 case HLEPrefixRelease:
42164a71
L		 3496 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3497 {
3498 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3499 i.tm.name);
3500 return 0;
3501 }
3502 if (i.mem_operands == 0
3503 || !operand_type_check (i.types[i.operands - 1], anymem))
3504 {
3505 as_bad (_("memory destination needed for instruction `%s'"
3506 " after `xrelease'"), i.tm.name);
3507 return 0;
3508 }
3509 return 1;
3510 }
3511}
3512
252b5132
RH		 3513/* This is the guts of the machine-dependent assembler. LINE points to a
3514 machine dependent instruction. This function is supposed to emit
3515 the frags/bytes it assembles to. */
3516
3517void
65da13b5 3518md_assemble (char *line)
252b5132 3519{
40fb9820 3520 unsigned int j;
252b5132 3521 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3522 const insn_template *t;
252b5132 3523
47926f60 3524 /* Initialize globals. */
252b5132
RH		 3525 memset (&i, '\0', sizeof (i));
3526 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3527 i.reloc[j] = NO_RELOC;
252b5132
RH		 3528 memset (disp_expressions, '\0', sizeof (disp_expressions));
3529 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3530 save_stack_p = save_stack;
252b5132
RH		 3531
3532 /* First parse an instruction mnemonic & call i386_operand for the operands.
3533 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3534 start of a (possibly prefixed) mnemonic. */
252b5132 3535
29b0f896
AM		 3536 line = parse_insn (line, mnemonic);
3537 if (line == NULL)
3538 return;
252b5132 3539
29b0f896 3540 line = parse_operands (line, mnemonic);
ee86248c 3541 this_operand = -1;
29b0f896
AM		 3542 if (line == NULL)
3543 return;
252b5132 3544
29b0f896
AM		 3545 /* Now we've parsed the mnemonic into a set of templates, and have the
3546 operands at hand. */
3547
3548 /* All intel opcodes have reversed operands except for "bound" and
3549 "enter". We also don't reverse intersegment "jmp" and "call"
3550 instructions with 2 immediate operands so that the immediate segment
050dfa73 3551 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3552 if (intel_syntax
3553 && i.operands > 1
29b0f896 3554 && (strcmp (mnemonic, "bound") != 0)
30123838 3555 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3556 && !(operand_type_check (i.types[0], imm)
3557 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3558 swap_operands ();
3559
ec56d5c0
JB		 3560 /* The order of the immediates should be reversed
3561 for 2 immediates extrq and insertq instructions */
3562 if (i.imm_operands == 2
3563 && (strcmp (mnemonic, "extrq") == 0
3564 || strcmp (mnemonic, "insertq") == 0))
3565 swap_2_operands (0, 1);
3566
29b0f896
AM		 3567 if (i.imm_operands)
3568 optimize_imm ();
3569
b300c311
L		 3570 /* Don't optimize displacement for movabs since it only takes 64bit
3571 displacement. */
3572 if (i.disp_operands
a501d77e 3573 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3574 && (flag_code != CODE_64BIT
3575 || strcmp (mnemonic, "movabs") != 0))
3576 optimize_disp ();
29b0f896
AM		 3577
3578 /* Next, we find a template that matches the given insn,
3579 making sure the overlap of the given operands types is consistent
3580 with the template operand types. */
252b5132 3581
fa99fab2 3582 if (!(t = match_template ()))
29b0f896 3583 return;
252b5132 3584
7bab8ab5 3585 if (sse_check != check_none
81f8a913 3586 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3587 && (i.tm.cpu_flags.bitfield.cpusse
3588 || i.tm.cpu_flags.bitfield.cpusse2
3589 || i.tm.cpu_flags.bitfield.cpusse3
3590 || i.tm.cpu_flags.bitfield.cpussse3
3591 || i.tm.cpu_flags.bitfield.cpusse4_1
3592 || i.tm.cpu_flags.bitfield.cpusse4_2))
3593 {
7bab8ab5 3594 (sse_check == check_warning
daf50ae7
L		 3595 ? as_warn
3596 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3597 }
3598
321fd21e
L		 3599 /* Zap movzx and movsx suffix. The suffix has been set from
3600 "word ptr" or "byte ptr" on the source operand in Intel syntax
3601 or extracted from mnemonic in AT&T syntax. But we'll use
3602 the destination register to choose the suffix for encoding. */
3603 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3604 {
321fd21e
L		 3605 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3606 there is no suffix, the default will be byte extension. */
3607 if (i.reg_operands != 2
3608 && !i.suffix
7ab9ffdd 3609 && intel_syntax)
321fd21e
L		 3610 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3611
3612 i.suffix = 0;
cd61ebfe 3613 }
24eab124 3614
40fb9820 3615 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3616 if (!add_prefix (FWAIT_OPCODE))
3617 return;
252b5132 3618
d5de92cf
L		 3619 /* Check if REP prefix is OK. */
3620 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3621 {
3622 as_bad (_("invalid instruction `%s' after `%s'"),
3623 i.tm.name, i.rep_prefix);
3624 return;
3625 }
3626
c1ba0266
L		 3627 /* Check for lock without a lockable instruction. Destination operand
3628 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3629 if (i.prefix[LOCK_PREFIX]
3630 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3631 || i.mem_operands == 0
3632 || (i.tm.base_opcode != 0x86
3633 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3634 {
3635 as_bad (_("expecting lockable instruction after `lock'"));
3636 return;
3637 }
3638
42164a71 3639 /* Check if HLE prefix is OK. */
165de32a 3640 if (i.hle_prefix && !check_hle ())
42164a71
L		 3641 return;
3642
7e8b059b
L		 3643 /* Check BND prefix. */
3644 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3645 as_bad (_("expecting valid branch instruction after `bnd'"));
3646
3647 if (i.tm.cpu_flags.bitfield.cpumpx
3648 && flag_code == CODE_64BIT
3649 && i.prefix[ADDR_PREFIX])
3650 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3651
3652 /* Insert BND prefix. */
3653 if (add_bnd_prefix
3654 && i.tm.opcode_modifier.bndprefixok
3655 && !i.prefix[BND_PREFIX])
3656 add_prefix (BND_PREFIX_OPCODE);
3657
29b0f896 3658 /* Check string instruction segment overrides. */
40fb9820 3659 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3660 {
3661 if (!check_string ())
5dd0794d 3662 return;
fc0763e6 3663 i.disp_operands = 0;
29b0f896 3664 }
5dd0794d 3665
29b0f896
AM		 3666 if (!process_suffix ())
3667 return;
e413e4e9 3668
bc0844ae
L		 3669 /* Update operand types. */
3670 for (j = 0; j < i.operands; j++)
3671 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3672
29b0f896
AM		 3673 /* Make still unresolved immediate matches conform to size of immediate
3674 given in i.suffix. */
3675 if (!finalize_imm ())
3676 return;
252b5132 3677
40fb9820 3678 if (i.types[0].bitfield.imm1)
29b0f896 3679 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3680
9afe6eb8
L		 3681 /* We only need to check those implicit registers for instructions
3682 with 3 operands or less. */
3683 if (i.operands <= 3)
3684 for (j = 0; j < i.operands; j++)
3685 if (i.types[j].bitfield.inoutportreg
3686 || i.types[j].bitfield.shiftcount
3687 || i.types[j].bitfield.acc
3688 || i.types[j].bitfield.floatacc)
3689 i.reg_operands--;
40fb9820 3690
c0f3af97
L		 3691 /* ImmExt should be processed after SSE2AVX. */
3692 if (!i.tm.opcode_modifier.sse2avx
3693 && i.tm.opcode_modifier.immext)
65da13b5 3694 process_immext ();
252b5132 3695
29b0f896
AM		 3696 /* For insns with operands there are more diddles to do to the opcode. */
3697 if (i.operands)
3698 {
3699 if (!process_operands ())
3700 return;
3701 }
40fb9820 3702 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3703 {
3704 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3705 as_warn (_("translating to `%sp'"), i.tm.name);
3706 }
252b5132 3707
9e5e5283
L		 3708 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3709 {
3710 if (flag_code == CODE_16BIT)
3711 {
3712 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3713 i.tm.name);
3714 return;
3715 }
c0f3af97 3716
9e5e5283
L		 3717 if (i.tm.opcode_modifier.vex)
3718 build_vex_prefix (t);
3719 else
3720 build_evex_prefix ();
3721 }
43234a1e 3722
5dd85c99
SP		 3723 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3724 instructions may define INT_OPCODE as well, so avoid this corner
3725 case for those instructions that use MODRM. */
3726 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3727 && !i.tm.opcode_modifier.modrm
3728 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3729 {
3730 i.tm.base_opcode = INT3_OPCODE;
3731 i.imm_operands = 0;
3732 }
252b5132 3733
40fb9820
L		 3734 if ((i.tm.opcode_modifier.jump
3735 || i.tm.opcode_modifier.jumpbyte
3736 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3737 && i.op[0].disps->X_op == O_constant)
3738 {
3739 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3740 the absolute address given by the constant. Since ix86 jumps and
3741 calls are pc relative, we need to generate a reloc. */
3742 i.op[0].disps->X_add_symbol = &abs_symbol;
3743 i.op[0].disps->X_op = O_symbol;
3744 }
252b5132 3745
40fb9820 3746 if (i.tm.opcode_modifier.rex64)
161a04f6 3747 i.rex |= REX_W;
252b5132 3748
29b0f896
AM		 3749 /* For 8 bit registers we need an empty rex prefix. Also if the
3750 instruction already has a prefix, we need to convert old
3751 registers to new ones. */
773f551c 3752
40fb9820 3753 if ((i.types[0].bitfield.reg8
29b0f896 3754 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3755 || (i.types[1].bitfield.reg8
29b0f896 3756 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3757 || ((i.types[0].bitfield.reg8
3758 || i.types[1].bitfield.reg8)
29b0f896
AM		 3759 && i.rex != 0))
3760 {
3761 int x;
726c5dcd 3762
29b0f896
AM		 3763 i.rex |= REX_OPCODE;
3764 for (x = 0; x < 2; x++)
3765 {
3766 /* Look for 8 bit operand that uses old registers. */
40fb9820 3767 if (i.types[x].bitfield.reg8
29b0f896 3768 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3769 {
29b0f896
AM		 3770 /* In case it is "hi" register, give up. */
3771 if (i.op[x].regs->reg_num > 3)
a540244d 3772 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3773 "instruction requiring REX prefix."),
a540244d 3774 register_prefix, i.op[x].regs->reg_name);
773f551c 3775
29b0f896
AM		 3776 /* Otherwise it is equivalent to the extended register.
3777 Since the encoding doesn't change this is merely
3778 cosmetic cleanup for debug output. */
3779
3780 i.op[x].regs = i.op[x].regs + 8;
773f551c 3781 }
29b0f896
AM		 3782 }
3783 }
773f551c 3784
7ab9ffdd 3785 if (i.rex != 0)
29b0f896
AM		 3786 add_prefix (REX_OPCODE | i.rex);
3787
3788 /* We are ready to output the insn. */
3789 output_insn ();
3790}
3791
3792static char *
e3bb37b5 3793parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3794{
3795 char *l = line;
3796 char *token_start = l;
3797 char *mnem_p;
5c6af06e 3798 int supported;
d3ce72d0 3799 const insn_template *t;
b6169b20 3800 char *dot_p = NULL;
29b0f896 3801
29b0f896
AM		 3802 while (1)
3803 {
3804 mnem_p = mnemonic;
3805 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3806 {
b6169b20
L		 3807 if (*mnem_p == '.')
3808 dot_p = mnem_p;
29b0f896
AM		 3809 mnem_p++;
3810 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3811 {
29b0f896
AM		 3812 as_bad (_("no such instruction: `%s'"), token_start);
3813 return NULL;
3814 }
3815 l++;
3816 }
3817 if (!is_space_char (*l)
3818 && *l != END_OF_INSN
e44823cf
JB		 3819 && (intel_syntax
3820 || (*l != PREFIX_SEPARATOR
3821 && *l != ',')))
29b0f896
AM		 3822 {
3823 as_bad (_("invalid character %s in mnemonic"),
3824 output_invalid (*l));
3825 return NULL;
3826 }
3827 if (token_start == l)
3828 {
e44823cf 3829 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3830 as_bad (_("expecting prefix; got nothing"));
3831 else
3832 as_bad (_("expecting mnemonic; got nothing"));
3833 return NULL;
3834 }
45288df1 3835
29b0f896 3836 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3837 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3838
29b0f896
AM		 3839 if (*l != END_OF_INSN
3840 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3841 && current_templates
40fb9820 3842 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3843 {
c6fb90c8 3844 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3845 {
3846 as_bad ((flag_code != CODE_64BIT
3847 ? _("`%s' is only supported in 64-bit mode")
3848 : _("`%s' is not supported in 64-bit mode")),
3849 current_templates->start->name);
3850 return NULL;
3851 }
29b0f896
AM		 3852 /* If we are in 16-bit mode, do not allow addr16 or data16.
3853 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3854 if ((current_templates->start->opcode_modifier.size16
3855 || current_templates->start->opcode_modifier.size32)
29b0f896 3856 && flag_code != CODE_64BIT
40fb9820 3857 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3858 ^ (flag_code == CODE_16BIT)))
3859 {
3860 as_bad (_("redundant %s prefix"),
3861 current_templates->start->name);
3862 return NULL;
45288df1 3863 }
29b0f896
AM		 3864 /* Add prefix, checking for repeated prefixes. */
3865 switch (add_prefix (current_templates->start->base_opcode))
3866 {
c32fa91d 3867 case PREFIX_EXIST:
29b0f896 3868 return NULL;
c32fa91d 3869 case PREFIX_REP:
42164a71 3870 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3871 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3872 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3873 i.bnd_prefix = current_templates->start->name;
42164a71 3874 else
d5de92cf 3875 i.rep_prefix = current_templates->start->name;
29b0f896 3876 break;
c32fa91d
L		 3877 default:
3878 break;
29b0f896
AM		 3879 }
3880 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3881 token_start = ++l;
3882 }
3883 else
3884 break;
3885 }
45288df1 3886
30a55f88 3887 if (!current_templates)
b6169b20 3888 {
f8a5c266
L		 3889 /* Check if we should swap operand or force 32bit displacement in
3890 encoding. */
30a55f88
L		 3891 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3892 i.swap_operand = 1;
8d63c93e 3893 else if (mnem_p - 3 == dot_p
a501d77e
L		 3894 && dot_p[1] == 'd'
3895 && dot_p[2] == '8')
3896 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3897 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3898 && dot_p[1] == 'd'
3899 && dot_p[2] == '3'
3900 && dot_p[3] == '2')
a501d77e 3901 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3902 else
3903 goto check_suffix;
3904 mnem_p = dot_p;
3905 *dot_p = '\0';
d3ce72d0 3906 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3907 }
3908
29b0f896
AM		 3909 if (!current_templates)
3910 {
b6169b20 3911check_suffix:
29b0f896
AM		 3912 /* See if we can get a match by trimming off a suffix. */
3913 switch (mnem_p[-1])
3914 {
3915 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3916 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3917 i.suffix = SHORT_MNEM_SUFFIX;
3918 else
29b0f896
AM		 3919 case BYTE_MNEM_SUFFIX:
3920 case QWORD_MNEM_SUFFIX:
3921 i.suffix = mnem_p[-1];
3922 mnem_p[-1] = '\0';
d3ce72d0
NC		 3923 current_templates = (const templates *) hash_find (op_hash,
3924 mnemonic);
29b0f896
AM		 3925 break;
3926 case SHORT_MNEM_SUFFIX:
3927 case LONG_MNEM_SUFFIX:
3928 if (!intel_syntax)
3929 {
3930 i.suffix = mnem_p[-1];
3931 mnem_p[-1] = '\0';
d3ce72d0
NC		 3932 current_templates = (const templates *) hash_find (op_hash,
3933 mnemonic);
29b0f896
AM		 3934 }
3935 break;
252b5132 3936
29b0f896
AM		 3937 /* Intel Syntax. */
3938 case 'd':
3939 if (intel_syntax)
3940 {
9306ca4a 3941 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3942 i.suffix = SHORT_MNEM_SUFFIX;
3943 else
3944 i.suffix = LONG_MNEM_SUFFIX;
3945 mnem_p[-1] = '\0';
d3ce72d0
NC		 3946 current_templates = (const templates *) hash_find (op_hash,
3947 mnemonic);
29b0f896
AM		 3948 }
3949 break;
3950 }
3951 if (!current_templates)
3952 {
3953 as_bad (_("no such instruction: `%s'"), token_start);
3954 return NULL;
3955 }
3956 }
252b5132 3957
40fb9820
L		 3958 if (current_templates->start->opcode_modifier.jump
3959 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3960 {
3961 /* Check for a branch hint. We allow ",pt" and ",pn" for
3962 predict taken and predict not taken respectively.
3963 I'm not sure that branch hints actually do anything on loop
3964 and jcxz insns (JumpByte) for current Pentium4 chips. They
3965 may work in the future and it doesn't hurt to accept them
3966 now. */
3967 if (l[0] == ',' && l[1] == 'p')
3968 {
3969 if (l[2] == 't')
3970 {
3971 if (!add_prefix (DS_PREFIX_OPCODE))
3972 return NULL;
3973 l += 3;
3974 }
3975 else if (l[2] == 'n')
3976 {
3977 if (!add_prefix (CS_PREFIX_OPCODE))
3978 return NULL;
3979 l += 3;
3980 }
3981 }
3982 }
3983 /* Any other comma loses. */
3984 if (*l == ',')
3985 {
3986 as_bad (_("invalid character %s in mnemonic"),
3987 output_invalid (*l));
3988 return NULL;
3989 }
252b5132 3990
29b0f896 3991 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3992 supported = 0;
3993 for (t = current_templates->start; t < current_templates->end; ++t)
3994 {
c0f3af97
L		 3995 supported |= cpu_flags_match (t);
3996 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3997 goto skip;
5c6af06e 3998 }
3629bb00 3999
c0f3af97 4000 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4001 {
4002 as_bad (flag_code == CODE_64BIT
4003 ? _("`%s' is not supported in 64-bit mode")
4004 : _("`%s' is only supported in 64-bit mode"),
4005 current_templates->start->name);
4006 return NULL;
4007 }
c0f3af97 4008 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4009 {
3629bb00 4010 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4011 current_templates->start->name,
41aacd83 4012 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4013 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4014 return NULL;
29b0f896 4015 }
3629bb00
L		 4016
4017skip:
4018 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4019 && (flag_code != CODE_16BIT))
29b0f896
AM		 4020 {
4021 as_warn (_("use .code16 to ensure correct addressing mode"));
4022 }
252b5132 4023
29b0f896
AM		 4024 return l;
4025}
252b5132 4026
29b0f896 4027static char *
e3bb37b5 4028parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4029{
4030 char *token_start;
3138f287 4031
29b0f896
AM		 4032 /* 1 if operand is pending after ','. */
4033 unsigned int expecting_operand = 0;
252b5132 4034
29b0f896
AM		 4035 /* Non-zero if operand parens not balanced. */
4036 unsigned int paren_not_balanced;
4037
4038 while (*l != END_OF_INSN)
4039 {
4040 /* Skip optional white space before operand. */
4041 if (is_space_char (*l))
4042 ++l;
d02603dc 4043 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4044 {
4045 as_bad (_("invalid character %s before operand %d"),
4046 output_invalid (*l),
4047 i.operands + 1);
4048 return NULL;
4049 }
d02603dc 4050 token_start = l; /* After white space. */
29b0f896
AM		 4051 paren_not_balanced = 0;
4052 while (paren_not_balanced || *l != ',')
4053 {
4054 if (*l == END_OF_INSN)
4055 {
4056 if (paren_not_balanced)
4057 {
4058 if (!intel_syntax)
4059 as_bad (_("unbalanced parenthesis in operand %d."),
4060 i.operands + 1);
4061 else
4062 as_bad (_("unbalanced brackets in operand %d."),
4063 i.operands + 1);
4064 return NULL;
4065 }
4066 else
4067 break; /* we are done */
4068 }
d02603dc 4069 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4070 {
4071 as_bad (_("invalid character %s in operand %d"),
4072 output_invalid (*l),
4073 i.operands + 1);
4074 return NULL;
4075 }
4076 if (!intel_syntax)
4077 {
4078 if (*l == '(')
4079 ++paren_not_balanced;
4080 if (*l == ')')
4081 --paren_not_balanced;
4082 }
4083 else
4084 {
4085 if (*l == '[')
4086 ++paren_not_balanced;
4087 if (*l == ']')
4088 --paren_not_balanced;
4089 }
4090 l++;
4091 }
4092 if (l != token_start)
4093 { /* Yes, we've read in another operand. */
4094 unsigned int operand_ok;
4095 this_operand = i.operands++;
7d5e4556 4096 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4097 if (i.operands > MAX_OPERANDS)
4098 {
4099 as_bad (_("spurious operands; (%d operands/instruction max)"),
4100 MAX_OPERANDS);
4101 return NULL;
4102 }
4103 /* Now parse operand adding info to 'i' as we go along. */
4104 END_STRING_AND_SAVE (l);
4105
4106 if (intel_syntax)
4107 operand_ok =
4108 i386_intel_operand (token_start,
4109 intel_float_operand (mnemonic));
4110 else
a7619375 4111 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4112
4113 RESTORE_END_STRING (l);
4114 if (!operand_ok)
4115 return NULL;
4116 }
4117 else
4118 {
4119 if (expecting_operand)
4120 {
4121 expecting_operand_after_comma:
4122 as_bad (_("expecting operand after ','; got nothing"));
4123 return NULL;
4124 }
4125 if (*l == ',')
4126 {
4127 as_bad (_("expecting operand before ','; got nothing"));
4128 return NULL;
4129 }
4130 }
7f3f1ea2 4131
29b0f896
AM		 4132 /* Now *l must be either ',' or END_OF_INSN. */
4133 if (*l == ',')
4134 {
4135 if (*++l == END_OF_INSN)
4136 {
4137 /* Just skip it, if it's \n complain. */
4138 goto expecting_operand_after_comma;
4139 }
4140 expecting_operand = 1;
4141 }
4142 }
4143 return l;
4144}
7f3f1ea2 4145
050dfa73 4146static void
4d456e3d 4147swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4148{
4149 union i386_op temp_op;
40fb9820 4150 i386_operand_type temp_type;
050dfa73 4151 enum bfd_reloc_code_real temp_reloc;
4eed87de 4152
050dfa73
MM		 4153 temp_type = i.types[xchg2];
4154 i.types[xchg2] = i.types[xchg1];
4155 i.types[xchg1] = temp_type;
4156 temp_op = i.op[xchg2];
4157 i.op[xchg2] = i.op[xchg1];
4158 i.op[xchg1] = temp_op;
4159 temp_reloc = i.reloc[xchg2];
4160 i.reloc[xchg2] = i.reloc[xchg1];
4161 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4162
4163 if (i.mask)
4164 {
4165 if (i.mask->operand == xchg1)
4166 i.mask->operand = xchg2;
4167 else if (i.mask->operand == xchg2)
4168 i.mask->operand = xchg1;
4169 }
4170 if (i.broadcast)
4171 {
4172 if (i.broadcast->operand == xchg1)
4173 i.broadcast->operand = xchg2;
4174 else if (i.broadcast->operand == xchg2)
4175 i.broadcast->operand = xchg1;
4176 }
4177 if (i.rounding)
4178 {
4179 if (i.rounding->operand == xchg1)
4180 i.rounding->operand = xchg2;
4181 else if (i.rounding->operand == xchg2)
4182 i.rounding->operand = xchg1;
4183 }
050dfa73
MM		 4184}
4185
29b0f896 4186static void
e3bb37b5 4187swap_operands (void)
29b0f896 4188{
b7c61d9a 4189 switch (i.operands)
050dfa73 4190 {
c0f3af97 4191 case 5:
b7c61d9a 4192 case 4:
4d456e3d 4193 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4194 case 3:
4195 case 2:
4d456e3d 4196 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4197 break;
4198 default:
4199 abort ();
29b0f896 4200 }
29b0f896
AM		 4201
4202 if (i.mem_operands == 2)
4203 {
4204 const seg_entry *temp_seg;
4205 temp_seg = i.seg[0];
4206 i.seg[0] = i.seg[1];
4207 i.seg[1] = temp_seg;
4208 }
4209}
252b5132 4210
29b0f896
AM		 4211/* Try to ensure constant immediates are represented in the smallest
4212 opcode possible. */
4213static void
e3bb37b5 4214optimize_imm (void)
29b0f896
AM		 4215{
4216 char guess_suffix = 0;
4217 int op;
252b5132 4218
29b0f896
AM		 4219 if (i.suffix)
4220 guess_suffix = i.suffix;
4221 else if (i.reg_operands)
4222 {
4223 /* Figure out a suffix from the last register operand specified.
4224 We can't do this properly yet, ie. excluding InOutPortReg,
4225 but the following works for instructions with immediates.
4226 In any case, we can't set i.suffix yet. */
4227 for (op = i.operands; --op >= 0;)
40fb9820 4228 if (i.types[op].bitfield.reg8)
7ab9ffdd 4229 {
40fb9820
L		 4230 guess_suffix = BYTE_MNEM_SUFFIX;
4231 break;
4232 }
4233 else if (i.types[op].bitfield.reg16)
252b5132 4234 {
40fb9820
L		 4235 guess_suffix = WORD_MNEM_SUFFIX;
4236 break;
4237 }
4238 else if (i.types[op].bitfield.reg32)
4239 {
4240 guess_suffix = LONG_MNEM_SUFFIX;
4241 break;
4242 }
4243 else if (i.types[op].bitfield.reg64)
4244 {
4245 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4246 break;
252b5132 4247 }
29b0f896
AM		 4248 }
4249 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4250 guess_suffix = WORD_MNEM_SUFFIX;
4251
4252 for (op = i.operands; --op >= 0;)
40fb9820 4253 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4254 {
4255 switch (i.op[op].imms->X_op)
252b5132 4256 {
29b0f896
AM		 4257 case O_constant:
4258 /* If a suffix is given, this operand may be shortened. */
4259 switch (guess_suffix)
252b5132 4260 {
29b0f896 4261 case LONG_MNEM_SUFFIX:
40fb9820
L		 4262 i.types[op].bitfield.imm32 = 1;
4263 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4264 break;
4265 case WORD_MNEM_SUFFIX:
40fb9820
L		 4266 i.types[op].bitfield.imm16 = 1;
4267 i.types[op].bitfield.imm32 = 1;
4268 i.types[op].bitfield.imm32s = 1;
4269 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4270 break;
4271 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4272 i.types[op].bitfield.imm8 = 1;
4273 i.types[op].bitfield.imm8s = 1;
4274 i.types[op].bitfield.imm16 = 1;
4275 i.types[op].bitfield.imm32 = 1;
4276 i.types[op].bitfield.imm32s = 1;
4277 i.types[op].bitfield.imm64 = 1;
29b0f896 4278 break;
252b5132 4279 }
252b5132 4280
29b0f896
AM		 4281 /* If this operand is at most 16 bits, convert it
4282 to a signed 16 bit number before trying to see
4283 whether it will fit in an even smaller size.
4284 This allows a 16-bit operand such as $0xffe0 to
4285 be recognised as within Imm8S range. */
40fb9820 4286 if ((i.types[op].bitfield.imm16)
29b0f896 4287 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4288 {
29b0f896
AM		 4289 i.op[op].imms->X_add_number =
4290 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4291 }
a28def75
L		 4292#ifdef BFD64
4293 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4294 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4295 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4296 == 0))
4297 {
4298 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4299 ^ ((offsetT) 1 << 31))
4300 - ((offsetT) 1 << 31));
4301 }
a28def75 4302#endif
40fb9820 4303 i.types[op]
c6fb90c8
L		 4304 = operand_type_or (i.types[op],
4305 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4306
29b0f896
AM		 4307 /* We must avoid matching of Imm32 templates when 64bit
4308 only immediate is available. */
4309 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4310 i.types[op].bitfield.imm32 = 0;
29b0f896 4311 break;
252b5132 4312
29b0f896
AM		 4313 case O_absent:
4314 case O_register:
4315 abort ();
4316
4317 /* Symbols and expressions. */
4318 default:
9cd96992
JB		 4319 /* Convert symbolic operand to proper sizes for matching, but don't
4320 prevent matching a set of insns that only supports sizes other
4321 than those matching the insn suffix. */
4322 {
40fb9820 4323 i386_operand_type mask, allowed;
d3ce72d0 4324 const insn_template *t;
9cd96992 4325
0dfbf9d7
L		 4326 operand_type_set (&mask, 0);
4327 operand_type_set (&allowed, 0);
40fb9820 4328
4eed87de
AM		 4329 for (t = current_templates->start;
4330 t < current_templates->end;
4331 ++t)
c6fb90c8
L		 4332 allowed = operand_type_or (allowed,
4333 t->operand_types[op]);
9cd96992
JB		 4334 switch (guess_suffix)
4335 {
4336 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4337 mask.bitfield.imm64 = 1;
4338 mask.bitfield.imm32s = 1;
9cd96992
JB		 4339 break;
4340 case LONG_MNEM_SUFFIX:
40fb9820 4341 mask.bitfield.imm32 = 1;
9cd96992
JB		 4342 break;
4343 case WORD_MNEM_SUFFIX:
40fb9820 4344 mask.bitfield.imm16 = 1;
9cd96992
JB		 4345 break;
4346 case BYTE_MNEM_SUFFIX:
40fb9820 4347 mask.bitfield.imm8 = 1;
9cd96992
JB		 4348 break;
4349 default:
9cd96992
JB		 4350 break;
4351 }
c6fb90c8 4352 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4353 if (!operand_type_all_zero (&allowed))
c6fb90c8 4354 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4355 }
29b0f896 4356 break;
252b5132 4357 }
29b0f896
AM		 4358 }
4359}
47926f60 4360
29b0f896
AM		 4361/* Try to use the smallest displacement type too. */
4362static void
e3bb37b5 4363optimize_disp (void)
29b0f896
AM		 4364{
4365 int op;
3e73aa7c 4366
29b0f896 4367 for (op = i.operands; --op >= 0;)
40fb9820 4368 if (operand_type_check (i.types[op], disp))
252b5132 4369 {
b300c311 4370 if (i.op[op].disps->X_op == O_constant)
252b5132 4371 {
91d6fa6a 4372 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4373
40fb9820 4374 if (i.types[op].bitfield.disp16
91d6fa6a 4375 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4376 {
4377 /* If this operand is at most 16 bits, convert
4378 to a signed 16 bit number and don't use 64bit
4379 displacement. */
91d6fa6a 4380 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4381 i.types[op].bitfield.disp64 = 0;
b300c311 4382 }
a28def75
L		 4383#ifdef BFD64
4384 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4385 if (i.types[op].bitfield.disp32
91d6fa6a 4386 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4387 {
4388 /* If this operand is at most 32 bits, convert
4389 to a signed 32 bit number and don't use 64bit
4390 displacement. */
91d6fa6a
NC		 4391 op_disp &= (((offsetT) 2 << 31) - 1);
4392 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4393 i.types[op].bitfield.disp64 = 0;
b300c311 4394 }
a28def75 4395#endif
91d6fa6a 4396 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4397 {
40fb9820
L		 4398 i.types[op].bitfield.disp8 = 0;
4399 i.types[op].bitfield.disp16 = 0;
4400 i.types[op].bitfield.disp32 = 0;
4401 i.types[op].bitfield.disp32s = 0;
4402 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4403 i.op[op].disps = 0;
4404 i.disp_operands--;
4405 }
4406 else if (flag_code == CODE_64BIT)
4407 {
91d6fa6a 4408 if (fits_in_signed_long (op_disp))
28a9d8f5 4409 {
40fb9820
L		 4410 i.types[op].bitfield.disp64 = 0;
4411 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4412 }
0e1147d9 4413 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4414 && fits_in_unsigned_long (op_disp))
40fb9820 4415 i.types[op].bitfield.disp32 = 1;
b300c311 4416 }
40fb9820
L		 4417 if ((i.types[op].bitfield.disp32
4418 || i.types[op].bitfield.disp32s
4419 || i.types[op].bitfield.disp16)
91d6fa6a 4420 && fits_in_signed_byte (op_disp))
40fb9820 4421 i.types[op].bitfield.disp8 = 1;
252b5132 4422 }
67a4f2b7
AO		 4423 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4424 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4425 {
4426 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4427 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4428 i.types[op].bitfield.disp8 = 0;
4429 i.types[op].bitfield.disp16 = 0;
4430 i.types[op].bitfield.disp32 = 0;
4431 i.types[op].bitfield.disp32s = 0;
4432 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4433 }
4434 else
b300c311 4435 /* We only support 64bit displacement on constants. */
40fb9820 4436 i.types[op].bitfield.disp64 = 0;
252b5132 4437 }
29b0f896
AM		 4438}
4439
6c30d220
L		 4440/* Check if operands are valid for the instruction. */
4441
4442static int
4443check_VecOperands (const insn_template *t)
4444{
43234a1e
L		 4445 unsigned int op;
4446
6c30d220
L		 4447 /* Without VSIB byte, we can't have a vector register for index. */
4448 if (!t->opcode_modifier.vecsib
4449 && i.index_reg
4450 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4451 || i.index_reg->reg_type.bitfield.regymm
4452 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4453 {
4454 i.error = unsupported_vector_index_register;
4455 return 1;
4456 }
4457
ad8ecc81
MZ		 4458 /* Check if default mask is allowed. */
4459 if (t->opcode_modifier.nodefmask
4460 && (!i.mask || i.mask->mask->reg_num == 0))
4461 {
4462 i.error = no_default_mask;
4463 return 1;
4464 }
4465
7bab8ab5
JB		 4466 /* For VSIB byte, we need a vector register for index, and all vector
4467 registers must be distinct. */
4468 if (t->opcode_modifier.vecsib)
4469 {
4470 if (!i.index_reg
6c30d220
L		 4471 || !((t->opcode_modifier.vecsib == VecSIB128
4472 && i.index_reg->reg_type.bitfield.regxmm)
4473 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4474 && i.index_reg->reg_type.bitfield.regymm)
4475 || (t->opcode_modifier.vecsib == VecSIB512
4476 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4477 {
4478 i.error = invalid_vsib_address;
4479 return 1;
4480 }
4481
43234a1e
L		 4482 gas_assert (i.reg_operands == 2 || i.mask);
4483 if (i.reg_operands == 2 && !i.mask)
4484 {
4485 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4486 || i.types[0].bitfield.regymm);
43234a1e 4487 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4488 || i.types[2].bitfield.regymm);
43234a1e
L		 4489 if (operand_check == check_none)
4490 return 0;
4491 if (register_number (i.op[0].regs)
4492 != register_number (i.index_reg)
4493 && register_number (i.op[2].regs)
4494 != register_number (i.index_reg)
4495 && register_number (i.op[0].regs)
4496 != register_number (i.op[2].regs))
4497 return 0;
4498 if (operand_check == check_error)
4499 {
4500 i.error = invalid_vector_register_set;
4501 return 1;
4502 }
4503 as_warn (_("mask, index, and destination registers should be distinct"));
4504 }
8444f82a
MZ		 4505 else if (i.reg_operands == 1 && i.mask)
4506 {
4507 if ((i.types[1].bitfield.regymm
4508 || i.types[1].bitfield.regzmm)
4509 && (register_number (i.op[1].regs)
4510 == register_number (i.index_reg)))
4511 {
4512 if (operand_check == check_error)
4513 {
4514 i.error = invalid_vector_register_set;
4515 return 1;
4516 }
4517 if (operand_check != check_none)
4518 as_warn (_("index and destination registers should be distinct"));
4519 }
4520 }
43234a1e 4521 }
7bab8ab5 4522
43234a1e
L		 4523 /* Check if broadcast is supported by the instruction and is applied
4524 to the memory operand. */
4525 if (i.broadcast)
4526 {
4527 int broadcasted_opnd_size;
4528
4529 /* Check if specified broadcast is supported in this instruction,
4530 and it's applied to memory operand of DWORD or QWORD type,
4531 depending on VecESize. */
4532 if (i.broadcast->type != t->opcode_modifier.broadcast
4533 || !i.types[i.broadcast->operand].bitfield.mem
4534 || (t->opcode_modifier.vecesize == 0
4535 && !i.types[i.broadcast->operand].bitfield.dword
4536 && !i.types[i.broadcast->operand].bitfield.unspecified)
4537 || (t->opcode_modifier.vecesize == 1
4538 && !i.types[i.broadcast->operand].bitfield.qword
4539 && !i.types[i.broadcast->operand].bitfield.unspecified))
4540 goto bad_broadcast;
4541
4542 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4543 if (i.broadcast->type == BROADCAST_1TO16)
4544 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4545 else if (i.broadcast->type == BROADCAST_1TO8)
4546 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4547 else if (i.broadcast->type == BROADCAST_1TO4)
4548 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4549 else if (i.broadcast->type == BROADCAST_1TO2)
4550 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4551 else
4552 goto bad_broadcast;
4553
4554 if ((broadcasted_opnd_size == 256
4555 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4556 || (broadcasted_opnd_size == 512
4557 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4558 {
4559 bad_broadcast:
4560 i.error = unsupported_broadcast;
4561 return 1;
4562 }
4563 }
4564 /* If broadcast is supported in this instruction, we need to check if
4565 operand of one-element size isn't specified without broadcast. */
4566 else if (t->opcode_modifier.broadcast && i.mem_operands)
4567 {
4568 /* Find memory operand. */
4569 for (op = 0; op < i.operands; op++)
4570 if (operand_type_check (i.types[op], anymem))
4571 break;
4572 gas_assert (op < i.operands);
4573 /* Check size of the memory operand. */
4574 if ((t->opcode_modifier.vecesize == 0
4575 && i.types[op].bitfield.dword)
4576 || (t->opcode_modifier.vecesize == 1
4577 && i.types[op].bitfield.qword))
4578 {
4579 i.error = broadcast_needed;
4580 return 1;
4581 }
4582 }
4583
4584 /* Check if requested masking is supported. */
4585 if (i.mask
4586 && (!t->opcode_modifier.masking
4587 || (i.mask->zeroing
4588 && t->opcode_modifier.masking == MERGING_MASKING)))
4589 {
4590 i.error = unsupported_masking;
4591 return 1;
4592 }
4593
4594 /* Check if masking is applied to dest operand. */
4595 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4596 {
4597 i.error = mask_not_on_destination;
4598 return 1;
4599 }
4600
43234a1e
L		 4601 /* Check RC/SAE. */
4602 if (i.rounding)
4603 {
4604 if ((i.rounding->type != saeonly
4605 && !t->opcode_modifier.staticrounding)
4606 || (i.rounding->type == saeonly
4607 && (t->opcode_modifier.staticrounding
4608 || !t->opcode_modifier.sae)))
4609 {
4610 i.error = unsupported_rc_sae;
4611 return 1;
4612 }
4613 /* If the instruction has several immediate operands and one of
4614 them is rounding, the rounding operand should be the last
4615 immediate operand. */
4616 if (i.imm_operands > 1
4617 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4618 {
43234a1e 4619 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4620 return 1;
4621 }
6c30d220
L		 4622 }
4623
43234a1e
L		 4624 /* Check vector Disp8 operand. */
4625 if (t->opcode_modifier.disp8memshift)
4626 {
4627 if (i.broadcast)
4628 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4629 else
4630 i.memshift = t->opcode_modifier.disp8memshift;
4631
4632 for (op = 0; op < i.operands; op++)
4633 if (operand_type_check (i.types[op], disp)
4634 && i.op[op].disps->X_op == O_constant)
4635 {
4636 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4637 int vec_disp8_ok
4638 = (i.disp_encoding != disp_encoding_32bit
4639 && fits_in_vec_disp8 (value));
43234a1e
L		 4640 if (t->operand_types [op].bitfield.vec_disp8)
4641 {
4642 if (vec_disp8_ok)
4643 i.types[op].bitfield.vec_disp8 = 1;
4644 else
4645 {
4646 /* Vector insn can only have Vec_Disp8/Disp32 in
4647 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4648 mode. */
4649 i.types[op].bitfield.disp8 = 0;
4650 if (flag_code != CODE_16BIT)
4651 i.types[op].bitfield.disp16 = 0;
4652 }
4653 }
4654 else if (flag_code != CODE_16BIT)
4655 {
4656 /* One form of this instruction supports vector Disp8.
4657 Try vector Disp8 if we need to use Disp32. */
4658 if (vec_disp8_ok && !fits_in_signed_byte (value))
4659 {
4660 i.error = try_vector_disp8;
4661 return 1;
4662 }
4663 }
4664 }
4665 }
4666 else
4667 i.memshift = -1;
4668
6c30d220
L		 4669 return 0;
4670}
4671
43f3e2ee 4672/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4673 operand types. */
4674
4675static int
4676VEX_check_operands (const insn_template *t)
4677{
43234a1e
L		 4678 /* VREX is only valid with EVEX prefix. */
4679 if (i.need_vrex && !t->opcode_modifier.evex)
4680 {
4681 i.error = invalid_register_operand;
4682 return 1;
4683 }
4684
a683cc34
SP		 4685 if (!t->opcode_modifier.vex)
4686 return 0;
4687
4688 /* Only check VEX_Imm4, which must be the first operand. */
4689 if (t->operand_types[0].bitfield.vec_imm4)
4690 {
4691 if (i.op[0].imms->X_op != O_constant
4692 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4693 {
a65babc9 4694 i.error = bad_imm4;
891edac4
L		 4695 return 1;
4696 }
a683cc34
SP		 4697
4698 /* Turn off Imm8 so that update_imm won't complain. */
4699 i.types[0] = vec_imm4;
4700 }
4701
4702 return 0;
4703}
4704
d3ce72d0 4705static const insn_template *
e3bb37b5 4706match_template (void)
29b0f896
AM		 4707{
4708 /* Points to template once we've found it. */
d3ce72d0 4709 const insn_template *t;
40fb9820 4710 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4711 i386_operand_type overlap4;
29b0f896 4712 unsigned int found_reverse_match;
40fb9820
L		 4713 i386_opcode_modifier suffix_check;
4714 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4715 int addr_prefix_disp;
a5c311ca 4716 unsigned int j;
3629bb00 4717 unsigned int found_cpu_match;
45664ddb 4718 unsigned int check_register;
5614d22c 4719 enum i386_error specific_error = 0;
29b0f896 4720
c0f3af97
L		 4721#if MAX_OPERANDS != 5
4722# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4723#endif
4724
29b0f896 4725 found_reverse_match = 0;
539e75ad 4726 addr_prefix_disp = -1;
40fb9820
L		 4727
4728 memset (&suffix_check, 0, sizeof (suffix_check));
4729 if (i.suffix == BYTE_MNEM_SUFFIX)
4730 suffix_check.no_bsuf = 1;
4731 else if (i.suffix == WORD_MNEM_SUFFIX)
4732 suffix_check.no_wsuf = 1;
4733 else if (i.suffix == SHORT_MNEM_SUFFIX)
4734 suffix_check.no_ssuf = 1;
4735 else if (i.suffix == LONG_MNEM_SUFFIX)
4736 suffix_check.no_lsuf = 1;
4737 else if (i.suffix == QWORD_MNEM_SUFFIX)
4738 suffix_check.no_qsuf = 1;
4739 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4740 suffix_check.no_ldsuf = 1;
29b0f896 4741
01559ecc
L		 4742 /* Must have right number of operands. */
4743 i.error = number_of_operands_mismatch;
4744
45aa61fe 4745 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4746 {
539e75ad
L		 4747 addr_prefix_disp = -1;
4748
29b0f896
AM		 4749 if (i.operands != t->operands)
4750 continue;
4751
50aecf8c 4752 /* Check processor support. */
a65babc9 4753 i.error = unsupported;
c0f3af97
L		 4754 found_cpu_match = (cpu_flags_match (t)
4755 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4756 if (!found_cpu_match)
4757 continue;
4758
e1d4d893 4759 /* Check old gcc support. */
a65babc9 4760 i.error = old_gcc_only;
e1d4d893
L		 4761 if (!old_gcc && t->opcode_modifier.oldgcc)
4762 continue;
4763
4764 /* Check AT&T mnemonic. */
a65babc9 4765 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4766 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4767 continue;
4768
891edac4 4769 /* Check AT&T/Intel syntax. */
a65babc9 4770 i.error = unsupported_syntax;
5c07affc
L		 4771 if ((intel_syntax && t->opcode_modifier.attsyntax)
4772 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4773 continue;
4774
20592a94 4775 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4776 i.error = invalid_instruction_suffix;
567e4e96
L		 4777 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4778 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4779 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4780 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4781 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4782 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4783 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4784 continue;
4785
5c07affc 4786 if (!operand_size_match (t))
7d5e4556 4787 continue;
539e75ad 4788
5c07affc
L		 4789 for (j = 0; j < MAX_OPERANDS; j++)
4790 operand_types[j] = t->operand_types[j];
4791
45aa61fe
AM		 4792 /* In general, don't allow 64-bit operands in 32-bit mode. */
4793 if (i.suffix == QWORD_MNEM_SUFFIX
4794 && flag_code != CODE_64BIT
4795 && (intel_syntax
40fb9820 4796 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4797 && !intel_float_operand (t->name))
4798 : intel_float_operand (t->name) != 2)
40fb9820 4799 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4800 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4801 && !operand_types[0].bitfield.regymm
4802 && !operand_types[0].bitfield.regzmm)
40fb9820 4803 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4804 && operand_types[t->operands > 1].bitfield.regxmm
4805 && operand_types[t->operands > 1].bitfield.regymm
4806 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4807 && (t->base_opcode != 0x0fc7
4808 || t->extension_opcode != 1 /* cmpxchg8b */))
4809 continue;
4810
192dc9c6
JB		 4811 /* In general, don't allow 32-bit operands on pre-386. */
4812 else if (i.suffix == LONG_MNEM_SUFFIX
4813 && !cpu_arch_flags.bitfield.cpui386
4814 && (intel_syntax
4815 ? (!t->opcode_modifier.ignoresize
4816 && !intel_float_operand (t->name))
4817 : intel_float_operand (t->name) != 2)
4818 && ((!operand_types[0].bitfield.regmmx
4819 && !operand_types[0].bitfield.regxmm)
4820 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4821 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4822 continue;
4823
29b0f896 4824 /* Do not verify operands when there are none. */
50aecf8c 4825 else
29b0f896 4826 {
c6fb90c8 4827 if (!t->operands)
2dbab7d5
L		 4828 /* We've found a match; break out of loop. */
4829 break;
29b0f896 4830 }
252b5132 4831
539e75ad
L		 4832 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4833 into Disp32/Disp16/Disp32 operand. */
4834 if (i.prefix[ADDR_PREFIX] != 0)
4835 {
40fb9820 4836 /* There should be only one Disp operand. */
539e75ad
L		 4837 switch (flag_code)
4838 {
4839 case CODE_16BIT:
40fb9820
L		 4840 for (j = 0; j < MAX_OPERANDS; j++)
4841 {
4842 if (operand_types[j].bitfield.disp16)
4843 {
4844 addr_prefix_disp = j;
4845 operand_types[j].bitfield.disp32 = 1;
4846 operand_types[j].bitfield.disp16 = 0;
4847 break;
4848 }
4849 }
539e75ad
L		 4850 break;
4851 case CODE_32BIT:
40fb9820
L		 4852 for (j = 0; j < MAX_OPERANDS; j++)
4853 {
4854 if (operand_types[j].bitfield.disp32)
4855 {
4856 addr_prefix_disp = j;
4857 operand_types[j].bitfield.disp32 = 0;
4858 operand_types[j].bitfield.disp16 = 1;
4859 break;
4860 }
4861 }
539e75ad
L		 4862 break;
4863 case CODE_64BIT:
40fb9820
L		 4864 for (j = 0; j < MAX_OPERANDS; j++)
4865 {
4866 if (operand_types[j].bitfield.disp64)
4867 {
4868 addr_prefix_disp = j;
4869 operand_types[j].bitfield.disp64 = 0;
4870 operand_types[j].bitfield.disp32 = 1;
4871 break;
4872 }
4873 }
539e75ad
L		 4874 break;
4875 }
539e75ad
L		 4876 }
4877
02a86693
L		 4878 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4879 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4880 continue;
4881
56ffb741
L		 4882 /* We check register size if needed. */
4883 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4884 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4885 switch (t->operands)
4886 {
4887 case 1:
40fb9820 4888 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4889 continue;
4890 break;
4891 case 2:
8b38ad71
L		 4892 /* xchg %eax, %eax is a special case. It is an aliase for nop
4893 only in 32bit mode and we can use opcode 0x90. In 64bit
4894 mode, we can't use 0x90 for xchg %eax, %eax since it should
4895 zero-extend %eax to %rax. */
4896 if (flag_code == CODE_64BIT
4897 && t->base_opcode == 0x90
0dfbf9d7
L		 4898 && operand_type_equal (&i.types [0], &acc32)
4899 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4900 continue;
b6169b20
L		 4901 if (i.swap_operand)
4902 {
4903 /* If we swap operand in encoding, we either match
4904 the next one or reverse direction of operands. */
4905 if (t->opcode_modifier.s)
4906 continue;
4907 else if (t->opcode_modifier.d)
4908 goto check_reverse;
4909 }
4910
29b0f896 4911 case 3:
fa99fab2
L		 4912 /* If we swap operand in encoding, we match the next one. */
4913 if (i.swap_operand && t->opcode_modifier.s)
4914 continue;
f48ff2ae 4915 case 4:
c0f3af97 4916 case 5:
c6fb90c8 4917 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4918 if (!operand_type_match (overlap0, i.types[0])
4919 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4920 || (check_register
4921 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4922 operand_types[0],
4923 overlap1, i.types[1],
4924 operand_types[1])))
29b0f896
AM		 4925 {
4926 /* Check if other direction is valid ... */
40fb9820 4927 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4928 continue;
4929
b6169b20 4930check_reverse:
29b0f896 4931 /* Try reversing direction of operands. */
c6fb90c8
L		 4932 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4933 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4934 if (!operand_type_match (overlap0, i.types[0])
4935 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4936 || (check_register
4937 && !operand_type_register_match (overlap0,
4938 i.types[0],
4939 operand_types[1],
4940 overlap1,
4941 i.types[1],
4942 operand_types[0])))
29b0f896
AM		 4943 {
4944 /* Does not match either direction. */
4945 continue;
4946 }
4947 /* found_reverse_match holds which of D or FloatDR
4948 we've found. */
40fb9820 4949 if (t->opcode_modifier.d)
8a2ed489 4950 found_reverse_match = Opcode_D;
40fb9820 4951 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4952 found_reverse_match = Opcode_FloatD;
4953 else
4954 found_reverse_match = 0;
40fb9820 4955 if (t->opcode_modifier.floatr)
8a2ed489 4956 found_reverse_match |= Opcode_FloatR;
29b0f896 4957 }
f48ff2ae 4958 else
29b0f896 4959 {
f48ff2ae 4960 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4961 switch (t->operands)
4962 {
c0f3af97
L		 4963 case 5:
4964 overlap4 = operand_type_and (i.types[4],
4965 operand_types[4]);
d1cbb4db 4966 case 4:
c6fb90c8
L		 4967 overlap3 = operand_type_and (i.types[3],
4968 operand_types[3]);
d1cbb4db 4969 case 3:
c6fb90c8
L		 4970 overlap2 = operand_type_and (i.types[2],
4971 operand_types[2]);
d1cbb4db
L		 4972 break;
4973 }
29b0f896 4974
f48ff2ae
L		 4975 switch (t->operands)
4976 {
c0f3af97
L		 4977 case 5:
4978 if (!operand_type_match (overlap4, i.types[4])
4979 || !operand_type_register_match (overlap3,
4980 i.types[3],
4981 operand_types[3],
4982 overlap4,
4983 i.types[4],
4984 operand_types[4]))
4985 continue;
f48ff2ae 4986 case 4:
40fb9820 4987 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4988 || (check_register
4989 && !operand_type_register_match (overlap2,
4990 i.types[2],
4991 operand_types[2],
4992 overlap3,
4993 i.types[3],
4994 operand_types[3])))
f48ff2ae
L		 4995 continue;
4996 case 3:
4997 /* Here we make use of the fact that there are no
4998 reverse match 3 operand instructions, and all 3
4999 operand instructions only need to be checked for
5000 register consistency between operands 2 and 3. */
40fb9820 5001 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5002 || (check_register
5003 && !operand_type_register_match (overlap1,
5004 i.types[1],
5005 operand_types[1],
5006 overlap2,
5007 i.types[2],
5008 operand_types[2])))
f48ff2ae
L		 5009 continue;
5010 break;
5011 }
29b0f896 5012 }
f48ff2ae 5013 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5014 slip through to break. */
5015 }
3629bb00 5016 if (!found_cpu_match)
29b0f896
AM		 5017 {
5018 found_reverse_match = 0;
5019 continue;
5020 }
c0f3af97 5021
5614d22c
JB		 5022 /* Check if vector and VEX operands are valid. */
5023 if (check_VecOperands (t) || VEX_check_operands (t))
5024 {
5025 specific_error = i.error;
5026 continue;
5027 }
a683cc34 5028
29b0f896
AM		 5029 /* We've found a match; break out of loop. */
5030 break;
5031 }
5032
5033 if (t == current_templates->end)
5034 {
5035 /* We found no match. */
a65babc9 5036 const char *err_msg;
5614d22c 5037 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5038 {
5039 default:
5040 abort ();
86e026a4 5041 case operand_size_mismatch:
a65babc9
L		 5042 err_msg = _("operand size mismatch");
5043 break;
5044 case operand_type_mismatch:
5045 err_msg = _("operand type mismatch");
5046 break;
5047 case register_type_mismatch:
5048 err_msg = _("register type mismatch");
5049 break;
5050 case number_of_operands_mismatch:
5051 err_msg = _("number of operands mismatch");
5052 break;
5053 case invalid_instruction_suffix:
5054 err_msg = _("invalid instruction suffix");
5055 break;
5056 case bad_imm4:
4a2608e3 5057 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5058 break;
5059 case old_gcc_only:
5060 err_msg = _("only supported with old gcc");
5061 break;
5062 case unsupported_with_intel_mnemonic:
5063 err_msg = _("unsupported with Intel mnemonic");
5064 break;
5065 case unsupported_syntax:
5066 err_msg = _("unsupported syntax");
5067 break;
5068 case unsupported:
35262a23 5069 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5070 current_templates->start->name);
5071 return NULL;
6c30d220
L		 5072 case invalid_vsib_address:
5073 err_msg = _("invalid VSIB address");
5074 break;
7bab8ab5
JB		 5075 case invalid_vector_register_set:
5076 err_msg = _("mask, index, and destination registers must be distinct");
5077 break;
6c30d220
L		 5078 case unsupported_vector_index_register:
5079 err_msg = _("unsupported vector index register");
5080 break;
43234a1e
L		 5081 case unsupported_broadcast:
5082 err_msg = _("unsupported broadcast");
5083 break;
5084 case broadcast_not_on_src_operand:
5085 err_msg = _("broadcast not on source memory operand");
5086 break;
5087 case broadcast_needed:
5088 err_msg = _("broadcast is needed for operand of such type");
5089 break;
5090 case unsupported_masking:
5091 err_msg = _("unsupported masking");
5092 break;
5093 case mask_not_on_destination:
5094 err_msg = _("mask not on destination operand");
5095 break;
5096 case no_default_mask:
5097 err_msg = _("default mask isn't allowed");
5098 break;
5099 case unsupported_rc_sae:
5100 err_msg = _("unsupported static rounding/sae");
5101 break;
5102 case rc_sae_operand_not_last_imm:
5103 if (intel_syntax)
5104 err_msg = _("RC/SAE operand must precede immediate operands");
5105 else
5106 err_msg = _("RC/SAE operand must follow immediate operands");
5107 break;
5108 case invalid_register_operand:
5109 err_msg = _("invalid register operand");
5110 break;
a65babc9
L		 5111 }
5112 as_bad (_("%s for `%s'"), err_msg,
891edac4 5113 current_templates->start->name);
fa99fab2 5114 return NULL;
29b0f896 5115 }
252b5132 5116
29b0f896
AM		 5117 if (!quiet_warnings)
5118 {
5119 if (!intel_syntax
40fb9820
L		 5120 && (i.types[0].bitfield.jumpabsolute
5121 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5122 {
5123 as_warn (_("indirect %s without `*'"), t->name);
5124 }
5125
40fb9820
L		 5126 if (t->opcode_modifier.isprefix
5127 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5128 {
5129 /* Warn them that a data or address size prefix doesn't
5130 affect assembly of the next line of code. */
5131 as_warn (_("stand-alone `%s' prefix"), t->name);
5132 }
5133 }
5134
5135 /* Copy the template we found. */
5136 i.tm = *t;
539e75ad
L		 5137
5138 if (addr_prefix_disp != -1)
5139 i.tm.operand_types[addr_prefix_disp]
5140 = operand_types[addr_prefix_disp];
5141
29b0f896
AM		 5142 if (found_reverse_match)
5143 {
5144 /* If we found a reverse match we must alter the opcode
5145 direction bit. found_reverse_match holds bits to change
5146 (different for int & float insns). */
5147
5148 i.tm.base_opcode ^= found_reverse_match;
5149
539e75ad
L		 5150 i.tm.operand_types[0] = operand_types[1];
5151 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5152 }
5153
fa99fab2 5154 return t;
29b0f896
AM		 5155}
5156
5157static int
e3bb37b5 5158check_string (void)
29b0f896 5159{
40fb9820
L		 5160 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5161 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5162 {
5163 if (i.seg[0] != NULL && i.seg[0] != &es)
5164 {
a87af027 5165 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5166 i.tm.name,
a87af027
JB		 5167 mem_op + 1,
5168 register_prefix);
29b0f896
AM		 5169 return 0;
5170 }
5171 /* There's only ever one segment override allowed per instruction.
5172 This instruction possibly has a legal segment override on the
5173 second operand, so copy the segment to where non-string
5174 instructions store it, allowing common code. */
5175 i.seg[0] = i.seg[1];
5176 }
40fb9820 5177 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5178 {
5179 if (i.seg[1] != NULL && i.seg[1] != &es)
5180 {
a87af027 5181 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5182 i.tm.name,
a87af027
JB		 5183 mem_op + 2,
5184 register_prefix);
29b0f896
AM		 5185 return 0;
5186 }
5187 }
5188 return 1;
5189}
5190
5191static int
543613e9 5192process_suffix (void)
29b0f896
AM		 5193{
5194 /* If matched instruction specifies an explicit instruction mnemonic
5195 suffix, use it. */
40fb9820
L		 5196 if (i.tm.opcode_modifier.size16)
5197 i.suffix = WORD_MNEM_SUFFIX;
5198 else if (i.tm.opcode_modifier.size32)
5199 i.suffix = LONG_MNEM_SUFFIX;
5200 else if (i.tm.opcode_modifier.size64)
5201 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5202 else if (i.reg_operands)
5203 {
5204 /* If there's no instruction mnemonic suffix we try to invent one
5205 based on register operands. */
5206 if (!i.suffix)
5207 {
5208 /* We take i.suffix from the last register operand specified,
5209 Destination register type is more significant than source
381d071f
L		 5210 register type. crc32 in SSE4.2 prefers source register
5211 type. */
5212 if (i.tm.base_opcode == 0xf20f38f1)
5213 {
40fb9820
L		 5214 if (i.types[0].bitfield.reg16)
5215 i.suffix = WORD_MNEM_SUFFIX;
5216 else if (i.types[0].bitfield.reg32)
5217 i.suffix = LONG_MNEM_SUFFIX;
5218 else if (i.types[0].bitfield.reg64)
5219 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5220 }
9344ff29 5221 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5222 {
40fb9820 5223 if (i.types[0].bitfield.reg8)
20592a94
L		 5224 i.suffix = BYTE_MNEM_SUFFIX;
5225 }
381d071f
L		 5226
5227 if (!i.suffix)
5228 {
5229 int op;
5230
20592a94
L		 5231 if (i.tm.base_opcode == 0xf20f38f1
5232 || i.tm.base_opcode == 0xf20f38f0)
5233 {
5234 /* We have to know the operand size for crc32. */
5235 as_bad (_("ambiguous memory operand size for `%s`"),
5236 i.tm.name);
5237 return 0;
5238 }
5239
381d071f 5240 for (op = i.operands; --op >= 0;)
40fb9820 5241 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5242 {
40fb9820
L		 5243 if (i.types[op].bitfield.reg8)
5244 {
5245 i.suffix = BYTE_MNEM_SUFFIX;
5246 break;
5247 }
5248 else if (i.types[op].bitfield.reg16)
5249 {
5250 i.suffix = WORD_MNEM_SUFFIX;
5251 break;
5252 }
5253 else if (i.types[op].bitfield.reg32)
5254 {
5255 i.suffix = LONG_MNEM_SUFFIX;
5256 break;
5257 }
5258 else if (i.types[op].bitfield.reg64)
5259 {
5260 i.suffix = QWORD_MNEM_SUFFIX;
5261 break;
5262 }
381d071f
L		 5263 }
5264 }
29b0f896
AM		 5265 }
5266 else if (i.suffix == BYTE_MNEM_SUFFIX)
5267 {
2eb952a4
L		 5268 if (intel_syntax
5269 && i.tm.opcode_modifier.ignoresize
5270 && i.tm.opcode_modifier.no_bsuf)
5271 i.suffix = 0;
5272 else if (!check_byte_reg ())
29b0f896
AM		 5273 return 0;
5274 }
5275 else if (i.suffix == LONG_MNEM_SUFFIX)
5276 {
2eb952a4
L		 5277 if (intel_syntax
5278 && i.tm.opcode_modifier.ignoresize
5279 && i.tm.opcode_modifier.no_lsuf)
5280 i.suffix = 0;
5281 else if (!check_long_reg ())
29b0f896
AM		 5282 return 0;
5283 }
5284 else if (i.suffix == QWORD_MNEM_SUFFIX)
5285 {
955e1e6a
L		 5286 if (intel_syntax
5287 && i.tm.opcode_modifier.ignoresize
5288 && i.tm.opcode_modifier.no_qsuf)
5289 i.suffix = 0;
5290 else if (!check_qword_reg ())
29b0f896
AM		 5291 return 0;
5292 }
5293 else if (i.suffix == WORD_MNEM_SUFFIX)
5294 {
2eb952a4
L		 5295 if (intel_syntax
5296 && i.tm.opcode_modifier.ignoresize
5297 && i.tm.opcode_modifier.no_wsuf)
5298 i.suffix = 0;
5299 else if (!check_word_reg ())
29b0f896
AM		 5300 return 0;
5301 }
c0f3af97 5302 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5303 || i.suffix == YMMWORD_MNEM_SUFFIX
5304 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5305 {
43234a1e 5306 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5307 should check if it is a valid suffix. */
5308 }
40fb9820 5309 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5310 /* Do nothing if the instruction is going to ignore the prefix. */
5311 ;
5312 else
5313 abort ();
5314 }
40fb9820 5315 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5316 && !i.suffix
5317 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5318 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5319 {
5320 i.suffix = stackop_size;
5321 }
9306ca4a
JB		 5322 else if (intel_syntax
5323 && !i.suffix
40fb9820
L		 5324 && (i.tm.operand_types[0].bitfield.jumpabsolute
5325 || i.tm.opcode_modifier.jumpbyte
5326 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5327 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5328 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5329 {
5330 switch (flag_code)
5331 {
5332 case CODE_64BIT:
40fb9820 5333 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5334 {
5335 i.suffix = QWORD_MNEM_SUFFIX;
5336 break;
5337 }
5338 case CODE_32BIT:
40fb9820 5339 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5340 i.suffix = LONG_MNEM_SUFFIX;
5341 break;
5342 case CODE_16BIT:
40fb9820 5343 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5344 i.suffix = WORD_MNEM_SUFFIX;
5345 break;
5346 }
5347 }
252b5132 5348
9306ca4a 5349 if (!i.suffix)
29b0f896 5350 {
9306ca4a
JB		 5351 if (!intel_syntax)
5352 {
40fb9820 5353 if (i.tm.opcode_modifier.w)
9306ca4a 5354 {
4eed87de
AM		 5355 as_bad (_("no instruction mnemonic suffix given and "
5356 "no register operands; can't size instruction"));
9306ca4a
JB		 5357 return 0;
5358 }
5359 }
5360 else
5361 {
40fb9820 5362 unsigned int suffixes;
7ab9ffdd 5363
40fb9820
L		 5364 suffixes = !i.tm.opcode_modifier.no_bsuf;
5365 if (!i.tm.opcode_modifier.no_wsuf)
5366 suffixes |= 1 << 1;
5367 if (!i.tm.opcode_modifier.no_lsuf)
5368 suffixes |= 1 << 2;
fc4adea1 5369 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5370 suffixes |= 1 << 3;
5371 if (!i.tm.opcode_modifier.no_ssuf)
5372 suffixes |= 1 << 4;
5373 if (!i.tm.opcode_modifier.no_qsuf)
5374 suffixes |= 1 << 5;
5375
5376 /* There are more than suffix matches. */
5377 if (i.tm.opcode_modifier.w
9306ca4a 5378 || ((suffixes & (suffixes - 1))
40fb9820
L		 5379 && !i.tm.opcode_modifier.defaultsize
5380 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5381 {
5382 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5383 return 0;
5384 }
5385 }
29b0f896 5386 }
252b5132 5387
9306ca4a
JB		 5388 /* Change the opcode based on the operand size given by i.suffix;
5389 We don't need to change things for byte insns. */
5390
582d5edd
L		 5391 if (i.suffix
5392 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5393 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5394 && i.suffix != YMMWORD_MNEM_SUFFIX
5395 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5396 {
5397 /* It's not a byte, select word/dword operation. */
40fb9820 5398 if (i.tm.opcode_modifier.w)
29b0f896 5399 {
40fb9820 5400 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5401 i.tm.base_opcode |= 8;
5402 else
5403 i.tm.base_opcode |= 1;
5404 }
0f3f3d8b 5405
29b0f896
AM		 5406 /* Now select between word & dword operations via the operand
5407 size prefix, except for instructions that will ignore this
5408 prefix anyway. */
ca61edf2 5409 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5410 {
ca61edf2
L		 5411 /* The address size override prefix changes the size of the
5412 first operand. */
40fb9820
L		 5413 if ((flag_code == CODE_32BIT
5414 && i.op->regs[0].reg_type.bitfield.reg16)
5415 || (flag_code != CODE_32BIT
5416 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5417 if (!add_prefix (ADDR_PREFIX_OPCODE))
5418 return 0;
5419 }
5420 else if (i.suffix != QWORD_MNEM_SUFFIX
5421 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5422 && !i.tm.opcode_modifier.ignoresize
5423 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5424 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5425 || (flag_code == CODE_64BIT
40fb9820 5426 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5427 {
5428 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5429
40fb9820 5430 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5431 prefix = ADDR_PREFIX_OPCODE;
252b5132 5432
29b0f896
AM		 5433 if (!add_prefix (prefix))
5434 return 0;
24eab124 5435 }
252b5132 5436
29b0f896
AM		 5437 /* Set mode64 for an operand. */
5438 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5439 && flag_code == CODE_64BIT
40fb9820 5440 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5441 {
5442 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5443 need rex64. cmpxchg8b is also a special case. */
5444 if (! (i.operands == 2
5445 && i.tm.base_opcode == 0x90
5446 && i.tm.extension_opcode == None
0dfbf9d7
L		 5447 && operand_type_equal (&i.types [0], &acc64)
5448 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5449 && ! (i.operands == 1
5450 && i.tm.base_opcode == 0xfc7
5451 && i.tm.extension_opcode == 1
40fb9820
L		 5452 && !operand_type_check (i.types [0], reg)
5453 && operand_type_check (i.types [0], anymem)))
f6bee062 5454 i.rex |= REX_W;
46e883c5 5455 }
3e73aa7c 5456
29b0f896
AM		 5457 /* Size floating point instruction. */
5458 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5459 if (i.tm.opcode_modifier.floatmf)
543613e9 5460 i.tm.base_opcode ^= 4;
29b0f896 5461 }
7ecd2f8b 5462
29b0f896
AM		 5463 return 1;
5464}
3e73aa7c 5465
29b0f896 5466static int
543613e9 5467check_byte_reg (void)
29b0f896
AM		 5468{
5469 int op;
543613e9 5470
29b0f896
AM		 5471 for (op = i.operands; --op >= 0;)
5472 {
5473 /* If this is an eight bit register, it's OK. If it's the 16 or
5474 32 bit version of an eight bit register, we will just use the
5475 low portion, and that's OK too. */
40fb9820 5476 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5477 continue;
5478
5a819eb9
JB		 5479 /* I/O port address operands are OK too. */
5480 if (i.tm.operand_types[op].bitfield.inoutportreg)
5481 continue;
5482
9344ff29
L		 5483 /* crc32 doesn't generate this warning. */
5484 if (i.tm.base_opcode == 0xf20f38f0)
5485 continue;
5486
40fb9820
L		 5487 if ((i.types[op].bitfield.reg16
5488 || i.types[op].bitfield.reg32
5489 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5490 && i.op[op].regs->reg_num < 4
5491 /* Prohibit these changes in 64bit mode, since the lowering
5492 would be more complicated. */
5493 && flag_code != CODE_64BIT)
29b0f896 5494 {
29b0f896 5495#if REGISTER_WARNINGS
5a819eb9 5496 if (!quiet_warnings)
a540244d
L		 5497 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5498 register_prefix,
40fb9820 5499 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5500 ? REGNAM_AL - REGNAM_AX
5501 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5502 register_prefix,
29b0f896
AM		 5503 i.op[op].regs->reg_name,
5504 i.suffix);
5505#endif
5506 continue;
5507 }
5508 /* Any other register is bad. */
40fb9820
L		 5509 if (i.types[op].bitfield.reg16
5510 || i.types[op].bitfield.reg32
5511 || i.types[op].bitfield.reg64
5512 || i.types[op].bitfield.regmmx
5513 || i.types[op].bitfield.regxmm
c0f3af97 5514 || i.types[op].bitfield.regymm
43234a1e 5515 || i.types[op].bitfield.regzmm
40fb9820
L		 5516 || i.types[op].bitfield.sreg2
5517 || i.types[op].bitfield.sreg3
5518 || i.types[op].bitfield.control
5519 || i.types[op].bitfield.debug
5520 || i.types[op].bitfield.test
5521 || i.types[op].bitfield.floatreg
5522 || i.types[op].bitfield.floatacc)
29b0f896 5523 {
a540244d
L		 5524 as_bad (_("`%s%s' not allowed with `%s%c'"),
5525 register_prefix,
29b0f896
AM		 5526 i.op[op].regs->reg_name,
5527 i.tm.name,
5528 i.suffix);
5529 return 0;
5530 }
5531 }
5532 return 1;
5533}
5534
5535static int
e3bb37b5 5536check_long_reg (void)
29b0f896
AM		 5537{
5538 int op;
5539
5540 for (op = i.operands; --op >= 0;)
5541 /* Reject eight bit registers, except where the template requires
5542 them. (eg. movzb) */
40fb9820
L		 5543 if (i.types[op].bitfield.reg8
5544 && (i.tm.operand_types[op].bitfield.reg16
5545 || i.tm.operand_types[op].bitfield.reg32
5546 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5547 {
a540244d
L		 5548 as_bad (_("`%s%s' not allowed with `%s%c'"),
5549 register_prefix,
29b0f896
AM		 5550 i.op[op].regs->reg_name,
5551 i.tm.name,
5552 i.suffix);
5553 return 0;
5554 }
e4630f71 5555 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5556 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5557 && i.types[op].bitfield.reg16
5558 && (i.tm.operand_types[op].bitfield.reg32
5559 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5560 {
5561 /* Prohibit these changes in the 64bit mode, since the
5562 lowering is more complicated. */
5563 if (flag_code == CODE_64BIT)
252b5132 5564 {
2b5d6a91 5565 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5566 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5567 i.suffix);
5568 return 0;
252b5132 5569 }
29b0f896 5570#if REGISTER_WARNINGS
cecf1424
JB		 5571 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5572 register_prefix,
5573 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5574 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5575#endif
252b5132 5576 }
e4630f71 5577 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5578 else if (i.types[op].bitfield.reg64
5579 && (i.tm.operand_types[op].bitfield.reg32
5580 || i.tm.operand_types[op].bitfield.acc))
252b5132 5581 {
34828aad 5582 if (intel_syntax
ca61edf2 5583 && i.tm.opcode_modifier.toqword
40fb9820 5584 && !i.types[0].bitfield.regxmm)
34828aad 5585 {
ca61edf2 5586 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5587 i.suffix = QWORD_MNEM_SUFFIX;
5588 }
5589 else
5590 {
2b5d6a91 5591 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5592 register_prefix, i.op[op].regs->reg_name,
5593 i.suffix);
5594 return 0;
5595 }
29b0f896
AM		 5596 }
5597 return 1;
5598}
252b5132 5599
29b0f896 5600static int
e3bb37b5 5601check_qword_reg (void)
29b0f896
AM		 5602{
5603 int op;
252b5132 5604
29b0f896
AM		 5605 for (op = i.operands; --op >= 0; )
5606 /* Reject eight bit registers, except where the template requires
5607 them. (eg. movzb) */
40fb9820
L		 5608 if (i.types[op].bitfield.reg8
5609 && (i.tm.operand_types[op].bitfield.reg16
5610 || i.tm.operand_types[op].bitfield.reg32
5611 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5612 {
a540244d
L		 5613 as_bad (_("`%s%s' not allowed with `%s%c'"),
5614 register_prefix,
29b0f896
AM		 5615 i.op[op].regs->reg_name,
5616 i.tm.name,
5617 i.suffix);
5618 return 0;
5619 }
e4630f71 5620 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5621 else if ((i.types[op].bitfield.reg16
5622 || i.types[op].bitfield.reg32)
5623 && (i.tm.operand_types[op].bitfield.reg32
5624 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5625 {
5626 /* Prohibit these changes in the 64bit mode, since the
5627 lowering is more complicated. */
34828aad 5628 if (intel_syntax
ca61edf2 5629 && i.tm.opcode_modifier.todword
40fb9820 5630 && !i.types[0].bitfield.regxmm)
34828aad 5631 {
ca61edf2 5632 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5633 i.suffix = LONG_MNEM_SUFFIX;
5634 }
5635 else
5636 {
2b5d6a91 5637 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5638 register_prefix, i.op[op].regs->reg_name,
5639 i.suffix);
5640 return 0;
5641 }
252b5132 5642 }
29b0f896
AM		 5643 return 1;
5644}
252b5132 5645
29b0f896 5646static int
e3bb37b5 5647check_word_reg (void)
29b0f896
AM		 5648{
5649 int op;
5650 for (op = i.operands; --op >= 0;)
5651 /* Reject eight bit registers, except where the template requires
5652 them. (eg. movzb) */
40fb9820
L		 5653 if (i.types[op].bitfield.reg8
5654 && (i.tm.operand_types[op].bitfield.reg16
5655 || i.tm.operand_types[op].bitfield.reg32
5656 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5657 {
a540244d
L		 5658 as_bad (_("`%s%s' not allowed with `%s%c'"),
5659 register_prefix,
29b0f896
AM		 5660 i.op[op].regs->reg_name,
5661 i.tm.name,
5662 i.suffix);
5663 return 0;
5664 }
e4630f71 5665 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5666 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5667 && (i.types[op].bitfield.reg32
5668 || i.types[op].bitfield.reg64)
40fb9820
L		 5669 && (i.tm.operand_types[op].bitfield.reg16
5670 || i.tm.operand_types[op].bitfield.acc))
252b5132 5671 {
29b0f896
AM		 5672 /* Prohibit these changes in the 64bit mode, since the
5673 lowering is more complicated. */
5674 if (flag_code == CODE_64BIT)
252b5132 5675 {
2b5d6a91 5676 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5677 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5678 i.suffix);
5679 return 0;
252b5132 5680 }
29b0f896 5681#if REGISTER_WARNINGS
cecf1424
JB		 5682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5683 register_prefix,
5684 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5685 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5686#endif
5687 }
5688 return 1;
5689}
252b5132 5690
29b0f896 5691static int
40fb9820 5692update_imm (unsigned int j)
29b0f896 5693{
bc0844ae 5694 i386_operand_type overlap = i.types[j];
40fb9820
L		 5695 if ((overlap.bitfield.imm8
5696 || overlap.bitfield.imm8s
5697 || overlap.bitfield.imm16
5698 || overlap.bitfield.imm32
5699 || overlap.bitfield.imm32s
5700 || overlap.bitfield.imm64)
0dfbf9d7
L		 5701 && !operand_type_equal (&overlap, &imm8)
5702 && !operand_type_equal (&overlap, &imm8s)
5703 && !operand_type_equal (&overlap, &imm16)
5704 && !operand_type_equal (&overlap, &imm32)
5705 && !operand_type_equal (&overlap, &imm32s)
5706 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5707 {
5708 if (i.suffix)
5709 {
40fb9820
L		 5710 i386_operand_type temp;
5711
0dfbf9d7 5712 operand_type_set (&temp, 0);
7ab9ffdd 5713 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5714 {
5715 temp.bitfield.imm8 = overlap.bitfield.imm8;
5716 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5717 }
5718 else if (i.suffix == WORD_MNEM_SUFFIX)
5719 temp.bitfield.imm16 = overlap.bitfield.imm16;
5720 else if (i.suffix == QWORD_MNEM_SUFFIX)
5721 {
5722 temp.bitfield.imm64 = overlap.bitfield.imm64;
5723 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5724 }
5725 else
5726 temp.bitfield.imm32 = overlap.bitfield.imm32;
5727 overlap = temp;
29b0f896 5728 }
0dfbf9d7
L		 5729 else if (operand_type_equal (&overlap, &imm16_32_32s)
5730 || operand_type_equal (&overlap, &imm16_32)
5731 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5732 {
40fb9820 5733 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5734 overlap = imm16;
40fb9820 5735 else
65da13b5 5736 overlap = imm32s;
29b0f896 5737 }
0dfbf9d7
L		 5738 if (!operand_type_equal (&overlap, &imm8)
5739 && !operand_type_equal (&overlap, &imm8s)
5740 && !operand_type_equal (&overlap, &imm16)
5741 && !operand_type_equal (&overlap, &imm32)
5742 && !operand_type_equal (&overlap, &imm32s)
5743 && !operand_type_equal (&overlap, &imm64))
29b0f896 5744 {
4eed87de
AM		 5745 as_bad (_("no instruction mnemonic suffix given; "
5746 "can't determine immediate size"));
29b0f896
AM		 5747 return 0;
5748 }
5749 }
40fb9820 5750 i.types[j] = overlap;
29b0f896 5751
40fb9820
L		 5752 return 1;
5753}
5754
5755static int
5756finalize_imm (void)
5757{
bc0844ae 5758 unsigned int j, n;
29b0f896 5759
bc0844ae
L		 5760 /* Update the first 2 immediate operands. */
5761 n = i.operands > 2 ? 2 : i.operands;
5762 if (n)
5763 {
5764 for (j = 0; j < n; j++)
5765 if (update_imm (j) == 0)
5766 return 0;
40fb9820 5767
bc0844ae
L		 5768 /* The 3rd operand can't be immediate operand. */
5769 gas_assert (operand_type_check (i.types[2], imm) == 0);
5770 }
29b0f896
AM		 5771
5772 return 1;
5773}
5774
c0f3af97
L		 5775static int
5776bad_implicit_operand (int xmm)
5777{
91d6fa6a
NC		 5778 const char *ireg = xmm ? "xmm0" : "ymm0";
5779
c0f3af97
L		 5780 if (intel_syntax)
5781 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5782 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5783 else
5784 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5785 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5786 return 0;
5787}
5788
29b0f896 5789static int
e3bb37b5 5790process_operands (void)
29b0f896
AM		 5791{
5792 /* Default segment register this instruction will use for memory
5793 accesses. 0 means unknown. This is only for optimizing out
5794 unnecessary segment overrides. */
5795 const seg_entry *default_seg = 0;
5796
2426c15f 5797 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5798 {
91d6fa6a
NC		 5799 unsigned int dupl = i.operands;
5800 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5801 unsigned int j;
5802
c0f3af97 5803 /* The destination must be an xmm register. */
9c2799c2 5804 gas_assert (i.reg_operands
91d6fa6a 5805 && MAX_OPERANDS > dupl
7ab9ffdd 5806 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5807
5808 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5809 {
c0f3af97 5810 /* The first operand is implicit and must be xmm0. */
9c2799c2 5811 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5812 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5813 return bad_implicit_operand (1);
5814
8cd7925b 5815 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5816 {
5817 /* Keep xmm0 for instructions with VEX prefix and 3
5818 sources. */
5819 goto duplicate;
5820 }
e2ec9d29 5821 else
c0f3af97
L		 5822 {
5823 /* We remove the first xmm0 and keep the number of
5824 operands unchanged, which in fact duplicates the
5825 destination. */
5826 for (j = 1; j < i.operands; j++)
5827 {
5828 i.op[j - 1] = i.op[j];
5829 i.types[j - 1] = i.types[j];
5830 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5831 }
5832 }
5833 }
5834 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5835 {
91d6fa6a 5836 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5837 && (i.tm.opcode_modifier.vexsources
5838 == VEX3SOURCES));
c0f3af97
L		 5839
5840 /* Add the implicit xmm0 for instructions with VEX prefix
5841 and 3 sources. */
5842 for (j = i.operands; j > 0; j--)
5843 {
5844 i.op[j] = i.op[j - 1];
5845 i.types[j] = i.types[j - 1];
5846 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5847 }
5848 i.op[0].regs
5849 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5850 i.types[0] = regxmm;
c0f3af97
L		 5851 i.tm.operand_types[0] = regxmm;
5852
5853 i.operands += 2;
5854 i.reg_operands += 2;
5855 i.tm.operands += 2;
5856
91d6fa6a 5857 dupl++;
c0f3af97 5858 dest++;
91d6fa6a
NC		 5859 i.op[dupl] = i.op[dest];
5860 i.types[dupl] = i.types[dest];
5861 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5862 }
c0f3af97
L		 5863 else
5864 {
5865duplicate:
5866 i.operands++;
5867 i.reg_operands++;
5868 i.tm.operands++;
5869
91d6fa6a
NC		 5870 i.op[dupl] = i.op[dest];
5871 i.types[dupl] = i.types[dest];
5872 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5873 }
5874
5875 if (i.tm.opcode_modifier.immext)
5876 process_immext ();
5877 }
5878 else if (i.tm.opcode_modifier.firstxmm0)
5879 {
5880 unsigned int j;
5881
43234a1e 5882 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5883 gas_assert (i.reg_operands
7ab9ffdd 5884 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5885 || operand_type_equal (&i.types[0], &regymm)
5886 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5887 if (register_number (i.op[0].regs) != 0)
c0f3af97 5888 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5889
5890 for (j = 1; j < i.operands; j++)
5891 {
5892 i.op[j - 1] = i.op[j];
5893 i.types[j - 1] = i.types[j];
5894
5895 /* We need to adjust fields in i.tm since they are used by
5896 build_modrm_byte. */
5897 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5898 }
5899
e2ec9d29
L		 5900 i.operands--;
5901 i.reg_operands--;
e2ec9d29
L		 5902 i.tm.operands--;
5903 }
5904 else if (i.tm.opcode_modifier.regkludge)
5905 {
5906 /* The imul $imm, %reg instruction is converted into
5907 imul $imm, %reg, %reg, and the clr %reg instruction
5908 is converted into xor %reg, %reg. */
5909
5910 unsigned int first_reg_op;
5911
5912 if (operand_type_check (i.types[0], reg))
5913 first_reg_op = 0;
5914 else
5915 first_reg_op = 1;
5916 /* Pretend we saw the extra register operand. */
9c2799c2 5917 gas_assert (i.reg_operands == 1
7ab9ffdd 5918 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5919 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5920 i.types[first_reg_op + 1] = i.types[first_reg_op];
5921 i.operands++;
5922 i.reg_operands++;
29b0f896
AM		 5923 }
5924
40fb9820 5925 if (i.tm.opcode_modifier.shortform)
29b0f896 5926 {
40fb9820
L		 5927 if (i.types[0].bitfield.sreg2
5928 || i.types[0].bitfield.sreg3)
29b0f896 5929 {
4eed87de
AM		 5930 if (i.tm.base_opcode == POP_SEG_SHORT
5931 && i.op[0].regs->reg_num == 1)
29b0f896 5932 {
a87af027 5933 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5934 return 0;
29b0f896 5935 }
4eed87de
AM		 5936 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5937 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5938 i.rex |= REX_B;
4eed87de
AM		 5939 }
5940 else
5941 {
7ab9ffdd 5942 /* The register or float register operand is in operand
85f10a01 5943 0 or 1. */
40fb9820 5944 unsigned int op;
7ab9ffdd
L		 5945
5946 if (i.types[0].bitfield.floatreg
5947 || operand_type_check (i.types[0], reg))
5948 op = 0;
5949 else
5950 op = 1;
4eed87de
AM		 5951 /* Register goes in low 3 bits of opcode. */
5952 i.tm.base_opcode |= i.op[op].regs->reg_num;
5953 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5954 i.rex |= REX_B;
40fb9820 5955 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5956 {
4eed87de
AM		 5957 /* Warn about some common errors, but press on regardless.
5958 The first case can be generated by gcc (<= 2.8.1). */
5959 if (i.operands == 2)
5960 {
5961 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5962 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5963 register_prefix, i.op[!intel_syntax].regs->reg_name,
5964 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5965 }
5966 else
5967 {
5968 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5969 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5970 register_prefix, i.op[0].regs->reg_name);
4eed87de 5971 }
29b0f896
AM		 5972 }
5973 }
5974 }
40fb9820 5975 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5976 {
5977 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5978 must be put into the modrm byte). Now, we make the modrm and
5979 index base bytes based on all the info we've collected. */
29b0f896
AM		 5980
5981 default_seg = build_modrm_byte ();
5982 }
8a2ed489 5983 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5984 {
5985 default_seg = &ds;
5986 }
40fb9820 5987 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5988 {
5989 /* For the string instructions that allow a segment override
5990 on one of their operands, the default segment is ds. */
5991 default_seg = &ds;
5992 }
5993
75178d9d
L		 5994 if (i.tm.base_opcode == 0x8d /* lea */
5995 && i.seg[0]
5996 && !quiet_warnings)
30123838 5997 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5998
5999 /* If a segment was explicitly specified, and the specified segment
6000 is not the default, use an opcode prefix to select it. If we
6001 never figured out what the default segment is, then default_seg
6002 will be zero at this point, and the specified segment prefix will
6003 always be used. */
29b0f896
AM		 6004 if ((i.seg[0]) && (i.seg[0] != default_seg))
6005 {
6006 if (!add_prefix (i.seg[0]->seg_prefix))
6007 return 0;
6008 }
6009 return 1;
6010}
6011
6012static const seg_entry *
e3bb37b5 6013build_modrm_byte (void)
29b0f896
AM		 6014{
6015 const seg_entry *default_seg = 0;
c0f3af97 6016 unsigned int source, dest;
8cd7925b 6017 int vex_3_sources;
c0f3af97
L		 6018
6019 /* The first operand of instructions with VEX prefix and 3 sources
6020 must be VEX_Imm4. */
8cd7925b 6021 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6022 if (vex_3_sources)
6023 {
91d6fa6a 6024 unsigned int nds, reg_slot;
4c2c6516 6025 expressionS *exp;
c0f3af97 6026
922d8de8 6027 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6028 && i.tm.opcode_modifier.immext)
6029 {
6030 dest = i.operands - 2;
6031 gas_assert (dest == 3);
6032 }
922d8de8 6033 else
a683cc34 6034 dest = i.operands - 1;
c0f3af97 6035 nds = dest - 1;
922d8de8 6036
a683cc34
SP		 6037 /* There are 2 kinds of instructions:
6038 1. 5 operands: 4 register operands or 3 register operands
6039 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6040 VexW0 or VexW1. The destination must be either XMM, YMM or
6041 ZMM register.
a683cc34
SP		 6042 2. 4 operands: 4 register operands or 3 register operands
6043 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6044 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6045 || (i.reg_operands == 3 && i.mem_operands == 1))
6046 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6047 && (i.tm.opcode_modifier.veximmext
6048 || (i.imm_operands == 1
6049 && i.types[0].bitfield.vec_imm4
6050 && (i.tm.opcode_modifier.vexw == VEXW0
6051 || i.tm.opcode_modifier.vexw == VEXW1)
6052 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6053 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6054 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6055
6056 if (i.imm_operands == 0)
6057 {
6058 /* When there is no immediate operand, generate an 8bit
6059 immediate operand to encode the first operand. */
6060 exp = &im_expressions[i.imm_operands++];
6061 i.op[i.operands].imms = exp;
6062 i.types[i.operands] = imm8;
6063 i.operands++;
6064 /* If VexW1 is set, the first operand is the source and
6065 the second operand is encoded in the immediate operand. */
6066 if (i.tm.opcode_modifier.vexw == VEXW1)
6067 {
6068 source = 0;
6069 reg_slot = 1;
6070 }
6071 else
6072 {
6073 source = 1;
6074 reg_slot = 0;
6075 }
6076
6077 /* FMA swaps REG and NDS. */
6078 if (i.tm.cpu_flags.bitfield.cpufma)
6079 {
6080 unsigned int tmp;
6081 tmp = reg_slot;
6082 reg_slot = nds;
6083 nds = tmp;
6084 }
6085
24981e7b
L		 6086 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6087 &regxmm)
a683cc34 6088 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6089 &regymm)
6090 || operand_type_equal (&i.tm.operand_types[reg_slot],
6091 &regzmm));
a683cc34 6092 exp->X_op = O_constant;
4c692bc7 6093 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6094 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6095 }
922d8de8 6096 else
a683cc34
SP		 6097 {
6098 unsigned int imm_slot;
6099
6100 if (i.tm.opcode_modifier.vexw == VEXW0)
6101 {
6102 /* If VexW0 is set, the third operand is the source and
6103 the second operand is encoded in the immediate
6104 operand. */
6105 source = 2;
6106 reg_slot = 1;
6107 }
6108 else
6109 {
6110 /* VexW1 is set, the second operand is the source and
6111 the third operand is encoded in the immediate
6112 operand. */
6113 source = 1;
6114 reg_slot = 2;
6115 }
6116
6117 if (i.tm.opcode_modifier.immext)
6118 {
6119 /* When ImmExt is set, the immdiate byte is the last
6120 operand. */
6121 imm_slot = i.operands - 1;
6122 source--;
6123 reg_slot--;
6124 }
6125 else
6126 {
6127 imm_slot = 0;
6128
6129 /* Turn on Imm8 so that output_imm will generate it. */
6130 i.types[imm_slot].bitfield.imm8 = 1;
6131 }
6132
24981e7b
L		 6133 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6134 &regxmm)
6135 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6136 &regymm)
6137 || operand_type_equal (&i.tm.operand_types[reg_slot],
6138 &regzmm));
a683cc34 6139 i.op[imm_slot].imms->X_add_number
4c692bc7 6140 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6141 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6142 }
6143
6144 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6145 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6146 &regymm)
6147 || operand_type_equal (&i.tm.operand_types[nds],
6148 &regzmm));
dae39acc 6149 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6150 }
6151 else
6152 source = dest = 0;
29b0f896
AM		 6153
6154 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6155 implicit registers do not count. If there are 3 register
6156 operands, it must be a instruction with VexNDS. For a
6157 instruction with VexNDD, the destination register is encoded
6158 in VEX prefix. If there are 4 register operands, it must be
6159 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6160 if (i.mem_operands == 0
6161 && ((i.reg_operands == 2
2426c15f 6162 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6163 || (i.reg_operands == 3
2426c15f 6164 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6165 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6166 {
cab737b9
L		 6167 switch (i.operands)
6168 {
6169 case 2:
6170 source = 0;
6171 break;
6172 case 3:
c81128dc
L		 6173 /* When there are 3 operands, one of them may be immediate,
6174 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6175 the first operand must be shift count register (cl) or it
6176 is an instruction with VexNDS. */
9c2799c2 6177 gas_assert (i.imm_operands == 1
7ab9ffdd 6178 || (i.imm_operands == 0
2426c15f 6179 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6180 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6181 if (operand_type_check (i.types[0], imm)
6182 || i.types[0].bitfield.shiftcount)
6183 source = 1;
6184 else
6185 source = 0;
cab737b9
L		 6186 break;
6187 case 4:
368d64cc
L		 6188 /* When there are 4 operands, the first two must be 8bit
6189 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6190 one.
6191
6192 For instructions with VexNDS, if the first operand
6193 an imm8, the source operand is the 2nd one. If the last
6194 operand is imm8, the source operand is the first one. */
9c2799c2 6195 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6196 && i.types[0].bitfield.imm8
6197 && i.types[1].bitfield.imm8)
2426c15f 6198 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6199 && i.imm_operands == 1
6200 && (i.types[0].bitfield.imm8
43234a1e
L		 6201 || i.types[i.operands - 1].bitfield.imm8
6202 || i.rounding)));
9f2670f2
L		 6203 if (i.imm_operands == 2)
6204 source = 2;
6205 else
c0f3af97
L		 6206 {
6207 if (i.types[0].bitfield.imm8)
6208 source = 1;
6209 else
6210 source = 0;
6211 }
c0f3af97
L		 6212 break;
6213 case 5:
43234a1e
L		 6214 if (i.tm.opcode_modifier.evex)
6215 {
6216 /* For EVEX instructions, when there are 5 operands, the
6217 first one must be immediate operand. If the second one
6218 is immediate operand, the source operand is the 3th
6219 one. If the last one is immediate operand, the source
6220 operand is the 2nd one. */
6221 gas_assert (i.imm_operands == 2
6222 && i.tm.opcode_modifier.sae
6223 && operand_type_check (i.types[0], imm));
6224 if (operand_type_check (i.types[1], imm))
6225 source = 2;
6226 else if (operand_type_check (i.types[4], imm))
6227 source = 1;
6228 else
6229 abort ();
6230 }
cab737b9
L		 6231 break;
6232 default:
6233 abort ();
6234 }
6235
c0f3af97
L		 6236 if (!vex_3_sources)
6237 {
6238 dest = source + 1;
6239
43234a1e
L		 6240 /* RC/SAE operand could be between DEST and SRC. That happens
6241 when one operand is GPR and the other one is XMM/YMM/ZMM
6242 register. */
6243 if (i.rounding && i.rounding->operand == (int) dest)
6244 dest++;
6245
2426c15f 6246 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6247 {
43234a1e
L		 6248 /* For instructions with VexNDS, the register-only source
6249 operand must be 32/64bit integer, XMM, YMM or ZMM
6250 register. It is encoded in VEX prefix. We need to
6251 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6252
6253 i386_operand_type op;
6254 unsigned int vvvv;
6255
6256 /* Check register-only source operand when two source
6257 operands are swapped. */
6258 if (!i.tm.operand_types[source].bitfield.baseindex
6259 && i.tm.operand_types[dest].bitfield.baseindex)
6260 {
6261 vvvv = source;
6262 source = dest;
6263 }
6264 else
6265 vvvv = dest;
6266
6267 op = i.tm.operand_types[vvvv];
fa99fab2 6268 op.bitfield.regmem = 0;
c0f3af97 6269 if ((dest + 1) >= i.operands
ac4eb736
AM		 6270 || (!op.bitfield.reg32
6271 && op.bitfield.reg64
f12dc422 6272 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6273 && !operand_type_equal (&op, &regymm)
6274 && !operand_type_equal (&op, &regzmm)
6275 && !operand_type_equal (&op, &regmask)))
c0f3af97 6276 abort ();
f12dc422 6277 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6278 dest++;
6279 }
6280 }
29b0f896
AM		 6281
6282 i.rm.mode = 3;
6283 /* One of the register operands will be encoded in the i.tm.reg
6284 field, the other in the combined i.tm.mode and i.tm.regmem
6285 fields. If no form of this instruction supports a memory
6286 destination operand, then we assume the source operand may
6287 sometimes be a memory operand and so we need to store the
6288 destination in the i.rm.reg field. */
40fb9820
L		 6289 if (!i.tm.operand_types[dest].bitfield.regmem
6290 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6291 {
6292 i.rm.reg = i.op[dest].regs->reg_num;
6293 i.rm.regmem = i.op[source].regs->reg_num;
6294 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6295 i.rex |= REX_R;
43234a1e
L		 6296 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6297 i.vrex |= REX_R;
29b0f896 6298 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6299 i.rex |= REX_B;
43234a1e
L		 6300 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6301 i.vrex |= REX_B;
29b0f896
AM		 6302 }
6303 else
6304 {
6305 i.rm.reg = i.op[source].regs->reg_num;
6306 i.rm.regmem = i.op[dest].regs->reg_num;
6307 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6308 i.rex |= REX_B;
43234a1e
L		 6309 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6310 i.vrex |= REX_B;
29b0f896 6311 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6312 i.rex |= REX_R;
43234a1e
L		 6313 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6314 i.vrex |= REX_R;
29b0f896 6315 }
161a04f6 6316 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6317 {
40fb9820
L		 6318 if (!i.types[0].bitfield.control
6319 && !i.types[1].bitfield.control)
c4a530c5 6320 abort ();
161a04f6 6321 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6322 add_prefix (LOCK_PREFIX_OPCODE);
6323 }
29b0f896
AM		 6324 }
6325 else
6326 { /* If it's not 2 reg operands... */
c0f3af97
L		 6327 unsigned int mem;
6328
29b0f896
AM		 6329 if (i.mem_operands)
6330 {
6331 unsigned int fake_zero_displacement = 0;
99018f42 6332 unsigned int op;
4eed87de 6333
7ab9ffdd
L		 6334 for (op = 0; op < i.operands; op++)
6335 if (operand_type_check (i.types[op], anymem))
6336 break;
7ab9ffdd 6337 gas_assert (op < i.operands);
29b0f896 6338
6c30d220
L		 6339 if (i.tm.opcode_modifier.vecsib)
6340 {
6341 if (i.index_reg->reg_num == RegEiz
6342 || i.index_reg->reg_num == RegRiz)
6343 abort ();
6344
6345 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6346 if (!i.base_reg)
6347 {
6348 i.sib.base = NO_BASE_REGISTER;
6349 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6350 /* No Vec_Disp8 if there is no base. */
6351 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6352 i.types[op].bitfield.disp8 = 0;
6353 i.types[op].bitfield.disp16 = 0;
6354 i.types[op].bitfield.disp64 = 0;
6355 if (flag_code != CODE_64BIT)
6356 {
6357 /* Must be 32 bit */
6358 i.types[op].bitfield.disp32 = 1;
6359 i.types[op].bitfield.disp32s = 0;
6360 }
6361 else
6362 {
6363 i.types[op].bitfield.disp32 = 0;
6364 i.types[op].bitfield.disp32s = 1;
6365 }
6366 }
6367 i.sib.index = i.index_reg->reg_num;
6368 if ((i.index_reg->reg_flags & RegRex) != 0)
6369 i.rex |= REX_X;
43234a1e
L		 6370 if ((i.index_reg->reg_flags & RegVRex) != 0)
6371 i.vrex |= REX_X;
6c30d220
L		 6372 }
6373
29b0f896
AM		 6374 default_seg = &ds;
6375
6376 if (i.base_reg == 0)
6377 {
6378 i.rm.mode = 0;
6379 if (!i.disp_operands)
6c30d220
L		 6380 {
6381 fake_zero_displacement = 1;
6382 /* Instructions with VSIB byte need 32bit displacement
6383 if there is no base register. */
6384 if (i.tm.opcode_modifier.vecsib)
6385 i.types[op].bitfield.disp32 = 1;
6386 }
29b0f896
AM		 6387 if (i.index_reg == 0)
6388 {
6c30d220 6389 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6390 /* Operand is just <disp> */
20f0a1fc 6391 if (flag_code == CODE_64BIT)
29b0f896
AM		 6392 {
6393 /* 64bit mode overwrites the 32bit absolute
6394 addressing by RIP relative addressing and
6395 absolute addressing is encoded by one of the
6396 redundant SIB forms. */
6397 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6398 i.sib.base = NO_BASE_REGISTER;
6399 i.sib.index = NO_INDEX_REGISTER;
fc225355 6400 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6401 ? disp32s : disp32);
20f0a1fc 6402 }
fc225355
L		 6403 else if ((flag_code == CODE_16BIT)
6404 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6405 {
6406 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6407 i.types[op] = disp16;
20f0a1fc
NC		 6408 }
6409 else
6410 {
6411 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6412 i.types[op] = disp32;
29b0f896
AM		 6413 }
6414 }
6c30d220 6415 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6416 {
6c30d220 6417 /* !i.base_reg && i.index_reg */
db51cc60
L		 6418 if (i.index_reg->reg_num == RegEiz
6419 || i.index_reg->reg_num == RegRiz)
6420 i.sib.index = NO_INDEX_REGISTER;
6421 else
6422 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6423 i.sib.base = NO_BASE_REGISTER;
6424 i.sib.scale = i.log2_scale_factor;
6425 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6426 /* No Vec_Disp8 if there is no base. */
6427 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6428 i.types[op].bitfield.disp8 = 0;
6429 i.types[op].bitfield.disp16 = 0;
6430 i.types[op].bitfield.disp64 = 0;
29b0f896 6431 if (flag_code != CODE_64BIT)
40fb9820
L		 6432 {
6433 /* Must be 32 bit */
6434 i.types[op].bitfield.disp32 = 1;
6435 i.types[op].bitfield.disp32s = 0;
6436 }
29b0f896 6437 else
40fb9820
L		 6438 {
6439 i.types[op].bitfield.disp32 = 0;
6440 i.types[op].bitfield.disp32s = 1;
6441 }
29b0f896 6442 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6443 i.rex |= REX_X;
29b0f896
AM		 6444 }
6445 }
6446 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6447 else if (i.base_reg->reg_num == RegRip ||
6448 i.base_reg->reg_num == RegEip)
29b0f896 6449 {
6c30d220 6450 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6451 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6452 i.types[op].bitfield.disp8 = 0;
6453 i.types[op].bitfield.disp16 = 0;
6454 i.types[op].bitfield.disp32 = 0;
6455 i.types[op].bitfield.disp32s = 1;
6456 i.types[op].bitfield.disp64 = 0;
43234a1e 6457 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6458 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6459 if (! i.disp_operands)
6460 fake_zero_displacement = 1;
29b0f896 6461 }
40fb9820 6462 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6463 {
6c30d220 6464 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6465 switch (i.base_reg->reg_num)
6466 {
6467 case 3: /* (%bx) */
6468 if (i.index_reg == 0)
6469 i.rm.regmem = 7;
6470 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6471 i.rm.regmem = i.index_reg->reg_num - 6;
6472 break;
6473 case 5: /* (%bp) */
6474 default_seg = &ss;
6475 if (i.index_reg == 0)
6476 {
6477 i.rm.regmem = 6;
40fb9820 6478 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6479 {
6480 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6481 if (i.tm.operand_types[op].bitfield.vec_disp8)
6482 i.types[op].bitfield.vec_disp8 = 1;
6483 else
6484 i.types[op].bitfield.disp8 = 1;
252b5132 6485 fake_zero_displacement = 1;
29b0f896
AM		 6486 }
6487 }
6488 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6489 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6490 break;
6491 default: /* (%si) -> 4 or (%di) -> 5 */
6492 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6493 }
6494 i.rm.mode = mode_from_disp_size (i.types[op]);
6495 }
6496 else /* i.base_reg and 32/64 bit mode */
6497 {
6498 if (flag_code == CODE_64BIT
40fb9820
L		 6499 && operand_type_check (i.types[op], disp))
6500 {
6501 i386_operand_type temp;
0dfbf9d7 6502 operand_type_set (&temp, 0);
40fb9820 6503 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6504 temp.bitfield.vec_disp8
6505 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6506 i.types[op] = temp;
6507 if (i.prefix[ADDR_PREFIX] == 0)
6508 i.types[op].bitfield.disp32s = 1;
6509 else
6510 i.types[op].bitfield.disp32 = 1;
6511 }
20f0a1fc 6512
6c30d220
L		 6513 if (!i.tm.opcode_modifier.vecsib)
6514 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6515 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6516 i.rex |= REX_B;
29b0f896
AM		 6517 i.sib.base = i.base_reg->reg_num;
6518 /* x86-64 ignores REX prefix bit here to avoid decoder
6519 complications. */
848930b2
JB		 6520 if (!(i.base_reg->reg_flags & RegRex)
6521 && (i.base_reg->reg_num == EBP_REG_NUM
6522 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6523 default_seg = &ss;
848930b2 6524 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6525 {
848930b2 6526 fake_zero_displacement = 1;
43234a1e
L		 6527 if (i.tm.operand_types [op].bitfield.vec_disp8)
6528 i.types[op].bitfield.vec_disp8 = 1;
6529 else
6530 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6531 }
6532 i.sib.scale = i.log2_scale_factor;
6533 if (i.index_reg == 0)
6534 {
6c30d220 6535 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6536 /* <disp>(%esp) becomes two byte modrm with no index
6537 register. We've already stored the code for esp
6538 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6539 Any base register besides %esp will not use the
6540 extra modrm byte. */
6541 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6542 }
6c30d220 6543 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6544 {
db51cc60
L		 6545 if (i.index_reg->reg_num == RegEiz
6546 || i.index_reg->reg_num == RegRiz)
6547 i.sib.index = NO_INDEX_REGISTER;
6548 else
6549 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6550 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6551 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6552 i.rex |= REX_X;
29b0f896 6553 }
67a4f2b7
AO		 6554
6555 if (i.disp_operands
6556 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6557 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6558 i.rm.mode = 0;
6559 else
a501d77e
L		 6560 {
6561 if (!fake_zero_displacement
6562 && !i.disp_operands
6563 && i.disp_encoding)
6564 {
6565 fake_zero_displacement = 1;
6566 if (i.disp_encoding == disp_encoding_8bit)
6567 i.types[op].bitfield.disp8 = 1;
6568 else
6569 i.types[op].bitfield.disp32 = 1;
6570 }
6571 i.rm.mode = mode_from_disp_size (i.types[op]);
6572 }
29b0f896 6573 }
252b5132 6574
29b0f896
AM		 6575 if (fake_zero_displacement)
6576 {
6577 /* Fakes a zero displacement assuming that i.types[op]
6578 holds the correct displacement size. */
6579 expressionS *exp;
6580
9c2799c2 6581 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6582 exp = &disp_expressions[i.disp_operands++];
6583 i.op[op].disps = exp;
6584 exp->X_op = O_constant;
6585 exp->X_add_number = 0;
6586 exp->X_add_symbol = (symbolS *) 0;
6587 exp->X_op_symbol = (symbolS *) 0;
6588 }
c0f3af97
L		 6589
6590 mem = op;
29b0f896 6591 }
c0f3af97
L		 6592 else
6593 mem = ~0;
252b5132 6594
8c43a48b 6595 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6596 {
6597 if (operand_type_check (i.types[0], imm))
6598 i.vex.register_specifier = NULL;
6599 else
6600 {
6601 /* VEX.vvvv encodes one of the sources when the first
6602 operand is not an immediate. */
1ef99a7b 6603 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6604 i.vex.register_specifier = i.op[0].regs;
6605 else
6606 i.vex.register_specifier = i.op[1].regs;
6607 }
6608
6609 /* Destination is a XMM register encoded in the ModRM.reg
6610 and VEX.R bit. */
6611 i.rm.reg = i.op[2].regs->reg_num;
6612 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6613 i.rex |= REX_R;
6614
6615 /* ModRM.rm and VEX.B encodes the other source. */
6616 if (!i.mem_operands)
6617 {
6618 i.rm.mode = 3;
6619
1ef99a7b 6620 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6621 i.rm.regmem = i.op[1].regs->reg_num;
6622 else
6623 i.rm.regmem = i.op[0].regs->reg_num;
6624
6625 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6626 i.rex |= REX_B;
6627 }
6628 }
2426c15f 6629 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6630 {
6631 i.vex.register_specifier = i.op[2].regs;
6632 if (!i.mem_operands)
6633 {
6634 i.rm.mode = 3;
6635 i.rm.regmem = i.op[1].regs->reg_num;
6636 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6637 i.rex |= REX_B;
6638 }
6639 }
29b0f896
AM		 6640 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6641 (if any) based on i.tm.extension_opcode. Again, we must be
6642 careful to make sure that segment/control/debug/test/MMX
6643 registers are coded into the i.rm.reg field. */
f88c9eb0 6644 else if (i.reg_operands)
29b0f896 6645 {
99018f42 6646 unsigned int op;
7ab9ffdd
L		 6647 unsigned int vex_reg = ~0;
6648
6649 for (op = 0; op < i.operands; op++)
6650 if (i.types[op].bitfield.reg8
6651 || i.types[op].bitfield.reg16
6652 || i.types[op].bitfield.reg32
6653 || i.types[op].bitfield.reg64
6654 || i.types[op].bitfield.regmmx
6655 || i.types[op].bitfield.regxmm
6656 || i.types[op].bitfield.regymm
7e8b059b 6657 || i.types[op].bitfield.regbnd
43234a1e
L		 6658 || i.types[op].bitfield.regzmm
6659 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6660 || i.types[op].bitfield.sreg2
6661 || i.types[op].bitfield.sreg3
6662 || i.types[op].bitfield.control
6663 || i.types[op].bitfield.debug
6664 || i.types[op].bitfield.test)
6665 break;
c0209578 6666
7ab9ffdd
L		 6667 if (vex_3_sources)
6668 op = dest;
2426c15f 6669 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6670 {
6671 /* For instructions with VexNDS, the register-only
6672 source operand is encoded in VEX prefix. */
6673 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6674
7ab9ffdd 6675 if (op > mem)
c0f3af97 6676 {
7ab9ffdd
L		 6677 vex_reg = op++;
6678 gas_assert (op < i.operands);
c0f3af97
L		 6679 }
6680 else
c0f3af97 6681 {
f12dc422
L		 6682 /* Check register-only source operand when two source
6683 operands are swapped. */
6684 if (!i.tm.operand_types[op].bitfield.baseindex
6685 && i.tm.operand_types[op + 1].bitfield.baseindex)
6686 {
6687 vex_reg = op;
6688 op += 2;
6689 gas_assert (mem == (vex_reg + 1)
6690 && op < i.operands);
6691 }
6692 else
6693 {
6694 vex_reg = op + 1;
6695 gas_assert (vex_reg < i.operands);
6696 }
c0f3af97 6697 }
7ab9ffdd 6698 }
2426c15f 6699 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6700 {
f12dc422 6701 /* For instructions with VexNDD, the register destination
7ab9ffdd 6702 is encoded in VEX prefix. */
f12dc422
L		 6703 if (i.mem_operands == 0)
6704 {
6705 /* There is no memory operand. */
6706 gas_assert ((op + 2) == i.operands);
6707 vex_reg = op + 1;
6708 }
6709 else
8d63c93e 6710 {
f12dc422
L		 6711 /* There are only 2 operands. */
6712 gas_assert (op < 2 && i.operands == 2);
6713 vex_reg = 1;
6714 }
7ab9ffdd
L		 6715 }
6716 else
6717 gas_assert (op < i.operands);
99018f42 6718
7ab9ffdd
L		 6719 if (vex_reg != (unsigned int) ~0)
6720 {
f12dc422 6721 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6722
f12dc422
L		 6723 if (type->bitfield.reg32 != 1
6724 && type->bitfield.reg64 != 1
6725 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6726 && !operand_type_equal (type, &regymm)
6727 && !operand_type_equal (type, &regzmm)
6728 && !operand_type_equal (type, &regmask))
7ab9ffdd 6729 abort ();
f88c9eb0 6730
7ab9ffdd
L		 6731 i.vex.register_specifier = i.op[vex_reg].regs;
6732 }
6733
1b9f0c97
L		 6734 /* Don't set OP operand twice. */
6735 if (vex_reg != op)
7ab9ffdd 6736 {
1b9f0c97
L		 6737 /* If there is an extension opcode to put here, the
6738 register number must be put into the regmem field. */
6739 if (i.tm.extension_opcode != None)
6740 {
6741 i.rm.regmem = i.op[op].regs->reg_num;
6742 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6743 i.rex |= REX_B;
43234a1e
L		 6744 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6745 i.vrex |= REX_B;
1b9f0c97
L		 6746 }
6747 else
6748 {
6749 i.rm.reg = i.op[op].regs->reg_num;
6750 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6751 i.rex |= REX_R;
43234a1e
L		 6752 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6753 i.vrex |= REX_R;
1b9f0c97 6754 }
7ab9ffdd 6755 }
252b5132 6756
29b0f896
AM		 6757 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6758 must set it to 3 to indicate this is a register operand
6759 in the regmem field. */
6760 if (!i.mem_operands)
6761 i.rm.mode = 3;
6762 }
252b5132 6763
29b0f896 6764 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6765 if (i.tm.extension_opcode != None)
29b0f896
AM		 6766 i.rm.reg = i.tm.extension_opcode;
6767 }
6768 return default_seg;
6769}
252b5132 6770
29b0f896 6771static void
e3bb37b5 6772output_branch (void)
29b0f896
AM		 6773{
6774 char *p;
f8a5c266 6775 int size;
29b0f896
AM		 6776 int code16;
6777 int prefix;
6778 relax_substateT subtype;
6779 symbolS *sym;
6780 offsetT off;
6781
f8a5c266 6782 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6783 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6784
6785 prefix = 0;
6786 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6787 {
29b0f896
AM		 6788 prefix = 1;
6789 i.prefixes -= 1;
6790 code16 ^= CODE16;
252b5132 6791 }
29b0f896
AM		 6792 /* Pentium4 branch hints. */
6793 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6794 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6795 {
29b0f896
AM		 6796 prefix++;
6797 i.prefixes--;
6798 }
6799 if (i.prefix[REX_PREFIX] != 0)
6800 {
6801 prefix++;
6802 i.prefixes--;
2f66722d
AM		 6803 }
6804
7e8b059b
L		 6805 /* BND prefixed jump. */
6806 if (i.prefix[BND_PREFIX] != 0)
6807 {
6808 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6809 i.prefixes -= 1;
6810 }
6811
29b0f896
AM		 6812 if (i.prefixes != 0 && !intel_syntax)
6813 as_warn (_("skipping prefixes on this instruction"));
6814
6815 /* It's always a symbol; End frag & setup for relax.
6816 Make sure there is enough room in this frag for the largest
6817 instruction we may generate in md_convert_frag. This is 2
6818 bytes for the opcode and room for the prefix and largest
6819 displacement. */
6820 frag_grow (prefix + 2 + 4);
6821 /* Prefix and 1 opcode byte go in fr_fix. */
6822 p = frag_more (prefix + 1);
6823 if (i.prefix[DATA_PREFIX] != 0)
6824 *p++ = DATA_PREFIX_OPCODE;
6825 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6826 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6827 *p++ = i.prefix[SEG_PREFIX];
6828 if (i.prefix[REX_PREFIX] != 0)
6829 *p++ = i.prefix[REX_PREFIX];
6830 *p = i.tm.base_opcode;
6831
6832 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6833 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6834 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6835 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6836 else
f8a5c266 6837 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6838 subtype |= code16;
3e73aa7c 6839
29b0f896
AM		 6840 sym = i.op[0].disps->X_add_symbol;
6841 off = i.op[0].disps->X_add_number;
3e73aa7c 6842
29b0f896
AM		 6843 if (i.op[0].disps->X_op != O_constant
6844 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6845 {
29b0f896
AM		 6846 /* Handle complex expressions. */
6847 sym = make_expr_symbol (i.op[0].disps);
6848 off = 0;
6849 }
3e73aa7c 6850
29b0f896
AM		 6851 /* 1 possible extra opcode + 4 byte displacement go in var part.
6852 Pass reloc in fr_var. */
d258b828 6853 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6854}
3e73aa7c 6855
29b0f896 6856static void
e3bb37b5 6857output_jump (void)
29b0f896
AM		 6858{
6859 char *p;
6860 int size;
3e02c1cc 6861 fixS *fixP;
29b0f896 6862
40fb9820 6863 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6864 {
6865 /* This is a loop or jecxz type instruction. */
6866 size = 1;
6867 if (i.prefix[ADDR_PREFIX] != 0)
6868 {
6869 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6870 i.prefixes -= 1;
6871 }
6872 /* Pentium4 branch hints. */
6873 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6874 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6875 {
6876 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6877 i.prefixes--;
3e73aa7c
JH		 6878 }
6879 }
29b0f896
AM		 6880 else
6881 {
6882 int code16;
3e73aa7c 6883
29b0f896
AM		 6884 code16 = 0;
6885 if (flag_code == CODE_16BIT)
6886 code16 = CODE16;
3e73aa7c 6887
29b0f896
AM		 6888 if (i.prefix[DATA_PREFIX] != 0)
6889 {
6890 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6891 i.prefixes -= 1;
6892 code16 ^= CODE16;
6893 }
252b5132 6894
29b0f896
AM		 6895 size = 4;
6896 if (code16)
6897 size = 2;
6898 }
9fcc94b6 6899
29b0f896
AM		 6900 if (i.prefix[REX_PREFIX] != 0)
6901 {
6902 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6903 i.prefixes -= 1;
6904 }
252b5132 6905
7e8b059b
L		 6906 /* BND prefixed jump. */
6907 if (i.prefix[BND_PREFIX] != 0)
6908 {
6909 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6910 i.prefixes -= 1;
6911 }
6912
29b0f896
AM		 6913 if (i.prefixes != 0 && !intel_syntax)
6914 as_warn (_("skipping prefixes on this instruction"));
e0890092 6915
42164a71
L		 6916 p = frag_more (i.tm.opcode_length + size);
6917 switch (i.tm.opcode_length)
6918 {
6919 case 2:
6920 *p++ = i.tm.base_opcode >> 8;
6921 case 1:
6922 *p++ = i.tm.base_opcode;
6923 break;
6924 default:
6925 abort ();
6926 }
e0890092 6927
3e02c1cc 6928 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6929 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6930
6931 /* All jumps handled here are signed, but don't use a signed limit
6932 check for 32 and 16 bit jumps as we want to allow wrap around at
6933 4G and 64k respectively. */
6934 if (size == 1)
6935 fixP->fx_signed = 1;
29b0f896 6936}
e0890092 6937
29b0f896 6938static void
e3bb37b5 6939output_interseg_jump (void)
29b0f896
AM		 6940{
6941 char *p;
6942 int size;
6943 int prefix;
6944 int code16;
252b5132 6945
29b0f896
AM		 6946 code16 = 0;
6947 if (flag_code == CODE_16BIT)
6948 code16 = CODE16;
a217f122 6949
29b0f896
AM		 6950 prefix = 0;
6951 if (i.prefix[DATA_PREFIX] != 0)
6952 {
6953 prefix = 1;
6954 i.prefixes -= 1;
6955 code16 ^= CODE16;
6956 }
6957 if (i.prefix[REX_PREFIX] != 0)
6958 {
6959 prefix++;
6960 i.prefixes -= 1;
6961 }
252b5132 6962
29b0f896
AM		 6963 size = 4;
6964 if (code16)
6965 size = 2;
252b5132 6966
29b0f896
AM		 6967 if (i.prefixes != 0 && !intel_syntax)
6968 as_warn (_("skipping prefixes on this instruction"));
252b5132 6969
29b0f896
AM		 6970 /* 1 opcode; 2 segment; offset */
6971 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6972
29b0f896
AM		 6973 if (i.prefix[DATA_PREFIX] != 0)
6974 *p++ = DATA_PREFIX_OPCODE;
252b5132 6975
29b0f896
AM		 6976 if (i.prefix[REX_PREFIX] != 0)
6977 *p++ = i.prefix[REX_PREFIX];
252b5132 6978
29b0f896
AM		 6979 *p++ = i.tm.base_opcode;
6980 if (i.op[1].imms->X_op == O_constant)
6981 {
6982 offsetT n = i.op[1].imms->X_add_number;
252b5132 6983
29b0f896
AM		 6984 if (size == 2
6985 && !fits_in_unsigned_word (n)
6986 && !fits_in_signed_word (n))
6987 {
6988 as_bad (_("16-bit jump out of range"));
6989 return;
6990 }
6991 md_number_to_chars (p, n, size);
6992 }
6993 else
6994 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6995 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6996 if (i.op[0].imms->X_op != O_constant)
6997 as_bad (_("can't handle non absolute segment in `%s'"),
6998 i.tm.name);
6999 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7000}
a217f122 7001
29b0f896 7002static void
e3bb37b5 7003output_insn (void)
29b0f896 7004{
2bbd9c25
JJ		 7005 fragS *insn_start_frag;
7006 offsetT insn_start_off;
7007
29b0f896
AM		 7008 /* Tie dwarf2 debug info to the address at the start of the insn.
7009 We can't do this after the insn has been output as the current
7010 frag may have been closed off. eg. by frag_var. */
7011 dwarf2_emit_insn (0);
7012
2bbd9c25
JJ		 7013 insn_start_frag = frag_now;
7014 insn_start_off = frag_now_fix ();
7015
29b0f896 7016 /* Output jumps. */
40fb9820 7017 if (i.tm.opcode_modifier.jump)
29b0f896 7018 output_branch ();
40fb9820
L		 7019 else if (i.tm.opcode_modifier.jumpbyte
7020 || i.tm.opcode_modifier.jumpdword)
29b0f896 7021 output_jump ();
40fb9820 7022 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7023 output_interseg_jump ();
7024 else
7025 {
7026 /* Output normal instructions here. */
7027 char *p;
7028 unsigned char *q;
47465058 7029 unsigned int j;
331d2d0d 7030 unsigned int prefix;
4dffcebc 7031
e4e00185
AS		 7032 if (avoid_fence
7033 && i.tm.base_opcode == 0xfae
7034 && i.operands == 1
7035 && i.imm_operands == 1
7036 && (i.op[0].imms->X_add_number == 0xe8
7037 || i.op[0].imms->X_add_number == 0xf0
7038 || i.op[0].imms->X_add_number == 0xf8))
7039 {
7040 /* Encode lfence, mfence, and sfence as
7041 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7042 offsetT val = 0x240483f0ULL;
7043 p = frag_more (5);
7044 md_number_to_chars (p, val, 5);
7045 return;
7046 }
7047
d022bddd
IT		 7048 /* Some processors fail on LOCK prefix. This options makes
7049 assembler ignore LOCK prefix and serves as a workaround. */
7050 if (omit_lock_prefix)
7051 {
7052 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7053 return;
7054 i.prefix[LOCK_PREFIX] = 0;
7055 }
7056
43234a1e
L		 7057 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7058 don't need the explicit prefix. */
7059 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7060 {
c0f3af97 7061 switch (i.tm.opcode_length)
bc4bd9ab 7062 {
c0f3af97
L		 7063 case 3:
7064 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7065 {
c0f3af97
L		 7066 prefix = (i.tm.base_opcode >> 24) & 0xff;
7067 goto check_prefix;
7068 }
7069 break;
7070 case 2:
7071 if ((i.tm.base_opcode & 0xff0000) != 0)
7072 {
7073 prefix = (i.tm.base_opcode >> 16) & 0xff;
7074 if (i.tm.cpu_flags.bitfield.cpupadlock)
7075 {
4dffcebc 7076check_prefix:
c0f3af97 7077 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7078 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7079 != REPE_PREFIX_OPCODE))
7080 add_prefix (prefix);
7081 }
7082 else
4dffcebc
L		 7083 add_prefix (prefix);
7084 }
c0f3af97
L		 7085 break;
7086 case 1:
7087 break;
7088 default:
7089 abort ();
bc4bd9ab 7090 }
c0f3af97 7091
6d19a37a 7092#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7093 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7094 R_X86_64_GOTTPOFF relocation so that linker can safely
7095 perform IE->LE optimization. */
7096 if (x86_elf_abi == X86_64_X32_ABI
7097 && i.operands == 2
7098 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7099 && i.prefix[REX_PREFIX] == 0)
7100 add_prefix (REX_OPCODE);
6d19a37a 7101#endif
cf61b747 7102
c0f3af97
L		 7103 /* The prefix bytes. */
7104 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7105 if (*q)
7106 FRAG_APPEND_1_CHAR (*q);
0f10071e 7107 }
ae5c1c7b 7108 else
c0f3af97
L		 7109 {
7110 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7111 if (*q)
7112 switch (j)
7113 {
7114 case REX_PREFIX:
7115 /* REX byte is encoded in VEX prefix. */
7116 break;
7117 case SEG_PREFIX:
7118 case ADDR_PREFIX:
7119 FRAG_APPEND_1_CHAR (*q);
7120 break;
7121 default:
7122 /* There should be no other prefixes for instructions
7123 with VEX prefix. */
7124 abort ();
7125 }
7126
43234a1e
L		 7127 /* For EVEX instructions i.vrex should become 0 after
7128 build_evex_prefix. For VEX instructions upper 16 registers
7129 aren't available, so VREX should be 0. */
7130 if (i.vrex)
7131 abort ();
c0f3af97
L		 7132 /* Now the VEX prefix. */
7133 p = frag_more (i.vex.length);
7134 for (j = 0; j < i.vex.length; j++)
7135 p[j] = i.vex.bytes[j];
7136 }
252b5132 7137
29b0f896 7138 /* Now the opcode; be careful about word order here! */
4dffcebc 7139 if (i.tm.opcode_length == 1)
29b0f896
AM		 7140 {
7141 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7142 }
7143 else
7144 {
4dffcebc 7145 switch (i.tm.opcode_length)
331d2d0d 7146 {
43234a1e
L		 7147 case 4:
7148 p = frag_more (4);
7149 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7150 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7151 break;
4dffcebc 7152 case 3:
331d2d0d
L		 7153 p = frag_more (3);
7154 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7155 break;
7156 case 2:
7157 p = frag_more (2);
7158 break;
7159 default:
7160 abort ();
7161 break;
331d2d0d 7162 }
0f10071e 7163
29b0f896
AM		 7164 /* Put out high byte first: can't use md_number_to_chars! */
7165 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7166 *p = i.tm.base_opcode & 0xff;
7167 }
3e73aa7c 7168
29b0f896 7169 /* Now the modrm byte and sib byte (if present). */
40fb9820 7170 if (i.tm.opcode_modifier.modrm)
29b0f896 7171 {
4a3523fa
L		 7172 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7173 | i.rm.reg << 3
7174 | i.rm.mode << 6));
29b0f896
AM		 7175 /* If i.rm.regmem == ESP (4)
7176 && i.rm.mode != (Register mode)
7177 && not 16 bit
7178 ==> need second modrm byte. */
7179 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7180 && i.rm.mode != 3
40fb9820 7181 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7182 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7183 | i.sib.index << 3
7184 | i.sib.scale << 6));
29b0f896 7185 }
3e73aa7c 7186
29b0f896 7187 if (i.disp_operands)
2bbd9c25 7188 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7189
29b0f896 7190 if (i.imm_operands)
2bbd9c25 7191 output_imm (insn_start_frag, insn_start_off);
29b0f896 7192 }
252b5132 7193
29b0f896
AM		 7194#ifdef DEBUG386
7195 if (flag_debug)
7196 {
7b81dfbb 7197 pi ("" /*line*/, &i);
29b0f896
AM		 7198 }
7199#endif /* DEBUG386 */
7200}
252b5132 7201
e205caa7
L		 7202/* Return the size of the displacement operand N. */
7203
7204static int
7205disp_size (unsigned int n)
7206{
7207 int size = 4;
43234a1e
L		 7208
7209 /* Vec_Disp8 has to be 8bit. */
7210 if (i.types[n].bitfield.vec_disp8)
7211 size = 1;
7212 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7213 size = 8;
7214 else if (i.types[n].bitfield.disp8)
7215 size = 1;
7216 else if (i.types[n].bitfield.disp16)
7217 size = 2;
e205caa7
L		 7218 return size;
7219}
7220
7221/* Return the size of the immediate operand N. */
7222
7223static int
7224imm_size (unsigned int n)
7225{
7226 int size = 4;
40fb9820
L		 7227 if (i.types[n].bitfield.imm64)
7228 size = 8;
7229 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7230 size = 1;
7231 else if (i.types[n].bitfield.imm16)
7232 size = 2;
e205caa7
L		 7233 return size;
7234}
7235
29b0f896 7236static void
64e74474 7237output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7238{
7239 char *p;
7240 unsigned int n;
252b5132 7241
29b0f896
AM		 7242 for (n = 0; n < i.operands; n++)
7243 {
43234a1e
L		 7244 if (i.types[n].bitfield.vec_disp8
7245 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7246 {
7247 if (i.op[n].disps->X_op == O_constant)
7248 {
e205caa7 7249 int size = disp_size (n);
43234a1e 7250 offsetT val = i.op[n].disps->X_add_number;
252b5132 7251
43234a1e
L		 7252 if (i.types[n].bitfield.vec_disp8)
7253 val >>= i.memshift;
7254 val = offset_in_range (val, size);
29b0f896
AM		 7255 p = frag_more (size);
7256 md_number_to_chars (p, val, size);
7257 }
7258 else
7259 {
f86103b7 7260 enum bfd_reloc_code_real reloc_type;
e205caa7 7261 int size = disp_size (n);
40fb9820 7262 int sign = i.types[n].bitfield.disp32s;
29b0f896 7263 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7264 fixS *fixP;
29b0f896 7265
e205caa7 7266 /* We can't have 8 bit displacement here. */
9c2799c2 7267 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7268
29b0f896
AM		 7269 /* The PC relative address is computed relative
7270 to the instruction boundary, so in case immediate
7271 fields follows, we need to adjust the value. */
7272 if (pcrel && i.imm_operands)
7273 {
29b0f896 7274 unsigned int n1;
e205caa7 7275 int sz = 0;
252b5132 7276
29b0f896 7277 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7278 if (operand_type_check (i.types[n1], imm))
252b5132 7279 {
e205caa7
L		 7280 /* Only one immediate is allowed for PC
7281 relative address. */
9c2799c2 7282 gas_assert (sz == 0);
e205caa7
L		 7283 sz = imm_size (n1);
7284 i.op[n].disps->X_add_number -= sz;
252b5132 7285 }
29b0f896 7286 /* We should find the immediate. */
9c2799c2 7287 gas_assert (sz != 0);
29b0f896 7288 }
520dc8e8 7289
29b0f896 7290 p = frag_more (size);
d258b828 7291 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7292 if (GOT_symbol
2bbd9c25 7293 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7294 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7295 || reloc_type == BFD_RELOC_X86_64_32S
7296 || (reloc_type == BFD_RELOC_64
7297 && object_64bit))
d6ab8113
JB		 7298 && (i.op[n].disps->X_op == O_symbol
7299 || (i.op[n].disps->X_op == O_add
7300 && ((symbol_get_value_expression
7301 (i.op[n].disps->X_op_symbol)->X_op)
7302 == O_subtract))))
7303 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7304 {
7305 offsetT add;
7306
7307 if (insn_start_frag == frag_now)
7308 add = (p - frag_now->fr_literal) - insn_start_off;
7309 else
7310 {
7311 fragS *fr;
7312
7313 add = insn_start_frag->fr_fix - insn_start_off;
7314 for (fr = insn_start_frag->fr_next;
7315 fr && fr != frag_now; fr = fr->fr_next)
7316 add += fr->fr_fix;
7317 add += p - frag_now->fr_literal;
7318 }
7319
4fa24527 7320 if (!object_64bit)
7b81dfbb
AJ		 7321 {
7322 reloc_type = BFD_RELOC_386_GOTPC;
7323 i.op[n].imms->X_add_number += add;
7324 }
7325 else if (reloc_type == BFD_RELOC_64)
7326 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7327 else
7b81dfbb
AJ		 7328 /* Don't do the adjustment for x86-64, as there
7329 the pcrel addressing is relative to the _next_
7330 insn, and that is taken care of in other code. */
d6ab8113 7331 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7332 }
02a86693
L		 7333 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7334 size, i.op[n].disps, pcrel,
7335 reloc_type);
7336 /* Check for "call/jmp *mem", "mov mem, %reg",
7337 "test %reg, mem" and "binop mem, %reg" where binop
7338 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7339 instructions. Always generate R_386_GOT32X for
7340 "sym*GOT" operand in 32-bit mode. */
7341 if ((generate_relax_relocations
7342 || (!object_64bit
7343 && i.rm.mode == 0
7344 && i.rm.regmem == 5))
7345 && (i.rm.mode == 2
7346 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7347 && ((i.operands == 1
7348 && i.tm.base_opcode == 0xff
7349 && (i.rm.reg == 2 || i.rm.reg == 4))
7350 || (i.operands == 2
7351 && (i.tm.base_opcode == 0x8b
7352 || i.tm.base_opcode == 0x85
7353 || (i.tm.base_opcode & 0xc7) == 0x03))))
7354 {
7355 if (object_64bit)
7356 {
7357 fixP->fx_tcbit = i.rex != 0;
7358 if (i.base_reg
7359 && (i.base_reg->reg_num == RegRip
7360 || i.base_reg->reg_num == RegEip))
7361 fixP->fx_tcbit2 = 1;
7362 }
7363 else
7364 fixP->fx_tcbit2 = 1;
7365 }
29b0f896
AM		 7366 }
7367 }
7368 }
7369}
252b5132 7370
29b0f896 7371static void
64e74474 7372output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7373{
7374 char *p;
7375 unsigned int n;
252b5132 7376
29b0f896
AM		 7377 for (n = 0; n < i.operands; n++)
7378 {
43234a1e
L		 7379 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7380 if (i.rounding && (int) n == i.rounding->operand)
7381 continue;
7382
40fb9820 7383 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7384 {
7385 if (i.op[n].imms->X_op == O_constant)
7386 {
e205caa7 7387 int size = imm_size (n);
29b0f896 7388 offsetT val;
b4cac588 7389
29b0f896
AM		 7390 val = offset_in_range (i.op[n].imms->X_add_number,
7391 size);
7392 p = frag_more (size);
7393 md_number_to_chars (p, val, size);
7394 }
7395 else
7396 {
7397 /* Not absolute_section.
7398 Need a 32-bit fixup (don't support 8bit
7399 non-absolute imms). Try to support other
7400 sizes ... */
f86103b7 7401 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7402 int size = imm_size (n);
7403 int sign;
29b0f896 7404
40fb9820 7405 if (i.types[n].bitfield.imm32s
a7d61044 7406 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7407 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7408 sign = 1;
e205caa7
L		 7409 else
7410 sign = 0;
520dc8e8 7411
29b0f896 7412 p = frag_more (size);
d258b828 7413 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7414
2bbd9c25
JJ		 7415 /* This is tough to explain. We end up with this one if we
7416 * have operands that look like
7417 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7418 * obtain the absolute address of the GOT, and it is strongly
7419 * preferable from a performance point of view to avoid using
7420 * a runtime relocation for this. The actual sequence of
7421 * instructions often look something like:
7422 *
7423 * call .L66
7424 * .L66:
7425 * popl %ebx
7426 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7427 *
7428 * The call and pop essentially return the absolute address
7429 * of the label .L66 and store it in %ebx. The linker itself
7430 * will ultimately change the first operand of the addl so
7431 * that %ebx points to the GOT, but to keep things simple, the
7432 * .o file must have this operand set so that it generates not
7433 * the absolute address of .L66, but the absolute address of
7434 * itself. This allows the linker itself simply treat a GOTPC
7435 * relocation as asking for a pcrel offset to the GOT to be
7436 * added in, and the addend of the relocation is stored in the
7437 * operand field for the instruction itself.
7438 *
7439 * Our job here is to fix the operand so that it would add
7440 * the correct offset so that %ebx would point to itself. The
7441 * thing that is tricky is that .-.L66 will point to the
7442 * beginning of the instruction, so we need to further modify
7443 * the operand so that it will point to itself. There are
7444 * other cases where you have something like:
7445 *
7446 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7447 *
7448 * and here no correction would be required. Internally in
7449 * the assembler we treat operands of this form as not being
7450 * pcrel since the '.' is explicitly mentioned, and I wonder
7451 * whether it would simplify matters to do it this way. Who
7452 * knows. In earlier versions of the PIC patches, the
7453 * pcrel_adjust field was used to store the correction, but
7454 * since the expression is not pcrel, I felt it would be
7455 * confusing to do it this way. */
7456
d6ab8113 7457 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7458 || reloc_type == BFD_RELOC_X86_64_32S
7459 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7460 && GOT_symbol
7461 && GOT_symbol == i.op[n].imms->X_add_symbol
7462 && (i.op[n].imms->X_op == O_symbol
7463 || (i.op[n].imms->X_op == O_add
7464 && ((symbol_get_value_expression
7465 (i.op[n].imms->X_op_symbol)->X_op)
7466 == O_subtract))))
7467 {
2bbd9c25
JJ		 7468 offsetT add;
7469
7470 if (insn_start_frag == frag_now)
7471 add = (p - frag_now->fr_literal) - insn_start_off;
7472 else
7473 {
7474 fragS *fr;
7475
7476 add = insn_start_frag->fr_fix - insn_start_off;
7477 for (fr = insn_start_frag->fr_next;
7478 fr && fr != frag_now; fr = fr->fr_next)
7479 add += fr->fr_fix;
7480 add += p - frag_now->fr_literal;
7481 }
7482
4fa24527 7483 if (!object_64bit)
d6ab8113 7484 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7485 else if (size == 4)
d6ab8113 7486 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7487 else if (size == 8)
7488 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7489 i.op[n].imms->X_add_number += add;
29b0f896 7490 }
29b0f896
AM		 7491 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7492 i.op[n].imms, 0, reloc_type);
7493 }
7494 }
7495 }
252b5132
RH		 7496}
7497\f
d182319b
JB		 7498/* x86_cons_fix_new is called via the expression parsing code when a
7499 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7500static int cons_sign = -1;
7501
7502void
e3bb37b5 7503x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7504 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7505{
d258b828 7506 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7507
7508#ifdef TE_PE
7509 if (exp->X_op == O_secrel)
7510 {
7511 exp->X_op = O_symbol;
7512 r = BFD_RELOC_32_SECREL;
7513 }
7514#endif
7515
7516 fix_new_exp (frag, off, len, exp, 0, r);
7517}
7518
357d1bd8
L		 7519/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7520 purpose of the `.dc.a' internal pseudo-op. */
7521
7522int
7523x86_address_bytes (void)
7524{
7525 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7526 return 4;
7527 return stdoutput->arch_info->bits_per_address / 8;
7528}
7529
d382c579
TG		 7530#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7531 || defined (LEX_AT)
d258b828 7532# define lex_got(reloc, adjust, types) NULL
718ddfc0 7533#else
f3c180ae
AM		 7534/* Parse operands of the form
7535 <symbol>@GOTOFF+<nnn>
7536 and similar .plt or .got references.
7537
7538 If we find one, set up the correct relocation in RELOC and copy the
7539 input string, minus the `@GOTOFF' into a malloc'd buffer for
7540 parsing by the calling routine. Return this buffer, and if ADJUST
7541 is non-null set it to the length of the string we removed from the
7542 input line. Otherwise return NULL. */
7543static char *
91d6fa6a 7544lex_got (enum bfd_reloc_code_real *rel,
64e74474 7545 int *adjust,
d258b828 7546 i386_operand_type *types)
f3c180ae 7547{
7b81dfbb
AJ		 7548 /* Some of the relocations depend on the size of what field is to
7549 be relocated. But in our callers i386_immediate and i386_displacement
7550 we don't yet know the operand size (this will be set by insn
7551 matching). Hence we record the word32 relocation here,
7552 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7553 static const struct {
7554 const char *str;
cff8d58a 7555 int len;
4fa24527 7556 const enum bfd_reloc_code_real rel[2];
40fb9820 7557 const i386_operand_type types64;
f3c180ae 7558 } gotrel[] = {
8ce3d284 7559#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7560 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7561 BFD_RELOC_SIZE32 },
7562 OPERAND_TYPE_IMM32_64 },
8ce3d284 7563#endif
cff8d58a
L		 7564 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7565 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7566 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7567 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7568 BFD_RELOC_X86_64_PLT32 },
40fb9820 7569 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7570 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7571 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7572 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7573 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7574 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7575 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7576 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7577 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7578 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7579 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7580 BFD_RELOC_X86_64_TLSGD },
40fb9820 7581 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7582 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7583 _dummy_first_bfd_reloc_code_real },
40fb9820 7584 OPERAND_TYPE_NONE },
cff8d58a
L		 7585 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7586 BFD_RELOC_X86_64_TLSLD },
40fb9820 7587 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7588 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7589 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7590 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7591 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7592 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7593 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7594 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7595 _dummy_first_bfd_reloc_code_real },
40fb9820 7596 OPERAND_TYPE_NONE },
cff8d58a
L		 7597 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7598 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7599 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7600 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7601 _dummy_first_bfd_reloc_code_real },
40fb9820 7602 OPERAND_TYPE_NONE },
cff8d58a
L		 7603 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7604 _dummy_first_bfd_reloc_code_real },
40fb9820 7605 OPERAND_TYPE_NONE },
cff8d58a
L		 7606 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7607 BFD_RELOC_X86_64_GOT32 },
40fb9820 7608 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7609 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7610 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7611 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7612 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7613 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7614 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7615 };
7616 char *cp;
7617 unsigned int j;
7618
d382c579 7619#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7620 if (!IS_ELF)
7621 return NULL;
d382c579 7622#endif
718ddfc0 7623
f3c180ae 7624 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7625 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7626 return NULL;
7627
47465058 7628 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7629 {
cff8d58a 7630 int len = gotrel[j].len;
28f81592 7631 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7632 {
4fa24527 7633 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7634 {
28f81592
AM		 7635 int first, second;
7636 char *tmpbuf, *past_reloc;
f3c180ae 7637
91d6fa6a 7638 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7639
3956db08
JB		 7640 if (types)
7641 {
7642 if (flag_code != CODE_64BIT)
40fb9820
L		 7643 {
7644 types->bitfield.imm32 = 1;
7645 types->bitfield.disp32 = 1;
7646 }
3956db08
JB		 7647 else
7648 *types = gotrel[j].types64;
7649 }
7650
8fd4256d 7651 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7652 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7653
28f81592 7654 /* The length of the first part of our input line. */
f3c180ae 7655 first = cp - input_line_pointer;
28f81592
AM		 7656
7657 /* The second part goes from after the reloc token until
67c11a9b 7658 (and including) an end_of_line char or comma. */
28f81592 7659 past_reloc = cp + 1 + len;
67c11a9b
AM		 7660 cp = past_reloc;
7661 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7662 ++cp;
7663 second = cp + 1 - past_reloc;
28f81592
AM		 7664
7665 /* Allocate and copy string. The trailing NUL shouldn't
7666 be necessary, but be safe. */
add39d23 7667 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7668 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7669 if (second != 0 && *past_reloc != ' ')
7670 /* Replace the relocation token with ' ', so that
7671 errors like foo@GOTOFF1 will be detected. */
7672 tmpbuf[first++] = ' ';
af89796a
L		 7673 else
7674 /* Increment length by 1 if the relocation token is
7675 removed. */
7676 len++;
7677 if (adjust)
7678 *adjust = len;
0787a12d
AM		 7679 memcpy (tmpbuf + first, past_reloc, second);
7680 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7681 return tmpbuf;
7682 }
7683
4fa24527
JB		 7684 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7685 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7686 return NULL;
7687 }
7688 }
7689
7690 /* Might be a symbol version string. Don't as_bad here. */
7691 return NULL;
7692}
4e4f7c87 7693#endif
f3c180ae 7694
a988325c
NC		 7695#ifdef TE_PE
7696#ifdef lex_got
7697#undef lex_got
7698#endif
7699/* Parse operands of the form
7700 <symbol>@SECREL32+<nnn>
7701
7702 If we find one, set up the correct relocation in RELOC and copy the
7703 input string, minus the `@SECREL32' into a malloc'd buffer for
7704 parsing by the calling routine. Return this buffer, and if ADJUST
7705 is non-null set it to the length of the string we removed from the
34bca508
L		 7706 input line. Otherwise return NULL.
7707
a988325c
NC		 7708 This function is copied from the ELF version above adjusted for PE targets. */
7709
7710static char *
7711lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7712 int *adjust ATTRIBUTE_UNUSED,
d258b828 7713 i386_operand_type *types)
a988325c
NC		 7714{
7715 static const struct
7716 {
7717 const char *str;
7718 int len;
7719 const enum bfd_reloc_code_real rel[2];
7720 const i386_operand_type types64;
7721 }
7722 gotrel[] =
7723 {
7724 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7725 BFD_RELOC_32_SECREL },
7726 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7727 };
7728
7729 char *cp;
7730 unsigned j;
7731
7732 for (cp = input_line_pointer; *cp != '@'; cp++)
7733 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7734 return NULL;
7735
7736 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7737 {
7738 int len = gotrel[j].len;
7739
7740 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7741 {
7742 if (gotrel[j].rel[object_64bit] != 0)
7743 {
7744 int first, second;
7745 char *tmpbuf, *past_reloc;
7746
7747 *rel = gotrel[j].rel[object_64bit];
7748 if (adjust)
7749 *adjust = len;
7750
7751 if (types)
7752 {
7753 if (flag_code != CODE_64BIT)
7754 {
7755 types->bitfield.imm32 = 1;
7756 types->bitfield.disp32 = 1;
7757 }
7758 else
7759 *types = gotrel[j].types64;
7760 }
7761
7762 /* The length of the first part of our input line. */
7763 first = cp - input_line_pointer;
7764
7765 /* The second part goes from after the reloc token until
7766 (and including) an end_of_line char or comma. */
7767 past_reloc = cp + 1 + len;
7768 cp = past_reloc;
7769 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7770 ++cp;
7771 second = cp + 1 - past_reloc;
7772
7773 /* Allocate and copy string. The trailing NUL shouldn't
7774 be necessary, but be safe. */
add39d23 7775 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7776 memcpy (tmpbuf, input_line_pointer, first);
7777 if (second != 0 && *past_reloc != ' ')
7778 /* Replace the relocation token with ' ', so that
7779 errors like foo@SECLREL321 will be detected. */
7780 tmpbuf[first++] = ' ';
7781 memcpy (tmpbuf + first, past_reloc, second);
7782 tmpbuf[first + second] = '\0';
7783 return tmpbuf;
7784 }
7785
7786 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7787 gotrel[j].str, 1 << (5 + object_64bit));
7788 return NULL;
7789 }
7790 }
7791
7792 /* Might be a symbol version string. Don't as_bad here. */
7793 return NULL;
7794}
7795
7796#endif /* TE_PE */
7797
62ebcb5c 7798bfd_reloc_code_real_type
e3bb37b5 7799x86_cons (expressionS *exp, int size)
f3c180ae 7800{
62ebcb5c
AM		 7801 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7802
ee86248c
JB		 7803 intel_syntax = -intel_syntax;
7804
3c7b9c2c 7805 exp->X_md = 0;
4fa24527 7806 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7807 {
7808 /* Handle @GOTOFF and the like in an expression. */
7809 char *save;
7810 char *gotfree_input_line;
4a57f2cf 7811 int adjust = 0;
f3c180ae
AM		 7812
7813 save = input_line_pointer;
d258b828 7814 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7815 if (gotfree_input_line)
7816 input_line_pointer = gotfree_input_line;
7817
7818 expression (exp);
7819
7820 if (gotfree_input_line)
7821 {
7822 /* expression () has merrily parsed up to the end of line,
7823 or a comma - in the wrong buffer. Transfer how far
7824 input_line_pointer has moved to the right buffer. */
7825 input_line_pointer = (save
7826 + (input_line_pointer - gotfree_input_line)
7827 + adjust);
7828 free (gotfree_input_line);
3992d3b7
AM		 7829 if (exp->X_op == O_constant
7830 || exp->X_op == O_absent
7831 || exp->X_op == O_illegal
0398aac5 7832 || exp->X_op == O_register
3992d3b7
AM		 7833 || exp->X_op == O_big)
7834 {
7835 char c = *input_line_pointer;
7836 *input_line_pointer = 0;
7837 as_bad (_("missing or invalid expression `%s'"), save);
7838 *input_line_pointer = c;
7839 }
f3c180ae
AM		 7840 }
7841 }
7842 else
7843 expression (exp);
ee86248c
JB		 7844
7845 intel_syntax = -intel_syntax;
7846
7847 if (intel_syntax)
7848 i386_intel_simplify (exp);
62ebcb5c
AM		 7849
7850 return got_reloc;
f3c180ae 7851}
f3c180ae 7852
9f32dd5b
L		 7853static void
7854signed_cons (int size)
6482c264 7855{
d182319b
JB		 7856 if (flag_code == CODE_64BIT)
7857 cons_sign = 1;
7858 cons (size);
7859 cons_sign = -1;
6482c264
NC		 7860}
7861
d182319b 7862#ifdef TE_PE
6482c264 7863static void
7016a5d5 7864pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7865{
7866 expressionS exp;
7867
7868 do
7869 {
7870 expression (&exp);
7871 if (exp.X_op == O_symbol)
7872 exp.X_op = O_secrel;
7873
7874 emit_expr (&exp, 4);
7875 }
7876 while (*input_line_pointer++ == ',');
7877
7878 input_line_pointer--;
7879 demand_empty_rest_of_line ();
7880}
6482c264
NC		 7881#endif
7882
43234a1e
L		 7883/* Handle Vector operations. */
7884
7885static char *
7886check_VecOperations (char *op_string, char *op_end)
7887{
7888 const reg_entry *mask;
7889 const char *saved;
7890 char *end_op;
7891
7892 while (*op_string
7893 && (op_end == NULL || op_string < op_end))
7894 {
7895 saved = op_string;
7896 if (*op_string == '{')
7897 {
7898 op_string++;
7899
7900 /* Check broadcasts. */
7901 if (strncmp (op_string, "1to", 3) == 0)
7902 {
7903 int bcst_type;
7904
7905 if (i.broadcast)
7906 goto duplicated_vec_op;
7907
7908 op_string += 3;
7909 if (*op_string == '8')
7910 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7911 else if (*op_string == '4')
7912 bcst_type = BROADCAST_1TO4;
7913 else if (*op_string == '2')
7914 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7915 else if (*op_string == '1'
7916 && *(op_string+1) == '6')
7917 {
7918 bcst_type = BROADCAST_1TO16;
7919 op_string++;
7920 }
7921 else
7922 {
7923 as_bad (_("Unsupported broadcast: `%s'"), saved);
7924 return NULL;
7925 }
7926 op_string++;
7927
7928 broadcast_op.type = bcst_type;
7929 broadcast_op.operand = this_operand;
7930 i.broadcast = &broadcast_op;
7931 }
7932 /* Check masking operation. */
7933 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7934 {
7935 /* k0 can't be used for write mask. */
7936 if (mask->reg_num == 0)
7937 {
7938 as_bad (_("`%s' can't be used for write mask"),
7939 op_string);
7940 return NULL;
7941 }
7942
7943 if (!i.mask)
7944 {
7945 mask_op.mask = mask;
7946 mask_op.zeroing = 0;
7947 mask_op.operand = this_operand;
7948 i.mask = &mask_op;
7949 }
7950 else
7951 {
7952 if (i.mask->mask)
7953 goto duplicated_vec_op;
7954
7955 i.mask->mask = mask;
7956
7957 /* Only "{z}" is allowed here. No need to check
7958 zeroing mask explicitly. */
7959 if (i.mask->operand != this_operand)
7960 {
7961 as_bad (_("invalid write mask `%s'"), saved);
7962 return NULL;
7963 }
7964 }
7965
7966 op_string = end_op;
7967 }
7968 /* Check zeroing-flag for masking operation. */
7969 else if (*op_string == 'z')
7970 {
7971 if (!i.mask)
7972 {
7973 mask_op.mask = NULL;
7974 mask_op.zeroing = 1;
7975 mask_op.operand = this_operand;
7976 i.mask = &mask_op;
7977 }
7978 else
7979 {
7980 if (i.mask->zeroing)
7981 {
7982 duplicated_vec_op:
7983 as_bad (_("duplicated `%s'"), saved);
7984 return NULL;
7985 }
7986
7987 i.mask->zeroing = 1;
7988
7989 /* Only "{%k}" is allowed here. No need to check mask
7990 register explicitly. */
7991 if (i.mask->operand != this_operand)
7992 {
7993 as_bad (_("invalid zeroing-masking `%s'"),
7994 saved);
7995 return NULL;
7996 }
7997 }
7998
7999 op_string++;
8000 }
8001 else
8002 goto unknown_vec_op;
8003
8004 if (*op_string != '}')
8005 {
8006 as_bad (_("missing `}' in `%s'"), saved);
8007 return NULL;
8008 }
8009 op_string++;
8010 continue;
8011 }
8012 unknown_vec_op:
8013 /* We don't know this one. */
8014 as_bad (_("unknown vector operation: `%s'"), saved);
8015 return NULL;
8016 }
8017
8018 return op_string;
8019}
8020
252b5132 8021static int
70e41ade 8022i386_immediate (char *imm_start)
252b5132
RH		 8023{
8024 char *save_input_line_pointer;
f3c180ae 8025 char *gotfree_input_line;
252b5132 8026 segT exp_seg = 0;
47926f60 8027 expressionS *exp;
40fb9820
L		 8028 i386_operand_type types;
8029
0dfbf9d7 8030 operand_type_set (&types, ~0);
252b5132
RH		 8031
8032 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8033 {
31b2323c
L		 8034 as_bad (_("at most %d immediate operands are allowed"),
8035 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8036 return 0;
8037 }
8038
8039 exp = &im_expressions[i.imm_operands++];
520dc8e8 8040 i.op[this_operand].imms = exp;
252b5132
RH		 8041
8042 if (is_space_char (*imm_start))
8043 ++imm_start;
8044
8045 save_input_line_pointer = input_line_pointer;
8046 input_line_pointer = imm_start;
8047
d258b828 8048 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8049 if (gotfree_input_line)
8050 input_line_pointer = gotfree_input_line;
252b5132
RH		 8051
8052 exp_seg = expression (exp);
8053
83183c0c 8054 SKIP_WHITESPACE ();
43234a1e
L		 8055
8056 /* Handle vector operations. */
8057 if (*input_line_pointer == '{')
8058 {
8059 input_line_pointer = check_VecOperations (input_line_pointer,
8060 NULL);
8061 if (input_line_pointer == NULL)
8062 return 0;
8063 }
8064
252b5132 8065 if (*input_line_pointer)
f3c180ae 8066 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8067
8068 input_line_pointer = save_input_line_pointer;
f3c180ae 8069 if (gotfree_input_line)
ee86248c
JB		 8070 {
8071 free (gotfree_input_line);
8072
8073 if (exp->X_op == O_constant || exp->X_op == O_register)
8074 exp->X_op = O_illegal;
8075 }
8076
8077 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8078}
252b5132 8079
ee86248c
JB		 8080static int
8081i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8082 i386_operand_type types, const char *imm_start)
8083{
8084 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8085 {
313c53d1
L		 8086 if (imm_start)
8087 as_bad (_("missing or invalid immediate expression `%s'"),
8088 imm_start);
3992d3b7 8089 return 0;
252b5132 8090 }
3e73aa7c 8091 else if (exp->X_op == O_constant)
252b5132 8092 {
47926f60 8093 /* Size it properly later. */
40fb9820 8094 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8095 /* If not 64bit, sign extend val. */
8096 if (flag_code != CODE_64BIT
4eed87de
AM		 8097 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8098 exp->X_add_number
8099 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8100 }
4c63da97 8101#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8102 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8103 && exp_seg != absolute_section
47926f60 8104 && exp_seg != text_section
24eab124
AM		 8105 && exp_seg != data_section
8106 && exp_seg != bss_section
8107 && exp_seg != undefined_section
f86103b7 8108 && !bfd_is_com_section (exp_seg))
252b5132 8109 {
d0b47220 8110 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8111 return 0;
8112 }
8113#endif
a841bdf5 8114 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8115 {
313c53d1
L		 8116 if (imm_start)
8117 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8118 return 0;
8119 }
252b5132
RH		 8120 else
8121 {
8122 /* This is an address. The size of the address will be
24eab124 8123 determined later, depending on destination register,
3e73aa7c 8124 suffix, or the default for the section. */
40fb9820
L		 8125 i.types[this_operand].bitfield.imm8 = 1;
8126 i.types[this_operand].bitfield.imm16 = 1;
8127 i.types[this_operand].bitfield.imm32 = 1;
8128 i.types[this_operand].bitfield.imm32s = 1;
8129 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8130 i.types[this_operand] = operand_type_and (i.types[this_operand],
8131 types);
252b5132
RH		 8132 }
8133
8134 return 1;
8135}
8136
551c1ca1 8137static char *
e3bb37b5 8138i386_scale (char *scale)
252b5132 8139{
551c1ca1
AM		 8140 offsetT val;
8141 char *save = input_line_pointer;
252b5132 8142
551c1ca1
AM		 8143 input_line_pointer = scale;
8144 val = get_absolute_expression ();
8145
8146 switch (val)
252b5132 8147 {
551c1ca1 8148 case 1:
252b5132
RH		 8149 i.log2_scale_factor = 0;
8150 break;
551c1ca1 8151 case 2:
252b5132
RH		 8152 i.log2_scale_factor = 1;
8153 break;
551c1ca1 8154 case 4:
252b5132
RH		 8155 i.log2_scale_factor = 2;
8156 break;
551c1ca1 8157 case 8:
252b5132
RH		 8158 i.log2_scale_factor = 3;
8159 break;
8160 default:
a724f0f4
JB		 8161 {
8162 char sep = *input_line_pointer;
8163
8164 *input_line_pointer = '\0';
8165 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8166 scale);
8167 *input_line_pointer = sep;
8168 input_line_pointer = save;
8169 return NULL;
8170 }
252b5132 8171 }
29b0f896 8172 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8173 {
8174 as_warn (_("scale factor of %d without an index register"),
24eab124 8175 1 << i.log2_scale_factor);
252b5132 8176 i.log2_scale_factor = 0;
252b5132 8177 }
551c1ca1
AM		 8178 scale = input_line_pointer;
8179 input_line_pointer = save;
8180 return scale;
252b5132
RH		 8181}
8182
252b5132 8183static int
e3bb37b5 8184i386_displacement (char *disp_start, char *disp_end)
252b5132 8185{
29b0f896 8186 expressionS *exp;
252b5132
RH		 8187 segT exp_seg = 0;
8188 char *save_input_line_pointer;
f3c180ae 8189 char *gotfree_input_line;
40fb9820
L		 8190 int override;
8191 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8192 int ret;
252b5132 8193
31b2323c
L		 8194 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8195 {
8196 as_bad (_("at most %d displacement operands are allowed"),
8197 MAX_MEMORY_OPERANDS);
8198 return 0;
8199 }
8200
0dfbf9d7 8201 operand_type_set (&bigdisp, 0);
40fb9820
L		 8202 if ((i.types[this_operand].bitfield.jumpabsolute)
8203 || (!current_templates->start->opcode_modifier.jump
8204 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8205 {
40fb9820 8206 bigdisp.bitfield.disp32 = 1;
e05278af 8207 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8208 if (flag_code == CODE_64BIT)
8209 {
8210 if (!override)
8211 {
8212 bigdisp.bitfield.disp32s = 1;
8213 bigdisp.bitfield.disp64 = 1;
8214 }
8215 }
8216 else if ((flag_code == CODE_16BIT) ^ override)
8217 {
8218 bigdisp.bitfield.disp32 = 0;
8219 bigdisp.bitfield.disp16 = 1;
8220 }
e05278af
JB		 8221 }
8222 else
8223 {
8224 /* For PC-relative branches, the width of the displacement
8225 is dependent upon data size, not address size. */
e05278af 8226 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8227 if (flag_code == CODE_64BIT)
8228 {
8229 if (override || i.suffix == WORD_MNEM_SUFFIX)
8230 bigdisp.bitfield.disp16 = 1;
8231 else
8232 {
8233 bigdisp.bitfield.disp32 = 1;
8234 bigdisp.bitfield.disp32s = 1;
8235 }
8236 }
8237 else
e05278af
JB		 8238 {
8239 if (!override)
8240 override = (i.suffix == (flag_code != CODE_16BIT
8241 ? WORD_MNEM_SUFFIX
8242 : LONG_MNEM_SUFFIX));
40fb9820
L		 8243 bigdisp.bitfield.disp32 = 1;
8244 if ((flag_code == CODE_16BIT) ^ override)
8245 {
8246 bigdisp.bitfield.disp32 = 0;
8247 bigdisp.bitfield.disp16 = 1;
8248 }
e05278af 8249 }
e05278af 8250 }
c6fb90c8
L		 8251 i.types[this_operand] = operand_type_or (i.types[this_operand],
8252 bigdisp);
252b5132
RH		 8253
8254 exp = &disp_expressions[i.disp_operands];
520dc8e8 8255 i.op[this_operand].disps = exp;
252b5132
RH		 8256 i.disp_operands++;
8257 save_input_line_pointer = input_line_pointer;
8258 input_line_pointer = disp_start;
8259 END_STRING_AND_SAVE (disp_end);
8260
8261#ifndef GCC_ASM_O_HACK
8262#define GCC_ASM_O_HACK 0
8263#endif
8264#if GCC_ASM_O_HACK
8265 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8266 if (i.types[this_operand].bitfield.baseIndex
24eab124 8267 && displacement_string_end[-1] == '+')
252b5132
RH		 8268 {
8269 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8270 constraint within gcc asm statements.
8271 For instance:
8272
8273 #define _set_tssldt_desc(n,addr,limit,type) \
8274 __asm__ __volatile__ ( \
8275 "movw %w2,%0\n\t" \
8276 "movw %w1,2+%0\n\t" \
8277 "rorl $16,%1\n\t" \
8278 "movb %b1,4+%0\n\t" \
8279 "movb %4,5+%0\n\t" \
8280 "movb $0,6+%0\n\t" \
8281 "movb %h1,7+%0\n\t" \
8282 "rorl $16,%1" \
8283 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8284
8285 This works great except that the output assembler ends
8286 up looking a bit weird if it turns out that there is
8287 no offset. You end up producing code that looks like:
8288
8289 #APP
8290 movw $235,(%eax)
8291 movw %dx,2+(%eax)
8292 rorl $16,%edx
8293 movb %dl,4+(%eax)
8294 movb $137,5+(%eax)
8295 movb $0,6+(%eax)
8296 movb %dh,7+(%eax)
8297 rorl $16,%edx
8298 #NO_APP
8299
47926f60 8300 So here we provide the missing zero. */
24eab124
AM		 8301
8302 *displacement_string_end = '0';
252b5132
RH		 8303 }
8304#endif
d258b828 8305 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8306 if (gotfree_input_line)
8307 input_line_pointer = gotfree_input_line;
252b5132 8308
24eab124 8309 exp_seg = expression (exp);
252b5132 8310
636c26b0
AM		 8311 SKIP_WHITESPACE ();
8312 if (*input_line_pointer)
8313 as_bad (_("junk `%s' after expression"), input_line_pointer);
8314#if GCC_ASM_O_HACK
8315 RESTORE_END_STRING (disp_end + 1);
8316#endif
636c26b0 8317 input_line_pointer = save_input_line_pointer;
636c26b0 8318 if (gotfree_input_line)
ee86248c
JB		 8319 {
8320 free (gotfree_input_line);
8321
8322 if (exp->X_op == O_constant || exp->X_op == O_register)
8323 exp->X_op = O_illegal;
8324 }
8325
8326 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8327
8328 RESTORE_END_STRING (disp_end);
8329
8330 return ret;
8331}
8332
8333static int
8334i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8335 i386_operand_type types, const char *disp_start)
8336{
8337 i386_operand_type bigdisp;
8338 int ret = 1;
636c26b0 8339
24eab124
AM		 8340 /* We do this to make sure that the section symbol is in
8341 the symbol table. We will ultimately change the relocation
47926f60 8342 to be relative to the beginning of the section. */
1ae12ab7 8343 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8344 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8345 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8346 {
636c26b0 8347 if (exp->X_op != O_symbol)
3992d3b7 8348 goto inv_disp;
636c26b0 8349
e5cb08ac 8350 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8351 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8352 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8353 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8354 exp->X_op = O_subtract;
8355 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8356 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8357 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8358 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8359 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8360 else
29b0f896 8361 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8362 }
252b5132 8363
3992d3b7
AM		 8364 else if (exp->X_op == O_absent
8365 || exp->X_op == O_illegal
ee86248c 8366 || exp->X_op == O_big)
2daf4fd8 8367 {
3992d3b7
AM		 8368 inv_disp:
8369 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8370 disp_start);
3992d3b7 8371 ret = 0;
2daf4fd8
AM		 8372 }
8373
0e1147d9
L		 8374 else if (flag_code == CODE_64BIT
8375 && !i.prefix[ADDR_PREFIX]
8376 && exp->X_op == O_constant)
8377 {
8378 /* Since displacement is signed extended to 64bit, don't allow
8379 disp32 and turn off disp32s if they are out of range. */
8380 i.types[this_operand].bitfield.disp32 = 0;
8381 if (!fits_in_signed_long (exp->X_add_number))
8382 {
8383 i.types[this_operand].bitfield.disp32s = 0;
8384 if (i.types[this_operand].bitfield.baseindex)
8385 {
8386 as_bad (_("0x%lx out range of signed 32bit displacement"),
8387 (long) exp->X_add_number);
8388 ret = 0;
8389 }
8390 }
8391 }
8392
4c63da97 8393#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8394 else if (exp->X_op != O_constant
8395 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8396 && exp_seg != absolute_section
8397 && exp_seg != text_section
8398 && exp_seg != data_section
8399 && exp_seg != bss_section
8400 && exp_seg != undefined_section
8401 && !bfd_is_com_section (exp_seg))
24eab124 8402 {
d0b47220 8403 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8404 ret = 0;
24eab124 8405 }
252b5132 8406#endif
3956db08 8407
40fb9820
L		 8408 /* Check if this is a displacement only operand. */
8409 bigdisp = i.types[this_operand];
8410 bigdisp.bitfield.disp8 = 0;
8411 bigdisp.bitfield.disp16 = 0;
8412 bigdisp.bitfield.disp32 = 0;
8413 bigdisp.bitfield.disp32s = 0;
8414 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8415 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8416 i.types[this_operand] = operand_type_and (i.types[this_operand],
8417 types);
3956db08 8418
3992d3b7 8419 return ret;
252b5132
RH		 8420}
8421
eecb386c 8422/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8423 Return 1 on success, 0 on a failure. */
8424
252b5132 8425static int
e3bb37b5 8426i386_index_check (const char *operand_string)
252b5132 8427{
fc0763e6 8428 const char *kind = "base/index";
be05d201
L		 8429 enum flag_code addr_mode;
8430
8431 if (i.prefix[ADDR_PREFIX])
8432 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8433 else
8434 {
8435 addr_mode = flag_code;
8436
24eab124 8437#if INFER_ADDR_PREFIX
be05d201
L		 8438 if (i.mem_operands == 0)
8439 {
8440 /* Infer address prefix from the first memory operand. */
8441 const reg_entry *addr_reg = i.base_reg;
8442
8443 if (addr_reg == NULL)
8444 addr_reg = i.index_reg;
eecb386c 8445
be05d201
L		 8446 if (addr_reg)
8447 {
8448 if (addr_reg->reg_num == RegEip
8449 || addr_reg->reg_num == RegEiz
8450 || addr_reg->reg_type.bitfield.reg32)
8451 addr_mode = CODE_32BIT;
8452 else if (flag_code != CODE_64BIT
8453 && addr_reg->reg_type.bitfield.reg16)
8454 addr_mode = CODE_16BIT;
8455
8456 if (addr_mode != flag_code)
8457 {
8458 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8459 i.prefixes += 1;
8460 /* Change the size of any displacement too. At most one
8461 of Disp16 or Disp32 is set.
8462 FIXME. There doesn't seem to be any real need for
8463 separate Disp16 and Disp32 flags. The same goes for
8464 Imm16 and Imm32. Removing them would probably clean
8465 up the code quite a lot. */
8466 if (flag_code != CODE_64BIT
8467 && (i.types[this_operand].bitfield.disp16
8468 || i.types[this_operand].bitfield.disp32))
8469 i.types[this_operand]
8470 = operand_type_xor (i.types[this_operand], disp16_32);
8471 }
8472 }
8473 }
24eab124 8474#endif
be05d201
L		 8475 }
8476
fc0763e6
JB		 8477 if (current_templates->start->opcode_modifier.isstring
8478 && !current_templates->start->opcode_modifier.immext
8479 && (current_templates->end[-1].opcode_modifier.isstring
8480 || i.mem_operands))
8481 {
8482 /* Memory operands of string insns are special in that they only allow
8483 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8484 const reg_entry *expected_reg;
8485 static const char *di_si[][2] =
8486 {
8487 { "esi", "edi" },
8488 { "si", "di" },
8489 { "rsi", "rdi" }
8490 };
8491 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8492
8493 kind = "string address";
8494
8495 if (current_templates->start->opcode_modifier.w)
8496 {
8497 i386_operand_type type = current_templates->end[-1].operand_types[0];
8498
8499 if (!type.bitfield.baseindex
8500 || ((!i.mem_operands != !intel_syntax)
8501 && current_templates->end[-1].operand_types[1]
8502 .bitfield.baseindex))
8503 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8504 expected_reg = hash_find (reg_hash,
8505 di_si[addr_mode][type.bitfield.esseg]);
8506
fc0763e6
JB		 8507 }
8508 else
be05d201 8509 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8510
be05d201
L		 8511 if (i.base_reg != expected_reg
8512 || i.index_reg
fc0763e6 8513 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8514 {
be05d201
L		 8515 /* The second memory operand must have the same size as
8516 the first one. */
8517 if (i.mem_operands
8518 && i.base_reg
8519 && !((addr_mode == CODE_64BIT
8520 && i.base_reg->reg_type.bitfield.reg64)
8521 || (addr_mode == CODE_32BIT
8522 ? i.base_reg->reg_type.bitfield.reg32
8523 : i.base_reg->reg_type.bitfield.reg16)))
8524 goto bad_address;
8525
fc0763e6
JB		 8526 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8527 operand_string,
8528 intel_syntax ? '[' : '(',
8529 register_prefix,
be05d201 8530 expected_reg->reg_name,
fc0763e6 8531 intel_syntax ? ']' : ')');
be05d201 8532 return 1;
fc0763e6 8533 }
be05d201
L		 8534 else
8535 return 1;
8536
8537bad_address:
8538 as_bad (_("`%s' is not a valid %s expression"),
8539 operand_string, kind);
8540 return 0;
3e73aa7c
JH		 8541 }
8542 else
8543 {
be05d201
L		 8544 if (addr_mode != CODE_16BIT)
8545 {
8546 /* 32-bit/64-bit checks. */
8547 if ((i.base_reg
8548 && (addr_mode == CODE_64BIT
8549 ? !i.base_reg->reg_type.bitfield.reg64
8550 : !i.base_reg->reg_type.bitfield.reg32)
8551 && (i.index_reg
8552 || (i.base_reg->reg_num
8553 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8554 || (i.index_reg
8555 && !i.index_reg->reg_type.bitfield.regxmm
8556 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8557 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8558 && ((addr_mode == CODE_64BIT
8559 ? !(i.index_reg->reg_type.bitfield.reg64
8560 || i.index_reg->reg_num == RegRiz)
8561 : !(i.index_reg->reg_type.bitfield.reg32
8562 || i.index_reg->reg_num == RegEiz))
8563 || !i.index_reg->reg_type.bitfield.baseindex)))
8564 goto bad_address;
8565 }
8566 else
3e73aa7c 8567 {
be05d201 8568 /* 16-bit checks. */
3e73aa7c 8569 if ((i.base_reg
40fb9820
L		 8570 && (!i.base_reg->reg_type.bitfield.reg16
8571 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8572 || (i.index_reg
40fb9820
L		 8573 && (!i.index_reg->reg_type.bitfield.reg16
8574 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8575 || !(i.base_reg
8576 && i.base_reg->reg_num < 6
8577 && i.index_reg->reg_num >= 6
8578 && i.log2_scale_factor == 0))))
be05d201 8579 goto bad_address;
3e73aa7c
JH		 8580 }
8581 }
be05d201 8582 return 1;
24eab124 8583}
252b5132 8584
43234a1e
L		 8585/* Handle vector immediates. */
8586
8587static int
8588RC_SAE_immediate (const char *imm_start)
8589{
8590 unsigned int match_found, j;
8591 const char *pstr = imm_start;
8592 expressionS *exp;
8593
8594 if (*pstr != '{')
8595 return 0;
8596
8597 pstr++;
8598 match_found = 0;
8599 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8600 {
8601 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8602 {
8603 if (!i.rounding)
8604 {
8605 rc_op.type = RC_NamesTable[j].type;
8606 rc_op.operand = this_operand;
8607 i.rounding = &rc_op;
8608 }
8609 else
8610 {
8611 as_bad (_("duplicated `%s'"), imm_start);
8612 return 0;
8613 }
8614 pstr += RC_NamesTable[j].len;
8615 match_found = 1;
8616 break;
8617 }
8618 }
8619 if (!match_found)
8620 return 0;
8621
8622 if (*pstr++ != '}')
8623 {
8624 as_bad (_("Missing '}': '%s'"), imm_start);
8625 return 0;
8626 }
8627 /* RC/SAE immediate string should contain nothing more. */;
8628 if (*pstr != 0)
8629 {
8630 as_bad (_("Junk after '}': '%s'"), imm_start);
8631 return 0;
8632 }
8633
8634 exp = &im_expressions[i.imm_operands++];
8635 i.op[this_operand].imms = exp;
8636
8637 exp->X_op = O_constant;
8638 exp->X_add_number = 0;
8639 exp->X_add_symbol = (symbolS *) 0;
8640 exp->X_op_symbol = (symbolS *) 0;
8641
8642 i.types[this_operand].bitfield.imm8 = 1;
8643 return 1;
8644}
8645
fc0763e6 8646/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8647 on error. */
252b5132 8648
252b5132 8649static int
a7619375 8650i386_att_operand (char *operand_string)
252b5132 8651{
af6bdddf
AM		 8652 const reg_entry *r;
8653 char *end_op;
24eab124 8654 char *op_string = operand_string;
252b5132 8655
24eab124 8656 if (is_space_char (*op_string))
252b5132
RH		 8657 ++op_string;
8658
24eab124 8659 /* We check for an absolute prefix (differentiating,
47926f60 8660 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8661 if (*op_string == ABSOLUTE_PREFIX)
8662 {
8663 ++op_string;
8664 if (is_space_char (*op_string))
8665 ++op_string;
40fb9820 8666 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8667 }
252b5132 8668
47926f60 8669 /* Check if operand is a register. */
4d1bb795 8670 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8671 {
40fb9820
L		 8672 i386_operand_type temp;
8673
24eab124
AM		 8674 /* Check for a segment override by searching for ':' after a
8675 segment register. */
8676 op_string = end_op;
8677 if (is_space_char (*op_string))
8678 ++op_string;
40fb9820
L		 8679 if (*op_string == ':'
8680 && (r->reg_type.bitfield.sreg2
8681 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8682 {
8683 switch (r->reg_num)
8684 {
8685 case 0:
8686 i.seg[i.mem_operands] = &es;
8687 break;
8688 case 1:
8689 i.seg[i.mem_operands] = &cs;
8690 break;
8691 case 2:
8692 i.seg[i.mem_operands] = &ss;
8693 break;
8694 case 3:
8695 i.seg[i.mem_operands] = &ds;
8696 break;
8697 case 4:
8698 i.seg[i.mem_operands] = &fs;
8699 break;
8700 case 5:
8701 i.seg[i.mem_operands] = &gs;
8702 break;
8703 }
252b5132 8704
24eab124 8705 /* Skip the ':' and whitespace. */
252b5132
RH		 8706 ++op_string;
8707 if (is_space_char (*op_string))
24eab124 8708 ++op_string;
252b5132 8709
24eab124
AM		 8710 if (!is_digit_char (*op_string)
8711 && !is_identifier_char (*op_string)
8712 && *op_string != '('
8713 && *op_string != ABSOLUTE_PREFIX)
8714 {
8715 as_bad (_("bad memory operand `%s'"), op_string);
8716 return 0;
8717 }
47926f60 8718 /* Handle case of %es:*foo. */
24eab124
AM		 8719 if (*op_string == ABSOLUTE_PREFIX)
8720 {
8721 ++op_string;
8722 if (is_space_char (*op_string))
8723 ++op_string;
40fb9820 8724 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8725 }
8726 goto do_memory_reference;
8727 }
43234a1e
L		 8728
8729 /* Handle vector operations. */
8730 if (*op_string == '{')
8731 {
8732 op_string = check_VecOperations (op_string, NULL);
8733 if (op_string == NULL)
8734 return 0;
8735 }
8736
24eab124
AM		 8737 if (*op_string)
8738 {
d0b47220 8739 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8740 return 0;
8741 }
40fb9820
L		 8742 temp = r->reg_type;
8743 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8744 i.types[this_operand] = operand_type_or (i.types[this_operand],
8745 temp);
7d5e4556 8746 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8747 i.op[this_operand].regs = r;
24eab124
AM		 8748 i.reg_operands++;
8749 }
af6bdddf
AM		 8750 else if (*op_string == REGISTER_PREFIX)
8751 {
8752 as_bad (_("bad register name `%s'"), op_string);
8753 return 0;
8754 }
24eab124 8755 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8756 {
24eab124 8757 ++op_string;
40fb9820 8758 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8759 {
d0b47220 8760 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8761 return 0;
8762 }
8763 if (!i386_immediate (op_string))
8764 return 0;
8765 }
43234a1e
L		 8766 else if (RC_SAE_immediate (operand_string))
8767 {
8768 /* If it is a RC or SAE immediate, do nothing. */
8769 ;
8770 }
24eab124
AM		 8771 else if (is_digit_char (*op_string)
8772 || is_identifier_char (*op_string)
d02603dc 8773 || *op_string == '"'
e5cb08ac 8774 || *op_string == '(')
24eab124 8775 {
47926f60 8776 /* This is a memory reference of some sort. */
af6bdddf 8777 char *base_string;
252b5132 8778
47926f60 8779 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8780 char *displacement_string_start;
8781 char *displacement_string_end;
43234a1e 8782 char *vop_start;
252b5132 8783
24eab124 8784 do_memory_reference:
24eab124 8785 if ((i.mem_operands == 1
40fb9820 8786 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8787 || i.mem_operands == 2)
8788 {
8789 as_bad (_("too many memory references for `%s'"),
8790 current_templates->start->name);
8791 return 0;
8792 }
252b5132 8793
24eab124
AM		 8794 /* Check for base index form. We detect the base index form by
8795 looking for an ')' at the end of the operand, searching
8796 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8797 after the '('. */
af6bdddf 8798 base_string = op_string + strlen (op_string);
c3332e24 8799
43234a1e
L		 8800 /* Handle vector operations. */
8801 vop_start = strchr (op_string, '{');
8802 if (vop_start && vop_start < base_string)
8803 {
8804 if (check_VecOperations (vop_start, base_string) == NULL)
8805 return 0;
8806 base_string = vop_start;
8807 }
8808
af6bdddf
AM		 8809 --base_string;
8810 if (is_space_char (*base_string))
8811 --base_string;
252b5132 8812
47926f60 8813 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8814 displacement_string_start = op_string;
8815 displacement_string_end = base_string + 1;
252b5132 8816
24eab124
AM		 8817 if (*base_string == ')')
8818 {
af6bdddf 8819 char *temp_string;
24eab124
AM		 8820 unsigned int parens_balanced = 1;
8821 /* We've already checked that the number of left & right ()'s are
47926f60 8822 equal, so this loop will not be infinite. */
24eab124
AM		 8823 do
8824 {
8825 base_string--;
8826 if (*base_string == ')')
8827 parens_balanced++;
8828 if (*base_string == '(')
8829 parens_balanced--;
8830 }
8831 while (parens_balanced);
c3332e24 8832
af6bdddf 8833 temp_string = base_string;
c3332e24 8834
24eab124 8835 /* Skip past '(' and whitespace. */
252b5132
RH		 8836 ++base_string;
8837 if (is_space_char (*base_string))
24eab124 8838 ++base_string;
252b5132 8839
af6bdddf 8840 if (*base_string == ','
4eed87de
AM		 8841 || ((i.base_reg = parse_register (base_string, &end_op))
8842 != NULL))
252b5132 8843 {
af6bdddf 8844 displacement_string_end = temp_string;
252b5132 8845
40fb9820 8846 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8847
af6bdddf 8848 if (i.base_reg)
24eab124 8849 {
24eab124
AM		 8850 base_string = end_op;
8851 if (is_space_char (*base_string))
8852 ++base_string;
af6bdddf
AM		 8853 }
8854
8855 /* There may be an index reg or scale factor here. */
8856 if (*base_string == ',')
8857 {
8858 ++base_string;
8859 if (is_space_char (*base_string))
8860 ++base_string;
8861
4eed87de
AM		 8862 if ((i.index_reg = parse_register (base_string, &end_op))
8863 != NULL)
24eab124 8864 {
af6bdddf 8865 base_string = end_op;
24eab124
AM		 8866 if (is_space_char (*base_string))
8867 ++base_string;
af6bdddf
AM		 8868 if (*base_string == ',')
8869 {
8870 ++base_string;
8871 if (is_space_char (*base_string))
8872 ++base_string;
8873 }
e5cb08ac 8874 else if (*base_string != ')')
af6bdddf 8875 {
4eed87de
AM		 8876 as_bad (_("expecting `,' or `)' "
8877 "after index register in `%s'"),
af6bdddf
AM		 8878 operand_string);
8879 return 0;
8880 }
24eab124 8881 }
af6bdddf 8882 else if (*base_string == REGISTER_PREFIX)
24eab124 8883 {
f76bf5e0
L		 8884 end_op = strchr (base_string, ',');
8885 if (end_op)
8886 *end_op = '\0';
af6bdddf 8887 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8888 return 0;
8889 }
252b5132 8890
47926f60 8891 /* Check for scale factor. */
551c1ca1 8892 if (*base_string != ')')
af6bdddf 8893 {
551c1ca1
AM		 8894 char *end_scale = i386_scale (base_string);
8895
8896 if (!end_scale)
af6bdddf 8897 return 0;
24eab124 8898
551c1ca1 8899 base_string = end_scale;
af6bdddf
AM		 8900 if (is_space_char (*base_string))
8901 ++base_string;
8902 if (*base_string != ')')
8903 {
4eed87de
AM		 8904 as_bad (_("expecting `)' "
8905 "after scale factor in `%s'"),
af6bdddf
AM		 8906 operand_string);
8907 return 0;
8908 }
8909 }
8910 else if (!i.index_reg)
24eab124 8911 {
4eed87de
AM		 8912 as_bad (_("expecting index register or scale factor "
8913 "after `,'; got '%c'"),
af6bdddf 8914 *base_string);
24eab124
AM		 8915 return 0;
8916 }
8917 }
af6bdddf 8918 else if (*base_string != ')')
24eab124 8919 {
4eed87de
AM		 8920 as_bad (_("expecting `,' or `)' "
8921 "after base register in `%s'"),
af6bdddf 8922 operand_string);
24eab124
AM		 8923 return 0;
8924 }
c3332e24 8925 }
af6bdddf 8926 else if (*base_string == REGISTER_PREFIX)
c3332e24 8927 {
f76bf5e0
L		 8928 end_op = strchr (base_string, ',');
8929 if (end_op)
8930 *end_op = '\0';
af6bdddf 8931 as_bad (_("bad register name `%s'"), base_string);
24eab124 8932 return 0;
c3332e24 8933 }
24eab124
AM		 8934 }
8935
8936 /* If there's an expression beginning the operand, parse it,
8937 assuming displacement_string_start and
8938 displacement_string_end are meaningful. */
8939 if (displacement_string_start != displacement_string_end)
8940 {
8941 if (!i386_displacement (displacement_string_start,
8942 displacement_string_end))
8943 return 0;
8944 }
8945
8946 /* Special case for (%dx) while doing input/output op. */
8947 if (i.base_reg
0dfbf9d7
L		 8948 && operand_type_equal (&i.base_reg->reg_type,
8949 &reg16_inoutportreg)
24eab124
AM		 8950 && i.index_reg == 0
8951 && i.log2_scale_factor == 0
8952 && i.seg[i.mem_operands] == 0
40fb9820 8953 && !operand_type_check (i.types[this_operand], disp))
24eab124 8954 {
65da13b5 8955 i.types[this_operand] = inoutportreg;
24eab124
AM		 8956 return 1;
8957 }
8958
eecb386c
AM		 8959 if (i386_index_check (operand_string) == 0)
8960 return 0;
5c07affc 8961 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8962 i.mem_operands++;
8963 }
8964 else
ce8a8b2f
AM		 8965 {
8966 /* It's not a memory operand; argh! */
24eab124
AM		 8967 as_bad (_("invalid char %s beginning operand %d `%s'"),
8968 output_invalid (*op_string),
8969 this_operand + 1,
8970 op_string);
8971 return 0;
8972 }
47926f60 8973 return 1; /* Normal return. */
252b5132
RH		 8974}
8975\f
fa94de6b
RM		 8976/* Calculate the maximum variable size (i.e., excluding fr_fix)
8977 that an rs_machine_dependent frag may reach. */
8978
8979unsigned int
8980i386_frag_max_var (fragS *frag)
8981{
8982 /* The only relaxable frags are for jumps.
8983 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8984 gas_assert (frag->fr_type == rs_machine_dependent);
8985 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8986}
8987
b084df0b
L		 8988#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8989static int
8dcea932 8990elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8991{
8992 /* STT_GNU_IFUNC symbol must go through PLT. */
8993 if ((symbol_get_bfdsym (fr_symbol)->flags
8994 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8995 return 0;
8996
8997 if (!S_IS_EXTERNAL (fr_symbol))
8998 /* Symbol may be weak or local. */
8999 return !S_IS_WEAK (fr_symbol);
9000
8dcea932
L		 9001 /* Global symbols with non-default visibility can't be preempted. */
9002 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9003 return 1;
9004
9005 if (fr_var != NO_RELOC)
9006 switch ((enum bfd_reloc_code_real) fr_var)
9007 {
9008 case BFD_RELOC_386_PLT32:
9009 case BFD_RELOC_X86_64_PLT32:
9010 /* Symbol with PLT relocatin may be preempted. */
9011 return 0;
9012 default:
9013 abort ();
9014 }
9015
b084df0b
L		 9016 /* Global symbols with default visibility in a shared library may be
9017 preempted by another definition. */
8dcea932 9018 return !shared;
b084df0b
L		 9019}
9020#endif
9021
ee7fcc42
AM		 9022/* md_estimate_size_before_relax()
9023
9024 Called just before relax() for rs_machine_dependent frags. The x86
9025 assembler uses these frags to handle variable size jump
9026 instructions.
9027
9028 Any symbol that is now undefined will not become defined.
9029 Return the correct fr_subtype in the frag.
9030 Return the initial "guess for variable size of frag" to caller.
9031 The guess is actually the growth beyond the fixed part. Whatever
9032 we do to grow the fixed or variable part contributes to our
9033 returned value. */
9034
252b5132 9035int
7016a5d5 9036md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9037{
252b5132 9038 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9039 check for un-relaxable symbols. On an ELF system, we can't relax
9040 an externally visible symbol, because it may be overridden by a
9041 shared library. */
9042 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9043#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9044 || (IS_ELF
8dcea932
L		 9045 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9046 fragP->fr_var))
fbeb56a4
DK		 9047#endif
9048#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9049 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9050 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9051#endif
9052 )
252b5132 9053 {
b98ef147
AM		 9054 /* Symbol is undefined in this segment, or we need to keep a
9055 reloc so that weak symbols can be overridden. */
9056 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9057 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9058 unsigned char *opcode;
9059 int old_fr_fix;
f6af82bd 9060
ee7fcc42 9061 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9062 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9063 else if (size == 2)
f6af82bd
AM		 9064 reloc_type = BFD_RELOC_16_PCREL;
9065 else
9066 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9067
ee7fcc42
AM		 9068 old_fr_fix = fragP->fr_fix;
9069 opcode = (unsigned char *) fragP->fr_opcode;
9070
fddf5b5b 9071 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9072 {
fddf5b5b
AM		 9073 case UNCOND_JUMP:
9074 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9075 opcode[0] = 0xe9;
252b5132 9076 fragP->fr_fix += size;
062cd5e7
AS		 9077 fix_new (fragP, old_fr_fix, size,
9078 fragP->fr_symbol,
9079 fragP->fr_offset, 1,
9080 reloc_type);
252b5132
RH		 9081 break;
9082
fddf5b5b 9083 case COND_JUMP86:
412167cb
AM		 9084 if (size == 2
9085 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9086 {
9087 /* Negate the condition, and branch past an
9088 unconditional jump. */
9089 opcode[0] ^= 1;
9090 opcode[1] = 3;
9091 /* Insert an unconditional jump. */
9092 opcode[2] = 0xe9;
9093 /* We added two extra opcode bytes, and have a two byte
9094 offset. */
9095 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9096 fix_new (fragP, old_fr_fix + 2, 2,
9097 fragP->fr_symbol,
9098 fragP->fr_offset, 1,
9099 reloc_type);
fddf5b5b
AM		 9100 break;
9101 }
9102 /* Fall through. */
9103
9104 case COND_JUMP:
412167cb
AM		 9105 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9106 {
3e02c1cc
AM		 9107 fixS *fixP;
9108
412167cb 9109 fragP->fr_fix += 1;
3e02c1cc
AM		 9110 fixP = fix_new (fragP, old_fr_fix, 1,
9111 fragP->fr_symbol,
9112 fragP->fr_offset, 1,
9113 BFD_RELOC_8_PCREL);
9114 fixP->fx_signed = 1;
412167cb
AM		 9115 break;
9116 }
93c2a809 9117
24eab124 9118 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9119 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9120 opcode[1] = opcode[0] + 0x10;
f6af82bd 9121 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9122 /* We've added an opcode byte. */
9123 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9124 fix_new (fragP, old_fr_fix + 1, size,
9125 fragP->fr_symbol,
9126 fragP->fr_offset, 1,
9127 reloc_type);
252b5132 9128 break;
fddf5b5b
AM		 9129
9130 default:
9131 BAD_CASE (fragP->fr_subtype);
9132 break;
252b5132
RH		 9133 }
9134 frag_wane (fragP);
ee7fcc42 9135 return fragP->fr_fix - old_fr_fix;
252b5132 9136 }
93c2a809 9137
93c2a809
AM		 9138 /* Guess size depending on current relax state. Initially the relax
9139 state will correspond to a short jump and we return 1, because
9140 the variable part of the frag (the branch offset) is one byte
9141 long. However, we can relax a section more than once and in that
9142 case we must either set fr_subtype back to the unrelaxed state,
9143 or return the value for the appropriate branch. */
9144 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9145}
9146
47926f60
KH		 9147/* Called after relax() is finished.
9148
9149 In: Address of frag.
9150 fr_type == rs_machine_dependent.
9151 fr_subtype is what the address relaxed to.
9152
9153 Out: Any fixSs and constants are set up.
9154 Caller will turn frag into a ".space 0". */
9155
252b5132 9156void
7016a5d5
TG		 9157md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9158 fragS *fragP)
252b5132 9159{
29b0f896 9160 unsigned char *opcode;
252b5132 9161 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9162 offsetT target_address;
9163 offsetT opcode_address;
252b5132 9164 unsigned int extension = 0;
847f7ad4 9165 offsetT displacement_from_opcode_start;
252b5132
RH		 9166
9167 opcode = (unsigned char *) fragP->fr_opcode;
9168
47926f60 9169 /* Address we want to reach in file space. */
252b5132 9170 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9171
47926f60 9172 /* Address opcode resides at in file space. */
252b5132
RH		 9173 opcode_address = fragP->fr_address + fragP->fr_fix;
9174
47926f60 9175 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9176 displacement_from_opcode_start = target_address - opcode_address;
9177
fddf5b5b 9178 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9179 {
47926f60
KH		 9180 /* Don't have to change opcode. */
9181 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9182 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9183 }
9184 else
9185 {
9186 if (no_cond_jump_promotion
9187 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9188 as_warn_where (fragP->fr_file, fragP->fr_line,
9189 _("long jump required"));
252b5132 9190
fddf5b5b
AM		 9191 switch (fragP->fr_subtype)
9192 {
9193 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9194 extension = 4; /* 1 opcode + 4 displacement */
9195 opcode[0] = 0xe9;
9196 where_to_put_displacement = &opcode[1];
9197 break;
252b5132 9198
fddf5b5b
AM		 9199 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9200 extension = 2; /* 1 opcode + 2 displacement */
9201 opcode[0] = 0xe9;
9202 where_to_put_displacement = &opcode[1];
9203 break;
252b5132 9204
fddf5b5b
AM		 9205 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9206 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9207 extension = 5; /* 2 opcode + 4 displacement */
9208 opcode[1] = opcode[0] + 0x10;
9209 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9210 where_to_put_displacement = &opcode[2];
9211 break;
252b5132 9212
fddf5b5b
AM		 9213 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9214 extension = 3; /* 2 opcode + 2 displacement */
9215 opcode[1] = opcode[0] + 0x10;
9216 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9217 where_to_put_displacement = &opcode[2];
9218 break;
252b5132 9219
fddf5b5b
AM		 9220 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9221 extension = 4;
9222 opcode[0] ^= 1;
9223 opcode[1] = 3;
9224 opcode[2] = 0xe9;
9225 where_to_put_displacement = &opcode[3];
9226 break;
9227
9228 default:
9229 BAD_CASE (fragP->fr_subtype);
9230 break;
9231 }
252b5132 9232 }
fddf5b5b 9233
7b81dfbb
AJ		 9234 /* If size if less then four we are sure that the operand fits,
9235 but if it's 4, then it could be that the displacement is larger
9236 then -/+ 2GB. */
9237 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9238 && object_64bit
9239 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9240 + ((addressT) 1 << 31))
9241 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9242 {
9243 as_bad_where (fragP->fr_file, fragP->fr_line,
9244 _("jump target out of range"));
9245 /* Make us emit 0. */
9246 displacement_from_opcode_start = extension;
9247 }
47926f60 9248 /* Now put displacement after opcode. */
252b5132
RH		 9249 md_number_to_chars ((char *) where_to_put_displacement,
9250 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9251 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9252 fragP->fr_fix += extension;
9253}
9254\f
7016a5d5 9255/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9256 by our caller that we have all the info we need to fix it up.
9257
7016a5d5
TG		 9258 Parameter valP is the pointer to the value of the bits.
9259
252b5132
RH		 9260 On the 386, immediates, displacements, and data pointers are all in
9261 the same (little-endian) format, so we don't need to care about which
9262 we are handling. */
9263
94f592af 9264void
7016a5d5 9265md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9266{
94f592af 9267 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9268 valueT value = *valP;
252b5132 9269
f86103b7 9270#if !defined (TE_Mach)
93382f6d
AM		 9271 if (fixP->fx_pcrel)
9272 {
9273 switch (fixP->fx_r_type)
9274 {
5865bb77
ILT		 9275 default:
9276 break;
9277
d6ab8113
JB		 9278 case BFD_RELOC_64:
9279 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9280 break;
93382f6d 9281 case BFD_RELOC_32:
ae8887b5 9282 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9283 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9284 break;
9285 case BFD_RELOC_16:
9286 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9287 break;
9288 case BFD_RELOC_8:
9289 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9290 break;
9291 }
9292 }
252b5132 9293
a161fe53 9294 if (fixP->fx_addsy != NULL
31312f95 9295 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9296 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9297 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9298 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9299 && !use_rela_relocations)
252b5132 9300 {
31312f95
AM		 9301 /* This is a hack. There should be a better way to handle this.
9302 This covers for the fact that bfd_install_relocation will
9303 subtract the current location (for partial_inplace, PC relative
9304 relocations); see more below. */
252b5132 9305#ifndef OBJ_AOUT
718ddfc0 9306 if (IS_ELF
252b5132
RH		 9307#ifdef TE_PE
9308 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9309#endif
9310 )
9311 value += fixP->fx_where + fixP->fx_frag->fr_address;
9312#endif
9313#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9314 if (IS_ELF)
252b5132 9315 {
6539b54b 9316 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9317
6539b54b 9318 if ((sym_seg == seg
2f66722d 9319 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9320 && sym_seg != absolute_section))
af65af87 9321 && !generic_force_reloc (fixP))
2f66722d
AM		 9322 {
9323 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9324 bfd_install_relocation subtracts them out again. I think
9325 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9326 it. FIXME. */
9327 value += fixP->fx_where + fixP->fx_frag->fr_address;
9328 }
252b5132
RH		 9329 }
9330#endif
9331#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9332 /* For some reason, the PE format does not store a
9333 section address offset for a PC relative symbol. */
9334 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9335 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9336 value += md_pcrel_from (fixP);
9337#endif
9338 }
fbeb56a4 9339#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9340 if (fixP->fx_addsy != NULL
9341 && S_IS_WEAK (fixP->fx_addsy)
9342 /* PR 16858: Do not modify weak function references. */
9343 && ! fixP->fx_pcrel)
fbeb56a4 9344 {
296a8689
NC		 9345#if !defined (TE_PEP)
9346 /* For x86 PE weak function symbols are neither PC-relative
9347 nor do they set S_IS_FUNCTION. So the only reliable way
9348 to detect them is to check the flags of their containing
9349 section. */
9350 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9351 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9352 ;
9353 else
9354#endif
fbeb56a4
DK		 9355 value -= S_GET_VALUE (fixP->fx_addsy);
9356 }
9357#endif
252b5132
RH		 9358
9359 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9360 and we must not disappoint it. */
252b5132 9361#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9362 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9363 switch (fixP->fx_r_type)
9364 {
9365 case BFD_RELOC_386_PLT32:
3e73aa7c 9366 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9367 /* Make the jump instruction point to the address of the operand. At
9368 runtime we merely add the offset to the actual PLT entry. */
9369 value = -4;
9370 break;
31312f95 9371
13ae64f3
JJ		 9372 case BFD_RELOC_386_TLS_GD:
9373 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9374 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9375 case BFD_RELOC_386_TLS_IE:
9376 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9377 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9378 case BFD_RELOC_X86_64_TLSGD:
9379 case BFD_RELOC_X86_64_TLSLD:
9380 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9381 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9382 value = 0; /* Fully resolved at runtime. No addend. */
9383 /* Fallthrough */
9384 case BFD_RELOC_386_TLS_LE:
9385 case BFD_RELOC_386_TLS_LDO_32:
9386 case BFD_RELOC_386_TLS_LE_32:
9387 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9388 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9389 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9390 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9391 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9392 break;
9393
67a4f2b7
AO		 9394 case BFD_RELOC_386_TLS_DESC_CALL:
9395 case BFD_RELOC_X86_64_TLSDESC_CALL:
9396 value = 0; /* Fully resolved at runtime. No addend. */
9397 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9398 fixP->fx_done = 0;
9399 return;
9400
47926f60
KH		 9401 case BFD_RELOC_VTABLE_INHERIT:
9402 case BFD_RELOC_VTABLE_ENTRY:
9403 fixP->fx_done = 0;
94f592af 9404 return;
47926f60
KH		 9405
9406 default:
9407 break;
9408 }
9409#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9410 *valP = value;
f86103b7 9411#endif /* !defined (TE_Mach) */
3e73aa7c 9412
3e73aa7c 9413 /* Are we finished with this relocation now? */
c6682705 9414 if (fixP->fx_addsy == NULL)
3e73aa7c 9415 fixP->fx_done = 1;
fbeb56a4
DK		 9416#if defined (OBJ_COFF) && defined (TE_PE)
9417 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9418 {
9419 fixP->fx_done = 0;
9420 /* Remember value for tc_gen_reloc. */
9421 fixP->fx_addnumber = value;
9422 /* Clear out the frag for now. */
9423 value = 0;
9424 }
9425#endif
3e73aa7c
JH		 9426 else if (use_rela_relocations)
9427 {
9428 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9429 /* Remember value for tc_gen_reloc. */
9430 fixP->fx_addnumber = value;
3e73aa7c
JH		 9431 value = 0;
9432 }
f86103b7 9433
94f592af 9434 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9435}
252b5132 9436\f
6d4af3c2 9437const char *
499ac353 9438md_atof (int type, char *litP, int *sizeP)
252b5132 9439{
499ac353
NC		 9440 /* This outputs the LITTLENUMs in REVERSE order;
9441 in accord with the bigendian 386. */
9442 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9443}
9444\f
2d545b82 9445static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9446
252b5132 9447static char *
e3bb37b5 9448output_invalid (int c)
252b5132 9449{
3882b010 9450 if (ISPRINT (c))
f9f21a03
L		 9451 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9452 "'%c'", c);
252b5132 9453 else
f9f21a03 9454 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9455 "(0x%x)", (unsigned char) c);
252b5132
RH		 9456 return output_invalid_buf;
9457}
9458
af6bdddf 9459/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9460
9461static const reg_entry *
4d1bb795 9462parse_real_register (char *reg_string, char **end_op)
252b5132 9463{
af6bdddf
AM		 9464 char *s = reg_string;
9465 char *p;
252b5132
RH		 9466 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9467 const reg_entry *r;
9468
9469 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9470 if (*s == REGISTER_PREFIX)
9471 ++s;
9472
9473 if (is_space_char (*s))
9474 ++s;
9475
9476 p = reg_name_given;
af6bdddf 9477 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9478 {
9479 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9480 return (const reg_entry *) NULL;
9481 s++;
252b5132
RH		 9482 }
9483
6588847e
DN		 9484 /* For naked regs, make sure that we are not dealing with an identifier.
9485 This prevents confusing an identifier like `eax_var' with register
9486 `eax'. */
9487 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9488 return (const reg_entry *) NULL;
9489
af6bdddf 9490 *end_op = s;
252b5132
RH		 9491
9492 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9493
5f47d35b 9494 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9495 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9496 {
5f47d35b
AM		 9497 if (is_space_char (*s))
9498 ++s;
9499 if (*s == '(')
9500 {
af6bdddf 9501 ++s;
5f47d35b
AM		 9502 if (is_space_char (*s))
9503 ++s;
9504 if (*s >= '0' && *s <= '7')
9505 {
db557034 9506 int fpr = *s - '0';
af6bdddf 9507 ++s;
5f47d35b
AM		 9508 if (is_space_char (*s))
9509 ++s;
9510 if (*s == ')')
9511 {
9512 *end_op = s + 1;
1e9cc1c2 9513 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9514 know (r);
9515 return r + fpr;
5f47d35b 9516 }
5f47d35b 9517 }
47926f60 9518 /* We have "%st(" then garbage. */
5f47d35b
AM		 9519 return (const reg_entry *) NULL;
9520 }
9521 }
9522
a60de03c
JB		 9523 if (r == NULL || allow_pseudo_reg)
9524 return r;
9525
0dfbf9d7 9526 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9527 return (const reg_entry *) NULL;
9528
192dc9c6
JB		 9529 if ((r->reg_type.bitfield.reg32
9530 || r->reg_type.bitfield.sreg3
9531 || r->reg_type.bitfield.control
9532 || r->reg_type.bitfield.debug
9533 || r->reg_type.bitfield.test)
9534 && !cpu_arch_flags.bitfield.cpui386)
9535 return (const reg_entry *) NULL;
9536
309d3373
JB		 9537 if (r->reg_type.bitfield.floatreg
9538 && !cpu_arch_flags.bitfield.cpu8087
9539 && !cpu_arch_flags.bitfield.cpu287
9540 && !cpu_arch_flags.bitfield.cpu387)
9541 return (const reg_entry *) NULL;
9542
192dc9c6
JB		 9543 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9544 return (const reg_entry *) NULL;
9545
9546 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9547 return (const reg_entry *) NULL;
9548
40f12533
L		 9549 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9550 return (const reg_entry *) NULL;
9551
43234a1e
L		 9552 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9553 && !cpu_arch_flags.bitfield.cpuavx512f)
9554 return (const reg_entry *) NULL;
9555
db51cc60 9556 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9557 if (!allow_index_reg
db51cc60
L		 9558 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9559 return (const reg_entry *) NULL;
9560
43234a1e
L		 9561 /* Upper 16 vector register is only available with VREX in 64bit
9562 mode. */
9563 if ((r->reg_flags & RegVRex))
9564 {
9565 if (!cpu_arch_flags.bitfield.cpuvrex
9566 || flag_code != CODE_64BIT)
9567 return (const reg_entry *) NULL;
9568
9569 i.need_vrex = 1;
9570 }
9571
a60de03c
JB		 9572 if (((r->reg_flags & (RegRex64 | RegRex))
9573 || r->reg_type.bitfield.reg64)
40fb9820 9574 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9575 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9576 && flag_code != CODE_64BIT)
20f0a1fc 9577 return (const reg_entry *) NULL;
1ae00879 9578
b7240065
JB		 9579 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9580 return (const reg_entry *) NULL;
9581
252b5132
RH		 9582 return r;
9583}
4d1bb795
JB		 9584
9585/* REG_STRING starts *before* REGISTER_PREFIX. */
9586
9587static const reg_entry *
9588parse_register (char *reg_string, char **end_op)
9589{
9590 const reg_entry *r;
9591
9592 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9593 r = parse_real_register (reg_string, end_op);
9594 else
9595 r = NULL;
9596 if (!r)
9597 {
9598 char *save = input_line_pointer;
9599 char c;
9600 symbolS *symbolP;
9601
9602 input_line_pointer = reg_string;
d02603dc 9603 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9604 symbolP = symbol_find (reg_string);
9605 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9606 {
9607 const expressionS *e = symbol_get_value_expression (symbolP);
9608
0398aac5 9609 know (e->X_op == O_register);
4eed87de 9610 know (e->X_add_number >= 0
c3fe08fa 9611 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9612 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9613 if ((r->reg_flags & RegVRex))
9614 i.need_vrex = 1;
4d1bb795
JB		 9615 *end_op = input_line_pointer;
9616 }
9617 *input_line_pointer = c;
9618 input_line_pointer = save;
9619 }
9620 return r;
9621}
9622
9623int
9624i386_parse_name (char *name, expressionS *e, char *nextcharP)
9625{
9626 const reg_entry *r;
9627 char *end = input_line_pointer;
9628
9629 *end = *nextcharP;
9630 r = parse_register (name, &input_line_pointer);
9631 if (r && end <= input_line_pointer)
9632 {
9633 *nextcharP = *input_line_pointer;
9634 *input_line_pointer = 0;
9635 e->X_op = O_register;
9636 e->X_add_number = r - i386_regtab;
9637 return 1;
9638 }
9639 input_line_pointer = end;
9640 *end = 0;
ee86248c 9641 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9642}
9643
9644void
9645md_operand (expressionS *e)
9646{
ee86248c
JB		 9647 char *end;
9648 const reg_entry *r;
4d1bb795 9649
ee86248c
JB		 9650 switch (*input_line_pointer)
9651 {
9652 case REGISTER_PREFIX:
9653 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9654 if (r)
9655 {
9656 e->X_op = O_register;
9657 e->X_add_number = r - i386_regtab;
9658 input_line_pointer = end;
9659 }
ee86248c
JB		 9660 break;
9661
9662 case '[':
9c2799c2 9663 gas_assert (intel_syntax);
ee86248c
JB		 9664 end = input_line_pointer++;
9665 expression (e);
9666 if (*input_line_pointer == ']')
9667 {
9668 ++input_line_pointer;
9669 e->X_op_symbol = make_expr_symbol (e);
9670 e->X_add_symbol = NULL;
9671 e->X_add_number = 0;
9672 e->X_op = O_index;
9673 }
9674 else
9675 {
9676 e->X_op = O_absent;
9677 input_line_pointer = end;
9678 }
9679 break;
4d1bb795
JB		 9680 }
9681}
9682
252b5132 9683\f
4cc782b5 9684#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9685const char *md_shortopts = "kVQ:sqn";
252b5132 9686#else
12b55ccc 9687const char *md_shortopts = "qn";
252b5132 9688#endif
6e0b89ee 9689
3e73aa7c 9690#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9691#define OPTION_64 (OPTION_MD_BASE + 1)
9692#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9693#define OPTION_MARCH (OPTION_MD_BASE + 3)
9694#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9695#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9696#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9697#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9698#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9699#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9700#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9701#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9702#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9703#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9704#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9705#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9706#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9707#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9708#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9709#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9710#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9711#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9712#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9713#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9714#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9715#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9716
99ad8390
NC		 9717struct option md_longopts[] =
9718{
3e73aa7c 9719 {"32", no_argument, NULL, OPTION_32},
321098a5 9720#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9721 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9722 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9723#endif
9724#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9725 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9726 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9727#endif
b3b91714 9728 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9729 {"march", required_argument, NULL, OPTION_MARCH},
9730 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9731 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9732 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9733 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9734 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9735 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9736 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9737 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9738 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9739 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9740 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9741 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9742 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9743# if defined (TE_PE) || defined (TE_PEP)
9744 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9745#endif
d1982f93 9746 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9747 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9748 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9749 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9750 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9751 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9752 {NULL, no_argument, NULL, 0}
9753};
9754size_t md_longopts_size = sizeof (md_longopts);
9755
9756int
17b9d67d 9757md_parse_option (int c, const char *arg)
252b5132 9758{
91d6fa6a 9759 unsigned int j;
293f5f65 9760 char *arch, *next, *saved;
9103f4f4 9761
252b5132
RH		 9762 switch (c)
9763 {
12b55ccc
L		 9764 case 'n':
9765 optimize_align_code = 0;
9766 break;
9767
a38cf1db
AM		 9768 case 'q':
9769 quiet_warnings = 1;
252b5132
RH		 9770 break;
9771
9772#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9773 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9774 should be emitted or not. FIXME: Not implemented. */
9775 case 'Q':
252b5132
RH		 9776 break;
9777
9778 /* -V: SVR4 argument to print version ID. */
9779 case 'V':
9780 print_version_id ();
9781 break;
9782
a38cf1db
AM		 9783 /* -k: Ignore for FreeBSD compatibility. */
9784 case 'k':
252b5132 9785 break;
4cc782b5
ILT		 9786
9787 case 's':
9788 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9789 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9790 break;
8dcea932
L		 9791
9792 case OPTION_MSHARED:
9793 shared = 1;
9794 break;
99ad8390 9795#endif
321098a5 9796#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9797 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9798 case OPTION_64:
9799 {
9800 const char **list, **l;
9801
3e73aa7c
JH		 9802 list = bfd_target_list ();
9803 for (l = list; *l != NULL; l++)
8620418b 9804 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9805 || strcmp (*l, "coff-x86-64") == 0
9806 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9807 || strcmp (*l, "pei-x86-64") == 0
9808 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9809 {
9810 default_arch = "x86_64";
9811 break;
9812 }
3e73aa7c 9813 if (*l == NULL)
2b5d6a91 9814 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9815 free (list);
9816 }
9817 break;
9818#endif
252b5132 9819
351f65ca 9820#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9821 case OPTION_X32:
351f65ca
L		 9822 if (IS_ELF)
9823 {
9824 const char **list, **l;
9825
9826 list = bfd_target_list ();
9827 for (l = list; *l != NULL; l++)
9828 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9829 {
9830 default_arch = "x86_64:32";
9831 break;
9832 }
9833 if (*l == NULL)
2b5d6a91 9834 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9835 free (list);
9836 }
9837 else
9838 as_fatal (_("32bit x86_64 is only supported for ELF"));
9839 break;
9840#endif
9841
6e0b89ee
AM		 9842 case OPTION_32:
9843 default_arch = "i386";
9844 break;
9845
b3b91714
AM		 9846 case OPTION_DIVIDE:
9847#ifdef SVR4_COMMENT_CHARS
9848 {
9849 char *n, *t;
9850 const char *s;
9851
add39d23 9852 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9853 t = n;
9854 for (s = i386_comment_chars; *s != '\0'; s++)
9855 if (*s != '/')
9856 *t++ = *s;
9857 *t = '\0';
9858 i386_comment_chars = n;
9859 }
9860#endif
9861 break;
9862
9103f4f4 9863 case OPTION_MARCH:
293f5f65
L		 9864 saved = xstrdup (arg);
9865 arch = saved;
9866 /* Allow -march=+nosse. */
9867 if (*arch == '+')
9868 arch++;
6305a203 9869 do
9103f4f4 9870 {
6305a203 9871 if (*arch == '.')
2b5d6a91 9872 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9873 next = strchr (arch, '+');
9874 if (next)
9875 *next++ = '\0';
91d6fa6a 9876 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9877 {
91d6fa6a 9878 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9879 {
6305a203 9880 /* Processor. */
1ded5609
JB		 9881 if (! cpu_arch[j].flags.bitfield.cpui386)
9882 continue;
9883
91d6fa6a 9884 cpu_arch_name = cpu_arch[j].name;
6305a203 9885 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9886 cpu_arch_flags = cpu_arch[j].flags;
9887 cpu_arch_isa = cpu_arch[j].type;
9888 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9889 if (!cpu_arch_tune_set)
9890 {
9891 cpu_arch_tune = cpu_arch_isa;
9892 cpu_arch_tune_flags = cpu_arch_isa_flags;
9893 }
9894 break;
9895 }
91d6fa6a
NC		 9896 else if (*cpu_arch [j].name == '.'
9897 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9898 {
9899 /* ISA entension. */
9900 i386_cpu_flags flags;
309d3373 9901
293f5f65
L		 9902 flags = cpu_flags_or (cpu_arch_flags,
9903 cpu_arch[j].flags);
81486035
L		 9904
9905 if (!valid_iamcu_cpu_flags (&flags))
9906 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9907 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9908 {
9909 if (cpu_sub_arch_name)
9910 {
9911 char *name = cpu_sub_arch_name;
9912 cpu_sub_arch_name = concat (name,
91d6fa6a 9913 cpu_arch[j].name,
1bf57e9f 9914 (const char *) NULL);
6305a203
L		 9915 free (name);
9916 }
9917 else
91d6fa6a 9918 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9919 cpu_arch_flags = flags;
a586129e 9920 cpu_arch_isa_flags = flags;
6305a203
L		 9921 }
9922 break;
ccc9c027 9923 }
9103f4f4 9924 }
6305a203 9925
293f5f65
L		 9926 if (j >= ARRAY_SIZE (cpu_arch))
9927 {
9928 /* Disable an ISA entension. */
9929 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
9930 if (strcmp (arch, cpu_noarch [j].name) == 0)
9931 {
9932 i386_cpu_flags flags;
9933
9934 flags = cpu_flags_and_not (cpu_arch_flags,
9935 cpu_noarch[j].flags);
9936 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9937 {
9938 if (cpu_sub_arch_name)
9939 {
9940 char *name = cpu_sub_arch_name;
9941 cpu_sub_arch_name = concat (arch,
9942 (const char *) NULL);
9943 free (name);
9944 }
9945 else
9946 cpu_sub_arch_name = xstrdup (arch);
9947 cpu_arch_flags = flags;
9948 cpu_arch_isa_flags = flags;
9949 }
9950 break;
9951 }
9952
9953 if (j >= ARRAY_SIZE (cpu_noarch))
9954 j = ARRAY_SIZE (cpu_arch);
9955 }
9956
91d6fa6a 9957 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9958 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9959
9960 arch = next;
9103f4f4 9961 }
293f5f65
L		 9962 while (next != NULL);
9963 free (saved);
9103f4f4
L		 9964 break;
9965
9966 case OPTION_MTUNE:
9967 if (*arg == '.')
2b5d6a91 9968 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9969 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9970 {
91d6fa6a 9971 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9972 {
ccc9c027 9973 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9974 cpu_arch_tune = cpu_arch [j].type;
9975 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9976 break;
9977 }
9978 }
91d6fa6a 9979 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9980 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9981 break;
9982
1efbbeb4
L		 9983 case OPTION_MMNEMONIC:
9984 if (strcasecmp (arg, "att") == 0)
9985 intel_mnemonic = 0;
9986 else if (strcasecmp (arg, "intel") == 0)
9987 intel_mnemonic = 1;
9988 else
2b5d6a91 9989 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9990 break;
9991
9992 case OPTION_MSYNTAX:
9993 if (strcasecmp (arg, "att") == 0)
9994 intel_syntax = 0;
9995 else if (strcasecmp (arg, "intel") == 0)
9996 intel_syntax = 1;
9997 else
2b5d6a91 9998 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9999 break;
10000
10001 case OPTION_MINDEX_REG:
10002 allow_index_reg = 1;
10003 break;
10004
10005 case OPTION_MNAKED_REG:
10006 allow_naked_reg = 1;
10007 break;
10008
10009 case OPTION_MOLD_GCC:
10010 old_gcc = 1;
1efbbeb4
L		 10011 break;
10012
c0f3af97
L		 10013 case OPTION_MSSE2AVX:
10014 sse2avx = 1;
10015 break;
10016
daf50ae7
L		 10017 case OPTION_MSSE_CHECK:
10018 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10019 sse_check = check_error;
daf50ae7 10020 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10021 sse_check = check_warning;
daf50ae7 10022 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10023 sse_check = check_none;
daf50ae7 10024 else
2b5d6a91 10025 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10026 break;
10027
7bab8ab5
JB		 10028 case OPTION_MOPERAND_CHECK:
10029 if (strcasecmp (arg, "error") == 0)
10030 operand_check = check_error;
10031 else if (strcasecmp (arg, "warning") == 0)
10032 operand_check = check_warning;
10033 else if (strcasecmp (arg, "none") == 0)
10034 operand_check = check_none;
10035 else
10036 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10037 break;
10038
539f890d
L		 10039 case OPTION_MAVXSCALAR:
10040 if (strcasecmp (arg, "128") == 0)
10041 avxscalar = vex128;
10042 else if (strcasecmp (arg, "256") == 0)
10043 avxscalar = vex256;
10044 else
2b5d6a91 10045 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10046 break;
10047
7e8b059b
L		 10048 case OPTION_MADD_BND_PREFIX:
10049 add_bnd_prefix = 1;
10050 break;
10051
43234a1e
L		 10052 case OPTION_MEVEXLIG:
10053 if (strcmp (arg, "128") == 0)
10054 evexlig = evexl128;
10055 else if (strcmp (arg, "256") == 0)
10056 evexlig = evexl256;
10057 else if (strcmp (arg, "512") == 0)
10058 evexlig = evexl512;
10059 else
10060 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10061 break;
10062
d3d3c6db
IT		 10063 case OPTION_MEVEXRCIG:
10064 if (strcmp (arg, "rne") == 0)
10065 evexrcig = rne;
10066 else if (strcmp (arg, "rd") == 0)
10067 evexrcig = rd;
10068 else if (strcmp (arg, "ru") == 0)
10069 evexrcig = ru;
10070 else if (strcmp (arg, "rz") == 0)
10071 evexrcig = rz;
10072 else
10073 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10074 break;
10075
43234a1e
L		 10076 case OPTION_MEVEXWIG:
10077 if (strcmp (arg, "0") == 0)
10078 evexwig = evexw0;
10079 else if (strcmp (arg, "1") == 0)
10080 evexwig = evexw1;
10081 else
10082 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10083 break;
10084
167ad85b
TG		 10085# if defined (TE_PE) || defined (TE_PEP)
10086 case OPTION_MBIG_OBJ:
10087 use_big_obj = 1;
10088 break;
10089#endif
10090
d1982f93 10091 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10092 if (strcasecmp (arg, "yes") == 0)
10093 omit_lock_prefix = 1;
10094 else if (strcasecmp (arg, "no") == 0)
10095 omit_lock_prefix = 0;
10096 else
10097 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10098 break;
10099
e4e00185
AS		 10100 case OPTION_MFENCE_AS_LOCK_ADD:
10101 if (strcasecmp (arg, "yes") == 0)
10102 avoid_fence = 1;
10103 else if (strcasecmp (arg, "no") == 0)
10104 avoid_fence = 0;
10105 else
10106 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10107 break;
10108
0cb4071e
L		 10109 case OPTION_MRELAX_RELOCATIONS:
10110 if (strcasecmp (arg, "yes") == 0)
10111 generate_relax_relocations = 1;
10112 else if (strcasecmp (arg, "no") == 0)
10113 generate_relax_relocations = 0;
10114 else
10115 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10116 break;
10117
5db04b09 10118 case OPTION_MAMD64:
e89c5eaa 10119 intel64 = 0;
5db04b09
L		 10120 break;
10121
10122 case OPTION_MINTEL64:
e89c5eaa 10123 intel64 = 1;
5db04b09
L		 10124 break;
10125
252b5132
RH		 10126 default:
10127 return 0;
10128 }
10129 return 1;
10130}
10131
8a2c8fef
L		 10132#define MESSAGE_TEMPLATE \
10133" "
10134
293f5f65
L		 10135static char *
10136output_message (FILE *stream, char *p, char *message, char *start,
10137 int *left_p, const char *name, int len)
10138{
10139 int size = sizeof (MESSAGE_TEMPLATE);
10140 int left = *left_p;
10141
10142 /* Reserve 2 spaces for ", " or ",\0" */
10143 left -= len + 2;
10144
10145 /* Check if there is any room. */
10146 if (left >= 0)
10147 {
10148 if (p != start)
10149 {
10150 *p++ = ',';
10151 *p++ = ' ';
10152 }
10153 p = mempcpy (p, name, len);
10154 }
10155 else
10156 {
10157 /* Output the current message now and start a new one. */
10158 *p++ = ',';
10159 *p = '\0';
10160 fprintf (stream, "%s\n", message);
10161 p = start;
10162 left = size - (start - message) - len - 2;
10163
10164 gas_assert (left >= 0);
10165
10166 p = mempcpy (p, name, len);
10167 }
10168
10169 *left_p = left;
10170 return p;
10171}
10172
8a2c8fef 10173static void
1ded5609 10174show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10175{
10176 static char message[] = MESSAGE_TEMPLATE;
10177 char *start = message + 27;
10178 char *p;
10179 int size = sizeof (MESSAGE_TEMPLATE);
10180 int left;
10181 const char *name;
10182 int len;
10183 unsigned int j;
10184
10185 p = start;
10186 left = size - (start - message);
10187 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10188 {
10189 /* Should it be skipped? */
10190 if (cpu_arch [j].skip)
10191 continue;
10192
10193 name = cpu_arch [j].name;
10194 len = cpu_arch [j].len;
10195 if (*name == '.')
10196 {
10197 /* It is an extension. Skip if we aren't asked to show it. */
10198 if (ext)
10199 {
10200 name++;
10201 len--;
10202 }
10203 else
10204 continue;
10205 }
10206 else if (ext)
10207 {
10208 /* It is an processor. Skip if we show only extension. */
10209 continue;
10210 }
1ded5609
JB		 10211 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10212 {
10213 /* It is an impossible processor - skip. */
10214 continue;
10215 }
8a2c8fef 10216
293f5f65 10217 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10218 }
10219
293f5f65
L		 10220 /* Display disabled extensions. */
10221 if (ext)
10222 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10223 {
10224 name = cpu_noarch [j].name;
10225 len = cpu_noarch [j].len;
10226 p = output_message (stream, p, message, start, &left, name,
10227 len);
10228 }
10229
8a2c8fef
L		 10230 *p = '\0';
10231 fprintf (stream, "%s\n", message);
10232}
10233
252b5132 10234void
8a2c8fef 10235md_show_usage (FILE *stream)
252b5132 10236{
4cc782b5
ILT		 10237#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10238 fprintf (stream, _("\
a38cf1db
AM		 10239 -Q ignored\n\
10240 -V print assembler version number\n\
b3b91714
AM		 10241 -k ignored\n"));
10242#endif
10243 fprintf (stream, _("\
12b55ccc 10244 -n Do not optimize code alignment\n\
b3b91714
AM		 10245 -q quieten some warnings\n"));
10246#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10247 fprintf (stream, _("\
a38cf1db 10248 -s ignored\n"));
b3b91714 10249#endif
321098a5
L		 10250#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10251 || defined (TE_PE) || defined (TE_PEP))
751d281c 10252 fprintf (stream, _("\
570561f7 10253 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10254#endif
b3b91714
AM		 10255#ifdef SVR4_COMMENT_CHARS
10256 fprintf (stream, _("\
10257 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10258#else
10259 fprintf (stream, _("\
b3b91714 10260 --divide ignored\n"));
4cc782b5 10261#endif
9103f4f4 10262 fprintf (stream, _("\
6305a203 10263 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10264 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10265 show_arch (stream, 0, 1);
8a2c8fef
L		 10266 fprintf (stream, _("\
10267 EXTENSION is combination of:\n"));
1ded5609 10268 show_arch (stream, 1, 0);
6305a203 10269 fprintf (stream, _("\
8a2c8fef 10270 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10271 show_arch (stream, 0, 0);
ba104c83 10272 fprintf (stream, _("\
c0f3af97
L		 10273 -msse2avx encode SSE instructions with VEX prefix\n"));
10274 fprintf (stream, _("\
daf50ae7
L		 10275 -msse-check=[none|error|warning]\n\
10276 check SSE instructions\n"));
10277 fprintf (stream, _("\
7bab8ab5
JB		 10278 -moperand-check=[none|error|warning]\n\
10279 check operand combinations for validity\n"));
10280 fprintf (stream, _("\
539f890d
L		 10281 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10282 length\n"));
10283 fprintf (stream, _("\
43234a1e
L		 10284 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10285 length\n"));
10286 fprintf (stream, _("\
10287 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10288 for EVEX.W bit ignored instructions\n"));
10289 fprintf (stream, _("\
d3d3c6db
IT		 10290 -mevexrcig=[rne|rd|ru|rz]\n\
10291 encode EVEX instructions with specific EVEX.RC value\n\
10292 for SAE-only ignored instructions\n"));
10293 fprintf (stream, _("\
ba104c83
L		 10294 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10295 fprintf (stream, _("\
10296 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10297 fprintf (stream, _("\
10298 -mindex-reg support pseudo index registers\n"));
10299 fprintf (stream, _("\
10300 -mnaked-reg don't require `%%' prefix for registers\n"));
10301 fprintf (stream, _("\
10302 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10303 fprintf (stream, _("\
10304 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10305 fprintf (stream, _("\
10306 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10307# if defined (TE_PE) || defined (TE_PEP)
10308 fprintf (stream, _("\
10309 -mbig-obj generate big object files\n"));
10310#endif
d022bddd
IT		 10311 fprintf (stream, _("\
10312 -momit-lock-prefix=[no|yes]\n\
10313 strip all lock prefixes\n"));
5db04b09 10314 fprintf (stream, _("\
e4e00185
AS		 10315 -mfence-as-lock-add=[no|yes]\n\
10316 encode lfence, mfence and sfence as\n\
10317 lock addl $0x0, (%%{re}sp)\n"));
10318 fprintf (stream, _("\
0cb4071e
L		 10319 -mrelax-relocations=[no|yes]\n\
10320 generate relax relocations\n"));
10321 fprintf (stream, _("\
5db04b09
L		 10322 -mamd64 accept only AMD64 ISA\n"));
10323 fprintf (stream, _("\
10324 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10325}
10326
3e73aa7c 10327#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10328 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10329 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10330
10331/* Pick the target format to use. */
10332
47926f60 10333const char *
e3bb37b5 10334i386_target_format (void)
252b5132 10335{
351f65ca
L		 10336 if (!strncmp (default_arch, "x86_64", 6))
10337 {
10338 update_code_flag (CODE_64BIT, 1);
10339 if (default_arch[6] == '\0')
7f56bc95 10340 x86_elf_abi = X86_64_ABI;
351f65ca 10341 else
7f56bc95 10342 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10343 }
3e73aa7c 10344 else if (!strcmp (default_arch, "i386"))
78f12dd3 10345 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10346 else if (!strcmp (default_arch, "iamcu"))
10347 {
10348 update_code_flag (CODE_32BIT, 1);
10349 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10350 {
10351 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10352 cpu_arch_name = "iamcu";
10353 cpu_sub_arch_name = NULL;
10354 cpu_arch_flags = iamcu_flags;
10355 cpu_arch_isa = PROCESSOR_IAMCU;
10356 cpu_arch_isa_flags = iamcu_flags;
10357 if (!cpu_arch_tune_set)
10358 {
10359 cpu_arch_tune = cpu_arch_isa;
10360 cpu_arch_tune_flags = cpu_arch_isa_flags;
10361 }
10362 }
10363 else
10364 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10365 cpu_arch_name);
10366 }
3e73aa7c 10367 else
2b5d6a91 10368 as_fatal (_("unknown architecture"));
89507696
JB		 10369
10370 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10371 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10372 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10373 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10374
252b5132
RH		 10375 switch (OUTPUT_FLAVOR)
10376 {
9384f2ff 10377#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10378 case bfd_target_aout_flavour:
47926f60 10379 return AOUT_TARGET_FORMAT;
4c63da97 10380#endif
9384f2ff
AM		 10381#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10382# if defined (TE_PE) || defined (TE_PEP)
10383 case bfd_target_coff_flavour:
167ad85b
TG		 10384 if (flag_code == CODE_64BIT)
10385 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10386 else
10387 return "pe-i386";
9384f2ff 10388# elif defined (TE_GO32)
0561d57c
JK		 10389 case bfd_target_coff_flavour:
10390 return "coff-go32";
9384f2ff 10391# else
252b5132
RH		 10392 case bfd_target_coff_flavour:
10393 return "coff-i386";
9384f2ff 10394# endif
4c63da97 10395#endif
3e73aa7c 10396#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10397 case bfd_target_elf_flavour:
3e73aa7c 10398 {
351f65ca
L		 10399 const char *format;
10400
10401 switch (x86_elf_abi)
4fa24527 10402 {
351f65ca
L		 10403 default:
10404 format = ELF_TARGET_FORMAT;
10405 break;
7f56bc95 10406 case X86_64_ABI:
351f65ca 10407 use_rela_relocations = 1;
4fa24527 10408 object_64bit = 1;
351f65ca
L		 10409 format = ELF_TARGET_FORMAT64;
10410 break;
7f56bc95 10411 case X86_64_X32_ABI:
4fa24527 10412 use_rela_relocations = 1;
351f65ca 10413 object_64bit = 1;
862be3fb 10414 disallow_64bit_reloc = 1;
351f65ca
L		 10415 format = ELF_TARGET_FORMAT32;
10416 break;
4fa24527 10417 }
3632d14b 10418 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10419 {
7f56bc95 10420 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10421 as_fatal (_("Intel L1OM is 64bit only"));
10422 return ELF_TARGET_L1OM_FORMAT;
10423 }
b49f93f6 10424 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10425 {
10426 if (x86_elf_abi != X86_64_ABI)
10427 as_fatal (_("Intel K1OM is 64bit only"));
10428 return ELF_TARGET_K1OM_FORMAT;
10429 }
81486035
L		 10430 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10431 {
10432 if (x86_elf_abi != I386_ABI)
10433 as_fatal (_("Intel MCU is 32bit only"));
10434 return ELF_TARGET_IAMCU_FORMAT;
10435 }
8a9036a4 10436 else
351f65ca 10437 return format;
3e73aa7c 10438 }
e57f8c65
TG		 10439#endif
10440#if defined (OBJ_MACH_O)
10441 case bfd_target_mach_o_flavour:
d382c579
TG		 10442 if (flag_code == CODE_64BIT)
10443 {
10444 use_rela_relocations = 1;
10445 object_64bit = 1;
10446 return "mach-o-x86-64";
10447 }
10448 else
10449 return "mach-o-i386";
4c63da97 10450#endif
252b5132
RH		 10451 default:
10452 abort ();
10453 return NULL;
10454 }
10455}
10456
47926f60 10457#endif /* OBJ_MAYBE_ more than one */
252b5132 10458\f
252b5132 10459symbolS *
7016a5d5 10460md_undefined_symbol (char *name)
252b5132 10461{
18dc2407
ILT		 10462 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10463 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10464 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10465 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10466 {
10467 if (!GOT_symbol)
10468 {
10469 if (symbol_find (name))
10470 as_bad (_("GOT already in symbol table"));
10471 GOT_symbol = symbol_new (name, undefined_section,
10472 (valueT) 0, &zero_address_frag);
10473 };
10474 return GOT_symbol;
10475 }
252b5132
RH		 10476 return 0;
10477}
10478
10479/* Round up a section size to the appropriate boundary. */
47926f60 10480
252b5132 10481valueT
7016a5d5 10482md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10483{
4c63da97
AM		 10484#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10485 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10486 {
10487 /* For a.out, force the section size to be aligned. If we don't do
10488 this, BFD will align it for us, but it will not write out the
10489 final bytes of the section. This may be a bug in BFD, but it is
10490 easier to fix it here since that is how the other a.out targets
10491 work. */
10492 int align;
10493
10494 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10495 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10496 }
252b5132
RH		 10497#endif
10498
10499 return size;
10500}
10501
10502/* On the i386, PC-relative offsets are relative to the start of the
10503 next instruction. That is, the address of the offset, plus its
10504 size, since the offset is always the last part of the insn. */
10505
10506long
e3bb37b5 10507md_pcrel_from (fixS *fixP)
252b5132
RH		 10508{
10509 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10510}
10511
10512#ifndef I386COFF
10513
10514static void
e3bb37b5 10515s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10516{
29b0f896 10517 int temp;
252b5132 10518
8a75718c
JB		 10519#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10520 if (IS_ELF)
10521 obj_elf_section_change_hook ();
10522#endif
252b5132
RH		 10523 temp = get_absolute_expression ();
10524 subseg_set (bss_section, (subsegT) temp);
10525 demand_empty_rest_of_line ();
10526}
10527
10528#endif
10529
252b5132 10530void
e3bb37b5 10531i386_validate_fix (fixS *fixp)
252b5132 10532{
02a86693 10533 if (fixp->fx_subsy)
252b5132 10534 {
02a86693 10535 if (fixp->fx_subsy == GOT_symbol)
23df1078 10536 {
02a86693
L		 10537 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10538 {
10539 if (!object_64bit)
10540 abort ();
10541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10542 if (fixp->fx_tcbit2)
56ceb5b5
L		 10543 fixp->fx_r_type = (fixp->fx_tcbit
10544 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10545 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10546 else
10547#endif
10548 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10549 }
d6ab8113 10550 else
02a86693
L		 10551 {
10552 if (!object_64bit)
10553 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10554 else
10555 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10556 }
10557 fixp->fx_subsy = 0;
23df1078 10558 }
252b5132 10559 }
02a86693
L		 10560#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10561 else if (!object_64bit)
10562 {
10563 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10564 && fixp->fx_tcbit2)
10565 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10566 }
10567#endif
252b5132
RH		 10568}
10569
252b5132 10570arelent *
7016a5d5 10571tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10572{
10573 arelent *rel;
10574 bfd_reloc_code_real_type code;
10575
10576 switch (fixp->fx_r_type)
10577 {
8ce3d284 10578#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10579 case BFD_RELOC_SIZE32:
10580 case BFD_RELOC_SIZE64:
10581 if (S_IS_DEFINED (fixp->fx_addsy)
10582 && !S_IS_EXTERNAL (fixp->fx_addsy))
10583 {
10584 /* Resolve size relocation against local symbol to size of
10585 the symbol plus addend. */
10586 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10587 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10588 && !fits_in_unsigned_long (value))
10589 as_bad_where (fixp->fx_file, fixp->fx_line,
10590 _("symbol size computation overflow"));
10591 fixp->fx_addsy = NULL;
10592 fixp->fx_subsy = NULL;
10593 md_apply_fix (fixp, (valueT *) &value, NULL);
10594 return NULL;
10595 }
8ce3d284 10596#endif
8fd4256d 10597
3e73aa7c
JH		 10598 case BFD_RELOC_X86_64_PLT32:
10599 case BFD_RELOC_X86_64_GOT32:
10600 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10601 case BFD_RELOC_X86_64_GOTPCRELX:
10602 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10603 case BFD_RELOC_386_PLT32:
10604 case BFD_RELOC_386_GOT32:
02a86693 10605 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10606 case BFD_RELOC_386_GOTOFF:
10607 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10608 case BFD_RELOC_386_TLS_GD:
10609 case BFD_RELOC_386_TLS_LDM:
10610 case BFD_RELOC_386_TLS_LDO_32:
10611 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10612 case BFD_RELOC_386_TLS_IE:
10613 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10614 case BFD_RELOC_386_TLS_LE_32:
10615 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10616 case BFD_RELOC_386_TLS_GOTDESC:
10617 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10618 case BFD_RELOC_X86_64_TLSGD:
10619 case BFD_RELOC_X86_64_TLSLD:
10620 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10621 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10622 case BFD_RELOC_X86_64_GOTTPOFF:
10623 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10624 case BFD_RELOC_X86_64_TPOFF64:
10625 case BFD_RELOC_X86_64_GOTOFF64:
10626 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10627 case BFD_RELOC_X86_64_GOT64:
10628 case BFD_RELOC_X86_64_GOTPCREL64:
10629 case BFD_RELOC_X86_64_GOTPC64:
10630 case BFD_RELOC_X86_64_GOTPLT64:
10631 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10632 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10633 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10634 case BFD_RELOC_RVA:
10635 case BFD_RELOC_VTABLE_ENTRY:
10636 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10637#ifdef TE_PE
10638 case BFD_RELOC_32_SECREL:
10639#endif
252b5132
RH		 10640 code = fixp->fx_r_type;
10641 break;
dbbaec26
L		 10642 case BFD_RELOC_X86_64_32S:
10643 if (!fixp->fx_pcrel)
10644 {
10645 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10646 code = fixp->fx_r_type;
10647 break;
10648 }
252b5132 10649 default:
93382f6d 10650 if (fixp->fx_pcrel)
252b5132 10651 {
93382f6d
AM		 10652 switch (fixp->fx_size)
10653 {
10654 default:
b091f402
AM		 10655 as_bad_where (fixp->fx_file, fixp->fx_line,
10656 _("can not do %d byte pc-relative relocation"),
10657 fixp->fx_size);
93382f6d
AM		 10658 code = BFD_RELOC_32_PCREL;
10659 break;
10660 case 1: code = BFD_RELOC_8_PCREL; break;
10661 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10662 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10663#ifdef BFD64
10664 case 8: code = BFD_RELOC_64_PCREL; break;
10665#endif
93382f6d
AM		 10666 }
10667 }
10668 else
10669 {
10670 switch (fixp->fx_size)
10671 {
10672 default:
b091f402
AM		 10673 as_bad_where (fixp->fx_file, fixp->fx_line,
10674 _("can not do %d byte relocation"),
10675 fixp->fx_size);
93382f6d
AM		 10676 code = BFD_RELOC_32;
10677 break;
10678 case 1: code = BFD_RELOC_8; break;
10679 case 2: code = BFD_RELOC_16; break;
10680 case 4: code = BFD_RELOC_32; break;
937149dd 10681#ifdef BFD64
3e73aa7c 10682 case 8: code = BFD_RELOC_64; break;
937149dd 10683#endif
93382f6d 10684 }
252b5132
RH		 10685 }
10686 break;
10687 }
252b5132 10688
d182319b
JB		 10689 if ((code == BFD_RELOC_32
10690 || code == BFD_RELOC_32_PCREL
10691 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10692 && GOT_symbol
10693 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10694 {
4fa24527 10695 if (!object_64bit)
d6ab8113
JB		 10696 code = BFD_RELOC_386_GOTPC;
10697 else
10698 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10699 }
7b81dfbb
AJ		 10700 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10701 && GOT_symbol
10702 && fixp->fx_addsy == GOT_symbol)
10703 {
10704 code = BFD_RELOC_X86_64_GOTPC64;
10705 }
252b5132 10706
add39d23
TS		 10707 rel = XNEW (arelent);
10708 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10709 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10710
10711 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10712
3e73aa7c
JH		 10713 if (!use_rela_relocations)
10714 {
10715 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10716 vtable entry to be used in the relocation's section offset. */
10717 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10718 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10719#if defined (OBJ_COFF) && defined (TE_PE)
10720 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10721 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10722 else
10723#endif
c6682705 10724 rel->addend = 0;
3e73aa7c
JH		 10725 }
10726 /* Use the rela in 64bit mode. */
252b5132 10727 else
3e73aa7c 10728 {
862be3fb
L		 10729 if (disallow_64bit_reloc)
10730 switch (code)
10731 {
862be3fb
L		 10732 case BFD_RELOC_X86_64_DTPOFF64:
10733 case BFD_RELOC_X86_64_TPOFF64:
10734 case BFD_RELOC_64_PCREL:
10735 case BFD_RELOC_X86_64_GOTOFF64:
10736 case BFD_RELOC_X86_64_GOT64:
10737 case BFD_RELOC_X86_64_GOTPCREL64:
10738 case BFD_RELOC_X86_64_GOTPC64:
10739 case BFD_RELOC_X86_64_GOTPLT64:
10740 case BFD_RELOC_X86_64_PLTOFF64:
10741 as_bad_where (fixp->fx_file, fixp->fx_line,
10742 _("cannot represent relocation type %s in x32 mode"),
10743 bfd_get_reloc_code_name (code));
10744 break;
10745 default:
10746 break;
10747 }
10748
062cd5e7
AS		 10749 if (!fixp->fx_pcrel)
10750 rel->addend = fixp->fx_offset;
10751 else
10752 switch (code)
10753 {
10754 case BFD_RELOC_X86_64_PLT32:
10755 case BFD_RELOC_X86_64_GOT32:
10756 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10757 case BFD_RELOC_X86_64_GOTPCRELX:
10758 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10759 case BFD_RELOC_X86_64_TLSGD:
10760 case BFD_RELOC_X86_64_TLSLD:
10761 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10762 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10763 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10764 rel->addend = fixp->fx_offset - fixp->fx_size;
10765 break;
10766 default:
10767 rel->addend = (section->vma
10768 - fixp->fx_size
10769 + fixp->fx_addnumber
10770 + md_pcrel_from (fixp));
10771 break;
10772 }
3e73aa7c
JH		 10773 }
10774
252b5132
RH		 10775 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10776 if (rel->howto == NULL)
10777 {
10778 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10779 _("cannot represent relocation type %s"),
252b5132
RH		 10780 bfd_get_reloc_code_name (code));
10781 /* Set howto to a garbage value so that we can keep going. */
10782 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10783 gas_assert (rel->howto != NULL);
252b5132
RH		 10784 }
10785
10786 return rel;
10787}
10788
ee86248c 10789#include "tc-i386-intel.c"
54cfded0 10790
a60de03c
JB		 10791void
10792tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10793{
a60de03c
JB		 10794 int saved_naked_reg;
10795 char saved_register_dot;
54cfded0 10796
a60de03c
JB		 10797 saved_naked_reg = allow_naked_reg;
10798 allow_naked_reg = 1;
10799 saved_register_dot = register_chars['.'];
10800 register_chars['.'] = '.';
10801 allow_pseudo_reg = 1;
10802 expression_and_evaluate (exp);
10803 allow_pseudo_reg = 0;
10804 register_chars['.'] = saved_register_dot;
10805 allow_naked_reg = saved_naked_reg;
10806
e96d56a1 10807 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10808 {
a60de03c
JB		 10809 if ((addressT) exp->X_add_number < i386_regtab_size)
10810 {
10811 exp->X_op = O_constant;
10812 exp->X_add_number = i386_regtab[exp->X_add_number]
10813 .dw2_regnum[flag_code >> 1];
10814 }
10815 else
10816 exp->X_op = O_illegal;
54cfded0 10817 }
54cfded0
AM		 10818}
10819
10820void
10821tc_x86_frame_initial_instructions (void)
10822{
a60de03c
JB		 10823 static unsigned int sp_regno[2];
10824
10825 if (!sp_regno[flag_code >> 1])
10826 {
10827 char *saved_input = input_line_pointer;
10828 char sp[][4] = {"esp", "rsp"};
10829 expressionS exp;
a4447b93 10830
a60de03c
JB		 10831 input_line_pointer = sp[flag_code >> 1];
10832 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10833 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10834 sp_regno[flag_code >> 1] = exp.X_add_number;
10835 input_line_pointer = saved_input;
10836 }
a4447b93 10837
61ff971f
L		 10838 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10839 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10840}
d2b2c203 10841
d7921315
L		 10842int
10843x86_dwarf2_addr_size (void)
10844{
10845#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10846 if (x86_elf_abi == X86_64_X32_ABI)
10847 return 4;
10848#endif
10849 return bfd_arch_bits_per_address (stdoutput) / 8;
10850}
10851
d2b2c203
DJ		 10852int
10853i386_elf_section_type (const char *str, size_t len)
10854{
10855 if (flag_code == CODE_64BIT
10856 && len == sizeof ("unwind") - 1
10857 && strncmp (str, "unwind", 6) == 0)
10858 return SHT_X86_64_UNWIND;
10859
10860 return -1;
10861}
bb41ade5 10862
ad5fec3b
EB		 10863#ifdef TE_SOLARIS
10864void
10865i386_solaris_fix_up_eh_frame (segT sec)
10866{
10867 if (flag_code == CODE_64BIT)
10868 elf_section_type (sec) = SHT_X86_64_UNWIND;
10869}
10870#endif
10871
bb41ade5
AM		 10872#ifdef TE_PE
10873void
10874tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10875{
91d6fa6a 10876 expressionS exp;
bb41ade5 10877
91d6fa6a
NC		 10878 exp.X_op = O_secrel;
10879 exp.X_add_symbol = symbol;
10880 exp.X_add_number = 0;
10881 emit_expr (&exp, size);
bb41ade5
AM		 10882}
10883#endif
3b22753a
L		 10884
10885#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10886/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10887
01e1a5bc 10888bfd_vma
6d4af3c2 10889x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10890{
10891 if (flag_code == CODE_64BIT)
10892 {
10893 if (letter == 'l')
10894 return SHF_X86_64_LARGE;
10895
8f3bae45 10896 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10897 }
3b22753a 10898 else
8f3bae45 10899 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10900 return -1;
10901}
10902
01e1a5bc 10903bfd_vma
3b22753a
L		 10904x86_64_section_word (char *str, size_t len)
10905{
8620418b 10906 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10907 return SHF_X86_64_LARGE;
10908
10909 return -1;
10910}
10911
10912static void
10913handle_large_common (int small ATTRIBUTE_UNUSED)
10914{
10915 if (flag_code != CODE_64BIT)
10916 {
10917 s_comm_internal (0, elf_common_parse);
10918 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10919 }
10920 else
10921 {
10922 static segT lbss_section;
10923 asection *saved_com_section_ptr = elf_com_section_ptr;
10924 asection *saved_bss_section = bss_section;
10925
10926 if (lbss_section == NULL)
10927 {
10928 flagword applicable;
10929 segT seg = now_seg;
10930 subsegT subseg = now_subseg;
10931
10932 /* The .lbss section is for local .largecomm symbols. */
10933 lbss_section = subseg_new (".lbss", 0);
10934 applicable = bfd_applicable_section_flags (stdoutput);
10935 bfd_set_section_flags (stdoutput, lbss_section,
10936 applicable & SEC_ALLOC);
10937 seg_info (lbss_section)->bss = 1;
10938
10939 subseg_set (seg, subseg);
10940 }
10941
10942 elf_com_section_ptr = &_bfd_elf_large_com_section;
10943 bss_section = lbss_section;
10944
10945 s_comm_internal (0, elf_common_parse);
10946
10947 elf_com_section_ptr = saved_com_section_ptr;
10948 bss_section = saved_bss_section;
10949 }
10950}
10951#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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