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x86: drop VecESize
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e
RM		 434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
29b0f896 436 && !defined (TE_FreeBSD) \
5b806d27 437 && !defined (TE_DragonFly) \
29b0f896 438 && !defined (TE_NetBSD)))
252b5132 439/* This array holds the chars that always start a comment. If the
b3b91714
AM		 440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442const char *i386_comment_chars = "#/";
443#define SVR4_COMMENT_CHARS 1
252b5132 444#define PREFIX_SEPARATOR '\\'
252b5132 445
b3b91714
AM		 446#else
447const char *i386_comment_chars = "#";
448#define PREFIX_SEPARATOR '/'
449#endif
450
252b5132
RH		 451/* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 455 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
252b5132 458 '/' isn't otherwise defined. */
b3b91714 459const char line_comment_chars[] = "#/";
252b5132 460
63a0b638 461const char line_separator_chars[] = ";";
252b5132 462
ce8a8b2f
AM		 463/* Chars that can be used to separate mant from exp in floating point
464 nums. */
252b5132
RH		 465const char EXP_CHARS[] = "eE";
466
ce8a8b2f
AM		 467/* Chars that mean this number is a floating point constant
468 As in 0f12.456
469 or 0d1.2345e12. */
252b5132
RH		 470const char FLT_CHARS[] = "fFdDxX";
471
ce8a8b2f 472/* Tables for lexical analysis. */
252b5132
RH		 473static char mnemonic_chars[256];
474static char register_chars[256];
475static char operand_chars[256];
476static char identifier_chars[256];
477static char digit_chars[256];
478
ce8a8b2f 479/* Lexical macros. */
252b5132
RH		 480#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481#define is_operand_char(x) (operand_chars[(unsigned char) x])
482#define is_register_char(x) (register_chars[(unsigned char) x])
483#define is_space_char(x) ((x) == ' ')
484#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485#define is_digit_char(x) (digit_chars[(unsigned char) x])
486
0234cb7c 487/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 488static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489
490/* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
47926f60 493 assembler instruction). */
252b5132 494static char save_stack[32];
ce8a8b2f 495static char *save_stack_p;
252b5132
RH		 496#define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498#define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
500
47926f60 501/* The instruction we're assembling. */
252b5132
RH		 502static i386_insn i;
503
504/* Possible templates for current insn. */
505static const templates *current_templates;
506
31b2323c
L		 507/* Per instruction expressionS buffers: max displacements & immediates. */
508static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 510
47926f60 511/* Current operand we are working on. */
ee86248c 512static int this_operand = -1;
252b5132 513
3e73aa7c
JH		 514/* We support four different modes. FLAG_CODE variable is used to distinguish
515 these. */
516
517enum flag_code {
518 CODE_32BIT,
519 CODE_16BIT,
520 CODE_64BIT };
521
522static enum flag_code flag_code;
4fa24527 523static unsigned int object_64bit;
862be3fb 524static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 525static int use_rela_relocations = 0;
526
7af8ed2d
NC		 527#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530
351f65ca
L		 531/* The ELF ABI to use. */
532enum x86_elf_abi
533{
534 I386_ABI,
7f56bc95
L		 535 X86_64_ABI,
536 X86_64_X32_ABI
351f65ca
L		 537};
538
539static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 540#endif
351f65ca 541
167ad85b
TG		 542#if defined (TE_PE) || defined (TE_PEP)
543/* Use big object file format. */
544static int use_big_obj = 0;
545#endif
546
8dcea932
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548/* 1 if generating code for a shared library. */
549static int shared = 0;
550#endif
551
47926f60
KH		 552/* 1 for intel syntax,
553 0 if att syntax. */
554static int intel_syntax = 0;
252b5132 555
e89c5eaa
L		 556/* 1 for Intel64 ISA,
557 0 if AMD64 ISA. */
558static int intel64;
559
1efbbeb4
L		 560/* 1 for intel mnemonic,
561 0 if att mnemonic. */
562static int intel_mnemonic = !SYSV386_COMPAT;
563
a60de03c
JB		 564/* 1 if pseudo registers are permitted. */
565static int allow_pseudo_reg = 0;
566
47926f60
KH		 567/* 1 if register prefix % not required. */
568static int allow_naked_reg = 0;
252b5132 569
33eaf5de 570/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 571 instructions supporting it, even if this prefix wasn't specified
572 explicitly. */
573static int add_bnd_prefix = 0;
574
ba104c83 575/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 576static int allow_index_reg = 0;
577
d022bddd
IT		 578/* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580static int omit_lock_prefix = 0;
581
e4e00185
AS		 582/* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584static int avoid_fence = 0;
585
0cb4071e
L		 586/* 1 if the assembler should generate relax relocations. */
587
588static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590
7bab8ab5 591static enum check_kind
daf50ae7 592 {
7bab8ab5
JB		 593 check_none = 0,
594 check_warning,
595 check_error
daf50ae7 596 }
7bab8ab5 597sse_check, operand_check = check_warning;
daf50ae7 598
b6f8c7c4
L		 599/* Optimization:
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
602 register.
603 */
604static int optimize = 0;
605
606/* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 "testb $imm7,%r8".
612 */
613static int optimize_for_space = 0;
614
2ca3ace5
L		 615/* Register prefix used for error message. */
616static const char *register_prefix = "%";
617
47926f60
KH		 618/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621static char stackop_size = '\0';
eecb386c 622
12b55ccc
L		 623/* Non-zero to optimize code alignment. */
624int optimize_align_code = 1;
625
47926f60
KH		 626/* Non-zero to quieten some warnings. */
627static int quiet_warnings = 0;
a38cf1db 628
47926f60
KH		 629/* CPU name. */
630static const char *cpu_arch_name = NULL;
6305a203 631static char *cpu_sub_arch_name = NULL;
a38cf1db 632
47926f60 633/* CPU feature flags. */
40fb9820
L		 634static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635
ccc9c027
L		 636/* If we have selected a cpu we are generating instructions for. */
637static int cpu_arch_tune_set = 0;
638
9103f4f4 639/* Cpu we are generating instructions for. */
fbf3f584 640enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 641
642/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 643static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 644
ccc9c027 645/* CPU instruction set architecture used. */
fbf3f584 646enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 647
9103f4f4 648/* CPU feature flags of instruction set architecture used. */
fbf3f584 649i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 650
fddf5b5b
AM		 651/* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653static unsigned int no_cond_jump_promotion = 0;
654
c0f3af97
L		 655/* Encode SSE instructions with VEX prefix. */
656static unsigned int sse2avx;
657
539f890d
L		 658/* Encode scalar AVX instructions with specific vector length. */
659static enum
660 {
661 vex128 = 0,
662 vex256
663 } avxscalar;
664
43234a1e
L		 665/* Encode scalar EVEX LIG instructions with specific vector length. */
666static enum
667 {
668 evexl128 = 0,
669 evexl256,
670 evexl512
671 } evexlig;
672
673/* Encode EVEX WIG instructions with specific evex.w. */
674static enum
675 {
676 evexw0 = 0,
677 evexw1
678 } evexwig;
679
d3d3c6db
IT		 680/* Value to encode in EVEX RC bits, for SAE-only instructions. */
681static enum rc_type evexrcig = rne;
682
29b0f896 683/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 684static symbolS *GOT_symbol;
29b0f896 685
a4447b93
RH		 686/* The dwarf2 return column, adjusted for 32 or 64 bit. */
687unsigned int x86_dwarf2_return_column;
688
689/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690int x86_cie_data_alignment;
691
252b5132 692/* Interface to relax_segment.
fddf5b5b
AM		 693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
252b5132 696
47926f60 697/* Types. */
93c2a809
AM		 698#define UNCOND_JUMP 0
699#define COND_JUMP 1
700#define COND_JUMP86 2
fddf5b5b 701
47926f60 702/* Sizes. */
252b5132
RH		 703#define CODE16 1
704#define SMALL 0
29b0f896 705#define SMALL16 (SMALL | CODE16)
252b5132 706#define BIG 2
29b0f896 707#define BIG16 (BIG | CODE16)
252b5132
RH		 708
709#ifndef INLINE
710#ifdef __GNUC__
711#define INLINE __inline__
712#else
713#define INLINE
714#endif
715#endif
716
fddf5b5b
AM		 717#define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719#define TYPE_FROM_RELAX_STATE(s) \
720 ((s) >> 2)
721#define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 723
724/* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
731
732const relax_typeS md_relax_table[] =
733{
24eab124
AM		 734 /* The fields are:
735 1) most positive reach of this state,
736 2) most negative reach of this state,
93c2a809 737 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 738 4) which index into the table to try if we can't fit into this one. */
252b5132 739
fddf5b5b 740 /* UNCOND_JUMP states. */
93c2a809
AM		 741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
252b5132 745 {0, 0, 4, 0},
93c2a809
AM		 746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 748 {0, 0, 2, 0},
749
93c2a809
AM		 750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
755 {0, 0, 5, 0},
fddf5b5b 756 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 757 1 extra opcode byte, 2 displacement bytes. */
758 {0, 0, 3, 0},
759
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
765 {0, 0, 5, 0},
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
768 {0, 0, 4, 0}
252b5132
RH		 769};
770
9103f4f4
L		 771static const arch_entry cpu_arch[] =
772{
89507696
JB		 773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
8a2c8fef 775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 776 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 778 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 780 CPU_NONE_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 782 CPU_I186_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 784 CPU_I286_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 786 CPU_I386_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 788 CPU_I486_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 790 CPU_I586_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 792 CPU_I686_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 794 CPU_I586_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 796 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 798 CPU_P2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 800 CPU_P3_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 802 CPU_P4_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 804 CPU_CORE_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 806 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 808 CPU_CORE_FLAGS, 1 },
8a2c8fef 809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 810 CPU_CORE_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 812 CPU_CORE2_FLAGS, 1 },
8a2c8fef 813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 814 CPU_CORE2_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 816 CPU_COREI7_FLAGS, 0 },
8a2c8fef 817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 818 CPU_L1OM_FLAGS, 0 },
7a9068fe 819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 820 CPU_K1OM_FLAGS, 0 },
81486035 821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 822 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 824 CPU_K6_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 826 CPU_K6_2_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 828 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 830 CPU_K8_FLAGS, 1 },
8a2c8fef 831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 832 CPU_K8_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 834 CPU_K8_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 836 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 838 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 840 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 842 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 844 CPU_BDVER4_FLAGS, 0 },
029f3522 845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 846 CPU_ZNVER1_FLAGS, 0 },
7b458c12 847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 848 CPU_BTVER1_FLAGS, 0 },
7b458c12 849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 850 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_8087_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_287_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_387_FLAGS, 0 },
1848e567
L		 857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_MMX_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_SSE_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_SSE2_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_SSE3_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX_FLAGS, 0 },
6c30d220 877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX2_FLAGS, 0 },
43234a1e 879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AVX512F_FLAGS, 0 },
43234a1e 881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_AVX512CD_FLAGS, 0 },
43234a1e 883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_AVX512ER_FLAGS, 0 },
43234a1e 885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_VMX_FLAGS, 0 },
8729a6f6 895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_SMX_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_AES_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_F16C_FLAGS, 0 },
6c30d220 919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_BMI2_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_FMA_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_FMA4_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_XOP_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_LWP_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_MOVBE_FLAGS, 0 },
60aa667e 931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_CX16_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_EPT_FLAGS, 0 },
6c30d220 935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_LZCNT_FLAGS, 0 },
42164a71 937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_HLE_FLAGS, 0 },
42164a71 939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_RTM_FLAGS, 0 },
6c30d220 941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_CLFLUSH_FLAGS, 0 },
22109423 945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_NOP_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SVME_FLAGS, 1 },
8a2c8fef 959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_SVME_FLAGS, 0 },
8a2c8fef 961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_ABM_FLAGS, 0 },
87973e9f 965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_BMI_FLAGS, 0 },
2a2a0f38 967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_TBM_FLAGS, 0 },
e2e1fcde 969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_ADX_FLAGS, 0 },
e2e1fcde 971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_PRFCHW_FLAGS, 0 },
5c111e37 975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_SMAP_FLAGS, 0 },
7e8b059b 977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_MPX_FLAGS, 0 },
a0046408 979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_SHA_FLAGS, 0 },
963f3586 981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_SE1_FLAGS, 0 },
c5e7287a 987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1006 CPU_CLZERO_FLAGS, 0 },
9916071f 1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1008 CPU_MWAITX_FLAGS, 0 },
8eab4136 1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_OSPKE_FLAGS, 0 },
8bc52696 1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
293f5f65
L		 1029};
1030
1031static const noarch_entry cpu_noarch[] =
1032{
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1064};
1065
704209c0 1066#ifdef I386COFF
a6c24e68
NC		 1067/* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1069
1070static symbolS *
1071pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1072{
1073 addressT align = 0;
1074
1075 SKIP_WHITESPACE ();
1076
7ab9ffdd 1077 if (needs_align
a6c24e68
NC		 1078 && *input_line_pointer == ',')
1079 {
1080 align = parse_align (needs_align - 1);
7ab9ffdd 1081
a6c24e68
NC		 1082 if (align == (addressT) -1)
1083 return NULL;
1084 }
1085 else
1086 {
1087 if (size >= 8)
1088 align = 3;
1089 else if (size >= 4)
1090 align = 2;
1091 else if (size >= 2)
1092 align = 1;
1093 else
1094 align = 0;
1095 }
1096
1097 bss_alloc (symbolP, size, align);
1098 return symbolP;
1099}
1100
704209c0 1101static void
a6c24e68
NC		 1102pe_lcomm (int needs_align)
1103{
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1105}
704209c0 1106#endif
a6c24e68 1107
29b0f896
AM		 1108const pseudo_typeS md_pseudo_table[] =
1109{
1110#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1112#else
1113 {"align", s_align_ptwo, 0},
1114#endif
1115 {"arch", set_cpu_arch, 0},
1116#ifndef I386COFF
1117 {"bss", s_bss, 0},
a6c24e68
NC		 1118#else
1119 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1120#endif
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1124 {"value", cons, 2},
d182319b 1125 {"slong", signed_cons, 4},
29b0f896
AM		 1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1131#ifdef BFD64
29b0f896 1132 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1133#endif
29b0f896
AM		 1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
3b22753a
L		 1142#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
07a53e5c 1144#else
68d20676 1145 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1148#endif
6482c264
NC		 1149#ifdef TE_PE
1150 {"secrel32", pe_directive_secrel, 0},
1151#endif
29b0f896
AM		 1152 {0, 0, 0}
1153};
1154
1155/* For interface with expression (). */
1156extern char *input_line_pointer;
1157
1158/* Hash table for instruction mnemonic lookup. */
1159static struct hash_control *op_hash;
1160
1161/* Hash table for register lookup. */
1162static struct hash_control *reg_hash;
1163\f
ce8a8b2f
AM		 1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
62a02d25
L		 1167static const unsigned char f32_1[] =
1168 {0x90}; /* nop */
1169static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1175static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1179static const unsigned char f16_3[] =
3ae729d5 1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1181static const unsigned char f16_4[] =
3ae729d5
L		 1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1189/* 32-bit NOPs patterns. */
1190static const unsigned char *const f32_patt[] = {
3ae729d5 1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1192};
1193/* 16-bit NOPs patterns. */
1194static const unsigned char *const f16_patt[] = {
3ae729d5 1195 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1196};
1197/* nopl (%[re]ax) */
1198static const unsigned char alt_3[] =
1199 {0x0f,0x1f,0x00};
1200/* nopl 0(%[re]ax) */
1201static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203/* nopl 0(%[re]ax,%[re]ax,1) */
1204static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206/* nopw 0(%[re]ax,%[re]ax,1) */
1207static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209/* nopl 0L(%[re]ax) */
1210static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212/* nopl 0L(%[re]ax,%[re]ax,1) */
1213static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215/* nopw 0L(%[re]ax,%[re]ax,1) */
1216static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1221/* data16 nopw %cs:0L(%eax,%eax,1) */
1222static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1224/* 32-bit and 64-bit NOPs patterns. */
1225static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1227 alt_9, alt_10, alt_11
62a02d25
L		 1228};
1229
1230/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1232
1233static void
1234i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1236
1237{
3ae729d5
L		 1238 /* Place the longer NOP first. */
1239 int last;
1240 int offset;
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1242
1243 /* Use the smaller one if the requsted one isn't available. */
1244 if (nops == NULL)
62a02d25 1245 {
3ae729d5
L		 1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1248 }
1249
3ae729d5
L		 1250 last = count % max_single_nop_size;
1251
1252 count -= last;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1255
1256 if (last)
1257 {
1258 nops = patt[last - 1];
1259 if (nops == NULL)
1260 {
1261 /* Use the smaller one plus one-byte NOP if the needed one
1262 isn't available. */
1263 last--;
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1267 }
1268 else
1269 memcpy (where + offset, nops, last);
1270 }
62a02d25
L		 1271}
1272
3ae729d5
L		 1273static INLINE int
1274fits_in_imm7 (offsetT num)
1275{
1276 return (num & 0x7f) == num;
1277}
1278
1279static INLINE int
1280fits_in_imm31 (offsetT num)
1281{
1282 return (num & 0x7fffffff) == num;
1283}
62a02d25
L		 1284
1285/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1287
1288void
3ae729d5 1289i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1290{
3ae729d5 1291 const unsigned char *const *patt = NULL;
62a02d25 1292 int max_single_nop_size;
3ae729d5
L		 1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
62a02d25 1295
3ae729d5 1296 switch (fragP->fr_type)
62a02d25 1297 {
3ae729d5
L		 1298 case rs_fill_nop:
1299 case rs_align_code:
1300 break;
1301 default:
62a02d25
L		 1302 return;
1303 }
1304
ccc9c027
L		 1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
4eed87de 1307
76bc74dc
L		 1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1310 2. For the rest, alt_patt will be used.
1311
1312 When -mtune= isn't used, alt_patt will be used if
22109423 1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1314 be used.
ccc9c027
L		 1315
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1318
1319 if (flag_code == CODE_16BIT)
1320 {
3ae729d5
L		 1321 patt = f16_patt;
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
252b5132 1325 }
33fef721 1326 else
ccc9c027 1327 {
fbf3f584 1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1329 {
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1332 {
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1337 patt = alt_patt;
ccc9c027
L		 1338 else
1339 patt = f32_patt;
1340 break;
ccc9c027
L		 1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
ef05d495 1343 case PROCESSOR_CORE:
76bc74dc 1344 case PROCESSOR_CORE2:
bd5295b2 1345 case PROCESSOR_COREI7:
3632d14b 1346 case PROCESSOR_L1OM:
7a9068fe 1347 case PROCESSOR_K1OM:
76bc74dc 1348 case PROCESSOR_GENERIC64:
ccc9c027
L		 1349 case PROCESSOR_K6:
1350 case PROCESSOR_ATHLON:
1351 case PROCESSOR_K8:
4eed87de 1352 case PROCESSOR_AMDFAM10:
8aedb9fe 1353 case PROCESSOR_BD:
029f3522 1354 case PROCESSOR_ZNVER:
7b458c12 1355 case PROCESSOR_BT:
80b8656c 1356 patt = alt_patt;
ccc9c027 1357 break;
76bc74dc 1358 case PROCESSOR_I386:
ccc9c027
L		 1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
2dde1948 1361 case PROCESSOR_PENTIUMPRO:
81486035 1362 case PROCESSOR_IAMCU:
ccc9c027
L		 1363 case PROCESSOR_GENERIC32:
1364 patt = f32_patt;
1365 break;
4eed87de 1366 }
ccc9c027
L		 1367 }
1368 else
1369 {
fbf3f584 1370 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1371 {
1372 case PROCESSOR_UNKNOWN:
e6a14101 1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1374 PROCESSOR_UNKNOWN. */
1375 abort ();
1376 break;
1377
76bc74dc 1378 case PROCESSOR_I386:
ccc9c027
L		 1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
81486035 1381 case PROCESSOR_IAMCU:
ccc9c027
L		 1382 case PROCESSOR_K6:
1383 case PROCESSOR_ATHLON:
1384 case PROCESSOR_K8:
4eed87de 1385 case PROCESSOR_AMDFAM10:
8aedb9fe 1386 case PROCESSOR_BD:
029f3522 1387 case PROCESSOR_ZNVER:
7b458c12 1388 case PROCESSOR_BT:
ccc9c027
L		 1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1391 with nops. */
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1393 patt = alt_patt;
ccc9c027
L		 1394 else
1395 patt = f32_patt;
1396 break;
76bc74dc
L		 1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
ef05d495 1401 case PROCESSOR_CORE2:
bd5295b2 1402 case PROCESSOR_COREI7:
3632d14b 1403 case PROCESSOR_L1OM:
7a9068fe 1404 case PROCESSOR_K1OM:
22109423 1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1406 patt = alt_patt;
ccc9c027
L		 1407 else
1408 patt = f32_patt;
1409 break;
1410 case PROCESSOR_GENERIC64:
80b8656c 1411 patt = alt_patt;
ccc9c027 1412 break;
4eed87de 1413 }
ccc9c027
L		 1414 }
1415
76bc74dc
L		 1416 if (patt == f32_patt)
1417 {
3ae729d5
L		 1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
76bc74dc
L		 1421 }
1422 else
1423 {
3ae729d5
L		 1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1427 }
1428 }
1429
1430 if (limit == 0)
1431 limit = max_single_nop_size;
1432
1433 if (fragP->fr_type == rs_fill_nop)
1434 {
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1437 {
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1442 return;
1443 }
1444 }
1445 else
1446 fragP->fr_var = count;
1447
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1449 {
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1453 {
1454 /* Use "jmp disp8" if possible. */
1455 count = disp;
1456 where[0] = jump_disp8[0];
1457 where[1] = count;
1458 where += 2;
1459 }
1460 else
1461 {
1462 unsigned int size_of_jump;
1463
1464 if (flag_code == CODE_16BIT)
1465 {
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1468 size_of_jump = 2;
1469 }
1470 else
1471 {
1472 where[0] = jump32_disp32[0];
1473 size_of_jump = 1;
1474 }
1475
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1478 {
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1481 return;
1482 }
1483
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
76bc74dc 1486 }
ccc9c027 1487 }
3ae729d5
L		 1488
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1491}
1492
c6fb90c8 1493static INLINE int
0dfbf9d7 1494operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1495{
0dfbf9d7 1496 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1497 {
1498 case 3:
0dfbf9d7 1499 if (x->array[2])
c6fb90c8 1500 return 0;
1a0670f3 1501 /* Fall through. */
c6fb90c8 1502 case 2:
0dfbf9d7 1503 if (x->array[1])
c6fb90c8 1504 return 0;
1a0670f3 1505 /* Fall through. */
c6fb90c8 1506 case 1:
0dfbf9d7 1507 return !x->array[0];
c6fb90c8
L		 1508 default:
1509 abort ();
1510 }
40fb9820
L		 1511}
1512
c6fb90c8 1513static INLINE void
0dfbf9d7 1514operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1515{
0dfbf9d7 1516 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1517 {
1518 case 3:
0dfbf9d7 1519 x->array[2] = v;
1a0670f3 1520 /* Fall through. */
c6fb90c8 1521 case 2:
0dfbf9d7 1522 x->array[1] = v;
1a0670f3 1523 /* Fall through. */
c6fb90c8 1524 case 1:
0dfbf9d7 1525 x->array[0] = v;
1a0670f3 1526 /* Fall through. */
c6fb90c8
L		 1527 break;
1528 default:
1529 abort ();
1530 }
1531}
40fb9820 1532
c6fb90c8 1533static INLINE int
0dfbf9d7
L		 1534operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
c6fb90c8 1536{
0dfbf9d7 1537 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1538 {
1539 case 3:
0dfbf9d7 1540 if (x->array[2] != y->array[2])
c6fb90c8 1541 return 0;
1a0670f3 1542 /* Fall through. */
c6fb90c8 1543 case 2:
0dfbf9d7 1544 if (x->array[1] != y->array[1])
c6fb90c8 1545 return 0;
1a0670f3 1546 /* Fall through. */
c6fb90c8 1547 case 1:
0dfbf9d7 1548 return x->array[0] == y->array[0];
c6fb90c8
L		 1549 break;
1550 default:
1551 abort ();
1552 }
1553}
40fb9820 1554
0dfbf9d7
L		 1555static INLINE int
1556cpu_flags_all_zero (const union i386_cpu_flags *x)
1557{
1558 switch (ARRAY_SIZE(x->array))
1559 {
53467f57
IT		 1560 case 4:
1561 if (x->array[3])
1562 return 0;
1563 /* Fall through. */
0dfbf9d7
L		 1564 case 3:
1565 if (x->array[2])
1566 return 0;
1a0670f3 1567 /* Fall through. */
0dfbf9d7
L		 1568 case 2:
1569 if (x->array[1])
1570 return 0;
1a0670f3 1571 /* Fall through. */
0dfbf9d7
L		 1572 case 1:
1573 return !x->array[0];
1574 default:
1575 abort ();
1576 }
1577}
1578
0dfbf9d7
L		 1579static INLINE int
1580cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1582{
1583 switch (ARRAY_SIZE(x->array))
1584 {
53467f57
IT		 1585 case 4:
1586 if (x->array[3] != y->array[3])
1587 return 0;
1588 /* Fall through. */
0dfbf9d7
L		 1589 case 3:
1590 if (x->array[2] != y->array[2])
1591 return 0;
1a0670f3 1592 /* Fall through. */
0dfbf9d7
L		 1593 case 2:
1594 if (x->array[1] != y->array[1])
1595 return 0;
1a0670f3 1596 /* Fall through. */
0dfbf9d7
L		 1597 case 1:
1598 return x->array[0] == y->array[0];
1599 break;
1600 default:
1601 abort ();
1602 }
1603}
c6fb90c8
L		 1604
1605static INLINE int
1606cpu_flags_check_cpu64 (i386_cpu_flags f)
1607{
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1610}
1611
c6fb90c8
L		 1612static INLINE i386_cpu_flags
1613cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1614{
c6fb90c8
L		 1615 switch (ARRAY_SIZE (x.array))
1616 {
53467f57
IT		 1617 case 4:
1618 x.array [3] &= y.array [3];
1619 /* Fall through. */
c6fb90c8
L		 1620 case 3:
1621 x.array [2] &= y.array [2];
1a0670f3 1622 /* Fall through. */
c6fb90c8
L		 1623 case 2:
1624 x.array [1] &= y.array [1];
1a0670f3 1625 /* Fall through. */
c6fb90c8
L		 1626 case 1:
1627 x.array [0] &= y.array [0];
1628 break;
1629 default:
1630 abort ();
1631 }
1632 return x;
1633}
40fb9820 1634
c6fb90c8
L		 1635static INLINE i386_cpu_flags
1636cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1637{
c6fb90c8 1638 switch (ARRAY_SIZE (x.array))
40fb9820 1639 {
53467f57
IT		 1640 case 4:
1641 x.array [3] |= y.array [3];
1642 /* Fall through. */
c6fb90c8
L		 1643 case 3:
1644 x.array [2] |= y.array [2];
1a0670f3 1645 /* Fall through. */
c6fb90c8
L		 1646 case 2:
1647 x.array [1] |= y.array [1];
1a0670f3 1648 /* Fall through. */
c6fb90c8
L		 1649 case 1:
1650 x.array [0] |= y.array [0];
40fb9820
L		 1651 break;
1652 default:
1653 abort ();
1654 }
40fb9820
L		 1655 return x;
1656}
1657
309d3373
JB		 1658static INLINE i386_cpu_flags
1659cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1660{
1661 switch (ARRAY_SIZE (x.array))
1662 {
53467f57
IT		 1663 case 4:
1664 x.array [3] &= ~y.array [3];
1665 /* Fall through. */
309d3373
JB		 1666 case 3:
1667 x.array [2] &= ~y.array [2];
1a0670f3 1668 /* Fall through. */
309d3373
JB		 1669 case 2:
1670 x.array [1] &= ~y.array [1];
1a0670f3 1671 /* Fall through. */
309d3373
JB		 1672 case 1:
1673 x.array [0] &= ~y.array [0];
1674 break;
1675 default:
1676 abort ();
1677 }
1678 return x;
1679}
1680
c0f3af97
L		 1681#define CPU_FLAGS_ARCH_MATCH 0x1
1682#define CPU_FLAGS_64BIT_MATCH 0x2
1683
c0f3af97 1684#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1686
1687/* Return CPU flags match bits. */
3629bb00 1688
40fb9820 1689static int
d3ce72d0 1690cpu_flags_match (const insn_template *t)
40fb9820 1691{
c0f3af97
L		 1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1694
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1697
0dfbf9d7 1698 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1699 {
1700 /* This instruction is available on all archs. */
db12e14e 1701 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1702 }
3629bb00
L		 1703 else
1704 {
c0f3af97 1705 /* This instruction is available only on some archs. */
3629bb00
L		 1706 i386_cpu_flags cpu = cpu_arch_flags;
1707
ab592e75
JB		 1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1710 return match;
1711 x.bitfield.cpuavx512vl = 0;
1712
3629bb00 1713 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1714 if (!cpu_flags_all_zero (&cpu))
1715 {
a5ff0eb2
L		 1716 if (x.bitfield.cpuavx)
1717 {
929f69fa 1718 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1725 }
929f69fa
JB		 1726 else if (x.bitfield.cpuavx512f)
1727 {
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1734 }
a5ff0eb2 1735 else
db12e14e 1736 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1737 }
3629bb00 1738 }
c0f3af97 1739 return match;
40fb9820
L		 1740}
1741
c6fb90c8
L		 1742static INLINE i386_operand_type
1743operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1744{
c6fb90c8
L		 1745 switch (ARRAY_SIZE (x.array))
1746 {
1747 case 3:
1748 x.array [2] &= y.array [2];
1a0670f3 1749 /* Fall through. */
c6fb90c8
L		 1750 case 2:
1751 x.array [1] &= y.array [1];
1a0670f3 1752 /* Fall through. */
c6fb90c8
L		 1753 case 1:
1754 x.array [0] &= y.array [0];
1755 break;
1756 default:
1757 abort ();
1758 }
1759 return x;
40fb9820
L		 1760}
1761
73053c1f
JB		 1762static INLINE i386_operand_type
1763operand_type_and_not (i386_operand_type x, i386_operand_type y)
1764{
1765 switch (ARRAY_SIZE (x.array))
1766 {
1767 case 3:
1768 x.array [2] &= ~y.array [2];
1769 /* Fall through. */
1770 case 2:
1771 x.array [1] &= ~y.array [1];
1772 /* Fall through. */
1773 case 1:
1774 x.array [0] &= ~y.array [0];
1775 break;
1776 default:
1777 abort ();
1778 }
1779 return x;
1780}
1781
c6fb90c8
L		 1782static INLINE i386_operand_type
1783operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1784{
c6fb90c8 1785 switch (ARRAY_SIZE (x.array))
40fb9820 1786 {
c6fb90c8
L		 1787 case 3:
1788 x.array [2] |= y.array [2];
1a0670f3 1789 /* Fall through. */
c6fb90c8
L		 1790 case 2:
1791 x.array [1] |= y.array [1];
1a0670f3 1792 /* Fall through. */
c6fb90c8
L		 1793 case 1:
1794 x.array [0] |= y.array [0];
40fb9820
L		 1795 break;
1796 default:
1797 abort ();
1798 }
c6fb90c8
L		 1799 return x;
1800}
40fb9820 1801
c6fb90c8
L		 1802static INLINE i386_operand_type
1803operand_type_xor (i386_operand_type x, i386_operand_type y)
1804{
1805 switch (ARRAY_SIZE (x.array))
1806 {
1807 case 3:
1808 x.array [2] ^= y.array [2];
1a0670f3 1809 /* Fall through. */
c6fb90c8
L		 1810 case 2:
1811 x.array [1] ^= y.array [1];
1a0670f3 1812 /* Fall through. */
c6fb90c8
L		 1813 case 1:
1814 x.array [0] ^= y.array [0];
1815 break;
1816 default:
1817 abort ();
1818 }
40fb9820
L		 1819 return x;
1820}
1821
1822static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1825static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1827static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
40fb9820 1835static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1836static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1837static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1846static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1847
1848enum operand_type
1849{
1850 reg,
40fb9820
L		 1851 imm,
1852 disp,
1853 anymem
1854};
1855
c6fb90c8 1856static INLINE int
40fb9820
L		 1857operand_type_check (i386_operand_type t, enum operand_type c)
1858{
1859 switch (c)
1860 {
1861 case reg:
dc821c5f 1862 return t.bitfield.reg;
40fb9820 1863
40fb9820
L		 1864 case imm:
1865 return (t.bitfield.imm8
1866 || t.bitfield.imm8s
1867 || t.bitfield.imm16
1868 || t.bitfield.imm32
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1871
1872 case disp:
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1878
1879 case anymem:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1886
1887 default:
1888 abort ();
1889 }
2cfe26b6
AM		 1890
1891 return 0;
40fb9820
L		 1892}
1893
ca0d63fe 1894/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1895 operand J for instruction template T. */
1896
1897static INLINE int
d3ce72d0 1898match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1899{
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1910}
1911
1b54b8d7
JB		 1912/* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1914
1915static INLINE int
1916match_simd_size (const insn_template *t, unsigned int j)
1917{
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1924}
1925
5c07affc
L		 1926/* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1928
1929static INLINE int
d3ce72d0 1930match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1931{
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
af508cb9 1934 && !i.broadcast
5c07affc
L		 1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
d6793fa1
JB		 1940 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1941 down-conversion vpmov*. */
1b54b8d7
JB		 1942 || ((t->operand_types[j].bitfield.regsimd
1943 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1944 && (t->operand_types[j].bitfield.byte
1945 || t->operand_types[j].bitfield.word
1946 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1947 || t->operand_types[j].bitfield.qword))
1948 ? (i.types[j].bitfield.xmmword
1949 || i.types[j].bitfield.ymmword
1950 || i.types[j].bitfield.zmmword)
1951 : !match_simd_size(t, j))));
5c07affc
L		 1952}
1953
1954/* Return 1 if there is no size conflict on any operands for
1955 instruction template T. */
1956
1957static INLINE int
d3ce72d0 1958operand_size_match (const insn_template *t)
5c07affc
L		 1959{
1960 unsigned int j;
1961 int match = 1;
1962
1963 /* Don't check jump instructions. */
1964 if (t->opcode_modifier.jump
1965 || t->opcode_modifier.jumpbyte
1966 || t->opcode_modifier.jumpdword
1967 || t->opcode_modifier.jumpintersegment)
1968 return match;
1969
1970 /* Check memory and accumulator operand size. */
1971 for (j = 0; j < i.operands; j++)
1972 {
1b54b8d7
JB		 1973 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1974 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1975 continue;
1976
1b54b8d7 1977 if (t->operand_types[j].bitfield.reg
dc821c5f 1978 && !match_reg_size (t, j))
5c07affc
L		 1979 {
1980 match = 0;
1981 break;
1982 }
1983
1b54b8d7
JB		 1984 if (t->operand_types[j].bitfield.regsimd
1985 && !match_simd_size (t, j))
1986 {
1987 match = 0;
1988 break;
1989 }
1990
1991 if (t->operand_types[j].bitfield.acc
1992 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1993 {
1994 match = 0;
1995 break;
1996 }
1997
5c07affc
L		 1998 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1999 {
2000 match = 0;
2001 break;
2002 }
2003 }
2004
891edac4 2005 if (match)
5c07affc 2006 return match;
38e314eb 2007 else if (!t->opcode_modifier.d)
891edac4
L		 2008 {
2009mismatch:
86e026a4 2010 i.error = operand_size_mismatch;
891edac4
L		 2011 return 0;
2012 }
5c07affc
L		 2013
2014 /* Check reverse. */
9c2799c2 2015 gas_assert (i.operands == 2);
5c07affc
L		 2016
2017 match = 1;
2018 for (j = 0; j < 2; j++)
2019 {
dc821c5f
JB		 2020 if ((t->operand_types[j].bitfield.reg
2021 || t->operand_types[j].bitfield.acc)
5c07affc 2022 && !match_reg_size (t, j ? 0 : 1))
891edac4 2023 goto mismatch;
5c07affc
L		 2024
2025 if (i.types[j].bitfield.mem
2026 && !match_mem_size (t, j ? 0 : 1))
891edac4 2027 goto mismatch;
5c07affc
L		 2028 }
2029
2030 return match;
2031}
2032
c6fb90c8 2033static INLINE int
40fb9820
L		 2034operand_type_match (i386_operand_type overlap,
2035 i386_operand_type given)
2036{
2037 i386_operand_type temp = overlap;
2038
2039 temp.bitfield.jumpabsolute = 0;
7d5e4556 2040 temp.bitfield.unspecified = 0;
5c07affc
L		 2041 temp.bitfield.byte = 0;
2042 temp.bitfield.word = 0;
2043 temp.bitfield.dword = 0;
2044 temp.bitfield.fword = 0;
2045 temp.bitfield.qword = 0;
2046 temp.bitfield.tbyte = 0;
2047 temp.bitfield.xmmword = 0;
c0f3af97 2048 temp.bitfield.ymmword = 0;
43234a1e 2049 temp.bitfield.zmmword = 0;
0dfbf9d7 2050 if (operand_type_all_zero (&temp))
891edac4 2051 goto mismatch;
40fb9820 2052
891edac4
L		 2053 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2054 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2055 return 1;
2056
2057mismatch:
a65babc9 2058 i.error = operand_type_mismatch;
891edac4 2059 return 0;
40fb9820
L		 2060}
2061
7d5e4556 2062/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2063 unless the expected operand type register overlap is null.
2064 Memory operand size of certain SIMD instructions is also being checked
2065 here. */
40fb9820 2066
c6fb90c8 2067static INLINE int
dc821c5f 2068operand_type_register_match (i386_operand_type g0,
40fb9820 2069 i386_operand_type t0,
40fb9820
L		 2070 i386_operand_type g1,
2071 i386_operand_type t1)
2072{
10c17abd
JB		 2073 if (!g0.bitfield.reg
2074 && !g0.bitfield.regsimd
2075 && (!operand_type_check (g0, anymem)
2076 || g0.bitfield.unspecified
2077 || !t0.bitfield.regsimd))
40fb9820
L		 2078 return 1;
2079
10c17abd
JB		 2080 if (!g1.bitfield.reg
2081 && !g1.bitfield.regsimd
2082 && (!operand_type_check (g1, anymem)
2083 || g1.bitfield.unspecified
2084 || !t1.bitfield.regsimd))
40fb9820
L		 2085 return 1;
2086
dc821c5f
JB		 2087 if (g0.bitfield.byte == g1.bitfield.byte
2088 && g0.bitfield.word == g1.bitfield.word
2089 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2090 && g0.bitfield.qword == g1.bitfield.qword
2091 && g0.bitfield.xmmword == g1.bitfield.xmmword
2092 && g0.bitfield.ymmword == g1.bitfield.ymmword
2093 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2094 return 1;
2095
dc821c5f
JB		 2096 if (!(t0.bitfield.byte & t1.bitfield.byte)
2097 && !(t0.bitfield.word & t1.bitfield.word)
2098 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2099 && !(t0.bitfield.qword & t1.bitfield.qword)
2100 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2101 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2102 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2103 return 1;
2104
a65babc9 2105 i.error = register_type_mismatch;
891edac4
L		 2106
2107 return 0;
40fb9820
L		 2108}
2109
4c692bc7
JB		 2110static INLINE unsigned int
2111register_number (const reg_entry *r)
2112{
2113 unsigned int nr = r->reg_num;
2114
2115 if (r->reg_flags & RegRex)
2116 nr += 8;
2117
200cbe0f
L		 2118 if (r->reg_flags & RegVRex)
2119 nr += 16;
2120
4c692bc7
JB		 2121 return nr;
2122}
2123
252b5132 2124static INLINE unsigned int
40fb9820 2125mode_from_disp_size (i386_operand_type t)
252b5132 2126{
b5014f7a 2127 if (t.bitfield.disp8)
40fb9820
L		 2128 return 1;
2129 else if (t.bitfield.disp16
2130 || t.bitfield.disp32
2131 || t.bitfield.disp32s)
2132 return 2;
2133 else
2134 return 0;
252b5132
RH		 2135}
2136
2137static INLINE int
65879393 2138fits_in_signed_byte (addressT num)
252b5132 2139{
65879393 2140 return num + 0x80 <= 0xff;
47926f60 2141}
252b5132
RH		 2142
2143static INLINE int
65879393 2144fits_in_unsigned_byte (addressT num)
252b5132 2145{
65879393 2146 return num <= 0xff;
47926f60 2147}
252b5132
RH		 2148
2149static INLINE int
65879393 2150fits_in_unsigned_word (addressT num)
252b5132 2151{
65879393 2152 return num <= 0xffff;
47926f60 2153}
252b5132
RH		 2154
2155static INLINE int
65879393 2156fits_in_signed_word (addressT num)
252b5132 2157{
65879393 2158 return num + 0x8000 <= 0xffff;
47926f60 2159}
2a962e6d 2160
3e73aa7c 2161static INLINE int
65879393 2162fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2163{
2164#ifndef BFD64
2165 return 1;
2166#else
65879393 2167 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2168#endif
2169} /* fits_in_signed_long() */
2a962e6d 2170
3e73aa7c 2171static INLINE int
65879393 2172fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2173{
2174#ifndef BFD64
2175 return 1;
2176#else
65879393 2177 return num <= 0xffffffff;
3e73aa7c
JH		 2178#endif
2179} /* fits_in_unsigned_long() */
252b5132 2180
43234a1e 2181static INLINE int
b5014f7a 2182fits_in_disp8 (offsetT num)
43234a1e
L		 2183{
2184 int shift = i.memshift;
2185 unsigned int mask;
2186
2187 if (shift == -1)
2188 abort ();
2189
2190 mask = (1 << shift) - 1;
2191
2192 /* Return 0 if NUM isn't properly aligned. */
2193 if ((num & mask))
2194 return 0;
2195
2196 /* Check if NUM will fit in 8bit after shift. */
2197 return fits_in_signed_byte (num >> shift);
2198}
2199
a683cc34
SP		 2200static INLINE int
2201fits_in_imm4 (offsetT num)
2202{
2203 return (num & 0xf) == num;
2204}
2205
40fb9820 2206static i386_operand_type
e3bb37b5 2207smallest_imm_type (offsetT num)
252b5132 2208{
40fb9820 2209 i386_operand_type t;
7ab9ffdd 2210
0dfbf9d7 2211 operand_type_set (&t, 0);
40fb9820
L		 2212 t.bitfield.imm64 = 1;
2213
2214 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2215 {
2216 /* This code is disabled on the 486 because all the Imm1 forms
2217 in the opcode table are slower on the i486. They're the
2218 versions with the implicitly specified single-position
2219 displacement, which has another syntax if you really want to
2220 use that form. */
40fb9820
L		 2221 t.bitfield.imm1 = 1;
2222 t.bitfield.imm8 = 1;
2223 t.bitfield.imm8s = 1;
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2227 }
2228 else if (fits_in_signed_byte (num))
2229 {
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2235 }
2236 else if (fits_in_unsigned_byte (num))
2237 {
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2242 }
2243 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2244 {
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2248 }
2249 else if (fits_in_signed_long (num))
2250 {
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2253 }
2254 else if (fits_in_unsigned_long (num))
2255 t.bitfield.imm32 = 1;
2256
2257 return t;
47926f60 2258}
252b5132 2259
847f7ad4 2260static offsetT
e3bb37b5 2261offset_in_range (offsetT val, int size)
847f7ad4 2262{
508866be 2263 addressT mask;
ba2adb93 2264
847f7ad4
AM		 2265 switch (size)
2266 {
508866be
L		 2267 case 1: mask = ((addressT) 1 << 8) - 1; break;
2268 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2269 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2270#ifdef BFD64
2271 case 8: mask = ((addressT) 2 << 63) - 1; break;
2272#endif
47926f60 2273 default: abort ();
847f7ad4
AM		 2274 }
2275
9de868bf
L		 2276#ifdef BFD64
2277 /* If BFD64, sign extend val for 32bit address mode. */
2278 if (flag_code != CODE_64BIT
2279 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2280 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2281 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2282#endif
ba2adb93 2283
47926f60 2284 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2285 {
2286 char buf1[40], buf2[40];
2287
2288 sprint_value (buf1, val);
2289 sprint_value (buf2, val & mask);
2290 as_warn (_("%s shortened to %s"), buf1, buf2);
2291 }
2292 return val & mask;
2293}
2294
c32fa91d
L		 2295enum PREFIX_GROUP
2296{
2297 PREFIX_EXIST = 0,
2298 PREFIX_LOCK,
2299 PREFIX_REP,
04ef582a 2300 PREFIX_DS,
c32fa91d
L		 2301 PREFIX_OTHER
2302};
2303
2304/* Returns
2305 a. PREFIX_EXIST if attempting to add a prefix where one from the
2306 same class already exists.
2307 b. PREFIX_LOCK if lock prefix is added.
2308 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2309 d. PREFIX_DS if ds prefix is added.
2310 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2311 */
2312
2313static enum PREFIX_GROUP
e3bb37b5 2314add_prefix (unsigned int prefix)
252b5132 2315{
c32fa91d 2316 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2317 unsigned int q;
252b5132 2318
29b0f896
AM		 2319 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2320 && flag_code == CODE_64BIT)
b1905489 2321 {
161a04f6
L		 2322 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2323 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2324 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2325 ret = PREFIX_EXIST;
b1905489
JB		 2326 q = REX_PREFIX;
2327 }
3e73aa7c 2328 else
b1905489
JB		 2329 {
2330 switch (prefix)
2331 {
2332 default:
2333 abort ();
2334
b1905489 2335 case DS_PREFIX_OPCODE:
04ef582a
L		 2336 ret = PREFIX_DS;
2337 /* Fall through. */
2338 case CS_PREFIX_OPCODE:
b1905489
JB		 2339 case ES_PREFIX_OPCODE:
2340 case FS_PREFIX_OPCODE:
2341 case GS_PREFIX_OPCODE:
2342 case SS_PREFIX_OPCODE:
2343 q = SEG_PREFIX;
2344 break;
2345
2346 case REPNE_PREFIX_OPCODE:
2347 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2348 q = REP_PREFIX;
2349 ret = PREFIX_REP;
2350 break;
2351
b1905489 2352 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2353 q = LOCK_PREFIX;
2354 ret = PREFIX_LOCK;
b1905489
JB		 2355 break;
2356
2357 case FWAIT_OPCODE:
2358 q = WAIT_PREFIX;
2359 break;
2360
2361 case ADDR_PREFIX_OPCODE:
2362 q = ADDR_PREFIX;
2363 break;
2364
2365 case DATA_PREFIX_OPCODE:
2366 q = DATA_PREFIX;
2367 break;
2368 }
2369 if (i.prefix[q] != 0)
c32fa91d 2370 ret = PREFIX_EXIST;
b1905489 2371 }
252b5132 2372
b1905489 2373 if (ret)
252b5132 2374 {
b1905489
JB		 2375 if (!i.prefix[q])
2376 ++i.prefixes;
2377 i.prefix[q] |= prefix;
252b5132 2378 }
b1905489
JB		 2379 else
2380 as_bad (_("same type of prefix used twice"));
252b5132 2381
252b5132
RH		 2382 return ret;
2383}
2384
2385static void
78f12dd3 2386update_code_flag (int value, int check)
eecb386c 2387{
78f12dd3
L		 2388 PRINTF_LIKE ((*as_error));
2389
1e9cc1c2 2390 flag_code = (enum flag_code) value;
40fb9820
L		 2391 if (flag_code == CODE_64BIT)
2392 {
2393 cpu_arch_flags.bitfield.cpu64 = 1;
2394 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2395 }
2396 else
2397 {
2398 cpu_arch_flags.bitfield.cpu64 = 0;
2399 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2400 }
2401 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2402 {
78f12dd3
L		 2403 if (check)
2404 as_error = as_fatal;
2405 else
2406 as_error = as_bad;
2407 (*as_error) (_("64bit mode not supported on `%s'."),
2408 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2409 }
40fb9820 2410 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2411 {
78f12dd3
L		 2412 if (check)
2413 as_error = as_fatal;
2414 else
2415 as_error = as_bad;
2416 (*as_error) (_("32bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2418 }
eecb386c
AM		 2419 stackop_size = '\0';
2420}
2421
78f12dd3
L		 2422static void
2423set_code_flag (int value)
2424{
2425 update_code_flag (value, 0);
2426}
2427
eecb386c 2428static void
e3bb37b5 2429set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2430{
1e9cc1c2 2431 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2432 if (flag_code != CODE_16BIT)
2433 abort ();
2434 cpu_arch_flags.bitfield.cpu64 = 0;
2435 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2436 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2437}
2438
2439static void
e3bb37b5 2440set_intel_syntax (int syntax_flag)
252b5132
RH		 2441{
2442 /* Find out if register prefixing is specified. */
2443 int ask_naked_reg = 0;
2444
2445 SKIP_WHITESPACE ();
29b0f896 2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2447 {
d02603dc
NC		 2448 char *string;
2449 int e = get_symbol_name (&string);
252b5132 2450
47926f60 2451 if (strcmp (string, "prefix") == 0)
252b5132 2452 ask_naked_reg = 1;
47926f60 2453 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2454 ask_naked_reg = -1;
2455 else
d0b47220 2456 as_bad (_("bad argument to syntax directive."));
d02603dc 2457 (void) restore_line_pointer (e);
252b5132
RH		 2458 }
2459 demand_empty_rest_of_line ();
c3332e24 2460
252b5132
RH		 2461 intel_syntax = syntax_flag;
2462
2463 if (ask_naked_reg == 0)
f86103b7
AM		 2464 allow_naked_reg = (intel_syntax
2465 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2466 else
2467 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2468
ee86248c 2469 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2470
e4a3b5a4 2471 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2472 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2473 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2474}
2475
1efbbeb4
L		 2476static void
2477set_intel_mnemonic (int mnemonic_flag)
2478{
e1d4d893 2479 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2480}
2481
db51cc60
L		 2482static void
2483set_allow_index_reg (int flag)
2484{
2485 allow_index_reg = flag;
2486}
2487
cb19c032 2488static void
7bab8ab5 2489set_check (int what)
cb19c032 2490{
7bab8ab5
JB		 2491 enum check_kind *kind;
2492 const char *str;
2493
2494 if (what)
2495 {
2496 kind = &operand_check;
2497 str = "operand";
2498 }
2499 else
2500 {
2501 kind = &sse_check;
2502 str = "sse";
2503 }
2504
cb19c032
L		 2505 SKIP_WHITESPACE ();
2506
2507 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2508 {
d02603dc
NC		 2509 char *string;
2510 int e = get_symbol_name (&string);
cb19c032
L		 2511
2512 if (strcmp (string, "none") == 0)
7bab8ab5 2513 *kind = check_none;
cb19c032 2514 else if (strcmp (string, "warning") == 0)
7bab8ab5 2515 *kind = check_warning;
cb19c032 2516 else if (strcmp (string, "error") == 0)
7bab8ab5 2517 *kind = check_error;
cb19c032 2518 else
7bab8ab5 2519 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2520 (void) restore_line_pointer (e);
cb19c032
L		 2521 }
2522 else
7bab8ab5 2523 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2524
2525 demand_empty_rest_of_line ();
2526}
2527
8a9036a4
L		 2528static void
2529check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2530 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2531{
2532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 static const char *arch;
2534
2535 /* Intel LIOM is only supported on ELF. */
2536 if (!IS_ELF)
2537 return;
2538
2539 if (!arch)
2540 {
2541 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2542 use default_arch. */
2543 arch = cpu_arch_name;
2544 if (!arch)
2545 arch = default_arch;
2546 }
2547
81486035
L		 2548 /* If we are targeting Intel MCU, we must enable it. */
2549 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2550 || new_flag.bitfield.cpuiamcu)
2551 return;
2552
3632d14b 2553 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2554 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2555 || new_flag.bitfield.cpul1om)
8a9036a4 2556 return;
76ba9986 2557
7a9068fe
L		 2558 /* If we are targeting Intel K1OM, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2560 || new_flag.bitfield.cpuk1om)
2561 return;
2562
8a9036a4
L		 2563 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2564#endif
2565}
2566
e413e4e9 2567static void
e3bb37b5 2568set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2569{
47926f60 2570 SKIP_WHITESPACE ();
e413e4e9 2571
29b0f896 2572 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2573 {
d02603dc
NC		 2574 char *string;
2575 int e = get_symbol_name (&string);
91d6fa6a 2576 unsigned int j;
40fb9820 2577 i386_cpu_flags flags;
e413e4e9 2578
91d6fa6a 2579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2580 {
91d6fa6a 2581 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2582 {
91d6fa6a 2583 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2584
5c6af06e
JB		 2585 if (*string != '.')
2586 {
91d6fa6a 2587 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2588 cpu_sub_arch_name = NULL;
91d6fa6a 2589 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2590 if (flag_code == CODE_64BIT)
2591 {
2592 cpu_arch_flags.bitfield.cpu64 = 1;
2593 cpu_arch_flags.bitfield.cpuno64 = 0;
2594 }
2595 else
2596 {
2597 cpu_arch_flags.bitfield.cpu64 = 0;
2598 cpu_arch_flags.bitfield.cpuno64 = 1;
2599 }
91d6fa6a
NC		 2600 cpu_arch_isa = cpu_arch[j].type;
2601 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2602 if (!cpu_arch_tune_set)
2603 {
2604 cpu_arch_tune = cpu_arch_isa;
2605 cpu_arch_tune_flags = cpu_arch_isa_flags;
2606 }
5c6af06e
JB		 2607 break;
2608 }
40fb9820 2609
293f5f65
L		 2610 flags = cpu_flags_or (cpu_arch_flags,
2611 cpu_arch[j].flags);
81486035 2612
5b64d091 2613 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2614 {
6305a203
L		 2615 if (cpu_sub_arch_name)
2616 {
2617 char *name = cpu_sub_arch_name;
2618 cpu_sub_arch_name = concat (name,
91d6fa6a 2619 cpu_arch[j].name,
1bf57e9f 2620 (const char *) NULL);
6305a203
L		 2621 free (name);
2622 }
2623 else
91d6fa6a 2624 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2625 cpu_arch_flags = flags;
a586129e 2626 cpu_arch_isa_flags = flags;
5c6af06e 2627 }
0089dace
L		 2628 else
2629 cpu_arch_isa_flags
2630 = cpu_flags_or (cpu_arch_isa_flags,
2631 cpu_arch[j].flags);
d02603dc 2632 (void) restore_line_pointer (e);
5c6af06e
JB		 2633 demand_empty_rest_of_line ();
2634 return;
e413e4e9
AM		 2635 }
2636 }
293f5f65
L		 2637
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2639 {
33eaf5de 2640 /* Disable an ISA extension. */
293f5f65
L		 2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2643 {
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2647 {
2648 if (cpu_sub_arch_name)
2649 {
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2653 free (name);
2654 }
2655 else
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2659 }
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2662 return;
2663 }
2664
2665 j = ARRAY_SIZE (cpu_arch);
2666 }
2667
91d6fa6a 2668 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2669 as_bad (_("no such architecture: `%s'"), string);
2670
2671 *input_line_pointer = e;
2672 }
2673 else
2674 as_bad (_("missing cpu architecture"));
2675
fddf5b5b
AM		 2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
29b0f896 2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2679 {
d02603dc
NC		 2680 char *string;
2681 char e;
2682
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
fddf5b5b
AM		 2685
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2689 ;
2690 else
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2692
d02603dc 2693 (void) restore_line_pointer (e);
fddf5b5b
AM		 2694 }
2695
e413e4e9
AM		 2696 demand_empty_rest_of_line ();
2697}
2698
8a9036a4
L		 2699enum bfd_architecture
2700i386_arch (void)
2701{
3632d14b 2702 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2703 {
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2708 }
7a9068fe
L		 2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2710 {
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2715 }
81486035
L		 2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2717 {
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2722 }
8a9036a4
L		 2723 else
2724 return bfd_arch_i386;
2725}
2726
b9d79e03 2727unsigned long
7016a5d5 2728i386_mach (void)
b9d79e03 2729{
351f65ca 2730 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2731 {
3632d14b 2732 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2733 {
351f65ca
L		 2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
8a9036a4
L		 2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2738 }
7a9068fe
L		 2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2740 {
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2745 }
351f65ca 2746 else if (default_arch[6] == '\0')
8a9036a4 2747 return bfd_mach_x86_64;
351f65ca
L		 2748 else
2749 return bfd_mach_x64_32;
8a9036a4 2750 }
5197d474
L		 2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
81486035
L		 2753 {
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2755 {
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2759 }
2760 else
2761 return bfd_mach_i386_i386;
2762 }
b9d79e03 2763 else
2b5d6a91 2764 as_fatal (_("unknown architecture"));
b9d79e03 2765}
b9d79e03 2766\f
252b5132 2767void
7016a5d5 2768md_begin (void)
252b5132
RH		 2769{
2770 const char *hash_err;
2771
86fa6981
L		 2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2774
47926f60 2775 /* Initialize op_hash hash table. */
252b5132
RH		 2776 op_hash = hash_new ();
2777
2778 {
d3ce72d0 2779 const insn_template *optab;
29b0f896 2780 templates *core_optab;
252b5132 2781
47926f60
KH		 2782 /* Setup for loop. */
2783 optab = i386_optab;
add39d23 2784 core_optab = XNEW (templates);
252b5132
RH		 2785 core_optab->start = optab;
2786
2787 while (1)
2788 {
2789 ++optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2792 {
2793 /* different name --> ship out current template list;
47926f60 2794 add to hash table; & begin anew. */
252b5132
RH		 2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2797 (optab - 1)->name,
5a49b8ac 2798 (void *) core_optab);
252b5132
RH		 2799 if (hash_err)
2800 {
b37df7c4 2801 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2802 (optab - 1)->name,
2803 hash_err);
2804 }
2805 if (optab->name == NULL)
2806 break;
add39d23 2807 core_optab = XNEW (templates);
252b5132
RH		 2808 core_optab->start = optab;
2809 }
2810 }
2811 }
2812
47926f60 2813 /* Initialize reg_hash hash table. */
252b5132
RH		 2814 reg_hash = hash_new ();
2815 {
29b0f896 2816 const reg_entry *regtab;
c3fe08fa 2817 unsigned int regtab_size = i386_regtab_size;
252b5132 2818
c3fe08fa 2819 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2820 {
5a49b8ac 2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2822 if (hash_err)
b37df7c4 2823 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2824 regtab->reg_name,
2825 hash_err);
252b5132
RH		 2826 }
2827 }
2828
47926f60 2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2830 {
29b0f896
AM		 2831 int c;
2832 char *p;
252b5132
RH		 2833
2834 for (c = 0; c < 256; c++)
2835 {
3882b010 2836 if (ISDIGIT (c))
252b5132
RH		 2837 {
2838 digit_chars[c] = c;
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2842 }
3882b010 2843 else if (ISLOWER (c))
252b5132
RH		 2844 {
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2848 }
3882b010 2849 else if (ISUPPER (c))
252b5132 2850 {
3882b010 2851 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2854 }
43234a1e 2855 else if (c == '{' || c == '}')
86fa6981
L		 2856 {
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
252b5132 2860
3882b010 2861 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2862 identifier_chars[c] = c;
2863 else if (c >= 128)
2864 {
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2867 }
2868 }
2869
2870#ifdef LEX_AT
2871 identifier_chars['@'] = '@';
32137342
NC		 2872#endif
2873#ifdef LEX_QM
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
252b5132 2876#endif
252b5132 2877 digit_chars['-'] = '-';
c0f3af97 2878 mnemonic_chars['_'] = '_';
791fe849 2879 mnemonic_chars['-'] = '-';
0003779b 2880 mnemonic_chars['.'] = '.';
252b5132
RH		 2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2883
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2886 }
2887
a4447b93
RH		 2888 if (flag_code == CODE_64BIT)
2889 {
ca19b261
KT		 2890#if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2892 ? 32 : 16);
2893#else
a4447b93 2894 x86_dwarf2_return_column = 16;
ca19b261 2895#endif
61ff971f 2896 x86_cie_data_alignment = -8;
a4447b93
RH		 2897 }
2898 else
2899 {
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2902 }
252b5132
RH		 2903}
2904
2905void
e3bb37b5 2906i386_print_statistics (FILE *file)
252b5132
RH		 2907{
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2910}
2911\f
252b5132
RH		 2912#ifdef DEBUG386
2913
ce8a8b2f 2914/* Debugging routines for md_assemble. */
d3ce72d0 2915static void pte (insn_template *);
40fb9820 2916static void pt (i386_operand_type);
e3bb37b5
L		 2917static void pe (expressionS *);
2918static void ps (symbolS *);
252b5132
RH		 2919
2920static void
e3bb37b5 2921pi (char *line, i386_insn *x)
252b5132 2922{
09137c09 2923 unsigned int j;
252b5132
RH		 2924
2925 fprintf (stdout, "%s: template ", line);
2926 pte (&x->tm);
09f131f2
JH		 2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2932 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
09137c09 2940 for (j = 0; j < x->operands; j++)
252b5132 2941 {
09137c09
SP		 2942 fprintf (stdout, " #%d: ", j + 1);
2943 pt (x->types[j]);
252b5132 2944 fprintf (stdout, "\n");
dc821c5f 2945 if (x->types[j].bitfield.reg
09137c09 2946 || x->types[j].bitfield.regmmx
1b54b8d7 2947 || x->types[j].bitfield.regsimd
09137c09
SP		 2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2955 pe (x->op[j].imms);
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
252b5132
RH		 2958 }
2959}
2960
2961static void
d3ce72d0 2962pte (insn_template *t)
252b5132 2963{
09137c09 2964 unsigned int j;
252b5132 2965 fprintf (stdout, " %d operands ", t->operands);
47926f60 2966 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2969 if (t->opcode_modifier.d)
252b5132 2970 fprintf (stdout, "D");
40fb9820 2971 if (t->opcode_modifier.w)
252b5132
RH		 2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
09137c09 2974 for (j = 0; j < t->operands; j++)
252b5132 2975 {
09137c09
SP		 2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
252b5132
RH		 2978 fprintf (stdout, "\n");
2979 }
2980}
2981
2982static void
e3bb37b5 2983pe (expressionS *e)
252b5132 2984{
24eab124 2985 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2988 if (e->X_add_symbol)
2989 {
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2993 }
2994 if (e->X_op_symbol)
2995 {
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
2999 }
3000}
3001
3002static void
e3bb37b5 3003ps (symbolS *s)
252b5132
RH		 3004{
3005 fprintf (stdout, "%s type %s%s",
3006 S_GET_NAME (s),
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3009}
3010
7b81dfbb 3011static struct type_name
252b5132 3012 {
40fb9820
L		 3013 i386_operand_type mask;
3014 const char *name;
252b5132 3015 }
7b81dfbb 3016const type_names[] =
252b5132 3017{
40fb9820
L		 3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3048 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3051 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3052};
3053
3054static void
40fb9820 3055pt (i386_operand_type t)
252b5132 3056{
40fb9820 3057 unsigned int j;
c6fb90c8 3058 i386_operand_type a;
252b5132 3059
40fb9820 3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3061 {
3062 a = operand_type_and (t, type_names[j].mask);
0349dc08 3063 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3064 fprintf (stdout, "%s, ", type_names[j].name);
3065 }
252b5132
RH		 3066 fflush (stdout);
3067}
3068
3069#endif /* DEBUG386 */
3070\f
252b5132 3071static bfd_reloc_code_real_type
3956db08 3072reloc (unsigned int size,
64e74474
AM		 3073 int pcrel,
3074 int sign,
3075 bfd_reloc_code_real_type other)
252b5132 3076{
47926f60 3077 if (other != NO_RELOC)
3956db08 3078 {
91d6fa6a 3079 reloc_howto_type *rel;
3956db08
JB		 3080
3081 if (size == 8)
3082 switch (other)
3083 {
64e74474
AM		 3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3086 break;
553d1284
L		 3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3089 break;
64e74474
AM		 3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3098 break;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3104 break;
3105 default:
3106 break;
3956db08 3107 }
e05278af 3108
8ce3d284 3109#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3110 if (other == BFD_RELOC_SIZE32)
3111 {
3112 if (size == 8)
1ab668bf 3113 other = BFD_RELOC_SIZE64;
8fd4256d 3114 if (pcrel)
1ab668bf
AM		 3115 {
3116 as_bad (_("there are no pc-relative size relocations"));
3117 return NO_RELOC;
3118 }
8fd4256d 3119 }
8ce3d284 3120#endif
8fd4256d 3121
e05278af 3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3124 sign = -1;
3125
91d6fa6a
NC		 3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3127 if (!rel)
3956db08 3128 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3129 else if (size != bfd_get_reloc_size (rel))
3956db08 3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3131 bfd_get_reloc_size (rel),
3956db08 3132 size);
91d6fa6a 3133 else if (pcrel && !rel->pc_relative)
3956db08 3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3136 && !sign)
91d6fa6a 3137 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3138 && sign > 0))
3956db08
JB		 3139 as_bad (_("relocated field and relocation type differ in signedness"));
3140 else
3141 return other;
3142 return NO_RELOC;
3143 }
252b5132
RH		 3144
3145 if (pcrel)
3146 {
3e73aa7c 3147 if (!sign)
3956db08 3148 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3149 switch (size)
3150 {
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
d258b828 3153 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3154 case 8: return BFD_RELOC_64_PCREL;
252b5132 3155 }
3956db08 3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3157 }
3158 else
3159 {
3956db08 3160 if (sign > 0)
e5cb08ac 3161 switch (size)
3e73aa7c
JH		 3162 {
3163 case 4: return BFD_RELOC_X86_64_32S;
3164 }
3165 else
3166 switch (size)
3167 {
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3172 }
3956db08
JB		 3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3175 }
3176
0cc9e1d3 3177 return NO_RELOC;
252b5132
RH		 3178}
3179
47926f60
KH		 3180/* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3184
252b5132 3185int
e3bb37b5 3186tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3187{
6d249963 3188#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3189 if (!IS_ELF)
31312f95
AM		 3190 return 1;
3191
a161fe53
AM		 3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3193 mode. */
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3196 && fixP->fx_pcrel)
252b5132 3197 return 0;
31312f95 3198
8d01d9a9
AJ		 3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3203 return 0;
3204
8fd4256d
L		 3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3240 return 0;
31312f95 3241#endif
252b5132
RH		 3242 return 1;
3243}
252b5132 3244
b4cac588 3245static int
e3bb37b5 3246intel_float_operand (const char *mnemonic)
252b5132 3247{
9306ca4a
JB		 3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3251
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3254
3255 switch (mnemonic[1])
3256 {
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3260 case 'i':
3261 return 2 /* integer op */;
3262 case 'l':
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3265 break;
3266 case 'n':
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3269 break;
3270 case 'r':
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3273 break;
3274 case 's':
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3278 {
3279 switch (mnemonic[3])
3280 {
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3285 return 3;
3286 }
3287 }
3288 break;
3289 case 'x':
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3292 break;
3293 }
252b5132 3294
9306ca4a 3295 return 1;
252b5132
RH		 3296}
3297
c0f3af97
L		 3298/* Build the VEX prefix. */
3299
3300static void
d3ce72d0 3301build_vex_prefix (const insn_template *t)
c0f3af97
L		 3302{
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3306
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
43234a1e
L		 3309 {
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3313 }
c0f3af97
L		 3314 else
3315 register_specifier = 0xf;
3316
33eaf5de 3317 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3318 operand. */
86fa6981
L		 3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
fa99fab2 3321 && i.operands == i.reg_operands
7f399153 3322 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3323 && i.tm.opcode_modifier.load
fa99fab2
L		 3324 && i.rex == REX_B)
3325 {
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3329
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3335 i.op[0] = temp_op;
3336
9c2799c2 3337 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3338
3339 i.rex = REX_R;
3340 xchg = i.rm.regmem;
3341 i.rm.regmem = i.rm.reg;
3342 i.rm.reg = xchg;
3343
3344 /* Use the next insn. */
3345 i.tm = t[1];
3346 }
3347
539f890d
L		 3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
10c17abd
JB		 3350 else if (i.tm.opcode_modifier.vex == VEX256)
3351 vector_length = 1;
539f890d 3352 else
10c17abd
JB		 3353 {
3354 unsigned int op;
3355
3356 vector_length = 0;
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3361 {
3362 vector_length = 1;
3363 break;
3364 }
3365 }
c0f3af97
L		 3366
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3368 {
3369 case 0:
3370 implied_prefix = 0;
3371 break;
3372 case DATA_PREFIX_OPCODE:
3373 implied_prefix = 1;
3374 break;
3375 case REPE_PREFIX_OPCODE:
3376 implied_prefix = 2;
3377 break;
3378 case REPNE_PREFIX_OPCODE:
3379 implied_prefix = 3;
3380 break;
3381 default:
3382 abort ();
3383 }
3384
3385 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3388 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3390 {
3391 /* 2-byte VEX prefix. */
3392 unsigned int r;
3393
3394 i.vex.length = 2;
3395 i.vex.bytes[0] = 0xc5;
3396
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3402 | implied_prefix);
3403 }
3404 else
3405 {
3406 /* 3-byte VEX prefix. */
3407 unsigned int m, w;
3408
f88c9eb0 3409 i.vex.length = 3;
f88c9eb0 3410
7f399153 3411 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3412 {
7f399153
L		 3413 case VEX0F:
3414 m = 0x1;
80de6e00 3415 i.vex.bytes[0] = 0xc4;
7f399153
L		 3416 break;
3417 case VEX0F38:
3418 m = 0x2;
80de6e00 3419 i.vex.bytes[0] = 0xc4;
7f399153
L		 3420 break;
3421 case VEX0F3A:
3422 m = 0x3;
80de6e00 3423 i.vex.bytes[0] = 0xc4;
7f399153
L		 3424 break;
3425 case XOP08:
5dd85c99
SP		 3426 m = 0x8;
3427 i.vex.bytes[0] = 0x8f;
7f399153
L		 3428 break;
3429 case XOP09:
f88c9eb0
SP		 3430 m = 0x9;
3431 i.vex.bytes[0] = 0x8f;
7f399153
L		 3432 break;
3433 case XOP0A:
f88c9eb0
SP		 3434 m = 0xa;
3435 i.vex.bytes[0] = 0x8f;
7f399153
L		 3436 break;
3437 default:
3438 abort ();
f88c9eb0 3439 }
c0f3af97 3440
c0f3af97
L		 3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3444
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3448 w = 1;
c0f3af97
L		 3449
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3453 | implied_prefix);
3454 }
3455}
3456
e771e7c9
JB		 3457static INLINE bfd_boolean
3458is_evex_encoding (const insn_template *t)
3459{
3460 return t->opcode_modifier.evex
3461 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3462 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3463}
3464
43234a1e
L		 3465/* Build the EVEX prefix. */
3466
3467static void
3468build_evex_prefix (void)
3469{
3470 unsigned int register_specifier;
3471 unsigned int implied_prefix;
3472 unsigned int m, w;
3473 rex_byte vrex_used = 0;
3474
3475 /* Check register specifier. */
3476 if (i.vex.register_specifier)
3477 {
3478 gas_assert ((i.vrex & REX_X) == 0);
3479
3480 register_specifier = i.vex.register_specifier->reg_num;
3481 if ((i.vex.register_specifier->reg_flags & RegRex))
3482 register_specifier += 8;
3483 /* The upper 16 registers are encoded in the fourth byte of the
3484 EVEX prefix. */
3485 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3486 i.vex.bytes[3] = 0x8;
3487 register_specifier = ~register_specifier & 0xf;
3488 }
3489 else
3490 {
3491 register_specifier = 0xf;
3492
3493 /* Encode upper 16 vector index register in the fourth byte of
3494 the EVEX prefix. */
3495 if (!(i.vrex & REX_X))
3496 i.vex.bytes[3] = 0x8;
3497 else
3498 vrex_used |= REX_X;
3499 }
3500
3501 switch ((i.tm.base_opcode >> 8) & 0xff)
3502 {
3503 case 0:
3504 implied_prefix = 0;
3505 break;
3506 case DATA_PREFIX_OPCODE:
3507 implied_prefix = 1;
3508 break;
3509 case REPE_PREFIX_OPCODE:
3510 implied_prefix = 2;
3511 break;
3512 case REPNE_PREFIX_OPCODE:
3513 implied_prefix = 3;
3514 break;
3515 default:
3516 abort ();
3517 }
3518
3519 /* 4 byte EVEX prefix. */
3520 i.vex.length = 4;
3521 i.vex.bytes[0] = 0x62;
3522
3523 /* mmmm bits. */
3524 switch (i.tm.opcode_modifier.vexopcode)
3525 {
3526 case VEX0F:
3527 m = 1;
3528 break;
3529 case VEX0F38:
3530 m = 2;
3531 break;
3532 case VEX0F3A:
3533 m = 3;
3534 break;
3535 default:
3536 abort ();
3537 break;
3538 }
3539
3540 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3541 bits from REX. */
3542 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3543
3544 /* The fifth bit of the second EVEX byte is 1's compliment of the
3545 REX_R bit in VREX. */
3546 if (!(i.vrex & REX_R))
3547 i.vex.bytes[1] |= 0x10;
3548 else
3549 vrex_used |= REX_R;
3550
3551 if ((i.reg_operands + i.imm_operands) == i.operands)
3552 {
3553 /* When all operands are registers, the REX_X bit in REX is not
3554 used. We reuse it to encode the upper 16 registers, which is
3555 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3556 as 1's compliment. */
3557 if ((i.vrex & REX_B))
3558 {
3559 vrex_used |= REX_B;
3560 i.vex.bytes[1] &= ~0x40;
3561 }
3562 }
3563
3564 /* EVEX instructions shouldn't need the REX prefix. */
3565 i.vrex &= ~vrex_used;
3566 gas_assert (i.vrex == 0);
3567
3568 /* Check the REX.W bit. */
3569 w = (i.rex & REX_W) ? 1 : 0;
3570 if (i.tm.opcode_modifier.vexw)
3571 {
3572 if (i.tm.opcode_modifier.vexw == VEXW1)
3573 w = 1;
3574 }
3575 /* If w is not set it means we are dealing with WIG instruction. */
3576 else if (!w)
3577 {
3578 if (evexwig == evexw1)
3579 w = 1;
3580 }
3581
3582 /* Encode the U bit. */
3583 implied_prefix |= 0x4;
3584
3585 /* The third byte of the EVEX prefix. */
3586 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3587
3588 /* The fourth byte of the EVEX prefix. */
3589 /* The zeroing-masking bit. */
3590 if (i.mask && i.mask->zeroing)
3591 i.vex.bytes[3] |= 0x80;
3592
3593 /* Don't always set the broadcast bit if there is no RC. */
3594 if (!i.rounding)
3595 {
3596 /* Encode the vector length. */
3597 unsigned int vec_length;
3598
e771e7c9
JB		 3599 if (!i.tm.opcode_modifier.evex
3600 || i.tm.opcode_modifier.evex == EVEXDYN)
3601 {
3602 unsigned int op;
3603
3604 vec_length = 0;
3605 for (op = 0; op < i.tm.operands; ++op)
3606 if (i.tm.operand_types[op].bitfield.xmmword
3607 + i.tm.operand_types[op].bitfield.ymmword
3608 + i.tm.operand_types[op].bitfield.zmmword > 1)
3609 {
3610 if (i.types[op].bitfield.zmmword)
3611 i.tm.opcode_modifier.evex = EVEX512;
3612 else if (i.types[op].bitfield.ymmword)
3613 i.tm.opcode_modifier.evex = EVEX256;
3614 else if (i.types[op].bitfield.xmmword)
3615 i.tm.opcode_modifier.evex = EVEX128;
3616 else
3617 continue;
3618 break;
3619 }
3620 }
3621
43234a1e
L		 3622 switch (i.tm.opcode_modifier.evex)
3623 {
3624 case EVEXLIG: /* LL' is ignored */
3625 vec_length = evexlig << 5;
3626 break;
3627 case EVEX128:
3628 vec_length = 0 << 5;
3629 break;
3630 case EVEX256:
3631 vec_length = 1 << 5;
3632 break;
3633 case EVEX512:
3634 vec_length = 2 << 5;
3635 break;
3636 default:
3637 abort ();
3638 break;
3639 }
3640 i.vex.bytes[3] |= vec_length;
3641 /* Encode the broadcast bit. */
3642 if (i.broadcast)
3643 i.vex.bytes[3] |= 0x10;
3644 }
3645 else
3646 {
3647 if (i.rounding->type != saeonly)
3648 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3649 else
d3d3c6db 3650 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3651 }
3652
3653 if (i.mask && i.mask->mask)
3654 i.vex.bytes[3] |= i.mask->mask->reg_num;
3655}
3656
65da13b5
L		 3657static void
3658process_immext (void)
3659{
3660 expressionS *exp;
3661
4c692bc7
JB		 3662 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3663 && i.operands > 0)
65da13b5 3664 {
4c692bc7
JB		 3665 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3666 with an opcode suffix which is coded in the same place as an
3667 8-bit immediate field would be.
3668 Here we check those operands and remove them afterwards. */
65da13b5
L		 3669 unsigned int x;
3670
3671 for (x = 0; x < i.operands; x++)
4c692bc7 3672 if (register_number (i.op[x].regs) != x)
65da13b5 3673 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3674 register_prefix, i.op[x].regs->reg_name, x + 1,
3675 i.tm.name);
3676
3677 i.operands = 0;
65da13b5
L		 3678 }
3679
9916071f
AP		 3680 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3681 {
3682 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3683 suffix which is coded in the same place as an 8-bit immediate
3684 field would be.
3685 Here we check those operands and remove them afterwards. */
3686 unsigned int x;
3687
3688 if (i.operands != 3)
3689 abort();
3690
3691 for (x = 0; x < 2; x++)
3692 if (register_number (i.op[x].regs) != x)
3693 goto bad_register_operand;
3694
3695 /* Check for third operand for mwaitx/monitorx insn. */
3696 if (register_number (i.op[x].regs)
3697 != (x + (i.tm.extension_opcode == 0xfb)))
3698 {
3699bad_register_operand:
3700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3701 register_prefix, i.op[x].regs->reg_name, x+1,
3702 i.tm.name);
3703 }
3704
3705 i.operands = 0;
3706 }
3707
c0f3af97 3708 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3709 which is coded in the same place as an 8-bit immediate field
3710 would be. Here we fake an 8-bit immediate operand from the
3711 opcode suffix stored in tm.extension_opcode.
3712
c1e679ec 3713 AVX instructions also use this encoding, for some of
c0f3af97 3714 3 argument instructions. */
65da13b5 3715
43234a1e 3716 gas_assert (i.imm_operands <= 1
7ab9ffdd 3717 && (i.operands <= 2
43234a1e 3718 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3719 || i.tm.opcode_modifier.vexopcode
3720 || is_evex_encoding (&i.tm))
7ab9ffdd 3721 && i.operands <= 4)));
65da13b5
L		 3722
3723 exp = &im_expressions[i.imm_operands++];
3724 i.op[i.operands].imms = exp;
3725 i.types[i.operands] = imm8;
3726 i.operands++;
3727 exp->X_op = O_constant;
3728 exp->X_add_number = i.tm.extension_opcode;
3729 i.tm.extension_opcode = None;
3730}
3731
42164a71
L		 3732
3733static int
3734check_hle (void)
3735{
3736 switch (i.tm.opcode_modifier.hleprefixok)
3737 {
3738 default:
3739 abort ();
82c2def5 3740 case HLEPrefixNone:
165de32a
L		 3741 as_bad (_("invalid instruction `%s' after `%s'"),
3742 i.tm.name, i.hle_prefix);
42164a71 3743 return 0;
82c2def5 3744 case HLEPrefixLock:
42164a71
L		 3745 if (i.prefix[LOCK_PREFIX])
3746 return 1;
165de32a 3747 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3748 return 0;
82c2def5 3749 case HLEPrefixAny:
42164a71 3750 return 1;
82c2def5 3751 case HLEPrefixRelease:
42164a71
L		 3752 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3753 {
3754 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3755 i.tm.name);
3756 return 0;
3757 }
3758 if (i.mem_operands == 0
3759 || !operand_type_check (i.types[i.operands - 1], anymem))
3760 {
3761 as_bad (_("memory destination needed for instruction `%s'"
3762 " after `xrelease'"), i.tm.name);
3763 return 0;
3764 }
3765 return 1;
3766 }
3767}
3768
b6f8c7c4
L		 3769/* Try the shortest encoding by shortening operand size. */
3770
3771static void
3772optimize_encoding (void)
3773{
3774 int j;
3775
3776 if (optimize_for_space
3777 && i.reg_operands == 1
3778 && i.imm_operands == 1
3779 && !i.types[1].bitfield.byte
3780 && i.op[0].imms->X_op == O_constant
3781 && fits_in_imm7 (i.op[0].imms->X_add_number)
3782 && ((i.tm.base_opcode == 0xa8
3783 && i.tm.extension_opcode == None)
3784 || (i.tm.base_opcode == 0xf6
3785 && i.tm.extension_opcode == 0x0)))
3786 {
3787 /* Optimize: -Os:
3788 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3789 */
3790 unsigned int base_regnum = i.op[1].regs->reg_num;
3791 if (flag_code == CODE_64BIT || base_regnum < 4)
3792 {
3793 i.types[1].bitfield.byte = 1;
3794 /* Ignore the suffix. */
3795 i.suffix = 0;
3796 if (base_regnum >= 4
3797 && !(i.op[1].regs->reg_flags & RegRex))
3798 {
3799 /* Handle SP, BP, SI and DI registers. */
3800 if (i.types[1].bitfield.word)
3801 j = 16;
3802 else if (i.types[1].bitfield.dword)
3803 j = 32;
3804 else
3805 j = 48;
3806 i.op[1].regs -= j;
3807 }
3808 }
3809 }
3810 else if (flag_code == CODE_64BIT
d3d50934
L		 3811 && ((i.types[1].bitfield.qword
3812 && i.reg_operands == 1
b6f8c7c4
L		 3813 && i.imm_operands == 1
3814 && i.op[0].imms->X_op == O_constant
3815 && ((i.tm.base_opcode == 0xb0
3816 && i.tm.extension_opcode == None
3817 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3818 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3819 && (((i.tm.base_opcode == 0x24
3820 || i.tm.base_opcode == 0xa8)
3821 && i.tm.extension_opcode == None)
3822 || (i.tm.base_opcode == 0x80
3823 && i.tm.extension_opcode == 0x4)
3824 || ((i.tm.base_opcode == 0xf6
3825 || i.tm.base_opcode == 0xc6)
3826 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3827 || (i.types[0].bitfield.qword
3828 && ((i.reg_operands == 2
3829 && i.op[0].regs == i.op[1].regs
3830 && ((i.tm.base_opcode == 0x30
3831 || i.tm.base_opcode == 0x28)
3832 && i.tm.extension_opcode == None))
3833 || (i.reg_operands == 1
3834 && i.operands == 1
3835 && i.tm.base_opcode == 0x30
3836 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3837 {
3838 /* Optimize: -O:
3839 andq $imm31, %r64 -> andl $imm31, %r32
3840 testq $imm31, %r64 -> testl $imm31, %r32
3841 xorq %r64, %r64 -> xorl %r32, %r32
3842 subq %r64, %r64 -> subl %r32, %r32
3843 movq $imm31, %r64 -> movl $imm31, %r32
3844 movq $imm32, %r64 -> movl $imm32, %r32
3845 */
3846 i.tm.opcode_modifier.norex64 = 1;
3847 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3848 {
3849 /* Handle
3850 movq $imm31, %r64 -> movl $imm31, %r32
3851 movq $imm32, %r64 -> movl $imm32, %r32
3852 */
3853 i.tm.operand_types[0].bitfield.imm32 = 1;
3854 i.tm.operand_types[0].bitfield.imm32s = 0;
3855 i.tm.operand_types[0].bitfield.imm64 = 0;
3856 i.types[0].bitfield.imm32 = 1;
3857 i.types[0].bitfield.imm32s = 0;
3858 i.types[0].bitfield.imm64 = 0;
3859 i.types[1].bitfield.dword = 1;
3860 i.types[1].bitfield.qword = 0;
3861 if (i.tm.base_opcode == 0xc6)
3862 {
3863 /* Handle
3864 movq $imm31, %r64 -> movl $imm31, %r32
3865 */
3866 i.tm.base_opcode = 0xb0;
3867 i.tm.extension_opcode = None;
3868 i.tm.opcode_modifier.shortform = 1;
3869 i.tm.opcode_modifier.modrm = 0;
3870 }
3871 }
3872 }
3873 else if (optimize > 1
3874 && i.reg_operands == 3
3875 && i.op[0].regs == i.op[1].regs
3876 && !i.types[2].bitfield.xmmword
3877 && (i.tm.opcode_modifier.vex
3878 || (!i.mask
3879 && !i.rounding
e771e7c9 3880 && is_evex_encoding (&i.tm)
80c34c38
L		 3881 && (i.vec_encoding != vex_encoding_evex
3882 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3883 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3884 && ((i.tm.base_opcode == 0x55
3885 || i.tm.base_opcode == 0x6655
3886 || i.tm.base_opcode == 0x66df
3887 || i.tm.base_opcode == 0x57
3888 || i.tm.base_opcode == 0x6657
8305403a
L		 3889 || i.tm.base_opcode == 0x66ef
3890 || i.tm.base_opcode == 0x66f8
3891 || i.tm.base_opcode == 0x66f9
3892 || i.tm.base_opcode == 0x66fa
3893 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3894 && i.tm.extension_opcode == None))
3895 {
3896 /* Optimize: -O2:
8305403a
L		 3897 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3898 vpsubq and vpsubw:
b6f8c7c4
L		 3899 EVEX VOP %zmmM, %zmmM, %zmmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 EVEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandn and vpxor:
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandnd and vpandnq:
3911 EVEX VOP %zmmM, %zmmM, %zmmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 EVEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 VOP, one of vpxord and vpxorq:
3918 EVEX VOP %zmmM, %zmmM, %zmmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 EVEX VOP %ymmM, %ymmM, %ymmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 */
e771e7c9 3925 if (is_evex_encoding (&i.tm))
b6f8c7c4 3926 {
0089dace 3927 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3928 i.tm.opcode_modifier.evex = EVEX128;
3929 else
3930 {
3931 i.tm.opcode_modifier.vex = VEX128;
3932 i.tm.opcode_modifier.vexw = VEXW0;
3933 i.tm.opcode_modifier.evex = 0;
3934 }
3935 }
3936 else
3937 i.tm.opcode_modifier.vex = VEX128;
3938
3939 if (i.tm.opcode_modifier.vex)
3940 for (j = 0; j < 3; j++)
3941 {
3942 i.types[j].bitfield.xmmword = 1;
3943 i.types[j].bitfield.ymmword = 0;
3944 }
3945 }
3946}
3947
252b5132
RH		 3948/* This is the guts of the machine-dependent assembler. LINE points to a
3949 machine dependent instruction. This function is supposed to emit
3950 the frags/bytes it assembles to. */
3951
3952void
65da13b5 3953md_assemble (char *line)
252b5132 3954{
40fb9820 3955 unsigned int j;
83b16ac6 3956 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3957 const insn_template *t;
252b5132 3958
47926f60 3959 /* Initialize globals. */
252b5132
RH		 3960 memset (&i, '\0', sizeof (i));
3961 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3962 i.reloc[j] = NO_RELOC;
252b5132
RH		 3963 memset (disp_expressions, '\0', sizeof (disp_expressions));
3964 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3965 save_stack_p = save_stack;
252b5132
RH		 3966
3967 /* First parse an instruction mnemonic & call i386_operand for the operands.
3968 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3969 start of a (possibly prefixed) mnemonic. */
252b5132 3970
29b0f896
AM		 3971 line = parse_insn (line, mnemonic);
3972 if (line == NULL)
3973 return;
83b16ac6 3974 mnem_suffix = i.suffix;
252b5132 3975
29b0f896 3976 line = parse_operands (line, mnemonic);
ee86248c 3977 this_operand = -1;
8325cc63
JB		 3978 xfree (i.memop1_string);
3979 i.memop1_string = NULL;
29b0f896
AM		 3980 if (line == NULL)
3981 return;
252b5132 3982
29b0f896
AM		 3983 /* Now we've parsed the mnemonic into a set of templates, and have the
3984 operands at hand. */
3985
3986 /* All intel opcodes have reversed operands except for "bound" and
3987 "enter". We also don't reverse intersegment "jmp" and "call"
3988 instructions with 2 immediate operands so that the immediate segment
050dfa73 3989 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3990 if (intel_syntax
3991 && i.operands > 1
29b0f896 3992 && (strcmp (mnemonic, "bound") != 0)
30123838 3993 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3994 && !(operand_type_check (i.types[0], imm)
3995 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3996 swap_operands ();
3997
ec56d5c0
JB		 3998 /* The order of the immediates should be reversed
3999 for 2 immediates extrq and insertq instructions */
4000 if (i.imm_operands == 2
4001 && (strcmp (mnemonic, "extrq") == 0
4002 || strcmp (mnemonic, "insertq") == 0))
4003 swap_2_operands (0, 1);
4004
29b0f896
AM		 4005 if (i.imm_operands)
4006 optimize_imm ();
4007
b300c311
L		 4008 /* Don't optimize displacement for movabs since it only takes 64bit
4009 displacement. */
4010 if (i.disp_operands
a501d77e 4011 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4012 && (flag_code != CODE_64BIT
4013 || strcmp (mnemonic, "movabs") != 0))
4014 optimize_disp ();
29b0f896
AM		 4015
4016 /* Next, we find a template that matches the given insn,
4017 making sure the overlap of the given operands types is consistent
4018 with the template operand types. */
252b5132 4019
83b16ac6 4020 if (!(t = match_template (mnem_suffix)))
29b0f896 4021 return;
252b5132 4022
7bab8ab5 4023 if (sse_check != check_none
81f8a913 4024 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4025 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4026 && (i.tm.cpu_flags.bitfield.cpusse
4027 || i.tm.cpu_flags.bitfield.cpusse2
4028 || i.tm.cpu_flags.bitfield.cpusse3
4029 || i.tm.cpu_flags.bitfield.cpussse3
4030 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4031 || i.tm.cpu_flags.bitfield.cpusse4_2
4032 || i.tm.cpu_flags.bitfield.cpupclmul
4033 || i.tm.cpu_flags.bitfield.cpuaes
4034 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4035 {
7bab8ab5 4036 (sse_check == check_warning
daf50ae7
L		 4037 ? as_warn
4038 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4039 }
4040
321fd21e
L		 4041 /* Zap movzx and movsx suffix. The suffix has been set from
4042 "word ptr" or "byte ptr" on the source operand in Intel syntax
4043 or extracted from mnemonic in AT&T syntax. But we'll use
4044 the destination register to choose the suffix for encoding. */
4045 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4046 {
321fd21e
L		 4047 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4048 there is no suffix, the default will be byte extension. */
4049 if (i.reg_operands != 2
4050 && !i.suffix
7ab9ffdd 4051 && intel_syntax)
321fd21e
L		 4052 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4053
4054 i.suffix = 0;
cd61ebfe 4055 }
24eab124 4056
40fb9820 4057 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4058 if (!add_prefix (FWAIT_OPCODE))
4059 return;
252b5132 4060
d5de92cf
L		 4061 /* Check if REP prefix is OK. */
4062 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4063 {
4064 as_bad (_("invalid instruction `%s' after `%s'"),
4065 i.tm.name, i.rep_prefix);
4066 return;
4067 }
4068
c1ba0266
L		 4069 /* Check for lock without a lockable instruction. Destination operand
4070 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4071 if (i.prefix[LOCK_PREFIX]
4072 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4073 || i.mem_operands == 0
4074 || (i.tm.base_opcode != 0x86
4075 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4076 {
4077 as_bad (_("expecting lockable instruction after `lock'"));
4078 return;
4079 }
4080
42164a71 4081 /* Check if HLE prefix is OK. */
165de32a 4082 if (i.hle_prefix && !check_hle ())
42164a71
L		 4083 return;
4084
7e8b059b
L		 4085 /* Check BND prefix. */
4086 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4087 as_bad (_("expecting valid branch instruction after `bnd'"));
4088
04ef582a 4089 /* Check NOTRACK prefix. */
9fef80d6
L		 4090 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4091 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4092
327e8c42
JB		 4093 if (i.tm.cpu_flags.bitfield.cpumpx)
4094 {
4095 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4096 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4097 else if (flag_code != CODE_16BIT
4098 ? i.prefix[ADDR_PREFIX]
4099 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4100 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4101 }
7e8b059b
L		 4102
4103 /* Insert BND prefix. */
4104 if (add_bnd_prefix
4105 && i.tm.opcode_modifier.bndprefixok
4106 && !i.prefix[BND_PREFIX])
4107 add_prefix (BND_PREFIX_OPCODE);
4108
29b0f896 4109 /* Check string instruction segment overrides. */
40fb9820 4110 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4111 {
4112 if (!check_string ())
5dd0794d 4113 return;
fc0763e6 4114 i.disp_operands = 0;
29b0f896 4115 }
5dd0794d 4116
b6f8c7c4
L		 4117 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4118 optimize_encoding ();
4119
29b0f896
AM		 4120 if (!process_suffix ())
4121 return;
e413e4e9 4122
bc0844ae
L		 4123 /* Update operand types. */
4124 for (j = 0; j < i.operands; j++)
4125 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4126
29b0f896
AM		 4127 /* Make still unresolved immediate matches conform to size of immediate
4128 given in i.suffix. */
4129 if (!finalize_imm ())
4130 return;
252b5132 4131
40fb9820 4132 if (i.types[0].bitfield.imm1)
29b0f896 4133 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4134
9afe6eb8
L		 4135 /* We only need to check those implicit registers for instructions
4136 with 3 operands or less. */
4137 if (i.operands <= 3)
4138 for (j = 0; j < i.operands; j++)
4139 if (i.types[j].bitfield.inoutportreg
4140 || i.types[j].bitfield.shiftcount
1b54b8d7 4141 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4142 i.reg_operands--;
40fb9820 4143
c0f3af97
L		 4144 /* ImmExt should be processed after SSE2AVX. */
4145 if (!i.tm.opcode_modifier.sse2avx
4146 && i.tm.opcode_modifier.immext)
65da13b5 4147 process_immext ();
252b5132 4148
29b0f896
AM		 4149 /* For insns with operands there are more diddles to do to the opcode. */
4150 if (i.operands)
4151 {
4152 if (!process_operands ())
4153 return;
4154 }
40fb9820 4155 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4156 {
4157 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4158 as_warn (_("translating to `%sp'"), i.tm.name);
4159 }
252b5132 4160
e771e7c9
JB		 4161 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4162 || is_evex_encoding (&i.tm))
9e5e5283
L		 4163 {
4164 if (flag_code == CODE_16BIT)
4165 {
4166 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4167 i.tm.name);
4168 return;
4169 }
c0f3af97 4170
9e5e5283
L		 4171 if (i.tm.opcode_modifier.vex)
4172 build_vex_prefix (t);
4173 else
4174 build_evex_prefix ();
4175 }
43234a1e 4176
5dd85c99
SP		 4177 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4178 instructions may define INT_OPCODE as well, so avoid this corner
4179 case for those instructions that use MODRM. */
4180 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4181 && !i.tm.opcode_modifier.modrm
4182 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4183 {
4184 i.tm.base_opcode = INT3_OPCODE;
4185 i.imm_operands = 0;
4186 }
252b5132 4187
40fb9820
L		 4188 if ((i.tm.opcode_modifier.jump
4189 || i.tm.opcode_modifier.jumpbyte
4190 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4191 && i.op[0].disps->X_op == O_constant)
4192 {
4193 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4194 the absolute address given by the constant. Since ix86 jumps and
4195 calls are pc relative, we need to generate a reloc. */
4196 i.op[0].disps->X_add_symbol = &abs_symbol;
4197 i.op[0].disps->X_op = O_symbol;
4198 }
252b5132 4199
40fb9820 4200 if (i.tm.opcode_modifier.rex64)
161a04f6 4201 i.rex |= REX_W;
252b5132 4202
29b0f896
AM		 4203 /* For 8 bit registers we need an empty rex prefix. Also if the
4204 instruction already has a prefix, we need to convert old
4205 registers to new ones. */
773f551c 4206
dc821c5f 4207 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4208 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4210 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4211 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4213 && i.rex != 0))
4214 {
4215 int x;
726c5dcd 4216
29b0f896
AM		 4217 i.rex |= REX_OPCODE;
4218 for (x = 0; x < 2; x++)
4219 {
4220 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4221 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4222 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4223 {
29b0f896
AM		 4224 /* In case it is "hi" register, give up. */
4225 if (i.op[x].regs->reg_num > 3)
a540244d 4226 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4227 "instruction requiring REX prefix."),
a540244d 4228 register_prefix, i.op[x].regs->reg_name);
773f551c 4229
29b0f896
AM		 4230 /* Otherwise it is equivalent to the extended register.
4231 Since the encoding doesn't change this is merely
4232 cosmetic cleanup for debug output. */
4233
4234 i.op[x].regs = i.op[x].regs + 8;
773f551c 4235 }
29b0f896
AM		 4236 }
4237 }
773f551c 4238
6b6b6807
L		 4239 if (i.rex == 0 && i.rex_encoding)
4240 {
4241 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4242 that uses legacy register. If it is "hi" register, don't add
4243 the REX_OPCODE byte. */
4244 int x;
4245 for (x = 0; x < 2; x++)
4246 if (i.types[x].bitfield.reg
4247 && i.types[x].bitfield.byte
4248 && (i.op[x].regs->reg_flags & RegRex64) == 0
4249 && i.op[x].regs->reg_num > 3)
4250 {
4251 i.rex_encoding = FALSE;
4252 break;
4253 }
4254
4255 if (i.rex_encoding)
4256 i.rex = REX_OPCODE;
4257 }
4258
7ab9ffdd 4259 if (i.rex != 0)
29b0f896
AM		 4260 add_prefix (REX_OPCODE | i.rex);
4261
4262 /* We are ready to output the insn. */
4263 output_insn ();
4264}
4265
4266static char *
e3bb37b5 4267parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4268{
4269 char *l = line;
4270 char *token_start = l;
4271 char *mnem_p;
5c6af06e 4272 int supported;
d3ce72d0 4273 const insn_template *t;
b6169b20 4274 char *dot_p = NULL;
29b0f896 4275
29b0f896
AM		 4276 while (1)
4277 {
4278 mnem_p = mnemonic;
4279 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4280 {
b6169b20
L		 4281 if (*mnem_p == '.')
4282 dot_p = mnem_p;
29b0f896
AM		 4283 mnem_p++;
4284 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4285 {
29b0f896
AM		 4286 as_bad (_("no such instruction: `%s'"), token_start);
4287 return NULL;
4288 }
4289 l++;
4290 }
4291 if (!is_space_char (*l)
4292 && *l != END_OF_INSN
e44823cf
JB		 4293 && (intel_syntax
4294 || (*l != PREFIX_SEPARATOR
4295 && *l != ',')))
29b0f896
AM		 4296 {
4297 as_bad (_("invalid character %s in mnemonic"),
4298 output_invalid (*l));
4299 return NULL;
4300 }
4301 if (token_start == l)
4302 {
e44823cf 4303 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4304 as_bad (_("expecting prefix; got nothing"));
4305 else
4306 as_bad (_("expecting mnemonic; got nothing"));
4307 return NULL;
4308 }
45288df1 4309
29b0f896 4310 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4311 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4312
29b0f896
AM		 4313 if (*l != END_OF_INSN
4314 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4315 && current_templates
40fb9820 4316 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4317 {
c6fb90c8 4318 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4319 {
4320 as_bad ((flag_code != CODE_64BIT
4321 ? _("`%s' is only supported in 64-bit mode")
4322 : _("`%s' is not supported in 64-bit mode")),
4323 current_templates->start->name);
4324 return NULL;
4325 }
29b0f896
AM		 4326 /* If we are in 16-bit mode, do not allow addr16 or data16.
4327 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4328 if ((current_templates->start->opcode_modifier.size16
4329 || current_templates->start->opcode_modifier.size32)
29b0f896 4330 && flag_code != CODE_64BIT
40fb9820 4331 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4332 ^ (flag_code == CODE_16BIT)))
4333 {
4334 as_bad (_("redundant %s prefix"),
4335 current_templates->start->name);
4336 return NULL;
45288df1 4337 }
86fa6981 4338 if (current_templates->start->opcode_length == 0)
29b0f896 4339 {
86fa6981
L		 4340 /* Handle pseudo prefixes. */
4341 switch (current_templates->start->base_opcode)
4342 {
4343 case 0x0:
4344 /* {disp8} */
4345 i.disp_encoding = disp_encoding_8bit;
4346 break;
4347 case 0x1:
4348 /* {disp32} */
4349 i.disp_encoding = disp_encoding_32bit;
4350 break;
4351 case 0x2:
4352 /* {load} */
4353 i.dir_encoding = dir_encoding_load;
4354 break;
4355 case 0x3:
4356 /* {store} */
4357 i.dir_encoding = dir_encoding_store;
4358 break;
4359 case 0x4:
4360 /* {vex2} */
4361 i.vec_encoding = vex_encoding_vex2;
4362 break;
4363 case 0x5:
4364 /* {vex3} */
4365 i.vec_encoding = vex_encoding_vex3;
4366 break;
4367 case 0x6:
4368 /* {evex} */
4369 i.vec_encoding = vex_encoding_evex;
4370 break;
6b6b6807
L		 4371 case 0x7:
4372 /* {rex} */
4373 i.rex_encoding = TRUE;
4374 break;
b6f8c7c4
L		 4375 case 0x8:
4376 /* {nooptimize} */
4377 i.no_optimize = TRUE;
4378 break;
86fa6981
L		 4379 default:
4380 abort ();
4381 }
4382 }
4383 else
4384 {
4385 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4386 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4387 {
4e9ac44a
L		 4388 case PREFIX_EXIST:
4389 return NULL;
4390 case PREFIX_DS:
d777820b 4391 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4392 i.notrack_prefix = current_templates->start->name;
4393 break;
4394 case PREFIX_REP:
4395 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4396 i.hle_prefix = current_templates->start->name;
4397 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4398 i.bnd_prefix = current_templates->start->name;
4399 else
4400 i.rep_prefix = current_templates->start->name;
4401 break;
4402 default:
4403 break;
86fa6981 4404 }
29b0f896
AM		 4405 }
4406 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4407 token_start = ++l;
4408 }
4409 else
4410 break;
4411 }
45288df1 4412
30a55f88 4413 if (!current_templates)
b6169b20 4414 {
f8a5c266
L		 4415 /* Check if we should swap operand or force 32bit displacement in
4416 encoding. */
30a55f88 4417 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4418 i.dir_encoding = dir_encoding_store;
8d63c93e 4419 else if (mnem_p - 3 == dot_p
a501d77e
L		 4420 && dot_p[1] == 'd'
4421 && dot_p[2] == '8')
4422 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4423 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4424 && dot_p[1] == 'd'
4425 && dot_p[2] == '3'
4426 && dot_p[3] == '2')
a501d77e 4427 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4428 else
4429 goto check_suffix;
4430 mnem_p = dot_p;
4431 *dot_p = '\0';
d3ce72d0 4432 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4433 }
4434
29b0f896
AM		 4435 if (!current_templates)
4436 {
b6169b20 4437check_suffix:
29b0f896
AM		 4438 /* See if we can get a match by trimming off a suffix. */
4439 switch (mnem_p[-1])
4440 {
4441 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4442 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4443 i.suffix = SHORT_MNEM_SUFFIX;
4444 else
1a0670f3 4445 /* Fall through. */
29b0f896
AM		 4446 case BYTE_MNEM_SUFFIX:
4447 case QWORD_MNEM_SUFFIX:
4448 i.suffix = mnem_p[-1];
4449 mnem_p[-1] = '\0';
d3ce72d0
NC		 4450 current_templates = (const templates *) hash_find (op_hash,
4451 mnemonic);
29b0f896
AM		 4452 break;
4453 case SHORT_MNEM_SUFFIX:
4454 case LONG_MNEM_SUFFIX:
4455 if (!intel_syntax)
4456 {
4457 i.suffix = mnem_p[-1];
4458 mnem_p[-1] = '\0';
d3ce72d0
NC		 4459 current_templates = (const templates *) hash_find (op_hash,
4460 mnemonic);
29b0f896
AM		 4461 }
4462 break;
252b5132 4463
29b0f896
AM		 4464 /* Intel Syntax. */
4465 case 'd':
4466 if (intel_syntax)
4467 {
9306ca4a 4468 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4469 i.suffix = SHORT_MNEM_SUFFIX;
4470 else
4471 i.suffix = LONG_MNEM_SUFFIX;
4472 mnem_p[-1] = '\0';
d3ce72d0
NC		 4473 current_templates = (const templates *) hash_find (op_hash,
4474 mnemonic);
29b0f896
AM		 4475 }
4476 break;
4477 }
4478 if (!current_templates)
4479 {
4480 as_bad (_("no such instruction: `%s'"), token_start);
4481 return NULL;
4482 }
4483 }
252b5132 4484
40fb9820
L		 4485 if (current_templates->start->opcode_modifier.jump
4486 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4487 {
4488 /* Check for a branch hint. We allow ",pt" and ",pn" for
4489 predict taken and predict not taken respectively.
4490 I'm not sure that branch hints actually do anything on loop
4491 and jcxz insns (JumpByte) for current Pentium4 chips. They
4492 may work in the future and it doesn't hurt to accept them
4493 now. */
4494 if (l[0] == ',' && l[1] == 'p')
4495 {
4496 if (l[2] == 't')
4497 {
4498 if (!add_prefix (DS_PREFIX_OPCODE))
4499 return NULL;
4500 l += 3;
4501 }
4502 else if (l[2] == 'n')
4503 {
4504 if (!add_prefix (CS_PREFIX_OPCODE))
4505 return NULL;
4506 l += 3;
4507 }
4508 }
4509 }
4510 /* Any other comma loses. */
4511 if (*l == ',')
4512 {
4513 as_bad (_("invalid character %s in mnemonic"),
4514 output_invalid (*l));
4515 return NULL;
4516 }
252b5132 4517
29b0f896 4518 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4519 supported = 0;
4520 for (t = current_templates->start; t < current_templates->end; ++t)
4521 {
c0f3af97
L		 4522 supported |= cpu_flags_match (t);
4523 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4524 {
4525 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4526 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4527
548d0ee6
JB		 4528 return l;
4529 }
29b0f896 4530 }
3629bb00 4531
548d0ee6
JB		 4532 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4533 as_bad (flag_code == CODE_64BIT
4534 ? _("`%s' is not supported in 64-bit mode")
4535 : _("`%s' is only supported in 64-bit mode"),
4536 current_templates->start->name);
4537 else
4538 as_bad (_("`%s' is not supported on `%s%s'"),
4539 current_templates->start->name,
4540 cpu_arch_name ? cpu_arch_name : default_arch,
4541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4542
548d0ee6 4543 return NULL;
29b0f896 4544}
252b5132 4545
29b0f896 4546static char *
e3bb37b5 4547parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4548{
4549 char *token_start;
3138f287 4550
29b0f896
AM		 4551 /* 1 if operand is pending after ','. */
4552 unsigned int expecting_operand = 0;
252b5132 4553
29b0f896
AM		 4554 /* Non-zero if operand parens not balanced. */
4555 unsigned int paren_not_balanced;
4556
4557 while (*l != END_OF_INSN)
4558 {
4559 /* Skip optional white space before operand. */
4560 if (is_space_char (*l))
4561 ++l;
d02603dc 4562 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4563 {
4564 as_bad (_("invalid character %s before operand %d"),
4565 output_invalid (*l),
4566 i.operands + 1);
4567 return NULL;
4568 }
d02603dc 4569 token_start = l; /* After white space. */
29b0f896
AM		 4570 paren_not_balanced = 0;
4571 while (paren_not_balanced || *l != ',')
4572 {
4573 if (*l == END_OF_INSN)
4574 {
4575 if (paren_not_balanced)
4576 {
4577 if (!intel_syntax)
4578 as_bad (_("unbalanced parenthesis in operand %d."),
4579 i.operands + 1);
4580 else
4581 as_bad (_("unbalanced brackets in operand %d."),
4582 i.operands + 1);
4583 return NULL;
4584 }
4585 else
4586 break; /* we are done */
4587 }
d02603dc 4588 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4589 {
4590 as_bad (_("invalid character %s in operand %d"),
4591 output_invalid (*l),
4592 i.operands + 1);
4593 return NULL;
4594 }
4595 if (!intel_syntax)
4596 {
4597 if (*l == '(')
4598 ++paren_not_balanced;
4599 if (*l == ')')
4600 --paren_not_balanced;
4601 }
4602 else
4603 {
4604 if (*l == '[')
4605 ++paren_not_balanced;
4606 if (*l == ']')
4607 --paren_not_balanced;
4608 }
4609 l++;
4610 }
4611 if (l != token_start)
4612 { /* Yes, we've read in another operand. */
4613 unsigned int operand_ok;
4614 this_operand = i.operands++;
4615 if (i.operands > MAX_OPERANDS)
4616 {
4617 as_bad (_("spurious operands; (%d operands/instruction max)"),
4618 MAX_OPERANDS);
4619 return NULL;
4620 }
9d46ce34 4621 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4622 /* Now parse operand adding info to 'i' as we go along. */
4623 END_STRING_AND_SAVE (l);
4624
4625 if (intel_syntax)
4626 operand_ok =
4627 i386_intel_operand (token_start,
4628 intel_float_operand (mnemonic));
4629 else
a7619375 4630 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4631
4632 RESTORE_END_STRING (l);
4633 if (!operand_ok)
4634 return NULL;
4635 }
4636 else
4637 {
4638 if (expecting_operand)
4639 {
4640 expecting_operand_after_comma:
4641 as_bad (_("expecting operand after ','; got nothing"));
4642 return NULL;
4643 }
4644 if (*l == ',')
4645 {
4646 as_bad (_("expecting operand before ','; got nothing"));
4647 return NULL;
4648 }
4649 }
7f3f1ea2 4650
29b0f896
AM		 4651 /* Now *l must be either ',' or END_OF_INSN. */
4652 if (*l == ',')
4653 {
4654 if (*++l == END_OF_INSN)
4655 {
4656 /* Just skip it, if it's \n complain. */
4657 goto expecting_operand_after_comma;
4658 }
4659 expecting_operand = 1;
4660 }
4661 }
4662 return l;
4663}
7f3f1ea2 4664
050dfa73 4665static void
4d456e3d 4666swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4667{
4668 union i386_op temp_op;
40fb9820 4669 i386_operand_type temp_type;
050dfa73 4670 enum bfd_reloc_code_real temp_reloc;
4eed87de 4671
050dfa73
MM		 4672 temp_type = i.types[xchg2];
4673 i.types[xchg2] = i.types[xchg1];
4674 i.types[xchg1] = temp_type;
4675 temp_op = i.op[xchg2];
4676 i.op[xchg2] = i.op[xchg1];
4677 i.op[xchg1] = temp_op;
4678 temp_reloc = i.reloc[xchg2];
4679 i.reloc[xchg2] = i.reloc[xchg1];
4680 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4681
4682 if (i.mask)
4683 {
4684 if (i.mask->operand == xchg1)
4685 i.mask->operand = xchg2;
4686 else if (i.mask->operand == xchg2)
4687 i.mask->operand = xchg1;
4688 }
4689 if (i.broadcast)
4690 {
4691 if (i.broadcast->operand == xchg1)
4692 i.broadcast->operand = xchg2;
4693 else if (i.broadcast->operand == xchg2)
4694 i.broadcast->operand = xchg1;
4695 }
4696 if (i.rounding)
4697 {
4698 if (i.rounding->operand == xchg1)
4699 i.rounding->operand = xchg2;
4700 else if (i.rounding->operand == xchg2)
4701 i.rounding->operand = xchg1;
4702 }
050dfa73
MM		 4703}
4704
29b0f896 4705static void
e3bb37b5 4706swap_operands (void)
29b0f896 4707{
b7c61d9a 4708 switch (i.operands)
050dfa73 4709 {
c0f3af97 4710 case 5:
b7c61d9a 4711 case 4:
4d456e3d 4712 swap_2_operands (1, i.operands - 2);
1a0670f3 4713 /* Fall through. */
b7c61d9a
L		 4714 case 3:
4715 case 2:
4d456e3d 4716 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4717 break;
4718 default:
4719 abort ();
29b0f896 4720 }
29b0f896
AM		 4721
4722 if (i.mem_operands == 2)
4723 {
4724 const seg_entry *temp_seg;
4725 temp_seg = i.seg[0];
4726 i.seg[0] = i.seg[1];
4727 i.seg[1] = temp_seg;
4728 }
4729}
252b5132 4730
29b0f896
AM		 4731/* Try to ensure constant immediates are represented in the smallest
4732 opcode possible. */
4733static void
e3bb37b5 4734optimize_imm (void)
29b0f896
AM		 4735{
4736 char guess_suffix = 0;
4737 int op;
252b5132 4738
29b0f896
AM		 4739 if (i.suffix)
4740 guess_suffix = i.suffix;
4741 else if (i.reg_operands)
4742 {
4743 /* Figure out a suffix from the last register operand specified.
4744 We can't do this properly yet, ie. excluding InOutPortReg,
4745 but the following works for instructions with immediates.
4746 In any case, we can't set i.suffix yet. */
4747 for (op = i.operands; --op >= 0;)
dc821c5f 4748 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4749 {
40fb9820
L		 4750 guess_suffix = BYTE_MNEM_SUFFIX;
4751 break;
4752 }
dc821c5f 4753 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4754 {
40fb9820
L		 4755 guess_suffix = WORD_MNEM_SUFFIX;
4756 break;
4757 }
dc821c5f 4758 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4759 {
4760 guess_suffix = LONG_MNEM_SUFFIX;
4761 break;
4762 }
dc821c5f 4763 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4764 {
4765 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4766 break;
252b5132 4767 }
29b0f896
AM		 4768 }
4769 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4770 guess_suffix = WORD_MNEM_SUFFIX;
4771
4772 for (op = i.operands; --op >= 0;)
40fb9820 4773 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4774 {
4775 switch (i.op[op].imms->X_op)
252b5132 4776 {
29b0f896
AM		 4777 case O_constant:
4778 /* If a suffix is given, this operand may be shortened. */
4779 switch (guess_suffix)
252b5132 4780 {
29b0f896 4781 case LONG_MNEM_SUFFIX:
40fb9820
L		 4782 i.types[op].bitfield.imm32 = 1;
4783 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4784 break;
4785 case WORD_MNEM_SUFFIX:
40fb9820
L		 4786 i.types[op].bitfield.imm16 = 1;
4787 i.types[op].bitfield.imm32 = 1;
4788 i.types[op].bitfield.imm32s = 1;
4789 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4790 break;
4791 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4792 i.types[op].bitfield.imm8 = 1;
4793 i.types[op].bitfield.imm8s = 1;
4794 i.types[op].bitfield.imm16 = 1;
4795 i.types[op].bitfield.imm32 = 1;
4796 i.types[op].bitfield.imm32s = 1;
4797 i.types[op].bitfield.imm64 = 1;
29b0f896 4798 break;
252b5132 4799 }
252b5132 4800
29b0f896
AM		 4801 /* If this operand is at most 16 bits, convert it
4802 to a signed 16 bit number before trying to see
4803 whether it will fit in an even smaller size.
4804 This allows a 16-bit operand such as $0xffe0 to
4805 be recognised as within Imm8S range. */
40fb9820 4806 if ((i.types[op].bitfield.imm16)
29b0f896 4807 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4808 {
29b0f896
AM		 4809 i.op[op].imms->X_add_number =
4810 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4811 }
a28def75
L		 4812#ifdef BFD64
4813 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4814 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4815 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4816 == 0))
4817 {
4818 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4819 ^ ((offsetT) 1 << 31))
4820 - ((offsetT) 1 << 31));
4821 }
a28def75 4822#endif
40fb9820 4823 i.types[op]
c6fb90c8
L		 4824 = operand_type_or (i.types[op],
4825 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4826
29b0f896
AM		 4827 /* We must avoid matching of Imm32 templates when 64bit
4828 only immediate is available. */
4829 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4830 i.types[op].bitfield.imm32 = 0;
29b0f896 4831 break;
252b5132 4832
29b0f896
AM		 4833 case O_absent:
4834 case O_register:
4835 abort ();
4836
4837 /* Symbols and expressions. */
4838 default:
9cd96992
JB		 4839 /* Convert symbolic operand to proper sizes for matching, but don't
4840 prevent matching a set of insns that only supports sizes other
4841 than those matching the insn suffix. */
4842 {
40fb9820 4843 i386_operand_type mask, allowed;
d3ce72d0 4844 const insn_template *t;
9cd96992 4845
0dfbf9d7
L		 4846 operand_type_set (&mask, 0);
4847 operand_type_set (&allowed, 0);
40fb9820 4848
4eed87de
AM		 4849 for (t = current_templates->start;
4850 t < current_templates->end;
4851 ++t)
c6fb90c8
L		 4852 allowed = operand_type_or (allowed,
4853 t->operand_types[op]);
9cd96992
JB		 4854 switch (guess_suffix)
4855 {
4856 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4857 mask.bitfield.imm64 = 1;
4858 mask.bitfield.imm32s = 1;
9cd96992
JB		 4859 break;
4860 case LONG_MNEM_SUFFIX:
40fb9820 4861 mask.bitfield.imm32 = 1;
9cd96992
JB		 4862 break;
4863 case WORD_MNEM_SUFFIX:
40fb9820 4864 mask.bitfield.imm16 = 1;
9cd96992
JB		 4865 break;
4866 case BYTE_MNEM_SUFFIX:
40fb9820 4867 mask.bitfield.imm8 = 1;
9cd96992
JB		 4868 break;
4869 default:
9cd96992
JB		 4870 break;
4871 }
c6fb90c8 4872 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4873 if (!operand_type_all_zero (&allowed))
c6fb90c8 4874 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4875 }
29b0f896 4876 break;
252b5132 4877 }
29b0f896
AM		 4878 }
4879}
47926f60 4880
29b0f896
AM		 4881/* Try to use the smallest displacement type too. */
4882static void
e3bb37b5 4883optimize_disp (void)
29b0f896
AM		 4884{
4885 int op;
3e73aa7c 4886
29b0f896 4887 for (op = i.operands; --op >= 0;)
40fb9820 4888 if (operand_type_check (i.types[op], disp))
252b5132 4889 {
b300c311 4890 if (i.op[op].disps->X_op == O_constant)
252b5132 4891 {
91d6fa6a 4892 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4893
40fb9820 4894 if (i.types[op].bitfield.disp16
91d6fa6a 4895 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4896 {
4897 /* If this operand is at most 16 bits, convert
4898 to a signed 16 bit number and don't use 64bit
4899 displacement. */
91d6fa6a 4900 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4901 i.types[op].bitfield.disp64 = 0;
b300c311 4902 }
a28def75
L		 4903#ifdef BFD64
4904 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4905 if (i.types[op].bitfield.disp32
91d6fa6a 4906 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4907 {
4908 /* If this operand is at most 32 bits, convert
4909 to a signed 32 bit number and don't use 64bit
4910 displacement. */
91d6fa6a
NC		 4911 op_disp &= (((offsetT) 2 << 31) - 1);
4912 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4913 i.types[op].bitfield.disp64 = 0;
b300c311 4914 }
a28def75 4915#endif
91d6fa6a 4916 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4917 {
40fb9820
L		 4918 i.types[op].bitfield.disp8 = 0;
4919 i.types[op].bitfield.disp16 = 0;
4920 i.types[op].bitfield.disp32 = 0;
4921 i.types[op].bitfield.disp32s = 0;
4922 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4923 i.op[op].disps = 0;
4924 i.disp_operands--;
4925 }
4926 else if (flag_code == CODE_64BIT)
4927 {
91d6fa6a 4928 if (fits_in_signed_long (op_disp))
28a9d8f5 4929 {
40fb9820
L		 4930 i.types[op].bitfield.disp64 = 0;
4931 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4932 }
0e1147d9 4933 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4934 && fits_in_unsigned_long (op_disp))
40fb9820 4935 i.types[op].bitfield.disp32 = 1;
b300c311 4936 }
40fb9820
L		 4937 if ((i.types[op].bitfield.disp32
4938 || i.types[op].bitfield.disp32s
4939 || i.types[op].bitfield.disp16)
b5014f7a 4940 && fits_in_disp8 (op_disp))
40fb9820 4941 i.types[op].bitfield.disp8 = 1;
252b5132 4942 }
67a4f2b7
AO		 4943 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4944 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4945 {
4946 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4947 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4948 i.types[op].bitfield.disp8 = 0;
4949 i.types[op].bitfield.disp16 = 0;
4950 i.types[op].bitfield.disp32 = 0;
4951 i.types[op].bitfield.disp32s = 0;
4952 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4953 }
4954 else
b300c311 4955 /* We only support 64bit displacement on constants. */
40fb9820 4956 i.types[op].bitfield.disp64 = 0;
252b5132 4957 }
29b0f896
AM		 4958}
4959
6c30d220
L		 4960/* Check if operands are valid for the instruction. */
4961
4962static int
4963check_VecOperands (const insn_template *t)
4964{
43234a1e
L		 4965 unsigned int op;
4966
6c30d220
L		 4967 /* Without VSIB byte, we can't have a vector register for index. */
4968 if (!t->opcode_modifier.vecsib
4969 && i.index_reg
1b54b8d7
JB		 4970 && (i.index_reg->reg_type.bitfield.xmmword
4971 || i.index_reg->reg_type.bitfield.ymmword
4972 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4973 {
4974 i.error = unsupported_vector_index_register;
4975 return 1;
4976 }
4977
ad8ecc81
MZ		 4978 /* Check if default mask is allowed. */
4979 if (t->opcode_modifier.nodefmask
4980 && (!i.mask || i.mask->mask->reg_num == 0))
4981 {
4982 i.error = no_default_mask;
4983 return 1;
4984 }
4985
7bab8ab5
JB		 4986 /* For VSIB byte, we need a vector register for index, and all vector
4987 registers must be distinct. */
4988 if (t->opcode_modifier.vecsib)
4989 {
4990 if (!i.index_reg
6c30d220 4991 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4992 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4993 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4994 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4995 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4996 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4997 {
4998 i.error = invalid_vsib_address;
4999 return 1;
5000 }
5001
43234a1e
L		 5002 gas_assert (i.reg_operands == 2 || i.mask);
5003 if (i.reg_operands == 2 && !i.mask)
5004 {
1b54b8d7
JB		 5005 gas_assert (i.types[0].bitfield.regsimd);
5006 gas_assert (i.types[0].bitfield.xmmword
5007 || i.types[0].bitfield.ymmword);
5008 gas_assert (i.types[2].bitfield.regsimd);
5009 gas_assert (i.types[2].bitfield.xmmword
5010 || i.types[2].bitfield.ymmword);
43234a1e
L		 5011 if (operand_check == check_none)
5012 return 0;
5013 if (register_number (i.op[0].regs)
5014 != register_number (i.index_reg)
5015 && register_number (i.op[2].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[0].regs)
5018 != register_number (i.op[2].regs))
5019 return 0;
5020 if (operand_check == check_error)
5021 {
5022 i.error = invalid_vector_register_set;
5023 return 1;
5024 }
5025 as_warn (_("mask, index, and destination registers should be distinct"));
5026 }
8444f82a
MZ		 5027 else if (i.reg_operands == 1 && i.mask)
5028 {
1b54b8d7
JB		 5029 if (i.types[1].bitfield.regsimd
5030 && (i.types[1].bitfield.xmmword
5031 || i.types[1].bitfield.ymmword
5032 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5033 && (register_number (i.op[1].regs)
5034 == register_number (i.index_reg)))
5035 {
5036 if (operand_check == check_error)
5037 {
5038 i.error = invalid_vector_register_set;
5039 return 1;
5040 }
5041 if (operand_check != check_none)
5042 as_warn (_("index and destination registers should be distinct"));
5043 }
5044 }
43234a1e 5045 }
7bab8ab5 5046
43234a1e
L		 5047 /* Check if broadcast is supported by the instruction and is applied
5048 to the memory operand. */
5049 if (i.broadcast)
5050 {
8e6e0792 5051 i386_operand_type type, overlap;
43234a1e
L		 5052
5053 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5054 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5055 op = i.broadcast->operand;
8e6e0792 5056 if (!t->opcode_modifier.broadcast
32546502 5057 || !i.types[op].bitfield.mem
c39e5b26
JB		 5058 || (!i.types[op].bitfield.unspecified
5059 && (t->operand_types[op].bitfield.dword
5060 ? !i.types[op].bitfield.dword
5061 : !i.types[op].bitfield.qword)))
43234a1e
L		 5062 {
5063 bad_broadcast:
5064 i.error = unsupported_broadcast;
5065 return 1;
5066 }
8e6e0792
JB		 5067
5068 operand_type_set (&type, 0);
c39e5b26 5069 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5070 {
5071 case 8:
5072 type.bitfield.qword = 1;
5073 break;
5074 case 16:
5075 type.bitfield.xmmword = 1;
5076 break;
5077 case 32:
5078 type.bitfield.ymmword = 1;
5079 break;
5080 case 64:
5081 type.bitfield.zmmword = 1;
5082 break;
5083 default:
5084 goto bad_broadcast;
5085 }
5086
5087 overlap = operand_type_and (type, t->operand_types[op]);
5088 if (operand_type_all_zero (&overlap))
5089 goto bad_broadcast;
5090
5091 if (t->opcode_modifier.checkregsize)
5092 {
5093 unsigned int j;
5094
5095 for (j = 0; j < i.operands; ++j)
5096 {
5097 if (j != op
5098 && !operand_type_register_match(i.types[j],
5099 t->operand_types[j],
5100 type,
5101 t->operand_types[op]))
5102 goto bad_broadcast;
5103 }
5104 }
43234a1e
L		 5105 }
5106 /* If broadcast is supported in this instruction, we need to check if
5107 operand of one-element size isn't specified without broadcast. */
5108 else if (t->opcode_modifier.broadcast && i.mem_operands)
5109 {
5110 /* Find memory operand. */
5111 for (op = 0; op < i.operands; op++)
5112 if (operand_type_check (i.types[op], anymem))
5113 break;
5114 gas_assert (op < i.operands);
5115 /* Check size of the memory operand. */
c39e5b26
JB		 5116 if (t->operand_types[op].bitfield.dword
5117 ? i.types[op].bitfield.dword
5118 : i.types[op].bitfield.qword)
43234a1e
L		 5119 {
5120 i.error = broadcast_needed;
5121 return 1;
5122 }
5123 }
c39e5b26
JB		 5124 else
5125 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5126
5127 /* Check if requested masking is supported. */
5128 if (i.mask
5129 && (!t->opcode_modifier.masking
5130 || (i.mask->zeroing
5131 && t->opcode_modifier.masking == MERGING_MASKING)))
5132 {
5133 i.error = unsupported_masking;
5134 return 1;
5135 }
5136
5137 /* Check if masking is applied to dest operand. */
5138 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5139 {
5140 i.error = mask_not_on_destination;
5141 return 1;
5142 }
5143
43234a1e
L		 5144 /* Check RC/SAE. */
5145 if (i.rounding)
5146 {
5147 if ((i.rounding->type != saeonly
5148 && !t->opcode_modifier.staticrounding)
5149 || (i.rounding->type == saeonly
5150 && (t->opcode_modifier.staticrounding
5151 || !t->opcode_modifier.sae)))
5152 {
5153 i.error = unsupported_rc_sae;
5154 return 1;
5155 }
5156 /* If the instruction has several immediate operands and one of
5157 them is rounding, the rounding operand should be the last
5158 immediate operand. */
5159 if (i.imm_operands > 1
5160 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5161 {
43234a1e 5162 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5163 return 1;
5164 }
6c30d220
L		 5165 }
5166
43234a1e 5167 /* Check vector Disp8 operand. */
b5014f7a
JB		 5168 if (t->opcode_modifier.disp8memshift
5169 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5170 {
5171 if (i.broadcast)
c39e5b26 5172 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
43234a1e
L		 5173 else
5174 i.memshift = t->opcode_modifier.disp8memshift;
5175
5176 for (op = 0; op < i.operands; op++)
5177 if (operand_type_check (i.types[op], disp)
5178 && i.op[op].disps->X_op == O_constant)
5179 {
b5014f7a 5180 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5181 {
b5014f7a
JB		 5182 i.types[op].bitfield.disp8 = 1;
5183 return 0;
43234a1e 5184 }
b5014f7a 5185 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5186 }
5187 }
b5014f7a
JB		 5188
5189 i.memshift = 0;
43234a1e 5190
6c30d220
L		 5191 return 0;
5192}
5193
43f3e2ee 5194/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5195 operand types. */
5196
5197static int
5198VEX_check_operands (const insn_template *t)
5199{
86fa6981 5200 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5201 {
86fa6981 5202 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5203 if (!is_evex_encoding (t))
86fa6981
L		 5204 {
5205 i.error = unsupported;
5206 return 1;
5207 }
5208 return 0;
43234a1e
L		 5209 }
5210
a683cc34 5211 if (!t->opcode_modifier.vex)
86fa6981
L		 5212 {
5213 /* This instruction template doesn't have VEX prefix. */
5214 if (i.vec_encoding != vex_encoding_default)
5215 {
5216 i.error = unsupported;
5217 return 1;
5218 }
5219 return 0;
5220 }
a683cc34
SP		 5221
5222 /* Only check VEX_Imm4, which must be the first operand. */
5223 if (t->operand_types[0].bitfield.vec_imm4)
5224 {
5225 if (i.op[0].imms->X_op != O_constant
5226 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5227 {
a65babc9 5228 i.error = bad_imm4;
891edac4
L		 5229 return 1;
5230 }
a683cc34
SP		 5231
5232 /* Turn off Imm8 so that update_imm won't complain. */
5233 i.types[0] = vec_imm4;
5234 }
5235
5236 return 0;
5237}
5238
d3ce72d0 5239static const insn_template *
83b16ac6 5240match_template (char mnem_suffix)
29b0f896
AM		 5241{
5242 /* Points to template once we've found it. */
d3ce72d0 5243 const insn_template *t;
40fb9820 5244 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5245 i386_operand_type overlap4;
29b0f896 5246 unsigned int found_reverse_match;
83b16ac6 5247 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5248 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5249 int addr_prefix_disp;
a5c311ca 5250 unsigned int j;
3629bb00 5251 unsigned int found_cpu_match;
45664ddb 5252 unsigned int check_register;
5614d22c 5253 enum i386_error specific_error = 0;
29b0f896 5254
c0f3af97
L		 5255#if MAX_OPERANDS != 5
5256# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5257#endif
5258
29b0f896 5259 found_reverse_match = 0;
539e75ad 5260 addr_prefix_disp = -1;
40fb9820
L		 5261
5262 memset (&suffix_check, 0, sizeof (suffix_check));
5263 if (i.suffix == BYTE_MNEM_SUFFIX)
5264 suffix_check.no_bsuf = 1;
5265 else if (i.suffix == WORD_MNEM_SUFFIX)
5266 suffix_check.no_wsuf = 1;
5267 else if (i.suffix == SHORT_MNEM_SUFFIX)
5268 suffix_check.no_ssuf = 1;
5269 else if (i.suffix == LONG_MNEM_SUFFIX)
5270 suffix_check.no_lsuf = 1;
5271 else if (i.suffix == QWORD_MNEM_SUFFIX)
5272 suffix_check.no_qsuf = 1;
5273 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5274 suffix_check.no_ldsuf = 1;
29b0f896 5275
83b16ac6
JB		 5276 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5277 if (intel_syntax)
5278 {
5279 switch (mnem_suffix)
5280 {
5281 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5282 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5283 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5284 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5285 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5286 }
5287 }
5288
01559ecc
L		 5289 /* Must have right number of operands. */
5290 i.error = number_of_operands_mismatch;
5291
45aa61fe 5292 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5293 {
539e75ad
L		 5294 addr_prefix_disp = -1;
5295
29b0f896
AM		 5296 if (i.operands != t->operands)
5297 continue;
5298
50aecf8c 5299 /* Check processor support. */
a65babc9 5300 i.error = unsupported;
c0f3af97
L		 5301 found_cpu_match = (cpu_flags_match (t)
5302 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5303 if (!found_cpu_match)
5304 continue;
5305
e1d4d893 5306 /* Check AT&T mnemonic. */
a65babc9 5307 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5308 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5309 continue;
5310
e92bae62 5311 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5312 i.error = unsupported_syntax;
5c07affc 5313 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5314 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5315 || (intel64 && t->opcode_modifier.amd64)
5316 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5317 continue;
5318
20592a94 5319 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5320 i.error = invalid_instruction_suffix;
567e4e96
L		 5321 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5322 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5323 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5324 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5325 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5326 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5327 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5328 continue;
83b16ac6
JB		 5329 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5330 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5331 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5332 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5333 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5334 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5335 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5336 continue;
29b0f896 5337
5c07affc 5338 if (!operand_size_match (t))
7d5e4556 5339 continue;
539e75ad 5340
5c07affc
L		 5341 for (j = 0; j < MAX_OPERANDS; j++)
5342 operand_types[j] = t->operand_types[j];
5343
45aa61fe
AM		 5344 /* In general, don't allow 64-bit operands in 32-bit mode. */
5345 if (i.suffix == QWORD_MNEM_SUFFIX
5346 && flag_code != CODE_64BIT
5347 && (intel_syntax
40fb9820 5348 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5349 && !intel_float_operand (t->name))
5350 : intel_float_operand (t->name) != 2)
40fb9820 5351 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5352 && !operand_types[0].bitfield.regsimd)
40fb9820 5353 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5354 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5355 && (t->base_opcode != 0x0fc7
5356 || t->extension_opcode != 1 /* cmpxchg8b */))
5357 continue;
5358
192dc9c6
JB		 5359 /* In general, don't allow 32-bit operands on pre-386. */
5360 else if (i.suffix == LONG_MNEM_SUFFIX
5361 && !cpu_arch_flags.bitfield.cpui386
5362 && (intel_syntax
5363 ? (!t->opcode_modifier.ignoresize
5364 && !intel_float_operand (t->name))
5365 : intel_float_operand (t->name) != 2)
5366 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5367 && !operand_types[0].bitfield.regsimd)
192dc9c6 5368 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5369 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5370 continue;
5371
29b0f896 5372 /* Do not verify operands when there are none. */
50aecf8c 5373 else
29b0f896 5374 {
c6fb90c8 5375 if (!t->operands)
2dbab7d5
L		 5376 /* We've found a match; break out of loop. */
5377 break;
29b0f896 5378 }
252b5132 5379
539e75ad
L		 5380 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5381 into Disp32/Disp16/Disp32 operand. */
5382 if (i.prefix[ADDR_PREFIX] != 0)
5383 {
40fb9820 5384 /* There should be only one Disp operand. */
539e75ad
L		 5385 switch (flag_code)
5386 {
5387 case CODE_16BIT:
40fb9820
L		 5388 for (j = 0; j < MAX_OPERANDS; j++)
5389 {
5390 if (operand_types[j].bitfield.disp16)
5391 {
5392 addr_prefix_disp = j;
5393 operand_types[j].bitfield.disp32 = 1;
5394 operand_types[j].bitfield.disp16 = 0;
5395 break;
5396 }
5397 }
539e75ad
L		 5398 break;
5399 case CODE_32BIT:
40fb9820
L		 5400 for (j = 0; j < MAX_OPERANDS; j++)
5401 {
5402 if (operand_types[j].bitfield.disp32)
5403 {
5404 addr_prefix_disp = j;
5405 operand_types[j].bitfield.disp32 = 0;
5406 operand_types[j].bitfield.disp16 = 1;
5407 break;
5408 }
5409 }
539e75ad
L		 5410 break;
5411 case CODE_64BIT:
40fb9820
L		 5412 for (j = 0; j < MAX_OPERANDS; j++)
5413 {
5414 if (operand_types[j].bitfield.disp64)
5415 {
5416 addr_prefix_disp = j;
5417 operand_types[j].bitfield.disp64 = 0;
5418 operand_types[j].bitfield.disp32 = 1;
5419 break;
5420 }
5421 }
539e75ad
L		 5422 break;
5423 }
539e75ad
L		 5424 }
5425
02a86693
L		 5426 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5427 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5428 continue;
5429
56ffb741
L		 5430 /* We check register size if needed. */
5431 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5432 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5433 switch (t->operands)
5434 {
5435 case 1:
40fb9820 5436 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5437 continue;
5438 break;
5439 case 2:
33eaf5de 5440 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5441 only in 32bit mode and we can use opcode 0x90. In 64bit
5442 mode, we can't use 0x90 for xchg %eax, %eax since it should
5443 zero-extend %eax to %rax. */
5444 if (flag_code == CODE_64BIT
5445 && t->base_opcode == 0x90
0dfbf9d7
L		 5446 && operand_type_equal (&i.types [0], &acc32)
5447 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5448 continue;
1212781b
JB		 5449 /* xrelease mov %eax, <disp> is another special case. It must not
5450 match the accumulator-only encoding of mov. */
5451 if (flag_code != CODE_64BIT
5452 && i.hle_prefix
5453 && t->base_opcode == 0xa0
5454 && i.types[0].bitfield.acc
5455 && operand_type_check (i.types[1], anymem))
5456 continue;
86fa6981
L		 5457 /* If we want store form, we reverse direction of operands. */
5458 if (i.dir_encoding == dir_encoding_store
5459 && t->opcode_modifier.d)
5460 goto check_reverse;
1a0670f3 5461 /* Fall through. */
b6169b20 5462
29b0f896 5463 case 3:
86fa6981
L		 5464 /* If we want store form, we skip the current load. */
5465 if (i.dir_encoding == dir_encoding_store
5466 && i.mem_operands == 0
5467 && t->opcode_modifier.load)
fa99fab2 5468 continue;
1a0670f3 5469 /* Fall through. */
f48ff2ae 5470 case 4:
c0f3af97 5471 case 5:
c6fb90c8 5472 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5473 if (!operand_type_match (overlap0, i.types[0])
5474 || !operand_type_match (overlap1, i.types[1])
45664ddb 5475 || (check_register
dc821c5f 5476 && !operand_type_register_match (i.types[0],
40fb9820 5477 operand_types[0],
dc821c5f 5478 i.types[1],
40fb9820 5479 operand_types[1])))
29b0f896
AM		 5480 {
5481 /* Check if other direction is valid ... */
38e314eb 5482 if (!t->opcode_modifier.d)
29b0f896
AM		 5483 continue;
5484
b6169b20 5485check_reverse:
29b0f896 5486 /* Try reversing direction of operands. */
c6fb90c8
L		 5487 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5488 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5489 if (!operand_type_match (overlap0, i.types[0])
5490 || !operand_type_match (overlap1, i.types[1])
45664ddb 5491 || (check_register
dc821c5f 5492 && !operand_type_register_match (i.types[0],
45664ddb 5493 operand_types[1],
45664ddb
L		 5494 i.types[1],
5495 operand_types[0])))
29b0f896
AM		 5496 {
5497 /* Does not match either direction. */
5498 continue;
5499 }
38e314eb 5500 /* found_reverse_match holds which of D or FloatR
29b0f896 5501 we've found. */
38e314eb
JB		 5502 if (!t->opcode_modifier.d)
5503 found_reverse_match = 0;
5504 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5505 found_reverse_match = Opcode_FloatD;
5506 else
38e314eb 5507 found_reverse_match = Opcode_D;
40fb9820 5508 if (t->opcode_modifier.floatr)
8a2ed489 5509 found_reverse_match |= Opcode_FloatR;
29b0f896 5510 }
f48ff2ae 5511 else
29b0f896 5512 {
f48ff2ae 5513 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5514 switch (t->operands)
5515 {
c0f3af97
L		 5516 case 5:
5517 overlap4 = operand_type_and (i.types[4],
5518 operand_types[4]);
1a0670f3 5519 /* Fall through. */
d1cbb4db 5520 case 4:
c6fb90c8
L		 5521 overlap3 = operand_type_and (i.types[3],
5522 operand_types[3]);
1a0670f3 5523 /* Fall through. */
d1cbb4db 5524 case 3:
c6fb90c8
L		 5525 overlap2 = operand_type_and (i.types[2],
5526 operand_types[2]);
d1cbb4db
L		 5527 break;
5528 }
29b0f896 5529
f48ff2ae
L		 5530 switch (t->operands)
5531 {
c0f3af97
L		 5532 case 5:
5533 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5534 || !operand_type_register_match (i.types[3],
c0f3af97 5535 operand_types[3],
c0f3af97
L		 5536 i.types[4],
5537 operand_types[4]))
5538 continue;
1a0670f3 5539 /* Fall through. */
f48ff2ae 5540 case 4:
40fb9820 5541 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5542 || (check_register
f7768225
JB		 5543 && (!operand_type_register_match (i.types[1],
5544 operand_types[1],
5545 i.types[3],
5546 operand_types[3])
5547 || !operand_type_register_match (i.types[2],
5548 operand_types[2],
5549 i.types[3],
5550 operand_types[3]))))
f48ff2ae 5551 continue;
1a0670f3 5552 /* Fall through. */
f48ff2ae
L		 5553 case 3:
5554 /* Here we make use of the fact that there are no
23e42951 5555 reverse match 3 operand instructions. */
40fb9820 5556 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5557 || (check_register
23e42951
JB		 5558 && (!operand_type_register_match (i.types[0],
5559 operand_types[0],
5560 i.types[2],
5561 operand_types[2])
5562 || !operand_type_register_match (i.types[1],
5563 operand_types[1],
5564 i.types[2],
5565 operand_types[2]))))
f48ff2ae
L		 5566 continue;
5567 break;
5568 }
29b0f896 5569 }
f48ff2ae 5570 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5571 slip through to break. */
5572 }
3629bb00 5573 if (!found_cpu_match)
29b0f896
AM		 5574 {
5575 found_reverse_match = 0;
5576 continue;
5577 }
c0f3af97 5578
5614d22c
JB		 5579 /* Check if vector and VEX operands are valid. */
5580 if (check_VecOperands (t) || VEX_check_operands (t))
5581 {
5582 specific_error = i.error;
5583 continue;
5584 }
a683cc34 5585
29b0f896
AM		 5586 /* We've found a match; break out of loop. */
5587 break;
5588 }
5589
5590 if (t == current_templates->end)
5591 {
5592 /* We found no match. */
a65babc9 5593 const char *err_msg;
5614d22c 5594 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5595 {
5596 default:
5597 abort ();
86e026a4 5598 case operand_size_mismatch:
a65babc9
L		 5599 err_msg = _("operand size mismatch");
5600 break;
5601 case operand_type_mismatch:
5602 err_msg = _("operand type mismatch");
5603 break;
5604 case register_type_mismatch:
5605 err_msg = _("register type mismatch");
5606 break;
5607 case number_of_operands_mismatch:
5608 err_msg = _("number of operands mismatch");
5609 break;
5610 case invalid_instruction_suffix:
5611 err_msg = _("invalid instruction suffix");
5612 break;
5613 case bad_imm4:
4a2608e3 5614 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5615 break;
a65babc9
L		 5616 case unsupported_with_intel_mnemonic:
5617 err_msg = _("unsupported with Intel mnemonic");
5618 break;
5619 case unsupported_syntax:
5620 err_msg = _("unsupported syntax");
5621 break;
5622 case unsupported:
35262a23 5623 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5624 current_templates->start->name);
5625 return NULL;
6c30d220
L		 5626 case invalid_vsib_address:
5627 err_msg = _("invalid VSIB address");
5628 break;
7bab8ab5
JB		 5629 case invalid_vector_register_set:
5630 err_msg = _("mask, index, and destination registers must be distinct");
5631 break;
6c30d220
L		 5632 case unsupported_vector_index_register:
5633 err_msg = _("unsupported vector index register");
5634 break;
43234a1e
L		 5635 case unsupported_broadcast:
5636 err_msg = _("unsupported broadcast");
5637 break;
5638 case broadcast_not_on_src_operand:
5639 err_msg = _("broadcast not on source memory operand");
5640 break;
5641 case broadcast_needed:
5642 err_msg = _("broadcast is needed for operand of such type");
5643 break;
5644 case unsupported_masking:
5645 err_msg = _("unsupported masking");
5646 break;
5647 case mask_not_on_destination:
5648 err_msg = _("mask not on destination operand");
5649 break;
5650 case no_default_mask:
5651 err_msg = _("default mask isn't allowed");
5652 break;
5653 case unsupported_rc_sae:
5654 err_msg = _("unsupported static rounding/sae");
5655 break;
5656 case rc_sae_operand_not_last_imm:
5657 if (intel_syntax)
5658 err_msg = _("RC/SAE operand must precede immediate operands");
5659 else
5660 err_msg = _("RC/SAE operand must follow immediate operands");
5661 break;
5662 case invalid_register_operand:
5663 err_msg = _("invalid register operand");
5664 break;
a65babc9
L		 5665 }
5666 as_bad (_("%s for `%s'"), err_msg,
891edac4 5667 current_templates->start->name);
fa99fab2 5668 return NULL;
29b0f896 5669 }
252b5132 5670
29b0f896
AM		 5671 if (!quiet_warnings)
5672 {
5673 if (!intel_syntax
40fb9820
L		 5674 && (i.types[0].bitfield.jumpabsolute
5675 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5676 {
5677 as_warn (_("indirect %s without `*'"), t->name);
5678 }
5679
40fb9820
L		 5680 if (t->opcode_modifier.isprefix
5681 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5682 {
5683 /* Warn them that a data or address size prefix doesn't
5684 affect assembly of the next line of code. */
5685 as_warn (_("stand-alone `%s' prefix"), t->name);
5686 }
5687 }
5688
5689 /* Copy the template we found. */
5690 i.tm = *t;
539e75ad
L		 5691
5692 if (addr_prefix_disp != -1)
5693 i.tm.operand_types[addr_prefix_disp]
5694 = operand_types[addr_prefix_disp];
5695
29b0f896
AM		 5696 if (found_reverse_match)
5697 {
5698 /* If we found a reverse match we must alter the opcode
5699 direction bit. found_reverse_match holds bits to change
5700 (different for int & float insns). */
5701
5702 i.tm.base_opcode ^= found_reverse_match;
5703
539e75ad
L		 5704 i.tm.operand_types[0] = operand_types[1];
5705 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5706 }
5707
fa99fab2 5708 return t;
29b0f896
AM		 5709}
5710
5711static int
e3bb37b5 5712check_string (void)
29b0f896 5713{
40fb9820
L		 5714 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5715 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5716 {
5717 if (i.seg[0] != NULL && i.seg[0] != &es)
5718 {
a87af027 5719 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5720 i.tm.name,
a87af027
JB		 5721 mem_op + 1,
5722 register_prefix);
29b0f896
AM		 5723 return 0;
5724 }
5725 /* There's only ever one segment override allowed per instruction.
5726 This instruction possibly has a legal segment override on the
5727 second operand, so copy the segment to where non-string
5728 instructions store it, allowing common code. */
5729 i.seg[0] = i.seg[1];
5730 }
40fb9820 5731 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5732 {
5733 if (i.seg[1] != NULL && i.seg[1] != &es)
5734 {
a87af027 5735 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5736 i.tm.name,
a87af027
JB		 5737 mem_op + 2,
5738 register_prefix);
29b0f896
AM		 5739 return 0;
5740 }
5741 }
5742 return 1;
5743}
5744
5745static int
543613e9 5746process_suffix (void)
29b0f896
AM		 5747{
5748 /* If matched instruction specifies an explicit instruction mnemonic
5749 suffix, use it. */
40fb9820
L		 5750 if (i.tm.opcode_modifier.size16)
5751 i.suffix = WORD_MNEM_SUFFIX;
5752 else if (i.tm.opcode_modifier.size32)
5753 i.suffix = LONG_MNEM_SUFFIX;
5754 else if (i.tm.opcode_modifier.size64)
5755 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5756 else if (i.reg_operands)
5757 {
5758 /* If there's no instruction mnemonic suffix we try to invent one
5759 based on register operands. */
5760 if (!i.suffix)
5761 {
5762 /* We take i.suffix from the last register operand specified,
5763 Destination register type is more significant than source
381d071f
L		 5764 register type. crc32 in SSE4.2 prefers source register
5765 type. */
5766 if (i.tm.base_opcode == 0xf20f38f1)
5767 {
dc821c5f 5768 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5769 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5770 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5771 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5772 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5773 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5774 }
9344ff29 5775 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5776 {
dc821c5f 5777 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5778 i.suffix = BYTE_MNEM_SUFFIX;
5779 }
381d071f
L		 5780
5781 if (!i.suffix)
5782 {
5783 int op;
5784
20592a94
L		 5785 if (i.tm.base_opcode == 0xf20f38f1
5786 || i.tm.base_opcode == 0xf20f38f0)
5787 {
5788 /* We have to know the operand size for crc32. */
5789 as_bad (_("ambiguous memory operand size for `%s`"),
5790 i.tm.name);
5791 return 0;
5792 }
5793
381d071f 5794 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5795 if (!i.tm.operand_types[op].bitfield.inoutportreg
5796 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5797 {
8819ada6
JB		 5798 if (!i.types[op].bitfield.reg)
5799 continue;
5800 if (i.types[op].bitfield.byte)
5801 i.suffix = BYTE_MNEM_SUFFIX;
5802 else if (i.types[op].bitfield.word)
5803 i.suffix = WORD_MNEM_SUFFIX;
5804 else if (i.types[op].bitfield.dword)
5805 i.suffix = LONG_MNEM_SUFFIX;
5806 else if (i.types[op].bitfield.qword)
5807 i.suffix = QWORD_MNEM_SUFFIX;
5808 else
5809 continue;
5810 break;
381d071f
L		 5811 }
5812 }
29b0f896
AM		 5813 }
5814 else if (i.suffix == BYTE_MNEM_SUFFIX)
5815 {
2eb952a4
L		 5816 if (intel_syntax
5817 && i.tm.opcode_modifier.ignoresize
5818 && i.tm.opcode_modifier.no_bsuf)
5819 i.suffix = 0;
5820 else if (!check_byte_reg ())
29b0f896
AM		 5821 return 0;
5822 }
5823 else if (i.suffix == LONG_MNEM_SUFFIX)
5824 {
2eb952a4
L		 5825 if (intel_syntax
5826 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5827 && i.tm.opcode_modifier.no_lsuf
5828 && !i.tm.opcode_modifier.todword
5829 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5830 i.suffix = 0;
5831 else if (!check_long_reg ())
29b0f896
AM		 5832 return 0;
5833 }
5834 else if (i.suffix == QWORD_MNEM_SUFFIX)
5835 {
955e1e6a
L		 5836 if (intel_syntax
5837 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5838 && i.tm.opcode_modifier.no_qsuf
5839 && !i.tm.opcode_modifier.todword
5840 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5841 i.suffix = 0;
5842 else if (!check_qword_reg ())
29b0f896
AM		 5843 return 0;
5844 }
5845 else if (i.suffix == WORD_MNEM_SUFFIX)
5846 {
2eb952a4
L		 5847 if (intel_syntax
5848 && i.tm.opcode_modifier.ignoresize
5849 && i.tm.opcode_modifier.no_wsuf)
5850 i.suffix = 0;
5851 else if (!check_word_reg ())
29b0f896
AM		 5852 return 0;
5853 }
40fb9820 5854 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5855 /* Do nothing if the instruction is going to ignore the prefix. */
5856 ;
5857 else
5858 abort ();
5859 }
40fb9820 5860 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5861 && !i.suffix
5862 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5863 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5864 {
5865 i.suffix = stackop_size;
5866 }
9306ca4a
JB		 5867 else if (intel_syntax
5868 && !i.suffix
40fb9820
L		 5869 && (i.tm.operand_types[0].bitfield.jumpabsolute
5870 || i.tm.opcode_modifier.jumpbyte
5871 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5872 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5873 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5874 {
5875 switch (flag_code)
5876 {
5877 case CODE_64BIT:
40fb9820 5878 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5879 {
5880 i.suffix = QWORD_MNEM_SUFFIX;
5881 break;
5882 }
1a0670f3 5883 /* Fall through. */
9306ca4a 5884 case CODE_32BIT:
40fb9820 5885 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5886 i.suffix = LONG_MNEM_SUFFIX;
5887 break;
5888 case CODE_16BIT:
40fb9820 5889 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5890 i.suffix = WORD_MNEM_SUFFIX;
5891 break;
5892 }
5893 }
252b5132 5894
9306ca4a 5895 if (!i.suffix)
29b0f896 5896 {
9306ca4a
JB		 5897 if (!intel_syntax)
5898 {
40fb9820 5899 if (i.tm.opcode_modifier.w)
9306ca4a 5900 {
4eed87de
AM		 5901 as_bad (_("no instruction mnemonic suffix given and "
5902 "no register operands; can't size instruction"));
9306ca4a
JB		 5903 return 0;
5904 }
5905 }
5906 else
5907 {
40fb9820 5908 unsigned int suffixes;
7ab9ffdd 5909
40fb9820
L		 5910 suffixes = !i.tm.opcode_modifier.no_bsuf;
5911 if (!i.tm.opcode_modifier.no_wsuf)
5912 suffixes |= 1 << 1;
5913 if (!i.tm.opcode_modifier.no_lsuf)
5914 suffixes |= 1 << 2;
fc4adea1 5915 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5916 suffixes |= 1 << 3;
5917 if (!i.tm.opcode_modifier.no_ssuf)
5918 suffixes |= 1 << 4;
c2b9da16 5919 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5920 suffixes |= 1 << 5;
5921
5922 /* There are more than suffix matches. */
5923 if (i.tm.opcode_modifier.w
9306ca4a 5924 || ((suffixes & (suffixes - 1))
40fb9820
L		 5925 && !i.tm.opcode_modifier.defaultsize
5926 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5927 {
5928 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5929 return 0;
5930 }
5931 }
29b0f896 5932 }
252b5132 5933
d2224064
JB		 5934 /* Change the opcode based on the operand size given by i.suffix. */
5935 switch (i.suffix)
29b0f896 5936 {
d2224064
JB		 5937 /* Size floating point instruction. */
5938 case LONG_MNEM_SUFFIX:
5939 if (i.tm.opcode_modifier.floatmf)
5940 {
5941 i.tm.base_opcode ^= 4;
5942 break;
5943 }
5944 /* fall through */
5945 case WORD_MNEM_SUFFIX:
5946 case QWORD_MNEM_SUFFIX:
29b0f896 5947 /* It's not a byte, select word/dword operation. */
40fb9820 5948 if (i.tm.opcode_modifier.w)
29b0f896 5949 {
40fb9820 5950 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5951 i.tm.base_opcode |= 8;
5952 else
5953 i.tm.base_opcode |= 1;
5954 }
d2224064
JB		 5955 /* fall through */
5956 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 5957 /* Now select between word & dword operations via the operand
5958 size prefix, except for instructions that will ignore this
5959 prefix anyway. */
ca61edf2 5960 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5961 {
ca61edf2
L		 5962 /* The address size override prefix changes the size of the
5963 first operand. */
40fb9820 5964 if ((flag_code == CODE_32BIT
dc821c5f 5965 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5966 || (flag_code != CODE_32BIT
dc821c5f 5967 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5968 if (!add_prefix (ADDR_PREFIX_OPCODE))
5969 return 0;
5970 }
5971 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 5972 && !i.tm.opcode_modifier.ignoresize
5973 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5974 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5975 || (flag_code == CODE_64BIT
40fb9820 5976 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5977 {
5978 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5979
40fb9820 5980 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5981 prefix = ADDR_PREFIX_OPCODE;
252b5132 5982
29b0f896
AM		 5983 if (!add_prefix (prefix))
5984 return 0;
24eab124 5985 }
252b5132 5986
29b0f896
AM		 5987 /* Set mode64 for an operand. */
5988 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5989 && flag_code == CODE_64BIT
d2224064 5990 && !i.tm.opcode_modifier.norex64
46e883c5 5991 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 5992 need rex64. */
5993 && ! (i.operands == 2
5994 && i.tm.base_opcode == 0x90
5995 && i.tm.extension_opcode == None
5996 && operand_type_equal (&i.types [0], &acc64)
5997 && operand_type_equal (&i.types [1], &acc64)))
5998 i.rex |= REX_W;
3e73aa7c 5999
d2224064 6000 break;
29b0f896 6001 }
7ecd2f8b 6002
29b0f896
AM		 6003 return 1;
6004}
3e73aa7c 6005
29b0f896 6006static int
543613e9 6007check_byte_reg (void)
29b0f896
AM		 6008{
6009 int op;
543613e9 6010
29b0f896
AM		 6011 for (op = i.operands; --op >= 0;)
6012 {
dc821c5f
JB		 6013 /* Skip non-register operands. */
6014 if (!i.types[op].bitfield.reg)
6015 continue;
6016
29b0f896
AM		 6017 /* If this is an eight bit register, it's OK. If it's the 16 or
6018 32 bit version of an eight bit register, we will just use the
6019 low portion, and that's OK too. */
dc821c5f 6020 if (i.types[op].bitfield.byte)
29b0f896
AM		 6021 continue;
6022
5a819eb9
JB		 6023 /* I/O port address operands are OK too. */
6024 if (i.tm.operand_types[op].bitfield.inoutportreg)
6025 continue;
6026
9344ff29
L		 6027 /* crc32 doesn't generate this warning. */
6028 if (i.tm.base_opcode == 0xf20f38f0)
6029 continue;
6030
dc821c5f
JB		 6031 if ((i.types[op].bitfield.word
6032 || i.types[op].bitfield.dword
6033 || i.types[op].bitfield.qword)
5a819eb9
JB		 6034 && i.op[op].regs->reg_num < 4
6035 /* Prohibit these changes in 64bit mode, since the lowering
6036 would be more complicated. */
6037 && flag_code != CODE_64BIT)
29b0f896 6038 {
29b0f896 6039#if REGISTER_WARNINGS
5a819eb9 6040 if (!quiet_warnings)
a540244d
L		 6041 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6042 register_prefix,
dc821c5f 6043 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6044 ? REGNAM_AL - REGNAM_AX
6045 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6046 register_prefix,
29b0f896
AM		 6047 i.op[op].regs->reg_name,
6048 i.suffix);
6049#endif
6050 continue;
6051 }
6052 /* Any other register is bad. */
dc821c5f 6053 if (i.types[op].bitfield.reg
40fb9820 6054 || i.types[op].bitfield.regmmx
1b54b8d7 6055 || i.types[op].bitfield.regsimd
40fb9820
L		 6056 || i.types[op].bitfield.sreg2
6057 || i.types[op].bitfield.sreg3
6058 || i.types[op].bitfield.control
6059 || i.types[op].bitfield.debug
ca0d63fe 6060 || i.types[op].bitfield.test)
29b0f896 6061 {
a540244d
L		 6062 as_bad (_("`%s%s' not allowed with `%s%c'"),
6063 register_prefix,
29b0f896
AM		 6064 i.op[op].regs->reg_name,
6065 i.tm.name,
6066 i.suffix);
6067 return 0;
6068 }
6069 }
6070 return 1;
6071}
6072
6073static int
e3bb37b5 6074check_long_reg (void)
29b0f896
AM		 6075{
6076 int op;
6077
6078 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6079 /* Skip non-register operands. */
6080 if (!i.types[op].bitfield.reg)
6081 continue;
29b0f896
AM		 6082 /* Reject eight bit registers, except where the template requires
6083 them. (eg. movzb) */
dc821c5f
JB		 6084 else if (i.types[op].bitfield.byte
6085 && (i.tm.operand_types[op].bitfield.reg
6086 || i.tm.operand_types[op].bitfield.acc)
6087 && (i.tm.operand_types[op].bitfield.word
6088 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6089 {
a540244d
L		 6090 as_bad (_("`%s%s' not allowed with `%s%c'"),
6091 register_prefix,
29b0f896
AM		 6092 i.op[op].regs->reg_name,
6093 i.tm.name,
6094 i.suffix);
6095 return 0;
6096 }
e4630f71 6097 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6098 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6099 && i.types[op].bitfield.word
6100 && (i.tm.operand_types[op].bitfield.reg
6101 || i.tm.operand_types[op].bitfield.acc)
6102 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6103 {
6104 /* Prohibit these changes in the 64bit mode, since the
6105 lowering is more complicated. */
6106 if (flag_code == CODE_64BIT)
252b5132 6107 {
2b5d6a91 6108 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6109 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6110 i.suffix);
6111 return 0;
252b5132 6112 }
29b0f896 6113#if REGISTER_WARNINGS
cecf1424
JB		 6114 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6115 register_prefix,
6116 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6117 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6118#endif
252b5132 6119 }
e4630f71 6120 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6121 else if (i.types[op].bitfield.qword
6122 && (i.tm.operand_types[op].bitfield.reg
6123 || i.tm.operand_types[op].bitfield.acc)
6124 && i.tm.operand_types[op].bitfield.dword)
252b5132 6125 {
34828aad 6126 if (intel_syntax
ca61edf2 6127 && i.tm.opcode_modifier.toqword
1b54b8d7 6128 && !i.types[0].bitfield.regsimd)
34828aad 6129 {
ca61edf2 6130 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6131 i.suffix = QWORD_MNEM_SUFFIX;
6132 }
6133 else
6134 {
2b5d6a91 6135 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6136 register_prefix, i.op[op].regs->reg_name,
6137 i.suffix);
6138 return 0;
6139 }
29b0f896
AM		 6140 }
6141 return 1;
6142}
252b5132 6143
29b0f896 6144static int
e3bb37b5 6145check_qword_reg (void)
29b0f896
AM		 6146{
6147 int op;
252b5132 6148
29b0f896 6149 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6150 /* Skip non-register operands. */
6151 if (!i.types[op].bitfield.reg)
6152 continue;
29b0f896
AM		 6153 /* Reject eight bit registers, except where the template requires
6154 them. (eg. movzb) */
dc821c5f
JB		 6155 else if (i.types[op].bitfield.byte
6156 && (i.tm.operand_types[op].bitfield.reg
6157 || i.tm.operand_types[op].bitfield.acc)
6158 && (i.tm.operand_types[op].bitfield.word
6159 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6160 {
a540244d
L		 6161 as_bad (_("`%s%s' not allowed with `%s%c'"),
6162 register_prefix,
29b0f896
AM		 6163 i.op[op].regs->reg_name,
6164 i.tm.name,
6165 i.suffix);
6166 return 0;
6167 }
e4630f71 6168 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6169 else if ((i.types[op].bitfield.word
6170 || i.types[op].bitfield.dword)
6171 && (i.tm.operand_types[op].bitfield.reg
6172 || i.tm.operand_types[op].bitfield.acc)
6173 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6174 {
6175 /* Prohibit these changes in the 64bit mode, since the
6176 lowering is more complicated. */
34828aad 6177 if (intel_syntax
ca61edf2 6178 && i.tm.opcode_modifier.todword
1b54b8d7 6179 && !i.types[0].bitfield.regsimd)
34828aad 6180 {
ca61edf2 6181 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6182 i.suffix = LONG_MNEM_SUFFIX;
6183 }
6184 else
6185 {
2b5d6a91 6186 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6187 register_prefix, i.op[op].regs->reg_name,
6188 i.suffix);
6189 return 0;
6190 }
252b5132 6191 }
29b0f896
AM		 6192 return 1;
6193}
252b5132 6194
29b0f896 6195static int
e3bb37b5 6196check_word_reg (void)
29b0f896
AM		 6197{
6198 int op;
6199 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6200 /* Skip non-register operands. */
6201 if (!i.types[op].bitfield.reg)
6202 continue;
29b0f896
AM		 6203 /* Reject eight bit registers, except where the template requires
6204 them. (eg. movzb) */
dc821c5f
JB		 6205 else if (i.types[op].bitfield.byte
6206 && (i.tm.operand_types[op].bitfield.reg
6207 || i.tm.operand_types[op].bitfield.acc)
6208 && (i.tm.operand_types[op].bitfield.word
6209 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6210 {
a540244d
L		 6211 as_bad (_("`%s%s' not allowed with `%s%c'"),
6212 register_prefix,
29b0f896
AM		 6213 i.op[op].regs->reg_name,
6214 i.tm.name,
6215 i.suffix);
6216 return 0;
6217 }
e4630f71 6218 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6219 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6220 && (i.types[op].bitfield.dword
6221 || i.types[op].bitfield.qword)
6222 && (i.tm.operand_types[op].bitfield.reg
6223 || i.tm.operand_types[op].bitfield.acc)
6224 && i.tm.operand_types[op].bitfield.word)
252b5132 6225 {
29b0f896
AM		 6226 /* Prohibit these changes in the 64bit mode, since the
6227 lowering is more complicated. */
6228 if (flag_code == CODE_64BIT)
252b5132 6229 {
2b5d6a91 6230 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6231 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6232 i.suffix);
6233 return 0;
252b5132 6234 }
29b0f896 6235#if REGISTER_WARNINGS
cecf1424
JB		 6236 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6237 register_prefix,
6238 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6239 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6240#endif
6241 }
6242 return 1;
6243}
252b5132 6244
29b0f896 6245static int
40fb9820 6246update_imm (unsigned int j)
29b0f896 6247{
bc0844ae 6248 i386_operand_type overlap = i.types[j];
40fb9820
L		 6249 if ((overlap.bitfield.imm8
6250 || overlap.bitfield.imm8s
6251 || overlap.bitfield.imm16
6252 || overlap.bitfield.imm32
6253 || overlap.bitfield.imm32s
6254 || overlap.bitfield.imm64)
0dfbf9d7
L		 6255 && !operand_type_equal (&overlap, &imm8)
6256 && !operand_type_equal (&overlap, &imm8s)
6257 && !operand_type_equal (&overlap, &imm16)
6258 && !operand_type_equal (&overlap, &imm32)
6259 && !operand_type_equal (&overlap, &imm32s)
6260 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6261 {
6262 if (i.suffix)
6263 {
40fb9820
L		 6264 i386_operand_type temp;
6265
0dfbf9d7 6266 operand_type_set (&temp, 0);
7ab9ffdd 6267 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6268 {
6269 temp.bitfield.imm8 = overlap.bitfield.imm8;
6270 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6271 }
6272 else if (i.suffix == WORD_MNEM_SUFFIX)
6273 temp.bitfield.imm16 = overlap.bitfield.imm16;
6274 else if (i.suffix == QWORD_MNEM_SUFFIX)
6275 {
6276 temp.bitfield.imm64 = overlap.bitfield.imm64;
6277 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6278 }
6279 else
6280 temp.bitfield.imm32 = overlap.bitfield.imm32;
6281 overlap = temp;
29b0f896 6282 }
0dfbf9d7
L		 6283 else if (operand_type_equal (&overlap, &imm16_32_32s)
6284 || operand_type_equal (&overlap, &imm16_32)
6285 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6286 {
40fb9820 6287 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6288 overlap = imm16;
40fb9820 6289 else
65da13b5 6290 overlap = imm32s;
29b0f896 6291 }
0dfbf9d7
L		 6292 if (!operand_type_equal (&overlap, &imm8)
6293 && !operand_type_equal (&overlap, &imm8s)
6294 && !operand_type_equal (&overlap, &imm16)
6295 && !operand_type_equal (&overlap, &imm32)
6296 && !operand_type_equal (&overlap, &imm32s)
6297 && !operand_type_equal (&overlap, &imm64))
29b0f896 6298 {
4eed87de
AM		 6299 as_bad (_("no instruction mnemonic suffix given; "
6300 "can't determine immediate size"));
29b0f896
AM		 6301 return 0;
6302 }
6303 }
40fb9820 6304 i.types[j] = overlap;
29b0f896 6305
40fb9820
L		 6306 return 1;
6307}
6308
6309static int
6310finalize_imm (void)
6311{
bc0844ae 6312 unsigned int j, n;
29b0f896 6313
bc0844ae
L		 6314 /* Update the first 2 immediate operands. */
6315 n = i.operands > 2 ? 2 : i.operands;
6316 if (n)
6317 {
6318 for (j = 0; j < n; j++)
6319 if (update_imm (j) == 0)
6320 return 0;
40fb9820 6321
bc0844ae
L		 6322 /* The 3rd operand can't be immediate operand. */
6323 gas_assert (operand_type_check (i.types[2], imm) == 0);
6324 }
29b0f896
AM		 6325
6326 return 1;
6327}
6328
6329static int
e3bb37b5 6330process_operands (void)
29b0f896
AM		 6331{
6332 /* Default segment register this instruction will use for memory
6333 accesses. 0 means unknown. This is only for optimizing out
6334 unnecessary segment overrides. */
6335 const seg_entry *default_seg = 0;
6336
2426c15f 6337 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6338 {
91d6fa6a
NC		 6339 unsigned int dupl = i.operands;
6340 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6341 unsigned int j;
6342
c0f3af97 6343 /* The destination must be an xmm register. */
9c2799c2 6344 gas_assert (i.reg_operands
91d6fa6a 6345 && MAX_OPERANDS > dupl
7ab9ffdd 6346 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6347
1b54b8d7
JB		 6348 if (i.tm.operand_types[0].bitfield.acc
6349 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6350 {
8cd7925b 6351 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6352 {
6353 /* Keep xmm0 for instructions with VEX prefix and 3
6354 sources. */
1b54b8d7
JB		 6355 i.tm.operand_types[0].bitfield.acc = 0;
6356 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6357 goto duplicate;
6358 }
e2ec9d29 6359 else
c0f3af97
L		 6360 {
6361 /* We remove the first xmm0 and keep the number of
6362 operands unchanged, which in fact duplicates the
6363 destination. */
6364 for (j = 1; j < i.operands; j++)
6365 {
6366 i.op[j - 1] = i.op[j];
6367 i.types[j - 1] = i.types[j];
6368 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6369 }
6370 }
6371 }
6372 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6373 {
91d6fa6a 6374 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6375 && (i.tm.opcode_modifier.vexsources
6376 == VEX3SOURCES));
c0f3af97
L		 6377
6378 /* Add the implicit xmm0 for instructions with VEX prefix
6379 and 3 sources. */
6380 for (j = i.operands; j > 0; j--)
6381 {
6382 i.op[j] = i.op[j - 1];
6383 i.types[j] = i.types[j - 1];
6384 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6385 }
6386 i.op[0].regs
6387 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6388 i.types[0] = regxmm;
c0f3af97
L		 6389 i.tm.operand_types[0] = regxmm;
6390
6391 i.operands += 2;
6392 i.reg_operands += 2;
6393 i.tm.operands += 2;
6394
91d6fa6a 6395 dupl++;
c0f3af97 6396 dest++;
91d6fa6a
NC		 6397 i.op[dupl] = i.op[dest];
6398 i.types[dupl] = i.types[dest];
6399 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6400 }
c0f3af97
L		 6401 else
6402 {
6403duplicate:
6404 i.operands++;
6405 i.reg_operands++;
6406 i.tm.operands++;
6407
91d6fa6a
NC		 6408 i.op[dupl] = i.op[dest];
6409 i.types[dupl] = i.types[dest];
6410 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6411 }
6412
6413 if (i.tm.opcode_modifier.immext)
6414 process_immext ();
6415 }
1b54b8d7
JB		 6416 else if (i.tm.operand_types[0].bitfield.acc
6417 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6418 {
6419 unsigned int j;
6420
9fcfb3d7
L		 6421 for (j = 1; j < i.operands; j++)
6422 {
6423 i.op[j - 1] = i.op[j];
6424 i.types[j - 1] = i.types[j];
6425
6426 /* We need to adjust fields in i.tm since they are used by
6427 build_modrm_byte. */
6428 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6429 }
6430
e2ec9d29
L		 6431 i.operands--;
6432 i.reg_operands--;
e2ec9d29
L		 6433 i.tm.operands--;
6434 }
920d2ddc
IT		 6435 else if (i.tm.opcode_modifier.implicitquadgroup)
6436 {
a477a8c4
JB		 6437 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6438
920d2ddc 6439 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6440 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6441 regnum = register_number (i.op[1].regs);
6442 first_reg_in_group = regnum & ~3;
6443 last_reg_in_group = first_reg_in_group + 3;
6444 if (regnum != first_reg_in_group)
6445 as_warn (_("source register `%s%s' implicitly denotes"
6446 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6447 register_prefix, i.op[1].regs->reg_name,
6448 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6449 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6450 i.tm.name);
6451 }
e2ec9d29
L		 6452 else if (i.tm.opcode_modifier.regkludge)
6453 {
6454 /* The imul $imm, %reg instruction is converted into
6455 imul $imm, %reg, %reg, and the clr %reg instruction
6456 is converted into xor %reg, %reg. */
6457
6458 unsigned int first_reg_op;
6459
6460 if (operand_type_check (i.types[0], reg))
6461 first_reg_op = 0;
6462 else
6463 first_reg_op = 1;
6464 /* Pretend we saw the extra register operand. */
9c2799c2 6465 gas_assert (i.reg_operands == 1
7ab9ffdd 6466 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6467 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6468 i.types[first_reg_op + 1] = i.types[first_reg_op];
6469 i.operands++;
6470 i.reg_operands++;
29b0f896
AM		 6471 }
6472
40fb9820 6473 if (i.tm.opcode_modifier.shortform)
29b0f896 6474 {
40fb9820
L		 6475 if (i.types[0].bitfield.sreg2
6476 || i.types[0].bitfield.sreg3)
29b0f896 6477 {
4eed87de
AM		 6478 if (i.tm.base_opcode == POP_SEG_SHORT
6479 && i.op[0].regs->reg_num == 1)
29b0f896 6480 {
a87af027 6481 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6482 return 0;
29b0f896 6483 }
4eed87de
AM		 6484 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6485 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6486 i.rex |= REX_B;
4eed87de
AM		 6487 }
6488 else
6489 {
7ab9ffdd 6490 /* The register or float register operand is in operand
85f10a01 6491 0 or 1. */
40fb9820 6492 unsigned int op;
7ab9ffdd 6493
ca0d63fe 6494 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6495 || operand_type_check (i.types[0], reg))
6496 op = 0;
6497 else
6498 op = 1;
4eed87de
AM		 6499 /* Register goes in low 3 bits of opcode. */
6500 i.tm.base_opcode |= i.op[op].regs->reg_num;
6501 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6502 i.rex |= REX_B;
40fb9820 6503 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6504 {
4eed87de
AM		 6505 /* Warn about some common errors, but press on regardless.
6506 The first case can be generated by gcc (<= 2.8.1). */
6507 if (i.operands == 2)
6508 {
6509 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6510 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6511 register_prefix, i.op[!intel_syntax].regs->reg_name,
6512 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6513 }
6514 else
6515 {
6516 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6517 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6518 register_prefix, i.op[0].regs->reg_name);
4eed87de 6519 }
29b0f896
AM		 6520 }
6521 }
6522 }
40fb9820 6523 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6524 {
6525 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6526 must be put into the modrm byte). Now, we make the modrm and
6527 index base bytes based on all the info we've collected. */
29b0f896
AM		 6528
6529 default_seg = build_modrm_byte ();
6530 }
8a2ed489 6531 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6532 {
6533 default_seg = &ds;
6534 }
40fb9820 6535 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6536 {
6537 /* For the string instructions that allow a segment override
6538 on one of their operands, the default segment is ds. */
6539 default_seg = &ds;
6540 }
6541
75178d9d
L		 6542 if (i.tm.base_opcode == 0x8d /* lea */
6543 && i.seg[0]
6544 && !quiet_warnings)
30123838 6545 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6546
6547 /* If a segment was explicitly specified, and the specified segment
6548 is not the default, use an opcode prefix to select it. If we
6549 never figured out what the default segment is, then default_seg
6550 will be zero at this point, and the specified segment prefix will
6551 always be used. */
29b0f896
AM		 6552 if ((i.seg[0]) && (i.seg[0] != default_seg))
6553 {
6554 if (!add_prefix (i.seg[0]->seg_prefix))
6555 return 0;
6556 }
6557 return 1;
6558}
6559
6560static const seg_entry *
e3bb37b5 6561build_modrm_byte (void)
29b0f896
AM		 6562{
6563 const seg_entry *default_seg = 0;
c0f3af97 6564 unsigned int source, dest;
8cd7925b 6565 int vex_3_sources;
c0f3af97
L		 6566
6567 /* The first operand of instructions with VEX prefix and 3 sources
6568 must be VEX_Imm4. */
8cd7925b 6569 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6570 if (vex_3_sources)
6571 {
91d6fa6a 6572 unsigned int nds, reg_slot;
4c2c6516 6573 expressionS *exp;
c0f3af97 6574
922d8de8 6575 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6576 && i.tm.opcode_modifier.immext)
6577 {
6578 dest = i.operands - 2;
6579 gas_assert (dest == 3);
6580 }
922d8de8 6581 else
a683cc34 6582 dest = i.operands - 1;
c0f3af97 6583 nds = dest - 1;
922d8de8 6584
a683cc34
SP		 6585 /* There are 2 kinds of instructions:
6586 1. 5 operands: 4 register operands or 3 register operands
6587 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6588 VexW0 or VexW1. The destination must be either XMM, YMM or
6589 ZMM register.
a683cc34
SP		 6590 2. 4 operands: 4 register operands or 3 register operands
6591 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6592 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6593 || (i.reg_operands == 3 && i.mem_operands == 1))
6594 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6595 && (i.tm.opcode_modifier.veximmext
6596 || (i.imm_operands == 1
6597 && i.types[0].bitfield.vec_imm4
6598 && (i.tm.opcode_modifier.vexw == VEXW0
6599 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6600 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6601
6602 if (i.imm_operands == 0)
6603 {
6604 /* When there is no immediate operand, generate an 8bit
6605 immediate operand to encode the first operand. */
6606 exp = &im_expressions[i.imm_operands++];
6607 i.op[i.operands].imms = exp;
6608 i.types[i.operands] = imm8;
6609 i.operands++;
6610 /* If VexW1 is set, the first operand is the source and
6611 the second operand is encoded in the immediate operand. */
6612 if (i.tm.opcode_modifier.vexw == VEXW1)
6613 {
6614 source = 0;
6615 reg_slot = 1;
6616 }
6617 else
6618 {
6619 source = 1;
6620 reg_slot = 0;
6621 }
6622
6623 /* FMA swaps REG and NDS. */
6624 if (i.tm.cpu_flags.bitfield.cpufma)
6625 {
6626 unsigned int tmp;
6627 tmp = reg_slot;
6628 reg_slot = nds;
6629 nds = tmp;
6630 }
6631
10c17abd 6632 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6633 exp->X_op = O_constant;
4c692bc7 6634 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6635 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6636 }
922d8de8 6637 else
a683cc34
SP		 6638 {
6639 unsigned int imm_slot;
6640
6641 if (i.tm.opcode_modifier.vexw == VEXW0)
6642 {
6643 /* If VexW0 is set, the third operand is the source and
6644 the second operand is encoded in the immediate
6645 operand. */
6646 source = 2;
6647 reg_slot = 1;
6648 }
6649 else
6650 {
6651 /* VexW1 is set, the second operand is the source and
6652 the third operand is encoded in the immediate
6653 operand. */
6654 source = 1;
6655 reg_slot = 2;
6656 }
6657
6658 if (i.tm.opcode_modifier.immext)
6659 {
33eaf5de 6660 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6661 operand. */
6662 imm_slot = i.operands - 1;
6663 source--;
6664 reg_slot--;
6665 }
6666 else
6667 {
6668 imm_slot = 0;
6669
6670 /* Turn on Imm8 so that output_imm will generate it. */
6671 i.types[imm_slot].bitfield.imm8 = 1;
6672 }
6673
10c17abd 6674 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6675 i.op[imm_slot].imms->X_add_number
4c692bc7 6676 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6677 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6678 }
6679
10c17abd 6680 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6681 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6682 }
6683 else
6684 source = dest = 0;
29b0f896
AM		 6685
6686 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6687 implicit registers do not count. If there are 3 register
6688 operands, it must be a instruction with VexNDS. For a
6689 instruction with VexNDD, the destination register is encoded
6690 in VEX prefix. If there are 4 register operands, it must be
6691 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6692 if (i.mem_operands == 0
6693 && ((i.reg_operands == 2
2426c15f 6694 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6695 || (i.reg_operands == 3
2426c15f 6696 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6697 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6698 {
cab737b9
L		 6699 switch (i.operands)
6700 {
6701 case 2:
6702 source = 0;
6703 break;
6704 case 3:
c81128dc
L		 6705 /* When there are 3 operands, one of them may be immediate,
6706 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6707 the first operand must be shift count register (cl) or it
6708 is an instruction with VexNDS. */
9c2799c2 6709 gas_assert (i.imm_operands == 1
7ab9ffdd 6710 || (i.imm_operands == 0
2426c15f 6711 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6712 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6713 if (operand_type_check (i.types[0], imm)
6714 || i.types[0].bitfield.shiftcount)
6715 source = 1;
6716 else
6717 source = 0;
cab737b9
L		 6718 break;
6719 case 4:
368d64cc
L		 6720 /* When there are 4 operands, the first two must be 8bit
6721 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6722 one.
6723
6724 For instructions with VexNDS, if the first operand
6725 an imm8, the source operand is the 2nd one. If the last
6726 operand is imm8, the source operand is the first one. */
9c2799c2 6727 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6728 && i.types[0].bitfield.imm8
6729 && i.types[1].bitfield.imm8)
2426c15f 6730 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6731 && i.imm_operands == 1
6732 && (i.types[0].bitfield.imm8
43234a1e
L		 6733 || i.types[i.operands - 1].bitfield.imm8
6734 || i.rounding)));
9f2670f2
L		 6735 if (i.imm_operands == 2)
6736 source = 2;
6737 else
c0f3af97
L		 6738 {
6739 if (i.types[0].bitfield.imm8)
6740 source = 1;
6741 else
6742 source = 0;
6743 }
c0f3af97
L		 6744 break;
6745 case 5:
e771e7c9 6746 if (is_evex_encoding (&i.tm))
43234a1e
L		 6747 {
6748 /* For EVEX instructions, when there are 5 operands, the
6749 first one must be immediate operand. If the second one
6750 is immediate operand, the source operand is the 3th
6751 one. If the last one is immediate operand, the source
6752 operand is the 2nd one. */
6753 gas_assert (i.imm_operands == 2
6754 && i.tm.opcode_modifier.sae
6755 && operand_type_check (i.types[0], imm));
6756 if (operand_type_check (i.types[1], imm))
6757 source = 2;
6758 else if (operand_type_check (i.types[4], imm))
6759 source = 1;
6760 else
6761 abort ();
6762 }
cab737b9
L		 6763 break;
6764 default:
6765 abort ();
6766 }
6767
c0f3af97
L		 6768 if (!vex_3_sources)
6769 {
6770 dest = source + 1;
6771
43234a1e
L		 6772 /* RC/SAE operand could be between DEST and SRC. That happens
6773 when one operand is GPR and the other one is XMM/YMM/ZMM
6774 register. */
6775 if (i.rounding && i.rounding->operand == (int) dest)
6776 dest++;
6777
2426c15f 6778 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6779 {
43234a1e 6780 /* For instructions with VexNDS, the register-only source
c5d0745b 6781 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6782 register. It is encoded in VEX prefix. We need to
6783 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6784
6785 i386_operand_type op;
6786 unsigned int vvvv;
6787
6788 /* Check register-only source operand when two source
6789 operands are swapped. */
6790 if (!i.tm.operand_types[source].bitfield.baseindex
6791 && i.tm.operand_types[dest].bitfield.baseindex)
6792 {
6793 vvvv = source;
6794 source = dest;
6795 }
6796 else
6797 vvvv = dest;
6798
6799 op = i.tm.operand_types[vvvv];
fa99fab2 6800 op.bitfield.regmem = 0;
c0f3af97 6801 if ((dest + 1) >= i.operands
dc821c5f
JB		 6802 || ((!op.bitfield.reg
6803 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6804 && !op.bitfield.regsimd
43234a1e 6805 && !operand_type_equal (&op, &regmask)))
c0f3af97 6806 abort ();
f12dc422 6807 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6808 dest++;
6809 }
6810 }
29b0f896
AM		 6811
6812 i.rm.mode = 3;
6813 /* One of the register operands will be encoded in the i.tm.reg
6814 field, the other in the combined i.tm.mode and i.tm.regmem
6815 fields. If no form of this instruction supports a memory
6816 destination operand, then we assume the source operand may
6817 sometimes be a memory operand and so we need to store the
6818 destination in the i.rm.reg field. */
40fb9820
L		 6819 if (!i.tm.operand_types[dest].bitfield.regmem
6820 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6821 {
6822 i.rm.reg = i.op[dest].regs->reg_num;
6823 i.rm.regmem = i.op[source].regs->reg_num;
6824 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6825 i.rex |= REX_R;
43234a1e
L		 6826 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6827 i.vrex |= REX_R;
29b0f896 6828 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6829 i.rex |= REX_B;
43234a1e
L		 6830 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6831 i.vrex |= REX_B;
29b0f896
AM		 6832 }
6833 else
6834 {
6835 i.rm.reg = i.op[source].regs->reg_num;
6836 i.rm.regmem = i.op[dest].regs->reg_num;
6837 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6838 i.rex |= REX_B;
43234a1e
L		 6839 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6840 i.vrex |= REX_B;
29b0f896 6841 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6842 i.rex |= REX_R;
43234a1e
L		 6843 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6844 i.vrex |= REX_R;
29b0f896 6845 }
161a04f6 6846 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6847 {
40fb9820
L		 6848 if (!i.types[0].bitfield.control
6849 && !i.types[1].bitfield.control)
c4a530c5 6850 abort ();
161a04f6 6851 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6852 add_prefix (LOCK_PREFIX_OPCODE);
6853 }
29b0f896
AM		 6854 }
6855 else
6856 { /* If it's not 2 reg operands... */
c0f3af97
L		 6857 unsigned int mem;
6858
29b0f896
AM		 6859 if (i.mem_operands)
6860 {
6861 unsigned int fake_zero_displacement = 0;
99018f42 6862 unsigned int op;
4eed87de 6863
7ab9ffdd
L		 6864 for (op = 0; op < i.operands; op++)
6865 if (operand_type_check (i.types[op], anymem))
6866 break;
7ab9ffdd 6867 gas_assert (op < i.operands);
29b0f896 6868
6c30d220
L		 6869 if (i.tm.opcode_modifier.vecsib)
6870 {
6871 if (i.index_reg->reg_num == RegEiz
6872 || i.index_reg->reg_num == RegRiz)
6873 abort ();
6874
6875 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6876 if (!i.base_reg)
6877 {
6878 i.sib.base = NO_BASE_REGISTER;
6879 i.sib.scale = i.log2_scale_factor;
6880 i.types[op].bitfield.disp8 = 0;
6881 i.types[op].bitfield.disp16 = 0;
6882 i.types[op].bitfield.disp64 = 0;
43083a50 6883 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6884 {
6885 /* Must be 32 bit */
6886 i.types[op].bitfield.disp32 = 1;
6887 i.types[op].bitfield.disp32s = 0;
6888 }
6889 else
6890 {
6891 i.types[op].bitfield.disp32 = 0;
6892 i.types[op].bitfield.disp32s = 1;
6893 }
6894 }
6895 i.sib.index = i.index_reg->reg_num;
6896 if ((i.index_reg->reg_flags & RegRex) != 0)
6897 i.rex |= REX_X;
43234a1e
L		 6898 if ((i.index_reg->reg_flags & RegVRex) != 0)
6899 i.vrex |= REX_X;
6c30d220
L		 6900 }
6901
29b0f896
AM		 6902 default_seg = &ds;
6903
6904 if (i.base_reg == 0)
6905 {
6906 i.rm.mode = 0;
6907 if (!i.disp_operands)
9bb129e8 6908 fake_zero_displacement = 1;
29b0f896
AM		 6909 if (i.index_reg == 0)
6910 {
73053c1f
JB		 6911 i386_operand_type newdisp;
6912
6c30d220 6913 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6914 /* Operand is just <disp> */
20f0a1fc 6915 if (flag_code == CODE_64BIT)
29b0f896
AM		 6916 {
6917 /* 64bit mode overwrites the 32bit absolute
6918 addressing by RIP relative addressing and
6919 absolute addressing is encoded by one of the
6920 redundant SIB forms. */
6921 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6922 i.sib.base = NO_BASE_REGISTER;
6923 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6924 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6925 }
fc225355
L		 6926 else if ((flag_code == CODE_16BIT)
6927 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6928 {
6929 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6930 newdisp = disp16;
20f0a1fc
NC		 6931 }
6932 else
6933 {
6934 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6935 newdisp = disp32;
29b0f896 6936 }
73053c1f
JB		 6937 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6938 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6939 }
6c30d220 6940 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6941 {
6c30d220 6942 /* !i.base_reg && i.index_reg */
db51cc60
L		 6943 if (i.index_reg->reg_num == RegEiz
6944 || i.index_reg->reg_num == RegRiz)
6945 i.sib.index = NO_INDEX_REGISTER;
6946 else
6947 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6948 i.sib.base = NO_BASE_REGISTER;
6949 i.sib.scale = i.log2_scale_factor;
6950 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6951 i.types[op].bitfield.disp8 = 0;
6952 i.types[op].bitfield.disp16 = 0;
6953 i.types[op].bitfield.disp64 = 0;
43083a50 6954 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6955 {
6956 /* Must be 32 bit */
6957 i.types[op].bitfield.disp32 = 1;
6958 i.types[op].bitfield.disp32s = 0;
6959 }
29b0f896 6960 else
40fb9820
L		 6961 {
6962 i.types[op].bitfield.disp32 = 0;
6963 i.types[op].bitfield.disp32s = 1;
6964 }
29b0f896 6965 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6966 i.rex |= REX_X;
29b0f896
AM		 6967 }
6968 }
6969 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6970 else if (i.base_reg->reg_num == RegRip ||
6971 i.base_reg->reg_num == RegEip)
29b0f896 6972 {
6c30d220 6973 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6974 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6975 i.types[op].bitfield.disp8 = 0;
6976 i.types[op].bitfield.disp16 = 0;
6977 i.types[op].bitfield.disp32 = 0;
6978 i.types[op].bitfield.disp32s = 1;
6979 i.types[op].bitfield.disp64 = 0;
71903a11 6980 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6981 if (! i.disp_operands)
6982 fake_zero_displacement = 1;
29b0f896 6983 }
dc821c5f 6984 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6985 {
6c30d220 6986 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6987 switch (i.base_reg->reg_num)
6988 {
6989 case 3: /* (%bx) */
6990 if (i.index_reg == 0)
6991 i.rm.regmem = 7;
6992 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6993 i.rm.regmem = i.index_reg->reg_num - 6;
6994 break;
6995 case 5: /* (%bp) */
6996 default_seg = &ss;
6997 if (i.index_reg == 0)
6998 {
6999 i.rm.regmem = 6;
40fb9820 7000 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7001 {
7002 /* fake (%bp) into 0(%bp) */
b5014f7a 7003 i.types[op].bitfield.disp8 = 1;
252b5132 7004 fake_zero_displacement = 1;
29b0f896
AM		 7005 }
7006 }
7007 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7008 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7009 break;
7010 default: /* (%si) -> 4 or (%di) -> 5 */
7011 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7012 }
7013 i.rm.mode = mode_from_disp_size (i.types[op]);
7014 }
7015 else /* i.base_reg and 32/64 bit mode */
7016 {
7017 if (flag_code == CODE_64BIT
40fb9820
L		 7018 && operand_type_check (i.types[op], disp))
7019 {
73053c1f
JB		 7020 i.types[op].bitfield.disp16 = 0;
7021 i.types[op].bitfield.disp64 = 0;
40fb9820 7022 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7023 {
7024 i.types[op].bitfield.disp32 = 0;
7025 i.types[op].bitfield.disp32s = 1;
7026 }
40fb9820 7027 else
73053c1f
JB		 7028 {
7029 i.types[op].bitfield.disp32 = 1;
7030 i.types[op].bitfield.disp32s = 0;
7031 }
40fb9820 7032 }
20f0a1fc 7033
6c30d220
L		 7034 if (!i.tm.opcode_modifier.vecsib)
7035 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7036 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7037 i.rex |= REX_B;
29b0f896
AM		 7038 i.sib.base = i.base_reg->reg_num;
7039 /* x86-64 ignores REX prefix bit here to avoid decoder
7040 complications. */
848930b2
JB		 7041 if (!(i.base_reg->reg_flags & RegRex)
7042 && (i.base_reg->reg_num == EBP_REG_NUM
7043 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7044 default_seg = &ss;
848930b2 7045 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7046 {
848930b2 7047 fake_zero_displacement = 1;
b5014f7a 7048 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7049 }
7050 i.sib.scale = i.log2_scale_factor;
7051 if (i.index_reg == 0)
7052 {
6c30d220 7053 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7054 /* <disp>(%esp) becomes two byte modrm with no index
7055 register. We've already stored the code for esp
7056 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7057 Any base register besides %esp will not use the
7058 extra modrm byte. */
7059 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7060 }
6c30d220 7061 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7062 {
db51cc60
L		 7063 if (i.index_reg->reg_num == RegEiz
7064 || i.index_reg->reg_num == RegRiz)
7065 i.sib.index = NO_INDEX_REGISTER;
7066 else
7067 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7068 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7069 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7070 i.rex |= REX_X;
29b0f896 7071 }
67a4f2b7
AO		 7072
7073 if (i.disp_operands
7074 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7075 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7076 i.rm.mode = 0;
7077 else
a501d77e
L		 7078 {
7079 if (!fake_zero_displacement
7080 && !i.disp_operands
7081 && i.disp_encoding)
7082 {
7083 fake_zero_displacement = 1;
7084 if (i.disp_encoding == disp_encoding_8bit)
7085 i.types[op].bitfield.disp8 = 1;
7086 else
7087 i.types[op].bitfield.disp32 = 1;
7088 }
7089 i.rm.mode = mode_from_disp_size (i.types[op]);
7090 }
29b0f896 7091 }
252b5132 7092
29b0f896
AM		 7093 if (fake_zero_displacement)
7094 {
7095 /* Fakes a zero displacement assuming that i.types[op]
7096 holds the correct displacement size. */
7097 expressionS *exp;
7098
9c2799c2 7099 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7100 exp = &disp_expressions[i.disp_operands++];
7101 i.op[op].disps = exp;
7102 exp->X_op = O_constant;
7103 exp->X_add_number = 0;
7104 exp->X_add_symbol = (symbolS *) 0;
7105 exp->X_op_symbol = (symbolS *) 0;
7106 }
c0f3af97
L		 7107
7108 mem = op;
29b0f896 7109 }
c0f3af97
L		 7110 else
7111 mem = ~0;
252b5132 7112
8c43a48b 7113 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7114 {
7115 if (operand_type_check (i.types[0], imm))
7116 i.vex.register_specifier = NULL;
7117 else
7118 {
7119 /* VEX.vvvv encodes one of the sources when the first
7120 operand is not an immediate. */
1ef99a7b 7121 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7122 i.vex.register_specifier = i.op[0].regs;
7123 else
7124 i.vex.register_specifier = i.op[1].regs;
7125 }
7126
7127 /* Destination is a XMM register encoded in the ModRM.reg
7128 and VEX.R bit. */
7129 i.rm.reg = i.op[2].regs->reg_num;
7130 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7131 i.rex |= REX_R;
7132
7133 /* ModRM.rm and VEX.B encodes the other source. */
7134 if (!i.mem_operands)
7135 {
7136 i.rm.mode = 3;
7137
1ef99a7b 7138 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7139 i.rm.regmem = i.op[1].regs->reg_num;
7140 else
7141 i.rm.regmem = i.op[0].regs->reg_num;
7142
7143 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7144 i.rex |= REX_B;
7145 }
7146 }
2426c15f 7147 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7148 {
7149 i.vex.register_specifier = i.op[2].regs;
7150 if (!i.mem_operands)
7151 {
7152 i.rm.mode = 3;
7153 i.rm.regmem = i.op[1].regs->reg_num;
7154 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7155 i.rex |= REX_B;
7156 }
7157 }
29b0f896
AM		 7158 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7159 (if any) based on i.tm.extension_opcode. Again, we must be
7160 careful to make sure that segment/control/debug/test/MMX
7161 registers are coded into the i.rm.reg field. */
f88c9eb0 7162 else if (i.reg_operands)
29b0f896 7163 {
99018f42 7164 unsigned int op;
7ab9ffdd
L		 7165 unsigned int vex_reg = ~0;
7166
7167 for (op = 0; op < i.operands; op++)
dc821c5f 7168 if (i.types[op].bitfield.reg
7ab9ffdd 7169 || i.types[op].bitfield.regmmx
1b54b8d7 7170 || i.types[op].bitfield.regsimd
7e8b059b 7171 || i.types[op].bitfield.regbnd
43234a1e 7172 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7173 || i.types[op].bitfield.sreg2
7174 || i.types[op].bitfield.sreg3
7175 || i.types[op].bitfield.control
7176 || i.types[op].bitfield.debug
7177 || i.types[op].bitfield.test)
7178 break;
c0209578 7179
7ab9ffdd
L		 7180 if (vex_3_sources)
7181 op = dest;
2426c15f 7182 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7183 {
7184 /* For instructions with VexNDS, the register-only
7185 source operand is encoded in VEX prefix. */
7186 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7187
7ab9ffdd 7188 if (op > mem)
c0f3af97 7189 {
7ab9ffdd
L		 7190 vex_reg = op++;
7191 gas_assert (op < i.operands);
c0f3af97
L		 7192 }
7193 else
c0f3af97 7194 {
f12dc422
L		 7195 /* Check register-only source operand when two source
7196 operands are swapped. */
7197 if (!i.tm.operand_types[op].bitfield.baseindex
7198 && i.tm.operand_types[op + 1].bitfield.baseindex)
7199 {
7200 vex_reg = op;
7201 op += 2;
7202 gas_assert (mem == (vex_reg + 1)
7203 && op < i.operands);
7204 }
7205 else
7206 {
7207 vex_reg = op + 1;
7208 gas_assert (vex_reg < i.operands);
7209 }
c0f3af97 7210 }
7ab9ffdd 7211 }
2426c15f 7212 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7213 {
f12dc422 7214 /* For instructions with VexNDD, the register destination
7ab9ffdd 7215 is encoded in VEX prefix. */
f12dc422
L		 7216 if (i.mem_operands == 0)
7217 {
7218 /* There is no memory operand. */
7219 gas_assert ((op + 2) == i.operands);
7220 vex_reg = op + 1;
7221 }
7222 else
8d63c93e 7223 {
ed438a93
JB		 7224 /* There are only 2 non-immediate operands. */
7225 gas_assert (op < i.imm_operands + 2
7226 && i.operands == i.imm_operands + 2);
7227 vex_reg = i.imm_operands + 1;
f12dc422 7228 }
7ab9ffdd
L		 7229 }
7230 else
7231 gas_assert (op < i.operands);
99018f42 7232
7ab9ffdd
L		 7233 if (vex_reg != (unsigned int) ~0)
7234 {
f12dc422 7235 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7236
dc821c5f
JB		 7237 if ((!type->bitfield.reg
7238 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7239 && !type->bitfield.regsimd
43234a1e 7240 && !operand_type_equal (type, &regmask))
7ab9ffdd 7241 abort ();
f88c9eb0 7242
7ab9ffdd
L		 7243 i.vex.register_specifier = i.op[vex_reg].regs;
7244 }
7245
1b9f0c97
L		 7246 /* Don't set OP operand twice. */
7247 if (vex_reg != op)
7ab9ffdd 7248 {
1b9f0c97
L		 7249 /* If there is an extension opcode to put here, the
7250 register number must be put into the regmem field. */
7251 if (i.tm.extension_opcode != None)
7252 {
7253 i.rm.regmem = i.op[op].regs->reg_num;
7254 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7255 i.rex |= REX_B;
43234a1e
L		 7256 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7257 i.vrex |= REX_B;
1b9f0c97
L		 7258 }
7259 else
7260 {
7261 i.rm.reg = i.op[op].regs->reg_num;
7262 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7263 i.rex |= REX_R;
43234a1e
L		 7264 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7265 i.vrex |= REX_R;
1b9f0c97 7266 }
7ab9ffdd 7267 }
252b5132 7268
29b0f896
AM		 7269 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7270 must set it to 3 to indicate this is a register operand
7271 in the regmem field. */
7272 if (!i.mem_operands)
7273 i.rm.mode = 3;
7274 }
252b5132 7275
29b0f896 7276 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7277 if (i.tm.extension_opcode != None)
29b0f896
AM		 7278 i.rm.reg = i.tm.extension_opcode;
7279 }
7280 return default_seg;
7281}
252b5132 7282
29b0f896 7283static void
e3bb37b5 7284output_branch (void)
29b0f896
AM		 7285{
7286 char *p;
f8a5c266 7287 int size;
29b0f896
AM		 7288 int code16;
7289 int prefix;
7290 relax_substateT subtype;
7291 symbolS *sym;
7292 offsetT off;
7293
f8a5c266 7294 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7295 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7296
7297 prefix = 0;
7298 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7299 {
29b0f896
AM		 7300 prefix = 1;
7301 i.prefixes -= 1;
7302 code16 ^= CODE16;
252b5132 7303 }
29b0f896
AM		 7304 /* Pentium4 branch hints. */
7305 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7306 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7307 {
29b0f896
AM		 7308 prefix++;
7309 i.prefixes--;
7310 }
7311 if (i.prefix[REX_PREFIX] != 0)
7312 {
7313 prefix++;
7314 i.prefixes--;
2f66722d
AM		 7315 }
7316
7e8b059b
L		 7317 /* BND prefixed jump. */
7318 if (i.prefix[BND_PREFIX] != 0)
7319 {
7320 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7321 i.prefixes -= 1;
7322 }
7323
29b0f896
AM		 7324 if (i.prefixes != 0 && !intel_syntax)
7325 as_warn (_("skipping prefixes on this instruction"));
7326
7327 /* It's always a symbol; End frag & setup for relax.
7328 Make sure there is enough room in this frag for the largest
7329 instruction we may generate in md_convert_frag. This is 2
7330 bytes for the opcode and room for the prefix and largest
7331 displacement. */
7332 frag_grow (prefix + 2 + 4);
7333 /* Prefix and 1 opcode byte go in fr_fix. */
7334 p = frag_more (prefix + 1);
7335 if (i.prefix[DATA_PREFIX] != 0)
7336 *p++ = DATA_PREFIX_OPCODE;
7337 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7338 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7339 *p++ = i.prefix[SEG_PREFIX];
7340 if (i.prefix[REX_PREFIX] != 0)
7341 *p++ = i.prefix[REX_PREFIX];
7342 *p = i.tm.base_opcode;
7343
7344 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7345 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7346 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7347 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7348 else
f8a5c266 7349 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7350 subtype |= code16;
3e73aa7c 7351
29b0f896
AM		 7352 sym = i.op[0].disps->X_add_symbol;
7353 off = i.op[0].disps->X_add_number;
3e73aa7c 7354
29b0f896
AM		 7355 if (i.op[0].disps->X_op != O_constant
7356 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7357 {
29b0f896
AM		 7358 /* Handle complex expressions. */
7359 sym = make_expr_symbol (i.op[0].disps);
7360 off = 0;
7361 }
3e73aa7c 7362
29b0f896
AM		 7363 /* 1 possible extra opcode + 4 byte displacement go in var part.
7364 Pass reloc in fr_var. */
d258b828 7365 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7366}
3e73aa7c 7367
bd7ab16b
L		 7368#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7369/* Return TRUE iff PLT32 relocation should be used for branching to
7370 symbol S. */
7371
7372static bfd_boolean
7373need_plt32_p (symbolS *s)
7374{
7375 /* PLT32 relocation is ELF only. */
7376 if (!IS_ELF)
7377 return FALSE;
7378
7379 /* Since there is no need to prepare for PLT branch on x86-64, we
7380 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7381 be used as a marker for 32-bit PC-relative branches. */
7382 if (!object_64bit)
7383 return FALSE;
7384
7385 /* Weak or undefined symbol need PLT32 relocation. */
7386 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7387 return TRUE;
7388
7389 /* Non-global symbol doesn't need PLT32 relocation. */
7390 if (! S_IS_EXTERNAL (s))
7391 return FALSE;
7392
7393 /* Other global symbols need PLT32 relocation. NB: Symbol with
7394 non-default visibilities are treated as normal global symbol
7395 so that PLT32 relocation can be used as a marker for 32-bit
7396 PC-relative branches. It is useful for linker relaxation. */
7397 return TRUE;
7398}
7399#endif
7400
29b0f896 7401static void
e3bb37b5 7402output_jump (void)
29b0f896
AM		 7403{
7404 char *p;
7405 int size;
3e02c1cc 7406 fixS *fixP;
bd7ab16b 7407 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7408
40fb9820 7409 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7410 {
7411 /* This is a loop or jecxz type instruction. */
7412 size = 1;
7413 if (i.prefix[ADDR_PREFIX] != 0)
7414 {
7415 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7416 i.prefixes -= 1;
7417 }
7418 /* Pentium4 branch hints. */
7419 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7420 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7421 {
7422 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7423 i.prefixes--;
3e73aa7c
JH		 7424 }
7425 }
29b0f896
AM		 7426 else
7427 {
7428 int code16;
3e73aa7c 7429
29b0f896
AM		 7430 code16 = 0;
7431 if (flag_code == CODE_16BIT)
7432 code16 = CODE16;
3e73aa7c 7433
29b0f896
AM		 7434 if (i.prefix[DATA_PREFIX] != 0)
7435 {
7436 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7437 i.prefixes -= 1;
7438 code16 ^= CODE16;
7439 }
252b5132 7440
29b0f896
AM		 7441 size = 4;
7442 if (code16)
7443 size = 2;
7444 }
9fcc94b6 7445
29b0f896
AM		 7446 if (i.prefix[REX_PREFIX] != 0)
7447 {
7448 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7449 i.prefixes -= 1;
7450 }
252b5132 7451
7e8b059b
L		 7452 /* BND prefixed jump. */
7453 if (i.prefix[BND_PREFIX] != 0)
7454 {
7455 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7456 i.prefixes -= 1;
7457 }
7458
29b0f896
AM		 7459 if (i.prefixes != 0 && !intel_syntax)
7460 as_warn (_("skipping prefixes on this instruction"));
e0890092 7461
42164a71
L		 7462 p = frag_more (i.tm.opcode_length + size);
7463 switch (i.tm.opcode_length)
7464 {
7465 case 2:
7466 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7467 /* Fall through. */
42164a71
L		 7468 case 1:
7469 *p++ = i.tm.base_opcode;
7470 break;
7471 default:
7472 abort ();
7473 }
e0890092 7474
bd7ab16b
L		 7475#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7476 if (size == 4
7477 && jump_reloc == NO_RELOC
7478 && need_plt32_p (i.op[0].disps->X_add_symbol))
7479 jump_reloc = BFD_RELOC_X86_64_PLT32;
7480#endif
7481
7482 jump_reloc = reloc (size, 1, 1, jump_reloc);
7483
3e02c1cc 7484 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7485 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7486
7487 /* All jumps handled here are signed, but don't use a signed limit
7488 check for 32 and 16 bit jumps as we want to allow wrap around at
7489 4G and 64k respectively. */
7490 if (size == 1)
7491 fixP->fx_signed = 1;
29b0f896 7492}
e0890092 7493
29b0f896 7494static void
e3bb37b5 7495output_interseg_jump (void)
29b0f896
AM		 7496{
7497 char *p;
7498 int size;
7499 int prefix;
7500 int code16;
252b5132 7501
29b0f896
AM		 7502 code16 = 0;
7503 if (flag_code == CODE_16BIT)
7504 code16 = CODE16;
a217f122 7505
29b0f896
AM		 7506 prefix = 0;
7507 if (i.prefix[DATA_PREFIX] != 0)
7508 {
7509 prefix = 1;
7510 i.prefixes -= 1;
7511 code16 ^= CODE16;
7512 }
7513 if (i.prefix[REX_PREFIX] != 0)
7514 {
7515 prefix++;
7516 i.prefixes -= 1;
7517 }
252b5132 7518
29b0f896
AM		 7519 size = 4;
7520 if (code16)
7521 size = 2;
252b5132 7522
29b0f896
AM		 7523 if (i.prefixes != 0 && !intel_syntax)
7524 as_warn (_("skipping prefixes on this instruction"));
252b5132 7525
29b0f896
AM		 7526 /* 1 opcode; 2 segment; offset */
7527 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7528
29b0f896
AM		 7529 if (i.prefix[DATA_PREFIX] != 0)
7530 *p++ = DATA_PREFIX_OPCODE;
252b5132 7531
29b0f896
AM		 7532 if (i.prefix[REX_PREFIX] != 0)
7533 *p++ = i.prefix[REX_PREFIX];
252b5132 7534
29b0f896
AM		 7535 *p++ = i.tm.base_opcode;
7536 if (i.op[1].imms->X_op == O_constant)
7537 {
7538 offsetT n = i.op[1].imms->X_add_number;
252b5132 7539
29b0f896
AM		 7540 if (size == 2
7541 && !fits_in_unsigned_word (n)
7542 && !fits_in_signed_word (n))
7543 {
7544 as_bad (_("16-bit jump out of range"));
7545 return;
7546 }
7547 md_number_to_chars (p, n, size);
7548 }
7549 else
7550 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7551 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7552 if (i.op[0].imms->X_op != O_constant)
7553 as_bad (_("can't handle non absolute segment in `%s'"),
7554 i.tm.name);
7555 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7556}
a217f122 7557
29b0f896 7558static void
e3bb37b5 7559output_insn (void)
29b0f896 7560{
2bbd9c25
JJ		 7561 fragS *insn_start_frag;
7562 offsetT insn_start_off;
7563
29b0f896
AM		 7564 /* Tie dwarf2 debug info to the address at the start of the insn.
7565 We can't do this after the insn has been output as the current
7566 frag may have been closed off. eg. by frag_var. */
7567 dwarf2_emit_insn (0);
7568
2bbd9c25
JJ		 7569 insn_start_frag = frag_now;
7570 insn_start_off = frag_now_fix ();
7571
29b0f896 7572 /* Output jumps. */
40fb9820 7573 if (i.tm.opcode_modifier.jump)
29b0f896 7574 output_branch ();
40fb9820
L		 7575 else if (i.tm.opcode_modifier.jumpbyte
7576 || i.tm.opcode_modifier.jumpdword)
29b0f896 7577 output_jump ();
40fb9820 7578 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7579 output_interseg_jump ();
7580 else
7581 {
7582 /* Output normal instructions here. */
7583 char *p;
7584 unsigned char *q;
47465058 7585 unsigned int j;
331d2d0d 7586 unsigned int prefix;
4dffcebc 7587
e4e00185
AS		 7588 if (avoid_fence
7589 && i.tm.base_opcode == 0xfae
7590 && i.operands == 1
7591 && i.imm_operands == 1
7592 && (i.op[0].imms->X_add_number == 0xe8
7593 || i.op[0].imms->X_add_number == 0xf0
7594 || i.op[0].imms->X_add_number == 0xf8))
7595 {
7596 /* Encode lfence, mfence, and sfence as
7597 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7598 offsetT val = 0x240483f0ULL;
7599 p = frag_more (5);
7600 md_number_to_chars (p, val, 5);
7601 return;
7602 }
7603
d022bddd
IT		 7604 /* Some processors fail on LOCK prefix. This options makes
7605 assembler ignore LOCK prefix and serves as a workaround. */
7606 if (omit_lock_prefix)
7607 {
7608 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7609 return;
7610 i.prefix[LOCK_PREFIX] = 0;
7611 }
7612
43234a1e
L		 7613 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7614 don't need the explicit prefix. */
7615 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7616 {
c0f3af97 7617 switch (i.tm.opcode_length)
bc4bd9ab 7618 {
c0f3af97
L		 7619 case 3:
7620 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7621 {
c0f3af97
L		 7622 prefix = (i.tm.base_opcode >> 24) & 0xff;
7623 goto check_prefix;
7624 }
7625 break;
7626 case 2:
7627 if ((i.tm.base_opcode & 0xff0000) != 0)
7628 {
7629 prefix = (i.tm.base_opcode >> 16) & 0xff;
7630 if (i.tm.cpu_flags.bitfield.cpupadlock)
7631 {
4dffcebc 7632check_prefix:
c0f3af97 7633 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7634 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7635 != REPE_PREFIX_OPCODE))
7636 add_prefix (prefix);
7637 }
7638 else
4dffcebc
L		 7639 add_prefix (prefix);
7640 }
c0f3af97
L		 7641 break;
7642 case 1:
7643 break;
390c91cf
L		 7644 case 0:
7645 /* Check for pseudo prefixes. */
7646 as_bad_where (insn_start_frag->fr_file,
7647 insn_start_frag->fr_line,
7648 _("pseudo prefix without instruction"));
7649 return;
c0f3af97
L		 7650 default:
7651 abort ();
bc4bd9ab 7652 }
c0f3af97 7653
6d19a37a 7654#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7655 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7656 R_X86_64_GOTTPOFF relocation so that linker can safely
7657 perform IE->LE optimization. */
7658 if (x86_elf_abi == X86_64_X32_ABI
7659 && i.operands == 2
7660 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7661 && i.prefix[REX_PREFIX] == 0)
7662 add_prefix (REX_OPCODE);
6d19a37a 7663#endif
cf61b747 7664
c0f3af97
L		 7665 /* The prefix bytes. */
7666 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7667 if (*q)
7668 FRAG_APPEND_1_CHAR (*q);
0f10071e 7669 }
ae5c1c7b 7670 else
c0f3af97
L		 7671 {
7672 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7673 if (*q)
7674 switch (j)
7675 {
7676 case REX_PREFIX:
7677 /* REX byte is encoded in VEX prefix. */
7678 break;
7679 case SEG_PREFIX:
7680 case ADDR_PREFIX:
7681 FRAG_APPEND_1_CHAR (*q);
7682 break;
7683 default:
7684 /* There should be no other prefixes for instructions
7685 with VEX prefix. */
7686 abort ();
7687 }
7688
43234a1e
L		 7689 /* For EVEX instructions i.vrex should become 0 after
7690 build_evex_prefix. For VEX instructions upper 16 registers
7691 aren't available, so VREX should be 0. */
7692 if (i.vrex)
7693 abort ();
c0f3af97
L		 7694 /* Now the VEX prefix. */
7695 p = frag_more (i.vex.length);
7696 for (j = 0; j < i.vex.length; j++)
7697 p[j] = i.vex.bytes[j];
7698 }
252b5132 7699
29b0f896 7700 /* Now the opcode; be careful about word order here! */
4dffcebc 7701 if (i.tm.opcode_length == 1)
29b0f896
AM		 7702 {
7703 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7704 }
7705 else
7706 {
4dffcebc 7707 switch (i.tm.opcode_length)
331d2d0d 7708 {
43234a1e
L		 7709 case 4:
7710 p = frag_more (4);
7711 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7712 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7713 break;
4dffcebc 7714 case 3:
331d2d0d
L		 7715 p = frag_more (3);
7716 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7717 break;
7718 case 2:
7719 p = frag_more (2);
7720 break;
7721 default:
7722 abort ();
7723 break;
331d2d0d 7724 }
0f10071e 7725
29b0f896
AM		 7726 /* Put out high byte first: can't use md_number_to_chars! */
7727 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7728 *p = i.tm.base_opcode & 0xff;
7729 }
3e73aa7c 7730
29b0f896 7731 /* Now the modrm byte and sib byte (if present). */
40fb9820 7732 if (i.tm.opcode_modifier.modrm)
29b0f896 7733 {
4a3523fa
L		 7734 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7735 | i.rm.reg << 3
7736 | i.rm.mode << 6));
29b0f896
AM		 7737 /* If i.rm.regmem == ESP (4)
7738 && i.rm.mode != (Register mode)
7739 && not 16 bit
7740 ==> need second modrm byte. */
7741 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7742 && i.rm.mode != 3
dc821c5f 7743 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7744 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7745 | i.sib.index << 3
7746 | i.sib.scale << 6));
29b0f896 7747 }
3e73aa7c 7748
29b0f896 7749 if (i.disp_operands)
2bbd9c25 7750 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7751
29b0f896 7752 if (i.imm_operands)
2bbd9c25 7753 output_imm (insn_start_frag, insn_start_off);
29b0f896 7754 }
252b5132 7755
29b0f896
AM		 7756#ifdef DEBUG386
7757 if (flag_debug)
7758 {
7b81dfbb 7759 pi ("" /*line*/, &i);
29b0f896
AM		 7760 }
7761#endif /* DEBUG386 */
7762}
252b5132 7763
e205caa7
L		 7764/* Return the size of the displacement operand N. */
7765
7766static int
7767disp_size (unsigned int n)
7768{
7769 int size = 4;
43234a1e 7770
b5014f7a 7771 if (i.types[n].bitfield.disp64)
40fb9820
L		 7772 size = 8;
7773 else if (i.types[n].bitfield.disp8)
7774 size = 1;
7775 else if (i.types[n].bitfield.disp16)
7776 size = 2;
e205caa7
L		 7777 return size;
7778}
7779
7780/* Return the size of the immediate operand N. */
7781
7782static int
7783imm_size (unsigned int n)
7784{
7785 int size = 4;
40fb9820
L		 7786 if (i.types[n].bitfield.imm64)
7787 size = 8;
7788 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7789 size = 1;
7790 else if (i.types[n].bitfield.imm16)
7791 size = 2;
e205caa7
L		 7792 return size;
7793}
7794
29b0f896 7795static void
64e74474 7796output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7797{
7798 char *p;
7799 unsigned int n;
252b5132 7800
29b0f896
AM		 7801 for (n = 0; n < i.operands; n++)
7802 {
b5014f7a 7803 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7804 {
7805 if (i.op[n].disps->X_op == O_constant)
7806 {
e205caa7 7807 int size = disp_size (n);
43234a1e 7808 offsetT val = i.op[n].disps->X_add_number;
252b5132 7809
b5014f7a 7810 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7811 p = frag_more (size);
7812 md_number_to_chars (p, val, size);
7813 }
7814 else
7815 {
f86103b7 7816 enum bfd_reloc_code_real reloc_type;
e205caa7 7817 int size = disp_size (n);
40fb9820 7818 int sign = i.types[n].bitfield.disp32s;
29b0f896 7819 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7820 fixS *fixP;
29b0f896 7821
e205caa7 7822 /* We can't have 8 bit displacement here. */
9c2799c2 7823 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7824
29b0f896
AM		 7825 /* The PC relative address is computed relative
7826 to the instruction boundary, so in case immediate
7827 fields follows, we need to adjust the value. */
7828 if (pcrel && i.imm_operands)
7829 {
29b0f896 7830 unsigned int n1;
e205caa7 7831 int sz = 0;
252b5132 7832
29b0f896 7833 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7834 if (operand_type_check (i.types[n1], imm))
252b5132 7835 {
e205caa7
L		 7836 /* Only one immediate is allowed for PC
7837 relative address. */
9c2799c2 7838 gas_assert (sz == 0);
e205caa7
L		 7839 sz = imm_size (n1);
7840 i.op[n].disps->X_add_number -= sz;
252b5132 7841 }
29b0f896 7842 /* We should find the immediate. */
9c2799c2 7843 gas_assert (sz != 0);
29b0f896 7844 }
520dc8e8 7845
29b0f896 7846 p = frag_more (size);
d258b828 7847 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7848 if (GOT_symbol
2bbd9c25 7849 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7850 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7851 || reloc_type == BFD_RELOC_X86_64_32S
7852 || (reloc_type == BFD_RELOC_64
7853 && object_64bit))
d6ab8113
JB		 7854 && (i.op[n].disps->X_op == O_symbol
7855 || (i.op[n].disps->X_op == O_add
7856 && ((symbol_get_value_expression
7857 (i.op[n].disps->X_op_symbol)->X_op)
7858 == O_subtract))))
7859 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7860 {
7861 offsetT add;
7862
7863 if (insn_start_frag == frag_now)
7864 add = (p - frag_now->fr_literal) - insn_start_off;
7865 else
7866 {
7867 fragS *fr;
7868
7869 add = insn_start_frag->fr_fix - insn_start_off;
7870 for (fr = insn_start_frag->fr_next;
7871 fr && fr != frag_now; fr = fr->fr_next)
7872 add += fr->fr_fix;
7873 add += p - frag_now->fr_literal;
7874 }
7875
4fa24527 7876 if (!object_64bit)
7b81dfbb
AJ		 7877 {
7878 reloc_type = BFD_RELOC_386_GOTPC;
7879 i.op[n].imms->X_add_number += add;
7880 }
7881 else if (reloc_type == BFD_RELOC_64)
7882 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7883 else
7b81dfbb
AJ		 7884 /* Don't do the adjustment for x86-64, as there
7885 the pcrel addressing is relative to the _next_
7886 insn, and that is taken care of in other code. */
d6ab8113 7887 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7888 }
02a86693
L		 7889 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7890 size, i.op[n].disps, pcrel,
7891 reloc_type);
7892 /* Check for "call/jmp *mem", "mov mem, %reg",
7893 "test %reg, mem" and "binop mem, %reg" where binop
7894 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7895 instructions. Always generate R_386_GOT32X for
7896 "sym*GOT" operand in 32-bit mode. */
7897 if ((generate_relax_relocations
7898 || (!object_64bit
7899 && i.rm.mode == 0
7900 && i.rm.regmem == 5))
7901 && (i.rm.mode == 2
7902 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7903 && ((i.operands == 1
7904 && i.tm.base_opcode == 0xff
7905 && (i.rm.reg == 2 || i.rm.reg == 4))
7906 || (i.operands == 2
7907 && (i.tm.base_opcode == 0x8b
7908 || i.tm.base_opcode == 0x85
7909 || (i.tm.base_opcode & 0xc7) == 0x03))))
7910 {
7911 if (object_64bit)
7912 {
7913 fixP->fx_tcbit = i.rex != 0;
7914 if (i.base_reg
7915 && (i.base_reg->reg_num == RegRip
7916 || i.base_reg->reg_num == RegEip))
7917 fixP->fx_tcbit2 = 1;
7918 }
7919 else
7920 fixP->fx_tcbit2 = 1;
7921 }
29b0f896
AM		 7922 }
7923 }
7924 }
7925}
252b5132 7926
29b0f896 7927static void
64e74474 7928output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7929{
7930 char *p;
7931 unsigned int n;
252b5132 7932
29b0f896
AM		 7933 for (n = 0; n < i.operands; n++)
7934 {
43234a1e
L		 7935 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7936 if (i.rounding && (int) n == i.rounding->operand)
7937 continue;
7938
40fb9820 7939 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7940 {
7941 if (i.op[n].imms->X_op == O_constant)
7942 {
e205caa7 7943 int size = imm_size (n);
29b0f896 7944 offsetT val;
b4cac588 7945
29b0f896
AM		 7946 val = offset_in_range (i.op[n].imms->X_add_number,
7947 size);
7948 p = frag_more (size);
7949 md_number_to_chars (p, val, size);
7950 }
7951 else
7952 {
7953 /* Not absolute_section.
7954 Need a 32-bit fixup (don't support 8bit
7955 non-absolute imms). Try to support other
7956 sizes ... */
f86103b7 7957 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7958 int size = imm_size (n);
7959 int sign;
29b0f896 7960
40fb9820 7961 if (i.types[n].bitfield.imm32s
a7d61044 7962 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7963 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7964 sign = 1;
e205caa7
L		 7965 else
7966 sign = 0;
520dc8e8 7967
29b0f896 7968 p = frag_more (size);
d258b828 7969 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7970
2bbd9c25
JJ		 7971 /* This is tough to explain. We end up with this one if we
7972 * have operands that look like
7973 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7974 * obtain the absolute address of the GOT, and it is strongly
7975 * preferable from a performance point of view to avoid using
7976 * a runtime relocation for this. The actual sequence of
7977 * instructions often look something like:
7978 *
7979 * call .L66
7980 * .L66:
7981 * popl %ebx
7982 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7983 *
7984 * The call and pop essentially return the absolute address
7985 * of the label .L66 and store it in %ebx. The linker itself
7986 * will ultimately change the first operand of the addl so
7987 * that %ebx points to the GOT, but to keep things simple, the
7988 * .o file must have this operand set so that it generates not
7989 * the absolute address of .L66, but the absolute address of
7990 * itself. This allows the linker itself simply treat a GOTPC
7991 * relocation as asking for a pcrel offset to the GOT to be
7992 * added in, and the addend of the relocation is stored in the
7993 * operand field for the instruction itself.
7994 *
7995 * Our job here is to fix the operand so that it would add
7996 * the correct offset so that %ebx would point to itself. The
7997 * thing that is tricky is that .-.L66 will point to the
7998 * beginning of the instruction, so we need to further modify
7999 * the operand so that it will point to itself. There are
8000 * other cases where you have something like:
8001 *
8002 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8003 *
8004 * and here no correction would be required. Internally in
8005 * the assembler we treat operands of this form as not being
8006 * pcrel since the '.' is explicitly mentioned, and I wonder
8007 * whether it would simplify matters to do it this way. Who
8008 * knows. In earlier versions of the PIC patches, the
8009 * pcrel_adjust field was used to store the correction, but
8010 * since the expression is not pcrel, I felt it would be
8011 * confusing to do it this way. */
8012
d6ab8113 8013 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8014 || reloc_type == BFD_RELOC_X86_64_32S
8015 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8016 && GOT_symbol
8017 && GOT_symbol == i.op[n].imms->X_add_symbol
8018 && (i.op[n].imms->X_op == O_symbol
8019 || (i.op[n].imms->X_op == O_add
8020 && ((symbol_get_value_expression
8021 (i.op[n].imms->X_op_symbol)->X_op)
8022 == O_subtract))))
8023 {
2bbd9c25
JJ		 8024 offsetT add;
8025
8026 if (insn_start_frag == frag_now)
8027 add = (p - frag_now->fr_literal) - insn_start_off;
8028 else
8029 {
8030 fragS *fr;
8031
8032 add = insn_start_frag->fr_fix - insn_start_off;
8033 for (fr = insn_start_frag->fr_next;
8034 fr && fr != frag_now; fr = fr->fr_next)
8035 add += fr->fr_fix;
8036 add += p - frag_now->fr_literal;
8037 }
8038
4fa24527 8039 if (!object_64bit)
d6ab8113 8040 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8041 else if (size == 4)
d6ab8113 8042 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8043 else if (size == 8)
8044 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8045 i.op[n].imms->X_add_number += add;
29b0f896 8046 }
29b0f896
AM		 8047 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8048 i.op[n].imms, 0, reloc_type);
8049 }
8050 }
8051 }
252b5132
RH		 8052}
8053\f
d182319b
JB		 8054/* x86_cons_fix_new is called via the expression parsing code when a
8055 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8056static int cons_sign = -1;
8057
8058void
e3bb37b5 8059x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8060 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8061{
d258b828 8062 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8063
8064#ifdef TE_PE
8065 if (exp->X_op == O_secrel)
8066 {
8067 exp->X_op = O_symbol;
8068 r = BFD_RELOC_32_SECREL;
8069 }
8070#endif
8071
8072 fix_new_exp (frag, off, len, exp, 0, r);
8073}
8074
357d1bd8
L		 8075/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8076 purpose of the `.dc.a' internal pseudo-op. */
8077
8078int
8079x86_address_bytes (void)
8080{
8081 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8082 return 4;
8083 return stdoutput->arch_info->bits_per_address / 8;
8084}
8085
d382c579
TG		 8086#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8087 || defined (LEX_AT)
d258b828 8088# define lex_got(reloc, adjust, types) NULL
718ddfc0 8089#else
f3c180ae
AM		 8090/* Parse operands of the form
8091 <symbol>@GOTOFF+<nnn>
8092 and similar .plt or .got references.
8093
8094 If we find one, set up the correct relocation in RELOC and copy the
8095 input string, minus the `@GOTOFF' into a malloc'd buffer for
8096 parsing by the calling routine. Return this buffer, and if ADJUST
8097 is non-null set it to the length of the string we removed from the
8098 input line. Otherwise return NULL. */
8099static char *
91d6fa6a 8100lex_got (enum bfd_reloc_code_real *rel,
64e74474 8101 int *adjust,
d258b828 8102 i386_operand_type *types)
f3c180ae 8103{
7b81dfbb
AJ		 8104 /* Some of the relocations depend on the size of what field is to
8105 be relocated. But in our callers i386_immediate and i386_displacement
8106 we don't yet know the operand size (this will be set by insn
8107 matching). Hence we record the word32 relocation here,
8108 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8109 static const struct {
8110 const char *str;
cff8d58a 8111 int len;
4fa24527 8112 const enum bfd_reloc_code_real rel[2];
40fb9820 8113 const i386_operand_type types64;
f3c180ae 8114 } gotrel[] = {
8ce3d284 8115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8116 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8117 BFD_RELOC_SIZE32 },
8118 OPERAND_TYPE_IMM32_64 },
8ce3d284 8119#endif
cff8d58a
L		 8120 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8121 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8122 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8123 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8124 BFD_RELOC_X86_64_PLT32 },
40fb9820 8125 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8126 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8127 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8128 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8129 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8130 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8131 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8132 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8133 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8134 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8135 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8136 BFD_RELOC_X86_64_TLSGD },
40fb9820 8137 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8138 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8139 _dummy_first_bfd_reloc_code_real },
40fb9820 8140 OPERAND_TYPE_NONE },
cff8d58a
L		 8141 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8142 BFD_RELOC_X86_64_TLSLD },
40fb9820 8143 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8144 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8145 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8146 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8147 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8148 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8149 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8150 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8151 _dummy_first_bfd_reloc_code_real },
40fb9820 8152 OPERAND_TYPE_NONE },
cff8d58a
L		 8153 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8154 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8155 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8156 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8157 _dummy_first_bfd_reloc_code_real },
40fb9820 8158 OPERAND_TYPE_NONE },
cff8d58a
L		 8159 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8160 _dummy_first_bfd_reloc_code_real },
40fb9820 8161 OPERAND_TYPE_NONE },
cff8d58a
L		 8162 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8163 BFD_RELOC_X86_64_GOT32 },
40fb9820 8164 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8165 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8166 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8167 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8168 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8169 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8170 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8171 };
8172 char *cp;
8173 unsigned int j;
8174
d382c579 8175#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8176 if (!IS_ELF)
8177 return NULL;
d382c579 8178#endif
718ddfc0 8179
f3c180ae 8180 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8181 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8182 return NULL;
8183
47465058 8184 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8185 {
cff8d58a 8186 int len = gotrel[j].len;
28f81592 8187 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8188 {
4fa24527 8189 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8190 {
28f81592
AM		 8191 int first, second;
8192 char *tmpbuf, *past_reloc;
f3c180ae 8193
91d6fa6a 8194 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8195
3956db08
JB		 8196 if (types)
8197 {
8198 if (flag_code != CODE_64BIT)
40fb9820
L		 8199 {
8200 types->bitfield.imm32 = 1;
8201 types->bitfield.disp32 = 1;
8202 }
3956db08
JB		 8203 else
8204 *types = gotrel[j].types64;
8205 }
8206
8fd4256d 8207 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8208 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8209
28f81592 8210 /* The length of the first part of our input line. */
f3c180ae 8211 first = cp - input_line_pointer;
28f81592
AM		 8212
8213 /* The second part goes from after the reloc token until
67c11a9b 8214 (and including) an end_of_line char or comma. */
28f81592 8215 past_reloc = cp + 1 + len;
67c11a9b
AM		 8216 cp = past_reloc;
8217 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8218 ++cp;
8219 second = cp + 1 - past_reloc;
28f81592
AM		 8220
8221 /* Allocate and copy string. The trailing NUL shouldn't
8222 be necessary, but be safe. */
add39d23 8223 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8224 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8225 if (second != 0 && *past_reloc != ' ')
8226 /* Replace the relocation token with ' ', so that
8227 errors like foo@GOTOFF1 will be detected. */
8228 tmpbuf[first++] = ' ';
af89796a
L		 8229 else
8230 /* Increment length by 1 if the relocation token is
8231 removed. */
8232 len++;
8233 if (adjust)
8234 *adjust = len;
0787a12d
AM		 8235 memcpy (tmpbuf + first, past_reloc, second);
8236 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8237 return tmpbuf;
8238 }
8239
4fa24527
JB		 8240 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8241 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8242 return NULL;
8243 }
8244 }
8245
8246 /* Might be a symbol version string. Don't as_bad here. */
8247 return NULL;
8248}
4e4f7c87 8249#endif
f3c180ae 8250
a988325c
NC		 8251#ifdef TE_PE
8252#ifdef lex_got
8253#undef lex_got
8254#endif
8255/* Parse operands of the form
8256 <symbol>@SECREL32+<nnn>
8257
8258 If we find one, set up the correct relocation in RELOC and copy the
8259 input string, minus the `@SECREL32' into a malloc'd buffer for
8260 parsing by the calling routine. Return this buffer, and if ADJUST
8261 is non-null set it to the length of the string we removed from the
34bca508
L		 8262 input line. Otherwise return NULL.
8263
a988325c
NC		 8264 This function is copied from the ELF version above adjusted for PE targets. */
8265
8266static char *
8267lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8268 int *adjust ATTRIBUTE_UNUSED,
d258b828 8269 i386_operand_type *types)
a988325c
NC		 8270{
8271 static const struct
8272 {
8273 const char *str;
8274 int len;
8275 const enum bfd_reloc_code_real rel[2];
8276 const i386_operand_type types64;
8277 }
8278 gotrel[] =
8279 {
8280 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8281 BFD_RELOC_32_SECREL },
8282 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8283 };
8284
8285 char *cp;
8286 unsigned j;
8287
8288 for (cp = input_line_pointer; *cp != '@'; cp++)
8289 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8290 return NULL;
8291
8292 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8293 {
8294 int len = gotrel[j].len;
8295
8296 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8297 {
8298 if (gotrel[j].rel[object_64bit] != 0)
8299 {
8300 int first, second;
8301 char *tmpbuf, *past_reloc;
8302
8303 *rel = gotrel[j].rel[object_64bit];
8304 if (adjust)
8305 *adjust = len;
8306
8307 if (types)
8308 {
8309 if (flag_code != CODE_64BIT)
8310 {
8311 types->bitfield.imm32 = 1;
8312 types->bitfield.disp32 = 1;
8313 }
8314 else
8315 *types = gotrel[j].types64;
8316 }
8317
8318 /* The length of the first part of our input line. */
8319 first = cp - input_line_pointer;
8320
8321 /* The second part goes from after the reloc token until
8322 (and including) an end_of_line char or comma. */
8323 past_reloc = cp + 1 + len;
8324 cp = past_reloc;
8325 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8326 ++cp;
8327 second = cp + 1 - past_reloc;
8328
8329 /* Allocate and copy string. The trailing NUL shouldn't
8330 be necessary, but be safe. */
add39d23 8331 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8332 memcpy (tmpbuf, input_line_pointer, first);
8333 if (second != 0 && *past_reloc != ' ')
8334 /* Replace the relocation token with ' ', so that
8335 errors like foo@SECLREL321 will be detected. */
8336 tmpbuf[first++] = ' ';
8337 memcpy (tmpbuf + first, past_reloc, second);
8338 tmpbuf[first + second] = '\0';
8339 return tmpbuf;
8340 }
8341
8342 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8343 gotrel[j].str, 1 << (5 + object_64bit));
8344 return NULL;
8345 }
8346 }
8347
8348 /* Might be a symbol version string. Don't as_bad here. */
8349 return NULL;
8350}
8351
8352#endif /* TE_PE */
8353
62ebcb5c 8354bfd_reloc_code_real_type
e3bb37b5 8355x86_cons (expressionS *exp, int size)
f3c180ae 8356{
62ebcb5c
AM		 8357 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8358
ee86248c
JB		 8359 intel_syntax = -intel_syntax;
8360
3c7b9c2c 8361 exp->X_md = 0;
4fa24527 8362 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8363 {
8364 /* Handle @GOTOFF and the like in an expression. */
8365 char *save;
8366 char *gotfree_input_line;
4a57f2cf 8367 int adjust = 0;
f3c180ae
AM		 8368
8369 save = input_line_pointer;
d258b828 8370 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8371 if (gotfree_input_line)
8372 input_line_pointer = gotfree_input_line;
8373
8374 expression (exp);
8375
8376 if (gotfree_input_line)
8377 {
8378 /* expression () has merrily parsed up to the end of line,
8379 or a comma - in the wrong buffer. Transfer how far
8380 input_line_pointer has moved to the right buffer. */
8381 input_line_pointer = (save
8382 + (input_line_pointer - gotfree_input_line)
8383 + adjust);
8384 free (gotfree_input_line);
3992d3b7
AM		 8385 if (exp->X_op == O_constant
8386 || exp->X_op == O_absent
8387 || exp->X_op == O_illegal
0398aac5 8388 || exp->X_op == O_register
3992d3b7
AM		 8389 || exp->X_op == O_big)
8390 {
8391 char c = *input_line_pointer;
8392 *input_line_pointer = 0;
8393 as_bad (_("missing or invalid expression `%s'"), save);
8394 *input_line_pointer = c;
8395 }
f3c180ae
AM		 8396 }
8397 }
8398 else
8399 expression (exp);
ee86248c
JB		 8400
8401 intel_syntax = -intel_syntax;
8402
8403 if (intel_syntax)
8404 i386_intel_simplify (exp);
62ebcb5c
AM		 8405
8406 return got_reloc;
f3c180ae 8407}
f3c180ae 8408
9f32dd5b
L		 8409static void
8410signed_cons (int size)
6482c264 8411{
d182319b
JB		 8412 if (flag_code == CODE_64BIT)
8413 cons_sign = 1;
8414 cons (size);
8415 cons_sign = -1;
6482c264
NC		 8416}
8417
d182319b 8418#ifdef TE_PE
6482c264 8419static void
7016a5d5 8420pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8421{
8422 expressionS exp;
8423
8424 do
8425 {
8426 expression (&exp);
8427 if (exp.X_op == O_symbol)
8428 exp.X_op = O_secrel;
8429
8430 emit_expr (&exp, 4);
8431 }
8432 while (*input_line_pointer++ == ',');
8433
8434 input_line_pointer--;
8435 demand_empty_rest_of_line ();
8436}
6482c264
NC		 8437#endif
8438
43234a1e
L		 8439/* Handle Vector operations. */
8440
8441static char *
8442check_VecOperations (char *op_string, char *op_end)
8443{
8444 const reg_entry *mask;
8445 const char *saved;
8446 char *end_op;
8447
8448 while (*op_string
8449 && (op_end == NULL || op_string < op_end))
8450 {
8451 saved = op_string;
8452 if (*op_string == '{')
8453 {
8454 op_string++;
8455
8456 /* Check broadcasts. */
8457 if (strncmp (op_string, "1to", 3) == 0)
8458 {
8459 int bcst_type;
8460
8461 if (i.broadcast)
8462 goto duplicated_vec_op;
8463
8464 op_string += 3;
8465 if (*op_string == '8')
8e6e0792 8466 bcst_type = 8;
b28d1bda 8467 else if (*op_string == '4')
8e6e0792 8468 bcst_type = 4;
b28d1bda 8469 else if (*op_string == '2')
8e6e0792 8470 bcst_type = 2;
43234a1e
L		 8471 else if (*op_string == '1'
8472 && *(op_string+1) == '6')
8473 {
8e6e0792 8474 bcst_type = 16;
43234a1e
L		 8475 op_string++;
8476 }
8477 else
8478 {
8479 as_bad (_("Unsupported broadcast: `%s'"), saved);
8480 return NULL;
8481 }
8482 op_string++;
8483
8484 broadcast_op.type = bcst_type;
8485 broadcast_op.operand = this_operand;
8486 i.broadcast = &broadcast_op;
8487 }
8488 /* Check masking operation. */
8489 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8490 {
8491 /* k0 can't be used for write mask. */
6d2cd6b2 8492 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8493 {
6d2cd6b2
JB		 8494 as_bad (_("`%s%s' can't be used for write mask"),
8495 register_prefix, mask->reg_name);
43234a1e
L		 8496 return NULL;
8497 }
8498
8499 if (!i.mask)
8500 {
8501 mask_op.mask = mask;
8502 mask_op.zeroing = 0;
8503 mask_op.operand = this_operand;
8504 i.mask = &mask_op;
8505 }
8506 else
8507 {
8508 if (i.mask->mask)
8509 goto duplicated_vec_op;
8510
8511 i.mask->mask = mask;
8512
8513 /* Only "{z}" is allowed here. No need to check
8514 zeroing mask explicitly. */
8515 if (i.mask->operand != this_operand)
8516 {
8517 as_bad (_("invalid write mask `%s'"), saved);
8518 return NULL;
8519 }
8520 }
8521
8522 op_string = end_op;
8523 }
8524 /* Check zeroing-flag for masking operation. */
8525 else if (*op_string == 'z')
8526 {
8527 if (!i.mask)
8528 {
8529 mask_op.mask = NULL;
8530 mask_op.zeroing = 1;
8531 mask_op.operand = this_operand;
8532 i.mask = &mask_op;
8533 }
8534 else
8535 {
8536 if (i.mask->zeroing)
8537 {
8538 duplicated_vec_op:
8539 as_bad (_("duplicated `%s'"), saved);
8540 return NULL;
8541 }
8542
8543 i.mask->zeroing = 1;
8544
8545 /* Only "{%k}" is allowed here. No need to check mask
8546 register explicitly. */
8547 if (i.mask->operand != this_operand)
8548 {
8549 as_bad (_("invalid zeroing-masking `%s'"),
8550 saved);
8551 return NULL;
8552 }
8553 }
8554
8555 op_string++;
8556 }
8557 else
8558 goto unknown_vec_op;
8559
8560 if (*op_string != '}')
8561 {
8562 as_bad (_("missing `}' in `%s'"), saved);
8563 return NULL;
8564 }
8565 op_string++;
0ba3a731
L		 8566
8567 /* Strip whitespace since the addition of pseudo prefixes
8568 changed how the scrubber treats '{'. */
8569 if (is_space_char (*op_string))
8570 ++op_string;
8571
43234a1e
L		 8572 continue;
8573 }
8574 unknown_vec_op:
8575 /* We don't know this one. */
8576 as_bad (_("unknown vector operation: `%s'"), saved);
8577 return NULL;
8578 }
8579
6d2cd6b2
JB		 8580 if (i.mask && i.mask->zeroing && !i.mask->mask)
8581 {
8582 as_bad (_("zeroing-masking only allowed with write mask"));
8583 return NULL;
8584 }
8585
43234a1e
L		 8586 return op_string;
8587}
8588
252b5132 8589static int
70e41ade 8590i386_immediate (char *imm_start)
252b5132
RH		 8591{
8592 char *save_input_line_pointer;
f3c180ae 8593 char *gotfree_input_line;
252b5132 8594 segT exp_seg = 0;
47926f60 8595 expressionS *exp;
40fb9820
L		 8596 i386_operand_type types;
8597
0dfbf9d7 8598 operand_type_set (&types, ~0);
252b5132
RH		 8599
8600 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8601 {
31b2323c
L		 8602 as_bad (_("at most %d immediate operands are allowed"),
8603 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8604 return 0;
8605 }
8606
8607 exp = &im_expressions[i.imm_operands++];
520dc8e8 8608 i.op[this_operand].imms = exp;
252b5132
RH		 8609
8610 if (is_space_char (*imm_start))
8611 ++imm_start;
8612
8613 save_input_line_pointer = input_line_pointer;
8614 input_line_pointer = imm_start;
8615
d258b828 8616 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8617 if (gotfree_input_line)
8618 input_line_pointer = gotfree_input_line;
252b5132
RH		 8619
8620 exp_seg = expression (exp);
8621
83183c0c 8622 SKIP_WHITESPACE ();
43234a1e
L		 8623
8624 /* Handle vector operations. */
8625 if (*input_line_pointer == '{')
8626 {
8627 input_line_pointer = check_VecOperations (input_line_pointer,
8628 NULL);
8629 if (input_line_pointer == NULL)
8630 return 0;
8631 }
8632
252b5132 8633 if (*input_line_pointer)
f3c180ae 8634 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8635
8636 input_line_pointer = save_input_line_pointer;
f3c180ae 8637 if (gotfree_input_line)
ee86248c
JB		 8638 {
8639 free (gotfree_input_line);
8640
8641 if (exp->X_op == O_constant || exp->X_op == O_register)
8642 exp->X_op = O_illegal;
8643 }
8644
8645 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8646}
252b5132 8647
ee86248c
JB		 8648static int
8649i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8650 i386_operand_type types, const char *imm_start)
8651{
8652 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8653 {
313c53d1
L		 8654 if (imm_start)
8655 as_bad (_("missing or invalid immediate expression `%s'"),
8656 imm_start);
3992d3b7 8657 return 0;
252b5132 8658 }
3e73aa7c 8659 else if (exp->X_op == O_constant)
252b5132 8660 {
47926f60 8661 /* Size it properly later. */
40fb9820 8662 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8663 /* If not 64bit, sign extend val. */
8664 if (flag_code != CODE_64BIT
4eed87de
AM		 8665 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8666 exp->X_add_number
8667 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8668 }
4c63da97 8669#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8670 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8671 && exp_seg != absolute_section
47926f60 8672 && exp_seg != text_section
24eab124
AM		 8673 && exp_seg != data_section
8674 && exp_seg != bss_section
8675 && exp_seg != undefined_section
f86103b7 8676 && !bfd_is_com_section (exp_seg))
252b5132 8677 {
d0b47220 8678 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8679 return 0;
8680 }
8681#endif
a841bdf5 8682 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8683 {
313c53d1
L		 8684 if (imm_start)
8685 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8686 return 0;
8687 }
252b5132
RH		 8688 else
8689 {
8690 /* This is an address. The size of the address will be
24eab124 8691 determined later, depending on destination register,
3e73aa7c 8692 suffix, or the default for the section. */
40fb9820
L		 8693 i.types[this_operand].bitfield.imm8 = 1;
8694 i.types[this_operand].bitfield.imm16 = 1;
8695 i.types[this_operand].bitfield.imm32 = 1;
8696 i.types[this_operand].bitfield.imm32s = 1;
8697 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8698 i.types[this_operand] = operand_type_and (i.types[this_operand],
8699 types);
252b5132
RH		 8700 }
8701
8702 return 1;
8703}
8704
551c1ca1 8705static char *
e3bb37b5 8706i386_scale (char *scale)
252b5132 8707{
551c1ca1
AM		 8708 offsetT val;
8709 char *save = input_line_pointer;
252b5132 8710
551c1ca1
AM		 8711 input_line_pointer = scale;
8712 val = get_absolute_expression ();
8713
8714 switch (val)
252b5132 8715 {
551c1ca1 8716 case 1:
252b5132
RH		 8717 i.log2_scale_factor = 0;
8718 break;
551c1ca1 8719 case 2:
252b5132
RH		 8720 i.log2_scale_factor = 1;
8721 break;
551c1ca1 8722 case 4:
252b5132
RH		 8723 i.log2_scale_factor = 2;
8724 break;
551c1ca1 8725 case 8:
252b5132
RH		 8726 i.log2_scale_factor = 3;
8727 break;
8728 default:
a724f0f4
JB		 8729 {
8730 char sep = *input_line_pointer;
8731
8732 *input_line_pointer = '\0';
8733 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8734 scale);
8735 *input_line_pointer = sep;
8736 input_line_pointer = save;
8737 return NULL;
8738 }
252b5132 8739 }
29b0f896 8740 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8741 {
8742 as_warn (_("scale factor of %d without an index register"),
24eab124 8743 1 << i.log2_scale_factor);
252b5132 8744 i.log2_scale_factor = 0;
252b5132 8745 }
551c1ca1
AM		 8746 scale = input_line_pointer;
8747 input_line_pointer = save;
8748 return scale;
252b5132
RH		 8749}
8750
252b5132 8751static int
e3bb37b5 8752i386_displacement (char *disp_start, char *disp_end)
252b5132 8753{
29b0f896 8754 expressionS *exp;
252b5132
RH		 8755 segT exp_seg = 0;
8756 char *save_input_line_pointer;
f3c180ae 8757 char *gotfree_input_line;
40fb9820
L		 8758 int override;
8759 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8760 int ret;
252b5132 8761
31b2323c
L		 8762 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8763 {
8764 as_bad (_("at most %d displacement operands are allowed"),
8765 MAX_MEMORY_OPERANDS);
8766 return 0;
8767 }
8768
0dfbf9d7 8769 operand_type_set (&bigdisp, 0);
40fb9820
L		 8770 if ((i.types[this_operand].bitfield.jumpabsolute)
8771 || (!current_templates->start->opcode_modifier.jump
8772 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8773 {
40fb9820 8774 bigdisp.bitfield.disp32 = 1;
e05278af 8775 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8776 if (flag_code == CODE_64BIT)
8777 {
8778 if (!override)
8779 {
8780 bigdisp.bitfield.disp32s = 1;
8781 bigdisp.bitfield.disp64 = 1;
8782 }
8783 }
8784 else if ((flag_code == CODE_16BIT) ^ override)
8785 {
8786 bigdisp.bitfield.disp32 = 0;
8787 bigdisp.bitfield.disp16 = 1;
8788 }
e05278af
JB		 8789 }
8790 else
8791 {
8792 /* For PC-relative branches, the width of the displacement
8793 is dependent upon data size, not address size. */
e05278af 8794 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8795 if (flag_code == CODE_64BIT)
8796 {
8797 if (override || i.suffix == WORD_MNEM_SUFFIX)
8798 bigdisp.bitfield.disp16 = 1;
8799 else
8800 {
8801 bigdisp.bitfield.disp32 = 1;
8802 bigdisp.bitfield.disp32s = 1;
8803 }
8804 }
8805 else
e05278af
JB		 8806 {
8807 if (!override)
8808 override = (i.suffix == (flag_code != CODE_16BIT
8809 ? WORD_MNEM_SUFFIX
8810 : LONG_MNEM_SUFFIX));
40fb9820
L		 8811 bigdisp.bitfield.disp32 = 1;
8812 if ((flag_code == CODE_16BIT) ^ override)
8813 {
8814 bigdisp.bitfield.disp32 = 0;
8815 bigdisp.bitfield.disp16 = 1;
8816 }
e05278af 8817 }
e05278af 8818 }
c6fb90c8
L		 8819 i.types[this_operand] = operand_type_or (i.types[this_operand],
8820 bigdisp);
252b5132
RH		 8821
8822 exp = &disp_expressions[i.disp_operands];
520dc8e8 8823 i.op[this_operand].disps = exp;
252b5132
RH		 8824 i.disp_operands++;
8825 save_input_line_pointer = input_line_pointer;
8826 input_line_pointer = disp_start;
8827 END_STRING_AND_SAVE (disp_end);
8828
8829#ifndef GCC_ASM_O_HACK
8830#define GCC_ASM_O_HACK 0
8831#endif
8832#if GCC_ASM_O_HACK
8833 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8834 if (i.types[this_operand].bitfield.baseIndex
24eab124 8835 && displacement_string_end[-1] == '+')
252b5132
RH		 8836 {
8837 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8838 constraint within gcc asm statements.
8839 For instance:
8840
8841 #define _set_tssldt_desc(n,addr,limit,type) \
8842 __asm__ __volatile__ ( \
8843 "movw %w2,%0\n\t" \
8844 "movw %w1,2+%0\n\t" \
8845 "rorl $16,%1\n\t" \
8846 "movb %b1,4+%0\n\t" \
8847 "movb %4,5+%0\n\t" \
8848 "movb $0,6+%0\n\t" \
8849 "movb %h1,7+%0\n\t" \
8850 "rorl $16,%1" \
8851 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8852
8853 This works great except that the output assembler ends
8854 up looking a bit weird if it turns out that there is
8855 no offset. You end up producing code that looks like:
8856
8857 #APP
8858 movw $235,(%eax)
8859 movw %dx,2+(%eax)
8860 rorl $16,%edx
8861 movb %dl,4+(%eax)
8862 movb $137,5+(%eax)
8863 movb $0,6+(%eax)
8864 movb %dh,7+(%eax)
8865 rorl $16,%edx
8866 #NO_APP
8867
47926f60 8868 So here we provide the missing zero. */
24eab124
AM		 8869
8870 *displacement_string_end = '0';
252b5132
RH		 8871 }
8872#endif
d258b828 8873 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8874 if (gotfree_input_line)
8875 input_line_pointer = gotfree_input_line;
252b5132 8876
24eab124 8877 exp_seg = expression (exp);
252b5132 8878
636c26b0
AM		 8879 SKIP_WHITESPACE ();
8880 if (*input_line_pointer)
8881 as_bad (_("junk `%s' after expression"), input_line_pointer);
8882#if GCC_ASM_O_HACK
8883 RESTORE_END_STRING (disp_end + 1);
8884#endif
636c26b0 8885 input_line_pointer = save_input_line_pointer;
636c26b0 8886 if (gotfree_input_line)
ee86248c
JB		 8887 {
8888 free (gotfree_input_line);
8889
8890 if (exp->X_op == O_constant || exp->X_op == O_register)
8891 exp->X_op = O_illegal;
8892 }
8893
8894 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8895
8896 RESTORE_END_STRING (disp_end);
8897
8898 return ret;
8899}
8900
8901static int
8902i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8903 i386_operand_type types, const char *disp_start)
8904{
8905 i386_operand_type bigdisp;
8906 int ret = 1;
636c26b0 8907
24eab124
AM		 8908 /* We do this to make sure that the section symbol is in
8909 the symbol table. We will ultimately change the relocation
47926f60 8910 to be relative to the beginning of the section. */
1ae12ab7 8911 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8912 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8913 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8914 {
636c26b0 8915 if (exp->X_op != O_symbol)
3992d3b7 8916 goto inv_disp;
636c26b0 8917
e5cb08ac 8918 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8919 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8920 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8921 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8922 exp->X_op = O_subtract;
8923 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8924 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8925 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8926 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8927 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8928 else
29b0f896 8929 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8930 }
252b5132 8931
3992d3b7
AM		 8932 else if (exp->X_op == O_absent
8933 || exp->X_op == O_illegal
ee86248c 8934 || exp->X_op == O_big)
2daf4fd8 8935 {
3992d3b7
AM		 8936 inv_disp:
8937 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8938 disp_start);
3992d3b7 8939 ret = 0;
2daf4fd8
AM		 8940 }
8941
0e1147d9
L		 8942 else if (flag_code == CODE_64BIT
8943 && !i.prefix[ADDR_PREFIX]
8944 && exp->X_op == O_constant)
8945 {
8946 /* Since displacement is signed extended to 64bit, don't allow
8947 disp32 and turn off disp32s if they are out of range. */
8948 i.types[this_operand].bitfield.disp32 = 0;
8949 if (!fits_in_signed_long (exp->X_add_number))
8950 {
8951 i.types[this_operand].bitfield.disp32s = 0;
8952 if (i.types[this_operand].bitfield.baseindex)
8953 {
8954 as_bad (_("0x%lx out range of signed 32bit displacement"),
8955 (long) exp->X_add_number);
8956 ret = 0;
8957 }
8958 }
8959 }
8960
4c63da97 8961#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8962 else if (exp->X_op != O_constant
8963 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8964 && exp_seg != absolute_section
8965 && exp_seg != text_section
8966 && exp_seg != data_section
8967 && exp_seg != bss_section
8968 && exp_seg != undefined_section
8969 && !bfd_is_com_section (exp_seg))
24eab124 8970 {
d0b47220 8971 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8972 ret = 0;
24eab124 8973 }
252b5132 8974#endif
3956db08 8975
40fb9820
L		 8976 /* Check if this is a displacement only operand. */
8977 bigdisp = i.types[this_operand];
8978 bigdisp.bitfield.disp8 = 0;
8979 bigdisp.bitfield.disp16 = 0;
8980 bigdisp.bitfield.disp32 = 0;
8981 bigdisp.bitfield.disp32s = 0;
8982 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8983 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8984 i.types[this_operand] = operand_type_and (i.types[this_operand],
8985 types);
3956db08 8986
3992d3b7 8987 return ret;
252b5132
RH		 8988}
8989
2abc2bec
JB		 8990/* Return the active addressing mode, taking address override and
8991 registers forming the address into consideration. Update the
8992 address override prefix if necessary. */
47926f60 8993
2abc2bec
JB		 8994static enum flag_code
8995i386_addressing_mode (void)
252b5132 8996{
be05d201
L		 8997 enum flag_code addr_mode;
8998
8999 if (i.prefix[ADDR_PREFIX])
9000 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9001 else
9002 {
9003 addr_mode = flag_code;
9004
24eab124 9005#if INFER_ADDR_PREFIX
be05d201
L		 9006 if (i.mem_operands == 0)
9007 {
9008 /* Infer address prefix from the first memory operand. */
9009 const reg_entry *addr_reg = i.base_reg;
9010
9011 if (addr_reg == NULL)
9012 addr_reg = i.index_reg;
eecb386c 9013
be05d201
L		 9014 if (addr_reg)
9015 {
9016 if (addr_reg->reg_num == RegEip
9017 || addr_reg->reg_num == RegEiz
dc821c5f 9018 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9019 addr_mode = CODE_32BIT;
9020 else if (flag_code != CODE_64BIT
dc821c5f 9021 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9022 addr_mode = CODE_16BIT;
9023
9024 if (addr_mode != flag_code)
9025 {
9026 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9027 i.prefixes += 1;
9028 /* Change the size of any displacement too. At most one
9029 of Disp16 or Disp32 is set.
9030 FIXME. There doesn't seem to be any real need for
9031 separate Disp16 and Disp32 flags. The same goes for
9032 Imm16 and Imm32. Removing them would probably clean
9033 up the code quite a lot. */
9034 if (flag_code != CODE_64BIT
9035 && (i.types[this_operand].bitfield.disp16
9036 || i.types[this_operand].bitfield.disp32))
9037 i.types[this_operand]
9038 = operand_type_xor (i.types[this_operand], disp16_32);
9039 }
9040 }
9041 }
24eab124 9042#endif
be05d201
L		 9043 }
9044
2abc2bec
JB		 9045 return addr_mode;
9046}
9047
9048/* Make sure the memory operand we've been dealt is valid.
9049 Return 1 on success, 0 on a failure. */
9050
9051static int
9052i386_index_check (const char *operand_string)
9053{
9054 const char *kind = "base/index";
9055 enum flag_code addr_mode = i386_addressing_mode ();
9056
fc0763e6
JB		 9057 if (current_templates->start->opcode_modifier.isstring
9058 && !current_templates->start->opcode_modifier.immext
9059 && (current_templates->end[-1].opcode_modifier.isstring
9060 || i.mem_operands))
9061 {
9062 /* Memory operands of string insns are special in that they only allow
9063 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9064 const reg_entry *expected_reg;
9065 static const char *di_si[][2] =
9066 {
9067 { "esi", "edi" },
9068 { "si", "di" },
9069 { "rsi", "rdi" }
9070 };
9071 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9072
9073 kind = "string address";
9074
8325cc63 9075 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9076 {
9077 i386_operand_type type = current_templates->end[-1].operand_types[0];
9078
9079 if (!type.bitfield.baseindex
9080 || ((!i.mem_operands != !intel_syntax)
9081 && current_templates->end[-1].operand_types[1]
9082 .bitfield.baseindex))
9083 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9084 expected_reg = hash_find (reg_hash,
9085 di_si[addr_mode][type.bitfield.esseg]);
9086
fc0763e6
JB		 9087 }
9088 else
be05d201 9089 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9090
be05d201
L		 9091 if (i.base_reg != expected_reg
9092 || i.index_reg
fc0763e6 9093 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9094 {
be05d201
L		 9095 /* The second memory operand must have the same size as
9096 the first one. */
9097 if (i.mem_operands
9098 && i.base_reg
9099 && !((addr_mode == CODE_64BIT
dc821c5f 9100 && i.base_reg->reg_type.bitfield.qword)
be05d201 9101 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9102 ? i.base_reg->reg_type.bitfield.dword
9103 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9104 goto bad_address;
9105
fc0763e6
JB		 9106 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9107 operand_string,
9108 intel_syntax ? '[' : '(',
9109 register_prefix,
be05d201 9110 expected_reg->reg_name,
fc0763e6 9111 intel_syntax ? ']' : ')');
be05d201 9112 return 1;
fc0763e6 9113 }
be05d201
L		 9114 else
9115 return 1;
9116
9117bad_address:
9118 as_bad (_("`%s' is not a valid %s expression"),
9119 operand_string, kind);
9120 return 0;
3e73aa7c
JH		 9121 }
9122 else
9123 {
be05d201
L		 9124 if (addr_mode != CODE_16BIT)
9125 {
9126 /* 32-bit/64-bit checks. */
9127 if ((i.base_reg
9128 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9129 ? !i.base_reg->reg_type.bitfield.qword
9130 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9131 && (i.index_reg
9132 || (i.base_reg->reg_num
9133 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9134 || (i.index_reg
1b54b8d7
JB		 9135 && !i.index_reg->reg_type.bitfield.xmmword
9136 && !i.index_reg->reg_type.bitfield.ymmword
9137 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9138 && ((addr_mode == CODE_64BIT
dc821c5f 9139 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9140 || i.index_reg->reg_num == RegRiz)
dc821c5f 9141 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9142 || i.index_reg->reg_num == RegEiz))
9143 || !i.index_reg->reg_type.bitfield.baseindex)))
9144 goto bad_address;
8178be5b
JB		 9145
9146 /* bndmk, bndldx, and bndstx have special restrictions. */
9147 if (current_templates->start->base_opcode == 0xf30f1b
9148 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9149 {
9150 /* They cannot use RIP-relative addressing. */
9151 if (i.base_reg && i.base_reg->reg_num == RegRip)
9152 {
9153 as_bad (_("`%s' cannot be used here"), operand_string);
9154 return 0;
9155 }
9156
9157 /* bndldx and bndstx ignore their scale factor. */
9158 if (current_templates->start->base_opcode != 0xf30f1b
9159 && i.log2_scale_factor)
9160 as_warn (_("register scaling is being ignored here"));
9161 }
be05d201
L		 9162 }
9163 else
3e73aa7c 9164 {
be05d201 9165 /* 16-bit checks. */
3e73aa7c 9166 if ((i.base_reg
dc821c5f 9167 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9168 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9169 || (i.index_reg
dc821c5f 9170 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9171 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9172 || !(i.base_reg
9173 && i.base_reg->reg_num < 6
9174 && i.index_reg->reg_num >= 6
9175 && i.log2_scale_factor == 0))))
be05d201 9176 goto bad_address;
3e73aa7c
JH		 9177 }
9178 }
be05d201 9179 return 1;
24eab124 9180}
252b5132 9181
43234a1e
L		 9182/* Handle vector immediates. */
9183
9184static int
9185RC_SAE_immediate (const char *imm_start)
9186{
9187 unsigned int match_found, j;
9188 const char *pstr = imm_start;
9189 expressionS *exp;
9190
9191 if (*pstr != '{')
9192 return 0;
9193
9194 pstr++;
9195 match_found = 0;
9196 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9197 {
9198 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9199 {
9200 if (!i.rounding)
9201 {
9202 rc_op.type = RC_NamesTable[j].type;
9203 rc_op.operand = this_operand;
9204 i.rounding = &rc_op;
9205 }
9206 else
9207 {
9208 as_bad (_("duplicated `%s'"), imm_start);
9209 return 0;
9210 }
9211 pstr += RC_NamesTable[j].len;
9212 match_found = 1;
9213 break;
9214 }
9215 }
9216 if (!match_found)
9217 return 0;
9218
9219 if (*pstr++ != '}')
9220 {
9221 as_bad (_("Missing '}': '%s'"), imm_start);
9222 return 0;
9223 }
9224 /* RC/SAE immediate string should contain nothing more. */;
9225 if (*pstr != 0)
9226 {
9227 as_bad (_("Junk after '}': '%s'"), imm_start);
9228 return 0;
9229 }
9230
9231 exp = &im_expressions[i.imm_operands++];
9232 i.op[this_operand].imms = exp;
9233
9234 exp->X_op = O_constant;
9235 exp->X_add_number = 0;
9236 exp->X_add_symbol = (symbolS *) 0;
9237 exp->X_op_symbol = (symbolS *) 0;
9238
9239 i.types[this_operand].bitfield.imm8 = 1;
9240 return 1;
9241}
9242
8325cc63
JB		 9243/* Only string instructions can have a second memory operand, so
9244 reduce current_templates to just those if it contains any. */
9245static int
9246maybe_adjust_templates (void)
9247{
9248 const insn_template *t;
9249
9250 gas_assert (i.mem_operands == 1);
9251
9252 for (t = current_templates->start; t < current_templates->end; ++t)
9253 if (t->opcode_modifier.isstring)
9254 break;
9255
9256 if (t < current_templates->end)
9257 {
9258 static templates aux_templates;
9259 bfd_boolean recheck;
9260
9261 aux_templates.start = t;
9262 for (; t < current_templates->end; ++t)
9263 if (!t->opcode_modifier.isstring)
9264 break;
9265 aux_templates.end = t;
9266
9267 /* Determine whether to re-check the first memory operand. */
9268 recheck = (aux_templates.start != current_templates->start
9269 || t != current_templates->end);
9270
9271 current_templates = &aux_templates;
9272
9273 if (recheck)
9274 {
9275 i.mem_operands = 0;
9276 if (i.memop1_string != NULL
9277 && i386_index_check (i.memop1_string) == 0)
9278 return 0;
9279 i.mem_operands = 1;
9280 }
9281 }
9282
9283 return 1;
9284}
9285
fc0763e6 9286/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9287 on error. */
252b5132 9288
252b5132 9289static int
a7619375 9290i386_att_operand (char *operand_string)
252b5132 9291{
af6bdddf
AM		 9292 const reg_entry *r;
9293 char *end_op;
24eab124 9294 char *op_string = operand_string;
252b5132 9295
24eab124 9296 if (is_space_char (*op_string))
252b5132
RH		 9297 ++op_string;
9298
24eab124 9299 /* We check for an absolute prefix (differentiating,
47926f60 9300 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9301 if (*op_string == ABSOLUTE_PREFIX)
9302 {
9303 ++op_string;
9304 if (is_space_char (*op_string))
9305 ++op_string;
40fb9820 9306 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9307 }
252b5132 9308
47926f60 9309 /* Check if operand is a register. */
4d1bb795 9310 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9311 {
40fb9820
L		 9312 i386_operand_type temp;
9313
24eab124
AM		 9314 /* Check for a segment override by searching for ':' after a
9315 segment register. */
9316 op_string = end_op;
9317 if (is_space_char (*op_string))
9318 ++op_string;
40fb9820
L		 9319 if (*op_string == ':'
9320 && (r->reg_type.bitfield.sreg2
9321 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9322 {
9323 switch (r->reg_num)
9324 {
9325 case 0:
9326 i.seg[i.mem_operands] = &es;
9327 break;
9328 case 1:
9329 i.seg[i.mem_operands] = &cs;
9330 break;
9331 case 2:
9332 i.seg[i.mem_operands] = &ss;
9333 break;
9334 case 3:
9335 i.seg[i.mem_operands] = &ds;
9336 break;
9337 case 4:
9338 i.seg[i.mem_operands] = &fs;
9339 break;
9340 case 5:
9341 i.seg[i.mem_operands] = &gs;
9342 break;
9343 }
252b5132 9344
24eab124 9345 /* Skip the ':' and whitespace. */
252b5132
RH		 9346 ++op_string;
9347 if (is_space_char (*op_string))
24eab124 9348 ++op_string;
252b5132 9349
24eab124
AM		 9350 if (!is_digit_char (*op_string)
9351 && !is_identifier_char (*op_string)
9352 && *op_string != '('
9353 && *op_string != ABSOLUTE_PREFIX)
9354 {
9355 as_bad (_("bad memory operand `%s'"), op_string);
9356 return 0;
9357 }
47926f60 9358 /* Handle case of %es:*foo. */
24eab124
AM		 9359 if (*op_string == ABSOLUTE_PREFIX)
9360 {
9361 ++op_string;
9362 if (is_space_char (*op_string))
9363 ++op_string;
40fb9820 9364 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9365 }
9366 goto do_memory_reference;
9367 }
43234a1e
L		 9368
9369 /* Handle vector operations. */
9370 if (*op_string == '{')
9371 {
9372 op_string = check_VecOperations (op_string, NULL);
9373 if (op_string == NULL)
9374 return 0;
9375 }
9376
24eab124
AM		 9377 if (*op_string)
9378 {
d0b47220 9379 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9380 return 0;
9381 }
40fb9820
L		 9382 temp = r->reg_type;
9383 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9384 i.types[this_operand] = operand_type_or (i.types[this_operand],
9385 temp);
7d5e4556 9386 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9387 i.op[this_operand].regs = r;
24eab124
AM		 9388 i.reg_operands++;
9389 }
af6bdddf
AM		 9390 else if (*op_string == REGISTER_PREFIX)
9391 {
9392 as_bad (_("bad register name `%s'"), op_string);
9393 return 0;
9394 }
24eab124 9395 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9396 {
24eab124 9397 ++op_string;
40fb9820 9398 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9399 {
d0b47220 9400 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9401 return 0;
9402 }
9403 if (!i386_immediate (op_string))
9404 return 0;
9405 }
43234a1e
L		 9406 else if (RC_SAE_immediate (operand_string))
9407 {
9408 /* If it is a RC or SAE immediate, do nothing. */
9409 ;
9410 }
24eab124
AM		 9411 else if (is_digit_char (*op_string)
9412 || is_identifier_char (*op_string)
d02603dc 9413 || *op_string == '"'
e5cb08ac 9414 || *op_string == '(')
24eab124 9415 {
47926f60 9416 /* This is a memory reference of some sort. */
af6bdddf 9417 char *base_string;
252b5132 9418
47926f60 9419 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9420 char *displacement_string_start;
9421 char *displacement_string_end;
43234a1e 9422 char *vop_start;
252b5132 9423
24eab124 9424 do_memory_reference:
8325cc63
JB		 9425 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9426 return 0;
24eab124 9427 if ((i.mem_operands == 1
40fb9820 9428 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9429 || i.mem_operands == 2)
9430 {
9431 as_bad (_("too many memory references for `%s'"),
9432 current_templates->start->name);
9433 return 0;
9434 }
252b5132 9435
24eab124
AM		 9436 /* Check for base index form. We detect the base index form by
9437 looking for an ')' at the end of the operand, searching
9438 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9439 after the '('. */
af6bdddf 9440 base_string = op_string + strlen (op_string);
c3332e24 9441
43234a1e
L		 9442 /* Handle vector operations. */
9443 vop_start = strchr (op_string, '{');
9444 if (vop_start && vop_start < base_string)
9445 {
9446 if (check_VecOperations (vop_start, base_string) == NULL)
9447 return 0;
9448 base_string = vop_start;
9449 }
9450
af6bdddf
AM		 9451 --base_string;
9452 if (is_space_char (*base_string))
9453 --base_string;
252b5132 9454
47926f60 9455 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9456 displacement_string_start = op_string;
9457 displacement_string_end = base_string + 1;
252b5132 9458
24eab124
AM		 9459 if (*base_string == ')')
9460 {
af6bdddf 9461 char *temp_string;
24eab124
AM		 9462 unsigned int parens_balanced = 1;
9463 /* We've already checked that the number of left & right ()'s are
47926f60 9464 equal, so this loop will not be infinite. */
24eab124
AM		 9465 do
9466 {
9467 base_string--;
9468 if (*base_string == ')')
9469 parens_balanced++;
9470 if (*base_string == '(')
9471 parens_balanced--;
9472 }
9473 while (parens_balanced);
c3332e24 9474
af6bdddf 9475 temp_string = base_string;
c3332e24 9476
24eab124 9477 /* Skip past '(' and whitespace. */
252b5132
RH		 9478 ++base_string;
9479 if (is_space_char (*base_string))
24eab124 9480 ++base_string;
252b5132 9481
af6bdddf 9482 if (*base_string == ','
4eed87de
AM		 9483 || ((i.base_reg = parse_register (base_string, &end_op))
9484 != NULL))
252b5132 9485 {
af6bdddf 9486 displacement_string_end = temp_string;
252b5132 9487
40fb9820 9488 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9489
af6bdddf 9490 if (i.base_reg)
24eab124 9491 {
24eab124
AM		 9492 base_string = end_op;
9493 if (is_space_char (*base_string))
9494 ++base_string;
af6bdddf
AM		 9495 }
9496
9497 /* There may be an index reg or scale factor here. */
9498 if (*base_string == ',')
9499 {
9500 ++base_string;
9501 if (is_space_char (*base_string))
9502 ++base_string;
9503
4eed87de
AM		 9504 if ((i.index_reg = parse_register (base_string, &end_op))
9505 != NULL)
24eab124 9506 {
af6bdddf 9507 base_string = end_op;
24eab124
AM		 9508 if (is_space_char (*base_string))
9509 ++base_string;
af6bdddf
AM		 9510 if (*base_string == ',')
9511 {
9512 ++base_string;
9513 if (is_space_char (*base_string))
9514 ++base_string;
9515 }
e5cb08ac 9516 else if (*base_string != ')')
af6bdddf 9517 {
4eed87de
AM		 9518 as_bad (_("expecting `,' or `)' "
9519 "after index register in `%s'"),
af6bdddf
AM		 9520 operand_string);
9521 return 0;
9522 }
24eab124 9523 }
af6bdddf 9524 else if (*base_string == REGISTER_PREFIX)
24eab124 9525 {
f76bf5e0
L		 9526 end_op = strchr (base_string, ',');
9527 if (end_op)
9528 *end_op = '\0';
af6bdddf 9529 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9530 return 0;
9531 }
252b5132 9532
47926f60 9533 /* Check for scale factor. */
551c1ca1 9534 if (*base_string != ')')
af6bdddf 9535 {
551c1ca1
AM		 9536 char *end_scale = i386_scale (base_string);
9537
9538 if (!end_scale)
af6bdddf 9539 return 0;
24eab124 9540
551c1ca1 9541 base_string = end_scale;
af6bdddf
AM		 9542 if (is_space_char (*base_string))
9543 ++base_string;
9544 if (*base_string != ')')
9545 {
4eed87de
AM		 9546 as_bad (_("expecting `)' "
9547 "after scale factor in `%s'"),
af6bdddf
AM		 9548 operand_string);
9549 return 0;
9550 }
9551 }
9552 else if (!i.index_reg)
24eab124 9553 {
4eed87de
AM		 9554 as_bad (_("expecting index register or scale factor "
9555 "after `,'; got '%c'"),
af6bdddf 9556 *base_string);
24eab124
AM		 9557 return 0;
9558 }
9559 }
af6bdddf 9560 else if (*base_string != ')')
24eab124 9561 {
4eed87de
AM		 9562 as_bad (_("expecting `,' or `)' "
9563 "after base register in `%s'"),
af6bdddf 9564 operand_string);
24eab124
AM		 9565 return 0;
9566 }
c3332e24 9567 }
af6bdddf 9568 else if (*base_string == REGISTER_PREFIX)
c3332e24 9569 {
f76bf5e0
L		 9570 end_op = strchr (base_string, ',');
9571 if (end_op)
9572 *end_op = '\0';
af6bdddf 9573 as_bad (_("bad register name `%s'"), base_string);
24eab124 9574 return 0;
c3332e24 9575 }
24eab124
AM		 9576 }
9577
9578 /* If there's an expression beginning the operand, parse it,
9579 assuming displacement_string_start and
9580 displacement_string_end are meaningful. */
9581 if (displacement_string_start != displacement_string_end)
9582 {
9583 if (!i386_displacement (displacement_string_start,
9584 displacement_string_end))
9585 return 0;
9586 }
9587
9588 /* Special case for (%dx) while doing input/output op. */
9589 if (i.base_reg
0dfbf9d7
L		 9590 && operand_type_equal (&i.base_reg->reg_type,
9591 &reg16_inoutportreg)
24eab124
AM		 9592 && i.index_reg == 0
9593 && i.log2_scale_factor == 0
9594 && i.seg[i.mem_operands] == 0
40fb9820 9595 && !operand_type_check (i.types[this_operand], disp))
24eab124 9596 {
65da13b5 9597 i.types[this_operand] = inoutportreg;
24eab124
AM		 9598 return 1;
9599 }
9600
eecb386c
AM		 9601 if (i386_index_check (operand_string) == 0)
9602 return 0;
5c07affc 9603 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9604 if (i.mem_operands == 0)
9605 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9606 i.mem_operands++;
9607 }
9608 else
ce8a8b2f
AM		 9609 {
9610 /* It's not a memory operand; argh! */
24eab124
AM		 9611 as_bad (_("invalid char %s beginning operand %d `%s'"),
9612 output_invalid (*op_string),
9613 this_operand + 1,
9614 op_string);
9615 return 0;
9616 }
47926f60 9617 return 1; /* Normal return. */
252b5132
RH		 9618}
9619\f
fa94de6b
RM		 9620/* Calculate the maximum variable size (i.e., excluding fr_fix)
9621 that an rs_machine_dependent frag may reach. */
9622
9623unsigned int
9624i386_frag_max_var (fragS *frag)
9625{
9626 /* The only relaxable frags are for jumps.
9627 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9628 gas_assert (frag->fr_type == rs_machine_dependent);
9629 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9630}
9631
b084df0b
L		 9632#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9633static int
8dcea932 9634elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9635{
9636 /* STT_GNU_IFUNC symbol must go through PLT. */
9637 if ((symbol_get_bfdsym (fr_symbol)->flags
9638 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9639 return 0;
9640
9641 if (!S_IS_EXTERNAL (fr_symbol))
9642 /* Symbol may be weak or local. */
9643 return !S_IS_WEAK (fr_symbol);
9644
8dcea932
L		 9645 /* Global symbols with non-default visibility can't be preempted. */
9646 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9647 return 1;
9648
9649 if (fr_var != NO_RELOC)
9650 switch ((enum bfd_reloc_code_real) fr_var)
9651 {
9652 case BFD_RELOC_386_PLT32:
9653 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9654 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9655 return 0;
9656 default:
9657 abort ();
9658 }
9659
b084df0b
L		 9660 /* Global symbols with default visibility in a shared library may be
9661 preempted by another definition. */
8dcea932 9662 return !shared;
b084df0b
L		 9663}
9664#endif
9665
ee7fcc42
AM		 9666/* md_estimate_size_before_relax()
9667
9668 Called just before relax() for rs_machine_dependent frags. The x86
9669 assembler uses these frags to handle variable size jump
9670 instructions.
9671
9672 Any symbol that is now undefined will not become defined.
9673 Return the correct fr_subtype in the frag.
9674 Return the initial "guess for variable size of frag" to caller.
9675 The guess is actually the growth beyond the fixed part. Whatever
9676 we do to grow the fixed or variable part contributes to our
9677 returned value. */
9678
252b5132 9679int
7016a5d5 9680md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9681{
252b5132 9682 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9683 check for un-relaxable symbols. On an ELF system, we can't relax
9684 an externally visible symbol, because it may be overridden by a
9685 shared library. */
9686 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9687#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9688 || (IS_ELF
8dcea932
L		 9689 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9690 fragP->fr_var))
fbeb56a4
DK		 9691#endif
9692#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9693 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9694 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9695#endif
9696 )
252b5132 9697 {
b98ef147
AM		 9698 /* Symbol is undefined in this segment, or we need to keep a
9699 reloc so that weak symbols can be overridden. */
9700 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9701 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9702 unsigned char *opcode;
9703 int old_fr_fix;
f6af82bd 9704
ee7fcc42 9705 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9706 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9707 else if (size == 2)
f6af82bd 9708 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9709#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9710 else if (need_plt32_p (fragP->fr_symbol))
9711 reloc_type = BFD_RELOC_X86_64_PLT32;
9712#endif
f6af82bd
AM		 9713 else
9714 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9715
ee7fcc42
AM		 9716 old_fr_fix = fragP->fr_fix;
9717 opcode = (unsigned char *) fragP->fr_opcode;
9718
fddf5b5b 9719 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9720 {
fddf5b5b
AM		 9721 case UNCOND_JUMP:
9722 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9723 opcode[0] = 0xe9;
252b5132 9724 fragP->fr_fix += size;
062cd5e7
AS		 9725 fix_new (fragP, old_fr_fix, size,
9726 fragP->fr_symbol,
9727 fragP->fr_offset, 1,
9728 reloc_type);
252b5132
RH		 9729 break;
9730
fddf5b5b 9731 case COND_JUMP86:
412167cb
AM		 9732 if (size == 2
9733 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9734 {
9735 /* Negate the condition, and branch past an
9736 unconditional jump. */
9737 opcode[0] ^= 1;
9738 opcode[1] = 3;
9739 /* Insert an unconditional jump. */
9740 opcode[2] = 0xe9;
9741 /* We added two extra opcode bytes, and have a two byte
9742 offset. */
9743 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9744 fix_new (fragP, old_fr_fix + 2, 2,
9745 fragP->fr_symbol,
9746 fragP->fr_offset, 1,
9747 reloc_type);
fddf5b5b
AM		 9748 break;
9749 }
9750 /* Fall through. */
9751
9752 case COND_JUMP:
412167cb
AM		 9753 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9754 {
3e02c1cc
AM		 9755 fixS *fixP;
9756
412167cb 9757 fragP->fr_fix += 1;
3e02c1cc
AM		 9758 fixP = fix_new (fragP, old_fr_fix, 1,
9759 fragP->fr_symbol,
9760 fragP->fr_offset, 1,
9761 BFD_RELOC_8_PCREL);
9762 fixP->fx_signed = 1;
412167cb
AM		 9763 break;
9764 }
93c2a809 9765
24eab124 9766 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9767 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9768 opcode[1] = opcode[0] + 0x10;
f6af82bd 9769 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9770 /* We've added an opcode byte. */
9771 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9772 fix_new (fragP, old_fr_fix + 1, size,
9773 fragP->fr_symbol,
9774 fragP->fr_offset, 1,
9775 reloc_type);
252b5132 9776 break;
fddf5b5b
AM		 9777
9778 default:
9779 BAD_CASE (fragP->fr_subtype);
9780 break;
252b5132
RH		 9781 }
9782 frag_wane (fragP);
ee7fcc42 9783 return fragP->fr_fix - old_fr_fix;
252b5132 9784 }
93c2a809 9785
93c2a809
AM		 9786 /* Guess size depending on current relax state. Initially the relax
9787 state will correspond to a short jump and we return 1, because
9788 the variable part of the frag (the branch offset) is one byte
9789 long. However, we can relax a section more than once and in that
9790 case we must either set fr_subtype back to the unrelaxed state,
9791 or return the value for the appropriate branch. */
9792 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9793}
9794
47926f60
KH		 9795/* Called after relax() is finished.
9796
9797 In: Address of frag.
9798 fr_type == rs_machine_dependent.
9799 fr_subtype is what the address relaxed to.
9800
9801 Out: Any fixSs and constants are set up.
9802 Caller will turn frag into a ".space 0". */
9803
252b5132 9804void
7016a5d5
TG		 9805md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9806 fragS *fragP)
252b5132 9807{
29b0f896 9808 unsigned char *opcode;
252b5132 9809 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9810 offsetT target_address;
9811 offsetT opcode_address;
252b5132 9812 unsigned int extension = 0;
847f7ad4 9813 offsetT displacement_from_opcode_start;
252b5132
RH		 9814
9815 opcode = (unsigned char *) fragP->fr_opcode;
9816
47926f60 9817 /* Address we want to reach in file space. */
252b5132 9818 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9819
47926f60 9820 /* Address opcode resides at in file space. */
252b5132
RH		 9821 opcode_address = fragP->fr_address + fragP->fr_fix;
9822
47926f60 9823 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9824 displacement_from_opcode_start = target_address - opcode_address;
9825
fddf5b5b 9826 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9827 {
47926f60
KH		 9828 /* Don't have to change opcode. */
9829 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9830 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9831 }
9832 else
9833 {
9834 if (no_cond_jump_promotion
9835 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9836 as_warn_where (fragP->fr_file, fragP->fr_line,
9837 _("long jump required"));
252b5132 9838
fddf5b5b
AM		 9839 switch (fragP->fr_subtype)
9840 {
9841 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9842 extension = 4; /* 1 opcode + 4 displacement */
9843 opcode[0] = 0xe9;
9844 where_to_put_displacement = &opcode[1];
9845 break;
252b5132 9846
fddf5b5b
AM		 9847 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9848 extension = 2; /* 1 opcode + 2 displacement */
9849 opcode[0] = 0xe9;
9850 where_to_put_displacement = &opcode[1];
9851 break;
252b5132 9852
fddf5b5b
AM		 9853 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9854 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9855 extension = 5; /* 2 opcode + 4 displacement */
9856 opcode[1] = opcode[0] + 0x10;
9857 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9858 where_to_put_displacement = &opcode[2];
9859 break;
252b5132 9860
fddf5b5b
AM		 9861 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9862 extension = 3; /* 2 opcode + 2 displacement */
9863 opcode[1] = opcode[0] + 0x10;
9864 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9865 where_to_put_displacement = &opcode[2];
9866 break;
252b5132 9867
fddf5b5b
AM		 9868 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9869 extension = 4;
9870 opcode[0] ^= 1;
9871 opcode[1] = 3;
9872 opcode[2] = 0xe9;
9873 where_to_put_displacement = &opcode[3];
9874 break;
9875
9876 default:
9877 BAD_CASE (fragP->fr_subtype);
9878 break;
9879 }
252b5132 9880 }
fddf5b5b 9881
7b81dfbb
AJ		 9882 /* If size if less then four we are sure that the operand fits,
9883 but if it's 4, then it could be that the displacement is larger
9884 then -/+ 2GB. */
9885 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9886 && object_64bit
9887 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9888 + ((addressT) 1 << 31))
9889 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9890 {
9891 as_bad_where (fragP->fr_file, fragP->fr_line,
9892 _("jump target out of range"));
9893 /* Make us emit 0. */
9894 displacement_from_opcode_start = extension;
9895 }
47926f60 9896 /* Now put displacement after opcode. */
252b5132
RH		 9897 md_number_to_chars ((char *) where_to_put_displacement,
9898 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9899 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9900 fragP->fr_fix += extension;
9901}
9902\f
7016a5d5 9903/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9904 by our caller that we have all the info we need to fix it up.
9905
7016a5d5
TG		 9906 Parameter valP is the pointer to the value of the bits.
9907
252b5132
RH		 9908 On the 386, immediates, displacements, and data pointers are all in
9909 the same (little-endian) format, so we don't need to care about which
9910 we are handling. */
9911
94f592af 9912void
7016a5d5 9913md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9914{
94f592af 9915 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9916 valueT value = *valP;
252b5132 9917
f86103b7 9918#if !defined (TE_Mach)
93382f6d
AM		 9919 if (fixP->fx_pcrel)
9920 {
9921 switch (fixP->fx_r_type)
9922 {
5865bb77
ILT		 9923 default:
9924 break;
9925
d6ab8113
JB		 9926 case BFD_RELOC_64:
9927 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9928 break;
93382f6d 9929 case BFD_RELOC_32:
ae8887b5 9930 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9931 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9932 break;
9933 case BFD_RELOC_16:
9934 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9935 break;
9936 case BFD_RELOC_8:
9937 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9938 break;
9939 }
9940 }
252b5132 9941
a161fe53 9942 if (fixP->fx_addsy != NULL
31312f95 9943 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9944 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9945 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9946 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9947 && !use_rela_relocations)
252b5132 9948 {
31312f95
AM		 9949 /* This is a hack. There should be a better way to handle this.
9950 This covers for the fact that bfd_install_relocation will
9951 subtract the current location (for partial_inplace, PC relative
9952 relocations); see more below. */
252b5132 9953#ifndef OBJ_AOUT
718ddfc0 9954 if (IS_ELF
252b5132
RH		 9955#ifdef TE_PE
9956 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9957#endif
9958 )
9959 value += fixP->fx_where + fixP->fx_frag->fr_address;
9960#endif
9961#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9962 if (IS_ELF)
252b5132 9963 {
6539b54b 9964 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9965
6539b54b 9966 if ((sym_seg == seg
2f66722d 9967 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9968 && sym_seg != absolute_section))
af65af87 9969 && !generic_force_reloc (fixP))
2f66722d
AM		 9970 {
9971 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9972 bfd_install_relocation subtracts them out again. I think
9973 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9974 it. FIXME. */
9975 value += fixP->fx_where + fixP->fx_frag->fr_address;
9976 }
252b5132
RH		 9977 }
9978#endif
9979#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9980 /* For some reason, the PE format does not store a
9981 section address offset for a PC relative symbol. */
9982 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9983 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9984 value += md_pcrel_from (fixP);
9985#endif
9986 }
fbeb56a4 9987#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9988 if (fixP->fx_addsy != NULL
9989 && S_IS_WEAK (fixP->fx_addsy)
9990 /* PR 16858: Do not modify weak function references. */
9991 && ! fixP->fx_pcrel)
fbeb56a4 9992 {
296a8689
NC		 9993#if !defined (TE_PEP)
9994 /* For x86 PE weak function symbols are neither PC-relative
9995 nor do they set S_IS_FUNCTION. So the only reliable way
9996 to detect them is to check the flags of their containing
9997 section. */
9998 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9999 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10000 ;
10001 else
10002#endif
fbeb56a4
DK		 10003 value -= S_GET_VALUE (fixP->fx_addsy);
10004 }
10005#endif
252b5132
RH		 10006
10007 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10008 and we must not disappoint it. */
252b5132 10009#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10010 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10011 switch (fixP->fx_r_type)
10012 {
10013 case BFD_RELOC_386_PLT32:
3e73aa7c 10014 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10015 /* Make the jump instruction point to the address of the operand. At
10016 runtime we merely add the offset to the actual PLT entry. */
10017 value = -4;
10018 break;
31312f95 10019
13ae64f3
JJ		 10020 case BFD_RELOC_386_TLS_GD:
10021 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10022 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10023 case BFD_RELOC_386_TLS_IE:
10024 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10025 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10026 case BFD_RELOC_X86_64_TLSGD:
10027 case BFD_RELOC_X86_64_TLSLD:
10028 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10029 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10030 value = 0; /* Fully resolved at runtime. No addend. */
10031 /* Fallthrough */
10032 case BFD_RELOC_386_TLS_LE:
10033 case BFD_RELOC_386_TLS_LDO_32:
10034 case BFD_RELOC_386_TLS_LE_32:
10035 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10036 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10037 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10038 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10039 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10040 break;
10041
67a4f2b7
AO		 10042 case BFD_RELOC_386_TLS_DESC_CALL:
10043 case BFD_RELOC_X86_64_TLSDESC_CALL:
10044 value = 0; /* Fully resolved at runtime. No addend. */
10045 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10046 fixP->fx_done = 0;
10047 return;
10048
47926f60
KH		 10049 case BFD_RELOC_VTABLE_INHERIT:
10050 case BFD_RELOC_VTABLE_ENTRY:
10051 fixP->fx_done = 0;
94f592af 10052 return;
47926f60
KH		 10053
10054 default:
10055 break;
10056 }
10057#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10058 *valP = value;
f86103b7 10059#endif /* !defined (TE_Mach) */
3e73aa7c 10060
3e73aa7c 10061 /* Are we finished with this relocation now? */
c6682705 10062 if (fixP->fx_addsy == NULL)
3e73aa7c 10063 fixP->fx_done = 1;
fbeb56a4
DK		 10064#if defined (OBJ_COFF) && defined (TE_PE)
10065 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10066 {
10067 fixP->fx_done = 0;
10068 /* Remember value for tc_gen_reloc. */
10069 fixP->fx_addnumber = value;
10070 /* Clear out the frag for now. */
10071 value = 0;
10072 }
10073#endif
3e73aa7c
JH		 10074 else if (use_rela_relocations)
10075 {
10076 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10077 /* Remember value for tc_gen_reloc. */
10078 fixP->fx_addnumber = value;
3e73aa7c
JH		 10079 value = 0;
10080 }
f86103b7 10081
94f592af 10082 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10083}
252b5132 10084\f
6d4af3c2 10085const char *
499ac353 10086md_atof (int type, char *litP, int *sizeP)
252b5132 10087{
499ac353
NC		 10088 /* This outputs the LITTLENUMs in REVERSE order;
10089 in accord with the bigendian 386. */
10090 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10091}
10092\f
2d545b82 10093static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10094
252b5132 10095static char *
e3bb37b5 10096output_invalid (int c)
252b5132 10097{
3882b010 10098 if (ISPRINT (c))
f9f21a03
L		 10099 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10100 "'%c'", c);
252b5132 10101 else
f9f21a03 10102 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10103 "(0x%x)", (unsigned char) c);
252b5132
RH		 10104 return output_invalid_buf;
10105}
10106
af6bdddf 10107/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10108
10109static const reg_entry *
4d1bb795 10110parse_real_register (char *reg_string, char **end_op)
252b5132 10111{
af6bdddf
AM		 10112 char *s = reg_string;
10113 char *p;
252b5132
RH		 10114 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10115 const reg_entry *r;
10116
10117 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10118 if (*s == REGISTER_PREFIX)
10119 ++s;
10120
10121 if (is_space_char (*s))
10122 ++s;
10123
10124 p = reg_name_given;
af6bdddf 10125 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10126 {
10127 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10128 return (const reg_entry *) NULL;
10129 s++;
252b5132
RH		 10130 }
10131
6588847e
DN		 10132 /* For naked regs, make sure that we are not dealing with an identifier.
10133 This prevents confusing an identifier like `eax_var' with register
10134 `eax'. */
10135 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10136 return (const reg_entry *) NULL;
10137
af6bdddf 10138 *end_op = s;
252b5132
RH		 10139
10140 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10141
5f47d35b 10142 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10143 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10144 {
5f47d35b
AM		 10145 if (is_space_char (*s))
10146 ++s;
10147 if (*s == '(')
10148 {
af6bdddf 10149 ++s;
5f47d35b
AM		 10150 if (is_space_char (*s))
10151 ++s;
10152 if (*s >= '0' && *s <= '7')
10153 {
db557034 10154 int fpr = *s - '0';
af6bdddf 10155 ++s;
5f47d35b
AM		 10156 if (is_space_char (*s))
10157 ++s;
10158 if (*s == ')')
10159 {
10160 *end_op = s + 1;
1e9cc1c2 10161 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10162 know (r);
10163 return r + fpr;
5f47d35b 10164 }
5f47d35b 10165 }
47926f60 10166 /* We have "%st(" then garbage. */
5f47d35b
AM		 10167 return (const reg_entry *) NULL;
10168 }
10169 }
10170
a60de03c
JB		 10171 if (r == NULL || allow_pseudo_reg)
10172 return r;
10173
0dfbf9d7 10174 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10175 return (const reg_entry *) NULL;
10176
dc821c5f 10177 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10178 || r->reg_type.bitfield.sreg3
10179 || r->reg_type.bitfield.control
10180 || r->reg_type.bitfield.debug
10181 || r->reg_type.bitfield.test)
10182 && !cpu_arch_flags.bitfield.cpui386)
10183 return (const reg_entry *) NULL;
10184
ca0d63fe 10185 if (r->reg_type.bitfield.tbyte
309d3373
JB		 10186 && !cpu_arch_flags.bitfield.cpu8087
10187 && !cpu_arch_flags.bitfield.cpu287
10188 && !cpu_arch_flags.bitfield.cpu387)
10189 return (const reg_entry *) NULL;
10190
1848e567 10191 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 10192 return (const reg_entry *) NULL;
10193
1b54b8d7 10194 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 10195 return (const reg_entry *) NULL;
10196
1b54b8d7 10197 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 10198 return (const reg_entry *) NULL;
10199
1b54b8d7 10200 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 10201 return (const reg_entry *) NULL;
10202
10203 if (r->reg_type.bitfield.regmask
10204 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 10205 return (const reg_entry *) NULL;
10206
db51cc60 10207 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10208 if (!allow_index_reg
db51cc60
L		 10209 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10210 return (const reg_entry *) NULL;
10211
43234a1e
L		 10212 /* Upper 16 vector register is only available with VREX in 64bit
10213 mode. */
10214 if ((r->reg_flags & RegVRex))
10215 {
86fa6981
L		 10216 if (i.vec_encoding == vex_encoding_default)
10217 i.vec_encoding = vex_encoding_evex;
10218
43234a1e 10219 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 10220 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 10221 || flag_code != CODE_64BIT)
10222 return (const reg_entry *) NULL;
43234a1e
L		 10223 }
10224
a60de03c 10225 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10226 || r->reg_type.bitfield.qword)
40fb9820 10227 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10228 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10229 && flag_code != CODE_64BIT)
20f0a1fc 10230 return (const reg_entry *) NULL;
1ae00879 10231
b7240065
JB		 10232 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10233 return (const reg_entry *) NULL;
10234
252b5132
RH		 10235 return r;
10236}
4d1bb795
JB		 10237
10238/* REG_STRING starts *before* REGISTER_PREFIX. */
10239
10240static const reg_entry *
10241parse_register (char *reg_string, char **end_op)
10242{
10243 const reg_entry *r;
10244
10245 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10246 r = parse_real_register (reg_string, end_op);
10247 else
10248 r = NULL;
10249 if (!r)
10250 {
10251 char *save = input_line_pointer;
10252 char c;
10253 symbolS *symbolP;
10254
10255 input_line_pointer = reg_string;
d02603dc 10256 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10257 symbolP = symbol_find (reg_string);
10258 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10259 {
10260 const expressionS *e = symbol_get_value_expression (symbolP);
10261
0398aac5 10262 know (e->X_op == O_register);
4eed87de 10263 know (e->X_add_number >= 0
c3fe08fa 10264 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10265 r = i386_regtab + e->X_add_number;
d3bb6b49 10266 if ((r->reg_flags & RegVRex))
86fa6981 10267 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10268 *end_op = input_line_pointer;
10269 }
10270 *input_line_pointer = c;
10271 input_line_pointer = save;
10272 }
10273 return r;
10274}
10275
10276int
10277i386_parse_name (char *name, expressionS *e, char *nextcharP)
10278{
10279 const reg_entry *r;
10280 char *end = input_line_pointer;
10281
10282 *end = *nextcharP;
10283 r = parse_register (name, &input_line_pointer);
10284 if (r && end <= input_line_pointer)
10285 {
10286 *nextcharP = *input_line_pointer;
10287 *input_line_pointer = 0;
10288 e->X_op = O_register;
10289 e->X_add_number = r - i386_regtab;
10290 return 1;
10291 }
10292 input_line_pointer = end;
10293 *end = 0;
ee86248c 10294 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10295}
10296
10297void
10298md_operand (expressionS *e)
10299{
ee86248c
JB		 10300 char *end;
10301 const reg_entry *r;
4d1bb795 10302
ee86248c
JB		 10303 switch (*input_line_pointer)
10304 {
10305 case REGISTER_PREFIX:
10306 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10307 if (r)
10308 {
10309 e->X_op = O_register;
10310 e->X_add_number = r - i386_regtab;
10311 input_line_pointer = end;
10312 }
ee86248c
JB		 10313 break;
10314
10315 case '[':
9c2799c2 10316 gas_assert (intel_syntax);
ee86248c
JB		 10317 end = input_line_pointer++;
10318 expression (e);
10319 if (*input_line_pointer == ']')
10320 {
10321 ++input_line_pointer;
10322 e->X_op_symbol = make_expr_symbol (e);
10323 e->X_add_symbol = NULL;
10324 e->X_add_number = 0;
10325 e->X_op = O_index;
10326 }
10327 else
10328 {
10329 e->X_op = O_absent;
10330 input_line_pointer = end;
10331 }
10332 break;
4d1bb795
JB		 10333 }
10334}
10335
252b5132 10336\f
4cc782b5 10337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10338const char *md_shortopts = "kVQ:sqnO::";
252b5132 10339#else
b6f8c7c4 10340const char *md_shortopts = "qnO::";
252b5132 10341#endif
6e0b89ee 10342
3e73aa7c 10343#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10344#define OPTION_64 (OPTION_MD_BASE + 1)
10345#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10346#define OPTION_MARCH (OPTION_MD_BASE + 3)
10347#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10348#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10349#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10350#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10351#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10352#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10353#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10354#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10355#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10356#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10357#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10358#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10359#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10360#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10361#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10362#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10363#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10364#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10365#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10366#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10367#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10368
99ad8390
NC		 10369struct option md_longopts[] =
10370{
3e73aa7c 10371 {"32", no_argument, NULL, OPTION_32},
321098a5 10372#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10373 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10374 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10375#endif
10376#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10377 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10378 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10379#endif
b3b91714 10380 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10381 {"march", required_argument, NULL, OPTION_MARCH},
10382 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10383 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10384 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10385 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10386 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10387 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10388 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10389 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10390 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10391 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10392 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10393 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10394# if defined (TE_PE) || defined (TE_PEP)
10395 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10396#endif
d1982f93 10397 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10398 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10399 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10400 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10401 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10402 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10403 {NULL, no_argument, NULL, 0}
10404};
10405size_t md_longopts_size = sizeof (md_longopts);
10406
10407int
17b9d67d 10408md_parse_option (int c, const char *arg)
252b5132 10409{
91d6fa6a 10410 unsigned int j;
293f5f65 10411 char *arch, *next, *saved;
9103f4f4 10412
252b5132
RH		 10413 switch (c)
10414 {
12b55ccc
L		 10415 case 'n':
10416 optimize_align_code = 0;
10417 break;
10418
a38cf1db
AM		 10419 case 'q':
10420 quiet_warnings = 1;
252b5132
RH		 10421 break;
10422
10423#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10424 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10425 should be emitted or not. FIXME: Not implemented. */
10426 case 'Q':
252b5132
RH		 10427 break;
10428
10429 /* -V: SVR4 argument to print version ID. */
10430 case 'V':
10431 print_version_id ();
10432 break;
10433
a38cf1db
AM		 10434 /* -k: Ignore for FreeBSD compatibility. */
10435 case 'k':
252b5132 10436 break;
4cc782b5
ILT		 10437
10438 case 's':
10439 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10440 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10441 break;
8dcea932
L		 10442
10443 case OPTION_MSHARED:
10444 shared = 1;
10445 break;
99ad8390 10446#endif
321098a5 10447#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10448 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10449 case OPTION_64:
10450 {
10451 const char **list, **l;
10452
3e73aa7c
JH		 10453 list = bfd_target_list ();
10454 for (l = list; *l != NULL; l++)
8620418b 10455 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10456 || strcmp (*l, "coff-x86-64") == 0
10457 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10458 || strcmp (*l, "pei-x86-64") == 0
10459 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10460 {
10461 default_arch = "x86_64";
10462 break;
10463 }
3e73aa7c 10464 if (*l == NULL)
2b5d6a91 10465 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10466 free (list);
10467 }
10468 break;
10469#endif
252b5132 10470
351f65ca 10471#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10472 case OPTION_X32:
351f65ca
L		 10473 if (IS_ELF)
10474 {
10475 const char **list, **l;
10476
10477 list = bfd_target_list ();
10478 for (l = list; *l != NULL; l++)
10479 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10480 {
10481 default_arch = "x86_64:32";
10482 break;
10483 }
10484 if (*l == NULL)
2b5d6a91 10485 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10486 free (list);
10487 }
10488 else
10489 as_fatal (_("32bit x86_64 is only supported for ELF"));
10490 break;
10491#endif
10492
6e0b89ee
AM		 10493 case OPTION_32:
10494 default_arch = "i386";
10495 break;
10496
b3b91714
AM		 10497 case OPTION_DIVIDE:
10498#ifdef SVR4_COMMENT_CHARS
10499 {
10500 char *n, *t;
10501 const char *s;
10502
add39d23 10503 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10504 t = n;
10505 for (s = i386_comment_chars; *s != '\0'; s++)
10506 if (*s != '/')
10507 *t++ = *s;
10508 *t = '\0';
10509 i386_comment_chars = n;
10510 }
10511#endif
10512 break;
10513
9103f4f4 10514 case OPTION_MARCH:
293f5f65
L		 10515 saved = xstrdup (arg);
10516 arch = saved;
10517 /* Allow -march=+nosse. */
10518 if (*arch == '+')
10519 arch++;
6305a203 10520 do
9103f4f4 10521 {
6305a203 10522 if (*arch == '.')
2b5d6a91 10523 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10524 next = strchr (arch, '+');
10525 if (next)
10526 *next++ = '\0';
91d6fa6a 10527 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10528 {
91d6fa6a 10529 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10530 {
6305a203 10531 /* Processor. */
1ded5609
JB		 10532 if (! cpu_arch[j].flags.bitfield.cpui386)
10533 continue;
10534
91d6fa6a 10535 cpu_arch_name = cpu_arch[j].name;
6305a203 10536 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10537 cpu_arch_flags = cpu_arch[j].flags;
10538 cpu_arch_isa = cpu_arch[j].type;
10539 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10540 if (!cpu_arch_tune_set)
10541 {
10542 cpu_arch_tune = cpu_arch_isa;
10543 cpu_arch_tune_flags = cpu_arch_isa_flags;
10544 }
10545 break;
10546 }
91d6fa6a
NC		 10547 else if (*cpu_arch [j].name == '.'
10548 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10549 {
33eaf5de 10550 /* ISA extension. */
6305a203 10551 i386_cpu_flags flags;
309d3373 10552
293f5f65
L		 10553 flags = cpu_flags_or (cpu_arch_flags,
10554 cpu_arch[j].flags);
81486035 10555
5b64d091 10556 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10557 {
10558 if (cpu_sub_arch_name)
10559 {
10560 char *name = cpu_sub_arch_name;
10561 cpu_sub_arch_name = concat (name,
91d6fa6a 10562 cpu_arch[j].name,
1bf57e9f 10563 (const char *) NULL);
6305a203
L		 10564 free (name);
10565 }
10566 else
91d6fa6a 10567 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10568 cpu_arch_flags = flags;
a586129e 10569 cpu_arch_isa_flags = flags;
6305a203 10570 }
0089dace
L		 10571 else
10572 cpu_arch_isa_flags
10573 = cpu_flags_or (cpu_arch_isa_flags,
10574 cpu_arch[j].flags);
6305a203 10575 break;
ccc9c027 10576 }
9103f4f4 10577 }
6305a203 10578
293f5f65
L		 10579 if (j >= ARRAY_SIZE (cpu_arch))
10580 {
33eaf5de 10581 /* Disable an ISA extension. */
293f5f65
L		 10582 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10583 if (strcmp (arch, cpu_noarch [j].name) == 0)
10584 {
10585 i386_cpu_flags flags;
10586
10587 flags = cpu_flags_and_not (cpu_arch_flags,
10588 cpu_noarch[j].flags);
10589 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10590 {
10591 if (cpu_sub_arch_name)
10592 {
10593 char *name = cpu_sub_arch_name;
10594 cpu_sub_arch_name = concat (arch,
10595 (const char *) NULL);
10596 free (name);
10597 }
10598 else
10599 cpu_sub_arch_name = xstrdup (arch);
10600 cpu_arch_flags = flags;
10601 cpu_arch_isa_flags = flags;
10602 }
10603 break;
10604 }
10605
10606 if (j >= ARRAY_SIZE (cpu_noarch))
10607 j = ARRAY_SIZE (cpu_arch);
10608 }
10609
91d6fa6a 10610 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10611 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10612
10613 arch = next;
9103f4f4 10614 }
293f5f65
L		 10615 while (next != NULL);
10616 free (saved);
9103f4f4
L		 10617 break;
10618
10619 case OPTION_MTUNE:
10620 if (*arg == '.')
2b5d6a91 10621 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10622 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10623 {
91d6fa6a 10624 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10625 {
ccc9c027 10626 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10627 cpu_arch_tune = cpu_arch [j].type;
10628 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10629 break;
10630 }
10631 }
91d6fa6a 10632 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10633 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10634 break;
10635
1efbbeb4
L		 10636 case OPTION_MMNEMONIC:
10637 if (strcasecmp (arg, "att") == 0)
10638 intel_mnemonic = 0;
10639 else if (strcasecmp (arg, "intel") == 0)
10640 intel_mnemonic = 1;
10641 else
2b5d6a91 10642 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10643 break;
10644
10645 case OPTION_MSYNTAX:
10646 if (strcasecmp (arg, "att") == 0)
10647 intel_syntax = 0;
10648 else if (strcasecmp (arg, "intel") == 0)
10649 intel_syntax = 1;
10650 else
2b5d6a91 10651 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10652 break;
10653
10654 case OPTION_MINDEX_REG:
10655 allow_index_reg = 1;
10656 break;
10657
10658 case OPTION_MNAKED_REG:
10659 allow_naked_reg = 1;
10660 break;
10661
c0f3af97
L		 10662 case OPTION_MSSE2AVX:
10663 sse2avx = 1;
10664 break;
10665
daf50ae7
L		 10666 case OPTION_MSSE_CHECK:
10667 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10668 sse_check = check_error;
daf50ae7 10669 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10670 sse_check = check_warning;
daf50ae7 10671 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10672 sse_check = check_none;
daf50ae7 10673 else
2b5d6a91 10674 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10675 break;
10676
7bab8ab5
JB		 10677 case OPTION_MOPERAND_CHECK:
10678 if (strcasecmp (arg, "error") == 0)
10679 operand_check = check_error;
10680 else if (strcasecmp (arg, "warning") == 0)
10681 operand_check = check_warning;
10682 else if (strcasecmp (arg, "none") == 0)
10683 operand_check = check_none;
10684 else
10685 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10686 break;
10687
539f890d
L		 10688 case OPTION_MAVXSCALAR:
10689 if (strcasecmp (arg, "128") == 0)
10690 avxscalar = vex128;
10691 else if (strcasecmp (arg, "256") == 0)
10692 avxscalar = vex256;
10693 else
2b5d6a91 10694 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10695 break;
10696
7e8b059b
L		 10697 case OPTION_MADD_BND_PREFIX:
10698 add_bnd_prefix = 1;
10699 break;
10700
43234a1e
L		 10701 case OPTION_MEVEXLIG:
10702 if (strcmp (arg, "128") == 0)
10703 evexlig = evexl128;
10704 else if (strcmp (arg, "256") == 0)
10705 evexlig = evexl256;
10706 else if (strcmp (arg, "512") == 0)
10707 evexlig = evexl512;
10708 else
10709 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10710 break;
10711
d3d3c6db
IT		 10712 case OPTION_MEVEXRCIG:
10713 if (strcmp (arg, "rne") == 0)
10714 evexrcig = rne;
10715 else if (strcmp (arg, "rd") == 0)
10716 evexrcig = rd;
10717 else if (strcmp (arg, "ru") == 0)
10718 evexrcig = ru;
10719 else if (strcmp (arg, "rz") == 0)
10720 evexrcig = rz;
10721 else
10722 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10723 break;
10724
43234a1e
L		 10725 case OPTION_MEVEXWIG:
10726 if (strcmp (arg, "0") == 0)
10727 evexwig = evexw0;
10728 else if (strcmp (arg, "1") == 0)
10729 evexwig = evexw1;
10730 else
10731 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10732 break;
10733
167ad85b
TG		 10734# if defined (TE_PE) || defined (TE_PEP)
10735 case OPTION_MBIG_OBJ:
10736 use_big_obj = 1;
10737 break;
10738#endif
10739
d1982f93 10740 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10741 if (strcasecmp (arg, "yes") == 0)
10742 omit_lock_prefix = 1;
10743 else if (strcasecmp (arg, "no") == 0)
10744 omit_lock_prefix = 0;
10745 else
10746 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10747 break;
10748
e4e00185
AS		 10749 case OPTION_MFENCE_AS_LOCK_ADD:
10750 if (strcasecmp (arg, "yes") == 0)
10751 avoid_fence = 1;
10752 else if (strcasecmp (arg, "no") == 0)
10753 avoid_fence = 0;
10754 else
10755 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10756 break;
10757
0cb4071e
L		 10758 case OPTION_MRELAX_RELOCATIONS:
10759 if (strcasecmp (arg, "yes") == 0)
10760 generate_relax_relocations = 1;
10761 else if (strcasecmp (arg, "no") == 0)
10762 generate_relax_relocations = 0;
10763 else
10764 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10765 break;
10766
5db04b09 10767 case OPTION_MAMD64:
e89c5eaa 10768 intel64 = 0;
5db04b09
L		 10769 break;
10770
10771 case OPTION_MINTEL64:
e89c5eaa 10772 intel64 = 1;
5db04b09
L		 10773 break;
10774
b6f8c7c4
L		 10775 case 'O':
10776 if (arg == NULL)
10777 {
10778 optimize = 1;
10779 /* Turn off -Os. */
10780 optimize_for_space = 0;
10781 }
10782 else if (*arg == 's')
10783 {
10784 optimize_for_space = 1;
10785 /* Turn on all encoding optimizations. */
10786 optimize = -1;
10787 }
10788 else
10789 {
10790 optimize = atoi (arg);
10791 /* Turn off -Os. */
10792 optimize_for_space = 0;
10793 }
10794 break;
10795
252b5132
RH		 10796 default:
10797 return 0;
10798 }
10799 return 1;
10800}
10801
8a2c8fef
L		 10802#define MESSAGE_TEMPLATE \
10803" "
10804
293f5f65
L		 10805static char *
10806output_message (FILE *stream, char *p, char *message, char *start,
10807 int *left_p, const char *name, int len)
10808{
10809 int size = sizeof (MESSAGE_TEMPLATE);
10810 int left = *left_p;
10811
10812 /* Reserve 2 spaces for ", " or ",\0" */
10813 left -= len + 2;
10814
10815 /* Check if there is any room. */
10816 if (left >= 0)
10817 {
10818 if (p != start)
10819 {
10820 *p++ = ',';
10821 *p++ = ' ';
10822 }
10823 p = mempcpy (p, name, len);
10824 }
10825 else
10826 {
10827 /* Output the current message now and start a new one. */
10828 *p++ = ',';
10829 *p = '\0';
10830 fprintf (stream, "%s\n", message);
10831 p = start;
10832 left = size - (start - message) - len - 2;
10833
10834 gas_assert (left >= 0);
10835
10836 p = mempcpy (p, name, len);
10837 }
10838
10839 *left_p = left;
10840 return p;
10841}
10842
8a2c8fef 10843static void
1ded5609 10844show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10845{
10846 static char message[] = MESSAGE_TEMPLATE;
10847 char *start = message + 27;
10848 char *p;
10849 int size = sizeof (MESSAGE_TEMPLATE);
10850 int left;
10851 const char *name;
10852 int len;
10853 unsigned int j;
10854
10855 p = start;
10856 left = size - (start - message);
10857 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10858 {
10859 /* Should it be skipped? */
10860 if (cpu_arch [j].skip)
10861 continue;
10862
10863 name = cpu_arch [j].name;
10864 len = cpu_arch [j].len;
10865 if (*name == '.')
10866 {
10867 /* It is an extension. Skip if we aren't asked to show it. */
10868 if (ext)
10869 {
10870 name++;
10871 len--;
10872 }
10873 else
10874 continue;
10875 }
10876 else if (ext)
10877 {
10878 /* It is an processor. Skip if we show only extension. */
10879 continue;
10880 }
1ded5609
JB		 10881 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10882 {
10883 /* It is an impossible processor - skip. */
10884 continue;
10885 }
8a2c8fef 10886
293f5f65 10887 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10888 }
10889
293f5f65
L		 10890 /* Display disabled extensions. */
10891 if (ext)
10892 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10893 {
10894 name = cpu_noarch [j].name;
10895 len = cpu_noarch [j].len;
10896 p = output_message (stream, p, message, start, &left, name,
10897 len);
10898 }
10899
8a2c8fef
L		 10900 *p = '\0';
10901 fprintf (stream, "%s\n", message);
10902}
10903
252b5132 10904void
8a2c8fef 10905md_show_usage (FILE *stream)
252b5132 10906{
4cc782b5
ILT		 10907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10908 fprintf (stream, _("\
a38cf1db
AM		 10909 -Q ignored\n\
10910 -V print assembler version number\n\
b3b91714
AM		 10911 -k ignored\n"));
10912#endif
10913 fprintf (stream, _("\
12b55ccc 10914 -n Do not optimize code alignment\n\
b3b91714
AM		 10915 -q quieten some warnings\n"));
10916#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10917 fprintf (stream, _("\
a38cf1db 10918 -s ignored\n"));
b3b91714 10919#endif
321098a5
L		 10920#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10921 || defined (TE_PE) || defined (TE_PEP))
751d281c 10922 fprintf (stream, _("\
570561f7 10923 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10924#endif
b3b91714
AM		 10925#ifdef SVR4_COMMENT_CHARS
10926 fprintf (stream, _("\
10927 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10928#else
10929 fprintf (stream, _("\
b3b91714 10930 --divide ignored\n"));
4cc782b5 10931#endif
9103f4f4 10932 fprintf (stream, _("\
6305a203 10933 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10934 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10935 show_arch (stream, 0, 1);
8a2c8fef
L		 10936 fprintf (stream, _("\
10937 EXTENSION is combination of:\n"));
1ded5609 10938 show_arch (stream, 1, 0);
6305a203 10939 fprintf (stream, _("\
8a2c8fef 10940 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10941 show_arch (stream, 0, 0);
ba104c83 10942 fprintf (stream, _("\
c0f3af97
L		 10943 -msse2avx encode SSE instructions with VEX prefix\n"));
10944 fprintf (stream, _("\
daf50ae7
L		 10945 -msse-check=[none|error|warning]\n\
10946 check SSE instructions\n"));
10947 fprintf (stream, _("\
7bab8ab5
JB		 10948 -moperand-check=[none|error|warning]\n\
10949 check operand combinations for validity\n"));
10950 fprintf (stream, _("\
539f890d
L		 10951 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10952 length\n"));
10953 fprintf (stream, _("\
43234a1e
L		 10954 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10955 length\n"));
10956 fprintf (stream, _("\
10957 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10958 for EVEX.W bit ignored instructions\n"));
10959 fprintf (stream, _("\
d3d3c6db
IT		 10960 -mevexrcig=[rne|rd|ru|rz]\n\
10961 encode EVEX instructions with specific EVEX.RC value\n\
10962 for SAE-only ignored instructions\n"));
10963 fprintf (stream, _("\
ba104c83
L		 10964 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10965 fprintf (stream, _("\
10966 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10967 fprintf (stream, _("\
10968 -mindex-reg support pseudo index registers\n"));
10969 fprintf (stream, _("\
10970 -mnaked-reg don't require `%%' prefix for registers\n"));
10971 fprintf (stream, _("\
7e8b059b 10972 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10973 fprintf (stream, _("\
10974 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10975# if defined (TE_PE) || defined (TE_PEP)
10976 fprintf (stream, _("\
10977 -mbig-obj generate big object files\n"));
10978#endif
d022bddd
IT		 10979 fprintf (stream, _("\
10980 -momit-lock-prefix=[no|yes]\n\
10981 strip all lock prefixes\n"));
5db04b09 10982 fprintf (stream, _("\
e4e00185
AS		 10983 -mfence-as-lock-add=[no|yes]\n\
10984 encode lfence, mfence and sfence as\n\
10985 lock addl $0x0, (%%{re}sp)\n"));
10986 fprintf (stream, _("\
0cb4071e
L		 10987 -mrelax-relocations=[no|yes]\n\
10988 generate relax relocations\n"));
10989 fprintf (stream, _("\
5db04b09
L		 10990 -mamd64 accept only AMD64 ISA\n"));
10991 fprintf (stream, _("\
10992 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10993}
10994
3e73aa7c 10995#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10996 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10997 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10998
10999/* Pick the target format to use. */
11000
47926f60 11001const char *
e3bb37b5 11002i386_target_format (void)
252b5132 11003{
351f65ca
L		 11004 if (!strncmp (default_arch, "x86_64", 6))
11005 {
11006 update_code_flag (CODE_64BIT, 1);
11007 if (default_arch[6] == '\0')
7f56bc95 11008 x86_elf_abi = X86_64_ABI;
351f65ca 11009 else
7f56bc95 11010 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11011 }
3e73aa7c 11012 else if (!strcmp (default_arch, "i386"))
78f12dd3 11013 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11014 else if (!strcmp (default_arch, "iamcu"))
11015 {
11016 update_code_flag (CODE_32BIT, 1);
11017 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11018 {
11019 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11020 cpu_arch_name = "iamcu";
11021 cpu_sub_arch_name = NULL;
11022 cpu_arch_flags = iamcu_flags;
11023 cpu_arch_isa = PROCESSOR_IAMCU;
11024 cpu_arch_isa_flags = iamcu_flags;
11025 if (!cpu_arch_tune_set)
11026 {
11027 cpu_arch_tune = cpu_arch_isa;
11028 cpu_arch_tune_flags = cpu_arch_isa_flags;
11029 }
11030 }
8d471ec1 11031 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11032 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11033 cpu_arch_name);
11034 }
3e73aa7c 11035 else
2b5d6a91 11036 as_fatal (_("unknown architecture"));
89507696
JB		 11037
11038 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11039 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11040 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11041 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11042
252b5132
RH		 11043 switch (OUTPUT_FLAVOR)
11044 {
9384f2ff 11045#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11046 case bfd_target_aout_flavour:
47926f60 11047 return AOUT_TARGET_FORMAT;
4c63da97 11048#endif
9384f2ff
AM		 11049#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11050# if defined (TE_PE) || defined (TE_PEP)
11051 case bfd_target_coff_flavour:
167ad85b
TG		 11052 if (flag_code == CODE_64BIT)
11053 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11054 else
11055 return "pe-i386";
9384f2ff 11056# elif defined (TE_GO32)
0561d57c
JK		 11057 case bfd_target_coff_flavour:
11058 return "coff-go32";
9384f2ff 11059# else
252b5132
RH		 11060 case bfd_target_coff_flavour:
11061 return "coff-i386";
9384f2ff 11062# endif
4c63da97 11063#endif
3e73aa7c 11064#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11065 case bfd_target_elf_flavour:
3e73aa7c 11066 {
351f65ca
L		 11067 const char *format;
11068
11069 switch (x86_elf_abi)
4fa24527 11070 {
351f65ca
L		 11071 default:
11072 format = ELF_TARGET_FORMAT;
11073 break;
7f56bc95 11074 case X86_64_ABI:
351f65ca 11075 use_rela_relocations = 1;
4fa24527 11076 object_64bit = 1;
351f65ca
L		 11077 format = ELF_TARGET_FORMAT64;
11078 break;
7f56bc95 11079 case X86_64_X32_ABI:
4fa24527 11080 use_rela_relocations = 1;
351f65ca 11081 object_64bit = 1;
862be3fb 11082 disallow_64bit_reloc = 1;
351f65ca
L		 11083 format = ELF_TARGET_FORMAT32;
11084 break;
4fa24527 11085 }
3632d14b 11086 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11087 {
7f56bc95 11088 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11089 as_fatal (_("Intel L1OM is 64bit only"));
11090 return ELF_TARGET_L1OM_FORMAT;
11091 }
b49f93f6 11092 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11093 {
11094 if (x86_elf_abi != X86_64_ABI)
11095 as_fatal (_("Intel K1OM is 64bit only"));
11096 return ELF_TARGET_K1OM_FORMAT;
11097 }
81486035
L		 11098 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11099 {
11100 if (x86_elf_abi != I386_ABI)
11101 as_fatal (_("Intel MCU is 32bit only"));
11102 return ELF_TARGET_IAMCU_FORMAT;
11103 }
8a9036a4 11104 else
351f65ca 11105 return format;
3e73aa7c 11106 }
e57f8c65
TG		 11107#endif
11108#if defined (OBJ_MACH_O)
11109 case bfd_target_mach_o_flavour:
d382c579
TG		 11110 if (flag_code == CODE_64BIT)
11111 {
11112 use_rela_relocations = 1;
11113 object_64bit = 1;
11114 return "mach-o-x86-64";
11115 }
11116 else
11117 return "mach-o-i386";
4c63da97 11118#endif
252b5132
RH		 11119 default:
11120 abort ();
11121 return NULL;
11122 }
11123}
11124
47926f60 11125#endif /* OBJ_MAYBE_ more than one */
252b5132 11126\f
252b5132 11127symbolS *
7016a5d5 11128md_undefined_symbol (char *name)
252b5132 11129{
18dc2407
ILT		 11130 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11131 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11132 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11133 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11134 {
11135 if (!GOT_symbol)
11136 {
11137 if (symbol_find (name))
11138 as_bad (_("GOT already in symbol table"));
11139 GOT_symbol = symbol_new (name, undefined_section,
11140 (valueT) 0, &zero_address_frag);
11141 };
11142 return GOT_symbol;
11143 }
252b5132
RH		 11144 return 0;
11145}
11146
11147/* Round up a section size to the appropriate boundary. */
47926f60 11148
252b5132 11149valueT
7016a5d5 11150md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11151{
4c63da97
AM		 11152#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11153 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11154 {
11155 /* For a.out, force the section size to be aligned. If we don't do
11156 this, BFD will align it for us, but it will not write out the
11157 final bytes of the section. This may be a bug in BFD, but it is
11158 easier to fix it here since that is how the other a.out targets
11159 work. */
11160 int align;
11161
11162 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11163 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11164 }
252b5132
RH		 11165#endif
11166
11167 return size;
11168}
11169
11170/* On the i386, PC-relative offsets are relative to the start of the
11171 next instruction. That is, the address of the offset, plus its
11172 size, since the offset is always the last part of the insn. */
11173
11174long
e3bb37b5 11175md_pcrel_from (fixS *fixP)
252b5132
RH		 11176{
11177 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11178}
11179
11180#ifndef I386COFF
11181
11182static void
e3bb37b5 11183s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11184{
29b0f896 11185 int temp;
252b5132 11186
8a75718c
JB		 11187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11188 if (IS_ELF)
11189 obj_elf_section_change_hook ();
11190#endif
252b5132
RH		 11191 temp = get_absolute_expression ();
11192 subseg_set (bss_section, (subsegT) temp);
11193 demand_empty_rest_of_line ();
11194}
11195
11196#endif
11197
252b5132 11198void
e3bb37b5 11199i386_validate_fix (fixS *fixp)
252b5132 11200{
02a86693 11201 if (fixp->fx_subsy)
252b5132 11202 {
02a86693 11203 if (fixp->fx_subsy == GOT_symbol)
23df1078 11204 {
02a86693
L		 11205 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11206 {
11207 if (!object_64bit)
11208 abort ();
11209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11210 if (fixp->fx_tcbit2)
56ceb5b5
L		 11211 fixp->fx_r_type = (fixp->fx_tcbit
11212 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11213 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11214 else
11215#endif
11216 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11217 }
d6ab8113 11218 else
02a86693
L		 11219 {
11220 if (!object_64bit)
11221 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11222 else
11223 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11224 }
11225 fixp->fx_subsy = 0;
23df1078 11226 }
252b5132 11227 }
02a86693
L		 11228#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11229 else if (!object_64bit)
11230 {
11231 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11232 && fixp->fx_tcbit2)
11233 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11234 }
11235#endif
252b5132
RH		 11236}
11237
252b5132 11238arelent *
7016a5d5 11239tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11240{
11241 arelent *rel;
11242 bfd_reloc_code_real_type code;
11243
11244 switch (fixp->fx_r_type)
11245 {
8ce3d284 11246#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11247 case BFD_RELOC_SIZE32:
11248 case BFD_RELOC_SIZE64:
11249 if (S_IS_DEFINED (fixp->fx_addsy)
11250 && !S_IS_EXTERNAL (fixp->fx_addsy))
11251 {
11252 /* Resolve size relocation against local symbol to size of
11253 the symbol plus addend. */
11254 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11255 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11256 && !fits_in_unsigned_long (value))
11257 as_bad_where (fixp->fx_file, fixp->fx_line,
11258 _("symbol size computation overflow"));
11259 fixp->fx_addsy = NULL;
11260 fixp->fx_subsy = NULL;
11261 md_apply_fix (fixp, (valueT *) &value, NULL);
11262 return NULL;
11263 }
8ce3d284 11264#endif
1a0670f3 11265 /* Fall through. */
8fd4256d 11266
3e73aa7c
JH		 11267 case BFD_RELOC_X86_64_PLT32:
11268 case BFD_RELOC_X86_64_GOT32:
11269 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11270 case BFD_RELOC_X86_64_GOTPCRELX:
11271 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11272 case BFD_RELOC_386_PLT32:
11273 case BFD_RELOC_386_GOT32:
02a86693 11274 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11275 case BFD_RELOC_386_GOTOFF:
11276 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11277 case BFD_RELOC_386_TLS_GD:
11278 case BFD_RELOC_386_TLS_LDM:
11279 case BFD_RELOC_386_TLS_LDO_32:
11280 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11281 case BFD_RELOC_386_TLS_IE:
11282 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11283 case BFD_RELOC_386_TLS_LE_32:
11284 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11285 case BFD_RELOC_386_TLS_GOTDESC:
11286 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11287 case BFD_RELOC_X86_64_TLSGD:
11288 case BFD_RELOC_X86_64_TLSLD:
11289 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11290 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11291 case BFD_RELOC_X86_64_GOTTPOFF:
11292 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11293 case BFD_RELOC_X86_64_TPOFF64:
11294 case BFD_RELOC_X86_64_GOTOFF64:
11295 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11296 case BFD_RELOC_X86_64_GOT64:
11297 case BFD_RELOC_X86_64_GOTPCREL64:
11298 case BFD_RELOC_X86_64_GOTPC64:
11299 case BFD_RELOC_X86_64_GOTPLT64:
11300 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11301 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11302 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11303 case BFD_RELOC_RVA:
11304 case BFD_RELOC_VTABLE_ENTRY:
11305 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11306#ifdef TE_PE
11307 case BFD_RELOC_32_SECREL:
11308#endif
252b5132
RH		 11309 code = fixp->fx_r_type;
11310 break;
dbbaec26
L		 11311 case BFD_RELOC_X86_64_32S:
11312 if (!fixp->fx_pcrel)
11313 {
11314 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11315 code = fixp->fx_r_type;
11316 break;
11317 }
1a0670f3 11318 /* Fall through. */
252b5132 11319 default:
93382f6d 11320 if (fixp->fx_pcrel)
252b5132 11321 {
93382f6d
AM		 11322 switch (fixp->fx_size)
11323 {
11324 default:
b091f402
AM		 11325 as_bad_where (fixp->fx_file, fixp->fx_line,
11326 _("can not do %d byte pc-relative relocation"),
11327 fixp->fx_size);
93382f6d
AM		 11328 code = BFD_RELOC_32_PCREL;
11329 break;
11330 case 1: code = BFD_RELOC_8_PCREL; break;
11331 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11332 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11333#ifdef BFD64
11334 case 8: code = BFD_RELOC_64_PCREL; break;
11335#endif
93382f6d
AM		 11336 }
11337 }
11338 else
11339 {
11340 switch (fixp->fx_size)
11341 {
11342 default:
b091f402
AM		 11343 as_bad_where (fixp->fx_file, fixp->fx_line,
11344 _("can not do %d byte relocation"),
11345 fixp->fx_size);
93382f6d
AM		 11346 code = BFD_RELOC_32;
11347 break;
11348 case 1: code = BFD_RELOC_8; break;
11349 case 2: code = BFD_RELOC_16; break;
11350 case 4: code = BFD_RELOC_32; break;
937149dd 11351#ifdef BFD64
3e73aa7c 11352 case 8: code = BFD_RELOC_64; break;
937149dd 11353#endif
93382f6d 11354 }
252b5132
RH		 11355 }
11356 break;
11357 }
252b5132 11358
d182319b
JB		 11359 if ((code == BFD_RELOC_32
11360 || code == BFD_RELOC_32_PCREL
11361 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11362 && GOT_symbol
11363 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11364 {
4fa24527 11365 if (!object_64bit)
d6ab8113
JB		 11366 code = BFD_RELOC_386_GOTPC;
11367 else
11368 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11369 }
7b81dfbb
AJ		 11370 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11371 && GOT_symbol
11372 && fixp->fx_addsy == GOT_symbol)
11373 {
11374 code = BFD_RELOC_X86_64_GOTPC64;
11375 }
252b5132 11376
add39d23
TS		 11377 rel = XNEW (arelent);
11378 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11379 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11380
11381 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11382
3e73aa7c
JH		 11383 if (!use_rela_relocations)
11384 {
11385 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11386 vtable entry to be used in the relocation's section offset. */
11387 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11388 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11389#if defined (OBJ_COFF) && defined (TE_PE)
11390 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11391 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11392 else
11393#endif
c6682705 11394 rel->addend = 0;
3e73aa7c
JH		 11395 }
11396 /* Use the rela in 64bit mode. */
252b5132 11397 else
3e73aa7c 11398 {
862be3fb
L		 11399 if (disallow_64bit_reloc)
11400 switch (code)
11401 {
862be3fb
L		 11402 case BFD_RELOC_X86_64_DTPOFF64:
11403 case BFD_RELOC_X86_64_TPOFF64:
11404 case BFD_RELOC_64_PCREL:
11405 case BFD_RELOC_X86_64_GOTOFF64:
11406 case BFD_RELOC_X86_64_GOT64:
11407 case BFD_RELOC_X86_64_GOTPCREL64:
11408 case BFD_RELOC_X86_64_GOTPC64:
11409 case BFD_RELOC_X86_64_GOTPLT64:
11410 case BFD_RELOC_X86_64_PLTOFF64:
11411 as_bad_where (fixp->fx_file, fixp->fx_line,
11412 _("cannot represent relocation type %s in x32 mode"),
11413 bfd_get_reloc_code_name (code));
11414 break;
11415 default:
11416 break;
11417 }
11418
062cd5e7
AS		 11419 if (!fixp->fx_pcrel)
11420 rel->addend = fixp->fx_offset;
11421 else
11422 switch (code)
11423 {
11424 case BFD_RELOC_X86_64_PLT32:
11425 case BFD_RELOC_X86_64_GOT32:
11426 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11427 case BFD_RELOC_X86_64_GOTPCRELX:
11428 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11429 case BFD_RELOC_X86_64_TLSGD:
11430 case BFD_RELOC_X86_64_TLSLD:
11431 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11432 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11433 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11434 rel->addend = fixp->fx_offset - fixp->fx_size;
11435 break;
11436 default:
11437 rel->addend = (section->vma
11438 - fixp->fx_size
11439 + fixp->fx_addnumber
11440 + md_pcrel_from (fixp));
11441 break;
11442 }
3e73aa7c
JH		 11443 }
11444
252b5132
RH		 11445 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11446 if (rel->howto == NULL)
11447 {
11448 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11449 _("cannot represent relocation type %s"),
252b5132
RH		 11450 bfd_get_reloc_code_name (code));
11451 /* Set howto to a garbage value so that we can keep going. */
11452 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11453 gas_assert (rel->howto != NULL);
252b5132
RH		 11454 }
11455
11456 return rel;
11457}
11458
ee86248c 11459#include "tc-i386-intel.c"
54cfded0 11460
a60de03c
JB		 11461void
11462tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11463{
a60de03c
JB		 11464 int saved_naked_reg;
11465 char saved_register_dot;
54cfded0 11466
a60de03c
JB		 11467 saved_naked_reg = allow_naked_reg;
11468 allow_naked_reg = 1;
11469 saved_register_dot = register_chars['.'];
11470 register_chars['.'] = '.';
11471 allow_pseudo_reg = 1;
11472 expression_and_evaluate (exp);
11473 allow_pseudo_reg = 0;
11474 register_chars['.'] = saved_register_dot;
11475 allow_naked_reg = saved_naked_reg;
11476
e96d56a1 11477 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11478 {
a60de03c
JB		 11479 if ((addressT) exp->X_add_number < i386_regtab_size)
11480 {
11481 exp->X_op = O_constant;
11482 exp->X_add_number = i386_regtab[exp->X_add_number]
11483 .dw2_regnum[flag_code >> 1];
11484 }
11485 else
11486 exp->X_op = O_illegal;
54cfded0 11487 }
54cfded0
AM		 11488}
11489
11490void
11491tc_x86_frame_initial_instructions (void)
11492{
a60de03c
JB		 11493 static unsigned int sp_regno[2];
11494
11495 if (!sp_regno[flag_code >> 1])
11496 {
11497 char *saved_input = input_line_pointer;
11498 char sp[][4] = {"esp", "rsp"};
11499 expressionS exp;
a4447b93 11500
a60de03c
JB		 11501 input_line_pointer = sp[flag_code >> 1];
11502 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11503 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11504 sp_regno[flag_code >> 1] = exp.X_add_number;
11505 input_line_pointer = saved_input;
11506 }
a4447b93 11507
61ff971f
L		 11508 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11509 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11510}
d2b2c203 11511
d7921315
L		 11512int
11513x86_dwarf2_addr_size (void)
11514{
11515#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11516 if (x86_elf_abi == X86_64_X32_ABI)
11517 return 4;
11518#endif
11519 return bfd_arch_bits_per_address (stdoutput) / 8;
11520}
11521
d2b2c203
DJ		 11522int
11523i386_elf_section_type (const char *str, size_t len)
11524{
11525 if (flag_code == CODE_64BIT
11526 && len == sizeof ("unwind") - 1
11527 && strncmp (str, "unwind", 6) == 0)
11528 return SHT_X86_64_UNWIND;
11529
11530 return -1;
11531}
bb41ade5 11532
ad5fec3b
EB		 11533#ifdef TE_SOLARIS
11534void
11535i386_solaris_fix_up_eh_frame (segT sec)
11536{
11537 if (flag_code == CODE_64BIT)
11538 elf_section_type (sec) = SHT_X86_64_UNWIND;
11539}
11540#endif
11541
bb41ade5
AM		 11542#ifdef TE_PE
11543void
11544tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11545{
91d6fa6a 11546 expressionS exp;
bb41ade5 11547
91d6fa6a
NC		 11548 exp.X_op = O_secrel;
11549 exp.X_add_symbol = symbol;
11550 exp.X_add_number = 0;
11551 emit_expr (&exp, size);
bb41ade5
AM		 11552}
11553#endif
3b22753a
L		 11554
11555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11556/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11557
01e1a5bc 11558bfd_vma
6d4af3c2 11559x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11560{
11561 if (flag_code == CODE_64BIT)
11562 {
11563 if (letter == 'l')
11564 return SHF_X86_64_LARGE;
11565
8f3bae45 11566 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11567 }
3b22753a 11568 else
8f3bae45 11569 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11570 return -1;
11571}
11572
01e1a5bc 11573bfd_vma
3b22753a
L		 11574x86_64_section_word (char *str, size_t len)
11575{
8620418b 11576 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11577 return SHF_X86_64_LARGE;
11578
11579 return -1;
11580}
11581
11582static void
11583handle_large_common (int small ATTRIBUTE_UNUSED)
11584{
11585 if (flag_code != CODE_64BIT)
11586 {
11587 s_comm_internal (0, elf_common_parse);
11588 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11589 }
11590 else
11591 {
11592 static segT lbss_section;
11593 asection *saved_com_section_ptr = elf_com_section_ptr;
11594 asection *saved_bss_section = bss_section;
11595
11596 if (lbss_section == NULL)
11597 {
11598 flagword applicable;
11599 segT seg = now_seg;
11600 subsegT subseg = now_subseg;
11601
11602 /* The .lbss section is for local .largecomm symbols. */
11603 lbss_section = subseg_new (".lbss", 0);
11604 applicable = bfd_applicable_section_flags (stdoutput);
11605 bfd_set_section_flags (stdoutput, lbss_section,
11606 applicable & SEC_ALLOC);
11607 seg_info (lbss_section)->bss = 1;
11608
11609 subseg_set (seg, subseg);
11610 }
11611
11612 elf_com_section_ptr = &_bfd_elf_large_com_section;
11613 bss_section = lbss_section;
11614
11615 s_comm_internal (0, elf_common_parse);
11616
11617 elf_com_section_ptr = saved_com_section_ptr;
11618 bss_section = saved_bss_section;
11619 }
11620}
11621#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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