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2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
4d456e3d 81static void swap_2_operands (int, int);
e3bb37b5
L		 82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
40fb9820 135 i386_operand_type types[MAX_OPERANDS];
252b5132 136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
2ca3ace5
L		 294/* Register prefix used for error message. */
295static const char *register_prefix = "%";
296
47926f60
KH		 297/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300static char stackop_size = '\0';
eecb386c 301
12b55ccc
L		 302/* Non-zero to optimize code alignment. */
303int optimize_align_code = 1;
304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
5c6af06e 310static const char *cpu_sub_arch_name = NULL;
a38cf1db 311
47926f60 312/* CPU feature flags. */
40fb9820
L		 313static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
314
315/* Bitwise NOT of cpu_arch_flags. */
316static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 317
ccc9c027
L		 318/* If we have selected a cpu we are generating instructions for. */
319static int cpu_arch_tune_set = 0;
320
9103f4f4
L		 321/* Cpu we are generating instructions for. */
322static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
323
324/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 325static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 326
ccc9c027
L		 327/* CPU instruction set architecture used. */
328static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
329
9103f4f4 330/* CPU feature flags of instruction set architecture used. */
40fb9820 331static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 332
fddf5b5b
AM		 333/* If set, conditional jumps are not automatically promoted to handle
334 larger than a byte offset. */
335static unsigned int no_cond_jump_promotion = 0;
336
29b0f896 337/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 338static symbolS *GOT_symbol;
29b0f896 339
a4447b93
RH		 340/* The dwarf2 return column, adjusted for 32 or 64 bit. */
341unsigned int x86_dwarf2_return_column;
342
343/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
344int x86_cie_data_alignment;
345
252b5132 346/* Interface to relax_segment.
fddf5b5b
AM		 347 There are 3 major relax states for 386 jump insns because the
348 different types of jumps add different sizes to frags when we're
349 figuring out what sort of jump to choose to reach a given label. */
252b5132 350
47926f60 351/* Types. */
93c2a809
AM		 352#define UNCOND_JUMP 0
353#define COND_JUMP 1
354#define COND_JUMP86 2
fddf5b5b 355
47926f60 356/* Sizes. */
252b5132
RH		 357#define CODE16 1
358#define SMALL 0
29b0f896 359#define SMALL16 (SMALL | CODE16)
252b5132 360#define BIG 2
29b0f896 361#define BIG16 (BIG | CODE16)
252b5132
RH		 362
363#ifndef INLINE
364#ifdef __GNUC__
365#define INLINE __inline__
366#else
367#define INLINE
368#endif
369#endif
370
fddf5b5b
AM		 371#define ENCODE_RELAX_STATE(type, size) \
372 ((relax_substateT) (((type) << 2) | (size)))
373#define TYPE_FROM_RELAX_STATE(s) \
374 ((s) >> 2)
375#define DISP_SIZE_FROM_RELAX_STATE(s) \
376 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 377
378/* This table is used by relax_frag to promote short jumps to long
379 ones where necessary. SMALL (short) jumps may be promoted to BIG
380 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
381 don't allow a short jump in a 32 bit code segment to be promoted to
382 a 16 bit offset jump because it's slower (requires data size
383 prefix), and doesn't work, unless the destination is in the bottom
384 64k of the code segment (The top 16 bits of eip are zeroed). */
385
386const relax_typeS md_relax_table[] =
387{
24eab124
AM		 388 /* The fields are:
389 1) most positive reach of this state,
390 2) most negative reach of this state,
93c2a809 391 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 392 4) which index into the table to try if we can't fit into this one. */
252b5132 393
fddf5b5b 394 /* UNCOND_JUMP states. */
93c2a809
AM		 395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
397 /* dword jmp adds 4 bytes to frag:
398 0 extra opcode bytes, 4 displacement bytes. */
252b5132 399 {0, 0, 4, 0},
93c2a809
AM		 400 /* word jmp adds 2 byte2 to frag:
401 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 402 {0, 0, 2, 0},
403
93c2a809
AM		 404 /* COND_JUMP states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
409 {0, 0, 5, 0},
fddf5b5b 410 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 411 1 extra opcode byte, 2 displacement bytes. */
412 {0, 0, 3, 0},
413
414 /* COND_JUMP86 states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
419 {0, 0, 5, 0},
420 /* word conditionals add 4 bytes to frag:
421 1 displacement byte and a 3 byte long branch insn. */
422 {0, 0, 4, 0}
252b5132
RH		 423};
424
9103f4f4
L		 425static const arch_entry cpu_arch[] =
426{
427 {"generic32", PROCESSOR_GENERIC32,
40fb9820 428 CPU_GENERIC32_FLAGS },
9103f4f4 429 {"generic64", PROCESSOR_GENERIC64,
40fb9820 430 CPU_GENERIC64_FLAGS },
9103f4f4 431 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 432 CPU_NONE_FLAGS },
9103f4f4 433 {"i186", PROCESSOR_UNKNOWN,
40fb9820 434 CPU_I186_FLAGS },
9103f4f4 435 {"i286", PROCESSOR_UNKNOWN,
40fb9820 436 CPU_I286_FLAGS },
76bc74dc 437 {"i386", PROCESSOR_I386,
40fb9820 438 CPU_I386_FLAGS },
9103f4f4 439 {"i486", PROCESSOR_I486,
40fb9820 440 CPU_I486_FLAGS },
9103f4f4 441 {"i586", PROCESSOR_PENTIUM,
40fb9820 442 CPU_I586_FLAGS },
9103f4f4 443 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 444 CPU_I686_FLAGS },
9103f4f4 445 {"pentium", PROCESSOR_PENTIUM,
40fb9820 446 CPU_I586_FLAGS },
9103f4f4 447 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 448 CPU_I686_FLAGS },
9103f4f4 449 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_P2_FLAGS },
9103f4f4 451 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 452 CPU_P3_FLAGS },
9103f4f4 453 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 454 CPU_P4_FLAGS },
9103f4f4 455 {"prescott", PROCESSOR_NOCONA,
40fb9820 456 CPU_CORE_FLAGS },
9103f4f4 457 {"nocona", PROCESSOR_NOCONA,
40fb9820 458 CPU_NOCONA_FLAGS },
ef05d495 459 {"yonah", PROCESSOR_CORE,
40fb9820 460 CPU_CORE_FLAGS },
ef05d495 461 {"core", PROCESSOR_CORE,
40fb9820 462 CPU_CORE_FLAGS },
ef05d495 463 {"merom", PROCESSOR_CORE2,
40fb9820 464 CPU_CORE2_FLAGS },
ef05d495 465 {"core2", PROCESSOR_CORE2,
40fb9820 466 CPU_CORE2_FLAGS },
9103f4f4 467 {"k6", PROCESSOR_K6,
40fb9820 468 CPU_K6_FLAGS },
9103f4f4 469 {"k6_2", PROCESSOR_K6,
40fb9820 470 CPU_K6_2_FLAGS },
9103f4f4 471 {"athlon", PROCESSOR_ATHLON,
40fb9820 472 CPU_ATHLON_FLAGS },
9103f4f4 473 {"sledgehammer", PROCESSOR_K8,
40fb9820 474 CPU_K8_FLAGS },
9103f4f4 475 {"opteron", PROCESSOR_K8,
40fb9820 476 CPU_K8_FLAGS },
9103f4f4 477 {"k8", PROCESSOR_K8,
40fb9820 478 CPU_K8_FLAGS },
050dfa73 479 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 480 CPU_AMDFAM10_FLAGS },
9103f4f4 481 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 482 CPU_MMX_FLAGS },
9103f4f4 483 {".sse", PROCESSOR_UNKNOWN,
40fb9820 484 CPU_SSE_FLAGS },
9103f4f4 485 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 486 CPU_SSE2_FLAGS },
9103f4f4 487 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_SSE3_FLAGS },
ef05d495 489 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSSE3_FLAGS },
42903f7f 491 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE4_1_FLAGS },
381d071f 493 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE4_2_FLAGS },
381d071f 495 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_SSE4_2_FLAGS },
9103f4f4 497 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_3DNOW_FLAGS },
9103f4f4 499 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_3DNOWA_FLAGS },
9103f4f4 501 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_PADLOCK_FLAGS },
9103f4f4 503 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_SVME_FLAGS },
9103f4f4 505 {".svme", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_SVME_FLAGS },
050dfa73 507 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_SSE4A_FLAGS },
050dfa73 509 {".abm", PROCESSOR_UNKNOWN,
40fb9820 510 CPU_ABM_FLAGS },
e413e4e9
AM		 511};
512
29b0f896
AM		 513const pseudo_typeS md_pseudo_table[] =
514{
515#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
517#else
518 {"align", s_align_ptwo, 0},
519#endif
520 {"arch", set_cpu_arch, 0},
521#ifndef I386COFF
522 {"bss", s_bss, 0},
523#endif
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
527 {"value", cons, 2},
d182319b 528 {"slong", signed_cons, 4},
29b0f896
AM		 529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 537#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
538 {"largecomm", handle_large_common, 0},
07a53e5c 539#else
e3bb37b5 540 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 541 {"loc", dwarf2_directive_loc, 0},
542 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 543#endif
6482c264
NC		 544#ifdef TE_PE
545 {"secrel32", pe_directive_secrel, 0},
546#endif
29b0f896
AM		 547 {0, 0, 0}
548};
549
550/* For interface with expression (). */
551extern char *input_line_pointer;
552
553/* Hash table for instruction mnemonic lookup. */
554static struct hash_control *op_hash;
555
556/* Hash table for register lookup. */
557static struct hash_control *reg_hash;
558\f
252b5132 559void
e3bb37b5 560i386_align_code (fragS *fragP, int count)
252b5132 561{
ce8a8b2f
AM		 562 /* Various efficient no-op patterns for aligning code labels.
563 Note: Don't try to assemble the instructions in the comments.
564 0L and 0w are not legal. */
252b5132
RH		 565 static const char f32_1[] =
566 {0x90}; /* nop */
567 static const char f32_2[] =
ccc9c027 568 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 569 static const char f32_3[] =
570 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
571 static const char f32_4[] =
572 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
573 static const char f32_5[] =
574 {0x90, /* nop */
575 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_6[] =
577 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
578 static const char f32_7[] =
579 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
580 static const char f32_8[] =
581 {0x90, /* nop */
582 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_9[] =
584 {0x89,0xf6, /* movl %esi,%esi */
585 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
586 static const char f32_10[] =
587 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_11[] =
590 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_12[] =
593 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
594 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
595 static const char f32_13[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_14[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 601 static const char f16_3[] =
602 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 603 static const char f16_4[] =
604 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
605 static const char f16_5[] =
606 {0x90, /* nop */
607 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_6[] =
609 {0x89,0xf6, /* mov %si,%si */
610 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
611 static const char f16_7[] =
612 {0x8d,0x74,0x00, /* lea 0(%si),%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_8[] =
615 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 617 static const char jump_31[] =
618 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
619 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
620 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 622 static const char *const f32_patt[] = {
623 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 624 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 625 };
626 static const char *const f16_patt[] = {
76bc74dc 627 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 628 };
ccc9c027
L		 629 /* nopl (%[re]ax) */
630 static const char alt_3[] =
631 {0x0f,0x1f,0x00};
632 /* nopl 0(%[re]ax) */
633 static const char alt_4[] =
634 {0x0f,0x1f,0x40,0x00};
635 /* nopl 0(%[re]ax,%[re]ax,1) */
636 static const char alt_5[] =
637 {0x0f,0x1f,0x44,0x00,0x00};
638 /* nopw 0(%[re]ax,%[re]ax,1) */
639 static const char alt_6[] =
640 {0x66,0x0f,0x1f,0x44,0x00,0x00};
641 /* nopl 0L(%[re]ax) */
642 static const char alt_7[] =
643 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
644 /* nopl 0L(%[re]ax,%[re]ax,1) */
645 static const char alt_8[] =
646 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
647 /* nopw 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_9[] =
649 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
651 static const char alt_10[] =
652 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* data16
654 nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_long_11[] =
656 {0x66,
657 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 /* data16
659 data16
660 nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_long_12[] =
662 {0x66,
663 0x66,
664 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* data16
666 data16
667 data16
668 nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_long_13[] =
670 {0x66,
671 0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_14[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,
684 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
685 /* data16
686 data16
687 data16
688 data16
689 data16
690 nopw %cs:0L(%[re]ax,%[re]ax,1) */
691 static const char alt_long_15[] =
692 {0x66,
693 0x66,
694 0x66,
695 0x66,
696 0x66,
697 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
698 /* nopl 0(%[re]ax,%[re]ax,1)
699 nopw 0(%[re]ax,%[re]ax,1) */
700 static const char alt_short_11[] =
701 {0x0f,0x1f,0x44,0x00,0x00,
702 0x66,0x0f,0x1f,0x44,0x00,0x00};
703 /* nopw 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_12[] =
706 {0x66,0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopl 0L(%[re]ax) */
710 static const char alt_short_13[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
713 /* nopl 0L(%[re]ax)
714 nopl 0L(%[re]ax) */
715 static const char alt_short_14[] =
716 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 /* nopl 0L(%[re]ax)
719 nopl 0L(%[re]ax,%[re]ax,1) */
720 static const char alt_short_15[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
723 static const char *const alt_short_patt[] = {
724 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
725 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
726 alt_short_14, alt_short_15
727 };
728 static const char *const alt_long_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
731 alt_long_14, alt_long_15
732 };
252b5132 733
76bc74dc
L		 734 /* Only align for at least a positive non-zero boundary. */
735 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 736 return;
3e73aa7c 737
ccc9c027
L		 738 /* We need to decide which NOP sequence to use for 32bit and
739 64bit. When -mtune= is used:
4eed87de 740
76bc74dc
L		 741 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
742 PROCESSOR_GENERIC32, f32_patt will be used.
743 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
744 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
745 alt_long_patt will be used.
746 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
747 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 748
76bc74dc
L		 749 When -mtune= isn't used, alt_long_patt will be used if
750 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
751 be used.
ccc9c027
L		 752
753 When -march= or .arch is used, we can't use anything beyond
754 cpu_arch_isa_flags. */
755
756 if (flag_code == CODE_16BIT)
757 {
ccc9c027 758 if (count > 8)
33fef721 759 {
76bc74dc
L		 760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 jump_31, count);
762 /* Adjust jump offset. */
763 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 764 }
76bc74dc
L		 765 else
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
252b5132 768 }
33fef721 769 else
ccc9c027
L		 770 {
771 const char *const *patt = NULL;
772
773 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
774 {
775 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
776 switch (cpu_arch_tune)
777 {
778 case PROCESSOR_UNKNOWN:
779 /* We use cpu_arch_isa_flags to check if we SHOULD
780 optimize for Cpu686. */
40fb9820 781 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 782 patt = alt_long_patt;
ccc9c027
L		 783 else
784 patt = f32_patt;
785 break;
ccc9c027
L		 786 case PROCESSOR_PENTIUMPRO:
787 case PROCESSOR_PENTIUM4:
788 case PROCESSOR_NOCONA:
ef05d495 789 case PROCESSOR_CORE:
76bc74dc
L		 790 case PROCESSOR_CORE2:
791 case PROCESSOR_GENERIC64:
792 patt = alt_long_patt;
793 break;
ccc9c027
L		 794 case PROCESSOR_K6:
795 case PROCESSOR_ATHLON:
796 case PROCESSOR_K8:
4eed87de 797 case PROCESSOR_AMDFAM10:
ccc9c027
L		 798 patt = alt_short_patt;
799 break;
76bc74dc 800 case PROCESSOR_I386:
ccc9c027
L		 801 case PROCESSOR_I486:
802 case PROCESSOR_PENTIUM:
803 case PROCESSOR_GENERIC32:
804 patt = f32_patt;
805 break;
4eed87de 806 }
ccc9c027
L		 807 }
808 else
809 {
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
814 PROCESSOR_UNKNOWN. */
815 abort ();
816 break;
817
76bc74dc 818 case PROCESSOR_I386:
ccc9c027
L		 819 case PROCESSOR_I486:
820 case PROCESSOR_PENTIUM:
ccc9c027
L		 821 case PROCESSOR_K6:
822 case PROCESSOR_ATHLON:
823 case PROCESSOR_K8:
4eed87de 824 case PROCESSOR_AMDFAM10:
ccc9c027
L		 825 case PROCESSOR_GENERIC32:
826 /* We use cpu_arch_isa_flags to check if we CAN optimize
827 for Cpu686. */
40fb9820 828 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 829 patt = alt_short_patt;
830 else
831 patt = f32_patt;
832 break;
76bc74dc
L		 833 case PROCESSOR_PENTIUMPRO:
834 case PROCESSOR_PENTIUM4:
835 case PROCESSOR_NOCONA:
836 case PROCESSOR_CORE:
ef05d495 837 case PROCESSOR_CORE2:
40fb9820 838 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 839 patt = alt_long_patt;
840 else
841 patt = f32_patt;
842 break;
843 case PROCESSOR_GENERIC64:
76bc74dc 844 patt = alt_long_patt;
ccc9c027 845 break;
4eed87de 846 }
ccc9c027
L		 847 }
848
76bc74dc
L		 849 if (patt == f32_patt)
850 {
851 /* If the padding is less than 15 bytes, we use the normal
852 ones. Otherwise, we use a jump instruction and adjust
853 its offset. */
854 if (count < 15)
855 memcpy (fragP->fr_literal + fragP->fr_fix,
856 patt[count - 1], count);
857 else
858 {
859 memcpy (fragP->fr_literal + fragP->fr_fix,
860 jump_31, count);
861 /* Adjust jump offset. */
862 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
863 }
864 }
865 else
866 {
867 /* Maximum length of an instruction is 15 byte. If the
868 padding is greater than 15 bytes and we don't use jump,
869 we have to break it into smaller pieces. */
870 int padding = count;
871 while (padding > 15)
872 {
873 padding -= 15;
874 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
875 patt [14], 15);
876 }
877
878 if (padding)
879 memcpy (fragP->fr_literal + fragP->fr_fix,
880 patt [padding - 1], padding);
881 }
ccc9c027 882 }
33fef721 883 fragP->fr_var = count;
252b5132
RH		 884}
885
c6fb90c8
L		 886static INLINE int
887uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 888{
c6fb90c8
L		 889 switch (size)
890 {
891 case 3:
892 if (x[2])
893 return 0;
894 case 2:
895 if (x[1])
896 return 0;
897 case 1:
898 return !x[0];
899 default:
900 abort ();
901 }
40fb9820
L		 902}
903
c6fb90c8
L		 904static INLINE void
905uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 906{
c6fb90c8
L		 907 switch (size)
908 {
909 case 3:
910 x[2] = v;
911 case 2:
912 x[1] = v;
913 case 1:
914 x[0] = v;
915 break;
916 default:
917 abort ();
918 }
919}
40fb9820 920
c6fb90c8
L		 921static INLINE int
922uints_equal (const unsigned int *x, const unsigned int *y,
923 unsigned int size)
924{
925 switch (size)
926 {
927 case 3:
928 if (x[2] != y [2])
929 return 0;
930 case 2:
931 if (x[1] != y [1])
932 return 0;
933 case 1:
934 return x[0] == y [0];
935 break;
936 default:
937 abort ();
938 }
939}
40fb9820 940
c6fb90c8
L		 941#define UINTS_ALL_ZERO(x) \
942 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
943#define UINTS_SET(x, v) \
944 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
945#define UINTS_CLEAR(x) \
946 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
947#define UINTS_EQUAL(x, y) \
948 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
949
950static INLINE int
951cpu_flags_check_cpu64 (i386_cpu_flags f)
952{
953 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
954 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 955}
956
c6fb90c8 957static INLINE i386_cpu_flags
40fb9820
L		 958cpu_flags_not (i386_cpu_flags x)
959{
c6fb90c8
L		 960 switch (ARRAY_SIZE (x.array))
961 {
962 case 3:
963 x.array [2] = ~x.array [2];
964 case 2:
965 x.array [1] = ~x.array [1];
966 case 1:
967 x.array [0] = ~x.array [0];
968 break;
969 default:
970 abort ();
971 }
40fb9820
L		 972
973#ifdef CpuUnused
974 x.bitfield.unused = 0;
975#endif
976
977 return x;
978}
979
c6fb90c8
L		 980static INLINE i386_cpu_flags
981cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 982{
c6fb90c8
L		 983 switch (ARRAY_SIZE (x.array))
984 {
985 case 3:
986 x.array [2] &= y.array [2];
987 case 2:
988 x.array [1] &= y.array [1];
989 case 1:
990 x.array [0] &= y.array [0];
991 break;
992 default:
993 abort ();
994 }
995 return x;
996}
40fb9820 997
c6fb90c8
L		 998static INLINE i386_cpu_flags
999cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1000{
c6fb90c8 1001 switch (ARRAY_SIZE (x.array))
40fb9820 1002 {
c6fb90c8
L		 1003 case 3:
1004 x.array [2] |= y.array [2];
1005 case 2:
1006 x.array [1] |= y.array [1];
1007 case 1:
1008 x.array [0] |= y.array [0];
40fb9820
L		 1009 break;
1010 default:
1011 abort ();
1012 }
40fb9820
L		 1013 return x;
1014}
1015
1016static int
1017cpu_flags_match (i386_cpu_flags x)
1018{
1019 i386_cpu_flags not = cpu_arch_flags_not;
1020
1021 not.bitfield.cpu64 = 1;
1022 not.bitfield.cpuno64 = 1;
1023
1024 x.bitfield.cpu64 = 0;
1025 x.bitfield.cpuno64 = 0;
1026
c6fb90c8
L		 1027 not = cpu_flags_and (x, not);
1028 return UINTS_ALL_ZERO (not);
40fb9820
L		 1029}
1030
c6fb90c8
L		 1031static INLINE i386_operand_type
1032operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1033{
c6fb90c8
L		 1034 switch (ARRAY_SIZE (x.array))
1035 {
1036 case 3:
1037 x.array [2] &= y.array [2];
1038 case 2:
1039 x.array [1] &= y.array [1];
1040 case 1:
1041 x.array [0] &= y.array [0];
1042 break;
1043 default:
1044 abort ();
1045 }
1046 return x;
40fb9820
L		 1047}
1048
c6fb90c8
L		 1049static INLINE i386_operand_type
1050operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1051{
c6fb90c8 1052 switch (ARRAY_SIZE (x.array))
40fb9820 1053 {
c6fb90c8
L		 1054 case 3:
1055 x.array [2] |= y.array [2];
1056 case 2:
1057 x.array [1] |= y.array [1];
1058 case 1:
1059 x.array [0] |= y.array [0];
40fb9820
L		 1060 break;
1061 default:
1062 abort ();
1063 }
c6fb90c8
L		 1064 return x;
1065}
40fb9820 1066
c6fb90c8
L		 1067static INLINE i386_operand_type
1068operand_type_xor (i386_operand_type x, i386_operand_type y)
1069{
1070 switch (ARRAY_SIZE (x.array))
1071 {
1072 case 3:
1073 x.array [2] ^= y.array [2];
1074 case 2:
1075 x.array [1] ^= y.array [1];
1076 case 1:
1077 x.array [0] ^= y.array [0];
1078 break;
1079 default:
1080 abort ();
1081 }
40fb9820
L		 1082 return x;
1083}
1084
1085static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1086static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1087static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1088static const i386_operand_type reg16_inoutportreg
1089 = OPERAND_TYPE_REG16_INOUTPORTREG;
1090static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1091static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1092static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1093static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1094static const i386_operand_type anydisp
1095 = OPERAND_TYPE_ANYDISP;
1096static const i386_operand_type baseindex = OPERAND_TYPE_BASEINDEX;
1097static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1098static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1099static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1100static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1101static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1102static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1103static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1104static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1105static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1106static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1107
1108enum operand_type
1109{
1110 reg,
40fb9820
L		 1111 imm,
1112 disp,
1113 anymem
1114};
1115
c6fb90c8 1116static INLINE int
40fb9820
L		 1117operand_type_check (i386_operand_type t, enum operand_type c)
1118{
1119 switch (c)
1120 {
1121 case reg:
1122 return (t.bitfield.reg8
1123 || t.bitfield.reg16
1124 || t.bitfield.reg32
1125 || t.bitfield.reg64);
1126
40fb9820
L		 1127 case imm:
1128 return (t.bitfield.imm8
1129 || t.bitfield.imm8s
1130 || t.bitfield.imm16
1131 || t.bitfield.imm32
1132 || t.bitfield.imm32s
1133 || t.bitfield.imm64);
1134
1135 case disp:
1136 return (t.bitfield.disp8
1137 || t.bitfield.disp16
1138 || t.bitfield.disp32
1139 || t.bitfield.disp32s
1140 || t.bitfield.disp64);
1141
1142 case anymem:
1143 return (t.bitfield.disp8
1144 || t.bitfield.disp16
1145 || t.bitfield.disp32
1146 || t.bitfield.disp32s
1147 || t.bitfield.disp64
1148 || t.bitfield.baseindex);
1149
1150 default:
1151 abort ();
1152 }
1153}
1154
c6fb90c8 1155static INLINE int
40fb9820
L		 1156operand_type_match (i386_operand_type overlap,
1157 i386_operand_type given)
1158{
1159 i386_operand_type temp = overlap;
1160
1161 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1162 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1163 return 0;
1164
1165 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1166 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1167}
1168
1169/* If given types r0 and r1 are registers they must be of the same type
1170 unless the expected operand type register overlap is null.
1171 Note that Acc in a template matches every size of reg. */
1172
c6fb90c8 1173static INLINE int
40fb9820
L		 1174operand_type_register_match (i386_operand_type m0,
1175 i386_operand_type g0,
1176 i386_operand_type t0,
1177 i386_operand_type m1,
1178 i386_operand_type g1,
1179 i386_operand_type t1)
1180{
1181 if (!operand_type_check (g0, reg))
1182 return 1;
1183
1184 if (!operand_type_check (g1, reg))
1185 return 1;
1186
1187 if (g0.bitfield.reg8 == g1.bitfield.reg8
1188 && g0.bitfield.reg16 == g1.bitfield.reg16
1189 && g0.bitfield.reg32 == g1.bitfield.reg32
1190 && g0.bitfield.reg64 == g1.bitfield.reg64)
1191 return 1;
1192
1193 if (m0.bitfield.acc)
1194 {
1195 t0.bitfield.reg8 = 1;
1196 t0.bitfield.reg16 = 1;
1197 t0.bitfield.reg32 = 1;
1198 t0.bitfield.reg64 = 1;
1199 }
1200
1201 if (m1.bitfield.acc)
1202 {
1203 t1.bitfield.reg8 = 1;
1204 t1.bitfield.reg16 = 1;
1205 t1.bitfield.reg32 = 1;
1206 t1.bitfield.reg64 = 1;
1207 }
1208
1209 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1210 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1211 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1212 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1213}
1214
252b5132 1215static INLINE unsigned int
40fb9820 1216mode_from_disp_size (i386_operand_type t)
252b5132 1217{
40fb9820
L		 1218 if (t.bitfield.disp8)
1219 return 1;
1220 else if (t.bitfield.disp16
1221 || t.bitfield.disp32
1222 || t.bitfield.disp32s)
1223 return 2;
1224 else
1225 return 0;
252b5132
RH		 1226}
1227
1228static INLINE int
e3bb37b5 1229fits_in_signed_byte (offsetT num)
252b5132
RH		 1230{
1231 return (num >= -128) && (num <= 127);
47926f60 1232}
252b5132
RH		 1233
1234static INLINE int
e3bb37b5 1235fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1236{
1237 return (num & 0xff) == num;
47926f60 1238}
252b5132
RH		 1239
1240static INLINE int
e3bb37b5 1241fits_in_unsigned_word (offsetT num)
252b5132
RH		 1242{
1243 return (num & 0xffff) == num;
47926f60 1244}
252b5132
RH		 1245
1246static INLINE int
e3bb37b5 1247fits_in_signed_word (offsetT num)
252b5132
RH		 1248{
1249 return (-32768 <= num) && (num <= 32767);
47926f60 1250}
2a962e6d 1251
3e73aa7c 1252static INLINE int
e3bb37b5 1253fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1254{
1255#ifndef BFD64
1256 return 1;
1257#else
1258 return (!(((offsetT) -1 << 31) & num)
1259 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1260#endif
1261} /* fits_in_signed_long() */
2a962e6d 1262
3e73aa7c 1263static INLINE int
e3bb37b5 1264fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1265{
1266#ifndef BFD64
1267 return 1;
1268#else
1269 return (num & (((offsetT) 2 << 31) - 1)) == num;
1270#endif
1271} /* fits_in_unsigned_long() */
252b5132 1272
40fb9820 1273static i386_operand_type
e3bb37b5 1274smallest_imm_type (offsetT num)
252b5132 1275{
40fb9820
L		 1276 i386_operand_type t;
1277
c6fb90c8 1278 UINTS_CLEAR (t);
40fb9820
L		 1279 t.bitfield.imm64 = 1;
1280
1281 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1282 {
1283 /* This code is disabled on the 486 because all the Imm1 forms
1284 in the opcode table are slower on the i486. They're the
1285 versions with the implicitly specified single-position
1286 displacement, which has another syntax if you really want to
1287 use that form. */
40fb9820
L		 1288 t.bitfield.imm1 = 1;
1289 t.bitfield.imm8 = 1;
1290 t.bitfield.imm8s = 1;
1291 t.bitfield.imm16 = 1;
1292 t.bitfield.imm32 = 1;
1293 t.bitfield.imm32s = 1;
1294 }
1295 else if (fits_in_signed_byte (num))
1296 {
1297 t.bitfield.imm8 = 1;
1298 t.bitfield.imm8s = 1;
1299 t.bitfield.imm16 = 1;
1300 t.bitfield.imm32 = 1;
1301 t.bitfield.imm32s = 1;
1302 }
1303 else if (fits_in_unsigned_byte (num))
1304 {
1305 t.bitfield.imm8 = 1;
1306 t.bitfield.imm16 = 1;
1307 t.bitfield.imm32 = 1;
1308 t.bitfield.imm32s = 1;
1309 }
1310 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1311 {
1312 t.bitfield.imm16 = 1;
1313 t.bitfield.imm32 = 1;
1314 t.bitfield.imm32s = 1;
1315 }
1316 else if (fits_in_signed_long (num))
1317 {
1318 t.bitfield.imm32 = 1;
1319 t.bitfield.imm32s = 1;
1320 }
1321 else if (fits_in_unsigned_long (num))
1322 t.bitfield.imm32 = 1;
1323
1324 return t;
47926f60 1325}
252b5132 1326
847f7ad4 1327static offsetT
e3bb37b5 1328offset_in_range (offsetT val, int size)
847f7ad4 1329{
508866be 1330 addressT mask;
ba2adb93 1331
847f7ad4
AM		 1332 switch (size)
1333 {
508866be
L		 1334 case 1: mask = ((addressT) 1 << 8) - 1; break;
1335 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1336 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1337#ifdef BFD64
1338 case 8: mask = ((addressT) 2 << 63) - 1; break;
1339#endif
47926f60 1340 default: abort ();
847f7ad4
AM		 1341 }
1342
ba2adb93 1343 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1344 if (!use_rela_relocations)
1345 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1346 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1347
47926f60 1348 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1349 {
1350 char buf1[40], buf2[40];
1351
1352 sprint_value (buf1, val);
1353 sprint_value (buf2, val & mask);
1354 as_warn (_("%s shortened to %s"), buf1, buf2);
1355 }
1356 return val & mask;
1357}
1358
252b5132
RH		 1359/* Returns 0 if attempting to add a prefix where one from the same
1360 class already exists, 1 if non rep/repne added, 2 if rep/repne
1361 added. */
1362static int
e3bb37b5 1363add_prefix (unsigned int prefix)
252b5132
RH		 1364{
1365 int ret = 1;
b1905489 1366 unsigned int q;
252b5132 1367
29b0f896
AM		 1368 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1369 && flag_code == CODE_64BIT)
b1905489 1370 {
161a04f6
L		 1371 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1372 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1373 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1374 ret = 0;
1375 q = REX_PREFIX;
1376 }
3e73aa7c 1377 else
b1905489
JB		 1378 {
1379 switch (prefix)
1380 {
1381 default:
1382 abort ();
1383
1384 case CS_PREFIX_OPCODE:
1385 case DS_PREFIX_OPCODE:
1386 case ES_PREFIX_OPCODE:
1387 case FS_PREFIX_OPCODE:
1388 case GS_PREFIX_OPCODE:
1389 case SS_PREFIX_OPCODE:
1390 q = SEG_PREFIX;
1391 break;
1392
1393 case REPNE_PREFIX_OPCODE:
1394 case REPE_PREFIX_OPCODE:
1395 ret = 2;
1396 /* fall thru */
1397 case LOCK_PREFIX_OPCODE:
1398 q = LOCKREP_PREFIX;
1399 break;
1400
1401 case FWAIT_OPCODE:
1402 q = WAIT_PREFIX;
1403 break;
1404
1405 case ADDR_PREFIX_OPCODE:
1406 q = ADDR_PREFIX;
1407 break;
1408
1409 case DATA_PREFIX_OPCODE:
1410 q = DATA_PREFIX;
1411 break;
1412 }
1413 if (i.prefix[q] != 0)
1414 ret = 0;
1415 }
252b5132 1416
b1905489 1417 if (ret)
252b5132 1418 {
b1905489
JB		 1419 if (!i.prefix[q])
1420 ++i.prefixes;
1421 i.prefix[q] |= prefix;
252b5132 1422 }
b1905489
JB		 1423 else
1424 as_bad (_("same type of prefix used twice"));
252b5132 1425
252b5132
RH		 1426 return ret;
1427}
1428
1429static void
e3bb37b5 1430set_code_flag (int value)
eecb386c 1431{
3e73aa7c 1432 flag_code = value;
40fb9820
L		 1433 if (flag_code == CODE_64BIT)
1434 {
1435 cpu_arch_flags.bitfield.cpu64 = 1;
1436 cpu_arch_flags.bitfield.cpuno64 = 0;
1437 cpu_arch_flags_not.bitfield.cpu64 = 0;
1438 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1439 }
1440 else
1441 {
1442 cpu_arch_flags.bitfield.cpu64 = 0;
1443 cpu_arch_flags.bitfield.cpuno64 = 1;
1444 cpu_arch_flags_not.bitfield.cpu64 = 1;
1445 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1446 }
1447 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1448 {
1449 as_bad (_("64bit mode not supported on this CPU."));
1450 }
40fb9820 1451 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1452 {
1453 as_bad (_("32bit mode not supported on this CPU."));
1454 }
eecb386c
AM		 1455 stackop_size = '\0';
1456}
1457
1458static void
e3bb37b5 1459set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1460{
3e73aa7c 1461 flag_code = new_code_flag;
40fb9820
L		 1462 if (flag_code != CODE_16BIT)
1463 abort ();
1464 cpu_arch_flags.bitfield.cpu64 = 0;
1465 cpu_arch_flags.bitfield.cpuno64 = 1;
1466 cpu_arch_flags_not.bitfield.cpu64 = 1;
1467 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1468 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1469}
1470
1471static void
e3bb37b5 1472set_intel_syntax (int syntax_flag)
252b5132
RH		 1473{
1474 /* Find out if register prefixing is specified. */
1475 int ask_naked_reg = 0;
1476
1477 SKIP_WHITESPACE ();
29b0f896 1478 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1479 {
1480 char *string = input_line_pointer;
1481 int e = get_symbol_end ();
1482
47926f60 1483 if (strcmp (string, "prefix") == 0)
252b5132 1484 ask_naked_reg = 1;
47926f60 1485 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1486 ask_naked_reg = -1;
1487 else
d0b47220 1488 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1489 *input_line_pointer = e;
1490 }
1491 demand_empty_rest_of_line ();
c3332e24 1492
252b5132
RH		 1493 intel_syntax = syntax_flag;
1494
1495 if (ask_naked_reg == 0)
f86103b7
AM		 1496 allow_naked_reg = (intel_syntax
1497 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1498 else
1499 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1500
e4a3b5a4 1501 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1502 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1503 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1504}
1505
e413e4e9 1506static void
e3bb37b5 1507set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1508{
47926f60 1509 SKIP_WHITESPACE ();
e413e4e9 1510
29b0f896 1511 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1512 {
1513 char *string = input_line_pointer;
1514 int e = get_symbol_end ();
9103f4f4 1515 unsigned int i;
40fb9820 1516 i386_cpu_flags flags;
e413e4e9 1517
9103f4f4 1518 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1519 {
1520 if (strcmp (string, cpu_arch[i].name) == 0)
1521 {
5c6af06e
JB		 1522 if (*string != '.')
1523 {
1524 cpu_arch_name = cpu_arch[i].name;
1525 cpu_sub_arch_name = NULL;
40fb9820
L		 1526 cpu_arch_flags = cpu_arch[i].flags;
1527 if (flag_code == CODE_64BIT)
1528 {
1529 cpu_arch_flags.bitfield.cpu64 = 1;
1530 cpu_arch_flags.bitfield.cpuno64 = 0;
1531 }
1532 else
1533 {
1534 cpu_arch_flags.bitfield.cpu64 = 0;
1535 cpu_arch_flags.bitfield.cpuno64 = 1;
1536 }
1537 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1538 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1539 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1540 if (!cpu_arch_tune_set)
1541 {
1542 cpu_arch_tune = cpu_arch_isa;
1543 cpu_arch_tune_flags = cpu_arch_isa_flags;
1544 }
5c6af06e
JB		 1545 break;
1546 }
40fb9820 1547
c6fb90c8
L		 1548 flags = cpu_flags_or (cpu_arch_flags,
1549 cpu_arch[i].flags);
1550 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1551 {
1552 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1553 cpu_arch_flags = flags;
1554 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1555 }
1556 *input_line_pointer = e;
1557 demand_empty_rest_of_line ();
1558 return;
e413e4e9
AM		 1559 }
1560 }
9103f4f4 1561 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1562 as_bad (_("no such architecture: `%s'"), string);
1563
1564 *input_line_pointer = e;
1565 }
1566 else
1567 as_bad (_("missing cpu architecture"));
1568
fddf5b5b
AM		 1569 no_cond_jump_promotion = 0;
1570 if (*input_line_pointer == ','
29b0f896 1571 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1572 {
1573 char *string = ++input_line_pointer;
1574 int e = get_symbol_end ();
1575
1576 if (strcmp (string, "nojumps") == 0)
1577 no_cond_jump_promotion = 1;
1578 else if (strcmp (string, "jumps") == 0)
1579 ;
1580 else
1581 as_bad (_("no such architecture modifier: `%s'"), string);
1582
1583 *input_line_pointer = e;
1584 }
1585
e413e4e9
AM		 1586 demand_empty_rest_of_line ();
1587}
1588
b9d79e03
JH		 1589unsigned long
1590i386_mach ()
1591{
1592 if (!strcmp (default_arch, "x86_64"))
1593 return bfd_mach_x86_64;
1594 else if (!strcmp (default_arch, "i386"))
1595 return bfd_mach_i386_i386;
1596 else
1597 as_fatal (_("Unknown architecture"));
1598}
b9d79e03 1599\f
252b5132
RH		 1600void
1601md_begin ()
1602{
1603 const char *hash_err;
1604
40fb9820
L		 1605 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1606
47926f60 1607 /* Initialize op_hash hash table. */
252b5132
RH		 1608 op_hash = hash_new ();
1609
1610 {
29b0f896
AM		 1611 const template *optab;
1612 templates *core_optab;
252b5132 1613
47926f60
KH		 1614 /* Setup for loop. */
1615 optab = i386_optab;
252b5132
RH		 1616 core_optab = (templates *) xmalloc (sizeof (templates));
1617 core_optab->start = optab;
1618
1619 while (1)
1620 {
1621 ++optab;
1622 if (optab->name == NULL
1623 || strcmp (optab->name, (optab - 1)->name) != 0)
1624 {
1625 /* different name --> ship out current template list;
47926f60 1626 add to hash table; & begin anew. */
252b5132
RH		 1627 core_optab->end = optab;
1628 hash_err = hash_insert (op_hash,
1629 (optab - 1)->name,
1630 (PTR) core_optab);
1631 if (hash_err)
1632 {
252b5132
RH		 1633 as_fatal (_("Internal Error: Can't hash %s: %s"),
1634 (optab - 1)->name,
1635 hash_err);
1636 }
1637 if (optab->name == NULL)
1638 break;
1639 core_optab = (templates *) xmalloc (sizeof (templates));
1640 core_optab->start = optab;
1641 }
1642 }
1643 }
1644
47926f60 1645 /* Initialize reg_hash hash table. */
252b5132
RH		 1646 reg_hash = hash_new ();
1647 {
29b0f896 1648 const reg_entry *regtab;
c3fe08fa 1649 unsigned int regtab_size = i386_regtab_size;
252b5132 1650
c3fe08fa 1651 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1652 {
1653 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1654 if (hash_err)
3e73aa7c
JH		 1655 as_fatal (_("Internal Error: Can't hash %s: %s"),
1656 regtab->reg_name,
1657 hash_err);
252b5132
RH		 1658 }
1659 }
1660
47926f60 1661 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1662 {
29b0f896
AM		 1663 int c;
1664 char *p;
252b5132
RH		 1665
1666 for (c = 0; c < 256; c++)
1667 {
3882b010 1668 if (ISDIGIT (c))
252b5132
RH		 1669 {
1670 digit_chars[c] = c;
1671 mnemonic_chars[c] = c;
1672 register_chars[c] = c;
1673 operand_chars[c] = c;
1674 }
3882b010 1675 else if (ISLOWER (c))
252b5132
RH		 1676 {
1677 mnemonic_chars[c] = c;
1678 register_chars[c] = c;
1679 operand_chars[c] = c;
1680 }
3882b010 1681 else if (ISUPPER (c))
252b5132 1682 {
3882b010 1683 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1684 register_chars[c] = mnemonic_chars[c];
1685 operand_chars[c] = c;
1686 }
1687
3882b010 1688 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1689 identifier_chars[c] = c;
1690 else if (c >= 128)
1691 {
1692 identifier_chars[c] = c;
1693 operand_chars[c] = c;
1694 }
1695 }
1696
1697#ifdef LEX_AT
1698 identifier_chars['@'] = '@';
32137342
NC		 1699#endif
1700#ifdef LEX_QM
1701 identifier_chars['?'] = '?';
1702 operand_chars['?'] = '?';
252b5132 1703#endif
252b5132 1704 digit_chars['-'] = '-';
791fe849 1705 mnemonic_chars['-'] = '-';
0003779b 1706 mnemonic_chars['.'] = '.';
252b5132
RH		 1707 identifier_chars['_'] = '_';
1708 identifier_chars['.'] = '.';
1709
1710 for (p = operand_special_chars; *p != '\0'; p++)
1711 operand_chars[(unsigned char) *p] = *p;
1712 }
1713
1714#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1715 if (IS_ELF)
252b5132
RH		 1716 {
1717 record_alignment (text_section, 2);
1718 record_alignment (data_section, 2);
1719 record_alignment (bss_section, 2);
1720 }
1721#endif
a4447b93
RH		 1722
1723 if (flag_code == CODE_64BIT)
1724 {
1725 x86_dwarf2_return_column = 16;
1726 x86_cie_data_alignment = -8;
1727 }
1728 else
1729 {
1730 x86_dwarf2_return_column = 8;
1731 x86_cie_data_alignment = -4;
1732 }
252b5132
RH		 1733}
1734
1735void
e3bb37b5 1736i386_print_statistics (FILE *file)
252b5132
RH		 1737{
1738 hash_print_statistics (file, "i386 opcode", op_hash);
1739 hash_print_statistics (file, "i386 register", reg_hash);
1740}
1741\f
252b5132
RH		 1742#ifdef DEBUG386
1743
ce8a8b2f 1744/* Debugging routines for md_assemble. */
e3bb37b5 1745static void pte (template *);
40fb9820 1746static void pt (i386_operand_type);
e3bb37b5
L		 1747static void pe (expressionS *);
1748static void ps (symbolS *);
252b5132
RH		 1749
1750static void
e3bb37b5 1751pi (char *line, i386_insn *x)
252b5132 1752{
09f131f2 1753 unsigned int i;
252b5132
RH		 1754
1755 fprintf (stdout, "%s: template ", line);
1756 pte (&x->tm);
09f131f2
JH		 1757 fprintf (stdout, " address: base %s index %s scale %x\n",
1758 x->base_reg ? x->base_reg->reg_name : "none",
1759 x->index_reg ? x->index_reg->reg_name : "none",
1760 x->log2_scale_factor);
1761 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1762 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1763 fprintf (stdout, " sib: base %x index %x scale %x\n",
1764 x->sib.base, x->sib.index, x->sib.scale);
1765 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1766 (x->rex & REX_W) != 0,
1767 (x->rex & REX_R) != 0,
1768 (x->rex & REX_X) != 0,
1769 (x->rex & REX_B) != 0);
252b5132
RH		 1770 for (i = 0; i < x->operands; i++)
1771 {
1772 fprintf (stdout, " #%d: ", i + 1);
1773 pt (x->types[i]);
1774 fprintf (stdout, "\n");
40fb9820
L		 1775 if (x->types[i].bitfield.reg8
1776 || x->types[i].bitfield.reg16
1777 || x->types[i].bitfield.reg32
1778 || x->types[i].bitfield.reg64
1779 || x->types[i].bitfield.regmmx
1780 || x->types[i].bitfield.regxmm
1781 || x->types[i].bitfield.sreg2
1782 || x->types[i].bitfield.sreg3
1783 || x->types[i].bitfield.control
1784 || x->types[i].bitfield.debug
1785 || x->types[i].bitfield.test)
520dc8e8 1786 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1787 if (operand_type_check (x->types[i], imm))
520dc8e8 1788 pe (x->op[i].imms);
40fb9820 1789 if (operand_type_check (x->types[i], disp))
520dc8e8 1790 pe (x->op[i].disps);
252b5132
RH		 1791 }
1792}
1793
1794static void
e3bb37b5 1795pte (template *t)
252b5132 1796{
09f131f2 1797 unsigned int i;
252b5132 1798 fprintf (stdout, " %d operands ", t->operands);
47926f60 1799 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1800 if (t->extension_opcode != None)
1801 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1802 if (t->opcode_modifier.d)
252b5132 1803 fprintf (stdout, "D");
40fb9820 1804 if (t->opcode_modifier.w)
252b5132
RH		 1805 fprintf (stdout, "W");
1806 fprintf (stdout, "\n");
1807 for (i = 0; i < t->operands; i++)
1808 {
1809 fprintf (stdout, " #%d type ", i + 1);
1810 pt (t->operand_types[i]);
1811 fprintf (stdout, "\n");
1812 }
1813}
1814
1815static void
e3bb37b5 1816pe (expressionS *e)
252b5132 1817{
24eab124 1818 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1819 fprintf (stdout, " add_number %ld (%lx)\n",
1820 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1821 if (e->X_add_symbol)
1822 {
1823 fprintf (stdout, " add_symbol ");
1824 ps (e->X_add_symbol);
1825 fprintf (stdout, "\n");
1826 }
1827 if (e->X_op_symbol)
1828 {
1829 fprintf (stdout, " op_symbol ");
1830 ps (e->X_op_symbol);
1831 fprintf (stdout, "\n");
1832 }
1833}
1834
1835static void
e3bb37b5 1836ps (symbolS *s)
252b5132
RH		 1837{
1838 fprintf (stdout, "%s type %s%s",
1839 S_GET_NAME (s),
1840 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1841 segment_name (S_GET_SEGMENT (s)));
1842}
1843
7b81dfbb 1844static struct type_name
252b5132 1845 {
40fb9820
L		 1846 i386_operand_type mask;
1847 const char *name;
252b5132 1848 }
7b81dfbb 1849const type_names[] =
252b5132 1850{
40fb9820
L		 1851 { OPERAND_TYPE_REG8, "r8" },
1852 { OPERAND_TYPE_REG16, "r16" },
1853 { OPERAND_TYPE_REG32, "r32" },
1854 { OPERAND_TYPE_REG64, "r64" },
1855 { OPERAND_TYPE_IMM8, "i8" },
1856 { OPERAND_TYPE_IMM8, "i8s" },
1857 { OPERAND_TYPE_IMM16, "i16" },
1858 { OPERAND_TYPE_IMM32, "i32" },
1859 { OPERAND_TYPE_IMM32S, "i32s" },
1860 { OPERAND_TYPE_IMM64, "i64" },
1861 { OPERAND_TYPE_IMM1, "i1" },
1862 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1863 { OPERAND_TYPE_DISP8, "d8" },
1864 { OPERAND_TYPE_DISP16, "d16" },
1865 { OPERAND_TYPE_DISP32, "d32" },
1866 { OPERAND_TYPE_DISP32S, "d32s" },
1867 { OPERAND_TYPE_DISP64, "d64" },
1868 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1869 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1870 { OPERAND_TYPE_CONTROL, "control reg" },
1871 { OPERAND_TYPE_TEST, "test reg" },
1872 { OPERAND_TYPE_DEBUG, "debug reg" },
1873 { OPERAND_TYPE_FLOATREG, "FReg" },
1874 { OPERAND_TYPE_FLOATACC, "FAcc" },
1875 { OPERAND_TYPE_SREG2, "SReg2" },
1876 { OPERAND_TYPE_SREG3, "SReg3" },
1877 { OPERAND_TYPE_ACC, "Acc" },
1878 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1879 { OPERAND_TYPE_REGMMX, "rMMX" },
1880 { OPERAND_TYPE_REGXMM, "rXMM" },
1881 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1882};
1883
1884static void
40fb9820 1885pt (i386_operand_type t)
252b5132 1886{
40fb9820 1887 unsigned int j;
c6fb90c8 1888 i386_operand_type a;
252b5132 1889
40fb9820 1890 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1891 {
1892 a = operand_type_and (t, type_names[j].mask);
1893 if (!UINTS_ALL_ZERO (a))
1894 fprintf (stdout, "%s, ", type_names[j].name);
1895 }
252b5132
RH		 1896 fflush (stdout);
1897}
1898
1899#endif /* DEBUG386 */
1900\f
252b5132 1901static bfd_reloc_code_real_type
3956db08 1902reloc (unsigned int size,
64e74474
AM		 1903 int pcrel,
1904 int sign,
1905 bfd_reloc_code_real_type other)
252b5132 1906{
47926f60 1907 if (other != NO_RELOC)
3956db08
JB		 1908 {
1909 reloc_howto_type *reloc;
1910
1911 if (size == 8)
1912 switch (other)
1913 {
64e74474
AM		 1914 case BFD_RELOC_X86_64_GOT32:
1915 return BFD_RELOC_X86_64_GOT64;
1916 break;
1917 case BFD_RELOC_X86_64_PLTOFF64:
1918 return BFD_RELOC_X86_64_PLTOFF64;
1919 break;
1920 case BFD_RELOC_X86_64_GOTPC32:
1921 other = BFD_RELOC_X86_64_GOTPC64;
1922 break;
1923 case BFD_RELOC_X86_64_GOTPCREL:
1924 other = BFD_RELOC_X86_64_GOTPCREL64;
1925 break;
1926 case BFD_RELOC_X86_64_TPOFF32:
1927 other = BFD_RELOC_X86_64_TPOFF64;
1928 break;
1929 case BFD_RELOC_X86_64_DTPOFF32:
1930 other = BFD_RELOC_X86_64_DTPOFF64;
1931 break;
1932 default:
1933 break;
3956db08 1934 }
e05278af
JB		 1935
1936 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1937 if (size == 4 && flag_code != CODE_64BIT)
1938 sign = -1;
1939
3956db08
JB		 1940 reloc = bfd_reloc_type_lookup (stdoutput, other);
1941 if (!reloc)
1942 as_bad (_("unknown relocation (%u)"), other);
1943 else if (size != bfd_get_reloc_size (reloc))
1944 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1945 bfd_get_reloc_size (reloc),
1946 size);
1947 else if (pcrel && !reloc->pc_relative)
1948 as_bad (_("non-pc-relative relocation for pc-relative field"));
1949 else if ((reloc->complain_on_overflow == complain_overflow_signed
1950 && !sign)
1951 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1952 && sign > 0))
3956db08
JB		 1953 as_bad (_("relocated field and relocation type differ in signedness"));
1954 else
1955 return other;
1956 return NO_RELOC;
1957 }
252b5132
RH		 1958
1959 if (pcrel)
1960 {
3e73aa7c 1961 if (!sign)
3956db08 1962 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1963 switch (size)
1964 {
1965 case 1: return BFD_RELOC_8_PCREL;
1966 case 2: return BFD_RELOC_16_PCREL;
1967 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1968 case 8: return BFD_RELOC_64_PCREL;
252b5132 1969 }
3956db08 1970 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1971 }
1972 else
1973 {
3956db08 1974 if (sign > 0)
e5cb08ac 1975 switch (size)
3e73aa7c
JH		 1976 {
1977 case 4: return BFD_RELOC_X86_64_32S;
1978 }
1979 else
1980 switch (size)
1981 {
1982 case 1: return BFD_RELOC_8;
1983 case 2: return BFD_RELOC_16;
1984 case 4: return BFD_RELOC_32;
1985 case 8: return BFD_RELOC_64;
1986 }
3956db08
JB		 1987 as_bad (_("cannot do %s %u byte relocation"),
1988 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1989 }
1990
bfb32b52 1991 abort ();
252b5132
RH		 1992 return BFD_RELOC_NONE;
1993}
1994
47926f60
KH		 1995/* Here we decide which fixups can be adjusted to make them relative to
1996 the beginning of the section instead of the symbol. Basically we need
1997 to make sure that the dynamic relocations are done correctly, so in
1998 some cases we force the original symbol to be used. */
1999
252b5132 2000int
e3bb37b5 2001tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2002{
6d249963 2003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2004 if (!IS_ELF)
31312f95
AM		 2005 return 1;
2006
a161fe53
AM		 2007 /* Don't adjust pc-relative references to merge sections in 64-bit
2008 mode. */
2009 if (use_rela_relocations
2010 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2011 && fixP->fx_pcrel)
252b5132 2012 return 0;
31312f95 2013
8d01d9a9
AJ		 2014 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2015 and changed later by validate_fix. */
2016 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2017 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2018 return 0;
2019
ce8a8b2f 2020 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2021 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2022 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2023 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2034 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2036 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2040 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2041 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2048 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2049 return 0;
31312f95 2050#endif
252b5132
RH		 2051 return 1;
2052}
252b5132 2053
b4cac588 2054static int
e3bb37b5 2055intel_float_operand (const char *mnemonic)
252b5132 2056{
9306ca4a
JB		 2057 /* Note that the value returned is meaningful only for opcodes with (memory)
2058 operands, hence the code here is free to improperly handle opcodes that
2059 have no operands (for better performance and smaller code). */
2060
2061 if (mnemonic[0] != 'f')
2062 return 0; /* non-math */
2063
2064 switch (mnemonic[1])
2065 {
2066 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2067 the fs segment override prefix not currently handled because no
2068 call path can make opcodes without operands get here */
2069 case 'i':
2070 return 2 /* integer op */;
2071 case 'l':
2072 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2073 return 3; /* fldcw/fldenv */
2074 break;
2075 case 'n':
2076 if (mnemonic[2] != 'o' /* fnop */)
2077 return 3; /* non-waiting control op */
2078 break;
2079 case 'r':
2080 if (mnemonic[2] == 's')
2081 return 3; /* frstor/frstpm */
2082 break;
2083 case 's':
2084 if (mnemonic[2] == 'a')
2085 return 3; /* fsave */
2086 if (mnemonic[2] == 't')
2087 {
2088 switch (mnemonic[3])
2089 {
2090 case 'c': /* fstcw */
2091 case 'd': /* fstdw */
2092 case 'e': /* fstenv */
2093 case 's': /* fsts[gw] */
2094 return 3;
2095 }
2096 }
2097 break;
2098 case 'x':
2099 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2100 return 0; /* fxsave/fxrstor are not really math ops */
2101 break;
2102 }
252b5132 2103
9306ca4a 2104 return 1;
252b5132
RH		 2105}
2106
2107/* This is the guts of the machine-dependent assembler. LINE points to a
2108 machine dependent instruction. This function is supposed to emit
2109 the frags/bytes it assembles to. */
2110
2111void
2112md_assemble (line)
2113 char *line;
2114{
40fb9820 2115 unsigned int j;
252b5132
RH		 2116 char mnemonic[MAX_MNEM_SIZE];
2117
47926f60 2118 /* Initialize globals. */
252b5132
RH		 2119 memset (&i, '\0', sizeof (i));
2120 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2121 i.reloc[j] = NO_RELOC;
252b5132
RH		 2122 memset (disp_expressions, '\0', sizeof (disp_expressions));
2123 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2124 save_stack_p = save_stack;
252b5132
RH		 2125
2126 /* First parse an instruction mnemonic & call i386_operand for the operands.
2127 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2128 start of a (possibly prefixed) mnemonic. */
252b5132 2129
29b0f896
AM		 2130 line = parse_insn (line, mnemonic);
2131 if (line == NULL)
2132 return;
252b5132 2133
29b0f896
AM		 2134 line = parse_operands (line, mnemonic);
2135 if (line == NULL)
2136 return;
252b5132 2137
4eed87de 2138 /* The order of the immediates should be reversed
050dfa73 2139 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 2140 if ((i.imm_operands == 2)
2141 && ((strcmp (mnemonic, "extrq") == 0)
2142 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 2143 {
4eed87de
AM		 2144 swap_2_operands (0, 1);
2145 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 2146 have to be reversed even though they have two immediate operands.
2147 */
2148 if (intel_syntax)
2149 swap_operands ();
2150 }
2151
29b0f896
AM		 2152 /* Now we've parsed the mnemonic into a set of templates, and have the
2153 operands at hand. */
2154
2155 /* All intel opcodes have reversed operands except for "bound" and
2156 "enter". We also don't reverse intersegment "jmp" and "call"
2157 instructions with 2 immediate operands so that the immediate segment
050dfa73 2158 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2159 if (intel_syntax
2160 && i.operands > 1
29b0f896 2161 && (strcmp (mnemonic, "bound") != 0)
30123838 2162 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2163 && !(operand_type_check (i.types[0], imm)
2164 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2165 swap_operands ();
2166
2167 if (i.imm_operands)
2168 optimize_imm ();
2169
b300c311
L		 2170 /* Don't optimize displacement for movabs since it only takes 64bit
2171 displacement. */
2172 if (i.disp_operands
2173 && (flag_code != CODE_64BIT
2174 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2175 optimize_disp ();
2176
2177 /* Next, we find a template that matches the given insn,
2178 making sure the overlap of the given operands types is consistent
2179 with the template operand types. */
252b5132 2180
29b0f896
AM		 2181 if (!match_template ())
2182 return;
252b5132 2183
cd61ebfe
AM		 2184 if (intel_syntax)
2185 {
2186 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2187 if (SYSV386_COMPAT
2188 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2189 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2190
2191 /* Zap movzx and movsx suffix. The suffix may have been set from
2192 "word ptr" or "byte ptr" on the source operand, but we'll use
2193 the suffix later to choose the destination register. */
2194 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2195 {
2196 if (i.reg_operands < 2
2197 && !i.suffix
40fb9820
L		 2198 && (!i.tm.opcode_modifier.no_bsuf
2199 || !i.tm.opcode_modifier.no_wsuf
2200 || !i.tm.opcode_modifier.no_lsuf
2201 || !i.tm.opcode_modifier.no_ssuf
2202 || !i.tm.opcode_modifier.no_xsuf
2203 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2204 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2205
2206 i.suffix = 0;
2207 }
cd61ebfe 2208 }
24eab124 2209
40fb9820 2210 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2211 if (!add_prefix (FWAIT_OPCODE))
2212 return;
252b5132 2213
29b0f896 2214 /* Check string instruction segment overrides. */
40fb9820 2215 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2216 {
2217 if (!check_string ())
5dd0794d 2218 return;
29b0f896 2219 }
5dd0794d 2220
29b0f896
AM		 2221 if (!process_suffix ())
2222 return;
e413e4e9 2223
29b0f896
AM		 2224 /* Make still unresolved immediate matches conform to size of immediate
2225 given in i.suffix. */
2226 if (!finalize_imm ())
2227 return;
252b5132 2228
40fb9820 2229 if (i.types[0].bitfield.imm1)
29b0f896 2230 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2231
40fb9820 2232 for (j = 0; j < 3; j++)
c6fb90c8
L		 2233 if (i.types[j].bitfield.inoutportreg
2234 || i.types[j].bitfield.shiftcount
2235 || i.types[j].bitfield.acc
2236 || i.types[j].bitfield.floatacc)
40fb9820
L		 2237 i.reg_operands--;
2238
2239 if (i.tm.opcode_modifier.immext)
29b0f896 2240 {
02fc3089
L		 2241 expressionS *exp;
2242
40fb9820 2243 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2244 {
b7d9ef37 2245 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2246 operands with an opcode suffix which is coded in the same
2247 place as an 8-bit immediate field would be. Here we check
2248 those operands and remove them afterwards. */
2249 unsigned int x;
2250
a4622f40 2251 for (x = 0; x < i.operands; x++)
ca164297 2252 if (i.op[x].regs->reg_num != x)
a540244d
L		 2253 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2254 register_prefix,
2255 i.op[x].regs->reg_name,
2256 x + 1,
2257 i.tm.name);
ca164297
L		 2258 i.operands = 0;
2259 }
2260
29b0f896
AM		 2261 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2262 opcode suffix which is coded in the same place as an 8-bit
2263 immediate field would be. Here we fake an 8-bit immediate
2264 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 2265
29b0f896 2266 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 2267
29b0f896
AM		 2268 exp = &im_expressions[i.imm_operands++];
2269 i.op[i.operands].imms = exp;
c6fb90c8 2270 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2271 i.types[i.operands].bitfield.imm8 = 1;
2272 i.operands++;
29b0f896
AM		 2273 exp->X_op = O_constant;
2274 exp->X_add_number = i.tm.extension_opcode;
2275 i.tm.extension_opcode = None;
2276 }
252b5132 2277
29b0f896
AM		 2278 /* For insns with operands there are more diddles to do to the opcode. */
2279 if (i.operands)
2280 {
2281 if (!process_operands ())
2282 return;
2283 }
40fb9820 2284 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2285 {
2286 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2287 as_warn (_("translating to `%sp'"), i.tm.name);
2288 }
252b5132 2289
29b0f896
AM		 2290 /* Handle conversion of 'int $3' --> special int3 insn. */
2291 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2292 {
2293 i.tm.base_opcode = INT3_OPCODE;
2294 i.imm_operands = 0;
2295 }
252b5132 2296
40fb9820
L		 2297 if ((i.tm.opcode_modifier.jump
2298 || i.tm.opcode_modifier.jumpbyte
2299 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2300 && i.op[0].disps->X_op == O_constant)
2301 {
2302 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2303 the absolute address given by the constant. Since ix86 jumps and
2304 calls are pc relative, we need to generate a reloc. */
2305 i.op[0].disps->X_add_symbol = &abs_symbol;
2306 i.op[0].disps->X_op = O_symbol;
2307 }
252b5132 2308
40fb9820 2309 if (i.tm.opcode_modifier.rex64)
161a04f6 2310 i.rex |= REX_W;
252b5132 2311
29b0f896
AM		 2312 /* For 8 bit registers we need an empty rex prefix. Also if the
2313 instruction already has a prefix, we need to convert old
2314 registers to new ones. */
773f551c 2315
40fb9820 2316 if ((i.types[0].bitfield.reg8
29b0f896 2317 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2318 || (i.types[1].bitfield.reg8
29b0f896 2319 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2320 || ((i.types[0].bitfield.reg8
2321 || i.types[1].bitfield.reg8)
29b0f896
AM		 2322 && i.rex != 0))
2323 {
2324 int x;
726c5dcd 2325
29b0f896
AM		 2326 i.rex |= REX_OPCODE;
2327 for (x = 0; x < 2; x++)
2328 {
2329 /* Look for 8 bit operand that uses old registers. */
40fb9820 2330 if (i.types[x].bitfield.reg8
29b0f896 2331 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2332 {
29b0f896
AM		 2333 /* In case it is "hi" register, give up. */
2334 if (i.op[x].regs->reg_num > 3)
a540244d 2335 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2336 "instruction requiring REX prefix."),
a540244d 2337 register_prefix, i.op[x].regs->reg_name);
773f551c 2338
29b0f896
AM		 2339 /* Otherwise it is equivalent to the extended register.
2340 Since the encoding doesn't change this is merely
2341 cosmetic cleanup for debug output. */
2342
2343 i.op[x].regs = i.op[x].regs + 8;
773f551c 2344 }
29b0f896
AM		 2345 }
2346 }
773f551c 2347
29b0f896
AM		 2348 if (i.rex != 0)
2349 add_prefix (REX_OPCODE | i.rex);
2350
2351 /* We are ready to output the insn. */
2352 output_insn ();
2353}
2354
2355static char *
e3bb37b5 2356parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2357{
2358 char *l = line;
2359 char *token_start = l;
2360 char *mnem_p;
5c6af06e
JB		 2361 int supported;
2362 const template *t;
29b0f896
AM		 2363
2364 /* Non-zero if we found a prefix only acceptable with string insns. */
2365 const char *expecting_string_instruction = NULL;
45288df1 2366
29b0f896
AM		 2367 while (1)
2368 {
2369 mnem_p = mnemonic;
2370 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2371 {
2372 mnem_p++;
2373 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2374 {
29b0f896
AM		 2375 as_bad (_("no such instruction: `%s'"), token_start);
2376 return NULL;
2377 }
2378 l++;
2379 }
2380 if (!is_space_char (*l)
2381 && *l != END_OF_INSN
e44823cf
JB		 2382 && (intel_syntax
2383 || (*l != PREFIX_SEPARATOR
2384 && *l != ',')))
29b0f896
AM		 2385 {
2386 as_bad (_("invalid character %s in mnemonic"),
2387 output_invalid (*l));
2388 return NULL;
2389 }
2390 if (token_start == l)
2391 {
e44823cf 2392 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2393 as_bad (_("expecting prefix; got nothing"));
2394 else
2395 as_bad (_("expecting mnemonic; got nothing"));
2396 return NULL;
2397 }
45288df1 2398
29b0f896
AM		 2399 /* Look up instruction (or prefix) via hash table. */
2400 current_templates = hash_find (op_hash, mnemonic);
47926f60 2401
29b0f896
AM		 2402 if (*l != END_OF_INSN
2403 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2404 && current_templates
40fb9820 2405 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2406 {
c6fb90c8 2407 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2408 {
2409 as_bad ((flag_code != CODE_64BIT
2410 ? _("`%s' is only supported in 64-bit mode")
2411 : _("`%s' is not supported in 64-bit mode")),
2412 current_templates->start->name);
2413 return NULL;
2414 }
29b0f896
AM		 2415 /* If we are in 16-bit mode, do not allow addr16 or data16.
2416 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2417 if ((current_templates->start->opcode_modifier.size16
2418 || current_templates->start->opcode_modifier.size32)
29b0f896 2419 && flag_code != CODE_64BIT
40fb9820 2420 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2421 ^ (flag_code == CODE_16BIT)))
2422 {
2423 as_bad (_("redundant %s prefix"),
2424 current_templates->start->name);
2425 return NULL;
45288df1 2426 }
29b0f896
AM		 2427 /* Add prefix, checking for repeated prefixes. */
2428 switch (add_prefix (current_templates->start->base_opcode))
2429 {
2430 case 0:
2431 return NULL;
2432 case 2:
2433 expecting_string_instruction = current_templates->start->name;
2434 break;
2435 }
2436 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2437 token_start = ++l;
2438 }
2439 else
2440 break;
2441 }
45288df1 2442
29b0f896
AM		 2443 if (!current_templates)
2444 {
2445 /* See if we can get a match by trimming off a suffix. */
2446 switch (mnem_p[-1])
2447 {
2448 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2449 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2450 i.suffix = SHORT_MNEM_SUFFIX;
2451 else
29b0f896
AM		 2452 case BYTE_MNEM_SUFFIX:
2453 case QWORD_MNEM_SUFFIX:
2454 i.suffix = mnem_p[-1];
2455 mnem_p[-1] = '\0';
2456 current_templates = hash_find (op_hash, mnemonic);
2457 break;
2458 case SHORT_MNEM_SUFFIX:
2459 case LONG_MNEM_SUFFIX:
2460 if (!intel_syntax)
2461 {
2462 i.suffix = mnem_p[-1];
2463 mnem_p[-1] = '\0';
2464 current_templates = hash_find (op_hash, mnemonic);
2465 }
2466 break;
252b5132 2467
29b0f896
AM		 2468 /* Intel Syntax. */
2469 case 'd':
2470 if (intel_syntax)
2471 {
9306ca4a 2472 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2473 i.suffix = SHORT_MNEM_SUFFIX;
2474 else
2475 i.suffix = LONG_MNEM_SUFFIX;
2476 mnem_p[-1] = '\0';
2477 current_templates = hash_find (op_hash, mnemonic);
2478 }
2479 break;
2480 }
2481 if (!current_templates)
2482 {
2483 as_bad (_("no such instruction: `%s'"), token_start);
2484 return NULL;
2485 }
2486 }
252b5132 2487
40fb9820
L		 2488 if (current_templates->start->opcode_modifier.jump
2489 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2490 {
2491 /* Check for a branch hint. We allow ",pt" and ",pn" for
2492 predict taken and predict not taken respectively.
2493 I'm not sure that branch hints actually do anything on loop
2494 and jcxz insns (JumpByte) for current Pentium4 chips. They
2495 may work in the future and it doesn't hurt to accept them
2496 now. */
2497 if (l[0] == ',' && l[1] == 'p')
2498 {
2499 if (l[2] == 't')
2500 {
2501 if (!add_prefix (DS_PREFIX_OPCODE))
2502 return NULL;
2503 l += 3;
2504 }
2505 else if (l[2] == 'n')
2506 {
2507 if (!add_prefix (CS_PREFIX_OPCODE))
2508 return NULL;
2509 l += 3;
2510 }
2511 }
2512 }
2513 /* Any other comma loses. */
2514 if (*l == ',')
2515 {
2516 as_bad (_("invalid character %s in mnemonic"),
2517 output_invalid (*l));
2518 return NULL;
2519 }
252b5132 2520
29b0f896 2521 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2522 supported = 0;
2523 for (t = current_templates->start; t < current_templates->end; ++t)
2524 {
40fb9820 2525 if (cpu_flags_match (t->cpu_flags))
64e74474 2526 supported |= 1;
c6fb90c8 2527 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2528 supported |= 2;
5c6af06e
JB		 2529 }
2530 if (!(supported & 2))
2531 {
2532 as_bad (flag_code == CODE_64BIT
2533 ? _("`%s' is not supported in 64-bit mode")
2534 : _("`%s' is only supported in 64-bit mode"),
2535 current_templates->start->name);
2536 return NULL;
2537 }
2538 if (!(supported & 1))
29b0f896 2539 {
5c6af06e
JB		 2540 as_warn (_("`%s' is not supported on `%s%s'"),
2541 current_templates->start->name,
2542 cpu_arch_name,
2543 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2544 }
40fb9820
L		 2545 else if (!cpu_arch_flags.bitfield.cpui386
2546 && (flag_code != CODE_16BIT))
29b0f896
AM		 2547 {
2548 as_warn (_("use .code16 to ensure correct addressing mode"));
2549 }
252b5132 2550
29b0f896 2551 /* Check for rep/repne without a string instruction. */
f41bbced 2552 if (expecting_string_instruction)
29b0f896 2553 {
f41bbced
JB		 2554 static templates override;
2555
2556 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2557 if (t->opcode_modifier.isstring)
f41bbced
JB		 2558 break;
2559 if (t >= current_templates->end)
2560 {
2561 as_bad (_("expecting string instruction after `%s'"),
64e74474 2562 expecting_string_instruction);
f41bbced
JB		 2563 return NULL;
2564 }
2565 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2566 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2567 break;
2568 override.end = t;
2569 current_templates = &override;
29b0f896 2570 }
252b5132 2571
29b0f896
AM		 2572 return l;
2573}
252b5132 2574
29b0f896 2575static char *
e3bb37b5 2576parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2577{
2578 char *token_start;
3138f287 2579
29b0f896
AM		 2580 /* 1 if operand is pending after ','. */
2581 unsigned int expecting_operand = 0;
252b5132 2582
29b0f896
AM		 2583 /* Non-zero if operand parens not balanced. */
2584 unsigned int paren_not_balanced;
2585
2586 while (*l != END_OF_INSN)
2587 {
2588 /* Skip optional white space before operand. */
2589 if (is_space_char (*l))
2590 ++l;
2591 if (!is_operand_char (*l) && *l != END_OF_INSN)
2592 {
2593 as_bad (_("invalid character %s before operand %d"),
2594 output_invalid (*l),
2595 i.operands + 1);
2596 return NULL;
2597 }
2598 token_start = l; /* after white space */
2599 paren_not_balanced = 0;
2600 while (paren_not_balanced || *l != ',')
2601 {
2602 if (*l == END_OF_INSN)
2603 {
2604 if (paren_not_balanced)
2605 {
2606 if (!intel_syntax)
2607 as_bad (_("unbalanced parenthesis in operand %d."),
2608 i.operands + 1);
2609 else
2610 as_bad (_("unbalanced brackets in operand %d."),
2611 i.operands + 1);
2612 return NULL;
2613 }
2614 else
2615 break; /* we are done */
2616 }
2617 else if (!is_operand_char (*l) && !is_space_char (*l))
2618 {
2619 as_bad (_("invalid character %s in operand %d"),
2620 output_invalid (*l),
2621 i.operands + 1);
2622 return NULL;
2623 }
2624 if (!intel_syntax)
2625 {
2626 if (*l == '(')
2627 ++paren_not_balanced;
2628 if (*l == ')')
2629 --paren_not_balanced;
2630 }
2631 else
2632 {
2633 if (*l == '[')
2634 ++paren_not_balanced;
2635 if (*l == ']')
2636 --paren_not_balanced;
2637 }
2638 l++;
2639 }
2640 if (l != token_start)
2641 { /* Yes, we've read in another operand. */
2642 unsigned int operand_ok;
2643 this_operand = i.operands++;
2644 if (i.operands > MAX_OPERANDS)
2645 {
2646 as_bad (_("spurious operands; (%d operands/instruction max)"),
2647 MAX_OPERANDS);
2648 return NULL;
2649 }
2650 /* Now parse operand adding info to 'i' as we go along. */
2651 END_STRING_AND_SAVE (l);
2652
2653 if (intel_syntax)
2654 operand_ok =
2655 i386_intel_operand (token_start,
2656 intel_float_operand (mnemonic));
2657 else
2658 operand_ok = i386_operand (token_start);
2659
2660 RESTORE_END_STRING (l);
2661 if (!operand_ok)
2662 return NULL;
2663 }
2664 else
2665 {
2666 if (expecting_operand)
2667 {
2668 expecting_operand_after_comma:
2669 as_bad (_("expecting operand after ','; got nothing"));
2670 return NULL;
2671 }
2672 if (*l == ',')
2673 {
2674 as_bad (_("expecting operand before ','; got nothing"));
2675 return NULL;
2676 }
2677 }
7f3f1ea2 2678
29b0f896
AM		 2679 /* Now *l must be either ',' or END_OF_INSN. */
2680 if (*l == ',')
2681 {
2682 if (*++l == END_OF_INSN)
2683 {
2684 /* Just skip it, if it's \n complain. */
2685 goto expecting_operand_after_comma;
2686 }
2687 expecting_operand = 1;
2688 }
2689 }
2690 return l;
2691}
7f3f1ea2 2692
050dfa73 2693static void
4d456e3d 2694swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2695{
2696 union i386_op temp_op;
40fb9820 2697 i386_operand_type temp_type;
050dfa73 2698 enum bfd_reloc_code_real temp_reloc;
4eed87de 2699
050dfa73
MM		 2700 temp_type = i.types[xchg2];
2701 i.types[xchg2] = i.types[xchg1];
2702 i.types[xchg1] = temp_type;
2703 temp_op = i.op[xchg2];
2704 i.op[xchg2] = i.op[xchg1];
2705 i.op[xchg1] = temp_op;
2706 temp_reloc = i.reloc[xchg2];
2707 i.reloc[xchg2] = i.reloc[xchg1];
2708 i.reloc[xchg1] = temp_reloc;
2709}
2710
29b0f896 2711static void
e3bb37b5 2712swap_operands (void)
29b0f896 2713{
b7c61d9a 2714 switch (i.operands)
050dfa73 2715 {
b7c61d9a 2716 case 4:
4d456e3d 2717 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2718 case 3:
2719 case 2:
4d456e3d 2720 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2721 break;
2722 default:
2723 abort ();
29b0f896 2724 }
29b0f896
AM		 2725
2726 if (i.mem_operands == 2)
2727 {
2728 const seg_entry *temp_seg;
2729 temp_seg = i.seg[0];
2730 i.seg[0] = i.seg[1];
2731 i.seg[1] = temp_seg;
2732 }
2733}
252b5132 2734
29b0f896
AM		 2735/* Try to ensure constant immediates are represented in the smallest
2736 opcode possible. */
2737static void
e3bb37b5 2738optimize_imm (void)
29b0f896
AM		 2739{
2740 char guess_suffix = 0;
2741 int op;
252b5132 2742
29b0f896
AM		 2743 if (i.suffix)
2744 guess_suffix = i.suffix;
2745 else if (i.reg_operands)
2746 {
2747 /* Figure out a suffix from the last register operand specified.
2748 We can't do this properly yet, ie. excluding InOutPortReg,
2749 but the following works for instructions with immediates.
2750 In any case, we can't set i.suffix yet. */
2751 for (op = i.operands; --op >= 0;)
40fb9820
L		 2752 if (i.types[op].bitfield.reg8)
2753 {
2754 guess_suffix = BYTE_MNEM_SUFFIX;
2755 break;
2756 }
2757 else if (i.types[op].bitfield.reg16)
252b5132 2758 {
40fb9820
L		 2759 guess_suffix = WORD_MNEM_SUFFIX;
2760 break;
2761 }
2762 else if (i.types[op].bitfield.reg32)
2763 {
2764 guess_suffix = LONG_MNEM_SUFFIX;
2765 break;
2766 }
2767 else if (i.types[op].bitfield.reg64)
2768 {
2769 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2770 break;
252b5132 2771 }
29b0f896
AM		 2772 }
2773 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2774 guess_suffix = WORD_MNEM_SUFFIX;
2775
2776 for (op = i.operands; --op >= 0;)
40fb9820 2777 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2778 {
2779 switch (i.op[op].imms->X_op)
252b5132 2780 {
29b0f896
AM		 2781 case O_constant:
2782 /* If a suffix is given, this operand may be shortened. */
2783 switch (guess_suffix)
252b5132 2784 {
29b0f896 2785 case LONG_MNEM_SUFFIX:
40fb9820
L		 2786 i.types[op].bitfield.imm32 = 1;
2787 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2788 break;
2789 case WORD_MNEM_SUFFIX:
40fb9820
L		 2790 i.types[op].bitfield.imm16 = 1;
2791 i.types[op].bitfield.imm32 = 1;
2792 i.types[op].bitfield.imm32s = 1;
2793 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2794 break;
2795 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2796 i.types[op].bitfield.imm8 = 1;
2797 i.types[op].bitfield.imm8s = 1;
2798 i.types[op].bitfield.imm16 = 1;
2799 i.types[op].bitfield.imm32 = 1;
2800 i.types[op].bitfield.imm32s = 1;
2801 i.types[op].bitfield.imm64 = 1;
29b0f896 2802 break;
252b5132 2803 }
252b5132 2804
29b0f896
AM		 2805 /* If this operand is at most 16 bits, convert it
2806 to a signed 16 bit number before trying to see
2807 whether it will fit in an even smaller size.
2808 This allows a 16-bit operand such as $0xffe0 to
2809 be recognised as within Imm8S range. */
40fb9820 2810 if ((i.types[op].bitfield.imm16)
29b0f896 2811 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2812 {
29b0f896
AM		 2813 i.op[op].imms->X_add_number =
2814 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2815 }
40fb9820 2816 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2817 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2818 == 0))
2819 {
2820 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2821 ^ ((offsetT) 1 << 31))
2822 - ((offsetT) 1 << 31));
2823 }
40fb9820 2824 i.types[op]
c6fb90c8
L		 2825 = operand_type_or (i.types[op],
2826 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2827
29b0f896
AM		 2828 /* We must avoid matching of Imm32 templates when 64bit
2829 only immediate is available. */
2830 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2831 i.types[op].bitfield.imm32 = 0;
29b0f896 2832 break;
252b5132 2833
29b0f896
AM		 2834 case O_absent:
2835 case O_register:
2836 abort ();
2837
2838 /* Symbols and expressions. */
2839 default:
9cd96992
JB		 2840 /* Convert symbolic operand to proper sizes for matching, but don't
2841 prevent matching a set of insns that only supports sizes other
2842 than those matching the insn suffix. */
2843 {
40fb9820 2844 i386_operand_type mask, allowed;
9cd96992
JB		 2845 const template *t;
2846
c6fb90c8
L		 2847 UINTS_CLEAR (mask);
2848 UINTS_CLEAR (allowed);
40fb9820 2849
4eed87de
AM		 2850 for (t = current_templates->start;
2851 t < current_templates->end;
2852 ++t)
c6fb90c8
L		 2853 allowed = operand_type_or (allowed,
2854 t->operand_types[op]);
9cd96992
JB		 2855 switch (guess_suffix)
2856 {
2857 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2858 mask.bitfield.imm64 = 1;
2859 mask.bitfield.imm32s = 1;
9cd96992
JB		 2860 break;
2861 case LONG_MNEM_SUFFIX:
40fb9820 2862 mask.bitfield.imm32 = 1;
9cd96992
JB		 2863 break;
2864 case WORD_MNEM_SUFFIX:
40fb9820 2865 mask.bitfield.imm16 = 1;
9cd96992
JB		 2866 break;
2867 case BYTE_MNEM_SUFFIX:
40fb9820 2868 mask.bitfield.imm8 = 1;
9cd96992
JB		 2869 break;
2870 default:
9cd96992
JB		 2871 break;
2872 }
c6fb90c8
L		 2873 allowed = operand_type_and (mask, allowed);
2874 if (!UINTS_ALL_ZERO (allowed))
2875 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2876 }
29b0f896 2877 break;
252b5132 2878 }
29b0f896
AM		 2879 }
2880}
47926f60 2881
29b0f896
AM		 2882/* Try to use the smallest displacement type too. */
2883static void
e3bb37b5 2884optimize_disp (void)
29b0f896
AM		 2885{
2886 int op;
3e73aa7c 2887
29b0f896 2888 for (op = i.operands; --op >= 0;)
40fb9820 2889 if (operand_type_check (i.types[op], disp))
252b5132 2890 {
b300c311 2891 if (i.op[op].disps->X_op == O_constant)
252b5132 2892 {
b300c311 2893 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2894
40fb9820 2895 if (i.types[op].bitfield.disp16
b300c311
L		 2896 && (disp & ~(offsetT) 0xffff) == 0)
2897 {
2898 /* If this operand is at most 16 bits, convert
2899 to a signed 16 bit number and don't use 64bit
2900 displacement. */
2901 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2902 i.types[op].bitfield.disp64 = 0;
b300c311 2903 }
40fb9820 2904 if (i.types[op].bitfield.disp32
b300c311
L		 2905 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2906 {
2907 /* If this operand is at most 32 bits, convert
2908 to a signed 32 bit number and don't use 64bit
2909 displacement. */
2910 disp &= (((offsetT) 2 << 31) - 1);
2911 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2912 i.types[op].bitfield.disp64 = 0;
b300c311 2913 }
40fb9820 2914 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2915 {
40fb9820
L		 2916 i.types[op].bitfield.disp8 = 0;
2917 i.types[op].bitfield.disp16 = 0;
2918 i.types[op].bitfield.disp32 = 0;
2919 i.types[op].bitfield.disp32s = 0;
2920 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2921 i.op[op].disps = 0;
2922 i.disp_operands--;
2923 }
2924 else if (flag_code == CODE_64BIT)
2925 {
2926 if (fits_in_signed_long (disp))
28a9d8f5 2927 {
40fb9820
L		 2928 i.types[op].bitfield.disp64 = 0;
2929 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2930 }
b300c311 2931 if (fits_in_unsigned_long (disp))
40fb9820 2932 i.types[op].bitfield.disp32 = 1;
b300c311 2933 }
40fb9820
L		 2934 if ((i.types[op].bitfield.disp32
2935 || i.types[op].bitfield.disp32s
2936 || i.types[op].bitfield.disp16)
b300c311 2937 && fits_in_signed_byte (disp))
40fb9820 2938 i.types[op].bitfield.disp8 = 1;
252b5132 2939 }
67a4f2b7
AO		 2940 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2941 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2942 {
2943 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2944 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2945 i.types[op].bitfield.disp8 = 0;
2946 i.types[op].bitfield.disp16 = 0;
2947 i.types[op].bitfield.disp32 = 0;
2948 i.types[op].bitfield.disp32s = 0;
2949 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2950 }
2951 else
b300c311 2952 /* We only support 64bit displacement on constants. */
40fb9820 2953 i.types[op].bitfield.disp64 = 0;
252b5132 2954 }
29b0f896
AM		 2955}
2956
2957static int
e3bb37b5 2958match_template (void)
29b0f896
AM		 2959{
2960 /* Points to template once we've found it. */
2961 const template *t;
40fb9820 2962 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2963 unsigned int found_reverse_match;
40fb9820
L		 2964 i386_opcode_modifier suffix_check;
2965 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2966 int addr_prefix_disp;
a5c311ca 2967 unsigned int j;
c6fb90c8 2968 i386_cpu_flags overlap;
29b0f896 2969
f48ff2ae
L		 2970#if MAX_OPERANDS != 4
2971# error "MAX_OPERANDS must be 4."
2972#endif
2973
29b0f896 2974 found_reverse_match = 0;
539e75ad 2975 addr_prefix_disp = -1;
40fb9820
L		 2976
2977 memset (&suffix_check, 0, sizeof (suffix_check));
2978 if (i.suffix == BYTE_MNEM_SUFFIX)
2979 suffix_check.no_bsuf = 1;
2980 else if (i.suffix == WORD_MNEM_SUFFIX)
2981 suffix_check.no_wsuf = 1;
2982 else if (i.suffix == SHORT_MNEM_SUFFIX)
2983 suffix_check.no_ssuf = 1;
2984 else if (i.suffix == LONG_MNEM_SUFFIX)
2985 suffix_check.no_lsuf = 1;
2986 else if (i.suffix == QWORD_MNEM_SUFFIX)
2987 suffix_check.no_qsuf = 1;
2988 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
2989 suffix_check.no_xsuf = 1;
29b0f896 2990
45aa61fe 2991 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2992 {
539e75ad
L		 2993 addr_prefix_disp = -1;
2994
29b0f896
AM		 2995 /* Must have right number of operands. */
2996 if (i.operands != t->operands)
2997 continue;
2998
20592a94 2999 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 3000 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3001 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3002 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3003 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3004 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3005 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3006 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3007 continue;
3008
a5c311ca
L		 3009 for (j = 0; j < MAX_OPERANDS; j++)
3010 operand_types [j] = t->operand_types [j];
539e75ad 3011
45aa61fe
AM		 3012 /* In general, don't allow 64-bit operands in 32-bit mode. */
3013 if (i.suffix == QWORD_MNEM_SUFFIX
3014 && flag_code != CODE_64BIT
3015 && (intel_syntax
40fb9820 3016 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3017 && !intel_float_operand (t->name))
3018 : intel_float_operand (t->name) != 2)
40fb9820
L		 3019 && ((!operand_types[0].bitfield.regmmx
3020 && !operand_types[0].bitfield.regxmm)
3021 || (!operand_types[t->operands > 1].bitfield.regmmx
3022 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3023 && (t->base_opcode != 0x0fc7
3024 || t->extension_opcode != 1 /* cmpxchg8b */))
3025 continue;
3026
29b0f896 3027 /* Do not verify operands when there are none. */
c6fb90c8 3028 else
29b0f896 3029 {
c6fb90c8
L		 3030 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3031 if (!t->operands)
3032 {
3033 if (!UINTS_ALL_ZERO (overlap))
3034 continue;
3035 /* We've found a match; break out of loop. */
3036 break;
3037 }
29b0f896 3038 }
252b5132 3039
539e75ad
L		 3040 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3041 into Disp32/Disp16/Disp32 operand. */
3042 if (i.prefix[ADDR_PREFIX] != 0)
3043 {
40fb9820 3044 /* There should be only one Disp operand. */
539e75ad
L		 3045 switch (flag_code)
3046 {
3047 case CODE_16BIT:
40fb9820
L		 3048 for (j = 0; j < MAX_OPERANDS; j++)
3049 {
3050 if (operand_types[j].bitfield.disp16)
3051 {
3052 addr_prefix_disp = j;
3053 operand_types[j].bitfield.disp32 = 1;
3054 operand_types[j].bitfield.disp16 = 0;
3055 break;
3056 }
3057 }
539e75ad
L		 3058 break;
3059 case CODE_32BIT:
40fb9820
L		 3060 for (j = 0; j < MAX_OPERANDS; j++)
3061 {
3062 if (operand_types[j].bitfield.disp32)
3063 {
3064 addr_prefix_disp = j;
3065 operand_types[j].bitfield.disp32 = 0;
3066 operand_types[j].bitfield.disp16 = 1;
3067 break;
3068 }
3069 }
539e75ad
L		 3070 break;
3071 case CODE_64BIT:
40fb9820
L		 3072 for (j = 0; j < MAX_OPERANDS; j++)
3073 {
3074 if (operand_types[j].bitfield.disp64)
3075 {
3076 addr_prefix_disp = j;
3077 operand_types[j].bitfield.disp64 = 0;
3078 operand_types[j].bitfield.disp32 = 1;
3079 break;
3080 }
3081 }
539e75ad
L		 3082 break;
3083 }
539e75ad
L		 3084 }
3085
c6fb90c8 3086 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3087 switch (t->operands)
3088 {
3089 case 1:
40fb9820 3090 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3091 continue;
3092 break;
3093 case 2:
8b38ad71
L		 3094 /* xchg %eax, %eax is a special case. It is an aliase for nop
3095 only in 32bit mode and we can use opcode 0x90. In 64bit
3096 mode, we can't use 0x90 for xchg %eax, %eax since it should
3097 zero-extend %eax to %rax. */
3098 if (flag_code == CODE_64BIT
3099 && t->base_opcode == 0x90
c6fb90c8
L		 3100 && UINTS_EQUAL (i.types [0], acc32)
3101 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3102 continue;
29b0f896 3103 case 3:
f48ff2ae 3104 case 4:
c6fb90c8 3105 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3106 if (!operand_type_match (overlap0, i.types[0])
3107 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3108 /* monitor in SSE3 is a very special case. The first
708587a4 3109 register and the second register may have different
26186d74
L		 3110 sizes. The same applies to crc32 in SSE4.2. It is
3111 also true for invlpga, vmload, vmrun and vmsave in
3112 SVME. */
cb712a9e 3113 || !((t->base_opcode == 0x0f01
26186d74
L		 3114 && (t->extension_opcode == 0xc8
3115 || t->extension_opcode == 0xd8
3116 || t->extension_opcode == 0xda
3117 || t->extension_opcode == 0xdb
3118 || t->extension_opcode == 0xdf))
381d071f 3119 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3120 || operand_type_register_match (overlap0, i.types[0],
3121 operand_types[0],
3122 overlap1, i.types[1],
3123 operand_types[1])))
29b0f896
AM		 3124 {
3125 /* Check if other direction is valid ... */
40fb9820 3126 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3127 continue;
3128
3129 /* Try reversing direction of operands. */
c6fb90c8
L		 3130 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3131 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3132 if (!operand_type_match (overlap0, i.types[0])
3133 || !operand_type_match (overlap1, i.types[1])
3134 || !operand_type_register_match (overlap0, i.types[0],
3135 operand_types[1],
3136 overlap1, i.types[1],
3137 operand_types[0]))
29b0f896
AM		 3138 {
3139 /* Does not match either direction. */
3140 continue;
3141 }
3142 /* found_reverse_match holds which of D or FloatDR
3143 we've found. */
40fb9820 3144 if (t->opcode_modifier.d)
8a2ed489 3145 found_reverse_match = Opcode_D;
40fb9820 3146 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3147 found_reverse_match = Opcode_FloatD;
3148 else
3149 found_reverse_match = 0;
40fb9820 3150 if (t->opcode_modifier.floatr)
8a2ed489 3151 found_reverse_match |= Opcode_FloatR;
29b0f896 3152 }
f48ff2ae 3153 else
29b0f896 3154 {
f48ff2ae 3155 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3156 switch (t->operands)
3157 {
3158 case 4:
c6fb90c8
L		 3159 overlap3 = operand_type_and (i.types[3],
3160 operand_types[3]);
d1cbb4db 3161 case 3:
c6fb90c8
L		 3162 overlap2 = operand_type_and (i.types[2],
3163 operand_types[2]);
d1cbb4db
L		 3164 break;
3165 }
29b0f896 3166
f48ff2ae
L		 3167 switch (t->operands)
3168 {
3169 case 4:
40fb9820
L		 3170 if (!operand_type_match (overlap3, i.types[3])
3171 || !operand_type_register_match (overlap2,
3172 i.types[2],
3173 operand_types[2],
3174 overlap3,
3175 i.types[3],
3176 operand_types[3]))
f48ff2ae
L		 3177 continue;
3178 case 3:
3179 /* Here we make use of the fact that there are no
3180 reverse match 3 operand instructions, and all 3
3181 operand instructions only need to be checked for
3182 register consistency between operands 2 and 3. */
40fb9820
L		 3183 if (!operand_type_match (overlap2, i.types[2])
3184 || !operand_type_register_match (overlap1,
3185 i.types[1],
3186 operand_types[1],
3187 overlap2,
3188 i.types[2],
3189 operand_types[2]))
f48ff2ae
L		 3190 continue;
3191 break;
3192 }
29b0f896 3193 }
f48ff2ae 3194 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3195 slip through to break. */
3196 }
c6fb90c8 3197 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3198 {
3199 found_reverse_match = 0;
3200 continue;
3201 }
3202 /* We've found a match; break out of loop. */
3203 break;
3204 }
3205
3206 if (t == current_templates->end)
3207 {
3208 /* We found no match. */
3209 as_bad (_("suffix or operands invalid for `%s'"),
3210 current_templates->start->name);
3211 return 0;
3212 }
252b5132 3213
29b0f896
AM		 3214 if (!quiet_warnings)
3215 {
3216 if (!intel_syntax
40fb9820
L		 3217 && (i.types[0].bitfield.jumpabsolute
3218 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3219 {
3220 as_warn (_("indirect %s without `*'"), t->name);
3221 }
3222
40fb9820
L		 3223 if (t->opcode_modifier.isprefix
3224 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3225 {
3226 /* Warn them that a data or address size prefix doesn't
3227 affect assembly of the next line of code. */
3228 as_warn (_("stand-alone `%s' prefix"), t->name);
3229 }
3230 }
3231
3232 /* Copy the template we found. */
3233 i.tm = *t;
539e75ad
L		 3234
3235 if (addr_prefix_disp != -1)
3236 i.tm.operand_types[addr_prefix_disp]
3237 = operand_types[addr_prefix_disp];
3238
29b0f896
AM		 3239 if (found_reverse_match)
3240 {
3241 /* If we found a reverse match we must alter the opcode
3242 direction bit. found_reverse_match holds bits to change
3243 (different for int & float insns). */
3244
3245 i.tm.base_opcode ^= found_reverse_match;
3246
539e75ad
L		 3247 i.tm.operand_types[0] = operand_types[1];
3248 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3249 }
3250
3251 return 1;
3252}
3253
3254static int
e3bb37b5 3255check_string (void)
29b0f896 3256{
40fb9820
L		 3257 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3258 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3259 {
3260 if (i.seg[0] != NULL && i.seg[0] != &es)
3261 {
3262 as_bad (_("`%s' operand %d must use `%%es' segment"),
3263 i.tm.name,
3264 mem_op + 1);
3265 return 0;
3266 }
3267 /* There's only ever one segment override allowed per instruction.
3268 This instruction possibly has a legal segment override on the
3269 second operand, so copy the segment to where non-string
3270 instructions store it, allowing common code. */
3271 i.seg[0] = i.seg[1];
3272 }
40fb9820 3273 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3274 {
3275 if (i.seg[1] != NULL && i.seg[1] != &es)
3276 {
3277 as_bad (_("`%s' operand %d must use `%%es' segment"),
3278 i.tm.name,
3279 mem_op + 2);
3280 return 0;
3281 }
3282 }
3283 return 1;
3284}
3285
3286static int
543613e9 3287process_suffix (void)
29b0f896
AM		 3288{
3289 /* If matched instruction specifies an explicit instruction mnemonic
3290 suffix, use it. */
40fb9820
L		 3291 if (i.tm.opcode_modifier.size16)
3292 i.suffix = WORD_MNEM_SUFFIX;
3293 else if (i.tm.opcode_modifier.size32)
3294 i.suffix = LONG_MNEM_SUFFIX;
3295 else if (i.tm.opcode_modifier.size64)
3296 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3297 else if (i.reg_operands)
3298 {
3299 /* If there's no instruction mnemonic suffix we try to invent one
3300 based on register operands. */
3301 if (!i.suffix)
3302 {
3303 /* We take i.suffix from the last register operand specified,
3304 Destination register type is more significant than source
381d071f
L		 3305 register type. crc32 in SSE4.2 prefers source register
3306 type. */
3307 if (i.tm.base_opcode == 0xf20f38f1)
3308 {
40fb9820
L		 3309 if (i.types[0].bitfield.reg16)
3310 i.suffix = WORD_MNEM_SUFFIX;
3311 else if (i.types[0].bitfield.reg32)
3312 i.suffix = LONG_MNEM_SUFFIX;
3313 else if (i.types[0].bitfield.reg64)
3314 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3315 }
9344ff29 3316 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3317 {
40fb9820 3318 if (i.types[0].bitfield.reg8)
20592a94
L		 3319 i.suffix = BYTE_MNEM_SUFFIX;
3320 }
381d071f
L		 3321
3322 if (!i.suffix)
3323 {
3324 int op;
3325
20592a94
L		 3326 if (i.tm.base_opcode == 0xf20f38f1
3327 || i.tm.base_opcode == 0xf20f38f0)
3328 {
3329 /* We have to know the operand size for crc32. */
3330 as_bad (_("ambiguous memory operand size for `%s`"),
3331 i.tm.name);
3332 return 0;
3333 }
3334
381d071f 3335 for (op = i.operands; --op >= 0;)
40fb9820 3336 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3337 {
40fb9820
L		 3338 if (i.types[op].bitfield.reg8)
3339 {
3340 i.suffix = BYTE_MNEM_SUFFIX;
3341 break;
3342 }
3343 else if (i.types[op].bitfield.reg16)
3344 {
3345 i.suffix = WORD_MNEM_SUFFIX;
3346 break;
3347 }
3348 else if (i.types[op].bitfield.reg32)
3349 {
3350 i.suffix = LONG_MNEM_SUFFIX;
3351 break;
3352 }
3353 else if (i.types[op].bitfield.reg64)
3354 {
3355 i.suffix = QWORD_MNEM_SUFFIX;
3356 break;
3357 }
381d071f
L		 3358 }
3359 }
29b0f896
AM		 3360 }
3361 else if (i.suffix == BYTE_MNEM_SUFFIX)
3362 {
3363 if (!check_byte_reg ())
3364 return 0;
3365 }
3366 else if (i.suffix == LONG_MNEM_SUFFIX)
3367 {
3368 if (!check_long_reg ())
3369 return 0;
3370 }
3371 else if (i.suffix == QWORD_MNEM_SUFFIX)
3372 {
3373 if (!check_qword_reg ())
3374 return 0;
3375 }
3376 else if (i.suffix == WORD_MNEM_SUFFIX)
3377 {
3378 if (!check_word_reg ())
3379 return 0;
3380 }
40fb9820 3381 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3382 /* Do nothing if the instruction is going to ignore the prefix. */
3383 ;
3384 else
3385 abort ();
3386 }
40fb9820 3387 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3388 && !i.suffix
3389 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3390 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3391 {
3392 i.suffix = stackop_size;
3393 }
9306ca4a
JB		 3394 else if (intel_syntax
3395 && !i.suffix
40fb9820
L		 3396 && (i.tm.operand_types[0].bitfield.jumpabsolute
3397 || i.tm.opcode_modifier.jumpbyte
3398 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3399 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3400 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3401 {
3402 switch (flag_code)
3403 {
3404 case CODE_64BIT:
40fb9820 3405 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3406 {
3407 i.suffix = QWORD_MNEM_SUFFIX;
3408 break;
3409 }
3410 case CODE_32BIT:
40fb9820 3411 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3412 i.suffix = LONG_MNEM_SUFFIX;
3413 break;
3414 case CODE_16BIT:
40fb9820 3415 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3416 i.suffix = WORD_MNEM_SUFFIX;
3417 break;
3418 }
3419 }
252b5132 3420
9306ca4a 3421 if (!i.suffix)
29b0f896 3422 {
9306ca4a
JB		 3423 if (!intel_syntax)
3424 {
40fb9820 3425 if (i.tm.opcode_modifier.w)
9306ca4a 3426 {
4eed87de
AM		 3427 as_bad (_("no instruction mnemonic suffix given and "
3428 "no register operands; can't size instruction"));
9306ca4a
JB		 3429 return 0;
3430 }
3431 }
3432 else
3433 {
40fb9820
L		 3434 unsigned int suffixes;
3435
3436 suffixes = !i.tm.opcode_modifier.no_bsuf;
3437 if (!i.tm.opcode_modifier.no_wsuf)
3438 suffixes |= 1 << 1;
3439 if (!i.tm.opcode_modifier.no_lsuf)
3440 suffixes |= 1 << 2;
3441 if (!i.tm.opcode_modifier.no_lsuf)
3442 suffixes |= 1 << 3;
3443 if (!i.tm.opcode_modifier.no_ssuf)
3444 suffixes |= 1 << 4;
3445 if (!i.tm.opcode_modifier.no_qsuf)
3446 suffixes |= 1 << 5;
3447
3448 /* There are more than suffix matches. */
3449 if (i.tm.opcode_modifier.w
9306ca4a 3450 || ((suffixes & (suffixes - 1))
40fb9820
L		 3451 && !i.tm.opcode_modifier.defaultsize
3452 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3453 {
3454 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3455 return 0;
3456 }
3457 }
29b0f896 3458 }
252b5132 3459
9306ca4a
JB		 3460 /* Change the opcode based on the operand size given by i.suffix;
3461 We don't need to change things for byte insns. */
3462
29b0f896
AM		 3463 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3464 {
3465 /* It's not a byte, select word/dword operation. */
40fb9820 3466 if (i.tm.opcode_modifier.w)
29b0f896 3467 {
40fb9820 3468 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3469 i.tm.base_opcode |= 8;
3470 else
3471 i.tm.base_opcode |= 1;
3472 }
0f3f3d8b 3473
29b0f896
AM		 3474 /* Now select between word & dword operations via the operand
3475 size prefix, except for instructions that will ignore this
3476 prefix anyway. */
26186d74
L		 3477 if (i.tm.base_opcode == 0x0f01
3478 && (i.tm.extension_opcode == 0xc8
3479 || i.tm.extension_opcode == 0xd8
3480 || i.tm.extension_opcode == 0xda
3481 || i.tm.extension_opcode == 0xdb
3482 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3483 {
3484 /* monitor in SSE3 is a very special case. The default size
3485 of AX is the size of mode. The address size override
26186d74
L		 3486 prefix will change the size of AX. It is also true for
3487 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3488 if ((flag_code == CODE_32BIT
3489 && i.op->regs[0].reg_type.bitfield.reg16)
3490 || (flag_code != CODE_32BIT
3491 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3492 if (!add_prefix (ADDR_PREFIX_OPCODE))
3493 return 0;
3494 }
3495 else if (i.suffix != QWORD_MNEM_SUFFIX
3496 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3497 && !i.tm.opcode_modifier.ignoresize
3498 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3499 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3500 || (flag_code == CODE_64BIT
40fb9820 3501 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3502 {
3503 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3504
40fb9820 3505 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3506 prefix = ADDR_PREFIX_OPCODE;
252b5132 3507
29b0f896
AM		 3508 if (!add_prefix (prefix))
3509 return 0;
24eab124 3510 }
252b5132 3511
29b0f896
AM		 3512 /* Set mode64 for an operand. */
3513 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3514 && flag_code == CODE_64BIT
40fb9820 3515 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3516 {
3517 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3518 need rex64. cmpxchg8b is also a special case. */
3519 if (! (i.operands == 2
3520 && i.tm.base_opcode == 0x90
3521 && i.tm.extension_opcode == None
c6fb90c8
L		 3522 && UINTS_EQUAL (i.types [0], acc64)
3523 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3524 && ! (i.operands == 1
3525 && i.tm.base_opcode == 0xfc7
3526 && i.tm.extension_opcode == 1
40fb9820
L		 3527 && !operand_type_check (i.types [0], reg)
3528 && operand_type_check (i.types [0], anymem)))
f6bee062 3529 i.rex |= REX_W;
46e883c5 3530 }
3e73aa7c 3531
29b0f896
AM		 3532 /* Size floating point instruction. */
3533 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3534 if (i.tm.opcode_modifier.floatmf)
543613e9 3535 i.tm.base_opcode ^= 4;
29b0f896 3536 }
7ecd2f8b 3537
29b0f896
AM		 3538 return 1;
3539}
3e73aa7c 3540
29b0f896 3541static int
543613e9 3542check_byte_reg (void)
29b0f896
AM		 3543{
3544 int op;
543613e9 3545
29b0f896
AM		 3546 for (op = i.operands; --op >= 0;)
3547 {
3548 /* If this is an eight bit register, it's OK. If it's the 16 or
3549 32 bit version of an eight bit register, we will just use the
3550 low portion, and that's OK too. */
40fb9820 3551 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3552 continue;
3553
c3ad16c0
L		 3554 /* movzx, movsx, pextrb and pinsrb should not generate this
3555 warning. */
29b0f896
AM		 3556 if (intel_syntax
3557 && (i.tm.base_opcode == 0xfb7
3558 || i.tm.base_opcode == 0xfb6
3559 || i.tm.base_opcode == 0x63
3560 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3561 || i.tm.base_opcode == 0xfbf
3562 || i.tm.base_opcode == 0x660f3a14
3563 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3564 continue;
3565
9344ff29
L		 3566 /* crc32 doesn't generate this warning. */
3567 if (i.tm.base_opcode == 0xf20f38f0)
3568 continue;
3569
40fb9820
L		 3570 if ((i.types[op].bitfield.reg16
3571 || i.types[op].bitfield.reg32
3572 || i.types[op].bitfield.reg64)
3573 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3574 {
3575 /* Prohibit these changes in the 64bit mode, since the
3576 lowering is more complicated. */
3577 if (flag_code == CODE_64BIT
40fb9820 3578 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3579 {
2ca3ace5
L		 3580 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3581 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3582 i.suffix);
3583 return 0;
3584 }
3585#if REGISTER_WARNINGS
3586 if (!quiet_warnings
40fb9820 3587 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3588 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3589 register_prefix,
40fb9820 3590 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3591 ? REGNAM_AL - REGNAM_AX
3592 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3593 register_prefix,
29b0f896
AM		 3594 i.op[op].regs->reg_name,
3595 i.suffix);
3596#endif
3597 continue;
3598 }
3599 /* Any other register is bad. */
40fb9820
L		 3600 if (i.types[op].bitfield.reg16
3601 || i.types[op].bitfield.reg32
3602 || i.types[op].bitfield.reg64
3603 || i.types[op].bitfield.regmmx
3604 || i.types[op].bitfield.regxmm
3605 || i.types[op].bitfield.sreg2
3606 || i.types[op].bitfield.sreg3
3607 || i.types[op].bitfield.control
3608 || i.types[op].bitfield.debug
3609 || i.types[op].bitfield.test
3610 || i.types[op].bitfield.floatreg
3611 || i.types[op].bitfield.floatacc)
29b0f896 3612 {
a540244d
L		 3613 as_bad (_("`%s%s' not allowed with `%s%c'"),
3614 register_prefix,
29b0f896
AM		 3615 i.op[op].regs->reg_name,
3616 i.tm.name,
3617 i.suffix);
3618 return 0;
3619 }
3620 }
3621 return 1;
3622}
3623
3624static int
e3bb37b5 3625check_long_reg (void)
29b0f896
AM		 3626{
3627 int op;
3628
3629 for (op = i.operands; --op >= 0;)
3630 /* Reject eight bit registers, except where the template requires
3631 them. (eg. movzb) */
40fb9820
L		 3632 if (i.types[op].bitfield.reg8
3633 && (i.tm.operand_types[op].bitfield.reg16
3634 || i.tm.operand_types[op].bitfield.reg32
3635 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3636 {
a540244d
L		 3637 as_bad (_("`%s%s' not allowed with `%s%c'"),
3638 register_prefix,
29b0f896
AM		 3639 i.op[op].regs->reg_name,
3640 i.tm.name,
3641 i.suffix);
3642 return 0;
3643 }
3644 /* Warn if the e prefix on a general reg is missing. */
3645 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3646 && i.types[op].bitfield.reg16
3647 && (i.tm.operand_types[op].bitfield.reg32
3648 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3649 {
3650 /* Prohibit these changes in the 64bit mode, since the
3651 lowering is more complicated. */
3652 if (flag_code == CODE_64BIT)
252b5132 3653 {
2ca3ace5
L		 3654 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3655 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3656 i.suffix);
3657 return 0;
252b5132 3658 }
29b0f896
AM		 3659#if REGISTER_WARNINGS
3660 else
a540244d
L		 3661 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3662 register_prefix,
29b0f896 3663 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3664 register_prefix,
29b0f896
AM		 3665 i.op[op].regs->reg_name,
3666 i.suffix);
3667#endif
252b5132 3668 }
29b0f896 3669 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3670 else if (i.types[op].bitfield.reg64
3671 && (i.tm.operand_types[op].bitfield.reg32
3672 || i.tm.operand_types[op].bitfield.acc))
252b5132 3673 {
34828aad
L		 3674 if (intel_syntax
3675 && i.tm.base_opcode == 0xf30f2d
40fb9820 3676 && !i.types[0].bitfield.regxmm)
34828aad
L		 3677 {
3678 /* cvtss2si converts DWORD memory to Reg64. We want
3679 REX byte. */
3680 i.suffix = QWORD_MNEM_SUFFIX;
3681 }
3682 else
3683 {
3684 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3685 register_prefix, i.op[op].regs->reg_name,
3686 i.suffix);
3687 return 0;
3688 }
29b0f896
AM		 3689 }
3690 return 1;
3691}
252b5132 3692
29b0f896 3693static int
e3bb37b5 3694check_qword_reg (void)
29b0f896
AM		 3695{
3696 int op;
252b5132 3697
29b0f896
AM		 3698 for (op = i.operands; --op >= 0; )
3699 /* Reject eight bit registers, except where the template requires
3700 them. (eg. movzb) */
40fb9820
L		 3701 if (i.types[op].bitfield.reg8
3702 && (i.tm.operand_types[op].bitfield.reg16
3703 || i.tm.operand_types[op].bitfield.reg32
3704 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3705 {
a540244d
L		 3706 as_bad (_("`%s%s' not allowed with `%s%c'"),
3707 register_prefix,
29b0f896
AM		 3708 i.op[op].regs->reg_name,
3709 i.tm.name,
3710 i.suffix);
3711 return 0;
3712 }
3713 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3714 else if ((i.types[op].bitfield.reg16
3715 || i.types[op].bitfield.reg32)
3716 && (i.tm.operand_types[op].bitfield.reg32
3717 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3718 {
3719 /* Prohibit these changes in the 64bit mode, since the
3720 lowering is more complicated. */
34828aad
L		 3721 if (intel_syntax
3722 && i.tm.base_opcode == 0xf20f2d
40fb9820 3723 && !i.types[0].bitfield.regxmm)
34828aad
L		 3724 {
3725 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3726 REX byte. */
3727 i.suffix = LONG_MNEM_SUFFIX;
3728 }
3729 else
3730 {
3731 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3732 register_prefix, i.op[op].regs->reg_name,
3733 i.suffix);
3734 return 0;
3735 }
252b5132 3736 }
29b0f896
AM		 3737 return 1;
3738}
252b5132 3739
29b0f896 3740static int
e3bb37b5 3741check_word_reg (void)
29b0f896
AM		 3742{
3743 int op;
3744 for (op = i.operands; --op >= 0;)
3745 /* Reject eight bit registers, except where the template requires
3746 them. (eg. movzb) */
40fb9820
L		 3747 if (i.types[op].bitfield.reg8
3748 && (i.tm.operand_types[op].bitfield.reg16
3749 || i.tm.operand_types[op].bitfield.reg32
3750 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3751 {
a540244d
L		 3752 as_bad (_("`%s%s' not allowed with `%s%c'"),
3753 register_prefix,
29b0f896
AM		 3754 i.op[op].regs->reg_name,
3755 i.tm.name,
3756 i.suffix);
3757 return 0;
3758 }
3759 /* Warn if the e prefix on a general reg is present. */
3760 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3761 && i.types[op].bitfield.reg32
3762 && (i.tm.operand_types[op].bitfield.reg16
3763 || i.tm.operand_types[op].bitfield.acc))
252b5132 3764 {
29b0f896
AM		 3765 /* Prohibit these changes in the 64bit mode, since the
3766 lowering is more complicated. */
3767 if (flag_code == CODE_64BIT)
252b5132 3768 {
2ca3ace5
L		 3769 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3770 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3771 i.suffix);
3772 return 0;
252b5132 3773 }
29b0f896
AM		 3774 else
3775#if REGISTER_WARNINGS
a540244d
L		 3776 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3777 register_prefix,
29b0f896 3778 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3779 register_prefix,
29b0f896
AM		 3780 i.op[op].regs->reg_name,
3781 i.suffix);
3782#endif
3783 }
3784 return 1;
3785}
252b5132 3786
29b0f896 3787static int
40fb9820 3788update_imm (unsigned int j)
29b0f896 3789{
40fb9820
L		 3790 i386_operand_type overlap;
3791
c6fb90c8 3792 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3793 if ((overlap.bitfield.imm8
3794 || overlap.bitfield.imm8s
3795 || overlap.bitfield.imm16
3796 || overlap.bitfield.imm32
3797 || overlap.bitfield.imm32s
3798 || overlap.bitfield.imm64)
c6fb90c8
L		 3799 && !UINTS_EQUAL (overlap, imm8)
3800 && !UINTS_EQUAL (overlap, imm8s)
3801 && !UINTS_EQUAL (overlap, imm16)
3802 && !UINTS_EQUAL (overlap, imm32)
3803 && !UINTS_EQUAL (overlap, imm32s)
3804 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3805 {
3806 if (i.suffix)
3807 {
40fb9820
L		 3808 i386_operand_type temp;
3809
c6fb90c8 3810 UINTS_CLEAR (temp);
40fb9820
L		 3811 if (i.suffix == BYTE_MNEM_SUFFIX)
3812 {
3813 temp.bitfield.imm8 = overlap.bitfield.imm8;
3814 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3815 }
3816 else if (i.suffix == WORD_MNEM_SUFFIX)
3817 temp.bitfield.imm16 = overlap.bitfield.imm16;
3818 else if (i.suffix == QWORD_MNEM_SUFFIX)
3819 {
3820 temp.bitfield.imm64 = overlap.bitfield.imm64;
3821 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3822 }
3823 else
3824 temp.bitfield.imm32 = overlap.bitfield.imm32;
3825 overlap = temp;
29b0f896 3826 }
c6fb90c8
L		 3827 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3828 || UINTS_EQUAL (overlap, imm16_32)
3829 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3830 {
c6fb90c8 3831 UINTS_CLEAR (overlap);
40fb9820
L		 3832 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3833 overlap.bitfield.imm16 = 1;
3834 else
3835 overlap.bitfield.imm32s = 1;
29b0f896 3836 }
c6fb90c8
L		 3837 if (!UINTS_EQUAL (overlap, imm8)
3838 && !UINTS_EQUAL (overlap, imm8s)
3839 && !UINTS_EQUAL (overlap, imm16)
3840 && !UINTS_EQUAL (overlap, imm32)
3841 && !UINTS_EQUAL (overlap, imm32s)
3842 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3843 {
4eed87de
AM		 3844 as_bad (_("no instruction mnemonic suffix given; "
3845 "can't determine immediate size"));
29b0f896
AM		 3846 return 0;
3847 }
3848 }
40fb9820 3849 i.types[j] = overlap;
29b0f896 3850
40fb9820
L		 3851 return 1;
3852}
3853
3854static int
3855finalize_imm (void)
3856{
3857 unsigned int j;
29b0f896 3858
40fb9820
L		 3859 for (j = 0; j < 2; j++)
3860 if (update_imm (j) == 0)
3861 return 0;
3862
c6fb90c8 3863 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3864 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3865
3866 return 1;
3867}
3868
3869static int
e3bb37b5 3870process_operands (void)
29b0f896
AM		 3871{
3872 /* Default segment register this instruction will use for memory
3873 accesses. 0 means unknown. This is only for optimizing out
3874 unnecessary segment overrides. */
3875 const seg_entry *default_seg = 0;
3876
3877 /* The imul $imm, %reg instruction is converted into
3878 imul $imm, %reg, %reg, and the clr %reg instruction
3879 is converted into xor %reg, %reg. */
40fb9820 3880 if (i.tm.opcode_modifier.regkludge)
29b0f896 3881 {
40fb9820 3882 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 3883 {
3884 /* The first operand in instruction blendvpd, blendvps and
3885 pblendvb in SSE4.1 is implicit and must be xmm0. */
3886 assert (i.operands == 3
3887 && i.reg_operands >= 2
c6fb90c8 3888 && UINTS_EQUAL (i.types[0], regxmm));
42903f7f
L		 3889 if (i.op[0].regs->reg_num != 0)
3890 {
3891 if (intel_syntax)
3892 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3893 i.tm.name, register_prefix);
3894 else
3895 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3896 i.tm.name, register_prefix);
3897 return 0;
3898 }
3899 i.op[0] = i.op[1];
3900 i.op[1] = i.op[2];
3901 i.types[0] = i.types[1];
3902 i.types[1] = i.types[2];
3903 i.operands--;
3904 i.reg_operands--;
3905
3906 /* We need to adjust fields in i.tm since they are used by
3907 build_modrm_byte. */
3908 i.tm.operand_types [0] = i.tm.operand_types [1];
3909 i.tm.operand_types [1] = i.tm.operand_types [2];
3910 i.tm.operands--;
3911 }
3912 else
3913 {
40fb9820
L		 3914 unsigned int first_reg_op;
3915
3916 if (operand_type_check (i.types[0], reg))
3917 first_reg_op = 0;
3918 else
3919 first_reg_op = 1;
42903f7f
L		 3920 /* Pretend we saw the extra register operand. */
3921 assert (i.reg_operands == 1
3922 && i.op[first_reg_op + 1].regs == 0);
3923 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3924 i.types[first_reg_op + 1] = i.types[first_reg_op];
3925 i.operands++;
3926 i.reg_operands++;
3927 }
29b0f896
AM		 3928 }
3929
40fb9820 3930 if (i.tm.opcode_modifier.shortform)
29b0f896 3931 {
40fb9820
L		 3932 if (i.types[0].bitfield.sreg2
3933 || i.types[0].bitfield.sreg3)
29b0f896 3934 {
4eed87de
AM		 3935 if (i.tm.base_opcode == POP_SEG_SHORT
3936 && i.op[0].regs->reg_num == 1)
29b0f896 3937 {
4eed87de
AM		 3938 as_bad (_("you can't `pop %%cs'"));
3939 return 0;
29b0f896 3940 }
4eed87de
AM		 3941 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3942 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3943 i.rex |= REX_B;
4eed87de
AM		 3944 }
3945 else
3946 {
3947 /* The register or float register operand is in operand 0 or 1. */
40fb9820
L		 3948 unsigned int op;
3949
3950 if (i.types[0].bitfield.floatreg
3951 || operand_type_check (i.types[0], reg))
3952 op = 0;
3953 else
3954 op = 1;
4eed87de
AM		 3955 /* Register goes in low 3 bits of opcode. */
3956 i.tm.base_opcode |= i.op[op].regs->reg_num;
3957 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3958 i.rex |= REX_B;
40fb9820 3959 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 3960 {
4eed87de
AM		 3961 /* Warn about some common errors, but press on regardless.
3962 The first case can be generated by gcc (<= 2.8.1). */
3963 if (i.operands == 2)
3964 {
3965 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3966 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3967 register_prefix, i.op[1].regs->reg_name,
3968 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3969 }
3970 else
3971 {
3972 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3973 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3974 register_prefix, i.op[0].regs->reg_name);
4eed87de 3975 }
29b0f896
AM		 3976 }
3977 }
3978 }
40fb9820 3979 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 3980 {
3981 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3982 must be put into the modrm byte). Now, we make the modrm and
3983 index base bytes based on all the info we've collected. */
29b0f896
AM		 3984
3985 default_seg = build_modrm_byte ();
3986 }
8a2ed489 3987 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3988 {
3989 default_seg = &ds;
3990 }
40fb9820 3991 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 3992 {
3993 /* For the string instructions that allow a segment override
3994 on one of their operands, the default segment is ds. */
3995 default_seg = &ds;
3996 }
3997
75178d9d
L		 3998 if (i.tm.base_opcode == 0x8d /* lea */
3999 && i.seg[0]
4000 && !quiet_warnings)
30123838 4001 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4002
4003 /* If a segment was explicitly specified, and the specified segment
4004 is not the default, use an opcode prefix to select it. If we
4005 never figured out what the default segment is, then default_seg
4006 will be zero at this point, and the specified segment prefix will
4007 always be used. */
29b0f896
AM		 4008 if ((i.seg[0]) && (i.seg[0] != default_seg))
4009 {
4010 if (!add_prefix (i.seg[0]->seg_prefix))
4011 return 0;
4012 }
4013 return 1;
4014}
4015
4016static const seg_entry *
e3bb37b5 4017build_modrm_byte (void)
29b0f896
AM		 4018{
4019 const seg_entry *default_seg = 0;
4020
4021 /* i.reg_operands MUST be the number of real register operands;
4022 implicit registers do not count. */
4023 if (i.reg_operands == 2)
4024 {
4025 unsigned int source, dest;
cab737b9
L		 4026
4027 switch (i.operands)
4028 {
4029 case 2:
4030 source = 0;
4031 break;
4032 case 3:
c81128dc
L		 4033 /* When there are 3 operands, one of them may be immediate,
4034 which may be the first or the last operand. Otherwise,
4035 the first operand must be shift count register (cl). */
4036 assert (i.imm_operands == 1
4037 || (i.imm_operands == 0
40fb9820
L		 4038 && i.types[0].bitfield.shiftcount));
4039 if (operand_type_check (i.types[0], imm)
4040 || i.types[0].bitfield.shiftcount)
4041 source = 1;
4042 else
4043 source = 0;
cab737b9
L		 4044 break;
4045 case 4:
4046 /* When there are 4 operands, the first two must be immediate
4047 operands. The source operand will be the 3rd one. */
4048 assert (i.imm_operands == 2
40fb9820
L		 4049 && operand_type_check (i.types[0], imm)
4050 && operand_type_check (i.types[1], imm));
cab737b9
L		 4051 source = 2;
4052 break;
4053 default:
4054 abort ();
4055 }
4056
29b0f896
AM		 4057 dest = source + 1;
4058
4059 i.rm.mode = 3;
4060 /* One of the register operands will be encoded in the i.tm.reg
4061 field, the other in the combined i.tm.mode and i.tm.regmem
4062 fields. If no form of this instruction supports a memory
4063 destination operand, then we assume the source operand may
4064 sometimes be a memory operand and so we need to store the
4065 destination in the i.rm.reg field. */
40fb9820
L		 4066 if (!i.tm.operand_types[dest].bitfield.regmem
4067 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4068 {
4069 i.rm.reg = i.op[dest].regs->reg_num;
4070 i.rm.regmem = i.op[source].regs->reg_num;
4071 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4072 i.rex |= REX_R;
29b0f896 4073 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4074 i.rex |= REX_B;
29b0f896
AM		 4075 }
4076 else
4077 {
4078 i.rm.reg = i.op[source].regs->reg_num;
4079 i.rm.regmem = i.op[dest].regs->reg_num;
4080 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4081 i.rex |= REX_B;
29b0f896 4082 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4083 i.rex |= REX_R;
29b0f896 4084 }
161a04f6 4085 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4086 {
40fb9820
L		 4087 if (!i.types[0].bitfield.control
4088 && !i.types[1].bitfield.control)
c4a530c5 4089 abort ();
161a04f6 4090 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4091 add_prefix (LOCK_PREFIX_OPCODE);
4092 }
29b0f896
AM		 4093 }
4094 else
4095 { /* If it's not 2 reg operands... */
4096 if (i.mem_operands)
4097 {
4098 unsigned int fake_zero_displacement = 0;
99018f42 4099 unsigned int op;
4eed87de 4100
99018f42 4101 for (op = 0; op < i.operands; op++)
40fb9820 4102 if (operand_type_check (i.types[op], anymem))
99018f42
L		 4103 break;
4104 assert (op < i.operands);
29b0f896
AM		 4105
4106 default_seg = &ds;
4107
4108 if (i.base_reg == 0)
4109 {
4110 i.rm.mode = 0;
4111 if (!i.disp_operands)
4112 fake_zero_displacement = 1;
4113 if (i.index_reg == 0)
4114 {
4115 /* Operand is just <disp> */
20f0a1fc 4116 if (flag_code == CODE_64BIT)
29b0f896
AM		 4117 {
4118 /* 64bit mode overwrites the 32bit absolute
4119 addressing by RIP relative addressing and
4120 absolute addressing is encoded by one of the
4121 redundant SIB forms. */
4122 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4123 i.sib.base = NO_BASE_REGISTER;
4124 i.sib.index = NO_INDEX_REGISTER;
fc225355 4125 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4126 ? disp32s : disp32);
20f0a1fc 4127 }
fc225355
L		 4128 else if ((flag_code == CODE_16BIT)
4129 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4130 {
4131 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4132 i.types[op] = disp16;
20f0a1fc
NC		 4133 }
4134 else
4135 {
4136 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4137 i.types[op] = disp32;
29b0f896
AM		 4138 }
4139 }
4140 else /* !i.base_reg && i.index_reg */
4141 {
4142 i.sib.index = i.index_reg->reg_num;
4143 i.sib.base = NO_BASE_REGISTER;
4144 i.sib.scale = i.log2_scale_factor;
4145 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4146 i.types[op].bitfield.disp8 = 0;
4147 i.types[op].bitfield.disp16 = 0;
4148 i.types[op].bitfield.disp64 = 0;
29b0f896 4149 if (flag_code != CODE_64BIT)
40fb9820
L		 4150 {
4151 /* Must be 32 bit */
4152 i.types[op].bitfield.disp32 = 1;
4153 i.types[op].bitfield.disp32s = 0;
4154 }
29b0f896 4155 else
40fb9820
L		 4156 {
4157 i.types[op].bitfield.disp32 = 0;
4158 i.types[op].bitfield.disp32s = 1;
4159 }
29b0f896 4160 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4161 i.rex |= REX_X;
29b0f896
AM		 4162 }
4163 }
4164 /* RIP addressing for 64bit mode. */
c6fb90c8 4165 else if (UINTS_EQUAL (i.base_reg->reg_type, baseindex))
29b0f896
AM		 4166 {
4167 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4168 i.types[op].bitfield.disp8 = 0;
4169 i.types[op].bitfield.disp16 = 0;
4170 i.types[op].bitfield.disp32 = 0;
4171 i.types[op].bitfield.disp32s = 1;
4172 i.types[op].bitfield.disp64 = 0;
71903a11 4173 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4174 if (! i.disp_operands)
4175 fake_zero_displacement = 1;
29b0f896 4176 }
40fb9820 4177 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4178 {
4179 switch (i.base_reg->reg_num)
4180 {
4181 case 3: /* (%bx) */
4182 if (i.index_reg == 0)
4183 i.rm.regmem = 7;
4184 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4185 i.rm.regmem = i.index_reg->reg_num - 6;
4186 break;
4187 case 5: /* (%bp) */
4188 default_seg = &ss;
4189 if (i.index_reg == 0)
4190 {
4191 i.rm.regmem = 6;
40fb9820 4192 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4193 {
4194 /* fake (%bp) into 0(%bp) */
40fb9820 4195 i.types[op].bitfield.disp8 = 1;
252b5132 4196 fake_zero_displacement = 1;
29b0f896
AM		 4197 }
4198 }
4199 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4200 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4201 break;
4202 default: /* (%si) -> 4 or (%di) -> 5 */
4203 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4204 }
4205 i.rm.mode = mode_from_disp_size (i.types[op]);
4206 }
4207 else /* i.base_reg and 32/64 bit mode */
4208 {
4209 if (flag_code == CODE_64BIT
40fb9820
L		 4210 && operand_type_check (i.types[op], disp))
4211 {
4212 i386_operand_type temp;
c6fb90c8 4213 UINTS_CLEAR (temp);
40fb9820
L		 4214 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4215 i.types[op] = temp;
4216 if (i.prefix[ADDR_PREFIX] == 0)
4217 i.types[op].bitfield.disp32s = 1;
4218 else
4219 i.types[op].bitfield.disp32 = 1;
4220 }
20f0a1fc 4221
29b0f896
AM		 4222 i.rm.regmem = i.base_reg->reg_num;
4223 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4224 i.rex |= REX_B;
29b0f896
AM		 4225 i.sib.base = i.base_reg->reg_num;
4226 /* x86-64 ignores REX prefix bit here to avoid decoder
4227 complications. */
4228 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4229 {
4230 default_seg = &ss;
4231 if (i.disp_operands == 0)
4232 {
4233 fake_zero_displacement = 1;
40fb9820 4234 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4235 }
4236 }
4237 else if (i.base_reg->reg_num == ESP_REG_NUM)
4238 {
4239 default_seg = &ss;
4240 }
4241 i.sib.scale = i.log2_scale_factor;
4242 if (i.index_reg == 0)
4243 {
4244 /* <disp>(%esp) becomes two byte modrm with no index
4245 register. We've already stored the code for esp
4246 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4247 Any base register besides %esp will not use the
4248 extra modrm byte. */
4249 i.sib.index = NO_INDEX_REGISTER;
4250#if !SCALE1_WHEN_NO_INDEX
4251 /* Another case where we force the second modrm byte. */
4252 if (i.log2_scale_factor)
4253 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 4254#endif
29b0f896
AM		 4255 }
4256 else
4257 {
4258 i.sib.index = i.index_reg->reg_num;
4259 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4260 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4261 i.rex |= REX_X;
29b0f896 4262 }
67a4f2b7
AO		 4263
4264 if (i.disp_operands
4265 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4266 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4267 i.rm.mode = 0;
4268 else
4269 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4270 }
252b5132 4271
29b0f896
AM		 4272 if (fake_zero_displacement)
4273 {
4274 /* Fakes a zero displacement assuming that i.types[op]
4275 holds the correct displacement size. */
4276 expressionS *exp;
4277
4278 assert (i.op[op].disps == 0);
4279 exp = &disp_expressions[i.disp_operands++];
4280 i.op[op].disps = exp;
4281 exp->X_op = O_constant;
4282 exp->X_add_number = 0;
4283 exp->X_add_symbol = (symbolS *) 0;
4284 exp->X_op_symbol = (symbolS *) 0;
4285 }
4286 }
252b5132 4287
29b0f896
AM		 4288 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4289 (if any) based on i.tm.extension_opcode. Again, we must be
4290 careful to make sure that segment/control/debug/test/MMX
4291 registers are coded into the i.rm.reg field. */
4292 if (i.reg_operands)
4293 {
99018f42
L		 4294 unsigned int op;
4295
4296 for (op = 0; op < i.operands; op++)
40fb9820
L		 4297 if (i.types[op].bitfield.reg8
4298 || i.types[op].bitfield.reg16
4299 || i.types[op].bitfield.reg32
4300 || i.types[op].bitfield.reg64
4301 || i.types[op].bitfield.regmmx
4302 || i.types[op].bitfield.regxmm
4303 || i.types[op].bitfield.sreg2
4304 || i.types[op].bitfield.sreg3
4305 || i.types[op].bitfield.control
4306 || i.types[op].bitfield.debug
4307 || i.types[op].bitfield.test)
99018f42
L		 4308 break;
4309 assert (op < i.operands);
4310
29b0f896
AM		 4311 /* If there is an extension opcode to put here, the register
4312 number must be put into the regmem field. */
4313 if (i.tm.extension_opcode != None)
4314 {
4315 i.rm.regmem = i.op[op].regs->reg_num;
4316 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4317 i.rex |= REX_B;
29b0f896
AM		 4318 }
4319 else
4320 {
4321 i.rm.reg = i.op[op].regs->reg_num;
4322 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4323 i.rex |= REX_R;
29b0f896 4324 }
252b5132 4325
29b0f896
AM		 4326 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4327 must set it to 3 to indicate this is a register operand
4328 in the regmem field. */
4329 if (!i.mem_operands)
4330 i.rm.mode = 3;
4331 }
252b5132 4332
29b0f896
AM		 4333 /* Fill in i.rm.reg field with extension opcode (if any). */
4334 if (i.tm.extension_opcode != None)
4335 i.rm.reg = i.tm.extension_opcode;
4336 }
4337 return default_seg;
4338}
252b5132 4339
29b0f896 4340static void
e3bb37b5 4341output_branch (void)
29b0f896
AM		 4342{
4343 char *p;
4344 int code16;
4345 int prefix;
4346 relax_substateT subtype;
4347 symbolS *sym;
4348 offsetT off;
4349
4350 code16 = 0;
4351 if (flag_code == CODE_16BIT)
4352 code16 = CODE16;
4353
4354 prefix = 0;
4355 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4356 {
29b0f896
AM		 4357 prefix = 1;
4358 i.prefixes -= 1;
4359 code16 ^= CODE16;
252b5132 4360 }
29b0f896
AM		 4361 /* Pentium4 branch hints. */
4362 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4363 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4364 {
29b0f896
AM		 4365 prefix++;
4366 i.prefixes--;
4367 }
4368 if (i.prefix[REX_PREFIX] != 0)
4369 {
4370 prefix++;
4371 i.prefixes--;
2f66722d
AM		 4372 }
4373
29b0f896
AM		 4374 if (i.prefixes != 0 && !intel_syntax)
4375 as_warn (_("skipping prefixes on this instruction"));
4376
4377 /* It's always a symbol; End frag & setup for relax.
4378 Make sure there is enough room in this frag for the largest
4379 instruction we may generate in md_convert_frag. This is 2
4380 bytes for the opcode and room for the prefix and largest
4381 displacement. */
4382 frag_grow (prefix + 2 + 4);
4383 /* Prefix and 1 opcode byte go in fr_fix. */
4384 p = frag_more (prefix + 1);
4385 if (i.prefix[DATA_PREFIX] != 0)
4386 *p++ = DATA_PREFIX_OPCODE;
4387 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4388 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4389 *p++ = i.prefix[SEG_PREFIX];
4390 if (i.prefix[REX_PREFIX] != 0)
4391 *p++ = i.prefix[REX_PREFIX];
4392 *p = i.tm.base_opcode;
4393
4394 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4395 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4396 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4397 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4398 else
4399 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4400 subtype |= code16;
3e73aa7c 4401
29b0f896
AM		 4402 sym = i.op[0].disps->X_add_symbol;
4403 off = i.op[0].disps->X_add_number;
3e73aa7c 4404
29b0f896
AM		 4405 if (i.op[0].disps->X_op != O_constant
4406 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4407 {
29b0f896
AM		 4408 /* Handle complex expressions. */
4409 sym = make_expr_symbol (i.op[0].disps);
4410 off = 0;
4411 }
3e73aa7c 4412
29b0f896
AM		 4413 /* 1 possible extra opcode + 4 byte displacement go in var part.
4414 Pass reloc in fr_var. */
4415 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4416}
3e73aa7c 4417
29b0f896 4418static void
e3bb37b5 4419output_jump (void)
29b0f896
AM		 4420{
4421 char *p;
4422 int size;
3e02c1cc 4423 fixS *fixP;
29b0f896 4424
40fb9820 4425 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4426 {
4427 /* This is a loop or jecxz type instruction. */
4428 size = 1;
4429 if (i.prefix[ADDR_PREFIX] != 0)
4430 {
4431 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4432 i.prefixes -= 1;
4433 }
4434 /* Pentium4 branch hints. */
4435 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4436 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4437 {
4438 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4439 i.prefixes--;
3e73aa7c
JH		 4440 }
4441 }
29b0f896
AM		 4442 else
4443 {
4444 int code16;
3e73aa7c 4445
29b0f896
AM		 4446 code16 = 0;
4447 if (flag_code == CODE_16BIT)
4448 code16 = CODE16;
3e73aa7c 4449
29b0f896
AM		 4450 if (i.prefix[DATA_PREFIX] != 0)
4451 {
4452 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4453 i.prefixes -= 1;
4454 code16 ^= CODE16;
4455 }
252b5132 4456
29b0f896
AM		 4457 size = 4;
4458 if (code16)
4459 size = 2;
4460 }
9fcc94b6 4461
29b0f896
AM		 4462 if (i.prefix[REX_PREFIX] != 0)
4463 {
4464 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4465 i.prefixes -= 1;
4466 }
252b5132 4467
29b0f896
AM		 4468 if (i.prefixes != 0 && !intel_syntax)
4469 as_warn (_("skipping prefixes on this instruction"));
e0890092 4470
29b0f896
AM		 4471 p = frag_more (1 + size);
4472 *p++ = i.tm.base_opcode;
e0890092 4473
3e02c1cc
AM		 4474 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4475 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4476
4477 /* All jumps handled here are signed, but don't use a signed limit
4478 check for 32 and 16 bit jumps as we want to allow wrap around at
4479 4G and 64k respectively. */
4480 if (size == 1)
4481 fixP->fx_signed = 1;
29b0f896 4482}
e0890092 4483
29b0f896 4484static void
e3bb37b5 4485output_interseg_jump (void)
29b0f896
AM		 4486{
4487 char *p;
4488 int size;
4489 int prefix;
4490 int code16;
252b5132 4491
29b0f896
AM		 4492 code16 = 0;
4493 if (flag_code == CODE_16BIT)
4494 code16 = CODE16;
a217f122 4495
29b0f896
AM		 4496 prefix = 0;
4497 if (i.prefix[DATA_PREFIX] != 0)
4498 {
4499 prefix = 1;
4500 i.prefixes -= 1;
4501 code16 ^= CODE16;
4502 }
4503 if (i.prefix[REX_PREFIX] != 0)
4504 {
4505 prefix++;
4506 i.prefixes -= 1;
4507 }
252b5132 4508
29b0f896
AM		 4509 size = 4;
4510 if (code16)
4511 size = 2;
252b5132 4512
29b0f896
AM		 4513 if (i.prefixes != 0 && !intel_syntax)
4514 as_warn (_("skipping prefixes on this instruction"));
252b5132 4515
29b0f896
AM		 4516 /* 1 opcode; 2 segment; offset */
4517 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4518
29b0f896
AM		 4519 if (i.prefix[DATA_PREFIX] != 0)
4520 *p++ = DATA_PREFIX_OPCODE;
252b5132 4521
29b0f896
AM		 4522 if (i.prefix[REX_PREFIX] != 0)
4523 *p++ = i.prefix[REX_PREFIX];
252b5132 4524
29b0f896
AM		 4525 *p++ = i.tm.base_opcode;
4526 if (i.op[1].imms->X_op == O_constant)
4527 {
4528 offsetT n = i.op[1].imms->X_add_number;
252b5132 4529
29b0f896
AM		 4530 if (size == 2
4531 && !fits_in_unsigned_word (n)
4532 && !fits_in_signed_word (n))
4533 {
4534 as_bad (_("16-bit jump out of range"));
4535 return;
4536 }
4537 md_number_to_chars (p, n, size);
4538 }
4539 else
4540 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4541 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4542 if (i.op[0].imms->X_op != O_constant)
4543 as_bad (_("can't handle non absolute segment in `%s'"),
4544 i.tm.name);
4545 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4546}
a217f122 4547
29b0f896 4548static void
e3bb37b5 4549output_insn (void)
29b0f896 4550{
2bbd9c25
JJ		 4551 fragS *insn_start_frag;
4552 offsetT insn_start_off;
4553
29b0f896
AM		 4554 /* Tie dwarf2 debug info to the address at the start of the insn.
4555 We can't do this after the insn has been output as the current
4556 frag may have been closed off. eg. by frag_var. */
4557 dwarf2_emit_insn (0);
4558
2bbd9c25
JJ		 4559 insn_start_frag = frag_now;
4560 insn_start_off = frag_now_fix ();
4561
29b0f896 4562 /* Output jumps. */
40fb9820 4563 if (i.tm.opcode_modifier.jump)
29b0f896 4564 output_branch ();
40fb9820
L		 4565 else if (i.tm.opcode_modifier.jumpbyte
4566 || i.tm.opcode_modifier.jumpdword)
29b0f896 4567 output_jump ();
40fb9820 4568 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4569 output_interseg_jump ();
4570 else
4571 {
4572 /* Output normal instructions here. */
4573 char *p;
4574 unsigned char *q;
331d2d0d 4575 unsigned int prefix;
40fb9820 4576 int opc_3b;
252b5132 4577
42903f7f 4578 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 4579 SSE4 instructions have 3 bytes. We may use one more higher
4580 byte to specify a prefix the instruction requires. Exclude
4581 instructions which are in both SSE4 and ABM. */
40fb9820
L		 4582 opc_3b = ((i.tm.cpu_flags.bitfield.cpussse3
4583 || i.tm.cpu_flags.bitfield.cpusse4_1
4584 || i.tm.cpu_flags.bitfield.cpusse4_2)
4585 && !i.tm.cpu_flags.bitfield.cpuabm);
4586 if (opc_3b)
bc4bd9ab 4587 {
331d2d0d
L		 4588 if (i.tm.base_opcode & 0xff000000)
4589 {
4590 prefix = (i.tm.base_opcode >> 24) & 0xff;
4591 goto check_prefix;
4592 }
4593 }
4594 else if ((i.tm.base_opcode & 0xff0000) != 0)
4595 {
4596 prefix = (i.tm.base_opcode >> 16) & 0xff;
40fb9820 4597 if (i.tm.cpu_flags.bitfield.cpupadlock)
bc4bd9ab 4598 {
64e74474 4599 check_prefix:
bc4bd9ab
MK		 4600 if (prefix != REPE_PREFIX_OPCODE
4601 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4602 add_prefix (prefix);
4603 }
4604 else
331d2d0d 4605 add_prefix (prefix);
0f10071e 4606 }
252b5132 4607
29b0f896
AM		 4608 /* The prefix bytes. */
4609 for (q = i.prefix;
4610 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4611 q++)
4612 {
4613 if (*q)
4614 {
4615 p = frag_more (1);
4616 md_number_to_chars (p, (valueT) *q, 1);
4617 }
4618 }
252b5132 4619
29b0f896
AM		 4620 /* Now the opcode; be careful about word order here! */
4621 if (fits_in_unsigned_byte (i.tm.base_opcode))
4622 {
4623 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4624 }
4625 else
4626 {
40fb9820 4627 if (opc_3b)
331d2d0d
L		 4628 {
4629 p = frag_more (3);
4630 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4631 }
4632 else
4633 p = frag_more (2);
0f10071e 4634
29b0f896
AM		 4635 /* Put out high byte first: can't use md_number_to_chars! */
4636 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4637 *p = i.tm.base_opcode & 0xff;
4638 }
3e73aa7c 4639
29b0f896 4640 /* Now the modrm byte and sib byte (if present). */
40fb9820 4641 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4642 {
4643 p = frag_more (1);
4644 md_number_to_chars (p,
4645 (valueT) (i.rm.regmem << 0
4646 | i.rm.reg << 3
4647 | i.rm.mode << 6),
4648 1);
4649 /* If i.rm.regmem == ESP (4)
4650 && i.rm.mode != (Register mode)
4651 && not 16 bit
4652 ==> need second modrm byte. */
4653 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4654 && i.rm.mode != 3
40fb9820 4655 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 4656 {
4657 p = frag_more (1);
4658 md_number_to_chars (p,
4659 (valueT) (i.sib.base << 0
4660 | i.sib.index << 3
4661 | i.sib.scale << 6),
4662 1);
4663 }
4664 }
3e73aa7c 4665
29b0f896 4666 if (i.disp_operands)
2bbd9c25 4667 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4668
29b0f896 4669 if (i.imm_operands)
2bbd9c25 4670 output_imm (insn_start_frag, insn_start_off);
29b0f896 4671 }
252b5132 4672
29b0f896
AM		 4673#ifdef DEBUG386
4674 if (flag_debug)
4675 {
7b81dfbb 4676 pi ("" /*line*/, &i);
29b0f896
AM		 4677 }
4678#endif /* DEBUG386 */
4679}
252b5132 4680
e205caa7
L		 4681/* Return the size of the displacement operand N. */
4682
4683static int
4684disp_size (unsigned int n)
4685{
4686 int size = 4;
40fb9820
L		 4687 if (i.types[n].bitfield.disp64)
4688 size = 8;
4689 else if (i.types[n].bitfield.disp8)
4690 size = 1;
4691 else if (i.types[n].bitfield.disp16)
4692 size = 2;
e205caa7
L		 4693 return size;
4694}
4695
4696/* Return the size of the immediate operand N. */
4697
4698static int
4699imm_size (unsigned int n)
4700{
4701 int size = 4;
40fb9820
L		 4702 if (i.types[n].bitfield.imm64)
4703 size = 8;
4704 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
4705 size = 1;
4706 else if (i.types[n].bitfield.imm16)
4707 size = 2;
e205caa7
L		 4708 return size;
4709}
4710
29b0f896 4711static void
64e74474 4712output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4713{
4714 char *p;
4715 unsigned int n;
252b5132 4716
29b0f896
AM		 4717 for (n = 0; n < i.operands; n++)
4718 {
40fb9820 4719 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 4720 {
4721 if (i.op[n].disps->X_op == O_constant)
4722 {
e205caa7 4723 int size = disp_size (n);
29b0f896 4724 offsetT val;
252b5132 4725
29b0f896
AM		 4726 val = offset_in_range (i.op[n].disps->X_add_number,
4727 size);
4728 p = frag_more (size);
4729 md_number_to_chars (p, val, size);
4730 }
4731 else
4732 {
f86103b7 4733 enum bfd_reloc_code_real reloc_type;
e205caa7 4734 int size = disp_size (n);
40fb9820 4735 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 4736 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4737
e205caa7 4738 /* We can't have 8 bit displacement here. */
40fb9820 4739 assert (!i.types[n].bitfield.disp8);
e205caa7 4740
29b0f896
AM		 4741 /* The PC relative address is computed relative
4742 to the instruction boundary, so in case immediate
4743 fields follows, we need to adjust the value. */
4744 if (pcrel && i.imm_operands)
4745 {
29b0f896 4746 unsigned int n1;
e205caa7 4747 int sz = 0;
252b5132 4748
29b0f896 4749 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 4750 if (operand_type_check (i.types[n1], imm))
252b5132 4751 {
e205caa7
L		 4752 /* Only one immediate is allowed for PC
4753 relative address. */
4754 assert (sz == 0);
4755 sz = imm_size (n1);
4756 i.op[n].disps->X_add_number -= sz;
252b5132 4757 }
29b0f896 4758 /* We should find the immediate. */
e205caa7 4759 assert (sz != 0);
29b0f896 4760 }
520dc8e8 4761
29b0f896 4762 p = frag_more (size);
2bbd9c25 4763 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4764 if (GOT_symbol
2bbd9c25 4765 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4766 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4767 || reloc_type == BFD_RELOC_X86_64_32S
4768 || (reloc_type == BFD_RELOC_64
4769 && object_64bit))
d6ab8113
JB		 4770 && (i.op[n].disps->X_op == O_symbol
4771 || (i.op[n].disps->X_op == O_add
4772 && ((symbol_get_value_expression
4773 (i.op[n].disps->X_op_symbol)->X_op)
4774 == O_subtract))))
4775 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4776 {
4777 offsetT add;
4778
4779 if (insn_start_frag == frag_now)
4780 add = (p - frag_now->fr_literal) - insn_start_off;
4781 else
4782 {
4783 fragS *fr;
4784
4785 add = insn_start_frag->fr_fix - insn_start_off;
4786 for (fr = insn_start_frag->fr_next;
4787 fr && fr != frag_now; fr = fr->fr_next)
4788 add += fr->fr_fix;
4789 add += p - frag_now->fr_literal;
4790 }
4791
4fa24527 4792 if (!object_64bit)
7b81dfbb
AJ		 4793 {
4794 reloc_type = BFD_RELOC_386_GOTPC;
4795 i.op[n].imms->X_add_number += add;
4796 }
4797 else if (reloc_type == BFD_RELOC_64)
4798 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4799 else
7b81dfbb
AJ		 4800 /* Don't do the adjustment for x86-64, as there
4801 the pcrel addressing is relative to the _next_
4802 insn, and that is taken care of in other code. */
d6ab8113 4803 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4804 }
062cd5e7 4805 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4806 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4807 }
4808 }
4809 }
4810}
252b5132 4811
29b0f896 4812static void
64e74474 4813output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4814{
4815 char *p;
4816 unsigned int n;
252b5132 4817
29b0f896
AM		 4818 for (n = 0; n < i.operands; n++)
4819 {
40fb9820 4820 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 4821 {
4822 if (i.op[n].imms->X_op == O_constant)
4823 {
e205caa7 4824 int size = imm_size (n);
29b0f896 4825 offsetT val;
b4cac588 4826
29b0f896
AM		 4827 val = offset_in_range (i.op[n].imms->X_add_number,
4828 size);
4829 p = frag_more (size);
4830 md_number_to_chars (p, val, size);
4831 }
4832 else
4833 {
4834 /* Not absolute_section.
4835 Need a 32-bit fixup (don't support 8bit
4836 non-absolute imms). Try to support other
4837 sizes ... */
f86103b7 4838 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4839 int size = imm_size (n);
4840 int sign;
29b0f896 4841
40fb9820 4842 if (i.types[n].bitfield.imm32s
a7d61044 4843 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 4844 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 4845 sign = 1;
e205caa7
L		 4846 else
4847 sign = 0;
520dc8e8 4848
29b0f896
AM		 4849 p = frag_more (size);
4850 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4851
2bbd9c25
JJ		 4852 /* This is tough to explain. We end up with this one if we
4853 * have operands that look like
4854 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4855 * obtain the absolute address of the GOT, and it is strongly
4856 * preferable from a performance point of view to avoid using
4857 * a runtime relocation for this. The actual sequence of
4858 * instructions often look something like:
4859 *
4860 * call .L66
4861 * .L66:
4862 * popl %ebx
4863 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4864 *
4865 * The call and pop essentially return the absolute address
4866 * of the label .L66 and store it in %ebx. The linker itself
4867 * will ultimately change the first operand of the addl so
4868 * that %ebx points to the GOT, but to keep things simple, the
4869 * .o file must have this operand set so that it generates not
4870 * the absolute address of .L66, but the absolute address of
4871 * itself. This allows the linker itself simply treat a GOTPC
4872 * relocation as asking for a pcrel offset to the GOT to be
4873 * added in, and the addend of the relocation is stored in the
4874 * operand field for the instruction itself.
4875 *
4876 * Our job here is to fix the operand so that it would add
4877 * the correct offset so that %ebx would point to itself. The
4878 * thing that is tricky is that .-.L66 will point to the
4879 * beginning of the instruction, so we need to further modify
4880 * the operand so that it will point to itself. There are
4881 * other cases where you have something like:
4882 *
4883 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4884 *
4885 * and here no correction would be required. Internally in
4886 * the assembler we treat operands of this form as not being
4887 * pcrel since the '.' is explicitly mentioned, and I wonder
4888 * whether it would simplify matters to do it this way. Who
4889 * knows. In earlier versions of the PIC patches, the
4890 * pcrel_adjust field was used to store the correction, but
4891 * since the expression is not pcrel, I felt it would be
4892 * confusing to do it this way. */
4893
d6ab8113 4894 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4895 || reloc_type == BFD_RELOC_X86_64_32S
4896 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4897 && GOT_symbol
4898 && GOT_symbol == i.op[n].imms->X_add_symbol
4899 && (i.op[n].imms->X_op == O_symbol
4900 || (i.op[n].imms->X_op == O_add
4901 && ((symbol_get_value_expression
4902 (i.op[n].imms->X_op_symbol)->X_op)
4903 == O_subtract))))
4904 {
2bbd9c25
JJ		 4905 offsetT add;
4906
4907 if (insn_start_frag == frag_now)
4908 add = (p - frag_now->fr_literal) - insn_start_off;
4909 else
4910 {
4911 fragS *fr;
4912
4913 add = insn_start_frag->fr_fix - insn_start_off;
4914 for (fr = insn_start_frag->fr_next;
4915 fr && fr != frag_now; fr = fr->fr_next)
4916 add += fr->fr_fix;
4917 add += p - frag_now->fr_literal;
4918 }
4919
4fa24527 4920 if (!object_64bit)
d6ab8113 4921 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4922 else if (size == 4)
d6ab8113 4923 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4924 else if (size == 8)
4925 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4926 i.op[n].imms->X_add_number += add;
29b0f896 4927 }
29b0f896
AM		 4928 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4929 i.op[n].imms, 0, reloc_type);
4930 }
4931 }
4932 }
252b5132
RH		 4933}
4934\f
d182319b
JB		 4935/* x86_cons_fix_new is called via the expression parsing code when a
4936 reloc is needed. We use this hook to get the correct .got reloc. */
4937static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4938static int cons_sign = -1;
4939
4940void
e3bb37b5 4941x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4942 expressionS *exp)
d182319b
JB		 4943{
4944 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4945
4946 got_reloc = NO_RELOC;
4947
4948#ifdef TE_PE
4949 if (exp->X_op == O_secrel)
4950 {
4951 exp->X_op = O_symbol;
4952 r = BFD_RELOC_32_SECREL;
4953 }
4954#endif
4955
4956 fix_new_exp (frag, off, len, exp, 0, r);
4957}
4958
718ddfc0
JB		 4959#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4960# define lex_got(reloc, adjust, types) NULL
4961#else
f3c180ae
AM		 4962/* Parse operands of the form
4963 <symbol>@GOTOFF+<nnn>
4964 and similar .plt or .got references.
4965
4966 If we find one, set up the correct relocation in RELOC and copy the
4967 input string, minus the `@GOTOFF' into a malloc'd buffer for
4968 parsing by the calling routine. Return this buffer, and if ADJUST
4969 is non-null set it to the length of the string we removed from the
4970 input line. Otherwise return NULL. */
4971static char *
3956db08 4972lex_got (enum bfd_reloc_code_real *reloc,
64e74474 4973 int *adjust,
40fb9820 4974 i386_operand_type *types)
f3c180ae 4975{
7b81dfbb
AJ		 4976 /* Some of the relocations depend on the size of what field is to
4977 be relocated. But in our callers i386_immediate and i386_displacement
4978 we don't yet know the operand size (this will be set by insn
4979 matching). Hence we record the word32 relocation here,
4980 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4981 static const struct {
4982 const char *str;
4fa24527 4983 const enum bfd_reloc_code_real rel[2];
40fb9820 4984 const i386_operand_type types64;
f3c180ae 4985 } gotrel[] = {
4eed87de
AM		 4986 { "PLTOFF", { 0,
4987 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 4988 OPERAND_TYPE_IMM64 },
4eed87de
AM		 4989 { "PLT", { BFD_RELOC_386_PLT32,
4990 BFD_RELOC_X86_64_PLT32 },
40fb9820 4991 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 4992 { "GOTPLT", { 0,
4993 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 4994 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 4995 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4996 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 4997 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 4998 { "GOTPCREL", { 0,
4999 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5000 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5001 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5002 BFD_RELOC_X86_64_TLSGD },
40fb9820 5003 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5004 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5005 0 },
40fb9820 5006 OPERAND_TYPE_NONE },
4eed87de
AM		 5007 { "TLSLD", { 0,
5008 BFD_RELOC_X86_64_TLSLD },
40fb9820 5009 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5010 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5011 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5012 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5013 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5014 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5015 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5016 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5017 0 },
40fb9820 5018 OPERAND_TYPE_NONE },
4eed87de
AM		 5019 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5020 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5021
5022 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5023 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5024 0 },
40fb9820 5025 OPERAND_TYPE_NONE },
4eed87de
AM		 5026 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5027 0 },
40fb9820 5028 OPERAND_TYPE_NONE },
4eed87de
AM		 5029 { "GOT", { BFD_RELOC_386_GOT32,
5030 BFD_RELOC_X86_64_GOT32 },
40fb9820 5031 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5032 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5033 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5034 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5035 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5036 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5037 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5038 };
5039 char *cp;
5040 unsigned int j;
5041
718ddfc0
JB		 5042 if (!IS_ELF)
5043 return NULL;
5044
f3c180ae 5045 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5046 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5047 return NULL;
5048
5049 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5050 {
5051 int len;
5052
5053 len = strlen (gotrel[j].str);
28f81592 5054 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5055 {
4fa24527 5056 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5057 {
28f81592
AM		 5058 int first, second;
5059 char *tmpbuf, *past_reloc;
f3c180ae 5060
4fa24527 5061 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5062 if (adjust)
5063 *adjust = len;
f3c180ae 5064
3956db08
JB		 5065 if (types)
5066 {
5067 if (flag_code != CODE_64BIT)
40fb9820
L		 5068 {
5069 types->bitfield.imm32 = 1;
5070 types->bitfield.disp32 = 1;
5071 }
3956db08
JB		 5072 else
5073 *types = gotrel[j].types64;
5074 }
5075
f3c180ae
AM		 5076 if (GOT_symbol == NULL)
5077 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5078
28f81592 5079 /* The length of the first part of our input line. */
f3c180ae 5080 first = cp - input_line_pointer;
28f81592
AM		 5081
5082 /* The second part goes from after the reloc token until
67c11a9b 5083 (and including) an end_of_line char or comma. */
28f81592 5084 past_reloc = cp + 1 + len;
67c11a9b
AM		 5085 cp = past_reloc;
5086 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5087 ++cp;
5088 second = cp + 1 - past_reloc;
28f81592
AM		 5089
5090 /* Allocate and copy string. The trailing NUL shouldn't
5091 be necessary, but be safe. */
5092 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5093 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5094 if (second != 0 && *past_reloc != ' ')
5095 /* Replace the relocation token with ' ', so that
5096 errors like foo@GOTOFF1 will be detected. */
5097 tmpbuf[first++] = ' ';
5098 memcpy (tmpbuf + first, past_reloc, second);
5099 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5100 return tmpbuf;
5101 }
5102
4fa24527
JB		 5103 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5104 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5105 return NULL;
5106 }
5107 }
5108
5109 /* Might be a symbol version string. Don't as_bad here. */
5110 return NULL;
5111}
5112
f3c180ae 5113void
e3bb37b5 5114x86_cons (expressionS *exp, int size)
f3c180ae 5115{
4fa24527 5116 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5117 {
5118 /* Handle @GOTOFF and the like in an expression. */
5119 char *save;
5120 char *gotfree_input_line;
5121 int adjust;
5122
5123 save = input_line_pointer;
3956db08 5124 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5125 if (gotfree_input_line)
5126 input_line_pointer = gotfree_input_line;
5127
5128 expression (exp);
5129
5130 if (gotfree_input_line)
5131 {
5132 /* expression () has merrily parsed up to the end of line,
5133 or a comma - in the wrong buffer. Transfer how far
5134 input_line_pointer has moved to the right buffer. */
5135 input_line_pointer = (save
5136 + (input_line_pointer - gotfree_input_line)
5137 + adjust);
5138 free (gotfree_input_line);
3992d3b7
AM		 5139 if (exp->X_op == O_constant
5140 || exp->X_op == O_absent
5141 || exp->X_op == O_illegal
5142 || exp->X_op == O_register
5143 || exp->X_op == O_big)
5144 {
5145 char c = *input_line_pointer;
5146 *input_line_pointer = 0;
5147 as_bad (_("missing or invalid expression `%s'"), save);
5148 *input_line_pointer = c;
5149 }
f3c180ae
AM		 5150 }
5151 }
5152 else
5153 expression (exp);
5154}
5155#endif
5156
d182319b 5157static void signed_cons (int size)
6482c264 5158{
d182319b
JB		 5159 if (flag_code == CODE_64BIT)
5160 cons_sign = 1;
5161 cons (size);
5162 cons_sign = -1;
6482c264
NC		 5163}
5164
d182319b 5165#ifdef TE_PE
6482c264
NC		 5166static void
5167pe_directive_secrel (dummy)
5168 int dummy ATTRIBUTE_UNUSED;
5169{
5170 expressionS exp;
5171
5172 do
5173 {
5174 expression (&exp);
5175 if (exp.X_op == O_symbol)
5176 exp.X_op = O_secrel;
5177
5178 emit_expr (&exp, 4);
5179 }
5180 while (*input_line_pointer++ == ',');
5181
5182 input_line_pointer--;
5183 demand_empty_rest_of_line ();
5184}
6482c264
NC		 5185#endif
5186
252b5132 5187static int
70e41ade 5188i386_immediate (char *imm_start)
252b5132
RH		 5189{
5190 char *save_input_line_pointer;
f3c180ae 5191 char *gotfree_input_line;
252b5132 5192 segT exp_seg = 0;
47926f60 5193 expressionS *exp;
40fb9820
L		 5194 i386_operand_type types;
5195
c6fb90c8 5196 UINTS_SET (types, ~0);
252b5132
RH		 5197
5198 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5199 {
31b2323c
L		 5200 as_bad (_("at most %d immediate operands are allowed"),
5201 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5202 return 0;
5203 }
5204
5205 exp = &im_expressions[i.imm_operands++];
520dc8e8 5206 i.op[this_operand].imms = exp;
252b5132
RH		 5207
5208 if (is_space_char (*imm_start))
5209 ++imm_start;
5210
5211 save_input_line_pointer = input_line_pointer;
5212 input_line_pointer = imm_start;
5213
3956db08 5214 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5215 if (gotfree_input_line)
5216 input_line_pointer = gotfree_input_line;
252b5132
RH		 5217
5218 exp_seg = expression (exp);
5219
83183c0c 5220 SKIP_WHITESPACE ();
252b5132 5221 if (*input_line_pointer)
f3c180ae 5222 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5223
5224 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5225 if (gotfree_input_line)
5226 free (gotfree_input_line);
252b5132 5227
3992d3b7
AM		 5228 if (exp->X_op == O_absent
5229 || exp->X_op == O_illegal
5230 || exp->X_op == O_big
5231 || (gotfree_input_line
5232 && (exp->X_op == O_constant
5233 || exp->X_op == O_register)))
252b5132 5234 {
3992d3b7 5235 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5236 imm_start);
3992d3b7 5237 return 0;
252b5132 5238 }
3e73aa7c 5239 else if (exp->X_op == O_constant)
252b5132 5240 {
47926f60 5241 /* Size it properly later. */
40fb9820 5242 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5243 /* If BFD64, sign extend val. */
4eed87de
AM		 5244 if (!use_rela_relocations
5245 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5246 exp->X_add_number
5247 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5248 }
4c63da97 5249#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5250 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5251 && exp_seg != absolute_section
47926f60 5252 && exp_seg != text_section
24eab124
AM		 5253 && exp_seg != data_section
5254 && exp_seg != bss_section
5255 && exp_seg != undefined_section
f86103b7 5256 && !bfd_is_com_section (exp_seg))
252b5132 5257 {
d0b47220 5258 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5259 return 0;
5260 }
5261#endif
bb8f5920
L		 5262 else if (!intel_syntax && exp->X_op == O_register)
5263 {
5264 as_bad (_("illegal immediate register operand %s"), imm_start);
5265 return 0;
5266 }
252b5132
RH		 5267 else
5268 {
5269 /* This is an address. The size of the address will be
24eab124 5270 determined later, depending on destination register,
3e73aa7c 5271 suffix, or the default for the section. */
40fb9820
L		 5272 i.types[this_operand].bitfield.imm8 = 1;
5273 i.types[this_operand].bitfield.imm16 = 1;
5274 i.types[this_operand].bitfield.imm32 = 1;
5275 i.types[this_operand].bitfield.imm32s = 1;
5276 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5277 i.types[this_operand] = operand_type_and (i.types[this_operand],
5278 types);
252b5132
RH		 5279 }
5280
5281 return 1;
5282}
5283
551c1ca1 5284static char *
e3bb37b5 5285i386_scale (char *scale)
252b5132 5286{
551c1ca1
AM		 5287 offsetT val;
5288 char *save = input_line_pointer;
252b5132 5289
551c1ca1
AM		 5290 input_line_pointer = scale;
5291 val = get_absolute_expression ();
5292
5293 switch (val)
252b5132 5294 {
551c1ca1 5295 case 1:
252b5132
RH		 5296 i.log2_scale_factor = 0;
5297 break;
551c1ca1 5298 case 2:
252b5132
RH		 5299 i.log2_scale_factor = 1;
5300 break;
551c1ca1 5301 case 4:
252b5132
RH		 5302 i.log2_scale_factor = 2;
5303 break;
551c1ca1 5304 case 8:
252b5132
RH		 5305 i.log2_scale_factor = 3;
5306 break;
5307 default:
a724f0f4
JB		 5308 {
5309 char sep = *input_line_pointer;
5310
5311 *input_line_pointer = '\0';
5312 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5313 scale);
5314 *input_line_pointer = sep;
5315 input_line_pointer = save;
5316 return NULL;
5317 }
252b5132 5318 }
29b0f896 5319 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5320 {
5321 as_warn (_("scale factor of %d without an index register"),
24eab124 5322 1 << i.log2_scale_factor);
252b5132
RH		 5323#if SCALE1_WHEN_NO_INDEX
5324 i.log2_scale_factor = 0;
5325#endif
5326 }
551c1ca1
AM		 5327 scale = input_line_pointer;
5328 input_line_pointer = save;
5329 return scale;
252b5132
RH		 5330}
5331
252b5132 5332static int
e3bb37b5 5333i386_displacement (char *disp_start, char *disp_end)
252b5132 5334{
29b0f896 5335 expressionS *exp;
252b5132
RH		 5336 segT exp_seg = 0;
5337 char *save_input_line_pointer;
f3c180ae 5338 char *gotfree_input_line;
40fb9820
L		 5339 int override;
5340 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5341 int ret;
252b5132 5342
31b2323c
L		 5343 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5344 {
5345 as_bad (_("at most %d displacement operands are allowed"),
5346 MAX_MEMORY_OPERANDS);
5347 return 0;
5348 }
5349
c6fb90c8 5350 UINTS_CLEAR (bigdisp);
40fb9820
L		 5351 if ((i.types[this_operand].bitfield.jumpabsolute)
5352 || (!current_templates->start->opcode_modifier.jump
5353 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5354 {
40fb9820 5355 bigdisp.bitfield.disp32 = 1;
e05278af 5356 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5357 if (flag_code == CODE_64BIT)
5358 {
5359 if (!override)
5360 {
5361 bigdisp.bitfield.disp32s = 1;
5362 bigdisp.bitfield.disp64 = 1;
5363 }
5364 }
5365 else if ((flag_code == CODE_16BIT) ^ override)
5366 {
5367 bigdisp.bitfield.disp32 = 0;
5368 bigdisp.bitfield.disp16 = 1;
5369 }
e05278af
JB		 5370 }
5371 else
5372 {
5373 /* For PC-relative branches, the width of the displacement
5374 is dependent upon data size, not address size. */
e05278af 5375 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5376 if (flag_code == CODE_64BIT)
5377 {
5378 if (override || i.suffix == WORD_MNEM_SUFFIX)
5379 bigdisp.bitfield.disp16 = 1;
5380 else
5381 {
5382 bigdisp.bitfield.disp32 = 1;
5383 bigdisp.bitfield.disp32s = 1;
5384 }
5385 }
5386 else
e05278af
JB		 5387 {
5388 if (!override)
5389 override = (i.suffix == (flag_code != CODE_16BIT
5390 ? WORD_MNEM_SUFFIX
5391 : LONG_MNEM_SUFFIX));
40fb9820
L		 5392 bigdisp.bitfield.disp32 = 1;
5393 if ((flag_code == CODE_16BIT) ^ override)
5394 {
5395 bigdisp.bitfield.disp32 = 0;
5396 bigdisp.bitfield.disp16 = 1;
5397 }
e05278af 5398 }
e05278af 5399 }
c6fb90c8
L		 5400 i.types[this_operand] = operand_type_or (i.types[this_operand],
5401 bigdisp);
252b5132
RH		 5402
5403 exp = &disp_expressions[i.disp_operands];
520dc8e8 5404 i.op[this_operand].disps = exp;
252b5132
RH		 5405 i.disp_operands++;
5406 save_input_line_pointer = input_line_pointer;
5407 input_line_pointer = disp_start;
5408 END_STRING_AND_SAVE (disp_end);
5409
5410#ifndef GCC_ASM_O_HACK
5411#define GCC_ASM_O_HACK 0
5412#endif
5413#if GCC_ASM_O_HACK
5414 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5415 if (i.types[this_operand].bitfield.baseIndex
24eab124 5416 && displacement_string_end[-1] == '+')
252b5132
RH		 5417 {
5418 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5419 constraint within gcc asm statements.
5420 For instance:
5421
5422 #define _set_tssldt_desc(n,addr,limit,type) \
5423 __asm__ __volatile__ ( \
5424 "movw %w2,%0\n\t" \
5425 "movw %w1,2+%0\n\t" \
5426 "rorl $16,%1\n\t" \
5427 "movb %b1,4+%0\n\t" \
5428 "movb %4,5+%0\n\t" \
5429 "movb $0,6+%0\n\t" \
5430 "movb %h1,7+%0\n\t" \
5431 "rorl $16,%1" \
5432 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5433
5434 This works great except that the output assembler ends
5435 up looking a bit weird if it turns out that there is
5436 no offset. You end up producing code that looks like:
5437
5438 #APP
5439 movw $235,(%eax)
5440 movw %dx,2+(%eax)
5441 rorl $16,%edx
5442 movb %dl,4+(%eax)
5443 movb $137,5+(%eax)
5444 movb $0,6+(%eax)
5445 movb %dh,7+(%eax)
5446 rorl $16,%edx
5447 #NO_APP
5448
47926f60 5449 So here we provide the missing zero. */
24eab124
AM		 5450
5451 *displacement_string_end = '0';
252b5132
RH		 5452 }
5453#endif
3956db08 5454 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5455 if (gotfree_input_line)
5456 input_line_pointer = gotfree_input_line;
252b5132 5457
24eab124 5458 exp_seg = expression (exp);
252b5132 5459
636c26b0
AM		 5460 SKIP_WHITESPACE ();
5461 if (*input_line_pointer)
5462 as_bad (_("junk `%s' after expression"), input_line_pointer);
5463#if GCC_ASM_O_HACK
5464 RESTORE_END_STRING (disp_end + 1);
5465#endif
636c26b0 5466 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5467 if (gotfree_input_line)
5468 free (gotfree_input_line);
3992d3b7 5469 ret = 1;
636c26b0 5470
24eab124
AM		 5471 /* We do this to make sure that the section symbol is in
5472 the symbol table. We will ultimately change the relocation
47926f60 5473 to be relative to the beginning of the section. */
1ae12ab7 5474 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5475 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5476 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5477 {
636c26b0 5478 if (exp->X_op != O_symbol)
3992d3b7 5479 goto inv_disp;
636c26b0 5480
e5cb08ac 5481 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5482 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5483 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5484 exp->X_op = O_subtract;
5485 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5486 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5487 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5488 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5489 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5490 else
29b0f896 5491 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5492 }
252b5132 5493
3992d3b7
AM		 5494 else if (exp->X_op == O_absent
5495 || exp->X_op == O_illegal
5496 || exp->X_op == O_big
5497 || (gotfree_input_line
5498 && (exp->X_op == O_constant
5499 || exp->X_op == O_register)))
2daf4fd8 5500 {
3992d3b7
AM		 5501 inv_disp:
5502 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5503 disp_start);
3992d3b7 5504 ret = 0;
2daf4fd8
AM		 5505 }
5506
4c63da97 5507#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5508 else if (exp->X_op != O_constant
5509 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5510 && exp_seg != absolute_section
5511 && exp_seg != text_section
5512 && exp_seg != data_section
5513 && exp_seg != bss_section
5514 && exp_seg != undefined_section
5515 && !bfd_is_com_section (exp_seg))
24eab124 5516 {
d0b47220 5517 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5518 ret = 0;
24eab124 5519 }
252b5132 5520#endif
3956db08 5521
3992d3b7
AM		 5522 RESTORE_END_STRING (disp_end);
5523
40fb9820
L		 5524 /* Check if this is a displacement only operand. */
5525 bigdisp = i.types[this_operand];
5526 bigdisp.bitfield.disp8 = 0;
5527 bigdisp.bitfield.disp16 = 0;
5528 bigdisp.bitfield.disp32 = 0;
5529 bigdisp.bitfield.disp32s = 0;
5530 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5531 if (UINTS_ALL_ZERO (bigdisp))
5532 i.types[this_operand] = operand_type_and (i.types[this_operand],
5533 types);
3956db08 5534
3992d3b7 5535 return ret;
252b5132
RH		 5536}
5537
eecb386c 5538/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5539 Return 1 on success, 0 on a failure. */
5540
252b5132 5541static int
e3bb37b5 5542i386_index_check (const char *operand_string)
252b5132 5543{
3e73aa7c 5544 int ok;
24eab124 5545#if INFER_ADDR_PREFIX
eecb386c
AM		 5546 int fudged = 0;
5547
24eab124
AM		 5548 tryprefix:
5549#endif
3e73aa7c 5550 ok = 1;
75178d9d 5551 if (flag_code == CODE_64BIT)
64e74474 5552 {
64e74474 5553 if ((i.base_reg
40fb9820
L		 5554 && ((i.prefix[ADDR_PREFIX] == 0
5555 && !i.base_reg->reg_type.bitfield.reg64)
5556 || (i.prefix[ADDR_PREFIX]
5557 && !i.base_reg->reg_type.bitfield.reg32))
5558 && (i.index_reg
c6fb90c8 5559 || !UINTS_EQUAL (i.base_reg->reg_type, baseindex)))
64e74474 5560 || (i.index_reg
40fb9820
L		 5561 && (!i.index_reg->reg_type.bitfield.baseindex
5562 || (i.prefix[ADDR_PREFIX] == 0
5563 && !i.index_reg->reg_type.bitfield.reg64)
5564 || (i.prefix[ADDR_PREFIX]
5565 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5566 ok = 0;
3e73aa7c
JH		 5567 }
5568 else
5569 {
5570 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5571 {
5572 /* 16bit checks. */
5573 if ((i.base_reg
40fb9820
L		 5574 && (!i.base_reg->reg_type.bitfield.reg16
5575 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 5576 || (i.index_reg
40fb9820
L		 5577 && (!i.index_reg->reg_type.bitfield.reg16
5578 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 5579 || !(i.base_reg
5580 && i.base_reg->reg_num < 6
5581 && i.index_reg->reg_num >= 6
5582 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 5583 ok = 0;
5584 }
5585 else
e5cb08ac 5586 {
3e73aa7c
JH		 5587 /* 32bit checks. */
5588 if ((i.base_reg
40fb9820 5589 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 5590 || (i.index_reg
40fb9820
L		 5591 && (!i.index_reg->reg_type.bitfield.reg32
5592 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 5593 ok = 0;
3e73aa7c
JH		 5594 }
5595 }
5596 if (!ok)
24eab124
AM		 5597 {
5598#if INFER_ADDR_PREFIX
20f0a1fc 5599 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 5600 {
5601 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
5602 i.prefixes += 1;
b23bac36
AM		 5603 /* Change the size of any displacement too. At most one of
5604 Disp16 or Disp32 is set.
5605 FIXME. There doesn't seem to be any real need for separate
5606 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 5607 Removing them would probably clean up the code quite a lot. */
4eed87de 5608 if (flag_code != CODE_64BIT
40fb9820
L		 5609 && (i.types[this_operand].bitfield.disp16
5610 || i.types[this_operand].bitfield.disp32))
5611 i.types[this_operand]
c6fb90c8 5612 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 5613 fudged = 1;
24eab124
AM		 5614 goto tryprefix;
5615 }
eecb386c
AM		 5616 if (fudged)
5617 as_bad (_("`%s' is not a valid base/index expression"),
5618 operand_string);
5619 else
c388dee8 5620#endif
eecb386c
AM		 5621 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5622 operand_string,
3e73aa7c 5623 flag_code_names[flag_code]);
24eab124 5624 }
20f0a1fc 5625 return ok;
24eab124 5626}
252b5132 5627
252b5132 5628/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5629 on error. */
252b5132 5630
252b5132 5631static int
e3bb37b5 5632i386_operand (char *operand_string)
252b5132 5633{
af6bdddf
AM		 5634 const reg_entry *r;
5635 char *end_op;
24eab124 5636 char *op_string = operand_string;
252b5132 5637
24eab124 5638 if (is_space_char (*op_string))
252b5132
RH		 5639 ++op_string;
5640
24eab124 5641 /* We check for an absolute prefix (differentiating,
47926f60 5642 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5643 if (*op_string == ABSOLUTE_PREFIX)
5644 {
5645 ++op_string;
5646 if (is_space_char (*op_string))
5647 ++op_string;
40fb9820 5648 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 5649 }
252b5132 5650
47926f60 5651 /* Check if operand is a register. */
4d1bb795 5652 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5653 {
40fb9820
L		 5654 i386_operand_type temp;
5655
24eab124
AM		 5656 /* Check for a segment override by searching for ':' after a
5657 segment register. */
5658 op_string = end_op;
5659 if (is_space_char (*op_string))
5660 ++op_string;
40fb9820
L		 5661 if (*op_string == ':'
5662 && (r->reg_type.bitfield.sreg2
5663 || r->reg_type.bitfield.sreg3))
24eab124
AM		 5664 {
5665 switch (r->reg_num)
5666 {
5667 case 0:
5668 i.seg[i.mem_operands] = &es;
5669 break;
5670 case 1:
5671 i.seg[i.mem_operands] = &cs;
5672 break;
5673 case 2:
5674 i.seg[i.mem_operands] = &ss;
5675 break;
5676 case 3:
5677 i.seg[i.mem_operands] = &ds;
5678 break;
5679 case 4:
5680 i.seg[i.mem_operands] = &fs;
5681 break;
5682 case 5:
5683 i.seg[i.mem_operands] = &gs;
5684 break;
5685 }
252b5132 5686
24eab124 5687 /* Skip the ':' and whitespace. */
252b5132
RH		 5688 ++op_string;
5689 if (is_space_char (*op_string))
24eab124 5690 ++op_string;
252b5132 5691
24eab124
AM		 5692 if (!is_digit_char (*op_string)
5693 && !is_identifier_char (*op_string)
5694 && *op_string != '('
5695 && *op_string != ABSOLUTE_PREFIX)
5696 {
5697 as_bad (_("bad memory operand `%s'"), op_string);
5698 return 0;
5699 }
47926f60 5700 /* Handle case of %es:*foo. */
24eab124
AM		 5701 if (*op_string == ABSOLUTE_PREFIX)
5702 {
5703 ++op_string;
5704 if (is_space_char (*op_string))
5705 ++op_string;
40fb9820 5706 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 5707 }
5708 goto do_memory_reference;
5709 }
5710 if (*op_string)
5711 {
d0b47220 5712 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5713 return 0;
5714 }
40fb9820
L		 5715 temp = r->reg_type;
5716 temp.bitfield.baseindex = 0;
c6fb90c8
L		 5717 i.types[this_operand] = operand_type_or (i.types[this_operand],
5718 temp);
520dc8e8 5719 i.op[this_operand].regs = r;
24eab124
AM		 5720 i.reg_operands++;
5721 }
af6bdddf
AM		 5722 else if (*op_string == REGISTER_PREFIX)
5723 {
5724 as_bad (_("bad register name `%s'"), op_string);
5725 return 0;
5726 }
24eab124 5727 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5728 {
24eab124 5729 ++op_string;
40fb9820 5730 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 5731 {
d0b47220 5732 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5733 return 0;
5734 }
5735 if (!i386_immediate (op_string))
5736 return 0;
5737 }
5738 else if (is_digit_char (*op_string)
5739 || is_identifier_char (*op_string)
e5cb08ac 5740 || *op_string == '(')
24eab124 5741 {
47926f60 5742 /* This is a memory reference of some sort. */
af6bdddf 5743 char *base_string;
252b5132 5744
47926f60 5745 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5746 char *displacement_string_start;
5747 char *displacement_string_end;
252b5132 5748
24eab124 5749 do_memory_reference:
24eab124 5750 if ((i.mem_operands == 1
40fb9820 5751 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 5752 || i.mem_operands == 2)
5753 {
5754 as_bad (_("too many memory references for `%s'"),
5755 current_templates->start->name);
5756 return 0;
5757 }
252b5132 5758
24eab124
AM		 5759 /* Check for base index form. We detect the base index form by
5760 looking for an ')' at the end of the operand, searching
5761 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5762 after the '('. */
af6bdddf 5763 base_string = op_string + strlen (op_string);
c3332e24 5764
af6bdddf
AM		 5765 --base_string;
5766 if (is_space_char (*base_string))
5767 --base_string;
252b5132 5768
47926f60 5769 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5770 displacement_string_start = op_string;
5771 displacement_string_end = base_string + 1;
252b5132 5772
24eab124
AM		 5773 if (*base_string == ')')
5774 {
af6bdddf 5775 char *temp_string;
24eab124
AM		 5776 unsigned int parens_balanced = 1;
5777 /* We've already checked that the number of left & right ()'s are
47926f60 5778 equal, so this loop will not be infinite. */
24eab124
AM		 5779 do
5780 {
5781 base_string--;
5782 if (*base_string == ')')
5783 parens_balanced++;
5784 if (*base_string == '(')
5785 parens_balanced--;
5786 }
5787 while (parens_balanced);
c3332e24 5788
af6bdddf 5789 temp_string = base_string;
c3332e24 5790
24eab124 5791 /* Skip past '(' and whitespace. */
252b5132
RH		 5792 ++base_string;
5793 if (is_space_char (*base_string))
24eab124 5794 ++base_string;
252b5132 5795
af6bdddf 5796 if (*base_string == ','
4eed87de
AM		 5797 || ((i.base_reg = parse_register (base_string, &end_op))
5798 != NULL))
252b5132 5799 {
af6bdddf 5800 displacement_string_end = temp_string;
252b5132 5801
40fb9820 5802 i.types[this_operand].bitfield.baseindex = 1;
252b5132 5803
af6bdddf 5804 if (i.base_reg)
24eab124 5805 {
24eab124
AM		 5806 base_string = end_op;
5807 if (is_space_char (*base_string))
5808 ++base_string;
af6bdddf
AM		 5809 }
5810
5811 /* There may be an index reg or scale factor here. */
5812 if (*base_string == ',')
5813 {
5814 ++base_string;
5815 if (is_space_char (*base_string))
5816 ++base_string;
5817
4eed87de
AM		 5818 if ((i.index_reg = parse_register (base_string, &end_op))
5819 != NULL)
24eab124 5820 {
af6bdddf 5821 base_string = end_op;
24eab124
AM		 5822 if (is_space_char (*base_string))
5823 ++base_string;
af6bdddf
AM		 5824 if (*base_string == ',')
5825 {
5826 ++base_string;
5827 if (is_space_char (*base_string))
5828 ++base_string;
5829 }
e5cb08ac 5830 else if (*base_string != ')')
af6bdddf 5831 {
4eed87de
AM		 5832 as_bad (_("expecting `,' or `)' "
5833 "after index register in `%s'"),
af6bdddf
AM		 5834 operand_string);
5835 return 0;
5836 }
24eab124 5837 }
af6bdddf 5838 else if (*base_string == REGISTER_PREFIX)
24eab124 5839 {
af6bdddf 5840 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5841 return 0;
5842 }
252b5132 5843
47926f60 5844 /* Check for scale factor. */
551c1ca1 5845 if (*base_string != ')')
af6bdddf 5846 {
551c1ca1
AM		 5847 char *end_scale = i386_scale (base_string);
5848
5849 if (!end_scale)
af6bdddf 5850 return 0;
24eab124 5851
551c1ca1 5852 base_string = end_scale;
af6bdddf
AM		 5853 if (is_space_char (*base_string))
5854 ++base_string;
5855 if (*base_string != ')')
5856 {
4eed87de
AM		 5857 as_bad (_("expecting `)' "
5858 "after scale factor in `%s'"),
af6bdddf
AM		 5859 operand_string);
5860 return 0;
5861 }
5862 }
5863 else if (!i.index_reg)
24eab124 5864 {
4eed87de
AM		 5865 as_bad (_("expecting index register or scale factor "
5866 "after `,'; got '%c'"),
af6bdddf 5867 *base_string);
24eab124
AM		 5868 return 0;
5869 }
5870 }
af6bdddf 5871 else if (*base_string != ')')
24eab124 5872 {
4eed87de
AM		 5873 as_bad (_("expecting `,' or `)' "
5874 "after base register in `%s'"),
af6bdddf 5875 operand_string);
24eab124
AM		 5876 return 0;
5877 }
c3332e24 5878 }
af6bdddf 5879 else if (*base_string == REGISTER_PREFIX)
c3332e24 5880 {
af6bdddf 5881 as_bad (_("bad register name `%s'"), base_string);
24eab124 5882 return 0;
c3332e24 5883 }
24eab124
AM		 5884 }
5885
5886 /* If there's an expression beginning the operand, parse it,
5887 assuming displacement_string_start and
5888 displacement_string_end are meaningful. */
5889 if (displacement_string_start != displacement_string_end)
5890 {
5891 if (!i386_displacement (displacement_string_start,
5892 displacement_string_end))
5893 return 0;
5894 }
5895
5896 /* Special case for (%dx) while doing input/output op. */
5897 if (i.base_reg
c6fb90c8 5898 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 5899 && i.index_reg == 0
5900 && i.log2_scale_factor == 0
5901 && i.seg[i.mem_operands] == 0
40fb9820 5902 && !operand_type_check (i.types[this_operand], disp))
24eab124 5903 {
c6fb90c8 5904 UINTS_CLEAR (i.types[this_operand]);
40fb9820 5905 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 5906 return 1;
5907 }
5908
eecb386c
AM		 5909 if (i386_index_check (operand_string) == 0)
5910 return 0;
24eab124
AM		 5911 i.mem_operands++;
5912 }
5913 else
ce8a8b2f
AM		 5914 {
5915 /* It's not a memory operand; argh! */
24eab124
AM		 5916 as_bad (_("invalid char %s beginning operand %d `%s'"),
5917 output_invalid (*op_string),
5918 this_operand + 1,
5919 op_string);
5920 return 0;
5921 }
47926f60 5922 return 1; /* Normal return. */
252b5132
RH		 5923}
5924\f
ee7fcc42
AM		 5925/* md_estimate_size_before_relax()
5926
5927 Called just before relax() for rs_machine_dependent frags. The x86
5928 assembler uses these frags to handle variable size jump
5929 instructions.
5930
5931 Any symbol that is now undefined will not become defined.
5932 Return the correct fr_subtype in the frag.
5933 Return the initial "guess for variable size of frag" to caller.
5934 The guess is actually the growth beyond the fixed part. Whatever
5935 we do to grow the fixed or variable part contributes to our
5936 returned value. */
5937
252b5132
RH		 5938int
5939md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5940 fragS *fragP;
5941 segT segment;
252b5132 5942{
252b5132 5943 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5944 check for un-relaxable symbols. On an ELF system, we can't relax
5945 an externally visible symbol, because it may be overridden by a
5946 shared library. */
5947 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5948#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5949 || (IS_ELF
31312f95
AM		 5950 && (S_IS_EXTERNAL (fragP->fr_symbol)
5951 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5952#endif
5953 )
252b5132 5954 {
b98ef147
AM		 5955 /* Symbol is undefined in this segment, or we need to keep a
5956 reloc so that weak symbols can be overridden. */
5957 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5958 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5959 unsigned char *opcode;
5960 int old_fr_fix;
f6af82bd 5961
ee7fcc42
AM		 5962 if (fragP->fr_var != NO_RELOC)
5963 reloc_type = fragP->fr_var;
b98ef147 5964 else if (size == 2)
f6af82bd
AM		 5965 reloc_type = BFD_RELOC_16_PCREL;
5966 else
5967 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5968
ee7fcc42
AM		 5969 old_fr_fix = fragP->fr_fix;
5970 opcode = (unsigned char *) fragP->fr_opcode;
5971
fddf5b5b 5972 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5973 {
fddf5b5b
AM		 5974 case UNCOND_JUMP:
5975 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5976 opcode[0] = 0xe9;
252b5132 5977 fragP->fr_fix += size;
062cd5e7
AS		 5978 fix_new (fragP, old_fr_fix, size,
5979 fragP->fr_symbol,
5980 fragP->fr_offset, 1,
5981 reloc_type);
252b5132
RH		 5982 break;
5983
fddf5b5b 5984 case COND_JUMP86:
412167cb
AM		 5985 if (size == 2
5986 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5987 {
5988 /* Negate the condition, and branch past an
5989 unconditional jump. */
5990 opcode[0] ^= 1;
5991 opcode[1] = 3;
5992 /* Insert an unconditional jump. */
5993 opcode[2] = 0xe9;
5994 /* We added two extra opcode bytes, and have a two byte
5995 offset. */
5996 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5997 fix_new (fragP, old_fr_fix + 2, 2,
5998 fragP->fr_symbol,
5999 fragP->fr_offset, 1,
6000 reloc_type);
fddf5b5b
AM		 6001 break;
6002 }
6003 /* Fall through. */
6004
6005 case COND_JUMP:
412167cb
AM		 6006 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6007 {
3e02c1cc
AM		 6008 fixS *fixP;
6009
412167cb 6010 fragP->fr_fix += 1;
3e02c1cc
AM		 6011 fixP = fix_new (fragP, old_fr_fix, 1,
6012 fragP->fr_symbol,
6013 fragP->fr_offset, 1,
6014 BFD_RELOC_8_PCREL);
6015 fixP->fx_signed = 1;
412167cb
AM		 6016 break;
6017 }
93c2a809 6018
24eab124 6019 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6020 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6021 opcode[1] = opcode[0] + 0x10;
f6af82bd 6022 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6023 /* We've added an opcode byte. */
6024 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6025 fix_new (fragP, old_fr_fix + 1, size,
6026 fragP->fr_symbol,
6027 fragP->fr_offset, 1,
6028 reloc_type);
252b5132 6029 break;
fddf5b5b
AM		 6030
6031 default:
6032 BAD_CASE (fragP->fr_subtype);
6033 break;
252b5132
RH		 6034 }
6035 frag_wane (fragP);
ee7fcc42 6036 return fragP->fr_fix - old_fr_fix;
252b5132 6037 }
93c2a809 6038
93c2a809
AM		 6039 /* Guess size depending on current relax state. Initially the relax
6040 state will correspond to a short jump and we return 1, because
6041 the variable part of the frag (the branch offset) is one byte
6042 long. However, we can relax a section more than once and in that
6043 case we must either set fr_subtype back to the unrelaxed state,
6044 or return the value for the appropriate branch. */
6045 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6046}
6047
47926f60
KH		 6048/* Called after relax() is finished.
6049
6050 In: Address of frag.
6051 fr_type == rs_machine_dependent.
6052 fr_subtype is what the address relaxed to.
6053
6054 Out: Any fixSs and constants are set up.
6055 Caller will turn frag into a ".space 0". */
6056
252b5132
RH		 6057void
6058md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6059 bfd *abfd ATTRIBUTE_UNUSED;
6060 segT sec ATTRIBUTE_UNUSED;
29b0f896 6061 fragS *fragP;
252b5132 6062{
29b0f896 6063 unsigned char *opcode;
252b5132 6064 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6065 offsetT target_address;
6066 offsetT opcode_address;
252b5132 6067 unsigned int extension = 0;
847f7ad4 6068 offsetT displacement_from_opcode_start;
252b5132
RH		 6069
6070 opcode = (unsigned char *) fragP->fr_opcode;
6071
47926f60 6072 /* Address we want to reach in file space. */
252b5132 6073 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6074
47926f60 6075 /* Address opcode resides at in file space. */
252b5132
RH		 6076 opcode_address = fragP->fr_address + fragP->fr_fix;
6077
47926f60 6078 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6079 displacement_from_opcode_start = target_address - opcode_address;
6080
fddf5b5b 6081 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6082 {
47926f60
KH		 6083 /* Don't have to change opcode. */
6084 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6085 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6086 }
6087 else
6088 {
6089 if (no_cond_jump_promotion
6090 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6091 as_warn_where (fragP->fr_file, fragP->fr_line,
6092 _("long jump required"));
252b5132 6093
fddf5b5b
AM		 6094 switch (fragP->fr_subtype)
6095 {
6096 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6097 extension = 4; /* 1 opcode + 4 displacement */
6098 opcode[0] = 0xe9;
6099 where_to_put_displacement = &opcode[1];
6100 break;
252b5132 6101
fddf5b5b
AM		 6102 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6103 extension = 2; /* 1 opcode + 2 displacement */
6104 opcode[0] = 0xe9;
6105 where_to_put_displacement = &opcode[1];
6106 break;
252b5132 6107
fddf5b5b
AM		 6108 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6109 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6110 extension = 5; /* 2 opcode + 4 displacement */
6111 opcode[1] = opcode[0] + 0x10;
6112 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6113 where_to_put_displacement = &opcode[2];
6114 break;
252b5132 6115
fddf5b5b
AM		 6116 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6117 extension = 3; /* 2 opcode + 2 displacement */
6118 opcode[1] = opcode[0] + 0x10;
6119 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6120 where_to_put_displacement = &opcode[2];
6121 break;
252b5132 6122
fddf5b5b
AM		 6123 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6124 extension = 4;
6125 opcode[0] ^= 1;
6126 opcode[1] = 3;
6127 opcode[2] = 0xe9;
6128 where_to_put_displacement = &opcode[3];
6129 break;
6130
6131 default:
6132 BAD_CASE (fragP->fr_subtype);
6133 break;
6134 }
252b5132 6135 }
fddf5b5b 6136
7b81dfbb
AJ		 6137 /* If size if less then four we are sure that the operand fits,
6138 but if it's 4, then it could be that the displacement is larger
6139 then -/+ 2GB. */
6140 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6141 && object_64bit
6142 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6143 + ((addressT) 1 << 31))
6144 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6145 {
6146 as_bad_where (fragP->fr_file, fragP->fr_line,
6147 _("jump target out of range"));
6148 /* Make us emit 0. */
6149 displacement_from_opcode_start = extension;
6150 }
47926f60 6151 /* Now put displacement after opcode. */
252b5132
RH		 6152 md_number_to_chars ((char *) where_to_put_displacement,
6153 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6154 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6155 fragP->fr_fix += extension;
6156}
6157\f
47926f60
KH		 6158/* Size of byte displacement jmp. */
6159int md_short_jump_size = 2;
6160
6161/* Size of dword displacement jmp. */
6162int md_long_jump_size = 5;
252b5132 6163
252b5132
RH		 6164void
6165md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6166 char *ptr;
6167 addressT from_addr, to_addr;
ab9da554
ILT		 6168 fragS *frag ATTRIBUTE_UNUSED;
6169 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6170{
847f7ad4 6171 offsetT offset;
252b5132
RH		 6172
6173 offset = to_addr - (from_addr + 2);
47926f60
KH		 6174 /* Opcode for byte-disp jump. */
6175 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6176 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6177}
6178
6179void
6180md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6181 char *ptr;
6182 addressT from_addr, to_addr;
a38cf1db
AM		 6183 fragS *frag ATTRIBUTE_UNUSED;
6184 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6185{
847f7ad4 6186 offsetT offset;
252b5132 6187
a38cf1db
AM		 6188 offset = to_addr - (from_addr + 5);
6189 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6190 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6191}
6192\f
6193/* Apply a fixup (fixS) to segment data, once it has been determined
6194 by our caller that we have all the info we need to fix it up.
6195
6196 On the 386, immediates, displacements, and data pointers are all in
6197 the same (little-endian) format, so we don't need to care about which
6198 we are handling. */
6199
94f592af 6200void
55cf6793 6201md_apply_fix (fixP, valP, seg)
47926f60
KH		 6202 /* The fix we're to put in. */
6203 fixS *fixP;
47926f60 6204 /* Pointer to the value of the bits. */
c6682705 6205 valueT *valP;
47926f60
KH		 6206 /* Segment fix is from. */
6207 segT seg ATTRIBUTE_UNUSED;
252b5132 6208{
94f592af 6209 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6210 valueT value = *valP;
252b5132 6211
f86103b7 6212#if !defined (TE_Mach)
93382f6d
AM		 6213 if (fixP->fx_pcrel)
6214 {
6215 switch (fixP->fx_r_type)
6216 {
5865bb77
ILT		 6217 default:
6218 break;
6219
d6ab8113
JB		 6220 case BFD_RELOC_64:
6221 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6222 break;
93382f6d 6223 case BFD_RELOC_32:
ae8887b5 6224 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6225 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6226 break;
6227 case BFD_RELOC_16:
6228 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6229 break;
6230 case BFD_RELOC_8:
6231 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6232 break;
6233 }
6234 }
252b5132 6235
a161fe53 6236 if (fixP->fx_addsy != NULL
31312f95 6237 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6238 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6239 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6240 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6241 && !use_rela_relocations)
252b5132 6242 {
31312f95
AM		 6243 /* This is a hack. There should be a better way to handle this.
6244 This covers for the fact that bfd_install_relocation will
6245 subtract the current location (for partial_inplace, PC relative
6246 relocations); see more below. */
252b5132 6247#ifndef OBJ_AOUT
718ddfc0 6248 if (IS_ELF
252b5132
RH		 6249#ifdef TE_PE
6250 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6251#endif
6252 )
6253 value += fixP->fx_where + fixP->fx_frag->fr_address;
6254#endif
6255#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6256 if (IS_ELF)
252b5132 6257 {
6539b54b 6258 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6259
6539b54b 6260 if ((sym_seg == seg
2f66722d 6261 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6262 && sym_seg != absolute_section))
ae6063d4 6263 && !generic_force_reloc (fixP))
2f66722d
AM		 6264 {
6265 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6266 bfd_install_relocation subtracts them out again. I think
6267 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6268 it. FIXME. */
6269 value += fixP->fx_where + fixP->fx_frag->fr_address;
6270 }
252b5132
RH		 6271 }
6272#endif
6273#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6274 /* For some reason, the PE format does not store a
6275 section address offset for a PC relative symbol. */
6276 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6277 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6278 value += md_pcrel_from (fixP);
6279#endif
6280 }
6281
6282 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6283 and we must not disappoint it. */
252b5132 6284#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6285 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6286 switch (fixP->fx_r_type)
6287 {
6288 case BFD_RELOC_386_PLT32:
3e73aa7c 6289 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6290 /* Make the jump instruction point to the address of the operand. At
6291 runtime we merely add the offset to the actual PLT entry. */
6292 value = -4;
6293 break;
31312f95 6294
13ae64f3
JJ		 6295 case BFD_RELOC_386_TLS_GD:
6296 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6297 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6298 case BFD_RELOC_386_TLS_IE:
6299 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6300 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6301 case BFD_RELOC_X86_64_TLSGD:
6302 case BFD_RELOC_X86_64_TLSLD:
6303 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6304 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6305 value = 0; /* Fully resolved at runtime. No addend. */
6306 /* Fallthrough */
6307 case BFD_RELOC_386_TLS_LE:
6308 case BFD_RELOC_386_TLS_LDO_32:
6309 case BFD_RELOC_386_TLS_LE_32:
6310 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6311 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6312 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6313 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6314 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6315 break;
6316
67a4f2b7
AO		 6317 case BFD_RELOC_386_TLS_DESC_CALL:
6318 case BFD_RELOC_X86_64_TLSDESC_CALL:
6319 value = 0; /* Fully resolved at runtime. No addend. */
6320 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6321 fixP->fx_done = 0;
6322 return;
6323
00f7efb6
JJ		 6324 case BFD_RELOC_386_GOT32:
6325 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6326 value = 0; /* Fully resolved at runtime. No addend. */
6327 break;
47926f60
KH		 6328
6329 case BFD_RELOC_VTABLE_INHERIT:
6330 case BFD_RELOC_VTABLE_ENTRY:
6331 fixP->fx_done = 0;
94f592af 6332 return;
47926f60
KH		 6333
6334 default:
6335 break;
6336 }
6337#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6338 *valP = value;
f86103b7 6339#endif /* !defined (TE_Mach) */
3e73aa7c 6340
3e73aa7c 6341 /* Are we finished with this relocation now? */
c6682705 6342 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6343 fixP->fx_done = 1;
6344 else if (use_rela_relocations)
6345 {
6346 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6347 /* Remember value for tc_gen_reloc. */
6348 fixP->fx_addnumber = value;
3e73aa7c
JH		 6349 value = 0;
6350 }
f86103b7 6351
94f592af 6352 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6353}
252b5132 6354\f
252b5132
RH		 6355#define MAX_LITTLENUMS 6
6356
47926f60
KH		 6357/* Turn the string pointed to by litP into a floating point constant
6358 of type TYPE, and emit the appropriate bytes. The number of
6359 LITTLENUMS emitted is stored in *SIZEP. An error message is
6360 returned, or NULL on OK. */
6361
252b5132
RH		 6362char *
6363md_atof (type, litP, sizeP)
2ab9b79e 6364 int type;
252b5132
RH		 6365 char *litP;
6366 int *sizeP;
6367{
6368 int prec;
6369 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6370 LITTLENUM_TYPE *wordP;
6371 char *t;
6372
6373 switch (type)
6374 {
6375 case 'f':
6376 case 'F':
6377 prec = 2;
6378 break;
6379
6380 case 'd':
6381 case 'D':
6382 prec = 4;
6383 break;
6384
6385 case 'x':
6386 case 'X':
6387 prec = 5;
6388 break;
6389
6390 default:
6391 *sizeP = 0;
6392 return _("Bad call to md_atof ()");
6393 }
6394 t = atof_ieee (input_line_pointer, type, words);
6395 if (t)
6396 input_line_pointer = t;
6397
6398 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6399 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6400 the bigendian 386. */
6401 for (wordP = words + prec - 1; prec--;)
6402 {
6403 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6404 litP += sizeof (LITTLENUM_TYPE);
6405 }
6406 return 0;
6407}
6408\f
2d545b82 6409static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6410
252b5132 6411static char *
e3bb37b5 6412output_invalid (int c)
252b5132 6413{
3882b010 6414 if (ISPRINT (c))
f9f21a03
L		 6415 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6416 "'%c'", c);
252b5132 6417 else
f9f21a03 6418 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6419 "(0x%x)", (unsigned char) c);
252b5132
RH		 6420 return output_invalid_buf;
6421}
6422
af6bdddf 6423/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6424
6425static const reg_entry *
4d1bb795 6426parse_real_register (char *reg_string, char **end_op)
252b5132 6427{
af6bdddf
AM		 6428 char *s = reg_string;
6429 char *p;
252b5132
RH		 6430 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6431 const reg_entry *r;
6432
6433 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6434 if (*s == REGISTER_PREFIX)
6435 ++s;
6436
6437 if (is_space_char (*s))
6438 ++s;
6439
6440 p = reg_name_given;
af6bdddf 6441 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6442 {
6443 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6444 return (const reg_entry *) NULL;
6445 s++;
252b5132
RH		 6446 }
6447
6588847e
DN		 6448 /* For naked regs, make sure that we are not dealing with an identifier.
6449 This prevents confusing an identifier like `eax_var' with register
6450 `eax'. */
6451 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6452 return (const reg_entry *) NULL;
6453
af6bdddf 6454 *end_op = s;
252b5132
RH		 6455
6456 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6457
5f47d35b 6458 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6459 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6460 {
5f47d35b
AM		 6461 if (is_space_char (*s))
6462 ++s;
6463 if (*s == '(')
6464 {
af6bdddf 6465 ++s;
5f47d35b
AM		 6466 if (is_space_char (*s))
6467 ++s;
6468 if (*s >= '0' && *s <= '7')
6469 {
db557034 6470 int fpr = *s - '0';
af6bdddf 6471 ++s;
5f47d35b
AM		 6472 if (is_space_char (*s))
6473 ++s;
6474 if (*s == ')')
6475 {
6476 *end_op = s + 1;
db557034
AM		 6477 r = hash_find (reg_hash, "st(0)");
6478 know (r);
6479 return r + fpr;
5f47d35b 6480 }
5f47d35b 6481 }
47926f60 6482 /* We have "%st(" then garbage. */
5f47d35b
AM		 6483 return (const reg_entry *) NULL;
6484 }
6485 }
6486
1ae00879 6487 if (r != NULL
d946b91f 6488 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6489 || r->reg_type.bitfield.reg64)
6490 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6491 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6492 && flag_code != CODE_64BIT)
20f0a1fc 6493 return (const reg_entry *) NULL;
1ae00879 6494
252b5132
RH		 6495 return r;
6496}
4d1bb795
JB		 6497
6498/* REG_STRING starts *before* REGISTER_PREFIX. */
6499
6500static const reg_entry *
6501parse_register (char *reg_string, char **end_op)
6502{
6503 const reg_entry *r;
6504
6505 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6506 r = parse_real_register (reg_string, end_op);
6507 else
6508 r = NULL;
6509 if (!r)
6510 {
6511 char *save = input_line_pointer;
6512 char c;
6513 symbolS *symbolP;
6514
6515 input_line_pointer = reg_string;
6516 c = get_symbol_end ();
6517 symbolP = symbol_find (reg_string);
6518 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6519 {
6520 const expressionS *e = symbol_get_value_expression (symbolP);
6521
6522 know (e->X_op == O_register);
4eed87de 6523 know (e->X_add_number >= 0
c3fe08fa 6524 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6525 r = i386_regtab + e->X_add_number;
6526 *end_op = input_line_pointer;
6527 }
6528 *input_line_pointer = c;
6529 input_line_pointer = save;
6530 }
6531 return r;
6532}
6533
6534int
6535i386_parse_name (char *name, expressionS *e, char *nextcharP)
6536{
6537 const reg_entry *r;
6538 char *end = input_line_pointer;
6539
6540 *end = *nextcharP;
6541 r = parse_register (name, &input_line_pointer);
6542 if (r && end <= input_line_pointer)
6543 {
6544 *nextcharP = *input_line_pointer;
6545 *input_line_pointer = 0;
6546 e->X_op = O_register;
6547 e->X_add_number = r - i386_regtab;
6548 return 1;
6549 }
6550 input_line_pointer = end;
6551 *end = 0;
6552 return 0;
6553}
6554
6555void
6556md_operand (expressionS *e)
6557{
6558 if (*input_line_pointer == REGISTER_PREFIX)
6559 {
6560 char *end;
6561 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6562
6563 if (r)
6564 {
6565 e->X_op = O_register;
6566 e->X_add_number = r - i386_regtab;
6567 input_line_pointer = end;
6568 }
6569 }
6570}
6571
252b5132 6572\f
4cc782b5 6573#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6574const char *md_shortopts = "kVQ:sqn";
252b5132 6575#else
12b55ccc 6576const char *md_shortopts = "qn";
252b5132 6577#endif
6e0b89ee 6578
3e73aa7c 6579#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6580#define OPTION_64 (OPTION_MD_BASE + 1)
6581#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6582#define OPTION_MARCH (OPTION_MD_BASE + 3)
6583#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 6584
99ad8390
NC		 6585struct option md_longopts[] =
6586{
3e73aa7c 6587 {"32", no_argument, NULL, OPTION_32},
99ad8390 6588#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6589 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6590#endif
b3b91714 6591 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6592 {"march", required_argument, NULL, OPTION_MARCH},
6593 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6594 {NULL, no_argument, NULL, 0}
6595};
6596size_t md_longopts_size = sizeof (md_longopts);
6597
6598int
9103f4f4 6599md_parse_option (int c, char *arg)
252b5132 6600{
9103f4f4
L		 6601 unsigned int i;
6602
252b5132
RH		 6603 switch (c)
6604 {
12b55ccc
L		 6605 case 'n':
6606 optimize_align_code = 0;
6607 break;
6608
a38cf1db
AM		 6609 case 'q':
6610 quiet_warnings = 1;
252b5132
RH		 6611 break;
6612
6613#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6614 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6615 should be emitted or not. FIXME: Not implemented. */
6616 case 'Q':
252b5132
RH		 6617 break;
6618
6619 /* -V: SVR4 argument to print version ID. */
6620 case 'V':
6621 print_version_id ();
6622 break;
6623
a38cf1db
AM		 6624 /* -k: Ignore for FreeBSD compatibility. */
6625 case 'k':
252b5132 6626 break;
4cc782b5
ILT		 6627
6628 case 's':
6629 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6630 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6631 break;
99ad8390
NC		 6632#endif
6633#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6634 case OPTION_64:
6635 {
6636 const char **list, **l;
6637
3e73aa7c
JH		 6638 list = bfd_target_list ();
6639 for (l = list; *l != NULL; l++)
8620418b 6640 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6641 || strcmp (*l, "coff-x86-64") == 0
6642 || strcmp (*l, "pe-x86-64") == 0
6643 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6644 {
6645 default_arch = "x86_64";
6646 break;
6647 }
3e73aa7c 6648 if (*l == NULL)
6e0b89ee 6649 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6650 free (list);
6651 }
6652 break;
6653#endif
252b5132 6654
6e0b89ee
AM		 6655 case OPTION_32:
6656 default_arch = "i386";
6657 break;
6658
b3b91714
AM		 6659 case OPTION_DIVIDE:
6660#ifdef SVR4_COMMENT_CHARS
6661 {
6662 char *n, *t;
6663 const char *s;
6664
6665 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6666 t = n;
6667 for (s = i386_comment_chars; *s != '\0'; s++)
6668 if (*s != '/')
6669 *t++ = *s;
6670 *t = '\0';
6671 i386_comment_chars = n;
6672 }
6673#endif
6674 break;
6675
9103f4f4
L		 6676 case OPTION_MARCH:
6677 if (*arg == '.')
6678 as_fatal (_("Invalid -march= option: `%s'"), arg);
6679 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6680 {
6681 if (strcmp (arg, cpu_arch [i].name) == 0)
6682 {
ccc9c027 6683 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6684 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6685 if (!cpu_arch_tune_set)
6686 {
6687 cpu_arch_tune = cpu_arch_isa;
6688 cpu_arch_tune_flags = cpu_arch_isa_flags;
6689 }
9103f4f4
L		 6690 break;
6691 }
6692 }
6693 if (i >= ARRAY_SIZE (cpu_arch))
6694 as_fatal (_("Invalid -march= option: `%s'"), arg);
6695 break;
6696
6697 case OPTION_MTUNE:
6698 if (*arg == '.')
6699 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6700 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6701 {
6702 if (strcmp (arg, cpu_arch [i].name) == 0)
6703 {
ccc9c027 6704 cpu_arch_tune_set = 1;
9103f4f4
L		 6705 cpu_arch_tune = cpu_arch [i].type;
6706 cpu_arch_tune_flags = cpu_arch[i].flags;
6707 break;
6708 }
6709 }
6710 if (i >= ARRAY_SIZE (cpu_arch))
6711 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6712 break;
6713
252b5132
RH		 6714 default:
6715 return 0;
6716 }
6717 return 1;
6718}
6719
6720void
6721md_show_usage (stream)
6722 FILE *stream;
6723{
4cc782b5
ILT		 6724#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6725 fprintf (stream, _("\
a38cf1db
AM		 6726 -Q ignored\n\
6727 -V print assembler version number\n\
b3b91714
AM		 6728 -k ignored\n"));
6729#endif
6730 fprintf (stream, _("\
12b55ccc 6731 -n Do not optimize code alignment\n\
b3b91714
AM		 6732 -q quieten some warnings\n"));
6733#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6734 fprintf (stream, _("\
a38cf1db 6735 -s ignored\n"));
b3b91714 6736#endif
751d281c
L		 6737#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6738 fprintf (stream, _("\
6739 --32/--64 generate 32bit/64bit code\n"));
6740#endif
b3b91714
AM		 6741#ifdef SVR4_COMMENT_CHARS
6742 fprintf (stream, _("\
6743 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6744#else
6745 fprintf (stream, _("\
b3b91714 6746 --divide ignored\n"));
4cc782b5 6747#endif
9103f4f4
L		 6748 fprintf (stream, _("\
6749 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6750 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6751 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6752
252b5132
RH		 6753}
6754
3e73aa7c 6755#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 6756 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 6757
6758/* Pick the target format to use. */
6759
47926f60 6760const char *
e3bb37b5 6761i386_target_format (void)
252b5132 6762{
3e73aa7c 6763 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6764 {
6765 set_code_flag (CODE_64BIT);
c6fb90c8 6766 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 6767 {
6768 cpu_arch_isa_flags.bitfield.cpui186 = 1;
6769 cpu_arch_isa_flags.bitfield.cpui286 = 1;
6770 cpu_arch_isa_flags.bitfield.cpui386 = 1;
6771 cpu_arch_isa_flags.bitfield.cpui486 = 1;
6772 cpu_arch_isa_flags.bitfield.cpui586 = 1;
6773 cpu_arch_isa_flags.bitfield.cpui686 = 1;
6774 cpu_arch_isa_flags.bitfield.cpup4 = 1;
6775 cpu_arch_isa_flags.bitfield.cpummx= 1;
6776 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
6777 cpu_arch_isa_flags.bitfield.cpusse = 1;
6778 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
6779 }
c6fb90c8 6780 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 6781 {
6782 cpu_arch_tune_flags.bitfield.cpui186 = 1;
6783 cpu_arch_tune_flags.bitfield.cpui286 = 1;
6784 cpu_arch_tune_flags.bitfield.cpui386 = 1;
6785 cpu_arch_tune_flags.bitfield.cpui486 = 1;
6786 cpu_arch_tune_flags.bitfield.cpui586 = 1;
6787 cpu_arch_tune_flags.bitfield.cpui686 = 1;
6788 cpu_arch_tune_flags.bitfield.cpup4 = 1;
6789 cpu_arch_tune_flags.bitfield.cpummx= 1;
6790 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
6791 cpu_arch_tune_flags.bitfield.cpusse = 1;
6792 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
6793 }
9103f4f4 6794 }
3e73aa7c 6795 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6796 {
6797 set_code_flag (CODE_32BIT);
c6fb90c8 6798 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 6799 {
6800 cpu_arch_isa_flags.bitfield.cpui186 = 1;
6801 cpu_arch_isa_flags.bitfield.cpui286 = 1;
6802 cpu_arch_isa_flags.bitfield.cpui386 = 1;
6803 }
c6fb90c8 6804 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 6805 {
6806 cpu_arch_tune_flags.bitfield.cpui186 = 1;
6807 cpu_arch_tune_flags.bitfield.cpui286 = 1;
6808 cpu_arch_tune_flags.bitfield.cpui386 = 1;
6809 }
9103f4f4 6810 }
3e73aa7c
JH		 6811 else
6812 as_fatal (_("Unknown architecture"));
252b5132
RH		 6813 switch (OUTPUT_FLAVOR)
6814 {
872ce6ff
L		 6815#ifdef TE_PEP
6816 case bfd_target_coff_flavour:
6817 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
6818 break;
6819#endif
4c63da97
AM		 6820#ifdef OBJ_MAYBE_AOUT
6821 case bfd_target_aout_flavour:
47926f60 6822 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6823#endif
6824#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6825 case bfd_target_coff_flavour:
6826 return "coff-i386";
4c63da97 6827#endif
3e73aa7c 6828#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6829 case bfd_target_elf_flavour:
3e73aa7c 6830 {
e5cb08ac 6831 if (flag_code == CODE_64BIT)
4fa24527
JB		 6832 {
6833 object_64bit = 1;
6834 use_rela_relocations = 1;
6835 }
9d7cbccd 6836 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6837 }
4c63da97 6838#endif
252b5132
RH		 6839 default:
6840 abort ();
6841 return NULL;
6842 }
6843}
6844
47926f60 6845#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6846
6847#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6848void
6849i386_elf_emit_arch_note (void)
a847613f 6850{
718ddfc0 6851 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6852 {
6853 char *p;
6854 asection *seg = now_seg;
6855 subsegT subseg = now_subseg;
6856 Elf_Internal_Note i_note;
6857 Elf_External_Note e_note;
6858 asection *note_secp;
6859 int len;
6860
6861 /* Create the .note section. */
6862 note_secp = subseg_new (".note", 0);
6863 bfd_set_section_flags (stdoutput,
6864 note_secp,
6865 SEC_HAS_CONTENTS | SEC_READONLY);
6866
6867 /* Process the arch string. */
6868 len = strlen (cpu_arch_name);
6869
6870 i_note.namesz = len + 1;
6871 i_note.descsz = 0;
6872 i_note.type = NT_ARCH;
6873 p = frag_more (sizeof (e_note.namesz));
6874 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6875 p = frag_more (sizeof (e_note.descsz));
6876 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6877 p = frag_more (sizeof (e_note.type));
6878 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6879 p = frag_more (len + 1);
6880 strcpy (p, cpu_arch_name);
6881
6882 frag_align (2, 0, 0);
6883
6884 subseg_set (seg, subseg);
6885 }
6886}
6887#endif
252b5132 6888\f
252b5132
RH		 6889symbolS *
6890md_undefined_symbol (name)
6891 char *name;
6892{
18dc2407
ILT		 6893 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6894 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6895 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6896 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6897 {
6898 if (!GOT_symbol)
6899 {
6900 if (symbol_find (name))
6901 as_bad (_("GOT already in symbol table"));
6902 GOT_symbol = symbol_new (name, undefined_section,
6903 (valueT) 0, &zero_address_frag);
6904 };
6905 return GOT_symbol;
6906 }
252b5132
RH		 6907 return 0;
6908}
6909
6910/* Round up a section size to the appropriate boundary. */
47926f60 6911
252b5132
RH		 6912valueT
6913md_section_align (segment, size)
ab9da554 6914 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6915 valueT size;
6916{
4c63da97
AM		 6917#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6918 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6919 {
6920 /* For a.out, force the section size to be aligned. If we don't do
6921 this, BFD will align it for us, but it will not write out the
6922 final bytes of the section. This may be a bug in BFD, but it is
6923 easier to fix it here since that is how the other a.out targets
6924 work. */
6925 int align;
6926
6927 align = bfd_get_section_alignment (stdoutput, segment);
6928 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6929 }
252b5132
RH		 6930#endif
6931
6932 return size;
6933}
6934
6935/* On the i386, PC-relative offsets are relative to the start of the
6936 next instruction. That is, the address of the offset, plus its
6937 size, since the offset is always the last part of the insn. */
6938
6939long
e3bb37b5 6940md_pcrel_from (fixS *fixP)
252b5132
RH		 6941{
6942 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6943}
6944
6945#ifndef I386COFF
6946
6947static void
e3bb37b5 6948s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6949{
29b0f896 6950 int temp;
252b5132 6951
8a75718c
JB		 6952#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6953 if (IS_ELF)
6954 obj_elf_section_change_hook ();
6955#endif
252b5132
RH		 6956 temp = get_absolute_expression ();
6957 subseg_set (bss_section, (subsegT) temp);
6958 demand_empty_rest_of_line ();
6959}
6960
6961#endif
6962
252b5132 6963void
e3bb37b5 6964i386_validate_fix (fixS *fixp)
252b5132
RH		 6965{
6966 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6967 {
23df1078
JH		 6968 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6969 {
4fa24527 6970 if (!object_64bit)
23df1078
JH		 6971 abort ();
6972 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6973 }
6974 else
6975 {
4fa24527 6976 if (!object_64bit)
d6ab8113
JB		 6977 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6978 else
6979 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6980 }
252b5132
RH		 6981 fixp->fx_subsy = 0;
6982 }
6983}
6984
252b5132
RH		 6985arelent *
6986tc_gen_reloc (section, fixp)
ab9da554 6987 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6988 fixS *fixp;
6989{
6990 arelent *rel;
6991 bfd_reloc_code_real_type code;
6992
6993 switch (fixp->fx_r_type)
6994 {
3e73aa7c
JH		 6995 case BFD_RELOC_X86_64_PLT32:
6996 case BFD_RELOC_X86_64_GOT32:
6997 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6998 case BFD_RELOC_386_PLT32:
6999 case BFD_RELOC_386_GOT32:
7000 case BFD_RELOC_386_GOTOFF:
7001 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7002 case BFD_RELOC_386_TLS_GD:
7003 case BFD_RELOC_386_TLS_LDM:
7004 case BFD_RELOC_386_TLS_LDO_32:
7005 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7006 case BFD_RELOC_386_TLS_IE:
7007 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7008 case BFD_RELOC_386_TLS_LE_32:
7009 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7010 case BFD_RELOC_386_TLS_GOTDESC:
7011 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7012 case BFD_RELOC_X86_64_TLSGD:
7013 case BFD_RELOC_X86_64_TLSLD:
7014 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7015 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7016 case BFD_RELOC_X86_64_GOTTPOFF:
7017 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7018 case BFD_RELOC_X86_64_TPOFF64:
7019 case BFD_RELOC_X86_64_GOTOFF64:
7020 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7021 case BFD_RELOC_X86_64_GOT64:
7022 case BFD_RELOC_X86_64_GOTPCREL64:
7023 case BFD_RELOC_X86_64_GOTPC64:
7024 case BFD_RELOC_X86_64_GOTPLT64:
7025 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7026 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7027 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7028 case BFD_RELOC_RVA:
7029 case BFD_RELOC_VTABLE_ENTRY:
7030 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7031#ifdef TE_PE
7032 case BFD_RELOC_32_SECREL:
7033#endif
252b5132
RH		 7034 code = fixp->fx_r_type;
7035 break;
dbbaec26
L		 7036 case BFD_RELOC_X86_64_32S:
7037 if (!fixp->fx_pcrel)
7038 {
7039 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7040 code = fixp->fx_r_type;
7041 break;
7042 }
252b5132 7043 default:
93382f6d 7044 if (fixp->fx_pcrel)
252b5132 7045 {
93382f6d
AM		 7046 switch (fixp->fx_size)
7047 {
7048 default:
b091f402
AM		 7049 as_bad_where (fixp->fx_file, fixp->fx_line,
7050 _("can not do %d byte pc-relative relocation"),
7051 fixp->fx_size);
93382f6d
AM		 7052 code = BFD_RELOC_32_PCREL;
7053 break;
7054 case 1: code = BFD_RELOC_8_PCREL; break;
7055 case 2: code = BFD_RELOC_16_PCREL; break;
7056 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7057#ifdef BFD64
7058 case 8: code = BFD_RELOC_64_PCREL; break;
7059#endif
93382f6d
AM		 7060 }
7061 }
7062 else
7063 {
7064 switch (fixp->fx_size)
7065 {
7066 default:
b091f402
AM		 7067 as_bad_where (fixp->fx_file, fixp->fx_line,
7068 _("can not do %d byte relocation"),
7069 fixp->fx_size);
93382f6d
AM		 7070 code = BFD_RELOC_32;
7071 break;
7072 case 1: code = BFD_RELOC_8; break;
7073 case 2: code = BFD_RELOC_16; break;
7074 case 4: code = BFD_RELOC_32; break;
937149dd 7075#ifdef BFD64
3e73aa7c 7076 case 8: code = BFD_RELOC_64; break;
937149dd 7077#endif
93382f6d 7078 }
252b5132
RH		 7079 }
7080 break;
7081 }
252b5132 7082
d182319b
JB		 7083 if ((code == BFD_RELOC_32
7084 || code == BFD_RELOC_32_PCREL
7085 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7086 && GOT_symbol
7087 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7088 {
4fa24527 7089 if (!object_64bit)
d6ab8113
JB		 7090 code = BFD_RELOC_386_GOTPC;
7091 else
7092 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7093 }
7b81dfbb
AJ		 7094 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7095 && GOT_symbol
7096 && fixp->fx_addsy == GOT_symbol)
7097 {
7098 code = BFD_RELOC_X86_64_GOTPC64;
7099 }
252b5132
RH		 7100
7101 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7102 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7103 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7104
7105 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7106
3e73aa7c
JH		 7107 if (!use_rela_relocations)
7108 {
7109 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7110 vtable entry to be used in the relocation's section offset. */
7111 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7112 rel->address = fixp->fx_offset;
252b5132 7113
c6682705 7114 rel->addend = 0;
3e73aa7c
JH		 7115 }
7116 /* Use the rela in 64bit mode. */
252b5132 7117 else
3e73aa7c 7118 {
062cd5e7
AS		 7119 if (!fixp->fx_pcrel)
7120 rel->addend = fixp->fx_offset;
7121 else
7122 switch (code)
7123 {
7124 case BFD_RELOC_X86_64_PLT32:
7125 case BFD_RELOC_X86_64_GOT32:
7126 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7127 case BFD_RELOC_X86_64_TLSGD:
7128 case BFD_RELOC_X86_64_TLSLD:
7129 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7130 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7131 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7132 rel->addend = fixp->fx_offset - fixp->fx_size;
7133 break;
7134 default:
7135 rel->addend = (section->vma
7136 - fixp->fx_size
7137 + fixp->fx_addnumber
7138 + md_pcrel_from (fixp));
7139 break;
7140 }
3e73aa7c
JH		 7141 }
7142
252b5132
RH		 7143 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7144 if (rel->howto == NULL)
7145 {
7146 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7147 _("cannot represent relocation type %s"),
252b5132
RH		 7148 bfd_get_reloc_code_name (code));
7149 /* Set howto to a garbage value so that we can keep going. */
7150 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7151 assert (rel->howto != NULL);
7152 }
7153
7154 return rel;
7155}
7156
64a0c779
DN		 7157\f
7158/* Parse operands using Intel syntax. This implements a recursive descent
7159 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7160 Programmer's Guide.
7161
7162 FIXME: We do not recognize the full operand grammar defined in the MASM
7163 documentation. In particular, all the structure/union and
7164 high-level macro operands are missing.
7165
7166 Uppercase words are terminals, lower case words are non-terminals.
7167 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7168 bars '|' denote choices. Most grammar productions are implemented in
7169 functions called 'intel_<production>'.
7170
7171 Initial production is 'expr'.
7172
9306ca4a 7173 addOp + | -
64a0c779
DN		 7174
7175 alpha [a-zA-Z]
7176
9306ca4a
JB		 7177 binOp & | AND | \| | OR | ^ | XOR
7178
64a0c779
DN		 7179 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7180
7181 constant digits [[ radixOverride ]]
7182
9306ca4a 7183 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7184
7185 digits decdigit
b77a7acd
AJ		 7186 | digits decdigit
7187 | digits hexdigit
64a0c779
DN		 7188
7189 decdigit [0-9]
7190
9306ca4a
JB		 7191 e04 e04 addOp e05
7192 | e05
7193
7194 e05 e05 binOp e06
b77a7acd 7195 | e06
64a0c779
DN		 7196
7197 e06 e06 mulOp e09
b77a7acd 7198 | e09
64a0c779
DN		 7199
7200 e09 OFFSET e10
a724f0f4
JB		 7201 | SHORT e10
7202 | + e10
7203 | - e10
9306ca4a
JB		 7204 | ~ e10
7205 | NOT e10
64a0c779
DN		 7206 | e09 PTR e10
7207 | e09 : e10
7208 | e10
7209
7210 e10 e10 [ expr ]
b77a7acd 7211 | e11
64a0c779
DN		 7212
7213 e11 ( expr )
b77a7acd 7214 | [ expr ]
64a0c779
DN		 7215 | constant
7216 | dataType
7217 | id
7218 | $
7219 | register
7220
a724f0f4 7221 => expr expr cmpOp e04
9306ca4a 7222 | e04
64a0c779
DN		 7223
7224 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7225 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7226
7227 hexdigit a | b | c | d | e | f
b77a7acd 7228 | A | B | C | D | E | F
64a0c779
DN		 7229
7230 id alpha
b77a7acd 7231 | id alpha
64a0c779
DN		 7232 | id decdigit
7233
9306ca4a 7234 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7235
7236 quote " | '
7237
7238 register specialRegister
b77a7acd 7239 | gpRegister
64a0c779
DN		 7240 | byteRegister
7241
7242 segmentRegister CS | DS | ES | FS | GS | SS
7243
9306ca4a 7244 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7245 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7246 | TR3 | TR4 | TR5 | TR6 | TR7
7247
64a0c779
DN		 7248 We simplify the grammar in obvious places (e.g., register parsing is
7249 done by calling parse_register) and eliminate immediate left recursion
7250 to implement a recursive-descent parser.
7251
a724f0f4
JB		 7252 expr e04 expr'
7253
7254 expr' cmpOp e04 expr'
7255 | Empty
9306ca4a
JB		 7256
7257 e04 e05 e04'
7258
7259 e04' addOp e05 e04'
7260 | Empty
64a0c779
DN		 7261
7262 e05 e06 e05'
7263
9306ca4a 7264 e05' binOp e06 e05'
b77a7acd 7265 | Empty
64a0c779
DN		 7266
7267 e06 e09 e06'
7268
7269 e06' mulOp e09 e06'
b77a7acd 7270 | Empty
64a0c779
DN		 7271
7272 e09 OFFSET e10 e09'
a724f0f4
JB		 7273 | SHORT e10'
7274 | + e10'
7275 | - e10'
7276 | ~ e10'
7277 | NOT e10'
b77a7acd 7278 | e10 e09'
64a0c779
DN		 7279
7280 e09' PTR e10 e09'
b77a7acd 7281 | : e10 e09'
64a0c779
DN		 7282 | Empty
7283
7284 e10 e11 e10'
7285
7286 e10' [ expr ] e10'
b77a7acd 7287 | Empty
64a0c779
DN		 7288
7289 e11 ( expr )
b77a7acd 7290 | [ expr ]
64a0c779
DN		 7291 | BYTE
7292 | WORD
7293 | DWORD
9306ca4a 7294 | FWORD
64a0c779 7295 | QWORD
9306ca4a
JB		 7296 | TBYTE
7297 | OWORD
7298 | XMMWORD
64a0c779
DN		 7299 | .
7300 | $
7301 | register
7302 | id
7303 | constant */
7304
7305/* Parsing structure for the intel syntax parser. Used to implement the
7306 semantic actions for the operand grammar. */
7307struct intel_parser_s
7308 {
7309 char *op_string; /* The string being parsed. */
7310 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7311 int op_modifier; /* Operand modifier. */
64a0c779 7312 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7313 int in_offset; /* >=1 if parsing operand of offset. */
7314 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7315 const reg_entry *reg; /* Last register reference found. */
7316 char *disp; /* Displacement string being built. */
a724f0f4 7317 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7318 };
7319
7320static struct intel_parser_s intel_parser;
7321
7322/* Token structure for parsing intel syntax. */
7323struct intel_token
7324 {
7325 int code; /* Token code. */
7326 const reg_entry *reg; /* Register entry for register tokens. */
7327 char *str; /* String representation. */
7328 };
7329
7330static struct intel_token cur_token, prev_token;
7331
50705ef4
AM		 7332/* Token codes for the intel parser. Since T_SHORT is already used
7333 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7334#define T_NIL -1
7335#define T_CONST 1
7336#define T_REG 2
7337#define T_BYTE 3
7338#define T_WORD 4
9306ca4a
JB		 7339#define T_DWORD 5
7340#define T_FWORD 6
7341#define T_QWORD 7
7342#define T_TBYTE 8
7343#define T_XMMWORD 9
50705ef4 7344#undef T_SHORT
9306ca4a
JB		 7345#define T_SHORT 10
7346#define T_OFFSET 11
7347#define T_PTR 12
7348#define T_ID 13
7349#define T_SHL 14
7350#define T_SHR 15
64a0c779
DN		 7351
7352/* Prototypes for intel parser functions. */
e3bb37b5
L		 7353static int intel_match_token (int);
7354static void intel_putback_token (void);
7355static void intel_get_token (void);
7356static int intel_expr (void);
7357static int intel_e04 (void);
7358static int intel_e05 (void);
7359static int intel_e06 (void);
7360static int intel_e09 (void);
7361static int intel_e10 (void);
7362static int intel_e11 (void);
64a0c779 7363
64a0c779 7364static int
e3bb37b5 7365i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7366{
7367 int ret;
7368 char *p;
7369
a724f0f4
JB		 7370 p = intel_parser.op_string = xstrdup (operand_string);
7371 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7372
7373 for (;;)
64a0c779 7374 {
a724f0f4
JB		 7375 /* Initialize token holders. */
7376 cur_token.code = prev_token.code = T_NIL;
7377 cur_token.reg = prev_token.reg = NULL;
7378 cur_token.str = prev_token.str = NULL;
7379
7380 /* Initialize parser structure. */
7381 intel_parser.got_a_float = got_a_float;
7382 intel_parser.op_modifier = 0;
7383 intel_parser.is_mem = 0;
7384 intel_parser.in_offset = 0;
7385 intel_parser.in_bracket = 0;
7386 intel_parser.reg = NULL;
7387 intel_parser.disp[0] = '\0';
7388 intel_parser.next_operand = NULL;
7389
7390 /* Read the first token and start the parser. */
7391 intel_get_token ();
7392 ret = intel_expr ();
7393
7394 if (!ret)
7395 break;
7396
9306ca4a
JB		 7397 if (cur_token.code != T_NIL)
7398 {
7399 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7400 current_templates->start->name, cur_token.str);
7401 ret = 0;
7402 }
64a0c779
DN		 7403 /* If we found a memory reference, hand it over to i386_displacement
7404 to fill in the rest of the operand fields. */
9306ca4a 7405 else if (intel_parser.is_mem)
64a0c779
DN		 7406 {
7407 if ((i.mem_operands == 1
40fb9820 7408 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7409 || i.mem_operands == 2)
7410 {
7411 as_bad (_("too many memory references for '%s'"),
7412 current_templates->start->name);
7413 ret = 0;
7414 }
7415 else
7416 {
7417 char *s = intel_parser.disp;
7418 i.mem_operands++;
7419
a724f0f4
JB		 7420 if (!quiet_warnings && intel_parser.is_mem < 0)
7421 /* See the comments in intel_bracket_expr. */
7422 as_warn (_("Treating `%s' as memory reference"), operand_string);
7423
64a0c779
DN		 7424 /* Add the displacement expression. */
7425 if (*s != '\0')
a4622f40
AM		 7426 ret = i386_displacement (s, s + strlen (s));
7427 if (ret)
a724f0f4
JB		 7428 {
7429 /* Swap base and index in 16-bit memory operands like
7430 [si+bx]. Since i386_index_check is also used in AT&T
7431 mode we have to do that here. */
7432 if (i.base_reg
7433 && i.index_reg
40fb9820
L		 7434 && i.base_reg->reg_type.bitfield.reg16
7435 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7436 && i.base_reg->reg_num >= 6
7437 && i.index_reg->reg_num < 6)
7438 {
7439 const reg_entry *base = i.index_reg;
7440
7441 i.index_reg = i.base_reg;
7442 i.base_reg = base;
7443 }
7444 ret = i386_index_check (operand_string);
7445 }
64a0c779
DN		 7446 }
7447 }
7448
7449 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7450 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7451 || intel_parser.reg == NULL)
7452 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7453
7454 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7455 ret = 0;
a724f0f4
JB		 7456 if (!ret || !intel_parser.next_operand)
7457 break;
7458 intel_parser.op_string = intel_parser.next_operand;
7459 this_operand = i.operands++;
64a0c779
DN		 7460 }
7461
7462 free (p);
7463 free (intel_parser.disp);
7464
7465 return ret;
7466}
7467
a724f0f4
JB		 7468#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7469
7470/* expr e04 expr'
7471
7472 expr' cmpOp e04 expr'
7473 | Empty */
64a0c779 7474static int
e3bb37b5 7475intel_expr (void)
64a0c779 7476{
a724f0f4
JB		 7477 /* XXX Implement the comparison operators. */
7478 return intel_e04 ();
9306ca4a
JB		 7479}
7480
a724f0f4 7481/* e04 e05 e04'
9306ca4a 7482
a724f0f4 7483 e04' addOp e05 e04'
9306ca4a
JB		 7484 | Empty */
7485static int
e3bb37b5 7486intel_e04 (void)
9306ca4a 7487{
a724f0f4 7488 int nregs = -1;
9306ca4a 7489
a724f0f4 7490 for (;;)
9306ca4a 7491 {
a724f0f4
JB		 7492 if (!intel_e05())
7493 return 0;
9306ca4a 7494
a724f0f4
JB		 7495 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7496 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7497
a724f0f4
JB		 7498 if (cur_token.code == '+')
7499 nregs = -1;
7500 else if (cur_token.code == '-')
7501 nregs = NUM_ADDRESS_REGS;
7502 else
7503 return 1;
64a0c779 7504
a724f0f4
JB		 7505 strcat (intel_parser.disp, cur_token.str);
7506 intel_match_token (cur_token.code);
7507 }
64a0c779
DN		 7508}
7509
64a0c779
DN		 7510/* e05 e06 e05'
7511
9306ca4a 7512 e05' binOp e06 e05'
64a0c779
DN		 7513 | Empty */
7514static int
e3bb37b5 7515intel_e05 (void)
64a0c779 7516{
a724f0f4 7517 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7518
a724f0f4 7519 for (;;)
64a0c779 7520 {
a724f0f4
JB		 7521 if (!intel_e06())
7522 return 0;
7523
4eed87de
AM		 7524 if (cur_token.code == '&'
7525 || cur_token.code == '|'
7526 || cur_token.code == '^')
a724f0f4
JB		 7527 {
7528 char str[2];
7529
7530 str[0] = cur_token.code;
7531 str[1] = 0;
7532 strcat (intel_parser.disp, str);
7533 }
7534 else
7535 break;
9306ca4a 7536
64a0c779
DN		 7537 intel_match_token (cur_token.code);
7538
a724f0f4
JB		 7539 if (nregs < 0)
7540 nregs = ~nregs;
64a0c779 7541 }
a724f0f4
JB		 7542 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7543 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7544 return 1;
4a1805b1 7545}
64a0c779
DN		 7546
7547/* e06 e09 e06'
7548
7549 e06' mulOp e09 e06'
b77a7acd 7550 | Empty */
64a0c779 7551static int
e3bb37b5 7552intel_e06 (void)
64a0c779 7553{
a724f0f4 7554 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7555
a724f0f4 7556 for (;;)
64a0c779 7557 {
a724f0f4
JB		 7558 if (!intel_e09())
7559 return 0;
9306ca4a 7560
4eed87de
AM		 7561 if (cur_token.code == '*'
7562 || cur_token.code == '/'
7563 || cur_token.code == '%')
a724f0f4
JB		 7564 {
7565 char str[2];
9306ca4a 7566
a724f0f4
JB		 7567 str[0] = cur_token.code;
7568 str[1] = 0;
7569 strcat (intel_parser.disp, str);
7570 }
7571 else if (cur_token.code == T_SHL)
7572 strcat (intel_parser.disp, "<<");
7573 else if (cur_token.code == T_SHR)
7574 strcat (intel_parser.disp, ">>");
7575 else
7576 break;
9306ca4a 7577
64e74474 7578 intel_match_token (cur_token.code);
64a0c779 7579
a724f0f4
JB		 7580 if (nregs < 0)
7581 nregs = ~nregs;
64a0c779 7582 }
a724f0f4
JB		 7583 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7584 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7585 return 1;
64a0c779
DN		 7586}
7587
a724f0f4
JB		 7588/* e09 OFFSET e09
7589 | SHORT e09
7590 | + e09
7591 | - e09
7592 | ~ e09
7593 | NOT e09
9306ca4a
JB		 7594 | e10 e09'
7595
64a0c779 7596 e09' PTR e10 e09'
b77a7acd 7597 | : e10 e09'
64a0c779
DN		 7598 | Empty */
7599static int
e3bb37b5 7600intel_e09 (void)
64a0c779 7601{
a724f0f4
JB		 7602 int nregs = ~NUM_ADDRESS_REGS;
7603 int in_offset = 0;
7604
7605 for (;;)
64a0c779 7606 {
a724f0f4
JB		 7607 /* Don't consume constants here. */
7608 if (cur_token.code == '+' || cur_token.code == '-')
7609 {
7610 /* Need to look one token ahead - if the next token
7611 is a constant, the current token is its sign. */
7612 int next_code;
7613
7614 intel_match_token (cur_token.code);
7615 next_code = cur_token.code;
7616 intel_putback_token ();
7617 if (next_code == T_CONST)
7618 break;
7619 }
7620
7621 /* e09 OFFSET e09 */
7622 if (cur_token.code == T_OFFSET)
7623 {
7624 if (!in_offset++)
7625 ++intel_parser.in_offset;
7626 }
7627
7628 /* e09 SHORT e09 */
7629 else if (cur_token.code == T_SHORT)
7630 intel_parser.op_modifier |= 1 << T_SHORT;
7631
7632 /* e09 + e09 */
7633 else if (cur_token.code == '+')
7634 strcat (intel_parser.disp, "+");
7635
7636 /* e09 - e09
7637 | ~ e09
7638 | NOT e09 */
7639 else if (cur_token.code == '-' || cur_token.code == '~')
7640 {
7641 char str[2];
64a0c779 7642
a724f0f4
JB		 7643 if (nregs < 0)
7644 nregs = ~nregs;
7645 str[0] = cur_token.code;
7646 str[1] = 0;
7647 strcat (intel_parser.disp, str);
7648 }
7649
7650 /* e09 e10 e09' */
7651 else
7652 break;
7653
7654 intel_match_token (cur_token.code);
64a0c779
DN		 7655 }
7656
a724f0f4 7657 for (;;)
9306ca4a 7658 {
a724f0f4
JB		 7659 if (!intel_e10 ())
7660 return 0;
9306ca4a 7661
a724f0f4
JB		 7662 /* e09' PTR e10 e09' */
7663 if (cur_token.code == T_PTR)
7664 {
7665 char suffix;
9306ca4a 7666
a724f0f4
JB		 7667 if (prev_token.code == T_BYTE)
7668 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7669
a724f0f4
JB		 7670 else if (prev_token.code == T_WORD)
7671 {
7672 if (current_templates->start->name[0] == 'l'
7673 && current_templates->start->name[2] == 's'
7674 && current_templates->start->name[3] == 0)
7675 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7676 else if (intel_parser.got_a_float == 2) /* "fi..." */
7677 suffix = SHORT_MNEM_SUFFIX;
7678 else
7679 suffix = WORD_MNEM_SUFFIX;
7680 }
64a0c779 7681
a724f0f4
JB		 7682 else if (prev_token.code == T_DWORD)
7683 {
7684 if (current_templates->start->name[0] == 'l'
7685 && current_templates->start->name[2] == 's'
7686 && current_templates->start->name[3] == 0)
7687 suffix = WORD_MNEM_SUFFIX;
7688 else if (flag_code == CODE_16BIT
40fb9820
L		 7689 && (current_templates->start->opcode_modifier.jump
7690 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 7691 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7692 else if (intel_parser.got_a_float == 1) /* "f..." */
7693 suffix = SHORT_MNEM_SUFFIX;
7694 else
7695 suffix = LONG_MNEM_SUFFIX;
7696 }
9306ca4a 7697
a724f0f4
JB		 7698 else if (prev_token.code == T_FWORD)
7699 {
7700 if (current_templates->start->name[0] == 'l'
7701 && current_templates->start->name[2] == 's'
7702 && current_templates->start->name[3] == 0)
7703 suffix = LONG_MNEM_SUFFIX;
7704 else if (!intel_parser.got_a_float)
7705 {
7706 if (flag_code == CODE_16BIT)
7707 add_prefix (DATA_PREFIX_OPCODE);
7708 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7709 }
7710 else
7711 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7712 }
64a0c779 7713
a724f0f4
JB		 7714 else if (prev_token.code == T_QWORD)
7715 {
7716 if (intel_parser.got_a_float == 1) /* "f..." */
7717 suffix = LONG_MNEM_SUFFIX;
7718 else
7719 suffix = QWORD_MNEM_SUFFIX;
7720 }
64a0c779 7721
a724f0f4
JB		 7722 else if (prev_token.code == T_TBYTE)
7723 {
7724 if (intel_parser.got_a_float == 1)
7725 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7726 else
7727 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7728 }
9306ca4a 7729
a724f0f4 7730 else if (prev_token.code == T_XMMWORD)
9306ca4a 7731 {
a724f0f4
JB		 7732 /* XXX ignored for now, but accepted since gcc uses it */
7733 suffix = 0;
9306ca4a 7734 }
64a0c779 7735
f16b83df 7736 else
a724f0f4
JB		 7737 {
7738 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7739 return 0;
7740 }
7741
435acd52
JB		 7742 /* Operands for jump/call using 'ptr' notation denote absolute
7743 addresses. */
40fb9820
L		 7744 if (current_templates->start->opcode_modifier.jump
7745 || current_templates->start->opcode_modifier.jumpdword)
7746 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 7747
a724f0f4
JB		 7748 if (current_templates->start->base_opcode == 0x8d /* lea */)
7749 ;
7750 else if (!i.suffix)
7751 i.suffix = suffix;
7752 else if (i.suffix != suffix)
7753 {
7754 as_bad (_("Conflicting operand modifiers"));
7755 return 0;
7756 }
64a0c779 7757
9306ca4a
JB		 7758 }
7759
a724f0f4
JB		 7760 /* e09' : e10 e09' */
7761 else if (cur_token.code == ':')
9306ca4a 7762 {
a724f0f4
JB		 7763 if (prev_token.code != T_REG)
7764 {
7765 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7766 segment/group identifier (which we don't have), using comma
7767 as the operand separator there is even less consistent, since
7768 there all branches only have a single operand. */
7769 if (this_operand != 0
7770 || intel_parser.in_offset
7771 || intel_parser.in_bracket
40fb9820
L		 7772 || (!current_templates->start->opcode_modifier.jump
7773 && !current_templates->start->opcode_modifier.jumpdword
7774 && !current_templates->start->opcode_modifier.jumpintersegment
7775 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 7776 return intel_match_token (T_NIL);
7777 /* Remember the start of the 2nd operand and terminate 1st
7778 operand here.
7779 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7780 another expression), but it gets at least the simplest case
7781 (a plain number or symbol on the left side) right. */
7782 intel_parser.next_operand = intel_parser.op_string;
7783 *--intel_parser.op_string = '\0';
7784 return intel_match_token (':');
7785 }
9306ca4a 7786 }
64a0c779 7787
a724f0f4 7788 /* e09' Empty */
64a0c779 7789 else
a724f0f4 7790 break;
64a0c779 7791
a724f0f4
JB		 7792 intel_match_token (cur_token.code);
7793
7794 }
7795
7796 if (in_offset)
7797 {
7798 --intel_parser.in_offset;
7799 if (nregs < 0)
7800 nregs = ~nregs;
7801 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7802 {
a724f0f4 7803 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7804 return 0;
7805 }
a724f0f4
JB		 7806 intel_parser.op_modifier |= 1 << T_OFFSET;
7807 }
9306ca4a 7808
a724f0f4
JB		 7809 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7810 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7811 return 1;
7812}
64a0c779 7813
a724f0f4 7814static int
e3bb37b5 7815intel_bracket_expr (void)
a724f0f4
JB		 7816{
7817 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7818 const char *start = intel_parser.op_string;
7819 int len;
7820
7821 if (i.op[this_operand].regs)
7822 return intel_match_token (T_NIL);
7823
7824 intel_match_token ('[');
7825
7826 /* Mark as a memory operand only if it's not already known to be an
7827 offset expression. If it's an offset expression, we need to keep
7828 the brace in. */
7829 if (!intel_parser.in_offset)
7830 {
7831 ++intel_parser.in_bracket;
435acd52
JB		 7832
7833 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 7834 if (current_templates->start->opcode_modifier.jump
7835 || current_templates->start->opcode_modifier.jumpdword)
7836 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 7837
a724f0f4
JB		 7838 /* Unfortunately gas always diverged from MASM in a respect that can't
7839 be easily fixed without risking to break code sequences likely to be
7840 encountered (the testsuite even check for this): MASM doesn't consider
7841 an expression inside brackets unconditionally as a memory reference.
7842 When that is e.g. a constant, an offset expression, or the sum of the
7843 two, this is still taken as a constant load. gas, however, always
7844 treated these as memory references. As a compromise, we'll try to make
7845 offset expressions inside brackets work the MASM way (since that's
7846 less likely to be found in real world code), but make constants alone
7847 continue to work the traditional gas way. In either case, issue a
7848 warning. */
7849 intel_parser.op_modifier &= ~was_offset;
64a0c779 7850 }
a724f0f4 7851 else
64e74474 7852 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7853
7854 /* Add a '+' to the displacement string if necessary. */
7855 if (*intel_parser.disp != '\0'
7856 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7857 strcat (intel_parser.disp, "+");
64a0c779 7858
a724f0f4
JB		 7859 if (intel_expr ()
7860 && (len = intel_parser.op_string - start - 1,
7861 intel_match_token (']')))
64a0c779 7862 {
a724f0f4
JB		 7863 /* Preserve brackets when the operand is an offset expression. */
7864 if (intel_parser.in_offset)
7865 strcat (intel_parser.disp, "]");
7866 else
7867 {
7868 --intel_parser.in_bracket;
7869 if (i.base_reg || i.index_reg)
7870 intel_parser.is_mem = 1;
7871 if (!intel_parser.is_mem)
7872 {
7873 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7874 /* Defer the warning until all of the operand was parsed. */
7875 intel_parser.is_mem = -1;
7876 else if (!quiet_warnings)
4eed87de
AM		 7877 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7878 len, start, len, start);
a724f0f4
JB		 7879 }
7880 }
7881 intel_parser.op_modifier |= was_offset;
64a0c779 7882
a724f0f4 7883 return 1;
64a0c779 7884 }
a724f0f4 7885 return 0;
64a0c779
DN		 7886}
7887
7888/* e10 e11 e10'
7889
7890 e10' [ expr ] e10'
b77a7acd 7891 | Empty */
64a0c779 7892static int
e3bb37b5 7893intel_e10 (void)
64a0c779 7894{
a724f0f4
JB		 7895 if (!intel_e11 ())
7896 return 0;
64a0c779 7897
a724f0f4 7898 while (cur_token.code == '[')
64a0c779 7899 {
a724f0f4 7900 if (!intel_bracket_expr ())
21d6c4af 7901 return 0;
64a0c779
DN		 7902 }
7903
a724f0f4 7904 return 1;
64a0c779
DN		 7905}
7906
64a0c779 7907/* e11 ( expr )
b77a7acd 7908 | [ expr ]
64a0c779
DN		 7909 | BYTE
7910 | WORD
7911 | DWORD
9306ca4a 7912 | FWORD
64a0c779 7913 | QWORD
9306ca4a
JB		 7914 | TBYTE
7915 | OWORD
7916 | XMMWORD
4a1805b1 7917 | $
64a0c779
DN		 7918 | .
7919 | register
7920 | id
7921 | constant */
7922static int
e3bb37b5 7923intel_e11 (void)
64a0c779 7924{
a724f0f4 7925 switch (cur_token.code)
64a0c779 7926 {
a724f0f4
JB		 7927 /* e11 ( expr ) */
7928 case '(':
64a0c779
DN		 7929 intel_match_token ('(');
7930 strcat (intel_parser.disp, "(");
7931
7932 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7933 {
7934 strcat (intel_parser.disp, ")");
7935 return 1;
7936 }
a724f0f4 7937 return 0;
4a1805b1 7938
a724f0f4
JB		 7939 /* e11 [ expr ] */
7940 case '[':
a724f0f4 7941 return intel_bracket_expr ();
64a0c779 7942
a724f0f4
JB		 7943 /* e11 $
7944 | . */
7945 case '.':
64a0c779
DN		 7946 strcat (intel_parser.disp, cur_token.str);
7947 intel_match_token (cur_token.code);
21d6c4af
DN		 7948
7949 /* Mark as a memory operand only if it's not already known to be an
7950 offset expression. */
a724f0f4 7951 if (!intel_parser.in_offset)
21d6c4af 7952 intel_parser.is_mem = 1;
64a0c779
DN		 7953
7954 return 1;
64a0c779 7955
a724f0f4
JB		 7956 /* e11 register */
7957 case T_REG:
7958 {
7959 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7960
a724f0f4 7961 intel_match_token (T_REG);
64a0c779 7962
a724f0f4
JB		 7963 /* Check for segment change. */
7964 if (cur_token.code == ':')
7965 {
40fb9820
L		 7966 if (!reg->reg_type.bitfield.sreg2
7967 && !reg->reg_type.bitfield.sreg3)
a724f0f4 7968 {
4eed87de
AM		 7969 as_bad (_("`%s' is not a valid segment register"),
7970 reg->reg_name);
a724f0f4
JB		 7971 return 0;
7972 }
7973 else if (i.seg[i.mem_operands])
7974 as_warn (_("Extra segment override ignored"));
7975 else
7976 {
7977 if (!intel_parser.in_offset)
7978 intel_parser.is_mem = 1;
7979 switch (reg->reg_num)
7980 {
7981 case 0:
7982 i.seg[i.mem_operands] = &es;
7983 break;
7984 case 1:
7985 i.seg[i.mem_operands] = &cs;
7986 break;
7987 case 2:
7988 i.seg[i.mem_operands] = &ss;
7989 break;
7990 case 3:
7991 i.seg[i.mem_operands] = &ds;
7992 break;
7993 case 4:
7994 i.seg[i.mem_operands] = &fs;
7995 break;
7996 case 5:
7997 i.seg[i.mem_operands] = &gs;
7998 break;
7999 }
8000 }
8001 }
64a0c779 8002
a724f0f4
JB		 8003 /* Not a segment register. Check for register scaling. */
8004 else if (cur_token.code == '*')
8005 {
8006 if (!intel_parser.in_bracket)
8007 {
8008 as_bad (_("Register scaling only allowed in memory operands"));
8009 return 0;
8010 }
64a0c779 8011
40fb9820 8012 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8013 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8014 else if (i.index_reg)
8015 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8016
a724f0f4
JB		 8017 /* What follows must be a valid scale. */
8018 intel_match_token ('*');
8019 i.index_reg = reg;
40fb9820 8020 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8021
a724f0f4
JB		 8022 /* Set the scale after setting the register (otherwise,
8023 i386_scale will complain) */
8024 if (cur_token.code == '+' || cur_token.code == '-')
8025 {
8026 char *str, sign = cur_token.code;
8027 intel_match_token (cur_token.code);
8028 if (cur_token.code != T_CONST)
8029 {
8030 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8031 cur_token.str);
8032 return 0;
8033 }
8034 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8035 strcpy (str + 1, cur_token.str);
8036 *str = sign;
8037 if (!i386_scale (str))
8038 return 0;
8039 free (str);
8040 }
8041 else if (!i386_scale (cur_token.str))
64a0c779 8042 return 0;
a724f0f4
JB		 8043 intel_match_token (cur_token.code);
8044 }
64a0c779 8045
a724f0f4
JB		 8046 /* No scaling. If this is a memory operand, the register is either a
8047 base register (first occurrence) or an index register (second
8048 occurrence). */
7b0441f6 8049 else if (intel_parser.in_bracket)
a724f0f4 8050 {
64a0c779 8051
a724f0f4
JB		 8052 if (!i.base_reg)
8053 i.base_reg = reg;
8054 else if (!i.index_reg)
8055 i.index_reg = reg;
8056 else
8057 {
8058 as_bad (_("Too many register references in memory operand"));
8059 return 0;
8060 }
64a0c779 8061
40fb9820 8062 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8063 }
4a1805b1 8064
4d1bb795
JB		 8065 /* It's neither base nor index. */
8066 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8067 {
40fb9820
L		 8068 i386_operand_type temp = reg->reg_type;
8069 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8070 i.types[this_operand] = operand_type_or (i.types[this_operand],
8071 temp);
a724f0f4
JB		 8072 i.op[this_operand].regs = reg;
8073 i.reg_operands++;
8074 }
8075 else
8076 {
8077 as_bad (_("Invalid use of register"));
8078 return 0;
8079 }
64a0c779 8080
a724f0f4
JB		 8081 /* Since registers are not part of the displacement string (except
8082 when we're parsing offset operands), we may need to remove any
8083 preceding '+' from the displacement string. */
8084 if (*intel_parser.disp != '\0'
8085 && !intel_parser.in_offset)
8086 {
8087 char *s = intel_parser.disp;
8088 s += strlen (s) - 1;
8089 if (*s == '+')
8090 *s = '\0';
8091 }
4a1805b1 8092
a724f0f4
JB		 8093 return 1;
8094 }
8095
8096 /* e11 BYTE
8097 | WORD
8098 | DWORD
8099 | FWORD
8100 | QWORD
8101 | TBYTE
8102 | OWORD
8103 | XMMWORD */
8104 case T_BYTE:
8105 case T_WORD:
8106 case T_DWORD:
8107 case T_FWORD:
8108 case T_QWORD:
8109 case T_TBYTE:
8110 case T_XMMWORD:
8111 intel_match_token (cur_token.code);
64a0c779 8112
a724f0f4
JB		 8113 if (cur_token.code == T_PTR)
8114 return 1;
8115
8116 /* It must have been an identifier. */
8117 intel_putback_token ();
8118 cur_token.code = T_ID;
8119 /* FALLTHRU */
8120
8121 /* e11 id
8122 | constant */
8123 case T_ID:
8124 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8125 {
8126 symbolS *symbolP;
8127
a724f0f4
JB		 8128 /* The identifier represents a memory reference only if it's not
8129 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8130 symbolP = symbol_find(cur_token.str);
8131 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8132 intel_parser.is_mem = 1;
8133 }
a724f0f4 8134 /* FALLTHRU */
64a0c779 8135
a724f0f4
JB		 8136 case T_CONST:
8137 case '-':
8138 case '+':
8139 {
8140 char *save_str, sign = 0;
64a0c779 8141
a724f0f4
JB		 8142 /* Allow constants that start with `+' or `-'. */
8143 if (cur_token.code == '-' || cur_token.code == '+')
8144 {
8145 sign = cur_token.code;
8146 intel_match_token (cur_token.code);
8147 if (cur_token.code != T_CONST)
8148 {
8149 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8150 cur_token.str);
8151 return 0;
8152 }
8153 }
64a0c779 8154
a724f0f4
JB		 8155 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8156 strcpy (save_str + !!sign, cur_token.str);
8157 if (sign)
8158 *save_str = sign;
64a0c779 8159
a724f0f4
JB		 8160 /* Get the next token to check for register scaling. */
8161 intel_match_token (cur_token.code);
64a0c779 8162
4eed87de
AM		 8163 /* Check if this constant is a scaling factor for an
8164 index register. */
a724f0f4
JB		 8165 if (cur_token.code == '*')
8166 {
8167 if (intel_match_token ('*') && cur_token.code == T_REG)
8168 {
8169 const reg_entry *reg = cur_token.reg;
8170
8171 if (!intel_parser.in_bracket)
8172 {
4eed87de
AM		 8173 as_bad (_("Register scaling only allowed "
8174 "in memory operands"));
a724f0f4
JB		 8175 return 0;
8176 }
8177
4eed87de
AM		 8178 /* Disallow things like [1*si].
8179 sp and esp are invalid as index. */
40fb9820 8180 if (reg->reg_type.bitfield.reg16)
4eed87de 8181 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8182 else if (i.index_reg)
4eed87de 8183 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8184
8185 /* The constant is followed by `* reg', so it must be
8186 a valid scale. */
8187 i.index_reg = reg;
40fb9820 8188 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8189
8190 /* Set the scale after setting the register (otherwise,
8191 i386_scale will complain) */
8192 if (!i386_scale (save_str))
64a0c779 8193 return 0;
a724f0f4
JB		 8194 intel_match_token (T_REG);
8195
8196 /* Since registers are not part of the displacement
8197 string, we may need to remove any preceding '+' from
8198 the displacement string. */
8199 if (*intel_parser.disp != '\0')
8200 {
8201 char *s = intel_parser.disp;
8202 s += strlen (s) - 1;
8203 if (*s == '+')
8204 *s = '\0';
8205 }
8206
8207 free (save_str);
8208
8209 return 1;
8210 }
64a0c779 8211
a724f0f4
JB		 8212 /* The constant was not used for register scaling. Since we have
8213 already consumed the token following `*' we now need to put it
8214 back in the stream. */
64a0c779 8215 intel_putback_token ();
a724f0f4 8216 }
64a0c779 8217
a724f0f4
JB		 8218 /* Add the constant to the displacement string. */
8219 strcat (intel_parser.disp, save_str);
8220 free (save_str);
64a0c779 8221
a724f0f4
JB		 8222 return 1;
8223 }
64a0c779
DN		 8224 }
8225
64a0c779
DN		 8226 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8227 return 0;
8228}
8229
64a0c779
DN		 8230/* Match the given token against cur_token. If they match, read the next
8231 token from the operand string. */
8232static int
e3bb37b5 8233intel_match_token (int code)
64a0c779
DN		 8234{
8235 if (cur_token.code == code)
8236 {
8237 intel_get_token ();
8238 return 1;
8239 }
8240 else
8241 {
0477af35 8242 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8243 return 0;
8244 }
8245}
8246
64a0c779
DN		 8247/* Read a new token from intel_parser.op_string and store it in cur_token. */
8248static void
e3bb37b5 8249intel_get_token (void)
64a0c779
DN		 8250{
8251 char *end_op;
8252 const reg_entry *reg;
8253 struct intel_token new_token;
8254
8255 new_token.code = T_NIL;
8256 new_token.reg = NULL;
8257 new_token.str = NULL;
8258
4a1805b1 8259 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8260 cur_token to prev_token. */
8261 if (prev_token.str)
8262 free (prev_token.str);
8263
8264 prev_token = cur_token;
8265
8266 /* Skip whitespace. */
8267 while (is_space_char (*intel_parser.op_string))
8268 intel_parser.op_string++;
8269
8270 /* Return an empty token if we find nothing else on the line. */
8271 if (*intel_parser.op_string == '\0')
8272 {
8273 cur_token = new_token;
8274 return;
8275 }
8276
8277 /* The new token cannot be larger than the remainder of the operand
8278 string. */
a724f0f4 8279 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8280 new_token.str[0] = '\0';
8281
8282 if (strchr ("0123456789", *intel_parser.op_string))
8283 {
8284 char *p = new_token.str;
8285 char *q = intel_parser.op_string;
8286 new_token.code = T_CONST;
8287
8288 /* Allow any kind of identifier char to encompass floating point and
8289 hexadecimal numbers. */
8290 while (is_identifier_char (*q))
8291 *p++ = *q++;
8292 *p = '\0';
8293
8294 /* Recognize special symbol names [0-9][bf]. */
8295 if (strlen (intel_parser.op_string) == 2
4a1805b1 8296 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8297 || intel_parser.op_string[1] == 'f'))
8298 new_token.code = T_ID;
8299 }
8300
4d1bb795 8301 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8302 {
4d1bb795
JB		 8303 size_t len = end_op - intel_parser.op_string;
8304
64a0c779
DN		 8305 new_token.code = T_REG;
8306 new_token.reg = reg;
8307
4d1bb795
JB		 8308 memcpy (new_token.str, intel_parser.op_string, len);
8309 new_token.str[len] = '\0';
64a0c779
DN		 8310 }
8311
8312 else if (is_identifier_char (*intel_parser.op_string))
8313 {
8314 char *p = new_token.str;
8315 char *q = intel_parser.op_string;
8316
8317 /* A '.' or '$' followed by an identifier char is an identifier.
8318 Otherwise, it's operator '.' followed by an expression. */
8319 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8320 {
9306ca4a
JB		 8321 new_token.code = '.';
8322 new_token.str[0] = '.';
64a0c779
DN		 8323 new_token.str[1] = '\0';
8324 }
8325 else
8326 {
8327 while (is_identifier_char (*q) || *q == '@')
8328 *p++ = *q++;
8329 *p = '\0';
8330
9306ca4a
JB		 8331 if (strcasecmp (new_token.str, "NOT") == 0)
8332 new_token.code = '~';
8333
8334 else if (strcasecmp (new_token.str, "MOD") == 0)
8335 new_token.code = '%';
8336
8337 else if (strcasecmp (new_token.str, "AND") == 0)
8338 new_token.code = '&';
8339
8340 else if (strcasecmp (new_token.str, "OR") == 0)
8341 new_token.code = '|';
8342
8343 else if (strcasecmp (new_token.str, "XOR") == 0)
8344 new_token.code = '^';
8345
8346 else if (strcasecmp (new_token.str, "SHL") == 0)
8347 new_token.code = T_SHL;
8348
8349 else if (strcasecmp (new_token.str, "SHR") == 0)
8350 new_token.code = T_SHR;
8351
8352 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8353 new_token.code = T_BYTE;
8354
8355 else if (strcasecmp (new_token.str, "WORD") == 0)
8356 new_token.code = T_WORD;
8357
8358 else if (strcasecmp (new_token.str, "DWORD") == 0)
8359 new_token.code = T_DWORD;
8360
9306ca4a
JB		 8361 else if (strcasecmp (new_token.str, "FWORD") == 0)
8362 new_token.code = T_FWORD;
8363
64a0c779
DN		 8364 else if (strcasecmp (new_token.str, "QWORD") == 0)
8365 new_token.code = T_QWORD;
8366
9306ca4a
JB		 8367 else if (strcasecmp (new_token.str, "TBYTE") == 0
8368 /* XXX remove (gcc still uses it) */
8369 || strcasecmp (new_token.str, "XWORD") == 0)
8370 new_token.code = T_TBYTE;
8371
8372 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8373 || strcasecmp (new_token.str, "OWORD") == 0)
8374 new_token.code = T_XMMWORD;
64a0c779
DN		 8375
8376 else if (strcasecmp (new_token.str, "PTR") == 0)
8377 new_token.code = T_PTR;
8378
8379 else if (strcasecmp (new_token.str, "SHORT") == 0)
8380 new_token.code = T_SHORT;
8381
8382 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8383 {
8384 new_token.code = T_OFFSET;
8385
8386 /* ??? This is not mentioned in the MASM grammar but gcc
8387 makes use of it with -mintel-syntax. OFFSET may be
8388 followed by FLAT: */
8389 if (strncasecmp (q, " FLAT:", 6) == 0)
8390 strcat (new_token.str, " FLAT:");
8391 }
8392
8393 /* ??? This is not mentioned in the MASM grammar. */
8394 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8395 {
8396 new_token.code = T_OFFSET;
8397 if (*q == ':')
8398 strcat (new_token.str, ":");
8399 else
8400 as_bad (_("`:' expected"));
8401 }
64a0c779
DN		 8402
8403 else
8404 new_token.code = T_ID;
8405 }
8406 }
8407
9306ca4a
JB		 8408 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8409 {
8410 new_token.code = *intel_parser.op_string;
8411 new_token.str[0] = *intel_parser.op_string;
8412 new_token.str[1] = '\0';
8413 }
8414
8415 else if (strchr ("<>", *intel_parser.op_string)
8416 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8417 {
8418 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8419 new_token.str[0] = *intel_parser.op_string;
8420 new_token.str[1] = *intel_parser.op_string;
8421 new_token.str[2] = '\0';
8422 }
8423
64a0c779 8424 else
0477af35 8425 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8426
8427 intel_parser.op_string += strlen (new_token.str);
8428 cur_token = new_token;
8429}
8430
64a0c779
DN		 8431/* Put cur_token back into the token stream and make cur_token point to
8432 prev_token. */
8433static void
e3bb37b5 8434intel_putback_token (void)
64a0c779 8435{
a724f0f4
JB		 8436 if (cur_token.code != T_NIL)
8437 {
8438 intel_parser.op_string -= strlen (cur_token.str);
8439 free (cur_token.str);
8440 }
64a0c779 8441 cur_token = prev_token;
4a1805b1 8442
64a0c779
DN		 8443 /* Forget prev_token. */
8444 prev_token.code = T_NIL;
8445 prev_token.reg = NULL;
8446 prev_token.str = NULL;
8447}
54cfded0 8448
a4447b93 8449int
1df69f4f 8450tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8451{
8452 unsigned int regnum;
8453 unsigned int regnames_count;
089dfecd 8454 static const char *const regnames_32[] =
54cfded0 8455 {
a4447b93
RH		 8456 "eax", "ecx", "edx", "ebx",
8457 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8458 "eip", "eflags", NULL,
8459 "st0", "st1", "st2", "st3",
8460 "st4", "st5", "st6", "st7",
8461 NULL, NULL,
8462 "xmm0", "xmm1", "xmm2", "xmm3",
8463 "xmm4", "xmm5", "xmm6", "xmm7",
8464 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8465 "mm4", "mm5", "mm6", "mm7",
8466 "fcw", "fsw", "mxcsr",
8467 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8468 "tr", "ldtr"
54cfded0 8469 };
089dfecd 8470 static const char *const regnames_64[] =
54cfded0 8471 {
089dfecd
JB		 8472 "rax", "rdx", "rcx", "rbx",
8473 "rsi", "rdi", "rbp", "rsp",
8474 "r8", "r9", "r10", "r11",
54cfded0 8475 "r12", "r13", "r14", "r15",
089dfecd
JB		 8476 "rip",
8477 "xmm0", "xmm1", "xmm2", "xmm3",
8478 "xmm4", "xmm5", "xmm6", "xmm7",
8479 "xmm8", "xmm9", "xmm10", "xmm11",
8480 "xmm12", "xmm13", "xmm14", "xmm15",
8481 "st0", "st1", "st2", "st3",
8482 "st4", "st5", "st6", "st7",
8483 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8484 "mm4", "mm5", "mm6", "mm7",
8485 "rflags",
8486 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8487 "fs.base", "gs.base", NULL, NULL,
8488 "tr", "ldtr",
8489 "mxcsr", "fcw", "fsw"
54cfded0 8490 };
089dfecd 8491 const char *const *regnames;
54cfded0
AM		 8492
8493 if (flag_code == CODE_64BIT)
8494 {
8495 regnames = regnames_64;
0cea6190 8496 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8497 }
8498 else
8499 {
8500 regnames = regnames_32;
0cea6190 8501 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8502 }
8503
8504 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8505 if (regnames[regnum] != NULL
8506 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8507 return regnum;
8508
54cfded0
AM		 8509 return -1;
8510}
8511
8512void
8513tc_x86_frame_initial_instructions (void)
8514{
a4447b93
RH		 8515 static unsigned int sp_regno;
8516
8517 if (!sp_regno)
8518 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8519 ? "rsp" : "esp");
8520
8521 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8522 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8523}
d2b2c203
DJ		 8524
8525int
8526i386_elf_section_type (const char *str, size_t len)
8527{
8528 if (flag_code == CODE_64BIT
8529 && len == sizeof ("unwind") - 1
8530 && strncmp (str, "unwind", 6) == 0)
8531 return SHT_X86_64_UNWIND;
8532
8533 return -1;
8534}
bb41ade5
AM		 8535
8536#ifdef TE_PE
8537void
8538tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8539{
8540 expressionS expr;
8541
8542 expr.X_op = O_secrel;
8543 expr.X_add_symbol = symbol;
8544 expr.X_add_number = 0;
8545 emit_expr (&expr, size);
8546}
8547#endif
3b22753a
L		 8548
8549#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8550/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8551
8552int
8553x86_64_section_letter (int letter, char **ptr_msg)
8554{
8555 if (flag_code == CODE_64BIT)
8556 {
8557 if (letter == 'l')
8558 return SHF_X86_64_LARGE;
8559
8560 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8561 }
3b22753a 8562 else
64e74474 8563 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8564 return -1;
8565}
8566
8567int
8568x86_64_section_word (char *str, size_t len)
8569{
8620418b 8570 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8571 return SHF_X86_64_LARGE;
8572
8573 return -1;
8574}
8575
8576static void
8577handle_large_common (int small ATTRIBUTE_UNUSED)
8578{
8579 if (flag_code != CODE_64BIT)
8580 {
8581 s_comm_internal (0, elf_common_parse);
8582 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8583 }
8584 else
8585 {
8586 static segT lbss_section;
8587 asection *saved_com_section_ptr = elf_com_section_ptr;
8588 asection *saved_bss_section = bss_section;
8589
8590 if (lbss_section == NULL)
8591 {
8592 flagword applicable;
8593 segT seg = now_seg;
8594 subsegT subseg = now_subseg;
8595
8596 /* The .lbss section is for local .largecomm symbols. */
8597 lbss_section = subseg_new (".lbss", 0);
8598 applicable = bfd_applicable_section_flags (stdoutput);
8599 bfd_set_section_flags (stdoutput, lbss_section,
8600 applicable & SEC_ALLOC);
8601 seg_info (lbss_section)->bss = 1;
8602
8603 subseg_set (seg, subseg);
8604 }
8605
8606 elf_com_section_ptr = &_bfd_elf_large_com_section;
8607 bss_section = lbss_section;
8608
8609 s_comm_internal (0, elf_common_parse);
8610
8611 elf_com_section_ptr = saved_com_section_ptr;
8612 bss_section = saved_bss_section;
8613 }
8614}
8615#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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