Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0bfee649 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
6305a203 L |
58 | /* Prefixes will be emitted in the order defined below. |
59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
60 | instruction, and so must come before any prefixes. | |
61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
62 | LOCKREP_PREFIX. */ | |
63 | #define WAIT_PREFIX 0 | |
64 | #define SEG_PREFIX 1 | |
65 | #define ADDR_PREFIX 2 | |
66 | #define DATA_PREFIX 3 | |
67 | #define LOCKREP_PREFIX 4 | |
68 | #define REX_PREFIX 5 /* must come last. */ | |
69 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ | |
70 | ||
71 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
72 | #define REGISTER_PREFIX '%' | |
73 | #define IMMEDIATE_PREFIX '$' | |
74 | #define ABSOLUTE_PREFIX '*' | |
75 | ||
76 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
77 | memory operand size in Intel syntax. */ | |
78 | #define WORD_MNEM_SUFFIX 'w' | |
79 | #define BYTE_MNEM_SUFFIX 'b' | |
80 | #define SHORT_MNEM_SUFFIX 's' | |
81 | #define LONG_MNEM_SUFFIX 'l' | |
82 | #define QWORD_MNEM_SUFFIX 'q' | |
83 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 84 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
85 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
86 | in instructions. */ | |
87 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
88 | ||
89 | #define END_OF_INSN '\0' | |
90 | ||
91 | /* | |
92 | 'templates' is for grouping together 'template' structures for opcodes | |
93 | of the same name. This is only used for storing the insns in the grand | |
94 | ole hash table of insns. | |
95 | The templates themselves start at START and range up to (but not including) | |
96 | END. | |
97 | */ | |
98 | typedef struct | |
99 | { | |
100 | const template *start; | |
101 | const template *end; | |
102 | } | |
103 | templates; | |
104 | ||
105 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
106 | typedef struct | |
107 | { | |
108 | unsigned int regmem; /* codes register or memory operand */ | |
109 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
110 | unsigned int mode; /* how to interpret regmem & reg */ | |
111 | } | |
112 | modrm_byte; | |
113 | ||
114 | /* x86-64 extension prefix. */ | |
115 | typedef int rex_byte; | |
116 | ||
117 | /* The SSE5 instructions have a two bit instruction modifier (OC) that | |
118 | is stored in two separate bytes in the instruction. Pick apart OC | |
119 | into the 2 separate bits for instruction. */ | |
120 | #define DREX_OC0(x) (((x) & 1) != 0) | |
121 | #define DREX_OC1(x) (((x) & 2) != 0) | |
122 | ||
123 | #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ | |
124 | #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ | |
125 | ||
126 | /* OC mappings */ | |
127 | #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ | |
128 | #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ | |
129 | #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ | |
130 | #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ | |
131 | ||
132 | #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ | |
133 | #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ | |
134 | ||
135 | /* Information needed to create the DREX byte in SSE5 instructions. */ | |
136 | typedef struct | |
137 | { | |
138 | unsigned int reg; /* register */ | |
139 | unsigned int rex; /* REX flags */ | |
140 | unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ | |
141 | unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ | |
142 | } drex_byte; | |
143 | ||
144 | /* 386 opcode byte to code indirect addressing. */ | |
145 | typedef struct | |
146 | { | |
147 | unsigned base; | |
148 | unsigned index; | |
149 | unsigned scale; | |
150 | } | |
151 | sib_byte; | |
152 | ||
6305a203 L |
153 | /* x86 arch names, types and features */ |
154 | typedef struct | |
155 | { | |
156 | const char *name; /* arch name */ | |
157 | enum processor_type type; /* arch type */ | |
158 | i386_cpu_flags flags; /* cpu feature flags */ | |
159 | } | |
160 | arch_entry; | |
161 | ||
e3bb37b5 L |
162 | static void set_code_flag (int); |
163 | static void set_16bit_gcc_code_flag (int); | |
164 | static void set_intel_syntax (int); | |
1efbbeb4 | 165 | static void set_intel_mnemonic (int); |
db51cc60 | 166 | static void set_allow_index_reg (int); |
cb19c032 | 167 | static void set_sse_check (int); |
e3bb37b5 | 168 | static void set_cpu_arch (int); |
6482c264 | 169 | #ifdef TE_PE |
e3bb37b5 | 170 | static void pe_directive_secrel (int); |
6482c264 | 171 | #endif |
e3bb37b5 L |
172 | static void signed_cons (int); |
173 | static char *output_invalid (int c); | |
ee86248c JB |
174 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
175 | const char *); | |
176 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
177 | const char *); | |
a7619375 | 178 | static int i386_att_operand (char *); |
e3bb37b5 | 179 | static int i386_intel_operand (char *, int); |
ee86248c JB |
180 | static int i386_intel_simplify (expressionS *); |
181 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
182 | static const reg_entry *parse_register (char *, char **); |
183 | static char *parse_insn (char *, char *); | |
184 | static char *parse_operands (char *, const char *); | |
185 | static void swap_operands (void); | |
4d456e3d | 186 | static void swap_2_operands (int, int); |
e3bb37b5 L |
187 | static void optimize_imm (void); |
188 | static void optimize_disp (void); | |
fa99fab2 | 189 | static const template *match_template (void); |
e3bb37b5 L |
190 | static int check_string (void); |
191 | static int process_suffix (void); | |
192 | static int check_byte_reg (void); | |
193 | static int check_long_reg (void); | |
194 | static int check_qword_reg (void); | |
195 | static int check_word_reg (void); | |
196 | static int finalize_imm (void); | |
85f10a01 | 197 | static void process_drex (void); |
e3bb37b5 L |
198 | static int process_operands (void); |
199 | static const seg_entry *build_modrm_byte (void); | |
200 | static void output_insn (void); | |
201 | static void output_imm (fragS *, offsetT); | |
202 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 203 | #ifndef I386COFF |
e3bb37b5 | 204 | static void s_bss (int); |
252b5132 | 205 | #endif |
17d4e2a2 L |
206 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
207 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
208 | #endif | |
252b5132 | 209 | |
a847613f | 210 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 211 | |
c0f3af97 L |
212 | /* VEX prefix. */ |
213 | typedef struct | |
214 | { | |
215 | /* VEX prefix is either 2 byte or 3 byte. */ | |
216 | unsigned char bytes[3]; | |
217 | unsigned int length; | |
218 | /* Destination or source register specifier. */ | |
219 | const reg_entry *register_specifier; | |
220 | } vex_prefix; | |
221 | ||
252b5132 | 222 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 223 | i386_insn. */ |
252b5132 | 224 | |
520dc8e8 AM |
225 | union i386_op |
226 | { | |
227 | expressionS *disps; | |
228 | expressionS *imms; | |
229 | const reg_entry *regs; | |
230 | }; | |
231 | ||
252b5132 RH |
232 | struct _i386_insn |
233 | { | |
47926f60 | 234 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
235 | template tm; |
236 | ||
7d5e4556 L |
237 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
238 | or qword, if given. */ | |
252b5132 RH |
239 | char suffix; |
240 | ||
47926f60 | 241 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
242 | unsigned int operands; |
243 | ||
244 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
245 | of given register, displacement, memory operands and immediate | |
47926f60 | 246 | operands. */ |
252b5132 RH |
247 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
248 | ||
249 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 250 | use OP[i] for the corresponding operand. */ |
40fb9820 | 251 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 252 | |
520dc8e8 AM |
253 | /* Displacement expression, immediate expression, or register for each |
254 | operand. */ | |
255 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 256 | |
3e73aa7c JH |
257 | /* Flags for operands. */ |
258 | unsigned int flags[MAX_OPERANDS]; | |
259 | #define Operand_PCrel 1 | |
260 | ||
252b5132 | 261 | /* Relocation type for operand */ |
f86103b7 | 262 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 263 | |
252b5132 RH |
264 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
265 | the base index byte below. */ | |
266 | const reg_entry *base_reg; | |
267 | const reg_entry *index_reg; | |
268 | unsigned int log2_scale_factor; | |
269 | ||
270 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 271 | explicit segment overrides are given. */ |
ce8a8b2f | 272 | const seg_entry *seg[2]; |
252b5132 RH |
273 | |
274 | /* PREFIX holds all the given prefix opcodes (usually null). | |
275 | PREFIXES is the number of prefix opcodes. */ | |
276 | unsigned int prefixes; | |
277 | unsigned char prefix[MAX_PREFIXES]; | |
278 | ||
279 | /* RM and SIB are the modrm byte and the sib byte where the | |
85f10a01 MM |
280 | addressing modes of this insn are encoded. DREX is the byte |
281 | added by the SSE5 instructions. */ | |
252b5132 RH |
282 | |
283 | modrm_byte rm; | |
3e73aa7c | 284 | rex_byte rex; |
252b5132 | 285 | sib_byte sib; |
85f10a01 | 286 | drex_byte drex; |
c0f3af97 | 287 | vex_prefix vex; |
b6169b20 L |
288 | |
289 | /* Swap operand in encoding. */ | |
290 | unsigned int swap_operand : 1; | |
252b5132 RH |
291 | }; |
292 | ||
293 | typedef struct _i386_insn i386_insn; | |
294 | ||
295 | /* List of chars besides those in app.c:symbol_chars that can start an | |
296 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 297 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 298 | #ifdef LEX_AT |
32137342 NC |
299 | "@" |
300 | #endif | |
301 | #ifdef LEX_QM | |
302 | "?" | |
252b5132 | 303 | #endif |
32137342 | 304 | ; |
252b5132 | 305 | |
29b0f896 AM |
306 | #if (defined (TE_I386AIX) \ |
307 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 308 | && !defined (TE_GNU) \ |
29b0f896 | 309 | && !defined (TE_LINUX) \ |
32137342 | 310 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
311 | && !defined (TE_FreeBSD) \ |
312 | && !defined (TE_NetBSD))) | |
252b5132 | 313 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
314 | pre-processor is disabled, these aren't very useful. The option |
315 | --divide will remove '/' from this list. */ | |
316 | const char *i386_comment_chars = "#/"; | |
317 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 318 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 319 | |
b3b91714 AM |
320 | #else |
321 | const char *i386_comment_chars = "#"; | |
322 | #define PREFIX_SEPARATOR '/' | |
323 | #endif | |
324 | ||
252b5132 RH |
325 | /* This array holds the chars that only start a comment at the beginning of |
326 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
327 | .line and .file directives will appear in the pre-processed output. |
328 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 329 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
330 | #NO_APP at the beginning of its output. |
331 | Also note that comments started like this one will always work if | |
252b5132 | 332 | '/' isn't otherwise defined. */ |
b3b91714 | 333 | const char line_comment_chars[] = "#/"; |
252b5132 | 334 | |
63a0b638 | 335 | const char line_separator_chars[] = ";"; |
252b5132 | 336 | |
ce8a8b2f AM |
337 | /* Chars that can be used to separate mant from exp in floating point |
338 | nums. */ | |
252b5132 RH |
339 | const char EXP_CHARS[] = "eE"; |
340 | ||
ce8a8b2f AM |
341 | /* Chars that mean this number is a floating point constant |
342 | As in 0f12.456 | |
343 | or 0d1.2345e12. */ | |
252b5132 RH |
344 | const char FLT_CHARS[] = "fFdDxX"; |
345 | ||
ce8a8b2f | 346 | /* Tables for lexical analysis. */ |
252b5132 RH |
347 | static char mnemonic_chars[256]; |
348 | static char register_chars[256]; | |
349 | static char operand_chars[256]; | |
350 | static char identifier_chars[256]; | |
351 | static char digit_chars[256]; | |
352 | ||
ce8a8b2f | 353 | /* Lexical macros. */ |
252b5132 RH |
354 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
355 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
356 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
357 | #define is_space_char(x) ((x) == ' ') | |
358 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
359 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
360 | ||
0234cb7c | 361 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
362 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
363 | ||
364 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
365 | effect this we maintain a stack of saved characters that we've smashed | |
366 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 367 | assembler instruction). */ |
252b5132 | 368 | static char save_stack[32]; |
ce8a8b2f | 369 | static char *save_stack_p; |
252b5132 RH |
370 | #define END_STRING_AND_SAVE(s) \ |
371 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
372 | #define RESTORE_END_STRING(s) \ | |
373 | do { *(s) = *--save_stack_p; } while (0) | |
374 | ||
47926f60 | 375 | /* The instruction we're assembling. */ |
252b5132 RH |
376 | static i386_insn i; |
377 | ||
378 | /* Possible templates for current insn. */ | |
379 | static const templates *current_templates; | |
380 | ||
31b2323c L |
381 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
382 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
383 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 384 | |
47926f60 | 385 | /* Current operand we are working on. */ |
ee86248c | 386 | static int this_operand = -1; |
252b5132 | 387 | |
3e73aa7c JH |
388 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
389 | these. */ | |
390 | ||
391 | enum flag_code { | |
392 | CODE_32BIT, | |
393 | CODE_16BIT, | |
394 | CODE_64BIT }; | |
395 | ||
396 | static enum flag_code flag_code; | |
4fa24527 | 397 | static unsigned int object_64bit; |
3e73aa7c JH |
398 | static int use_rela_relocations = 0; |
399 | ||
400 | /* The names used to print error messages. */ | |
b77a7acd | 401 | static const char *flag_code_names[] = |
3e73aa7c JH |
402 | { |
403 | "32", | |
404 | "16", | |
405 | "64" | |
406 | }; | |
252b5132 | 407 | |
47926f60 KH |
408 | /* 1 for intel syntax, |
409 | 0 if att syntax. */ | |
410 | static int intel_syntax = 0; | |
252b5132 | 411 | |
1efbbeb4 L |
412 | /* 1 for intel mnemonic, |
413 | 0 if att mnemonic. */ | |
414 | static int intel_mnemonic = !SYSV386_COMPAT; | |
415 | ||
5209009a | 416 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
417 | static int old_gcc = OLDGCC_COMPAT; |
418 | ||
a60de03c JB |
419 | /* 1 if pseudo registers are permitted. */ |
420 | static int allow_pseudo_reg = 0; | |
421 | ||
47926f60 KH |
422 | /* 1 if register prefix % not required. */ |
423 | static int allow_naked_reg = 0; | |
252b5132 | 424 | |
ba104c83 | 425 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
426 | static int allow_index_reg = 0; |
427 | ||
daf50ae7 L |
428 | static enum |
429 | { | |
430 | sse_check_none = 0, | |
431 | sse_check_warning, | |
432 | sse_check_error | |
433 | } | |
434 | sse_check; | |
435 | ||
2ca3ace5 L |
436 | /* Register prefix used for error message. */ |
437 | static const char *register_prefix = "%"; | |
438 | ||
47926f60 KH |
439 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
440 | leave, push, and pop instructions so that gcc has the same stack | |
441 | frame as in 32 bit mode. */ | |
442 | static char stackop_size = '\0'; | |
eecb386c | 443 | |
12b55ccc L |
444 | /* Non-zero to optimize code alignment. */ |
445 | int optimize_align_code = 1; | |
446 | ||
47926f60 KH |
447 | /* Non-zero to quieten some warnings. */ |
448 | static int quiet_warnings = 0; | |
a38cf1db | 449 | |
47926f60 KH |
450 | /* CPU name. */ |
451 | static const char *cpu_arch_name = NULL; | |
6305a203 | 452 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 453 | |
47926f60 | 454 | /* CPU feature flags. */ |
40fb9820 L |
455 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
456 | ||
ccc9c027 L |
457 | /* If we have selected a cpu we are generating instructions for. */ |
458 | static int cpu_arch_tune_set = 0; | |
459 | ||
9103f4f4 | 460 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 461 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
462 | |
463 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 464 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 465 | |
ccc9c027 | 466 | /* CPU instruction set architecture used. */ |
fbf3f584 | 467 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 468 | |
9103f4f4 | 469 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 470 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 471 | |
fddf5b5b AM |
472 | /* If set, conditional jumps are not automatically promoted to handle |
473 | larger than a byte offset. */ | |
474 | static unsigned int no_cond_jump_promotion = 0; | |
475 | ||
c0f3af97 L |
476 | /* Encode SSE instructions with VEX prefix. */ |
477 | static unsigned int sse2avx; | |
478 | ||
29b0f896 | 479 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 480 | static symbolS *GOT_symbol; |
29b0f896 | 481 | |
a4447b93 RH |
482 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
483 | unsigned int x86_dwarf2_return_column; | |
484 | ||
485 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
486 | int x86_cie_data_alignment; | |
487 | ||
252b5132 | 488 | /* Interface to relax_segment. |
fddf5b5b AM |
489 | There are 3 major relax states for 386 jump insns because the |
490 | different types of jumps add different sizes to frags when we're | |
491 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 492 | |
47926f60 | 493 | /* Types. */ |
93c2a809 AM |
494 | #define UNCOND_JUMP 0 |
495 | #define COND_JUMP 1 | |
496 | #define COND_JUMP86 2 | |
fddf5b5b | 497 | |
47926f60 | 498 | /* Sizes. */ |
252b5132 RH |
499 | #define CODE16 1 |
500 | #define SMALL 0 | |
29b0f896 | 501 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 502 | #define BIG 2 |
29b0f896 | 503 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
504 | |
505 | #ifndef INLINE | |
506 | #ifdef __GNUC__ | |
507 | #define INLINE __inline__ | |
508 | #else | |
509 | #define INLINE | |
510 | #endif | |
511 | #endif | |
512 | ||
fddf5b5b AM |
513 | #define ENCODE_RELAX_STATE(type, size) \ |
514 | ((relax_substateT) (((type) << 2) | (size))) | |
515 | #define TYPE_FROM_RELAX_STATE(s) \ | |
516 | ((s) >> 2) | |
517 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
518 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
519 | |
520 | /* This table is used by relax_frag to promote short jumps to long | |
521 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
522 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
523 | don't allow a short jump in a 32 bit code segment to be promoted to | |
524 | a 16 bit offset jump because it's slower (requires data size | |
525 | prefix), and doesn't work, unless the destination is in the bottom | |
526 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
527 | ||
528 | const relax_typeS md_relax_table[] = | |
529 | { | |
24eab124 AM |
530 | /* The fields are: |
531 | 1) most positive reach of this state, | |
532 | 2) most negative reach of this state, | |
93c2a809 | 533 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 534 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 535 | |
fddf5b5b | 536 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
537 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
538 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
539 | /* dword jmp adds 4 bytes to frag: | |
540 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 541 | {0, 0, 4, 0}, |
93c2a809 AM |
542 | /* word jmp adds 2 byte2 to frag: |
543 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
544 | {0, 0, 2, 0}, |
545 | ||
93c2a809 AM |
546 | /* COND_JUMP states. */ |
547 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
548 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
549 | /* dword conditionals adds 5 bytes to frag: | |
550 | 1 extra opcode byte, 4 displacement bytes. */ | |
551 | {0, 0, 5, 0}, | |
fddf5b5b | 552 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
553 | 1 extra opcode byte, 2 displacement bytes. */ |
554 | {0, 0, 3, 0}, | |
555 | ||
556 | /* COND_JUMP86 states. */ | |
557 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
558 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
559 | /* dword conditionals adds 5 bytes to frag: | |
560 | 1 extra opcode byte, 4 displacement bytes. */ | |
561 | {0, 0, 5, 0}, | |
562 | /* word conditionals add 4 bytes to frag: | |
563 | 1 displacement byte and a 3 byte long branch insn. */ | |
564 | {0, 0, 4, 0} | |
252b5132 RH |
565 | }; |
566 | ||
9103f4f4 L |
567 | static const arch_entry cpu_arch[] = |
568 | { | |
6305a203 L |
569 | { "generic32", PROCESSOR_GENERIC32, |
570 | CPU_GENERIC32_FLAGS }, | |
571 | { "generic64", PROCESSOR_GENERIC64, | |
572 | CPU_GENERIC64_FLAGS }, | |
573 | { "i8086", PROCESSOR_UNKNOWN, | |
574 | CPU_NONE_FLAGS }, | |
575 | { "i186", PROCESSOR_UNKNOWN, | |
576 | CPU_I186_FLAGS }, | |
577 | { "i286", PROCESSOR_UNKNOWN, | |
578 | CPU_I286_FLAGS }, | |
579 | { "i386", PROCESSOR_I386, | |
580 | CPU_I386_FLAGS }, | |
581 | { "i486", PROCESSOR_I486, | |
582 | CPU_I486_FLAGS }, | |
583 | { "i586", PROCESSOR_PENTIUM, | |
584 | CPU_I586_FLAGS }, | |
585 | { "i686", PROCESSOR_PENTIUMPRO, | |
586 | CPU_I686_FLAGS }, | |
587 | { "pentium", PROCESSOR_PENTIUM, | |
588 | CPU_I586_FLAGS }, | |
589 | { "pentiumpro", PROCESSOR_PENTIUMPRO, | |
590 | CPU_I686_FLAGS }, | |
591 | { "pentiumii", PROCESSOR_PENTIUMPRO, | |
592 | CPU_P2_FLAGS }, | |
593 | { "pentiumiii",PROCESSOR_PENTIUMPRO, | |
594 | CPU_P3_FLAGS }, | |
595 | { "pentium4", PROCESSOR_PENTIUM4, | |
596 | CPU_P4_FLAGS }, | |
597 | { "prescott", PROCESSOR_NOCONA, | |
598 | CPU_CORE_FLAGS }, | |
599 | { "nocona", PROCESSOR_NOCONA, | |
600 | CPU_NOCONA_FLAGS }, | |
601 | { "yonah", PROCESSOR_CORE, | |
602 | CPU_CORE_FLAGS }, | |
603 | { "core", PROCESSOR_CORE, | |
604 | CPU_CORE_FLAGS }, | |
605 | { "merom", PROCESSOR_CORE2, | |
606 | CPU_CORE2_FLAGS }, | |
607 | { "core2", PROCESSOR_CORE2, | |
608 | CPU_CORE2_FLAGS }, | |
bd5295b2 L |
609 | { "corei7", PROCESSOR_COREI7, |
610 | CPU_COREI7_FLAGS }, | |
6305a203 L |
611 | { "k6", PROCESSOR_K6, |
612 | CPU_K6_FLAGS }, | |
613 | { "k6_2", PROCESSOR_K6, | |
614 | CPU_K6_2_FLAGS }, | |
615 | { "athlon", PROCESSOR_ATHLON, | |
616 | CPU_ATHLON_FLAGS }, | |
617 | { "sledgehammer", PROCESSOR_K8, | |
618 | CPU_K8_FLAGS }, | |
619 | { "opteron", PROCESSOR_K8, | |
620 | CPU_K8_FLAGS }, | |
621 | { "k8", PROCESSOR_K8, | |
622 | CPU_K8_FLAGS }, | |
623 | { "amdfam10", PROCESSOR_AMDFAM10, | |
624 | CPU_AMDFAM10_FLAGS }, | |
625 | { ".mmx", PROCESSOR_UNKNOWN, | |
626 | CPU_MMX_FLAGS }, | |
627 | { ".sse", PROCESSOR_UNKNOWN, | |
628 | CPU_SSE_FLAGS }, | |
629 | { ".sse2", PROCESSOR_UNKNOWN, | |
630 | CPU_SSE2_FLAGS }, | |
631 | { ".sse3", PROCESSOR_UNKNOWN, | |
632 | CPU_SSE3_FLAGS }, | |
633 | { ".ssse3", PROCESSOR_UNKNOWN, | |
634 | CPU_SSSE3_FLAGS }, | |
635 | { ".sse4.1", PROCESSOR_UNKNOWN, | |
636 | CPU_SSE4_1_FLAGS }, | |
637 | { ".sse4.2", PROCESSOR_UNKNOWN, | |
638 | CPU_SSE4_2_FLAGS }, | |
639 | { ".sse4", PROCESSOR_UNKNOWN, | |
640 | CPU_SSE4_2_FLAGS }, | |
c0f3af97 L |
641 | { ".avx", PROCESSOR_UNKNOWN, |
642 | CPU_AVX_FLAGS }, | |
6305a203 L |
643 | { ".vmx", PROCESSOR_UNKNOWN, |
644 | CPU_VMX_FLAGS }, | |
645 | { ".smx", PROCESSOR_UNKNOWN, | |
646 | CPU_SMX_FLAGS }, | |
f03fe4c1 L |
647 | { ".xsave", PROCESSOR_UNKNOWN, |
648 | CPU_XSAVE_FLAGS }, | |
c0f3af97 L |
649 | { ".aes", PROCESSOR_UNKNOWN, |
650 | CPU_AES_FLAGS }, | |
594ab6a3 L |
651 | { ".pclmul", PROCESSOR_UNKNOWN, |
652 | CPU_PCLMUL_FLAGS }, | |
c0f3af97 | 653 | { ".clmul", PROCESSOR_UNKNOWN, |
594ab6a3 | 654 | CPU_PCLMUL_FLAGS }, |
c0f3af97 L |
655 | { ".fma", PROCESSOR_UNKNOWN, |
656 | CPU_FMA_FLAGS }, | |
f1f8f695 L |
657 | { ".movbe", PROCESSOR_UNKNOWN, |
658 | CPU_MOVBE_FLAGS }, | |
659 | { ".ept", PROCESSOR_UNKNOWN, | |
660 | CPU_EPT_FLAGS }, | |
bd5295b2 L |
661 | { ".clflush", PROCESSOR_UNKNOWN, |
662 | CPU_CLFLUSH_FLAGS }, | |
663 | { ".syscall", PROCESSOR_UNKNOWN, | |
664 | CPU_SYSCALL_FLAGS }, | |
1b7f3fb0 L |
665 | { ".rdtscp", PROCESSOR_UNKNOWN, |
666 | CPU_RDTSCP_FLAGS }, | |
6305a203 L |
667 | { ".3dnow", PROCESSOR_UNKNOWN, |
668 | CPU_3DNOW_FLAGS }, | |
669 | { ".3dnowa", PROCESSOR_UNKNOWN, | |
670 | CPU_3DNOWA_FLAGS }, | |
671 | { ".padlock", PROCESSOR_UNKNOWN, | |
672 | CPU_PADLOCK_FLAGS }, | |
673 | { ".pacifica", PROCESSOR_UNKNOWN, | |
674 | CPU_SVME_FLAGS }, | |
675 | { ".svme", PROCESSOR_UNKNOWN, | |
676 | CPU_SVME_FLAGS }, | |
677 | { ".sse4a", PROCESSOR_UNKNOWN, | |
678 | CPU_SSE4A_FLAGS }, | |
679 | { ".abm", PROCESSOR_UNKNOWN, | |
680 | CPU_ABM_FLAGS }, | |
681 | { ".sse5", PROCESSOR_UNKNOWN, | |
682 | CPU_SSE5_FLAGS }, | |
e413e4e9 AM |
683 | }; |
684 | ||
704209c0 | 685 | #ifdef I386COFF |
a6c24e68 NC |
686 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
687 | is allowed to be optional. */ | |
688 | ||
689 | static symbolS * | |
690 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
691 | { | |
692 | addressT align = 0; | |
693 | ||
694 | SKIP_WHITESPACE (); | |
695 | ||
696 | if (needs_align | |
697 | && *input_line_pointer == ',') | |
698 | { | |
699 | align = parse_align (needs_align - 1); | |
700 | ||
701 | if (align == (addressT) -1) | |
702 | return NULL; | |
703 | } | |
704 | else | |
705 | { | |
706 | if (size >= 8) | |
707 | align = 3; | |
708 | else if (size >= 4) | |
709 | align = 2; | |
710 | else if (size >= 2) | |
711 | align = 1; | |
712 | else | |
713 | align = 0; | |
714 | } | |
715 | ||
716 | bss_alloc (symbolP, size, align); | |
717 | return symbolP; | |
718 | } | |
719 | ||
704209c0 | 720 | static void |
a6c24e68 NC |
721 | pe_lcomm (int needs_align) |
722 | { | |
723 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
724 | } | |
704209c0 | 725 | #endif |
a6c24e68 | 726 | |
29b0f896 AM |
727 | const pseudo_typeS md_pseudo_table[] = |
728 | { | |
729 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
730 | {"align", s_align_bytes, 0}, | |
731 | #else | |
732 | {"align", s_align_ptwo, 0}, | |
733 | #endif | |
734 | {"arch", set_cpu_arch, 0}, | |
735 | #ifndef I386COFF | |
736 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
737 | #else |
738 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
739 | #endif |
740 | {"ffloat", float_cons, 'f'}, | |
741 | {"dfloat", float_cons, 'd'}, | |
742 | {"tfloat", float_cons, 'x'}, | |
743 | {"value", cons, 2}, | |
d182319b | 744 | {"slong", signed_cons, 4}, |
29b0f896 AM |
745 | {"noopt", s_ignore, 0}, |
746 | {"optim", s_ignore, 0}, | |
747 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
748 | {"code16", set_code_flag, CODE_16BIT}, | |
749 | {"code32", set_code_flag, CODE_32BIT}, | |
750 | {"code64", set_code_flag, CODE_64BIT}, | |
751 | {"intel_syntax", set_intel_syntax, 1}, | |
752 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
753 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
754 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
755 | {"allow_index_reg", set_allow_index_reg, 1}, |
756 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
cb19c032 | 757 | {"sse_check", set_sse_check, 0}, |
3b22753a L |
758 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
759 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 760 | #else |
e3bb37b5 | 761 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
762 | {"loc", dwarf2_directive_loc, 0}, |
763 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 764 | #endif |
6482c264 NC |
765 | #ifdef TE_PE |
766 | {"secrel32", pe_directive_secrel, 0}, | |
767 | #endif | |
29b0f896 AM |
768 | {0, 0, 0} |
769 | }; | |
770 | ||
771 | /* For interface with expression (). */ | |
772 | extern char *input_line_pointer; | |
773 | ||
774 | /* Hash table for instruction mnemonic lookup. */ | |
775 | static struct hash_control *op_hash; | |
776 | ||
777 | /* Hash table for register lookup. */ | |
778 | static struct hash_control *reg_hash; | |
779 | \f | |
252b5132 | 780 | void |
e3bb37b5 | 781 | i386_align_code (fragS *fragP, int count) |
252b5132 | 782 | { |
ce8a8b2f AM |
783 | /* Various efficient no-op patterns for aligning code labels. |
784 | Note: Don't try to assemble the instructions in the comments. | |
785 | 0L and 0w are not legal. */ | |
252b5132 RH |
786 | static const char f32_1[] = |
787 | {0x90}; /* nop */ | |
788 | static const char f32_2[] = | |
ccc9c027 | 789 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
790 | static const char f32_3[] = |
791 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
792 | static const char f32_4[] = | |
793 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
794 | static const char f32_5[] = | |
795 | {0x90, /* nop */ | |
796 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
797 | static const char f32_6[] = | |
798 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
799 | static const char f32_7[] = | |
800 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
801 | static const char f32_8[] = | |
802 | {0x90, /* nop */ | |
803 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
804 | static const char f32_9[] = | |
805 | {0x89,0xf6, /* movl %esi,%esi */ | |
806 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
807 | static const char f32_10[] = | |
808 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
809 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
810 | static const char f32_11[] = | |
811 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
812 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
813 | static const char f32_12[] = | |
814 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
815 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
816 | static const char f32_13[] = | |
817 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
818 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
819 | static const char f32_14[] = | |
820 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
821 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
822 | static const char f16_3[] = |
823 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
824 | static const char f16_4[] = |
825 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
826 | static const char f16_5[] = | |
827 | {0x90, /* nop */ | |
828 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
829 | static const char f16_6[] = | |
830 | {0x89,0xf6, /* mov %si,%si */ | |
831 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
832 | static const char f16_7[] = | |
833 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
834 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
835 | static const char f16_8[] = | |
836 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
837 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
838 | static const char jump_31[] = |
839 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
840 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
841 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
842 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
843 | static const char *const f32_patt[] = { |
844 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 845 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
846 | }; |
847 | static const char *const f16_patt[] = { | |
76bc74dc | 848 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 849 | }; |
ccc9c027 L |
850 | /* nopl (%[re]ax) */ |
851 | static const char alt_3[] = | |
852 | {0x0f,0x1f,0x00}; | |
853 | /* nopl 0(%[re]ax) */ | |
854 | static const char alt_4[] = | |
855 | {0x0f,0x1f,0x40,0x00}; | |
856 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
857 | static const char alt_5[] = | |
858 | {0x0f,0x1f,0x44,0x00,0x00}; | |
859 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
860 | static const char alt_6[] = | |
861 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
862 | /* nopl 0L(%[re]ax) */ | |
863 | static const char alt_7[] = | |
864 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
865 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
866 | static const char alt_8[] = | |
867 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
868 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
869 | static const char alt_9[] = | |
870 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
871 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
872 | static const char alt_10[] = | |
873 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
874 | /* data16 | |
875 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
876 | static const char alt_long_11[] = | |
877 | {0x66, | |
878 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
879 | /* data16 | |
880 | data16 | |
881 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
882 | static const char alt_long_12[] = | |
883 | {0x66, | |
884 | 0x66, | |
885 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
886 | /* data16 | |
887 | data16 | |
888 | data16 | |
889 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
890 | static const char alt_long_13[] = | |
891 | {0x66, | |
892 | 0x66, | |
893 | 0x66, | |
894 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
895 | /* data16 | |
896 | data16 | |
897 | data16 | |
898 | data16 | |
899 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
900 | static const char alt_long_14[] = | |
901 | {0x66, | |
902 | 0x66, | |
903 | 0x66, | |
904 | 0x66, | |
905 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
906 | /* data16 | |
907 | data16 | |
908 | data16 | |
909 | data16 | |
910 | data16 | |
911 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
912 | static const char alt_long_15[] = | |
913 | {0x66, | |
914 | 0x66, | |
915 | 0x66, | |
916 | 0x66, | |
917 | 0x66, | |
918 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
919 | /* nopl 0(%[re]ax,%[re]ax,1) | |
920 | nopw 0(%[re]ax,%[re]ax,1) */ | |
921 | static const char alt_short_11[] = | |
922 | {0x0f,0x1f,0x44,0x00,0x00, | |
923 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
924 | /* nopw 0(%[re]ax,%[re]ax,1) | |
925 | nopw 0(%[re]ax,%[re]ax,1) */ | |
926 | static const char alt_short_12[] = | |
927 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
928 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
929 | /* nopw 0(%[re]ax,%[re]ax,1) | |
930 | nopl 0L(%[re]ax) */ | |
931 | static const char alt_short_13[] = | |
932 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
933 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
934 | /* nopl 0L(%[re]ax) | |
935 | nopl 0L(%[re]ax) */ | |
936 | static const char alt_short_14[] = | |
937 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
938 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
939 | /* nopl 0L(%[re]ax) | |
940 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
941 | static const char alt_short_15[] = | |
942 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
943 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
944 | static const char *const alt_short_patt[] = { | |
945 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
946 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
947 | alt_short_14, alt_short_15 | |
948 | }; | |
949 | static const char *const alt_long_patt[] = { | |
950 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
951 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
952 | alt_long_14, alt_long_15 | |
953 | }; | |
252b5132 | 954 | |
76bc74dc L |
955 | /* Only align for at least a positive non-zero boundary. */ |
956 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 957 | return; |
3e73aa7c | 958 | |
ccc9c027 L |
959 | /* We need to decide which NOP sequence to use for 32bit and |
960 | 64bit. When -mtune= is used: | |
4eed87de | 961 | |
76bc74dc L |
962 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
963 | PROCESSOR_GENERIC32, f32_patt will be used. | |
964 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
bd5295b2 L |
965 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and |
966 | PROCESSOR_GENERIC64, alt_long_patt will be used. | |
76bc74dc L |
967 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and |
968 | PROCESSOR_AMDFAM10, alt_short_patt will be used. | |
ccc9c027 | 969 | |
76bc74dc L |
970 | When -mtune= isn't used, alt_long_patt will be used if |
971 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will | |
972 | be used. | |
ccc9c027 L |
973 | |
974 | When -march= or .arch is used, we can't use anything beyond | |
975 | cpu_arch_isa_flags. */ | |
976 | ||
977 | if (flag_code == CODE_16BIT) | |
978 | { | |
ccc9c027 | 979 | if (count > 8) |
33fef721 | 980 | { |
76bc74dc L |
981 | memcpy (fragP->fr_literal + fragP->fr_fix, |
982 | jump_31, count); | |
983 | /* Adjust jump offset. */ | |
984 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 985 | } |
76bc74dc L |
986 | else |
987 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
988 | f16_patt[count - 1], count); | |
252b5132 | 989 | } |
33fef721 | 990 | else |
ccc9c027 L |
991 | { |
992 | const char *const *patt = NULL; | |
993 | ||
fbf3f584 | 994 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
995 | { |
996 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
997 | switch (cpu_arch_tune) | |
998 | { | |
999 | case PROCESSOR_UNKNOWN: | |
1000 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
1001 | optimize for Cpu686. */ | |
fbf3f584 | 1002 | if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) |
76bc74dc | 1003 | patt = alt_long_patt; |
ccc9c027 L |
1004 | else |
1005 | patt = f32_patt; | |
1006 | break; | |
ccc9c027 L |
1007 | case PROCESSOR_PENTIUMPRO: |
1008 | case PROCESSOR_PENTIUM4: | |
1009 | case PROCESSOR_NOCONA: | |
ef05d495 | 1010 | case PROCESSOR_CORE: |
76bc74dc | 1011 | case PROCESSOR_CORE2: |
bd5295b2 | 1012 | case PROCESSOR_COREI7: |
76bc74dc L |
1013 | case PROCESSOR_GENERIC64: |
1014 | patt = alt_long_patt; | |
1015 | break; | |
ccc9c027 L |
1016 | case PROCESSOR_K6: |
1017 | case PROCESSOR_ATHLON: | |
1018 | case PROCESSOR_K8: | |
4eed87de | 1019 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1020 | patt = alt_short_patt; |
1021 | break; | |
76bc74dc | 1022 | case PROCESSOR_I386: |
ccc9c027 L |
1023 | case PROCESSOR_I486: |
1024 | case PROCESSOR_PENTIUM: | |
1025 | case PROCESSOR_GENERIC32: | |
1026 | patt = f32_patt; | |
1027 | break; | |
4eed87de | 1028 | } |
ccc9c027 L |
1029 | } |
1030 | else | |
1031 | { | |
fbf3f584 | 1032 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1033 | { |
1034 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1035 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1036 | PROCESSOR_UNKNOWN. */ |
1037 | abort (); | |
1038 | break; | |
1039 | ||
76bc74dc | 1040 | case PROCESSOR_I386: |
ccc9c027 L |
1041 | case PROCESSOR_I486: |
1042 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1043 | case PROCESSOR_K6: |
1044 | case PROCESSOR_ATHLON: | |
1045 | case PROCESSOR_K8: | |
4eed87de | 1046 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1047 | case PROCESSOR_GENERIC32: |
1048 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
1049 | for Cpu686. */ | |
fbf3f584 | 1050 | if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) |
ccc9c027 L |
1051 | patt = alt_short_patt; |
1052 | else | |
1053 | patt = f32_patt; | |
1054 | break; | |
76bc74dc L |
1055 | case PROCESSOR_PENTIUMPRO: |
1056 | case PROCESSOR_PENTIUM4: | |
1057 | case PROCESSOR_NOCONA: | |
1058 | case PROCESSOR_CORE: | |
ef05d495 | 1059 | case PROCESSOR_CORE2: |
bd5295b2 | 1060 | case PROCESSOR_COREI7: |
fbf3f584 | 1061 | if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) |
ccc9c027 L |
1062 | patt = alt_long_patt; |
1063 | else | |
1064 | patt = f32_patt; | |
1065 | break; | |
1066 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1067 | patt = alt_long_patt; |
ccc9c027 | 1068 | break; |
4eed87de | 1069 | } |
ccc9c027 L |
1070 | } |
1071 | ||
76bc74dc L |
1072 | if (patt == f32_patt) |
1073 | { | |
1074 | /* If the padding is less than 15 bytes, we use the normal | |
1075 | ones. Otherwise, we use a jump instruction and adjust | |
1076 | its offset. */ | |
1077 | if (count < 15) | |
1078 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1079 | patt[count - 1], count); | |
1080 | else | |
1081 | { | |
1082 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1083 | jump_31, count); | |
1084 | /* Adjust jump offset. */ | |
1085 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1086 | } | |
1087 | } | |
1088 | else | |
1089 | { | |
1090 | /* Maximum length of an instruction is 15 byte. If the | |
1091 | padding is greater than 15 bytes and we don't use jump, | |
1092 | we have to break it into smaller pieces. */ | |
1093 | int padding = count; | |
1094 | while (padding > 15) | |
1095 | { | |
1096 | padding -= 15; | |
1097 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1098 | patt [14], 15); | |
1099 | } | |
1100 | ||
1101 | if (padding) | |
1102 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1103 | patt [padding - 1], padding); | |
1104 | } | |
ccc9c027 | 1105 | } |
33fef721 | 1106 | fragP->fr_var = count; |
252b5132 RH |
1107 | } |
1108 | ||
c6fb90c8 | 1109 | static INLINE int |
0dfbf9d7 | 1110 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1111 | { |
0dfbf9d7 | 1112 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1113 | { |
1114 | case 3: | |
0dfbf9d7 | 1115 | if (x->array[2]) |
c6fb90c8 L |
1116 | return 0; |
1117 | case 2: | |
0dfbf9d7 | 1118 | if (x->array[1]) |
c6fb90c8 L |
1119 | return 0; |
1120 | case 1: | |
0dfbf9d7 | 1121 | return !x->array[0]; |
c6fb90c8 L |
1122 | default: |
1123 | abort (); | |
1124 | } | |
40fb9820 L |
1125 | } |
1126 | ||
c6fb90c8 | 1127 | static INLINE void |
0dfbf9d7 | 1128 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1129 | { |
0dfbf9d7 | 1130 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1131 | { |
1132 | case 3: | |
0dfbf9d7 | 1133 | x->array[2] = v; |
c6fb90c8 | 1134 | case 2: |
0dfbf9d7 | 1135 | x->array[1] = v; |
c6fb90c8 | 1136 | case 1: |
0dfbf9d7 | 1137 | x->array[0] = v; |
c6fb90c8 L |
1138 | break; |
1139 | default: | |
1140 | abort (); | |
1141 | } | |
1142 | } | |
40fb9820 | 1143 | |
c6fb90c8 | 1144 | static INLINE int |
0dfbf9d7 L |
1145 | operand_type_equal (const union i386_operand_type *x, |
1146 | const union i386_operand_type *y) | |
c6fb90c8 | 1147 | { |
0dfbf9d7 | 1148 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1149 | { |
1150 | case 3: | |
0dfbf9d7 | 1151 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1152 | return 0; |
1153 | case 2: | |
0dfbf9d7 | 1154 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1155 | return 0; |
1156 | case 1: | |
0dfbf9d7 | 1157 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1158 | break; |
1159 | default: | |
1160 | abort (); | |
1161 | } | |
1162 | } | |
40fb9820 | 1163 | |
0dfbf9d7 L |
1164 | static INLINE int |
1165 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1166 | { | |
1167 | switch (ARRAY_SIZE(x->array)) | |
1168 | { | |
1169 | case 3: | |
1170 | if (x->array[2]) | |
1171 | return 0; | |
1172 | case 2: | |
1173 | if (x->array[1]) | |
1174 | return 0; | |
1175 | case 1: | |
1176 | return !x->array[0]; | |
1177 | default: | |
1178 | abort (); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | static INLINE void | |
1183 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1184 | { | |
1185 | switch (ARRAY_SIZE(x->array)) | |
1186 | { | |
1187 | case 3: | |
1188 | x->array[2] = v; | |
1189 | case 2: | |
1190 | x->array[1] = v; | |
1191 | case 1: | |
1192 | x->array[0] = v; | |
1193 | break; | |
1194 | default: | |
1195 | abort (); | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | static INLINE int | |
1200 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1201 | const union i386_cpu_flags *y) | |
1202 | { | |
1203 | switch (ARRAY_SIZE(x->array)) | |
1204 | { | |
1205 | case 3: | |
1206 | if (x->array[2] != y->array[2]) | |
1207 | return 0; | |
1208 | case 2: | |
1209 | if (x->array[1] != y->array[1]) | |
1210 | return 0; | |
1211 | case 1: | |
1212 | return x->array[0] == y->array[0]; | |
1213 | break; | |
1214 | default: | |
1215 | abort (); | |
1216 | } | |
1217 | } | |
c6fb90c8 L |
1218 | |
1219 | static INLINE int | |
1220 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1221 | { | |
1222 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1223 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1224 | } |
1225 | ||
c6fb90c8 L |
1226 | static INLINE i386_cpu_flags |
1227 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1228 | { |
c6fb90c8 L |
1229 | switch (ARRAY_SIZE (x.array)) |
1230 | { | |
1231 | case 3: | |
1232 | x.array [2] &= y.array [2]; | |
1233 | case 2: | |
1234 | x.array [1] &= y.array [1]; | |
1235 | case 1: | |
1236 | x.array [0] &= y.array [0]; | |
1237 | break; | |
1238 | default: | |
1239 | abort (); | |
1240 | } | |
1241 | return x; | |
1242 | } | |
40fb9820 | 1243 | |
c6fb90c8 L |
1244 | static INLINE i386_cpu_flags |
1245 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1246 | { |
c6fb90c8 | 1247 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1248 | { |
c6fb90c8 L |
1249 | case 3: |
1250 | x.array [2] |= y.array [2]; | |
1251 | case 2: | |
1252 | x.array [1] |= y.array [1]; | |
1253 | case 1: | |
1254 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1255 | break; |
1256 | default: | |
1257 | abort (); | |
1258 | } | |
40fb9820 L |
1259 | return x; |
1260 | } | |
1261 | ||
c0f3af97 L |
1262 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1263 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1264 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1265 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1266 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1267 | |
a5ff0eb2 | 1268 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1269 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1270 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1271 | #define CPU_FLAGS_PERFECT_MATCH \ |
1272 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1273 | ||
1274 | /* Return CPU flags match bits. */ | |
3629bb00 | 1275 | |
40fb9820 | 1276 | static int |
c0f3af97 | 1277 | cpu_flags_match (const template *t) |
40fb9820 | 1278 | { |
c0f3af97 L |
1279 | i386_cpu_flags x = t->cpu_flags; |
1280 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1281 | |
1282 | x.bitfield.cpu64 = 0; | |
1283 | x.bitfield.cpuno64 = 0; | |
1284 | ||
0dfbf9d7 | 1285 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1286 | { |
1287 | /* This instruction is available on all archs. */ | |
1288 | match |= CPU_FLAGS_32BIT_MATCH; | |
1289 | } | |
3629bb00 L |
1290 | else |
1291 | { | |
c0f3af97 | 1292 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1293 | i386_cpu_flags cpu = cpu_arch_flags; |
1294 | ||
1295 | cpu.bitfield.cpu64 = 0; | |
1296 | cpu.bitfield.cpuno64 = 0; | |
1297 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1298 | if (!cpu_flags_all_zero (&cpu)) |
1299 | { | |
a5ff0eb2 L |
1300 | if (x.bitfield.cpuavx) |
1301 | { | |
ce2f5b3c | 1302 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1303 | if (cpu.bitfield.cpuavx) |
1304 | { | |
1305 | /* Check SSE2AVX. */ | |
1306 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1307 | { | |
1308 | match |= (CPU_FLAGS_ARCH_MATCH | |
1309 | | CPU_FLAGS_AVX_MATCH); | |
1310 | /* Check AES. */ | |
1311 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1312 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1313 | /* Check PCLMUL. */ |
1314 | if (!x.bitfield.cpupclmul | |
1315 | || cpu.bitfield.cpupclmul) | |
1316 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1317 | } |
1318 | } | |
1319 | else | |
1320 | match |= CPU_FLAGS_ARCH_MATCH; | |
1321 | } | |
1322 | else | |
c0f3af97 L |
1323 | match |= CPU_FLAGS_32BIT_MATCH; |
1324 | } | |
3629bb00 | 1325 | } |
c0f3af97 | 1326 | return match; |
40fb9820 L |
1327 | } |
1328 | ||
c6fb90c8 L |
1329 | static INLINE i386_operand_type |
1330 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1331 | { |
c6fb90c8 L |
1332 | switch (ARRAY_SIZE (x.array)) |
1333 | { | |
1334 | case 3: | |
1335 | x.array [2] &= y.array [2]; | |
1336 | case 2: | |
1337 | x.array [1] &= y.array [1]; | |
1338 | case 1: | |
1339 | x.array [0] &= y.array [0]; | |
1340 | break; | |
1341 | default: | |
1342 | abort (); | |
1343 | } | |
1344 | return x; | |
40fb9820 L |
1345 | } |
1346 | ||
c6fb90c8 L |
1347 | static INLINE i386_operand_type |
1348 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1349 | { |
c6fb90c8 | 1350 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1351 | { |
c6fb90c8 L |
1352 | case 3: |
1353 | x.array [2] |= y.array [2]; | |
1354 | case 2: | |
1355 | x.array [1] |= y.array [1]; | |
1356 | case 1: | |
1357 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1358 | break; |
1359 | default: | |
1360 | abort (); | |
1361 | } | |
c6fb90c8 L |
1362 | return x; |
1363 | } | |
40fb9820 | 1364 | |
c6fb90c8 L |
1365 | static INLINE i386_operand_type |
1366 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1367 | { | |
1368 | switch (ARRAY_SIZE (x.array)) | |
1369 | { | |
1370 | case 3: | |
1371 | x.array [2] ^= y.array [2]; | |
1372 | case 2: | |
1373 | x.array [1] ^= y.array [1]; | |
1374 | case 1: | |
1375 | x.array [0] ^= y.array [0]; | |
1376 | break; | |
1377 | default: | |
1378 | abort (); | |
1379 | } | |
40fb9820 L |
1380 | return x; |
1381 | } | |
1382 | ||
1383 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1384 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1385 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1386 | static const i386_operand_type inoutportreg |
1387 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1388 | static const i386_operand_type reg16_inoutportreg |
1389 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1390 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1391 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1392 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1393 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1394 | static const i386_operand_type anydisp | |
1395 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1396 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1397 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1398 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1399 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1400 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1401 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1402 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1403 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1404 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1405 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1406 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1407 | ||
1408 | enum operand_type | |
1409 | { | |
1410 | reg, | |
40fb9820 L |
1411 | imm, |
1412 | disp, | |
1413 | anymem | |
1414 | }; | |
1415 | ||
c6fb90c8 | 1416 | static INLINE int |
40fb9820 L |
1417 | operand_type_check (i386_operand_type t, enum operand_type c) |
1418 | { | |
1419 | switch (c) | |
1420 | { | |
1421 | case reg: | |
1422 | return (t.bitfield.reg8 | |
1423 | || t.bitfield.reg16 | |
1424 | || t.bitfield.reg32 | |
1425 | || t.bitfield.reg64); | |
1426 | ||
40fb9820 L |
1427 | case imm: |
1428 | return (t.bitfield.imm8 | |
1429 | || t.bitfield.imm8s | |
1430 | || t.bitfield.imm16 | |
1431 | || t.bitfield.imm32 | |
1432 | || t.bitfield.imm32s | |
1433 | || t.bitfield.imm64); | |
1434 | ||
1435 | case disp: | |
1436 | return (t.bitfield.disp8 | |
1437 | || t.bitfield.disp16 | |
1438 | || t.bitfield.disp32 | |
1439 | || t.bitfield.disp32s | |
1440 | || t.bitfield.disp64); | |
1441 | ||
1442 | case anymem: | |
1443 | return (t.bitfield.disp8 | |
1444 | || t.bitfield.disp16 | |
1445 | || t.bitfield.disp32 | |
1446 | || t.bitfield.disp32s | |
1447 | || t.bitfield.disp64 | |
1448 | || t.bitfield.baseindex); | |
1449 | ||
1450 | default: | |
1451 | abort (); | |
1452 | } | |
2cfe26b6 AM |
1453 | |
1454 | return 0; | |
40fb9820 L |
1455 | } |
1456 | ||
5c07affc L |
1457 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1458 | operand J for instruction template T. */ | |
1459 | ||
1460 | static INLINE int | |
1461 | match_reg_size (const template *t, unsigned int j) | |
1462 | { | |
1463 | return !((i.types[j].bitfield.byte | |
1464 | && !t->operand_types[j].bitfield.byte) | |
1465 | || (i.types[j].bitfield.word | |
1466 | && !t->operand_types[j].bitfield.word) | |
1467 | || (i.types[j].bitfield.dword | |
1468 | && !t->operand_types[j].bitfield.dword) | |
1469 | || (i.types[j].bitfield.qword | |
1470 | && !t->operand_types[j].bitfield.qword)); | |
1471 | } | |
1472 | ||
1473 | /* Return 1 if there is no conflict in any size on operand J for | |
1474 | instruction template T. */ | |
1475 | ||
1476 | static INLINE int | |
1477 | match_mem_size (const template *t, unsigned int j) | |
1478 | { | |
1479 | return (match_reg_size (t, j) | |
1480 | && !((i.types[j].bitfield.unspecified | |
1481 | && !t->operand_types[j].bitfield.unspecified) | |
1482 | || (i.types[j].bitfield.fword | |
1483 | && !t->operand_types[j].bitfield.fword) | |
1484 | || (i.types[j].bitfield.tbyte | |
1485 | && !t->operand_types[j].bitfield.tbyte) | |
1486 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1487 | && !t->operand_types[j].bitfield.xmmword) |
1488 | || (i.types[j].bitfield.ymmword | |
1489 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1490 | } |
1491 | ||
1492 | /* Return 1 if there is no size conflict on any operands for | |
1493 | instruction template T. */ | |
1494 | ||
1495 | static INLINE int | |
1496 | operand_size_match (const template *t) | |
1497 | { | |
1498 | unsigned int j; | |
1499 | int match = 1; | |
1500 | ||
1501 | /* Don't check jump instructions. */ | |
1502 | if (t->opcode_modifier.jump | |
1503 | || t->opcode_modifier.jumpbyte | |
1504 | || t->opcode_modifier.jumpdword | |
1505 | || t->opcode_modifier.jumpintersegment) | |
1506 | return match; | |
1507 | ||
1508 | /* Check memory and accumulator operand size. */ | |
1509 | for (j = 0; j < i.operands; j++) | |
1510 | { | |
1511 | if (t->operand_types[j].bitfield.anysize) | |
1512 | continue; | |
1513 | ||
1514 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1515 | { | |
1516 | match = 0; | |
1517 | break; | |
1518 | } | |
1519 | ||
1520 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1521 | { | |
1522 | match = 0; | |
1523 | break; | |
1524 | } | |
1525 | } | |
1526 | ||
1527 | if (match | |
1528 | || (!t->opcode_modifier.d && !t->opcode_modifier.floatd)) | |
1529 | return match; | |
1530 | ||
1531 | /* Check reverse. */ | |
1532 | assert (i.operands == 2); | |
1533 | ||
1534 | match = 1; | |
1535 | for (j = 0; j < 2; j++) | |
1536 | { | |
1537 | if (t->operand_types[j].bitfield.acc | |
1538 | && !match_reg_size (t, j ? 0 : 1)) | |
1539 | { | |
1540 | match = 0; | |
1541 | break; | |
1542 | } | |
1543 | ||
1544 | if (i.types[j].bitfield.mem | |
1545 | && !match_mem_size (t, j ? 0 : 1)) | |
1546 | { | |
1547 | match = 0; | |
1548 | break; | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | return match; | |
1553 | } | |
1554 | ||
c6fb90c8 | 1555 | static INLINE int |
40fb9820 L |
1556 | operand_type_match (i386_operand_type overlap, |
1557 | i386_operand_type given) | |
1558 | { | |
1559 | i386_operand_type temp = overlap; | |
1560 | ||
1561 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1562 | temp.bitfield.unspecified = 0; |
5c07affc L |
1563 | temp.bitfield.byte = 0; |
1564 | temp.bitfield.word = 0; | |
1565 | temp.bitfield.dword = 0; | |
1566 | temp.bitfield.fword = 0; | |
1567 | temp.bitfield.qword = 0; | |
1568 | temp.bitfield.tbyte = 0; | |
1569 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1570 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1571 | if (operand_type_all_zero (&temp)) |
40fb9820 L |
1572 | return 0; |
1573 | ||
1574 | return (given.bitfield.baseindex == overlap.bitfield.baseindex | |
1575 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute); | |
1576 | } | |
1577 | ||
7d5e4556 | 1578 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1579 | unless the expected operand type register overlap is null. |
1580 | Note that Acc in a template matches every size of reg. */ | |
1581 | ||
c6fb90c8 | 1582 | static INLINE int |
40fb9820 L |
1583 | operand_type_register_match (i386_operand_type m0, |
1584 | i386_operand_type g0, | |
1585 | i386_operand_type t0, | |
1586 | i386_operand_type m1, | |
1587 | i386_operand_type g1, | |
1588 | i386_operand_type t1) | |
1589 | { | |
1590 | if (!operand_type_check (g0, reg)) | |
1591 | return 1; | |
1592 | ||
1593 | if (!operand_type_check (g1, reg)) | |
1594 | return 1; | |
1595 | ||
1596 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1597 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1598 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1599 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1600 | return 1; | |
1601 | ||
1602 | if (m0.bitfield.acc) | |
1603 | { | |
1604 | t0.bitfield.reg8 = 1; | |
1605 | t0.bitfield.reg16 = 1; | |
1606 | t0.bitfield.reg32 = 1; | |
1607 | t0.bitfield.reg64 = 1; | |
1608 | } | |
1609 | ||
1610 | if (m1.bitfield.acc) | |
1611 | { | |
1612 | t1.bitfield.reg8 = 1; | |
1613 | t1.bitfield.reg16 = 1; | |
1614 | t1.bitfield.reg32 = 1; | |
1615 | t1.bitfield.reg64 = 1; | |
1616 | } | |
1617 | ||
1618 | return (!(t0.bitfield.reg8 & t1.bitfield.reg8) | |
1619 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1620 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1621 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)); | |
1622 | } | |
1623 | ||
252b5132 | 1624 | static INLINE unsigned int |
40fb9820 | 1625 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1626 | { |
40fb9820 L |
1627 | if (t.bitfield.disp8) |
1628 | return 1; | |
1629 | else if (t.bitfield.disp16 | |
1630 | || t.bitfield.disp32 | |
1631 | || t.bitfield.disp32s) | |
1632 | return 2; | |
1633 | else | |
1634 | return 0; | |
252b5132 RH |
1635 | } |
1636 | ||
1637 | static INLINE int | |
e3bb37b5 | 1638 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1639 | { |
1640 | return (num >= -128) && (num <= 127); | |
47926f60 | 1641 | } |
252b5132 RH |
1642 | |
1643 | static INLINE int | |
e3bb37b5 | 1644 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1645 | { |
1646 | return (num & 0xff) == num; | |
47926f60 | 1647 | } |
252b5132 RH |
1648 | |
1649 | static INLINE int | |
e3bb37b5 | 1650 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1651 | { |
1652 | return (num & 0xffff) == num; | |
47926f60 | 1653 | } |
252b5132 RH |
1654 | |
1655 | static INLINE int | |
e3bb37b5 | 1656 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1657 | { |
1658 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1659 | } |
2a962e6d | 1660 | |
3e73aa7c | 1661 | static INLINE int |
e3bb37b5 | 1662 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1663 | { |
1664 | #ifndef BFD64 | |
1665 | return 1; | |
1666 | #else | |
1667 | return (!(((offsetT) -1 << 31) & num) | |
1668 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1669 | #endif | |
1670 | } /* fits_in_signed_long() */ | |
2a962e6d | 1671 | |
3e73aa7c | 1672 | static INLINE int |
e3bb37b5 | 1673 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1674 | { |
1675 | #ifndef BFD64 | |
1676 | return 1; | |
1677 | #else | |
1678 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1679 | #endif | |
1680 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1681 | |
40fb9820 | 1682 | static i386_operand_type |
e3bb37b5 | 1683 | smallest_imm_type (offsetT num) |
252b5132 | 1684 | { |
40fb9820 L |
1685 | i386_operand_type t; |
1686 | ||
0dfbf9d7 | 1687 | operand_type_set (&t, 0); |
40fb9820 L |
1688 | t.bitfield.imm64 = 1; |
1689 | ||
1690 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1691 | { |
1692 | /* This code is disabled on the 486 because all the Imm1 forms | |
1693 | in the opcode table are slower on the i486. They're the | |
1694 | versions with the implicitly specified single-position | |
1695 | displacement, which has another syntax if you really want to | |
1696 | use that form. */ | |
40fb9820 L |
1697 | t.bitfield.imm1 = 1; |
1698 | t.bitfield.imm8 = 1; | |
1699 | t.bitfield.imm8s = 1; | |
1700 | t.bitfield.imm16 = 1; | |
1701 | t.bitfield.imm32 = 1; | |
1702 | t.bitfield.imm32s = 1; | |
1703 | } | |
1704 | else if (fits_in_signed_byte (num)) | |
1705 | { | |
1706 | t.bitfield.imm8 = 1; | |
1707 | t.bitfield.imm8s = 1; | |
1708 | t.bitfield.imm16 = 1; | |
1709 | t.bitfield.imm32 = 1; | |
1710 | t.bitfield.imm32s = 1; | |
1711 | } | |
1712 | else if (fits_in_unsigned_byte (num)) | |
1713 | { | |
1714 | t.bitfield.imm8 = 1; | |
1715 | t.bitfield.imm16 = 1; | |
1716 | t.bitfield.imm32 = 1; | |
1717 | t.bitfield.imm32s = 1; | |
1718 | } | |
1719 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1720 | { | |
1721 | t.bitfield.imm16 = 1; | |
1722 | t.bitfield.imm32 = 1; | |
1723 | t.bitfield.imm32s = 1; | |
1724 | } | |
1725 | else if (fits_in_signed_long (num)) | |
1726 | { | |
1727 | t.bitfield.imm32 = 1; | |
1728 | t.bitfield.imm32s = 1; | |
1729 | } | |
1730 | else if (fits_in_unsigned_long (num)) | |
1731 | t.bitfield.imm32 = 1; | |
1732 | ||
1733 | return t; | |
47926f60 | 1734 | } |
252b5132 | 1735 | |
847f7ad4 | 1736 | static offsetT |
e3bb37b5 | 1737 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1738 | { |
508866be | 1739 | addressT mask; |
ba2adb93 | 1740 | |
847f7ad4 AM |
1741 | switch (size) |
1742 | { | |
508866be L |
1743 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1744 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1745 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1746 | #ifdef BFD64 |
1747 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1748 | #endif | |
47926f60 | 1749 | default: abort (); |
847f7ad4 AM |
1750 | } |
1751 | ||
ba2adb93 | 1752 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
1753 | if (!use_rela_relocations) |
1754 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
1755 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 1756 | |
47926f60 | 1757 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1758 | { |
1759 | char buf1[40], buf2[40]; | |
1760 | ||
1761 | sprint_value (buf1, val); | |
1762 | sprint_value (buf2, val & mask); | |
1763 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1764 | } | |
1765 | return val & mask; | |
1766 | } | |
1767 | ||
252b5132 RH |
1768 | /* Returns 0 if attempting to add a prefix where one from the same |
1769 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
1770 | added. */ | |
1771 | static int | |
e3bb37b5 | 1772 | add_prefix (unsigned int prefix) |
252b5132 RH |
1773 | { |
1774 | int ret = 1; | |
b1905489 | 1775 | unsigned int q; |
252b5132 | 1776 | |
29b0f896 AM |
1777 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1778 | && flag_code == CODE_64BIT) | |
b1905489 | 1779 | { |
161a04f6 L |
1780 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1781 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1782 | && (prefix & (REX_R | REX_X | REX_B)))) | |
b1905489 JB |
1783 | ret = 0; |
1784 | q = REX_PREFIX; | |
1785 | } | |
3e73aa7c | 1786 | else |
b1905489 JB |
1787 | { |
1788 | switch (prefix) | |
1789 | { | |
1790 | default: | |
1791 | abort (); | |
1792 | ||
1793 | case CS_PREFIX_OPCODE: | |
1794 | case DS_PREFIX_OPCODE: | |
1795 | case ES_PREFIX_OPCODE: | |
1796 | case FS_PREFIX_OPCODE: | |
1797 | case GS_PREFIX_OPCODE: | |
1798 | case SS_PREFIX_OPCODE: | |
1799 | q = SEG_PREFIX; | |
1800 | break; | |
1801 | ||
1802 | case REPNE_PREFIX_OPCODE: | |
1803 | case REPE_PREFIX_OPCODE: | |
1804 | ret = 2; | |
1805 | /* fall thru */ | |
1806 | case LOCK_PREFIX_OPCODE: | |
1807 | q = LOCKREP_PREFIX; | |
1808 | break; | |
1809 | ||
1810 | case FWAIT_OPCODE: | |
1811 | q = WAIT_PREFIX; | |
1812 | break; | |
1813 | ||
1814 | case ADDR_PREFIX_OPCODE: | |
1815 | q = ADDR_PREFIX; | |
1816 | break; | |
1817 | ||
1818 | case DATA_PREFIX_OPCODE: | |
1819 | q = DATA_PREFIX; | |
1820 | break; | |
1821 | } | |
1822 | if (i.prefix[q] != 0) | |
1823 | ret = 0; | |
1824 | } | |
252b5132 | 1825 | |
b1905489 | 1826 | if (ret) |
252b5132 | 1827 | { |
b1905489 JB |
1828 | if (!i.prefix[q]) |
1829 | ++i.prefixes; | |
1830 | i.prefix[q] |= prefix; | |
252b5132 | 1831 | } |
b1905489 JB |
1832 | else |
1833 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1834 | |
252b5132 RH |
1835 | return ret; |
1836 | } | |
1837 | ||
1838 | static void | |
e3bb37b5 | 1839 | set_code_flag (int value) |
eecb386c | 1840 | { |
3e73aa7c | 1841 | flag_code = value; |
40fb9820 L |
1842 | if (flag_code == CODE_64BIT) |
1843 | { | |
1844 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1845 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
1846 | } |
1847 | else | |
1848 | { | |
1849 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1850 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
1851 | } |
1852 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c JH |
1853 | { |
1854 | as_bad (_("64bit mode not supported on this CPU.")); | |
1855 | } | |
40fb9820 | 1856 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c JH |
1857 | { |
1858 | as_bad (_("32bit mode not supported on this CPU.")); | |
1859 | } | |
eecb386c AM |
1860 | stackop_size = '\0'; |
1861 | } | |
1862 | ||
1863 | static void | |
e3bb37b5 | 1864 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1865 | { |
3e73aa7c | 1866 | flag_code = new_code_flag; |
40fb9820 L |
1867 | if (flag_code != CODE_16BIT) |
1868 | abort (); | |
1869 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1870 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 1871 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1872 | } |
1873 | ||
1874 | static void | |
e3bb37b5 | 1875 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1876 | { |
1877 | /* Find out if register prefixing is specified. */ | |
1878 | int ask_naked_reg = 0; | |
1879 | ||
1880 | SKIP_WHITESPACE (); | |
29b0f896 | 1881 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1882 | { |
1883 | char *string = input_line_pointer; | |
1884 | int e = get_symbol_end (); | |
1885 | ||
47926f60 | 1886 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1887 | ask_naked_reg = 1; |
47926f60 | 1888 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1889 | ask_naked_reg = -1; |
1890 | else | |
d0b47220 | 1891 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1892 | *input_line_pointer = e; |
1893 | } | |
1894 | demand_empty_rest_of_line (); | |
c3332e24 | 1895 | |
252b5132 RH |
1896 | intel_syntax = syntax_flag; |
1897 | ||
1898 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1899 | allow_naked_reg = (intel_syntax |
1900 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1901 | else |
1902 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1903 | |
ee86248c JB |
1904 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
1905 | ||
e4a3b5a4 | 1906 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1907 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1908 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1909 | } |
1910 | ||
1efbbeb4 L |
1911 | static void |
1912 | set_intel_mnemonic (int mnemonic_flag) | |
1913 | { | |
e1d4d893 | 1914 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
1915 | } |
1916 | ||
db51cc60 L |
1917 | static void |
1918 | set_allow_index_reg (int flag) | |
1919 | { | |
1920 | allow_index_reg = flag; | |
1921 | } | |
1922 | ||
cb19c032 L |
1923 | static void |
1924 | set_sse_check (int dummy ATTRIBUTE_UNUSED) | |
1925 | { | |
1926 | SKIP_WHITESPACE (); | |
1927 | ||
1928 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
1929 | { | |
1930 | char *string = input_line_pointer; | |
1931 | int e = get_symbol_end (); | |
1932 | ||
1933 | if (strcmp (string, "none") == 0) | |
1934 | sse_check = sse_check_none; | |
1935 | else if (strcmp (string, "warning") == 0) | |
1936 | sse_check = sse_check_warning; | |
1937 | else if (strcmp (string, "error") == 0) | |
1938 | sse_check = sse_check_error; | |
1939 | else | |
1940 | as_bad (_("bad argument to sse_check directive.")); | |
1941 | *input_line_pointer = e; | |
1942 | } | |
1943 | else | |
1944 | as_bad (_("missing argument for sse_check directive")); | |
1945 | ||
1946 | demand_empty_rest_of_line (); | |
1947 | } | |
1948 | ||
e413e4e9 | 1949 | static void |
e3bb37b5 | 1950 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1951 | { |
47926f60 | 1952 | SKIP_WHITESPACE (); |
e413e4e9 | 1953 | |
29b0f896 | 1954 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1955 | { |
1956 | char *string = input_line_pointer; | |
1957 | int e = get_symbol_end (); | |
9103f4f4 | 1958 | unsigned int i; |
40fb9820 | 1959 | i386_cpu_flags flags; |
e413e4e9 | 1960 | |
9103f4f4 | 1961 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
1962 | { |
1963 | if (strcmp (string, cpu_arch[i].name) == 0) | |
1964 | { | |
5c6af06e JB |
1965 | if (*string != '.') |
1966 | { | |
1967 | cpu_arch_name = cpu_arch[i].name; | |
1968 | cpu_sub_arch_name = NULL; | |
40fb9820 L |
1969 | cpu_arch_flags = cpu_arch[i].flags; |
1970 | if (flag_code == CODE_64BIT) | |
1971 | { | |
1972 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1973 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
1974 | } | |
1975 | else | |
1976 | { | |
1977 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1978 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1979 | } | |
ccc9c027 | 1980 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 1981 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
1982 | if (!cpu_arch_tune_set) |
1983 | { | |
1984 | cpu_arch_tune = cpu_arch_isa; | |
1985 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
1986 | } | |
5c6af06e JB |
1987 | break; |
1988 | } | |
40fb9820 | 1989 | |
c6fb90c8 L |
1990 | flags = cpu_flags_or (cpu_arch_flags, |
1991 | cpu_arch[i].flags); | |
0dfbf9d7 | 1992 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 1993 | { |
6305a203 L |
1994 | if (cpu_sub_arch_name) |
1995 | { | |
1996 | char *name = cpu_sub_arch_name; | |
1997 | cpu_sub_arch_name = concat (name, | |
1998 | cpu_arch[i].name, | |
1bf57e9f | 1999 | (const char *) NULL); |
6305a203 L |
2000 | free (name); |
2001 | } | |
2002 | else | |
2003 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
40fb9820 | 2004 | cpu_arch_flags = flags; |
5c6af06e JB |
2005 | } |
2006 | *input_line_pointer = e; | |
2007 | demand_empty_rest_of_line (); | |
2008 | return; | |
e413e4e9 AM |
2009 | } |
2010 | } | |
9103f4f4 | 2011 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2012 | as_bad (_("no such architecture: `%s'"), string); |
2013 | ||
2014 | *input_line_pointer = e; | |
2015 | } | |
2016 | else | |
2017 | as_bad (_("missing cpu architecture")); | |
2018 | ||
fddf5b5b AM |
2019 | no_cond_jump_promotion = 0; |
2020 | if (*input_line_pointer == ',' | |
29b0f896 | 2021 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
2022 | { |
2023 | char *string = ++input_line_pointer; | |
2024 | int e = get_symbol_end (); | |
2025 | ||
2026 | if (strcmp (string, "nojumps") == 0) | |
2027 | no_cond_jump_promotion = 1; | |
2028 | else if (strcmp (string, "jumps") == 0) | |
2029 | ; | |
2030 | else | |
2031 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2032 | ||
2033 | *input_line_pointer = e; | |
2034 | } | |
2035 | ||
e413e4e9 AM |
2036 | demand_empty_rest_of_line (); |
2037 | } | |
2038 | ||
b9d79e03 JH |
2039 | unsigned long |
2040 | i386_mach () | |
2041 | { | |
2042 | if (!strcmp (default_arch, "x86_64")) | |
2043 | return bfd_mach_x86_64; | |
2044 | else if (!strcmp (default_arch, "i386")) | |
2045 | return bfd_mach_i386_i386; | |
2046 | else | |
2047 | as_fatal (_("Unknown architecture")); | |
2048 | } | |
b9d79e03 | 2049 | \f |
252b5132 RH |
2050 | void |
2051 | md_begin () | |
2052 | { | |
2053 | const char *hash_err; | |
2054 | ||
47926f60 | 2055 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2056 | op_hash = hash_new (); |
2057 | ||
2058 | { | |
29b0f896 AM |
2059 | const template *optab; |
2060 | templates *core_optab; | |
252b5132 | 2061 | |
47926f60 KH |
2062 | /* Setup for loop. */ |
2063 | optab = i386_optab; | |
252b5132 RH |
2064 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2065 | core_optab->start = optab; | |
2066 | ||
2067 | while (1) | |
2068 | { | |
2069 | ++optab; | |
2070 | if (optab->name == NULL | |
2071 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2072 | { | |
2073 | /* different name --> ship out current template list; | |
47926f60 | 2074 | add to hash table; & begin anew. */ |
252b5132 RH |
2075 | core_optab->end = optab; |
2076 | hash_err = hash_insert (op_hash, | |
2077 | (optab - 1)->name, | |
5a49b8ac | 2078 | (void *) core_optab); |
252b5132 RH |
2079 | if (hash_err) |
2080 | { | |
252b5132 RH |
2081 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2082 | (optab - 1)->name, | |
2083 | hash_err); | |
2084 | } | |
2085 | if (optab->name == NULL) | |
2086 | break; | |
2087 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2088 | core_optab->start = optab; | |
2089 | } | |
2090 | } | |
2091 | } | |
2092 | ||
47926f60 | 2093 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2094 | reg_hash = hash_new (); |
2095 | { | |
29b0f896 | 2096 | const reg_entry *regtab; |
c3fe08fa | 2097 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2098 | |
c3fe08fa | 2099 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2100 | { |
5a49b8ac | 2101 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2102 | if (hash_err) |
3e73aa7c JH |
2103 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2104 | regtab->reg_name, | |
2105 | hash_err); | |
252b5132 RH |
2106 | } |
2107 | } | |
2108 | ||
47926f60 | 2109 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2110 | { |
29b0f896 AM |
2111 | int c; |
2112 | char *p; | |
252b5132 RH |
2113 | |
2114 | for (c = 0; c < 256; c++) | |
2115 | { | |
3882b010 | 2116 | if (ISDIGIT (c)) |
252b5132 RH |
2117 | { |
2118 | digit_chars[c] = c; | |
2119 | mnemonic_chars[c] = c; | |
2120 | register_chars[c] = c; | |
2121 | operand_chars[c] = c; | |
2122 | } | |
3882b010 | 2123 | else if (ISLOWER (c)) |
252b5132 RH |
2124 | { |
2125 | mnemonic_chars[c] = c; | |
2126 | register_chars[c] = c; | |
2127 | operand_chars[c] = c; | |
2128 | } | |
3882b010 | 2129 | else if (ISUPPER (c)) |
252b5132 | 2130 | { |
3882b010 | 2131 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2132 | register_chars[c] = mnemonic_chars[c]; |
2133 | operand_chars[c] = c; | |
2134 | } | |
2135 | ||
3882b010 | 2136 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2137 | identifier_chars[c] = c; |
2138 | else if (c >= 128) | |
2139 | { | |
2140 | identifier_chars[c] = c; | |
2141 | operand_chars[c] = c; | |
2142 | } | |
2143 | } | |
2144 | ||
2145 | #ifdef LEX_AT | |
2146 | identifier_chars['@'] = '@'; | |
32137342 NC |
2147 | #endif |
2148 | #ifdef LEX_QM | |
2149 | identifier_chars['?'] = '?'; | |
2150 | operand_chars['?'] = '?'; | |
252b5132 | 2151 | #endif |
252b5132 | 2152 | digit_chars['-'] = '-'; |
c0f3af97 | 2153 | mnemonic_chars['_'] = '_'; |
791fe849 | 2154 | mnemonic_chars['-'] = '-'; |
0003779b | 2155 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2156 | identifier_chars['_'] = '_'; |
2157 | identifier_chars['.'] = '.'; | |
2158 | ||
2159 | for (p = operand_special_chars; *p != '\0'; p++) | |
2160 | operand_chars[(unsigned char) *p] = *p; | |
2161 | } | |
2162 | ||
2163 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2164 | if (IS_ELF) |
252b5132 RH |
2165 | { |
2166 | record_alignment (text_section, 2); | |
2167 | record_alignment (data_section, 2); | |
2168 | record_alignment (bss_section, 2); | |
2169 | } | |
2170 | #endif | |
a4447b93 RH |
2171 | |
2172 | if (flag_code == CODE_64BIT) | |
2173 | { | |
2174 | x86_dwarf2_return_column = 16; | |
2175 | x86_cie_data_alignment = -8; | |
2176 | } | |
2177 | else | |
2178 | { | |
2179 | x86_dwarf2_return_column = 8; | |
2180 | x86_cie_data_alignment = -4; | |
2181 | } | |
252b5132 RH |
2182 | } |
2183 | ||
2184 | void | |
e3bb37b5 | 2185 | i386_print_statistics (FILE *file) |
252b5132 RH |
2186 | { |
2187 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2188 | hash_print_statistics (file, "i386 register", reg_hash); | |
2189 | } | |
2190 | \f | |
252b5132 RH |
2191 | #ifdef DEBUG386 |
2192 | ||
ce8a8b2f | 2193 | /* Debugging routines for md_assemble. */ |
e3bb37b5 | 2194 | static void pte (template *); |
40fb9820 | 2195 | static void pt (i386_operand_type); |
e3bb37b5 L |
2196 | static void pe (expressionS *); |
2197 | static void ps (symbolS *); | |
252b5132 RH |
2198 | |
2199 | static void | |
e3bb37b5 | 2200 | pi (char *line, i386_insn *x) |
252b5132 | 2201 | { |
09f131f2 | 2202 | unsigned int i; |
252b5132 RH |
2203 | |
2204 | fprintf (stdout, "%s: template ", line); | |
2205 | pte (&x->tm); | |
09f131f2 JH |
2206 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2207 | x->base_reg ? x->base_reg->reg_name : "none", | |
2208 | x->index_reg ? x->index_reg->reg_name : "none", | |
2209 | x->log2_scale_factor); | |
2210 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2211 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2212 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2213 | x->sib.base, x->sib.index, x->sib.scale); | |
2214 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2215 | (x->rex & REX_W) != 0, |
2216 | (x->rex & REX_R) != 0, | |
2217 | (x->rex & REX_X) != 0, | |
2218 | (x->rex & REX_B) != 0); | |
85f10a01 MM |
2219 | fprintf (stdout, " drex: reg %d rex 0x%x\n", |
2220 | x->drex.reg, x->drex.rex); | |
252b5132 RH |
2221 | for (i = 0; i < x->operands; i++) |
2222 | { | |
2223 | fprintf (stdout, " #%d: ", i + 1); | |
2224 | pt (x->types[i]); | |
2225 | fprintf (stdout, "\n"); | |
40fb9820 L |
2226 | if (x->types[i].bitfield.reg8 |
2227 | || x->types[i].bitfield.reg16 | |
2228 | || x->types[i].bitfield.reg32 | |
2229 | || x->types[i].bitfield.reg64 | |
2230 | || x->types[i].bitfield.regmmx | |
2231 | || x->types[i].bitfield.regxmm | |
c0f3af97 | 2232 | || x->types[i].bitfield.regymm |
40fb9820 L |
2233 | || x->types[i].bitfield.sreg2 |
2234 | || x->types[i].bitfield.sreg3 | |
2235 | || x->types[i].bitfield.control | |
2236 | || x->types[i].bitfield.debug | |
2237 | || x->types[i].bitfield.test) | |
520dc8e8 | 2238 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
40fb9820 | 2239 | if (operand_type_check (x->types[i], imm)) |
520dc8e8 | 2240 | pe (x->op[i].imms); |
40fb9820 | 2241 | if (operand_type_check (x->types[i], disp)) |
520dc8e8 | 2242 | pe (x->op[i].disps); |
252b5132 RH |
2243 | } |
2244 | } | |
2245 | ||
2246 | static void | |
e3bb37b5 | 2247 | pte (template *t) |
252b5132 | 2248 | { |
09f131f2 | 2249 | unsigned int i; |
252b5132 | 2250 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2251 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2252 | if (t->extension_opcode != None) |
2253 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2254 | if (t->opcode_modifier.d) |
252b5132 | 2255 | fprintf (stdout, "D"); |
40fb9820 | 2256 | if (t->opcode_modifier.w) |
252b5132 RH |
2257 | fprintf (stdout, "W"); |
2258 | fprintf (stdout, "\n"); | |
2259 | for (i = 0; i < t->operands; i++) | |
2260 | { | |
2261 | fprintf (stdout, " #%d type ", i + 1); | |
2262 | pt (t->operand_types[i]); | |
2263 | fprintf (stdout, "\n"); | |
2264 | } | |
2265 | } | |
2266 | ||
2267 | static void | |
e3bb37b5 | 2268 | pe (expressionS *e) |
252b5132 | 2269 | { |
24eab124 | 2270 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2271 | fprintf (stdout, " add_number %ld (%lx)\n", |
2272 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2273 | if (e->X_add_symbol) |
2274 | { | |
2275 | fprintf (stdout, " add_symbol "); | |
2276 | ps (e->X_add_symbol); | |
2277 | fprintf (stdout, "\n"); | |
2278 | } | |
2279 | if (e->X_op_symbol) | |
2280 | { | |
2281 | fprintf (stdout, " op_symbol "); | |
2282 | ps (e->X_op_symbol); | |
2283 | fprintf (stdout, "\n"); | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | static void | |
e3bb37b5 | 2288 | ps (symbolS *s) |
252b5132 RH |
2289 | { |
2290 | fprintf (stdout, "%s type %s%s", | |
2291 | S_GET_NAME (s), | |
2292 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2293 | segment_name (S_GET_SEGMENT (s))); | |
2294 | } | |
2295 | ||
7b81dfbb | 2296 | static struct type_name |
252b5132 | 2297 | { |
40fb9820 L |
2298 | i386_operand_type mask; |
2299 | const char *name; | |
252b5132 | 2300 | } |
7b81dfbb | 2301 | const type_names[] = |
252b5132 | 2302 | { |
40fb9820 L |
2303 | { OPERAND_TYPE_REG8, "r8" }, |
2304 | { OPERAND_TYPE_REG16, "r16" }, | |
2305 | { OPERAND_TYPE_REG32, "r32" }, | |
2306 | { OPERAND_TYPE_REG64, "r64" }, | |
2307 | { OPERAND_TYPE_IMM8, "i8" }, | |
2308 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2309 | { OPERAND_TYPE_IMM16, "i16" }, | |
2310 | { OPERAND_TYPE_IMM32, "i32" }, | |
2311 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2312 | { OPERAND_TYPE_IMM64, "i64" }, | |
2313 | { OPERAND_TYPE_IMM1, "i1" }, | |
2314 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2315 | { OPERAND_TYPE_DISP8, "d8" }, | |
2316 | { OPERAND_TYPE_DISP16, "d16" }, | |
2317 | { OPERAND_TYPE_DISP32, "d32" }, | |
2318 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2319 | { OPERAND_TYPE_DISP64, "d64" }, | |
2320 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2321 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2322 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2323 | { OPERAND_TYPE_TEST, "test reg" }, | |
2324 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2325 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2326 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2327 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2328 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2329 | { OPERAND_TYPE_ACC, "Acc" }, | |
2330 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2331 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2332 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2333 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
40fb9820 | 2334 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2335 | }; |
2336 | ||
2337 | static void | |
40fb9820 | 2338 | pt (i386_operand_type t) |
252b5132 | 2339 | { |
40fb9820 | 2340 | unsigned int j; |
c6fb90c8 | 2341 | i386_operand_type a; |
252b5132 | 2342 | |
40fb9820 | 2343 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2344 | { |
2345 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2346 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2347 | fprintf (stdout, "%s, ", type_names[j].name); |
2348 | } | |
252b5132 RH |
2349 | fflush (stdout); |
2350 | } | |
2351 | ||
2352 | #endif /* DEBUG386 */ | |
2353 | \f | |
252b5132 | 2354 | static bfd_reloc_code_real_type |
3956db08 | 2355 | reloc (unsigned int size, |
64e74474 AM |
2356 | int pcrel, |
2357 | int sign, | |
2358 | bfd_reloc_code_real_type other) | |
252b5132 | 2359 | { |
47926f60 | 2360 | if (other != NO_RELOC) |
3956db08 JB |
2361 | { |
2362 | reloc_howto_type *reloc; | |
2363 | ||
2364 | if (size == 8) | |
2365 | switch (other) | |
2366 | { | |
64e74474 AM |
2367 | case BFD_RELOC_X86_64_GOT32: |
2368 | return BFD_RELOC_X86_64_GOT64; | |
2369 | break; | |
2370 | case BFD_RELOC_X86_64_PLTOFF64: | |
2371 | return BFD_RELOC_X86_64_PLTOFF64; | |
2372 | break; | |
2373 | case BFD_RELOC_X86_64_GOTPC32: | |
2374 | other = BFD_RELOC_X86_64_GOTPC64; | |
2375 | break; | |
2376 | case BFD_RELOC_X86_64_GOTPCREL: | |
2377 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2378 | break; | |
2379 | case BFD_RELOC_X86_64_TPOFF32: | |
2380 | other = BFD_RELOC_X86_64_TPOFF64; | |
2381 | break; | |
2382 | case BFD_RELOC_X86_64_DTPOFF32: | |
2383 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2384 | break; | |
2385 | default: | |
2386 | break; | |
3956db08 | 2387 | } |
e05278af JB |
2388 | |
2389 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
2390 | if (size == 4 && flag_code != CODE_64BIT) | |
2391 | sign = -1; | |
2392 | ||
3956db08 JB |
2393 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
2394 | if (!reloc) | |
2395 | as_bad (_("unknown relocation (%u)"), other); | |
2396 | else if (size != bfd_get_reloc_size (reloc)) | |
2397 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
2398 | bfd_get_reloc_size (reloc), | |
2399 | size); | |
2400 | else if (pcrel && !reloc->pc_relative) | |
2401 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
2402 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
2403 | && !sign) | |
2404 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 2405 | && sign > 0)) |
3956db08 JB |
2406 | as_bad (_("relocated field and relocation type differ in signedness")); |
2407 | else | |
2408 | return other; | |
2409 | return NO_RELOC; | |
2410 | } | |
252b5132 RH |
2411 | |
2412 | if (pcrel) | |
2413 | { | |
3e73aa7c | 2414 | if (!sign) |
3956db08 | 2415 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2416 | switch (size) |
2417 | { | |
2418 | case 1: return BFD_RELOC_8_PCREL; | |
2419 | case 2: return BFD_RELOC_16_PCREL; | |
2420 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2421 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2422 | } |
3956db08 | 2423 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2424 | } |
2425 | else | |
2426 | { | |
3956db08 | 2427 | if (sign > 0) |
e5cb08ac | 2428 | switch (size) |
3e73aa7c JH |
2429 | { |
2430 | case 4: return BFD_RELOC_X86_64_32S; | |
2431 | } | |
2432 | else | |
2433 | switch (size) | |
2434 | { | |
2435 | case 1: return BFD_RELOC_8; | |
2436 | case 2: return BFD_RELOC_16; | |
2437 | case 4: return BFD_RELOC_32; | |
2438 | case 8: return BFD_RELOC_64; | |
2439 | } | |
3956db08 JB |
2440 | as_bad (_("cannot do %s %u byte relocation"), |
2441 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2442 | } |
2443 | ||
0cc9e1d3 | 2444 | return NO_RELOC; |
252b5132 RH |
2445 | } |
2446 | ||
47926f60 KH |
2447 | /* Here we decide which fixups can be adjusted to make them relative to |
2448 | the beginning of the section instead of the symbol. Basically we need | |
2449 | to make sure that the dynamic relocations are done correctly, so in | |
2450 | some cases we force the original symbol to be used. */ | |
2451 | ||
252b5132 | 2452 | int |
e3bb37b5 | 2453 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2454 | { |
6d249963 | 2455 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2456 | if (!IS_ELF) |
31312f95 AM |
2457 | return 1; |
2458 | ||
a161fe53 AM |
2459 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2460 | mode. */ | |
2461 | if (use_rela_relocations | |
2462 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2463 | && fixP->fx_pcrel) | |
252b5132 | 2464 | return 0; |
31312f95 | 2465 | |
8d01d9a9 AJ |
2466 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2467 | and changed later by validate_fix. */ | |
2468 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2469 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2470 | return 0; | |
2471 | ||
ce8a8b2f | 2472 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2473 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2474 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2475 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2476 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2477 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2478 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2479 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2480 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2481 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2482 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2483 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2484 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2485 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2486 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2487 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2488 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2489 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2490 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2491 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2492 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2493 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2494 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2495 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2496 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2497 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2498 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2499 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2500 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2501 | return 0; | |
d8045f23 NC |
2502 | |
2503 | if (fixP->fx_addsy != NULL | |
2504 | && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION) | |
2505 | return 0; | |
31312f95 | 2506 | #endif |
252b5132 RH |
2507 | return 1; |
2508 | } | |
252b5132 | 2509 | |
b4cac588 | 2510 | static int |
e3bb37b5 | 2511 | intel_float_operand (const char *mnemonic) |
252b5132 | 2512 | { |
9306ca4a JB |
2513 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2514 | operands, hence the code here is free to improperly handle opcodes that | |
2515 | have no operands (for better performance and smaller code). */ | |
2516 | ||
2517 | if (mnemonic[0] != 'f') | |
2518 | return 0; /* non-math */ | |
2519 | ||
2520 | switch (mnemonic[1]) | |
2521 | { | |
2522 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2523 | the fs segment override prefix not currently handled because no | |
2524 | call path can make opcodes without operands get here */ | |
2525 | case 'i': | |
2526 | return 2 /* integer op */; | |
2527 | case 'l': | |
2528 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2529 | return 3; /* fldcw/fldenv */ | |
2530 | break; | |
2531 | case 'n': | |
2532 | if (mnemonic[2] != 'o' /* fnop */) | |
2533 | return 3; /* non-waiting control op */ | |
2534 | break; | |
2535 | case 'r': | |
2536 | if (mnemonic[2] == 's') | |
2537 | return 3; /* frstor/frstpm */ | |
2538 | break; | |
2539 | case 's': | |
2540 | if (mnemonic[2] == 'a') | |
2541 | return 3; /* fsave */ | |
2542 | if (mnemonic[2] == 't') | |
2543 | { | |
2544 | switch (mnemonic[3]) | |
2545 | { | |
2546 | case 'c': /* fstcw */ | |
2547 | case 'd': /* fstdw */ | |
2548 | case 'e': /* fstenv */ | |
2549 | case 's': /* fsts[gw] */ | |
2550 | return 3; | |
2551 | } | |
2552 | } | |
2553 | break; | |
2554 | case 'x': | |
2555 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2556 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2557 | break; | |
2558 | } | |
252b5132 | 2559 | |
9306ca4a | 2560 | return 1; |
252b5132 RH |
2561 | } |
2562 | ||
c0f3af97 L |
2563 | /* Build the VEX prefix. */ |
2564 | ||
2565 | static void | |
fa99fab2 | 2566 | build_vex_prefix (const template *t) |
c0f3af97 L |
2567 | { |
2568 | unsigned int register_specifier; | |
2569 | unsigned int implied_prefix; | |
2570 | unsigned int vector_length; | |
2571 | ||
2572 | /* Check register specifier. */ | |
2573 | if (i.vex.register_specifier) | |
2574 | { | |
2575 | register_specifier = i.vex.register_specifier->reg_num; | |
2576 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
2577 | register_specifier += 8; | |
2578 | register_specifier = ~register_specifier & 0xf; | |
2579 | } | |
2580 | else | |
2581 | register_specifier = 0xf; | |
2582 | ||
fa99fab2 L |
2583 | /* Use 2-byte VEX prefix by swappping destination and source |
2584 | operand. */ | |
2585 | if (!i.swap_operand | |
2586 | && i.operands == i.reg_operands | |
2587 | && i.tm.opcode_modifier.vex0f | |
2588 | && i.tm.opcode_modifier.s | |
2589 | && i.rex == REX_B) | |
2590 | { | |
2591 | unsigned int xchg = i.operands - 1; | |
2592 | union i386_op temp_op; | |
2593 | i386_operand_type temp_type; | |
2594 | ||
2595 | temp_type = i.types[xchg]; | |
2596 | i.types[xchg] = i.types[0]; | |
2597 | i.types[0] = temp_type; | |
2598 | temp_op = i.op[xchg]; | |
2599 | i.op[xchg] = i.op[0]; | |
2600 | i.op[0] = temp_op; | |
2601 | ||
2602 | assert (i.rm.mode == 3); | |
2603 | ||
2604 | i.rex = REX_R; | |
2605 | xchg = i.rm.regmem; | |
2606 | i.rm.regmem = i.rm.reg; | |
2607 | i.rm.reg = xchg; | |
2608 | ||
2609 | /* Use the next insn. */ | |
2610 | i.tm = t[1]; | |
2611 | } | |
2612 | ||
c0f3af97 L |
2613 | vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0; |
2614 | ||
2615 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2616 | { | |
2617 | case 0: | |
2618 | implied_prefix = 0; | |
2619 | break; | |
2620 | case DATA_PREFIX_OPCODE: | |
2621 | implied_prefix = 1; | |
2622 | break; | |
2623 | case REPE_PREFIX_OPCODE: | |
2624 | implied_prefix = 2; | |
2625 | break; | |
2626 | case REPNE_PREFIX_OPCODE: | |
2627 | implied_prefix = 3; | |
2628 | break; | |
2629 | default: | |
2630 | abort (); | |
2631 | } | |
2632 | ||
2633 | /* Use 2-byte VEX prefix if possible. */ | |
2634 | if (i.tm.opcode_modifier.vex0f | |
2635 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) | |
2636 | { | |
2637 | /* 2-byte VEX prefix. */ | |
2638 | unsigned int r; | |
2639 | ||
2640 | i.vex.length = 2; | |
2641 | i.vex.bytes[0] = 0xc5; | |
2642 | ||
2643 | /* Check the REX.R bit. */ | |
2644 | r = (i.rex & REX_R) ? 0 : 1; | |
2645 | i.vex.bytes[1] = (r << 7 | |
2646 | | register_specifier << 3 | |
2647 | | vector_length << 2 | |
2648 | | implied_prefix); | |
2649 | } | |
2650 | else | |
2651 | { | |
2652 | /* 3-byte VEX prefix. */ | |
2653 | unsigned int m, w; | |
2654 | ||
2655 | if (i.tm.opcode_modifier.vex0f) | |
2656 | m = 0x1; | |
2657 | else if (i.tm.opcode_modifier.vex0f38) | |
2658 | m = 0x2; | |
2659 | else if (i.tm.opcode_modifier.vex0f3a) | |
2660 | m = 0x3; | |
2661 | else | |
2662 | abort (); | |
2663 | ||
2664 | i.vex.length = 3; | |
2665 | i.vex.bytes[0] = 0xc4; | |
2666 | ||
2667 | /* The high 3 bits of the second VEX byte are 1's compliment | |
2668 | of RXB bits from REX. */ | |
2669 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2670 | ||
2671 | /* Check the REX.W bit. */ | |
2672 | w = (i.rex & REX_W) ? 1 : 0; | |
2673 | if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1) | |
2674 | { | |
2675 | if (w) | |
2676 | abort (); | |
2677 | ||
2678 | if (i.tm.opcode_modifier.vexw1) | |
2679 | w = 1; | |
2680 | } | |
2681 | ||
2682 | i.vex.bytes[2] = (w << 7 | |
2683 | | register_specifier << 3 | |
2684 | | vector_length << 2 | |
2685 | | implied_prefix); | |
2686 | } | |
2687 | } | |
2688 | ||
65da13b5 L |
2689 | static void |
2690 | process_immext (void) | |
2691 | { | |
2692 | expressionS *exp; | |
2693 | ||
2694 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) | |
2695 | { | |
1fed0ba1 L |
2696 | /* SSE3 Instructions have the fixed operands with an opcode |
2697 | suffix which is coded in the same place as an 8-bit immediate | |
2698 | field would be. Here we check those operands and remove them | |
2699 | afterwards. */ | |
65da13b5 L |
2700 | unsigned int x; |
2701 | ||
2702 | for (x = 0; x < i.operands; x++) | |
2703 | if (i.op[x].regs->reg_num != x) | |
2704 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
1fed0ba1 L |
2705 | register_prefix, i.op[x].regs->reg_name, x + 1, |
2706 | i.tm.name); | |
2707 | ||
2708 | i.operands = 0; | |
65da13b5 L |
2709 | } |
2710 | ||
c0f3af97 | 2711 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
2712 | which is coded in the same place as an 8-bit immediate field |
2713 | would be. Here we fake an 8-bit immediate operand from the | |
2714 | opcode suffix stored in tm.extension_opcode. | |
2715 | ||
c0f3af97 L |
2716 | SSE5 and AVX instructions also use this encoding, for some of |
2717 | 3 argument instructions. */ | |
65da13b5 L |
2718 | |
2719 | assert (i.imm_operands == 0 | |
2720 | && (i.operands <= 2 | |
2721 | || (i.tm.cpu_flags.bitfield.cpusse5 | |
c0f3af97 L |
2722 | && i.operands <= 3) |
2723 | || (i.tm.opcode_modifier.vex | |
2724 | && i.operands <= 4))); | |
65da13b5 L |
2725 | |
2726 | exp = &im_expressions[i.imm_operands++]; | |
2727 | i.op[i.operands].imms = exp; | |
2728 | i.types[i.operands] = imm8; | |
2729 | i.operands++; | |
2730 | exp->X_op = O_constant; | |
2731 | exp->X_add_number = i.tm.extension_opcode; | |
2732 | i.tm.extension_opcode = None; | |
2733 | } | |
2734 | ||
252b5132 RH |
2735 | /* This is the guts of the machine-dependent assembler. LINE points to a |
2736 | machine dependent instruction. This function is supposed to emit | |
2737 | the frags/bytes it assembles to. */ | |
2738 | ||
2739 | void | |
65da13b5 | 2740 | md_assemble (char *line) |
252b5132 | 2741 | { |
40fb9820 | 2742 | unsigned int j; |
252b5132 | 2743 | char mnemonic[MAX_MNEM_SIZE]; |
fa99fab2 | 2744 | const template *t; |
252b5132 | 2745 | |
47926f60 | 2746 | /* Initialize globals. */ |
252b5132 RH |
2747 | memset (&i, '\0', sizeof (i)); |
2748 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2749 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2750 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2751 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2752 | save_stack_p = save_stack; |
252b5132 RH |
2753 | |
2754 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2755 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2756 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2757 | |
29b0f896 AM |
2758 | line = parse_insn (line, mnemonic); |
2759 | if (line == NULL) | |
2760 | return; | |
252b5132 | 2761 | |
29b0f896 | 2762 | line = parse_operands (line, mnemonic); |
ee86248c | 2763 | this_operand = -1; |
29b0f896 AM |
2764 | if (line == NULL) |
2765 | return; | |
252b5132 | 2766 | |
29b0f896 AM |
2767 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2768 | operands at hand. */ | |
2769 | ||
2770 | /* All intel opcodes have reversed operands except for "bound" and | |
2771 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2772 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2773 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2774 | if (intel_syntax |
2775 | && i.operands > 1 | |
29b0f896 | 2776 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2777 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
2778 | && !(operand_type_check (i.types[0], imm) |
2779 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
2780 | swap_operands (); |
2781 | ||
ec56d5c0 JB |
2782 | /* The order of the immediates should be reversed |
2783 | for 2 immediates extrq and insertq instructions */ | |
2784 | if (i.imm_operands == 2 | |
2785 | && (strcmp (mnemonic, "extrq") == 0 | |
2786 | || strcmp (mnemonic, "insertq") == 0)) | |
2787 | swap_2_operands (0, 1); | |
2788 | ||
29b0f896 AM |
2789 | if (i.imm_operands) |
2790 | optimize_imm (); | |
2791 | ||
b300c311 L |
2792 | /* Don't optimize displacement for movabs since it only takes 64bit |
2793 | displacement. */ | |
2794 | if (i.disp_operands | |
2795 | && (flag_code != CODE_64BIT | |
2796 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
2797 | optimize_disp (); |
2798 | ||
2799 | /* Next, we find a template that matches the given insn, | |
2800 | making sure the overlap of the given operands types is consistent | |
2801 | with the template operand types. */ | |
252b5132 | 2802 | |
fa99fab2 | 2803 | if (!(t = match_template ())) |
29b0f896 | 2804 | return; |
252b5132 | 2805 | |
daf50ae7 | 2806 | if (sse_check != sse_check_none |
81f8a913 | 2807 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
2808 | && (i.tm.cpu_flags.bitfield.cpusse |
2809 | || i.tm.cpu_flags.bitfield.cpusse2 | |
2810 | || i.tm.cpu_flags.bitfield.cpusse3 | |
2811 | || i.tm.cpu_flags.bitfield.cpussse3 | |
2812 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
2813 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
2814 | { | |
2815 | (sse_check == sse_check_warning | |
2816 | ? as_warn | |
2817 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
2818 | } | |
2819 | ||
321fd21e L |
2820 | /* Zap movzx and movsx suffix. The suffix has been set from |
2821 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
2822 | or extracted from mnemonic in AT&T syntax. But we'll use | |
2823 | the destination register to choose the suffix for encoding. */ | |
2824 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 2825 | { |
321fd21e L |
2826 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
2827 | there is no suffix, the default will be byte extension. */ | |
2828 | if (i.reg_operands != 2 | |
2829 | && !i.suffix | |
2830 | && intel_syntax) | |
2831 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
2832 | ||
2833 | i.suffix = 0; | |
cd61ebfe | 2834 | } |
24eab124 | 2835 | |
40fb9820 | 2836 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
2837 | if (!add_prefix (FWAIT_OPCODE)) |
2838 | return; | |
252b5132 | 2839 | |
29b0f896 | 2840 | /* Check string instruction segment overrides. */ |
40fb9820 | 2841 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
2842 | { |
2843 | if (!check_string ()) | |
5dd0794d | 2844 | return; |
fc0763e6 | 2845 | i.disp_operands = 0; |
29b0f896 | 2846 | } |
5dd0794d | 2847 | |
29b0f896 AM |
2848 | if (!process_suffix ()) |
2849 | return; | |
e413e4e9 | 2850 | |
29b0f896 AM |
2851 | /* Make still unresolved immediate matches conform to size of immediate |
2852 | given in i.suffix. */ | |
2853 | if (!finalize_imm ()) | |
2854 | return; | |
252b5132 | 2855 | |
40fb9820 | 2856 | if (i.types[0].bitfield.imm1) |
29b0f896 | 2857 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 2858 | |
40fb9820 | 2859 | for (j = 0; j < 3; j++) |
c6fb90c8 L |
2860 | if (i.types[j].bitfield.inoutportreg |
2861 | || i.types[j].bitfield.shiftcount | |
2862 | || i.types[j].bitfield.acc | |
2863 | || i.types[j].bitfield.floatacc) | |
40fb9820 L |
2864 | i.reg_operands--; |
2865 | ||
c0f3af97 L |
2866 | /* ImmExt should be processed after SSE2AVX. */ |
2867 | if (!i.tm.opcode_modifier.sse2avx | |
2868 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 2869 | process_immext (); |
252b5132 | 2870 | |
29b0f896 AM |
2871 | /* For insns with operands there are more diddles to do to the opcode. */ |
2872 | if (i.operands) | |
2873 | { | |
2874 | if (!process_operands ()) | |
2875 | return; | |
2876 | } | |
40fb9820 | 2877 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
2878 | { |
2879 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
2880 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2881 | } | |
252b5132 | 2882 | |
c0f3af97 | 2883 | if (i.tm.opcode_modifier.vex) |
fa99fab2 | 2884 | build_vex_prefix (t); |
c0f3af97 | 2885 | |
29b0f896 AM |
2886 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
2887 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
2888 | { | |
2889 | i.tm.base_opcode = INT3_OPCODE; | |
2890 | i.imm_operands = 0; | |
2891 | } | |
252b5132 | 2892 | |
40fb9820 L |
2893 | if ((i.tm.opcode_modifier.jump |
2894 | || i.tm.opcode_modifier.jumpbyte | |
2895 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
2896 | && i.op[0].disps->X_op == O_constant) |
2897 | { | |
2898 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2899 | the absolute address given by the constant. Since ix86 jumps and | |
2900 | calls are pc relative, we need to generate a reloc. */ | |
2901 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
2902 | i.op[0].disps->X_op = O_symbol; | |
2903 | } | |
252b5132 | 2904 | |
40fb9820 | 2905 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 2906 | i.rex |= REX_W; |
252b5132 | 2907 | |
29b0f896 AM |
2908 | /* For 8 bit registers we need an empty rex prefix. Also if the |
2909 | instruction already has a prefix, we need to convert old | |
2910 | registers to new ones. */ | |
773f551c | 2911 | |
40fb9820 | 2912 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 2913 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 2914 | || (i.types[1].bitfield.reg8 |
29b0f896 | 2915 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
2916 | || ((i.types[0].bitfield.reg8 |
2917 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
2918 | && i.rex != 0)) |
2919 | { | |
2920 | int x; | |
726c5dcd | 2921 | |
29b0f896 AM |
2922 | i.rex |= REX_OPCODE; |
2923 | for (x = 0; x < 2; x++) | |
2924 | { | |
2925 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 2926 | if (i.types[x].bitfield.reg8 |
29b0f896 | 2927 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 2928 | { |
29b0f896 AM |
2929 | /* In case it is "hi" register, give up. */ |
2930 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 2931 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 2932 | "instruction requiring REX prefix."), |
a540244d | 2933 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 2934 | |
29b0f896 AM |
2935 | /* Otherwise it is equivalent to the extended register. |
2936 | Since the encoding doesn't change this is merely | |
2937 | cosmetic cleanup for debug output. */ | |
2938 | ||
2939 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 2940 | } |
29b0f896 AM |
2941 | } |
2942 | } | |
773f551c | 2943 | |
85f10a01 MM |
2944 | /* If the instruction has the DREX attribute (aka SSE5), don't emit a |
2945 | REX prefix. */ | |
2946 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
2947 | { | |
2948 | i.drex.rex = i.rex; | |
2949 | i.rex = 0; | |
2950 | } | |
2951 | else if (i.rex != 0) | |
29b0f896 AM |
2952 | add_prefix (REX_OPCODE | i.rex); |
2953 | ||
2954 | /* We are ready to output the insn. */ | |
2955 | output_insn (); | |
2956 | } | |
2957 | ||
2958 | static char * | |
e3bb37b5 | 2959 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
2960 | { |
2961 | char *l = line; | |
2962 | char *token_start = l; | |
2963 | char *mnem_p; | |
5c6af06e JB |
2964 | int supported; |
2965 | const template *t; | |
b6169b20 | 2966 | char *dot_p = NULL; |
29b0f896 AM |
2967 | |
2968 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
2969 | const char *expecting_string_instruction = NULL; | |
45288df1 | 2970 | |
29b0f896 AM |
2971 | while (1) |
2972 | { | |
2973 | mnem_p = mnemonic; | |
2974 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
2975 | { | |
b6169b20 L |
2976 | if (*mnem_p == '.') |
2977 | dot_p = mnem_p; | |
29b0f896 AM |
2978 | mnem_p++; |
2979 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 2980 | { |
29b0f896 AM |
2981 | as_bad (_("no such instruction: `%s'"), token_start); |
2982 | return NULL; | |
2983 | } | |
2984 | l++; | |
2985 | } | |
2986 | if (!is_space_char (*l) | |
2987 | && *l != END_OF_INSN | |
e44823cf JB |
2988 | && (intel_syntax |
2989 | || (*l != PREFIX_SEPARATOR | |
2990 | && *l != ','))) | |
29b0f896 AM |
2991 | { |
2992 | as_bad (_("invalid character %s in mnemonic"), | |
2993 | output_invalid (*l)); | |
2994 | return NULL; | |
2995 | } | |
2996 | if (token_start == l) | |
2997 | { | |
e44823cf | 2998 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
2999 | as_bad (_("expecting prefix; got nothing")); |
3000 | else | |
3001 | as_bad (_("expecting mnemonic; got nothing")); | |
3002 | return NULL; | |
3003 | } | |
45288df1 | 3004 | |
29b0f896 AM |
3005 | /* Look up instruction (or prefix) via hash table. */ |
3006 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 3007 | |
29b0f896 AM |
3008 | if (*l != END_OF_INSN |
3009 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3010 | && current_templates | |
40fb9820 | 3011 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3012 | { |
c6fb90c8 | 3013 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3014 | { |
3015 | as_bad ((flag_code != CODE_64BIT | |
3016 | ? _("`%s' is only supported in 64-bit mode") | |
3017 | : _("`%s' is not supported in 64-bit mode")), | |
3018 | current_templates->start->name); | |
3019 | return NULL; | |
3020 | } | |
29b0f896 AM |
3021 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3022 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3023 | if ((current_templates->start->opcode_modifier.size16 |
3024 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3025 | && flag_code != CODE_64BIT |
40fb9820 | 3026 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3027 | ^ (flag_code == CODE_16BIT))) |
3028 | { | |
3029 | as_bad (_("redundant %s prefix"), | |
3030 | current_templates->start->name); | |
3031 | return NULL; | |
45288df1 | 3032 | } |
29b0f896 AM |
3033 | /* Add prefix, checking for repeated prefixes. */ |
3034 | switch (add_prefix (current_templates->start->base_opcode)) | |
3035 | { | |
3036 | case 0: | |
3037 | return NULL; | |
3038 | case 2: | |
3039 | expecting_string_instruction = current_templates->start->name; | |
3040 | break; | |
3041 | } | |
3042 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3043 | token_start = ++l; | |
3044 | } | |
3045 | else | |
3046 | break; | |
3047 | } | |
45288df1 | 3048 | |
30a55f88 | 3049 | if (!current_templates) |
b6169b20 | 3050 | { |
30a55f88 L |
3051 | /* Check if we should swap operand in encoding. */ |
3052 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') | |
3053 | i.swap_operand = 1; | |
3054 | else | |
3055 | goto check_suffix; | |
3056 | mnem_p = dot_p; | |
3057 | *dot_p = '\0'; | |
3058 | current_templates = hash_find (op_hash, mnemonic); | |
b6169b20 L |
3059 | } |
3060 | ||
29b0f896 AM |
3061 | if (!current_templates) |
3062 | { | |
b6169b20 | 3063 | check_suffix: |
29b0f896 AM |
3064 | /* See if we can get a match by trimming off a suffix. */ |
3065 | switch (mnem_p[-1]) | |
3066 | { | |
3067 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3068 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3069 | i.suffix = SHORT_MNEM_SUFFIX; | |
3070 | else | |
29b0f896 AM |
3071 | case BYTE_MNEM_SUFFIX: |
3072 | case QWORD_MNEM_SUFFIX: | |
3073 | i.suffix = mnem_p[-1]; | |
3074 | mnem_p[-1] = '\0'; | |
3075 | current_templates = hash_find (op_hash, mnemonic); | |
3076 | break; | |
3077 | case SHORT_MNEM_SUFFIX: | |
3078 | case LONG_MNEM_SUFFIX: | |
3079 | if (!intel_syntax) | |
3080 | { | |
3081 | i.suffix = mnem_p[-1]; | |
3082 | mnem_p[-1] = '\0'; | |
3083 | current_templates = hash_find (op_hash, mnemonic); | |
3084 | } | |
3085 | break; | |
252b5132 | 3086 | |
29b0f896 AM |
3087 | /* Intel Syntax. */ |
3088 | case 'd': | |
3089 | if (intel_syntax) | |
3090 | { | |
9306ca4a | 3091 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3092 | i.suffix = SHORT_MNEM_SUFFIX; |
3093 | else | |
3094 | i.suffix = LONG_MNEM_SUFFIX; | |
3095 | mnem_p[-1] = '\0'; | |
3096 | current_templates = hash_find (op_hash, mnemonic); | |
3097 | } | |
3098 | break; | |
3099 | } | |
3100 | if (!current_templates) | |
3101 | { | |
3102 | as_bad (_("no such instruction: `%s'"), token_start); | |
3103 | return NULL; | |
3104 | } | |
3105 | } | |
252b5132 | 3106 | |
40fb9820 L |
3107 | if (current_templates->start->opcode_modifier.jump |
3108 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3109 | { |
3110 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3111 | predict taken and predict not taken respectively. | |
3112 | I'm not sure that branch hints actually do anything on loop | |
3113 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3114 | may work in the future and it doesn't hurt to accept them | |
3115 | now. */ | |
3116 | if (l[0] == ',' && l[1] == 'p') | |
3117 | { | |
3118 | if (l[2] == 't') | |
3119 | { | |
3120 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3121 | return NULL; | |
3122 | l += 3; | |
3123 | } | |
3124 | else if (l[2] == 'n') | |
3125 | { | |
3126 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3127 | return NULL; | |
3128 | l += 3; | |
3129 | } | |
3130 | } | |
3131 | } | |
3132 | /* Any other comma loses. */ | |
3133 | if (*l == ',') | |
3134 | { | |
3135 | as_bad (_("invalid character %s in mnemonic"), | |
3136 | output_invalid (*l)); | |
3137 | return NULL; | |
3138 | } | |
252b5132 | 3139 | |
29b0f896 | 3140 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3141 | supported = 0; |
3142 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3143 | { | |
c0f3af97 L |
3144 | supported |= cpu_flags_match (t); |
3145 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3146 | goto skip; |
5c6af06e | 3147 | } |
3629bb00 | 3148 | |
c0f3af97 | 3149 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3150 | { |
3151 | as_bad (flag_code == CODE_64BIT | |
3152 | ? _("`%s' is not supported in 64-bit mode") | |
3153 | : _("`%s' is only supported in 64-bit mode"), | |
3154 | current_templates->start->name); | |
3155 | return NULL; | |
3156 | } | |
c0f3af97 | 3157 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3158 | { |
3629bb00 | 3159 | as_bad (_("`%s' is not supported on `%s%s'"), |
41aacd83 L |
3160 | current_templates->start->name, |
3161 | cpu_arch_name ? cpu_arch_name : default_arch, | |
3629bb00 L |
3162 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
3163 | return NULL; | |
29b0f896 | 3164 | } |
3629bb00 L |
3165 | |
3166 | skip: | |
3167 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3168 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3169 | { |
3170 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3171 | } | |
252b5132 | 3172 | |
29b0f896 | 3173 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 3174 | if (expecting_string_instruction) |
29b0f896 | 3175 | { |
f41bbced JB |
3176 | static templates override; |
3177 | ||
3178 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 3179 | if (t->opcode_modifier.isstring) |
f41bbced JB |
3180 | break; |
3181 | if (t >= current_templates->end) | |
3182 | { | |
3183 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3184 | expecting_string_instruction); |
f41bbced JB |
3185 | return NULL; |
3186 | } | |
3187 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 3188 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
3189 | break; |
3190 | override.end = t; | |
3191 | current_templates = &override; | |
29b0f896 | 3192 | } |
252b5132 | 3193 | |
29b0f896 AM |
3194 | return l; |
3195 | } | |
252b5132 | 3196 | |
29b0f896 | 3197 | static char * |
e3bb37b5 | 3198 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3199 | { |
3200 | char *token_start; | |
3138f287 | 3201 | |
29b0f896 AM |
3202 | /* 1 if operand is pending after ','. */ |
3203 | unsigned int expecting_operand = 0; | |
252b5132 | 3204 | |
29b0f896 AM |
3205 | /* Non-zero if operand parens not balanced. */ |
3206 | unsigned int paren_not_balanced; | |
3207 | ||
3208 | while (*l != END_OF_INSN) | |
3209 | { | |
3210 | /* Skip optional white space before operand. */ | |
3211 | if (is_space_char (*l)) | |
3212 | ++l; | |
3213 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3214 | { | |
3215 | as_bad (_("invalid character %s before operand %d"), | |
3216 | output_invalid (*l), | |
3217 | i.operands + 1); | |
3218 | return NULL; | |
3219 | } | |
3220 | token_start = l; /* after white space */ | |
3221 | paren_not_balanced = 0; | |
3222 | while (paren_not_balanced || *l != ',') | |
3223 | { | |
3224 | if (*l == END_OF_INSN) | |
3225 | { | |
3226 | if (paren_not_balanced) | |
3227 | { | |
3228 | if (!intel_syntax) | |
3229 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3230 | i.operands + 1); | |
3231 | else | |
3232 | as_bad (_("unbalanced brackets in operand %d."), | |
3233 | i.operands + 1); | |
3234 | return NULL; | |
3235 | } | |
3236 | else | |
3237 | break; /* we are done */ | |
3238 | } | |
3239 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3240 | { | |
3241 | as_bad (_("invalid character %s in operand %d"), | |
3242 | output_invalid (*l), | |
3243 | i.operands + 1); | |
3244 | return NULL; | |
3245 | } | |
3246 | if (!intel_syntax) | |
3247 | { | |
3248 | if (*l == '(') | |
3249 | ++paren_not_balanced; | |
3250 | if (*l == ')') | |
3251 | --paren_not_balanced; | |
3252 | } | |
3253 | else | |
3254 | { | |
3255 | if (*l == '[') | |
3256 | ++paren_not_balanced; | |
3257 | if (*l == ']') | |
3258 | --paren_not_balanced; | |
3259 | } | |
3260 | l++; | |
3261 | } | |
3262 | if (l != token_start) | |
3263 | { /* Yes, we've read in another operand. */ | |
3264 | unsigned int operand_ok; | |
3265 | this_operand = i.operands++; | |
7d5e4556 | 3266 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3267 | if (i.operands > MAX_OPERANDS) |
3268 | { | |
3269 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3270 | MAX_OPERANDS); | |
3271 | return NULL; | |
3272 | } | |
3273 | /* Now parse operand adding info to 'i' as we go along. */ | |
3274 | END_STRING_AND_SAVE (l); | |
3275 | ||
3276 | if (intel_syntax) | |
3277 | operand_ok = | |
3278 | i386_intel_operand (token_start, | |
3279 | intel_float_operand (mnemonic)); | |
3280 | else | |
a7619375 | 3281 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3282 | |
3283 | RESTORE_END_STRING (l); | |
3284 | if (!operand_ok) | |
3285 | return NULL; | |
3286 | } | |
3287 | else | |
3288 | { | |
3289 | if (expecting_operand) | |
3290 | { | |
3291 | expecting_operand_after_comma: | |
3292 | as_bad (_("expecting operand after ','; got nothing")); | |
3293 | return NULL; | |
3294 | } | |
3295 | if (*l == ',') | |
3296 | { | |
3297 | as_bad (_("expecting operand before ','; got nothing")); | |
3298 | return NULL; | |
3299 | } | |
3300 | } | |
7f3f1ea2 | 3301 | |
29b0f896 AM |
3302 | /* Now *l must be either ',' or END_OF_INSN. */ |
3303 | if (*l == ',') | |
3304 | { | |
3305 | if (*++l == END_OF_INSN) | |
3306 | { | |
3307 | /* Just skip it, if it's \n complain. */ | |
3308 | goto expecting_operand_after_comma; | |
3309 | } | |
3310 | expecting_operand = 1; | |
3311 | } | |
3312 | } | |
3313 | return l; | |
3314 | } | |
7f3f1ea2 | 3315 | |
050dfa73 | 3316 | static void |
4d456e3d | 3317 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3318 | { |
3319 | union i386_op temp_op; | |
40fb9820 | 3320 | i386_operand_type temp_type; |
050dfa73 | 3321 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3322 | |
050dfa73 MM |
3323 | temp_type = i.types[xchg2]; |
3324 | i.types[xchg2] = i.types[xchg1]; | |
3325 | i.types[xchg1] = temp_type; | |
3326 | temp_op = i.op[xchg2]; | |
3327 | i.op[xchg2] = i.op[xchg1]; | |
3328 | i.op[xchg1] = temp_op; | |
3329 | temp_reloc = i.reloc[xchg2]; | |
3330 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3331 | i.reloc[xchg1] = temp_reloc; | |
3332 | } | |
3333 | ||
29b0f896 | 3334 | static void |
e3bb37b5 | 3335 | swap_operands (void) |
29b0f896 | 3336 | { |
b7c61d9a | 3337 | switch (i.operands) |
050dfa73 | 3338 | { |
c0f3af97 | 3339 | case 5: |
b7c61d9a | 3340 | case 4: |
4d456e3d | 3341 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3342 | case 3: |
3343 | case 2: | |
4d456e3d | 3344 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3345 | break; |
3346 | default: | |
3347 | abort (); | |
29b0f896 | 3348 | } |
29b0f896 AM |
3349 | |
3350 | if (i.mem_operands == 2) | |
3351 | { | |
3352 | const seg_entry *temp_seg; | |
3353 | temp_seg = i.seg[0]; | |
3354 | i.seg[0] = i.seg[1]; | |
3355 | i.seg[1] = temp_seg; | |
3356 | } | |
3357 | } | |
252b5132 | 3358 | |
29b0f896 AM |
3359 | /* Try to ensure constant immediates are represented in the smallest |
3360 | opcode possible. */ | |
3361 | static void | |
e3bb37b5 | 3362 | optimize_imm (void) |
29b0f896 AM |
3363 | { |
3364 | char guess_suffix = 0; | |
3365 | int op; | |
252b5132 | 3366 | |
29b0f896 AM |
3367 | if (i.suffix) |
3368 | guess_suffix = i.suffix; | |
3369 | else if (i.reg_operands) | |
3370 | { | |
3371 | /* Figure out a suffix from the last register operand specified. | |
3372 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3373 | but the following works for instructions with immediates. | |
3374 | In any case, we can't set i.suffix yet. */ | |
3375 | for (op = i.operands; --op >= 0;) | |
40fb9820 L |
3376 | if (i.types[op].bitfield.reg8) |
3377 | { | |
3378 | guess_suffix = BYTE_MNEM_SUFFIX; | |
3379 | break; | |
3380 | } | |
3381 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3382 | { |
40fb9820 L |
3383 | guess_suffix = WORD_MNEM_SUFFIX; |
3384 | break; | |
3385 | } | |
3386 | else if (i.types[op].bitfield.reg32) | |
3387 | { | |
3388 | guess_suffix = LONG_MNEM_SUFFIX; | |
3389 | break; | |
3390 | } | |
3391 | else if (i.types[op].bitfield.reg64) | |
3392 | { | |
3393 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3394 | break; |
252b5132 | 3395 | } |
29b0f896 AM |
3396 | } |
3397 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3398 | guess_suffix = WORD_MNEM_SUFFIX; | |
3399 | ||
3400 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3401 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3402 | { |
3403 | switch (i.op[op].imms->X_op) | |
252b5132 | 3404 | { |
29b0f896 AM |
3405 | case O_constant: |
3406 | /* If a suffix is given, this operand may be shortened. */ | |
3407 | switch (guess_suffix) | |
252b5132 | 3408 | { |
29b0f896 | 3409 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3410 | i.types[op].bitfield.imm32 = 1; |
3411 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3412 | break; |
3413 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3414 | i.types[op].bitfield.imm16 = 1; |
3415 | i.types[op].bitfield.imm32 = 1; | |
3416 | i.types[op].bitfield.imm32s = 1; | |
3417 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3418 | break; |
3419 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3420 | i.types[op].bitfield.imm8 = 1; |
3421 | i.types[op].bitfield.imm8s = 1; | |
3422 | i.types[op].bitfield.imm16 = 1; | |
3423 | i.types[op].bitfield.imm32 = 1; | |
3424 | i.types[op].bitfield.imm32s = 1; | |
3425 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3426 | break; |
252b5132 | 3427 | } |
252b5132 | 3428 | |
29b0f896 AM |
3429 | /* If this operand is at most 16 bits, convert it |
3430 | to a signed 16 bit number before trying to see | |
3431 | whether it will fit in an even smaller size. | |
3432 | This allows a 16-bit operand such as $0xffe0 to | |
3433 | be recognised as within Imm8S range. */ | |
40fb9820 | 3434 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3435 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3436 | { |
29b0f896 AM |
3437 | i.op[op].imms->X_add_number = |
3438 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3439 | } | |
40fb9820 | 3440 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3441 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3442 | == 0)) | |
3443 | { | |
3444 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3445 | ^ ((offsetT) 1 << 31)) | |
3446 | - ((offsetT) 1 << 31)); | |
3447 | } | |
40fb9820 | 3448 | i.types[op] |
c6fb90c8 L |
3449 | = operand_type_or (i.types[op], |
3450 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3451 | |
29b0f896 AM |
3452 | /* We must avoid matching of Imm32 templates when 64bit |
3453 | only immediate is available. */ | |
3454 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3455 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3456 | break; |
252b5132 | 3457 | |
29b0f896 AM |
3458 | case O_absent: |
3459 | case O_register: | |
3460 | abort (); | |
3461 | ||
3462 | /* Symbols and expressions. */ | |
3463 | default: | |
9cd96992 JB |
3464 | /* Convert symbolic operand to proper sizes for matching, but don't |
3465 | prevent matching a set of insns that only supports sizes other | |
3466 | than those matching the insn suffix. */ | |
3467 | { | |
40fb9820 | 3468 | i386_operand_type mask, allowed; |
9cd96992 JB |
3469 | const template *t; |
3470 | ||
0dfbf9d7 L |
3471 | operand_type_set (&mask, 0); |
3472 | operand_type_set (&allowed, 0); | |
40fb9820 | 3473 | |
4eed87de AM |
3474 | for (t = current_templates->start; |
3475 | t < current_templates->end; | |
3476 | ++t) | |
c6fb90c8 L |
3477 | allowed = operand_type_or (allowed, |
3478 | t->operand_types[op]); | |
9cd96992 JB |
3479 | switch (guess_suffix) |
3480 | { | |
3481 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3482 | mask.bitfield.imm64 = 1; |
3483 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3484 | break; |
3485 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3486 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3487 | break; |
3488 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3489 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3490 | break; |
3491 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3492 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3493 | break; |
3494 | default: | |
9cd96992 JB |
3495 | break; |
3496 | } | |
c6fb90c8 | 3497 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3498 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3499 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3500 | } |
29b0f896 | 3501 | break; |
252b5132 | 3502 | } |
29b0f896 AM |
3503 | } |
3504 | } | |
47926f60 | 3505 | |
29b0f896 AM |
3506 | /* Try to use the smallest displacement type too. */ |
3507 | static void | |
e3bb37b5 | 3508 | optimize_disp (void) |
29b0f896 AM |
3509 | { |
3510 | int op; | |
3e73aa7c | 3511 | |
29b0f896 | 3512 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3513 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3514 | { |
b300c311 | 3515 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3516 | { |
b300c311 | 3517 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 3518 | |
40fb9820 | 3519 | if (i.types[op].bitfield.disp16 |
b300c311 L |
3520 | && (disp & ~(offsetT) 0xffff) == 0) |
3521 | { | |
3522 | /* If this operand is at most 16 bits, convert | |
3523 | to a signed 16 bit number and don't use 64bit | |
3524 | displacement. */ | |
3525 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
40fb9820 | 3526 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3527 | } |
40fb9820 | 3528 | if (i.types[op].bitfield.disp32 |
b300c311 L |
3529 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
3530 | { | |
3531 | /* If this operand is at most 32 bits, convert | |
3532 | to a signed 32 bit number and don't use 64bit | |
3533 | displacement. */ | |
3534 | disp &= (((offsetT) 2 << 31) - 1); | |
3535 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3536 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3537 | } |
40fb9820 | 3538 | if (!disp && i.types[op].bitfield.baseindex) |
b300c311 | 3539 | { |
40fb9820 L |
3540 | i.types[op].bitfield.disp8 = 0; |
3541 | i.types[op].bitfield.disp16 = 0; | |
3542 | i.types[op].bitfield.disp32 = 0; | |
3543 | i.types[op].bitfield.disp32s = 0; | |
3544 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3545 | i.op[op].disps = 0; |
3546 | i.disp_operands--; | |
3547 | } | |
3548 | else if (flag_code == CODE_64BIT) | |
3549 | { | |
3550 | if (fits_in_signed_long (disp)) | |
28a9d8f5 | 3551 | { |
40fb9820 L |
3552 | i.types[op].bitfield.disp64 = 0; |
3553 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3554 | } |
b300c311 | 3555 | if (fits_in_unsigned_long (disp)) |
40fb9820 | 3556 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3557 | } |
40fb9820 L |
3558 | if ((i.types[op].bitfield.disp32 |
3559 | || i.types[op].bitfield.disp32s | |
3560 | || i.types[op].bitfield.disp16) | |
b300c311 | 3561 | && fits_in_signed_byte (disp)) |
40fb9820 | 3562 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3563 | } |
67a4f2b7 AO |
3564 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3565 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3566 | { | |
3567 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3568 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3569 | i.types[op].bitfield.disp8 = 0; |
3570 | i.types[op].bitfield.disp16 = 0; | |
3571 | i.types[op].bitfield.disp32 = 0; | |
3572 | i.types[op].bitfield.disp32s = 0; | |
3573 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3574 | } |
3575 | else | |
b300c311 | 3576 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3577 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3578 | } |
29b0f896 AM |
3579 | } |
3580 | ||
fa99fab2 | 3581 | static const template * |
e3bb37b5 | 3582 | match_template (void) |
29b0f896 AM |
3583 | { |
3584 | /* Points to template once we've found it. */ | |
3585 | const template *t; | |
40fb9820 | 3586 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 3587 | i386_operand_type overlap4; |
29b0f896 | 3588 | unsigned int found_reverse_match; |
40fb9820 L |
3589 | i386_opcode_modifier suffix_check; |
3590 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3591 | int addr_prefix_disp; |
a5c311ca | 3592 | unsigned int j; |
3629bb00 | 3593 | unsigned int found_cpu_match; |
45664ddb | 3594 | unsigned int check_register; |
29b0f896 | 3595 | |
c0f3af97 L |
3596 | #if MAX_OPERANDS != 5 |
3597 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
3598 | #endif |
3599 | ||
29b0f896 | 3600 | found_reverse_match = 0; |
539e75ad | 3601 | addr_prefix_disp = -1; |
40fb9820 L |
3602 | |
3603 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3604 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3605 | suffix_check.no_bsuf = 1; | |
3606 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3607 | suffix_check.no_wsuf = 1; | |
3608 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3609 | suffix_check.no_ssuf = 1; | |
3610 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3611 | suffix_check.no_lsuf = 1; | |
3612 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3613 | suffix_check.no_qsuf = 1; | |
3614 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3615 | suffix_check.no_ldsuf = 1; |
29b0f896 | 3616 | |
45aa61fe | 3617 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3618 | { |
539e75ad L |
3619 | addr_prefix_disp = -1; |
3620 | ||
29b0f896 AM |
3621 | /* Must have right number of operands. */ |
3622 | if (i.operands != t->operands) | |
3623 | continue; | |
3624 | ||
50aecf8c | 3625 | /* Check processor support. */ |
c0f3af97 L |
3626 | found_cpu_match = (cpu_flags_match (t) |
3627 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
3628 | if (!found_cpu_match) |
3629 | continue; | |
3630 | ||
e1d4d893 L |
3631 | /* Check old gcc support. */ |
3632 | if (!old_gcc && t->opcode_modifier.oldgcc) | |
3633 | continue; | |
3634 | ||
3635 | /* Check AT&T mnemonic. */ | |
3636 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) | |
1efbbeb4 L |
3637 | continue; |
3638 | ||
5c07affc L |
3639 | /* Check AT&T syntax Intel syntax. */ |
3640 | if ((intel_syntax && t->opcode_modifier.attsyntax) | |
3641 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
3642 | continue; |
3643 | ||
20592a94 | 3644 | /* Check the suffix, except for some instructions in intel mode. */ |
567e4e96 L |
3645 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3646 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3647 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3648 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3649 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3650 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3651 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3652 | continue; |
3653 | ||
5c07affc | 3654 | if (!operand_size_match (t)) |
7d5e4556 | 3655 | continue; |
539e75ad | 3656 | |
5c07affc L |
3657 | for (j = 0; j < MAX_OPERANDS; j++) |
3658 | operand_types[j] = t->operand_types[j]; | |
3659 | ||
45aa61fe AM |
3660 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3661 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3662 | && flag_code != CODE_64BIT | |
3663 | && (intel_syntax | |
40fb9820 | 3664 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3665 | && !intel_float_operand (t->name)) |
3666 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 3667 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
3668 | && !operand_types[0].bitfield.regxmm |
3669 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 3670 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
3671 | && !!operand_types[t->operands > 1].bitfield.regxmm |
3672 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
3673 | && (t->base_opcode != 0x0fc7 |
3674 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3675 | continue; | |
3676 | ||
192dc9c6 JB |
3677 | /* In general, don't allow 32-bit operands on pre-386. */ |
3678 | else if (i.suffix == LONG_MNEM_SUFFIX | |
3679 | && !cpu_arch_flags.bitfield.cpui386 | |
3680 | && (intel_syntax | |
3681 | ? (!t->opcode_modifier.ignoresize | |
3682 | && !intel_float_operand (t->name)) | |
3683 | : intel_float_operand (t->name) != 2) | |
3684 | && ((!operand_types[0].bitfield.regmmx | |
3685 | && !operand_types[0].bitfield.regxmm) | |
3686 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3687 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
3688 | continue; | |
3689 | ||
29b0f896 | 3690 | /* Do not verify operands when there are none. */ |
50aecf8c | 3691 | else |
29b0f896 | 3692 | { |
c6fb90c8 | 3693 | if (!t->operands) |
2dbab7d5 L |
3694 | /* We've found a match; break out of loop. */ |
3695 | break; | |
29b0f896 | 3696 | } |
252b5132 | 3697 | |
539e75ad L |
3698 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3699 | into Disp32/Disp16/Disp32 operand. */ | |
3700 | if (i.prefix[ADDR_PREFIX] != 0) | |
3701 | { | |
40fb9820 | 3702 | /* There should be only one Disp operand. */ |
539e75ad L |
3703 | switch (flag_code) |
3704 | { | |
3705 | case CODE_16BIT: | |
40fb9820 L |
3706 | for (j = 0; j < MAX_OPERANDS; j++) |
3707 | { | |
3708 | if (operand_types[j].bitfield.disp16) | |
3709 | { | |
3710 | addr_prefix_disp = j; | |
3711 | operand_types[j].bitfield.disp32 = 1; | |
3712 | operand_types[j].bitfield.disp16 = 0; | |
3713 | break; | |
3714 | } | |
3715 | } | |
539e75ad L |
3716 | break; |
3717 | case CODE_32BIT: | |
40fb9820 L |
3718 | for (j = 0; j < MAX_OPERANDS; j++) |
3719 | { | |
3720 | if (operand_types[j].bitfield.disp32) | |
3721 | { | |
3722 | addr_prefix_disp = j; | |
3723 | operand_types[j].bitfield.disp32 = 0; | |
3724 | operand_types[j].bitfield.disp16 = 1; | |
3725 | break; | |
3726 | } | |
3727 | } | |
539e75ad L |
3728 | break; |
3729 | case CODE_64BIT: | |
40fb9820 L |
3730 | for (j = 0; j < MAX_OPERANDS; j++) |
3731 | { | |
3732 | if (operand_types[j].bitfield.disp64) | |
3733 | { | |
3734 | addr_prefix_disp = j; | |
3735 | operand_types[j].bitfield.disp64 = 0; | |
3736 | operand_types[j].bitfield.disp32 = 1; | |
3737 | break; | |
3738 | } | |
3739 | } | |
539e75ad L |
3740 | break; |
3741 | } | |
539e75ad L |
3742 | } |
3743 | ||
45664ddb L |
3744 | /* We check register size only if size of operands can be |
3745 | encoded the canonical way. */ | |
3746 | check_register = t->opcode_modifier.w; | |
c6fb90c8 | 3747 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
3748 | switch (t->operands) |
3749 | { | |
3750 | case 1: | |
40fb9820 | 3751 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
3752 | continue; |
3753 | break; | |
3754 | case 2: | |
8b38ad71 L |
3755 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
3756 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
3757 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
3758 | zero-extend %eax to %rax. */ | |
3759 | if (flag_code == CODE_64BIT | |
3760 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
3761 | && operand_type_equal (&i.types [0], &acc32) |
3762 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 3763 | continue; |
b6169b20 L |
3764 | if (i.swap_operand) |
3765 | { | |
3766 | /* If we swap operand in encoding, we either match | |
3767 | the next one or reverse direction of operands. */ | |
3768 | if (t->opcode_modifier.s) | |
3769 | continue; | |
3770 | else if (t->opcode_modifier.d) | |
3771 | goto check_reverse; | |
3772 | } | |
3773 | ||
29b0f896 | 3774 | case 3: |
fa99fab2 L |
3775 | /* If we swap operand in encoding, we match the next one. */ |
3776 | if (i.swap_operand && t->opcode_modifier.s) | |
3777 | continue; | |
f48ff2ae | 3778 | case 4: |
c0f3af97 | 3779 | case 5: |
c6fb90c8 | 3780 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
3781 | if (!operand_type_match (overlap0, i.types[0]) |
3782 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3783 | || (check_register |
3784 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
3785 | operand_types[0], |
3786 | overlap1, i.types[1], | |
3787 | operand_types[1]))) | |
29b0f896 AM |
3788 | { |
3789 | /* Check if other direction is valid ... */ | |
40fb9820 | 3790 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
3791 | continue; |
3792 | ||
b6169b20 | 3793 | check_reverse: |
29b0f896 | 3794 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
3795 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
3796 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
3797 | if (!operand_type_match (overlap0, i.types[0]) |
3798 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3799 | || (check_register |
3800 | && !operand_type_register_match (overlap0, | |
3801 | i.types[0], | |
3802 | operand_types[1], | |
3803 | overlap1, | |
3804 | i.types[1], | |
3805 | operand_types[0]))) | |
29b0f896 AM |
3806 | { |
3807 | /* Does not match either direction. */ | |
3808 | continue; | |
3809 | } | |
3810 | /* found_reverse_match holds which of D or FloatDR | |
3811 | we've found. */ | |
40fb9820 | 3812 | if (t->opcode_modifier.d) |
8a2ed489 | 3813 | found_reverse_match = Opcode_D; |
40fb9820 | 3814 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
3815 | found_reverse_match = Opcode_FloatD; |
3816 | else | |
3817 | found_reverse_match = 0; | |
40fb9820 | 3818 | if (t->opcode_modifier.floatr) |
8a2ed489 | 3819 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 3820 | } |
f48ff2ae | 3821 | else |
29b0f896 | 3822 | { |
f48ff2ae | 3823 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
3824 | switch (t->operands) |
3825 | { | |
c0f3af97 L |
3826 | case 5: |
3827 | overlap4 = operand_type_and (i.types[4], | |
3828 | operand_types[4]); | |
d1cbb4db | 3829 | case 4: |
c6fb90c8 L |
3830 | overlap3 = operand_type_and (i.types[3], |
3831 | operand_types[3]); | |
d1cbb4db | 3832 | case 3: |
c6fb90c8 L |
3833 | overlap2 = operand_type_and (i.types[2], |
3834 | operand_types[2]); | |
d1cbb4db L |
3835 | break; |
3836 | } | |
29b0f896 | 3837 | |
f48ff2ae L |
3838 | switch (t->operands) |
3839 | { | |
c0f3af97 L |
3840 | case 5: |
3841 | if (!operand_type_match (overlap4, i.types[4]) | |
3842 | || !operand_type_register_match (overlap3, | |
3843 | i.types[3], | |
3844 | operand_types[3], | |
3845 | overlap4, | |
3846 | i.types[4], | |
3847 | operand_types[4])) | |
3848 | continue; | |
f48ff2ae | 3849 | case 4: |
40fb9820 | 3850 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
3851 | || (check_register |
3852 | && !operand_type_register_match (overlap2, | |
3853 | i.types[2], | |
3854 | operand_types[2], | |
3855 | overlap3, | |
3856 | i.types[3], | |
3857 | operand_types[3]))) | |
f48ff2ae L |
3858 | continue; |
3859 | case 3: | |
3860 | /* Here we make use of the fact that there are no | |
3861 | reverse match 3 operand instructions, and all 3 | |
3862 | operand instructions only need to be checked for | |
3863 | register consistency between operands 2 and 3. */ | |
40fb9820 | 3864 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
3865 | || (check_register |
3866 | && !operand_type_register_match (overlap1, | |
3867 | i.types[1], | |
3868 | operand_types[1], | |
3869 | overlap2, | |
3870 | i.types[2], | |
3871 | operand_types[2]))) | |
f48ff2ae L |
3872 | continue; |
3873 | break; | |
3874 | } | |
29b0f896 | 3875 | } |
f48ff2ae | 3876 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
3877 | slip through to break. */ |
3878 | } | |
3629bb00 | 3879 | if (!found_cpu_match) |
29b0f896 AM |
3880 | { |
3881 | found_reverse_match = 0; | |
3882 | continue; | |
3883 | } | |
c0f3af97 | 3884 | |
29b0f896 AM |
3885 | /* We've found a match; break out of loop. */ |
3886 | break; | |
3887 | } | |
3888 | ||
3889 | if (t == current_templates->end) | |
3890 | { | |
3891 | /* We found no match. */ | |
95f283e8 L |
3892 | if (intel_syntax) |
3893 | as_bad (_("ambiguous operand size or operands invalid for `%s'"), | |
3894 | current_templates->start->name); | |
3895 | else | |
3896 | as_bad (_("suffix or operands invalid for `%s'"), | |
3897 | current_templates->start->name); | |
fa99fab2 | 3898 | return NULL; |
29b0f896 | 3899 | } |
252b5132 | 3900 | |
29b0f896 AM |
3901 | if (!quiet_warnings) |
3902 | { | |
3903 | if (!intel_syntax | |
40fb9820 L |
3904 | && (i.types[0].bitfield.jumpabsolute |
3905 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
3906 | { |
3907 | as_warn (_("indirect %s without `*'"), t->name); | |
3908 | } | |
3909 | ||
40fb9820 L |
3910 | if (t->opcode_modifier.isprefix |
3911 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
3912 | { |
3913 | /* Warn them that a data or address size prefix doesn't | |
3914 | affect assembly of the next line of code. */ | |
3915 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
3916 | } | |
3917 | } | |
3918 | ||
3919 | /* Copy the template we found. */ | |
3920 | i.tm = *t; | |
539e75ad L |
3921 | |
3922 | if (addr_prefix_disp != -1) | |
3923 | i.tm.operand_types[addr_prefix_disp] | |
3924 | = operand_types[addr_prefix_disp]; | |
3925 | ||
29b0f896 AM |
3926 | if (found_reverse_match) |
3927 | { | |
3928 | /* If we found a reverse match we must alter the opcode | |
3929 | direction bit. found_reverse_match holds bits to change | |
3930 | (different for int & float insns). */ | |
3931 | ||
3932 | i.tm.base_opcode ^= found_reverse_match; | |
3933 | ||
539e75ad L |
3934 | i.tm.operand_types[0] = operand_types[1]; |
3935 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
3936 | } |
3937 | ||
fa99fab2 | 3938 | return t; |
29b0f896 AM |
3939 | } |
3940 | ||
3941 | static int | |
e3bb37b5 | 3942 | check_string (void) |
29b0f896 | 3943 | { |
40fb9820 L |
3944 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
3945 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
3946 | { |
3947 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
3948 | { | |
a87af027 | 3949 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 3950 | i.tm.name, |
a87af027 JB |
3951 | mem_op + 1, |
3952 | register_prefix); | |
29b0f896 AM |
3953 | return 0; |
3954 | } | |
3955 | /* There's only ever one segment override allowed per instruction. | |
3956 | This instruction possibly has a legal segment override on the | |
3957 | second operand, so copy the segment to where non-string | |
3958 | instructions store it, allowing common code. */ | |
3959 | i.seg[0] = i.seg[1]; | |
3960 | } | |
40fb9820 | 3961 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
3962 | { |
3963 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
3964 | { | |
a87af027 | 3965 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 3966 | i.tm.name, |
a87af027 JB |
3967 | mem_op + 2, |
3968 | register_prefix); | |
29b0f896 AM |
3969 | return 0; |
3970 | } | |
3971 | } | |
3972 | return 1; | |
3973 | } | |
3974 | ||
3975 | static int | |
543613e9 | 3976 | process_suffix (void) |
29b0f896 AM |
3977 | { |
3978 | /* If matched instruction specifies an explicit instruction mnemonic | |
3979 | suffix, use it. */ | |
40fb9820 L |
3980 | if (i.tm.opcode_modifier.size16) |
3981 | i.suffix = WORD_MNEM_SUFFIX; | |
3982 | else if (i.tm.opcode_modifier.size32) | |
3983 | i.suffix = LONG_MNEM_SUFFIX; | |
3984 | else if (i.tm.opcode_modifier.size64) | |
3985 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
3986 | else if (i.reg_operands) |
3987 | { | |
3988 | /* If there's no instruction mnemonic suffix we try to invent one | |
3989 | based on register operands. */ | |
3990 | if (!i.suffix) | |
3991 | { | |
3992 | /* We take i.suffix from the last register operand specified, | |
3993 | Destination register type is more significant than source | |
381d071f L |
3994 | register type. crc32 in SSE4.2 prefers source register |
3995 | type. */ | |
3996 | if (i.tm.base_opcode == 0xf20f38f1) | |
3997 | { | |
40fb9820 L |
3998 | if (i.types[0].bitfield.reg16) |
3999 | i.suffix = WORD_MNEM_SUFFIX; | |
4000 | else if (i.types[0].bitfield.reg32) | |
4001 | i.suffix = LONG_MNEM_SUFFIX; | |
4002 | else if (i.types[0].bitfield.reg64) | |
4003 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 4004 | } |
9344ff29 | 4005 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 4006 | { |
40fb9820 | 4007 | if (i.types[0].bitfield.reg8) |
20592a94 L |
4008 | i.suffix = BYTE_MNEM_SUFFIX; |
4009 | } | |
381d071f L |
4010 | |
4011 | if (!i.suffix) | |
4012 | { | |
4013 | int op; | |
4014 | ||
20592a94 L |
4015 | if (i.tm.base_opcode == 0xf20f38f1 |
4016 | || i.tm.base_opcode == 0xf20f38f0) | |
4017 | { | |
4018 | /* We have to know the operand size for crc32. */ | |
4019 | as_bad (_("ambiguous memory operand size for `%s`"), | |
4020 | i.tm.name); | |
4021 | return 0; | |
4022 | } | |
4023 | ||
381d071f | 4024 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4025 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 4026 | { |
40fb9820 L |
4027 | if (i.types[op].bitfield.reg8) |
4028 | { | |
4029 | i.suffix = BYTE_MNEM_SUFFIX; | |
4030 | break; | |
4031 | } | |
4032 | else if (i.types[op].bitfield.reg16) | |
4033 | { | |
4034 | i.suffix = WORD_MNEM_SUFFIX; | |
4035 | break; | |
4036 | } | |
4037 | else if (i.types[op].bitfield.reg32) | |
4038 | { | |
4039 | i.suffix = LONG_MNEM_SUFFIX; | |
4040 | break; | |
4041 | } | |
4042 | else if (i.types[op].bitfield.reg64) | |
4043 | { | |
4044 | i.suffix = QWORD_MNEM_SUFFIX; | |
4045 | break; | |
4046 | } | |
381d071f L |
4047 | } |
4048 | } | |
29b0f896 AM |
4049 | } |
4050 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
4051 | { | |
4052 | if (!check_byte_reg ()) | |
4053 | return 0; | |
4054 | } | |
4055 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4056 | { | |
4057 | if (!check_long_reg ()) | |
4058 | return 0; | |
4059 | } | |
4060 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4061 | { | |
955e1e6a L |
4062 | if (intel_syntax |
4063 | && i.tm.opcode_modifier.ignoresize | |
4064 | && i.tm.opcode_modifier.no_qsuf) | |
4065 | i.suffix = 0; | |
4066 | else if (!check_qword_reg ()) | |
29b0f896 AM |
4067 | return 0; |
4068 | } | |
4069 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4070 | { | |
4071 | if (!check_word_reg ()) | |
4072 | return 0; | |
4073 | } | |
c0f3af97 L |
4074 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
4075 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 4076 | { |
c0f3af97 | 4077 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
4078 | should check if it is a valid suffix. */ |
4079 | } | |
40fb9820 | 4080 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
4081 | /* Do nothing if the instruction is going to ignore the prefix. */ |
4082 | ; | |
4083 | else | |
4084 | abort (); | |
4085 | } | |
40fb9820 | 4086 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4087 | && !i.suffix |
4088 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4089 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4090 | { |
4091 | i.suffix = stackop_size; | |
4092 | } | |
9306ca4a JB |
4093 | else if (intel_syntax |
4094 | && !i.suffix | |
40fb9820 L |
4095 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4096 | || i.tm.opcode_modifier.jumpbyte | |
4097 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4098 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4099 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4100 | { |
4101 | switch (flag_code) | |
4102 | { | |
4103 | case CODE_64BIT: | |
40fb9820 | 4104 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4105 | { |
4106 | i.suffix = QWORD_MNEM_SUFFIX; | |
4107 | break; | |
4108 | } | |
4109 | case CODE_32BIT: | |
40fb9820 | 4110 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4111 | i.suffix = LONG_MNEM_SUFFIX; |
4112 | break; | |
4113 | case CODE_16BIT: | |
40fb9820 | 4114 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4115 | i.suffix = WORD_MNEM_SUFFIX; |
4116 | break; | |
4117 | } | |
4118 | } | |
252b5132 | 4119 | |
9306ca4a | 4120 | if (!i.suffix) |
29b0f896 | 4121 | { |
9306ca4a JB |
4122 | if (!intel_syntax) |
4123 | { | |
40fb9820 | 4124 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4125 | { |
4eed87de AM |
4126 | as_bad (_("no instruction mnemonic suffix given and " |
4127 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4128 | return 0; |
4129 | } | |
4130 | } | |
4131 | else | |
4132 | { | |
40fb9820 L |
4133 | unsigned int suffixes; |
4134 | ||
4135 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
4136 | if (!i.tm.opcode_modifier.no_wsuf) | |
4137 | suffixes |= 1 << 1; | |
4138 | if (!i.tm.opcode_modifier.no_lsuf) | |
4139 | suffixes |= 1 << 2; | |
fc4adea1 | 4140 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4141 | suffixes |= 1 << 3; |
4142 | if (!i.tm.opcode_modifier.no_ssuf) | |
4143 | suffixes |= 1 << 4; | |
4144 | if (!i.tm.opcode_modifier.no_qsuf) | |
4145 | suffixes |= 1 << 5; | |
4146 | ||
4147 | /* There are more than suffix matches. */ | |
4148 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4149 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4150 | && !i.tm.opcode_modifier.defaultsize |
4151 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4152 | { |
4153 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4154 | return 0; | |
4155 | } | |
4156 | } | |
29b0f896 | 4157 | } |
252b5132 | 4158 | |
9306ca4a JB |
4159 | /* Change the opcode based on the operand size given by i.suffix; |
4160 | We don't need to change things for byte insns. */ | |
4161 | ||
582d5edd L |
4162 | if (i.suffix |
4163 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4164 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4165 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4166 | { |
4167 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4168 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4169 | { |
40fb9820 | 4170 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4171 | i.tm.base_opcode |= 8; |
4172 | else | |
4173 | i.tm.base_opcode |= 1; | |
4174 | } | |
0f3f3d8b | 4175 | |
29b0f896 AM |
4176 | /* Now select between word & dword operations via the operand |
4177 | size prefix, except for instructions that will ignore this | |
4178 | prefix anyway. */ | |
ca61edf2 | 4179 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4180 | { |
ca61edf2 L |
4181 | /* The address size override prefix changes the size of the |
4182 | first operand. */ | |
40fb9820 L |
4183 | if ((flag_code == CODE_32BIT |
4184 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4185 | || (flag_code != CODE_32BIT | |
4186 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4187 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4188 | return 0; | |
4189 | } | |
4190 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4191 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4192 | && !i.tm.opcode_modifier.ignoresize |
4193 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4194 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4195 | || (flag_code == CODE_64BIT | |
40fb9820 | 4196 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4197 | { |
4198 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4199 | |
40fb9820 | 4200 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4201 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4202 | |
29b0f896 AM |
4203 | if (!add_prefix (prefix)) |
4204 | return 0; | |
24eab124 | 4205 | } |
252b5132 | 4206 | |
29b0f896 AM |
4207 | /* Set mode64 for an operand. */ |
4208 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4209 | && flag_code == CODE_64BIT |
40fb9820 | 4210 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4211 | { |
4212 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4213 | need rex64. cmpxchg8b is also a special case. */ |
4214 | if (! (i.operands == 2 | |
4215 | && i.tm.base_opcode == 0x90 | |
4216 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4217 | && operand_type_equal (&i.types [0], &acc64) |
4218 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4219 | && ! (i.operands == 1 |
4220 | && i.tm.base_opcode == 0xfc7 | |
4221 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4222 | && !operand_type_check (i.types [0], reg) |
4223 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4224 | i.rex |= REX_W; |
46e883c5 | 4225 | } |
3e73aa7c | 4226 | |
29b0f896 AM |
4227 | /* Size floating point instruction. */ |
4228 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4229 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4230 | i.tm.base_opcode ^= 4; |
29b0f896 | 4231 | } |
7ecd2f8b | 4232 | |
29b0f896 AM |
4233 | return 1; |
4234 | } | |
3e73aa7c | 4235 | |
29b0f896 | 4236 | static int |
543613e9 | 4237 | check_byte_reg (void) |
29b0f896 AM |
4238 | { |
4239 | int op; | |
543613e9 | 4240 | |
29b0f896 AM |
4241 | for (op = i.operands; --op >= 0;) |
4242 | { | |
4243 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4244 | 32 bit version of an eight bit register, we will just use the | |
4245 | low portion, and that's OK too. */ | |
40fb9820 | 4246 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4247 | continue; |
4248 | ||
ca61edf2 L |
4249 | /* Don't generate this warning if not needed. */ |
4250 | if (intel_syntax && i.tm.opcode_modifier.byteokintel) | |
29b0f896 AM |
4251 | continue; |
4252 | ||
9344ff29 L |
4253 | /* crc32 doesn't generate this warning. */ |
4254 | if (i.tm.base_opcode == 0xf20f38f0) | |
4255 | continue; | |
4256 | ||
40fb9820 L |
4257 | if ((i.types[op].bitfield.reg16 |
4258 | || i.types[op].bitfield.reg32 | |
4259 | || i.types[op].bitfield.reg64) | |
4260 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
4261 | { |
4262 | /* Prohibit these changes in the 64bit mode, since the | |
4263 | lowering is more complicated. */ | |
4264 | if (flag_code == CODE_64BIT | |
40fb9820 | 4265 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 4266 | { |
2ca3ace5 L |
4267 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4268 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4269 | i.suffix); |
4270 | return 0; | |
4271 | } | |
4272 | #if REGISTER_WARNINGS | |
4273 | if (!quiet_warnings | |
40fb9820 | 4274 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
4275 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4276 | register_prefix, | |
40fb9820 | 4277 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4278 | ? REGNAM_AL - REGNAM_AX |
4279 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4280 | register_prefix, |
29b0f896 AM |
4281 | i.op[op].regs->reg_name, |
4282 | i.suffix); | |
4283 | #endif | |
4284 | continue; | |
4285 | } | |
4286 | /* Any other register is bad. */ | |
40fb9820 L |
4287 | if (i.types[op].bitfield.reg16 |
4288 | || i.types[op].bitfield.reg32 | |
4289 | || i.types[op].bitfield.reg64 | |
4290 | || i.types[op].bitfield.regmmx | |
4291 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4292 | || i.types[op].bitfield.regymm |
40fb9820 L |
4293 | || i.types[op].bitfield.sreg2 |
4294 | || i.types[op].bitfield.sreg3 | |
4295 | || i.types[op].bitfield.control | |
4296 | || i.types[op].bitfield.debug | |
4297 | || i.types[op].bitfield.test | |
4298 | || i.types[op].bitfield.floatreg | |
4299 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4300 | { |
a540244d L |
4301 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4302 | register_prefix, | |
29b0f896 AM |
4303 | i.op[op].regs->reg_name, |
4304 | i.tm.name, | |
4305 | i.suffix); | |
4306 | return 0; | |
4307 | } | |
4308 | } | |
4309 | return 1; | |
4310 | } | |
4311 | ||
4312 | static int | |
e3bb37b5 | 4313 | check_long_reg (void) |
29b0f896 AM |
4314 | { |
4315 | int op; | |
4316 | ||
4317 | for (op = i.operands; --op >= 0;) | |
4318 | /* Reject eight bit registers, except where the template requires | |
4319 | them. (eg. movzb) */ | |
40fb9820 L |
4320 | if (i.types[op].bitfield.reg8 |
4321 | && (i.tm.operand_types[op].bitfield.reg16 | |
4322 | || i.tm.operand_types[op].bitfield.reg32 | |
4323 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4324 | { |
a540244d L |
4325 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4326 | register_prefix, | |
29b0f896 AM |
4327 | i.op[op].regs->reg_name, |
4328 | i.tm.name, | |
4329 | i.suffix); | |
4330 | return 0; | |
4331 | } | |
4332 | /* Warn if the e prefix on a general reg is missing. */ | |
4333 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4334 | && i.types[op].bitfield.reg16 |
4335 | && (i.tm.operand_types[op].bitfield.reg32 | |
4336 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4337 | { |
4338 | /* Prohibit these changes in the 64bit mode, since the | |
4339 | lowering is more complicated. */ | |
4340 | if (flag_code == CODE_64BIT) | |
252b5132 | 4341 | { |
2ca3ace5 L |
4342 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4343 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4344 | i.suffix); |
4345 | return 0; | |
252b5132 | 4346 | } |
29b0f896 AM |
4347 | #if REGISTER_WARNINGS |
4348 | else | |
a540244d L |
4349 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4350 | register_prefix, | |
29b0f896 | 4351 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4352 | register_prefix, |
29b0f896 AM |
4353 | i.op[op].regs->reg_name, |
4354 | i.suffix); | |
4355 | #endif | |
252b5132 | 4356 | } |
29b0f896 | 4357 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4358 | else if (i.types[op].bitfield.reg64 |
4359 | && (i.tm.operand_types[op].bitfield.reg32 | |
4360 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4361 | { |
34828aad | 4362 | if (intel_syntax |
ca61edf2 | 4363 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4364 | && !i.types[0].bitfield.regxmm) |
34828aad | 4365 | { |
ca61edf2 | 4366 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4367 | i.suffix = QWORD_MNEM_SUFFIX; |
4368 | } | |
4369 | else | |
4370 | { | |
4371 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4372 | register_prefix, i.op[op].regs->reg_name, | |
4373 | i.suffix); | |
4374 | return 0; | |
4375 | } | |
29b0f896 AM |
4376 | } |
4377 | return 1; | |
4378 | } | |
252b5132 | 4379 | |
29b0f896 | 4380 | static int |
e3bb37b5 | 4381 | check_qword_reg (void) |
29b0f896 AM |
4382 | { |
4383 | int op; | |
252b5132 | 4384 | |
29b0f896 AM |
4385 | for (op = i.operands; --op >= 0; ) |
4386 | /* Reject eight bit registers, except where the template requires | |
4387 | them. (eg. movzb) */ | |
40fb9820 L |
4388 | if (i.types[op].bitfield.reg8 |
4389 | && (i.tm.operand_types[op].bitfield.reg16 | |
4390 | || i.tm.operand_types[op].bitfield.reg32 | |
4391 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4392 | { |
a540244d L |
4393 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4394 | register_prefix, | |
29b0f896 AM |
4395 | i.op[op].regs->reg_name, |
4396 | i.tm.name, | |
4397 | i.suffix); | |
4398 | return 0; | |
4399 | } | |
4400 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4401 | else if ((i.types[op].bitfield.reg16 |
4402 | || i.types[op].bitfield.reg32) | |
4403 | && (i.tm.operand_types[op].bitfield.reg32 | |
4404 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4405 | { |
4406 | /* Prohibit these changes in the 64bit mode, since the | |
4407 | lowering is more complicated. */ | |
34828aad | 4408 | if (intel_syntax |
ca61edf2 | 4409 | && i.tm.opcode_modifier.todword |
40fb9820 | 4410 | && !i.types[0].bitfield.regxmm) |
34828aad | 4411 | { |
ca61edf2 | 4412 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4413 | i.suffix = LONG_MNEM_SUFFIX; |
4414 | } | |
4415 | else | |
4416 | { | |
4417 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4418 | register_prefix, i.op[op].regs->reg_name, | |
4419 | i.suffix); | |
4420 | return 0; | |
4421 | } | |
252b5132 | 4422 | } |
29b0f896 AM |
4423 | return 1; |
4424 | } | |
252b5132 | 4425 | |
29b0f896 | 4426 | static int |
e3bb37b5 | 4427 | check_word_reg (void) |
29b0f896 AM |
4428 | { |
4429 | int op; | |
4430 | for (op = i.operands; --op >= 0;) | |
4431 | /* Reject eight bit registers, except where the template requires | |
4432 | them. (eg. movzb) */ | |
40fb9820 L |
4433 | if (i.types[op].bitfield.reg8 |
4434 | && (i.tm.operand_types[op].bitfield.reg16 | |
4435 | || i.tm.operand_types[op].bitfield.reg32 | |
4436 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4437 | { |
a540244d L |
4438 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4439 | register_prefix, | |
29b0f896 AM |
4440 | i.op[op].regs->reg_name, |
4441 | i.tm.name, | |
4442 | i.suffix); | |
4443 | return 0; | |
4444 | } | |
4445 | /* Warn if the e prefix on a general reg is present. */ | |
4446 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4447 | && i.types[op].bitfield.reg32 |
4448 | && (i.tm.operand_types[op].bitfield.reg16 | |
4449 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4450 | { |
29b0f896 AM |
4451 | /* Prohibit these changes in the 64bit mode, since the |
4452 | lowering is more complicated. */ | |
4453 | if (flag_code == CODE_64BIT) | |
252b5132 | 4454 | { |
2ca3ace5 L |
4455 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4456 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4457 | i.suffix); |
4458 | return 0; | |
252b5132 | 4459 | } |
29b0f896 AM |
4460 | else |
4461 | #if REGISTER_WARNINGS | |
a540244d L |
4462 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4463 | register_prefix, | |
29b0f896 | 4464 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4465 | register_prefix, |
29b0f896 AM |
4466 | i.op[op].regs->reg_name, |
4467 | i.suffix); | |
4468 | #endif | |
4469 | } | |
4470 | return 1; | |
4471 | } | |
252b5132 | 4472 | |
29b0f896 | 4473 | static int |
40fb9820 | 4474 | update_imm (unsigned int j) |
29b0f896 | 4475 | { |
40fb9820 L |
4476 | i386_operand_type overlap; |
4477 | ||
c6fb90c8 | 4478 | overlap = operand_type_and (i.types[j], i.tm.operand_types[j]); |
40fb9820 L |
4479 | if ((overlap.bitfield.imm8 |
4480 | || overlap.bitfield.imm8s | |
4481 | || overlap.bitfield.imm16 | |
4482 | || overlap.bitfield.imm32 | |
4483 | || overlap.bitfield.imm32s | |
4484 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
4485 | && !operand_type_equal (&overlap, &imm8) |
4486 | && !operand_type_equal (&overlap, &imm8s) | |
4487 | && !operand_type_equal (&overlap, &imm16) | |
4488 | && !operand_type_equal (&overlap, &imm32) | |
4489 | && !operand_type_equal (&overlap, &imm32s) | |
4490 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
4491 | { |
4492 | if (i.suffix) | |
4493 | { | |
40fb9820 L |
4494 | i386_operand_type temp; |
4495 | ||
0dfbf9d7 | 4496 | operand_type_set (&temp, 0); |
40fb9820 L |
4497 | if (i.suffix == BYTE_MNEM_SUFFIX) |
4498 | { | |
4499 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
4500 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
4501 | } | |
4502 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4503 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
4504 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4505 | { | |
4506 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
4507 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
4508 | } | |
4509 | else | |
4510 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
4511 | overlap = temp; | |
29b0f896 | 4512 | } |
0dfbf9d7 L |
4513 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
4514 | || operand_type_equal (&overlap, &imm16_32) | |
4515 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 4516 | { |
40fb9820 | 4517 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 4518 | overlap = imm16; |
40fb9820 | 4519 | else |
65da13b5 | 4520 | overlap = imm32s; |
29b0f896 | 4521 | } |
0dfbf9d7 L |
4522 | if (!operand_type_equal (&overlap, &imm8) |
4523 | && !operand_type_equal (&overlap, &imm8s) | |
4524 | && !operand_type_equal (&overlap, &imm16) | |
4525 | && !operand_type_equal (&overlap, &imm32) | |
4526 | && !operand_type_equal (&overlap, &imm32s) | |
4527 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 4528 | { |
4eed87de AM |
4529 | as_bad (_("no instruction mnemonic suffix given; " |
4530 | "can't determine immediate size")); | |
29b0f896 AM |
4531 | return 0; |
4532 | } | |
4533 | } | |
40fb9820 | 4534 | i.types[j] = overlap; |
29b0f896 | 4535 | |
40fb9820 L |
4536 | return 1; |
4537 | } | |
4538 | ||
4539 | static int | |
4540 | finalize_imm (void) | |
4541 | { | |
4542 | unsigned int j; | |
29b0f896 | 4543 | |
40fb9820 L |
4544 | for (j = 0; j < 2; j++) |
4545 | if (update_imm (j) == 0) | |
4546 | return 0; | |
4547 | ||
c6fb90c8 | 4548 | i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]); |
40fb9820 | 4549 | assert (operand_type_check (i.types[2], imm) == 0); |
29b0f896 AM |
4550 | |
4551 | return 1; | |
4552 | } | |
4553 | ||
85f10a01 MM |
4554 | static void |
4555 | process_drex (void) | |
4556 | { | |
5dd15031 JJ |
4557 | i.drex.modrm_reg = 0; |
4558 | i.drex.modrm_regmem = 0; | |
85f10a01 MM |
4559 | |
4560 | /* SSE5 4 operand instructions must have the destination the same as | |
4561 | one of the inputs. Figure out the destination register and cache | |
4562 | it away in the drex field, and remember which fields to use for | |
4563 | the modrm byte. */ | |
4564 | if (i.tm.opcode_modifier.drex | |
4565 | && i.tm.opcode_modifier.drexv | |
4566 | && i.operands == 4) | |
4567 | { | |
4568 | i.tm.extension_opcode = None; | |
4569 | ||
4570 | /* Case 1: 4 operand insn, dest = src1, src3 = register. */ | |
4571 | if (i.types[0].bitfield.regxmm != 0 | |
4572 | && i.types[1].bitfield.regxmm != 0 | |
4573 | && i.types[2].bitfield.regxmm != 0 | |
4574 | && i.types[3].bitfield.regxmm != 0 | |
4575 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4576 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4577 | { | |
4578 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4579 | operand_type_set (&i.types[0], 0); |
4580 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4581 | i.reg_operands -= 2; |
4582 | ||
4583 | /* There are two different ways to encode a 4 operand | |
4584 | instruction with all registers that uses OC1 set to | |
4585 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4586 | actions of other SSE5 assemblers. Use modrm encoding 2 | |
4587 | for register/register. Include the high order bit that | |
4588 | is normally stored in the REX byte in the register | |
4589 | field. */ | |
4590 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4591 | i.drex.modrm_reg = 2; | |
4592 | i.drex.modrm_regmem = 1; | |
4593 | i.drex.reg = (i.op[3].regs->reg_num | |
4594 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4595 | } | |
4596 | ||
4597 | /* Case 2: 4 operand insn, dest = src1, src3 = memory. */ | |
4598 | else if (i.types[0].bitfield.regxmm != 0 | |
4599 | && i.types[1].bitfield.regxmm != 0 | |
4600 | && (i.types[2].bitfield.regxmm | |
4601 | || operand_type_check (i.types[2], anymem)) | |
4602 | && i.types[3].bitfield.regxmm != 0 | |
4603 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4604 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4605 | { | |
4606 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4607 | operand_type_set (&i.types[0], 0); |
4608 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4609 | i.reg_operands -= 2; |
4610 | ||
4611 | /* Specify the modrm encoding for memory addressing. Include | |
4612 | the high order bit that is normally stored in the REX byte | |
4613 | in the register field. */ | |
4614 | i.tm.extension_opcode = DREX_X1_X2_XMEM_X1; | |
4615 | i.drex.modrm_reg = 1; | |
4616 | i.drex.modrm_regmem = 2; | |
4617 | i.drex.reg = (i.op[3].regs->reg_num | |
4618 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4619 | } | |
4620 | ||
4621 | /* Case 3: 4 operand insn, dest = src1, src2 = memory. */ | |
4622 | else if (i.types[0].bitfield.regxmm != 0 | |
4623 | && operand_type_check (i.types[1], anymem) != 0 | |
4624 | && i.types[2].bitfield.regxmm != 0 | |
4625 | && i.types[3].bitfield.regxmm != 0 | |
4626 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4627 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4628 | { | |
4629 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4630 | operand_type_set (&i.types[0], 0); |
4631 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4632 | i.reg_operands -= 2; |
4633 | ||
4634 | /* Specify the modrm encoding for memory addressing. Include | |
4635 | the high order bit that is normally stored in the REX byte | |
4636 | in the register field. */ | |
4637 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4638 | i.drex.modrm_reg = 2; | |
4639 | i.drex.modrm_regmem = 1; | |
4640 | i.drex.reg = (i.op[3].regs->reg_num | |
4641 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4642 | } | |
4643 | ||
4644 | /* Case 4: 4 operand insn, dest = src3, src2 = register. */ | |
4645 | else if (i.types[0].bitfield.regxmm != 0 | |
4646 | && i.types[1].bitfield.regxmm != 0 | |
4647 | && i.types[2].bitfield.regxmm != 0 | |
4648 | && i.types[3].bitfield.regxmm != 0 | |
4649 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4650 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4651 | { | |
4652 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4653 | operand_type_set (&i.types[2], 0); |
4654 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4655 | i.reg_operands -= 2; |
4656 | ||
4657 | /* There are two different ways to encode a 4 operand | |
4658 | instruction with all registers that uses OC1 set to | |
4659 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4660 | actions of other SSE5 assemblers. Use modrm encoding | |
4661 | 2 for register/register. Include the high order bit that | |
4662 | is normally stored in the REX byte in the register | |
4663 | field. */ | |
4664 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4665 | i.drex.modrm_reg = 1; | |
4666 | i.drex.modrm_regmem = 0; | |
4667 | ||
4668 | /* Remember the register, including the upper bits */ | |
4669 | i.drex.reg = (i.op[3].regs->reg_num | |
4670 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4671 | } | |
4672 | ||
4673 | /* Case 5: 4 operand insn, dest = src3, src2 = memory. */ | |
4674 | else if (i.types[0].bitfield.regxmm != 0 | |
4675 | && (i.types[1].bitfield.regxmm | |
4676 | || operand_type_check (i.types[1], anymem)) | |
4677 | && i.types[2].bitfield.regxmm != 0 | |
4678 | && i.types[3].bitfield.regxmm != 0 | |
4679 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4680 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4681 | { | |
4682 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4683 | operand_type_set (&i.types[2], 0); |
4684 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4685 | i.reg_operands -= 2; |
4686 | ||
4687 | /* Specify the modrm encoding and remember the register | |
4688 | including the bits normally stored in the REX byte. */ | |
4689 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X2; | |
4690 | i.drex.modrm_reg = 0; | |
4691 | i.drex.modrm_regmem = 1; | |
4692 | i.drex.reg = (i.op[3].regs->reg_num | |
4693 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4694 | } | |
4695 | ||
4696 | /* Case 6: 4 operand insn, dest = src3, src1 = memory. */ | |
4697 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4698 | && i.types[1].bitfield.regxmm != 0 | |
4699 | && i.types[2].bitfield.regxmm != 0 | |
4700 | && i.types[3].bitfield.regxmm != 0 | |
4701 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4702 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4703 | { | |
4704 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4705 | operand_type_set (&i.types[2], 0); |
4706 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4707 | i.reg_operands -= 2; |
4708 | ||
4709 | /* Specify the modrm encoding and remember the register | |
4710 | including the bits normally stored in the REX byte. */ | |
4711 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4712 | i.drex.modrm_reg = 1; | |
4713 | i.drex.modrm_regmem = 0; | |
4714 | i.drex.reg = (i.op[3].regs->reg_num | |
4715 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4716 | } | |
4717 | ||
4718 | else | |
4719 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4720 | i.tm.name); | |
4721 | } | |
4722 | ||
4723 | /* SSE5 instructions with the DREX byte where the only memory operand | |
4724 | is in the 2nd argument, and the first and last xmm register must | |
4725 | match, and is encoded in the DREX byte. */ | |
4726 | else if (i.tm.opcode_modifier.drex | |
4727 | && !i.tm.opcode_modifier.drexv | |
4728 | && i.operands == 4) | |
4729 | { | |
4730 | /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */ | |
4731 | if (i.types[0].bitfield.regxmm != 0 | |
4732 | && (i.types[1].bitfield.regxmm | |
4733 | || operand_type_check(i.types[1], anymem)) | |
4734 | && i.types[2].bitfield.regxmm != 0 | |
4735 | && i.types[3].bitfield.regxmm != 0 | |
4736 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4737 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4738 | { | |
4739 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4740 | operand_type_set (&i.types[0], 0); |
4741 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4742 | i.reg_operands -= 2; |
4743 | ||
4744 | /* Specify the modrm encoding and remember the register | |
4745 | including the high bit normally stored in the REX | |
4746 | byte. */ | |
4747 | i.drex.modrm_reg = 2; | |
4748 | i.drex.modrm_regmem = 1; | |
4749 | i.drex.reg = (i.op[3].regs->reg_num | |
4750 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4751 | } | |
4752 | ||
4753 | else | |
4754 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4755 | i.tm.name); | |
4756 | } | |
4757 | ||
4758 | /* SSE5 3 operand instructions that the result is a register, being | |
4759 | either operand can be a memory operand, using OC0 to note which | |
4760 | one is the memory. */ | |
4761 | else if (i.tm.opcode_modifier.drex | |
4762 | && i.tm.opcode_modifier.drexv | |
4763 | && i.operands == 3) | |
4764 | { | |
4765 | i.tm.extension_opcode = None; | |
4766 | ||
4767 | /* Case 1: 3 operand insn, src1 = register. */ | |
4768 | if (i.types[0].bitfield.regxmm != 0 | |
4769 | && i.types[1].bitfield.regxmm != 0 | |
4770 | && i.types[2].bitfield.regxmm != 0) | |
4771 | { | |
4772 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4773 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4774 | i.reg_operands--; |
4775 | ||
4776 | /* Specify the modrm encoding and remember the register | |
4777 | including the high bit normally stored in the REX byte. */ | |
4778 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4779 | i.drex.modrm_reg = 1; | |
4780 | i.drex.modrm_regmem = 0; | |
4781 | i.drex.reg = (i.op[2].regs->reg_num | |
4782 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4783 | } | |
4784 | ||
4785 | /* Case 2: 3 operand insn, src1 = memory. */ | |
4786 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4787 | && i.types[1].bitfield.regxmm != 0 | |
4788 | && i.types[2].bitfield.regxmm != 0) | |
4789 | { | |
4790 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4791 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4792 | i.reg_operands--; |
4793 | ||
4794 | /* Specify the modrm encoding and remember the register | |
4795 | including the high bit normally stored in the REX | |
4796 | byte. */ | |
4797 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4798 | i.drex.modrm_reg = 1; | |
4799 | i.drex.modrm_regmem = 0; | |
4800 | i.drex.reg = (i.op[2].regs->reg_num | |
4801 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4802 | } | |
4803 | ||
4804 | /* Case 3: 3 operand insn, src2 = memory. */ | |
4805 | else if (i.types[0].bitfield.regxmm != 0 | |
4806 | && operand_type_check (i.types[1], anymem) != 0 | |
4807 | && i.types[2].bitfield.regxmm != 0) | |
4808 | { | |
4809 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4810 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4811 | i.reg_operands--; |
4812 | ||
4813 | /* Specify the modrm encoding and remember the register | |
4814 | including the high bit normally stored in the REX byte. */ | |
4815 | i.tm.extension_opcode = DREX_X1_XMEM_X2; | |
4816 | i.drex.modrm_reg = 0; | |
4817 | i.drex.modrm_regmem = 1; | |
4818 | i.drex.reg = (i.op[2].regs->reg_num | |
4819 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4820 | } | |
4821 | ||
4822 | else | |
4823 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4824 | i.tm.name); | |
4825 | } | |
4826 | ||
4827 | /* SSE5 4 operand instructions that are the comparison instructions | |
4828 | where the first operand is the immediate value of the comparison | |
4829 | to be done. */ | |
4830 | else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4) | |
4831 | { | |
4832 | /* Case 1: 4 operand insn, src1 = reg/memory. */ | |
4833 | if (operand_type_check (i.types[0], imm) != 0 | |
4834 | && (i.types[1].bitfield.regxmm | |
4835 | || operand_type_check (i.types[1], anymem)) | |
4836 | && i.types[2].bitfield.regxmm != 0 | |
4837 | && i.types[3].bitfield.regxmm != 0) | |
4838 | { | |
4839 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 | 4840 | operand_type_set (&i.types[3], 0); |
85f10a01 MM |
4841 | i.reg_operands--; |
4842 | ||
4843 | /* Specify the modrm encoding and remember the register | |
4844 | including the high bit normally stored in the REX byte. */ | |
4845 | i.drex.modrm_reg = 2; | |
4846 | i.drex.modrm_regmem = 1; | |
4847 | i.drex.reg = (i.op[3].regs->reg_num | |
4848 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4849 | } | |
4850 | ||
4851 | /* Case 2: 3 operand insn with ImmExt that places the | |
4852 | opcode_extension as an immediate argument. This is used for | |
4853 | all of the varients of comparison that supplies the appropriate | |
4854 | value as part of the instruction. */ | |
4855 | else if ((i.types[0].bitfield.regxmm | |
4856 | || operand_type_check (i.types[0], anymem)) | |
4857 | && i.types[1].bitfield.regxmm != 0 | |
4858 | && i.types[2].bitfield.regxmm != 0 | |
4859 | && operand_type_check (i.types[3], imm) != 0) | |
4860 | { | |
4861 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 | 4862 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4863 | i.reg_operands--; |
4864 | ||
4865 | /* Specify the modrm encoding and remember the register | |
4866 | including the high bit normally stored in the REX byte. */ | |
4867 | i.drex.modrm_reg = 1; | |
4868 | i.drex.modrm_regmem = 0; | |
4869 | i.drex.reg = (i.op[2].regs->reg_num | |
4870 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4871 | } | |
4872 | ||
4873 | else | |
4874 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4875 | i.tm.name); | |
4876 | } | |
4877 | ||
4878 | else if (i.tm.opcode_modifier.drex | |
4879 | || i.tm.opcode_modifier.drexv | |
4880 | || i.tm.opcode_modifier.drexc) | |
4881 | as_bad (_("Internal error for the '%s' instruction"), i.tm.name); | |
4882 | } | |
4883 | ||
c0f3af97 L |
4884 | static int |
4885 | bad_implicit_operand (int xmm) | |
4886 | { | |
4887 | const char *reg = xmm ? "xmm0" : "ymm0"; | |
4888 | if (intel_syntax) | |
4889 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
4890 | i.tm.name, register_prefix, reg); | |
4891 | else | |
4892 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
4893 | i.tm.name, register_prefix, reg); | |
4894 | return 0; | |
4895 | } | |
4896 | ||
29b0f896 | 4897 | static int |
e3bb37b5 | 4898 | process_operands (void) |
29b0f896 AM |
4899 | { |
4900 | /* Default segment register this instruction will use for memory | |
4901 | accesses. 0 means unknown. This is only for optimizing out | |
4902 | unnecessary segment overrides. */ | |
4903 | const seg_entry *default_seg = 0; | |
4904 | ||
85f10a01 MM |
4905 | /* Handle all of the DREX munging that SSE5 needs. */ |
4906 | if (i.tm.opcode_modifier.drex | |
4907 | || i.tm.opcode_modifier.drexv | |
4908 | || i.tm.opcode_modifier.drexc) | |
4909 | process_drex (); | |
4910 | ||
c0f3af97 L |
4911 | if (i.tm.opcode_modifier.sse2avx |
4912 | && (i.tm.opcode_modifier.vexnds | |
4913 | || i.tm.opcode_modifier.vexndd)) | |
29b0f896 | 4914 | { |
c0f3af97 L |
4915 | unsigned int dup = i.operands; |
4916 | unsigned int dest = dup - 1; | |
9fcfb3d7 L |
4917 | unsigned int j; |
4918 | ||
c0f3af97 | 4919 | /* The destination must be an xmm register. */ |
0dfbf9d7 | 4920 | assert (i.reg_operands |
c0f3af97 L |
4921 | && MAX_OPERANDS > dup |
4922 | && operand_type_equal (&i.types[dest], ®xmm)); | |
4923 | ||
4924 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 4925 | { |
c0f3af97 L |
4926 | /* The first operand is implicit and must be xmm0. */ |
4927 | assert (operand_type_equal (&i.types[0], ®xmm)); | |
4928 | if (i.op[0].regs->reg_num != 0) | |
4929 | return bad_implicit_operand (1); | |
4930 | ||
4931 | if (i.tm.opcode_modifier.vex3sources) | |
4932 | { | |
4933 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
4934 | sources. */ | |
4935 | goto duplicate; | |
4936 | } | |
e2ec9d29 | 4937 | else |
c0f3af97 L |
4938 | { |
4939 | /* We remove the first xmm0 and keep the number of | |
4940 | operands unchanged, which in fact duplicates the | |
4941 | destination. */ | |
4942 | for (j = 1; j < i.operands; j++) | |
4943 | { | |
4944 | i.op[j - 1] = i.op[j]; | |
4945 | i.types[j - 1] = i.types[j]; | |
4946 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
4947 | } | |
4948 | } | |
4949 | } | |
4950 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
4951 | { | |
4952 | assert ((MAX_OPERANDS - 1) > dup | |
4953 | && i.tm.opcode_modifier.vex3sources); | |
4954 | ||
4955 | /* Add the implicit xmm0 for instructions with VEX prefix | |
4956 | and 3 sources. */ | |
4957 | for (j = i.operands; j > 0; j--) | |
4958 | { | |
4959 | i.op[j] = i.op[j - 1]; | |
4960 | i.types[j] = i.types[j - 1]; | |
4961 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
4962 | } | |
4963 | i.op[0].regs | |
4964 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
4965 | i.types[0] = regxmm; | |
4966 | i.tm.operand_types[0] = regxmm; | |
4967 | ||
4968 | i.operands += 2; | |
4969 | i.reg_operands += 2; | |
4970 | i.tm.operands += 2; | |
4971 | ||
4972 | dup++; | |
4973 | dest++; | |
4974 | i.op[dup] = i.op[dest]; | |
4975 | i.types[dup] = i.types[dest]; | |
4976 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
e2ec9d29 | 4977 | } |
c0f3af97 L |
4978 | else |
4979 | { | |
4980 | duplicate: | |
4981 | i.operands++; | |
4982 | i.reg_operands++; | |
4983 | i.tm.operands++; | |
4984 | ||
4985 | i.op[dup] = i.op[dest]; | |
4986 | i.types[dup] = i.types[dest]; | |
4987 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
4988 | } | |
4989 | ||
4990 | if (i.tm.opcode_modifier.immext) | |
4991 | process_immext (); | |
4992 | } | |
4993 | else if (i.tm.opcode_modifier.firstxmm0) | |
4994 | { | |
4995 | unsigned int j; | |
4996 | ||
4997 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
4998 | assert (i.reg_operands | |
4999 | && (operand_type_equal (&i.types[0], ®xmm) | |
5000 | || operand_type_equal (&i.types[0], ®ymm))); | |
5001 | if (i.op[0].regs->reg_num != 0) | |
5002 | return bad_implicit_operand (i.types[0].bitfield.regxmm); | |
9fcfb3d7 L |
5003 | |
5004 | for (j = 1; j < i.operands; j++) | |
5005 | { | |
5006 | i.op[j - 1] = i.op[j]; | |
5007 | i.types[j - 1] = i.types[j]; | |
5008 | ||
5009 | /* We need to adjust fields in i.tm since they are used by | |
5010 | build_modrm_byte. */ | |
5011 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
5012 | } | |
5013 | ||
e2ec9d29 L |
5014 | i.operands--; |
5015 | i.reg_operands--; | |
e2ec9d29 L |
5016 | i.tm.operands--; |
5017 | } | |
5018 | else if (i.tm.opcode_modifier.regkludge) | |
5019 | { | |
5020 | /* The imul $imm, %reg instruction is converted into | |
5021 | imul $imm, %reg, %reg, and the clr %reg instruction | |
5022 | is converted into xor %reg, %reg. */ | |
5023 | ||
5024 | unsigned int first_reg_op; | |
5025 | ||
5026 | if (operand_type_check (i.types[0], reg)) | |
5027 | first_reg_op = 0; | |
5028 | else | |
5029 | first_reg_op = 1; | |
5030 | /* Pretend we saw the extra register operand. */ | |
5031 | assert (i.reg_operands == 1 | |
5032 | && i.op[first_reg_op + 1].regs == 0); | |
5033 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
5034 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
5035 | i.operands++; | |
5036 | i.reg_operands++; | |
29b0f896 AM |
5037 | } |
5038 | ||
40fb9820 | 5039 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 5040 | { |
40fb9820 L |
5041 | if (i.types[0].bitfield.sreg2 |
5042 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 5043 | { |
4eed87de AM |
5044 | if (i.tm.base_opcode == POP_SEG_SHORT |
5045 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 5046 | { |
a87af027 | 5047 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 5048 | return 0; |
29b0f896 | 5049 | } |
4eed87de AM |
5050 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
5051 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5052 | i.rex |= REX_B; |
4eed87de AM |
5053 | } |
5054 | else | |
5055 | { | |
85f10a01 MM |
5056 | /* The register or float register operand is in operand |
5057 | 0 or 1. */ | |
40fb9820 L |
5058 | unsigned int op; |
5059 | ||
5060 | if (i.types[0].bitfield.floatreg | |
5061 | || operand_type_check (i.types[0], reg)) | |
5062 | op = 0; | |
5063 | else | |
5064 | op = 1; | |
4eed87de AM |
5065 | /* Register goes in low 3 bits of opcode. */ |
5066 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
5067 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5068 | i.rex |= REX_B; |
40fb9820 | 5069 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 5070 | { |
4eed87de AM |
5071 | /* Warn about some common errors, but press on regardless. |
5072 | The first case can be generated by gcc (<= 2.8.1). */ | |
5073 | if (i.operands == 2) | |
5074 | { | |
5075 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 5076 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
5077 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
5078 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
5079 | } |
5080 | else | |
5081 | { | |
5082 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
5083 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
5084 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 5085 | } |
29b0f896 AM |
5086 | } |
5087 | } | |
5088 | } | |
40fb9820 | 5089 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5090 | { |
5091 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
5092 | must be put into the modrm byte). Now, we make the modrm and |
5093 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
5094 | |
5095 | default_seg = build_modrm_byte (); | |
5096 | } | |
8a2ed489 | 5097 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
5098 | { |
5099 | default_seg = &ds; | |
5100 | } | |
40fb9820 | 5101 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
5102 | { |
5103 | /* For the string instructions that allow a segment override | |
5104 | on one of their operands, the default segment is ds. */ | |
5105 | default_seg = &ds; | |
5106 | } | |
5107 | ||
75178d9d L |
5108 | if (i.tm.base_opcode == 0x8d /* lea */ |
5109 | && i.seg[0] | |
5110 | && !quiet_warnings) | |
30123838 | 5111 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
5112 | |
5113 | /* If a segment was explicitly specified, and the specified segment | |
5114 | is not the default, use an opcode prefix to select it. If we | |
5115 | never figured out what the default segment is, then default_seg | |
5116 | will be zero at this point, and the specified segment prefix will | |
5117 | always be used. */ | |
29b0f896 AM |
5118 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
5119 | { | |
5120 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
5121 | return 0; | |
5122 | } | |
5123 | return 1; | |
5124 | } | |
5125 | ||
5126 | static const seg_entry * | |
e3bb37b5 | 5127 | build_modrm_byte (void) |
29b0f896 AM |
5128 | { |
5129 | const seg_entry *default_seg = 0; | |
c0f3af97 L |
5130 | unsigned int source, dest; |
5131 | int vex_3_sources; | |
5132 | ||
5133 | /* The first operand of instructions with VEX prefix and 3 sources | |
5134 | must be VEX_Imm4. */ | |
5135 | vex_3_sources = i.tm.opcode_modifier.vex3sources; | |
5136 | if (vex_3_sources) | |
5137 | { | |
5138 | unsigned int nds, reg; | |
5139 | ||
0bfee649 | 5140 | dest = i.operands - 1; |
c0f3af97 | 5141 | nds = dest - 1; |
0bfee649 L |
5142 | source = 1; |
5143 | reg = 0; | |
5144 | ||
5145 | /* This instruction must have 4 operands: 4 register operands | |
5146 | or 3 register operands plus 1 memory operand. It must have | |
5147 | VexNDS and VexImmExt. */ | |
5148 | assert (i.operands == 4 | |
5149 | && (i.reg_operands == 4 | |
5150 | || (i.reg_operands == 3 && i.mem_operands == 1)) | |
5151 | && i.tm.opcode_modifier.vexnds | |
5152 | && i.tm.opcode_modifier.veximmext | |
5153 | && (operand_type_equal (&i.tm.operand_types[dest], | |
5154 | ®xmm) | |
5155 | || operand_type_equal (&i.tm.operand_types[dest], | |
5156 | ®ymm)) | |
5157 | && (operand_type_equal (&i.tm.operand_types[nds], | |
5158 | ®xmm) | |
5159 | || operand_type_equal (&i.tm.operand_types[nds], | |
5160 | ®ymm)) | |
5161 | && (operand_type_equal (&i.tm.operand_types[reg], | |
5162 | ®xmm) | |
c0f3af97 | 5163 | || operand_type_equal (&i.tm.operand_types[reg], |
0bfee649 | 5164 | ®ymm))); |
c0f3af97 | 5165 | |
0bfee649 L |
5166 | /* Generate an 8bit immediate operand to encode the register |
5167 | operand. */ | |
5168 | expressionS *exp = &im_expressions[i.imm_operands++]; | |
5169 | i.op[i.operands].imms = exp; | |
5170 | i.types[i.operands] = imm8; | |
5171 | i.operands++; | |
5172 | exp->X_op = O_constant; | |
5173 | exp->X_add_number | |
5174 | = ((i.op[0].regs->reg_num | |
5175 | + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4); | |
dae39acc | 5176 | |
dae39acc | 5177 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
5178 | } |
5179 | else | |
5180 | source = dest = 0; | |
29b0f896 | 5181 | |
85f10a01 MM |
5182 | /* SSE5 4 operand instructions are encoded in such a way that one of |
5183 | the inputs must match the destination register. Process_drex hides | |
5184 | the 3rd argument in the drex field, so that by the time we get | |
5185 | here, it looks to GAS as if this is a 2 operand instruction. */ | |
5186 | if ((i.tm.opcode_modifier.drex | |
5187 | || i.tm.opcode_modifier.drexv | |
b5016f89 | 5188 | || i.tm.opcode_modifier.drexc) |
85f10a01 MM |
5189 | && i.reg_operands == 2) |
5190 | { | |
5191 | const reg_entry *reg = i.op[i.drex.modrm_reg].regs; | |
5192 | const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs; | |
5193 | ||
5194 | i.rm.reg = reg->reg_num; | |
5195 | i.rm.regmem = regmem->reg_num; | |
5196 | i.rm.mode = 3; | |
5197 | if ((reg->reg_flags & RegRex) != 0) | |
5198 | i.rex |= REX_R; | |
5199 | if ((regmem->reg_flags & RegRex) != 0) | |
5200 | i.rex |= REX_B; | |
5201 | } | |
5202 | ||
29b0f896 | 5203 | /* i.reg_operands MUST be the number of real register operands; |
c0f3af97 L |
5204 | implicit registers do not count. If there are 3 register |
5205 | operands, it must be a instruction with VexNDS. For a | |
5206 | instruction with VexNDD, the destination register is encoded | |
5207 | in VEX prefix. If there are 4 register operands, it must be | |
5208 | a instruction with VEX prefix and 3 sources. */ | |
5209 | else if (i.mem_operands == 0 | |
5210 | && ((i.reg_operands == 2 | |
5211 | && !i.tm.opcode_modifier.vexndd) | |
5212 | || (i.reg_operands == 3 | |
5213 | && i.tm.opcode_modifier.vexnds) | |
5214 | || (i.reg_operands == 4 && vex_3_sources))) | |
29b0f896 | 5215 | { |
cab737b9 L |
5216 | switch (i.operands) |
5217 | { | |
5218 | case 2: | |
5219 | source = 0; | |
5220 | break; | |
5221 | case 3: | |
c81128dc L |
5222 | /* When there are 3 operands, one of them may be immediate, |
5223 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
5224 | the first operand must be shift count register (cl) or it |
5225 | is an instruction with VexNDS. */ | |
c81128dc L |
5226 | assert (i.imm_operands == 1 |
5227 | || (i.imm_operands == 0 | |
c0f3af97 L |
5228 | && (i.tm.opcode_modifier.vexnds |
5229 | || i.types[0].bitfield.shiftcount))); | |
40fb9820 L |
5230 | if (operand_type_check (i.types[0], imm) |
5231 | || i.types[0].bitfield.shiftcount) | |
5232 | source = 1; | |
5233 | else | |
5234 | source = 0; | |
cab737b9 L |
5235 | break; |
5236 | case 4: | |
368d64cc L |
5237 | /* When there are 4 operands, the first two must be 8bit |
5238 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
5239 | one. |
5240 | ||
5241 | For instructions with VexNDS, if the first operand | |
5242 | an imm8, the source operand is the 2nd one. If the last | |
5243 | operand is imm8, the source operand is the first one. */ | |
5244 | assert ((i.imm_operands == 2 | |
5245 | && i.types[0].bitfield.imm8 | |
5246 | && i.types[1].bitfield.imm8) | |
5247 | || (i.tm.opcode_modifier.vexnds | |
5248 | && i.imm_operands == 1 | |
5249 | && (i.types[0].bitfield.imm8 | |
5250 | || i.types[i.operands - 1].bitfield.imm8))); | |
5251 | if (i.tm.opcode_modifier.vexnds) | |
5252 | { | |
5253 | if (i.types[0].bitfield.imm8) | |
5254 | source = 1; | |
5255 | else | |
5256 | source = 0; | |
5257 | } | |
5258 | else | |
5259 | source = 2; | |
5260 | break; | |
5261 | case 5: | |
cab737b9 L |
5262 | break; |
5263 | default: | |
5264 | abort (); | |
5265 | } | |
5266 | ||
c0f3af97 L |
5267 | if (!vex_3_sources) |
5268 | { | |
5269 | dest = source + 1; | |
5270 | ||
5271 | if (i.tm.opcode_modifier.vexnds) | |
5272 | { | |
5273 | /* For instructions with VexNDS, the register-only | |
5274 | source operand must be XMM or YMM register. It is | |
fa99fab2 L |
5275 | encoded in VEX prefix. We need to clear RegMem bit |
5276 | before calling operand_type_equal. */ | |
5277 | i386_operand_type op = i.tm.operand_types[dest]; | |
5278 | op.bitfield.regmem = 0; | |
c0f3af97 | 5279 | if ((dest + 1) >= i.operands |
fa99fab2 L |
5280 | || (!operand_type_equal (&op, ®xmm) |
5281 | && !operand_type_equal (&op, ®ymm))) | |
c0f3af97 L |
5282 | abort (); |
5283 | i.vex.register_specifier = i.op[dest].regs; | |
5284 | dest++; | |
5285 | } | |
5286 | } | |
29b0f896 AM |
5287 | |
5288 | i.rm.mode = 3; | |
5289 | /* One of the register operands will be encoded in the i.tm.reg | |
5290 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5291 | fields. If no form of this instruction supports a memory | |
5292 | destination operand, then we assume the source operand may | |
5293 | sometimes be a memory operand and so we need to store the | |
5294 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5295 | if (!i.tm.operand_types[dest].bitfield.regmem |
5296 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5297 | { |
5298 | i.rm.reg = i.op[dest].regs->reg_num; | |
5299 | i.rm.regmem = i.op[source].regs->reg_num; | |
5300 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5301 | i.rex |= REX_R; |
29b0f896 | 5302 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5303 | i.rex |= REX_B; |
29b0f896 AM |
5304 | } |
5305 | else | |
5306 | { | |
5307 | i.rm.reg = i.op[source].regs->reg_num; | |
5308 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5309 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5310 | i.rex |= REX_B; |
29b0f896 | 5311 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5312 | i.rex |= REX_R; |
29b0f896 | 5313 | } |
161a04f6 | 5314 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5315 | { |
40fb9820 L |
5316 | if (!i.types[0].bitfield.control |
5317 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5318 | abort (); |
161a04f6 | 5319 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5320 | add_prefix (LOCK_PREFIX_OPCODE); |
5321 | } | |
29b0f896 AM |
5322 | } |
5323 | else | |
5324 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5325 | unsigned int mem; |
5326 | ||
29b0f896 AM |
5327 | if (i.mem_operands) |
5328 | { | |
5329 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5330 | unsigned int op; |
4eed87de | 5331 | |
85f10a01 MM |
5332 | /* This has been precalculated for SSE5 instructions |
5333 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
5334 | if (i.tm.opcode_modifier.drex |
5335 | || i.tm.opcode_modifier.drexv | |
5336 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
5337 | op = i.drex.modrm_regmem; |
5338 | else | |
5339 | { | |
c0209578 L |
5340 | for (op = 0; op < i.operands; op++) |
5341 | if (operand_type_check (i.types[op], anymem)) | |
5342 | break; | |
5343 | assert (op < i.operands); | |
85f10a01 | 5344 | } |
29b0f896 AM |
5345 | |
5346 | default_seg = &ds; | |
5347 | ||
5348 | if (i.base_reg == 0) | |
5349 | { | |
5350 | i.rm.mode = 0; | |
5351 | if (!i.disp_operands) | |
5352 | fake_zero_displacement = 1; | |
5353 | if (i.index_reg == 0) | |
5354 | { | |
5355 | /* Operand is just <disp> */ | |
20f0a1fc | 5356 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5357 | { |
5358 | /* 64bit mode overwrites the 32bit absolute | |
5359 | addressing by RIP relative addressing and | |
5360 | absolute addressing is encoded by one of the | |
5361 | redundant SIB forms. */ | |
5362 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5363 | i.sib.base = NO_BASE_REGISTER; | |
5364 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5365 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5366 | ? disp32s : disp32); |
20f0a1fc | 5367 | } |
fc225355 L |
5368 | else if ((flag_code == CODE_16BIT) |
5369 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5370 | { |
5371 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5372 | i.types[op] = disp16; |
20f0a1fc NC |
5373 | } |
5374 | else | |
5375 | { | |
5376 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5377 | i.types[op] = disp32; |
29b0f896 AM |
5378 | } |
5379 | } | |
5380 | else /* !i.base_reg && i.index_reg */ | |
5381 | { | |
db51cc60 L |
5382 | if (i.index_reg->reg_num == RegEiz |
5383 | || i.index_reg->reg_num == RegRiz) | |
5384 | i.sib.index = NO_INDEX_REGISTER; | |
5385 | else | |
5386 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5387 | i.sib.base = NO_BASE_REGISTER; |
5388 | i.sib.scale = i.log2_scale_factor; | |
5389 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5390 | i.types[op].bitfield.disp8 = 0; |
5391 | i.types[op].bitfield.disp16 = 0; | |
5392 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5393 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5394 | { |
5395 | /* Must be 32 bit */ | |
5396 | i.types[op].bitfield.disp32 = 1; | |
5397 | i.types[op].bitfield.disp32s = 0; | |
5398 | } | |
29b0f896 | 5399 | else |
40fb9820 L |
5400 | { |
5401 | i.types[op].bitfield.disp32 = 0; | |
5402 | i.types[op].bitfield.disp32s = 1; | |
5403 | } | |
29b0f896 | 5404 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5405 | i.rex |= REX_X; |
29b0f896 AM |
5406 | } |
5407 | } | |
5408 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5409 | else if (i.base_reg->reg_num == RegRip || |
5410 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
5411 | { |
5412 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
5413 | i.types[op].bitfield.disp8 = 0; |
5414 | i.types[op].bitfield.disp16 = 0; | |
5415 | i.types[op].bitfield.disp32 = 0; | |
5416 | i.types[op].bitfield.disp32s = 1; | |
5417 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5418 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5419 | if (! i.disp_operands) |
5420 | fake_zero_displacement = 1; | |
29b0f896 | 5421 | } |
40fb9820 | 5422 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
5423 | { |
5424 | switch (i.base_reg->reg_num) | |
5425 | { | |
5426 | case 3: /* (%bx) */ | |
5427 | if (i.index_reg == 0) | |
5428 | i.rm.regmem = 7; | |
5429 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5430 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5431 | break; | |
5432 | case 5: /* (%bp) */ | |
5433 | default_seg = &ss; | |
5434 | if (i.index_reg == 0) | |
5435 | { | |
5436 | i.rm.regmem = 6; | |
40fb9820 | 5437 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5438 | { |
5439 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5440 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5441 | fake_zero_displacement = 1; |
29b0f896 AM |
5442 | } |
5443 | } | |
5444 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5445 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5446 | break; | |
5447 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5448 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5449 | } | |
5450 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5451 | } | |
5452 | else /* i.base_reg and 32/64 bit mode */ | |
5453 | { | |
5454 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5455 | && operand_type_check (i.types[op], disp)) |
5456 | { | |
5457 | i386_operand_type temp; | |
0dfbf9d7 | 5458 | operand_type_set (&temp, 0); |
40fb9820 L |
5459 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5460 | i.types[op] = temp; | |
5461 | if (i.prefix[ADDR_PREFIX] == 0) | |
5462 | i.types[op].bitfield.disp32s = 1; | |
5463 | else | |
5464 | i.types[op].bitfield.disp32 = 1; | |
5465 | } | |
20f0a1fc | 5466 | |
29b0f896 AM |
5467 | i.rm.regmem = i.base_reg->reg_num; |
5468 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5469 | i.rex |= REX_B; |
29b0f896 AM |
5470 | i.sib.base = i.base_reg->reg_num; |
5471 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5472 | complications. */ | |
5473 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
5474 | { | |
5475 | default_seg = &ss; | |
5476 | if (i.disp_operands == 0) | |
5477 | { | |
5478 | fake_zero_displacement = 1; | |
40fb9820 | 5479 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
5480 | } |
5481 | } | |
5482 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
5483 | { | |
5484 | default_seg = &ss; | |
5485 | } | |
5486 | i.sib.scale = i.log2_scale_factor; | |
5487 | if (i.index_reg == 0) | |
5488 | { | |
5489 | /* <disp>(%esp) becomes two byte modrm with no index | |
5490 | register. We've already stored the code for esp | |
5491 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5492 | Any base register besides %esp will not use the | |
5493 | extra modrm byte. */ | |
5494 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
5495 | } |
5496 | else | |
5497 | { | |
db51cc60 L |
5498 | if (i.index_reg->reg_num == RegEiz |
5499 | || i.index_reg->reg_num == RegRiz) | |
5500 | i.sib.index = NO_INDEX_REGISTER; | |
5501 | else | |
5502 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5503 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5504 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5505 | i.rex |= REX_X; |
29b0f896 | 5506 | } |
67a4f2b7 AO |
5507 | |
5508 | if (i.disp_operands | |
5509 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5510 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5511 | i.rm.mode = 0; | |
5512 | else | |
5513 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 5514 | } |
252b5132 | 5515 | |
29b0f896 AM |
5516 | if (fake_zero_displacement) |
5517 | { | |
5518 | /* Fakes a zero displacement assuming that i.types[op] | |
5519 | holds the correct displacement size. */ | |
5520 | expressionS *exp; | |
5521 | ||
5522 | assert (i.op[op].disps == 0); | |
5523 | exp = &disp_expressions[i.disp_operands++]; | |
5524 | i.op[op].disps = exp; | |
5525 | exp->X_op = O_constant; | |
5526 | exp->X_add_number = 0; | |
5527 | exp->X_add_symbol = (symbolS *) 0; | |
5528 | exp->X_op_symbol = (symbolS *) 0; | |
5529 | } | |
c0f3af97 L |
5530 | |
5531 | mem = op; | |
29b0f896 | 5532 | } |
c0f3af97 L |
5533 | else |
5534 | mem = ~0; | |
252b5132 | 5535 | |
29b0f896 AM |
5536 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5537 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5538 | careful to make sure that segment/control/debug/test/MMX | |
5539 | registers are coded into the i.rm.reg field. */ | |
5540 | if (i.reg_operands) | |
5541 | { | |
99018f42 L |
5542 | unsigned int op; |
5543 | ||
85f10a01 MM |
5544 | /* This has been precalculated for SSE5 instructions |
5545 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
5546 | if (i.tm.opcode_modifier.drex |
5547 | || i.tm.opcode_modifier.drexv | |
5548 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
5549 | { |
5550 | op = i.drex.modrm_reg; | |
5551 | i.rm.reg = i.op[op].regs->reg_num; | |
5552 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5553 | i.rex |= REX_R; | |
5554 | } | |
5555 | else | |
5556 | { | |
c0f3af97 L |
5557 | unsigned int vex_reg = ~0; |
5558 | ||
c0209578 L |
5559 | for (op = 0; op < i.operands; op++) |
5560 | if (i.types[op].bitfield.reg8 | |
5561 | || i.types[op].bitfield.reg16 | |
5562 | || i.types[op].bitfield.reg32 | |
5563 | || i.types[op].bitfield.reg64 | |
5564 | || i.types[op].bitfield.regmmx | |
5565 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 5566 | || i.types[op].bitfield.regymm |
c0209578 L |
5567 | || i.types[op].bitfield.sreg2 |
5568 | || i.types[op].bitfield.sreg3 | |
5569 | || i.types[op].bitfield.control | |
5570 | || i.types[op].bitfield.debug | |
5571 | || i.types[op].bitfield.test) | |
5572 | break; | |
5573 | ||
c0f3af97 L |
5574 | if (vex_3_sources) |
5575 | op = dest; | |
5576 | else if (i.tm.opcode_modifier.vexnds) | |
5577 | { | |
5578 | /* For instructions with VexNDS, the register-only | |
5579 | source operand is encoded in VEX prefix. */ | |
5580 | assert (mem != (unsigned int) ~0); | |
5581 | ||
5582 | if (op > mem) | |
5583 | { | |
5584 | vex_reg = op++; | |
5585 | assert (op < i.operands); | |
5586 | } | |
5587 | else | |
5588 | { | |
5589 | vex_reg = op + 1; | |
5590 | assert (vex_reg < i.operands); | |
5591 | } | |
5592 | } | |
5593 | else if (i.tm.opcode_modifier.vexndd) | |
5594 | { | |
5595 | /* For instructions with VexNDD, there should be | |
5596 | no memory operand and the register destination | |
5597 | is encoded in VEX prefix. */ | |
5598 | assert (i.mem_operands == 0 | |
5599 | && (op + 2) == i.operands); | |
5600 | vex_reg = op + 1; | |
5601 | } | |
5602 | else | |
5603 | assert (op < i.operands); | |
5604 | ||
5605 | if (vex_reg != (unsigned int) ~0) | |
5606 | { | |
5607 | assert (i.reg_operands == 2); | |
5608 | ||
5609 | if (!operand_type_equal (&i.tm.operand_types[vex_reg], | |
5610 | & regxmm) | |
5611 | && !operand_type_equal (&i.tm.operand_types[vex_reg], | |
5612 | ®ymm)) | |
5613 | abort (); | |
5614 | i.vex.register_specifier = i.op[vex_reg].regs; | |
5615 | } | |
99018f42 | 5616 | |
85f10a01 MM |
5617 | /* If there is an extension opcode to put here, the |
5618 | register number must be put into the regmem field. */ | |
c0209578 L |
5619 | if (i.tm.extension_opcode != None) |
5620 | { | |
5621 | i.rm.regmem = i.op[op].regs->reg_num; | |
5622 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5623 | i.rex |= REX_B; | |
5624 | } | |
5625 | else | |
5626 | { | |
5627 | i.rm.reg = i.op[op].regs->reg_num; | |
5628 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5629 | i.rex |= REX_R; | |
5630 | } | |
85f10a01 | 5631 | } |
252b5132 | 5632 | |
29b0f896 AM |
5633 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
5634 | must set it to 3 to indicate this is a register operand | |
5635 | in the regmem field. */ | |
5636 | if (!i.mem_operands) | |
5637 | i.rm.mode = 3; | |
5638 | } | |
252b5132 | 5639 | |
29b0f896 | 5640 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
85f10a01 MM |
5641 | if (i.tm.extension_opcode != None |
5642 | && !(i.tm.opcode_modifier.drex | |
5643 | || i.tm.opcode_modifier.drexv | |
5644 | || i.tm.opcode_modifier.drexc)) | |
29b0f896 AM |
5645 | i.rm.reg = i.tm.extension_opcode; |
5646 | } | |
5647 | return default_seg; | |
5648 | } | |
252b5132 | 5649 | |
29b0f896 | 5650 | static void |
e3bb37b5 | 5651 | output_branch (void) |
29b0f896 AM |
5652 | { |
5653 | char *p; | |
5654 | int code16; | |
5655 | int prefix; | |
5656 | relax_substateT subtype; | |
5657 | symbolS *sym; | |
5658 | offsetT off; | |
5659 | ||
5660 | code16 = 0; | |
5661 | if (flag_code == CODE_16BIT) | |
5662 | code16 = CODE16; | |
5663 | ||
5664 | prefix = 0; | |
5665 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 5666 | { |
29b0f896 AM |
5667 | prefix = 1; |
5668 | i.prefixes -= 1; | |
5669 | code16 ^= CODE16; | |
252b5132 | 5670 | } |
29b0f896 AM |
5671 | /* Pentium4 branch hints. */ |
5672 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5673 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 5674 | { |
29b0f896 AM |
5675 | prefix++; |
5676 | i.prefixes--; | |
5677 | } | |
5678 | if (i.prefix[REX_PREFIX] != 0) | |
5679 | { | |
5680 | prefix++; | |
5681 | i.prefixes--; | |
2f66722d AM |
5682 | } |
5683 | ||
29b0f896 AM |
5684 | if (i.prefixes != 0 && !intel_syntax) |
5685 | as_warn (_("skipping prefixes on this instruction")); | |
5686 | ||
5687 | /* It's always a symbol; End frag & setup for relax. | |
5688 | Make sure there is enough room in this frag for the largest | |
5689 | instruction we may generate in md_convert_frag. This is 2 | |
5690 | bytes for the opcode and room for the prefix and largest | |
5691 | displacement. */ | |
5692 | frag_grow (prefix + 2 + 4); | |
5693 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
5694 | p = frag_more (prefix + 1); | |
5695 | if (i.prefix[DATA_PREFIX] != 0) | |
5696 | *p++ = DATA_PREFIX_OPCODE; | |
5697 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
5698 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
5699 | *p++ = i.prefix[SEG_PREFIX]; | |
5700 | if (i.prefix[REX_PREFIX] != 0) | |
5701 | *p++ = i.prefix[REX_PREFIX]; | |
5702 | *p = i.tm.base_opcode; | |
5703 | ||
5704 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
5705 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
40fb9820 | 5706 | else if (cpu_arch_flags.bitfield.cpui386) |
29b0f896 AM |
5707 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); |
5708 | else | |
5709 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
5710 | subtype |= code16; | |
3e73aa7c | 5711 | |
29b0f896 AM |
5712 | sym = i.op[0].disps->X_add_symbol; |
5713 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 5714 | |
29b0f896 AM |
5715 | if (i.op[0].disps->X_op != O_constant |
5716 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 5717 | { |
29b0f896 AM |
5718 | /* Handle complex expressions. */ |
5719 | sym = make_expr_symbol (i.op[0].disps); | |
5720 | off = 0; | |
5721 | } | |
3e73aa7c | 5722 | |
29b0f896 AM |
5723 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
5724 | Pass reloc in fr_var. */ | |
5725 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
5726 | } | |
3e73aa7c | 5727 | |
29b0f896 | 5728 | static void |
e3bb37b5 | 5729 | output_jump (void) |
29b0f896 AM |
5730 | { |
5731 | char *p; | |
5732 | int size; | |
3e02c1cc | 5733 | fixS *fixP; |
29b0f896 | 5734 | |
40fb9820 | 5735 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
5736 | { |
5737 | /* This is a loop or jecxz type instruction. */ | |
5738 | size = 1; | |
5739 | if (i.prefix[ADDR_PREFIX] != 0) | |
5740 | { | |
5741 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
5742 | i.prefixes -= 1; | |
5743 | } | |
5744 | /* Pentium4 branch hints. */ | |
5745 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5746 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
5747 | { | |
5748 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
5749 | i.prefixes--; | |
3e73aa7c JH |
5750 | } |
5751 | } | |
29b0f896 AM |
5752 | else |
5753 | { | |
5754 | int code16; | |
3e73aa7c | 5755 | |
29b0f896 AM |
5756 | code16 = 0; |
5757 | if (flag_code == CODE_16BIT) | |
5758 | code16 = CODE16; | |
3e73aa7c | 5759 | |
29b0f896 AM |
5760 | if (i.prefix[DATA_PREFIX] != 0) |
5761 | { | |
5762 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
5763 | i.prefixes -= 1; | |
5764 | code16 ^= CODE16; | |
5765 | } | |
252b5132 | 5766 | |
29b0f896 AM |
5767 | size = 4; |
5768 | if (code16) | |
5769 | size = 2; | |
5770 | } | |
9fcc94b6 | 5771 | |
29b0f896 AM |
5772 | if (i.prefix[REX_PREFIX] != 0) |
5773 | { | |
5774 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
5775 | i.prefixes -= 1; | |
5776 | } | |
252b5132 | 5777 | |
29b0f896 AM |
5778 | if (i.prefixes != 0 && !intel_syntax) |
5779 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 5780 | |
29b0f896 AM |
5781 | p = frag_more (1 + size); |
5782 | *p++ = i.tm.base_opcode; | |
e0890092 | 5783 | |
3e02c1cc AM |
5784 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5785 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
5786 | ||
5787 | /* All jumps handled here are signed, but don't use a signed limit | |
5788 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
5789 | 4G and 64k respectively. */ | |
5790 | if (size == 1) | |
5791 | fixP->fx_signed = 1; | |
29b0f896 | 5792 | } |
e0890092 | 5793 | |
29b0f896 | 5794 | static void |
e3bb37b5 | 5795 | output_interseg_jump (void) |
29b0f896 AM |
5796 | { |
5797 | char *p; | |
5798 | int size; | |
5799 | int prefix; | |
5800 | int code16; | |
252b5132 | 5801 | |
29b0f896 AM |
5802 | code16 = 0; |
5803 | if (flag_code == CODE_16BIT) | |
5804 | code16 = CODE16; | |
a217f122 | 5805 | |
29b0f896 AM |
5806 | prefix = 0; |
5807 | if (i.prefix[DATA_PREFIX] != 0) | |
5808 | { | |
5809 | prefix = 1; | |
5810 | i.prefixes -= 1; | |
5811 | code16 ^= CODE16; | |
5812 | } | |
5813 | if (i.prefix[REX_PREFIX] != 0) | |
5814 | { | |
5815 | prefix++; | |
5816 | i.prefixes -= 1; | |
5817 | } | |
252b5132 | 5818 | |
29b0f896 AM |
5819 | size = 4; |
5820 | if (code16) | |
5821 | size = 2; | |
252b5132 | 5822 | |
29b0f896 AM |
5823 | if (i.prefixes != 0 && !intel_syntax) |
5824 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 5825 | |
29b0f896 AM |
5826 | /* 1 opcode; 2 segment; offset */ |
5827 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 5828 | |
29b0f896 AM |
5829 | if (i.prefix[DATA_PREFIX] != 0) |
5830 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 5831 | |
29b0f896 AM |
5832 | if (i.prefix[REX_PREFIX] != 0) |
5833 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 5834 | |
29b0f896 AM |
5835 | *p++ = i.tm.base_opcode; |
5836 | if (i.op[1].imms->X_op == O_constant) | |
5837 | { | |
5838 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 5839 | |
29b0f896 AM |
5840 | if (size == 2 |
5841 | && !fits_in_unsigned_word (n) | |
5842 | && !fits_in_signed_word (n)) | |
5843 | { | |
5844 | as_bad (_("16-bit jump out of range")); | |
5845 | return; | |
5846 | } | |
5847 | md_number_to_chars (p, n, size); | |
5848 | } | |
5849 | else | |
5850 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5851 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5852 | if (i.op[0].imms->X_op != O_constant) | |
5853 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5854 | i.tm.name); | |
5855 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5856 | } | |
a217f122 | 5857 | |
29b0f896 | 5858 | static void |
e3bb37b5 | 5859 | output_insn (void) |
29b0f896 | 5860 | { |
2bbd9c25 JJ |
5861 | fragS *insn_start_frag; |
5862 | offsetT insn_start_off; | |
5863 | ||
29b0f896 AM |
5864 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5865 | We can't do this after the insn has been output as the current | |
5866 | frag may have been closed off. eg. by frag_var. */ | |
5867 | dwarf2_emit_insn (0); | |
5868 | ||
2bbd9c25 JJ |
5869 | insn_start_frag = frag_now; |
5870 | insn_start_off = frag_now_fix (); | |
5871 | ||
29b0f896 | 5872 | /* Output jumps. */ |
40fb9820 | 5873 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5874 | output_branch (); |
40fb9820 L |
5875 | else if (i.tm.opcode_modifier.jumpbyte |
5876 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5877 | output_jump (); |
40fb9820 | 5878 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5879 | output_interseg_jump (); |
5880 | else | |
5881 | { | |
5882 | /* Output normal instructions here. */ | |
5883 | char *p; | |
5884 | unsigned char *q; | |
47465058 | 5885 | unsigned int j; |
331d2d0d | 5886 | unsigned int prefix; |
4dffcebc | 5887 | |
c0f3af97 L |
5888 | /* Since the VEX prefix contains the implicit prefix, we don't |
5889 | need the explicit prefix. */ | |
5890 | if (!i.tm.opcode_modifier.vex) | |
bc4bd9ab | 5891 | { |
c0f3af97 | 5892 | switch (i.tm.opcode_length) |
bc4bd9ab | 5893 | { |
c0f3af97 L |
5894 | case 3: |
5895 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 5896 | { |
c0f3af97 L |
5897 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
5898 | goto check_prefix; | |
5899 | } | |
5900 | break; | |
5901 | case 2: | |
5902 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
5903 | { | |
5904 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
5905 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
5906 | { | |
4dffcebc | 5907 | check_prefix: |
c0f3af97 L |
5908 | if (prefix != REPE_PREFIX_OPCODE |
5909 | || (i.prefix[LOCKREP_PREFIX] | |
5910 | != REPE_PREFIX_OPCODE)) | |
5911 | add_prefix (prefix); | |
5912 | } | |
5913 | else | |
4dffcebc L |
5914 | add_prefix (prefix); |
5915 | } | |
c0f3af97 L |
5916 | break; |
5917 | case 1: | |
5918 | break; | |
5919 | default: | |
5920 | abort (); | |
bc4bd9ab | 5921 | } |
c0f3af97 L |
5922 | |
5923 | /* The prefix bytes. */ | |
5924 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
5925 | if (*q) | |
5926 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 5927 | } |
252b5132 | 5928 | |
c0f3af97 L |
5929 | if (i.tm.opcode_modifier.vex) |
5930 | { | |
5931 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
5932 | if (*q) | |
5933 | switch (j) | |
5934 | { | |
5935 | case REX_PREFIX: | |
5936 | /* REX byte is encoded in VEX prefix. */ | |
5937 | break; | |
5938 | case SEG_PREFIX: | |
5939 | case ADDR_PREFIX: | |
5940 | FRAG_APPEND_1_CHAR (*q); | |
5941 | break; | |
5942 | default: | |
5943 | /* There should be no other prefixes for instructions | |
5944 | with VEX prefix. */ | |
5945 | abort (); | |
5946 | } | |
5947 | ||
5948 | /* Now the VEX prefix. */ | |
5949 | p = frag_more (i.vex.length); | |
5950 | for (j = 0; j < i.vex.length; j++) | |
5951 | p[j] = i.vex.bytes[j]; | |
5952 | } | |
252b5132 | 5953 | |
29b0f896 | 5954 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 5955 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
5956 | { |
5957 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
5958 | } | |
5959 | else | |
5960 | { | |
4dffcebc | 5961 | switch (i.tm.opcode_length) |
331d2d0d | 5962 | { |
4dffcebc | 5963 | case 3: |
331d2d0d L |
5964 | p = frag_more (3); |
5965 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
5966 | break; |
5967 | case 2: | |
5968 | p = frag_more (2); | |
5969 | break; | |
5970 | default: | |
5971 | abort (); | |
5972 | break; | |
331d2d0d | 5973 | } |
0f10071e | 5974 | |
29b0f896 AM |
5975 | /* Put out high byte first: can't use md_number_to_chars! */ |
5976 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
5977 | *p = i.tm.base_opcode & 0xff; | |
85f10a01 MM |
5978 | |
5979 | /* On SSE5, encode the OC1 bit in the DREX field if this | |
5980 | encoding has multiple formats. */ | |
5981 | if (i.tm.opcode_modifier.drex | |
5982 | && i.tm.opcode_modifier.drexv | |
5983 | && DREX_OC1 (i.tm.extension_opcode)) | |
5984 | *p |= DREX_OC1_MASK; | |
29b0f896 | 5985 | } |
3e73aa7c | 5986 | |
29b0f896 | 5987 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 5988 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 5989 | { |
4a3523fa L |
5990 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
5991 | | i.rm.reg << 3 | |
5992 | | i.rm.mode << 6)); | |
29b0f896 AM |
5993 | /* If i.rm.regmem == ESP (4) |
5994 | && i.rm.mode != (Register mode) | |
5995 | && not 16 bit | |
5996 | ==> need second modrm byte. */ | |
5997 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
5998 | && i.rm.mode != 3 | |
40fb9820 | 5999 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
6000 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
6001 | | i.sib.index << 3 | |
6002 | | i.sib.scale << 6)); | |
29b0f896 | 6003 | } |
3e73aa7c | 6004 | |
85f10a01 MM |
6005 | /* Write the DREX byte if needed. */ |
6006 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
6007 | { | |
6008 | p = frag_more (1); | |
6009 | *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7)); | |
6010 | ||
6011 | /* Encode the OC0 bit if this encoding has multiple | |
6012 | formats. */ | |
6013 | if ((i.tm.opcode_modifier.drex | |
6014 | || i.tm.opcode_modifier.drexv) | |
6015 | && DREX_OC0 (i.tm.extension_opcode)) | |
6016 | *p |= DREX_OC0_MASK; | |
6017 | } | |
6018 | ||
29b0f896 | 6019 | if (i.disp_operands) |
2bbd9c25 | 6020 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 6021 | |
29b0f896 | 6022 | if (i.imm_operands) |
2bbd9c25 | 6023 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 6024 | } |
252b5132 | 6025 | |
29b0f896 AM |
6026 | #ifdef DEBUG386 |
6027 | if (flag_debug) | |
6028 | { | |
7b81dfbb | 6029 | pi ("" /*line*/, &i); |
29b0f896 AM |
6030 | } |
6031 | #endif /* DEBUG386 */ | |
6032 | } | |
252b5132 | 6033 | |
e205caa7 L |
6034 | /* Return the size of the displacement operand N. */ |
6035 | ||
6036 | static int | |
6037 | disp_size (unsigned int n) | |
6038 | { | |
6039 | int size = 4; | |
40fb9820 L |
6040 | if (i.types[n].bitfield.disp64) |
6041 | size = 8; | |
6042 | else if (i.types[n].bitfield.disp8) | |
6043 | size = 1; | |
6044 | else if (i.types[n].bitfield.disp16) | |
6045 | size = 2; | |
e205caa7 L |
6046 | return size; |
6047 | } | |
6048 | ||
6049 | /* Return the size of the immediate operand N. */ | |
6050 | ||
6051 | static int | |
6052 | imm_size (unsigned int n) | |
6053 | { | |
6054 | int size = 4; | |
40fb9820 L |
6055 | if (i.types[n].bitfield.imm64) |
6056 | size = 8; | |
6057 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
6058 | size = 1; | |
6059 | else if (i.types[n].bitfield.imm16) | |
6060 | size = 2; | |
e205caa7 L |
6061 | return size; |
6062 | } | |
6063 | ||
29b0f896 | 6064 | static void |
64e74474 | 6065 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6066 | { |
6067 | char *p; | |
6068 | unsigned int n; | |
252b5132 | 6069 | |
29b0f896 AM |
6070 | for (n = 0; n < i.operands; n++) |
6071 | { | |
40fb9820 | 6072 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
6073 | { |
6074 | if (i.op[n].disps->X_op == O_constant) | |
6075 | { | |
e205caa7 | 6076 | int size = disp_size (n); |
29b0f896 | 6077 | offsetT val; |
252b5132 | 6078 | |
29b0f896 AM |
6079 | val = offset_in_range (i.op[n].disps->X_add_number, |
6080 | size); | |
6081 | p = frag_more (size); | |
6082 | md_number_to_chars (p, val, size); | |
6083 | } | |
6084 | else | |
6085 | { | |
f86103b7 | 6086 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 6087 | int size = disp_size (n); |
40fb9820 | 6088 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
6089 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
6090 | ||
e205caa7 | 6091 | /* We can't have 8 bit displacement here. */ |
40fb9820 | 6092 | assert (!i.types[n].bitfield.disp8); |
e205caa7 | 6093 | |
29b0f896 AM |
6094 | /* The PC relative address is computed relative |
6095 | to the instruction boundary, so in case immediate | |
6096 | fields follows, we need to adjust the value. */ | |
6097 | if (pcrel && i.imm_operands) | |
6098 | { | |
29b0f896 | 6099 | unsigned int n1; |
e205caa7 | 6100 | int sz = 0; |
252b5132 | 6101 | |
29b0f896 | 6102 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 6103 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 6104 | { |
e205caa7 L |
6105 | /* Only one immediate is allowed for PC |
6106 | relative address. */ | |
6107 | assert (sz == 0); | |
6108 | sz = imm_size (n1); | |
6109 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 6110 | } |
29b0f896 | 6111 | /* We should find the immediate. */ |
e205caa7 | 6112 | assert (sz != 0); |
29b0f896 | 6113 | } |
520dc8e8 | 6114 | |
29b0f896 | 6115 | p = frag_more (size); |
2bbd9c25 | 6116 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 6117 | if (GOT_symbol |
2bbd9c25 | 6118 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 6119 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6120 | || reloc_type == BFD_RELOC_X86_64_32S |
6121 | || (reloc_type == BFD_RELOC_64 | |
6122 | && object_64bit)) | |
d6ab8113 JB |
6123 | && (i.op[n].disps->X_op == O_symbol |
6124 | || (i.op[n].disps->X_op == O_add | |
6125 | && ((symbol_get_value_expression | |
6126 | (i.op[n].disps->X_op_symbol)->X_op) | |
6127 | == O_subtract)))) | |
6128 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
6129 | { |
6130 | offsetT add; | |
6131 | ||
6132 | if (insn_start_frag == frag_now) | |
6133 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6134 | else | |
6135 | { | |
6136 | fragS *fr; | |
6137 | ||
6138 | add = insn_start_frag->fr_fix - insn_start_off; | |
6139 | for (fr = insn_start_frag->fr_next; | |
6140 | fr && fr != frag_now; fr = fr->fr_next) | |
6141 | add += fr->fr_fix; | |
6142 | add += p - frag_now->fr_literal; | |
6143 | } | |
6144 | ||
4fa24527 | 6145 | if (!object_64bit) |
7b81dfbb AJ |
6146 | { |
6147 | reloc_type = BFD_RELOC_386_GOTPC; | |
6148 | i.op[n].imms->X_add_number += add; | |
6149 | } | |
6150 | else if (reloc_type == BFD_RELOC_64) | |
6151 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 6152 | else |
7b81dfbb AJ |
6153 | /* Don't do the adjustment for x86-64, as there |
6154 | the pcrel addressing is relative to the _next_ | |
6155 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 6156 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 6157 | } |
062cd5e7 | 6158 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 6159 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
6160 | } |
6161 | } | |
6162 | } | |
6163 | } | |
252b5132 | 6164 | |
29b0f896 | 6165 | static void |
64e74474 | 6166 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6167 | { |
6168 | char *p; | |
6169 | unsigned int n; | |
252b5132 | 6170 | |
29b0f896 AM |
6171 | for (n = 0; n < i.operands; n++) |
6172 | { | |
40fb9820 | 6173 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
6174 | { |
6175 | if (i.op[n].imms->X_op == O_constant) | |
6176 | { | |
e205caa7 | 6177 | int size = imm_size (n); |
29b0f896 | 6178 | offsetT val; |
b4cac588 | 6179 | |
29b0f896 AM |
6180 | val = offset_in_range (i.op[n].imms->X_add_number, |
6181 | size); | |
6182 | p = frag_more (size); | |
6183 | md_number_to_chars (p, val, size); | |
6184 | } | |
6185 | else | |
6186 | { | |
6187 | /* Not absolute_section. | |
6188 | Need a 32-bit fixup (don't support 8bit | |
6189 | non-absolute imms). Try to support other | |
6190 | sizes ... */ | |
f86103b7 | 6191 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
6192 | int size = imm_size (n); |
6193 | int sign; | |
29b0f896 | 6194 | |
40fb9820 | 6195 | if (i.types[n].bitfield.imm32s |
a7d61044 | 6196 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 6197 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 6198 | sign = 1; |
e205caa7 L |
6199 | else |
6200 | sign = 0; | |
520dc8e8 | 6201 | |
29b0f896 AM |
6202 | p = frag_more (size); |
6203 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 6204 | |
2bbd9c25 JJ |
6205 | /* This is tough to explain. We end up with this one if we |
6206 | * have operands that look like | |
6207 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
6208 | * obtain the absolute address of the GOT, and it is strongly | |
6209 | * preferable from a performance point of view to avoid using | |
6210 | * a runtime relocation for this. The actual sequence of | |
6211 | * instructions often look something like: | |
6212 | * | |
6213 | * call .L66 | |
6214 | * .L66: | |
6215 | * popl %ebx | |
6216 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
6217 | * | |
6218 | * The call and pop essentially return the absolute address | |
6219 | * of the label .L66 and store it in %ebx. The linker itself | |
6220 | * will ultimately change the first operand of the addl so | |
6221 | * that %ebx points to the GOT, but to keep things simple, the | |
6222 | * .o file must have this operand set so that it generates not | |
6223 | * the absolute address of .L66, but the absolute address of | |
6224 | * itself. This allows the linker itself simply treat a GOTPC | |
6225 | * relocation as asking for a pcrel offset to the GOT to be | |
6226 | * added in, and the addend of the relocation is stored in the | |
6227 | * operand field for the instruction itself. | |
6228 | * | |
6229 | * Our job here is to fix the operand so that it would add | |
6230 | * the correct offset so that %ebx would point to itself. The | |
6231 | * thing that is tricky is that .-.L66 will point to the | |
6232 | * beginning of the instruction, so we need to further modify | |
6233 | * the operand so that it will point to itself. There are | |
6234 | * other cases where you have something like: | |
6235 | * | |
6236 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
6237 | * | |
6238 | * and here no correction would be required. Internally in | |
6239 | * the assembler we treat operands of this form as not being | |
6240 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
6241 | * whether it would simplify matters to do it this way. Who | |
6242 | * knows. In earlier versions of the PIC patches, the | |
6243 | * pcrel_adjust field was used to store the correction, but | |
6244 | * since the expression is not pcrel, I felt it would be | |
6245 | * confusing to do it this way. */ | |
6246 | ||
d6ab8113 | 6247 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6248 | || reloc_type == BFD_RELOC_X86_64_32S |
6249 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
6250 | && GOT_symbol |
6251 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
6252 | && (i.op[n].imms->X_op == O_symbol | |
6253 | || (i.op[n].imms->X_op == O_add | |
6254 | && ((symbol_get_value_expression | |
6255 | (i.op[n].imms->X_op_symbol)->X_op) | |
6256 | == O_subtract)))) | |
6257 | { | |
2bbd9c25 JJ |
6258 | offsetT add; |
6259 | ||
6260 | if (insn_start_frag == frag_now) | |
6261 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6262 | else | |
6263 | { | |
6264 | fragS *fr; | |
6265 | ||
6266 | add = insn_start_frag->fr_fix - insn_start_off; | |
6267 | for (fr = insn_start_frag->fr_next; | |
6268 | fr && fr != frag_now; fr = fr->fr_next) | |
6269 | add += fr->fr_fix; | |
6270 | add += p - frag_now->fr_literal; | |
6271 | } | |
6272 | ||
4fa24527 | 6273 | if (!object_64bit) |
d6ab8113 | 6274 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 6275 | else if (size == 4) |
d6ab8113 | 6276 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
6277 | else if (size == 8) |
6278 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 6279 | i.op[n].imms->X_add_number += add; |
29b0f896 | 6280 | } |
29b0f896 AM |
6281 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6282 | i.op[n].imms, 0, reloc_type); | |
6283 | } | |
6284 | } | |
6285 | } | |
252b5132 RH |
6286 | } |
6287 | \f | |
d182319b JB |
6288 | /* x86_cons_fix_new is called via the expression parsing code when a |
6289 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
6290 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
6291 | static int cons_sign = -1; | |
6292 | ||
6293 | void | |
e3bb37b5 | 6294 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 6295 | expressionS *exp) |
d182319b JB |
6296 | { |
6297 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
6298 | ||
6299 | got_reloc = NO_RELOC; | |
6300 | ||
6301 | #ifdef TE_PE | |
6302 | if (exp->X_op == O_secrel) | |
6303 | { | |
6304 | exp->X_op = O_symbol; | |
6305 | r = BFD_RELOC_32_SECREL; | |
6306 | } | |
6307 | #endif | |
6308 | ||
6309 | fix_new_exp (frag, off, len, exp, 0, r); | |
6310 | } | |
6311 | ||
718ddfc0 JB |
6312 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
6313 | # define lex_got(reloc, adjust, types) NULL | |
6314 | #else | |
f3c180ae AM |
6315 | /* Parse operands of the form |
6316 | <symbol>@GOTOFF+<nnn> | |
6317 | and similar .plt or .got references. | |
6318 | ||
6319 | If we find one, set up the correct relocation in RELOC and copy the | |
6320 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6321 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6322 | is non-null set it to the length of the string we removed from the | |
6323 | input line. Otherwise return NULL. */ | |
6324 | static char * | |
3956db08 | 6325 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 | 6326 | int *adjust, |
40fb9820 | 6327 | i386_operand_type *types) |
f3c180ae | 6328 | { |
7b81dfbb AJ |
6329 | /* Some of the relocations depend on the size of what field is to |
6330 | be relocated. But in our callers i386_immediate and i386_displacement | |
6331 | we don't yet know the operand size (this will be set by insn | |
6332 | matching). Hence we record the word32 relocation here, | |
6333 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6334 | static const struct { |
6335 | const char *str; | |
4fa24527 | 6336 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6337 | const i386_operand_type types64; |
f3c180ae | 6338 | } gotrel[] = { |
4eed87de AM |
6339 | { "PLTOFF", { 0, |
6340 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6341 | OPERAND_TYPE_IMM64 }, |
4eed87de AM |
6342 | { "PLT", { BFD_RELOC_386_PLT32, |
6343 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6344 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6345 | { "GOTPLT", { 0, |
6346 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6347 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6348 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, |
6349 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6350 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6351 | { "GOTPCREL", { 0, |
6352 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6353 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6354 | { "TLSGD", { BFD_RELOC_386_TLS_GD, |
6355 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6356 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6357 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, |
6358 | 0 }, | |
40fb9820 | 6359 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6360 | { "TLSLD", { 0, |
6361 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6362 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6363 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, |
6364 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6365 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6366 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, |
6367 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6368 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
6369 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, |
6370 | 0 }, | |
40fb9820 | 6371 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6372 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, |
6373 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 L |
6374 | |
6375 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
4eed87de AM |
6376 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, |
6377 | 0 }, | |
40fb9820 | 6378 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6379 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, |
6380 | 0 }, | |
40fb9820 | 6381 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6382 | { "GOT", { BFD_RELOC_386_GOT32, |
6383 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6384 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
4eed87de AM |
6385 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, |
6386 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6387 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6388 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, |
6389 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6390 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6391 | }; |
6392 | char *cp; | |
6393 | unsigned int j; | |
6394 | ||
718ddfc0 JB |
6395 | if (!IS_ELF) |
6396 | return NULL; | |
6397 | ||
f3c180ae | 6398 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6399 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6400 | return NULL; |
6401 | ||
47465058 | 6402 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae AM |
6403 | { |
6404 | int len; | |
6405 | ||
6406 | len = strlen (gotrel[j].str); | |
28f81592 | 6407 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6408 | { |
4fa24527 | 6409 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6410 | { |
28f81592 AM |
6411 | int first, second; |
6412 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6413 | |
4fa24527 | 6414 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6415 | if (adjust) |
6416 | *adjust = len; | |
f3c180ae | 6417 | |
3956db08 JB |
6418 | if (types) |
6419 | { | |
6420 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6421 | { |
6422 | types->bitfield.imm32 = 1; | |
6423 | types->bitfield.disp32 = 1; | |
6424 | } | |
3956db08 JB |
6425 | else |
6426 | *types = gotrel[j].types64; | |
6427 | } | |
6428 | ||
f3c180ae AM |
6429 | if (GOT_symbol == NULL) |
6430 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6431 | ||
28f81592 | 6432 | /* The length of the first part of our input line. */ |
f3c180ae | 6433 | first = cp - input_line_pointer; |
28f81592 AM |
6434 | |
6435 | /* The second part goes from after the reloc token until | |
67c11a9b | 6436 | (and including) an end_of_line char or comma. */ |
28f81592 | 6437 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6438 | cp = past_reloc; |
6439 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6440 | ++cp; | |
6441 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6442 | |
6443 | /* Allocate and copy string. The trailing NUL shouldn't | |
6444 | be necessary, but be safe. */ | |
6445 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae | 6446 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6447 | if (second != 0 && *past_reloc != ' ') |
6448 | /* Replace the relocation token with ' ', so that | |
6449 | errors like foo@GOTOFF1 will be detected. */ | |
6450 | tmpbuf[first++] = ' '; | |
6451 | memcpy (tmpbuf + first, past_reloc, second); | |
6452 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6453 | return tmpbuf; |
6454 | } | |
6455 | ||
4fa24527 JB |
6456 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6457 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6458 | return NULL; |
6459 | } | |
6460 | } | |
6461 | ||
6462 | /* Might be a symbol version string. Don't as_bad here. */ | |
6463 | return NULL; | |
6464 | } | |
6465 | ||
f3c180ae | 6466 | void |
e3bb37b5 | 6467 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6468 | { |
ee86248c JB |
6469 | intel_syntax = -intel_syntax; |
6470 | ||
4fa24527 | 6471 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6472 | { |
6473 | /* Handle @GOTOFF and the like in an expression. */ | |
6474 | char *save; | |
6475 | char *gotfree_input_line; | |
6476 | int adjust; | |
6477 | ||
6478 | save = input_line_pointer; | |
3956db08 | 6479 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6480 | if (gotfree_input_line) |
6481 | input_line_pointer = gotfree_input_line; | |
6482 | ||
6483 | expression (exp); | |
6484 | ||
6485 | if (gotfree_input_line) | |
6486 | { | |
6487 | /* expression () has merrily parsed up to the end of line, | |
6488 | or a comma - in the wrong buffer. Transfer how far | |
6489 | input_line_pointer has moved to the right buffer. */ | |
6490 | input_line_pointer = (save | |
6491 | + (input_line_pointer - gotfree_input_line) | |
6492 | + adjust); | |
6493 | free (gotfree_input_line); | |
3992d3b7 AM |
6494 | if (exp->X_op == O_constant |
6495 | || exp->X_op == O_absent | |
6496 | || exp->X_op == O_illegal | |
6497 | || exp->X_op == O_register | |
6498 | || exp->X_op == O_big) | |
6499 | { | |
6500 | char c = *input_line_pointer; | |
6501 | *input_line_pointer = 0; | |
6502 | as_bad (_("missing or invalid expression `%s'"), save); | |
6503 | *input_line_pointer = c; | |
6504 | } | |
f3c180ae AM |
6505 | } |
6506 | } | |
6507 | else | |
6508 | expression (exp); | |
ee86248c JB |
6509 | |
6510 | intel_syntax = -intel_syntax; | |
6511 | ||
6512 | if (intel_syntax) | |
6513 | i386_intel_simplify (exp); | |
f3c180ae AM |
6514 | } |
6515 | #endif | |
6516 | ||
d182319b | 6517 | static void signed_cons (int size) |
6482c264 | 6518 | { |
d182319b JB |
6519 | if (flag_code == CODE_64BIT) |
6520 | cons_sign = 1; | |
6521 | cons (size); | |
6522 | cons_sign = -1; | |
6482c264 NC |
6523 | } |
6524 | ||
d182319b | 6525 | #ifdef TE_PE |
6482c264 NC |
6526 | static void |
6527 | pe_directive_secrel (dummy) | |
6528 | int dummy ATTRIBUTE_UNUSED; | |
6529 | { | |
6530 | expressionS exp; | |
6531 | ||
6532 | do | |
6533 | { | |
6534 | expression (&exp); | |
6535 | if (exp.X_op == O_symbol) | |
6536 | exp.X_op = O_secrel; | |
6537 | ||
6538 | emit_expr (&exp, 4); | |
6539 | } | |
6540 | while (*input_line_pointer++ == ','); | |
6541 | ||
6542 | input_line_pointer--; | |
6543 | demand_empty_rest_of_line (); | |
6544 | } | |
6482c264 NC |
6545 | #endif |
6546 | ||
252b5132 | 6547 | static int |
70e41ade | 6548 | i386_immediate (char *imm_start) |
252b5132 RH |
6549 | { |
6550 | char *save_input_line_pointer; | |
f3c180ae | 6551 | char *gotfree_input_line; |
252b5132 | 6552 | segT exp_seg = 0; |
47926f60 | 6553 | expressionS *exp; |
40fb9820 L |
6554 | i386_operand_type types; |
6555 | ||
0dfbf9d7 | 6556 | operand_type_set (&types, ~0); |
252b5132 RH |
6557 | |
6558 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
6559 | { | |
31b2323c L |
6560 | as_bad (_("at most %d immediate operands are allowed"), |
6561 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
6562 | return 0; |
6563 | } | |
6564 | ||
6565 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 6566 | i.op[this_operand].imms = exp; |
252b5132 RH |
6567 | |
6568 | if (is_space_char (*imm_start)) | |
6569 | ++imm_start; | |
6570 | ||
6571 | save_input_line_pointer = input_line_pointer; | |
6572 | input_line_pointer = imm_start; | |
6573 | ||
3956db08 | 6574 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6575 | if (gotfree_input_line) |
6576 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
6577 | |
6578 | exp_seg = expression (exp); | |
6579 | ||
83183c0c | 6580 | SKIP_WHITESPACE (); |
252b5132 | 6581 | if (*input_line_pointer) |
f3c180ae | 6582 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
6583 | |
6584 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 6585 | if (gotfree_input_line) |
ee86248c JB |
6586 | { |
6587 | free (gotfree_input_line); | |
6588 | ||
6589 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
6590 | exp->X_op = O_illegal; | |
6591 | } | |
6592 | ||
6593 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
6594 | } | |
252b5132 | 6595 | |
ee86248c JB |
6596 | static int |
6597 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
6598 | i386_operand_type types, const char *imm_start) | |
6599 | { | |
6600 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 6601 | { |
3992d3b7 | 6602 | as_bad (_("missing or invalid immediate expression `%s'"), |
24eab124 | 6603 | imm_start); |
3992d3b7 | 6604 | return 0; |
252b5132 | 6605 | } |
3e73aa7c | 6606 | else if (exp->X_op == O_constant) |
252b5132 | 6607 | { |
47926f60 | 6608 | /* Size it properly later. */ |
40fb9820 | 6609 | i.types[this_operand].bitfield.imm64 = 1; |
3e73aa7c | 6610 | /* If BFD64, sign extend val. */ |
4eed87de AM |
6611 | if (!use_rela_relocations |
6612 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
6613 | exp->X_add_number | |
6614 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 6615 | } |
4c63da97 | 6616 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 6617 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 6618 | && exp_seg != absolute_section |
47926f60 | 6619 | && exp_seg != text_section |
24eab124 AM |
6620 | && exp_seg != data_section |
6621 | && exp_seg != bss_section | |
6622 | && exp_seg != undefined_section | |
f86103b7 | 6623 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 6624 | { |
d0b47220 | 6625 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
6626 | return 0; |
6627 | } | |
6628 | #endif | |
bb8f5920 L |
6629 | else if (!intel_syntax && exp->X_op == O_register) |
6630 | { | |
6631 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
6632 | return 0; | |
6633 | } | |
252b5132 RH |
6634 | else |
6635 | { | |
6636 | /* This is an address. The size of the address will be | |
24eab124 | 6637 | determined later, depending on destination register, |
3e73aa7c | 6638 | suffix, or the default for the section. */ |
40fb9820 L |
6639 | i.types[this_operand].bitfield.imm8 = 1; |
6640 | i.types[this_operand].bitfield.imm16 = 1; | |
6641 | i.types[this_operand].bitfield.imm32 = 1; | |
6642 | i.types[this_operand].bitfield.imm32s = 1; | |
6643 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
6644 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6645 | types); | |
252b5132 RH |
6646 | } |
6647 | ||
6648 | return 1; | |
6649 | } | |
6650 | ||
551c1ca1 | 6651 | static char * |
e3bb37b5 | 6652 | i386_scale (char *scale) |
252b5132 | 6653 | { |
551c1ca1 AM |
6654 | offsetT val; |
6655 | char *save = input_line_pointer; | |
252b5132 | 6656 | |
551c1ca1 AM |
6657 | input_line_pointer = scale; |
6658 | val = get_absolute_expression (); | |
6659 | ||
6660 | switch (val) | |
252b5132 | 6661 | { |
551c1ca1 | 6662 | case 1: |
252b5132 RH |
6663 | i.log2_scale_factor = 0; |
6664 | break; | |
551c1ca1 | 6665 | case 2: |
252b5132 RH |
6666 | i.log2_scale_factor = 1; |
6667 | break; | |
551c1ca1 | 6668 | case 4: |
252b5132 RH |
6669 | i.log2_scale_factor = 2; |
6670 | break; | |
551c1ca1 | 6671 | case 8: |
252b5132 RH |
6672 | i.log2_scale_factor = 3; |
6673 | break; | |
6674 | default: | |
a724f0f4 JB |
6675 | { |
6676 | char sep = *input_line_pointer; | |
6677 | ||
6678 | *input_line_pointer = '\0'; | |
6679 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6680 | scale); | |
6681 | *input_line_pointer = sep; | |
6682 | input_line_pointer = save; | |
6683 | return NULL; | |
6684 | } | |
252b5132 | 6685 | } |
29b0f896 | 6686 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
6687 | { |
6688 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 6689 | 1 << i.log2_scale_factor); |
252b5132 | 6690 | i.log2_scale_factor = 0; |
252b5132 | 6691 | } |
551c1ca1 AM |
6692 | scale = input_line_pointer; |
6693 | input_line_pointer = save; | |
6694 | return scale; | |
252b5132 RH |
6695 | } |
6696 | ||
252b5132 | 6697 | static int |
e3bb37b5 | 6698 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 6699 | { |
29b0f896 | 6700 | expressionS *exp; |
252b5132 RH |
6701 | segT exp_seg = 0; |
6702 | char *save_input_line_pointer; | |
f3c180ae | 6703 | char *gotfree_input_line; |
40fb9820 L |
6704 | int override; |
6705 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 6706 | int ret; |
252b5132 | 6707 | |
31b2323c L |
6708 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
6709 | { | |
6710 | as_bad (_("at most %d displacement operands are allowed"), | |
6711 | MAX_MEMORY_OPERANDS); | |
6712 | return 0; | |
6713 | } | |
6714 | ||
0dfbf9d7 | 6715 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
6716 | if ((i.types[this_operand].bitfield.jumpabsolute) |
6717 | || (!current_templates->start->opcode_modifier.jump | |
6718 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 6719 | { |
40fb9820 | 6720 | bigdisp.bitfield.disp32 = 1; |
e05278af | 6721 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
6722 | if (flag_code == CODE_64BIT) |
6723 | { | |
6724 | if (!override) | |
6725 | { | |
6726 | bigdisp.bitfield.disp32s = 1; | |
6727 | bigdisp.bitfield.disp64 = 1; | |
6728 | } | |
6729 | } | |
6730 | else if ((flag_code == CODE_16BIT) ^ override) | |
6731 | { | |
6732 | bigdisp.bitfield.disp32 = 0; | |
6733 | bigdisp.bitfield.disp16 = 1; | |
6734 | } | |
e05278af JB |
6735 | } |
6736 | else | |
6737 | { | |
6738 | /* For PC-relative branches, the width of the displacement | |
6739 | is dependent upon data size, not address size. */ | |
e05278af | 6740 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
6741 | if (flag_code == CODE_64BIT) |
6742 | { | |
6743 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
6744 | bigdisp.bitfield.disp16 = 1; | |
6745 | else | |
6746 | { | |
6747 | bigdisp.bitfield.disp32 = 1; | |
6748 | bigdisp.bitfield.disp32s = 1; | |
6749 | } | |
6750 | } | |
6751 | else | |
e05278af JB |
6752 | { |
6753 | if (!override) | |
6754 | override = (i.suffix == (flag_code != CODE_16BIT | |
6755 | ? WORD_MNEM_SUFFIX | |
6756 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
6757 | bigdisp.bitfield.disp32 = 1; |
6758 | if ((flag_code == CODE_16BIT) ^ override) | |
6759 | { | |
6760 | bigdisp.bitfield.disp32 = 0; | |
6761 | bigdisp.bitfield.disp16 = 1; | |
6762 | } | |
e05278af | 6763 | } |
e05278af | 6764 | } |
c6fb90c8 L |
6765 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6766 | bigdisp); | |
252b5132 RH |
6767 | |
6768 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 6769 | i.op[this_operand].disps = exp; |
252b5132 RH |
6770 | i.disp_operands++; |
6771 | save_input_line_pointer = input_line_pointer; | |
6772 | input_line_pointer = disp_start; | |
6773 | END_STRING_AND_SAVE (disp_end); | |
6774 | ||
6775 | #ifndef GCC_ASM_O_HACK | |
6776 | #define GCC_ASM_O_HACK 0 | |
6777 | #endif | |
6778 | #if GCC_ASM_O_HACK | |
6779 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 6780 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 6781 | && displacement_string_end[-1] == '+') |
252b5132 RH |
6782 | { |
6783 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
6784 | constraint within gcc asm statements. |
6785 | For instance: | |
6786 | ||
6787 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
6788 | __asm__ __volatile__ ( \ | |
6789 | "movw %w2,%0\n\t" \ | |
6790 | "movw %w1,2+%0\n\t" \ | |
6791 | "rorl $16,%1\n\t" \ | |
6792 | "movb %b1,4+%0\n\t" \ | |
6793 | "movb %4,5+%0\n\t" \ | |
6794 | "movb $0,6+%0\n\t" \ | |
6795 | "movb %h1,7+%0\n\t" \ | |
6796 | "rorl $16,%1" \ | |
6797 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
6798 | ||
6799 | This works great except that the output assembler ends | |
6800 | up looking a bit weird if it turns out that there is | |
6801 | no offset. You end up producing code that looks like: | |
6802 | ||
6803 | #APP | |
6804 | movw $235,(%eax) | |
6805 | movw %dx,2+(%eax) | |
6806 | rorl $16,%edx | |
6807 | movb %dl,4+(%eax) | |
6808 | movb $137,5+(%eax) | |
6809 | movb $0,6+(%eax) | |
6810 | movb %dh,7+(%eax) | |
6811 | rorl $16,%edx | |
6812 | #NO_APP | |
6813 | ||
47926f60 | 6814 | So here we provide the missing zero. */ |
24eab124 AM |
6815 | |
6816 | *displacement_string_end = '0'; | |
252b5132 RH |
6817 | } |
6818 | #endif | |
3956db08 | 6819 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6820 | if (gotfree_input_line) |
6821 | input_line_pointer = gotfree_input_line; | |
252b5132 | 6822 | |
24eab124 | 6823 | exp_seg = expression (exp); |
252b5132 | 6824 | |
636c26b0 AM |
6825 | SKIP_WHITESPACE (); |
6826 | if (*input_line_pointer) | |
6827 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
6828 | #if GCC_ASM_O_HACK | |
6829 | RESTORE_END_STRING (disp_end + 1); | |
6830 | #endif | |
636c26b0 | 6831 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 6832 | if (gotfree_input_line) |
ee86248c JB |
6833 | { |
6834 | free (gotfree_input_line); | |
6835 | ||
6836 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
6837 | exp->X_op = O_illegal; | |
6838 | } | |
6839 | ||
6840 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
6841 | ||
6842 | RESTORE_END_STRING (disp_end); | |
6843 | ||
6844 | return ret; | |
6845 | } | |
6846 | ||
6847 | static int | |
6848 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
6849 | i386_operand_type types, const char *disp_start) | |
6850 | { | |
6851 | i386_operand_type bigdisp; | |
6852 | int ret = 1; | |
636c26b0 | 6853 | |
24eab124 AM |
6854 | /* We do this to make sure that the section symbol is in |
6855 | the symbol table. We will ultimately change the relocation | |
47926f60 | 6856 | to be relative to the beginning of the section. */ |
1ae12ab7 | 6857 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
6858 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
6859 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 6860 | { |
636c26b0 | 6861 | if (exp->X_op != O_symbol) |
3992d3b7 | 6862 | goto inv_disp; |
636c26b0 | 6863 | |
e5cb08ac | 6864 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
6865 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
6866 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
6867 | exp->X_op = O_subtract; |
6868 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 6869 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 6870 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
6871 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
6872 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 6873 | else |
29b0f896 | 6874 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 6875 | } |
252b5132 | 6876 | |
3992d3b7 AM |
6877 | else if (exp->X_op == O_absent |
6878 | || exp->X_op == O_illegal | |
ee86248c | 6879 | || exp->X_op == O_big) |
2daf4fd8 | 6880 | { |
3992d3b7 AM |
6881 | inv_disp: |
6882 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 6883 | disp_start); |
3992d3b7 | 6884 | ret = 0; |
2daf4fd8 AM |
6885 | } |
6886 | ||
4c63da97 | 6887 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
6888 | else if (exp->X_op != O_constant |
6889 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
6890 | && exp_seg != absolute_section | |
6891 | && exp_seg != text_section | |
6892 | && exp_seg != data_section | |
6893 | && exp_seg != bss_section | |
6894 | && exp_seg != undefined_section | |
6895 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 6896 | { |
d0b47220 | 6897 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 6898 | ret = 0; |
24eab124 | 6899 | } |
252b5132 | 6900 | #endif |
3956db08 | 6901 | |
40fb9820 L |
6902 | /* Check if this is a displacement only operand. */ |
6903 | bigdisp = i.types[this_operand]; | |
6904 | bigdisp.bitfield.disp8 = 0; | |
6905 | bigdisp.bitfield.disp16 = 0; | |
6906 | bigdisp.bitfield.disp32 = 0; | |
6907 | bigdisp.bitfield.disp32s = 0; | |
6908 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 6909 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
6910 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6911 | types); | |
3956db08 | 6912 | |
3992d3b7 | 6913 | return ret; |
252b5132 RH |
6914 | } |
6915 | ||
eecb386c | 6916 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
6917 | Return 1 on success, 0 on a failure. */ |
6918 | ||
252b5132 | 6919 | static int |
e3bb37b5 | 6920 | i386_index_check (const char *operand_string) |
252b5132 | 6921 | { |
3e73aa7c | 6922 | int ok; |
fc0763e6 | 6923 | const char *kind = "base/index"; |
24eab124 | 6924 | #if INFER_ADDR_PREFIX |
eecb386c AM |
6925 | int fudged = 0; |
6926 | ||
24eab124 AM |
6927 | tryprefix: |
6928 | #endif | |
3e73aa7c | 6929 | ok = 1; |
fc0763e6 JB |
6930 | if (current_templates->start->opcode_modifier.isstring |
6931 | && !current_templates->start->opcode_modifier.immext | |
6932 | && (current_templates->end[-1].opcode_modifier.isstring | |
6933 | || i.mem_operands)) | |
6934 | { | |
6935 | /* Memory operands of string insns are special in that they only allow | |
6936 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
6937 | unsigned int expected; | |
6938 | ||
6939 | kind = "string address"; | |
6940 | ||
6941 | if (current_templates->start->opcode_modifier.w) | |
6942 | { | |
6943 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
6944 | ||
6945 | if (!type.bitfield.baseindex | |
6946 | || ((!i.mem_operands != !intel_syntax) | |
6947 | && current_templates->end[-1].operand_types[1] | |
6948 | .bitfield.baseindex)) | |
6949 | type = current_templates->end[-1].operand_types[1]; | |
6950 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; | |
6951 | } | |
6952 | else | |
6953 | expected = 3 /* rBX */; | |
6954 | ||
6955 | if (!i.base_reg || i.index_reg | |
6956 | || operand_type_check (i.types[this_operand], disp)) | |
6957 | ok = -1; | |
6958 | else if (!(flag_code == CODE_64BIT | |
6959 | ? i.prefix[ADDR_PREFIX] | |
6960 | ? i.base_reg->reg_type.bitfield.reg32 | |
6961 | : i.base_reg->reg_type.bitfield.reg64 | |
6962 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
6963 | ? i.base_reg->reg_type.bitfield.reg32 | |
6964 | : i.base_reg->reg_type.bitfield.reg16)) | |
6965 | ok = 0; | |
6966 | else if (i.base_reg->reg_num != expected) | |
6967 | ok = -1; | |
6968 | ||
6969 | if (ok < 0) | |
6970 | { | |
6971 | unsigned int j; | |
6972 | ||
6973 | for (j = 0; j < i386_regtab_size; ++j) | |
6974 | if ((flag_code == CODE_64BIT | |
6975 | ? i.prefix[ADDR_PREFIX] | |
6976 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
6977 | : i386_regtab[j].reg_type.bitfield.reg64 | |
6978 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
6979 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
6980 | : i386_regtab[j].reg_type.bitfield.reg16) | |
6981 | && i386_regtab[j].reg_num == expected) | |
6982 | break; | |
6983 | assert (j < i386_regtab_size); | |
6984 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), | |
6985 | operand_string, | |
6986 | intel_syntax ? '[' : '(', | |
6987 | register_prefix, | |
6988 | i386_regtab[j].reg_name, | |
6989 | intel_syntax ? ']' : ')'); | |
6990 | ok = 1; | |
6991 | } | |
6992 | } | |
6993 | else if (flag_code == CODE_64BIT) | |
64e74474 | 6994 | { |
64e74474 | 6995 | if ((i.base_reg |
40fb9820 L |
6996 | && ((i.prefix[ADDR_PREFIX] == 0 |
6997 | && !i.base_reg->reg_type.bitfield.reg64) | |
6998 | || (i.prefix[ADDR_PREFIX] | |
6999 | && !i.base_reg->reg_type.bitfield.reg32)) | |
7000 | && (i.index_reg | |
9a04903e JB |
7001 | || i.base_reg->reg_num != |
7002 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 7003 | || (i.index_reg |
40fb9820 L |
7004 | && (!i.index_reg->reg_type.bitfield.baseindex |
7005 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
7006 | && i.index_reg->reg_num != RegRiz |
7007 | && !i.index_reg->reg_type.bitfield.reg64 | |
7008 | ) | |
40fb9820 | 7009 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 7010 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 7011 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 7012 | ok = 0; |
3e73aa7c JH |
7013 | } |
7014 | else | |
7015 | { | |
7016 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
7017 | { | |
7018 | /* 16bit checks. */ | |
7019 | if ((i.base_reg | |
40fb9820 L |
7020 | && (!i.base_reg->reg_type.bitfield.reg16 |
7021 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 7022 | || (i.index_reg |
40fb9820 L |
7023 | && (!i.index_reg->reg_type.bitfield.reg16 |
7024 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
7025 | || !(i.base_reg |
7026 | && i.base_reg->reg_num < 6 | |
7027 | && i.index_reg->reg_num >= 6 | |
7028 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
7029 | ok = 0; |
7030 | } | |
7031 | else | |
e5cb08ac | 7032 | { |
3e73aa7c JH |
7033 | /* 32bit checks. */ |
7034 | if ((i.base_reg | |
40fb9820 | 7035 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 7036 | || (i.index_reg |
db51cc60 L |
7037 | && ((!i.index_reg->reg_type.bitfield.reg32 |
7038 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 7039 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 7040 | ok = 0; |
3e73aa7c JH |
7041 | } |
7042 | } | |
7043 | if (!ok) | |
24eab124 AM |
7044 | { |
7045 | #if INFER_ADDR_PREFIX | |
fc0763e6 | 7046 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
24eab124 AM |
7047 | { |
7048 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
7049 | i.prefixes += 1; | |
b23bac36 AM |
7050 | /* Change the size of any displacement too. At most one of |
7051 | Disp16 or Disp32 is set. | |
7052 | FIXME. There doesn't seem to be any real need for separate | |
7053 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 7054 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 7055 | if (flag_code != CODE_64BIT |
40fb9820 L |
7056 | && (i.types[this_operand].bitfield.disp16 |
7057 | || i.types[this_operand].bitfield.disp32)) | |
7058 | i.types[this_operand] | |
c6fb90c8 | 7059 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 7060 | fudged = 1; |
24eab124 AM |
7061 | goto tryprefix; |
7062 | } | |
eecb386c | 7063 | if (fudged) |
fc0763e6 JB |
7064 | as_bad (_("`%s' is not a valid %s expression"), |
7065 | operand_string, | |
7066 | kind); | |
eecb386c | 7067 | else |
c388dee8 | 7068 | #endif |
fc0763e6 | 7069 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
eecb386c | 7070 | operand_string, |
fc0763e6 JB |
7071 | flag_code_names[i.prefix[ADDR_PREFIX] |
7072 | ? flag_code == CODE_32BIT | |
7073 | ? CODE_16BIT | |
7074 | : CODE_32BIT | |
7075 | : flag_code], | |
7076 | kind); | |
24eab124 | 7077 | } |
20f0a1fc | 7078 | return ok; |
24eab124 | 7079 | } |
252b5132 | 7080 | |
fc0763e6 | 7081 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 7082 | on error. */ |
252b5132 | 7083 | |
252b5132 | 7084 | static int |
a7619375 | 7085 | i386_att_operand (char *operand_string) |
252b5132 | 7086 | { |
af6bdddf AM |
7087 | const reg_entry *r; |
7088 | char *end_op; | |
24eab124 | 7089 | char *op_string = operand_string; |
252b5132 | 7090 | |
24eab124 | 7091 | if (is_space_char (*op_string)) |
252b5132 RH |
7092 | ++op_string; |
7093 | ||
24eab124 | 7094 | /* We check for an absolute prefix (differentiating, |
47926f60 | 7095 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
7096 | if (*op_string == ABSOLUTE_PREFIX) |
7097 | { | |
7098 | ++op_string; | |
7099 | if (is_space_char (*op_string)) | |
7100 | ++op_string; | |
40fb9820 | 7101 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 7102 | } |
252b5132 | 7103 | |
47926f60 | 7104 | /* Check if operand is a register. */ |
4d1bb795 | 7105 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 7106 | { |
40fb9820 L |
7107 | i386_operand_type temp; |
7108 | ||
24eab124 AM |
7109 | /* Check for a segment override by searching for ':' after a |
7110 | segment register. */ | |
7111 | op_string = end_op; | |
7112 | if (is_space_char (*op_string)) | |
7113 | ++op_string; | |
40fb9820 L |
7114 | if (*op_string == ':' |
7115 | && (r->reg_type.bitfield.sreg2 | |
7116 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
7117 | { |
7118 | switch (r->reg_num) | |
7119 | { | |
7120 | case 0: | |
7121 | i.seg[i.mem_operands] = &es; | |
7122 | break; | |
7123 | case 1: | |
7124 | i.seg[i.mem_operands] = &cs; | |
7125 | break; | |
7126 | case 2: | |
7127 | i.seg[i.mem_operands] = &ss; | |
7128 | break; | |
7129 | case 3: | |
7130 | i.seg[i.mem_operands] = &ds; | |
7131 | break; | |
7132 | case 4: | |
7133 | i.seg[i.mem_operands] = &fs; | |
7134 | break; | |
7135 | case 5: | |
7136 | i.seg[i.mem_operands] = &gs; | |
7137 | break; | |
7138 | } | |
252b5132 | 7139 | |
24eab124 | 7140 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
7141 | ++op_string; |
7142 | if (is_space_char (*op_string)) | |
24eab124 | 7143 | ++op_string; |
252b5132 | 7144 | |
24eab124 AM |
7145 | if (!is_digit_char (*op_string) |
7146 | && !is_identifier_char (*op_string) | |
7147 | && *op_string != '(' | |
7148 | && *op_string != ABSOLUTE_PREFIX) | |
7149 | { | |
7150 | as_bad (_("bad memory operand `%s'"), op_string); | |
7151 | return 0; | |
7152 | } | |
47926f60 | 7153 | /* Handle case of %es:*foo. */ |
24eab124 AM |
7154 | if (*op_string == ABSOLUTE_PREFIX) |
7155 | { | |
7156 | ++op_string; | |
7157 | if (is_space_char (*op_string)) | |
7158 | ++op_string; | |
40fb9820 | 7159 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
7160 | } |
7161 | goto do_memory_reference; | |
7162 | } | |
7163 | if (*op_string) | |
7164 | { | |
d0b47220 | 7165 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
7166 | return 0; |
7167 | } | |
40fb9820 L |
7168 | temp = r->reg_type; |
7169 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
7170 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7171 | temp); | |
7d5e4556 | 7172 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 7173 | i.op[this_operand].regs = r; |
24eab124 AM |
7174 | i.reg_operands++; |
7175 | } | |
af6bdddf AM |
7176 | else if (*op_string == REGISTER_PREFIX) |
7177 | { | |
7178 | as_bad (_("bad register name `%s'"), op_string); | |
7179 | return 0; | |
7180 | } | |
24eab124 | 7181 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 7182 | { |
24eab124 | 7183 | ++op_string; |
40fb9820 | 7184 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 7185 | { |
d0b47220 | 7186 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
7187 | return 0; |
7188 | } | |
7189 | if (!i386_immediate (op_string)) | |
7190 | return 0; | |
7191 | } | |
7192 | else if (is_digit_char (*op_string) | |
7193 | || is_identifier_char (*op_string) | |
e5cb08ac | 7194 | || *op_string == '(') |
24eab124 | 7195 | { |
47926f60 | 7196 | /* This is a memory reference of some sort. */ |
af6bdddf | 7197 | char *base_string; |
252b5132 | 7198 | |
47926f60 | 7199 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
7200 | char *displacement_string_start; |
7201 | char *displacement_string_end; | |
252b5132 | 7202 | |
24eab124 | 7203 | do_memory_reference: |
24eab124 | 7204 | if ((i.mem_operands == 1 |
40fb9820 | 7205 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
7206 | || i.mem_operands == 2) |
7207 | { | |
7208 | as_bad (_("too many memory references for `%s'"), | |
7209 | current_templates->start->name); | |
7210 | return 0; | |
7211 | } | |
252b5132 | 7212 | |
24eab124 AM |
7213 | /* Check for base index form. We detect the base index form by |
7214 | looking for an ')' at the end of the operand, searching | |
7215 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
7216 | after the '('. */ | |
af6bdddf | 7217 | base_string = op_string + strlen (op_string); |
c3332e24 | 7218 | |
af6bdddf AM |
7219 | --base_string; |
7220 | if (is_space_char (*base_string)) | |
7221 | --base_string; | |
252b5132 | 7222 | |
47926f60 | 7223 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
7224 | displacement_string_start = op_string; |
7225 | displacement_string_end = base_string + 1; | |
252b5132 | 7226 | |
24eab124 AM |
7227 | if (*base_string == ')') |
7228 | { | |
af6bdddf | 7229 | char *temp_string; |
24eab124 AM |
7230 | unsigned int parens_balanced = 1; |
7231 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 7232 | equal, so this loop will not be infinite. */ |
24eab124 AM |
7233 | do |
7234 | { | |
7235 | base_string--; | |
7236 | if (*base_string == ')') | |
7237 | parens_balanced++; | |
7238 | if (*base_string == '(') | |
7239 | parens_balanced--; | |
7240 | } | |
7241 | while (parens_balanced); | |
c3332e24 | 7242 | |
af6bdddf | 7243 | temp_string = base_string; |
c3332e24 | 7244 | |
24eab124 | 7245 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
7246 | ++base_string; |
7247 | if (is_space_char (*base_string)) | |
24eab124 | 7248 | ++base_string; |
252b5132 | 7249 | |
af6bdddf | 7250 | if (*base_string == ',' |
4eed87de AM |
7251 | || ((i.base_reg = parse_register (base_string, &end_op)) |
7252 | != NULL)) | |
252b5132 | 7253 | { |
af6bdddf | 7254 | displacement_string_end = temp_string; |
252b5132 | 7255 | |
40fb9820 | 7256 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 7257 | |
af6bdddf | 7258 | if (i.base_reg) |
24eab124 | 7259 | { |
24eab124 AM |
7260 | base_string = end_op; |
7261 | if (is_space_char (*base_string)) | |
7262 | ++base_string; | |
af6bdddf AM |
7263 | } |
7264 | ||
7265 | /* There may be an index reg or scale factor here. */ | |
7266 | if (*base_string == ',') | |
7267 | { | |
7268 | ++base_string; | |
7269 | if (is_space_char (*base_string)) | |
7270 | ++base_string; | |
7271 | ||
4eed87de AM |
7272 | if ((i.index_reg = parse_register (base_string, &end_op)) |
7273 | != NULL) | |
24eab124 | 7274 | { |
af6bdddf | 7275 | base_string = end_op; |
24eab124 AM |
7276 | if (is_space_char (*base_string)) |
7277 | ++base_string; | |
af6bdddf AM |
7278 | if (*base_string == ',') |
7279 | { | |
7280 | ++base_string; | |
7281 | if (is_space_char (*base_string)) | |
7282 | ++base_string; | |
7283 | } | |
e5cb08ac | 7284 | else if (*base_string != ')') |
af6bdddf | 7285 | { |
4eed87de AM |
7286 | as_bad (_("expecting `,' or `)' " |
7287 | "after index register in `%s'"), | |
af6bdddf AM |
7288 | operand_string); |
7289 | return 0; | |
7290 | } | |
24eab124 | 7291 | } |
af6bdddf | 7292 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 7293 | { |
af6bdddf | 7294 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
7295 | return 0; |
7296 | } | |
252b5132 | 7297 | |
47926f60 | 7298 | /* Check for scale factor. */ |
551c1ca1 | 7299 | if (*base_string != ')') |
af6bdddf | 7300 | { |
551c1ca1 AM |
7301 | char *end_scale = i386_scale (base_string); |
7302 | ||
7303 | if (!end_scale) | |
af6bdddf | 7304 | return 0; |
24eab124 | 7305 | |
551c1ca1 | 7306 | base_string = end_scale; |
af6bdddf AM |
7307 | if (is_space_char (*base_string)) |
7308 | ++base_string; | |
7309 | if (*base_string != ')') | |
7310 | { | |
4eed87de AM |
7311 | as_bad (_("expecting `)' " |
7312 | "after scale factor in `%s'"), | |
af6bdddf AM |
7313 | operand_string); |
7314 | return 0; | |
7315 | } | |
7316 | } | |
7317 | else if (!i.index_reg) | |
24eab124 | 7318 | { |
4eed87de AM |
7319 | as_bad (_("expecting index register or scale factor " |
7320 | "after `,'; got '%c'"), | |
af6bdddf | 7321 | *base_string); |
24eab124 AM |
7322 | return 0; |
7323 | } | |
7324 | } | |
af6bdddf | 7325 | else if (*base_string != ')') |
24eab124 | 7326 | { |
4eed87de AM |
7327 | as_bad (_("expecting `,' or `)' " |
7328 | "after base register in `%s'"), | |
af6bdddf | 7329 | operand_string); |
24eab124 AM |
7330 | return 0; |
7331 | } | |
c3332e24 | 7332 | } |
af6bdddf | 7333 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7334 | { |
af6bdddf | 7335 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7336 | return 0; |
c3332e24 | 7337 | } |
24eab124 AM |
7338 | } |
7339 | ||
7340 | /* If there's an expression beginning the operand, parse it, | |
7341 | assuming displacement_string_start and | |
7342 | displacement_string_end are meaningful. */ | |
7343 | if (displacement_string_start != displacement_string_end) | |
7344 | { | |
7345 | if (!i386_displacement (displacement_string_start, | |
7346 | displacement_string_end)) | |
7347 | return 0; | |
7348 | } | |
7349 | ||
7350 | /* Special case for (%dx) while doing input/output op. */ | |
7351 | if (i.base_reg | |
0dfbf9d7 L |
7352 | && operand_type_equal (&i.base_reg->reg_type, |
7353 | ®16_inoutportreg) | |
24eab124 AM |
7354 | && i.index_reg == 0 |
7355 | && i.log2_scale_factor == 0 | |
7356 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7357 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7358 | { |
65da13b5 | 7359 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7360 | return 1; |
7361 | } | |
7362 | ||
eecb386c AM |
7363 | if (i386_index_check (operand_string) == 0) |
7364 | return 0; | |
5c07affc | 7365 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7366 | i.mem_operands++; |
7367 | } | |
7368 | else | |
ce8a8b2f AM |
7369 | { |
7370 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7371 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7372 | output_invalid (*op_string), | |
7373 | this_operand + 1, | |
7374 | op_string); | |
7375 | return 0; | |
7376 | } | |
47926f60 | 7377 | return 1; /* Normal return. */ |
252b5132 RH |
7378 | } |
7379 | \f | |
ee7fcc42 AM |
7380 | /* md_estimate_size_before_relax() |
7381 | ||
7382 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7383 | assembler uses these frags to handle variable size jump | |
7384 | instructions. | |
7385 | ||
7386 | Any symbol that is now undefined will not become defined. | |
7387 | Return the correct fr_subtype in the frag. | |
7388 | Return the initial "guess for variable size of frag" to caller. | |
7389 | The guess is actually the growth beyond the fixed part. Whatever | |
7390 | we do to grow the fixed or variable part contributes to our | |
7391 | returned value. */ | |
7392 | ||
252b5132 RH |
7393 | int |
7394 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
7395 | fragS *fragP; |
7396 | segT segment; | |
252b5132 | 7397 | { |
252b5132 | 7398 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7399 | check for un-relaxable symbols. On an ELF system, we can't relax |
7400 | an externally visible symbol, because it may be overridden by a | |
7401 | shared library. */ | |
7402 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7403 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7404 | || (IS_ELF |
31312f95 AM |
7405 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
7406 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
7407 | #endif |
7408 | ) | |
252b5132 | 7409 | { |
b98ef147 AM |
7410 | /* Symbol is undefined in this segment, or we need to keep a |
7411 | reloc so that weak symbols can be overridden. */ | |
7412 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7413 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7414 | unsigned char *opcode; |
7415 | int old_fr_fix; | |
f6af82bd | 7416 | |
ee7fcc42 AM |
7417 | if (fragP->fr_var != NO_RELOC) |
7418 | reloc_type = fragP->fr_var; | |
b98ef147 | 7419 | else if (size == 2) |
f6af82bd AM |
7420 | reloc_type = BFD_RELOC_16_PCREL; |
7421 | else | |
7422 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7423 | |
ee7fcc42 AM |
7424 | old_fr_fix = fragP->fr_fix; |
7425 | opcode = (unsigned char *) fragP->fr_opcode; | |
7426 | ||
fddf5b5b | 7427 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7428 | { |
fddf5b5b AM |
7429 | case UNCOND_JUMP: |
7430 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7431 | opcode[0] = 0xe9; |
252b5132 | 7432 | fragP->fr_fix += size; |
062cd5e7 AS |
7433 | fix_new (fragP, old_fr_fix, size, |
7434 | fragP->fr_symbol, | |
7435 | fragP->fr_offset, 1, | |
7436 | reloc_type); | |
252b5132 RH |
7437 | break; |
7438 | ||
fddf5b5b | 7439 | case COND_JUMP86: |
412167cb AM |
7440 | if (size == 2 |
7441 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7442 | { |
7443 | /* Negate the condition, and branch past an | |
7444 | unconditional jump. */ | |
7445 | opcode[0] ^= 1; | |
7446 | opcode[1] = 3; | |
7447 | /* Insert an unconditional jump. */ | |
7448 | opcode[2] = 0xe9; | |
7449 | /* We added two extra opcode bytes, and have a two byte | |
7450 | offset. */ | |
7451 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7452 | fix_new (fragP, old_fr_fix + 2, 2, |
7453 | fragP->fr_symbol, | |
7454 | fragP->fr_offset, 1, | |
7455 | reloc_type); | |
fddf5b5b AM |
7456 | break; |
7457 | } | |
7458 | /* Fall through. */ | |
7459 | ||
7460 | case COND_JUMP: | |
412167cb AM |
7461 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7462 | { | |
3e02c1cc AM |
7463 | fixS *fixP; |
7464 | ||
412167cb | 7465 | fragP->fr_fix += 1; |
3e02c1cc AM |
7466 | fixP = fix_new (fragP, old_fr_fix, 1, |
7467 | fragP->fr_symbol, | |
7468 | fragP->fr_offset, 1, | |
7469 | BFD_RELOC_8_PCREL); | |
7470 | fixP->fx_signed = 1; | |
412167cb AM |
7471 | break; |
7472 | } | |
93c2a809 | 7473 | |
24eab124 | 7474 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7475 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7476 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 7477 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
7478 | /* We've added an opcode byte. */ |
7479 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
7480 | fix_new (fragP, old_fr_fix + 1, size, |
7481 | fragP->fr_symbol, | |
7482 | fragP->fr_offset, 1, | |
7483 | reloc_type); | |
252b5132 | 7484 | break; |
fddf5b5b AM |
7485 | |
7486 | default: | |
7487 | BAD_CASE (fragP->fr_subtype); | |
7488 | break; | |
252b5132 RH |
7489 | } |
7490 | frag_wane (fragP); | |
ee7fcc42 | 7491 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 7492 | } |
93c2a809 | 7493 | |
93c2a809 AM |
7494 | /* Guess size depending on current relax state. Initially the relax |
7495 | state will correspond to a short jump and we return 1, because | |
7496 | the variable part of the frag (the branch offset) is one byte | |
7497 | long. However, we can relax a section more than once and in that | |
7498 | case we must either set fr_subtype back to the unrelaxed state, | |
7499 | or return the value for the appropriate branch. */ | |
7500 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
7501 | } |
7502 | ||
47926f60 KH |
7503 | /* Called after relax() is finished. |
7504 | ||
7505 | In: Address of frag. | |
7506 | fr_type == rs_machine_dependent. | |
7507 | fr_subtype is what the address relaxed to. | |
7508 | ||
7509 | Out: Any fixSs and constants are set up. | |
7510 | Caller will turn frag into a ".space 0". */ | |
7511 | ||
252b5132 RH |
7512 | void |
7513 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
7514 | bfd *abfd ATTRIBUTE_UNUSED; |
7515 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 7516 | fragS *fragP; |
252b5132 | 7517 | { |
29b0f896 | 7518 | unsigned char *opcode; |
252b5132 | 7519 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
7520 | offsetT target_address; |
7521 | offsetT opcode_address; | |
252b5132 | 7522 | unsigned int extension = 0; |
847f7ad4 | 7523 | offsetT displacement_from_opcode_start; |
252b5132 RH |
7524 | |
7525 | opcode = (unsigned char *) fragP->fr_opcode; | |
7526 | ||
47926f60 | 7527 | /* Address we want to reach in file space. */ |
252b5132 | 7528 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 7529 | |
47926f60 | 7530 | /* Address opcode resides at in file space. */ |
252b5132 RH |
7531 | opcode_address = fragP->fr_address + fragP->fr_fix; |
7532 | ||
47926f60 | 7533 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
7534 | displacement_from_opcode_start = target_address - opcode_address; |
7535 | ||
fddf5b5b | 7536 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 7537 | { |
47926f60 KH |
7538 | /* Don't have to change opcode. */ |
7539 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 7540 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
7541 | } |
7542 | else | |
7543 | { | |
7544 | if (no_cond_jump_promotion | |
7545 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
7546 | as_warn_where (fragP->fr_file, fragP->fr_line, |
7547 | _("long jump required")); | |
252b5132 | 7548 | |
fddf5b5b AM |
7549 | switch (fragP->fr_subtype) |
7550 | { | |
7551 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
7552 | extension = 4; /* 1 opcode + 4 displacement */ | |
7553 | opcode[0] = 0xe9; | |
7554 | where_to_put_displacement = &opcode[1]; | |
7555 | break; | |
252b5132 | 7556 | |
fddf5b5b AM |
7557 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
7558 | extension = 2; /* 1 opcode + 2 displacement */ | |
7559 | opcode[0] = 0xe9; | |
7560 | where_to_put_displacement = &opcode[1]; | |
7561 | break; | |
252b5132 | 7562 | |
fddf5b5b AM |
7563 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
7564 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
7565 | extension = 5; /* 2 opcode + 4 displacement */ | |
7566 | opcode[1] = opcode[0] + 0x10; | |
7567 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7568 | where_to_put_displacement = &opcode[2]; | |
7569 | break; | |
252b5132 | 7570 | |
fddf5b5b AM |
7571 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
7572 | extension = 3; /* 2 opcode + 2 displacement */ | |
7573 | opcode[1] = opcode[0] + 0x10; | |
7574 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7575 | where_to_put_displacement = &opcode[2]; | |
7576 | break; | |
252b5132 | 7577 | |
fddf5b5b AM |
7578 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
7579 | extension = 4; | |
7580 | opcode[0] ^= 1; | |
7581 | opcode[1] = 3; | |
7582 | opcode[2] = 0xe9; | |
7583 | where_to_put_displacement = &opcode[3]; | |
7584 | break; | |
7585 | ||
7586 | default: | |
7587 | BAD_CASE (fragP->fr_subtype); | |
7588 | break; | |
7589 | } | |
252b5132 | 7590 | } |
fddf5b5b | 7591 | |
7b81dfbb AJ |
7592 | /* If size if less then four we are sure that the operand fits, |
7593 | but if it's 4, then it could be that the displacement is larger | |
7594 | then -/+ 2GB. */ | |
7595 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
7596 | && object_64bit | |
7597 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
7598 | + ((addressT) 1 << 31)) |
7599 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
7600 | { |
7601 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7602 | _("jump target out of range")); | |
7603 | /* Make us emit 0. */ | |
7604 | displacement_from_opcode_start = extension; | |
7605 | } | |
47926f60 | 7606 | /* Now put displacement after opcode. */ |
252b5132 RH |
7607 | md_number_to_chars ((char *) where_to_put_displacement, |
7608 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 7609 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
7610 | fragP->fr_fix += extension; |
7611 | } | |
7612 | \f | |
252b5132 RH |
7613 | /* Apply a fixup (fixS) to segment data, once it has been determined |
7614 | by our caller that we have all the info we need to fix it up. | |
7615 | ||
7616 | On the 386, immediates, displacements, and data pointers are all in | |
7617 | the same (little-endian) format, so we don't need to care about which | |
7618 | we are handling. */ | |
7619 | ||
94f592af | 7620 | void |
55cf6793 | 7621 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
7622 | /* The fix we're to put in. */ |
7623 | fixS *fixP; | |
47926f60 | 7624 | /* Pointer to the value of the bits. */ |
c6682705 | 7625 | valueT *valP; |
47926f60 KH |
7626 | /* Segment fix is from. */ |
7627 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 7628 | { |
94f592af | 7629 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 7630 | valueT value = *valP; |
252b5132 | 7631 | |
f86103b7 | 7632 | #if !defined (TE_Mach) |
93382f6d AM |
7633 | if (fixP->fx_pcrel) |
7634 | { | |
7635 | switch (fixP->fx_r_type) | |
7636 | { | |
5865bb77 ILT |
7637 | default: |
7638 | break; | |
7639 | ||
d6ab8113 JB |
7640 | case BFD_RELOC_64: |
7641 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7642 | break; | |
93382f6d | 7643 | case BFD_RELOC_32: |
ae8887b5 | 7644 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
7645 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
7646 | break; | |
7647 | case BFD_RELOC_16: | |
7648 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7649 | break; | |
7650 | case BFD_RELOC_8: | |
7651 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
7652 | break; | |
7653 | } | |
7654 | } | |
252b5132 | 7655 | |
a161fe53 | 7656 | if (fixP->fx_addsy != NULL |
31312f95 | 7657 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 7658 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
7659 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
7660 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7661 | && !use_rela_relocations) | |
252b5132 | 7662 | { |
31312f95 AM |
7663 | /* This is a hack. There should be a better way to handle this. |
7664 | This covers for the fact that bfd_install_relocation will | |
7665 | subtract the current location (for partial_inplace, PC relative | |
7666 | relocations); see more below. */ | |
252b5132 | 7667 | #ifndef OBJ_AOUT |
718ddfc0 | 7668 | if (IS_ELF |
252b5132 RH |
7669 | #ifdef TE_PE |
7670 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
7671 | #endif | |
7672 | ) | |
7673 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7674 | #endif | |
7675 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 7676 | if (IS_ELF) |
252b5132 | 7677 | { |
6539b54b | 7678 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 7679 | |
6539b54b | 7680 | if ((sym_seg == seg |
2f66722d | 7681 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 7682 | && sym_seg != absolute_section)) |
ae6063d4 | 7683 | && !generic_force_reloc (fixP)) |
2f66722d AM |
7684 | { |
7685 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
7686 | bfd_install_relocation subtracts them out again. I think |
7687 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
7688 | it. FIXME. */ |
7689 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7690 | } | |
252b5132 RH |
7691 | } |
7692 | #endif | |
7693 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
7694 | /* For some reason, the PE format does not store a |
7695 | section address offset for a PC relative symbol. */ | |
7696 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 7697 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
7698 | value += md_pcrel_from (fixP); |
7699 | #endif | |
7700 | } | |
7701 | ||
7702 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 7703 | and we must not disappoint it. */ |
252b5132 | 7704 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7705 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
7706 | switch (fixP->fx_r_type) |
7707 | { | |
7708 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 7709 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
7710 | /* Make the jump instruction point to the address of the operand. At |
7711 | runtime we merely add the offset to the actual PLT entry. */ | |
7712 | value = -4; | |
7713 | break; | |
31312f95 | 7714 | |
13ae64f3 JJ |
7715 | case BFD_RELOC_386_TLS_GD: |
7716 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 7717 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
7718 | case BFD_RELOC_386_TLS_IE: |
7719 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 7720 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
7721 | case BFD_RELOC_X86_64_TLSGD: |
7722 | case BFD_RELOC_X86_64_TLSLD: | |
7723 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 7724 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
7725 | value = 0; /* Fully resolved at runtime. No addend. */ |
7726 | /* Fallthrough */ | |
7727 | case BFD_RELOC_386_TLS_LE: | |
7728 | case BFD_RELOC_386_TLS_LDO_32: | |
7729 | case BFD_RELOC_386_TLS_LE_32: | |
7730 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7731 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 7732 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 7733 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
7734 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
7735 | break; | |
7736 | ||
67a4f2b7 AO |
7737 | case BFD_RELOC_386_TLS_DESC_CALL: |
7738 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
7739 | value = 0; /* Fully resolved at runtime. No addend. */ | |
7740 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7741 | fixP->fx_done = 0; | |
7742 | return; | |
7743 | ||
00f7efb6 JJ |
7744 | case BFD_RELOC_386_GOT32: |
7745 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
7746 | value = 0; /* Fully resolved at runtime. No addend. */ |
7747 | break; | |
47926f60 KH |
7748 | |
7749 | case BFD_RELOC_VTABLE_INHERIT: | |
7750 | case BFD_RELOC_VTABLE_ENTRY: | |
7751 | fixP->fx_done = 0; | |
94f592af | 7752 | return; |
47926f60 KH |
7753 | |
7754 | default: | |
7755 | break; | |
7756 | } | |
7757 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 7758 | *valP = value; |
f86103b7 | 7759 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 7760 | |
3e73aa7c | 7761 | /* Are we finished with this relocation now? */ |
c6682705 | 7762 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
7763 | fixP->fx_done = 1; |
7764 | else if (use_rela_relocations) | |
7765 | { | |
7766 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
7767 | /* Remember value for tc_gen_reloc. */ |
7768 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
7769 | value = 0; |
7770 | } | |
f86103b7 | 7771 | |
94f592af | 7772 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 7773 | } |
252b5132 | 7774 | \f |
252b5132 | 7775 | char * |
499ac353 | 7776 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 7777 | { |
499ac353 NC |
7778 | /* This outputs the LITTLENUMs in REVERSE order; |
7779 | in accord with the bigendian 386. */ | |
7780 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
7781 | } |
7782 | \f | |
2d545b82 | 7783 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 7784 | |
252b5132 | 7785 | static char * |
e3bb37b5 | 7786 | output_invalid (int c) |
252b5132 | 7787 | { |
3882b010 | 7788 | if (ISPRINT (c)) |
f9f21a03 L |
7789 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
7790 | "'%c'", c); | |
252b5132 | 7791 | else |
f9f21a03 | 7792 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 7793 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
7794 | return output_invalid_buf; |
7795 | } | |
7796 | ||
af6bdddf | 7797 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
7798 | |
7799 | static const reg_entry * | |
4d1bb795 | 7800 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 7801 | { |
af6bdddf AM |
7802 | char *s = reg_string; |
7803 | char *p; | |
252b5132 RH |
7804 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
7805 | const reg_entry *r; | |
7806 | ||
7807 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
7808 | if (*s == REGISTER_PREFIX) | |
7809 | ++s; | |
7810 | ||
7811 | if (is_space_char (*s)) | |
7812 | ++s; | |
7813 | ||
7814 | p = reg_name_given; | |
af6bdddf | 7815 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
7816 | { |
7817 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
7818 | return (const reg_entry *) NULL; |
7819 | s++; | |
252b5132 RH |
7820 | } |
7821 | ||
6588847e DN |
7822 | /* For naked regs, make sure that we are not dealing with an identifier. |
7823 | This prevents confusing an identifier like `eax_var' with register | |
7824 | `eax'. */ | |
7825 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
7826 | return (const reg_entry *) NULL; | |
7827 | ||
af6bdddf | 7828 | *end_op = s; |
252b5132 RH |
7829 | |
7830 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
7831 | ||
5f47d35b | 7832 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 7833 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 7834 | { |
5f47d35b AM |
7835 | if (is_space_char (*s)) |
7836 | ++s; | |
7837 | if (*s == '(') | |
7838 | { | |
af6bdddf | 7839 | ++s; |
5f47d35b AM |
7840 | if (is_space_char (*s)) |
7841 | ++s; | |
7842 | if (*s >= '0' && *s <= '7') | |
7843 | { | |
db557034 | 7844 | int fpr = *s - '0'; |
af6bdddf | 7845 | ++s; |
5f47d35b AM |
7846 | if (is_space_char (*s)) |
7847 | ++s; | |
7848 | if (*s == ')') | |
7849 | { | |
7850 | *end_op = s + 1; | |
db557034 AM |
7851 | r = hash_find (reg_hash, "st(0)"); |
7852 | know (r); | |
7853 | return r + fpr; | |
5f47d35b | 7854 | } |
5f47d35b | 7855 | } |
47926f60 | 7856 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
7857 | return (const reg_entry *) NULL; |
7858 | } | |
7859 | } | |
7860 | ||
a60de03c JB |
7861 | if (r == NULL || allow_pseudo_reg) |
7862 | return r; | |
7863 | ||
0dfbf9d7 | 7864 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
7865 | return (const reg_entry *) NULL; |
7866 | ||
192dc9c6 JB |
7867 | if ((r->reg_type.bitfield.reg32 |
7868 | || r->reg_type.bitfield.sreg3 | |
7869 | || r->reg_type.bitfield.control | |
7870 | || r->reg_type.bitfield.debug | |
7871 | || r->reg_type.bitfield.test) | |
7872 | && !cpu_arch_flags.bitfield.cpui386) | |
7873 | return (const reg_entry *) NULL; | |
7874 | ||
7875 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) | |
7876 | return (const reg_entry *) NULL; | |
7877 | ||
7878 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
7879 | return (const reg_entry *) NULL; | |
7880 | ||
40f12533 L |
7881 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
7882 | return (const reg_entry *) NULL; | |
7883 | ||
db51cc60 | 7884 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 7885 | if (!allow_index_reg |
db51cc60 L |
7886 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
7887 | return (const reg_entry *) NULL; | |
7888 | ||
a60de03c JB |
7889 | if (((r->reg_flags & (RegRex64 | RegRex)) |
7890 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 7891 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 7892 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 7893 | && flag_code != CODE_64BIT) |
20f0a1fc | 7894 | return (const reg_entry *) NULL; |
1ae00879 | 7895 | |
b7240065 JB |
7896 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
7897 | return (const reg_entry *) NULL; | |
7898 | ||
252b5132 RH |
7899 | return r; |
7900 | } | |
4d1bb795 JB |
7901 | |
7902 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
7903 | ||
7904 | static const reg_entry * | |
7905 | parse_register (char *reg_string, char **end_op) | |
7906 | { | |
7907 | const reg_entry *r; | |
7908 | ||
7909 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
7910 | r = parse_real_register (reg_string, end_op); | |
7911 | else | |
7912 | r = NULL; | |
7913 | if (!r) | |
7914 | { | |
7915 | char *save = input_line_pointer; | |
7916 | char c; | |
7917 | symbolS *symbolP; | |
7918 | ||
7919 | input_line_pointer = reg_string; | |
7920 | c = get_symbol_end (); | |
7921 | symbolP = symbol_find (reg_string); | |
7922 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
7923 | { | |
7924 | const expressionS *e = symbol_get_value_expression (symbolP); | |
7925 | ||
7926 | know (e->X_op == O_register); | |
4eed87de | 7927 | know (e->X_add_number >= 0 |
c3fe08fa | 7928 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
7929 | r = i386_regtab + e->X_add_number; |
7930 | *end_op = input_line_pointer; | |
7931 | } | |
7932 | *input_line_pointer = c; | |
7933 | input_line_pointer = save; | |
7934 | } | |
7935 | return r; | |
7936 | } | |
7937 | ||
7938 | int | |
7939 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
7940 | { | |
7941 | const reg_entry *r; | |
7942 | char *end = input_line_pointer; | |
7943 | ||
7944 | *end = *nextcharP; | |
7945 | r = parse_register (name, &input_line_pointer); | |
7946 | if (r && end <= input_line_pointer) | |
7947 | { | |
7948 | *nextcharP = *input_line_pointer; | |
7949 | *input_line_pointer = 0; | |
7950 | e->X_op = O_register; | |
7951 | e->X_add_number = r - i386_regtab; | |
7952 | return 1; | |
7953 | } | |
7954 | input_line_pointer = end; | |
7955 | *end = 0; | |
ee86248c | 7956 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
7957 | } |
7958 | ||
7959 | void | |
7960 | md_operand (expressionS *e) | |
7961 | { | |
ee86248c JB |
7962 | char *end; |
7963 | const reg_entry *r; | |
4d1bb795 | 7964 | |
ee86248c JB |
7965 | switch (*input_line_pointer) |
7966 | { | |
7967 | case REGISTER_PREFIX: | |
7968 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
7969 | if (r) |
7970 | { | |
7971 | e->X_op = O_register; | |
7972 | e->X_add_number = r - i386_regtab; | |
7973 | input_line_pointer = end; | |
7974 | } | |
ee86248c JB |
7975 | break; |
7976 | ||
7977 | case '[': | |
7978 | assert (intel_syntax); | |
7979 | end = input_line_pointer++; | |
7980 | expression (e); | |
7981 | if (*input_line_pointer == ']') | |
7982 | { | |
7983 | ++input_line_pointer; | |
7984 | e->X_op_symbol = make_expr_symbol (e); | |
7985 | e->X_add_symbol = NULL; | |
7986 | e->X_add_number = 0; | |
7987 | e->X_op = O_index; | |
7988 | } | |
7989 | else | |
7990 | { | |
7991 | e->X_op = O_absent; | |
7992 | input_line_pointer = end; | |
7993 | } | |
7994 | break; | |
4d1bb795 JB |
7995 | } |
7996 | } | |
7997 | ||
252b5132 | 7998 | \f |
4cc782b5 | 7999 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 8000 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 8001 | #else |
12b55ccc | 8002 | const char *md_shortopts = "qn"; |
252b5132 | 8003 | #endif |
6e0b89ee | 8004 | |
3e73aa7c | 8005 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
8006 | #define OPTION_64 (OPTION_MD_BASE + 1) |
8007 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
8008 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
8009 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
8010 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
8011 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
8012 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
8013 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
8014 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 8015 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 8016 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
b3b91714 | 8017 | |
99ad8390 NC |
8018 | struct option md_longopts[] = |
8019 | { | |
3e73aa7c | 8020 | {"32", no_argument, NULL, OPTION_32}, |
99ad8390 | 8021 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
3e73aa7c | 8022 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 8023 | #endif |
b3b91714 | 8024 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
8025 | {"march", required_argument, NULL, OPTION_MARCH}, |
8026 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
8027 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
8028 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
8029 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
8030 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
8031 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 8032 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 8033 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
252b5132 RH |
8034 | {NULL, no_argument, NULL, 0} |
8035 | }; | |
8036 | size_t md_longopts_size = sizeof (md_longopts); | |
8037 | ||
8038 | int | |
9103f4f4 | 8039 | md_parse_option (int c, char *arg) |
252b5132 | 8040 | { |
9103f4f4 | 8041 | unsigned int i; |
6305a203 | 8042 | char *arch, *next; |
9103f4f4 | 8043 | |
252b5132 RH |
8044 | switch (c) |
8045 | { | |
12b55ccc L |
8046 | case 'n': |
8047 | optimize_align_code = 0; | |
8048 | break; | |
8049 | ||
a38cf1db AM |
8050 | case 'q': |
8051 | quiet_warnings = 1; | |
252b5132 RH |
8052 | break; |
8053 | ||
8054 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
8055 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
8056 | should be emitted or not. FIXME: Not implemented. */ | |
8057 | case 'Q': | |
252b5132 RH |
8058 | break; |
8059 | ||
8060 | /* -V: SVR4 argument to print version ID. */ | |
8061 | case 'V': | |
8062 | print_version_id (); | |
8063 | break; | |
8064 | ||
a38cf1db AM |
8065 | /* -k: Ignore for FreeBSD compatibility. */ |
8066 | case 'k': | |
252b5132 | 8067 | break; |
4cc782b5 ILT |
8068 | |
8069 | case 's': | |
8070 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 8071 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 8072 | break; |
99ad8390 NC |
8073 | #endif |
8074 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) | |
3e73aa7c JH |
8075 | case OPTION_64: |
8076 | { | |
8077 | const char **list, **l; | |
8078 | ||
3e73aa7c JH |
8079 | list = bfd_target_list (); |
8080 | for (l = list; *l != NULL; l++) | |
8620418b | 8081 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
8082 | || strcmp (*l, "coff-x86-64") == 0 |
8083 | || strcmp (*l, "pe-x86-64") == 0 | |
8084 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
8085 | { |
8086 | default_arch = "x86_64"; | |
8087 | break; | |
8088 | } | |
3e73aa7c | 8089 | if (*l == NULL) |
6e0b89ee | 8090 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
8091 | free (list); |
8092 | } | |
8093 | break; | |
8094 | #endif | |
252b5132 | 8095 | |
6e0b89ee AM |
8096 | case OPTION_32: |
8097 | default_arch = "i386"; | |
8098 | break; | |
8099 | ||
b3b91714 AM |
8100 | case OPTION_DIVIDE: |
8101 | #ifdef SVR4_COMMENT_CHARS | |
8102 | { | |
8103 | char *n, *t; | |
8104 | const char *s; | |
8105 | ||
8106 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
8107 | t = n; | |
8108 | for (s = i386_comment_chars; *s != '\0'; s++) | |
8109 | if (*s != '/') | |
8110 | *t++ = *s; | |
8111 | *t = '\0'; | |
8112 | i386_comment_chars = n; | |
8113 | } | |
8114 | #endif | |
8115 | break; | |
8116 | ||
9103f4f4 | 8117 | case OPTION_MARCH: |
6305a203 L |
8118 | arch = xstrdup (arg); |
8119 | do | |
9103f4f4 | 8120 | { |
6305a203 L |
8121 | if (*arch == '.') |
8122 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
8123 | next = strchr (arch, '+'); | |
8124 | if (next) | |
8125 | *next++ = '\0'; | |
8126 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
9103f4f4 | 8127 | { |
6305a203 | 8128 | if (strcmp (arch, cpu_arch [i].name) == 0) |
ccc9c027 | 8129 | { |
6305a203 L |
8130 | /* Processor. */ |
8131 | cpu_arch_name = cpu_arch[i].name; | |
8132 | cpu_sub_arch_name = NULL; | |
8133 | cpu_arch_flags = cpu_arch[i].flags; | |
8134 | cpu_arch_isa = cpu_arch[i].type; | |
8135 | cpu_arch_isa_flags = cpu_arch[i].flags; | |
8136 | if (!cpu_arch_tune_set) | |
8137 | { | |
8138 | cpu_arch_tune = cpu_arch_isa; | |
8139 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
8140 | } | |
8141 | break; | |
8142 | } | |
8143 | else if (*cpu_arch [i].name == '.' | |
8144 | && strcmp (arch, cpu_arch [i].name + 1) == 0) | |
8145 | { | |
8146 | /* ISA entension. */ | |
8147 | i386_cpu_flags flags; | |
8148 | flags = cpu_flags_or (cpu_arch_flags, | |
8149 | cpu_arch[i].flags); | |
0dfbf9d7 | 8150 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
8151 | { |
8152 | if (cpu_sub_arch_name) | |
8153 | { | |
8154 | char *name = cpu_sub_arch_name; | |
8155 | cpu_sub_arch_name = concat (name, | |
8156 | cpu_arch[i].name, | |
1bf57e9f | 8157 | (const char *) NULL); |
6305a203 L |
8158 | free (name); |
8159 | } | |
8160 | else | |
8161 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
8162 | cpu_arch_flags = flags; | |
8163 | } | |
8164 | break; | |
ccc9c027 | 8165 | } |
9103f4f4 | 8166 | } |
6305a203 L |
8167 | |
8168 | if (i >= ARRAY_SIZE (cpu_arch)) | |
8169 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
8170 | ||
8171 | arch = next; | |
9103f4f4 | 8172 | } |
6305a203 | 8173 | while (next != NULL ); |
9103f4f4 L |
8174 | break; |
8175 | ||
8176 | case OPTION_MTUNE: | |
8177 | if (*arg == '.') | |
8178 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
8179 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
8180 | { | |
8181 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
8182 | { | |
ccc9c027 | 8183 | cpu_arch_tune_set = 1; |
9103f4f4 L |
8184 | cpu_arch_tune = cpu_arch [i].type; |
8185 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
8186 | break; | |
8187 | } | |
8188 | } | |
8189 | if (i >= ARRAY_SIZE (cpu_arch)) | |
8190 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
8191 | break; | |
8192 | ||
1efbbeb4 L |
8193 | case OPTION_MMNEMONIC: |
8194 | if (strcasecmp (arg, "att") == 0) | |
8195 | intel_mnemonic = 0; | |
8196 | else if (strcasecmp (arg, "intel") == 0) | |
8197 | intel_mnemonic = 1; | |
8198 | else | |
8199 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
8200 | break; | |
8201 | ||
8202 | case OPTION_MSYNTAX: | |
8203 | if (strcasecmp (arg, "att") == 0) | |
8204 | intel_syntax = 0; | |
8205 | else if (strcasecmp (arg, "intel") == 0) | |
8206 | intel_syntax = 1; | |
8207 | else | |
8208 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
8209 | break; | |
8210 | ||
8211 | case OPTION_MINDEX_REG: | |
8212 | allow_index_reg = 1; | |
8213 | break; | |
8214 | ||
8215 | case OPTION_MNAKED_REG: | |
8216 | allow_naked_reg = 1; | |
8217 | break; | |
8218 | ||
8219 | case OPTION_MOLD_GCC: | |
8220 | old_gcc = 1; | |
1efbbeb4 L |
8221 | break; |
8222 | ||
c0f3af97 L |
8223 | case OPTION_MSSE2AVX: |
8224 | sse2avx = 1; | |
8225 | break; | |
8226 | ||
daf50ae7 L |
8227 | case OPTION_MSSE_CHECK: |
8228 | if (strcasecmp (arg, "error") == 0) | |
8229 | sse_check = sse_check_error; | |
8230 | else if (strcasecmp (arg, "warning") == 0) | |
8231 | sse_check = sse_check_warning; | |
8232 | else if (strcasecmp (arg, "none") == 0) | |
8233 | sse_check = sse_check_none; | |
8234 | else | |
8235 | as_fatal (_("Invalid -msse-check= option: `%s'"), arg); | |
8236 | break; | |
8237 | ||
252b5132 RH |
8238 | default: |
8239 | return 0; | |
8240 | } | |
8241 | return 1; | |
8242 | } | |
8243 | ||
8244 | void | |
8245 | md_show_usage (stream) | |
8246 | FILE *stream; | |
8247 | { | |
4cc782b5 ILT |
8248 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8249 | fprintf (stream, _("\ | |
a38cf1db AM |
8250 | -Q ignored\n\ |
8251 | -V print assembler version number\n\ | |
b3b91714 AM |
8252 | -k ignored\n")); |
8253 | #endif | |
8254 | fprintf (stream, _("\ | |
12b55ccc | 8255 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
8256 | -q quieten some warnings\n")); |
8257 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8258 | fprintf (stream, _("\ | |
a38cf1db | 8259 | -s ignored\n")); |
b3b91714 | 8260 | #endif |
751d281c L |
8261 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
8262 | fprintf (stream, _("\ | |
8263 | --32/--64 generate 32bit/64bit code\n")); | |
8264 | #endif | |
b3b91714 AM |
8265 | #ifdef SVR4_COMMENT_CHARS |
8266 | fprintf (stream, _("\ | |
8267 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
8268 | #else |
8269 | fprintf (stream, _("\ | |
b3b91714 | 8270 | --divide ignored\n")); |
4cc782b5 | 8271 | #endif |
9103f4f4 | 8272 | fprintf (stream, _("\ |
6305a203 L |
8273 | -march=CPU[,+EXTENSION...]\n\ |
8274 | generate code for CPU and EXTENSION, CPU is one of:\n\ | |
2cb4f3d5 L |
8275 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ |
8276 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
bd5295b2 | 8277 | core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\ |
2cb4f3d5 | 8278 | generic32, generic64\n\ |
599121aa L |
8279 | EXTENSION is combination of:\n\ |
8280 | mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\ | |
f1f8f695 | 8281 | avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\ |
bd5295b2 L |
8282 | clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\ |
8283 | sse5, svme, abm, padlock\n")); | |
6305a203 | 8284 | fprintf (stream, _("\ |
2cb4f3d5 L |
8285 | -mtune=CPU optimize for CPU, CPU is one of:\n\ |
8286 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ | |
8287 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
bd5295b2 | 8288 | core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\ |
2cb4f3d5 | 8289 | generic32, generic64\n")); |
ba104c83 | 8290 | fprintf (stream, _("\ |
c0f3af97 L |
8291 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8292 | fprintf (stream, _("\ | |
daf50ae7 L |
8293 | -msse-check=[none|error|warning]\n\ |
8294 | check SSE instructions\n")); | |
8295 | fprintf (stream, _("\ | |
ba104c83 L |
8296 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8297 | fprintf (stream, _("\ | |
8298 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8299 | fprintf (stream, _("\ | |
8300 | -mindex-reg support pseudo index registers\n")); | |
8301 | fprintf (stream, _("\ | |
8302 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8303 | fprintf (stream, _("\ | |
8304 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8305 | } |
8306 | ||
3e73aa7c | 8307 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
872ce6ff | 8308 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP)) |
252b5132 RH |
8309 | |
8310 | /* Pick the target format to use. */ | |
8311 | ||
47926f60 | 8312 | const char * |
e3bb37b5 | 8313 | i386_target_format (void) |
252b5132 | 8314 | { |
3e73aa7c | 8315 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
8316 | { |
8317 | set_code_flag (CODE_64BIT); | |
0dfbf9d7 | 8318 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8319 | { |
8320 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8321 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8322 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8323 | cpu_arch_isa_flags.bitfield.cpui486 = 1; | |
8324 | cpu_arch_isa_flags.bitfield.cpui586 = 1; | |
8325 | cpu_arch_isa_flags.bitfield.cpui686 = 1; | |
bd5295b2 | 8326 | cpu_arch_isa_flags.bitfield.cpuclflush = 1; |
40fb9820 | 8327 | cpu_arch_isa_flags.bitfield.cpummx= 1; |
40fb9820 L |
8328 | cpu_arch_isa_flags.bitfield.cpusse = 1; |
8329 | cpu_arch_isa_flags.bitfield.cpusse2 = 1; | |
8330 | } | |
0dfbf9d7 | 8331 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8332 | { |
8333 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8334 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8335 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8336 | cpu_arch_tune_flags.bitfield.cpui486 = 1; | |
8337 | cpu_arch_tune_flags.bitfield.cpui586 = 1; | |
8338 | cpu_arch_tune_flags.bitfield.cpui686 = 1; | |
bd5295b2 | 8339 | cpu_arch_tune_flags.bitfield.cpuclflush = 1; |
40fb9820 | 8340 | cpu_arch_tune_flags.bitfield.cpummx= 1; |
40fb9820 L |
8341 | cpu_arch_tune_flags.bitfield.cpusse = 1; |
8342 | cpu_arch_tune_flags.bitfield.cpusse2 = 1; | |
8343 | } | |
9103f4f4 | 8344 | } |
3e73aa7c | 8345 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
8346 | { |
8347 | set_code_flag (CODE_32BIT); | |
0dfbf9d7 | 8348 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8349 | { |
8350 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8351 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8352 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8353 | } | |
0dfbf9d7 | 8354 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8355 | { |
8356 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8357 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8358 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8359 | } | |
9103f4f4 | 8360 | } |
3e73aa7c JH |
8361 | else |
8362 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
8363 | switch (OUTPUT_FLAVOR) |
8364 | { | |
872ce6ff L |
8365 | #ifdef TE_PEP |
8366 | case bfd_target_coff_flavour: | |
b01ee69d | 8367 | return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386"; |
872ce6ff L |
8368 | break; |
8369 | #endif | |
4c63da97 AM |
8370 | #ifdef OBJ_MAYBE_AOUT |
8371 | case bfd_target_aout_flavour: | |
47926f60 | 8372 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
8373 | #endif |
8374 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
8375 | case bfd_target_coff_flavour: |
8376 | return "coff-i386"; | |
4c63da97 | 8377 | #endif |
3e73aa7c | 8378 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 8379 | case bfd_target_elf_flavour: |
3e73aa7c | 8380 | { |
e5cb08ac | 8381 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
8382 | { |
8383 | object_64bit = 1; | |
8384 | use_rela_relocations = 1; | |
8385 | } | |
9d7cbccd | 8386 | return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; |
3e73aa7c | 8387 | } |
4c63da97 | 8388 | #endif |
252b5132 RH |
8389 | default: |
8390 | abort (); | |
8391 | return NULL; | |
8392 | } | |
8393 | } | |
8394 | ||
47926f60 | 8395 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
8396 | |
8397 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
8398 | void |
8399 | i386_elf_emit_arch_note (void) | |
a847613f | 8400 | { |
718ddfc0 | 8401 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
8402 | { |
8403 | char *p; | |
8404 | asection *seg = now_seg; | |
8405 | subsegT subseg = now_subseg; | |
8406 | Elf_Internal_Note i_note; | |
8407 | Elf_External_Note e_note; | |
8408 | asection *note_secp; | |
8409 | int len; | |
8410 | ||
8411 | /* Create the .note section. */ | |
8412 | note_secp = subseg_new (".note", 0); | |
8413 | bfd_set_section_flags (stdoutput, | |
8414 | note_secp, | |
8415 | SEC_HAS_CONTENTS | SEC_READONLY); | |
8416 | ||
8417 | /* Process the arch string. */ | |
8418 | len = strlen (cpu_arch_name); | |
8419 | ||
8420 | i_note.namesz = len + 1; | |
8421 | i_note.descsz = 0; | |
8422 | i_note.type = NT_ARCH; | |
8423 | p = frag_more (sizeof (e_note.namesz)); | |
8424 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
8425 | p = frag_more (sizeof (e_note.descsz)); | |
8426 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
8427 | p = frag_more (sizeof (e_note.type)); | |
8428 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
8429 | p = frag_more (len + 1); | |
8430 | strcpy (p, cpu_arch_name); | |
8431 | ||
8432 | frag_align (2, 0, 0); | |
8433 | ||
8434 | subseg_set (seg, subseg); | |
8435 | } | |
8436 | } | |
8437 | #endif | |
252b5132 | 8438 | \f |
252b5132 RH |
8439 | symbolS * |
8440 | md_undefined_symbol (name) | |
8441 | char *name; | |
8442 | { | |
18dc2407 ILT |
8443 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
8444 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
8445 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
8446 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
8447 | { |
8448 | if (!GOT_symbol) | |
8449 | { | |
8450 | if (symbol_find (name)) | |
8451 | as_bad (_("GOT already in symbol table")); | |
8452 | GOT_symbol = symbol_new (name, undefined_section, | |
8453 | (valueT) 0, &zero_address_frag); | |
8454 | }; | |
8455 | return GOT_symbol; | |
8456 | } | |
252b5132 RH |
8457 | return 0; |
8458 | } | |
8459 | ||
8460 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 8461 | |
252b5132 RH |
8462 | valueT |
8463 | md_section_align (segment, size) | |
ab9da554 | 8464 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
8465 | valueT size; |
8466 | { | |
4c63da97 AM |
8467 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
8468 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
8469 | { | |
8470 | /* For a.out, force the section size to be aligned. If we don't do | |
8471 | this, BFD will align it for us, but it will not write out the | |
8472 | final bytes of the section. This may be a bug in BFD, but it is | |
8473 | easier to fix it here since that is how the other a.out targets | |
8474 | work. */ | |
8475 | int align; | |
8476 | ||
8477 | align = bfd_get_section_alignment (stdoutput, segment); | |
8478 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
8479 | } | |
252b5132 RH |
8480 | #endif |
8481 | ||
8482 | return size; | |
8483 | } | |
8484 | ||
8485 | /* On the i386, PC-relative offsets are relative to the start of the | |
8486 | next instruction. That is, the address of the offset, plus its | |
8487 | size, since the offset is always the last part of the insn. */ | |
8488 | ||
8489 | long | |
e3bb37b5 | 8490 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
8491 | { |
8492 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
8493 | } | |
8494 | ||
8495 | #ifndef I386COFF | |
8496 | ||
8497 | static void | |
e3bb37b5 | 8498 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 8499 | { |
29b0f896 | 8500 | int temp; |
252b5132 | 8501 | |
8a75718c JB |
8502 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8503 | if (IS_ELF) | |
8504 | obj_elf_section_change_hook (); | |
8505 | #endif | |
252b5132 RH |
8506 | temp = get_absolute_expression (); |
8507 | subseg_set (bss_section, (subsegT) temp); | |
8508 | demand_empty_rest_of_line (); | |
8509 | } | |
8510 | ||
8511 | #endif | |
8512 | ||
252b5132 | 8513 | void |
e3bb37b5 | 8514 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
8515 | { |
8516 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
8517 | { | |
23df1078 JH |
8518 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
8519 | { | |
4fa24527 | 8520 | if (!object_64bit) |
23df1078 JH |
8521 | abort (); |
8522 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
8523 | } | |
8524 | else | |
8525 | { | |
4fa24527 | 8526 | if (!object_64bit) |
d6ab8113 JB |
8527 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
8528 | else | |
8529 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 8530 | } |
252b5132 RH |
8531 | fixp->fx_subsy = 0; |
8532 | } | |
8533 | } | |
8534 | ||
252b5132 RH |
8535 | arelent * |
8536 | tc_gen_reloc (section, fixp) | |
ab9da554 | 8537 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
8538 | fixS *fixp; |
8539 | { | |
8540 | arelent *rel; | |
8541 | bfd_reloc_code_real_type code; | |
8542 | ||
8543 | switch (fixp->fx_r_type) | |
8544 | { | |
3e73aa7c JH |
8545 | case BFD_RELOC_X86_64_PLT32: |
8546 | case BFD_RELOC_X86_64_GOT32: | |
8547 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
8548 | case BFD_RELOC_386_PLT32: |
8549 | case BFD_RELOC_386_GOT32: | |
8550 | case BFD_RELOC_386_GOTOFF: | |
8551 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
8552 | case BFD_RELOC_386_TLS_GD: |
8553 | case BFD_RELOC_386_TLS_LDM: | |
8554 | case BFD_RELOC_386_TLS_LDO_32: | |
8555 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
8556 | case BFD_RELOC_386_TLS_IE: |
8557 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
8558 | case BFD_RELOC_386_TLS_LE_32: |
8559 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
8560 | case BFD_RELOC_386_TLS_GOTDESC: |
8561 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
8562 | case BFD_RELOC_X86_64_TLSGD: |
8563 | case BFD_RELOC_X86_64_TLSLD: | |
8564 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8565 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
8566 | case BFD_RELOC_X86_64_GOTTPOFF: |
8567 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
8568 | case BFD_RELOC_X86_64_TPOFF64: |
8569 | case BFD_RELOC_X86_64_GOTOFF64: | |
8570 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
8571 | case BFD_RELOC_X86_64_GOT64: |
8572 | case BFD_RELOC_X86_64_GOTPCREL64: | |
8573 | case BFD_RELOC_X86_64_GOTPC64: | |
8574 | case BFD_RELOC_X86_64_GOTPLT64: | |
8575 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
8576 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8577 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
8578 | case BFD_RELOC_RVA: |
8579 | case BFD_RELOC_VTABLE_ENTRY: | |
8580 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
8581 | #ifdef TE_PE |
8582 | case BFD_RELOC_32_SECREL: | |
8583 | #endif | |
252b5132 RH |
8584 | code = fixp->fx_r_type; |
8585 | break; | |
dbbaec26 L |
8586 | case BFD_RELOC_X86_64_32S: |
8587 | if (!fixp->fx_pcrel) | |
8588 | { | |
8589 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
8590 | code = fixp->fx_r_type; | |
8591 | break; | |
8592 | } | |
252b5132 | 8593 | default: |
93382f6d | 8594 | if (fixp->fx_pcrel) |
252b5132 | 8595 | { |
93382f6d AM |
8596 | switch (fixp->fx_size) |
8597 | { | |
8598 | default: | |
b091f402 AM |
8599 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8600 | _("can not do %d byte pc-relative relocation"), | |
8601 | fixp->fx_size); | |
93382f6d AM |
8602 | code = BFD_RELOC_32_PCREL; |
8603 | break; | |
8604 | case 1: code = BFD_RELOC_8_PCREL; break; | |
8605 | case 2: code = BFD_RELOC_16_PCREL; break; | |
8606 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
8607 | #ifdef BFD64 |
8608 | case 8: code = BFD_RELOC_64_PCREL; break; | |
8609 | #endif | |
93382f6d AM |
8610 | } |
8611 | } | |
8612 | else | |
8613 | { | |
8614 | switch (fixp->fx_size) | |
8615 | { | |
8616 | default: | |
b091f402 AM |
8617 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8618 | _("can not do %d byte relocation"), | |
8619 | fixp->fx_size); | |
93382f6d AM |
8620 | code = BFD_RELOC_32; |
8621 | break; | |
8622 | case 1: code = BFD_RELOC_8; break; | |
8623 | case 2: code = BFD_RELOC_16; break; | |
8624 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 8625 | #ifdef BFD64 |
3e73aa7c | 8626 | case 8: code = BFD_RELOC_64; break; |
937149dd | 8627 | #endif |
93382f6d | 8628 | } |
252b5132 RH |
8629 | } |
8630 | break; | |
8631 | } | |
252b5132 | 8632 | |
d182319b JB |
8633 | if ((code == BFD_RELOC_32 |
8634 | || code == BFD_RELOC_32_PCREL | |
8635 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
8636 | && GOT_symbol |
8637 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 8638 | { |
4fa24527 | 8639 | if (!object_64bit) |
d6ab8113 JB |
8640 | code = BFD_RELOC_386_GOTPC; |
8641 | else | |
8642 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 8643 | } |
7b81dfbb AJ |
8644 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
8645 | && GOT_symbol | |
8646 | && fixp->fx_addsy == GOT_symbol) | |
8647 | { | |
8648 | code = BFD_RELOC_X86_64_GOTPC64; | |
8649 | } | |
252b5132 RH |
8650 | |
8651 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
8652 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
8653 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
8654 | |
8655 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 8656 | |
3e73aa7c JH |
8657 | if (!use_rela_relocations) |
8658 | { | |
8659 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
8660 | vtable entry to be used in the relocation's section offset. */ | |
8661 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8662 | rel->address = fixp->fx_offset; | |
252b5132 | 8663 | |
c6682705 | 8664 | rel->addend = 0; |
3e73aa7c JH |
8665 | } |
8666 | /* Use the rela in 64bit mode. */ | |
252b5132 | 8667 | else |
3e73aa7c | 8668 | { |
062cd5e7 AS |
8669 | if (!fixp->fx_pcrel) |
8670 | rel->addend = fixp->fx_offset; | |
8671 | else | |
8672 | switch (code) | |
8673 | { | |
8674 | case BFD_RELOC_X86_64_PLT32: | |
8675 | case BFD_RELOC_X86_64_GOT32: | |
8676 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
8677 | case BFD_RELOC_X86_64_TLSGD: |
8678 | case BFD_RELOC_X86_64_TLSLD: | |
8679 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
8680 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8681 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
8682 | rel->addend = fixp->fx_offset - fixp->fx_size; |
8683 | break; | |
8684 | default: | |
8685 | rel->addend = (section->vma | |
8686 | - fixp->fx_size | |
8687 | + fixp->fx_addnumber | |
8688 | + md_pcrel_from (fixp)); | |
8689 | break; | |
8690 | } | |
3e73aa7c JH |
8691 | } |
8692 | ||
252b5132 RH |
8693 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
8694 | if (rel->howto == NULL) | |
8695 | { | |
8696 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 8697 | _("cannot represent relocation type %s"), |
252b5132 RH |
8698 | bfd_get_reloc_code_name (code)); |
8699 | /* Set howto to a garbage value so that we can keep going. */ | |
8700 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
8701 | assert (rel->howto != NULL); | |
8702 | } | |
8703 | ||
8704 | return rel; | |
8705 | } | |
8706 | ||
ee86248c | 8707 | #include "tc-i386-intel.c" |
54cfded0 | 8708 | |
a60de03c JB |
8709 | void |
8710 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 8711 | { |
a60de03c JB |
8712 | int saved_naked_reg; |
8713 | char saved_register_dot; | |
54cfded0 | 8714 | |
a60de03c JB |
8715 | saved_naked_reg = allow_naked_reg; |
8716 | allow_naked_reg = 1; | |
8717 | saved_register_dot = register_chars['.']; | |
8718 | register_chars['.'] = '.'; | |
8719 | allow_pseudo_reg = 1; | |
8720 | expression_and_evaluate (exp); | |
8721 | allow_pseudo_reg = 0; | |
8722 | register_chars['.'] = saved_register_dot; | |
8723 | allow_naked_reg = saved_naked_reg; | |
8724 | ||
8725 | if (exp->X_op == O_register && exp->X_add_number >= 0) | |
54cfded0 | 8726 | { |
a60de03c JB |
8727 | if ((addressT) exp->X_add_number < i386_regtab_size) |
8728 | { | |
8729 | exp->X_op = O_constant; | |
8730 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
8731 | .dw2_regnum[flag_code >> 1]; | |
8732 | } | |
8733 | else | |
8734 | exp->X_op = O_illegal; | |
54cfded0 | 8735 | } |
54cfded0 AM |
8736 | } |
8737 | ||
8738 | void | |
8739 | tc_x86_frame_initial_instructions (void) | |
8740 | { | |
a60de03c JB |
8741 | static unsigned int sp_regno[2]; |
8742 | ||
8743 | if (!sp_regno[flag_code >> 1]) | |
8744 | { | |
8745 | char *saved_input = input_line_pointer; | |
8746 | char sp[][4] = {"esp", "rsp"}; | |
8747 | expressionS exp; | |
a4447b93 | 8748 | |
a60de03c JB |
8749 | input_line_pointer = sp[flag_code >> 1]; |
8750 | tc_x86_parse_to_dw2regnum (&exp); | |
8751 | assert (exp.X_op == O_constant); | |
8752 | sp_regno[flag_code >> 1] = exp.X_add_number; | |
8753 | input_line_pointer = saved_input; | |
8754 | } | |
a4447b93 | 8755 | |
a60de03c | 8756 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
a4447b93 | 8757 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
54cfded0 | 8758 | } |
d2b2c203 DJ |
8759 | |
8760 | int | |
8761 | i386_elf_section_type (const char *str, size_t len) | |
8762 | { | |
8763 | if (flag_code == CODE_64BIT | |
8764 | && len == sizeof ("unwind") - 1 | |
8765 | && strncmp (str, "unwind", 6) == 0) | |
8766 | return SHT_X86_64_UNWIND; | |
8767 | ||
8768 | return -1; | |
8769 | } | |
bb41ade5 | 8770 | |
ad5fec3b EB |
8771 | #ifdef TE_SOLARIS |
8772 | void | |
8773 | i386_solaris_fix_up_eh_frame (segT sec) | |
8774 | { | |
8775 | if (flag_code == CODE_64BIT) | |
8776 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
8777 | } | |
8778 | #endif | |
8779 | ||
bb41ade5 AM |
8780 | #ifdef TE_PE |
8781 | void | |
8782 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
8783 | { | |
8784 | expressionS expr; | |
8785 | ||
8786 | expr.X_op = O_secrel; | |
8787 | expr.X_add_symbol = symbol; | |
8788 | expr.X_add_number = 0; | |
8789 | emit_expr (&expr, size); | |
8790 | } | |
8791 | #endif | |
3b22753a L |
8792 | |
8793 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8794 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
8795 | ||
01e1a5bc | 8796 | bfd_vma |
3b22753a L |
8797 | x86_64_section_letter (int letter, char **ptr_msg) |
8798 | { | |
8799 | if (flag_code == CODE_64BIT) | |
8800 | { | |
8801 | if (letter == 'l') | |
8802 | return SHF_X86_64_LARGE; | |
8803 | ||
8804 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 8805 | } |
3b22753a | 8806 | else |
64e74474 | 8807 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
8808 | return -1; |
8809 | } | |
8810 | ||
01e1a5bc | 8811 | bfd_vma |
3b22753a L |
8812 | x86_64_section_word (char *str, size_t len) |
8813 | { | |
8620418b | 8814 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
8815 | return SHF_X86_64_LARGE; |
8816 | ||
8817 | return -1; | |
8818 | } | |
8819 | ||
8820 | static void | |
8821 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
8822 | { | |
8823 | if (flag_code != CODE_64BIT) | |
8824 | { | |
8825 | s_comm_internal (0, elf_common_parse); | |
8826 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
8827 | } | |
8828 | else | |
8829 | { | |
8830 | static segT lbss_section; | |
8831 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
8832 | asection *saved_bss_section = bss_section; | |
8833 | ||
8834 | if (lbss_section == NULL) | |
8835 | { | |
8836 | flagword applicable; | |
8837 | segT seg = now_seg; | |
8838 | subsegT subseg = now_subseg; | |
8839 | ||
8840 | /* The .lbss section is for local .largecomm symbols. */ | |
8841 | lbss_section = subseg_new (".lbss", 0); | |
8842 | applicable = bfd_applicable_section_flags (stdoutput); | |
8843 | bfd_set_section_flags (stdoutput, lbss_section, | |
8844 | applicable & SEC_ALLOC); | |
8845 | seg_info (lbss_section)->bss = 1; | |
8846 | ||
8847 | subseg_set (seg, subseg); | |
8848 | } | |
8849 | ||
8850 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
8851 | bss_section = lbss_section; | |
8852 | ||
8853 | s_comm_internal (0, elf_common_parse); | |
8854 | ||
8855 | elf_com_section_ptr = saved_com_section_ptr; | |
8856 | bss_section = saved_bss_section; | |
8857 | } | |
8858 | } | |
8859 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |