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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e
RM		 434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
29b0f896 436 && !defined (TE_FreeBSD) \
5b806d27 437 && !defined (TE_DragonFly) \
29b0f896 438 && !defined (TE_NetBSD)))
252b5132 439/* This array holds the chars that always start a comment. If the
b3b91714
AM		 440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442const char *i386_comment_chars = "#/";
443#define SVR4_COMMENT_CHARS 1
252b5132 444#define PREFIX_SEPARATOR '\\'
252b5132 445
b3b91714
AM		 446#else
447const char *i386_comment_chars = "#";
448#define PREFIX_SEPARATOR '/'
449#endif
450
252b5132
RH		 451/* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 455 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
252b5132 458 '/' isn't otherwise defined. */
b3b91714 459const char line_comment_chars[] = "#/";
252b5132 460
63a0b638 461const char line_separator_chars[] = ";";
252b5132 462
ce8a8b2f
AM		 463/* Chars that can be used to separate mant from exp in floating point
464 nums. */
252b5132
RH		 465const char EXP_CHARS[] = "eE";
466
ce8a8b2f
AM		 467/* Chars that mean this number is a floating point constant
468 As in 0f12.456
469 or 0d1.2345e12. */
252b5132
RH		 470const char FLT_CHARS[] = "fFdDxX";
471
ce8a8b2f 472/* Tables for lexical analysis. */
252b5132
RH		 473static char mnemonic_chars[256];
474static char register_chars[256];
475static char operand_chars[256];
476static char identifier_chars[256];
477static char digit_chars[256];
478
ce8a8b2f 479/* Lexical macros. */
252b5132
RH		 480#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481#define is_operand_char(x) (operand_chars[(unsigned char) x])
482#define is_register_char(x) (register_chars[(unsigned char) x])
483#define is_space_char(x) ((x) == ' ')
484#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485#define is_digit_char(x) (digit_chars[(unsigned char) x])
486
0234cb7c 487/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 488static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489
490/* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
47926f60 493 assembler instruction). */
252b5132 494static char save_stack[32];
ce8a8b2f 495static char *save_stack_p;
252b5132
RH		 496#define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498#define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
500
47926f60 501/* The instruction we're assembling. */
252b5132
RH		 502static i386_insn i;
503
504/* Possible templates for current insn. */
505static const templates *current_templates;
506
31b2323c
L		 507/* Per instruction expressionS buffers: max displacements & immediates. */
508static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 510
47926f60 511/* Current operand we are working on. */
ee86248c 512static int this_operand = -1;
252b5132 513
3e73aa7c
JH		 514/* We support four different modes. FLAG_CODE variable is used to distinguish
515 these. */
516
517enum flag_code {
518 CODE_32BIT,
519 CODE_16BIT,
520 CODE_64BIT };
521
522static enum flag_code flag_code;
4fa24527 523static unsigned int object_64bit;
862be3fb 524static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 525static int use_rela_relocations = 0;
526
7af8ed2d
NC		 527#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530
351f65ca
L		 531/* The ELF ABI to use. */
532enum x86_elf_abi
533{
534 I386_ABI,
7f56bc95
L		 535 X86_64_ABI,
536 X86_64_X32_ABI
351f65ca
L		 537};
538
539static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 540#endif
351f65ca 541
167ad85b
TG		 542#if defined (TE_PE) || defined (TE_PEP)
543/* Use big object file format. */
544static int use_big_obj = 0;
545#endif
546
8dcea932
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548/* 1 if generating code for a shared library. */
549static int shared = 0;
550#endif
551
47926f60
KH		 552/* 1 for intel syntax,
553 0 if att syntax. */
554static int intel_syntax = 0;
252b5132 555
e89c5eaa
L		 556/* 1 for Intel64 ISA,
557 0 if AMD64 ISA. */
558static int intel64;
559
1efbbeb4
L		 560/* 1 for intel mnemonic,
561 0 if att mnemonic. */
562static int intel_mnemonic = !SYSV386_COMPAT;
563
a60de03c
JB		 564/* 1 if pseudo registers are permitted. */
565static int allow_pseudo_reg = 0;
566
47926f60
KH		 567/* 1 if register prefix % not required. */
568static int allow_naked_reg = 0;
252b5132 569
33eaf5de 570/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 571 instructions supporting it, even if this prefix wasn't specified
572 explicitly. */
573static int add_bnd_prefix = 0;
574
ba104c83 575/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 576static int allow_index_reg = 0;
577
d022bddd
IT		 578/* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580static int omit_lock_prefix = 0;
581
e4e00185
AS		 582/* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584static int avoid_fence = 0;
585
0cb4071e
L		 586/* 1 if the assembler should generate relax relocations. */
587
588static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590
7bab8ab5 591static enum check_kind
daf50ae7 592 {
7bab8ab5
JB		 593 check_none = 0,
594 check_warning,
595 check_error
daf50ae7 596 }
7bab8ab5 597sse_check, operand_check = check_warning;
daf50ae7 598
b6f8c7c4
L		 599/* Optimization:
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
602 register.
603 */
604static int optimize = 0;
605
606/* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 "testb $imm7,%r8".
612 */
613static int optimize_for_space = 0;
614
2ca3ace5
L		 615/* Register prefix used for error message. */
616static const char *register_prefix = "%";
617
47926f60
KH		 618/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621static char stackop_size = '\0';
eecb386c 622
12b55ccc
L		 623/* Non-zero to optimize code alignment. */
624int optimize_align_code = 1;
625
47926f60
KH		 626/* Non-zero to quieten some warnings. */
627static int quiet_warnings = 0;
a38cf1db 628
47926f60
KH		 629/* CPU name. */
630static const char *cpu_arch_name = NULL;
6305a203 631static char *cpu_sub_arch_name = NULL;
a38cf1db 632
47926f60 633/* CPU feature flags. */
40fb9820
L		 634static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635
ccc9c027
L		 636/* If we have selected a cpu we are generating instructions for. */
637static int cpu_arch_tune_set = 0;
638
9103f4f4 639/* Cpu we are generating instructions for. */
fbf3f584 640enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 641
642/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 643static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 644
ccc9c027 645/* CPU instruction set architecture used. */
fbf3f584 646enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 647
9103f4f4 648/* CPU feature flags of instruction set architecture used. */
fbf3f584 649i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 650
fddf5b5b
AM		 651/* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653static unsigned int no_cond_jump_promotion = 0;
654
c0f3af97
L		 655/* Encode SSE instructions with VEX prefix. */
656static unsigned int sse2avx;
657
539f890d
L		 658/* Encode scalar AVX instructions with specific vector length. */
659static enum
660 {
661 vex128 = 0,
662 vex256
663 } avxscalar;
664
43234a1e
L		 665/* Encode scalar EVEX LIG instructions with specific vector length. */
666static enum
667 {
668 evexl128 = 0,
669 evexl256,
670 evexl512
671 } evexlig;
672
673/* Encode EVEX WIG instructions with specific evex.w. */
674static enum
675 {
676 evexw0 = 0,
677 evexw1
678 } evexwig;
679
d3d3c6db
IT		 680/* Value to encode in EVEX RC bits, for SAE-only instructions. */
681static enum rc_type evexrcig = rne;
682
29b0f896 683/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 684static symbolS *GOT_symbol;
29b0f896 685
a4447b93
RH		 686/* The dwarf2 return column, adjusted for 32 or 64 bit. */
687unsigned int x86_dwarf2_return_column;
688
689/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690int x86_cie_data_alignment;
691
252b5132 692/* Interface to relax_segment.
fddf5b5b
AM		 693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
252b5132 696
47926f60 697/* Types. */
93c2a809
AM		 698#define UNCOND_JUMP 0
699#define COND_JUMP 1
700#define COND_JUMP86 2
fddf5b5b 701
47926f60 702/* Sizes. */
252b5132
RH		 703#define CODE16 1
704#define SMALL 0
29b0f896 705#define SMALL16 (SMALL | CODE16)
252b5132 706#define BIG 2
29b0f896 707#define BIG16 (BIG | CODE16)
252b5132
RH		 708
709#ifndef INLINE
710#ifdef __GNUC__
711#define INLINE __inline__
712#else
713#define INLINE
714#endif
715#endif
716
fddf5b5b
AM		 717#define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719#define TYPE_FROM_RELAX_STATE(s) \
720 ((s) >> 2)
721#define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 723
724/* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
731
732const relax_typeS md_relax_table[] =
733{
24eab124
AM		 734 /* The fields are:
735 1) most positive reach of this state,
736 2) most negative reach of this state,
93c2a809 737 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 738 4) which index into the table to try if we can't fit into this one. */
252b5132 739
fddf5b5b 740 /* UNCOND_JUMP states. */
93c2a809
AM		 741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
252b5132 745 {0, 0, 4, 0},
93c2a809
AM		 746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 748 {0, 0, 2, 0},
749
93c2a809
AM		 750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
755 {0, 0, 5, 0},
fddf5b5b 756 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 757 1 extra opcode byte, 2 displacement bytes. */
758 {0, 0, 3, 0},
759
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
765 {0, 0, 5, 0},
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
768 {0, 0, 4, 0}
252b5132
RH		 769};
770
9103f4f4
L		 771static const arch_entry cpu_arch[] =
772{
89507696
JB		 773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
8a2c8fef 775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 776 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 778 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 780 CPU_NONE_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 782 CPU_I186_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 784 CPU_I286_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 786 CPU_I386_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 788 CPU_I486_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 790 CPU_I586_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 792 CPU_I686_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 794 CPU_I586_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 796 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 798 CPU_P2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 800 CPU_P3_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 802 CPU_P4_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 804 CPU_CORE_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 806 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 808 CPU_CORE_FLAGS, 1 },
8a2c8fef 809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 810 CPU_CORE_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 812 CPU_CORE2_FLAGS, 1 },
8a2c8fef 813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 814 CPU_CORE2_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 816 CPU_COREI7_FLAGS, 0 },
8a2c8fef 817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 818 CPU_L1OM_FLAGS, 0 },
7a9068fe 819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 820 CPU_K1OM_FLAGS, 0 },
81486035 821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 822 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 824 CPU_K6_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 826 CPU_K6_2_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 828 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 830 CPU_K8_FLAGS, 1 },
8a2c8fef 831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 832 CPU_K8_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 834 CPU_K8_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 836 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 838 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 840 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 842 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 844 CPU_BDVER4_FLAGS, 0 },
029f3522 845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 846 CPU_ZNVER1_FLAGS, 0 },
7b458c12 847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 848 CPU_BTVER1_FLAGS, 0 },
7b458c12 849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 850 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_8087_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_287_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_387_FLAGS, 0 },
1848e567
L		 857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_MMX_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_SSE_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_SSE2_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_SSE3_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX_FLAGS, 0 },
6c30d220 877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX2_FLAGS, 0 },
43234a1e 879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AVX512F_FLAGS, 0 },
43234a1e 881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_AVX512CD_FLAGS, 0 },
43234a1e 883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_AVX512ER_FLAGS, 0 },
43234a1e 885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_VMX_FLAGS, 0 },
8729a6f6 895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_SMX_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_AES_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_F16C_FLAGS, 0 },
6c30d220 919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_BMI2_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_FMA_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_FMA4_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_XOP_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_LWP_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_MOVBE_FLAGS, 0 },
60aa667e 931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_CX16_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_EPT_FLAGS, 0 },
6c30d220 935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_LZCNT_FLAGS, 0 },
42164a71 937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_HLE_FLAGS, 0 },
42164a71 939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_RTM_FLAGS, 0 },
6c30d220 941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_CLFLUSH_FLAGS, 0 },
22109423 945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_NOP_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SVME_FLAGS, 1 },
8a2c8fef 959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_SVME_FLAGS, 0 },
8a2c8fef 961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_ABM_FLAGS, 0 },
87973e9f 965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_BMI_FLAGS, 0 },
2a2a0f38 967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_TBM_FLAGS, 0 },
e2e1fcde 969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_ADX_FLAGS, 0 },
e2e1fcde 971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_PRFCHW_FLAGS, 0 },
5c111e37 975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_SMAP_FLAGS, 0 },
7e8b059b 977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_MPX_FLAGS, 0 },
a0046408 979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_SHA_FLAGS, 0 },
963f3586 981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_SE1_FLAGS, 0 },
c5e7287a 987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1006 CPU_CLZERO_FLAGS, 0 },
9916071f 1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1008 CPU_MWAITX_FLAGS, 0 },
8eab4136 1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_OSPKE_FLAGS, 0 },
8bc52696 1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1029 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1030 CPU_WAITPKG_FLAGS, 0 },
293f5f65
L		 1031};
1032
1033static const noarch_entry cpu_noarch[] =
1034{
1035 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1036 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1037 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1038 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1039 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1040 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1041 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1042 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1043 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1047 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1048 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1049 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1058 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1059 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1060 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1061 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1062 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1063 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1064 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1065 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1066};
1067
704209c0 1068#ifdef I386COFF
a6c24e68
NC		 1069/* Like s_lcomm_internal in gas/read.c but the alignment string
1070 is allowed to be optional. */
1071
1072static symbolS *
1073pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1074{
1075 addressT align = 0;
1076
1077 SKIP_WHITESPACE ();
1078
7ab9ffdd 1079 if (needs_align
a6c24e68
NC		 1080 && *input_line_pointer == ',')
1081 {
1082 align = parse_align (needs_align - 1);
7ab9ffdd 1083
a6c24e68
NC		 1084 if (align == (addressT) -1)
1085 return NULL;
1086 }
1087 else
1088 {
1089 if (size >= 8)
1090 align = 3;
1091 else if (size >= 4)
1092 align = 2;
1093 else if (size >= 2)
1094 align = 1;
1095 else
1096 align = 0;
1097 }
1098
1099 bss_alloc (symbolP, size, align);
1100 return symbolP;
1101}
1102
704209c0 1103static void
a6c24e68
NC		 1104pe_lcomm (int needs_align)
1105{
1106 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1107}
704209c0 1108#endif
a6c24e68 1109
29b0f896
AM		 1110const pseudo_typeS md_pseudo_table[] =
1111{
1112#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1113 {"align", s_align_bytes, 0},
1114#else
1115 {"align", s_align_ptwo, 0},
1116#endif
1117 {"arch", set_cpu_arch, 0},
1118#ifndef I386COFF
1119 {"bss", s_bss, 0},
a6c24e68
NC		 1120#else
1121 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1122#endif
1123 {"ffloat", float_cons, 'f'},
1124 {"dfloat", float_cons, 'd'},
1125 {"tfloat", float_cons, 'x'},
1126 {"value", cons, 2},
d182319b 1127 {"slong", signed_cons, 4},
29b0f896
AM		 1128 {"noopt", s_ignore, 0},
1129 {"optim", s_ignore, 0},
1130 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1131 {"code16", set_code_flag, CODE_16BIT},
1132 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1133#ifdef BFD64
29b0f896 1134 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1135#endif
29b0f896
AM		 1136 {"intel_syntax", set_intel_syntax, 1},
1137 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1138 {"intel_mnemonic", set_intel_mnemonic, 1},
1139 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1140 {"allow_index_reg", set_allow_index_reg, 1},
1141 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1142 {"sse_check", set_check, 0},
1143 {"operand_check", set_check, 1},
3b22753a
L		 1144#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1145 {"largecomm", handle_large_common, 0},
07a53e5c 1146#else
68d20676 1147 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1148 {"loc", dwarf2_directive_loc, 0},
1149 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1150#endif
6482c264
NC		 1151#ifdef TE_PE
1152 {"secrel32", pe_directive_secrel, 0},
1153#endif
29b0f896
AM		 1154 {0, 0, 0}
1155};
1156
1157/* For interface with expression (). */
1158extern char *input_line_pointer;
1159
1160/* Hash table for instruction mnemonic lookup. */
1161static struct hash_control *op_hash;
1162
1163/* Hash table for register lookup. */
1164static struct hash_control *reg_hash;
1165\f
ce8a8b2f
AM		 1166 /* Various efficient no-op patterns for aligning code labels.
1167 Note: Don't try to assemble the instructions in the comments.
1168 0L and 0w are not legal. */
62a02d25
L		 1169static const unsigned char f32_1[] =
1170 {0x90}; /* nop */
1171static const unsigned char f32_2[] =
1172 {0x66,0x90}; /* xchg %ax,%ax */
1173static const unsigned char f32_3[] =
1174 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1175static const unsigned char f32_4[] =
1176 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1177static const unsigned char f32_6[] =
1178 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1179static const unsigned char f32_7[] =
1180 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1181static const unsigned char f16_3[] =
3ae729d5 1182 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1183static const unsigned char f16_4[] =
3ae729d5
L		 1184 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1185static const unsigned char jump_disp8[] =
1186 {0xeb}; /* jmp disp8 */
1187static const unsigned char jump32_disp32[] =
1188 {0xe9}; /* jmp disp32 */
1189static const unsigned char jump16_disp32[] =
1190 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1191/* 32-bit NOPs patterns. */
1192static const unsigned char *const f32_patt[] = {
3ae729d5 1193 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1194};
1195/* 16-bit NOPs patterns. */
1196static const unsigned char *const f16_patt[] = {
3ae729d5 1197 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1198};
1199/* nopl (%[re]ax) */
1200static const unsigned char alt_3[] =
1201 {0x0f,0x1f,0x00};
1202/* nopl 0(%[re]ax) */
1203static const unsigned char alt_4[] =
1204 {0x0f,0x1f,0x40,0x00};
1205/* nopl 0(%[re]ax,%[re]ax,1) */
1206static const unsigned char alt_5[] =
1207 {0x0f,0x1f,0x44,0x00,0x00};
1208/* nopw 0(%[re]ax,%[re]ax,1) */
1209static const unsigned char alt_6[] =
1210 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1211/* nopl 0L(%[re]ax) */
1212static const unsigned char alt_7[] =
1213 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1214/* nopl 0L(%[re]ax,%[re]ax,1) */
1215static const unsigned char alt_8[] =
1216 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1217/* nopw 0L(%[re]ax,%[re]ax,1) */
1218static const unsigned char alt_9[] =
1219 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1220/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1221static const unsigned char alt_10[] =
1222 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1223/* data16 nopw %cs:0L(%eax,%eax,1) */
1224static const unsigned char alt_11[] =
1225 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1226/* 32-bit and 64-bit NOPs patterns. */
1227static const unsigned char *const alt_patt[] = {
1228 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1229 alt_9, alt_10, alt_11
62a02d25
L		 1230};
1231
1232/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1233 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1234
1235static void
1236i386_output_nops (char *where, const unsigned char *const *patt,
1237 int count, int max_single_nop_size)
1238
1239{
3ae729d5
L		 1240 /* Place the longer NOP first. */
1241 int last;
1242 int offset;
1243 const unsigned char *nops = patt[max_single_nop_size - 1];
1244
1245 /* Use the smaller one if the requsted one isn't available. */
1246 if (nops == NULL)
62a02d25 1247 {
3ae729d5
L		 1248 max_single_nop_size--;
1249 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1250 }
1251
3ae729d5
L		 1252 last = count % max_single_nop_size;
1253
1254 count -= last;
1255 for (offset = 0; offset < count; offset += max_single_nop_size)
1256 memcpy (where + offset, nops, max_single_nop_size);
1257
1258 if (last)
1259 {
1260 nops = patt[last - 1];
1261 if (nops == NULL)
1262 {
1263 /* Use the smaller one plus one-byte NOP if the needed one
1264 isn't available. */
1265 last--;
1266 nops = patt[last - 1];
1267 memcpy (where + offset, nops, last);
1268 where[offset + last] = *patt[0];
1269 }
1270 else
1271 memcpy (where + offset, nops, last);
1272 }
62a02d25
L		 1273}
1274
3ae729d5
L		 1275static INLINE int
1276fits_in_imm7 (offsetT num)
1277{
1278 return (num & 0x7f) == num;
1279}
1280
1281static INLINE int
1282fits_in_imm31 (offsetT num)
1283{
1284 return (num & 0x7fffffff) == num;
1285}
62a02d25
L		 1286
1287/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1288 single NOP instruction LIMIT. */
1289
1290void
3ae729d5 1291i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1292{
3ae729d5 1293 const unsigned char *const *patt = NULL;
62a02d25 1294 int max_single_nop_size;
3ae729d5
L		 1295 /* Maximum number of NOPs before switching to jump over NOPs. */
1296 int max_number_of_nops;
62a02d25 1297
3ae729d5 1298 switch (fragP->fr_type)
62a02d25 1299 {
3ae729d5
L		 1300 case rs_fill_nop:
1301 case rs_align_code:
1302 break;
1303 default:
62a02d25
L		 1304 return;
1305 }
1306
ccc9c027
L		 1307 /* We need to decide which NOP sequence to use for 32bit and
1308 64bit. When -mtune= is used:
4eed87de 1309
76bc74dc
L		 1310 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1311 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1312 2. For the rest, alt_patt will be used.
1313
1314 When -mtune= isn't used, alt_patt will be used if
22109423 1315 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1316 be used.
ccc9c027
L		 1317
1318 When -march= or .arch is used, we can't use anything beyond
1319 cpu_arch_isa_flags. */
1320
1321 if (flag_code == CODE_16BIT)
1322 {
3ae729d5
L		 1323 patt = f16_patt;
1324 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1325 /* Limit number of NOPs to 2 in 16-bit mode. */
1326 max_number_of_nops = 2;
252b5132 1327 }
33fef721 1328 else
ccc9c027 1329 {
fbf3f584 1330 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1331 {
1332 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1333 switch (cpu_arch_tune)
1334 {
1335 case PROCESSOR_UNKNOWN:
1336 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1337 optimize with nops. */
1338 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1339 patt = alt_patt;
ccc9c027
L		 1340 else
1341 patt = f32_patt;
1342 break;
ccc9c027
L		 1343 case PROCESSOR_PENTIUM4:
1344 case PROCESSOR_NOCONA:
ef05d495 1345 case PROCESSOR_CORE:
76bc74dc 1346 case PROCESSOR_CORE2:
bd5295b2 1347 case PROCESSOR_COREI7:
3632d14b 1348 case PROCESSOR_L1OM:
7a9068fe 1349 case PROCESSOR_K1OM:
76bc74dc 1350 case PROCESSOR_GENERIC64:
ccc9c027
L		 1351 case PROCESSOR_K6:
1352 case PROCESSOR_ATHLON:
1353 case PROCESSOR_K8:
4eed87de 1354 case PROCESSOR_AMDFAM10:
8aedb9fe 1355 case PROCESSOR_BD:
029f3522 1356 case PROCESSOR_ZNVER:
7b458c12 1357 case PROCESSOR_BT:
80b8656c 1358 patt = alt_patt;
ccc9c027 1359 break;
76bc74dc 1360 case PROCESSOR_I386:
ccc9c027
L		 1361 case PROCESSOR_I486:
1362 case PROCESSOR_PENTIUM:
2dde1948 1363 case PROCESSOR_PENTIUMPRO:
81486035 1364 case PROCESSOR_IAMCU:
ccc9c027
L		 1365 case PROCESSOR_GENERIC32:
1366 patt = f32_patt;
1367 break;
4eed87de 1368 }
ccc9c027
L		 1369 }
1370 else
1371 {
fbf3f584 1372 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1373 {
1374 case PROCESSOR_UNKNOWN:
e6a14101 1375 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1376 PROCESSOR_UNKNOWN. */
1377 abort ();
1378 break;
1379
76bc74dc 1380 case PROCESSOR_I386:
ccc9c027
L		 1381 case PROCESSOR_I486:
1382 case PROCESSOR_PENTIUM:
81486035 1383 case PROCESSOR_IAMCU:
ccc9c027
L		 1384 case PROCESSOR_K6:
1385 case PROCESSOR_ATHLON:
1386 case PROCESSOR_K8:
4eed87de 1387 case PROCESSOR_AMDFAM10:
8aedb9fe 1388 case PROCESSOR_BD:
029f3522 1389 case PROCESSOR_ZNVER:
7b458c12 1390 case PROCESSOR_BT:
ccc9c027
L		 1391 case PROCESSOR_GENERIC32:
1392 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1393 with nops. */
1394 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1395 patt = alt_patt;
ccc9c027
L		 1396 else
1397 patt = f32_patt;
1398 break;
76bc74dc
L		 1399 case PROCESSOR_PENTIUMPRO:
1400 case PROCESSOR_PENTIUM4:
1401 case PROCESSOR_NOCONA:
1402 case PROCESSOR_CORE:
ef05d495 1403 case PROCESSOR_CORE2:
bd5295b2 1404 case PROCESSOR_COREI7:
3632d14b 1405 case PROCESSOR_L1OM:
7a9068fe 1406 case PROCESSOR_K1OM:
22109423 1407 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1408 patt = alt_patt;
ccc9c027
L		 1409 else
1410 patt = f32_patt;
1411 break;
1412 case PROCESSOR_GENERIC64:
80b8656c 1413 patt = alt_patt;
ccc9c027 1414 break;
4eed87de 1415 }
ccc9c027
L		 1416 }
1417
76bc74dc
L		 1418 if (patt == f32_patt)
1419 {
3ae729d5
L		 1420 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1421 /* Limit number of NOPs to 2 for older processors. */
1422 max_number_of_nops = 2;
76bc74dc
L		 1423 }
1424 else
1425 {
3ae729d5
L		 1426 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1427 /* Limit number of NOPs to 7 for newer processors. */
1428 max_number_of_nops = 7;
1429 }
1430 }
1431
1432 if (limit == 0)
1433 limit = max_single_nop_size;
1434
1435 if (fragP->fr_type == rs_fill_nop)
1436 {
1437 /* Output NOPs for .nop directive. */
1438 if (limit > max_single_nop_size)
1439 {
1440 as_bad_where (fragP->fr_file, fragP->fr_line,
1441 _("invalid single nop size: %d "
1442 "(expect within [0, %d])"),
1443 limit, max_single_nop_size);
1444 return;
1445 }
1446 }
1447 else
1448 fragP->fr_var = count;
1449
1450 if ((count / max_single_nop_size) > max_number_of_nops)
1451 {
1452 /* Generate jump over NOPs. */
1453 offsetT disp = count - 2;
1454 if (fits_in_imm7 (disp))
1455 {
1456 /* Use "jmp disp8" if possible. */
1457 count = disp;
1458 where[0] = jump_disp8[0];
1459 where[1] = count;
1460 where += 2;
1461 }
1462 else
1463 {
1464 unsigned int size_of_jump;
1465
1466 if (flag_code == CODE_16BIT)
1467 {
1468 where[0] = jump16_disp32[0];
1469 where[1] = jump16_disp32[1];
1470 size_of_jump = 2;
1471 }
1472 else
1473 {
1474 where[0] = jump32_disp32[0];
1475 size_of_jump = 1;
1476 }
1477
1478 count -= size_of_jump + 4;
1479 if (!fits_in_imm31 (count))
1480 {
1481 as_bad_where (fragP->fr_file, fragP->fr_line,
1482 _("jump over nop padding out of range"));
1483 return;
1484 }
1485
1486 md_number_to_chars (where + size_of_jump, count, 4);
1487 where += size_of_jump + 4;
76bc74dc 1488 }
ccc9c027 1489 }
3ae729d5
L		 1490
1491 /* Generate multiple NOPs. */
1492 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1493}
1494
c6fb90c8 1495static INLINE int
0dfbf9d7 1496operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1497{
0dfbf9d7 1498 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1499 {
1500 case 3:
0dfbf9d7 1501 if (x->array[2])
c6fb90c8 1502 return 0;
1a0670f3 1503 /* Fall through. */
c6fb90c8 1504 case 2:
0dfbf9d7 1505 if (x->array[1])
c6fb90c8 1506 return 0;
1a0670f3 1507 /* Fall through. */
c6fb90c8 1508 case 1:
0dfbf9d7 1509 return !x->array[0];
c6fb90c8
L		 1510 default:
1511 abort ();
1512 }
40fb9820
L		 1513}
1514
c6fb90c8 1515static INLINE void
0dfbf9d7 1516operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1517{
0dfbf9d7 1518 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1519 {
1520 case 3:
0dfbf9d7 1521 x->array[2] = v;
1a0670f3 1522 /* Fall through. */
c6fb90c8 1523 case 2:
0dfbf9d7 1524 x->array[1] = v;
1a0670f3 1525 /* Fall through. */
c6fb90c8 1526 case 1:
0dfbf9d7 1527 x->array[0] = v;
1a0670f3 1528 /* Fall through. */
c6fb90c8
L		 1529 break;
1530 default:
1531 abort ();
1532 }
1533}
40fb9820 1534
c6fb90c8 1535static INLINE int
0dfbf9d7
L		 1536operand_type_equal (const union i386_operand_type *x,
1537 const union i386_operand_type *y)
c6fb90c8 1538{
0dfbf9d7 1539 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1540 {
1541 case 3:
0dfbf9d7 1542 if (x->array[2] != y->array[2])
c6fb90c8 1543 return 0;
1a0670f3 1544 /* Fall through. */
c6fb90c8 1545 case 2:
0dfbf9d7 1546 if (x->array[1] != y->array[1])
c6fb90c8 1547 return 0;
1a0670f3 1548 /* Fall through. */
c6fb90c8 1549 case 1:
0dfbf9d7 1550 return x->array[0] == y->array[0];
c6fb90c8
L		 1551 break;
1552 default:
1553 abort ();
1554 }
1555}
40fb9820 1556
0dfbf9d7
L		 1557static INLINE int
1558cpu_flags_all_zero (const union i386_cpu_flags *x)
1559{
1560 switch (ARRAY_SIZE(x->array))
1561 {
53467f57
IT		 1562 case 4:
1563 if (x->array[3])
1564 return 0;
1565 /* Fall through. */
0dfbf9d7
L		 1566 case 3:
1567 if (x->array[2])
1568 return 0;
1a0670f3 1569 /* Fall through. */
0dfbf9d7
L		 1570 case 2:
1571 if (x->array[1])
1572 return 0;
1a0670f3 1573 /* Fall through. */
0dfbf9d7
L		 1574 case 1:
1575 return !x->array[0];
1576 default:
1577 abort ();
1578 }
1579}
1580
0dfbf9d7
L		 1581static INLINE int
1582cpu_flags_equal (const union i386_cpu_flags *x,
1583 const union i386_cpu_flags *y)
1584{
1585 switch (ARRAY_SIZE(x->array))
1586 {
53467f57
IT		 1587 case 4:
1588 if (x->array[3] != y->array[3])
1589 return 0;
1590 /* Fall through. */
0dfbf9d7
L		 1591 case 3:
1592 if (x->array[2] != y->array[2])
1593 return 0;
1a0670f3 1594 /* Fall through. */
0dfbf9d7
L		 1595 case 2:
1596 if (x->array[1] != y->array[1])
1597 return 0;
1a0670f3 1598 /* Fall through. */
0dfbf9d7
L		 1599 case 1:
1600 return x->array[0] == y->array[0];
1601 break;
1602 default:
1603 abort ();
1604 }
1605}
c6fb90c8
L		 1606
1607static INLINE int
1608cpu_flags_check_cpu64 (i386_cpu_flags f)
1609{
1610 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1611 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1612}
1613
c6fb90c8
L		 1614static INLINE i386_cpu_flags
1615cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1616{
c6fb90c8
L		 1617 switch (ARRAY_SIZE (x.array))
1618 {
53467f57
IT		 1619 case 4:
1620 x.array [3] &= y.array [3];
1621 /* Fall through. */
c6fb90c8
L		 1622 case 3:
1623 x.array [2] &= y.array [2];
1a0670f3 1624 /* Fall through. */
c6fb90c8
L		 1625 case 2:
1626 x.array [1] &= y.array [1];
1a0670f3 1627 /* Fall through. */
c6fb90c8
L		 1628 case 1:
1629 x.array [0] &= y.array [0];
1630 break;
1631 default:
1632 abort ();
1633 }
1634 return x;
1635}
40fb9820 1636
c6fb90c8
L		 1637static INLINE i386_cpu_flags
1638cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1639{
c6fb90c8 1640 switch (ARRAY_SIZE (x.array))
40fb9820 1641 {
53467f57
IT		 1642 case 4:
1643 x.array [3] |= y.array [3];
1644 /* Fall through. */
c6fb90c8
L		 1645 case 3:
1646 x.array [2] |= y.array [2];
1a0670f3 1647 /* Fall through. */
c6fb90c8
L		 1648 case 2:
1649 x.array [1] |= y.array [1];
1a0670f3 1650 /* Fall through. */
c6fb90c8
L		 1651 case 1:
1652 x.array [0] |= y.array [0];
40fb9820
L		 1653 break;
1654 default:
1655 abort ();
1656 }
40fb9820
L		 1657 return x;
1658}
1659
309d3373
JB		 1660static INLINE i386_cpu_flags
1661cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1662{
1663 switch (ARRAY_SIZE (x.array))
1664 {
53467f57
IT		 1665 case 4:
1666 x.array [3] &= ~y.array [3];
1667 /* Fall through. */
309d3373
JB		 1668 case 3:
1669 x.array [2] &= ~y.array [2];
1a0670f3 1670 /* Fall through. */
309d3373
JB		 1671 case 2:
1672 x.array [1] &= ~y.array [1];
1a0670f3 1673 /* Fall through. */
309d3373
JB		 1674 case 1:
1675 x.array [0] &= ~y.array [0];
1676 break;
1677 default:
1678 abort ();
1679 }
1680 return x;
1681}
1682
c0f3af97
L		 1683#define CPU_FLAGS_ARCH_MATCH 0x1
1684#define CPU_FLAGS_64BIT_MATCH 0x2
1685
c0f3af97 1686#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1687 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1688
1689/* Return CPU flags match bits. */
3629bb00 1690
40fb9820 1691static int
d3ce72d0 1692cpu_flags_match (const insn_template *t)
40fb9820 1693{
c0f3af97
L		 1694 i386_cpu_flags x = t->cpu_flags;
1695 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1696
1697 x.bitfield.cpu64 = 0;
1698 x.bitfield.cpuno64 = 0;
1699
0dfbf9d7 1700 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1701 {
1702 /* This instruction is available on all archs. */
db12e14e 1703 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1704 }
3629bb00
L		 1705 else
1706 {
c0f3af97 1707 /* This instruction is available only on some archs. */
3629bb00
L		 1708 i386_cpu_flags cpu = cpu_arch_flags;
1709
ab592e75
JB		 1710 /* AVX512VL is no standalone feature - match it and then strip it. */
1711 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1712 return match;
1713 x.bitfield.cpuavx512vl = 0;
1714
3629bb00 1715 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1716 if (!cpu_flags_all_zero (&cpu))
1717 {
a5ff0eb2
L		 1718 if (x.bitfield.cpuavx)
1719 {
929f69fa 1720 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1721 if (cpu.bitfield.cpuavx
1722 && (!t->opcode_modifier.sse2avx || sse2avx)
1723 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1724 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1725 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1726 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1727 }
929f69fa
JB		 1728 else if (x.bitfield.cpuavx512f)
1729 {
1730 /* We need to check a few extra flags with AVX512F. */
1731 if (cpu.bitfield.cpuavx512f
1732 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1733 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1734 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1736 }
a5ff0eb2 1737 else
db12e14e 1738 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1739 }
3629bb00 1740 }
c0f3af97 1741 return match;
40fb9820
L		 1742}
1743
c6fb90c8
L		 1744static INLINE i386_operand_type
1745operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1746{
c6fb90c8
L		 1747 switch (ARRAY_SIZE (x.array))
1748 {
1749 case 3:
1750 x.array [2] &= y.array [2];
1a0670f3 1751 /* Fall through. */
c6fb90c8
L		 1752 case 2:
1753 x.array [1] &= y.array [1];
1a0670f3 1754 /* Fall through. */
c6fb90c8
L		 1755 case 1:
1756 x.array [0] &= y.array [0];
1757 break;
1758 default:
1759 abort ();
1760 }
1761 return x;
40fb9820
L		 1762}
1763
73053c1f
JB		 1764static INLINE i386_operand_type
1765operand_type_and_not (i386_operand_type x, i386_operand_type y)
1766{
1767 switch (ARRAY_SIZE (x.array))
1768 {
1769 case 3:
1770 x.array [2] &= ~y.array [2];
1771 /* Fall through. */
1772 case 2:
1773 x.array [1] &= ~y.array [1];
1774 /* Fall through. */
1775 case 1:
1776 x.array [0] &= ~y.array [0];
1777 break;
1778 default:
1779 abort ();
1780 }
1781 return x;
1782}
1783
c6fb90c8
L		 1784static INLINE i386_operand_type
1785operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1786{
c6fb90c8 1787 switch (ARRAY_SIZE (x.array))
40fb9820 1788 {
c6fb90c8
L		 1789 case 3:
1790 x.array [2] |= y.array [2];
1a0670f3 1791 /* Fall through. */
c6fb90c8
L		 1792 case 2:
1793 x.array [1] |= y.array [1];
1a0670f3 1794 /* Fall through. */
c6fb90c8
L		 1795 case 1:
1796 x.array [0] |= y.array [0];
40fb9820
L		 1797 break;
1798 default:
1799 abort ();
1800 }
c6fb90c8
L		 1801 return x;
1802}
40fb9820 1803
c6fb90c8
L		 1804static INLINE i386_operand_type
1805operand_type_xor (i386_operand_type x, i386_operand_type y)
1806{
1807 switch (ARRAY_SIZE (x.array))
1808 {
1809 case 3:
1810 x.array [2] ^= y.array [2];
1a0670f3 1811 /* Fall through. */
c6fb90c8
L		 1812 case 2:
1813 x.array [1] ^= y.array [1];
1a0670f3 1814 /* Fall through. */
c6fb90c8
L		 1815 case 1:
1816 x.array [0] ^= y.array [0];
1817 break;
1818 default:
1819 abort ();
1820 }
40fb9820
L		 1821 return x;
1822}
1823
1824static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1825static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1826static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1827static const i386_operand_type inoutportreg
1828 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1829static const i386_operand_type reg16_inoutportreg
1830 = OPERAND_TYPE_REG16_INOUTPORTREG;
1831static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1832static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1833static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1834static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1835static const i386_operand_type anydisp
1836 = OPERAND_TYPE_ANYDISP;
40fb9820 1837static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1838static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1839static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1840static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1841static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1842static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1843static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1844static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1845static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1846static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1847static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1848static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1849
1850enum operand_type
1851{
1852 reg,
40fb9820
L		 1853 imm,
1854 disp,
1855 anymem
1856};
1857
c6fb90c8 1858static INLINE int
40fb9820
L		 1859operand_type_check (i386_operand_type t, enum operand_type c)
1860{
1861 switch (c)
1862 {
1863 case reg:
dc821c5f 1864 return t.bitfield.reg;
40fb9820 1865
40fb9820
L		 1866 case imm:
1867 return (t.bitfield.imm8
1868 || t.bitfield.imm8s
1869 || t.bitfield.imm16
1870 || t.bitfield.imm32
1871 || t.bitfield.imm32s
1872 || t.bitfield.imm64);
1873
1874 case disp:
1875 return (t.bitfield.disp8
1876 || t.bitfield.disp16
1877 || t.bitfield.disp32
1878 || t.bitfield.disp32s
1879 || t.bitfield.disp64);
1880
1881 case anymem:
1882 return (t.bitfield.disp8
1883 || t.bitfield.disp16
1884 || t.bitfield.disp32
1885 || t.bitfield.disp32s
1886 || t.bitfield.disp64
1887 || t.bitfield.baseindex);
1888
1889 default:
1890 abort ();
1891 }
2cfe26b6
AM		 1892
1893 return 0;
40fb9820
L		 1894}
1895
ca0d63fe 1896/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1897 operand J for instruction template T. */
1898
1899static INLINE int
d3ce72d0 1900match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1901{
1902 return !((i.types[j].bitfield.byte
1903 && !t->operand_types[j].bitfield.byte)
1904 || (i.types[j].bitfield.word
1905 && !t->operand_types[j].bitfield.word)
1906 || (i.types[j].bitfield.dword
1907 && !t->operand_types[j].bitfield.dword)
1908 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1909 && !t->operand_types[j].bitfield.qword)
1910 || (i.types[j].bitfield.tbyte
1911 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1912}
1913
1b54b8d7
JB		 1914/* Return 1 if there is no conflict in SIMD register on
1915 operand J for instruction template T. */
1916
1917static INLINE int
1918match_simd_size (const insn_template *t, unsigned int j)
1919{
1920 return !((i.types[j].bitfield.xmmword
1921 && !t->operand_types[j].bitfield.xmmword)
1922 || (i.types[j].bitfield.ymmword
1923 && !t->operand_types[j].bitfield.ymmword)
1924 || (i.types[j].bitfield.zmmword
1925 && !t->operand_types[j].bitfield.zmmword));
1926}
1927
5c07affc
L		 1928/* Return 1 if there is no conflict in any size on operand J for
1929 instruction template T. */
1930
1931static INLINE int
d3ce72d0 1932match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1933{
1934 return (match_reg_size (t, j)
1935 && !((i.types[j].bitfield.unspecified
af508cb9 1936 && !i.broadcast
5c07affc
L		 1937 && !t->operand_types[j].bitfield.unspecified)
1938 || (i.types[j].bitfield.fword
1939 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1940 /* For scalar opcode templates to allow register and memory
1941 operands at the same time, some special casing is needed
d6793fa1
JB		 1942 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1943 down-conversion vpmov*. */
1b54b8d7
JB		 1944 || ((t->operand_types[j].bitfield.regsimd
1945 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1946 && (t->operand_types[j].bitfield.byte
1947 || t->operand_types[j].bitfield.word
1948 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1949 || t->operand_types[j].bitfield.qword))
1950 ? (i.types[j].bitfield.xmmword
1951 || i.types[j].bitfield.ymmword
1952 || i.types[j].bitfield.zmmword)
1953 : !match_simd_size(t, j))));
5c07affc
L		 1954}
1955
1956/* Return 1 if there is no size conflict on any operands for
1957 instruction template T. */
1958
1959static INLINE int
d3ce72d0 1960operand_size_match (const insn_template *t)
5c07affc
L		 1961{
1962 unsigned int j;
1963 int match = 1;
1964
1965 /* Don't check jump instructions. */
1966 if (t->opcode_modifier.jump
1967 || t->opcode_modifier.jumpbyte
1968 || t->opcode_modifier.jumpdword
1969 || t->opcode_modifier.jumpintersegment)
1970 return match;
1971
1972 /* Check memory and accumulator operand size. */
1973 for (j = 0; j < i.operands; j++)
1974 {
1b54b8d7
JB		 1975 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1976 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1977 continue;
1978
1b54b8d7 1979 if (t->operand_types[j].bitfield.reg
dc821c5f 1980 && !match_reg_size (t, j))
5c07affc
L		 1981 {
1982 match = 0;
1983 break;
1984 }
1985
1b54b8d7
JB		 1986 if (t->operand_types[j].bitfield.regsimd
1987 && !match_simd_size (t, j))
1988 {
1989 match = 0;
1990 break;
1991 }
1992
1993 if (t->operand_types[j].bitfield.acc
1994 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1995 {
1996 match = 0;
1997 break;
1998 }
1999
5c07affc
L		 2000 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2001 {
2002 match = 0;
2003 break;
2004 }
2005 }
2006
891edac4 2007 if (match)
5c07affc 2008 return match;
38e314eb 2009 else if (!t->opcode_modifier.d)
891edac4
L		 2010 {
2011mismatch:
86e026a4 2012 i.error = operand_size_mismatch;
891edac4
L		 2013 return 0;
2014 }
5c07affc
L		 2015
2016 /* Check reverse. */
9c2799c2 2017 gas_assert (i.operands == 2);
5c07affc
L		 2018
2019 match = 1;
2020 for (j = 0; j < 2; j++)
2021 {
dc821c5f
JB		 2022 if ((t->operand_types[j].bitfield.reg
2023 || t->operand_types[j].bitfield.acc)
5c07affc 2024 && !match_reg_size (t, j ? 0 : 1))
891edac4 2025 goto mismatch;
5c07affc
L		 2026
2027 if (i.types[j].bitfield.mem
2028 && !match_mem_size (t, j ? 0 : 1))
891edac4 2029 goto mismatch;
5c07affc
L		 2030 }
2031
2032 return match;
2033}
2034
c6fb90c8 2035static INLINE int
40fb9820
L		 2036operand_type_match (i386_operand_type overlap,
2037 i386_operand_type given)
2038{
2039 i386_operand_type temp = overlap;
2040
2041 temp.bitfield.jumpabsolute = 0;
7d5e4556 2042 temp.bitfield.unspecified = 0;
5c07affc
L		 2043 temp.bitfield.byte = 0;
2044 temp.bitfield.word = 0;
2045 temp.bitfield.dword = 0;
2046 temp.bitfield.fword = 0;
2047 temp.bitfield.qword = 0;
2048 temp.bitfield.tbyte = 0;
2049 temp.bitfield.xmmword = 0;
c0f3af97 2050 temp.bitfield.ymmword = 0;
43234a1e 2051 temp.bitfield.zmmword = 0;
0dfbf9d7 2052 if (operand_type_all_zero (&temp))
891edac4 2053 goto mismatch;
40fb9820 2054
891edac4
L		 2055 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2056 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2057 return 1;
2058
2059mismatch:
a65babc9 2060 i.error = operand_type_mismatch;
891edac4 2061 return 0;
40fb9820
L		 2062}
2063
7d5e4556 2064/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2065 unless the expected operand type register overlap is null.
2066 Memory operand size of certain SIMD instructions is also being checked
2067 here. */
40fb9820 2068
c6fb90c8 2069static INLINE int
dc821c5f 2070operand_type_register_match (i386_operand_type g0,
40fb9820 2071 i386_operand_type t0,
40fb9820
L		 2072 i386_operand_type g1,
2073 i386_operand_type t1)
2074{
10c17abd
JB		 2075 if (!g0.bitfield.reg
2076 && !g0.bitfield.regsimd
2077 && (!operand_type_check (g0, anymem)
2078 || g0.bitfield.unspecified
2079 || !t0.bitfield.regsimd))
40fb9820
L		 2080 return 1;
2081
10c17abd
JB		 2082 if (!g1.bitfield.reg
2083 && !g1.bitfield.regsimd
2084 && (!operand_type_check (g1, anymem)
2085 || g1.bitfield.unspecified
2086 || !t1.bitfield.regsimd))
40fb9820
L		 2087 return 1;
2088
dc821c5f
JB		 2089 if (g0.bitfield.byte == g1.bitfield.byte
2090 && g0.bitfield.word == g1.bitfield.word
2091 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2092 && g0.bitfield.qword == g1.bitfield.qword
2093 && g0.bitfield.xmmword == g1.bitfield.xmmword
2094 && g0.bitfield.ymmword == g1.bitfield.ymmword
2095 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2096 return 1;
2097
dc821c5f
JB		 2098 if (!(t0.bitfield.byte & t1.bitfield.byte)
2099 && !(t0.bitfield.word & t1.bitfield.word)
2100 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2101 && !(t0.bitfield.qword & t1.bitfield.qword)
2102 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2103 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2104 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2105 return 1;
2106
a65babc9 2107 i.error = register_type_mismatch;
891edac4
L		 2108
2109 return 0;
40fb9820
L		 2110}
2111
4c692bc7
JB		 2112static INLINE unsigned int
2113register_number (const reg_entry *r)
2114{
2115 unsigned int nr = r->reg_num;
2116
2117 if (r->reg_flags & RegRex)
2118 nr += 8;
2119
200cbe0f
L		 2120 if (r->reg_flags & RegVRex)
2121 nr += 16;
2122
4c692bc7
JB		 2123 return nr;
2124}
2125
252b5132 2126static INLINE unsigned int
40fb9820 2127mode_from_disp_size (i386_operand_type t)
252b5132 2128{
b5014f7a 2129 if (t.bitfield.disp8)
40fb9820
L		 2130 return 1;
2131 else if (t.bitfield.disp16
2132 || t.bitfield.disp32
2133 || t.bitfield.disp32s)
2134 return 2;
2135 else
2136 return 0;
252b5132
RH		 2137}
2138
2139static INLINE int
65879393 2140fits_in_signed_byte (addressT num)
252b5132 2141{
65879393 2142 return num + 0x80 <= 0xff;
47926f60 2143}
252b5132
RH		 2144
2145static INLINE int
65879393 2146fits_in_unsigned_byte (addressT num)
252b5132 2147{
65879393 2148 return num <= 0xff;
47926f60 2149}
252b5132
RH		 2150
2151static INLINE int
65879393 2152fits_in_unsigned_word (addressT num)
252b5132 2153{
65879393 2154 return num <= 0xffff;
47926f60 2155}
252b5132
RH		 2156
2157static INLINE int
65879393 2158fits_in_signed_word (addressT num)
252b5132 2159{
65879393 2160 return num + 0x8000 <= 0xffff;
47926f60 2161}
2a962e6d 2162
3e73aa7c 2163static INLINE int
65879393 2164fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2165{
2166#ifndef BFD64
2167 return 1;
2168#else
65879393 2169 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2170#endif
2171} /* fits_in_signed_long() */
2a962e6d 2172
3e73aa7c 2173static INLINE int
65879393 2174fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2175{
2176#ifndef BFD64
2177 return 1;
2178#else
65879393 2179 return num <= 0xffffffff;
3e73aa7c
JH		 2180#endif
2181} /* fits_in_unsigned_long() */
252b5132 2182
43234a1e 2183static INLINE int
b5014f7a 2184fits_in_disp8 (offsetT num)
43234a1e
L		 2185{
2186 int shift = i.memshift;
2187 unsigned int mask;
2188
2189 if (shift == -1)
2190 abort ();
2191
2192 mask = (1 << shift) - 1;
2193
2194 /* Return 0 if NUM isn't properly aligned. */
2195 if ((num & mask))
2196 return 0;
2197
2198 /* Check if NUM will fit in 8bit after shift. */
2199 return fits_in_signed_byte (num >> shift);
2200}
2201
a683cc34
SP		 2202static INLINE int
2203fits_in_imm4 (offsetT num)
2204{
2205 return (num & 0xf) == num;
2206}
2207
40fb9820 2208static i386_operand_type
e3bb37b5 2209smallest_imm_type (offsetT num)
252b5132 2210{
40fb9820 2211 i386_operand_type t;
7ab9ffdd 2212
0dfbf9d7 2213 operand_type_set (&t, 0);
40fb9820
L		 2214 t.bitfield.imm64 = 1;
2215
2216 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2217 {
2218 /* This code is disabled on the 486 because all the Imm1 forms
2219 in the opcode table are slower on the i486. They're the
2220 versions with the implicitly specified single-position
2221 displacement, which has another syntax if you really want to
2222 use that form. */
40fb9820
L		 2223 t.bitfield.imm1 = 1;
2224 t.bitfield.imm8 = 1;
2225 t.bitfield.imm8s = 1;
2226 t.bitfield.imm16 = 1;
2227 t.bitfield.imm32 = 1;
2228 t.bitfield.imm32s = 1;
2229 }
2230 else if (fits_in_signed_byte (num))
2231 {
2232 t.bitfield.imm8 = 1;
2233 t.bitfield.imm8s = 1;
2234 t.bitfield.imm16 = 1;
2235 t.bitfield.imm32 = 1;
2236 t.bitfield.imm32s = 1;
2237 }
2238 else if (fits_in_unsigned_byte (num))
2239 {
2240 t.bitfield.imm8 = 1;
2241 t.bitfield.imm16 = 1;
2242 t.bitfield.imm32 = 1;
2243 t.bitfield.imm32s = 1;
2244 }
2245 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2246 {
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2250 }
2251 else if (fits_in_signed_long (num))
2252 {
2253 t.bitfield.imm32 = 1;
2254 t.bitfield.imm32s = 1;
2255 }
2256 else if (fits_in_unsigned_long (num))
2257 t.bitfield.imm32 = 1;
2258
2259 return t;
47926f60 2260}
252b5132 2261
847f7ad4 2262static offsetT
e3bb37b5 2263offset_in_range (offsetT val, int size)
847f7ad4 2264{
508866be 2265 addressT mask;
ba2adb93 2266
847f7ad4
AM		 2267 switch (size)
2268 {
508866be
L		 2269 case 1: mask = ((addressT) 1 << 8) - 1; break;
2270 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2271 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2272#ifdef BFD64
2273 case 8: mask = ((addressT) 2 << 63) - 1; break;
2274#endif
47926f60 2275 default: abort ();
847f7ad4
AM		 2276 }
2277
9de868bf
L		 2278#ifdef BFD64
2279 /* If BFD64, sign extend val for 32bit address mode. */
2280 if (flag_code != CODE_64BIT
2281 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2282 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2283 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2284#endif
ba2adb93 2285
47926f60 2286 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2287 {
2288 char buf1[40], buf2[40];
2289
2290 sprint_value (buf1, val);
2291 sprint_value (buf2, val & mask);
2292 as_warn (_("%s shortened to %s"), buf1, buf2);
2293 }
2294 return val & mask;
2295}
2296
c32fa91d
L		 2297enum PREFIX_GROUP
2298{
2299 PREFIX_EXIST = 0,
2300 PREFIX_LOCK,
2301 PREFIX_REP,
04ef582a 2302 PREFIX_DS,
c32fa91d
L		 2303 PREFIX_OTHER
2304};
2305
2306/* Returns
2307 a. PREFIX_EXIST if attempting to add a prefix where one from the
2308 same class already exists.
2309 b. PREFIX_LOCK if lock prefix is added.
2310 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2311 d. PREFIX_DS if ds prefix is added.
2312 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2313 */
2314
2315static enum PREFIX_GROUP
e3bb37b5 2316add_prefix (unsigned int prefix)
252b5132 2317{
c32fa91d 2318 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2319 unsigned int q;
252b5132 2320
29b0f896
AM		 2321 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2322 && flag_code == CODE_64BIT)
b1905489 2323 {
161a04f6
L		 2324 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2325 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2326 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2327 ret = PREFIX_EXIST;
b1905489
JB		 2328 q = REX_PREFIX;
2329 }
3e73aa7c 2330 else
b1905489
JB		 2331 {
2332 switch (prefix)
2333 {
2334 default:
2335 abort ();
2336
b1905489 2337 case DS_PREFIX_OPCODE:
04ef582a
L		 2338 ret = PREFIX_DS;
2339 /* Fall through. */
2340 case CS_PREFIX_OPCODE:
b1905489
JB		 2341 case ES_PREFIX_OPCODE:
2342 case FS_PREFIX_OPCODE:
2343 case GS_PREFIX_OPCODE:
2344 case SS_PREFIX_OPCODE:
2345 q = SEG_PREFIX;
2346 break;
2347
2348 case REPNE_PREFIX_OPCODE:
2349 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2350 q = REP_PREFIX;
2351 ret = PREFIX_REP;
2352 break;
2353
b1905489 2354 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2355 q = LOCK_PREFIX;
2356 ret = PREFIX_LOCK;
b1905489
JB		 2357 break;
2358
2359 case FWAIT_OPCODE:
2360 q = WAIT_PREFIX;
2361 break;
2362
2363 case ADDR_PREFIX_OPCODE:
2364 q = ADDR_PREFIX;
2365 break;
2366
2367 case DATA_PREFIX_OPCODE:
2368 q = DATA_PREFIX;
2369 break;
2370 }
2371 if (i.prefix[q] != 0)
c32fa91d 2372 ret = PREFIX_EXIST;
b1905489 2373 }
252b5132 2374
b1905489 2375 if (ret)
252b5132 2376 {
b1905489
JB		 2377 if (!i.prefix[q])
2378 ++i.prefixes;
2379 i.prefix[q] |= prefix;
252b5132 2380 }
b1905489
JB		 2381 else
2382 as_bad (_("same type of prefix used twice"));
252b5132 2383
252b5132
RH		 2384 return ret;
2385}
2386
2387static void
78f12dd3 2388update_code_flag (int value, int check)
eecb386c 2389{
78f12dd3
L		 2390 PRINTF_LIKE ((*as_error));
2391
1e9cc1c2 2392 flag_code = (enum flag_code) value;
40fb9820
L		 2393 if (flag_code == CODE_64BIT)
2394 {
2395 cpu_arch_flags.bitfield.cpu64 = 1;
2396 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2397 }
2398 else
2399 {
2400 cpu_arch_flags.bitfield.cpu64 = 0;
2401 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2402 }
2403 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2404 {
78f12dd3
L		 2405 if (check)
2406 as_error = as_fatal;
2407 else
2408 as_error = as_bad;
2409 (*as_error) (_("64bit mode not supported on `%s'."),
2410 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2411 }
40fb9820 2412 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2413 {
78f12dd3
L		 2414 if (check)
2415 as_error = as_fatal;
2416 else
2417 as_error = as_bad;
2418 (*as_error) (_("32bit mode not supported on `%s'."),
2419 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2420 }
eecb386c
AM		 2421 stackop_size = '\0';
2422}
2423
78f12dd3
L		 2424static void
2425set_code_flag (int value)
2426{
2427 update_code_flag (value, 0);
2428}
2429
eecb386c 2430static void
e3bb37b5 2431set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2432{
1e9cc1c2 2433 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2434 if (flag_code != CODE_16BIT)
2435 abort ();
2436 cpu_arch_flags.bitfield.cpu64 = 0;
2437 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2438 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2439}
2440
2441static void
e3bb37b5 2442set_intel_syntax (int syntax_flag)
252b5132
RH		 2443{
2444 /* Find out if register prefixing is specified. */
2445 int ask_naked_reg = 0;
2446
2447 SKIP_WHITESPACE ();
29b0f896 2448 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2449 {
d02603dc
NC		 2450 char *string;
2451 int e = get_symbol_name (&string);
252b5132 2452
47926f60 2453 if (strcmp (string, "prefix") == 0)
252b5132 2454 ask_naked_reg = 1;
47926f60 2455 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2456 ask_naked_reg = -1;
2457 else
d0b47220 2458 as_bad (_("bad argument to syntax directive."));
d02603dc 2459 (void) restore_line_pointer (e);
252b5132
RH		 2460 }
2461 demand_empty_rest_of_line ();
c3332e24 2462
252b5132
RH		 2463 intel_syntax = syntax_flag;
2464
2465 if (ask_naked_reg == 0)
f86103b7
AM		 2466 allow_naked_reg = (intel_syntax
2467 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2468 else
2469 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2470
ee86248c 2471 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2472
e4a3b5a4 2473 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2474 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2475 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2476}
2477
1efbbeb4
L		 2478static void
2479set_intel_mnemonic (int mnemonic_flag)
2480{
e1d4d893 2481 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2482}
2483
db51cc60
L		 2484static void
2485set_allow_index_reg (int flag)
2486{
2487 allow_index_reg = flag;
2488}
2489
cb19c032 2490static void
7bab8ab5 2491set_check (int what)
cb19c032 2492{
7bab8ab5
JB		 2493 enum check_kind *kind;
2494 const char *str;
2495
2496 if (what)
2497 {
2498 kind = &operand_check;
2499 str = "operand";
2500 }
2501 else
2502 {
2503 kind = &sse_check;
2504 str = "sse";
2505 }
2506
cb19c032
L		 2507 SKIP_WHITESPACE ();
2508
2509 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2510 {
d02603dc
NC		 2511 char *string;
2512 int e = get_symbol_name (&string);
cb19c032
L		 2513
2514 if (strcmp (string, "none") == 0)
7bab8ab5 2515 *kind = check_none;
cb19c032 2516 else if (strcmp (string, "warning") == 0)
7bab8ab5 2517 *kind = check_warning;
cb19c032 2518 else if (strcmp (string, "error") == 0)
7bab8ab5 2519 *kind = check_error;
cb19c032 2520 else
7bab8ab5 2521 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2522 (void) restore_line_pointer (e);
cb19c032
L		 2523 }
2524 else
7bab8ab5 2525 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2526
2527 demand_empty_rest_of_line ();
2528}
2529
8a9036a4
L		 2530static void
2531check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2532 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2533{
2534#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2535 static const char *arch;
2536
2537 /* Intel LIOM is only supported on ELF. */
2538 if (!IS_ELF)
2539 return;
2540
2541 if (!arch)
2542 {
2543 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2544 use default_arch. */
2545 arch = cpu_arch_name;
2546 if (!arch)
2547 arch = default_arch;
2548 }
2549
81486035
L		 2550 /* If we are targeting Intel MCU, we must enable it. */
2551 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2552 || new_flag.bitfield.cpuiamcu)
2553 return;
2554
3632d14b 2555 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2556 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2557 || new_flag.bitfield.cpul1om)
8a9036a4 2558 return;
76ba9986 2559
7a9068fe
L		 2560 /* If we are targeting Intel K1OM, we must enable it. */
2561 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2562 || new_flag.bitfield.cpuk1om)
2563 return;
2564
8a9036a4
L		 2565 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2566#endif
2567}
2568
e413e4e9 2569static void
e3bb37b5 2570set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2571{
47926f60 2572 SKIP_WHITESPACE ();
e413e4e9 2573
29b0f896 2574 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2575 {
d02603dc
NC		 2576 char *string;
2577 int e = get_symbol_name (&string);
91d6fa6a 2578 unsigned int j;
40fb9820 2579 i386_cpu_flags flags;
e413e4e9 2580
91d6fa6a 2581 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2582 {
91d6fa6a 2583 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2584 {
91d6fa6a 2585 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2586
5c6af06e
JB		 2587 if (*string != '.')
2588 {
91d6fa6a 2589 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2590 cpu_sub_arch_name = NULL;
91d6fa6a 2591 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2592 if (flag_code == CODE_64BIT)
2593 {
2594 cpu_arch_flags.bitfield.cpu64 = 1;
2595 cpu_arch_flags.bitfield.cpuno64 = 0;
2596 }
2597 else
2598 {
2599 cpu_arch_flags.bitfield.cpu64 = 0;
2600 cpu_arch_flags.bitfield.cpuno64 = 1;
2601 }
91d6fa6a
NC		 2602 cpu_arch_isa = cpu_arch[j].type;
2603 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2604 if (!cpu_arch_tune_set)
2605 {
2606 cpu_arch_tune = cpu_arch_isa;
2607 cpu_arch_tune_flags = cpu_arch_isa_flags;
2608 }
5c6af06e
JB		 2609 break;
2610 }
40fb9820 2611
293f5f65
L		 2612 flags = cpu_flags_or (cpu_arch_flags,
2613 cpu_arch[j].flags);
81486035 2614
5b64d091 2615 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2616 {
6305a203
L		 2617 if (cpu_sub_arch_name)
2618 {
2619 char *name = cpu_sub_arch_name;
2620 cpu_sub_arch_name = concat (name,
91d6fa6a 2621 cpu_arch[j].name,
1bf57e9f 2622 (const char *) NULL);
6305a203
L		 2623 free (name);
2624 }
2625 else
91d6fa6a 2626 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2627 cpu_arch_flags = flags;
a586129e 2628 cpu_arch_isa_flags = flags;
5c6af06e 2629 }
0089dace
L		 2630 else
2631 cpu_arch_isa_flags
2632 = cpu_flags_or (cpu_arch_isa_flags,
2633 cpu_arch[j].flags);
d02603dc 2634 (void) restore_line_pointer (e);
5c6af06e
JB		 2635 demand_empty_rest_of_line ();
2636 return;
e413e4e9
AM		 2637 }
2638 }
293f5f65
L		 2639
2640 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2641 {
33eaf5de 2642 /* Disable an ISA extension. */
293f5f65
L		 2643 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2644 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2645 {
2646 flags = cpu_flags_and_not (cpu_arch_flags,
2647 cpu_noarch[j].flags);
2648 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2649 {
2650 if (cpu_sub_arch_name)
2651 {
2652 char *name = cpu_sub_arch_name;
2653 cpu_sub_arch_name = concat (name, string,
2654 (const char *) NULL);
2655 free (name);
2656 }
2657 else
2658 cpu_sub_arch_name = xstrdup (string);
2659 cpu_arch_flags = flags;
2660 cpu_arch_isa_flags = flags;
2661 }
2662 (void) restore_line_pointer (e);
2663 demand_empty_rest_of_line ();
2664 return;
2665 }
2666
2667 j = ARRAY_SIZE (cpu_arch);
2668 }
2669
91d6fa6a 2670 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2671 as_bad (_("no such architecture: `%s'"), string);
2672
2673 *input_line_pointer = e;
2674 }
2675 else
2676 as_bad (_("missing cpu architecture"));
2677
fddf5b5b
AM		 2678 no_cond_jump_promotion = 0;
2679 if (*input_line_pointer == ','
29b0f896 2680 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2681 {
d02603dc
NC		 2682 char *string;
2683 char e;
2684
2685 ++input_line_pointer;
2686 e = get_symbol_name (&string);
fddf5b5b
AM		 2687
2688 if (strcmp (string, "nojumps") == 0)
2689 no_cond_jump_promotion = 1;
2690 else if (strcmp (string, "jumps") == 0)
2691 ;
2692 else
2693 as_bad (_("no such architecture modifier: `%s'"), string);
2694
d02603dc 2695 (void) restore_line_pointer (e);
fddf5b5b
AM		 2696 }
2697
e413e4e9
AM		 2698 demand_empty_rest_of_line ();
2699}
2700
8a9036a4
L		 2701enum bfd_architecture
2702i386_arch (void)
2703{
3632d14b 2704 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2705 {
2706 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2707 || flag_code != CODE_64BIT)
2708 as_fatal (_("Intel L1OM is 64bit ELF only"));
2709 return bfd_arch_l1om;
2710 }
7a9068fe
L		 2711 else if (cpu_arch_isa == PROCESSOR_K1OM)
2712 {
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel K1OM is 64bit ELF only"));
2716 return bfd_arch_k1om;
2717 }
81486035
L		 2718 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2719 {
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code == CODE_64BIT)
2722 as_fatal (_("Intel MCU is 32bit ELF only"));
2723 return bfd_arch_iamcu;
2724 }
8a9036a4
L		 2725 else
2726 return bfd_arch_i386;
2727}
2728
b9d79e03 2729unsigned long
7016a5d5 2730i386_mach (void)
b9d79e03 2731{
351f65ca 2732 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2733 {
3632d14b 2734 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2735 {
351f65ca
L		 2736 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2737 || default_arch[6] != '\0')
8a9036a4
L		 2738 as_fatal (_("Intel L1OM is 64bit ELF only"));
2739 return bfd_mach_l1om;
2740 }
7a9068fe
L		 2741 else if (cpu_arch_isa == PROCESSOR_K1OM)
2742 {
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
2745 as_fatal (_("Intel K1OM is 64bit ELF only"));
2746 return bfd_mach_k1om;
2747 }
351f65ca 2748 else if (default_arch[6] == '\0')
8a9036a4 2749 return bfd_mach_x86_64;
351f65ca
L		 2750 else
2751 return bfd_mach_x64_32;
8a9036a4 2752 }
5197d474
L		 2753 else if (!strcmp (default_arch, "i386")
2754 || !strcmp (default_arch, "iamcu"))
81486035
L		 2755 {
2756 if (cpu_arch_isa == PROCESSOR_IAMCU)
2757 {
2758 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2759 as_fatal (_("Intel MCU is 32bit ELF only"));
2760 return bfd_mach_i386_iamcu;
2761 }
2762 else
2763 return bfd_mach_i386_i386;
2764 }
b9d79e03 2765 else
2b5d6a91 2766 as_fatal (_("unknown architecture"));
b9d79e03 2767}
b9d79e03 2768\f
252b5132 2769void
7016a5d5 2770md_begin (void)
252b5132
RH		 2771{
2772 const char *hash_err;
2773
86fa6981
L		 2774 /* Support pseudo prefixes like {disp32}. */
2775 lex_type ['{'] = LEX_BEGIN_NAME;
2776
47926f60 2777 /* Initialize op_hash hash table. */
252b5132
RH		 2778 op_hash = hash_new ();
2779
2780 {
d3ce72d0 2781 const insn_template *optab;
29b0f896 2782 templates *core_optab;
252b5132 2783
47926f60
KH		 2784 /* Setup for loop. */
2785 optab = i386_optab;
add39d23 2786 core_optab = XNEW (templates);
252b5132
RH		 2787 core_optab->start = optab;
2788
2789 while (1)
2790 {
2791 ++optab;
2792 if (optab->name == NULL
2793 || strcmp (optab->name, (optab - 1)->name) != 0)
2794 {
2795 /* different name --> ship out current template list;
47926f60 2796 add to hash table; & begin anew. */
252b5132
RH		 2797 core_optab->end = optab;
2798 hash_err = hash_insert (op_hash,
2799 (optab - 1)->name,
5a49b8ac 2800 (void *) core_optab);
252b5132
RH		 2801 if (hash_err)
2802 {
b37df7c4 2803 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2804 (optab - 1)->name,
2805 hash_err);
2806 }
2807 if (optab->name == NULL)
2808 break;
add39d23 2809 core_optab = XNEW (templates);
252b5132
RH		 2810 core_optab->start = optab;
2811 }
2812 }
2813 }
2814
47926f60 2815 /* Initialize reg_hash hash table. */
252b5132
RH		 2816 reg_hash = hash_new ();
2817 {
29b0f896 2818 const reg_entry *regtab;
c3fe08fa 2819 unsigned int regtab_size = i386_regtab_size;
252b5132 2820
c3fe08fa 2821 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2822 {
5a49b8ac 2823 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2824 if (hash_err)
b37df7c4 2825 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2826 regtab->reg_name,
2827 hash_err);
252b5132
RH		 2828 }
2829 }
2830
47926f60 2831 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2832 {
29b0f896
AM		 2833 int c;
2834 char *p;
252b5132
RH		 2835
2836 for (c = 0; c < 256; c++)
2837 {
3882b010 2838 if (ISDIGIT (c))
252b5132
RH		 2839 {
2840 digit_chars[c] = c;
2841 mnemonic_chars[c] = c;
2842 register_chars[c] = c;
2843 operand_chars[c] = c;
2844 }
3882b010 2845 else if (ISLOWER (c))
252b5132
RH		 2846 {
2847 mnemonic_chars[c] = c;
2848 register_chars[c] = c;
2849 operand_chars[c] = c;
2850 }
3882b010 2851 else if (ISUPPER (c))
252b5132 2852 {
3882b010 2853 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2854 register_chars[c] = mnemonic_chars[c];
2855 operand_chars[c] = c;
2856 }
43234a1e 2857 else if (c == '{' || c == '}')
86fa6981
L		 2858 {
2859 mnemonic_chars[c] = c;
2860 operand_chars[c] = c;
2861 }
252b5132 2862
3882b010 2863 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2864 identifier_chars[c] = c;
2865 else if (c >= 128)
2866 {
2867 identifier_chars[c] = c;
2868 operand_chars[c] = c;
2869 }
2870 }
2871
2872#ifdef LEX_AT
2873 identifier_chars['@'] = '@';
32137342
NC		 2874#endif
2875#ifdef LEX_QM
2876 identifier_chars['?'] = '?';
2877 operand_chars['?'] = '?';
252b5132 2878#endif
252b5132 2879 digit_chars['-'] = '-';
c0f3af97 2880 mnemonic_chars['_'] = '_';
791fe849 2881 mnemonic_chars['-'] = '-';
0003779b 2882 mnemonic_chars['.'] = '.';
252b5132
RH		 2883 identifier_chars['_'] = '_';
2884 identifier_chars['.'] = '.';
2885
2886 for (p = operand_special_chars; *p != '\0'; p++)
2887 operand_chars[(unsigned char) *p] = *p;
2888 }
2889
a4447b93
RH		 2890 if (flag_code == CODE_64BIT)
2891 {
ca19b261
KT		 2892#if defined (OBJ_COFF) && defined (TE_PE)
2893 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2894 ? 32 : 16);
2895#else
a4447b93 2896 x86_dwarf2_return_column = 16;
ca19b261 2897#endif
61ff971f 2898 x86_cie_data_alignment = -8;
a4447b93
RH		 2899 }
2900 else
2901 {
2902 x86_dwarf2_return_column = 8;
2903 x86_cie_data_alignment = -4;
2904 }
252b5132
RH		 2905}
2906
2907void
e3bb37b5 2908i386_print_statistics (FILE *file)
252b5132
RH		 2909{
2910 hash_print_statistics (file, "i386 opcode", op_hash);
2911 hash_print_statistics (file, "i386 register", reg_hash);
2912}
2913\f
252b5132
RH		 2914#ifdef DEBUG386
2915
ce8a8b2f 2916/* Debugging routines for md_assemble. */
d3ce72d0 2917static void pte (insn_template *);
40fb9820 2918static void pt (i386_operand_type);
e3bb37b5
L		 2919static void pe (expressionS *);
2920static void ps (symbolS *);
252b5132
RH		 2921
2922static void
e3bb37b5 2923pi (char *line, i386_insn *x)
252b5132 2924{
09137c09 2925 unsigned int j;
252b5132
RH		 2926
2927 fprintf (stdout, "%s: template ", line);
2928 pte (&x->tm);
09f131f2
JH		 2929 fprintf (stdout, " address: base %s index %s scale %x\n",
2930 x->base_reg ? x->base_reg->reg_name : "none",
2931 x->index_reg ? x->index_reg->reg_name : "none",
2932 x->log2_scale_factor);
2933 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2934 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2935 fprintf (stdout, " sib: base %x index %x scale %x\n",
2936 x->sib.base, x->sib.index, x->sib.scale);
2937 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2938 (x->rex & REX_W) != 0,
2939 (x->rex & REX_R) != 0,
2940 (x->rex & REX_X) != 0,
2941 (x->rex & REX_B) != 0);
09137c09 2942 for (j = 0; j < x->operands; j++)
252b5132 2943 {
09137c09
SP		 2944 fprintf (stdout, " #%d: ", j + 1);
2945 pt (x->types[j]);
252b5132 2946 fprintf (stdout, "\n");
dc821c5f 2947 if (x->types[j].bitfield.reg
09137c09 2948 || x->types[j].bitfield.regmmx
1b54b8d7 2949 || x->types[j].bitfield.regsimd
09137c09
SP		 2950 || x->types[j].bitfield.sreg2
2951 || x->types[j].bitfield.sreg3
2952 || x->types[j].bitfield.control
2953 || x->types[j].bitfield.debug
2954 || x->types[j].bitfield.test)
2955 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2956 if (operand_type_check (x->types[j], imm))
2957 pe (x->op[j].imms);
2958 if (operand_type_check (x->types[j], disp))
2959 pe (x->op[j].disps);
252b5132
RH		 2960 }
2961}
2962
2963static void
d3ce72d0 2964pte (insn_template *t)
252b5132 2965{
09137c09 2966 unsigned int j;
252b5132 2967 fprintf (stdout, " %d operands ", t->operands);
47926f60 2968 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2969 if (t->extension_opcode != None)
2970 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2971 if (t->opcode_modifier.d)
252b5132 2972 fprintf (stdout, "D");
40fb9820 2973 if (t->opcode_modifier.w)
252b5132
RH		 2974 fprintf (stdout, "W");
2975 fprintf (stdout, "\n");
09137c09 2976 for (j = 0; j < t->operands; j++)
252b5132 2977 {
09137c09
SP		 2978 fprintf (stdout, " #%d type ", j + 1);
2979 pt (t->operand_types[j]);
252b5132
RH		 2980 fprintf (stdout, "\n");
2981 }
2982}
2983
2984static void
e3bb37b5 2985pe (expressionS *e)
252b5132 2986{
24eab124 2987 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2988 fprintf (stdout, " add_number %ld (%lx)\n",
2989 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2990 if (e->X_add_symbol)
2991 {
2992 fprintf (stdout, " add_symbol ");
2993 ps (e->X_add_symbol);
2994 fprintf (stdout, "\n");
2995 }
2996 if (e->X_op_symbol)
2997 {
2998 fprintf (stdout, " op_symbol ");
2999 ps (e->X_op_symbol);
3000 fprintf (stdout, "\n");
3001 }
3002}
3003
3004static void
e3bb37b5 3005ps (symbolS *s)
252b5132
RH		 3006{
3007 fprintf (stdout, "%s type %s%s",
3008 S_GET_NAME (s),
3009 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3010 segment_name (S_GET_SEGMENT (s)));
3011}
3012
7b81dfbb 3013static struct type_name
252b5132 3014 {
40fb9820
L		 3015 i386_operand_type mask;
3016 const char *name;
252b5132 3017 }
7b81dfbb 3018const type_names[] =
252b5132 3019{
40fb9820
L		 3020 { OPERAND_TYPE_REG8, "r8" },
3021 { OPERAND_TYPE_REG16, "r16" },
3022 { OPERAND_TYPE_REG32, "r32" },
3023 { OPERAND_TYPE_REG64, "r64" },
3024 { OPERAND_TYPE_IMM8, "i8" },
3025 { OPERAND_TYPE_IMM8, "i8s" },
3026 { OPERAND_TYPE_IMM16, "i16" },
3027 { OPERAND_TYPE_IMM32, "i32" },
3028 { OPERAND_TYPE_IMM32S, "i32s" },
3029 { OPERAND_TYPE_IMM64, "i64" },
3030 { OPERAND_TYPE_IMM1, "i1" },
3031 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3032 { OPERAND_TYPE_DISP8, "d8" },
3033 { OPERAND_TYPE_DISP16, "d16" },
3034 { OPERAND_TYPE_DISP32, "d32" },
3035 { OPERAND_TYPE_DISP32S, "d32s" },
3036 { OPERAND_TYPE_DISP64, "d64" },
3037 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3038 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3039 { OPERAND_TYPE_CONTROL, "control reg" },
3040 { OPERAND_TYPE_TEST, "test reg" },
3041 { OPERAND_TYPE_DEBUG, "debug reg" },
3042 { OPERAND_TYPE_FLOATREG, "FReg" },
3043 { OPERAND_TYPE_FLOATACC, "FAcc" },
3044 { OPERAND_TYPE_SREG2, "SReg2" },
3045 { OPERAND_TYPE_SREG3, "SReg3" },
3046 { OPERAND_TYPE_ACC, "Acc" },
3047 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3048 { OPERAND_TYPE_REGMMX, "rMMX" },
3049 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3050 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3051 { OPERAND_TYPE_REGZMM, "rZMM" },
3052 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3053 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3054};
3055
3056static void
40fb9820 3057pt (i386_operand_type t)
252b5132 3058{
40fb9820 3059 unsigned int j;
c6fb90c8 3060 i386_operand_type a;
252b5132 3061
40fb9820 3062 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3063 {
3064 a = operand_type_and (t, type_names[j].mask);
0349dc08 3065 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3066 fprintf (stdout, "%s, ", type_names[j].name);
3067 }
252b5132
RH		 3068 fflush (stdout);
3069}
3070
3071#endif /* DEBUG386 */
3072\f
252b5132 3073static bfd_reloc_code_real_type
3956db08 3074reloc (unsigned int size,
64e74474
AM		 3075 int pcrel,
3076 int sign,
3077 bfd_reloc_code_real_type other)
252b5132 3078{
47926f60 3079 if (other != NO_RELOC)
3956db08 3080 {
91d6fa6a 3081 reloc_howto_type *rel;
3956db08
JB		 3082
3083 if (size == 8)
3084 switch (other)
3085 {
64e74474
AM		 3086 case BFD_RELOC_X86_64_GOT32:
3087 return BFD_RELOC_X86_64_GOT64;
3088 break;
553d1284
L		 3089 case BFD_RELOC_X86_64_GOTPLT64:
3090 return BFD_RELOC_X86_64_GOTPLT64;
3091 break;
64e74474
AM		 3092 case BFD_RELOC_X86_64_PLTOFF64:
3093 return BFD_RELOC_X86_64_PLTOFF64;
3094 break;
3095 case BFD_RELOC_X86_64_GOTPC32:
3096 other = BFD_RELOC_X86_64_GOTPC64;
3097 break;
3098 case BFD_RELOC_X86_64_GOTPCREL:
3099 other = BFD_RELOC_X86_64_GOTPCREL64;
3100 break;
3101 case BFD_RELOC_X86_64_TPOFF32:
3102 other = BFD_RELOC_X86_64_TPOFF64;
3103 break;
3104 case BFD_RELOC_X86_64_DTPOFF32:
3105 other = BFD_RELOC_X86_64_DTPOFF64;
3106 break;
3107 default:
3108 break;
3956db08 3109 }
e05278af 3110
8ce3d284 3111#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3112 if (other == BFD_RELOC_SIZE32)
3113 {
3114 if (size == 8)
1ab668bf 3115 other = BFD_RELOC_SIZE64;
8fd4256d 3116 if (pcrel)
1ab668bf
AM		 3117 {
3118 as_bad (_("there are no pc-relative size relocations"));
3119 return NO_RELOC;
3120 }
8fd4256d 3121 }
8ce3d284 3122#endif
8fd4256d 3123
e05278af 3124 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3125 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3126 sign = -1;
3127
91d6fa6a
NC		 3128 rel = bfd_reloc_type_lookup (stdoutput, other);
3129 if (!rel)
3956db08 3130 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3131 else if (size != bfd_get_reloc_size (rel))
3956db08 3132 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3133 bfd_get_reloc_size (rel),
3956db08 3134 size);
91d6fa6a 3135 else if (pcrel && !rel->pc_relative)
3956db08 3136 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3137 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3138 && !sign)
91d6fa6a 3139 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3140 && sign > 0))
3956db08
JB		 3141 as_bad (_("relocated field and relocation type differ in signedness"));
3142 else
3143 return other;
3144 return NO_RELOC;
3145 }
252b5132
RH		 3146
3147 if (pcrel)
3148 {
3e73aa7c 3149 if (!sign)
3956db08 3150 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3151 switch (size)
3152 {
3153 case 1: return BFD_RELOC_8_PCREL;
3154 case 2: return BFD_RELOC_16_PCREL;
d258b828 3155 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3156 case 8: return BFD_RELOC_64_PCREL;
252b5132 3157 }
3956db08 3158 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3159 }
3160 else
3161 {
3956db08 3162 if (sign > 0)
e5cb08ac 3163 switch (size)
3e73aa7c
JH		 3164 {
3165 case 4: return BFD_RELOC_X86_64_32S;
3166 }
3167 else
3168 switch (size)
3169 {
3170 case 1: return BFD_RELOC_8;
3171 case 2: return BFD_RELOC_16;
3172 case 4: return BFD_RELOC_32;
3173 case 8: return BFD_RELOC_64;
3174 }
3956db08
JB		 3175 as_bad (_("cannot do %s %u byte relocation"),
3176 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3177 }
3178
0cc9e1d3 3179 return NO_RELOC;
252b5132
RH		 3180}
3181
47926f60
KH		 3182/* Here we decide which fixups can be adjusted to make them relative to
3183 the beginning of the section instead of the symbol. Basically we need
3184 to make sure that the dynamic relocations are done correctly, so in
3185 some cases we force the original symbol to be used. */
3186
252b5132 3187int
e3bb37b5 3188tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3189{
6d249963 3190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3191 if (!IS_ELF)
31312f95
AM		 3192 return 1;
3193
a161fe53
AM		 3194 /* Don't adjust pc-relative references to merge sections in 64-bit
3195 mode. */
3196 if (use_rela_relocations
3197 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3198 && fixP->fx_pcrel)
252b5132 3199 return 0;
31312f95 3200
8d01d9a9
AJ		 3201 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3202 and changed later by validate_fix. */
3203 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3204 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3205 return 0;
3206
8fd4256d
L		 3207 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3208 for size relocations. */
3209 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3210 || fixP->fx_r_type == BFD_RELOC_SIZE64
3211 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3212 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3213 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3214 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3225 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3227 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3233 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3240 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3241 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3242 return 0;
31312f95 3243#endif
252b5132
RH		 3244 return 1;
3245}
252b5132 3246
b4cac588 3247static int
e3bb37b5 3248intel_float_operand (const char *mnemonic)
252b5132 3249{
9306ca4a
JB		 3250 /* Note that the value returned is meaningful only for opcodes with (memory)
3251 operands, hence the code here is free to improperly handle opcodes that
3252 have no operands (for better performance and smaller code). */
3253
3254 if (mnemonic[0] != 'f')
3255 return 0; /* non-math */
3256
3257 switch (mnemonic[1])
3258 {
3259 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3260 the fs segment override prefix not currently handled because no
3261 call path can make opcodes without operands get here */
3262 case 'i':
3263 return 2 /* integer op */;
3264 case 'l':
3265 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3266 return 3; /* fldcw/fldenv */
3267 break;
3268 case 'n':
3269 if (mnemonic[2] != 'o' /* fnop */)
3270 return 3; /* non-waiting control op */
3271 break;
3272 case 'r':
3273 if (mnemonic[2] == 's')
3274 return 3; /* frstor/frstpm */
3275 break;
3276 case 's':
3277 if (mnemonic[2] == 'a')
3278 return 3; /* fsave */
3279 if (mnemonic[2] == 't')
3280 {
3281 switch (mnemonic[3])
3282 {
3283 case 'c': /* fstcw */
3284 case 'd': /* fstdw */
3285 case 'e': /* fstenv */
3286 case 's': /* fsts[gw] */
3287 return 3;
3288 }
3289 }
3290 break;
3291 case 'x':
3292 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3293 return 0; /* fxsave/fxrstor are not really math ops */
3294 break;
3295 }
252b5132 3296
9306ca4a 3297 return 1;
252b5132
RH		 3298}
3299
c0f3af97
L		 3300/* Build the VEX prefix. */
3301
3302static void
d3ce72d0 3303build_vex_prefix (const insn_template *t)
c0f3af97
L		 3304{
3305 unsigned int register_specifier;
3306 unsigned int implied_prefix;
3307 unsigned int vector_length;
3308
3309 /* Check register specifier. */
3310 if (i.vex.register_specifier)
43234a1e
L		 3311 {
3312 register_specifier =
3313 ~register_number (i.vex.register_specifier) & 0xf;
3314 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3315 }
c0f3af97
L		 3316 else
3317 register_specifier = 0xf;
3318
33eaf5de 3319 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3320 operand. */
86fa6981
L		 3321 if (i.vec_encoding != vex_encoding_vex3
3322 && i.dir_encoding == dir_encoding_default
fa99fab2 3323 && i.operands == i.reg_operands
7f399153 3324 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3325 && i.tm.opcode_modifier.load
fa99fab2
L		 3326 && i.rex == REX_B)
3327 {
3328 unsigned int xchg = i.operands - 1;
3329 union i386_op temp_op;
3330 i386_operand_type temp_type;
3331
3332 temp_type = i.types[xchg];
3333 i.types[xchg] = i.types[0];
3334 i.types[0] = temp_type;
3335 temp_op = i.op[xchg];
3336 i.op[xchg] = i.op[0];
3337 i.op[0] = temp_op;
3338
9c2799c2 3339 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3340
3341 i.rex = REX_R;
3342 xchg = i.rm.regmem;
3343 i.rm.regmem = i.rm.reg;
3344 i.rm.reg = xchg;
3345
3346 /* Use the next insn. */
3347 i.tm = t[1];
3348 }
3349
539f890d
L		 3350 if (i.tm.opcode_modifier.vex == VEXScalar)
3351 vector_length = avxscalar;
10c17abd
JB		 3352 else if (i.tm.opcode_modifier.vex == VEX256)
3353 vector_length = 1;
539f890d 3354 else
10c17abd
JB		 3355 {
3356 unsigned int op;
3357
3358 vector_length = 0;
3359 for (op = 0; op < t->operands; ++op)
3360 if (t->operand_types[op].bitfield.xmmword
3361 && t->operand_types[op].bitfield.ymmword
3362 && i.types[op].bitfield.ymmword)
3363 {
3364 vector_length = 1;
3365 break;
3366 }
3367 }
c0f3af97
L		 3368
3369 switch ((i.tm.base_opcode >> 8) & 0xff)
3370 {
3371 case 0:
3372 implied_prefix = 0;
3373 break;
3374 case DATA_PREFIX_OPCODE:
3375 implied_prefix = 1;
3376 break;
3377 case REPE_PREFIX_OPCODE:
3378 implied_prefix = 2;
3379 break;
3380 case REPNE_PREFIX_OPCODE:
3381 implied_prefix = 3;
3382 break;
3383 default:
3384 abort ();
3385 }
3386
3387 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3388 if (i.vec_encoding != vex_encoding_vex3
3389 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3390 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3391 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3392 {
3393 /* 2-byte VEX prefix. */
3394 unsigned int r;
3395
3396 i.vex.length = 2;
3397 i.vex.bytes[0] = 0xc5;
3398
3399 /* Check the REX.R bit. */
3400 r = (i.rex & REX_R) ? 0 : 1;
3401 i.vex.bytes[1] = (r << 7
3402 | register_specifier << 3
3403 | vector_length << 2
3404 | implied_prefix);
3405 }
3406 else
3407 {
3408 /* 3-byte VEX prefix. */
3409 unsigned int m, w;
3410
f88c9eb0 3411 i.vex.length = 3;
f88c9eb0 3412
7f399153 3413 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3414 {
7f399153
L		 3415 case VEX0F:
3416 m = 0x1;
80de6e00 3417 i.vex.bytes[0] = 0xc4;
7f399153
L		 3418 break;
3419 case VEX0F38:
3420 m = 0x2;
80de6e00 3421 i.vex.bytes[0] = 0xc4;
7f399153
L		 3422 break;
3423 case VEX0F3A:
3424 m = 0x3;
80de6e00 3425 i.vex.bytes[0] = 0xc4;
7f399153
L		 3426 break;
3427 case XOP08:
5dd85c99
SP		 3428 m = 0x8;
3429 i.vex.bytes[0] = 0x8f;
7f399153
L		 3430 break;
3431 case XOP09:
f88c9eb0
SP		 3432 m = 0x9;
3433 i.vex.bytes[0] = 0x8f;
7f399153
L		 3434 break;
3435 case XOP0A:
f88c9eb0
SP		 3436 m = 0xa;
3437 i.vex.bytes[0] = 0x8f;
7f399153
L		 3438 break;
3439 default:
3440 abort ();
f88c9eb0 3441 }
c0f3af97 3442
c0f3af97
L		 3443 /* The high 3 bits of the second VEX byte are 1's compliment
3444 of RXB bits from REX. */
3445 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3446
3447 /* Check the REX.W bit. */
3448 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3449 if (i.tm.opcode_modifier.vexw == VEXW1)
3450 w = 1;
c0f3af97
L		 3451
3452 i.vex.bytes[2] = (w << 7
3453 | register_specifier << 3
3454 | vector_length << 2
3455 | implied_prefix);
3456 }
3457}
3458
e771e7c9
JB		 3459static INLINE bfd_boolean
3460is_evex_encoding (const insn_template *t)
3461{
3462 return t->opcode_modifier.evex
3463 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3464 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3465}
3466
43234a1e
L		 3467/* Build the EVEX prefix. */
3468
3469static void
3470build_evex_prefix (void)
3471{
3472 unsigned int register_specifier;
3473 unsigned int implied_prefix;
3474 unsigned int m, w;
3475 rex_byte vrex_used = 0;
3476
3477 /* Check register specifier. */
3478 if (i.vex.register_specifier)
3479 {
3480 gas_assert ((i.vrex & REX_X) == 0);
3481
3482 register_specifier = i.vex.register_specifier->reg_num;
3483 if ((i.vex.register_specifier->reg_flags & RegRex))
3484 register_specifier += 8;
3485 /* The upper 16 registers are encoded in the fourth byte of the
3486 EVEX prefix. */
3487 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3488 i.vex.bytes[3] = 0x8;
3489 register_specifier = ~register_specifier & 0xf;
3490 }
3491 else
3492 {
3493 register_specifier = 0xf;
3494
3495 /* Encode upper 16 vector index register in the fourth byte of
3496 the EVEX prefix. */
3497 if (!(i.vrex & REX_X))
3498 i.vex.bytes[3] = 0x8;
3499 else
3500 vrex_used |= REX_X;
3501 }
3502
3503 switch ((i.tm.base_opcode >> 8) & 0xff)
3504 {
3505 case 0:
3506 implied_prefix = 0;
3507 break;
3508 case DATA_PREFIX_OPCODE:
3509 implied_prefix = 1;
3510 break;
3511 case REPE_PREFIX_OPCODE:
3512 implied_prefix = 2;
3513 break;
3514 case REPNE_PREFIX_OPCODE:
3515 implied_prefix = 3;
3516 break;
3517 default:
3518 abort ();
3519 }
3520
3521 /* 4 byte EVEX prefix. */
3522 i.vex.length = 4;
3523 i.vex.bytes[0] = 0x62;
3524
3525 /* mmmm bits. */
3526 switch (i.tm.opcode_modifier.vexopcode)
3527 {
3528 case VEX0F:
3529 m = 1;
3530 break;
3531 case VEX0F38:
3532 m = 2;
3533 break;
3534 case VEX0F3A:
3535 m = 3;
3536 break;
3537 default:
3538 abort ();
3539 break;
3540 }
3541
3542 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3543 bits from REX. */
3544 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3545
3546 /* The fifth bit of the second EVEX byte is 1's compliment of the
3547 REX_R bit in VREX. */
3548 if (!(i.vrex & REX_R))
3549 i.vex.bytes[1] |= 0x10;
3550 else
3551 vrex_used |= REX_R;
3552
3553 if ((i.reg_operands + i.imm_operands) == i.operands)
3554 {
3555 /* When all operands are registers, the REX_X bit in REX is not
3556 used. We reuse it to encode the upper 16 registers, which is
3557 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3558 as 1's compliment. */
3559 if ((i.vrex & REX_B))
3560 {
3561 vrex_used |= REX_B;
3562 i.vex.bytes[1] &= ~0x40;
3563 }
3564 }
3565
3566 /* EVEX instructions shouldn't need the REX prefix. */
3567 i.vrex &= ~vrex_used;
3568 gas_assert (i.vrex == 0);
3569
3570 /* Check the REX.W bit. */
3571 w = (i.rex & REX_W) ? 1 : 0;
3572 if (i.tm.opcode_modifier.vexw)
3573 {
3574 if (i.tm.opcode_modifier.vexw == VEXW1)
3575 w = 1;
3576 }
3577 /* If w is not set it means we are dealing with WIG instruction. */
3578 else if (!w)
3579 {
3580 if (evexwig == evexw1)
3581 w = 1;
3582 }
3583
3584 /* Encode the U bit. */
3585 implied_prefix |= 0x4;
3586
3587 /* The third byte of the EVEX prefix. */
3588 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3589
3590 /* The fourth byte of the EVEX prefix. */
3591 /* The zeroing-masking bit. */
3592 if (i.mask && i.mask->zeroing)
3593 i.vex.bytes[3] |= 0x80;
3594
3595 /* Don't always set the broadcast bit if there is no RC. */
3596 if (!i.rounding)
3597 {
3598 /* Encode the vector length. */
3599 unsigned int vec_length;
3600
e771e7c9
JB		 3601 if (!i.tm.opcode_modifier.evex
3602 || i.tm.opcode_modifier.evex == EVEXDYN)
3603 {
3604 unsigned int op;
3605
3606 vec_length = 0;
3607 for (op = 0; op < i.tm.operands; ++op)
3608 if (i.tm.operand_types[op].bitfield.xmmword
3609 + i.tm.operand_types[op].bitfield.ymmword
3610 + i.tm.operand_types[op].bitfield.zmmword > 1)
3611 {
3612 if (i.types[op].bitfield.zmmword)
3613 i.tm.opcode_modifier.evex = EVEX512;
3614 else if (i.types[op].bitfield.ymmword)
3615 i.tm.opcode_modifier.evex = EVEX256;
3616 else if (i.types[op].bitfield.xmmword)
3617 i.tm.opcode_modifier.evex = EVEX128;
3618 else
3619 continue;
3620 break;
3621 }
3622 }
3623
43234a1e
L		 3624 switch (i.tm.opcode_modifier.evex)
3625 {
3626 case EVEXLIG: /* LL' is ignored */
3627 vec_length = evexlig << 5;
3628 break;
3629 case EVEX128:
3630 vec_length = 0 << 5;
3631 break;
3632 case EVEX256:
3633 vec_length = 1 << 5;
3634 break;
3635 case EVEX512:
3636 vec_length = 2 << 5;
3637 break;
3638 default:
3639 abort ();
3640 break;
3641 }
3642 i.vex.bytes[3] |= vec_length;
3643 /* Encode the broadcast bit. */
3644 if (i.broadcast)
3645 i.vex.bytes[3] |= 0x10;
3646 }
3647 else
3648 {
3649 if (i.rounding->type != saeonly)
3650 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3651 else
d3d3c6db 3652 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3653 }
3654
3655 if (i.mask && i.mask->mask)
3656 i.vex.bytes[3] |= i.mask->mask->reg_num;
3657}
3658
65da13b5
L		 3659static void
3660process_immext (void)
3661{
3662 expressionS *exp;
3663
4c692bc7
JB		 3664 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3665 && i.operands > 0)
65da13b5 3666 {
4c692bc7
JB		 3667 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3668 with an opcode suffix which is coded in the same place as an
3669 8-bit immediate field would be.
3670 Here we check those operands and remove them afterwards. */
65da13b5
L		 3671 unsigned int x;
3672
3673 for (x = 0; x < i.operands; x++)
4c692bc7 3674 if (register_number (i.op[x].regs) != x)
65da13b5 3675 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3676 register_prefix, i.op[x].regs->reg_name, x + 1,
3677 i.tm.name);
3678
3679 i.operands = 0;
65da13b5
L		 3680 }
3681
9916071f
AP		 3682 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3683 {
3684 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3685 suffix which is coded in the same place as an 8-bit immediate
3686 field would be.
3687 Here we check those operands and remove them afterwards. */
3688 unsigned int x;
3689
3690 if (i.operands != 3)
3691 abort();
3692
3693 for (x = 0; x < 2; x++)
3694 if (register_number (i.op[x].regs) != x)
3695 goto bad_register_operand;
3696
3697 /* Check for third operand for mwaitx/monitorx insn. */
3698 if (register_number (i.op[x].regs)
3699 != (x + (i.tm.extension_opcode == 0xfb)))
3700 {
3701bad_register_operand:
3702 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3703 register_prefix, i.op[x].regs->reg_name, x+1,
3704 i.tm.name);
3705 }
3706
3707 i.operands = 0;
3708 }
3709
c0f3af97 3710 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3711 which is coded in the same place as an 8-bit immediate field
3712 would be. Here we fake an 8-bit immediate operand from the
3713 opcode suffix stored in tm.extension_opcode.
3714
c1e679ec 3715 AVX instructions also use this encoding, for some of
c0f3af97 3716 3 argument instructions. */
65da13b5 3717
43234a1e 3718 gas_assert (i.imm_operands <= 1
7ab9ffdd 3719 && (i.operands <= 2
43234a1e 3720 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3721 || i.tm.opcode_modifier.vexopcode
3722 || is_evex_encoding (&i.tm))
7ab9ffdd 3723 && i.operands <= 4)));
65da13b5
L		 3724
3725 exp = &im_expressions[i.imm_operands++];
3726 i.op[i.operands].imms = exp;
3727 i.types[i.operands] = imm8;
3728 i.operands++;
3729 exp->X_op = O_constant;
3730 exp->X_add_number = i.tm.extension_opcode;
3731 i.tm.extension_opcode = None;
3732}
3733
42164a71
L		 3734
3735static int
3736check_hle (void)
3737{
3738 switch (i.tm.opcode_modifier.hleprefixok)
3739 {
3740 default:
3741 abort ();
82c2def5 3742 case HLEPrefixNone:
165de32a
L		 3743 as_bad (_("invalid instruction `%s' after `%s'"),
3744 i.tm.name, i.hle_prefix);
42164a71 3745 return 0;
82c2def5 3746 case HLEPrefixLock:
42164a71
L		 3747 if (i.prefix[LOCK_PREFIX])
3748 return 1;
165de32a 3749 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3750 return 0;
82c2def5 3751 case HLEPrefixAny:
42164a71 3752 return 1;
82c2def5 3753 case HLEPrefixRelease:
42164a71
L		 3754 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3755 {
3756 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3757 i.tm.name);
3758 return 0;
3759 }
3760 if (i.mem_operands == 0
3761 || !operand_type_check (i.types[i.operands - 1], anymem))
3762 {
3763 as_bad (_("memory destination needed for instruction `%s'"
3764 " after `xrelease'"), i.tm.name);
3765 return 0;
3766 }
3767 return 1;
3768 }
3769}
3770
b6f8c7c4
L		 3771/* Try the shortest encoding by shortening operand size. */
3772
3773static void
3774optimize_encoding (void)
3775{
3776 int j;
3777
3778 if (optimize_for_space
3779 && i.reg_operands == 1
3780 && i.imm_operands == 1
3781 && !i.types[1].bitfield.byte
3782 && i.op[0].imms->X_op == O_constant
3783 && fits_in_imm7 (i.op[0].imms->X_add_number)
3784 && ((i.tm.base_opcode == 0xa8
3785 && i.tm.extension_opcode == None)
3786 || (i.tm.base_opcode == 0xf6
3787 && i.tm.extension_opcode == 0x0)))
3788 {
3789 /* Optimize: -Os:
3790 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3791 */
3792 unsigned int base_regnum = i.op[1].regs->reg_num;
3793 if (flag_code == CODE_64BIT || base_regnum < 4)
3794 {
3795 i.types[1].bitfield.byte = 1;
3796 /* Ignore the suffix. */
3797 i.suffix = 0;
3798 if (base_regnum >= 4
3799 && !(i.op[1].regs->reg_flags & RegRex))
3800 {
3801 /* Handle SP, BP, SI and DI registers. */
3802 if (i.types[1].bitfield.word)
3803 j = 16;
3804 else if (i.types[1].bitfield.dword)
3805 j = 32;
3806 else
3807 j = 48;
3808 i.op[1].regs -= j;
3809 }
3810 }
3811 }
3812 else if (flag_code == CODE_64BIT
d3d50934
L		 3813 && ((i.types[1].bitfield.qword
3814 && i.reg_operands == 1
b6f8c7c4
L		 3815 && i.imm_operands == 1
3816 && i.op[0].imms->X_op == O_constant
3817 && ((i.tm.base_opcode == 0xb0
3818 && i.tm.extension_opcode == None
3819 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3820 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3821 && (((i.tm.base_opcode == 0x24
3822 || i.tm.base_opcode == 0xa8)
3823 && i.tm.extension_opcode == None)
3824 || (i.tm.base_opcode == 0x80
3825 && i.tm.extension_opcode == 0x4)
3826 || ((i.tm.base_opcode == 0xf6
3827 || i.tm.base_opcode == 0xc6)
3828 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3829 || (i.types[0].bitfield.qword
3830 && ((i.reg_operands == 2
3831 && i.op[0].regs == i.op[1].regs
3832 && ((i.tm.base_opcode == 0x30
3833 || i.tm.base_opcode == 0x28)
3834 && i.tm.extension_opcode == None))
3835 || (i.reg_operands == 1
3836 && i.operands == 1
3837 && i.tm.base_opcode == 0x30
3838 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3839 {
3840 /* Optimize: -O:
3841 andq $imm31, %r64 -> andl $imm31, %r32
3842 testq $imm31, %r64 -> testl $imm31, %r32
3843 xorq %r64, %r64 -> xorl %r32, %r32
3844 subq %r64, %r64 -> subl %r32, %r32
3845 movq $imm31, %r64 -> movl $imm31, %r32
3846 movq $imm32, %r64 -> movl $imm32, %r32
3847 */
3848 i.tm.opcode_modifier.norex64 = 1;
3849 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3850 {
3851 /* Handle
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3854 */
3855 i.tm.operand_types[0].bitfield.imm32 = 1;
3856 i.tm.operand_types[0].bitfield.imm32s = 0;
3857 i.tm.operand_types[0].bitfield.imm64 = 0;
3858 i.types[0].bitfield.imm32 = 1;
3859 i.types[0].bitfield.imm32s = 0;
3860 i.types[0].bitfield.imm64 = 0;
3861 i.types[1].bitfield.dword = 1;
3862 i.types[1].bitfield.qword = 0;
3863 if (i.tm.base_opcode == 0xc6)
3864 {
3865 /* Handle
3866 movq $imm31, %r64 -> movl $imm31, %r32
3867 */
3868 i.tm.base_opcode = 0xb0;
3869 i.tm.extension_opcode = None;
3870 i.tm.opcode_modifier.shortform = 1;
3871 i.tm.opcode_modifier.modrm = 0;
3872 }
3873 }
3874 }
3875 else if (optimize > 1
3876 && i.reg_operands == 3
3877 && i.op[0].regs == i.op[1].regs
3878 && !i.types[2].bitfield.xmmword
3879 && (i.tm.opcode_modifier.vex
3880 || (!i.mask
3881 && !i.rounding
e771e7c9 3882 && is_evex_encoding (&i.tm)
80c34c38
L		 3883 && (i.vec_encoding != vex_encoding_evex
3884 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3885 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3886 && ((i.tm.base_opcode == 0x55
3887 || i.tm.base_opcode == 0x6655
3888 || i.tm.base_opcode == 0x66df
3889 || i.tm.base_opcode == 0x57
3890 || i.tm.base_opcode == 0x6657
8305403a
L		 3891 || i.tm.base_opcode == 0x66ef
3892 || i.tm.base_opcode == 0x66f8
3893 || i.tm.base_opcode == 0x66f9
3894 || i.tm.base_opcode == 0x66fa
3895 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3896 && i.tm.extension_opcode == None))
3897 {
3898 /* Optimize: -O2:
8305403a
L		 3899 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3900 vpsubq and vpsubw:
b6f8c7c4
L		 3901 EVEX VOP %zmmM, %zmmM, %zmmN
3902 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3903 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3904 EVEX VOP %ymmM, %ymmM, %ymmN
3905 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3906 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3907 VEX VOP %ymmM, %ymmM, %ymmN
3908 -> VEX VOP %xmmM, %xmmM, %xmmN
3909 VOP, one of vpandn and vpxor:
3910 VEX VOP %ymmM, %ymmM, %ymmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN
3912 VOP, one of vpandnd and vpandnq:
3913 EVEX VOP %zmmM, %zmmM, %zmmN
3914 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 EVEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3918 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3919 VOP, one of vpxord and vpxorq:
3920 EVEX VOP %zmmM, %zmmM, %zmmN
3921 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3922 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3923 EVEX VOP %ymmM, %ymmM, %ymmN
3924 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3925 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3926 */
e771e7c9 3927 if (is_evex_encoding (&i.tm))
b6f8c7c4 3928 {
0089dace 3929 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3930 i.tm.opcode_modifier.evex = EVEX128;
3931 else
3932 {
3933 i.tm.opcode_modifier.vex = VEX128;
3934 i.tm.opcode_modifier.vexw = VEXW0;
3935 i.tm.opcode_modifier.evex = 0;
3936 }
3937 }
3938 else
3939 i.tm.opcode_modifier.vex = VEX128;
3940
3941 if (i.tm.opcode_modifier.vex)
3942 for (j = 0; j < 3; j++)
3943 {
3944 i.types[j].bitfield.xmmword = 1;
3945 i.types[j].bitfield.ymmword = 0;
3946 }
3947 }
3948}
3949
252b5132
RH		 3950/* This is the guts of the machine-dependent assembler. LINE points to a
3951 machine dependent instruction. This function is supposed to emit
3952 the frags/bytes it assembles to. */
3953
3954void
65da13b5 3955md_assemble (char *line)
252b5132 3956{
40fb9820 3957 unsigned int j;
83b16ac6 3958 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3959 const insn_template *t;
252b5132 3960
47926f60 3961 /* Initialize globals. */
252b5132
RH		 3962 memset (&i, '\0', sizeof (i));
3963 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3964 i.reloc[j] = NO_RELOC;
252b5132
RH		 3965 memset (disp_expressions, '\0', sizeof (disp_expressions));
3966 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3967 save_stack_p = save_stack;
252b5132
RH		 3968
3969 /* First parse an instruction mnemonic & call i386_operand for the operands.
3970 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3971 start of a (possibly prefixed) mnemonic. */
252b5132 3972
29b0f896
AM		 3973 line = parse_insn (line, mnemonic);
3974 if (line == NULL)
3975 return;
83b16ac6 3976 mnem_suffix = i.suffix;
252b5132 3977
29b0f896 3978 line = parse_operands (line, mnemonic);
ee86248c 3979 this_operand = -1;
8325cc63
JB		 3980 xfree (i.memop1_string);
3981 i.memop1_string = NULL;
29b0f896
AM		 3982 if (line == NULL)
3983 return;
252b5132 3984
29b0f896
AM		 3985 /* Now we've parsed the mnemonic into a set of templates, and have the
3986 operands at hand. */
3987
3988 /* All intel opcodes have reversed operands except for "bound" and
3989 "enter". We also don't reverse intersegment "jmp" and "call"
3990 instructions with 2 immediate operands so that the immediate segment
050dfa73 3991 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3992 if (intel_syntax
3993 && i.operands > 1
29b0f896 3994 && (strcmp (mnemonic, "bound") != 0)
30123838 3995 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3996 && !(operand_type_check (i.types[0], imm)
3997 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3998 swap_operands ();
3999
ec56d5c0
JB		 4000 /* The order of the immediates should be reversed
4001 for 2 immediates extrq and insertq instructions */
4002 if (i.imm_operands == 2
4003 && (strcmp (mnemonic, "extrq") == 0
4004 || strcmp (mnemonic, "insertq") == 0))
4005 swap_2_operands (0, 1);
4006
29b0f896
AM		 4007 if (i.imm_operands)
4008 optimize_imm ();
4009
b300c311
L		 4010 /* Don't optimize displacement for movabs since it only takes 64bit
4011 displacement. */
4012 if (i.disp_operands
a501d77e 4013 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4014 && (flag_code != CODE_64BIT
4015 || strcmp (mnemonic, "movabs") != 0))
4016 optimize_disp ();
29b0f896
AM		 4017
4018 /* Next, we find a template that matches the given insn,
4019 making sure the overlap of the given operands types is consistent
4020 with the template operand types. */
252b5132 4021
83b16ac6 4022 if (!(t = match_template (mnem_suffix)))
29b0f896 4023 return;
252b5132 4024
7bab8ab5 4025 if (sse_check != check_none
81f8a913 4026 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4027 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4028 && (i.tm.cpu_flags.bitfield.cpusse
4029 || i.tm.cpu_flags.bitfield.cpusse2
4030 || i.tm.cpu_flags.bitfield.cpusse3
4031 || i.tm.cpu_flags.bitfield.cpussse3
4032 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4033 || i.tm.cpu_flags.bitfield.cpusse4_2
4034 || i.tm.cpu_flags.bitfield.cpupclmul
4035 || i.tm.cpu_flags.bitfield.cpuaes
4036 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4037 {
7bab8ab5 4038 (sse_check == check_warning
daf50ae7
L		 4039 ? as_warn
4040 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4041 }
4042
321fd21e
L		 4043 /* Zap movzx and movsx suffix. The suffix has been set from
4044 "word ptr" or "byte ptr" on the source operand in Intel syntax
4045 or extracted from mnemonic in AT&T syntax. But we'll use
4046 the destination register to choose the suffix for encoding. */
4047 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4048 {
321fd21e
L		 4049 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4050 there is no suffix, the default will be byte extension. */
4051 if (i.reg_operands != 2
4052 && !i.suffix
7ab9ffdd 4053 && intel_syntax)
321fd21e
L		 4054 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4055
4056 i.suffix = 0;
cd61ebfe 4057 }
24eab124 4058
40fb9820 4059 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4060 if (!add_prefix (FWAIT_OPCODE))
4061 return;
252b5132 4062
d5de92cf
L		 4063 /* Check if REP prefix is OK. */
4064 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4065 {
4066 as_bad (_("invalid instruction `%s' after `%s'"),
4067 i.tm.name, i.rep_prefix);
4068 return;
4069 }
4070
c1ba0266
L		 4071 /* Check for lock without a lockable instruction. Destination operand
4072 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4073 if (i.prefix[LOCK_PREFIX]
4074 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4075 || i.mem_operands == 0
4076 || (i.tm.base_opcode != 0x86
4077 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4078 {
4079 as_bad (_("expecting lockable instruction after `lock'"));
4080 return;
4081 }
4082
42164a71 4083 /* Check if HLE prefix is OK. */
165de32a 4084 if (i.hle_prefix && !check_hle ())
42164a71
L		 4085 return;
4086
7e8b059b
L		 4087 /* Check BND prefix. */
4088 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4089 as_bad (_("expecting valid branch instruction after `bnd'"));
4090
04ef582a 4091 /* Check NOTRACK prefix. */
9fef80d6
L		 4092 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4093 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4094
327e8c42
JB		 4095 if (i.tm.cpu_flags.bitfield.cpumpx)
4096 {
4097 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4098 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4099 else if (flag_code != CODE_16BIT
4100 ? i.prefix[ADDR_PREFIX]
4101 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4102 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4103 }
7e8b059b
L		 4104
4105 /* Insert BND prefix. */
4106 if (add_bnd_prefix
4107 && i.tm.opcode_modifier.bndprefixok
4108 && !i.prefix[BND_PREFIX])
4109 add_prefix (BND_PREFIX_OPCODE);
4110
29b0f896 4111 /* Check string instruction segment overrides. */
40fb9820 4112 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4113 {
4114 if (!check_string ())
5dd0794d 4115 return;
fc0763e6 4116 i.disp_operands = 0;
29b0f896 4117 }
5dd0794d 4118
b6f8c7c4
L		 4119 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4120 optimize_encoding ();
4121
29b0f896
AM		 4122 if (!process_suffix ())
4123 return;
e413e4e9 4124
bc0844ae
L		 4125 /* Update operand types. */
4126 for (j = 0; j < i.operands; j++)
4127 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4128
29b0f896
AM		 4129 /* Make still unresolved immediate matches conform to size of immediate
4130 given in i.suffix. */
4131 if (!finalize_imm ())
4132 return;
252b5132 4133
40fb9820 4134 if (i.types[0].bitfield.imm1)
29b0f896 4135 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4136
9afe6eb8
L		 4137 /* We only need to check those implicit registers for instructions
4138 with 3 operands or less. */
4139 if (i.operands <= 3)
4140 for (j = 0; j < i.operands; j++)
4141 if (i.types[j].bitfield.inoutportreg
4142 || i.types[j].bitfield.shiftcount
1b54b8d7 4143 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4144 i.reg_operands--;
40fb9820 4145
c0f3af97
L		 4146 /* ImmExt should be processed after SSE2AVX. */
4147 if (!i.tm.opcode_modifier.sse2avx
4148 && i.tm.opcode_modifier.immext)
65da13b5 4149 process_immext ();
252b5132 4150
29b0f896
AM		 4151 /* For insns with operands there are more diddles to do to the opcode. */
4152 if (i.operands)
4153 {
4154 if (!process_operands ())
4155 return;
4156 }
40fb9820 4157 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4158 {
4159 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4160 as_warn (_("translating to `%sp'"), i.tm.name);
4161 }
252b5132 4162
e771e7c9
JB		 4163 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4164 || is_evex_encoding (&i.tm))
9e5e5283
L		 4165 {
4166 if (flag_code == CODE_16BIT)
4167 {
4168 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4169 i.tm.name);
4170 return;
4171 }
c0f3af97 4172
9e5e5283
L		 4173 if (i.tm.opcode_modifier.vex)
4174 build_vex_prefix (t);
4175 else
4176 build_evex_prefix ();
4177 }
43234a1e 4178
5dd85c99
SP		 4179 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4180 instructions may define INT_OPCODE as well, so avoid this corner
4181 case for those instructions that use MODRM. */
4182 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4183 && !i.tm.opcode_modifier.modrm
4184 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4185 {
4186 i.tm.base_opcode = INT3_OPCODE;
4187 i.imm_operands = 0;
4188 }
252b5132 4189
40fb9820
L		 4190 if ((i.tm.opcode_modifier.jump
4191 || i.tm.opcode_modifier.jumpbyte
4192 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4193 && i.op[0].disps->X_op == O_constant)
4194 {
4195 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4196 the absolute address given by the constant. Since ix86 jumps and
4197 calls are pc relative, we need to generate a reloc. */
4198 i.op[0].disps->X_add_symbol = &abs_symbol;
4199 i.op[0].disps->X_op = O_symbol;
4200 }
252b5132 4201
40fb9820 4202 if (i.tm.opcode_modifier.rex64)
161a04f6 4203 i.rex |= REX_W;
252b5132 4204
29b0f896
AM		 4205 /* For 8 bit registers we need an empty rex prefix. Also if the
4206 instruction already has a prefix, we need to convert old
4207 registers to new ones. */
773f551c 4208
dc821c5f 4209 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4210 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4211 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4212 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4213 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4214 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4215 && i.rex != 0))
4216 {
4217 int x;
726c5dcd 4218
29b0f896
AM		 4219 i.rex |= REX_OPCODE;
4220 for (x = 0; x < 2; x++)
4221 {
4222 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4223 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4224 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4225 {
29b0f896
AM		 4226 /* In case it is "hi" register, give up. */
4227 if (i.op[x].regs->reg_num > 3)
a540244d 4228 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4229 "instruction requiring REX prefix."),
a540244d 4230 register_prefix, i.op[x].regs->reg_name);
773f551c 4231
29b0f896
AM		 4232 /* Otherwise it is equivalent to the extended register.
4233 Since the encoding doesn't change this is merely
4234 cosmetic cleanup for debug output. */
4235
4236 i.op[x].regs = i.op[x].regs + 8;
773f551c 4237 }
29b0f896
AM		 4238 }
4239 }
773f551c 4240
6b6b6807
L		 4241 if (i.rex == 0 && i.rex_encoding)
4242 {
4243 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4244 that uses legacy register. If it is "hi" register, don't add
4245 the REX_OPCODE byte. */
4246 int x;
4247 for (x = 0; x < 2; x++)
4248 if (i.types[x].bitfield.reg
4249 && i.types[x].bitfield.byte
4250 && (i.op[x].regs->reg_flags & RegRex64) == 0
4251 && i.op[x].regs->reg_num > 3)
4252 {
4253 i.rex_encoding = FALSE;
4254 break;
4255 }
4256
4257 if (i.rex_encoding)
4258 i.rex = REX_OPCODE;
4259 }
4260
7ab9ffdd 4261 if (i.rex != 0)
29b0f896
AM		 4262 add_prefix (REX_OPCODE | i.rex);
4263
4264 /* We are ready to output the insn. */
4265 output_insn ();
4266}
4267
4268static char *
e3bb37b5 4269parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4270{
4271 char *l = line;
4272 char *token_start = l;
4273 char *mnem_p;
5c6af06e 4274 int supported;
d3ce72d0 4275 const insn_template *t;
b6169b20 4276 char *dot_p = NULL;
29b0f896 4277
29b0f896
AM		 4278 while (1)
4279 {
4280 mnem_p = mnemonic;
4281 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4282 {
b6169b20
L		 4283 if (*mnem_p == '.')
4284 dot_p = mnem_p;
29b0f896
AM		 4285 mnem_p++;
4286 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4287 {
29b0f896
AM		 4288 as_bad (_("no such instruction: `%s'"), token_start);
4289 return NULL;
4290 }
4291 l++;
4292 }
4293 if (!is_space_char (*l)
4294 && *l != END_OF_INSN
e44823cf
JB		 4295 && (intel_syntax
4296 || (*l != PREFIX_SEPARATOR
4297 && *l != ',')))
29b0f896
AM		 4298 {
4299 as_bad (_("invalid character %s in mnemonic"),
4300 output_invalid (*l));
4301 return NULL;
4302 }
4303 if (token_start == l)
4304 {
e44823cf 4305 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4306 as_bad (_("expecting prefix; got nothing"));
4307 else
4308 as_bad (_("expecting mnemonic; got nothing"));
4309 return NULL;
4310 }
45288df1 4311
29b0f896 4312 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4313 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4314
29b0f896
AM		 4315 if (*l != END_OF_INSN
4316 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4317 && current_templates
40fb9820 4318 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4319 {
c6fb90c8 4320 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4321 {
4322 as_bad ((flag_code != CODE_64BIT
4323 ? _("`%s' is only supported in 64-bit mode")
4324 : _("`%s' is not supported in 64-bit mode")),
4325 current_templates->start->name);
4326 return NULL;
4327 }
29b0f896
AM		 4328 /* If we are in 16-bit mode, do not allow addr16 or data16.
4329 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4330 if ((current_templates->start->opcode_modifier.size16
4331 || current_templates->start->opcode_modifier.size32)
29b0f896 4332 && flag_code != CODE_64BIT
40fb9820 4333 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4334 ^ (flag_code == CODE_16BIT)))
4335 {
4336 as_bad (_("redundant %s prefix"),
4337 current_templates->start->name);
4338 return NULL;
45288df1 4339 }
86fa6981 4340 if (current_templates->start->opcode_length == 0)
29b0f896 4341 {
86fa6981
L		 4342 /* Handle pseudo prefixes. */
4343 switch (current_templates->start->base_opcode)
4344 {
4345 case 0x0:
4346 /* {disp8} */
4347 i.disp_encoding = disp_encoding_8bit;
4348 break;
4349 case 0x1:
4350 /* {disp32} */
4351 i.disp_encoding = disp_encoding_32bit;
4352 break;
4353 case 0x2:
4354 /* {load} */
4355 i.dir_encoding = dir_encoding_load;
4356 break;
4357 case 0x3:
4358 /* {store} */
4359 i.dir_encoding = dir_encoding_store;
4360 break;
4361 case 0x4:
4362 /* {vex2} */
4363 i.vec_encoding = vex_encoding_vex2;
4364 break;
4365 case 0x5:
4366 /* {vex3} */
4367 i.vec_encoding = vex_encoding_vex3;
4368 break;
4369 case 0x6:
4370 /* {evex} */
4371 i.vec_encoding = vex_encoding_evex;
4372 break;
6b6b6807
L		 4373 case 0x7:
4374 /* {rex} */
4375 i.rex_encoding = TRUE;
4376 break;
b6f8c7c4
L		 4377 case 0x8:
4378 /* {nooptimize} */
4379 i.no_optimize = TRUE;
4380 break;
86fa6981
L		 4381 default:
4382 abort ();
4383 }
4384 }
4385 else
4386 {
4387 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4388 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4389 {
4e9ac44a
L		 4390 case PREFIX_EXIST:
4391 return NULL;
4392 case PREFIX_DS:
d777820b 4393 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4394 i.notrack_prefix = current_templates->start->name;
4395 break;
4396 case PREFIX_REP:
4397 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4398 i.hle_prefix = current_templates->start->name;
4399 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4400 i.bnd_prefix = current_templates->start->name;
4401 else
4402 i.rep_prefix = current_templates->start->name;
4403 break;
4404 default:
4405 break;
86fa6981 4406 }
29b0f896
AM		 4407 }
4408 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4409 token_start = ++l;
4410 }
4411 else
4412 break;
4413 }
45288df1 4414
30a55f88 4415 if (!current_templates)
b6169b20 4416 {
f8a5c266
L		 4417 /* Check if we should swap operand or force 32bit displacement in
4418 encoding. */
30a55f88 4419 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4420 i.dir_encoding = dir_encoding_store;
8d63c93e 4421 else if (mnem_p - 3 == dot_p
a501d77e
L		 4422 && dot_p[1] == 'd'
4423 && dot_p[2] == '8')
4424 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4425 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4426 && dot_p[1] == 'd'
4427 && dot_p[2] == '3'
4428 && dot_p[3] == '2')
a501d77e 4429 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4430 else
4431 goto check_suffix;
4432 mnem_p = dot_p;
4433 *dot_p = '\0';
d3ce72d0 4434 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4435 }
4436
29b0f896
AM		 4437 if (!current_templates)
4438 {
b6169b20 4439check_suffix:
29b0f896
AM		 4440 /* See if we can get a match by trimming off a suffix. */
4441 switch (mnem_p[-1])
4442 {
4443 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4444 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4445 i.suffix = SHORT_MNEM_SUFFIX;
4446 else
1a0670f3 4447 /* Fall through. */
29b0f896
AM		 4448 case BYTE_MNEM_SUFFIX:
4449 case QWORD_MNEM_SUFFIX:
4450 i.suffix = mnem_p[-1];
4451 mnem_p[-1] = '\0';
d3ce72d0
NC		 4452 current_templates = (const templates *) hash_find (op_hash,
4453 mnemonic);
29b0f896
AM		 4454 break;
4455 case SHORT_MNEM_SUFFIX:
4456 case LONG_MNEM_SUFFIX:
4457 if (!intel_syntax)
4458 {
4459 i.suffix = mnem_p[-1];
4460 mnem_p[-1] = '\0';
d3ce72d0
NC		 4461 current_templates = (const templates *) hash_find (op_hash,
4462 mnemonic);
29b0f896
AM		 4463 }
4464 break;
252b5132 4465
29b0f896
AM		 4466 /* Intel Syntax. */
4467 case 'd':
4468 if (intel_syntax)
4469 {
9306ca4a 4470 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4471 i.suffix = SHORT_MNEM_SUFFIX;
4472 else
4473 i.suffix = LONG_MNEM_SUFFIX;
4474 mnem_p[-1] = '\0';
d3ce72d0
NC		 4475 current_templates = (const templates *) hash_find (op_hash,
4476 mnemonic);
29b0f896
AM		 4477 }
4478 break;
4479 }
4480 if (!current_templates)
4481 {
4482 as_bad (_("no such instruction: `%s'"), token_start);
4483 return NULL;
4484 }
4485 }
252b5132 4486
40fb9820
L		 4487 if (current_templates->start->opcode_modifier.jump
4488 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4489 {
4490 /* Check for a branch hint. We allow ",pt" and ",pn" for
4491 predict taken and predict not taken respectively.
4492 I'm not sure that branch hints actually do anything on loop
4493 and jcxz insns (JumpByte) for current Pentium4 chips. They
4494 may work in the future and it doesn't hurt to accept them
4495 now. */
4496 if (l[0] == ',' && l[1] == 'p')
4497 {
4498 if (l[2] == 't')
4499 {
4500 if (!add_prefix (DS_PREFIX_OPCODE))
4501 return NULL;
4502 l += 3;
4503 }
4504 else if (l[2] == 'n')
4505 {
4506 if (!add_prefix (CS_PREFIX_OPCODE))
4507 return NULL;
4508 l += 3;
4509 }
4510 }
4511 }
4512 /* Any other comma loses. */
4513 if (*l == ',')
4514 {
4515 as_bad (_("invalid character %s in mnemonic"),
4516 output_invalid (*l));
4517 return NULL;
4518 }
252b5132 4519
29b0f896 4520 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4521 supported = 0;
4522 for (t = current_templates->start; t < current_templates->end; ++t)
4523 {
c0f3af97
L		 4524 supported |= cpu_flags_match (t);
4525 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4526 {
4527 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4528 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4529
548d0ee6
JB		 4530 return l;
4531 }
29b0f896 4532 }
3629bb00 4533
548d0ee6
JB		 4534 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4535 as_bad (flag_code == CODE_64BIT
4536 ? _("`%s' is not supported in 64-bit mode")
4537 : _("`%s' is only supported in 64-bit mode"),
4538 current_templates->start->name);
4539 else
4540 as_bad (_("`%s' is not supported on `%s%s'"),
4541 current_templates->start->name,
4542 cpu_arch_name ? cpu_arch_name : default_arch,
4543 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4544
548d0ee6 4545 return NULL;
29b0f896 4546}
252b5132 4547
29b0f896 4548static char *
e3bb37b5 4549parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4550{
4551 char *token_start;
3138f287 4552
29b0f896
AM		 4553 /* 1 if operand is pending after ','. */
4554 unsigned int expecting_operand = 0;
252b5132 4555
29b0f896
AM		 4556 /* Non-zero if operand parens not balanced. */
4557 unsigned int paren_not_balanced;
4558
4559 while (*l != END_OF_INSN)
4560 {
4561 /* Skip optional white space before operand. */
4562 if (is_space_char (*l))
4563 ++l;
d02603dc 4564 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4565 {
4566 as_bad (_("invalid character %s before operand %d"),
4567 output_invalid (*l),
4568 i.operands + 1);
4569 return NULL;
4570 }
d02603dc 4571 token_start = l; /* After white space. */
29b0f896
AM		 4572 paren_not_balanced = 0;
4573 while (paren_not_balanced || *l != ',')
4574 {
4575 if (*l == END_OF_INSN)
4576 {
4577 if (paren_not_balanced)
4578 {
4579 if (!intel_syntax)
4580 as_bad (_("unbalanced parenthesis in operand %d."),
4581 i.operands + 1);
4582 else
4583 as_bad (_("unbalanced brackets in operand %d."),
4584 i.operands + 1);
4585 return NULL;
4586 }
4587 else
4588 break; /* we are done */
4589 }
d02603dc 4590 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4591 {
4592 as_bad (_("invalid character %s in operand %d"),
4593 output_invalid (*l),
4594 i.operands + 1);
4595 return NULL;
4596 }
4597 if (!intel_syntax)
4598 {
4599 if (*l == '(')
4600 ++paren_not_balanced;
4601 if (*l == ')')
4602 --paren_not_balanced;
4603 }
4604 else
4605 {
4606 if (*l == '[')
4607 ++paren_not_balanced;
4608 if (*l == ']')
4609 --paren_not_balanced;
4610 }
4611 l++;
4612 }
4613 if (l != token_start)
4614 { /* Yes, we've read in another operand. */
4615 unsigned int operand_ok;
4616 this_operand = i.operands++;
4617 if (i.operands > MAX_OPERANDS)
4618 {
4619 as_bad (_("spurious operands; (%d operands/instruction max)"),
4620 MAX_OPERANDS);
4621 return NULL;
4622 }
9d46ce34 4623 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4624 /* Now parse operand adding info to 'i' as we go along. */
4625 END_STRING_AND_SAVE (l);
4626
4627 if (intel_syntax)
4628 operand_ok =
4629 i386_intel_operand (token_start,
4630 intel_float_operand (mnemonic));
4631 else
a7619375 4632 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4633
4634 RESTORE_END_STRING (l);
4635 if (!operand_ok)
4636 return NULL;
4637 }
4638 else
4639 {
4640 if (expecting_operand)
4641 {
4642 expecting_operand_after_comma:
4643 as_bad (_("expecting operand after ','; got nothing"));
4644 return NULL;
4645 }
4646 if (*l == ',')
4647 {
4648 as_bad (_("expecting operand before ','; got nothing"));
4649 return NULL;
4650 }
4651 }
7f3f1ea2 4652
29b0f896
AM		 4653 /* Now *l must be either ',' or END_OF_INSN. */
4654 if (*l == ',')
4655 {
4656 if (*++l == END_OF_INSN)
4657 {
4658 /* Just skip it, if it's \n complain. */
4659 goto expecting_operand_after_comma;
4660 }
4661 expecting_operand = 1;
4662 }
4663 }
4664 return l;
4665}
7f3f1ea2 4666
050dfa73 4667static void
4d456e3d 4668swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4669{
4670 union i386_op temp_op;
40fb9820 4671 i386_operand_type temp_type;
050dfa73 4672 enum bfd_reloc_code_real temp_reloc;
4eed87de 4673
050dfa73
MM		 4674 temp_type = i.types[xchg2];
4675 i.types[xchg2] = i.types[xchg1];
4676 i.types[xchg1] = temp_type;
4677 temp_op = i.op[xchg2];
4678 i.op[xchg2] = i.op[xchg1];
4679 i.op[xchg1] = temp_op;
4680 temp_reloc = i.reloc[xchg2];
4681 i.reloc[xchg2] = i.reloc[xchg1];
4682 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4683
4684 if (i.mask)
4685 {
4686 if (i.mask->operand == xchg1)
4687 i.mask->operand = xchg2;
4688 else if (i.mask->operand == xchg2)
4689 i.mask->operand = xchg1;
4690 }
4691 if (i.broadcast)
4692 {
4693 if (i.broadcast->operand == xchg1)
4694 i.broadcast->operand = xchg2;
4695 else if (i.broadcast->operand == xchg2)
4696 i.broadcast->operand = xchg1;
4697 }
4698 if (i.rounding)
4699 {
4700 if (i.rounding->operand == xchg1)
4701 i.rounding->operand = xchg2;
4702 else if (i.rounding->operand == xchg2)
4703 i.rounding->operand = xchg1;
4704 }
050dfa73
MM		 4705}
4706
29b0f896 4707static void
e3bb37b5 4708swap_operands (void)
29b0f896 4709{
b7c61d9a 4710 switch (i.operands)
050dfa73 4711 {
c0f3af97 4712 case 5:
b7c61d9a 4713 case 4:
4d456e3d 4714 swap_2_operands (1, i.operands - 2);
1a0670f3 4715 /* Fall through. */
b7c61d9a
L		 4716 case 3:
4717 case 2:
4d456e3d 4718 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4719 break;
4720 default:
4721 abort ();
29b0f896 4722 }
29b0f896
AM		 4723
4724 if (i.mem_operands == 2)
4725 {
4726 const seg_entry *temp_seg;
4727 temp_seg = i.seg[0];
4728 i.seg[0] = i.seg[1];
4729 i.seg[1] = temp_seg;
4730 }
4731}
252b5132 4732
29b0f896
AM		 4733/* Try to ensure constant immediates are represented in the smallest
4734 opcode possible. */
4735static void
e3bb37b5 4736optimize_imm (void)
29b0f896
AM		 4737{
4738 char guess_suffix = 0;
4739 int op;
252b5132 4740
29b0f896
AM		 4741 if (i.suffix)
4742 guess_suffix = i.suffix;
4743 else if (i.reg_operands)
4744 {
4745 /* Figure out a suffix from the last register operand specified.
4746 We can't do this properly yet, ie. excluding InOutPortReg,
4747 but the following works for instructions with immediates.
4748 In any case, we can't set i.suffix yet. */
4749 for (op = i.operands; --op >= 0;)
dc821c5f 4750 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4751 {
40fb9820
L		 4752 guess_suffix = BYTE_MNEM_SUFFIX;
4753 break;
4754 }
dc821c5f 4755 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4756 {
40fb9820
L		 4757 guess_suffix = WORD_MNEM_SUFFIX;
4758 break;
4759 }
dc821c5f 4760 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4761 {
4762 guess_suffix = LONG_MNEM_SUFFIX;
4763 break;
4764 }
dc821c5f 4765 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4766 {
4767 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4768 break;
252b5132 4769 }
29b0f896
AM		 4770 }
4771 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4772 guess_suffix = WORD_MNEM_SUFFIX;
4773
4774 for (op = i.operands; --op >= 0;)
40fb9820 4775 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4776 {
4777 switch (i.op[op].imms->X_op)
252b5132 4778 {
29b0f896
AM		 4779 case O_constant:
4780 /* If a suffix is given, this operand may be shortened. */
4781 switch (guess_suffix)
252b5132 4782 {
29b0f896 4783 case LONG_MNEM_SUFFIX:
40fb9820
L		 4784 i.types[op].bitfield.imm32 = 1;
4785 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4786 break;
4787 case WORD_MNEM_SUFFIX:
40fb9820
L		 4788 i.types[op].bitfield.imm16 = 1;
4789 i.types[op].bitfield.imm32 = 1;
4790 i.types[op].bitfield.imm32s = 1;
4791 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4792 break;
4793 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4794 i.types[op].bitfield.imm8 = 1;
4795 i.types[op].bitfield.imm8s = 1;
4796 i.types[op].bitfield.imm16 = 1;
4797 i.types[op].bitfield.imm32 = 1;
4798 i.types[op].bitfield.imm32s = 1;
4799 i.types[op].bitfield.imm64 = 1;
29b0f896 4800 break;
252b5132 4801 }
252b5132 4802
29b0f896
AM		 4803 /* If this operand is at most 16 bits, convert it
4804 to a signed 16 bit number before trying to see
4805 whether it will fit in an even smaller size.
4806 This allows a 16-bit operand such as $0xffe0 to
4807 be recognised as within Imm8S range. */
40fb9820 4808 if ((i.types[op].bitfield.imm16)
29b0f896 4809 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4810 {
29b0f896
AM		 4811 i.op[op].imms->X_add_number =
4812 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4813 }
a28def75
L		 4814#ifdef BFD64
4815 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4816 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4817 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4818 == 0))
4819 {
4820 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4821 ^ ((offsetT) 1 << 31))
4822 - ((offsetT) 1 << 31));
4823 }
a28def75 4824#endif
40fb9820 4825 i.types[op]
c6fb90c8
L		 4826 = operand_type_or (i.types[op],
4827 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4828
29b0f896
AM		 4829 /* We must avoid matching of Imm32 templates when 64bit
4830 only immediate is available. */
4831 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4832 i.types[op].bitfield.imm32 = 0;
29b0f896 4833 break;
252b5132 4834
29b0f896
AM		 4835 case O_absent:
4836 case O_register:
4837 abort ();
4838
4839 /* Symbols and expressions. */
4840 default:
9cd96992
JB		 4841 /* Convert symbolic operand to proper sizes for matching, but don't
4842 prevent matching a set of insns that only supports sizes other
4843 than those matching the insn suffix. */
4844 {
40fb9820 4845 i386_operand_type mask, allowed;
d3ce72d0 4846 const insn_template *t;
9cd96992 4847
0dfbf9d7
L		 4848 operand_type_set (&mask, 0);
4849 operand_type_set (&allowed, 0);
40fb9820 4850
4eed87de
AM		 4851 for (t = current_templates->start;
4852 t < current_templates->end;
4853 ++t)
c6fb90c8
L		 4854 allowed = operand_type_or (allowed,
4855 t->operand_types[op]);
9cd96992
JB		 4856 switch (guess_suffix)
4857 {
4858 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4859 mask.bitfield.imm64 = 1;
4860 mask.bitfield.imm32s = 1;
9cd96992
JB		 4861 break;
4862 case LONG_MNEM_SUFFIX:
40fb9820 4863 mask.bitfield.imm32 = 1;
9cd96992
JB		 4864 break;
4865 case WORD_MNEM_SUFFIX:
40fb9820 4866 mask.bitfield.imm16 = 1;
9cd96992
JB		 4867 break;
4868 case BYTE_MNEM_SUFFIX:
40fb9820 4869 mask.bitfield.imm8 = 1;
9cd96992
JB		 4870 break;
4871 default:
9cd96992
JB		 4872 break;
4873 }
c6fb90c8 4874 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4875 if (!operand_type_all_zero (&allowed))
c6fb90c8 4876 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4877 }
29b0f896 4878 break;
252b5132 4879 }
29b0f896
AM		 4880 }
4881}
47926f60 4882
29b0f896
AM		 4883/* Try to use the smallest displacement type too. */
4884static void
e3bb37b5 4885optimize_disp (void)
29b0f896
AM		 4886{
4887 int op;
3e73aa7c 4888
29b0f896 4889 for (op = i.operands; --op >= 0;)
40fb9820 4890 if (operand_type_check (i.types[op], disp))
252b5132 4891 {
b300c311 4892 if (i.op[op].disps->X_op == O_constant)
252b5132 4893 {
91d6fa6a 4894 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4895
40fb9820 4896 if (i.types[op].bitfield.disp16
91d6fa6a 4897 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4898 {
4899 /* If this operand is at most 16 bits, convert
4900 to a signed 16 bit number and don't use 64bit
4901 displacement. */
91d6fa6a 4902 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4903 i.types[op].bitfield.disp64 = 0;
b300c311 4904 }
a28def75
L		 4905#ifdef BFD64
4906 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4907 if (i.types[op].bitfield.disp32
91d6fa6a 4908 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4909 {
4910 /* If this operand is at most 32 bits, convert
4911 to a signed 32 bit number and don't use 64bit
4912 displacement. */
91d6fa6a
NC		 4913 op_disp &= (((offsetT) 2 << 31) - 1);
4914 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4915 i.types[op].bitfield.disp64 = 0;
b300c311 4916 }
a28def75 4917#endif
91d6fa6a 4918 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4919 {
40fb9820
L		 4920 i.types[op].bitfield.disp8 = 0;
4921 i.types[op].bitfield.disp16 = 0;
4922 i.types[op].bitfield.disp32 = 0;
4923 i.types[op].bitfield.disp32s = 0;
4924 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4925 i.op[op].disps = 0;
4926 i.disp_operands--;
4927 }
4928 else if (flag_code == CODE_64BIT)
4929 {
91d6fa6a 4930 if (fits_in_signed_long (op_disp))
28a9d8f5 4931 {
40fb9820
L		 4932 i.types[op].bitfield.disp64 = 0;
4933 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4934 }
0e1147d9 4935 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4936 && fits_in_unsigned_long (op_disp))
40fb9820 4937 i.types[op].bitfield.disp32 = 1;
b300c311 4938 }
40fb9820
L		 4939 if ((i.types[op].bitfield.disp32
4940 || i.types[op].bitfield.disp32s
4941 || i.types[op].bitfield.disp16)
b5014f7a 4942 && fits_in_disp8 (op_disp))
40fb9820 4943 i.types[op].bitfield.disp8 = 1;
252b5132 4944 }
67a4f2b7
AO		 4945 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4946 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4947 {
4948 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4949 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4950 i.types[op].bitfield.disp8 = 0;
4951 i.types[op].bitfield.disp16 = 0;
4952 i.types[op].bitfield.disp32 = 0;
4953 i.types[op].bitfield.disp32s = 0;
4954 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4955 }
4956 else
b300c311 4957 /* We only support 64bit displacement on constants. */
40fb9820 4958 i.types[op].bitfield.disp64 = 0;
252b5132 4959 }
29b0f896
AM		 4960}
4961
6c30d220
L		 4962/* Check if operands are valid for the instruction. */
4963
4964static int
4965check_VecOperands (const insn_template *t)
4966{
43234a1e
L		 4967 unsigned int op;
4968
6c30d220
L		 4969 /* Without VSIB byte, we can't have a vector register for index. */
4970 if (!t->opcode_modifier.vecsib
4971 && i.index_reg
1b54b8d7
JB		 4972 && (i.index_reg->reg_type.bitfield.xmmword
4973 || i.index_reg->reg_type.bitfield.ymmword
4974 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4975 {
4976 i.error = unsupported_vector_index_register;
4977 return 1;
4978 }
4979
ad8ecc81
MZ		 4980 /* Check if default mask is allowed. */
4981 if (t->opcode_modifier.nodefmask
4982 && (!i.mask || i.mask->mask->reg_num == 0))
4983 {
4984 i.error = no_default_mask;
4985 return 1;
4986 }
4987
7bab8ab5
JB		 4988 /* For VSIB byte, we need a vector register for index, and all vector
4989 registers must be distinct. */
4990 if (t->opcode_modifier.vecsib)
4991 {
4992 if (!i.index_reg
6c30d220 4993 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4994 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4995 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4996 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4997 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4998 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4999 {
5000 i.error = invalid_vsib_address;
5001 return 1;
5002 }
5003
43234a1e
L		 5004 gas_assert (i.reg_operands == 2 || i.mask);
5005 if (i.reg_operands == 2 && !i.mask)
5006 {
1b54b8d7
JB		 5007 gas_assert (i.types[0].bitfield.regsimd);
5008 gas_assert (i.types[0].bitfield.xmmword
5009 || i.types[0].bitfield.ymmword);
5010 gas_assert (i.types[2].bitfield.regsimd);
5011 gas_assert (i.types[2].bitfield.xmmword
5012 || i.types[2].bitfield.ymmword);
43234a1e
L		 5013 if (operand_check == check_none)
5014 return 0;
5015 if (register_number (i.op[0].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[2].regs)
5018 != register_number (i.index_reg)
5019 && register_number (i.op[0].regs)
5020 != register_number (i.op[2].regs))
5021 return 0;
5022 if (operand_check == check_error)
5023 {
5024 i.error = invalid_vector_register_set;
5025 return 1;
5026 }
5027 as_warn (_("mask, index, and destination registers should be distinct"));
5028 }
8444f82a
MZ		 5029 else if (i.reg_operands == 1 && i.mask)
5030 {
1b54b8d7
JB		 5031 if (i.types[1].bitfield.regsimd
5032 && (i.types[1].bitfield.xmmword
5033 || i.types[1].bitfield.ymmword
5034 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5035 && (register_number (i.op[1].regs)
5036 == register_number (i.index_reg)))
5037 {
5038 if (operand_check == check_error)
5039 {
5040 i.error = invalid_vector_register_set;
5041 return 1;
5042 }
5043 if (operand_check != check_none)
5044 as_warn (_("index and destination registers should be distinct"));
5045 }
5046 }
43234a1e 5047 }
7bab8ab5 5048
43234a1e
L		 5049 /* Check if broadcast is supported by the instruction and is applied
5050 to the memory operand. */
5051 if (i.broadcast)
5052 {
8e6e0792 5053 i386_operand_type type, overlap;
43234a1e
L		 5054
5055 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5056 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5057 op = i.broadcast->operand;
8e6e0792 5058 if (!t->opcode_modifier.broadcast
32546502 5059 || !i.types[op].bitfield.mem
c39e5b26
JB		 5060 || (!i.types[op].bitfield.unspecified
5061 && (t->operand_types[op].bitfield.dword
5062 ? !i.types[op].bitfield.dword
5063 : !i.types[op].bitfield.qword)))
43234a1e
L		 5064 {
5065 bad_broadcast:
5066 i.error = unsupported_broadcast;
5067 return 1;
5068 }
8e6e0792
JB		 5069
5070 operand_type_set (&type, 0);
c39e5b26 5071 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5072 {
5073 case 8:
5074 type.bitfield.qword = 1;
5075 break;
5076 case 16:
5077 type.bitfield.xmmword = 1;
5078 break;
5079 case 32:
5080 type.bitfield.ymmword = 1;
5081 break;
5082 case 64:
5083 type.bitfield.zmmword = 1;
5084 break;
5085 default:
5086 goto bad_broadcast;
5087 }
5088
5089 overlap = operand_type_and (type, t->operand_types[op]);
5090 if (operand_type_all_zero (&overlap))
5091 goto bad_broadcast;
5092
5093 if (t->opcode_modifier.checkregsize)
5094 {
5095 unsigned int j;
5096
5097 for (j = 0; j < i.operands; ++j)
5098 {
5099 if (j != op
5100 && !operand_type_register_match(i.types[j],
5101 t->operand_types[j],
5102 type,
5103 t->operand_types[op]))
5104 goto bad_broadcast;
5105 }
5106 }
43234a1e
L		 5107 }
5108 /* If broadcast is supported in this instruction, we need to check if
5109 operand of one-element size isn't specified without broadcast. */
5110 else if (t->opcode_modifier.broadcast && i.mem_operands)
5111 {
5112 /* Find memory operand. */
5113 for (op = 0; op < i.operands; op++)
5114 if (operand_type_check (i.types[op], anymem))
5115 break;
5116 gas_assert (op < i.operands);
5117 /* Check size of the memory operand. */
c39e5b26
JB		 5118 if (t->operand_types[op].bitfield.dword
5119 ? i.types[op].bitfield.dword
5120 : i.types[op].bitfield.qword)
43234a1e
L		 5121 {
5122 i.error = broadcast_needed;
5123 return 1;
5124 }
5125 }
c39e5b26
JB		 5126 else
5127 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5128
5129 /* Check if requested masking is supported. */
5130 if (i.mask
5131 && (!t->opcode_modifier.masking
5132 || (i.mask->zeroing
5133 && t->opcode_modifier.masking == MERGING_MASKING)))
5134 {
5135 i.error = unsupported_masking;
5136 return 1;
5137 }
5138
5139 /* Check if masking is applied to dest operand. */
5140 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5141 {
5142 i.error = mask_not_on_destination;
5143 return 1;
5144 }
5145
43234a1e
L		 5146 /* Check RC/SAE. */
5147 if (i.rounding)
5148 {
5149 if ((i.rounding->type != saeonly
5150 && !t->opcode_modifier.staticrounding)
5151 || (i.rounding->type == saeonly
5152 && (t->opcode_modifier.staticrounding
5153 || !t->opcode_modifier.sae)))
5154 {
5155 i.error = unsupported_rc_sae;
5156 return 1;
5157 }
5158 /* If the instruction has several immediate operands and one of
5159 them is rounding, the rounding operand should be the last
5160 immediate operand. */
5161 if (i.imm_operands > 1
5162 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5163 {
43234a1e 5164 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5165 return 1;
5166 }
6c30d220
L		 5167 }
5168
43234a1e 5169 /* Check vector Disp8 operand. */
b5014f7a
JB		 5170 if (t->opcode_modifier.disp8memshift
5171 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5172 {
5173 if (i.broadcast)
c39e5b26 5174 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
43234a1e
L		 5175 else
5176 i.memshift = t->opcode_modifier.disp8memshift;
5177
5178 for (op = 0; op < i.operands; op++)
5179 if (operand_type_check (i.types[op], disp)
5180 && i.op[op].disps->X_op == O_constant)
5181 {
b5014f7a 5182 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5183 {
b5014f7a
JB		 5184 i.types[op].bitfield.disp8 = 1;
5185 return 0;
43234a1e 5186 }
b5014f7a 5187 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5188 }
5189 }
b5014f7a
JB		 5190
5191 i.memshift = 0;
43234a1e 5192
6c30d220
L		 5193 return 0;
5194}
5195
43f3e2ee 5196/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5197 operand types. */
5198
5199static int
5200VEX_check_operands (const insn_template *t)
5201{
86fa6981 5202 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5203 {
86fa6981 5204 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5205 if (!is_evex_encoding (t))
86fa6981
L		 5206 {
5207 i.error = unsupported;
5208 return 1;
5209 }
5210 return 0;
43234a1e
L		 5211 }
5212
a683cc34 5213 if (!t->opcode_modifier.vex)
86fa6981
L		 5214 {
5215 /* This instruction template doesn't have VEX prefix. */
5216 if (i.vec_encoding != vex_encoding_default)
5217 {
5218 i.error = unsupported;
5219 return 1;
5220 }
5221 return 0;
5222 }
a683cc34
SP		 5223
5224 /* Only check VEX_Imm4, which must be the first operand. */
5225 if (t->operand_types[0].bitfield.vec_imm4)
5226 {
5227 if (i.op[0].imms->X_op != O_constant
5228 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5229 {
a65babc9 5230 i.error = bad_imm4;
891edac4
L		 5231 return 1;
5232 }
a683cc34
SP		 5233
5234 /* Turn off Imm8 so that update_imm won't complain. */
5235 i.types[0] = vec_imm4;
5236 }
5237
5238 return 0;
5239}
5240
d3ce72d0 5241static const insn_template *
83b16ac6 5242match_template (char mnem_suffix)
29b0f896
AM		 5243{
5244 /* Points to template once we've found it. */
d3ce72d0 5245 const insn_template *t;
40fb9820 5246 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5247 i386_operand_type overlap4;
29b0f896 5248 unsigned int found_reverse_match;
83b16ac6 5249 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5250 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5251 int addr_prefix_disp;
a5c311ca 5252 unsigned int j;
3629bb00 5253 unsigned int found_cpu_match;
45664ddb 5254 unsigned int check_register;
5614d22c 5255 enum i386_error specific_error = 0;
29b0f896 5256
c0f3af97
L		 5257#if MAX_OPERANDS != 5
5258# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5259#endif
5260
29b0f896 5261 found_reverse_match = 0;
539e75ad 5262 addr_prefix_disp = -1;
40fb9820
L		 5263
5264 memset (&suffix_check, 0, sizeof (suffix_check));
5265 if (i.suffix == BYTE_MNEM_SUFFIX)
5266 suffix_check.no_bsuf = 1;
5267 else if (i.suffix == WORD_MNEM_SUFFIX)
5268 suffix_check.no_wsuf = 1;
5269 else if (i.suffix == SHORT_MNEM_SUFFIX)
5270 suffix_check.no_ssuf = 1;
5271 else if (i.suffix == LONG_MNEM_SUFFIX)
5272 suffix_check.no_lsuf = 1;
5273 else if (i.suffix == QWORD_MNEM_SUFFIX)
5274 suffix_check.no_qsuf = 1;
5275 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5276 suffix_check.no_ldsuf = 1;
29b0f896 5277
83b16ac6
JB		 5278 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5279 if (intel_syntax)
5280 {
5281 switch (mnem_suffix)
5282 {
5283 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5284 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5285 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5286 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5287 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5288 }
5289 }
5290
01559ecc
L		 5291 /* Must have right number of operands. */
5292 i.error = number_of_operands_mismatch;
5293
45aa61fe 5294 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5295 {
539e75ad
L		 5296 addr_prefix_disp = -1;
5297
29b0f896
AM		 5298 if (i.operands != t->operands)
5299 continue;
5300
50aecf8c 5301 /* Check processor support. */
a65babc9 5302 i.error = unsupported;
c0f3af97
L		 5303 found_cpu_match = (cpu_flags_match (t)
5304 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5305 if (!found_cpu_match)
5306 continue;
5307
e1d4d893 5308 /* Check AT&T mnemonic. */
a65babc9 5309 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5310 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5311 continue;
5312
e92bae62 5313 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5314 i.error = unsupported_syntax;
5c07affc 5315 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5316 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5317 || (intel64 && t->opcode_modifier.amd64)
5318 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5319 continue;
5320
20592a94 5321 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5322 i.error = invalid_instruction_suffix;
567e4e96
L		 5323 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5324 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5325 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5326 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5327 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5328 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5329 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5330 continue;
83b16ac6
JB		 5331 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5332 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5333 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5334 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5335 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5336 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5337 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5338 continue;
29b0f896 5339
5c07affc 5340 if (!operand_size_match (t))
7d5e4556 5341 continue;
539e75ad 5342
5c07affc
L		 5343 for (j = 0; j < MAX_OPERANDS; j++)
5344 operand_types[j] = t->operand_types[j];
5345
45aa61fe
AM		 5346 /* In general, don't allow 64-bit operands in 32-bit mode. */
5347 if (i.suffix == QWORD_MNEM_SUFFIX
5348 && flag_code != CODE_64BIT
5349 && (intel_syntax
40fb9820 5350 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5351 && !intel_float_operand (t->name))
5352 : intel_float_operand (t->name) != 2)
40fb9820 5353 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5354 && !operand_types[0].bitfield.regsimd)
40fb9820 5355 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5356 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5357 && (t->base_opcode != 0x0fc7
5358 || t->extension_opcode != 1 /* cmpxchg8b */))
5359 continue;
5360
192dc9c6
JB		 5361 /* In general, don't allow 32-bit operands on pre-386. */
5362 else if (i.suffix == LONG_MNEM_SUFFIX
5363 && !cpu_arch_flags.bitfield.cpui386
5364 && (intel_syntax
5365 ? (!t->opcode_modifier.ignoresize
5366 && !intel_float_operand (t->name))
5367 : intel_float_operand (t->name) != 2)
5368 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5369 && !operand_types[0].bitfield.regsimd)
192dc9c6 5370 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5371 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5372 continue;
5373
29b0f896 5374 /* Do not verify operands when there are none. */
50aecf8c 5375 else
29b0f896 5376 {
c6fb90c8 5377 if (!t->operands)
2dbab7d5
L		 5378 /* We've found a match; break out of loop. */
5379 break;
29b0f896 5380 }
252b5132 5381
539e75ad
L		 5382 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5383 into Disp32/Disp16/Disp32 operand. */
5384 if (i.prefix[ADDR_PREFIX] != 0)
5385 {
40fb9820 5386 /* There should be only one Disp operand. */
539e75ad
L		 5387 switch (flag_code)
5388 {
5389 case CODE_16BIT:
40fb9820
L		 5390 for (j = 0; j < MAX_OPERANDS; j++)
5391 {
5392 if (operand_types[j].bitfield.disp16)
5393 {
5394 addr_prefix_disp = j;
5395 operand_types[j].bitfield.disp32 = 1;
5396 operand_types[j].bitfield.disp16 = 0;
5397 break;
5398 }
5399 }
539e75ad
L		 5400 break;
5401 case CODE_32BIT:
40fb9820
L		 5402 for (j = 0; j < MAX_OPERANDS; j++)
5403 {
5404 if (operand_types[j].bitfield.disp32)
5405 {
5406 addr_prefix_disp = j;
5407 operand_types[j].bitfield.disp32 = 0;
5408 operand_types[j].bitfield.disp16 = 1;
5409 break;
5410 }
5411 }
539e75ad
L		 5412 break;
5413 case CODE_64BIT:
40fb9820
L		 5414 for (j = 0; j < MAX_OPERANDS; j++)
5415 {
5416 if (operand_types[j].bitfield.disp64)
5417 {
5418 addr_prefix_disp = j;
5419 operand_types[j].bitfield.disp64 = 0;
5420 operand_types[j].bitfield.disp32 = 1;
5421 break;
5422 }
5423 }
539e75ad
L		 5424 break;
5425 }
539e75ad
L		 5426 }
5427
02a86693
L		 5428 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5429 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5430 continue;
5431
56ffb741
L		 5432 /* We check register size if needed. */
5433 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5434 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5435 switch (t->operands)
5436 {
5437 case 1:
40fb9820 5438 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5439 continue;
5440 break;
5441 case 2:
33eaf5de 5442 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5443 only in 32bit mode and we can use opcode 0x90. In 64bit
5444 mode, we can't use 0x90 for xchg %eax, %eax since it should
5445 zero-extend %eax to %rax. */
5446 if (flag_code == CODE_64BIT
5447 && t->base_opcode == 0x90
0dfbf9d7
L		 5448 && operand_type_equal (&i.types [0], &acc32)
5449 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5450 continue;
1212781b
JB		 5451 /* xrelease mov %eax, <disp> is another special case. It must not
5452 match the accumulator-only encoding of mov. */
5453 if (flag_code != CODE_64BIT
5454 && i.hle_prefix
5455 && t->base_opcode == 0xa0
5456 && i.types[0].bitfield.acc
5457 && operand_type_check (i.types[1], anymem))
5458 continue;
86fa6981
L		 5459 /* If we want store form, we reverse direction of operands. */
5460 if (i.dir_encoding == dir_encoding_store
5461 && t->opcode_modifier.d)
5462 goto check_reverse;
1a0670f3 5463 /* Fall through. */
b6169b20 5464
29b0f896 5465 case 3:
86fa6981
L		 5466 /* If we want store form, we skip the current load. */
5467 if (i.dir_encoding == dir_encoding_store
5468 && i.mem_operands == 0
5469 && t->opcode_modifier.load)
fa99fab2 5470 continue;
1a0670f3 5471 /* Fall through. */
f48ff2ae 5472 case 4:
c0f3af97 5473 case 5:
c6fb90c8 5474 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5475 if (!operand_type_match (overlap0, i.types[0])
5476 || !operand_type_match (overlap1, i.types[1])
45664ddb 5477 || (check_register
dc821c5f 5478 && !operand_type_register_match (i.types[0],
40fb9820 5479 operand_types[0],
dc821c5f 5480 i.types[1],
40fb9820 5481 operand_types[1])))
29b0f896
AM		 5482 {
5483 /* Check if other direction is valid ... */
38e314eb 5484 if (!t->opcode_modifier.d)
29b0f896
AM		 5485 continue;
5486
b6169b20 5487check_reverse:
29b0f896 5488 /* Try reversing direction of operands. */
c6fb90c8
L		 5489 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5490 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5491 if (!operand_type_match (overlap0, i.types[0])
5492 || !operand_type_match (overlap1, i.types[1])
45664ddb 5493 || (check_register
dc821c5f 5494 && !operand_type_register_match (i.types[0],
45664ddb 5495 operand_types[1],
45664ddb
L		 5496 i.types[1],
5497 operand_types[0])))
29b0f896
AM		 5498 {
5499 /* Does not match either direction. */
5500 continue;
5501 }
38e314eb 5502 /* found_reverse_match holds which of D or FloatR
29b0f896 5503 we've found. */
38e314eb
JB		 5504 if (!t->opcode_modifier.d)
5505 found_reverse_match = 0;
5506 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5507 found_reverse_match = Opcode_FloatD;
5508 else
38e314eb 5509 found_reverse_match = Opcode_D;
40fb9820 5510 if (t->opcode_modifier.floatr)
8a2ed489 5511 found_reverse_match |= Opcode_FloatR;
29b0f896 5512 }
f48ff2ae 5513 else
29b0f896 5514 {
f48ff2ae 5515 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5516 switch (t->operands)
5517 {
c0f3af97
L		 5518 case 5:
5519 overlap4 = operand_type_and (i.types[4],
5520 operand_types[4]);
1a0670f3 5521 /* Fall through. */
d1cbb4db 5522 case 4:
c6fb90c8
L		 5523 overlap3 = operand_type_and (i.types[3],
5524 operand_types[3]);
1a0670f3 5525 /* Fall through. */
d1cbb4db 5526 case 3:
c6fb90c8
L		 5527 overlap2 = operand_type_and (i.types[2],
5528 operand_types[2]);
d1cbb4db
L		 5529 break;
5530 }
29b0f896 5531
f48ff2ae
L		 5532 switch (t->operands)
5533 {
c0f3af97
L		 5534 case 5:
5535 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5536 || !operand_type_register_match (i.types[3],
c0f3af97 5537 operand_types[3],
c0f3af97
L		 5538 i.types[4],
5539 operand_types[4]))
5540 continue;
1a0670f3 5541 /* Fall through. */
f48ff2ae 5542 case 4:
40fb9820 5543 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5544 || (check_register
f7768225
JB		 5545 && (!operand_type_register_match (i.types[1],
5546 operand_types[1],
5547 i.types[3],
5548 operand_types[3])
5549 || !operand_type_register_match (i.types[2],
5550 operand_types[2],
5551 i.types[3],
5552 operand_types[3]))))
f48ff2ae 5553 continue;
1a0670f3 5554 /* Fall through. */
f48ff2ae
L		 5555 case 3:
5556 /* Here we make use of the fact that there are no
23e42951 5557 reverse match 3 operand instructions. */
40fb9820 5558 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5559 || (check_register
23e42951
JB		 5560 && (!operand_type_register_match (i.types[0],
5561 operand_types[0],
5562 i.types[2],
5563 operand_types[2])
5564 || !operand_type_register_match (i.types[1],
5565 operand_types[1],
5566 i.types[2],
5567 operand_types[2]))))
f48ff2ae
L		 5568 continue;
5569 break;
5570 }
29b0f896 5571 }
f48ff2ae 5572 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5573 slip through to break. */
5574 }
3629bb00 5575 if (!found_cpu_match)
29b0f896
AM		 5576 {
5577 found_reverse_match = 0;
5578 continue;
5579 }
c0f3af97 5580
5614d22c
JB		 5581 /* Check if vector and VEX operands are valid. */
5582 if (check_VecOperands (t) || VEX_check_operands (t))
5583 {
5584 specific_error = i.error;
5585 continue;
5586 }
a683cc34 5587
29b0f896
AM		 5588 /* We've found a match; break out of loop. */
5589 break;
5590 }
5591
5592 if (t == current_templates->end)
5593 {
5594 /* We found no match. */
a65babc9 5595 const char *err_msg;
5614d22c 5596 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5597 {
5598 default:
5599 abort ();
86e026a4 5600 case operand_size_mismatch:
a65babc9
L		 5601 err_msg = _("operand size mismatch");
5602 break;
5603 case operand_type_mismatch:
5604 err_msg = _("operand type mismatch");
5605 break;
5606 case register_type_mismatch:
5607 err_msg = _("register type mismatch");
5608 break;
5609 case number_of_operands_mismatch:
5610 err_msg = _("number of operands mismatch");
5611 break;
5612 case invalid_instruction_suffix:
5613 err_msg = _("invalid instruction suffix");
5614 break;
5615 case bad_imm4:
4a2608e3 5616 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5617 break;
a65babc9
L		 5618 case unsupported_with_intel_mnemonic:
5619 err_msg = _("unsupported with Intel mnemonic");
5620 break;
5621 case unsupported_syntax:
5622 err_msg = _("unsupported syntax");
5623 break;
5624 case unsupported:
35262a23 5625 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5626 current_templates->start->name);
5627 return NULL;
6c30d220
L		 5628 case invalid_vsib_address:
5629 err_msg = _("invalid VSIB address");
5630 break;
7bab8ab5
JB		 5631 case invalid_vector_register_set:
5632 err_msg = _("mask, index, and destination registers must be distinct");
5633 break;
6c30d220
L		 5634 case unsupported_vector_index_register:
5635 err_msg = _("unsupported vector index register");
5636 break;
43234a1e
L		 5637 case unsupported_broadcast:
5638 err_msg = _("unsupported broadcast");
5639 break;
5640 case broadcast_not_on_src_operand:
5641 err_msg = _("broadcast not on source memory operand");
5642 break;
5643 case broadcast_needed:
5644 err_msg = _("broadcast is needed for operand of such type");
5645 break;
5646 case unsupported_masking:
5647 err_msg = _("unsupported masking");
5648 break;
5649 case mask_not_on_destination:
5650 err_msg = _("mask not on destination operand");
5651 break;
5652 case no_default_mask:
5653 err_msg = _("default mask isn't allowed");
5654 break;
5655 case unsupported_rc_sae:
5656 err_msg = _("unsupported static rounding/sae");
5657 break;
5658 case rc_sae_operand_not_last_imm:
5659 if (intel_syntax)
5660 err_msg = _("RC/SAE operand must precede immediate operands");
5661 else
5662 err_msg = _("RC/SAE operand must follow immediate operands");
5663 break;
5664 case invalid_register_operand:
5665 err_msg = _("invalid register operand");
5666 break;
a65babc9
L		 5667 }
5668 as_bad (_("%s for `%s'"), err_msg,
891edac4 5669 current_templates->start->name);
fa99fab2 5670 return NULL;
29b0f896 5671 }
252b5132 5672
29b0f896
AM		 5673 if (!quiet_warnings)
5674 {
5675 if (!intel_syntax
40fb9820
L		 5676 && (i.types[0].bitfield.jumpabsolute
5677 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5678 {
5679 as_warn (_("indirect %s without `*'"), t->name);
5680 }
5681
40fb9820
L		 5682 if (t->opcode_modifier.isprefix
5683 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5684 {
5685 /* Warn them that a data or address size prefix doesn't
5686 affect assembly of the next line of code. */
5687 as_warn (_("stand-alone `%s' prefix"), t->name);
5688 }
5689 }
5690
5691 /* Copy the template we found. */
5692 i.tm = *t;
539e75ad
L		 5693
5694 if (addr_prefix_disp != -1)
5695 i.tm.operand_types[addr_prefix_disp]
5696 = operand_types[addr_prefix_disp];
5697
29b0f896
AM		 5698 if (found_reverse_match)
5699 {
5700 /* If we found a reverse match we must alter the opcode
5701 direction bit. found_reverse_match holds bits to change
5702 (different for int & float insns). */
5703
5704 i.tm.base_opcode ^= found_reverse_match;
5705
539e75ad
L		 5706 i.tm.operand_types[0] = operand_types[1];
5707 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5708 }
5709
fa99fab2 5710 return t;
29b0f896
AM		 5711}
5712
5713static int
e3bb37b5 5714check_string (void)
29b0f896 5715{
40fb9820
L		 5716 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5717 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5718 {
5719 if (i.seg[0] != NULL && i.seg[0] != &es)
5720 {
a87af027 5721 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5722 i.tm.name,
a87af027
JB		 5723 mem_op + 1,
5724 register_prefix);
29b0f896
AM		 5725 return 0;
5726 }
5727 /* There's only ever one segment override allowed per instruction.
5728 This instruction possibly has a legal segment override on the
5729 second operand, so copy the segment to where non-string
5730 instructions store it, allowing common code. */
5731 i.seg[0] = i.seg[1];
5732 }
40fb9820 5733 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5734 {
5735 if (i.seg[1] != NULL && i.seg[1] != &es)
5736 {
a87af027 5737 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5738 i.tm.name,
a87af027
JB		 5739 mem_op + 2,
5740 register_prefix);
29b0f896
AM		 5741 return 0;
5742 }
5743 }
5744 return 1;
5745}
5746
5747static int
543613e9 5748process_suffix (void)
29b0f896
AM		 5749{
5750 /* If matched instruction specifies an explicit instruction mnemonic
5751 suffix, use it. */
40fb9820
L		 5752 if (i.tm.opcode_modifier.size16)
5753 i.suffix = WORD_MNEM_SUFFIX;
5754 else if (i.tm.opcode_modifier.size32)
5755 i.suffix = LONG_MNEM_SUFFIX;
5756 else if (i.tm.opcode_modifier.size64)
5757 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5758 else if (i.reg_operands)
5759 {
5760 /* If there's no instruction mnemonic suffix we try to invent one
5761 based on register operands. */
5762 if (!i.suffix)
5763 {
5764 /* We take i.suffix from the last register operand specified,
5765 Destination register type is more significant than source
381d071f
L		 5766 register type. crc32 in SSE4.2 prefers source register
5767 type. */
5768 if (i.tm.base_opcode == 0xf20f38f1)
5769 {
dc821c5f 5770 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5771 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5772 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5773 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5774 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5775 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5776 }
9344ff29 5777 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5778 {
dc821c5f 5779 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5780 i.suffix = BYTE_MNEM_SUFFIX;
5781 }
381d071f
L		 5782
5783 if (!i.suffix)
5784 {
5785 int op;
5786
20592a94
L		 5787 if (i.tm.base_opcode == 0xf20f38f1
5788 || i.tm.base_opcode == 0xf20f38f0)
5789 {
5790 /* We have to know the operand size for crc32. */
5791 as_bad (_("ambiguous memory operand size for `%s`"),
5792 i.tm.name);
5793 return 0;
5794 }
5795
381d071f 5796 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5797 if (!i.tm.operand_types[op].bitfield.inoutportreg
5798 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5799 {
8819ada6
JB		 5800 if (!i.types[op].bitfield.reg)
5801 continue;
5802 if (i.types[op].bitfield.byte)
5803 i.suffix = BYTE_MNEM_SUFFIX;
5804 else if (i.types[op].bitfield.word)
5805 i.suffix = WORD_MNEM_SUFFIX;
5806 else if (i.types[op].bitfield.dword)
5807 i.suffix = LONG_MNEM_SUFFIX;
5808 else if (i.types[op].bitfield.qword)
5809 i.suffix = QWORD_MNEM_SUFFIX;
5810 else
5811 continue;
5812 break;
381d071f
L		 5813 }
5814 }
29b0f896
AM		 5815 }
5816 else if (i.suffix == BYTE_MNEM_SUFFIX)
5817 {
2eb952a4
L		 5818 if (intel_syntax
5819 && i.tm.opcode_modifier.ignoresize
5820 && i.tm.opcode_modifier.no_bsuf)
5821 i.suffix = 0;
5822 else if (!check_byte_reg ())
29b0f896
AM		 5823 return 0;
5824 }
5825 else if (i.suffix == LONG_MNEM_SUFFIX)
5826 {
2eb952a4
L		 5827 if (intel_syntax
5828 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5829 && i.tm.opcode_modifier.no_lsuf
5830 && !i.tm.opcode_modifier.todword
5831 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5832 i.suffix = 0;
5833 else if (!check_long_reg ())
29b0f896
AM		 5834 return 0;
5835 }
5836 else if (i.suffix == QWORD_MNEM_SUFFIX)
5837 {
955e1e6a
L		 5838 if (intel_syntax
5839 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5840 && i.tm.opcode_modifier.no_qsuf
5841 && !i.tm.opcode_modifier.todword
5842 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5843 i.suffix = 0;
5844 else if (!check_qword_reg ())
29b0f896
AM		 5845 return 0;
5846 }
5847 else if (i.suffix == WORD_MNEM_SUFFIX)
5848 {
2eb952a4
L		 5849 if (intel_syntax
5850 && i.tm.opcode_modifier.ignoresize
5851 && i.tm.opcode_modifier.no_wsuf)
5852 i.suffix = 0;
5853 else if (!check_word_reg ())
29b0f896
AM		 5854 return 0;
5855 }
40fb9820 5856 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5857 /* Do nothing if the instruction is going to ignore the prefix. */
5858 ;
5859 else
5860 abort ();
5861 }
40fb9820 5862 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5863 && !i.suffix
5864 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5865 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5866 {
5867 i.suffix = stackop_size;
5868 }
9306ca4a
JB		 5869 else if (intel_syntax
5870 && !i.suffix
40fb9820
L		 5871 && (i.tm.operand_types[0].bitfield.jumpabsolute
5872 || i.tm.opcode_modifier.jumpbyte
5873 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5874 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5875 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5876 {
5877 switch (flag_code)
5878 {
5879 case CODE_64BIT:
40fb9820 5880 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5881 {
5882 i.suffix = QWORD_MNEM_SUFFIX;
5883 break;
5884 }
1a0670f3 5885 /* Fall through. */
9306ca4a 5886 case CODE_32BIT:
40fb9820 5887 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5888 i.suffix = LONG_MNEM_SUFFIX;
5889 break;
5890 case CODE_16BIT:
40fb9820 5891 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5892 i.suffix = WORD_MNEM_SUFFIX;
5893 break;
5894 }
5895 }
252b5132 5896
9306ca4a 5897 if (!i.suffix)
29b0f896 5898 {
9306ca4a
JB		 5899 if (!intel_syntax)
5900 {
40fb9820 5901 if (i.tm.opcode_modifier.w)
9306ca4a 5902 {
4eed87de
AM		 5903 as_bad (_("no instruction mnemonic suffix given and "
5904 "no register operands; can't size instruction"));
9306ca4a
JB		 5905 return 0;
5906 }
5907 }
5908 else
5909 {
40fb9820 5910 unsigned int suffixes;
7ab9ffdd 5911
40fb9820
L		 5912 suffixes = !i.tm.opcode_modifier.no_bsuf;
5913 if (!i.tm.opcode_modifier.no_wsuf)
5914 suffixes |= 1 << 1;
5915 if (!i.tm.opcode_modifier.no_lsuf)
5916 suffixes |= 1 << 2;
fc4adea1 5917 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5918 suffixes |= 1 << 3;
5919 if (!i.tm.opcode_modifier.no_ssuf)
5920 suffixes |= 1 << 4;
c2b9da16 5921 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5922 suffixes |= 1 << 5;
5923
5924 /* There are more than suffix matches. */
5925 if (i.tm.opcode_modifier.w
9306ca4a 5926 || ((suffixes & (suffixes - 1))
40fb9820
L		 5927 && !i.tm.opcode_modifier.defaultsize
5928 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5929 {
5930 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5931 return 0;
5932 }
5933 }
29b0f896 5934 }
252b5132 5935
d2224064
JB		 5936 /* Change the opcode based on the operand size given by i.suffix. */
5937 switch (i.suffix)
29b0f896 5938 {
d2224064
JB		 5939 /* Size floating point instruction. */
5940 case LONG_MNEM_SUFFIX:
5941 if (i.tm.opcode_modifier.floatmf)
5942 {
5943 i.tm.base_opcode ^= 4;
5944 break;
5945 }
5946 /* fall through */
5947 case WORD_MNEM_SUFFIX:
5948 case QWORD_MNEM_SUFFIX:
29b0f896 5949 /* It's not a byte, select word/dword operation. */
40fb9820 5950 if (i.tm.opcode_modifier.w)
29b0f896 5951 {
40fb9820 5952 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5953 i.tm.base_opcode |= 8;
5954 else
5955 i.tm.base_opcode |= 1;
5956 }
d2224064
JB		 5957 /* fall through */
5958 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 5959 /* Now select between word & dword operations via the operand
5960 size prefix, except for instructions that will ignore this
5961 prefix anyway. */
ca61edf2 5962 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5963 {
ca61edf2
L		 5964 /* The address size override prefix changes the size of the
5965 first operand. */
40fb9820 5966 if ((flag_code == CODE_32BIT
dc821c5f 5967 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5968 || (flag_code != CODE_32BIT
dc821c5f 5969 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5970 if (!add_prefix (ADDR_PREFIX_OPCODE))
5971 return 0;
5972 }
5973 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 5974 && !i.tm.opcode_modifier.ignoresize
5975 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5976 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5977 || (flag_code == CODE_64BIT
40fb9820 5978 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5979 {
5980 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5981
40fb9820 5982 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5983 prefix = ADDR_PREFIX_OPCODE;
252b5132 5984
29b0f896
AM		 5985 if (!add_prefix (prefix))
5986 return 0;
24eab124 5987 }
252b5132 5988
29b0f896
AM		 5989 /* Set mode64 for an operand. */
5990 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5991 && flag_code == CODE_64BIT
d2224064 5992 && !i.tm.opcode_modifier.norex64
46e883c5 5993 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 5994 need rex64. */
5995 && ! (i.operands == 2
5996 && i.tm.base_opcode == 0x90
5997 && i.tm.extension_opcode == None
5998 && operand_type_equal (&i.types [0], &acc64)
5999 && operand_type_equal (&i.types [1], &acc64)))
6000 i.rex |= REX_W;
3e73aa7c 6001
d2224064 6002 break;
29b0f896 6003 }
7ecd2f8b 6004
29b0f896
AM		 6005 return 1;
6006}
3e73aa7c 6007
29b0f896 6008static int
543613e9 6009check_byte_reg (void)
29b0f896
AM		 6010{
6011 int op;
543613e9 6012
29b0f896
AM		 6013 for (op = i.operands; --op >= 0;)
6014 {
dc821c5f
JB		 6015 /* Skip non-register operands. */
6016 if (!i.types[op].bitfield.reg)
6017 continue;
6018
29b0f896
AM		 6019 /* If this is an eight bit register, it's OK. If it's the 16 or
6020 32 bit version of an eight bit register, we will just use the
6021 low portion, and that's OK too. */
dc821c5f 6022 if (i.types[op].bitfield.byte)
29b0f896
AM		 6023 continue;
6024
5a819eb9
JB		 6025 /* I/O port address operands are OK too. */
6026 if (i.tm.operand_types[op].bitfield.inoutportreg)
6027 continue;
6028
9344ff29
L		 6029 /* crc32 doesn't generate this warning. */
6030 if (i.tm.base_opcode == 0xf20f38f0)
6031 continue;
6032
dc821c5f
JB		 6033 if ((i.types[op].bitfield.word
6034 || i.types[op].bitfield.dword
6035 || i.types[op].bitfield.qword)
5a819eb9
JB		 6036 && i.op[op].regs->reg_num < 4
6037 /* Prohibit these changes in 64bit mode, since the lowering
6038 would be more complicated. */
6039 && flag_code != CODE_64BIT)
29b0f896 6040 {
29b0f896 6041#if REGISTER_WARNINGS
5a819eb9 6042 if (!quiet_warnings)
a540244d
L		 6043 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6044 register_prefix,
dc821c5f 6045 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6046 ? REGNAM_AL - REGNAM_AX
6047 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6048 register_prefix,
29b0f896
AM		 6049 i.op[op].regs->reg_name,
6050 i.suffix);
6051#endif
6052 continue;
6053 }
6054 /* Any other register is bad. */
dc821c5f 6055 if (i.types[op].bitfield.reg
40fb9820 6056 || i.types[op].bitfield.regmmx
1b54b8d7 6057 || i.types[op].bitfield.regsimd
40fb9820
L		 6058 || i.types[op].bitfield.sreg2
6059 || i.types[op].bitfield.sreg3
6060 || i.types[op].bitfield.control
6061 || i.types[op].bitfield.debug
ca0d63fe 6062 || i.types[op].bitfield.test)
29b0f896 6063 {
a540244d
L		 6064 as_bad (_("`%s%s' not allowed with `%s%c'"),
6065 register_prefix,
29b0f896
AM		 6066 i.op[op].regs->reg_name,
6067 i.tm.name,
6068 i.suffix);
6069 return 0;
6070 }
6071 }
6072 return 1;
6073}
6074
6075static int
e3bb37b5 6076check_long_reg (void)
29b0f896
AM		 6077{
6078 int op;
6079
6080 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6081 /* Skip non-register operands. */
6082 if (!i.types[op].bitfield.reg)
6083 continue;
29b0f896
AM		 6084 /* Reject eight bit registers, except where the template requires
6085 them. (eg. movzb) */
dc821c5f
JB		 6086 else if (i.types[op].bitfield.byte
6087 && (i.tm.operand_types[op].bitfield.reg
6088 || i.tm.operand_types[op].bitfield.acc)
6089 && (i.tm.operand_types[op].bitfield.word
6090 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6091 {
a540244d
L		 6092 as_bad (_("`%s%s' not allowed with `%s%c'"),
6093 register_prefix,
29b0f896
AM		 6094 i.op[op].regs->reg_name,
6095 i.tm.name,
6096 i.suffix);
6097 return 0;
6098 }
e4630f71 6099 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6100 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6101 && i.types[op].bitfield.word
6102 && (i.tm.operand_types[op].bitfield.reg
6103 || i.tm.operand_types[op].bitfield.acc)
6104 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6105 {
6106 /* Prohibit these changes in the 64bit mode, since the
6107 lowering is more complicated. */
6108 if (flag_code == CODE_64BIT)
252b5132 6109 {
2b5d6a91 6110 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6111 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6112 i.suffix);
6113 return 0;
252b5132 6114 }
29b0f896 6115#if REGISTER_WARNINGS
cecf1424
JB		 6116 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6117 register_prefix,
6118 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6119 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6120#endif
252b5132 6121 }
e4630f71 6122 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6123 else if (i.types[op].bitfield.qword
6124 && (i.tm.operand_types[op].bitfield.reg
6125 || i.tm.operand_types[op].bitfield.acc)
6126 && i.tm.operand_types[op].bitfield.dword)
252b5132 6127 {
34828aad 6128 if (intel_syntax
ca61edf2 6129 && i.tm.opcode_modifier.toqword
1b54b8d7 6130 && !i.types[0].bitfield.regsimd)
34828aad 6131 {
ca61edf2 6132 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6133 i.suffix = QWORD_MNEM_SUFFIX;
6134 }
6135 else
6136 {
2b5d6a91 6137 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6138 register_prefix, i.op[op].regs->reg_name,
6139 i.suffix);
6140 return 0;
6141 }
29b0f896
AM		 6142 }
6143 return 1;
6144}
252b5132 6145
29b0f896 6146static int
e3bb37b5 6147check_qword_reg (void)
29b0f896
AM		 6148{
6149 int op;
252b5132 6150
29b0f896 6151 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6152 /* Skip non-register operands. */
6153 if (!i.types[op].bitfield.reg)
6154 continue;
29b0f896
AM		 6155 /* Reject eight bit registers, except where the template requires
6156 them. (eg. movzb) */
dc821c5f
JB		 6157 else if (i.types[op].bitfield.byte
6158 && (i.tm.operand_types[op].bitfield.reg
6159 || i.tm.operand_types[op].bitfield.acc)
6160 && (i.tm.operand_types[op].bitfield.word
6161 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6162 {
a540244d
L		 6163 as_bad (_("`%s%s' not allowed with `%s%c'"),
6164 register_prefix,
29b0f896
AM		 6165 i.op[op].regs->reg_name,
6166 i.tm.name,
6167 i.suffix);
6168 return 0;
6169 }
e4630f71 6170 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6171 else if ((i.types[op].bitfield.word
6172 || i.types[op].bitfield.dword)
6173 && (i.tm.operand_types[op].bitfield.reg
6174 || i.tm.operand_types[op].bitfield.acc)
6175 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6176 {
6177 /* Prohibit these changes in the 64bit mode, since the
6178 lowering is more complicated. */
34828aad 6179 if (intel_syntax
ca61edf2 6180 && i.tm.opcode_modifier.todword
1b54b8d7 6181 && !i.types[0].bitfield.regsimd)
34828aad 6182 {
ca61edf2 6183 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6184 i.suffix = LONG_MNEM_SUFFIX;
6185 }
6186 else
6187 {
2b5d6a91 6188 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6189 register_prefix, i.op[op].regs->reg_name,
6190 i.suffix);
6191 return 0;
6192 }
252b5132 6193 }
29b0f896
AM		 6194 return 1;
6195}
252b5132 6196
29b0f896 6197static int
e3bb37b5 6198check_word_reg (void)
29b0f896
AM		 6199{
6200 int op;
6201 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6202 /* Skip non-register operands. */
6203 if (!i.types[op].bitfield.reg)
6204 continue;
29b0f896
AM		 6205 /* Reject eight bit registers, except where the template requires
6206 them. (eg. movzb) */
dc821c5f
JB		 6207 else if (i.types[op].bitfield.byte
6208 && (i.tm.operand_types[op].bitfield.reg
6209 || i.tm.operand_types[op].bitfield.acc)
6210 && (i.tm.operand_types[op].bitfield.word
6211 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6212 {
a540244d
L		 6213 as_bad (_("`%s%s' not allowed with `%s%c'"),
6214 register_prefix,
29b0f896
AM		 6215 i.op[op].regs->reg_name,
6216 i.tm.name,
6217 i.suffix);
6218 return 0;
6219 }
e4630f71 6220 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6221 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6222 && (i.types[op].bitfield.dword
6223 || i.types[op].bitfield.qword)
6224 && (i.tm.operand_types[op].bitfield.reg
6225 || i.tm.operand_types[op].bitfield.acc)
6226 && i.tm.operand_types[op].bitfield.word)
252b5132 6227 {
29b0f896
AM		 6228 /* Prohibit these changes in the 64bit mode, since the
6229 lowering is more complicated. */
6230 if (flag_code == CODE_64BIT)
252b5132 6231 {
2b5d6a91 6232 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6233 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6234 i.suffix);
6235 return 0;
252b5132 6236 }
29b0f896 6237#if REGISTER_WARNINGS
cecf1424
JB		 6238 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6239 register_prefix,
6240 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6241 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6242#endif
6243 }
6244 return 1;
6245}
252b5132 6246
29b0f896 6247static int
40fb9820 6248update_imm (unsigned int j)
29b0f896 6249{
bc0844ae 6250 i386_operand_type overlap = i.types[j];
40fb9820
L		 6251 if ((overlap.bitfield.imm8
6252 || overlap.bitfield.imm8s
6253 || overlap.bitfield.imm16
6254 || overlap.bitfield.imm32
6255 || overlap.bitfield.imm32s
6256 || overlap.bitfield.imm64)
0dfbf9d7
L		 6257 && !operand_type_equal (&overlap, &imm8)
6258 && !operand_type_equal (&overlap, &imm8s)
6259 && !operand_type_equal (&overlap, &imm16)
6260 && !operand_type_equal (&overlap, &imm32)
6261 && !operand_type_equal (&overlap, &imm32s)
6262 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6263 {
6264 if (i.suffix)
6265 {
40fb9820
L		 6266 i386_operand_type temp;
6267
0dfbf9d7 6268 operand_type_set (&temp, 0);
7ab9ffdd 6269 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6270 {
6271 temp.bitfield.imm8 = overlap.bitfield.imm8;
6272 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6273 }
6274 else if (i.suffix == WORD_MNEM_SUFFIX)
6275 temp.bitfield.imm16 = overlap.bitfield.imm16;
6276 else if (i.suffix == QWORD_MNEM_SUFFIX)
6277 {
6278 temp.bitfield.imm64 = overlap.bitfield.imm64;
6279 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6280 }
6281 else
6282 temp.bitfield.imm32 = overlap.bitfield.imm32;
6283 overlap = temp;
29b0f896 6284 }
0dfbf9d7
L		 6285 else if (operand_type_equal (&overlap, &imm16_32_32s)
6286 || operand_type_equal (&overlap, &imm16_32)
6287 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6288 {
40fb9820 6289 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6290 overlap = imm16;
40fb9820 6291 else
65da13b5 6292 overlap = imm32s;
29b0f896 6293 }
0dfbf9d7
L		 6294 if (!operand_type_equal (&overlap, &imm8)
6295 && !operand_type_equal (&overlap, &imm8s)
6296 && !operand_type_equal (&overlap, &imm16)
6297 && !operand_type_equal (&overlap, &imm32)
6298 && !operand_type_equal (&overlap, &imm32s)
6299 && !operand_type_equal (&overlap, &imm64))
29b0f896 6300 {
4eed87de
AM		 6301 as_bad (_("no instruction mnemonic suffix given; "
6302 "can't determine immediate size"));
29b0f896
AM		 6303 return 0;
6304 }
6305 }
40fb9820 6306 i.types[j] = overlap;
29b0f896 6307
40fb9820
L		 6308 return 1;
6309}
6310
6311static int
6312finalize_imm (void)
6313{
bc0844ae 6314 unsigned int j, n;
29b0f896 6315
bc0844ae
L		 6316 /* Update the first 2 immediate operands. */
6317 n = i.operands > 2 ? 2 : i.operands;
6318 if (n)
6319 {
6320 for (j = 0; j < n; j++)
6321 if (update_imm (j) == 0)
6322 return 0;
40fb9820 6323
bc0844ae
L		 6324 /* The 3rd operand can't be immediate operand. */
6325 gas_assert (operand_type_check (i.types[2], imm) == 0);
6326 }
29b0f896
AM		 6327
6328 return 1;
6329}
6330
6331static int
e3bb37b5 6332process_operands (void)
29b0f896
AM		 6333{
6334 /* Default segment register this instruction will use for memory
6335 accesses. 0 means unknown. This is only for optimizing out
6336 unnecessary segment overrides. */
6337 const seg_entry *default_seg = 0;
6338
2426c15f 6339 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6340 {
91d6fa6a
NC		 6341 unsigned int dupl = i.operands;
6342 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6343 unsigned int j;
6344
c0f3af97 6345 /* The destination must be an xmm register. */
9c2799c2 6346 gas_assert (i.reg_operands
91d6fa6a 6347 && MAX_OPERANDS > dupl
7ab9ffdd 6348 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6349
1b54b8d7
JB		 6350 if (i.tm.operand_types[0].bitfield.acc
6351 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6352 {
8cd7925b 6353 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6354 {
6355 /* Keep xmm0 for instructions with VEX prefix and 3
6356 sources. */
1b54b8d7
JB		 6357 i.tm.operand_types[0].bitfield.acc = 0;
6358 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6359 goto duplicate;
6360 }
e2ec9d29 6361 else
c0f3af97
L		 6362 {
6363 /* We remove the first xmm0 and keep the number of
6364 operands unchanged, which in fact duplicates the
6365 destination. */
6366 for (j = 1; j < i.operands; j++)
6367 {
6368 i.op[j - 1] = i.op[j];
6369 i.types[j - 1] = i.types[j];
6370 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6371 }
6372 }
6373 }
6374 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6375 {
91d6fa6a 6376 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6377 && (i.tm.opcode_modifier.vexsources
6378 == VEX3SOURCES));
c0f3af97
L		 6379
6380 /* Add the implicit xmm0 for instructions with VEX prefix
6381 and 3 sources. */
6382 for (j = i.operands; j > 0; j--)
6383 {
6384 i.op[j] = i.op[j - 1];
6385 i.types[j] = i.types[j - 1];
6386 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6387 }
6388 i.op[0].regs
6389 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6390 i.types[0] = regxmm;
c0f3af97
L		 6391 i.tm.operand_types[0] = regxmm;
6392
6393 i.operands += 2;
6394 i.reg_operands += 2;
6395 i.tm.operands += 2;
6396
91d6fa6a 6397 dupl++;
c0f3af97 6398 dest++;
91d6fa6a
NC		 6399 i.op[dupl] = i.op[dest];
6400 i.types[dupl] = i.types[dest];
6401 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6402 }
c0f3af97
L		 6403 else
6404 {
6405duplicate:
6406 i.operands++;
6407 i.reg_operands++;
6408 i.tm.operands++;
6409
91d6fa6a
NC		 6410 i.op[dupl] = i.op[dest];
6411 i.types[dupl] = i.types[dest];
6412 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6413 }
6414
6415 if (i.tm.opcode_modifier.immext)
6416 process_immext ();
6417 }
1b54b8d7
JB		 6418 else if (i.tm.operand_types[0].bitfield.acc
6419 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6420 {
6421 unsigned int j;
6422
9fcfb3d7
L		 6423 for (j = 1; j < i.operands; j++)
6424 {
6425 i.op[j - 1] = i.op[j];
6426 i.types[j - 1] = i.types[j];
6427
6428 /* We need to adjust fields in i.tm since they are used by
6429 build_modrm_byte. */
6430 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6431 }
6432
e2ec9d29
L		 6433 i.operands--;
6434 i.reg_operands--;
e2ec9d29
L		 6435 i.tm.operands--;
6436 }
920d2ddc
IT		 6437 else if (i.tm.opcode_modifier.implicitquadgroup)
6438 {
a477a8c4
JB		 6439 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6440
920d2ddc 6441 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6442 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6443 regnum = register_number (i.op[1].regs);
6444 first_reg_in_group = regnum & ~3;
6445 last_reg_in_group = first_reg_in_group + 3;
6446 if (regnum != first_reg_in_group)
6447 as_warn (_("source register `%s%s' implicitly denotes"
6448 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6449 register_prefix, i.op[1].regs->reg_name,
6450 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6451 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6452 i.tm.name);
6453 }
e2ec9d29
L		 6454 else if (i.tm.opcode_modifier.regkludge)
6455 {
6456 /* The imul $imm, %reg instruction is converted into
6457 imul $imm, %reg, %reg, and the clr %reg instruction
6458 is converted into xor %reg, %reg. */
6459
6460 unsigned int first_reg_op;
6461
6462 if (operand_type_check (i.types[0], reg))
6463 first_reg_op = 0;
6464 else
6465 first_reg_op = 1;
6466 /* Pretend we saw the extra register operand. */
9c2799c2 6467 gas_assert (i.reg_operands == 1
7ab9ffdd 6468 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6469 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6470 i.types[first_reg_op + 1] = i.types[first_reg_op];
6471 i.operands++;
6472 i.reg_operands++;
29b0f896
AM		 6473 }
6474
40fb9820 6475 if (i.tm.opcode_modifier.shortform)
29b0f896 6476 {
40fb9820
L		 6477 if (i.types[0].bitfield.sreg2
6478 || i.types[0].bitfield.sreg3)
29b0f896 6479 {
4eed87de
AM		 6480 if (i.tm.base_opcode == POP_SEG_SHORT
6481 && i.op[0].regs->reg_num == 1)
29b0f896 6482 {
a87af027 6483 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6484 return 0;
29b0f896 6485 }
4eed87de
AM		 6486 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6487 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6488 i.rex |= REX_B;
4eed87de
AM		 6489 }
6490 else
6491 {
7ab9ffdd 6492 /* The register or float register operand is in operand
85f10a01 6493 0 or 1. */
40fb9820 6494 unsigned int op;
7ab9ffdd 6495
ca0d63fe 6496 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6497 || operand_type_check (i.types[0], reg))
6498 op = 0;
6499 else
6500 op = 1;
4eed87de
AM		 6501 /* Register goes in low 3 bits of opcode. */
6502 i.tm.base_opcode |= i.op[op].regs->reg_num;
6503 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6504 i.rex |= REX_B;
40fb9820 6505 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6506 {
4eed87de
AM		 6507 /* Warn about some common errors, but press on regardless.
6508 The first case can be generated by gcc (<= 2.8.1). */
6509 if (i.operands == 2)
6510 {
6511 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6512 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6513 register_prefix, i.op[!intel_syntax].regs->reg_name,
6514 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6515 }
6516 else
6517 {
6518 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6519 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6520 register_prefix, i.op[0].regs->reg_name);
4eed87de 6521 }
29b0f896
AM		 6522 }
6523 }
6524 }
40fb9820 6525 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6526 {
6527 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6528 must be put into the modrm byte). Now, we make the modrm and
6529 index base bytes based on all the info we've collected. */
29b0f896
AM		 6530
6531 default_seg = build_modrm_byte ();
6532 }
8a2ed489 6533 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6534 {
6535 default_seg = &ds;
6536 }
40fb9820 6537 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6538 {
6539 /* For the string instructions that allow a segment override
6540 on one of their operands, the default segment is ds. */
6541 default_seg = &ds;
6542 }
6543
75178d9d
L		 6544 if (i.tm.base_opcode == 0x8d /* lea */
6545 && i.seg[0]
6546 && !quiet_warnings)
30123838 6547 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6548
6549 /* If a segment was explicitly specified, and the specified segment
6550 is not the default, use an opcode prefix to select it. If we
6551 never figured out what the default segment is, then default_seg
6552 will be zero at this point, and the specified segment prefix will
6553 always be used. */
29b0f896
AM		 6554 if ((i.seg[0]) && (i.seg[0] != default_seg))
6555 {
6556 if (!add_prefix (i.seg[0]->seg_prefix))
6557 return 0;
6558 }
6559 return 1;
6560}
6561
6562static const seg_entry *
e3bb37b5 6563build_modrm_byte (void)
29b0f896
AM		 6564{
6565 const seg_entry *default_seg = 0;
c0f3af97 6566 unsigned int source, dest;
8cd7925b 6567 int vex_3_sources;
c0f3af97
L		 6568
6569 /* The first operand of instructions with VEX prefix and 3 sources
6570 must be VEX_Imm4. */
8cd7925b 6571 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6572 if (vex_3_sources)
6573 {
91d6fa6a 6574 unsigned int nds, reg_slot;
4c2c6516 6575 expressionS *exp;
c0f3af97 6576
922d8de8 6577 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6578 && i.tm.opcode_modifier.immext)
6579 {
6580 dest = i.operands - 2;
6581 gas_assert (dest == 3);
6582 }
922d8de8 6583 else
a683cc34 6584 dest = i.operands - 1;
c0f3af97 6585 nds = dest - 1;
922d8de8 6586
a683cc34
SP		 6587 /* There are 2 kinds of instructions:
6588 1. 5 operands: 4 register operands or 3 register operands
6589 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6590 VexW0 or VexW1. The destination must be either XMM, YMM or
6591 ZMM register.
a683cc34
SP		 6592 2. 4 operands: 4 register operands or 3 register operands
6593 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6594 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6595 || (i.reg_operands == 3 && i.mem_operands == 1))
6596 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6597 && (i.tm.opcode_modifier.veximmext
6598 || (i.imm_operands == 1
6599 && i.types[0].bitfield.vec_imm4
6600 && (i.tm.opcode_modifier.vexw == VEXW0
6601 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6602 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6603
6604 if (i.imm_operands == 0)
6605 {
6606 /* When there is no immediate operand, generate an 8bit
6607 immediate operand to encode the first operand. */
6608 exp = &im_expressions[i.imm_operands++];
6609 i.op[i.operands].imms = exp;
6610 i.types[i.operands] = imm8;
6611 i.operands++;
6612 /* If VexW1 is set, the first operand is the source and
6613 the second operand is encoded in the immediate operand. */
6614 if (i.tm.opcode_modifier.vexw == VEXW1)
6615 {
6616 source = 0;
6617 reg_slot = 1;
6618 }
6619 else
6620 {
6621 source = 1;
6622 reg_slot = 0;
6623 }
6624
6625 /* FMA swaps REG and NDS. */
6626 if (i.tm.cpu_flags.bitfield.cpufma)
6627 {
6628 unsigned int tmp;
6629 tmp = reg_slot;
6630 reg_slot = nds;
6631 nds = tmp;
6632 }
6633
10c17abd 6634 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6635 exp->X_op = O_constant;
4c692bc7 6636 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6637 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6638 }
922d8de8 6639 else
a683cc34
SP		 6640 {
6641 unsigned int imm_slot;
6642
6643 if (i.tm.opcode_modifier.vexw == VEXW0)
6644 {
6645 /* If VexW0 is set, the third operand is the source and
6646 the second operand is encoded in the immediate
6647 operand. */
6648 source = 2;
6649 reg_slot = 1;
6650 }
6651 else
6652 {
6653 /* VexW1 is set, the second operand is the source and
6654 the third operand is encoded in the immediate
6655 operand. */
6656 source = 1;
6657 reg_slot = 2;
6658 }
6659
6660 if (i.tm.opcode_modifier.immext)
6661 {
33eaf5de 6662 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6663 operand. */
6664 imm_slot = i.operands - 1;
6665 source--;
6666 reg_slot--;
6667 }
6668 else
6669 {
6670 imm_slot = 0;
6671
6672 /* Turn on Imm8 so that output_imm will generate it. */
6673 i.types[imm_slot].bitfield.imm8 = 1;
6674 }
6675
10c17abd 6676 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6677 i.op[imm_slot].imms->X_add_number
4c692bc7 6678 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6679 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6680 }
6681
10c17abd 6682 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6683 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6684 }
6685 else
6686 source = dest = 0;
29b0f896
AM		 6687
6688 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6689 implicit registers do not count. If there are 3 register
6690 operands, it must be a instruction with VexNDS. For a
6691 instruction with VexNDD, the destination register is encoded
6692 in VEX prefix. If there are 4 register operands, it must be
6693 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6694 if (i.mem_operands == 0
6695 && ((i.reg_operands == 2
2426c15f 6696 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6697 || (i.reg_operands == 3
2426c15f 6698 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6699 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6700 {
cab737b9
L		 6701 switch (i.operands)
6702 {
6703 case 2:
6704 source = 0;
6705 break;
6706 case 3:
c81128dc
L		 6707 /* When there are 3 operands, one of them may be immediate,
6708 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6709 the first operand must be shift count register (cl) or it
6710 is an instruction with VexNDS. */
9c2799c2 6711 gas_assert (i.imm_operands == 1
7ab9ffdd 6712 || (i.imm_operands == 0
2426c15f 6713 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6714 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6715 if (operand_type_check (i.types[0], imm)
6716 || i.types[0].bitfield.shiftcount)
6717 source = 1;
6718 else
6719 source = 0;
cab737b9
L		 6720 break;
6721 case 4:
368d64cc
L		 6722 /* When there are 4 operands, the first two must be 8bit
6723 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6724 one.
6725
6726 For instructions with VexNDS, if the first operand
6727 an imm8, the source operand is the 2nd one. If the last
6728 operand is imm8, the source operand is the first one. */
9c2799c2 6729 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6730 && i.types[0].bitfield.imm8
6731 && i.types[1].bitfield.imm8)
2426c15f 6732 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6733 && i.imm_operands == 1
6734 && (i.types[0].bitfield.imm8
43234a1e
L		 6735 || i.types[i.operands - 1].bitfield.imm8
6736 || i.rounding)));
9f2670f2
L		 6737 if (i.imm_operands == 2)
6738 source = 2;
6739 else
c0f3af97
L		 6740 {
6741 if (i.types[0].bitfield.imm8)
6742 source = 1;
6743 else
6744 source = 0;
6745 }
c0f3af97
L		 6746 break;
6747 case 5:
e771e7c9 6748 if (is_evex_encoding (&i.tm))
43234a1e
L		 6749 {
6750 /* For EVEX instructions, when there are 5 operands, the
6751 first one must be immediate operand. If the second one
6752 is immediate operand, the source operand is the 3th
6753 one. If the last one is immediate operand, the source
6754 operand is the 2nd one. */
6755 gas_assert (i.imm_operands == 2
6756 && i.tm.opcode_modifier.sae
6757 && operand_type_check (i.types[0], imm));
6758 if (operand_type_check (i.types[1], imm))
6759 source = 2;
6760 else if (operand_type_check (i.types[4], imm))
6761 source = 1;
6762 else
6763 abort ();
6764 }
cab737b9
L		 6765 break;
6766 default:
6767 abort ();
6768 }
6769
c0f3af97
L		 6770 if (!vex_3_sources)
6771 {
6772 dest = source + 1;
6773
43234a1e
L		 6774 /* RC/SAE operand could be between DEST and SRC. That happens
6775 when one operand is GPR and the other one is XMM/YMM/ZMM
6776 register. */
6777 if (i.rounding && i.rounding->operand == (int) dest)
6778 dest++;
6779
2426c15f 6780 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6781 {
43234a1e 6782 /* For instructions with VexNDS, the register-only source
c5d0745b 6783 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6784 register. It is encoded in VEX prefix. We need to
6785 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6786
6787 i386_operand_type op;
6788 unsigned int vvvv;
6789
6790 /* Check register-only source operand when two source
6791 operands are swapped. */
6792 if (!i.tm.operand_types[source].bitfield.baseindex
6793 && i.tm.operand_types[dest].bitfield.baseindex)
6794 {
6795 vvvv = source;
6796 source = dest;
6797 }
6798 else
6799 vvvv = dest;
6800
6801 op = i.tm.operand_types[vvvv];
fa99fab2 6802 op.bitfield.regmem = 0;
c0f3af97 6803 if ((dest + 1) >= i.operands
dc821c5f
JB		 6804 || ((!op.bitfield.reg
6805 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6806 && !op.bitfield.regsimd
43234a1e 6807 && !operand_type_equal (&op, &regmask)))
c0f3af97 6808 abort ();
f12dc422 6809 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6810 dest++;
6811 }
6812 }
29b0f896
AM		 6813
6814 i.rm.mode = 3;
6815 /* One of the register operands will be encoded in the i.tm.reg
6816 field, the other in the combined i.tm.mode and i.tm.regmem
6817 fields. If no form of this instruction supports a memory
6818 destination operand, then we assume the source operand may
6819 sometimes be a memory operand and so we need to store the
6820 destination in the i.rm.reg field. */
40fb9820
L		 6821 if (!i.tm.operand_types[dest].bitfield.regmem
6822 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6823 {
6824 i.rm.reg = i.op[dest].regs->reg_num;
6825 i.rm.regmem = i.op[source].regs->reg_num;
6826 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6827 i.rex |= REX_R;
43234a1e
L		 6828 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6829 i.vrex |= REX_R;
29b0f896 6830 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6831 i.rex |= REX_B;
43234a1e
L		 6832 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6833 i.vrex |= REX_B;
29b0f896
AM		 6834 }
6835 else
6836 {
6837 i.rm.reg = i.op[source].regs->reg_num;
6838 i.rm.regmem = i.op[dest].regs->reg_num;
6839 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6840 i.rex |= REX_B;
43234a1e
L		 6841 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6842 i.vrex |= REX_B;
29b0f896 6843 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6844 i.rex |= REX_R;
43234a1e
L		 6845 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6846 i.vrex |= REX_R;
29b0f896 6847 }
161a04f6 6848 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6849 {
40fb9820
L		 6850 if (!i.types[0].bitfield.control
6851 && !i.types[1].bitfield.control)
c4a530c5 6852 abort ();
161a04f6 6853 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6854 add_prefix (LOCK_PREFIX_OPCODE);
6855 }
29b0f896
AM		 6856 }
6857 else
6858 { /* If it's not 2 reg operands... */
c0f3af97
L		 6859 unsigned int mem;
6860
29b0f896
AM		 6861 if (i.mem_operands)
6862 {
6863 unsigned int fake_zero_displacement = 0;
99018f42 6864 unsigned int op;
4eed87de 6865
7ab9ffdd
L		 6866 for (op = 0; op < i.operands; op++)
6867 if (operand_type_check (i.types[op], anymem))
6868 break;
7ab9ffdd 6869 gas_assert (op < i.operands);
29b0f896 6870
6c30d220
L		 6871 if (i.tm.opcode_modifier.vecsib)
6872 {
6873 if (i.index_reg->reg_num == RegEiz
6874 || i.index_reg->reg_num == RegRiz)
6875 abort ();
6876
6877 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6878 if (!i.base_reg)
6879 {
6880 i.sib.base = NO_BASE_REGISTER;
6881 i.sib.scale = i.log2_scale_factor;
6882 i.types[op].bitfield.disp8 = 0;
6883 i.types[op].bitfield.disp16 = 0;
6884 i.types[op].bitfield.disp64 = 0;
43083a50 6885 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6886 {
6887 /* Must be 32 bit */
6888 i.types[op].bitfield.disp32 = 1;
6889 i.types[op].bitfield.disp32s = 0;
6890 }
6891 else
6892 {
6893 i.types[op].bitfield.disp32 = 0;
6894 i.types[op].bitfield.disp32s = 1;
6895 }
6896 }
6897 i.sib.index = i.index_reg->reg_num;
6898 if ((i.index_reg->reg_flags & RegRex) != 0)
6899 i.rex |= REX_X;
43234a1e
L		 6900 if ((i.index_reg->reg_flags & RegVRex) != 0)
6901 i.vrex |= REX_X;
6c30d220
L		 6902 }
6903
29b0f896
AM		 6904 default_seg = &ds;
6905
6906 if (i.base_reg == 0)
6907 {
6908 i.rm.mode = 0;
6909 if (!i.disp_operands)
9bb129e8 6910 fake_zero_displacement = 1;
29b0f896
AM		 6911 if (i.index_reg == 0)
6912 {
73053c1f
JB		 6913 i386_operand_type newdisp;
6914
6c30d220 6915 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6916 /* Operand is just <disp> */
20f0a1fc 6917 if (flag_code == CODE_64BIT)
29b0f896
AM		 6918 {
6919 /* 64bit mode overwrites the 32bit absolute
6920 addressing by RIP relative addressing and
6921 absolute addressing is encoded by one of the
6922 redundant SIB forms. */
6923 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6924 i.sib.base = NO_BASE_REGISTER;
6925 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6926 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6927 }
fc225355
L		 6928 else if ((flag_code == CODE_16BIT)
6929 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6930 {
6931 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6932 newdisp = disp16;
20f0a1fc
NC		 6933 }
6934 else
6935 {
6936 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6937 newdisp = disp32;
29b0f896 6938 }
73053c1f
JB		 6939 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6940 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6941 }
6c30d220 6942 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6943 {
6c30d220 6944 /* !i.base_reg && i.index_reg */
db51cc60
L		 6945 if (i.index_reg->reg_num == RegEiz
6946 || i.index_reg->reg_num == RegRiz)
6947 i.sib.index = NO_INDEX_REGISTER;
6948 else
6949 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6950 i.sib.base = NO_BASE_REGISTER;
6951 i.sib.scale = i.log2_scale_factor;
6952 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6953 i.types[op].bitfield.disp8 = 0;
6954 i.types[op].bitfield.disp16 = 0;
6955 i.types[op].bitfield.disp64 = 0;
43083a50 6956 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6957 {
6958 /* Must be 32 bit */
6959 i.types[op].bitfield.disp32 = 1;
6960 i.types[op].bitfield.disp32s = 0;
6961 }
29b0f896 6962 else
40fb9820
L		 6963 {
6964 i.types[op].bitfield.disp32 = 0;
6965 i.types[op].bitfield.disp32s = 1;
6966 }
29b0f896 6967 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6968 i.rex |= REX_X;
29b0f896
AM		 6969 }
6970 }
6971 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6972 else if (i.base_reg->reg_num == RegRip ||
6973 i.base_reg->reg_num == RegEip)
29b0f896 6974 {
6c30d220 6975 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6976 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6977 i.types[op].bitfield.disp8 = 0;
6978 i.types[op].bitfield.disp16 = 0;
6979 i.types[op].bitfield.disp32 = 0;
6980 i.types[op].bitfield.disp32s = 1;
6981 i.types[op].bitfield.disp64 = 0;
71903a11 6982 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6983 if (! i.disp_operands)
6984 fake_zero_displacement = 1;
29b0f896 6985 }
dc821c5f 6986 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6987 {
6c30d220 6988 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6989 switch (i.base_reg->reg_num)
6990 {
6991 case 3: /* (%bx) */
6992 if (i.index_reg == 0)
6993 i.rm.regmem = 7;
6994 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6995 i.rm.regmem = i.index_reg->reg_num - 6;
6996 break;
6997 case 5: /* (%bp) */
6998 default_seg = &ss;
6999 if (i.index_reg == 0)
7000 {
7001 i.rm.regmem = 6;
40fb9820 7002 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7003 {
7004 /* fake (%bp) into 0(%bp) */
b5014f7a 7005 i.types[op].bitfield.disp8 = 1;
252b5132 7006 fake_zero_displacement = 1;
29b0f896
AM		 7007 }
7008 }
7009 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7010 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7011 break;
7012 default: /* (%si) -> 4 or (%di) -> 5 */
7013 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7014 }
7015 i.rm.mode = mode_from_disp_size (i.types[op]);
7016 }
7017 else /* i.base_reg and 32/64 bit mode */
7018 {
7019 if (flag_code == CODE_64BIT
40fb9820
L		 7020 && operand_type_check (i.types[op], disp))
7021 {
73053c1f
JB		 7022 i.types[op].bitfield.disp16 = 0;
7023 i.types[op].bitfield.disp64 = 0;
40fb9820 7024 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7025 {
7026 i.types[op].bitfield.disp32 = 0;
7027 i.types[op].bitfield.disp32s = 1;
7028 }
40fb9820 7029 else
73053c1f
JB		 7030 {
7031 i.types[op].bitfield.disp32 = 1;
7032 i.types[op].bitfield.disp32s = 0;
7033 }
40fb9820 7034 }
20f0a1fc 7035
6c30d220
L		 7036 if (!i.tm.opcode_modifier.vecsib)
7037 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7038 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7039 i.rex |= REX_B;
29b0f896
AM		 7040 i.sib.base = i.base_reg->reg_num;
7041 /* x86-64 ignores REX prefix bit here to avoid decoder
7042 complications. */
848930b2
JB		 7043 if (!(i.base_reg->reg_flags & RegRex)
7044 && (i.base_reg->reg_num == EBP_REG_NUM
7045 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7046 default_seg = &ss;
848930b2 7047 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7048 {
848930b2 7049 fake_zero_displacement = 1;
b5014f7a 7050 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7051 }
7052 i.sib.scale = i.log2_scale_factor;
7053 if (i.index_reg == 0)
7054 {
6c30d220 7055 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7056 /* <disp>(%esp) becomes two byte modrm with no index
7057 register. We've already stored the code for esp
7058 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7059 Any base register besides %esp will not use the
7060 extra modrm byte. */
7061 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7062 }
6c30d220 7063 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7064 {
db51cc60
L		 7065 if (i.index_reg->reg_num == RegEiz
7066 || i.index_reg->reg_num == RegRiz)
7067 i.sib.index = NO_INDEX_REGISTER;
7068 else
7069 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7070 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7071 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7072 i.rex |= REX_X;
29b0f896 7073 }
67a4f2b7
AO		 7074
7075 if (i.disp_operands
7076 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7077 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7078 i.rm.mode = 0;
7079 else
a501d77e
L		 7080 {
7081 if (!fake_zero_displacement
7082 && !i.disp_operands
7083 && i.disp_encoding)
7084 {
7085 fake_zero_displacement = 1;
7086 if (i.disp_encoding == disp_encoding_8bit)
7087 i.types[op].bitfield.disp8 = 1;
7088 else
7089 i.types[op].bitfield.disp32 = 1;
7090 }
7091 i.rm.mode = mode_from_disp_size (i.types[op]);
7092 }
29b0f896 7093 }
252b5132 7094
29b0f896
AM		 7095 if (fake_zero_displacement)
7096 {
7097 /* Fakes a zero displacement assuming that i.types[op]
7098 holds the correct displacement size. */
7099 expressionS *exp;
7100
9c2799c2 7101 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7102 exp = &disp_expressions[i.disp_operands++];
7103 i.op[op].disps = exp;
7104 exp->X_op = O_constant;
7105 exp->X_add_number = 0;
7106 exp->X_add_symbol = (symbolS *) 0;
7107 exp->X_op_symbol = (symbolS *) 0;
7108 }
c0f3af97
L		 7109
7110 mem = op;
29b0f896 7111 }
c0f3af97
L		 7112 else
7113 mem = ~0;
252b5132 7114
8c43a48b 7115 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7116 {
7117 if (operand_type_check (i.types[0], imm))
7118 i.vex.register_specifier = NULL;
7119 else
7120 {
7121 /* VEX.vvvv encodes one of the sources when the first
7122 operand is not an immediate. */
1ef99a7b 7123 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7124 i.vex.register_specifier = i.op[0].regs;
7125 else
7126 i.vex.register_specifier = i.op[1].regs;
7127 }
7128
7129 /* Destination is a XMM register encoded in the ModRM.reg
7130 and VEX.R bit. */
7131 i.rm.reg = i.op[2].regs->reg_num;
7132 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7133 i.rex |= REX_R;
7134
7135 /* ModRM.rm and VEX.B encodes the other source. */
7136 if (!i.mem_operands)
7137 {
7138 i.rm.mode = 3;
7139
1ef99a7b 7140 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7141 i.rm.regmem = i.op[1].regs->reg_num;
7142 else
7143 i.rm.regmem = i.op[0].regs->reg_num;
7144
7145 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7146 i.rex |= REX_B;
7147 }
7148 }
2426c15f 7149 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7150 {
7151 i.vex.register_specifier = i.op[2].regs;
7152 if (!i.mem_operands)
7153 {
7154 i.rm.mode = 3;
7155 i.rm.regmem = i.op[1].regs->reg_num;
7156 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7157 i.rex |= REX_B;
7158 }
7159 }
29b0f896
AM		 7160 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7161 (if any) based on i.tm.extension_opcode. Again, we must be
7162 careful to make sure that segment/control/debug/test/MMX
7163 registers are coded into the i.rm.reg field. */
f88c9eb0 7164 else if (i.reg_operands)
29b0f896 7165 {
99018f42 7166 unsigned int op;
7ab9ffdd
L		 7167 unsigned int vex_reg = ~0;
7168
7169 for (op = 0; op < i.operands; op++)
dc821c5f 7170 if (i.types[op].bitfield.reg
7ab9ffdd 7171 || i.types[op].bitfield.regmmx
1b54b8d7 7172 || i.types[op].bitfield.regsimd
7e8b059b 7173 || i.types[op].bitfield.regbnd
43234a1e 7174 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7175 || i.types[op].bitfield.sreg2
7176 || i.types[op].bitfield.sreg3
7177 || i.types[op].bitfield.control
7178 || i.types[op].bitfield.debug
7179 || i.types[op].bitfield.test)
7180 break;
c0209578 7181
7ab9ffdd
L		 7182 if (vex_3_sources)
7183 op = dest;
2426c15f 7184 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7185 {
7186 /* For instructions with VexNDS, the register-only
7187 source operand is encoded in VEX prefix. */
7188 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7189
7ab9ffdd 7190 if (op > mem)
c0f3af97 7191 {
7ab9ffdd
L		 7192 vex_reg = op++;
7193 gas_assert (op < i.operands);
c0f3af97
L		 7194 }
7195 else
c0f3af97 7196 {
f12dc422
L		 7197 /* Check register-only source operand when two source
7198 operands are swapped. */
7199 if (!i.tm.operand_types[op].bitfield.baseindex
7200 && i.tm.operand_types[op + 1].bitfield.baseindex)
7201 {
7202 vex_reg = op;
7203 op += 2;
7204 gas_assert (mem == (vex_reg + 1)
7205 && op < i.operands);
7206 }
7207 else
7208 {
7209 vex_reg = op + 1;
7210 gas_assert (vex_reg < i.operands);
7211 }
c0f3af97 7212 }
7ab9ffdd 7213 }
2426c15f 7214 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7215 {
f12dc422 7216 /* For instructions with VexNDD, the register destination
7ab9ffdd 7217 is encoded in VEX prefix. */
f12dc422
L		 7218 if (i.mem_operands == 0)
7219 {
7220 /* There is no memory operand. */
7221 gas_assert ((op + 2) == i.operands);
7222 vex_reg = op + 1;
7223 }
7224 else
8d63c93e 7225 {
ed438a93
JB		 7226 /* There are only 2 non-immediate operands. */
7227 gas_assert (op < i.imm_operands + 2
7228 && i.operands == i.imm_operands + 2);
7229 vex_reg = i.imm_operands + 1;
f12dc422 7230 }
7ab9ffdd
L		 7231 }
7232 else
7233 gas_assert (op < i.operands);
99018f42 7234
7ab9ffdd
L		 7235 if (vex_reg != (unsigned int) ~0)
7236 {
f12dc422 7237 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7238
dc821c5f
JB		 7239 if ((!type->bitfield.reg
7240 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7241 && !type->bitfield.regsimd
43234a1e 7242 && !operand_type_equal (type, &regmask))
7ab9ffdd 7243 abort ();
f88c9eb0 7244
7ab9ffdd
L		 7245 i.vex.register_specifier = i.op[vex_reg].regs;
7246 }
7247
1b9f0c97
L		 7248 /* Don't set OP operand twice. */
7249 if (vex_reg != op)
7ab9ffdd 7250 {
1b9f0c97
L		 7251 /* If there is an extension opcode to put here, the
7252 register number must be put into the regmem field. */
7253 if (i.tm.extension_opcode != None)
7254 {
7255 i.rm.regmem = i.op[op].regs->reg_num;
7256 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7257 i.rex |= REX_B;
43234a1e
L		 7258 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7259 i.vrex |= REX_B;
1b9f0c97
L		 7260 }
7261 else
7262 {
7263 i.rm.reg = i.op[op].regs->reg_num;
7264 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7265 i.rex |= REX_R;
43234a1e
L		 7266 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7267 i.vrex |= REX_R;
1b9f0c97 7268 }
7ab9ffdd 7269 }
252b5132 7270
29b0f896
AM		 7271 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7272 must set it to 3 to indicate this is a register operand
7273 in the regmem field. */
7274 if (!i.mem_operands)
7275 i.rm.mode = 3;
7276 }
252b5132 7277
29b0f896 7278 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7279 if (i.tm.extension_opcode != None)
29b0f896
AM		 7280 i.rm.reg = i.tm.extension_opcode;
7281 }
7282 return default_seg;
7283}
252b5132 7284
29b0f896 7285static void
e3bb37b5 7286output_branch (void)
29b0f896
AM		 7287{
7288 char *p;
f8a5c266 7289 int size;
29b0f896
AM		 7290 int code16;
7291 int prefix;
7292 relax_substateT subtype;
7293 symbolS *sym;
7294 offsetT off;
7295
f8a5c266 7296 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7297 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7298
7299 prefix = 0;
7300 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7301 {
29b0f896
AM		 7302 prefix = 1;
7303 i.prefixes -= 1;
7304 code16 ^= CODE16;
252b5132 7305 }
29b0f896
AM		 7306 /* Pentium4 branch hints. */
7307 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7308 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7309 {
29b0f896
AM		 7310 prefix++;
7311 i.prefixes--;
7312 }
7313 if (i.prefix[REX_PREFIX] != 0)
7314 {
7315 prefix++;
7316 i.prefixes--;
2f66722d
AM		 7317 }
7318
7e8b059b
L		 7319 /* BND prefixed jump. */
7320 if (i.prefix[BND_PREFIX] != 0)
7321 {
7322 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7323 i.prefixes -= 1;
7324 }
7325
29b0f896
AM		 7326 if (i.prefixes != 0 && !intel_syntax)
7327 as_warn (_("skipping prefixes on this instruction"));
7328
7329 /* It's always a symbol; End frag & setup for relax.
7330 Make sure there is enough room in this frag for the largest
7331 instruction we may generate in md_convert_frag. This is 2
7332 bytes for the opcode and room for the prefix and largest
7333 displacement. */
7334 frag_grow (prefix + 2 + 4);
7335 /* Prefix and 1 opcode byte go in fr_fix. */
7336 p = frag_more (prefix + 1);
7337 if (i.prefix[DATA_PREFIX] != 0)
7338 *p++ = DATA_PREFIX_OPCODE;
7339 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7340 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7341 *p++ = i.prefix[SEG_PREFIX];
7342 if (i.prefix[REX_PREFIX] != 0)
7343 *p++ = i.prefix[REX_PREFIX];
7344 *p = i.tm.base_opcode;
7345
7346 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7347 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7348 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7349 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7350 else
f8a5c266 7351 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7352 subtype |= code16;
3e73aa7c 7353
29b0f896
AM		 7354 sym = i.op[0].disps->X_add_symbol;
7355 off = i.op[0].disps->X_add_number;
3e73aa7c 7356
29b0f896
AM		 7357 if (i.op[0].disps->X_op != O_constant
7358 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7359 {
29b0f896
AM		 7360 /* Handle complex expressions. */
7361 sym = make_expr_symbol (i.op[0].disps);
7362 off = 0;
7363 }
3e73aa7c 7364
29b0f896
AM		 7365 /* 1 possible extra opcode + 4 byte displacement go in var part.
7366 Pass reloc in fr_var. */
d258b828 7367 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7368}
3e73aa7c 7369
bd7ab16b
L		 7370#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7371/* Return TRUE iff PLT32 relocation should be used for branching to
7372 symbol S. */
7373
7374static bfd_boolean
7375need_plt32_p (symbolS *s)
7376{
7377 /* PLT32 relocation is ELF only. */
7378 if (!IS_ELF)
7379 return FALSE;
7380
7381 /* Since there is no need to prepare for PLT branch on x86-64, we
7382 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7383 be used as a marker for 32-bit PC-relative branches. */
7384 if (!object_64bit)
7385 return FALSE;
7386
7387 /* Weak or undefined symbol need PLT32 relocation. */
7388 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7389 return TRUE;
7390
7391 /* Non-global symbol doesn't need PLT32 relocation. */
7392 if (! S_IS_EXTERNAL (s))
7393 return FALSE;
7394
7395 /* Other global symbols need PLT32 relocation. NB: Symbol with
7396 non-default visibilities are treated as normal global symbol
7397 so that PLT32 relocation can be used as a marker for 32-bit
7398 PC-relative branches. It is useful for linker relaxation. */
7399 return TRUE;
7400}
7401#endif
7402
29b0f896 7403static void
e3bb37b5 7404output_jump (void)
29b0f896
AM		 7405{
7406 char *p;
7407 int size;
3e02c1cc 7408 fixS *fixP;
bd7ab16b 7409 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7410
40fb9820 7411 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7412 {
7413 /* This is a loop or jecxz type instruction. */
7414 size = 1;
7415 if (i.prefix[ADDR_PREFIX] != 0)
7416 {
7417 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7418 i.prefixes -= 1;
7419 }
7420 /* Pentium4 branch hints. */
7421 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7422 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7423 {
7424 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7425 i.prefixes--;
3e73aa7c
JH		 7426 }
7427 }
29b0f896
AM		 7428 else
7429 {
7430 int code16;
3e73aa7c 7431
29b0f896
AM		 7432 code16 = 0;
7433 if (flag_code == CODE_16BIT)
7434 code16 = CODE16;
3e73aa7c 7435
29b0f896
AM		 7436 if (i.prefix[DATA_PREFIX] != 0)
7437 {
7438 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7439 i.prefixes -= 1;
7440 code16 ^= CODE16;
7441 }
252b5132 7442
29b0f896
AM		 7443 size = 4;
7444 if (code16)
7445 size = 2;
7446 }
9fcc94b6 7447
29b0f896
AM		 7448 if (i.prefix[REX_PREFIX] != 0)
7449 {
7450 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7451 i.prefixes -= 1;
7452 }
252b5132 7453
7e8b059b
L		 7454 /* BND prefixed jump. */
7455 if (i.prefix[BND_PREFIX] != 0)
7456 {
7457 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7458 i.prefixes -= 1;
7459 }
7460
29b0f896
AM		 7461 if (i.prefixes != 0 && !intel_syntax)
7462 as_warn (_("skipping prefixes on this instruction"));
e0890092 7463
42164a71
L		 7464 p = frag_more (i.tm.opcode_length + size);
7465 switch (i.tm.opcode_length)
7466 {
7467 case 2:
7468 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7469 /* Fall through. */
42164a71
L		 7470 case 1:
7471 *p++ = i.tm.base_opcode;
7472 break;
7473 default:
7474 abort ();
7475 }
e0890092 7476
bd7ab16b
L		 7477#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7478 if (size == 4
7479 && jump_reloc == NO_RELOC
7480 && need_plt32_p (i.op[0].disps->X_add_symbol))
7481 jump_reloc = BFD_RELOC_X86_64_PLT32;
7482#endif
7483
7484 jump_reloc = reloc (size, 1, 1, jump_reloc);
7485
3e02c1cc 7486 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7487 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7488
7489 /* All jumps handled here are signed, but don't use a signed limit
7490 check for 32 and 16 bit jumps as we want to allow wrap around at
7491 4G and 64k respectively. */
7492 if (size == 1)
7493 fixP->fx_signed = 1;
29b0f896 7494}
e0890092 7495
29b0f896 7496static void
e3bb37b5 7497output_interseg_jump (void)
29b0f896
AM		 7498{
7499 char *p;
7500 int size;
7501 int prefix;
7502 int code16;
252b5132 7503
29b0f896
AM		 7504 code16 = 0;
7505 if (flag_code == CODE_16BIT)
7506 code16 = CODE16;
a217f122 7507
29b0f896
AM		 7508 prefix = 0;
7509 if (i.prefix[DATA_PREFIX] != 0)
7510 {
7511 prefix = 1;
7512 i.prefixes -= 1;
7513 code16 ^= CODE16;
7514 }
7515 if (i.prefix[REX_PREFIX] != 0)
7516 {
7517 prefix++;
7518 i.prefixes -= 1;
7519 }
252b5132 7520
29b0f896
AM		 7521 size = 4;
7522 if (code16)
7523 size = 2;
252b5132 7524
29b0f896
AM		 7525 if (i.prefixes != 0 && !intel_syntax)
7526 as_warn (_("skipping prefixes on this instruction"));
252b5132 7527
29b0f896
AM		 7528 /* 1 opcode; 2 segment; offset */
7529 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7530
29b0f896
AM		 7531 if (i.prefix[DATA_PREFIX] != 0)
7532 *p++ = DATA_PREFIX_OPCODE;
252b5132 7533
29b0f896
AM		 7534 if (i.prefix[REX_PREFIX] != 0)
7535 *p++ = i.prefix[REX_PREFIX];
252b5132 7536
29b0f896
AM		 7537 *p++ = i.tm.base_opcode;
7538 if (i.op[1].imms->X_op == O_constant)
7539 {
7540 offsetT n = i.op[1].imms->X_add_number;
252b5132 7541
29b0f896
AM		 7542 if (size == 2
7543 && !fits_in_unsigned_word (n)
7544 && !fits_in_signed_word (n))
7545 {
7546 as_bad (_("16-bit jump out of range"));
7547 return;
7548 }
7549 md_number_to_chars (p, n, size);
7550 }
7551 else
7552 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7553 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7554 if (i.op[0].imms->X_op != O_constant)
7555 as_bad (_("can't handle non absolute segment in `%s'"),
7556 i.tm.name);
7557 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7558}
a217f122 7559
29b0f896 7560static void
e3bb37b5 7561output_insn (void)
29b0f896 7562{
2bbd9c25
JJ		 7563 fragS *insn_start_frag;
7564 offsetT insn_start_off;
7565
29b0f896
AM		 7566 /* Tie dwarf2 debug info to the address at the start of the insn.
7567 We can't do this after the insn has been output as the current
7568 frag may have been closed off. eg. by frag_var. */
7569 dwarf2_emit_insn (0);
7570
2bbd9c25
JJ		 7571 insn_start_frag = frag_now;
7572 insn_start_off = frag_now_fix ();
7573
29b0f896 7574 /* Output jumps. */
40fb9820 7575 if (i.tm.opcode_modifier.jump)
29b0f896 7576 output_branch ();
40fb9820
L		 7577 else if (i.tm.opcode_modifier.jumpbyte
7578 || i.tm.opcode_modifier.jumpdword)
29b0f896 7579 output_jump ();
40fb9820 7580 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7581 output_interseg_jump ();
7582 else
7583 {
7584 /* Output normal instructions here. */
7585 char *p;
7586 unsigned char *q;
47465058 7587 unsigned int j;
331d2d0d 7588 unsigned int prefix;
4dffcebc 7589
e4e00185
AS		 7590 if (avoid_fence
7591 && i.tm.base_opcode == 0xfae
7592 && i.operands == 1
7593 && i.imm_operands == 1
7594 && (i.op[0].imms->X_add_number == 0xe8
7595 || i.op[0].imms->X_add_number == 0xf0
7596 || i.op[0].imms->X_add_number == 0xf8))
7597 {
7598 /* Encode lfence, mfence, and sfence as
7599 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7600 offsetT val = 0x240483f0ULL;
7601 p = frag_more (5);
7602 md_number_to_chars (p, val, 5);
7603 return;
7604 }
7605
d022bddd
IT		 7606 /* Some processors fail on LOCK prefix. This options makes
7607 assembler ignore LOCK prefix and serves as a workaround. */
7608 if (omit_lock_prefix)
7609 {
7610 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7611 return;
7612 i.prefix[LOCK_PREFIX] = 0;
7613 }
7614
43234a1e
L		 7615 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7616 don't need the explicit prefix. */
7617 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7618 {
c0f3af97 7619 switch (i.tm.opcode_length)
bc4bd9ab 7620 {
c0f3af97
L		 7621 case 3:
7622 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7623 {
c0f3af97
L		 7624 prefix = (i.tm.base_opcode >> 24) & 0xff;
7625 goto check_prefix;
7626 }
7627 break;
7628 case 2:
7629 if ((i.tm.base_opcode & 0xff0000) != 0)
7630 {
7631 prefix = (i.tm.base_opcode >> 16) & 0xff;
7632 if (i.tm.cpu_flags.bitfield.cpupadlock)
7633 {
4dffcebc 7634check_prefix:
c0f3af97 7635 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7636 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7637 != REPE_PREFIX_OPCODE))
7638 add_prefix (prefix);
7639 }
7640 else
4dffcebc
L		 7641 add_prefix (prefix);
7642 }
c0f3af97
L		 7643 break;
7644 case 1:
7645 break;
390c91cf
L		 7646 case 0:
7647 /* Check for pseudo prefixes. */
7648 as_bad_where (insn_start_frag->fr_file,
7649 insn_start_frag->fr_line,
7650 _("pseudo prefix without instruction"));
7651 return;
c0f3af97
L		 7652 default:
7653 abort ();
bc4bd9ab 7654 }
c0f3af97 7655
6d19a37a 7656#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7657 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7658 R_X86_64_GOTTPOFF relocation so that linker can safely
7659 perform IE->LE optimization. */
7660 if (x86_elf_abi == X86_64_X32_ABI
7661 && i.operands == 2
7662 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7663 && i.prefix[REX_PREFIX] == 0)
7664 add_prefix (REX_OPCODE);
6d19a37a 7665#endif
cf61b747 7666
c0f3af97
L		 7667 /* The prefix bytes. */
7668 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7669 if (*q)
7670 FRAG_APPEND_1_CHAR (*q);
0f10071e 7671 }
ae5c1c7b 7672 else
c0f3af97
L		 7673 {
7674 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7675 if (*q)
7676 switch (j)
7677 {
7678 case REX_PREFIX:
7679 /* REX byte is encoded in VEX prefix. */
7680 break;
7681 case SEG_PREFIX:
7682 case ADDR_PREFIX:
7683 FRAG_APPEND_1_CHAR (*q);
7684 break;
7685 default:
7686 /* There should be no other prefixes for instructions
7687 with VEX prefix. */
7688 abort ();
7689 }
7690
43234a1e
L		 7691 /* For EVEX instructions i.vrex should become 0 after
7692 build_evex_prefix. For VEX instructions upper 16 registers
7693 aren't available, so VREX should be 0. */
7694 if (i.vrex)
7695 abort ();
c0f3af97
L		 7696 /* Now the VEX prefix. */
7697 p = frag_more (i.vex.length);
7698 for (j = 0; j < i.vex.length; j++)
7699 p[j] = i.vex.bytes[j];
7700 }
252b5132 7701
29b0f896 7702 /* Now the opcode; be careful about word order here! */
4dffcebc 7703 if (i.tm.opcode_length == 1)
29b0f896
AM		 7704 {
7705 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7706 }
7707 else
7708 {
4dffcebc 7709 switch (i.tm.opcode_length)
331d2d0d 7710 {
43234a1e
L		 7711 case 4:
7712 p = frag_more (4);
7713 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7714 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7715 break;
4dffcebc 7716 case 3:
331d2d0d
L		 7717 p = frag_more (3);
7718 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7719 break;
7720 case 2:
7721 p = frag_more (2);
7722 break;
7723 default:
7724 abort ();
7725 break;
331d2d0d 7726 }
0f10071e 7727
29b0f896
AM		 7728 /* Put out high byte first: can't use md_number_to_chars! */
7729 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7730 *p = i.tm.base_opcode & 0xff;
7731 }
3e73aa7c 7732
29b0f896 7733 /* Now the modrm byte and sib byte (if present). */
40fb9820 7734 if (i.tm.opcode_modifier.modrm)
29b0f896 7735 {
4a3523fa
L		 7736 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7737 | i.rm.reg << 3
7738 | i.rm.mode << 6));
29b0f896
AM		 7739 /* If i.rm.regmem == ESP (4)
7740 && i.rm.mode != (Register mode)
7741 && not 16 bit
7742 ==> need second modrm byte. */
7743 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7744 && i.rm.mode != 3
dc821c5f 7745 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7746 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7747 | i.sib.index << 3
7748 | i.sib.scale << 6));
29b0f896 7749 }
3e73aa7c 7750
29b0f896 7751 if (i.disp_operands)
2bbd9c25 7752 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7753
29b0f896 7754 if (i.imm_operands)
2bbd9c25 7755 output_imm (insn_start_frag, insn_start_off);
29b0f896 7756 }
252b5132 7757
29b0f896
AM		 7758#ifdef DEBUG386
7759 if (flag_debug)
7760 {
7b81dfbb 7761 pi ("" /*line*/, &i);
29b0f896
AM		 7762 }
7763#endif /* DEBUG386 */
7764}
252b5132 7765
e205caa7
L		 7766/* Return the size of the displacement operand N. */
7767
7768static int
7769disp_size (unsigned int n)
7770{
7771 int size = 4;
43234a1e 7772
b5014f7a 7773 if (i.types[n].bitfield.disp64)
40fb9820
L		 7774 size = 8;
7775 else if (i.types[n].bitfield.disp8)
7776 size = 1;
7777 else if (i.types[n].bitfield.disp16)
7778 size = 2;
e205caa7
L		 7779 return size;
7780}
7781
7782/* Return the size of the immediate operand N. */
7783
7784static int
7785imm_size (unsigned int n)
7786{
7787 int size = 4;
40fb9820
L		 7788 if (i.types[n].bitfield.imm64)
7789 size = 8;
7790 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7791 size = 1;
7792 else if (i.types[n].bitfield.imm16)
7793 size = 2;
e205caa7
L		 7794 return size;
7795}
7796
29b0f896 7797static void
64e74474 7798output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7799{
7800 char *p;
7801 unsigned int n;
252b5132 7802
29b0f896
AM		 7803 for (n = 0; n < i.operands; n++)
7804 {
b5014f7a 7805 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7806 {
7807 if (i.op[n].disps->X_op == O_constant)
7808 {
e205caa7 7809 int size = disp_size (n);
43234a1e 7810 offsetT val = i.op[n].disps->X_add_number;
252b5132 7811
b5014f7a 7812 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7813 p = frag_more (size);
7814 md_number_to_chars (p, val, size);
7815 }
7816 else
7817 {
f86103b7 7818 enum bfd_reloc_code_real reloc_type;
e205caa7 7819 int size = disp_size (n);
40fb9820 7820 int sign = i.types[n].bitfield.disp32s;
29b0f896 7821 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7822 fixS *fixP;
29b0f896 7823
e205caa7 7824 /* We can't have 8 bit displacement here. */
9c2799c2 7825 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7826
29b0f896
AM		 7827 /* The PC relative address is computed relative
7828 to the instruction boundary, so in case immediate
7829 fields follows, we need to adjust the value. */
7830 if (pcrel && i.imm_operands)
7831 {
29b0f896 7832 unsigned int n1;
e205caa7 7833 int sz = 0;
252b5132 7834
29b0f896 7835 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7836 if (operand_type_check (i.types[n1], imm))
252b5132 7837 {
e205caa7
L		 7838 /* Only one immediate is allowed for PC
7839 relative address. */
9c2799c2 7840 gas_assert (sz == 0);
e205caa7
L		 7841 sz = imm_size (n1);
7842 i.op[n].disps->X_add_number -= sz;
252b5132 7843 }
29b0f896 7844 /* We should find the immediate. */
9c2799c2 7845 gas_assert (sz != 0);
29b0f896 7846 }
520dc8e8 7847
29b0f896 7848 p = frag_more (size);
d258b828 7849 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7850 if (GOT_symbol
2bbd9c25 7851 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7852 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7853 || reloc_type == BFD_RELOC_X86_64_32S
7854 || (reloc_type == BFD_RELOC_64
7855 && object_64bit))
d6ab8113
JB		 7856 && (i.op[n].disps->X_op == O_symbol
7857 || (i.op[n].disps->X_op == O_add
7858 && ((symbol_get_value_expression
7859 (i.op[n].disps->X_op_symbol)->X_op)
7860 == O_subtract))))
7861 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7862 {
7863 offsetT add;
7864
7865 if (insn_start_frag == frag_now)
7866 add = (p - frag_now->fr_literal) - insn_start_off;
7867 else
7868 {
7869 fragS *fr;
7870
7871 add = insn_start_frag->fr_fix - insn_start_off;
7872 for (fr = insn_start_frag->fr_next;
7873 fr && fr != frag_now; fr = fr->fr_next)
7874 add += fr->fr_fix;
7875 add += p - frag_now->fr_literal;
7876 }
7877
4fa24527 7878 if (!object_64bit)
7b81dfbb
AJ		 7879 {
7880 reloc_type = BFD_RELOC_386_GOTPC;
7881 i.op[n].imms->X_add_number += add;
7882 }
7883 else if (reloc_type == BFD_RELOC_64)
7884 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7885 else
7b81dfbb
AJ		 7886 /* Don't do the adjustment for x86-64, as there
7887 the pcrel addressing is relative to the _next_
7888 insn, and that is taken care of in other code. */
d6ab8113 7889 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7890 }
02a86693
L		 7891 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7892 size, i.op[n].disps, pcrel,
7893 reloc_type);
7894 /* Check for "call/jmp *mem", "mov mem, %reg",
7895 "test %reg, mem" and "binop mem, %reg" where binop
7896 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7897 instructions. Always generate R_386_GOT32X for
7898 "sym*GOT" operand in 32-bit mode. */
7899 if ((generate_relax_relocations
7900 || (!object_64bit
7901 && i.rm.mode == 0
7902 && i.rm.regmem == 5))
7903 && (i.rm.mode == 2
7904 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7905 && ((i.operands == 1
7906 && i.tm.base_opcode == 0xff
7907 && (i.rm.reg == 2 || i.rm.reg == 4))
7908 || (i.operands == 2
7909 && (i.tm.base_opcode == 0x8b
7910 || i.tm.base_opcode == 0x85
7911 || (i.tm.base_opcode & 0xc7) == 0x03))))
7912 {
7913 if (object_64bit)
7914 {
7915 fixP->fx_tcbit = i.rex != 0;
7916 if (i.base_reg
7917 && (i.base_reg->reg_num == RegRip
7918 || i.base_reg->reg_num == RegEip))
7919 fixP->fx_tcbit2 = 1;
7920 }
7921 else
7922 fixP->fx_tcbit2 = 1;
7923 }
29b0f896
AM		 7924 }
7925 }
7926 }
7927}
252b5132 7928
29b0f896 7929static void
64e74474 7930output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7931{
7932 char *p;
7933 unsigned int n;
252b5132 7934
29b0f896
AM		 7935 for (n = 0; n < i.operands; n++)
7936 {
43234a1e
L		 7937 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7938 if (i.rounding && (int) n == i.rounding->operand)
7939 continue;
7940
40fb9820 7941 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7942 {
7943 if (i.op[n].imms->X_op == O_constant)
7944 {
e205caa7 7945 int size = imm_size (n);
29b0f896 7946 offsetT val;
b4cac588 7947
29b0f896
AM		 7948 val = offset_in_range (i.op[n].imms->X_add_number,
7949 size);
7950 p = frag_more (size);
7951 md_number_to_chars (p, val, size);
7952 }
7953 else
7954 {
7955 /* Not absolute_section.
7956 Need a 32-bit fixup (don't support 8bit
7957 non-absolute imms). Try to support other
7958 sizes ... */
f86103b7 7959 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7960 int size = imm_size (n);
7961 int sign;
29b0f896 7962
40fb9820 7963 if (i.types[n].bitfield.imm32s
a7d61044 7964 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7965 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7966 sign = 1;
e205caa7
L		 7967 else
7968 sign = 0;
520dc8e8 7969
29b0f896 7970 p = frag_more (size);
d258b828 7971 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7972
2bbd9c25
JJ		 7973 /* This is tough to explain. We end up with this one if we
7974 * have operands that look like
7975 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7976 * obtain the absolute address of the GOT, and it is strongly
7977 * preferable from a performance point of view to avoid using
7978 * a runtime relocation for this. The actual sequence of
7979 * instructions often look something like:
7980 *
7981 * call .L66
7982 * .L66:
7983 * popl %ebx
7984 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7985 *
7986 * The call and pop essentially return the absolute address
7987 * of the label .L66 and store it in %ebx. The linker itself
7988 * will ultimately change the first operand of the addl so
7989 * that %ebx points to the GOT, but to keep things simple, the
7990 * .o file must have this operand set so that it generates not
7991 * the absolute address of .L66, but the absolute address of
7992 * itself. This allows the linker itself simply treat a GOTPC
7993 * relocation as asking for a pcrel offset to the GOT to be
7994 * added in, and the addend of the relocation is stored in the
7995 * operand field for the instruction itself.
7996 *
7997 * Our job here is to fix the operand so that it would add
7998 * the correct offset so that %ebx would point to itself. The
7999 * thing that is tricky is that .-.L66 will point to the
8000 * beginning of the instruction, so we need to further modify
8001 * the operand so that it will point to itself. There are
8002 * other cases where you have something like:
8003 *
8004 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8005 *
8006 * and here no correction would be required. Internally in
8007 * the assembler we treat operands of this form as not being
8008 * pcrel since the '.' is explicitly mentioned, and I wonder
8009 * whether it would simplify matters to do it this way. Who
8010 * knows. In earlier versions of the PIC patches, the
8011 * pcrel_adjust field was used to store the correction, but
8012 * since the expression is not pcrel, I felt it would be
8013 * confusing to do it this way. */
8014
d6ab8113 8015 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8016 || reloc_type == BFD_RELOC_X86_64_32S
8017 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8018 && GOT_symbol
8019 && GOT_symbol == i.op[n].imms->X_add_symbol
8020 && (i.op[n].imms->X_op == O_symbol
8021 || (i.op[n].imms->X_op == O_add
8022 && ((symbol_get_value_expression
8023 (i.op[n].imms->X_op_symbol)->X_op)
8024 == O_subtract))))
8025 {
2bbd9c25
JJ		 8026 offsetT add;
8027
8028 if (insn_start_frag == frag_now)
8029 add = (p - frag_now->fr_literal) - insn_start_off;
8030 else
8031 {
8032 fragS *fr;
8033
8034 add = insn_start_frag->fr_fix - insn_start_off;
8035 for (fr = insn_start_frag->fr_next;
8036 fr && fr != frag_now; fr = fr->fr_next)
8037 add += fr->fr_fix;
8038 add += p - frag_now->fr_literal;
8039 }
8040
4fa24527 8041 if (!object_64bit)
d6ab8113 8042 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8043 else if (size == 4)
d6ab8113 8044 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8045 else if (size == 8)
8046 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8047 i.op[n].imms->X_add_number += add;
29b0f896 8048 }
29b0f896
AM		 8049 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8050 i.op[n].imms, 0, reloc_type);
8051 }
8052 }
8053 }
252b5132
RH		 8054}
8055\f
d182319b
JB		 8056/* x86_cons_fix_new is called via the expression parsing code when a
8057 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8058static int cons_sign = -1;
8059
8060void
e3bb37b5 8061x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8062 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8063{
d258b828 8064 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8065
8066#ifdef TE_PE
8067 if (exp->X_op == O_secrel)
8068 {
8069 exp->X_op = O_symbol;
8070 r = BFD_RELOC_32_SECREL;
8071 }
8072#endif
8073
8074 fix_new_exp (frag, off, len, exp, 0, r);
8075}
8076
357d1bd8
L		 8077/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8078 purpose of the `.dc.a' internal pseudo-op. */
8079
8080int
8081x86_address_bytes (void)
8082{
8083 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8084 return 4;
8085 return stdoutput->arch_info->bits_per_address / 8;
8086}
8087
d382c579
TG		 8088#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8089 || defined (LEX_AT)
d258b828 8090# define lex_got(reloc, adjust, types) NULL
718ddfc0 8091#else
f3c180ae
AM		 8092/* Parse operands of the form
8093 <symbol>@GOTOFF+<nnn>
8094 and similar .plt or .got references.
8095
8096 If we find one, set up the correct relocation in RELOC and copy the
8097 input string, minus the `@GOTOFF' into a malloc'd buffer for
8098 parsing by the calling routine. Return this buffer, and if ADJUST
8099 is non-null set it to the length of the string we removed from the
8100 input line. Otherwise return NULL. */
8101static char *
91d6fa6a 8102lex_got (enum bfd_reloc_code_real *rel,
64e74474 8103 int *adjust,
d258b828 8104 i386_operand_type *types)
f3c180ae 8105{
7b81dfbb
AJ		 8106 /* Some of the relocations depend on the size of what field is to
8107 be relocated. But in our callers i386_immediate and i386_displacement
8108 we don't yet know the operand size (this will be set by insn
8109 matching). Hence we record the word32 relocation here,
8110 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8111 static const struct {
8112 const char *str;
cff8d58a 8113 int len;
4fa24527 8114 const enum bfd_reloc_code_real rel[2];
40fb9820 8115 const i386_operand_type types64;
f3c180ae 8116 } gotrel[] = {
8ce3d284 8117#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8118 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8119 BFD_RELOC_SIZE32 },
8120 OPERAND_TYPE_IMM32_64 },
8ce3d284 8121#endif
cff8d58a
L		 8122 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8123 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8124 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8125 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8126 BFD_RELOC_X86_64_PLT32 },
40fb9820 8127 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8128 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8129 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8130 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8131 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8132 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8133 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8134 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8135 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8136 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8137 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8138 BFD_RELOC_X86_64_TLSGD },
40fb9820 8139 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8140 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8141 _dummy_first_bfd_reloc_code_real },
40fb9820 8142 OPERAND_TYPE_NONE },
cff8d58a
L		 8143 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8144 BFD_RELOC_X86_64_TLSLD },
40fb9820 8145 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8146 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8147 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8148 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8149 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8150 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8151 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8152 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8153 _dummy_first_bfd_reloc_code_real },
40fb9820 8154 OPERAND_TYPE_NONE },
cff8d58a
L		 8155 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8156 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8157 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8158 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8159 _dummy_first_bfd_reloc_code_real },
40fb9820 8160 OPERAND_TYPE_NONE },
cff8d58a
L		 8161 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8162 _dummy_first_bfd_reloc_code_real },
40fb9820 8163 OPERAND_TYPE_NONE },
cff8d58a
L		 8164 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8165 BFD_RELOC_X86_64_GOT32 },
40fb9820 8166 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8167 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8168 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8169 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8170 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8171 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8172 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8173 };
8174 char *cp;
8175 unsigned int j;
8176
d382c579 8177#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8178 if (!IS_ELF)
8179 return NULL;
d382c579 8180#endif
718ddfc0 8181
f3c180ae 8182 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8183 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8184 return NULL;
8185
47465058 8186 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8187 {
cff8d58a 8188 int len = gotrel[j].len;
28f81592 8189 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8190 {
4fa24527 8191 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8192 {
28f81592
AM		 8193 int first, second;
8194 char *tmpbuf, *past_reloc;
f3c180ae 8195
91d6fa6a 8196 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8197
3956db08
JB		 8198 if (types)
8199 {
8200 if (flag_code != CODE_64BIT)
40fb9820
L		 8201 {
8202 types->bitfield.imm32 = 1;
8203 types->bitfield.disp32 = 1;
8204 }
3956db08
JB		 8205 else
8206 *types = gotrel[j].types64;
8207 }
8208
8fd4256d 8209 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8210 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8211
28f81592 8212 /* The length of the first part of our input line. */
f3c180ae 8213 first = cp - input_line_pointer;
28f81592
AM		 8214
8215 /* The second part goes from after the reloc token until
67c11a9b 8216 (and including) an end_of_line char or comma. */
28f81592 8217 past_reloc = cp + 1 + len;
67c11a9b
AM		 8218 cp = past_reloc;
8219 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8220 ++cp;
8221 second = cp + 1 - past_reloc;
28f81592
AM		 8222
8223 /* Allocate and copy string. The trailing NUL shouldn't
8224 be necessary, but be safe. */
add39d23 8225 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8226 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8227 if (second != 0 && *past_reloc != ' ')
8228 /* Replace the relocation token with ' ', so that
8229 errors like foo@GOTOFF1 will be detected. */
8230 tmpbuf[first++] = ' ';
af89796a
L		 8231 else
8232 /* Increment length by 1 if the relocation token is
8233 removed. */
8234 len++;
8235 if (adjust)
8236 *adjust = len;
0787a12d
AM		 8237 memcpy (tmpbuf + first, past_reloc, second);
8238 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8239 return tmpbuf;
8240 }
8241
4fa24527
JB		 8242 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8243 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8244 return NULL;
8245 }
8246 }
8247
8248 /* Might be a symbol version string. Don't as_bad here. */
8249 return NULL;
8250}
4e4f7c87 8251#endif
f3c180ae 8252
a988325c
NC		 8253#ifdef TE_PE
8254#ifdef lex_got
8255#undef lex_got
8256#endif
8257/* Parse operands of the form
8258 <symbol>@SECREL32+<nnn>
8259
8260 If we find one, set up the correct relocation in RELOC and copy the
8261 input string, minus the `@SECREL32' into a malloc'd buffer for
8262 parsing by the calling routine. Return this buffer, and if ADJUST
8263 is non-null set it to the length of the string we removed from the
34bca508
L		 8264 input line. Otherwise return NULL.
8265
a988325c
NC		 8266 This function is copied from the ELF version above adjusted for PE targets. */
8267
8268static char *
8269lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8270 int *adjust ATTRIBUTE_UNUSED,
d258b828 8271 i386_operand_type *types)
a988325c
NC		 8272{
8273 static const struct
8274 {
8275 const char *str;
8276 int len;
8277 const enum bfd_reloc_code_real rel[2];
8278 const i386_operand_type types64;
8279 }
8280 gotrel[] =
8281 {
8282 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8283 BFD_RELOC_32_SECREL },
8284 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8285 };
8286
8287 char *cp;
8288 unsigned j;
8289
8290 for (cp = input_line_pointer; *cp != '@'; cp++)
8291 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8292 return NULL;
8293
8294 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8295 {
8296 int len = gotrel[j].len;
8297
8298 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8299 {
8300 if (gotrel[j].rel[object_64bit] != 0)
8301 {
8302 int first, second;
8303 char *tmpbuf, *past_reloc;
8304
8305 *rel = gotrel[j].rel[object_64bit];
8306 if (adjust)
8307 *adjust = len;
8308
8309 if (types)
8310 {
8311 if (flag_code != CODE_64BIT)
8312 {
8313 types->bitfield.imm32 = 1;
8314 types->bitfield.disp32 = 1;
8315 }
8316 else
8317 *types = gotrel[j].types64;
8318 }
8319
8320 /* The length of the first part of our input line. */
8321 first = cp - input_line_pointer;
8322
8323 /* The second part goes from after the reloc token until
8324 (and including) an end_of_line char or comma. */
8325 past_reloc = cp + 1 + len;
8326 cp = past_reloc;
8327 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8328 ++cp;
8329 second = cp + 1 - past_reloc;
8330
8331 /* Allocate and copy string. The trailing NUL shouldn't
8332 be necessary, but be safe. */
add39d23 8333 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8334 memcpy (tmpbuf, input_line_pointer, first);
8335 if (second != 0 && *past_reloc != ' ')
8336 /* Replace the relocation token with ' ', so that
8337 errors like foo@SECLREL321 will be detected. */
8338 tmpbuf[first++] = ' ';
8339 memcpy (tmpbuf + first, past_reloc, second);
8340 tmpbuf[first + second] = '\0';
8341 return tmpbuf;
8342 }
8343
8344 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8345 gotrel[j].str, 1 << (5 + object_64bit));
8346 return NULL;
8347 }
8348 }
8349
8350 /* Might be a symbol version string. Don't as_bad here. */
8351 return NULL;
8352}
8353
8354#endif /* TE_PE */
8355
62ebcb5c 8356bfd_reloc_code_real_type
e3bb37b5 8357x86_cons (expressionS *exp, int size)
f3c180ae 8358{
62ebcb5c
AM		 8359 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8360
ee86248c
JB		 8361 intel_syntax = -intel_syntax;
8362
3c7b9c2c 8363 exp->X_md = 0;
4fa24527 8364 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8365 {
8366 /* Handle @GOTOFF and the like in an expression. */
8367 char *save;
8368 char *gotfree_input_line;
4a57f2cf 8369 int adjust = 0;
f3c180ae
AM		 8370
8371 save = input_line_pointer;
d258b828 8372 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8373 if (gotfree_input_line)
8374 input_line_pointer = gotfree_input_line;
8375
8376 expression (exp);
8377
8378 if (gotfree_input_line)
8379 {
8380 /* expression () has merrily parsed up to the end of line,
8381 or a comma - in the wrong buffer. Transfer how far
8382 input_line_pointer has moved to the right buffer. */
8383 input_line_pointer = (save
8384 + (input_line_pointer - gotfree_input_line)
8385 + adjust);
8386 free (gotfree_input_line);
3992d3b7
AM		 8387 if (exp->X_op == O_constant
8388 || exp->X_op == O_absent
8389 || exp->X_op == O_illegal
0398aac5 8390 || exp->X_op == O_register
3992d3b7
AM		 8391 || exp->X_op == O_big)
8392 {
8393 char c = *input_line_pointer;
8394 *input_line_pointer = 0;
8395 as_bad (_("missing or invalid expression `%s'"), save);
8396 *input_line_pointer = c;
8397 }
f3c180ae
AM		 8398 }
8399 }
8400 else
8401 expression (exp);
ee86248c
JB		 8402
8403 intel_syntax = -intel_syntax;
8404
8405 if (intel_syntax)
8406 i386_intel_simplify (exp);
62ebcb5c
AM		 8407
8408 return got_reloc;
f3c180ae 8409}
f3c180ae 8410
9f32dd5b
L		 8411static void
8412signed_cons (int size)
6482c264 8413{
d182319b
JB		 8414 if (flag_code == CODE_64BIT)
8415 cons_sign = 1;
8416 cons (size);
8417 cons_sign = -1;
6482c264
NC		 8418}
8419
d182319b 8420#ifdef TE_PE
6482c264 8421static void
7016a5d5 8422pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8423{
8424 expressionS exp;
8425
8426 do
8427 {
8428 expression (&exp);
8429 if (exp.X_op == O_symbol)
8430 exp.X_op = O_secrel;
8431
8432 emit_expr (&exp, 4);
8433 }
8434 while (*input_line_pointer++ == ',');
8435
8436 input_line_pointer--;
8437 demand_empty_rest_of_line ();
8438}
6482c264
NC		 8439#endif
8440
43234a1e
L		 8441/* Handle Vector operations. */
8442
8443static char *
8444check_VecOperations (char *op_string, char *op_end)
8445{
8446 const reg_entry *mask;
8447 const char *saved;
8448 char *end_op;
8449
8450 while (*op_string
8451 && (op_end == NULL || op_string < op_end))
8452 {
8453 saved = op_string;
8454 if (*op_string == '{')
8455 {
8456 op_string++;
8457
8458 /* Check broadcasts. */
8459 if (strncmp (op_string, "1to", 3) == 0)
8460 {
8461 int bcst_type;
8462
8463 if (i.broadcast)
8464 goto duplicated_vec_op;
8465
8466 op_string += 3;
8467 if (*op_string == '8')
8e6e0792 8468 bcst_type = 8;
b28d1bda 8469 else if (*op_string == '4')
8e6e0792 8470 bcst_type = 4;
b28d1bda 8471 else if (*op_string == '2')
8e6e0792 8472 bcst_type = 2;
43234a1e
L		 8473 else if (*op_string == '1'
8474 && *(op_string+1) == '6')
8475 {
8e6e0792 8476 bcst_type = 16;
43234a1e
L		 8477 op_string++;
8478 }
8479 else
8480 {
8481 as_bad (_("Unsupported broadcast: `%s'"), saved);
8482 return NULL;
8483 }
8484 op_string++;
8485
8486 broadcast_op.type = bcst_type;
8487 broadcast_op.operand = this_operand;
8488 i.broadcast = &broadcast_op;
8489 }
8490 /* Check masking operation. */
8491 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8492 {
8493 /* k0 can't be used for write mask. */
6d2cd6b2 8494 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8495 {
6d2cd6b2
JB		 8496 as_bad (_("`%s%s' can't be used for write mask"),
8497 register_prefix, mask->reg_name);
43234a1e
L		 8498 return NULL;
8499 }
8500
8501 if (!i.mask)
8502 {
8503 mask_op.mask = mask;
8504 mask_op.zeroing = 0;
8505 mask_op.operand = this_operand;
8506 i.mask = &mask_op;
8507 }
8508 else
8509 {
8510 if (i.mask->mask)
8511 goto duplicated_vec_op;
8512
8513 i.mask->mask = mask;
8514
8515 /* Only "{z}" is allowed here. No need to check
8516 zeroing mask explicitly. */
8517 if (i.mask->operand != this_operand)
8518 {
8519 as_bad (_("invalid write mask `%s'"), saved);
8520 return NULL;
8521 }
8522 }
8523
8524 op_string = end_op;
8525 }
8526 /* Check zeroing-flag for masking operation. */
8527 else if (*op_string == 'z')
8528 {
8529 if (!i.mask)
8530 {
8531 mask_op.mask = NULL;
8532 mask_op.zeroing = 1;
8533 mask_op.operand = this_operand;
8534 i.mask = &mask_op;
8535 }
8536 else
8537 {
8538 if (i.mask->zeroing)
8539 {
8540 duplicated_vec_op:
8541 as_bad (_("duplicated `%s'"), saved);
8542 return NULL;
8543 }
8544
8545 i.mask->zeroing = 1;
8546
8547 /* Only "{%k}" is allowed here. No need to check mask
8548 register explicitly. */
8549 if (i.mask->operand != this_operand)
8550 {
8551 as_bad (_("invalid zeroing-masking `%s'"),
8552 saved);
8553 return NULL;
8554 }
8555 }
8556
8557 op_string++;
8558 }
8559 else
8560 goto unknown_vec_op;
8561
8562 if (*op_string != '}')
8563 {
8564 as_bad (_("missing `}' in `%s'"), saved);
8565 return NULL;
8566 }
8567 op_string++;
0ba3a731
L		 8568
8569 /* Strip whitespace since the addition of pseudo prefixes
8570 changed how the scrubber treats '{'. */
8571 if (is_space_char (*op_string))
8572 ++op_string;
8573
43234a1e
L		 8574 continue;
8575 }
8576 unknown_vec_op:
8577 /* We don't know this one. */
8578 as_bad (_("unknown vector operation: `%s'"), saved);
8579 return NULL;
8580 }
8581
6d2cd6b2
JB		 8582 if (i.mask && i.mask->zeroing && !i.mask->mask)
8583 {
8584 as_bad (_("zeroing-masking only allowed with write mask"));
8585 return NULL;
8586 }
8587
43234a1e
L		 8588 return op_string;
8589}
8590
252b5132 8591static int
70e41ade 8592i386_immediate (char *imm_start)
252b5132
RH		 8593{
8594 char *save_input_line_pointer;
f3c180ae 8595 char *gotfree_input_line;
252b5132 8596 segT exp_seg = 0;
47926f60 8597 expressionS *exp;
40fb9820
L		 8598 i386_operand_type types;
8599
0dfbf9d7 8600 operand_type_set (&types, ~0);
252b5132
RH		 8601
8602 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8603 {
31b2323c
L		 8604 as_bad (_("at most %d immediate operands are allowed"),
8605 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8606 return 0;
8607 }
8608
8609 exp = &im_expressions[i.imm_operands++];
520dc8e8 8610 i.op[this_operand].imms = exp;
252b5132
RH		 8611
8612 if (is_space_char (*imm_start))
8613 ++imm_start;
8614
8615 save_input_line_pointer = input_line_pointer;
8616 input_line_pointer = imm_start;
8617
d258b828 8618 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8619 if (gotfree_input_line)
8620 input_line_pointer = gotfree_input_line;
252b5132
RH		 8621
8622 exp_seg = expression (exp);
8623
83183c0c 8624 SKIP_WHITESPACE ();
43234a1e
L		 8625
8626 /* Handle vector operations. */
8627 if (*input_line_pointer == '{')
8628 {
8629 input_line_pointer = check_VecOperations (input_line_pointer,
8630 NULL);
8631 if (input_line_pointer == NULL)
8632 return 0;
8633 }
8634
252b5132 8635 if (*input_line_pointer)
f3c180ae 8636 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8637
8638 input_line_pointer = save_input_line_pointer;
f3c180ae 8639 if (gotfree_input_line)
ee86248c
JB		 8640 {
8641 free (gotfree_input_line);
8642
8643 if (exp->X_op == O_constant || exp->X_op == O_register)
8644 exp->X_op = O_illegal;
8645 }
8646
8647 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8648}
252b5132 8649
ee86248c
JB		 8650static int
8651i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8652 i386_operand_type types, const char *imm_start)
8653{
8654 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8655 {
313c53d1
L		 8656 if (imm_start)
8657 as_bad (_("missing or invalid immediate expression `%s'"),
8658 imm_start);
3992d3b7 8659 return 0;
252b5132 8660 }
3e73aa7c 8661 else if (exp->X_op == O_constant)
252b5132 8662 {
47926f60 8663 /* Size it properly later. */
40fb9820 8664 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8665 /* If not 64bit, sign extend val. */
8666 if (flag_code != CODE_64BIT
4eed87de
AM		 8667 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8668 exp->X_add_number
8669 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8670 }
4c63da97 8671#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8672 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8673 && exp_seg != absolute_section
47926f60 8674 && exp_seg != text_section
24eab124
AM		 8675 && exp_seg != data_section
8676 && exp_seg != bss_section
8677 && exp_seg != undefined_section
f86103b7 8678 && !bfd_is_com_section (exp_seg))
252b5132 8679 {
d0b47220 8680 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8681 return 0;
8682 }
8683#endif
a841bdf5 8684 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8685 {
313c53d1
L		 8686 if (imm_start)
8687 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8688 return 0;
8689 }
252b5132
RH		 8690 else
8691 {
8692 /* This is an address. The size of the address will be
24eab124 8693 determined later, depending on destination register,
3e73aa7c 8694 suffix, or the default for the section. */
40fb9820
L		 8695 i.types[this_operand].bitfield.imm8 = 1;
8696 i.types[this_operand].bitfield.imm16 = 1;
8697 i.types[this_operand].bitfield.imm32 = 1;
8698 i.types[this_operand].bitfield.imm32s = 1;
8699 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8700 i.types[this_operand] = operand_type_and (i.types[this_operand],
8701 types);
252b5132
RH		 8702 }
8703
8704 return 1;
8705}
8706
551c1ca1 8707static char *
e3bb37b5 8708i386_scale (char *scale)
252b5132 8709{
551c1ca1
AM		 8710 offsetT val;
8711 char *save = input_line_pointer;
252b5132 8712
551c1ca1
AM		 8713 input_line_pointer = scale;
8714 val = get_absolute_expression ();
8715
8716 switch (val)
252b5132 8717 {
551c1ca1 8718 case 1:
252b5132
RH		 8719 i.log2_scale_factor = 0;
8720 break;
551c1ca1 8721 case 2:
252b5132
RH		 8722 i.log2_scale_factor = 1;
8723 break;
551c1ca1 8724 case 4:
252b5132
RH		 8725 i.log2_scale_factor = 2;
8726 break;
551c1ca1 8727 case 8:
252b5132
RH		 8728 i.log2_scale_factor = 3;
8729 break;
8730 default:
a724f0f4
JB		 8731 {
8732 char sep = *input_line_pointer;
8733
8734 *input_line_pointer = '\0';
8735 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8736 scale);
8737 *input_line_pointer = sep;
8738 input_line_pointer = save;
8739 return NULL;
8740 }
252b5132 8741 }
29b0f896 8742 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8743 {
8744 as_warn (_("scale factor of %d without an index register"),
24eab124 8745 1 << i.log2_scale_factor);
252b5132 8746 i.log2_scale_factor = 0;
252b5132 8747 }
551c1ca1
AM		 8748 scale = input_line_pointer;
8749 input_line_pointer = save;
8750 return scale;
252b5132
RH		 8751}
8752
252b5132 8753static int
e3bb37b5 8754i386_displacement (char *disp_start, char *disp_end)
252b5132 8755{
29b0f896 8756 expressionS *exp;
252b5132
RH		 8757 segT exp_seg = 0;
8758 char *save_input_line_pointer;
f3c180ae 8759 char *gotfree_input_line;
40fb9820
L		 8760 int override;
8761 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8762 int ret;
252b5132 8763
31b2323c
L		 8764 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8765 {
8766 as_bad (_("at most %d displacement operands are allowed"),
8767 MAX_MEMORY_OPERANDS);
8768 return 0;
8769 }
8770
0dfbf9d7 8771 operand_type_set (&bigdisp, 0);
40fb9820
L		 8772 if ((i.types[this_operand].bitfield.jumpabsolute)
8773 || (!current_templates->start->opcode_modifier.jump
8774 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8775 {
40fb9820 8776 bigdisp.bitfield.disp32 = 1;
e05278af 8777 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8778 if (flag_code == CODE_64BIT)
8779 {
8780 if (!override)
8781 {
8782 bigdisp.bitfield.disp32s = 1;
8783 bigdisp.bitfield.disp64 = 1;
8784 }
8785 }
8786 else if ((flag_code == CODE_16BIT) ^ override)
8787 {
8788 bigdisp.bitfield.disp32 = 0;
8789 bigdisp.bitfield.disp16 = 1;
8790 }
e05278af
JB		 8791 }
8792 else
8793 {
8794 /* For PC-relative branches, the width of the displacement
8795 is dependent upon data size, not address size. */
e05278af 8796 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8797 if (flag_code == CODE_64BIT)
8798 {
8799 if (override || i.suffix == WORD_MNEM_SUFFIX)
8800 bigdisp.bitfield.disp16 = 1;
8801 else
8802 {
8803 bigdisp.bitfield.disp32 = 1;
8804 bigdisp.bitfield.disp32s = 1;
8805 }
8806 }
8807 else
e05278af
JB		 8808 {
8809 if (!override)
8810 override = (i.suffix == (flag_code != CODE_16BIT
8811 ? WORD_MNEM_SUFFIX
8812 : LONG_MNEM_SUFFIX));
40fb9820
L		 8813 bigdisp.bitfield.disp32 = 1;
8814 if ((flag_code == CODE_16BIT) ^ override)
8815 {
8816 bigdisp.bitfield.disp32 = 0;
8817 bigdisp.bitfield.disp16 = 1;
8818 }
e05278af 8819 }
e05278af 8820 }
c6fb90c8
L		 8821 i.types[this_operand] = operand_type_or (i.types[this_operand],
8822 bigdisp);
252b5132
RH		 8823
8824 exp = &disp_expressions[i.disp_operands];
520dc8e8 8825 i.op[this_operand].disps = exp;
252b5132
RH		 8826 i.disp_operands++;
8827 save_input_line_pointer = input_line_pointer;
8828 input_line_pointer = disp_start;
8829 END_STRING_AND_SAVE (disp_end);
8830
8831#ifndef GCC_ASM_O_HACK
8832#define GCC_ASM_O_HACK 0
8833#endif
8834#if GCC_ASM_O_HACK
8835 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8836 if (i.types[this_operand].bitfield.baseIndex
24eab124 8837 && displacement_string_end[-1] == '+')
252b5132
RH		 8838 {
8839 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8840 constraint within gcc asm statements.
8841 For instance:
8842
8843 #define _set_tssldt_desc(n,addr,limit,type) \
8844 __asm__ __volatile__ ( \
8845 "movw %w2,%0\n\t" \
8846 "movw %w1,2+%0\n\t" \
8847 "rorl $16,%1\n\t" \
8848 "movb %b1,4+%0\n\t" \
8849 "movb %4,5+%0\n\t" \
8850 "movb $0,6+%0\n\t" \
8851 "movb %h1,7+%0\n\t" \
8852 "rorl $16,%1" \
8853 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8854
8855 This works great except that the output assembler ends
8856 up looking a bit weird if it turns out that there is
8857 no offset. You end up producing code that looks like:
8858
8859 #APP
8860 movw $235,(%eax)
8861 movw %dx,2+(%eax)
8862 rorl $16,%edx
8863 movb %dl,4+(%eax)
8864 movb $137,5+(%eax)
8865 movb $0,6+(%eax)
8866 movb %dh,7+(%eax)
8867 rorl $16,%edx
8868 #NO_APP
8869
47926f60 8870 So here we provide the missing zero. */
24eab124
AM		 8871
8872 *displacement_string_end = '0';
252b5132
RH		 8873 }
8874#endif
d258b828 8875 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8876 if (gotfree_input_line)
8877 input_line_pointer = gotfree_input_line;
252b5132 8878
24eab124 8879 exp_seg = expression (exp);
252b5132 8880
636c26b0
AM		 8881 SKIP_WHITESPACE ();
8882 if (*input_line_pointer)
8883 as_bad (_("junk `%s' after expression"), input_line_pointer);
8884#if GCC_ASM_O_HACK
8885 RESTORE_END_STRING (disp_end + 1);
8886#endif
636c26b0 8887 input_line_pointer = save_input_line_pointer;
636c26b0 8888 if (gotfree_input_line)
ee86248c
JB		 8889 {
8890 free (gotfree_input_line);
8891
8892 if (exp->X_op == O_constant || exp->X_op == O_register)
8893 exp->X_op = O_illegal;
8894 }
8895
8896 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8897
8898 RESTORE_END_STRING (disp_end);
8899
8900 return ret;
8901}
8902
8903static int
8904i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8905 i386_operand_type types, const char *disp_start)
8906{
8907 i386_operand_type bigdisp;
8908 int ret = 1;
636c26b0 8909
24eab124
AM		 8910 /* We do this to make sure that the section symbol is in
8911 the symbol table. We will ultimately change the relocation
47926f60 8912 to be relative to the beginning of the section. */
1ae12ab7 8913 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8914 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8915 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8916 {
636c26b0 8917 if (exp->X_op != O_symbol)
3992d3b7 8918 goto inv_disp;
636c26b0 8919
e5cb08ac 8920 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8921 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8922 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8923 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8924 exp->X_op = O_subtract;
8925 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8926 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8927 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8928 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8929 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8930 else
29b0f896 8931 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8932 }
252b5132 8933
3992d3b7
AM		 8934 else if (exp->X_op == O_absent
8935 || exp->X_op == O_illegal
ee86248c 8936 || exp->X_op == O_big)
2daf4fd8 8937 {
3992d3b7
AM		 8938 inv_disp:
8939 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8940 disp_start);
3992d3b7 8941 ret = 0;
2daf4fd8
AM		 8942 }
8943
0e1147d9
L		 8944 else if (flag_code == CODE_64BIT
8945 && !i.prefix[ADDR_PREFIX]
8946 && exp->X_op == O_constant)
8947 {
8948 /* Since displacement is signed extended to 64bit, don't allow
8949 disp32 and turn off disp32s if they are out of range. */
8950 i.types[this_operand].bitfield.disp32 = 0;
8951 if (!fits_in_signed_long (exp->X_add_number))
8952 {
8953 i.types[this_operand].bitfield.disp32s = 0;
8954 if (i.types[this_operand].bitfield.baseindex)
8955 {
8956 as_bad (_("0x%lx out range of signed 32bit displacement"),
8957 (long) exp->X_add_number);
8958 ret = 0;
8959 }
8960 }
8961 }
8962
4c63da97 8963#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8964 else if (exp->X_op != O_constant
8965 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8966 && exp_seg != absolute_section
8967 && exp_seg != text_section
8968 && exp_seg != data_section
8969 && exp_seg != bss_section
8970 && exp_seg != undefined_section
8971 && !bfd_is_com_section (exp_seg))
24eab124 8972 {
d0b47220 8973 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8974 ret = 0;
24eab124 8975 }
252b5132 8976#endif
3956db08 8977
40fb9820
L		 8978 /* Check if this is a displacement only operand. */
8979 bigdisp = i.types[this_operand];
8980 bigdisp.bitfield.disp8 = 0;
8981 bigdisp.bitfield.disp16 = 0;
8982 bigdisp.bitfield.disp32 = 0;
8983 bigdisp.bitfield.disp32s = 0;
8984 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8985 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8986 i.types[this_operand] = operand_type_and (i.types[this_operand],
8987 types);
3956db08 8988
3992d3b7 8989 return ret;
252b5132
RH		 8990}
8991
2abc2bec
JB		 8992/* Return the active addressing mode, taking address override and
8993 registers forming the address into consideration. Update the
8994 address override prefix if necessary. */
47926f60 8995
2abc2bec
JB		 8996static enum flag_code
8997i386_addressing_mode (void)
252b5132 8998{
be05d201
L		 8999 enum flag_code addr_mode;
9000
9001 if (i.prefix[ADDR_PREFIX])
9002 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9003 else
9004 {
9005 addr_mode = flag_code;
9006
24eab124 9007#if INFER_ADDR_PREFIX
be05d201
L		 9008 if (i.mem_operands == 0)
9009 {
9010 /* Infer address prefix from the first memory operand. */
9011 const reg_entry *addr_reg = i.base_reg;
9012
9013 if (addr_reg == NULL)
9014 addr_reg = i.index_reg;
eecb386c 9015
be05d201
L		 9016 if (addr_reg)
9017 {
9018 if (addr_reg->reg_num == RegEip
9019 || addr_reg->reg_num == RegEiz
dc821c5f 9020 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9021 addr_mode = CODE_32BIT;
9022 else if (flag_code != CODE_64BIT
dc821c5f 9023 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9024 addr_mode = CODE_16BIT;
9025
9026 if (addr_mode != flag_code)
9027 {
9028 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9029 i.prefixes += 1;
9030 /* Change the size of any displacement too. At most one
9031 of Disp16 or Disp32 is set.
9032 FIXME. There doesn't seem to be any real need for
9033 separate Disp16 and Disp32 flags. The same goes for
9034 Imm16 and Imm32. Removing them would probably clean
9035 up the code quite a lot. */
9036 if (flag_code != CODE_64BIT
9037 && (i.types[this_operand].bitfield.disp16
9038 || i.types[this_operand].bitfield.disp32))
9039 i.types[this_operand]
9040 = operand_type_xor (i.types[this_operand], disp16_32);
9041 }
9042 }
9043 }
24eab124 9044#endif
be05d201
L		 9045 }
9046
2abc2bec
JB		 9047 return addr_mode;
9048}
9049
9050/* Make sure the memory operand we've been dealt is valid.
9051 Return 1 on success, 0 on a failure. */
9052
9053static int
9054i386_index_check (const char *operand_string)
9055{
9056 const char *kind = "base/index";
9057 enum flag_code addr_mode = i386_addressing_mode ();
9058
fc0763e6
JB		 9059 if (current_templates->start->opcode_modifier.isstring
9060 && !current_templates->start->opcode_modifier.immext
9061 && (current_templates->end[-1].opcode_modifier.isstring
9062 || i.mem_operands))
9063 {
9064 /* Memory operands of string insns are special in that they only allow
9065 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9066 const reg_entry *expected_reg;
9067 static const char *di_si[][2] =
9068 {
9069 { "esi", "edi" },
9070 { "si", "di" },
9071 { "rsi", "rdi" }
9072 };
9073 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9074
9075 kind = "string address";
9076
8325cc63 9077 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9078 {
9079 i386_operand_type type = current_templates->end[-1].operand_types[0];
9080
9081 if (!type.bitfield.baseindex
9082 || ((!i.mem_operands != !intel_syntax)
9083 && current_templates->end[-1].operand_types[1]
9084 .bitfield.baseindex))
9085 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9086 expected_reg = hash_find (reg_hash,
9087 di_si[addr_mode][type.bitfield.esseg]);
9088
fc0763e6
JB		 9089 }
9090 else
be05d201 9091 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9092
be05d201
L		 9093 if (i.base_reg != expected_reg
9094 || i.index_reg
fc0763e6 9095 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9096 {
be05d201
L		 9097 /* The second memory operand must have the same size as
9098 the first one. */
9099 if (i.mem_operands
9100 && i.base_reg
9101 && !((addr_mode == CODE_64BIT
dc821c5f 9102 && i.base_reg->reg_type.bitfield.qword)
be05d201 9103 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9104 ? i.base_reg->reg_type.bitfield.dword
9105 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9106 goto bad_address;
9107
fc0763e6
JB		 9108 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9109 operand_string,
9110 intel_syntax ? '[' : '(',
9111 register_prefix,
be05d201 9112 expected_reg->reg_name,
fc0763e6 9113 intel_syntax ? ']' : ')');
be05d201 9114 return 1;
fc0763e6 9115 }
be05d201
L		 9116 else
9117 return 1;
9118
9119bad_address:
9120 as_bad (_("`%s' is not a valid %s expression"),
9121 operand_string, kind);
9122 return 0;
3e73aa7c
JH		 9123 }
9124 else
9125 {
be05d201
L		 9126 if (addr_mode != CODE_16BIT)
9127 {
9128 /* 32-bit/64-bit checks. */
9129 if ((i.base_reg
9130 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9131 ? !i.base_reg->reg_type.bitfield.qword
9132 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9133 && (i.index_reg
9134 || (i.base_reg->reg_num
9135 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9136 || (i.index_reg
1b54b8d7
JB		 9137 && !i.index_reg->reg_type.bitfield.xmmword
9138 && !i.index_reg->reg_type.bitfield.ymmword
9139 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9140 && ((addr_mode == CODE_64BIT
dc821c5f 9141 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9142 || i.index_reg->reg_num == RegRiz)
dc821c5f 9143 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9144 || i.index_reg->reg_num == RegEiz))
9145 || !i.index_reg->reg_type.bitfield.baseindex)))
9146 goto bad_address;
8178be5b
JB		 9147
9148 /* bndmk, bndldx, and bndstx have special restrictions. */
9149 if (current_templates->start->base_opcode == 0xf30f1b
9150 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9151 {
9152 /* They cannot use RIP-relative addressing. */
9153 if (i.base_reg && i.base_reg->reg_num == RegRip)
9154 {
9155 as_bad (_("`%s' cannot be used here"), operand_string);
9156 return 0;
9157 }
9158
9159 /* bndldx and bndstx ignore their scale factor. */
9160 if (current_templates->start->base_opcode != 0xf30f1b
9161 && i.log2_scale_factor)
9162 as_warn (_("register scaling is being ignored here"));
9163 }
be05d201
L		 9164 }
9165 else
3e73aa7c 9166 {
be05d201 9167 /* 16-bit checks. */
3e73aa7c 9168 if ((i.base_reg
dc821c5f 9169 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9170 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9171 || (i.index_reg
dc821c5f 9172 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9173 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9174 || !(i.base_reg
9175 && i.base_reg->reg_num < 6
9176 && i.index_reg->reg_num >= 6
9177 && i.log2_scale_factor == 0))))
be05d201 9178 goto bad_address;
3e73aa7c
JH		 9179 }
9180 }
be05d201 9181 return 1;
24eab124 9182}
252b5132 9183
43234a1e
L		 9184/* Handle vector immediates. */
9185
9186static int
9187RC_SAE_immediate (const char *imm_start)
9188{
9189 unsigned int match_found, j;
9190 const char *pstr = imm_start;
9191 expressionS *exp;
9192
9193 if (*pstr != '{')
9194 return 0;
9195
9196 pstr++;
9197 match_found = 0;
9198 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9199 {
9200 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9201 {
9202 if (!i.rounding)
9203 {
9204 rc_op.type = RC_NamesTable[j].type;
9205 rc_op.operand = this_operand;
9206 i.rounding = &rc_op;
9207 }
9208 else
9209 {
9210 as_bad (_("duplicated `%s'"), imm_start);
9211 return 0;
9212 }
9213 pstr += RC_NamesTable[j].len;
9214 match_found = 1;
9215 break;
9216 }
9217 }
9218 if (!match_found)
9219 return 0;
9220
9221 if (*pstr++ != '}')
9222 {
9223 as_bad (_("Missing '}': '%s'"), imm_start);
9224 return 0;
9225 }
9226 /* RC/SAE immediate string should contain nothing more. */;
9227 if (*pstr != 0)
9228 {
9229 as_bad (_("Junk after '}': '%s'"), imm_start);
9230 return 0;
9231 }
9232
9233 exp = &im_expressions[i.imm_operands++];
9234 i.op[this_operand].imms = exp;
9235
9236 exp->X_op = O_constant;
9237 exp->X_add_number = 0;
9238 exp->X_add_symbol = (symbolS *) 0;
9239 exp->X_op_symbol = (symbolS *) 0;
9240
9241 i.types[this_operand].bitfield.imm8 = 1;
9242 return 1;
9243}
9244
8325cc63
JB		 9245/* Only string instructions can have a second memory operand, so
9246 reduce current_templates to just those if it contains any. */
9247static int
9248maybe_adjust_templates (void)
9249{
9250 const insn_template *t;
9251
9252 gas_assert (i.mem_operands == 1);
9253
9254 for (t = current_templates->start; t < current_templates->end; ++t)
9255 if (t->opcode_modifier.isstring)
9256 break;
9257
9258 if (t < current_templates->end)
9259 {
9260 static templates aux_templates;
9261 bfd_boolean recheck;
9262
9263 aux_templates.start = t;
9264 for (; t < current_templates->end; ++t)
9265 if (!t->opcode_modifier.isstring)
9266 break;
9267 aux_templates.end = t;
9268
9269 /* Determine whether to re-check the first memory operand. */
9270 recheck = (aux_templates.start != current_templates->start
9271 || t != current_templates->end);
9272
9273 current_templates = &aux_templates;
9274
9275 if (recheck)
9276 {
9277 i.mem_operands = 0;
9278 if (i.memop1_string != NULL
9279 && i386_index_check (i.memop1_string) == 0)
9280 return 0;
9281 i.mem_operands = 1;
9282 }
9283 }
9284
9285 return 1;
9286}
9287
fc0763e6 9288/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9289 on error. */
252b5132 9290
252b5132 9291static int
a7619375 9292i386_att_operand (char *operand_string)
252b5132 9293{
af6bdddf
AM		 9294 const reg_entry *r;
9295 char *end_op;
24eab124 9296 char *op_string = operand_string;
252b5132 9297
24eab124 9298 if (is_space_char (*op_string))
252b5132
RH		 9299 ++op_string;
9300
24eab124 9301 /* We check for an absolute prefix (differentiating,
47926f60 9302 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9303 if (*op_string == ABSOLUTE_PREFIX)
9304 {
9305 ++op_string;
9306 if (is_space_char (*op_string))
9307 ++op_string;
40fb9820 9308 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9309 }
252b5132 9310
47926f60 9311 /* Check if operand is a register. */
4d1bb795 9312 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9313 {
40fb9820
L		 9314 i386_operand_type temp;
9315
24eab124
AM		 9316 /* Check for a segment override by searching for ':' after a
9317 segment register. */
9318 op_string = end_op;
9319 if (is_space_char (*op_string))
9320 ++op_string;
40fb9820
L		 9321 if (*op_string == ':'
9322 && (r->reg_type.bitfield.sreg2
9323 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9324 {
9325 switch (r->reg_num)
9326 {
9327 case 0:
9328 i.seg[i.mem_operands] = &es;
9329 break;
9330 case 1:
9331 i.seg[i.mem_operands] = &cs;
9332 break;
9333 case 2:
9334 i.seg[i.mem_operands] = &ss;
9335 break;
9336 case 3:
9337 i.seg[i.mem_operands] = &ds;
9338 break;
9339 case 4:
9340 i.seg[i.mem_operands] = &fs;
9341 break;
9342 case 5:
9343 i.seg[i.mem_operands] = &gs;
9344 break;
9345 }
252b5132 9346
24eab124 9347 /* Skip the ':' and whitespace. */
252b5132
RH		 9348 ++op_string;
9349 if (is_space_char (*op_string))
24eab124 9350 ++op_string;
252b5132 9351
24eab124
AM		 9352 if (!is_digit_char (*op_string)
9353 && !is_identifier_char (*op_string)
9354 && *op_string != '('
9355 && *op_string != ABSOLUTE_PREFIX)
9356 {
9357 as_bad (_("bad memory operand `%s'"), op_string);
9358 return 0;
9359 }
47926f60 9360 /* Handle case of %es:*foo. */
24eab124
AM		 9361 if (*op_string == ABSOLUTE_PREFIX)
9362 {
9363 ++op_string;
9364 if (is_space_char (*op_string))
9365 ++op_string;
40fb9820 9366 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9367 }
9368 goto do_memory_reference;
9369 }
43234a1e
L		 9370
9371 /* Handle vector operations. */
9372 if (*op_string == '{')
9373 {
9374 op_string = check_VecOperations (op_string, NULL);
9375 if (op_string == NULL)
9376 return 0;
9377 }
9378
24eab124
AM		 9379 if (*op_string)
9380 {
d0b47220 9381 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9382 return 0;
9383 }
40fb9820
L		 9384 temp = r->reg_type;
9385 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9386 i.types[this_operand] = operand_type_or (i.types[this_operand],
9387 temp);
7d5e4556 9388 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9389 i.op[this_operand].regs = r;
24eab124
AM		 9390 i.reg_operands++;
9391 }
af6bdddf
AM		 9392 else if (*op_string == REGISTER_PREFIX)
9393 {
9394 as_bad (_("bad register name `%s'"), op_string);
9395 return 0;
9396 }
24eab124 9397 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9398 {
24eab124 9399 ++op_string;
40fb9820 9400 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9401 {
d0b47220 9402 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9403 return 0;
9404 }
9405 if (!i386_immediate (op_string))
9406 return 0;
9407 }
43234a1e
L		 9408 else if (RC_SAE_immediate (operand_string))
9409 {
9410 /* If it is a RC or SAE immediate, do nothing. */
9411 ;
9412 }
24eab124
AM		 9413 else if (is_digit_char (*op_string)
9414 || is_identifier_char (*op_string)
d02603dc 9415 || *op_string == '"'
e5cb08ac 9416 || *op_string == '(')
24eab124 9417 {
47926f60 9418 /* This is a memory reference of some sort. */
af6bdddf 9419 char *base_string;
252b5132 9420
47926f60 9421 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9422 char *displacement_string_start;
9423 char *displacement_string_end;
43234a1e 9424 char *vop_start;
252b5132 9425
24eab124 9426 do_memory_reference:
8325cc63
JB		 9427 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9428 return 0;
24eab124 9429 if ((i.mem_operands == 1
40fb9820 9430 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9431 || i.mem_operands == 2)
9432 {
9433 as_bad (_("too many memory references for `%s'"),
9434 current_templates->start->name);
9435 return 0;
9436 }
252b5132 9437
24eab124
AM		 9438 /* Check for base index form. We detect the base index form by
9439 looking for an ')' at the end of the operand, searching
9440 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9441 after the '('. */
af6bdddf 9442 base_string = op_string + strlen (op_string);
c3332e24 9443
43234a1e
L		 9444 /* Handle vector operations. */
9445 vop_start = strchr (op_string, '{');
9446 if (vop_start && vop_start < base_string)
9447 {
9448 if (check_VecOperations (vop_start, base_string) == NULL)
9449 return 0;
9450 base_string = vop_start;
9451 }
9452
af6bdddf
AM		 9453 --base_string;
9454 if (is_space_char (*base_string))
9455 --base_string;
252b5132 9456
47926f60 9457 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9458 displacement_string_start = op_string;
9459 displacement_string_end = base_string + 1;
252b5132 9460
24eab124
AM		 9461 if (*base_string == ')')
9462 {
af6bdddf 9463 char *temp_string;
24eab124
AM		 9464 unsigned int parens_balanced = 1;
9465 /* We've already checked that the number of left & right ()'s are
47926f60 9466 equal, so this loop will not be infinite. */
24eab124
AM		 9467 do
9468 {
9469 base_string--;
9470 if (*base_string == ')')
9471 parens_balanced++;
9472 if (*base_string == '(')
9473 parens_balanced--;
9474 }
9475 while (parens_balanced);
c3332e24 9476
af6bdddf 9477 temp_string = base_string;
c3332e24 9478
24eab124 9479 /* Skip past '(' and whitespace. */
252b5132
RH		 9480 ++base_string;
9481 if (is_space_char (*base_string))
24eab124 9482 ++base_string;
252b5132 9483
af6bdddf 9484 if (*base_string == ','
4eed87de
AM		 9485 || ((i.base_reg = parse_register (base_string, &end_op))
9486 != NULL))
252b5132 9487 {
af6bdddf 9488 displacement_string_end = temp_string;
252b5132 9489
40fb9820 9490 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9491
af6bdddf 9492 if (i.base_reg)
24eab124 9493 {
24eab124
AM		 9494 base_string = end_op;
9495 if (is_space_char (*base_string))
9496 ++base_string;
af6bdddf
AM		 9497 }
9498
9499 /* There may be an index reg or scale factor here. */
9500 if (*base_string == ',')
9501 {
9502 ++base_string;
9503 if (is_space_char (*base_string))
9504 ++base_string;
9505
4eed87de
AM		 9506 if ((i.index_reg = parse_register (base_string, &end_op))
9507 != NULL)
24eab124 9508 {
af6bdddf 9509 base_string = end_op;
24eab124
AM		 9510 if (is_space_char (*base_string))
9511 ++base_string;
af6bdddf
AM		 9512 if (*base_string == ',')
9513 {
9514 ++base_string;
9515 if (is_space_char (*base_string))
9516 ++base_string;
9517 }
e5cb08ac 9518 else if (*base_string != ')')
af6bdddf 9519 {
4eed87de
AM		 9520 as_bad (_("expecting `,' or `)' "
9521 "after index register in `%s'"),
af6bdddf
AM		 9522 operand_string);
9523 return 0;
9524 }
24eab124 9525 }
af6bdddf 9526 else if (*base_string == REGISTER_PREFIX)
24eab124 9527 {
f76bf5e0
L		 9528 end_op = strchr (base_string, ',');
9529 if (end_op)
9530 *end_op = '\0';
af6bdddf 9531 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9532 return 0;
9533 }
252b5132 9534
47926f60 9535 /* Check for scale factor. */
551c1ca1 9536 if (*base_string != ')')
af6bdddf 9537 {
551c1ca1
AM		 9538 char *end_scale = i386_scale (base_string);
9539
9540 if (!end_scale)
af6bdddf 9541 return 0;
24eab124 9542
551c1ca1 9543 base_string = end_scale;
af6bdddf
AM		 9544 if (is_space_char (*base_string))
9545 ++base_string;
9546 if (*base_string != ')')
9547 {
4eed87de
AM		 9548 as_bad (_("expecting `)' "
9549 "after scale factor in `%s'"),
af6bdddf
AM		 9550 operand_string);
9551 return 0;
9552 }
9553 }
9554 else if (!i.index_reg)
24eab124 9555 {
4eed87de
AM		 9556 as_bad (_("expecting index register or scale factor "
9557 "after `,'; got '%c'"),
af6bdddf 9558 *base_string);
24eab124
AM		 9559 return 0;
9560 }
9561 }
af6bdddf 9562 else if (*base_string != ')')
24eab124 9563 {
4eed87de
AM		 9564 as_bad (_("expecting `,' or `)' "
9565 "after base register in `%s'"),
af6bdddf 9566 operand_string);
24eab124
AM		 9567 return 0;
9568 }
c3332e24 9569 }
af6bdddf 9570 else if (*base_string == REGISTER_PREFIX)
c3332e24 9571 {
f76bf5e0
L		 9572 end_op = strchr (base_string, ',');
9573 if (end_op)
9574 *end_op = '\0';
af6bdddf 9575 as_bad (_("bad register name `%s'"), base_string);
24eab124 9576 return 0;
c3332e24 9577 }
24eab124
AM		 9578 }
9579
9580 /* If there's an expression beginning the operand, parse it,
9581 assuming displacement_string_start and
9582 displacement_string_end are meaningful. */
9583 if (displacement_string_start != displacement_string_end)
9584 {
9585 if (!i386_displacement (displacement_string_start,
9586 displacement_string_end))
9587 return 0;
9588 }
9589
9590 /* Special case for (%dx) while doing input/output op. */
9591 if (i.base_reg
0dfbf9d7
L		 9592 && operand_type_equal (&i.base_reg->reg_type,
9593 &reg16_inoutportreg)
24eab124
AM		 9594 && i.index_reg == 0
9595 && i.log2_scale_factor == 0
9596 && i.seg[i.mem_operands] == 0
40fb9820 9597 && !operand_type_check (i.types[this_operand], disp))
24eab124 9598 {
65da13b5 9599 i.types[this_operand] = inoutportreg;
24eab124
AM		 9600 return 1;
9601 }
9602
eecb386c
AM		 9603 if (i386_index_check (operand_string) == 0)
9604 return 0;
5c07affc 9605 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9606 if (i.mem_operands == 0)
9607 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9608 i.mem_operands++;
9609 }
9610 else
ce8a8b2f
AM		 9611 {
9612 /* It's not a memory operand; argh! */
24eab124
AM		 9613 as_bad (_("invalid char %s beginning operand %d `%s'"),
9614 output_invalid (*op_string),
9615 this_operand + 1,
9616 op_string);
9617 return 0;
9618 }
47926f60 9619 return 1; /* Normal return. */
252b5132
RH		 9620}
9621\f
fa94de6b
RM		 9622/* Calculate the maximum variable size (i.e., excluding fr_fix)
9623 that an rs_machine_dependent frag may reach. */
9624
9625unsigned int
9626i386_frag_max_var (fragS *frag)
9627{
9628 /* The only relaxable frags are for jumps.
9629 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9630 gas_assert (frag->fr_type == rs_machine_dependent);
9631 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9632}
9633
b084df0b
L		 9634#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9635static int
8dcea932 9636elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9637{
9638 /* STT_GNU_IFUNC symbol must go through PLT. */
9639 if ((symbol_get_bfdsym (fr_symbol)->flags
9640 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9641 return 0;
9642
9643 if (!S_IS_EXTERNAL (fr_symbol))
9644 /* Symbol may be weak or local. */
9645 return !S_IS_WEAK (fr_symbol);
9646
8dcea932
L		 9647 /* Global symbols with non-default visibility can't be preempted. */
9648 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9649 return 1;
9650
9651 if (fr_var != NO_RELOC)
9652 switch ((enum bfd_reloc_code_real) fr_var)
9653 {
9654 case BFD_RELOC_386_PLT32:
9655 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9656 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9657 return 0;
9658 default:
9659 abort ();
9660 }
9661
b084df0b
L		 9662 /* Global symbols with default visibility in a shared library may be
9663 preempted by another definition. */
8dcea932 9664 return !shared;
b084df0b
L		 9665}
9666#endif
9667
ee7fcc42
AM		 9668/* md_estimate_size_before_relax()
9669
9670 Called just before relax() for rs_machine_dependent frags. The x86
9671 assembler uses these frags to handle variable size jump
9672 instructions.
9673
9674 Any symbol that is now undefined will not become defined.
9675 Return the correct fr_subtype in the frag.
9676 Return the initial "guess for variable size of frag" to caller.
9677 The guess is actually the growth beyond the fixed part. Whatever
9678 we do to grow the fixed or variable part contributes to our
9679 returned value. */
9680
252b5132 9681int
7016a5d5 9682md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9683{
252b5132 9684 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9685 check for un-relaxable symbols. On an ELF system, we can't relax
9686 an externally visible symbol, because it may be overridden by a
9687 shared library. */
9688 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9689#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9690 || (IS_ELF
8dcea932
L		 9691 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9692 fragP->fr_var))
fbeb56a4
DK		 9693#endif
9694#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9695 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9696 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9697#endif
9698 )
252b5132 9699 {
b98ef147
AM		 9700 /* Symbol is undefined in this segment, or we need to keep a
9701 reloc so that weak symbols can be overridden. */
9702 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9703 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9704 unsigned char *opcode;
9705 int old_fr_fix;
f6af82bd 9706
ee7fcc42 9707 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9708 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9709 else if (size == 2)
f6af82bd 9710 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9711#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9712 else if (need_plt32_p (fragP->fr_symbol))
9713 reloc_type = BFD_RELOC_X86_64_PLT32;
9714#endif
f6af82bd
AM		 9715 else
9716 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9717
ee7fcc42
AM		 9718 old_fr_fix = fragP->fr_fix;
9719 opcode = (unsigned char *) fragP->fr_opcode;
9720
fddf5b5b 9721 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9722 {
fddf5b5b
AM		 9723 case UNCOND_JUMP:
9724 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9725 opcode[0] = 0xe9;
252b5132 9726 fragP->fr_fix += size;
062cd5e7
AS		 9727 fix_new (fragP, old_fr_fix, size,
9728 fragP->fr_symbol,
9729 fragP->fr_offset, 1,
9730 reloc_type);
252b5132
RH		 9731 break;
9732
fddf5b5b 9733 case COND_JUMP86:
412167cb
AM		 9734 if (size == 2
9735 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9736 {
9737 /* Negate the condition, and branch past an
9738 unconditional jump. */
9739 opcode[0] ^= 1;
9740 opcode[1] = 3;
9741 /* Insert an unconditional jump. */
9742 opcode[2] = 0xe9;
9743 /* We added two extra opcode bytes, and have a two byte
9744 offset. */
9745 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9746 fix_new (fragP, old_fr_fix + 2, 2,
9747 fragP->fr_symbol,
9748 fragP->fr_offset, 1,
9749 reloc_type);
fddf5b5b
AM		 9750 break;
9751 }
9752 /* Fall through. */
9753
9754 case COND_JUMP:
412167cb
AM		 9755 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9756 {
3e02c1cc
AM		 9757 fixS *fixP;
9758
412167cb 9759 fragP->fr_fix += 1;
3e02c1cc
AM		 9760 fixP = fix_new (fragP, old_fr_fix, 1,
9761 fragP->fr_symbol,
9762 fragP->fr_offset, 1,
9763 BFD_RELOC_8_PCREL);
9764 fixP->fx_signed = 1;
412167cb
AM		 9765 break;
9766 }
93c2a809 9767
24eab124 9768 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9769 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9770 opcode[1] = opcode[0] + 0x10;
f6af82bd 9771 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9772 /* We've added an opcode byte. */
9773 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9774 fix_new (fragP, old_fr_fix + 1, size,
9775 fragP->fr_symbol,
9776 fragP->fr_offset, 1,
9777 reloc_type);
252b5132 9778 break;
fddf5b5b
AM		 9779
9780 default:
9781 BAD_CASE (fragP->fr_subtype);
9782 break;
252b5132
RH		 9783 }
9784 frag_wane (fragP);
ee7fcc42 9785 return fragP->fr_fix - old_fr_fix;
252b5132 9786 }
93c2a809 9787
93c2a809
AM		 9788 /* Guess size depending on current relax state. Initially the relax
9789 state will correspond to a short jump and we return 1, because
9790 the variable part of the frag (the branch offset) is one byte
9791 long. However, we can relax a section more than once and in that
9792 case we must either set fr_subtype back to the unrelaxed state,
9793 or return the value for the appropriate branch. */
9794 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9795}
9796
47926f60
KH		 9797/* Called after relax() is finished.
9798
9799 In: Address of frag.
9800 fr_type == rs_machine_dependent.
9801 fr_subtype is what the address relaxed to.
9802
9803 Out: Any fixSs and constants are set up.
9804 Caller will turn frag into a ".space 0". */
9805
252b5132 9806void
7016a5d5
TG		 9807md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9808 fragS *fragP)
252b5132 9809{
29b0f896 9810 unsigned char *opcode;
252b5132 9811 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9812 offsetT target_address;
9813 offsetT opcode_address;
252b5132 9814 unsigned int extension = 0;
847f7ad4 9815 offsetT displacement_from_opcode_start;
252b5132
RH		 9816
9817 opcode = (unsigned char *) fragP->fr_opcode;
9818
47926f60 9819 /* Address we want to reach in file space. */
252b5132 9820 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9821
47926f60 9822 /* Address opcode resides at in file space. */
252b5132
RH		 9823 opcode_address = fragP->fr_address + fragP->fr_fix;
9824
47926f60 9825 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9826 displacement_from_opcode_start = target_address - opcode_address;
9827
fddf5b5b 9828 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9829 {
47926f60
KH		 9830 /* Don't have to change opcode. */
9831 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9832 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9833 }
9834 else
9835 {
9836 if (no_cond_jump_promotion
9837 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9838 as_warn_where (fragP->fr_file, fragP->fr_line,
9839 _("long jump required"));
252b5132 9840
fddf5b5b
AM		 9841 switch (fragP->fr_subtype)
9842 {
9843 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9844 extension = 4; /* 1 opcode + 4 displacement */
9845 opcode[0] = 0xe9;
9846 where_to_put_displacement = &opcode[1];
9847 break;
252b5132 9848
fddf5b5b
AM		 9849 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9850 extension = 2; /* 1 opcode + 2 displacement */
9851 opcode[0] = 0xe9;
9852 where_to_put_displacement = &opcode[1];
9853 break;
252b5132 9854
fddf5b5b
AM		 9855 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9856 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9857 extension = 5; /* 2 opcode + 4 displacement */
9858 opcode[1] = opcode[0] + 0x10;
9859 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9860 where_to_put_displacement = &opcode[2];
9861 break;
252b5132 9862
fddf5b5b
AM		 9863 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9864 extension = 3; /* 2 opcode + 2 displacement */
9865 opcode[1] = opcode[0] + 0x10;
9866 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9867 where_to_put_displacement = &opcode[2];
9868 break;
252b5132 9869
fddf5b5b
AM		 9870 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9871 extension = 4;
9872 opcode[0] ^= 1;
9873 opcode[1] = 3;
9874 opcode[2] = 0xe9;
9875 where_to_put_displacement = &opcode[3];
9876 break;
9877
9878 default:
9879 BAD_CASE (fragP->fr_subtype);
9880 break;
9881 }
252b5132 9882 }
fddf5b5b 9883
7b81dfbb
AJ		 9884 /* If size if less then four we are sure that the operand fits,
9885 but if it's 4, then it could be that the displacement is larger
9886 then -/+ 2GB. */
9887 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9888 && object_64bit
9889 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9890 + ((addressT) 1 << 31))
9891 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9892 {
9893 as_bad_where (fragP->fr_file, fragP->fr_line,
9894 _("jump target out of range"));
9895 /* Make us emit 0. */
9896 displacement_from_opcode_start = extension;
9897 }
47926f60 9898 /* Now put displacement after opcode. */
252b5132
RH		 9899 md_number_to_chars ((char *) where_to_put_displacement,
9900 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9901 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9902 fragP->fr_fix += extension;
9903}
9904\f
7016a5d5 9905/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9906 by our caller that we have all the info we need to fix it up.
9907
7016a5d5
TG		 9908 Parameter valP is the pointer to the value of the bits.
9909
252b5132
RH		 9910 On the 386, immediates, displacements, and data pointers are all in
9911 the same (little-endian) format, so we don't need to care about which
9912 we are handling. */
9913
94f592af 9914void
7016a5d5 9915md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9916{
94f592af 9917 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9918 valueT value = *valP;
252b5132 9919
f86103b7 9920#if !defined (TE_Mach)
93382f6d
AM		 9921 if (fixP->fx_pcrel)
9922 {
9923 switch (fixP->fx_r_type)
9924 {
5865bb77
ILT		 9925 default:
9926 break;
9927
d6ab8113
JB		 9928 case BFD_RELOC_64:
9929 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9930 break;
93382f6d 9931 case BFD_RELOC_32:
ae8887b5 9932 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9933 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9934 break;
9935 case BFD_RELOC_16:
9936 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9937 break;
9938 case BFD_RELOC_8:
9939 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9940 break;
9941 }
9942 }
252b5132 9943
a161fe53 9944 if (fixP->fx_addsy != NULL
31312f95 9945 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9946 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9947 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9948 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9949 && !use_rela_relocations)
252b5132 9950 {
31312f95
AM		 9951 /* This is a hack. There should be a better way to handle this.
9952 This covers for the fact that bfd_install_relocation will
9953 subtract the current location (for partial_inplace, PC relative
9954 relocations); see more below. */
252b5132 9955#ifndef OBJ_AOUT
718ddfc0 9956 if (IS_ELF
252b5132
RH		 9957#ifdef TE_PE
9958 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9959#endif
9960 )
9961 value += fixP->fx_where + fixP->fx_frag->fr_address;
9962#endif
9963#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9964 if (IS_ELF)
252b5132 9965 {
6539b54b 9966 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9967
6539b54b 9968 if ((sym_seg == seg
2f66722d 9969 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9970 && sym_seg != absolute_section))
af65af87 9971 && !generic_force_reloc (fixP))
2f66722d
AM		 9972 {
9973 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9974 bfd_install_relocation subtracts them out again. I think
9975 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9976 it. FIXME. */
9977 value += fixP->fx_where + fixP->fx_frag->fr_address;
9978 }
252b5132
RH		 9979 }
9980#endif
9981#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9982 /* For some reason, the PE format does not store a
9983 section address offset for a PC relative symbol. */
9984 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9985 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9986 value += md_pcrel_from (fixP);
9987#endif
9988 }
fbeb56a4 9989#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9990 if (fixP->fx_addsy != NULL
9991 && S_IS_WEAK (fixP->fx_addsy)
9992 /* PR 16858: Do not modify weak function references. */
9993 && ! fixP->fx_pcrel)
fbeb56a4 9994 {
296a8689
NC		 9995#if !defined (TE_PEP)
9996 /* For x86 PE weak function symbols are neither PC-relative
9997 nor do they set S_IS_FUNCTION. So the only reliable way
9998 to detect them is to check the flags of their containing
9999 section. */
10000 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10001 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10002 ;
10003 else
10004#endif
fbeb56a4
DK		 10005 value -= S_GET_VALUE (fixP->fx_addsy);
10006 }
10007#endif
252b5132
RH		 10008
10009 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10010 and we must not disappoint it. */
252b5132 10011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10012 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10013 switch (fixP->fx_r_type)
10014 {
10015 case BFD_RELOC_386_PLT32:
3e73aa7c 10016 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10017 /* Make the jump instruction point to the address of the operand. At
10018 runtime we merely add the offset to the actual PLT entry. */
10019 value = -4;
10020 break;
31312f95 10021
13ae64f3
JJ		 10022 case BFD_RELOC_386_TLS_GD:
10023 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10024 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10025 case BFD_RELOC_386_TLS_IE:
10026 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10027 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10028 case BFD_RELOC_X86_64_TLSGD:
10029 case BFD_RELOC_X86_64_TLSLD:
10030 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10031 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10032 value = 0; /* Fully resolved at runtime. No addend. */
10033 /* Fallthrough */
10034 case BFD_RELOC_386_TLS_LE:
10035 case BFD_RELOC_386_TLS_LDO_32:
10036 case BFD_RELOC_386_TLS_LE_32:
10037 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10038 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10039 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10040 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10041 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10042 break;
10043
67a4f2b7
AO		 10044 case BFD_RELOC_386_TLS_DESC_CALL:
10045 case BFD_RELOC_X86_64_TLSDESC_CALL:
10046 value = 0; /* Fully resolved at runtime. No addend. */
10047 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10048 fixP->fx_done = 0;
10049 return;
10050
47926f60
KH		 10051 case BFD_RELOC_VTABLE_INHERIT:
10052 case BFD_RELOC_VTABLE_ENTRY:
10053 fixP->fx_done = 0;
94f592af 10054 return;
47926f60
KH		 10055
10056 default:
10057 break;
10058 }
10059#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10060 *valP = value;
f86103b7 10061#endif /* !defined (TE_Mach) */
3e73aa7c 10062
3e73aa7c 10063 /* Are we finished with this relocation now? */
c6682705 10064 if (fixP->fx_addsy == NULL)
3e73aa7c 10065 fixP->fx_done = 1;
fbeb56a4
DK		 10066#if defined (OBJ_COFF) && defined (TE_PE)
10067 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10068 {
10069 fixP->fx_done = 0;
10070 /* Remember value for tc_gen_reloc. */
10071 fixP->fx_addnumber = value;
10072 /* Clear out the frag for now. */
10073 value = 0;
10074 }
10075#endif
3e73aa7c
JH		 10076 else if (use_rela_relocations)
10077 {
10078 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10079 /* Remember value for tc_gen_reloc. */
10080 fixP->fx_addnumber = value;
3e73aa7c
JH		 10081 value = 0;
10082 }
f86103b7 10083
94f592af 10084 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10085}
252b5132 10086\f
6d4af3c2 10087const char *
499ac353 10088md_atof (int type, char *litP, int *sizeP)
252b5132 10089{
499ac353
NC		 10090 /* This outputs the LITTLENUMs in REVERSE order;
10091 in accord with the bigendian 386. */
10092 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10093}
10094\f
2d545b82 10095static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10096
252b5132 10097static char *
e3bb37b5 10098output_invalid (int c)
252b5132 10099{
3882b010 10100 if (ISPRINT (c))
f9f21a03
L		 10101 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10102 "'%c'", c);
252b5132 10103 else
f9f21a03 10104 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10105 "(0x%x)", (unsigned char) c);
252b5132
RH		 10106 return output_invalid_buf;
10107}
10108
af6bdddf 10109/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10110
10111static const reg_entry *
4d1bb795 10112parse_real_register (char *reg_string, char **end_op)
252b5132 10113{
af6bdddf
AM		 10114 char *s = reg_string;
10115 char *p;
252b5132
RH		 10116 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10117 const reg_entry *r;
10118
10119 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10120 if (*s == REGISTER_PREFIX)
10121 ++s;
10122
10123 if (is_space_char (*s))
10124 ++s;
10125
10126 p = reg_name_given;
af6bdddf 10127 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10128 {
10129 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10130 return (const reg_entry *) NULL;
10131 s++;
252b5132
RH		 10132 }
10133
6588847e
DN		 10134 /* For naked regs, make sure that we are not dealing with an identifier.
10135 This prevents confusing an identifier like `eax_var' with register
10136 `eax'. */
10137 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10138 return (const reg_entry *) NULL;
10139
af6bdddf 10140 *end_op = s;
252b5132
RH		 10141
10142 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10143
5f47d35b 10144 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10145 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10146 {
5f47d35b
AM		 10147 if (is_space_char (*s))
10148 ++s;
10149 if (*s == '(')
10150 {
af6bdddf 10151 ++s;
5f47d35b
AM		 10152 if (is_space_char (*s))
10153 ++s;
10154 if (*s >= '0' && *s <= '7')
10155 {
db557034 10156 int fpr = *s - '0';
af6bdddf 10157 ++s;
5f47d35b
AM		 10158 if (is_space_char (*s))
10159 ++s;
10160 if (*s == ')')
10161 {
10162 *end_op = s + 1;
1e9cc1c2 10163 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10164 know (r);
10165 return r + fpr;
5f47d35b 10166 }
5f47d35b 10167 }
47926f60 10168 /* We have "%st(" then garbage. */
5f47d35b
AM		 10169 return (const reg_entry *) NULL;
10170 }
10171 }
10172
a60de03c
JB		 10173 if (r == NULL || allow_pseudo_reg)
10174 return r;
10175
0dfbf9d7 10176 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10177 return (const reg_entry *) NULL;
10178
dc821c5f 10179 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10180 || r->reg_type.bitfield.sreg3
10181 || r->reg_type.bitfield.control
10182 || r->reg_type.bitfield.debug
10183 || r->reg_type.bitfield.test)
10184 && !cpu_arch_flags.bitfield.cpui386)
10185 return (const reg_entry *) NULL;
10186
ca0d63fe 10187 if (r->reg_type.bitfield.tbyte
309d3373
JB		 10188 && !cpu_arch_flags.bitfield.cpu8087
10189 && !cpu_arch_flags.bitfield.cpu287
10190 && !cpu_arch_flags.bitfield.cpu387)
10191 return (const reg_entry *) NULL;
10192
1848e567 10193 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 10194 return (const reg_entry *) NULL;
10195
1b54b8d7 10196 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 10197 return (const reg_entry *) NULL;
10198
1b54b8d7 10199 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 10200 return (const reg_entry *) NULL;
10201
1b54b8d7 10202 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 10203 return (const reg_entry *) NULL;
10204
10205 if (r->reg_type.bitfield.regmask
10206 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 10207 return (const reg_entry *) NULL;
10208
db51cc60 10209 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10210 if (!allow_index_reg
db51cc60
L		 10211 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10212 return (const reg_entry *) NULL;
10213
43234a1e
L		 10214 /* Upper 16 vector register is only available with VREX in 64bit
10215 mode. */
10216 if ((r->reg_flags & RegVRex))
10217 {
86fa6981
L		 10218 if (i.vec_encoding == vex_encoding_default)
10219 i.vec_encoding = vex_encoding_evex;
10220
43234a1e 10221 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 10222 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 10223 || flag_code != CODE_64BIT)
10224 return (const reg_entry *) NULL;
43234a1e
L		 10225 }
10226
a60de03c 10227 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10228 || r->reg_type.bitfield.qword)
40fb9820 10229 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10230 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10231 && flag_code != CODE_64BIT)
20f0a1fc 10232 return (const reg_entry *) NULL;
1ae00879 10233
b7240065
JB		 10234 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10235 return (const reg_entry *) NULL;
10236
252b5132
RH		 10237 return r;
10238}
4d1bb795
JB		 10239
10240/* REG_STRING starts *before* REGISTER_PREFIX. */
10241
10242static const reg_entry *
10243parse_register (char *reg_string, char **end_op)
10244{
10245 const reg_entry *r;
10246
10247 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10248 r = parse_real_register (reg_string, end_op);
10249 else
10250 r = NULL;
10251 if (!r)
10252 {
10253 char *save = input_line_pointer;
10254 char c;
10255 symbolS *symbolP;
10256
10257 input_line_pointer = reg_string;
d02603dc 10258 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10259 symbolP = symbol_find (reg_string);
10260 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10261 {
10262 const expressionS *e = symbol_get_value_expression (symbolP);
10263
0398aac5 10264 know (e->X_op == O_register);
4eed87de 10265 know (e->X_add_number >= 0
c3fe08fa 10266 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10267 r = i386_regtab + e->X_add_number;
d3bb6b49 10268 if ((r->reg_flags & RegVRex))
86fa6981 10269 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10270 *end_op = input_line_pointer;
10271 }
10272 *input_line_pointer = c;
10273 input_line_pointer = save;
10274 }
10275 return r;
10276}
10277
10278int
10279i386_parse_name (char *name, expressionS *e, char *nextcharP)
10280{
10281 const reg_entry *r;
10282 char *end = input_line_pointer;
10283
10284 *end = *nextcharP;
10285 r = parse_register (name, &input_line_pointer);
10286 if (r && end <= input_line_pointer)
10287 {
10288 *nextcharP = *input_line_pointer;
10289 *input_line_pointer = 0;
10290 e->X_op = O_register;
10291 e->X_add_number = r - i386_regtab;
10292 return 1;
10293 }
10294 input_line_pointer = end;
10295 *end = 0;
ee86248c 10296 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10297}
10298
10299void
10300md_operand (expressionS *e)
10301{
ee86248c
JB		 10302 char *end;
10303 const reg_entry *r;
4d1bb795 10304
ee86248c
JB		 10305 switch (*input_line_pointer)
10306 {
10307 case REGISTER_PREFIX:
10308 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10309 if (r)
10310 {
10311 e->X_op = O_register;
10312 e->X_add_number = r - i386_regtab;
10313 input_line_pointer = end;
10314 }
ee86248c
JB		 10315 break;
10316
10317 case '[':
9c2799c2 10318 gas_assert (intel_syntax);
ee86248c
JB		 10319 end = input_line_pointer++;
10320 expression (e);
10321 if (*input_line_pointer == ']')
10322 {
10323 ++input_line_pointer;
10324 e->X_op_symbol = make_expr_symbol (e);
10325 e->X_add_symbol = NULL;
10326 e->X_add_number = 0;
10327 e->X_op = O_index;
10328 }
10329 else
10330 {
10331 e->X_op = O_absent;
10332 input_line_pointer = end;
10333 }
10334 break;
4d1bb795
JB		 10335 }
10336}
10337
252b5132 10338\f
4cc782b5 10339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10340const char *md_shortopts = "kVQ:sqnO::";
252b5132 10341#else
b6f8c7c4 10342const char *md_shortopts = "qnO::";
252b5132 10343#endif
6e0b89ee 10344
3e73aa7c 10345#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10346#define OPTION_64 (OPTION_MD_BASE + 1)
10347#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10348#define OPTION_MARCH (OPTION_MD_BASE + 3)
10349#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10350#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10351#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10352#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10353#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10354#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10355#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10356#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10357#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10358#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10359#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10360#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10361#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10362#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10363#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10364#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10365#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10366#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10367#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10368#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10369#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10370
99ad8390
NC		 10371struct option md_longopts[] =
10372{
3e73aa7c 10373 {"32", no_argument, NULL, OPTION_32},
321098a5 10374#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10375 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10376 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10377#endif
10378#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10379 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10380 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10381#endif
b3b91714 10382 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10383 {"march", required_argument, NULL, OPTION_MARCH},
10384 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10385 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10386 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10387 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10388 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10389 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10390 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10391 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10392 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10393 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10394 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10395 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10396# if defined (TE_PE) || defined (TE_PEP)
10397 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10398#endif
d1982f93 10399 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10400 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10401 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10402 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10403 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10404 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10405 {NULL, no_argument, NULL, 0}
10406};
10407size_t md_longopts_size = sizeof (md_longopts);
10408
10409int
17b9d67d 10410md_parse_option (int c, const char *arg)
252b5132 10411{
91d6fa6a 10412 unsigned int j;
293f5f65 10413 char *arch, *next, *saved;
9103f4f4 10414
252b5132
RH		 10415 switch (c)
10416 {
12b55ccc
L		 10417 case 'n':
10418 optimize_align_code = 0;
10419 break;
10420
a38cf1db
AM		 10421 case 'q':
10422 quiet_warnings = 1;
252b5132
RH		 10423 break;
10424
10425#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10426 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10427 should be emitted or not. FIXME: Not implemented. */
10428 case 'Q':
252b5132
RH		 10429 break;
10430
10431 /* -V: SVR4 argument to print version ID. */
10432 case 'V':
10433 print_version_id ();
10434 break;
10435
a38cf1db
AM		 10436 /* -k: Ignore for FreeBSD compatibility. */
10437 case 'k':
252b5132 10438 break;
4cc782b5
ILT		 10439
10440 case 's':
10441 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10442 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10443 break;
8dcea932
L		 10444
10445 case OPTION_MSHARED:
10446 shared = 1;
10447 break;
99ad8390 10448#endif
321098a5 10449#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10450 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10451 case OPTION_64:
10452 {
10453 const char **list, **l;
10454
3e73aa7c
JH		 10455 list = bfd_target_list ();
10456 for (l = list; *l != NULL; l++)
8620418b 10457 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10458 || strcmp (*l, "coff-x86-64") == 0
10459 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10460 || strcmp (*l, "pei-x86-64") == 0
10461 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10462 {
10463 default_arch = "x86_64";
10464 break;
10465 }
3e73aa7c 10466 if (*l == NULL)
2b5d6a91 10467 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10468 free (list);
10469 }
10470 break;
10471#endif
252b5132 10472
351f65ca 10473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10474 case OPTION_X32:
351f65ca
L		 10475 if (IS_ELF)
10476 {
10477 const char **list, **l;
10478
10479 list = bfd_target_list ();
10480 for (l = list; *l != NULL; l++)
10481 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10482 {
10483 default_arch = "x86_64:32";
10484 break;
10485 }
10486 if (*l == NULL)
2b5d6a91 10487 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10488 free (list);
10489 }
10490 else
10491 as_fatal (_("32bit x86_64 is only supported for ELF"));
10492 break;
10493#endif
10494
6e0b89ee
AM		 10495 case OPTION_32:
10496 default_arch = "i386";
10497 break;
10498
b3b91714
AM		 10499 case OPTION_DIVIDE:
10500#ifdef SVR4_COMMENT_CHARS
10501 {
10502 char *n, *t;
10503 const char *s;
10504
add39d23 10505 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10506 t = n;
10507 for (s = i386_comment_chars; *s != '\0'; s++)
10508 if (*s != '/')
10509 *t++ = *s;
10510 *t = '\0';
10511 i386_comment_chars = n;
10512 }
10513#endif
10514 break;
10515
9103f4f4 10516 case OPTION_MARCH:
293f5f65
L		 10517 saved = xstrdup (arg);
10518 arch = saved;
10519 /* Allow -march=+nosse. */
10520 if (*arch == '+')
10521 arch++;
6305a203 10522 do
9103f4f4 10523 {
6305a203 10524 if (*arch == '.')
2b5d6a91 10525 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10526 next = strchr (arch, '+');
10527 if (next)
10528 *next++ = '\0';
91d6fa6a 10529 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10530 {
91d6fa6a 10531 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10532 {
6305a203 10533 /* Processor. */
1ded5609
JB		 10534 if (! cpu_arch[j].flags.bitfield.cpui386)
10535 continue;
10536
91d6fa6a 10537 cpu_arch_name = cpu_arch[j].name;
6305a203 10538 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10539 cpu_arch_flags = cpu_arch[j].flags;
10540 cpu_arch_isa = cpu_arch[j].type;
10541 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10542 if (!cpu_arch_tune_set)
10543 {
10544 cpu_arch_tune = cpu_arch_isa;
10545 cpu_arch_tune_flags = cpu_arch_isa_flags;
10546 }
10547 break;
10548 }
91d6fa6a
NC		 10549 else if (*cpu_arch [j].name == '.'
10550 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10551 {
33eaf5de 10552 /* ISA extension. */
6305a203 10553 i386_cpu_flags flags;
309d3373 10554
293f5f65
L		 10555 flags = cpu_flags_or (cpu_arch_flags,
10556 cpu_arch[j].flags);
81486035 10557
5b64d091 10558 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10559 {
10560 if (cpu_sub_arch_name)
10561 {
10562 char *name = cpu_sub_arch_name;
10563 cpu_sub_arch_name = concat (name,
91d6fa6a 10564 cpu_arch[j].name,
1bf57e9f 10565 (const char *) NULL);
6305a203
L		 10566 free (name);
10567 }
10568 else
91d6fa6a 10569 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10570 cpu_arch_flags = flags;
a586129e 10571 cpu_arch_isa_flags = flags;
6305a203 10572 }
0089dace
L		 10573 else
10574 cpu_arch_isa_flags
10575 = cpu_flags_or (cpu_arch_isa_flags,
10576 cpu_arch[j].flags);
6305a203 10577 break;
ccc9c027 10578 }
9103f4f4 10579 }
6305a203 10580
293f5f65
L		 10581 if (j >= ARRAY_SIZE (cpu_arch))
10582 {
33eaf5de 10583 /* Disable an ISA extension. */
293f5f65
L		 10584 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10585 if (strcmp (arch, cpu_noarch [j].name) == 0)
10586 {
10587 i386_cpu_flags flags;
10588
10589 flags = cpu_flags_and_not (cpu_arch_flags,
10590 cpu_noarch[j].flags);
10591 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10592 {
10593 if (cpu_sub_arch_name)
10594 {
10595 char *name = cpu_sub_arch_name;
10596 cpu_sub_arch_name = concat (arch,
10597 (const char *) NULL);
10598 free (name);
10599 }
10600 else
10601 cpu_sub_arch_name = xstrdup (arch);
10602 cpu_arch_flags = flags;
10603 cpu_arch_isa_flags = flags;
10604 }
10605 break;
10606 }
10607
10608 if (j >= ARRAY_SIZE (cpu_noarch))
10609 j = ARRAY_SIZE (cpu_arch);
10610 }
10611
91d6fa6a 10612 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10613 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10614
10615 arch = next;
9103f4f4 10616 }
293f5f65
L		 10617 while (next != NULL);
10618 free (saved);
9103f4f4
L		 10619 break;
10620
10621 case OPTION_MTUNE:
10622 if (*arg == '.')
2b5d6a91 10623 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10624 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10625 {
91d6fa6a 10626 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10627 {
ccc9c027 10628 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10629 cpu_arch_tune = cpu_arch [j].type;
10630 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10631 break;
10632 }
10633 }
91d6fa6a 10634 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10635 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10636 break;
10637
1efbbeb4
L		 10638 case OPTION_MMNEMONIC:
10639 if (strcasecmp (arg, "att") == 0)
10640 intel_mnemonic = 0;
10641 else if (strcasecmp (arg, "intel") == 0)
10642 intel_mnemonic = 1;
10643 else
2b5d6a91 10644 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10645 break;
10646
10647 case OPTION_MSYNTAX:
10648 if (strcasecmp (arg, "att") == 0)
10649 intel_syntax = 0;
10650 else if (strcasecmp (arg, "intel") == 0)
10651 intel_syntax = 1;
10652 else
2b5d6a91 10653 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10654 break;
10655
10656 case OPTION_MINDEX_REG:
10657 allow_index_reg = 1;
10658 break;
10659
10660 case OPTION_MNAKED_REG:
10661 allow_naked_reg = 1;
10662 break;
10663
c0f3af97
L		 10664 case OPTION_MSSE2AVX:
10665 sse2avx = 1;
10666 break;
10667
daf50ae7
L		 10668 case OPTION_MSSE_CHECK:
10669 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10670 sse_check = check_error;
daf50ae7 10671 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10672 sse_check = check_warning;
daf50ae7 10673 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10674 sse_check = check_none;
daf50ae7 10675 else
2b5d6a91 10676 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10677 break;
10678
7bab8ab5
JB		 10679 case OPTION_MOPERAND_CHECK:
10680 if (strcasecmp (arg, "error") == 0)
10681 operand_check = check_error;
10682 else if (strcasecmp (arg, "warning") == 0)
10683 operand_check = check_warning;
10684 else if (strcasecmp (arg, "none") == 0)
10685 operand_check = check_none;
10686 else
10687 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10688 break;
10689
539f890d
L		 10690 case OPTION_MAVXSCALAR:
10691 if (strcasecmp (arg, "128") == 0)
10692 avxscalar = vex128;
10693 else if (strcasecmp (arg, "256") == 0)
10694 avxscalar = vex256;
10695 else
2b5d6a91 10696 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10697 break;
10698
7e8b059b
L		 10699 case OPTION_MADD_BND_PREFIX:
10700 add_bnd_prefix = 1;
10701 break;
10702
43234a1e
L		 10703 case OPTION_MEVEXLIG:
10704 if (strcmp (arg, "128") == 0)
10705 evexlig = evexl128;
10706 else if (strcmp (arg, "256") == 0)
10707 evexlig = evexl256;
10708 else if (strcmp (arg, "512") == 0)
10709 evexlig = evexl512;
10710 else
10711 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10712 break;
10713
d3d3c6db
IT		 10714 case OPTION_MEVEXRCIG:
10715 if (strcmp (arg, "rne") == 0)
10716 evexrcig = rne;
10717 else if (strcmp (arg, "rd") == 0)
10718 evexrcig = rd;
10719 else if (strcmp (arg, "ru") == 0)
10720 evexrcig = ru;
10721 else if (strcmp (arg, "rz") == 0)
10722 evexrcig = rz;
10723 else
10724 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10725 break;
10726
43234a1e
L		 10727 case OPTION_MEVEXWIG:
10728 if (strcmp (arg, "0") == 0)
10729 evexwig = evexw0;
10730 else if (strcmp (arg, "1") == 0)
10731 evexwig = evexw1;
10732 else
10733 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10734 break;
10735
167ad85b
TG		 10736# if defined (TE_PE) || defined (TE_PEP)
10737 case OPTION_MBIG_OBJ:
10738 use_big_obj = 1;
10739 break;
10740#endif
10741
d1982f93 10742 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10743 if (strcasecmp (arg, "yes") == 0)
10744 omit_lock_prefix = 1;
10745 else if (strcasecmp (arg, "no") == 0)
10746 omit_lock_prefix = 0;
10747 else
10748 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10749 break;
10750
e4e00185
AS		 10751 case OPTION_MFENCE_AS_LOCK_ADD:
10752 if (strcasecmp (arg, "yes") == 0)
10753 avoid_fence = 1;
10754 else if (strcasecmp (arg, "no") == 0)
10755 avoid_fence = 0;
10756 else
10757 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10758 break;
10759
0cb4071e
L		 10760 case OPTION_MRELAX_RELOCATIONS:
10761 if (strcasecmp (arg, "yes") == 0)
10762 generate_relax_relocations = 1;
10763 else if (strcasecmp (arg, "no") == 0)
10764 generate_relax_relocations = 0;
10765 else
10766 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10767 break;
10768
5db04b09 10769 case OPTION_MAMD64:
e89c5eaa 10770 intel64 = 0;
5db04b09
L		 10771 break;
10772
10773 case OPTION_MINTEL64:
e89c5eaa 10774 intel64 = 1;
5db04b09
L		 10775 break;
10776
b6f8c7c4
L		 10777 case 'O':
10778 if (arg == NULL)
10779 {
10780 optimize = 1;
10781 /* Turn off -Os. */
10782 optimize_for_space = 0;
10783 }
10784 else if (*arg == 's')
10785 {
10786 optimize_for_space = 1;
10787 /* Turn on all encoding optimizations. */
10788 optimize = -1;
10789 }
10790 else
10791 {
10792 optimize = atoi (arg);
10793 /* Turn off -Os. */
10794 optimize_for_space = 0;
10795 }
10796 break;
10797
252b5132
RH		 10798 default:
10799 return 0;
10800 }
10801 return 1;
10802}
10803
8a2c8fef
L		 10804#define MESSAGE_TEMPLATE \
10805" "
10806
293f5f65
L		 10807static char *
10808output_message (FILE *stream, char *p, char *message, char *start,
10809 int *left_p, const char *name, int len)
10810{
10811 int size = sizeof (MESSAGE_TEMPLATE);
10812 int left = *left_p;
10813
10814 /* Reserve 2 spaces for ", " or ",\0" */
10815 left -= len + 2;
10816
10817 /* Check if there is any room. */
10818 if (left >= 0)
10819 {
10820 if (p != start)
10821 {
10822 *p++ = ',';
10823 *p++ = ' ';
10824 }
10825 p = mempcpy (p, name, len);
10826 }
10827 else
10828 {
10829 /* Output the current message now and start a new one. */
10830 *p++ = ',';
10831 *p = '\0';
10832 fprintf (stream, "%s\n", message);
10833 p = start;
10834 left = size - (start - message) - len - 2;
10835
10836 gas_assert (left >= 0);
10837
10838 p = mempcpy (p, name, len);
10839 }
10840
10841 *left_p = left;
10842 return p;
10843}
10844
8a2c8fef 10845static void
1ded5609 10846show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10847{
10848 static char message[] = MESSAGE_TEMPLATE;
10849 char *start = message + 27;
10850 char *p;
10851 int size = sizeof (MESSAGE_TEMPLATE);
10852 int left;
10853 const char *name;
10854 int len;
10855 unsigned int j;
10856
10857 p = start;
10858 left = size - (start - message);
10859 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10860 {
10861 /* Should it be skipped? */
10862 if (cpu_arch [j].skip)
10863 continue;
10864
10865 name = cpu_arch [j].name;
10866 len = cpu_arch [j].len;
10867 if (*name == '.')
10868 {
10869 /* It is an extension. Skip if we aren't asked to show it. */
10870 if (ext)
10871 {
10872 name++;
10873 len--;
10874 }
10875 else
10876 continue;
10877 }
10878 else if (ext)
10879 {
10880 /* It is an processor. Skip if we show only extension. */
10881 continue;
10882 }
1ded5609
JB		 10883 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10884 {
10885 /* It is an impossible processor - skip. */
10886 continue;
10887 }
8a2c8fef 10888
293f5f65 10889 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10890 }
10891
293f5f65
L		 10892 /* Display disabled extensions. */
10893 if (ext)
10894 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10895 {
10896 name = cpu_noarch [j].name;
10897 len = cpu_noarch [j].len;
10898 p = output_message (stream, p, message, start, &left, name,
10899 len);
10900 }
10901
8a2c8fef
L		 10902 *p = '\0';
10903 fprintf (stream, "%s\n", message);
10904}
10905
252b5132 10906void
8a2c8fef 10907md_show_usage (FILE *stream)
252b5132 10908{
4cc782b5
ILT		 10909#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10910 fprintf (stream, _("\
a38cf1db
AM		 10911 -Q ignored\n\
10912 -V print assembler version number\n\
b3b91714
AM		 10913 -k ignored\n"));
10914#endif
10915 fprintf (stream, _("\
12b55ccc 10916 -n Do not optimize code alignment\n\
b3b91714
AM		 10917 -q quieten some warnings\n"));
10918#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10919 fprintf (stream, _("\
a38cf1db 10920 -s ignored\n"));
b3b91714 10921#endif
321098a5
L		 10922#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10923 || defined (TE_PE) || defined (TE_PEP))
751d281c 10924 fprintf (stream, _("\
570561f7 10925 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10926#endif
b3b91714
AM		 10927#ifdef SVR4_COMMENT_CHARS
10928 fprintf (stream, _("\
10929 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10930#else
10931 fprintf (stream, _("\
b3b91714 10932 --divide ignored\n"));
4cc782b5 10933#endif
9103f4f4 10934 fprintf (stream, _("\
6305a203 10935 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10936 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10937 show_arch (stream, 0, 1);
8a2c8fef
L		 10938 fprintf (stream, _("\
10939 EXTENSION is combination of:\n"));
1ded5609 10940 show_arch (stream, 1, 0);
6305a203 10941 fprintf (stream, _("\
8a2c8fef 10942 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10943 show_arch (stream, 0, 0);
ba104c83 10944 fprintf (stream, _("\
c0f3af97
L		 10945 -msse2avx encode SSE instructions with VEX prefix\n"));
10946 fprintf (stream, _("\
daf50ae7
L		 10947 -msse-check=[none|error|warning]\n\
10948 check SSE instructions\n"));
10949 fprintf (stream, _("\
7bab8ab5
JB		 10950 -moperand-check=[none|error|warning]\n\
10951 check operand combinations for validity\n"));
10952 fprintf (stream, _("\
539f890d
L		 10953 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10954 length\n"));
10955 fprintf (stream, _("\
43234a1e
L		 10956 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10957 length\n"));
10958 fprintf (stream, _("\
10959 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10960 for EVEX.W bit ignored instructions\n"));
10961 fprintf (stream, _("\
d3d3c6db
IT		 10962 -mevexrcig=[rne|rd|ru|rz]\n\
10963 encode EVEX instructions with specific EVEX.RC value\n\
10964 for SAE-only ignored instructions\n"));
10965 fprintf (stream, _("\
ba104c83
L		 10966 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10967 fprintf (stream, _("\
10968 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10969 fprintf (stream, _("\
10970 -mindex-reg support pseudo index registers\n"));
10971 fprintf (stream, _("\
10972 -mnaked-reg don't require `%%' prefix for registers\n"));
10973 fprintf (stream, _("\
7e8b059b 10974 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10975 fprintf (stream, _("\
10976 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10977# if defined (TE_PE) || defined (TE_PEP)
10978 fprintf (stream, _("\
10979 -mbig-obj generate big object files\n"));
10980#endif
d022bddd
IT		 10981 fprintf (stream, _("\
10982 -momit-lock-prefix=[no|yes]\n\
10983 strip all lock prefixes\n"));
5db04b09 10984 fprintf (stream, _("\
e4e00185
AS		 10985 -mfence-as-lock-add=[no|yes]\n\
10986 encode lfence, mfence and sfence as\n\
10987 lock addl $0x0, (%%{re}sp)\n"));
10988 fprintf (stream, _("\
0cb4071e
L		 10989 -mrelax-relocations=[no|yes]\n\
10990 generate relax relocations\n"));
10991 fprintf (stream, _("\
5db04b09
L		 10992 -mamd64 accept only AMD64 ISA\n"));
10993 fprintf (stream, _("\
10994 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10995}
10996
3e73aa7c 10997#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10998 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10999 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11000
11001/* Pick the target format to use. */
11002
47926f60 11003const char *
e3bb37b5 11004i386_target_format (void)
252b5132 11005{
351f65ca
L		 11006 if (!strncmp (default_arch, "x86_64", 6))
11007 {
11008 update_code_flag (CODE_64BIT, 1);
11009 if (default_arch[6] == '\0')
7f56bc95 11010 x86_elf_abi = X86_64_ABI;
351f65ca 11011 else
7f56bc95 11012 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11013 }
3e73aa7c 11014 else if (!strcmp (default_arch, "i386"))
78f12dd3 11015 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11016 else if (!strcmp (default_arch, "iamcu"))
11017 {
11018 update_code_flag (CODE_32BIT, 1);
11019 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11020 {
11021 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11022 cpu_arch_name = "iamcu";
11023 cpu_sub_arch_name = NULL;
11024 cpu_arch_flags = iamcu_flags;
11025 cpu_arch_isa = PROCESSOR_IAMCU;
11026 cpu_arch_isa_flags = iamcu_flags;
11027 if (!cpu_arch_tune_set)
11028 {
11029 cpu_arch_tune = cpu_arch_isa;
11030 cpu_arch_tune_flags = cpu_arch_isa_flags;
11031 }
11032 }
8d471ec1 11033 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11034 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11035 cpu_arch_name);
11036 }
3e73aa7c 11037 else
2b5d6a91 11038 as_fatal (_("unknown architecture"));
89507696
JB		 11039
11040 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11041 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11042 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11043 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11044
252b5132
RH		 11045 switch (OUTPUT_FLAVOR)
11046 {
9384f2ff 11047#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11048 case bfd_target_aout_flavour:
47926f60 11049 return AOUT_TARGET_FORMAT;
4c63da97 11050#endif
9384f2ff
AM		 11051#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11052# if defined (TE_PE) || defined (TE_PEP)
11053 case bfd_target_coff_flavour:
167ad85b
TG		 11054 if (flag_code == CODE_64BIT)
11055 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11056 else
11057 return "pe-i386";
9384f2ff 11058# elif defined (TE_GO32)
0561d57c
JK		 11059 case bfd_target_coff_flavour:
11060 return "coff-go32";
9384f2ff 11061# else
252b5132
RH		 11062 case bfd_target_coff_flavour:
11063 return "coff-i386";
9384f2ff 11064# endif
4c63da97 11065#endif
3e73aa7c 11066#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11067 case bfd_target_elf_flavour:
3e73aa7c 11068 {
351f65ca
L		 11069 const char *format;
11070
11071 switch (x86_elf_abi)
4fa24527 11072 {
351f65ca
L		 11073 default:
11074 format = ELF_TARGET_FORMAT;
11075 break;
7f56bc95 11076 case X86_64_ABI:
351f65ca 11077 use_rela_relocations = 1;
4fa24527 11078 object_64bit = 1;
351f65ca
L		 11079 format = ELF_TARGET_FORMAT64;
11080 break;
7f56bc95 11081 case X86_64_X32_ABI:
4fa24527 11082 use_rela_relocations = 1;
351f65ca 11083 object_64bit = 1;
862be3fb 11084 disallow_64bit_reloc = 1;
351f65ca
L		 11085 format = ELF_TARGET_FORMAT32;
11086 break;
4fa24527 11087 }
3632d14b 11088 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11089 {
7f56bc95 11090 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11091 as_fatal (_("Intel L1OM is 64bit only"));
11092 return ELF_TARGET_L1OM_FORMAT;
11093 }
b49f93f6 11094 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11095 {
11096 if (x86_elf_abi != X86_64_ABI)
11097 as_fatal (_("Intel K1OM is 64bit only"));
11098 return ELF_TARGET_K1OM_FORMAT;
11099 }
81486035
L		 11100 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11101 {
11102 if (x86_elf_abi != I386_ABI)
11103 as_fatal (_("Intel MCU is 32bit only"));
11104 return ELF_TARGET_IAMCU_FORMAT;
11105 }
8a9036a4 11106 else
351f65ca 11107 return format;
3e73aa7c 11108 }
e57f8c65
TG		 11109#endif
11110#if defined (OBJ_MACH_O)
11111 case bfd_target_mach_o_flavour:
d382c579
TG		 11112 if (flag_code == CODE_64BIT)
11113 {
11114 use_rela_relocations = 1;
11115 object_64bit = 1;
11116 return "mach-o-x86-64";
11117 }
11118 else
11119 return "mach-o-i386";
4c63da97 11120#endif
252b5132
RH		 11121 default:
11122 abort ();
11123 return NULL;
11124 }
11125}
11126
47926f60 11127#endif /* OBJ_MAYBE_ more than one */
252b5132 11128\f
252b5132 11129symbolS *
7016a5d5 11130md_undefined_symbol (char *name)
252b5132 11131{
18dc2407
ILT		 11132 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11133 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11134 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11135 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11136 {
11137 if (!GOT_symbol)
11138 {
11139 if (symbol_find (name))
11140 as_bad (_("GOT already in symbol table"));
11141 GOT_symbol = symbol_new (name, undefined_section,
11142 (valueT) 0, &zero_address_frag);
11143 };
11144 return GOT_symbol;
11145 }
252b5132
RH		 11146 return 0;
11147}
11148
11149/* Round up a section size to the appropriate boundary. */
47926f60 11150
252b5132 11151valueT
7016a5d5 11152md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11153{
4c63da97
AM		 11154#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11155 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11156 {
11157 /* For a.out, force the section size to be aligned. If we don't do
11158 this, BFD will align it for us, but it will not write out the
11159 final bytes of the section. This may be a bug in BFD, but it is
11160 easier to fix it here since that is how the other a.out targets
11161 work. */
11162 int align;
11163
11164 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11165 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11166 }
252b5132
RH		 11167#endif
11168
11169 return size;
11170}
11171
11172/* On the i386, PC-relative offsets are relative to the start of the
11173 next instruction. That is, the address of the offset, plus its
11174 size, since the offset is always the last part of the insn. */
11175
11176long
e3bb37b5 11177md_pcrel_from (fixS *fixP)
252b5132
RH		 11178{
11179 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11180}
11181
11182#ifndef I386COFF
11183
11184static void
e3bb37b5 11185s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11186{
29b0f896 11187 int temp;
252b5132 11188
8a75718c
JB		 11189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11190 if (IS_ELF)
11191 obj_elf_section_change_hook ();
11192#endif
252b5132
RH		 11193 temp = get_absolute_expression ();
11194 subseg_set (bss_section, (subsegT) temp);
11195 demand_empty_rest_of_line ();
11196}
11197
11198#endif
11199
252b5132 11200void
e3bb37b5 11201i386_validate_fix (fixS *fixp)
252b5132 11202{
02a86693 11203 if (fixp->fx_subsy)
252b5132 11204 {
02a86693 11205 if (fixp->fx_subsy == GOT_symbol)
23df1078 11206 {
02a86693
L		 11207 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11208 {
11209 if (!object_64bit)
11210 abort ();
11211#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11212 if (fixp->fx_tcbit2)
56ceb5b5
L		 11213 fixp->fx_r_type = (fixp->fx_tcbit
11214 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11215 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11216 else
11217#endif
11218 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11219 }
d6ab8113 11220 else
02a86693
L		 11221 {
11222 if (!object_64bit)
11223 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11224 else
11225 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11226 }
11227 fixp->fx_subsy = 0;
23df1078 11228 }
252b5132 11229 }
02a86693
L		 11230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11231 else if (!object_64bit)
11232 {
11233 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11234 && fixp->fx_tcbit2)
11235 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11236 }
11237#endif
252b5132
RH		 11238}
11239
252b5132 11240arelent *
7016a5d5 11241tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11242{
11243 arelent *rel;
11244 bfd_reloc_code_real_type code;
11245
11246 switch (fixp->fx_r_type)
11247 {
8ce3d284 11248#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11249 case BFD_RELOC_SIZE32:
11250 case BFD_RELOC_SIZE64:
11251 if (S_IS_DEFINED (fixp->fx_addsy)
11252 && !S_IS_EXTERNAL (fixp->fx_addsy))
11253 {
11254 /* Resolve size relocation against local symbol to size of
11255 the symbol plus addend. */
11256 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11257 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11258 && !fits_in_unsigned_long (value))
11259 as_bad_where (fixp->fx_file, fixp->fx_line,
11260 _("symbol size computation overflow"));
11261 fixp->fx_addsy = NULL;
11262 fixp->fx_subsy = NULL;
11263 md_apply_fix (fixp, (valueT *) &value, NULL);
11264 return NULL;
11265 }
8ce3d284 11266#endif
1a0670f3 11267 /* Fall through. */
8fd4256d 11268
3e73aa7c
JH		 11269 case BFD_RELOC_X86_64_PLT32:
11270 case BFD_RELOC_X86_64_GOT32:
11271 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11272 case BFD_RELOC_X86_64_GOTPCRELX:
11273 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11274 case BFD_RELOC_386_PLT32:
11275 case BFD_RELOC_386_GOT32:
02a86693 11276 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11277 case BFD_RELOC_386_GOTOFF:
11278 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11279 case BFD_RELOC_386_TLS_GD:
11280 case BFD_RELOC_386_TLS_LDM:
11281 case BFD_RELOC_386_TLS_LDO_32:
11282 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11283 case BFD_RELOC_386_TLS_IE:
11284 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11285 case BFD_RELOC_386_TLS_LE_32:
11286 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11287 case BFD_RELOC_386_TLS_GOTDESC:
11288 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11289 case BFD_RELOC_X86_64_TLSGD:
11290 case BFD_RELOC_X86_64_TLSLD:
11291 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11292 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11293 case BFD_RELOC_X86_64_GOTTPOFF:
11294 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11295 case BFD_RELOC_X86_64_TPOFF64:
11296 case BFD_RELOC_X86_64_GOTOFF64:
11297 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11298 case BFD_RELOC_X86_64_GOT64:
11299 case BFD_RELOC_X86_64_GOTPCREL64:
11300 case BFD_RELOC_X86_64_GOTPC64:
11301 case BFD_RELOC_X86_64_GOTPLT64:
11302 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11303 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11304 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11305 case BFD_RELOC_RVA:
11306 case BFD_RELOC_VTABLE_ENTRY:
11307 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11308#ifdef TE_PE
11309 case BFD_RELOC_32_SECREL:
11310#endif
252b5132
RH		 11311 code = fixp->fx_r_type;
11312 break;
dbbaec26
L		 11313 case BFD_RELOC_X86_64_32S:
11314 if (!fixp->fx_pcrel)
11315 {
11316 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11317 code = fixp->fx_r_type;
11318 break;
11319 }
1a0670f3 11320 /* Fall through. */
252b5132 11321 default:
93382f6d 11322 if (fixp->fx_pcrel)
252b5132 11323 {
93382f6d
AM		 11324 switch (fixp->fx_size)
11325 {
11326 default:
b091f402
AM		 11327 as_bad_where (fixp->fx_file, fixp->fx_line,
11328 _("can not do %d byte pc-relative relocation"),
11329 fixp->fx_size);
93382f6d
AM		 11330 code = BFD_RELOC_32_PCREL;
11331 break;
11332 case 1: code = BFD_RELOC_8_PCREL; break;
11333 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11334 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11335#ifdef BFD64
11336 case 8: code = BFD_RELOC_64_PCREL; break;
11337#endif
93382f6d
AM		 11338 }
11339 }
11340 else
11341 {
11342 switch (fixp->fx_size)
11343 {
11344 default:
b091f402
AM		 11345 as_bad_where (fixp->fx_file, fixp->fx_line,
11346 _("can not do %d byte relocation"),
11347 fixp->fx_size);
93382f6d
AM		 11348 code = BFD_RELOC_32;
11349 break;
11350 case 1: code = BFD_RELOC_8; break;
11351 case 2: code = BFD_RELOC_16; break;
11352 case 4: code = BFD_RELOC_32; break;
937149dd 11353#ifdef BFD64
3e73aa7c 11354 case 8: code = BFD_RELOC_64; break;
937149dd 11355#endif
93382f6d 11356 }
252b5132
RH		 11357 }
11358 break;
11359 }
252b5132 11360
d182319b
JB		 11361 if ((code == BFD_RELOC_32
11362 || code == BFD_RELOC_32_PCREL
11363 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11364 && GOT_symbol
11365 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11366 {
4fa24527 11367 if (!object_64bit)
d6ab8113
JB		 11368 code = BFD_RELOC_386_GOTPC;
11369 else
11370 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11371 }
7b81dfbb
AJ		 11372 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11373 && GOT_symbol
11374 && fixp->fx_addsy == GOT_symbol)
11375 {
11376 code = BFD_RELOC_X86_64_GOTPC64;
11377 }
252b5132 11378
add39d23
TS		 11379 rel = XNEW (arelent);
11380 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11381 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11382
11383 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11384
3e73aa7c
JH		 11385 if (!use_rela_relocations)
11386 {
11387 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11388 vtable entry to be used in the relocation's section offset. */
11389 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11390 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11391#if defined (OBJ_COFF) && defined (TE_PE)
11392 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11393 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11394 else
11395#endif
c6682705 11396 rel->addend = 0;
3e73aa7c
JH		 11397 }
11398 /* Use the rela in 64bit mode. */
252b5132 11399 else
3e73aa7c 11400 {
862be3fb
L		 11401 if (disallow_64bit_reloc)
11402 switch (code)
11403 {
862be3fb
L		 11404 case BFD_RELOC_X86_64_DTPOFF64:
11405 case BFD_RELOC_X86_64_TPOFF64:
11406 case BFD_RELOC_64_PCREL:
11407 case BFD_RELOC_X86_64_GOTOFF64:
11408 case BFD_RELOC_X86_64_GOT64:
11409 case BFD_RELOC_X86_64_GOTPCREL64:
11410 case BFD_RELOC_X86_64_GOTPC64:
11411 case BFD_RELOC_X86_64_GOTPLT64:
11412 case BFD_RELOC_X86_64_PLTOFF64:
11413 as_bad_where (fixp->fx_file, fixp->fx_line,
11414 _("cannot represent relocation type %s in x32 mode"),
11415 bfd_get_reloc_code_name (code));
11416 break;
11417 default:
11418 break;
11419 }
11420
062cd5e7
AS		 11421 if (!fixp->fx_pcrel)
11422 rel->addend = fixp->fx_offset;
11423 else
11424 switch (code)
11425 {
11426 case BFD_RELOC_X86_64_PLT32:
11427 case BFD_RELOC_X86_64_GOT32:
11428 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11429 case BFD_RELOC_X86_64_GOTPCRELX:
11430 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11431 case BFD_RELOC_X86_64_TLSGD:
11432 case BFD_RELOC_X86_64_TLSLD:
11433 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11434 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11435 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11436 rel->addend = fixp->fx_offset - fixp->fx_size;
11437 break;
11438 default:
11439 rel->addend = (section->vma
11440 - fixp->fx_size
11441 + fixp->fx_addnumber
11442 + md_pcrel_from (fixp));
11443 break;
11444 }
3e73aa7c
JH		 11445 }
11446
252b5132
RH		 11447 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11448 if (rel->howto == NULL)
11449 {
11450 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11451 _("cannot represent relocation type %s"),
252b5132
RH		 11452 bfd_get_reloc_code_name (code));
11453 /* Set howto to a garbage value so that we can keep going. */
11454 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11455 gas_assert (rel->howto != NULL);
252b5132
RH		 11456 }
11457
11458 return rel;
11459}
11460
ee86248c 11461#include "tc-i386-intel.c"
54cfded0 11462
a60de03c
JB		 11463void
11464tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11465{
a60de03c
JB		 11466 int saved_naked_reg;
11467 char saved_register_dot;
54cfded0 11468
a60de03c
JB		 11469 saved_naked_reg = allow_naked_reg;
11470 allow_naked_reg = 1;
11471 saved_register_dot = register_chars['.'];
11472 register_chars['.'] = '.';
11473 allow_pseudo_reg = 1;
11474 expression_and_evaluate (exp);
11475 allow_pseudo_reg = 0;
11476 register_chars['.'] = saved_register_dot;
11477 allow_naked_reg = saved_naked_reg;
11478
e96d56a1 11479 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11480 {
a60de03c
JB		 11481 if ((addressT) exp->X_add_number < i386_regtab_size)
11482 {
11483 exp->X_op = O_constant;
11484 exp->X_add_number = i386_regtab[exp->X_add_number]
11485 .dw2_regnum[flag_code >> 1];
11486 }
11487 else
11488 exp->X_op = O_illegal;
54cfded0 11489 }
54cfded0
AM		 11490}
11491
11492void
11493tc_x86_frame_initial_instructions (void)
11494{
a60de03c
JB		 11495 static unsigned int sp_regno[2];
11496
11497 if (!sp_regno[flag_code >> 1])
11498 {
11499 char *saved_input = input_line_pointer;
11500 char sp[][4] = {"esp", "rsp"};
11501 expressionS exp;
a4447b93 11502
a60de03c
JB		 11503 input_line_pointer = sp[flag_code >> 1];
11504 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11505 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11506 sp_regno[flag_code >> 1] = exp.X_add_number;
11507 input_line_pointer = saved_input;
11508 }
a4447b93 11509
61ff971f
L		 11510 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11511 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11512}
d2b2c203 11513
d7921315
L		 11514int
11515x86_dwarf2_addr_size (void)
11516{
11517#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11518 if (x86_elf_abi == X86_64_X32_ABI)
11519 return 4;
11520#endif
11521 return bfd_arch_bits_per_address (stdoutput) / 8;
11522}
11523
d2b2c203
DJ		 11524int
11525i386_elf_section_type (const char *str, size_t len)
11526{
11527 if (flag_code == CODE_64BIT
11528 && len == sizeof ("unwind") - 1
11529 && strncmp (str, "unwind", 6) == 0)
11530 return SHT_X86_64_UNWIND;
11531
11532 return -1;
11533}
bb41ade5 11534
ad5fec3b
EB		 11535#ifdef TE_SOLARIS
11536void
11537i386_solaris_fix_up_eh_frame (segT sec)
11538{
11539 if (flag_code == CODE_64BIT)
11540 elf_section_type (sec) = SHT_X86_64_UNWIND;
11541}
11542#endif
11543
bb41ade5
AM		 11544#ifdef TE_PE
11545void
11546tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11547{
91d6fa6a 11548 expressionS exp;
bb41ade5 11549
91d6fa6a
NC		 11550 exp.X_op = O_secrel;
11551 exp.X_add_symbol = symbol;
11552 exp.X_add_number = 0;
11553 emit_expr (&exp, size);
bb41ade5
AM		 11554}
11555#endif
3b22753a
L		 11556
11557#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11558/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11559
01e1a5bc 11560bfd_vma
6d4af3c2 11561x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11562{
11563 if (flag_code == CODE_64BIT)
11564 {
11565 if (letter == 'l')
11566 return SHF_X86_64_LARGE;
11567
8f3bae45 11568 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11569 }
3b22753a 11570 else
8f3bae45 11571 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11572 return -1;
11573}
11574
01e1a5bc 11575bfd_vma
3b22753a
L		 11576x86_64_section_word (char *str, size_t len)
11577{
8620418b 11578 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11579 return SHF_X86_64_LARGE;
11580
11581 return -1;
11582}
11583
11584static void
11585handle_large_common (int small ATTRIBUTE_UNUSED)
11586{
11587 if (flag_code != CODE_64BIT)
11588 {
11589 s_comm_internal (0, elf_common_parse);
11590 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11591 }
11592 else
11593 {
11594 static segT lbss_section;
11595 asection *saved_com_section_ptr = elf_com_section_ptr;
11596 asection *saved_bss_section = bss_section;
11597
11598 if (lbss_section == NULL)
11599 {
11600 flagword applicable;
11601 segT seg = now_seg;
11602 subsegT subseg = now_subseg;
11603
11604 /* The .lbss section is for local .largecomm symbols. */
11605 lbss_section = subseg_new (".lbss", 0);
11606 applicable = bfd_applicable_section_flags (stdoutput);
11607 bfd_set_section_flags (stdoutput, lbss_section,
11608 applicable & SEC_ALLOC);
11609 seg_info (lbss_section)->bss = 1;
11610
11611 subseg_set (seg, subseg);
11612 }
11613
11614 elf_com_section_ptr = &_bfd_elf_large_com_section;
11615 bss_section = lbss_section;
11616
11617 s_comm_internal (0, elf_common_parse);
11618
11619 elf_com_section_ptr = saved_com_section_ptr;
11620 bss_section = saved_bss_section;
11621 }
11622}
11623#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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