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2007-01-03 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
81static void swap_imm_operands (void);
82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
92static int process_operands (void);
93static const seg_entry *build_modrm_byte (void);
94static void output_insn (void);
95static void output_imm (fragS *, offsetT);
96static void output_disp (fragS *, offsetT);
29b0f896 97#ifndef I386COFF
e3bb37b5 98static void s_bss (int);
252b5132 99#endif
17d4e2a2
L		 100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101static void handle_large_common (int small ATTRIBUTE_UNUSED);
102#endif
252b5132 103
a847613f 104static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 105
252b5132 106/* 'md_assemble ()' gathers together information and puts it into a
47926f60 107 i386_insn. */
252b5132 108
520dc8e8
AM		 109union i386_op
110 {
111 expressionS *disps;
112 expressionS *imms;
113 const reg_entry *regs;
114 };
115
252b5132
RH		 116struct _i386_insn
117 {
47926f60 118 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 119 template tm;
120
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
123 char suffix;
124
47926f60 125 /* OPERANDS gives the number of given operands. */
252b5132
RH		 126 unsigned int operands;
127
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
47926f60 130 operands. */
252b5132
RH		 131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132
133 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 134 use OP[i] for the corresponding operand. */
252b5132
RH		 135 unsigned int types[MAX_OPERANDS];
136
520dc8e8
AM		 137 /* Displacement expression, immediate expression, or register for each
138 operand. */
139 union i386_op op[MAX_OPERANDS];
252b5132 140
3e73aa7c
JH		 141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143#define Operand_PCrel 1
144
252b5132 145 /* Relocation type for operand */
f86103b7 146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 147
252b5132
RH		 148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
153
154 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 155 explicit segment overrides are given. */
ce8a8b2f 156 const seg_entry *seg[2];
252b5132
RH		 157
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
162
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
165
166 modrm_byte rm;
3e73aa7c 167 rex_byte rex;
252b5132
RH		 168 sib_byte sib;
169 };
170
171typedef struct _i386_insn i386_insn;
172
173/* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
32137342 175const char extra_symbol_chars[] = "*%-(["
252b5132 176#ifdef LEX_AT
32137342
NC		 177 "@"
178#endif
179#ifdef LEX_QM
180 "?"
252b5132 181#endif
32137342 182 ;
252b5132 183
29b0f896
AM		 184#if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 186 && !defined (TE_GNU) \
29b0f896 187 && !defined (TE_LINUX) \
32137342 188 && !defined (TE_NETWARE) \
29b0f896
AM		 189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
252b5132 191/* This array holds the chars that always start a comment. If the
b3b91714
AM		 192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194const char *i386_comment_chars = "#/";
195#define SVR4_COMMENT_CHARS 1
252b5132 196#define PREFIX_SEPARATOR '\\'
252b5132 197
b3b91714
AM		 198#else
199const char *i386_comment_chars = "#";
200#define PREFIX_SEPARATOR '/'
201#endif
202
252b5132
RH		 203/* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 207 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
252b5132 210 '/' isn't otherwise defined. */
b3b91714 211const char line_comment_chars[] = "#/";
252b5132 212
63a0b638 213const char line_separator_chars[] = ";";
252b5132 214
ce8a8b2f
AM		 215/* Chars that can be used to separate mant from exp in floating point
216 nums. */
252b5132
RH		 217const char EXP_CHARS[] = "eE";
218
ce8a8b2f
AM		 219/* Chars that mean this number is a floating point constant
220 As in 0f12.456
221 or 0d1.2345e12. */
252b5132
RH		 222const char FLT_CHARS[] = "fFdDxX";
223
ce8a8b2f 224/* Tables for lexical analysis. */
252b5132
RH		 225static char mnemonic_chars[256];
226static char register_chars[256];
227static char operand_chars[256];
228static char identifier_chars[256];
229static char digit_chars[256];
230
ce8a8b2f 231/* Lexical macros. */
252b5132
RH		 232#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233#define is_operand_char(x) (operand_chars[(unsigned char) x])
234#define is_register_char(x) (register_chars[(unsigned char) x])
235#define is_space_char(x) ((x) == ' ')
236#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237#define is_digit_char(x) (digit_chars[(unsigned char) x])
238
0234cb7c 239/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 240static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241
242/* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
47926f60 245 assembler instruction). */
252b5132 246static char save_stack[32];
ce8a8b2f 247static char *save_stack_p;
252b5132
RH		 248#define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250#define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
252
47926f60 253/* The instruction we're assembling. */
252b5132
RH		 254static i386_insn i;
255
256/* Possible templates for current insn. */
257static const templates *current_templates;
258
31b2323c
L		 259/* Per instruction expressionS buffers: max displacements & immediates. */
260static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 262
47926f60
KH		 263/* Current operand we are working on. */
264static int this_operand;
252b5132 265
3e73aa7c
JH		 266/* We support four different modes. FLAG_CODE variable is used to distinguish
267 these. */
268
269enum flag_code {
270 CODE_32BIT,
271 CODE_16BIT,
272 CODE_64BIT };
f3c180ae 273#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 274
275static enum flag_code flag_code;
4fa24527 276static unsigned int object_64bit;
3e73aa7c
JH		 277static int use_rela_relocations = 0;
278
279/* The names used to print error messages. */
b77a7acd 280static const char *flag_code_names[] =
3e73aa7c
JH		 281 {
282 "32",
283 "16",
284 "64"
285 };
252b5132 286
47926f60
KH		 287/* 1 for intel syntax,
288 0 if att syntax. */
289static int intel_syntax = 0;
252b5132 290
47926f60
KH		 291/* 1 if register prefix % not required. */
292static int allow_naked_reg = 0;
252b5132 293
47926f60
KH		 294/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
295 leave, push, and pop instructions so that gcc has the same stack
296 frame as in 32 bit mode. */
297static char stackop_size = '\0';
eecb386c 298
12b55ccc
L		 299/* Non-zero to optimize code alignment. */
300int optimize_align_code = 1;
301
47926f60
KH		 302/* Non-zero to quieten some warnings. */
303static int quiet_warnings = 0;
a38cf1db 304
47926f60
KH		 305/* CPU name. */
306static const char *cpu_arch_name = NULL;
5c6af06e 307static const char *cpu_sub_arch_name = NULL;
a38cf1db 308
47926f60 309/* CPU feature flags. */
29b0f896 310static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 311
ccc9c027
L		 312/* If we have selected a cpu we are generating instructions for. */
313static int cpu_arch_tune_set = 0;
314
9103f4f4
L		 315/* Cpu we are generating instructions for. */
316static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
317
318/* CPU feature flags of cpu we are generating instructions for. */
319static unsigned int cpu_arch_tune_flags = 0;
320
ccc9c027
L		 321/* CPU instruction set architecture used. */
322static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
323
9103f4f4
L		 324/* CPU feature flags of instruction set architecture used. */
325static unsigned int cpu_arch_isa_flags = 0;
326
fddf5b5b
AM		 327/* If set, conditional jumps are not automatically promoted to handle
328 larger than a byte offset. */
329static unsigned int no_cond_jump_promotion = 0;
330
29b0f896 331/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 332static symbolS *GOT_symbol;
29b0f896 333
a4447b93
RH		 334/* The dwarf2 return column, adjusted for 32 or 64 bit. */
335unsigned int x86_dwarf2_return_column;
336
337/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
338int x86_cie_data_alignment;
339
252b5132 340/* Interface to relax_segment.
fddf5b5b
AM		 341 There are 3 major relax states for 386 jump insns because the
342 different types of jumps add different sizes to frags when we're
343 figuring out what sort of jump to choose to reach a given label. */
252b5132 344
47926f60 345/* Types. */
93c2a809
AM		 346#define UNCOND_JUMP 0
347#define COND_JUMP 1
348#define COND_JUMP86 2
fddf5b5b 349
47926f60 350/* Sizes. */
252b5132
RH		 351#define CODE16 1
352#define SMALL 0
29b0f896 353#define SMALL16 (SMALL | CODE16)
252b5132 354#define BIG 2
29b0f896 355#define BIG16 (BIG | CODE16)
252b5132
RH		 356
357#ifndef INLINE
358#ifdef __GNUC__
359#define INLINE __inline__
360#else
361#define INLINE
362#endif
363#endif
364
fddf5b5b
AM		 365#define ENCODE_RELAX_STATE(type, size) \
366 ((relax_substateT) (((type) << 2) | (size)))
367#define TYPE_FROM_RELAX_STATE(s) \
368 ((s) >> 2)
369#define DISP_SIZE_FROM_RELAX_STATE(s) \
370 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 371
372/* This table is used by relax_frag to promote short jumps to long
373 ones where necessary. SMALL (short) jumps may be promoted to BIG
374 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
375 don't allow a short jump in a 32 bit code segment to be promoted to
376 a 16 bit offset jump because it's slower (requires data size
377 prefix), and doesn't work, unless the destination is in the bottom
378 64k of the code segment (The top 16 bits of eip are zeroed). */
379
380const relax_typeS md_relax_table[] =
381{
24eab124
AM		 382 /* The fields are:
383 1) most positive reach of this state,
384 2) most negative reach of this state,
93c2a809 385 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 386 4) which index into the table to try if we can't fit into this one. */
252b5132 387
fddf5b5b 388 /* UNCOND_JUMP states. */
93c2a809
AM		 389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
391 /* dword jmp adds 4 bytes to frag:
392 0 extra opcode bytes, 4 displacement bytes. */
252b5132 393 {0, 0, 4, 0},
93c2a809
AM		 394 /* word jmp adds 2 byte2 to frag:
395 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 396 {0, 0, 2, 0},
397
93c2a809
AM		 398 /* COND_JUMP states. */
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
401 /* dword conditionals adds 5 bytes to frag:
402 1 extra opcode byte, 4 displacement bytes. */
403 {0, 0, 5, 0},
fddf5b5b 404 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 405 1 extra opcode byte, 2 displacement bytes. */
406 {0, 0, 3, 0},
407
408 /* COND_JUMP86 states. */
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
411 /* dword conditionals adds 5 bytes to frag:
412 1 extra opcode byte, 4 displacement bytes. */
413 {0, 0, 5, 0},
414 /* word conditionals add 4 bytes to frag:
415 1 displacement byte and a 3 byte long branch insn. */
416 {0, 0, 4, 0}
252b5132
RH		 417};
418
9103f4f4
L		 419static const arch_entry cpu_arch[] =
420{
421 {"generic32", PROCESSOR_GENERIC32,
d32cad65 422 Cpu186|Cpu286|Cpu386},
9103f4f4 423 {"generic64", PROCESSOR_GENERIC64,
d32cad65 424 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 425 |CpuMMX2|CpuSSE|CpuSSE2},
426 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 427 0},
9103f4f4 428 {"i186", PROCESSOR_UNKNOWN,
d32cad65 429 Cpu186},
9103f4f4 430 {"i286", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186|Cpu286},
9103f4f4 432 {"i386", PROCESSOR_GENERIC32,
d32cad65 433 Cpu186|Cpu286|Cpu386},
9103f4f4 434 {"i486", PROCESSOR_I486,
d32cad65 435 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 436 {"i586", PROCESSOR_PENTIUM,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 438 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 440 {"pentium", PROCESSOR_PENTIUM,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 442 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 444 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 446 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 448 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 450 |CpuMMX2|CpuSSE|CpuSSE2},
451 {"prescott", PROCESSOR_NOCONA,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 453 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
454 {"nocona", PROCESSOR_NOCONA,
d32cad65 455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 457 {"yonah", PROCESSOR_CORE,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 460 {"core", PROCESSOR_CORE,
d32cad65 461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
463 {"merom", PROCESSOR_CORE2,
464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
466 {"core2", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 469 {"k6", PROCESSOR_K6,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 471 {"k6_2", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 473 {"athlon", PROCESSOR_ATHLON,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 475 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
476 {"sledgehammer", PROCESSOR_K8,
d32cad65 477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 478 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
479 {"opteron", PROCESSOR_K8,
d32cad65 480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"k8", PROCESSOR_K8,
d32cad65 483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 485 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
487 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
488 |CpuABM},
9103f4f4
L		 489 {".mmx", PROCESSOR_UNKNOWN,
490 CpuMMX},
491 {".sse", PROCESSOR_UNKNOWN,
492 CpuMMX|CpuMMX2|CpuSSE},
493 {".sse2", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
495 {".sse3", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 497 {".ssse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 499 {".3dnow", PROCESSOR_UNKNOWN,
500 CpuMMX|Cpu3dnow},
501 {".3dnowa", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
503 {".padlock", PROCESSOR_UNKNOWN,
504 CpuPadLock},
505 {".pacifica", PROCESSOR_UNKNOWN,
506 CpuSVME},
507 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 508 CpuSVME},
509 {".sse4a", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
511 {".abm", PROCESSOR_UNKNOWN,
512 CpuABM}
e413e4e9
AM		 513};
514
29b0f896
AM		 515const pseudo_typeS md_pseudo_table[] =
516{
517#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
518 {"align", s_align_bytes, 0},
519#else
520 {"align", s_align_ptwo, 0},
521#endif
522 {"arch", set_cpu_arch, 0},
523#ifndef I386COFF
524 {"bss", s_bss, 0},
525#endif
526 {"ffloat", float_cons, 'f'},
527 {"dfloat", float_cons, 'd'},
528 {"tfloat", float_cons, 'x'},
529 {"value", cons, 2},
d182319b 530 {"slong", signed_cons, 4},
29b0f896
AM		 531 {"noopt", s_ignore, 0},
532 {"optim", s_ignore, 0},
533 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
534 {"code16", set_code_flag, CODE_16BIT},
535 {"code32", set_code_flag, CODE_32BIT},
536 {"code64", set_code_flag, CODE_64BIT},
537 {"intel_syntax", set_intel_syntax, 1},
538 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 539#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common, 0},
07a53e5c 541#else
e3bb37b5 542 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 543 {"loc", dwarf2_directive_loc, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 545#endif
6482c264
NC		 546#ifdef TE_PE
547 {"secrel32", pe_directive_secrel, 0},
548#endif
29b0f896
AM		 549 {0, 0, 0}
550};
551
552/* For interface with expression (). */
553extern char *input_line_pointer;
554
555/* Hash table for instruction mnemonic lookup. */
556static struct hash_control *op_hash;
557
558/* Hash table for register lookup. */
559static struct hash_control *reg_hash;
560\f
252b5132 561void
e3bb37b5 562i386_align_code (fragS *fragP, int count)
252b5132 563{
ce8a8b2f
AM		 564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
252b5132
RH		 567 static const char f32_1[] =
568 {0x90}; /* nop */
569 static const char f32_2[] =
ccc9c027 570 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 571 static const char f32_3[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5[] =
576 {0x90, /* nop */
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8[] =
583 {0x90, /* nop */
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_15[] =
604 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
605 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 606 static const char f16_3[] =
607 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 608 static const char f16_4[] =
609 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_5[] =
611 {0x90, /* nop */
612 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_6[] =
614 {0x89,0xf6, /* mov %si,%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_7[] =
617 {0x8d,0x74,0x00, /* lea 0(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_8[] =
620 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char *const f32_patt[] = {
623 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
624 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
625 };
626 static const char *const f16_patt[] = {
c3332e24 627 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 628 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
629 };
ccc9c027
L		 630 /* nopl (%[re]ax) */
631 static const char alt_3[] =
632 {0x0f,0x1f,0x00};
633 /* nopl 0(%[re]ax) */
634 static const char alt_4[] =
635 {0x0f,0x1f,0x40,0x00};
636 /* nopl 0(%[re]ax,%[re]ax,1) */
637 static const char alt_5[] =
638 {0x0f,0x1f,0x44,0x00,0x00};
639 /* nopw 0(%[re]ax,%[re]ax,1) */
640 static const char alt_6[] =
641 {0x66,0x0f,0x1f,0x44,0x00,0x00};
642 /* nopl 0L(%[re]ax) */
643 static const char alt_7[] =
644 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
645 /* nopl 0L(%[re]ax,%[re]ax,1) */
646 static const char alt_8[] =
647 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
648 /* nopw 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_9[] =
650 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
652 static const char alt_10[] =
653 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* data16
655 nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_long_11[] =
657 {0x66,
658 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* data16
660 data16
661 nopw %cs:0L(%[re]ax,%[re]ax,1) */
662 static const char alt_long_12[] =
663 {0x66,
664 0x66,
665 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
666 /* data16
667 data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_13[] =
671 {0x66,
672 0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 data16
679 nopw %cs:0L(%[re]ax,%[re]ax,1) */
680 static const char alt_long_14[] =
681 {0x66,
682 0x66,
683 0x66,
684 0x66,
685 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
686 /* data16
687 data16
688 data16
689 data16
690 data16
691 nopw %cs:0L(%[re]ax,%[re]ax,1) */
692 static const char alt_long_15[] =
693 {0x66,
694 0x66,
695 0x66,
696 0x66,
697 0x66,
698 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 /* nopl 0(%[re]ax,%[re]ax,1)
700 nopw 0(%[re]ax,%[re]ax,1) */
701 static const char alt_short_11[] =
702 {0x0f,0x1f,0x44,0x00,0x00,
703 0x66,0x0f,0x1f,0x44,0x00,0x00};
704 /* nopw 0(%[re]ax,%[re]ax,1)
705 nopw 0(%[re]ax,%[re]ax,1) */
706 static const char alt_short_12[] =
707 {0x66,0x0f,0x1f,0x44,0x00,0x00,
708 0x66,0x0f,0x1f,0x44,0x00,0x00};
709 /* nopw 0(%[re]ax,%[re]ax,1)
710 nopl 0L(%[re]ax) */
711 static const char alt_short_13[] =
712 {0x66,0x0f,0x1f,0x44,0x00,0x00,
713 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
714 /* nopl 0L(%[re]ax)
715 nopl 0L(%[re]ax) */
716 static const char alt_short_14[] =
717 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
718 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
719 /* nopl 0L(%[re]ax)
720 nopl 0L(%[re]ax,%[re]ax,1) */
721 static const char alt_short_15[] =
722 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
723 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
724 static const char *const alt_short_patt[] = {
725 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
726 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
727 alt_short_14, alt_short_15
728 };
729 static const char *const alt_long_patt[] = {
730 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
731 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
732 alt_long_14, alt_long_15
733 };
252b5132 734
33fef721
JH		 735 if (count <= 0 || count > 15)
736 return;
3e73aa7c 737
ccc9c027
L		 738 /* We need to decide which NOP sequence to use for 32bit and
739 64bit. When -mtune= is used:
740
741 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
742 f32_patt will be used.
050dfa73 743 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 744 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 745 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 746 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 747 and PROCESSOR_GENERIC64, alt_short_patt will be used.
748
749 When -mtune= isn't used, alt_short_patt will be used if
750 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
751
752 When -march= or .arch is used, we can't use anything beyond
753 cpu_arch_isa_flags. */
754
755 if (flag_code == CODE_16BIT)
756 {
757 memcpy (fragP->fr_literal + fragP->fr_fix,
758 f16_patt[count - 1], count);
759 if (count > 8)
760 /* Adjust jump offset. */
761 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
762 }
763 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 764 {
33fef721
JH		 765 int i;
766 int nnops = (count + 3) / 4;
767 int len = count / nnops;
768 int remains = count - nnops * len;
769 int pos = 0;
770
ccc9c027
L		 771 /* The recommended way to pad 64bit code is to use NOPs preceded
772 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 773 for (i = 0; i < remains; i++)
252b5132 774 {
33fef721
JH		 775 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
776 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
777 pos += len + 1;
778 }
779 for (; i < nnops; i++)
780 {
781 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
782 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
783 pos += len;
252b5132 784 }
252b5132 785 }
33fef721 786 else
ccc9c027
L		 787 {
788 const char *const *patt = NULL;
789
790 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
791 {
792 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
793 switch (cpu_arch_tune)
794 {
795 case PROCESSOR_UNKNOWN:
796 /* We use cpu_arch_isa_flags to check if we SHOULD
797 optimize for Cpu686. */
798 if ((cpu_arch_isa_flags & Cpu686) != 0)
799 patt = alt_short_patt;
800 else
801 patt = f32_patt;
802 break;
ef05d495 803 case PROCESSOR_CORE2:
ccc9c027
L		 804 patt = alt_long_patt;
805 break;
806 case PROCESSOR_PENTIUMPRO:
807 case PROCESSOR_PENTIUM4:
808 case PROCESSOR_NOCONA:
ef05d495 809 case PROCESSOR_CORE:
ccc9c027
L		 810 case PROCESSOR_K6:
811 case PROCESSOR_ATHLON:
812 case PROCESSOR_K8:
813 case PROCESSOR_GENERIC64:
050dfa73 814 case PROCESSOR_AMDFAM10:
ccc9c027
L		 815 patt = alt_short_patt;
816 break;
817 case PROCESSOR_I486:
818 case PROCESSOR_PENTIUM:
819 case PROCESSOR_GENERIC32:
820 patt = f32_patt;
821 break;
822 }
823 }
824 else
825 {
826 switch (cpu_arch_tune)
827 {
828 case PROCESSOR_UNKNOWN:
829 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
830 PROCESSOR_UNKNOWN. */
831 abort ();
832 break;
833
834 case PROCESSOR_I486:
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_PENTIUMPRO:
837 case PROCESSOR_PENTIUM4:
838 case PROCESSOR_NOCONA:
ef05d495 839 case PROCESSOR_CORE:
ccc9c027
L		 840 case PROCESSOR_K6:
841 case PROCESSOR_ATHLON:
842 case PROCESSOR_K8:
050dfa73 843 case PROCESSOR_AMDFAM10:
ccc9c027
L		 844 case PROCESSOR_GENERIC32:
845 /* We use cpu_arch_isa_flags to check if we CAN optimize
846 for Cpu686. */
847 if ((cpu_arch_isa_flags & Cpu686) != 0)
848 patt = alt_short_patt;
849 else
850 patt = f32_patt;
851 break;
ef05d495 852 case PROCESSOR_CORE2:
ccc9c027
L		 853 if ((cpu_arch_isa_flags & Cpu686) != 0)
854 patt = alt_long_patt;
855 else
856 patt = f32_patt;
857 break;
858 case PROCESSOR_GENERIC64:
859 patt = alt_short_patt;
860 break;
861 }
862 }
863
33fef721 864 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 865 patt[count - 1], count);
866 }
33fef721 867 fragP->fr_var = count;
252b5132
RH		 868}
869
252b5132 870static INLINE unsigned int
e3bb37b5 871mode_from_disp_size (unsigned int t)
252b5132 872{
3e73aa7c 873 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 874}
875
876static INLINE int
e3bb37b5 877fits_in_signed_byte (offsetT num)
252b5132
RH		 878{
879 return (num >= -128) && (num <= 127);
47926f60 880}
252b5132
RH		 881
882static INLINE int
e3bb37b5 883fits_in_unsigned_byte (offsetT num)
252b5132
RH		 884{
885 return (num & 0xff) == num;
47926f60 886}
252b5132
RH		 887
888static INLINE int
e3bb37b5 889fits_in_unsigned_word (offsetT num)
252b5132
RH		 890{
891 return (num & 0xffff) == num;
47926f60 892}
252b5132
RH		 893
894static INLINE int
e3bb37b5 895fits_in_signed_word (offsetT num)
252b5132
RH		 896{
897 return (-32768 <= num) && (num <= 32767);
47926f60 898}
2a962e6d 899
3e73aa7c 900static INLINE int
e3bb37b5 901fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 902{
903#ifndef BFD64
904 return 1;
905#else
906 return (!(((offsetT) -1 << 31) & num)
907 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
908#endif
909} /* fits_in_signed_long() */
2a962e6d 910
3e73aa7c 911static INLINE int
e3bb37b5 912fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 913{
914#ifndef BFD64
915 return 1;
916#else
917 return (num & (((offsetT) 2 << 31) - 1)) == num;
918#endif
919} /* fits_in_unsigned_long() */
252b5132
RH		 920
921static int
e3bb37b5 922smallest_imm_type (offsetT num)
252b5132 923{
d32cad65 924 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 925 {
926 /* This code is disabled on the 486 because all the Imm1 forms
927 in the opcode table are slower on the i486. They're the
928 versions with the implicitly specified single-position
929 displacement, which has another syntax if you really want to
930 use that form. */
931 if (num == 1)
3e73aa7c 932 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 933 }
252b5132 934 return (fits_in_signed_byte (num)
3e73aa7c 935 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 936 : fits_in_unsigned_byte (num)
3e73aa7c 937 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 938 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 939 ? (Imm16 | Imm32 | Imm32S | Imm64)
940 : fits_in_signed_long (num)
941 ? (Imm32 | Imm32S | Imm64)
942 : fits_in_unsigned_long (num)
943 ? (Imm32 | Imm64)
944 : Imm64);
47926f60 945}
252b5132 946
847f7ad4 947static offsetT
e3bb37b5 948offset_in_range (offsetT val, int size)
847f7ad4 949{
508866be 950 addressT mask;
ba2adb93 951
847f7ad4
AM		 952 switch (size)
953 {
508866be
L		 954 case 1: mask = ((addressT) 1 << 8) - 1; break;
955 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 956 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 957#ifdef BFD64
958 case 8: mask = ((addressT) 2 << 63) - 1; break;
959#endif
47926f60 960 default: abort ();
847f7ad4
AM		 961 }
962
ba2adb93 963 /* If BFD64, sign extend val. */
3e73aa7c
JH		 964 if (!use_rela_relocations)
965 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
966 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 967
47926f60 968 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 969 {
970 char buf1[40], buf2[40];
971
972 sprint_value (buf1, val);
973 sprint_value (buf2, val & mask);
974 as_warn (_("%s shortened to %s"), buf1, buf2);
975 }
976 return val & mask;
977}
978
252b5132
RH		 979/* Returns 0 if attempting to add a prefix where one from the same
980 class already exists, 1 if non rep/repne added, 2 if rep/repne
981 added. */
982static int
e3bb37b5 983add_prefix (unsigned int prefix)
252b5132
RH		 984{
985 int ret = 1;
b1905489 986 unsigned int q;
252b5132 987
29b0f896
AM		 988 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
989 && flag_code == CODE_64BIT)
b1905489
JB		 990 {
991 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
992 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
993 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
994 ret = 0;
995 q = REX_PREFIX;
996 }
3e73aa7c 997 else
b1905489
JB		 998 {
999 switch (prefix)
1000 {
1001 default:
1002 abort ();
1003
1004 case CS_PREFIX_OPCODE:
1005 case DS_PREFIX_OPCODE:
1006 case ES_PREFIX_OPCODE:
1007 case FS_PREFIX_OPCODE:
1008 case GS_PREFIX_OPCODE:
1009 case SS_PREFIX_OPCODE:
1010 q = SEG_PREFIX;
1011 break;
1012
1013 case REPNE_PREFIX_OPCODE:
1014 case REPE_PREFIX_OPCODE:
1015 ret = 2;
1016 /* fall thru */
1017 case LOCK_PREFIX_OPCODE:
1018 q = LOCKREP_PREFIX;
1019 break;
1020
1021 case FWAIT_OPCODE:
1022 q = WAIT_PREFIX;
1023 break;
1024
1025 case ADDR_PREFIX_OPCODE:
1026 q = ADDR_PREFIX;
1027 break;
1028
1029 case DATA_PREFIX_OPCODE:
1030 q = DATA_PREFIX;
1031 break;
1032 }
1033 if (i.prefix[q] != 0)
1034 ret = 0;
1035 }
252b5132 1036
b1905489 1037 if (ret)
252b5132 1038 {
b1905489
JB		 1039 if (!i.prefix[q])
1040 ++i.prefixes;
1041 i.prefix[q] |= prefix;
252b5132 1042 }
b1905489
JB		 1043 else
1044 as_bad (_("same type of prefix used twice"));
252b5132 1045
252b5132
RH		 1046 return ret;
1047}
1048
1049static void
e3bb37b5 1050set_code_flag (int value)
eecb386c 1051{
3e73aa7c
JH		 1052 flag_code = value;
1053 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1054 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1055 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1056 {
1057 as_bad (_("64bit mode not supported on this CPU."));
1058 }
1059 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1060 {
1061 as_bad (_("32bit mode not supported on this CPU."));
1062 }
eecb386c
AM		 1063 stackop_size = '\0';
1064}
1065
1066static void
e3bb37b5 1067set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1068{
3e73aa7c
JH		 1069 flag_code = new_code_flag;
1070 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1071 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1072 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1073}
1074
1075static void
e3bb37b5 1076set_intel_syntax (int syntax_flag)
252b5132
RH		 1077{
1078 /* Find out if register prefixing is specified. */
1079 int ask_naked_reg = 0;
1080
1081 SKIP_WHITESPACE ();
29b0f896 1082 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1083 {
1084 char *string = input_line_pointer;
1085 int e = get_symbol_end ();
1086
47926f60 1087 if (strcmp (string, "prefix") == 0)
252b5132 1088 ask_naked_reg = 1;
47926f60 1089 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1090 ask_naked_reg = -1;
1091 else
d0b47220 1092 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1093 *input_line_pointer = e;
1094 }
1095 demand_empty_rest_of_line ();
c3332e24 1096
252b5132
RH		 1097 intel_syntax = syntax_flag;
1098
1099 if (ask_naked_reg == 0)
f86103b7
AM		 1100 allow_naked_reg = (intel_syntax
1101 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1102 else
1103 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1104
1105 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1106 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1107}
1108
e413e4e9 1109static void
e3bb37b5 1110set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1111{
47926f60 1112 SKIP_WHITESPACE ();
e413e4e9 1113
29b0f896 1114 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1115 {
1116 char *string = input_line_pointer;
1117 int e = get_symbol_end ();
9103f4f4 1118 unsigned int i;
e413e4e9 1119
9103f4f4 1120 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1121 {
1122 if (strcmp (string, cpu_arch[i].name) == 0)
1123 {
5c6af06e
JB		 1124 if (*string != '.')
1125 {
1126 cpu_arch_name = cpu_arch[i].name;
1127 cpu_sub_arch_name = NULL;
1128 cpu_arch_flags = (cpu_arch[i].flags
1129 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1130 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1131 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1132 if (!cpu_arch_tune_set)
1133 {
1134 cpu_arch_tune = cpu_arch_isa;
1135 cpu_arch_tune_flags = cpu_arch_isa_flags;
1136 }
5c6af06e
JB		 1137 break;
1138 }
1139 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1140 {
1141 cpu_sub_arch_name = cpu_arch[i].name;
1142 cpu_arch_flags |= cpu_arch[i].flags;
1143 }
1144 *input_line_pointer = e;
1145 demand_empty_rest_of_line ();
1146 return;
e413e4e9
AM		 1147 }
1148 }
9103f4f4 1149 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1150 as_bad (_("no such architecture: `%s'"), string);
1151
1152 *input_line_pointer = e;
1153 }
1154 else
1155 as_bad (_("missing cpu architecture"));
1156
fddf5b5b
AM		 1157 no_cond_jump_promotion = 0;
1158 if (*input_line_pointer == ','
29b0f896 1159 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1160 {
1161 char *string = ++input_line_pointer;
1162 int e = get_symbol_end ();
1163
1164 if (strcmp (string, "nojumps") == 0)
1165 no_cond_jump_promotion = 1;
1166 else if (strcmp (string, "jumps") == 0)
1167 ;
1168 else
1169 as_bad (_("no such architecture modifier: `%s'"), string);
1170
1171 *input_line_pointer = e;
1172 }
1173
e413e4e9
AM		 1174 demand_empty_rest_of_line ();
1175}
1176
b9d79e03
JH		 1177unsigned long
1178i386_mach ()
1179{
1180 if (!strcmp (default_arch, "x86_64"))
1181 return bfd_mach_x86_64;
1182 else if (!strcmp (default_arch, "i386"))
1183 return bfd_mach_i386_i386;
1184 else
1185 as_fatal (_("Unknown architecture"));
1186}
b9d79e03 1187\f
252b5132
RH		 1188void
1189md_begin ()
1190{
1191 const char *hash_err;
1192
47926f60 1193 /* Initialize op_hash hash table. */
252b5132
RH		 1194 op_hash = hash_new ();
1195
1196 {
29b0f896
AM		 1197 const template *optab;
1198 templates *core_optab;
252b5132 1199
47926f60
KH		 1200 /* Setup for loop. */
1201 optab = i386_optab;
252b5132
RH		 1202 core_optab = (templates *) xmalloc (sizeof (templates));
1203 core_optab->start = optab;
1204
1205 while (1)
1206 {
1207 ++optab;
1208 if (optab->name == NULL
1209 || strcmp (optab->name, (optab - 1)->name) != 0)
1210 {
1211 /* different name --> ship out current template list;
47926f60 1212 add to hash table; & begin anew. */
252b5132
RH		 1213 core_optab->end = optab;
1214 hash_err = hash_insert (op_hash,
1215 (optab - 1)->name,
1216 (PTR) core_optab);
1217 if (hash_err)
1218 {
252b5132
RH		 1219 as_fatal (_("Internal Error: Can't hash %s: %s"),
1220 (optab - 1)->name,
1221 hash_err);
1222 }
1223 if (optab->name == NULL)
1224 break;
1225 core_optab = (templates *) xmalloc (sizeof (templates));
1226 core_optab->start = optab;
1227 }
1228 }
1229 }
1230
47926f60 1231 /* Initialize reg_hash hash table. */
252b5132
RH		 1232 reg_hash = hash_new ();
1233 {
29b0f896 1234 const reg_entry *regtab;
252b5132
RH		 1235
1236 for (regtab = i386_regtab;
1237 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1238 regtab++)
1239 {
1240 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1241 if (hash_err)
3e73aa7c
JH		 1242 as_fatal (_("Internal Error: Can't hash %s: %s"),
1243 regtab->reg_name,
1244 hash_err);
252b5132
RH		 1245 }
1246 }
1247
47926f60 1248 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1249 {
29b0f896
AM		 1250 int c;
1251 char *p;
252b5132
RH		 1252
1253 for (c = 0; c < 256; c++)
1254 {
3882b010 1255 if (ISDIGIT (c))
252b5132
RH		 1256 {
1257 digit_chars[c] = c;
1258 mnemonic_chars[c] = c;
1259 register_chars[c] = c;
1260 operand_chars[c] = c;
1261 }
3882b010 1262 else if (ISLOWER (c))
252b5132
RH		 1263 {
1264 mnemonic_chars[c] = c;
1265 register_chars[c] = c;
1266 operand_chars[c] = c;
1267 }
3882b010 1268 else if (ISUPPER (c))
252b5132 1269 {
3882b010 1270 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1271 register_chars[c] = mnemonic_chars[c];
1272 operand_chars[c] = c;
1273 }
1274
3882b010 1275 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1276 identifier_chars[c] = c;
1277 else if (c >= 128)
1278 {
1279 identifier_chars[c] = c;
1280 operand_chars[c] = c;
1281 }
1282 }
1283
1284#ifdef LEX_AT
1285 identifier_chars['@'] = '@';
32137342
NC		 1286#endif
1287#ifdef LEX_QM
1288 identifier_chars['?'] = '?';
1289 operand_chars['?'] = '?';
252b5132 1290#endif
252b5132 1291 digit_chars['-'] = '-';
791fe849 1292 mnemonic_chars['-'] = '-';
252b5132
RH		 1293 identifier_chars['_'] = '_';
1294 identifier_chars['.'] = '.';
1295
1296 for (p = operand_special_chars; *p != '\0'; p++)
1297 operand_chars[(unsigned char) *p] = *p;
1298 }
1299
1300#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1301 if (IS_ELF)
252b5132
RH		 1302 {
1303 record_alignment (text_section, 2);
1304 record_alignment (data_section, 2);
1305 record_alignment (bss_section, 2);
1306 }
1307#endif
a4447b93
RH		 1308
1309 if (flag_code == CODE_64BIT)
1310 {
1311 x86_dwarf2_return_column = 16;
1312 x86_cie_data_alignment = -8;
1313 }
1314 else
1315 {
1316 x86_dwarf2_return_column = 8;
1317 x86_cie_data_alignment = -4;
1318 }
252b5132
RH		 1319}
1320
1321void
e3bb37b5 1322i386_print_statistics (FILE *file)
252b5132
RH		 1323{
1324 hash_print_statistics (file, "i386 opcode", op_hash);
1325 hash_print_statistics (file, "i386 register", reg_hash);
1326}
1327\f
252b5132
RH		 1328#ifdef DEBUG386
1329
ce8a8b2f 1330/* Debugging routines for md_assemble. */
e3bb37b5
L		 1331static void pte (template *);
1332static void pt (unsigned int);
1333static void pe (expressionS *);
1334static void ps (symbolS *);
252b5132
RH		 1335
1336static void
e3bb37b5 1337pi (char *line, i386_insn *x)
252b5132 1338{
09f131f2 1339 unsigned int i;
252b5132
RH		 1340
1341 fprintf (stdout, "%s: template ", line);
1342 pte (&x->tm);
09f131f2
JH		 1343 fprintf (stdout, " address: base %s index %s scale %x\n",
1344 x->base_reg ? x->base_reg->reg_name : "none",
1345 x->index_reg ? x->index_reg->reg_name : "none",
1346 x->log2_scale_factor);
1347 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1348 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1349 fprintf (stdout, " sib: base %x index %x scale %x\n",
1350 x->sib.base, x->sib.index, x->sib.scale);
1351 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1352 (x->rex & REX_MODE64) != 0,
1353 (x->rex & REX_EXTX) != 0,
1354 (x->rex & REX_EXTY) != 0,
1355 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1356 for (i = 0; i < x->operands; i++)
1357 {
1358 fprintf (stdout, " #%d: ", i + 1);
1359 pt (x->types[i]);
1360 fprintf (stdout, "\n");
1361 if (x->types[i]
3f4438ab 1362 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1363 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1364 if (x->types[i] & Imm)
520dc8e8 1365 pe (x->op[i].imms);
252b5132 1366 if (x->types[i] & Disp)
520dc8e8 1367 pe (x->op[i].disps);
252b5132
RH		 1368 }
1369}
1370
1371static void
e3bb37b5 1372pte (template *t)
252b5132 1373{
09f131f2 1374 unsigned int i;
252b5132 1375 fprintf (stdout, " %d operands ", t->operands);
47926f60 1376 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1377 if (t->extension_opcode != None)
1378 fprintf (stdout, "ext %x ", t->extension_opcode);
1379 if (t->opcode_modifier & D)
1380 fprintf (stdout, "D");
1381 if (t->opcode_modifier & W)
1382 fprintf (stdout, "W");
1383 fprintf (stdout, "\n");
1384 for (i = 0; i < t->operands; i++)
1385 {
1386 fprintf (stdout, " #%d type ", i + 1);
1387 pt (t->operand_types[i]);
1388 fprintf (stdout, "\n");
1389 }
1390}
1391
1392static void
e3bb37b5 1393pe (expressionS *e)
252b5132 1394{
24eab124 1395 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1396 fprintf (stdout, " add_number %ld (%lx)\n",
1397 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1398 if (e->X_add_symbol)
1399 {
1400 fprintf (stdout, " add_symbol ");
1401 ps (e->X_add_symbol);
1402 fprintf (stdout, "\n");
1403 }
1404 if (e->X_op_symbol)
1405 {
1406 fprintf (stdout, " op_symbol ");
1407 ps (e->X_op_symbol);
1408 fprintf (stdout, "\n");
1409 }
1410}
1411
1412static void
e3bb37b5 1413ps (symbolS *s)
252b5132
RH		 1414{
1415 fprintf (stdout, "%s type %s%s",
1416 S_GET_NAME (s),
1417 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1418 segment_name (S_GET_SEGMENT (s)));
1419}
1420
7b81dfbb 1421static struct type_name
252b5132
RH		 1422 {
1423 unsigned int mask;
1424 char *tname;
1425 }
7b81dfbb 1426const type_names[] =
252b5132
RH		 1427{
1428 { Reg8, "r8" },
1429 { Reg16, "r16" },
1430 { Reg32, "r32" },
09f131f2 1431 { Reg64, "r64" },
252b5132
RH		 1432 { Imm8, "i8" },
1433 { Imm8S, "i8s" },
1434 { Imm16, "i16" },
1435 { Imm32, "i32" },
09f131f2
JH		 1436 { Imm32S, "i32s" },
1437 { Imm64, "i64" },
252b5132
RH		 1438 { Imm1, "i1" },
1439 { BaseIndex, "BaseIndex" },
1440 { Disp8, "d8" },
1441 { Disp16, "d16" },
1442 { Disp32, "d32" },
09f131f2
JH		 1443 { Disp32S, "d32s" },
1444 { Disp64, "d64" },
252b5132
RH		 1445 { InOutPortReg, "InOutPortReg" },
1446 { ShiftCount, "ShiftCount" },
1447 { Control, "control reg" },
1448 { Test, "test reg" },
1449 { Debug, "debug reg" },
1450 { FloatReg, "FReg" },
1451 { FloatAcc, "FAcc" },
1452 { SReg2, "SReg2" },
1453 { SReg3, "SReg3" },
1454 { Acc, "Acc" },
1455 { JumpAbsolute, "Jump Absolute" },
1456 { RegMMX, "rMMX" },
3f4438ab 1457 { RegXMM, "rXMM" },
252b5132
RH		 1458 { EsSeg, "es" },
1459 { 0, "" }
1460};
1461
1462static void
1463pt (t)
1464 unsigned int t;
1465{
29b0f896 1466 const struct type_name *ty;
252b5132 1467
09f131f2
JH		 1468 for (ty = type_names; ty->mask; ty++)
1469 if (t & ty->mask)
1470 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1471 fflush (stdout);
1472}
1473
1474#endif /* DEBUG386 */
1475\f
252b5132 1476static bfd_reloc_code_real_type
3956db08 1477reloc (unsigned int size,
64e74474
AM		 1478 int pcrel,
1479 int sign,
1480 bfd_reloc_code_real_type other)
252b5132 1481{
47926f60 1482 if (other != NO_RELOC)
3956db08
JB		 1483 {
1484 reloc_howto_type *reloc;
1485
1486 if (size == 8)
1487 switch (other)
1488 {
64e74474
AM		 1489 case BFD_RELOC_X86_64_GOT32:
1490 return BFD_RELOC_X86_64_GOT64;
1491 break;
1492 case BFD_RELOC_X86_64_PLTOFF64:
1493 return BFD_RELOC_X86_64_PLTOFF64;
1494 break;
1495 case BFD_RELOC_X86_64_GOTPC32:
1496 other = BFD_RELOC_X86_64_GOTPC64;
1497 break;
1498 case BFD_RELOC_X86_64_GOTPCREL:
1499 other = BFD_RELOC_X86_64_GOTPCREL64;
1500 break;
1501 case BFD_RELOC_X86_64_TPOFF32:
1502 other = BFD_RELOC_X86_64_TPOFF64;
1503 break;
1504 case BFD_RELOC_X86_64_DTPOFF32:
1505 other = BFD_RELOC_X86_64_DTPOFF64;
1506 break;
1507 default:
1508 break;
3956db08 1509 }
e05278af
JB		 1510
1511 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1512 if (size == 4 && flag_code != CODE_64BIT)
1513 sign = -1;
1514
3956db08
JB		 1515 reloc = bfd_reloc_type_lookup (stdoutput, other);
1516 if (!reloc)
1517 as_bad (_("unknown relocation (%u)"), other);
1518 else if (size != bfd_get_reloc_size (reloc))
1519 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1520 bfd_get_reloc_size (reloc),
1521 size);
1522 else if (pcrel && !reloc->pc_relative)
1523 as_bad (_("non-pc-relative relocation for pc-relative field"));
1524 else if ((reloc->complain_on_overflow == complain_overflow_signed
1525 && !sign)
1526 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1527 && sign > 0))
3956db08
JB		 1528 as_bad (_("relocated field and relocation type differ in signedness"));
1529 else
1530 return other;
1531 return NO_RELOC;
1532 }
252b5132
RH		 1533
1534 if (pcrel)
1535 {
3e73aa7c 1536 if (!sign)
3956db08 1537 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1538 switch (size)
1539 {
1540 case 1: return BFD_RELOC_8_PCREL;
1541 case 2: return BFD_RELOC_16_PCREL;
1542 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1543 case 8: return BFD_RELOC_64_PCREL;
252b5132 1544 }
3956db08 1545 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1546 }
1547 else
1548 {
3956db08 1549 if (sign > 0)
e5cb08ac 1550 switch (size)
3e73aa7c
JH		 1551 {
1552 case 4: return BFD_RELOC_X86_64_32S;
1553 }
1554 else
1555 switch (size)
1556 {
1557 case 1: return BFD_RELOC_8;
1558 case 2: return BFD_RELOC_16;
1559 case 4: return BFD_RELOC_32;
1560 case 8: return BFD_RELOC_64;
1561 }
3956db08
JB		 1562 as_bad (_("cannot do %s %u byte relocation"),
1563 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1564 }
1565
bfb32b52 1566 abort ();
252b5132
RH		 1567 return BFD_RELOC_NONE;
1568}
1569
47926f60
KH		 1570/* Here we decide which fixups can be adjusted to make them relative to
1571 the beginning of the section instead of the symbol. Basically we need
1572 to make sure that the dynamic relocations are done correctly, so in
1573 some cases we force the original symbol to be used. */
1574
252b5132 1575int
e3bb37b5 1576tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1577{
6d249963 1578#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1579 if (!IS_ELF)
31312f95
AM		 1580 return 1;
1581
a161fe53
AM		 1582 /* Don't adjust pc-relative references to merge sections in 64-bit
1583 mode. */
1584 if (use_rela_relocations
1585 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1586 && fixP->fx_pcrel)
252b5132 1587 return 0;
31312f95 1588
8d01d9a9
AJ		 1589 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1590 and changed later by validate_fix. */
1591 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1592 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1593 return 0;
1594
ce8a8b2f 1595 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1596 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1597 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1598 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1599 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1600 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1601 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1602 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1609 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1610 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1611 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1612 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1613 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1615 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1618 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1622 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1623 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1624 return 0;
31312f95 1625#endif
252b5132
RH		 1626 return 1;
1627}
252b5132 1628
b4cac588 1629static int
e3bb37b5 1630intel_float_operand (const char *mnemonic)
252b5132 1631{
9306ca4a
JB		 1632 /* Note that the value returned is meaningful only for opcodes with (memory)
1633 operands, hence the code here is free to improperly handle opcodes that
1634 have no operands (for better performance and smaller code). */
1635
1636 if (mnemonic[0] != 'f')
1637 return 0; /* non-math */
1638
1639 switch (mnemonic[1])
1640 {
1641 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1642 the fs segment override prefix not currently handled because no
1643 call path can make opcodes without operands get here */
1644 case 'i':
1645 return 2 /* integer op */;
1646 case 'l':
1647 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1648 return 3; /* fldcw/fldenv */
1649 break;
1650 case 'n':
1651 if (mnemonic[2] != 'o' /* fnop */)
1652 return 3; /* non-waiting control op */
1653 break;
1654 case 'r':
1655 if (mnemonic[2] == 's')
1656 return 3; /* frstor/frstpm */
1657 break;
1658 case 's':
1659 if (mnemonic[2] == 'a')
1660 return 3; /* fsave */
1661 if (mnemonic[2] == 't')
1662 {
1663 switch (mnemonic[3])
1664 {
1665 case 'c': /* fstcw */
1666 case 'd': /* fstdw */
1667 case 'e': /* fstenv */
1668 case 's': /* fsts[gw] */
1669 return 3;
1670 }
1671 }
1672 break;
1673 case 'x':
1674 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1675 return 0; /* fxsave/fxrstor are not really math ops */
1676 break;
1677 }
252b5132 1678
9306ca4a 1679 return 1;
252b5132
RH		 1680}
1681
1682/* This is the guts of the machine-dependent assembler. LINE points to a
1683 machine dependent instruction. This function is supposed to emit
1684 the frags/bytes it assembles to. */
1685
1686void
1687md_assemble (line)
1688 char *line;
1689{
252b5132 1690 int j;
252b5132
RH		 1691 char mnemonic[MAX_MNEM_SIZE];
1692
47926f60 1693 /* Initialize globals. */
252b5132
RH		 1694 memset (&i, '\0', sizeof (i));
1695 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1696 i.reloc[j] = NO_RELOC;
252b5132
RH		 1697 memset (disp_expressions, '\0', sizeof (disp_expressions));
1698 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1699 save_stack_p = save_stack;
252b5132
RH		 1700
1701 /* First parse an instruction mnemonic & call i386_operand for the operands.
1702 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1703 start of a (possibly prefixed) mnemonic. */
252b5132 1704
29b0f896
AM		 1705 line = parse_insn (line, mnemonic);
1706 if (line == NULL)
1707 return;
252b5132 1708
29b0f896
AM		 1709 line = parse_operands (line, mnemonic);
1710 if (line == NULL)
1711 return;
252b5132 1712
050dfa73
MM		 1713 /* The order of the immediates should be reversed
1714 for 2 immediates extrq and insertq instructions */
1715 if ((i.imm_operands == 2) &&
1716 ((strcmp (mnemonic, "extrq") == 0)
1717 || (strcmp (mnemonic, "insertq") == 0)))
1718 {
1719 swap_imm_operands ();
1720 /* "extrq" and insertq" are the only two instructions whose operands
1721 have to be reversed even though they have two immediate operands.
1722 */
1723 if (intel_syntax)
1724 swap_operands ();
1725 }
1726
29b0f896
AM		 1727 /* Now we've parsed the mnemonic into a set of templates, and have the
1728 operands at hand. */
1729
1730 /* All intel opcodes have reversed operands except for "bound" and
1731 "enter". We also don't reverse intersegment "jmp" and "call"
1732 instructions with 2 immediate operands so that the immediate segment
050dfa73 1733 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1734 if (intel_syntax && i.operands > 1
1735 && (strcmp (mnemonic, "bound") != 0)
30123838 1736 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1737 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1738 swap_operands ();
1739
1740 if (i.imm_operands)
1741 optimize_imm ();
1742
b300c311
L		 1743 /* Don't optimize displacement for movabs since it only takes 64bit
1744 displacement. */
1745 if (i.disp_operands
1746 && (flag_code != CODE_64BIT
1747 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1748 optimize_disp ();
1749
1750 /* Next, we find a template that matches the given insn,
1751 making sure the overlap of the given operands types is consistent
1752 with the template operand types. */
252b5132 1753
29b0f896
AM		 1754 if (!match_template ())
1755 return;
252b5132 1756
cd61ebfe
AM		 1757 if (intel_syntax)
1758 {
1759 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1760 if (SYSV386_COMPAT
1761 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1762 i.tm.base_opcode ^= FloatR;
1763
1764 /* Zap movzx and movsx suffix. The suffix may have been set from
1765 "word ptr" or "byte ptr" on the source operand, but we'll use
1766 the suffix later to choose the destination register. */
1767 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1768 {
1769 if (i.reg_operands < 2
1770 && !i.suffix
1771 && (~i.tm.opcode_modifier
1772 & (No_bSuf
1773 | No_wSuf
1774 | No_lSuf
1775 | No_sSuf
1776 | No_xSuf
1777 | No_qSuf)))
1778 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1779
1780 i.suffix = 0;
1781 }
cd61ebfe 1782 }
24eab124 1783
29b0f896
AM		 1784 if (i.tm.opcode_modifier & FWait)
1785 if (!add_prefix (FWAIT_OPCODE))
1786 return;
252b5132 1787
29b0f896
AM		 1788 /* Check string instruction segment overrides. */
1789 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1790 {
1791 if (!check_string ())
5dd0794d 1792 return;
29b0f896 1793 }
5dd0794d 1794
29b0f896
AM		 1795 if (!process_suffix ())
1796 return;
e413e4e9 1797
29b0f896
AM		 1798 /* Make still unresolved immediate matches conform to size of immediate
1799 given in i.suffix. */
1800 if (!finalize_imm ())
1801 return;
252b5132 1802
29b0f896
AM		 1803 if (i.types[0] & Imm1)
1804 i.imm_operands = 0; /* kludge for shift insns. */
1805 if (i.types[0] & ImplicitRegister)
1806 i.reg_operands--;
1807 if (i.types[1] & ImplicitRegister)
1808 i.reg_operands--;
1809 if (i.types[2] & ImplicitRegister)
1810 i.reg_operands--;
252b5132 1811
29b0f896
AM		 1812 if (i.tm.opcode_modifier & ImmExt)
1813 {
02fc3089
L		 1814 expressionS *exp;
1815
b7d9ef37 1816 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1817 {
b7d9ef37 1818 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1819 operands with an opcode suffix which is coded in the same
1820 place as an 8-bit immediate field would be. Here we check
1821 those operands and remove them afterwards. */
1822 unsigned int x;
1823
a4622f40 1824 for (x = 0; x < i.operands; x++)
ca164297
L		 1825 if (i.op[x].regs->reg_num != x)
1826 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1827 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1828 i.operands = 0;
1829 }
1830
29b0f896
AM		 1831 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1832 opcode suffix which is coded in the same place as an 8-bit
1833 immediate field would be. Here we fake an 8-bit immediate
1834 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1835
29b0f896 1836 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1837
29b0f896
AM		 1838 exp = &im_expressions[i.imm_operands++];
1839 i.op[i.operands].imms = exp;
1840 i.types[i.operands++] = Imm8;
1841 exp->X_op = O_constant;
1842 exp->X_add_number = i.tm.extension_opcode;
1843 i.tm.extension_opcode = None;
1844 }
252b5132 1845
29b0f896
AM		 1846 /* For insns with operands there are more diddles to do to the opcode. */
1847 if (i.operands)
1848 {
1849 if (!process_operands ())
1850 return;
1851 }
1852 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1853 {
1854 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1855 as_warn (_("translating to `%sp'"), i.tm.name);
1856 }
252b5132 1857
29b0f896
AM		 1858 /* Handle conversion of 'int $3' --> special int3 insn. */
1859 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1860 {
1861 i.tm.base_opcode = INT3_OPCODE;
1862 i.imm_operands = 0;
1863 }
252b5132 1864
29b0f896
AM		 1865 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1866 && i.op[0].disps->X_op == O_constant)
1867 {
1868 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1869 the absolute address given by the constant. Since ix86 jumps and
1870 calls are pc relative, we need to generate a reloc. */
1871 i.op[0].disps->X_add_symbol = &abs_symbol;
1872 i.op[0].disps->X_op = O_symbol;
1873 }
252b5132 1874
29b0f896
AM		 1875 if ((i.tm.opcode_modifier & Rex64) != 0)
1876 i.rex |= REX_MODE64;
252b5132 1877
29b0f896
AM		 1878 /* For 8 bit registers we need an empty rex prefix. Also if the
1879 instruction already has a prefix, we need to convert old
1880 registers to new ones. */
773f551c 1881
29b0f896
AM		 1882 if (((i.types[0] & Reg8) != 0
1883 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1884 || ((i.types[1] & Reg8) != 0
1885 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1886 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1887 && i.rex != 0))
1888 {
1889 int x;
726c5dcd 1890
29b0f896
AM		 1891 i.rex |= REX_OPCODE;
1892 for (x = 0; x < 2; x++)
1893 {
1894 /* Look for 8 bit operand that uses old registers. */
1895 if ((i.types[x] & Reg8) != 0
1896 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1897 {
29b0f896
AM		 1898 /* In case it is "hi" register, give up. */
1899 if (i.op[x].regs->reg_num > 3)
0477af35 1900 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1901 i.op[x].regs->reg_name);
773f551c 1902
29b0f896
AM		 1903 /* Otherwise it is equivalent to the extended register.
1904 Since the encoding doesn't change this is merely
1905 cosmetic cleanup for debug output. */
1906
1907 i.op[x].regs = i.op[x].regs + 8;
773f551c 1908 }
29b0f896
AM		 1909 }
1910 }
773f551c 1911
29b0f896
AM		 1912 if (i.rex != 0)
1913 add_prefix (REX_OPCODE | i.rex);
1914
1915 /* We are ready to output the insn. */
1916 output_insn ();
1917}
1918
1919static char *
e3bb37b5 1920parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1921{
1922 char *l = line;
1923 char *token_start = l;
1924 char *mnem_p;
5c6af06e
JB		 1925 int supported;
1926 const template *t;
29b0f896
AM		 1927
1928 /* Non-zero if we found a prefix only acceptable with string insns. */
1929 const char *expecting_string_instruction = NULL;
45288df1 1930
29b0f896
AM		 1931 while (1)
1932 {
1933 mnem_p = mnemonic;
1934 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1935 {
1936 mnem_p++;
1937 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1938 {
29b0f896
AM		 1939 as_bad (_("no such instruction: `%s'"), token_start);
1940 return NULL;
1941 }
1942 l++;
1943 }
1944 if (!is_space_char (*l)
1945 && *l != END_OF_INSN
e44823cf
JB		 1946 && (intel_syntax
1947 || (*l != PREFIX_SEPARATOR
1948 && *l != ',')))
29b0f896
AM		 1949 {
1950 as_bad (_("invalid character %s in mnemonic"),
1951 output_invalid (*l));
1952 return NULL;
1953 }
1954 if (token_start == l)
1955 {
e44823cf 1956 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1957 as_bad (_("expecting prefix; got nothing"));
1958 else
1959 as_bad (_("expecting mnemonic; got nothing"));
1960 return NULL;
1961 }
45288df1 1962
29b0f896
AM		 1963 /* Look up instruction (or prefix) via hash table. */
1964 current_templates = hash_find (op_hash, mnemonic);
47926f60 1965
29b0f896
AM		 1966 if (*l != END_OF_INSN
1967 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1968 && current_templates
1969 && (current_templates->start->opcode_modifier & IsPrefix))
1970 {
2dd88dca
JB		 1971 if (current_templates->start->cpu_flags
1972 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1973 {
1974 as_bad ((flag_code != CODE_64BIT
1975 ? _("`%s' is only supported in 64-bit mode")
1976 : _("`%s' is not supported in 64-bit mode")),
1977 current_templates->start->name);
1978 return NULL;
1979 }
29b0f896
AM		 1980 /* If we are in 16-bit mode, do not allow addr16 or data16.
1981 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1982 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1983 && flag_code != CODE_64BIT
1984 && (((current_templates->start->opcode_modifier & Size32) != 0)
1985 ^ (flag_code == CODE_16BIT)))
1986 {
1987 as_bad (_("redundant %s prefix"),
1988 current_templates->start->name);
1989 return NULL;
45288df1 1990 }
29b0f896
AM		 1991 /* Add prefix, checking for repeated prefixes. */
1992 switch (add_prefix (current_templates->start->base_opcode))
1993 {
1994 case 0:
1995 return NULL;
1996 case 2:
1997 expecting_string_instruction = current_templates->start->name;
1998 break;
1999 }
2000 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2001 token_start = ++l;
2002 }
2003 else
2004 break;
2005 }
45288df1 2006
29b0f896
AM		 2007 if (!current_templates)
2008 {
2009 /* See if we can get a match by trimming off a suffix. */
2010 switch (mnem_p[-1])
2011 {
2012 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2013 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2014 i.suffix = SHORT_MNEM_SUFFIX;
2015 else
29b0f896
AM		 2016 case BYTE_MNEM_SUFFIX:
2017 case QWORD_MNEM_SUFFIX:
2018 i.suffix = mnem_p[-1];
2019 mnem_p[-1] = '\0';
2020 current_templates = hash_find (op_hash, mnemonic);
2021 break;
2022 case SHORT_MNEM_SUFFIX:
2023 case LONG_MNEM_SUFFIX:
2024 if (!intel_syntax)
2025 {
2026 i.suffix = mnem_p[-1];
2027 mnem_p[-1] = '\0';
2028 current_templates = hash_find (op_hash, mnemonic);
2029 }
2030 break;
252b5132 2031
29b0f896
AM		 2032 /* Intel Syntax. */
2033 case 'd':
2034 if (intel_syntax)
2035 {
9306ca4a 2036 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2037 i.suffix = SHORT_MNEM_SUFFIX;
2038 else
2039 i.suffix = LONG_MNEM_SUFFIX;
2040 mnem_p[-1] = '\0';
2041 current_templates = hash_find (op_hash, mnemonic);
2042 }
2043 break;
2044 }
2045 if (!current_templates)
2046 {
2047 as_bad (_("no such instruction: `%s'"), token_start);
2048 return NULL;
2049 }
2050 }
252b5132 2051
29b0f896
AM		 2052 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2053 {
2054 /* Check for a branch hint. We allow ",pt" and ",pn" for
2055 predict taken and predict not taken respectively.
2056 I'm not sure that branch hints actually do anything on loop
2057 and jcxz insns (JumpByte) for current Pentium4 chips. They
2058 may work in the future and it doesn't hurt to accept them
2059 now. */
2060 if (l[0] == ',' && l[1] == 'p')
2061 {
2062 if (l[2] == 't')
2063 {
2064 if (!add_prefix (DS_PREFIX_OPCODE))
2065 return NULL;
2066 l += 3;
2067 }
2068 else if (l[2] == 'n')
2069 {
2070 if (!add_prefix (CS_PREFIX_OPCODE))
2071 return NULL;
2072 l += 3;
2073 }
2074 }
2075 }
2076 /* Any other comma loses. */
2077 if (*l == ',')
2078 {
2079 as_bad (_("invalid character %s in mnemonic"),
2080 output_invalid (*l));
2081 return NULL;
2082 }
252b5132 2083
29b0f896 2084 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2085 supported = 0;
2086 for (t = current_templates->start; t < current_templates->end; ++t)
2087 {
2088 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2089 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2090 supported |= 1;
5c6af06e 2091 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2092 supported |= 2;
5c6af06e
JB		 2093 }
2094 if (!(supported & 2))
2095 {
2096 as_bad (flag_code == CODE_64BIT
2097 ? _("`%s' is not supported in 64-bit mode")
2098 : _("`%s' is only supported in 64-bit mode"),
2099 current_templates->start->name);
2100 return NULL;
2101 }
2102 if (!(supported & 1))
29b0f896 2103 {
5c6af06e
JB		 2104 as_warn (_("`%s' is not supported on `%s%s'"),
2105 current_templates->start->name,
2106 cpu_arch_name,
2107 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2108 }
2109 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2110 {
2111 as_warn (_("use .code16 to ensure correct addressing mode"));
2112 }
252b5132 2113
29b0f896 2114 /* Check for rep/repne without a string instruction. */
f41bbced 2115 if (expecting_string_instruction)
29b0f896 2116 {
f41bbced
JB		 2117 static templates override;
2118
2119 for (t = current_templates->start; t < current_templates->end; ++t)
2120 if (t->opcode_modifier & IsString)
2121 break;
2122 if (t >= current_templates->end)
2123 {
2124 as_bad (_("expecting string instruction after `%s'"),
64e74474 2125 expecting_string_instruction);
f41bbced
JB		 2126 return NULL;
2127 }
2128 for (override.start = t; t < current_templates->end; ++t)
2129 if (!(t->opcode_modifier & IsString))
2130 break;
2131 override.end = t;
2132 current_templates = &override;
29b0f896 2133 }
252b5132 2134
29b0f896
AM		 2135 return l;
2136}
252b5132 2137
29b0f896 2138static char *
e3bb37b5 2139parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2140{
2141 char *token_start;
3138f287 2142
29b0f896
AM		 2143 /* 1 if operand is pending after ','. */
2144 unsigned int expecting_operand = 0;
252b5132 2145
29b0f896
AM		 2146 /* Non-zero if operand parens not balanced. */
2147 unsigned int paren_not_balanced;
2148
2149 while (*l != END_OF_INSN)
2150 {
2151 /* Skip optional white space before operand. */
2152 if (is_space_char (*l))
2153 ++l;
2154 if (!is_operand_char (*l) && *l != END_OF_INSN)
2155 {
2156 as_bad (_("invalid character %s before operand %d"),
2157 output_invalid (*l),
2158 i.operands + 1);
2159 return NULL;
2160 }
2161 token_start = l; /* after white space */
2162 paren_not_balanced = 0;
2163 while (paren_not_balanced || *l != ',')
2164 {
2165 if (*l == END_OF_INSN)
2166 {
2167 if (paren_not_balanced)
2168 {
2169 if (!intel_syntax)
2170 as_bad (_("unbalanced parenthesis in operand %d."),
2171 i.operands + 1);
2172 else
2173 as_bad (_("unbalanced brackets in operand %d."),
2174 i.operands + 1);
2175 return NULL;
2176 }
2177 else
2178 break; /* we are done */
2179 }
2180 else if (!is_operand_char (*l) && !is_space_char (*l))
2181 {
2182 as_bad (_("invalid character %s in operand %d"),
2183 output_invalid (*l),
2184 i.operands + 1);
2185 return NULL;
2186 }
2187 if (!intel_syntax)
2188 {
2189 if (*l == '(')
2190 ++paren_not_balanced;
2191 if (*l == ')')
2192 --paren_not_balanced;
2193 }
2194 else
2195 {
2196 if (*l == '[')
2197 ++paren_not_balanced;
2198 if (*l == ']')
2199 --paren_not_balanced;
2200 }
2201 l++;
2202 }
2203 if (l != token_start)
2204 { /* Yes, we've read in another operand. */
2205 unsigned int operand_ok;
2206 this_operand = i.operands++;
2207 if (i.operands > MAX_OPERANDS)
2208 {
2209 as_bad (_("spurious operands; (%d operands/instruction max)"),
2210 MAX_OPERANDS);
2211 return NULL;
2212 }
2213 /* Now parse operand adding info to 'i' as we go along. */
2214 END_STRING_AND_SAVE (l);
2215
2216 if (intel_syntax)
2217 operand_ok =
2218 i386_intel_operand (token_start,
2219 intel_float_operand (mnemonic));
2220 else
2221 operand_ok = i386_operand (token_start);
2222
2223 RESTORE_END_STRING (l);
2224 if (!operand_ok)
2225 return NULL;
2226 }
2227 else
2228 {
2229 if (expecting_operand)
2230 {
2231 expecting_operand_after_comma:
2232 as_bad (_("expecting operand after ','; got nothing"));
2233 return NULL;
2234 }
2235 if (*l == ',')
2236 {
2237 as_bad (_("expecting operand before ','; got nothing"));
2238 return NULL;
2239 }
2240 }
7f3f1ea2 2241
29b0f896
AM		 2242 /* Now *l must be either ',' or END_OF_INSN. */
2243 if (*l == ',')
2244 {
2245 if (*++l == END_OF_INSN)
2246 {
2247 /* Just skip it, if it's \n complain. */
2248 goto expecting_operand_after_comma;
2249 }
2250 expecting_operand = 1;
2251 }
2252 }
2253 return l;
2254}
7f3f1ea2 2255
050dfa73 2256static void
e3bb37b5 2257swap_imm_operands (void)
050dfa73
MM		 2258{
2259 union i386_op temp_op;
2260 unsigned int temp_type;
2261 enum bfd_reloc_code_real temp_reloc;
2262 int xchg1 = 0;
2263 int xchg2 = 1;
2264
2265 temp_type = i.types[xchg2];
2266 i.types[xchg2] = i.types[xchg1];
2267 i.types[xchg1] = temp_type;
2268 temp_op = i.op[xchg2];
2269 i.op[xchg2] = i.op[xchg1];
2270 i.op[xchg1] = temp_op;
2271 temp_reloc = i.reloc[xchg2];
2272 i.reloc[xchg2] = i.reloc[xchg1];
2273 i.reloc[xchg1] = temp_reloc;
2274}
2275
2276
29b0f896 2277static void
e3bb37b5 2278swap_operands (void)
29b0f896
AM		 2279{
2280 union i386_op temp_op;
2281 unsigned int temp_type;
f86103b7 2282 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2283 int xchg1 = 0;
2284 int xchg2 = 0;
252b5132 2285
050dfa73
MM		 2286 if (i.operands == 4)
2287 /* There will be two exchanges in a 4 operand instruction.
2288 First exchange is the done inside this block.(1st and 4rth operand)
2289 The next exchange is done outside this block.(2nd and 3rd operand) */
2290 {
2291 xchg1 = 0;
2292 xchg2 = 3;
2293 temp_type = i.types[xchg2];
2294 i.types[xchg2] = i.types[xchg1];
2295 i.types[xchg1] = temp_type;
2296 temp_op = i.op[xchg2];
2297 i.op[xchg2] = i.op[xchg1];
2298 i.op[xchg1] = temp_op;
2299 temp_reloc = i.reloc[xchg2];
2300 i.reloc[xchg2] = i.reloc[xchg1];
2301 i.reloc[xchg1] = temp_reloc;
2302 xchg1 = 1;
2303 xchg2 = 2;
2304 }
2305
29b0f896
AM		 2306 if (i.operands == 2)
2307 {
2308 xchg1 = 0;
2309 xchg2 = 1;
2310 }
2311 else if (i.operands == 3)
2312 {
2313 xchg1 = 0;
2314 xchg2 = 2;
2315 }
2316 temp_type = i.types[xchg2];
2317 i.types[xchg2] = i.types[xchg1];
2318 i.types[xchg1] = temp_type;
2319 temp_op = i.op[xchg2];
2320 i.op[xchg2] = i.op[xchg1];
2321 i.op[xchg1] = temp_op;
2322 temp_reloc = i.reloc[xchg2];
2323 i.reloc[xchg2] = i.reloc[xchg1];
2324 i.reloc[xchg1] = temp_reloc;
2325
2326 if (i.mem_operands == 2)
2327 {
2328 const seg_entry *temp_seg;
2329 temp_seg = i.seg[0];
2330 i.seg[0] = i.seg[1];
2331 i.seg[1] = temp_seg;
2332 }
2333}
252b5132 2334
29b0f896
AM		 2335/* Try to ensure constant immediates are represented in the smallest
2336 opcode possible. */
2337static void
e3bb37b5 2338optimize_imm (void)
29b0f896
AM		 2339{
2340 char guess_suffix = 0;
2341 int op;
252b5132 2342
29b0f896
AM		 2343 if (i.suffix)
2344 guess_suffix = i.suffix;
2345 else if (i.reg_operands)
2346 {
2347 /* Figure out a suffix from the last register operand specified.
2348 We can't do this properly yet, ie. excluding InOutPortReg,
2349 but the following works for instructions with immediates.
2350 In any case, we can't set i.suffix yet. */
2351 for (op = i.operands; --op >= 0;)
2352 if (i.types[op] & Reg)
252b5132 2353 {
29b0f896
AM		 2354 if (i.types[op] & Reg8)
2355 guess_suffix = BYTE_MNEM_SUFFIX;
2356 else if (i.types[op] & Reg16)
2357 guess_suffix = WORD_MNEM_SUFFIX;
2358 else if (i.types[op] & Reg32)
2359 guess_suffix = LONG_MNEM_SUFFIX;
2360 else if (i.types[op] & Reg64)
2361 guess_suffix = QWORD_MNEM_SUFFIX;
2362 break;
252b5132 2363 }
29b0f896
AM		 2364 }
2365 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2366 guess_suffix = WORD_MNEM_SUFFIX;
2367
2368 for (op = i.operands; --op >= 0;)
2369 if (i.types[op] & Imm)
2370 {
2371 switch (i.op[op].imms->X_op)
252b5132 2372 {
29b0f896
AM		 2373 case O_constant:
2374 /* If a suffix is given, this operand may be shortened. */
2375 switch (guess_suffix)
252b5132 2376 {
29b0f896
AM		 2377 case LONG_MNEM_SUFFIX:
2378 i.types[op] |= Imm32 | Imm64;
2379 break;
2380 case WORD_MNEM_SUFFIX:
2381 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2382 break;
2383 case BYTE_MNEM_SUFFIX:
2384 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2385 break;
252b5132 2386 }
252b5132 2387
29b0f896
AM		 2388 /* If this operand is at most 16 bits, convert it
2389 to a signed 16 bit number before trying to see
2390 whether it will fit in an even smaller size.
2391 This allows a 16-bit operand such as $0xffe0 to
2392 be recognised as within Imm8S range. */
2393 if ((i.types[op] & Imm16)
2394 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2395 {
29b0f896
AM		 2396 i.op[op].imms->X_add_number =
2397 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2398 }
2399 if ((i.types[op] & Imm32)
2400 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2401 == 0))
2402 {
2403 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2404 ^ ((offsetT) 1 << 31))
2405 - ((offsetT) 1 << 31));
2406 }
2407 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2408
29b0f896
AM		 2409 /* We must avoid matching of Imm32 templates when 64bit
2410 only immediate is available. */
2411 if (guess_suffix == QWORD_MNEM_SUFFIX)
2412 i.types[op] &= ~Imm32;
2413 break;
252b5132 2414
29b0f896
AM		 2415 case O_absent:
2416 case O_register:
2417 abort ();
2418
2419 /* Symbols and expressions. */
2420 default:
9cd96992
JB		 2421 /* Convert symbolic operand to proper sizes for matching, but don't
2422 prevent matching a set of insns that only supports sizes other
2423 than those matching the insn suffix. */
2424 {
2425 unsigned int mask, allowed = 0;
2426 const template *t;
2427
2428 for (t = current_templates->start; t < current_templates->end; ++t)
2429 allowed |= t->operand_types[op];
2430 switch (guess_suffix)
2431 {
2432 case QWORD_MNEM_SUFFIX:
2433 mask = Imm64 | Imm32S;
2434 break;
2435 case LONG_MNEM_SUFFIX:
2436 mask = Imm32;
2437 break;
2438 case WORD_MNEM_SUFFIX:
2439 mask = Imm16;
2440 break;
2441 case BYTE_MNEM_SUFFIX:
2442 mask = Imm8;
2443 break;
2444 default:
2445 mask = 0;
2446 break;
2447 }
64e74474
AM		 2448 if (mask & allowed)
2449 i.types[op] &= mask;
9cd96992 2450 }
29b0f896 2451 break;
252b5132 2452 }
29b0f896
AM		 2453 }
2454}
47926f60 2455
29b0f896
AM		 2456/* Try to use the smallest displacement type too. */
2457static void
e3bb37b5 2458optimize_disp (void)
29b0f896
AM		 2459{
2460 int op;
3e73aa7c 2461
29b0f896 2462 for (op = i.operands; --op >= 0;)
b300c311 2463 if (i.types[op] & Disp)
252b5132 2464 {
b300c311 2465 if (i.op[op].disps->X_op == O_constant)
252b5132 2466 {
b300c311 2467 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2468
b300c311
L		 2469 if ((i.types[op] & Disp16)
2470 && (disp & ~(offsetT) 0xffff) == 0)
2471 {
2472 /* If this operand is at most 16 bits, convert
2473 to a signed 16 bit number and don't use 64bit
2474 displacement. */
2475 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2476 i.types[op] &= ~Disp64;
2477 }
2478 if ((i.types[op] & Disp32)
2479 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2480 {
2481 /* If this operand is at most 32 bits, convert
2482 to a signed 32 bit number and don't use 64bit
2483 displacement. */
2484 disp &= (((offsetT) 2 << 31) - 1);
2485 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2486 i.types[op] &= ~Disp64;
2487 }
2488 if (!disp && (i.types[op] & BaseIndex))
2489 {
2490 i.types[op] &= ~Disp;
2491 i.op[op].disps = 0;
2492 i.disp_operands--;
2493 }
2494 else if (flag_code == CODE_64BIT)
2495 {
2496 if (fits_in_signed_long (disp))
28a9d8f5
L		 2497 {
2498 i.types[op] &= ~Disp64;
2499 i.types[op] |= Disp32S;
2500 }
b300c311
L		 2501 if (fits_in_unsigned_long (disp))
2502 i.types[op] |= Disp32;
2503 }
2504 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2505 && fits_in_signed_byte (disp))
2506 i.types[op] |= Disp8;
252b5132 2507 }
67a4f2b7
AO		 2508 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2509 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2510 {
2511 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2512 i.op[op].disps, 0, i.reloc[op]);
2513 i.types[op] &= ~Disp;
2514 }
2515 else
b300c311
L		 2516 /* We only support 64bit displacement on constants. */
2517 i.types[op] &= ~Disp64;
252b5132 2518 }
29b0f896
AM		 2519}
2520
2521static int
e3bb37b5 2522match_template (void)
29b0f896
AM		 2523{
2524 /* Points to template once we've found it. */
2525 const template *t;
f48ff2ae 2526 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2527 unsigned int found_reverse_match;
2528 int suffix_check;
f48ff2ae 2529 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2530 int addr_prefix_disp;
a5c311ca 2531 unsigned int j;
29b0f896 2532
f48ff2ae
L		 2533#if MAX_OPERANDS != 4
2534# error "MAX_OPERANDS must be 4."
2535#endif
2536
29b0f896
AM		 2537#define MATCH(overlap, given, template) \
2538 ((overlap & ~JumpAbsolute) \
2539 && (((given) & (BaseIndex | JumpAbsolute)) \
2540 == ((overlap) & (BaseIndex | JumpAbsolute))))
2541
2542 /* If given types r0 and r1 are registers they must be of the same type
2543 unless the expected operand type register overlap is null.
2544 Note that Acc in a template matches every size of reg. */
2545#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2546 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2547 || ((g0) & Reg) == ((g1) & Reg) \
2548 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2549
2550 overlap0 = 0;
2551 overlap1 = 0;
2552 overlap2 = 0;
f48ff2ae 2553 overlap3 = 0;
29b0f896 2554 found_reverse_match = 0;
a5c311ca
L		 2555 for (j = 0; j < MAX_OPERANDS; j++)
2556 operand_types [j] = 0;
539e75ad 2557 addr_prefix_disp = -1;
29b0f896
AM		 2558 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2559 ? No_bSuf
2560 : (i.suffix == WORD_MNEM_SUFFIX
2561 ? No_wSuf
2562 : (i.suffix == SHORT_MNEM_SUFFIX
2563 ? No_sSuf
2564 : (i.suffix == LONG_MNEM_SUFFIX
2565 ? No_lSuf
2566 : (i.suffix == QWORD_MNEM_SUFFIX
2567 ? No_qSuf
2568 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2569 ? No_xSuf : 0))))));
2570
45aa61fe 2571 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2572 {
539e75ad
L		 2573 addr_prefix_disp = -1;
2574
29b0f896
AM		 2575 /* Must have right number of operands. */
2576 if (i.operands != t->operands)
2577 continue;
2578
2579 /* Check the suffix, except for some instructions in intel mode. */
2580 if ((t->opcode_modifier & suffix_check)
2581 && !(intel_syntax
9306ca4a 2582 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2583 continue;
2584
a5c311ca
L		 2585 for (j = 0; j < MAX_OPERANDS; j++)
2586 operand_types [j] = t->operand_types [j];
539e75ad 2587
45aa61fe
AM		 2588 /* In general, don't allow 64-bit operands in 32-bit mode. */
2589 if (i.suffix == QWORD_MNEM_SUFFIX
2590 && flag_code != CODE_64BIT
2591 && (intel_syntax
2592 ? (!(t->opcode_modifier & IgnoreSize)
2593 && !intel_float_operand (t->name))
2594 : intel_float_operand (t->name) != 2)
539e75ad
L		 2595 && (!(operand_types[0] & (RegMMX | RegXMM))
2596 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2597 && (t->base_opcode != 0x0fc7
2598 || t->extension_opcode != 1 /* cmpxchg8b */))
2599 continue;
2600
29b0f896
AM		 2601 /* Do not verify operands when there are none. */
2602 else if (!t->operands)
2603 {
2604 if (t->cpu_flags & ~cpu_arch_flags)
2605 continue;
2606 /* We've found a match; break out of loop. */
2607 break;
2608 }
252b5132 2609
539e75ad
L		 2610 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2611 into Disp32/Disp16/Disp32 operand. */
2612 if (i.prefix[ADDR_PREFIX] != 0)
2613 {
a5c311ca 2614 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2615
2616 switch (flag_code)
2617 {
2618 case CODE_16BIT:
2619 DispOn = Disp32;
2620 DispOff = Disp16;
2621 break;
2622 case CODE_32BIT:
2623 DispOn = Disp16;
2624 DispOff = Disp32;
2625 break;
2626 case CODE_64BIT:
2627 DispOn = Disp32;
2628 DispOff = Disp64;
2629 break;
2630 }
2631
f48ff2ae 2632 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2633 {
2634 /* There should be only one Disp operand. */
2635 if ((operand_types[j] & DispOff))
2636 {
2637 addr_prefix_disp = j;
2638 operand_types[j] |= DispOn;
2639 operand_types[j] &= ~DispOff;
2640 break;
2641 }
2642 }
2643 }
2644
2645 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2646 switch (t->operands)
2647 {
2648 case 1:
539e75ad 2649 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2650 continue;
2651 break;
2652 case 2:
2653 case 3:
f48ff2ae 2654 case 4:
539e75ad
L		 2655 overlap1 = i.types[1] & operand_types[1];
2656 if (!MATCH (overlap0, i.types[0], operand_types[0])
2657 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2658 /* monitor in SSE3 is a very special case. The first
708587a4 2659 register and the second register may have different
cb712a9e
L		 2660 sizes. */
2661 || !((t->base_opcode == 0x0f01
2662 && t->extension_opcode == 0xc8)
2663 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2664 operand_types[0],
cb712a9e 2665 overlap1, i.types[1],
539e75ad 2666 operand_types[1])))
29b0f896
AM		 2667 {
2668 /* Check if other direction is valid ... */
2669 if ((t->opcode_modifier & (D | FloatD)) == 0)
2670 continue;
2671
2672 /* Try reversing direction of operands. */
539e75ad
L		 2673 overlap0 = i.types[0] & operand_types[1];
2674 overlap1 = i.types[1] & operand_types[0];
2675 if (!MATCH (overlap0, i.types[0], operand_types[1])
2676 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2677 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2678 operand_types[1],
29b0f896 2679 overlap1, i.types[1],
539e75ad 2680 operand_types[0]))
29b0f896
AM		 2681 {
2682 /* Does not match either direction. */
2683 continue;
2684 }
2685 /* found_reverse_match holds which of D or FloatDR
2686 we've found. */
2687 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2688 }
f48ff2ae 2689 else
29b0f896 2690 {
f48ff2ae 2691 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2692 switch (t->operands)
2693 {
2694 case 4:
2695 overlap3 = i.types[3] & operand_types[3];
2696 case 3:
2697 overlap2 = i.types[2] & operand_types[2];
2698 break;
2699 }
29b0f896 2700
f48ff2ae
L		 2701 switch (t->operands)
2702 {
2703 case 4:
2704 if (!MATCH (overlap3, i.types[3], operand_types[3])
2705 || !CONSISTENT_REGISTER_MATCH (overlap2,
2706 i.types[2],
2707 operand_types[2],
2708 overlap3,
2709 i.types[3],
2710 operand_types[3]))
2711 continue;
2712 case 3:
2713 /* Here we make use of the fact that there are no
2714 reverse match 3 operand instructions, and all 3
2715 operand instructions only need to be checked for
2716 register consistency between operands 2 and 3. */
2717 if (!MATCH (overlap2, i.types[2], operand_types[2])
2718 || !CONSISTENT_REGISTER_MATCH (overlap1,
2719 i.types[1],
2720 operand_types[1],
2721 overlap2,
2722 i.types[2],
2723 operand_types[2]))
2724 continue;
2725 break;
2726 }
29b0f896 2727 }
f48ff2ae 2728 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2729 slip through to break. */
2730 }
2731 if (t->cpu_flags & ~cpu_arch_flags)
2732 {
2733 found_reverse_match = 0;
2734 continue;
2735 }
2736 /* We've found a match; break out of loop. */
2737 break;
2738 }
2739
2740 if (t == current_templates->end)
2741 {
2742 /* We found no match. */
2743 as_bad (_("suffix or operands invalid for `%s'"),
2744 current_templates->start->name);
2745 return 0;
2746 }
252b5132 2747
29b0f896
AM		 2748 if (!quiet_warnings)
2749 {
2750 if (!intel_syntax
2751 && ((i.types[0] & JumpAbsolute)
539e75ad 2752 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2753 {
2754 as_warn (_("indirect %s without `*'"), t->name);
2755 }
2756
2757 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2758 == (IsPrefix | IgnoreSize))
2759 {
2760 /* Warn them that a data or address size prefix doesn't
2761 affect assembly of the next line of code. */
2762 as_warn (_("stand-alone `%s' prefix"), t->name);
2763 }
2764 }
2765
2766 /* Copy the template we found. */
2767 i.tm = *t;
539e75ad
L		 2768
2769 if (addr_prefix_disp != -1)
2770 i.tm.operand_types[addr_prefix_disp]
2771 = operand_types[addr_prefix_disp];
2772
29b0f896
AM		 2773 if (found_reverse_match)
2774 {
2775 /* If we found a reverse match we must alter the opcode
2776 direction bit. found_reverse_match holds bits to change
2777 (different for int & float insns). */
2778
2779 i.tm.base_opcode ^= found_reverse_match;
2780
539e75ad
L		 2781 i.tm.operand_types[0] = operand_types[1];
2782 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2783 }
2784
2785 return 1;
2786}
2787
2788static int
e3bb37b5 2789check_string (void)
29b0f896
AM		 2790{
2791 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2792 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2793 {
2794 if (i.seg[0] != NULL && i.seg[0] != &es)
2795 {
2796 as_bad (_("`%s' operand %d must use `%%es' segment"),
2797 i.tm.name,
2798 mem_op + 1);
2799 return 0;
2800 }
2801 /* There's only ever one segment override allowed per instruction.
2802 This instruction possibly has a legal segment override on the
2803 second operand, so copy the segment to where non-string
2804 instructions store it, allowing common code. */
2805 i.seg[0] = i.seg[1];
2806 }
2807 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2808 {
2809 if (i.seg[1] != NULL && i.seg[1] != &es)
2810 {
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2812 i.tm.name,
2813 mem_op + 2);
2814 return 0;
2815 }
2816 }
2817 return 1;
2818}
2819
2820static int
543613e9 2821process_suffix (void)
29b0f896
AM		 2822{
2823 /* If matched instruction specifies an explicit instruction mnemonic
2824 suffix, use it. */
2825 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2826 {
2827 if (i.tm.opcode_modifier & Size16)
2828 i.suffix = WORD_MNEM_SUFFIX;
2829 else if (i.tm.opcode_modifier & Size64)
2830 i.suffix = QWORD_MNEM_SUFFIX;
2831 else
2832 i.suffix = LONG_MNEM_SUFFIX;
2833 }
2834 else if (i.reg_operands)
2835 {
2836 /* If there's no instruction mnemonic suffix we try to invent one
2837 based on register operands. */
2838 if (!i.suffix)
2839 {
2840 /* We take i.suffix from the last register operand specified,
2841 Destination register type is more significant than source
2842 register type. */
2843 int op;
543613e9 2844
29b0f896
AM		 2845 for (op = i.operands; --op >= 0;)
2846 if ((i.types[op] & Reg)
2847 && !(i.tm.operand_types[op] & InOutPortReg))
2848 {
2849 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2850 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2851 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2852 LONG_MNEM_SUFFIX);
2853 break;
2854 }
2855 }
2856 else if (i.suffix == BYTE_MNEM_SUFFIX)
2857 {
2858 if (!check_byte_reg ())
2859 return 0;
2860 }
2861 else if (i.suffix == LONG_MNEM_SUFFIX)
2862 {
2863 if (!check_long_reg ())
2864 return 0;
2865 }
2866 else if (i.suffix == QWORD_MNEM_SUFFIX)
2867 {
2868 if (!check_qword_reg ())
2869 return 0;
2870 }
2871 else if (i.suffix == WORD_MNEM_SUFFIX)
2872 {
2873 if (!check_word_reg ())
2874 return 0;
2875 }
2876 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2877 /* Do nothing if the instruction is going to ignore the prefix. */
2878 ;
2879 else
2880 abort ();
2881 }
9306ca4a
JB		 2882 else if ((i.tm.opcode_modifier & DefaultSize)
2883 && !i.suffix
2884 /* exclude fldenv/frstor/fsave/fstenv */
2885 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2886 {
2887 i.suffix = stackop_size;
2888 }
9306ca4a
JB		 2889 else if (intel_syntax
2890 && !i.suffix
2891 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2892 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2893 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2894 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2895 {
2896 switch (flag_code)
2897 {
2898 case CODE_64BIT:
2899 if (!(i.tm.opcode_modifier & No_qSuf))
2900 {
2901 i.suffix = QWORD_MNEM_SUFFIX;
2902 break;
2903 }
2904 case CODE_32BIT:
2905 if (!(i.tm.opcode_modifier & No_lSuf))
2906 i.suffix = LONG_MNEM_SUFFIX;
2907 break;
2908 case CODE_16BIT:
2909 if (!(i.tm.opcode_modifier & No_wSuf))
2910 i.suffix = WORD_MNEM_SUFFIX;
2911 break;
2912 }
2913 }
252b5132 2914
9306ca4a 2915 if (!i.suffix)
29b0f896 2916 {
9306ca4a
JB		 2917 if (!intel_syntax)
2918 {
2919 if (i.tm.opcode_modifier & W)
2920 {
2921 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2922 return 0;
2923 }
2924 }
2925 else
2926 {
64e74474
AM		 2927 unsigned int suffixes = (~i.tm.opcode_modifier
2928 & (No_bSuf
2929 | No_wSuf
2930 | No_lSuf
2931 | No_sSuf
2932 | No_xSuf
2933 | No_qSuf));
9306ca4a
JB		 2934
2935 if ((i.tm.opcode_modifier & W)
2936 || ((suffixes & (suffixes - 1))
2937 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2938 {
2939 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2940 return 0;
2941 }
2942 }
29b0f896 2943 }
252b5132 2944
9306ca4a
JB		 2945 /* Change the opcode based on the operand size given by i.suffix;
2946 We don't need to change things for byte insns. */
2947
29b0f896
AM		 2948 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2949 {
2950 /* It's not a byte, select word/dword operation. */
2951 if (i.tm.opcode_modifier & W)
2952 {
2953 if (i.tm.opcode_modifier & ShortForm)
2954 i.tm.base_opcode |= 8;
2955 else
2956 i.tm.base_opcode |= 1;
2957 }
0f3f3d8b 2958
29b0f896
AM		 2959 /* Now select between word & dword operations via the operand
2960 size prefix, except for instructions that will ignore this
2961 prefix anyway. */
cb712a9e
L		 2962 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2963 {
2964 /* monitor in SSE3 is a very special case. The default size
2965 of AX is the size of mode. The address size override
2966 prefix will change the size of AX. */
2967 if (i.op->regs[0].reg_type &
2968 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2969 if (!add_prefix (ADDR_PREFIX_OPCODE))
2970 return 0;
2971 }
2972 else if (i.suffix != QWORD_MNEM_SUFFIX
2973 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2974 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2975 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2976 || (flag_code == CODE_64BIT
2977 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2978 {
2979 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2980
29b0f896
AM		 2981 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2982 prefix = ADDR_PREFIX_OPCODE;
252b5132 2983
29b0f896
AM		 2984 if (!add_prefix (prefix))
2985 return 0;
24eab124 2986 }
252b5132 2987
29b0f896
AM		 2988 /* Set mode64 for an operand. */
2989 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2990 && flag_code == CODE_64BIT
29b0f896 2991 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2992 {
2993 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2994 need rex64. */
2995 if (i.operands != 2
2996 || i.types [0] != (Acc | Reg64)
2997 || i.types [1] != (Acc | Reg64)
2998 || strcmp (i.tm.name, "xchg") != 0)
2999 i.rex |= REX_MODE64;
3000 }
3e73aa7c 3001
29b0f896
AM		 3002 /* Size floating point instruction. */
3003 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3004 if (i.tm.opcode_modifier & FloatMF)
3005 i.tm.base_opcode ^= 4;
29b0f896 3006 }
7ecd2f8b 3007
29b0f896
AM		 3008 return 1;
3009}
3e73aa7c 3010
29b0f896 3011static int
543613e9 3012check_byte_reg (void)
29b0f896
AM		 3013{
3014 int op;
543613e9 3015
29b0f896
AM		 3016 for (op = i.operands; --op >= 0;)
3017 {
3018 /* If this is an eight bit register, it's OK. If it's the 16 or
3019 32 bit version of an eight bit register, we will just use the
3020 low portion, and that's OK too. */
3021 if (i.types[op] & Reg8)
3022 continue;
3023
3024 /* movzx and movsx should not generate this warning. */
3025 if (intel_syntax
3026 && (i.tm.base_opcode == 0xfb7
3027 || i.tm.base_opcode == 0xfb6
3028 || i.tm.base_opcode == 0x63
3029 || i.tm.base_opcode == 0xfbe
3030 || i.tm.base_opcode == 0xfbf))
3031 continue;
3032
65ec77d2 3033 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3034 {
3035 /* Prohibit these changes in the 64bit mode, since the
3036 lowering is more complicated. */
3037 if (flag_code == CODE_64BIT
3038 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3039 {
0f3f3d8b 3040 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3041 i.op[op].regs->reg_name,
3042 i.suffix);
3043 return 0;
3044 }
3045#if REGISTER_WARNINGS
3046 if (!quiet_warnings
3047 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3048 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3049 (i.op[op].regs + (i.types[op] & Reg16
3050 ? REGNAM_AL - REGNAM_AX
3051 : REGNAM_AL - REGNAM_EAX))->reg_name,
3052 i.op[op].regs->reg_name,
3053 i.suffix);
3054#endif
3055 continue;
3056 }
3057 /* Any other register is bad. */
3058 if (i.types[op] & (Reg | RegMMX | RegXMM
3059 | SReg2 | SReg3
3060 | Control | Debug | Test
3061 | FloatReg | FloatAcc))
3062 {
3063 as_bad (_("`%%%s' not allowed with `%s%c'"),
3064 i.op[op].regs->reg_name,
3065 i.tm.name,
3066 i.suffix);
3067 return 0;
3068 }
3069 }
3070 return 1;
3071}
3072
3073static int
e3bb37b5 3074check_long_reg (void)
29b0f896
AM		 3075{
3076 int op;
3077
3078 for (op = i.operands; --op >= 0;)
3079 /* Reject eight bit registers, except where the template requires
3080 them. (eg. movzb) */
3081 if ((i.types[op] & Reg8) != 0
3082 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3083 {
3084 as_bad (_("`%%%s' not allowed with `%s%c'"),
3085 i.op[op].regs->reg_name,
3086 i.tm.name,
3087 i.suffix);
3088 return 0;
3089 }
3090 /* Warn if the e prefix on a general reg is missing. */
3091 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3092 && (i.types[op] & Reg16) != 0
3093 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3094 {
3095 /* Prohibit these changes in the 64bit mode, since the
3096 lowering is more complicated. */
3097 if (flag_code == CODE_64BIT)
252b5132 3098 {
0f3f3d8b 3099 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3100 i.op[op].regs->reg_name,
3101 i.suffix);
3102 return 0;
252b5132 3103 }
29b0f896
AM		 3104#if REGISTER_WARNINGS
3105 else
3106 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3107 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3108 i.op[op].regs->reg_name,
3109 i.suffix);
3110#endif
252b5132 3111 }
29b0f896
AM		 3112 /* Warn if the r prefix on a general reg is missing. */
3113 else if ((i.types[op] & Reg64) != 0
3114 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3115 {
0f3f3d8b 3116 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3117 i.op[op].regs->reg_name,
3118 i.suffix);
3119 return 0;
3120 }
3121 return 1;
3122}
252b5132 3123
29b0f896 3124static int
e3bb37b5 3125check_qword_reg (void)
29b0f896
AM		 3126{
3127 int op;
252b5132 3128
29b0f896
AM		 3129 for (op = i.operands; --op >= 0; )
3130 /* Reject eight bit registers, except where the template requires
3131 them. (eg. movzb) */
3132 if ((i.types[op] & Reg8) != 0
3133 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3134 {
3135 as_bad (_("`%%%s' not allowed with `%s%c'"),
3136 i.op[op].regs->reg_name,
3137 i.tm.name,
3138 i.suffix);
3139 return 0;
3140 }
3141 /* Warn if the e prefix on a general reg is missing. */
3142 else if (((i.types[op] & Reg16) != 0
3143 || (i.types[op] & Reg32) != 0)
3144 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3145 {
3146 /* Prohibit these changes in the 64bit mode, since the
3147 lowering is more complicated. */
0f3f3d8b 3148 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3149 i.op[op].regs->reg_name,
3150 i.suffix);
3151 return 0;
252b5132 3152 }
29b0f896
AM		 3153 return 1;
3154}
252b5132 3155
29b0f896 3156static int
e3bb37b5 3157check_word_reg (void)
29b0f896
AM		 3158{
3159 int op;
3160 for (op = i.operands; --op >= 0;)
3161 /* Reject eight bit registers, except where the template requires
3162 them. (eg. movzb) */
3163 if ((i.types[op] & Reg8) != 0
3164 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3165 {
3166 as_bad (_("`%%%s' not allowed with `%s%c'"),
3167 i.op[op].regs->reg_name,
3168 i.tm.name,
3169 i.suffix);
3170 return 0;
3171 }
3172 /* Warn if the e prefix on a general reg is present. */
3173 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3174 && (i.types[op] & Reg32) != 0
3175 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3176 {
29b0f896
AM		 3177 /* Prohibit these changes in the 64bit mode, since the
3178 lowering is more complicated. */
3179 if (flag_code == CODE_64BIT)
252b5132 3180 {
0f3f3d8b 3181 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3182 i.op[op].regs->reg_name,
3183 i.suffix);
3184 return 0;
252b5132 3185 }
29b0f896
AM		 3186 else
3187#if REGISTER_WARNINGS
3188 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3189 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3190 i.op[op].regs->reg_name,
3191 i.suffix);
3192#endif
3193 }
3194 return 1;
3195}
252b5132 3196
29b0f896 3197static int
e3bb37b5 3198finalize_imm (void)
29b0f896
AM		 3199{
3200 unsigned int overlap0, overlap1, overlap2;
3201
3202 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3203 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3204 && overlap0 != Imm8 && overlap0 != Imm8S
3205 && overlap0 != Imm16 && overlap0 != Imm32S
3206 && overlap0 != Imm32 && overlap0 != Imm64)
3207 {
3208 if (i.suffix)
3209 {
3210 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3211 ? Imm8 | Imm8S
3212 : (i.suffix == WORD_MNEM_SUFFIX
3213 ? Imm16
3214 : (i.suffix == QWORD_MNEM_SUFFIX
3215 ? Imm64 | Imm32S
3216 : Imm32)));
3217 }
3218 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3219 || overlap0 == (Imm16 | Imm32)
3220 || overlap0 == (Imm16 | Imm32S))
3221 {
3222 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3223 ? Imm16 : Imm32S);
3224 }
3225 if (overlap0 != Imm8 && overlap0 != Imm8S
3226 && overlap0 != Imm16 && overlap0 != Imm32S
3227 && overlap0 != Imm32 && overlap0 != Imm64)
3228 {
3229 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3230 return 0;
3231 }
3232 }
3233 i.types[0] = overlap0;
3234
3235 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3236 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3237 && overlap1 != Imm8 && overlap1 != Imm8S
3238 && overlap1 != Imm16 && overlap1 != Imm32S
3239 && overlap1 != Imm32 && overlap1 != Imm64)
3240 {
3241 if (i.suffix)
3242 {
3243 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3244 ? Imm8 | Imm8S
3245 : (i.suffix == WORD_MNEM_SUFFIX
3246 ? Imm16
3247 : (i.suffix == QWORD_MNEM_SUFFIX
3248 ? Imm64 | Imm32S
3249 : Imm32)));
3250 }
3251 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3252 || overlap1 == (Imm16 | Imm32)
3253 || overlap1 == (Imm16 | Imm32S))
3254 {
3255 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3256 ? Imm16 : Imm32S);
3257 }
3258 if (overlap1 != Imm8 && overlap1 != Imm8S
3259 && overlap1 != Imm16 && overlap1 != Imm32S
3260 && overlap1 != Imm32 && overlap1 != Imm64)
3261 {
3262 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3263 return 0;
3264 }
3265 }
3266 i.types[1] = overlap1;
3267
3268 overlap2 = i.types[2] & i.tm.operand_types[2];
3269 assert ((overlap2 & Imm) == 0);
3270 i.types[2] = overlap2;
3271
3272 return 1;
3273}
3274
3275static int
e3bb37b5 3276process_operands (void)
29b0f896
AM		 3277{
3278 /* Default segment register this instruction will use for memory
3279 accesses. 0 means unknown. This is only for optimizing out
3280 unnecessary segment overrides. */
3281 const seg_entry *default_seg = 0;
3282
3283 /* The imul $imm, %reg instruction is converted into
3284 imul $imm, %reg, %reg, and the clr %reg instruction
3285 is converted into xor %reg, %reg. */
3286 if (i.tm.opcode_modifier & regKludge)
3287 {
3288 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3289 /* Pretend we saw the extra register operand. */
cab737b9
L		 3290 assert (i.reg_operands == 1
3291 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM		 3292 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3293 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L		 3294 i.operands++;
3295 i.reg_operands++;
29b0f896
AM		 3296 }
3297
3298 if (i.tm.opcode_modifier & ShortForm)
3299 {
3300 /* The register or float register operand is in operand 0 or 1. */
3301 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3302 /* Register goes in low 3 bits of opcode. */
3303 i.tm.base_opcode |= i.op[op].regs->reg_num;
3304 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3305 i.rex |= REX_EXTZ;
3306 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3307 {
3308 /* Warn about some common errors, but press on regardless.
3309 The first case can be generated by gcc (<= 2.8.1). */
3310 if (i.operands == 2)
3311 {
3312 /* Reversed arguments on faddp, fsubp, etc. */
3313 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3314 i.op[1].regs->reg_name,
3315 i.op[0].regs->reg_name);
3316 }
3317 else
3318 {
3319 /* Extraneous `l' suffix on fp insn. */
3320 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3321 i.op[0].regs->reg_name);
3322 }
3323 }
3324 }
3325 else if (i.tm.opcode_modifier & Modrm)
3326 {
3327 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3328 must be put into the modrm byte). Now, we make the modrm and
3329 index base bytes based on all the info we've collected. */
29b0f896
AM		 3330
3331 default_seg = build_modrm_byte ();
3332 }
3333 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3334 {
3335 if (i.tm.base_opcode == POP_SEG_SHORT
3336 && i.op[0].regs->reg_num == 1)
3337 {
3338 as_bad (_("you can't `pop %%cs'"));
3339 return 0;
3340 }
3341 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3342 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3343 i.rex |= REX_EXTZ;
3344 }
3345 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3346 {
3347 default_seg = &ds;
3348 }
3349 else if ((i.tm.opcode_modifier & IsString) != 0)
3350 {
3351 /* For the string instructions that allow a segment override
3352 on one of their operands, the default segment is ds. */
3353 default_seg = &ds;
3354 }
3355
30123838
JB		 3356 if ((i.tm.base_opcode == 0x8d /* lea */
3357 || (i.tm.cpu_flags & CpuSVME))
3358 && i.seg[0] && !quiet_warnings)
3359 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3360
3361 /* If a segment was explicitly specified, and the specified segment
3362 is not the default, use an opcode prefix to select it. If we
3363 never figured out what the default segment is, then default_seg
3364 will be zero at this point, and the specified segment prefix will
3365 always be used. */
29b0f896
AM		 3366 if ((i.seg[0]) && (i.seg[0] != default_seg))
3367 {
3368 if (!add_prefix (i.seg[0]->seg_prefix))
3369 return 0;
3370 }
3371 return 1;
3372}
3373
3374static const seg_entry *
e3bb37b5 3375build_modrm_byte (void)
29b0f896
AM		 3376{
3377 const seg_entry *default_seg = 0;
3378
3379 /* i.reg_operands MUST be the number of real register operands;
3380 implicit registers do not count. */
3381 if (i.reg_operands == 2)
3382 {
3383 unsigned int source, dest;
cab737b9
L		 3384
3385 switch (i.operands)
3386 {
3387 case 2:
3388 source = 0;
3389 break;
3390 case 3:
c81128dc
L		 3391 /* When there are 3 operands, one of them may be immediate,
3392 which may be the first or the last operand. Otherwise,
3393 the first operand must be shift count register (cl). */
3394 assert (i.imm_operands == 1
3395 || (i.imm_operands == 0
3396 && (i.types[0] & ShiftCount)));
3397 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3398 break;
3399 case 4:
3400 /* When there are 4 operands, the first two must be immediate
3401 operands. The source operand will be the 3rd one. */
3402 assert (i.imm_operands == 2
3403 && (i.types[0] & Imm)
3404 && (i.types[1] & Imm));
3405 source = 2;
3406 break;
3407 default:
3408 abort ();
3409 }
3410
29b0f896
AM		 3411 dest = source + 1;
3412
3413 i.rm.mode = 3;
3414 /* One of the register operands will be encoded in the i.tm.reg
3415 field, the other in the combined i.tm.mode and i.tm.regmem
3416 fields. If no form of this instruction supports a memory
3417 destination operand, then we assume the source operand may
3418 sometimes be a memory operand and so we need to store the
3419 destination in the i.rm.reg field. */
3420 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3421 {
3422 i.rm.reg = i.op[dest].regs->reg_num;
3423 i.rm.regmem = i.op[source].regs->reg_num;
3424 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3425 i.rex |= REX_EXTX;
3426 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3427 i.rex |= REX_EXTZ;
3428 }
3429 else
3430 {
3431 i.rm.reg = i.op[source].regs->reg_num;
3432 i.rm.regmem = i.op[dest].regs->reg_num;
3433 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3434 i.rex |= REX_EXTZ;
3435 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3436 i.rex |= REX_EXTX;
3437 }
c4a530c5
JB		 3438 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3439 {
3440 if (!((i.types[0] | i.types[1]) & Control))
3441 abort ();
3442 i.rex &= ~(REX_EXTX | REX_EXTZ);
3443 add_prefix (LOCK_PREFIX_OPCODE);
3444 }
29b0f896
AM		 3445 }
3446 else
3447 { /* If it's not 2 reg operands... */
3448 if (i.mem_operands)
3449 {
3450 unsigned int fake_zero_displacement = 0;
3451 unsigned int op = ((i.types[0] & AnyMem)
3452 ? 0
3453 : (i.types[1] & AnyMem) ? 1 : 2);
3454
3455 default_seg = &ds;
3456
3457 if (i.base_reg == 0)
3458 {
3459 i.rm.mode = 0;
3460 if (!i.disp_operands)
3461 fake_zero_displacement = 1;
3462 if (i.index_reg == 0)
3463 {
3464 /* Operand is just <disp> */
20f0a1fc 3465 if (flag_code == CODE_64BIT)
29b0f896
AM		 3466 {
3467 /* 64bit mode overwrites the 32bit absolute
3468 addressing by RIP relative addressing and
3469 absolute addressing is encoded by one of the
3470 redundant SIB forms. */
3471 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3472 i.sib.base = NO_BASE_REGISTER;
3473 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3474 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3475 ? Disp32S : Disp32);
20f0a1fc 3476 }
fc225355
L		 3477 else if ((flag_code == CODE_16BIT)
3478 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3479 {
3480 i.rm.regmem = NO_BASE_REGISTER_16;
3481 i.types[op] = Disp16;
3482 }
3483 else
3484 {
3485 i.rm.regmem = NO_BASE_REGISTER;
3486 i.types[op] = Disp32;
29b0f896
AM		 3487 }
3488 }
3489 else /* !i.base_reg && i.index_reg */
3490 {
3491 i.sib.index = i.index_reg->reg_num;
3492 i.sib.base = NO_BASE_REGISTER;
3493 i.sib.scale = i.log2_scale_factor;
3494 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3495 i.types[op] &= ~Disp;
3496 if (flag_code != CODE_64BIT)
3497 i.types[op] |= Disp32; /* Must be 32 bit */
3498 else
3499 i.types[op] |= Disp32S;
3500 if ((i.index_reg->reg_flags & RegRex) != 0)
3501 i.rex |= REX_EXTY;
3502 }
3503 }
3504 /* RIP addressing for 64bit mode. */
3505 else if (i.base_reg->reg_type == BaseIndex)
3506 {
3507 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3508 i.types[op] &= ~ Disp;
29b0f896 3509 i.types[op] |= Disp32S;
71903a11 3510 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3511 if (! i.disp_operands)
3512 fake_zero_displacement = 1;
29b0f896
AM		 3513 }
3514 else if (i.base_reg->reg_type & Reg16)
3515 {
3516 switch (i.base_reg->reg_num)
3517 {
3518 case 3: /* (%bx) */
3519 if (i.index_reg == 0)
3520 i.rm.regmem = 7;
3521 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3522 i.rm.regmem = i.index_reg->reg_num - 6;
3523 break;
3524 case 5: /* (%bp) */
3525 default_seg = &ss;
3526 if (i.index_reg == 0)
3527 {
3528 i.rm.regmem = 6;
3529 if ((i.types[op] & Disp) == 0)
3530 {
3531 /* fake (%bp) into 0(%bp) */
3532 i.types[op] |= Disp8;
252b5132 3533 fake_zero_displacement = 1;
29b0f896
AM		 3534 }
3535 }
3536 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3537 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3538 break;
3539 default: /* (%si) -> 4 or (%di) -> 5 */
3540 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3541 }
3542 i.rm.mode = mode_from_disp_size (i.types[op]);
3543 }
3544 else /* i.base_reg and 32/64 bit mode */
3545 {
3546 if (flag_code == CODE_64BIT
3547 && (i.types[op] & Disp))
fc225355
L		 3548 i.types[op] = ((i.types[op] & Disp8)
3549 | (i.prefix[ADDR_PREFIX] == 0
3550 ? Disp32S : Disp32));
20f0a1fc 3551
29b0f896
AM		 3552 i.rm.regmem = i.base_reg->reg_num;
3553 if ((i.base_reg->reg_flags & RegRex) != 0)
3554 i.rex |= REX_EXTZ;
3555 i.sib.base = i.base_reg->reg_num;
3556 /* x86-64 ignores REX prefix bit here to avoid decoder
3557 complications. */
3558 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3559 {
3560 default_seg = &ss;
3561 if (i.disp_operands == 0)
3562 {
3563 fake_zero_displacement = 1;
3564 i.types[op] |= Disp8;
3565 }
3566 }
3567 else if (i.base_reg->reg_num == ESP_REG_NUM)
3568 {
3569 default_seg = &ss;
3570 }
3571 i.sib.scale = i.log2_scale_factor;
3572 if (i.index_reg == 0)
3573 {
3574 /* <disp>(%esp) becomes two byte modrm with no index
3575 register. We've already stored the code for esp
3576 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3577 Any base register besides %esp will not use the
3578 extra modrm byte. */
3579 i.sib.index = NO_INDEX_REGISTER;
3580#if !SCALE1_WHEN_NO_INDEX
3581 /* Another case where we force the second modrm byte. */
3582 if (i.log2_scale_factor)
3583 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3584#endif
29b0f896
AM		 3585 }
3586 else
3587 {
3588 i.sib.index = i.index_reg->reg_num;
3589 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3590 if ((i.index_reg->reg_flags & RegRex) != 0)
3591 i.rex |= REX_EXTY;
3592 }
67a4f2b7
AO		 3593
3594 if (i.disp_operands
3595 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3596 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3597 i.rm.mode = 0;
3598 else
3599 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3600 }
252b5132 3601
29b0f896
AM		 3602 if (fake_zero_displacement)
3603 {
3604 /* Fakes a zero displacement assuming that i.types[op]
3605 holds the correct displacement size. */
3606 expressionS *exp;
3607
3608 assert (i.op[op].disps == 0);
3609 exp = &disp_expressions[i.disp_operands++];
3610 i.op[op].disps = exp;
3611 exp->X_op = O_constant;
3612 exp->X_add_number = 0;
3613 exp->X_add_symbol = (symbolS *) 0;
3614 exp->X_op_symbol = (symbolS *) 0;
3615 }
3616 }
252b5132 3617
29b0f896
AM		 3618 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3619 (if any) based on i.tm.extension_opcode. Again, we must be
3620 careful to make sure that segment/control/debug/test/MMX
3621 registers are coded into the i.rm.reg field. */
3622 if (i.reg_operands)
3623 {
3624 unsigned int op =
3625 ((i.types[0]
3626 & (Reg | RegMMX | RegXMM
3627 | SReg2 | SReg3
3628 | Control | Debug | Test))
3629 ? 0
3630 : ((i.types[1]
3631 & (Reg | RegMMX | RegXMM
3632 | SReg2 | SReg3
3633 | Control | Debug | Test))
3634 ? 1
3635 : 2));
3636 /* If there is an extension opcode to put here, the register
3637 number must be put into the regmem field. */
3638 if (i.tm.extension_opcode != None)
3639 {
3640 i.rm.regmem = i.op[op].regs->reg_num;
3641 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3642 i.rex |= REX_EXTZ;
3643 }
3644 else
3645 {
3646 i.rm.reg = i.op[op].regs->reg_num;
3647 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3648 i.rex |= REX_EXTX;
3649 }
252b5132 3650
29b0f896
AM		 3651 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3652 must set it to 3 to indicate this is a register operand
3653 in the regmem field. */
3654 if (!i.mem_operands)
3655 i.rm.mode = 3;
3656 }
252b5132 3657
29b0f896
AM		 3658 /* Fill in i.rm.reg field with extension opcode (if any). */
3659 if (i.tm.extension_opcode != None)
3660 i.rm.reg = i.tm.extension_opcode;
3661 }
3662 return default_seg;
3663}
252b5132 3664
29b0f896 3665static void
e3bb37b5 3666output_branch (void)
29b0f896
AM		 3667{
3668 char *p;
3669 int code16;
3670 int prefix;
3671 relax_substateT subtype;
3672 symbolS *sym;
3673 offsetT off;
3674
3675 code16 = 0;
3676 if (flag_code == CODE_16BIT)
3677 code16 = CODE16;
3678
3679 prefix = 0;
3680 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3681 {
29b0f896
AM		 3682 prefix = 1;
3683 i.prefixes -= 1;
3684 code16 ^= CODE16;
252b5132 3685 }
29b0f896
AM		 3686 /* Pentium4 branch hints. */
3687 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3688 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3689 {
29b0f896
AM		 3690 prefix++;
3691 i.prefixes--;
3692 }
3693 if (i.prefix[REX_PREFIX] != 0)
3694 {
3695 prefix++;
3696 i.prefixes--;
2f66722d
AM		 3697 }
3698
29b0f896
AM		 3699 if (i.prefixes != 0 && !intel_syntax)
3700 as_warn (_("skipping prefixes on this instruction"));
3701
3702 /* It's always a symbol; End frag & setup for relax.
3703 Make sure there is enough room in this frag for the largest
3704 instruction we may generate in md_convert_frag. This is 2
3705 bytes for the opcode and room for the prefix and largest
3706 displacement. */
3707 frag_grow (prefix + 2 + 4);
3708 /* Prefix and 1 opcode byte go in fr_fix. */
3709 p = frag_more (prefix + 1);
3710 if (i.prefix[DATA_PREFIX] != 0)
3711 *p++ = DATA_PREFIX_OPCODE;
3712 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3713 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3714 *p++ = i.prefix[SEG_PREFIX];
3715 if (i.prefix[REX_PREFIX] != 0)
3716 *p++ = i.prefix[REX_PREFIX];
3717 *p = i.tm.base_opcode;
3718
3719 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3720 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3721 else if ((cpu_arch_flags & Cpu386) != 0)
3722 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3723 else
3724 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3725 subtype |= code16;
3e73aa7c 3726
29b0f896
AM		 3727 sym = i.op[0].disps->X_add_symbol;
3728 off = i.op[0].disps->X_add_number;
3e73aa7c 3729
29b0f896
AM		 3730 if (i.op[0].disps->X_op != O_constant
3731 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3732 {
29b0f896
AM		 3733 /* Handle complex expressions. */
3734 sym = make_expr_symbol (i.op[0].disps);
3735 off = 0;
3736 }
3e73aa7c 3737
29b0f896
AM		 3738 /* 1 possible extra opcode + 4 byte displacement go in var part.
3739 Pass reloc in fr_var. */
3740 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3741}
3e73aa7c 3742
29b0f896 3743static void
e3bb37b5 3744output_jump (void)
29b0f896
AM		 3745{
3746 char *p;
3747 int size;
3e02c1cc 3748 fixS *fixP;
29b0f896
AM		 3749
3750 if (i.tm.opcode_modifier & JumpByte)
3751 {
3752 /* This is a loop or jecxz type instruction. */
3753 size = 1;
3754 if (i.prefix[ADDR_PREFIX] != 0)
3755 {
3756 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3757 i.prefixes -= 1;
3758 }
3759 /* Pentium4 branch hints. */
3760 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3761 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3762 {
3763 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3764 i.prefixes--;
3e73aa7c
JH		 3765 }
3766 }
29b0f896
AM		 3767 else
3768 {
3769 int code16;
3e73aa7c 3770
29b0f896
AM		 3771 code16 = 0;
3772 if (flag_code == CODE_16BIT)
3773 code16 = CODE16;
3e73aa7c 3774
29b0f896
AM		 3775 if (i.prefix[DATA_PREFIX] != 0)
3776 {
3777 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3778 i.prefixes -= 1;
3779 code16 ^= CODE16;
3780 }
252b5132 3781
29b0f896
AM		 3782 size = 4;
3783 if (code16)
3784 size = 2;
3785 }
9fcc94b6 3786
29b0f896
AM		 3787 if (i.prefix[REX_PREFIX] != 0)
3788 {
3789 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3790 i.prefixes -= 1;
3791 }
252b5132 3792
29b0f896
AM		 3793 if (i.prefixes != 0 && !intel_syntax)
3794 as_warn (_("skipping prefixes on this instruction"));
e0890092 3795
29b0f896
AM		 3796 p = frag_more (1 + size);
3797 *p++ = i.tm.base_opcode;
e0890092 3798
3e02c1cc
AM		 3799 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3800 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3801
3802 /* All jumps handled here are signed, but don't use a signed limit
3803 check for 32 and 16 bit jumps as we want to allow wrap around at
3804 4G and 64k respectively. */
3805 if (size == 1)
3806 fixP->fx_signed = 1;
29b0f896 3807}
e0890092 3808
29b0f896 3809static void
e3bb37b5 3810output_interseg_jump (void)
29b0f896
AM		 3811{
3812 char *p;
3813 int size;
3814 int prefix;
3815 int code16;
252b5132 3816
29b0f896
AM		 3817 code16 = 0;
3818 if (flag_code == CODE_16BIT)
3819 code16 = CODE16;
a217f122 3820
29b0f896
AM		 3821 prefix = 0;
3822 if (i.prefix[DATA_PREFIX] != 0)
3823 {
3824 prefix = 1;
3825 i.prefixes -= 1;
3826 code16 ^= CODE16;
3827 }
3828 if (i.prefix[REX_PREFIX] != 0)
3829 {
3830 prefix++;
3831 i.prefixes -= 1;
3832 }
252b5132 3833
29b0f896
AM		 3834 size = 4;
3835 if (code16)
3836 size = 2;
252b5132 3837
29b0f896
AM		 3838 if (i.prefixes != 0 && !intel_syntax)
3839 as_warn (_("skipping prefixes on this instruction"));
252b5132 3840
29b0f896
AM		 3841 /* 1 opcode; 2 segment; offset */
3842 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3843
29b0f896
AM		 3844 if (i.prefix[DATA_PREFIX] != 0)
3845 *p++ = DATA_PREFIX_OPCODE;
252b5132 3846
29b0f896
AM		 3847 if (i.prefix[REX_PREFIX] != 0)
3848 *p++ = i.prefix[REX_PREFIX];
252b5132 3849
29b0f896
AM		 3850 *p++ = i.tm.base_opcode;
3851 if (i.op[1].imms->X_op == O_constant)
3852 {
3853 offsetT n = i.op[1].imms->X_add_number;
252b5132 3854
29b0f896
AM		 3855 if (size == 2
3856 && !fits_in_unsigned_word (n)
3857 && !fits_in_signed_word (n))
3858 {
3859 as_bad (_("16-bit jump out of range"));
3860 return;
3861 }
3862 md_number_to_chars (p, n, size);
3863 }
3864 else
3865 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3866 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3867 if (i.op[0].imms->X_op != O_constant)
3868 as_bad (_("can't handle non absolute segment in `%s'"),
3869 i.tm.name);
3870 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3871}
a217f122 3872
29b0f896 3873static void
e3bb37b5 3874output_insn (void)
29b0f896 3875{
2bbd9c25
JJ		 3876 fragS *insn_start_frag;
3877 offsetT insn_start_off;
3878
29b0f896
AM		 3879 /* Tie dwarf2 debug info to the address at the start of the insn.
3880 We can't do this after the insn has been output as the current
3881 frag may have been closed off. eg. by frag_var. */
3882 dwarf2_emit_insn (0);
3883
2bbd9c25
JJ		 3884 insn_start_frag = frag_now;
3885 insn_start_off = frag_now_fix ();
3886
29b0f896
AM		 3887 /* Output jumps. */
3888 if (i.tm.opcode_modifier & Jump)
3889 output_branch ();
3890 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3891 output_jump ();
3892 else if (i.tm.opcode_modifier & JumpInterSegment)
3893 output_interseg_jump ();
3894 else
3895 {
3896 /* Output normal instructions here. */
3897 char *p;
3898 unsigned char *q;
331d2d0d 3899 unsigned int prefix;
252b5132 3900
ef05d495
L		 3901 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3902 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3903 use one more higher byte to specify a prefix the instruction
3904 requires. */
3905 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3906 {
331d2d0d
L		 3907 if (i.tm.base_opcode & 0xff000000)
3908 {
3909 prefix = (i.tm.base_opcode >> 24) & 0xff;
3910 goto check_prefix;
3911 }
3912 }
3913 else if ((i.tm.base_opcode & 0xff0000) != 0)
3914 {
3915 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3916 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3917 {
64e74474 3918 check_prefix:
bc4bd9ab
MK		 3919 if (prefix != REPE_PREFIX_OPCODE
3920 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3921 add_prefix (prefix);
3922 }
3923 else
331d2d0d 3924 add_prefix (prefix);
0f10071e 3925 }
252b5132 3926
29b0f896
AM		 3927 /* The prefix bytes. */
3928 for (q = i.prefix;
3929 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3930 q++)
3931 {
3932 if (*q)
3933 {
3934 p = frag_more (1);
3935 md_number_to_chars (p, (valueT) *q, 1);
3936 }
3937 }
252b5132 3938
29b0f896
AM		 3939 /* Now the opcode; be careful about word order here! */
3940 if (fits_in_unsigned_byte (i.tm.base_opcode))
3941 {
3942 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3943 }
3944 else
3945 {
ef05d495 3946 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3947 {
3948 p = frag_more (3);
3949 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3950 }
3951 else
3952 p = frag_more (2);
0f10071e 3953
29b0f896
AM		 3954 /* Put out high byte first: can't use md_number_to_chars! */
3955 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3956 *p = i.tm.base_opcode & 0xff;
3957 }
3e73aa7c 3958
29b0f896
AM		 3959 /* Now the modrm byte and sib byte (if present). */
3960 if (i.tm.opcode_modifier & Modrm)
3961 {
3962 p = frag_more (1);
3963 md_number_to_chars (p,
3964 (valueT) (i.rm.regmem << 0
3965 | i.rm.reg << 3
3966 | i.rm.mode << 6),
3967 1);
3968 /* If i.rm.regmem == ESP (4)
3969 && i.rm.mode != (Register mode)
3970 && not 16 bit
3971 ==> need second modrm byte. */
3972 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3973 && i.rm.mode != 3
3974 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3975 {
3976 p = frag_more (1);
3977 md_number_to_chars (p,
3978 (valueT) (i.sib.base << 0
3979 | i.sib.index << 3
3980 | i.sib.scale << 6),
3981 1);
3982 }
3983 }
3e73aa7c 3984
29b0f896 3985 if (i.disp_operands)
2bbd9c25 3986 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3987
29b0f896 3988 if (i.imm_operands)
2bbd9c25 3989 output_imm (insn_start_frag, insn_start_off);
29b0f896 3990 }
252b5132 3991
29b0f896
AM		 3992#ifdef DEBUG386
3993 if (flag_debug)
3994 {
7b81dfbb 3995 pi ("" /*line*/, &i);
29b0f896
AM		 3996 }
3997#endif /* DEBUG386 */
3998}
252b5132 3999
29b0f896 4000static void
64e74474 4001output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4002{
4003 char *p;
4004 unsigned int n;
252b5132 4005
29b0f896
AM		 4006 for (n = 0; n < i.operands; n++)
4007 {
4008 if (i.types[n] & Disp)
4009 {
4010 if (i.op[n].disps->X_op == O_constant)
4011 {
4012 int size;
4013 offsetT val;
252b5132 4014
29b0f896
AM		 4015 size = 4;
4016 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4017 {
4018 size = 2;
4019 if (i.types[n] & Disp8)
4020 size = 1;
4021 if (i.types[n] & Disp64)
4022 size = 8;
4023 }
4024 val = offset_in_range (i.op[n].disps->X_add_number,
4025 size);
4026 p = frag_more (size);
4027 md_number_to_chars (p, val, size);
4028 }
4029 else
4030 {
f86103b7 4031 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4032 int size = 4;
4033 int sign = 0;
4034 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4035
4036 /* The PC relative address is computed relative
4037 to the instruction boundary, so in case immediate
4038 fields follows, we need to adjust the value. */
4039 if (pcrel && i.imm_operands)
4040 {
4041 int imm_size = 4;
4042 unsigned int n1;
252b5132 4043
29b0f896
AM		 4044 for (n1 = 0; n1 < i.operands; n1++)
4045 if (i.types[n1] & Imm)
252b5132 4046 {
29b0f896 4047 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4048 {
29b0f896
AM		 4049 imm_size = 2;
4050 if (i.types[n1] & (Imm8 | Imm8S))
4051 imm_size = 1;
4052 if (i.types[n1] & Imm64)
4053 imm_size = 8;
252b5132 4054 }
29b0f896 4055 break;
252b5132 4056 }
29b0f896
AM		 4057 /* We should find the immediate. */
4058 if (n1 == i.operands)
4059 abort ();
4060 i.op[n].disps->X_add_number -= imm_size;
4061 }
520dc8e8 4062
29b0f896
AM		 4063 if (i.types[n] & Disp32S)
4064 sign = 1;
3e73aa7c 4065
29b0f896
AM		 4066 if (i.types[n] & (Disp16 | Disp64))
4067 {
4068 size = 2;
4069 if (i.types[n] & Disp64)
4070 size = 8;
4071 }
520dc8e8 4072
29b0f896 4073 p = frag_more (size);
2bbd9c25 4074 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4075 if (GOT_symbol
2bbd9c25 4076 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4077 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4078 || reloc_type == BFD_RELOC_X86_64_32S
4079 || (reloc_type == BFD_RELOC_64
4080 && object_64bit))
d6ab8113
JB		 4081 && (i.op[n].disps->X_op == O_symbol
4082 || (i.op[n].disps->X_op == O_add
4083 && ((symbol_get_value_expression
4084 (i.op[n].disps->X_op_symbol)->X_op)
4085 == O_subtract))))
4086 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4087 {
4088 offsetT add;
4089
4090 if (insn_start_frag == frag_now)
4091 add = (p - frag_now->fr_literal) - insn_start_off;
4092 else
4093 {
4094 fragS *fr;
4095
4096 add = insn_start_frag->fr_fix - insn_start_off;
4097 for (fr = insn_start_frag->fr_next;
4098 fr && fr != frag_now; fr = fr->fr_next)
4099 add += fr->fr_fix;
4100 add += p - frag_now->fr_literal;
4101 }
4102
4fa24527 4103 if (!object_64bit)
7b81dfbb
AJ		 4104 {
4105 reloc_type = BFD_RELOC_386_GOTPC;
4106 i.op[n].imms->X_add_number += add;
4107 }
4108 else if (reloc_type == BFD_RELOC_64)
4109 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4110 else
7b81dfbb
AJ		 4111 /* Don't do the adjustment for x86-64, as there
4112 the pcrel addressing is relative to the _next_
4113 insn, and that is taken care of in other code. */
d6ab8113 4114 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4115 }
062cd5e7 4116 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4117 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4118 }
4119 }
4120 }
4121}
252b5132 4122
29b0f896 4123static void
64e74474 4124output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4125{
4126 char *p;
4127 unsigned int n;
252b5132 4128
29b0f896
AM		 4129 for (n = 0; n < i.operands; n++)
4130 {
4131 if (i.types[n] & Imm)
4132 {
4133 if (i.op[n].imms->X_op == O_constant)
4134 {
4135 int size;
4136 offsetT val;
b4cac588 4137
29b0f896
AM		 4138 size = 4;
4139 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4140 {
4141 size = 2;
4142 if (i.types[n] & (Imm8 | Imm8S))
4143 size = 1;
4144 else if (i.types[n] & Imm64)
4145 size = 8;
4146 }
4147 val = offset_in_range (i.op[n].imms->X_add_number,
4148 size);
4149 p = frag_more (size);
4150 md_number_to_chars (p, val, size);
4151 }
4152 else
4153 {
4154 /* Not absolute_section.
4155 Need a 32-bit fixup (don't support 8bit
4156 non-absolute imms). Try to support other
4157 sizes ... */
f86103b7 4158 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4159 int size = 4;
4160 int sign = 0;
4161
4162 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4163 && (i.suffix == QWORD_MNEM_SUFFIX
4164 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4165 sign = 1;
4166 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4167 {
4168 size = 2;
4169 if (i.types[n] & (Imm8 | Imm8S))
4170 size = 1;
4171 if (i.types[n] & Imm64)
4172 size = 8;
4173 }
520dc8e8 4174
29b0f896
AM		 4175 p = frag_more (size);
4176 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4177
2bbd9c25
JJ		 4178 /* This is tough to explain. We end up with this one if we
4179 * have operands that look like
4180 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4181 * obtain the absolute address of the GOT, and it is strongly
4182 * preferable from a performance point of view to avoid using
4183 * a runtime relocation for this. The actual sequence of
4184 * instructions often look something like:
4185 *
4186 * call .L66
4187 * .L66:
4188 * popl %ebx
4189 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4190 *
4191 * The call and pop essentially return the absolute address
4192 * of the label .L66 and store it in %ebx. The linker itself
4193 * will ultimately change the first operand of the addl so
4194 * that %ebx points to the GOT, but to keep things simple, the
4195 * .o file must have this operand set so that it generates not
4196 * the absolute address of .L66, but the absolute address of
4197 * itself. This allows the linker itself simply treat a GOTPC
4198 * relocation as asking for a pcrel offset to the GOT to be
4199 * added in, and the addend of the relocation is stored in the
4200 * operand field for the instruction itself.
4201 *
4202 * Our job here is to fix the operand so that it would add
4203 * the correct offset so that %ebx would point to itself. The
4204 * thing that is tricky is that .-.L66 will point to the
4205 * beginning of the instruction, so we need to further modify
4206 * the operand so that it will point to itself. There are
4207 * other cases where you have something like:
4208 *
4209 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4210 *
4211 * and here no correction would be required. Internally in
4212 * the assembler we treat operands of this form as not being
4213 * pcrel since the '.' is explicitly mentioned, and I wonder
4214 * whether it would simplify matters to do it this way. Who
4215 * knows. In earlier versions of the PIC patches, the
4216 * pcrel_adjust field was used to store the correction, but
4217 * since the expression is not pcrel, I felt it would be
4218 * confusing to do it this way. */
4219
d6ab8113 4220 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4221 || reloc_type == BFD_RELOC_X86_64_32S
4222 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4223 && GOT_symbol
4224 && GOT_symbol == i.op[n].imms->X_add_symbol
4225 && (i.op[n].imms->X_op == O_symbol
4226 || (i.op[n].imms->X_op == O_add
4227 && ((symbol_get_value_expression
4228 (i.op[n].imms->X_op_symbol)->X_op)
4229 == O_subtract))))
4230 {
2bbd9c25
JJ		 4231 offsetT add;
4232
4233 if (insn_start_frag == frag_now)
4234 add = (p - frag_now->fr_literal) - insn_start_off;
4235 else
4236 {
4237 fragS *fr;
4238
4239 add = insn_start_frag->fr_fix - insn_start_off;
4240 for (fr = insn_start_frag->fr_next;
4241 fr && fr != frag_now; fr = fr->fr_next)
4242 add += fr->fr_fix;
4243 add += p - frag_now->fr_literal;
4244 }
4245
4fa24527 4246 if (!object_64bit)
d6ab8113 4247 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4248 else if (size == 4)
d6ab8113 4249 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4250 else if (size == 8)
4251 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4252 i.op[n].imms->X_add_number += add;
29b0f896 4253 }
29b0f896
AM		 4254 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4255 i.op[n].imms, 0, reloc_type);
4256 }
4257 }
4258 }
252b5132
RH		 4259}
4260\f
d182319b
JB		 4261/* x86_cons_fix_new is called via the expression parsing code when a
4262 reloc is needed. We use this hook to get the correct .got reloc. */
4263static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4264static int cons_sign = -1;
4265
4266void
e3bb37b5 4267x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4268 expressionS *exp)
d182319b
JB		 4269{
4270 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4271
4272 got_reloc = NO_RELOC;
4273
4274#ifdef TE_PE
4275 if (exp->X_op == O_secrel)
4276 {
4277 exp->X_op = O_symbol;
4278 r = BFD_RELOC_32_SECREL;
4279 }
4280#endif
4281
4282 fix_new_exp (frag, off, len, exp, 0, r);
4283}
4284
718ddfc0
JB		 4285#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4286# define lex_got(reloc, adjust, types) NULL
4287#else
f3c180ae
AM		 4288/* Parse operands of the form
4289 <symbol>@GOTOFF+<nnn>
4290 and similar .plt or .got references.
4291
4292 If we find one, set up the correct relocation in RELOC and copy the
4293 input string, minus the `@GOTOFF' into a malloc'd buffer for
4294 parsing by the calling routine. Return this buffer, and if ADJUST
4295 is non-null set it to the length of the string we removed from the
4296 input line. Otherwise return NULL. */
4297static char *
3956db08 4298lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4299 int *adjust,
4300 unsigned int *types)
f3c180ae 4301{
7b81dfbb
AJ		 4302 /* Some of the relocations depend on the size of what field is to
4303 be relocated. But in our callers i386_immediate and i386_displacement
4304 we don't yet know the operand size (this will be set by insn
4305 matching). Hence we record the word32 relocation here,
4306 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4307 static const struct {
4308 const char *str;
4fa24527 4309 const enum bfd_reloc_code_real rel[2];
3956db08 4310 const unsigned int types64;
f3c180ae 4311 } gotrel[] = {
7b81dfbb 4312 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4313 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4314 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4315 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4316 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4317 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4318 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4319 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4320 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4321 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4322 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4323 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4324 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4325 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4326 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4327 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4328 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4329 };
4330 char *cp;
4331 unsigned int j;
4332
718ddfc0
JB		 4333 if (!IS_ELF)
4334 return NULL;
4335
f3c180ae
AM		 4336 for (cp = input_line_pointer; *cp != '@'; cp++)
4337 if (is_end_of_line[(unsigned char) *cp])
4338 return NULL;
4339
4340 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4341 {
4342 int len;
4343
4344 len = strlen (gotrel[j].str);
28f81592 4345 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4346 {
4fa24527 4347 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4348 {
28f81592
AM		 4349 int first, second;
4350 char *tmpbuf, *past_reloc;
f3c180ae 4351
4fa24527 4352 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4353 if (adjust)
4354 *adjust = len;
f3c180ae 4355
3956db08
JB		 4356 if (types)
4357 {
4358 if (flag_code != CODE_64BIT)
4359 *types = Imm32|Disp32;
4360 else
4361 *types = gotrel[j].types64;
4362 }
4363
f3c180ae
AM		 4364 if (GOT_symbol == NULL)
4365 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4366
4367 /* Replace the relocation token with ' ', so that
4368 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4369
4370 /* The length of the first part of our input line. */
f3c180ae 4371 first = cp - input_line_pointer;
28f81592
AM		 4372
4373 /* The second part goes from after the reloc token until
4374 (and including) an end_of_line char. Don't use strlen
4375 here as the end_of_line char may not be a NUL. */
4376 past_reloc = cp + 1 + len;
4377 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4378 ;
4379 second = cp - past_reloc;
4380
4381 /* Allocate and copy string. The trailing NUL shouldn't
4382 be necessary, but be safe. */
4383 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4384 memcpy (tmpbuf, input_line_pointer, first);
4385 tmpbuf[first] = ' ';
28f81592
AM		 4386 memcpy (tmpbuf + first + 1, past_reloc, second);
4387 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4388 return tmpbuf;
4389 }
4390
4fa24527
JB		 4391 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4392 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4393 return NULL;
4394 }
4395 }
4396
4397 /* Might be a symbol version string. Don't as_bad here. */
4398 return NULL;
4399}
4400
f3c180ae 4401void
e3bb37b5 4402x86_cons (expressionS *exp, int size)
f3c180ae 4403{
4fa24527 4404 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4405 {
4406 /* Handle @GOTOFF and the like in an expression. */
4407 char *save;
4408 char *gotfree_input_line;
4409 int adjust;
4410
4411 save = input_line_pointer;
3956db08 4412 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4413 if (gotfree_input_line)
4414 input_line_pointer = gotfree_input_line;
4415
4416 expression (exp);
4417
4418 if (gotfree_input_line)
4419 {
4420 /* expression () has merrily parsed up to the end of line,
4421 or a comma - in the wrong buffer. Transfer how far
4422 input_line_pointer has moved to the right buffer. */
4423 input_line_pointer = (save
4424 + (input_line_pointer - gotfree_input_line)
4425 + adjust);
4426 free (gotfree_input_line);
4427 }
4428 }
4429 else
4430 expression (exp);
4431}
4432#endif
4433
d182319b 4434static void signed_cons (int size)
6482c264 4435{
d182319b
JB		 4436 if (flag_code == CODE_64BIT)
4437 cons_sign = 1;
4438 cons (size);
4439 cons_sign = -1;
6482c264
NC		 4440}
4441
d182319b 4442#ifdef TE_PE
6482c264
NC		 4443static void
4444pe_directive_secrel (dummy)
4445 int dummy ATTRIBUTE_UNUSED;
4446{
4447 expressionS exp;
4448
4449 do
4450 {
4451 expression (&exp);
4452 if (exp.X_op == O_symbol)
4453 exp.X_op = O_secrel;
4454
4455 emit_expr (&exp, 4);
4456 }
4457 while (*input_line_pointer++ == ',');
4458
4459 input_line_pointer--;
4460 demand_empty_rest_of_line ();
4461}
6482c264
NC		 4462#endif
4463
252b5132 4464static int
70e41ade 4465i386_immediate (char *imm_start)
252b5132
RH		 4466{
4467 char *save_input_line_pointer;
f3c180ae 4468 char *gotfree_input_line;
252b5132 4469 segT exp_seg = 0;
47926f60 4470 expressionS *exp;
3956db08 4471 unsigned int types = ~0U;
252b5132
RH		 4472
4473 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4474 {
31b2323c
L		 4475 as_bad (_("at most %d immediate operands are allowed"),
4476 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4477 return 0;
4478 }
4479
4480 exp = &im_expressions[i.imm_operands++];
520dc8e8 4481 i.op[this_operand].imms = exp;
252b5132
RH		 4482
4483 if (is_space_char (*imm_start))
4484 ++imm_start;
4485
4486 save_input_line_pointer = input_line_pointer;
4487 input_line_pointer = imm_start;
4488
3956db08 4489 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4490 if (gotfree_input_line)
4491 input_line_pointer = gotfree_input_line;
252b5132
RH		 4492
4493 exp_seg = expression (exp);
4494
83183c0c 4495 SKIP_WHITESPACE ();
252b5132 4496 if (*input_line_pointer)
f3c180ae 4497 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4498
4499 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4500 if (gotfree_input_line)
4501 free (gotfree_input_line);
252b5132 4502
2daf4fd8 4503 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4504 {
47926f60 4505 /* Missing or bad expr becomes absolute 0. */
d0b47220 4506 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4507 imm_start);
252b5132
RH		 4508 exp->X_op = O_constant;
4509 exp->X_add_number = 0;
4510 exp->X_add_symbol = (symbolS *) 0;
4511 exp->X_op_symbol = (symbolS *) 0;
252b5132 4512 }
3e73aa7c 4513 else if (exp->X_op == O_constant)
252b5132 4514 {
47926f60 4515 /* Size it properly later. */
3e73aa7c
JH		 4516 i.types[this_operand] |= Imm64;
4517 /* If BFD64, sign extend val. */
4518 if (!use_rela_relocations)
4519 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4520 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4521 }
4c63da97 4522#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4523 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4524 && exp_seg != absolute_section
47926f60 4525 && exp_seg != text_section
24eab124
AM		 4526 && exp_seg != data_section
4527 && exp_seg != bss_section
4528 && exp_seg != undefined_section
f86103b7 4529 && !bfd_is_com_section (exp_seg))
252b5132 4530 {
d0b47220 4531 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4532 return 0;
4533 }
4534#endif
bb8f5920
L		 4535 else if (!intel_syntax && exp->X_op == O_register)
4536 {
4537 as_bad (_("illegal immediate register operand %s"), imm_start);
4538 return 0;
4539 }
252b5132
RH		 4540 else
4541 {
4542 /* This is an address. The size of the address will be
24eab124 4543 determined later, depending on destination register,
3e73aa7c
JH		 4544 suffix, or the default for the section. */
4545 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4546 i.types[this_operand] &= types;
252b5132
RH		 4547 }
4548
4549 return 1;
4550}
4551
551c1ca1 4552static char *
e3bb37b5 4553i386_scale (char *scale)
252b5132 4554{
551c1ca1
AM		 4555 offsetT val;
4556 char *save = input_line_pointer;
252b5132 4557
551c1ca1
AM		 4558 input_line_pointer = scale;
4559 val = get_absolute_expression ();
4560
4561 switch (val)
252b5132 4562 {
551c1ca1 4563 case 1:
252b5132
RH		 4564 i.log2_scale_factor = 0;
4565 break;
551c1ca1 4566 case 2:
252b5132
RH		 4567 i.log2_scale_factor = 1;
4568 break;
551c1ca1 4569 case 4:
252b5132
RH		 4570 i.log2_scale_factor = 2;
4571 break;
551c1ca1 4572 case 8:
252b5132
RH		 4573 i.log2_scale_factor = 3;
4574 break;
4575 default:
a724f0f4
JB		 4576 {
4577 char sep = *input_line_pointer;
4578
4579 *input_line_pointer = '\0';
4580 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4581 scale);
4582 *input_line_pointer = sep;
4583 input_line_pointer = save;
4584 return NULL;
4585 }
252b5132 4586 }
29b0f896 4587 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4588 {
4589 as_warn (_("scale factor of %d without an index register"),
24eab124 4590 1 << i.log2_scale_factor);
252b5132
RH		 4591#if SCALE1_WHEN_NO_INDEX
4592 i.log2_scale_factor = 0;
4593#endif
4594 }
551c1ca1
AM		 4595 scale = input_line_pointer;
4596 input_line_pointer = save;
4597 return scale;
252b5132
RH		 4598}
4599
252b5132 4600static int
e3bb37b5 4601i386_displacement (char *disp_start, char *disp_end)
252b5132 4602{
29b0f896 4603 expressionS *exp;
252b5132
RH		 4604 segT exp_seg = 0;
4605 char *save_input_line_pointer;
f3c180ae 4606 char *gotfree_input_line;
e05278af 4607 int bigdisp, override;
3956db08 4608 unsigned int types = Disp;
252b5132 4609
31b2323c
L		 4610 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4611 {
4612 as_bad (_("at most %d displacement operands are allowed"),
4613 MAX_MEMORY_OPERANDS);
4614 return 0;
4615 }
4616
e05278af
JB		 4617 if ((i.types[this_operand] & JumpAbsolute)
4618 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4619 {
4620 bigdisp = Disp32;
4621 override = (i.prefix[ADDR_PREFIX] != 0);
4622 }
4623 else
4624 {
4625 /* For PC-relative branches, the width of the displacement
4626 is dependent upon data size, not address size. */
4627 bigdisp = 0;
4628 override = (i.prefix[DATA_PREFIX] != 0);
4629 }
3e73aa7c 4630 if (flag_code == CODE_64BIT)
7ecd2f8b 4631 {
e05278af 4632 if (!bigdisp)
64e74474
AM		 4633 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4634 ? Disp16
4635 : Disp32S | Disp32);
e05278af 4636 else if (!override)
3956db08 4637 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4638 }
e05278af
JB		 4639 else
4640 {
4641 if (!bigdisp)
4642 {
4643 if (!override)
4644 override = (i.suffix == (flag_code != CODE_16BIT
4645 ? WORD_MNEM_SUFFIX
4646 : LONG_MNEM_SUFFIX));
4647 bigdisp = Disp32;
4648 }
4649 if ((flag_code == CODE_16BIT) ^ override)
4650 bigdisp = Disp16;
4651 }
252b5132
RH		 4652 i.types[this_operand] |= bigdisp;
4653
4654 exp = &disp_expressions[i.disp_operands];
520dc8e8 4655 i.op[this_operand].disps = exp;
252b5132
RH		 4656 i.disp_operands++;
4657 save_input_line_pointer = input_line_pointer;
4658 input_line_pointer = disp_start;
4659 END_STRING_AND_SAVE (disp_end);
4660
4661#ifndef GCC_ASM_O_HACK
4662#define GCC_ASM_O_HACK 0
4663#endif
4664#if GCC_ASM_O_HACK
4665 END_STRING_AND_SAVE (disp_end + 1);
4666 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4667 && displacement_string_end[-1] == '+')
252b5132
RH		 4668 {
4669 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4670 constraint within gcc asm statements.
4671 For instance:
4672
4673 #define _set_tssldt_desc(n,addr,limit,type) \
4674 __asm__ __volatile__ ( \
4675 "movw %w2,%0\n\t" \
4676 "movw %w1,2+%0\n\t" \
4677 "rorl $16,%1\n\t" \
4678 "movb %b1,4+%0\n\t" \
4679 "movb %4,5+%0\n\t" \
4680 "movb $0,6+%0\n\t" \
4681 "movb %h1,7+%0\n\t" \
4682 "rorl $16,%1" \
4683 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4684
4685 This works great except that the output assembler ends
4686 up looking a bit weird if it turns out that there is
4687 no offset. You end up producing code that looks like:
4688
4689 #APP
4690 movw $235,(%eax)
4691 movw %dx,2+(%eax)
4692 rorl $16,%edx
4693 movb %dl,4+(%eax)
4694 movb $137,5+(%eax)
4695 movb $0,6+(%eax)
4696 movb %dh,7+(%eax)
4697 rorl $16,%edx
4698 #NO_APP
4699
47926f60 4700 So here we provide the missing zero. */
24eab124
AM		 4701
4702 *displacement_string_end = '0';
252b5132
RH		 4703 }
4704#endif
3956db08 4705 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4706 if (gotfree_input_line)
4707 input_line_pointer = gotfree_input_line;
252b5132 4708
24eab124 4709 exp_seg = expression (exp);
252b5132 4710
636c26b0
AM		 4711 SKIP_WHITESPACE ();
4712 if (*input_line_pointer)
4713 as_bad (_("junk `%s' after expression"), input_line_pointer);
4714#if GCC_ASM_O_HACK
4715 RESTORE_END_STRING (disp_end + 1);
4716#endif
4717 RESTORE_END_STRING (disp_end);
4718 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4719 if (gotfree_input_line)
4720 free (gotfree_input_line);
636c26b0 4721
24eab124
AM		 4722 /* We do this to make sure that the section symbol is in
4723 the symbol table. We will ultimately change the relocation
47926f60 4724 to be relative to the beginning of the section. */
1ae12ab7 4725 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4726 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4727 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4728 {
636c26b0
AM		 4729 if (exp->X_op != O_symbol)
4730 {
4731 as_bad (_("bad expression used with @%s"),
4732 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4733 ? "GOTPCREL"
4734 : "GOTOFF"));
4735 return 0;
4736 }
4737
e5cb08ac 4738 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4739 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4740 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4741 exp->X_op = O_subtract;
4742 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4743 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4744 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4745 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4746 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4747 else
29b0f896 4748 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4749 }
252b5132 4750
2daf4fd8
AM		 4751 if (exp->X_op == O_absent || exp->X_op == O_big)
4752 {
47926f60 4753 /* Missing or bad expr becomes absolute 0. */
d0b47220 4754 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4755 disp_start);
4756 exp->X_op = O_constant;
4757 exp->X_add_number = 0;
4758 exp->X_add_symbol = (symbolS *) 0;
4759 exp->X_op_symbol = (symbolS *) 0;
4760 }
4761
4c63da97 4762#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4763 if (exp->X_op != O_constant
45288df1 4764 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4765 && exp_seg != absolute_section
45288df1
AM		 4766 && exp_seg != text_section
4767 && exp_seg != data_section
4768 && exp_seg != bss_section
31312f95 4769 && exp_seg != undefined_section
f86103b7 4770 && !bfd_is_com_section (exp_seg))
24eab124 4771 {
d0b47220 4772 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4773 return 0;
4774 }
252b5132 4775#endif
3956db08
JB		 4776
4777 if (!(i.types[this_operand] & ~Disp))
4778 i.types[this_operand] &= types;
4779
252b5132
RH		 4780 return 1;
4781}
4782
eecb386c 4783/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4784 Return 1 on success, 0 on a failure. */
4785
252b5132 4786static int
e3bb37b5 4787i386_index_check (const char *operand_string)
252b5132 4788{
3e73aa7c 4789 int ok;
24eab124 4790#if INFER_ADDR_PREFIX
eecb386c
AM		 4791 int fudged = 0;
4792
24eab124
AM		 4793 tryprefix:
4794#endif
3e73aa7c 4795 ok = 1;
30123838
JB		 4796 if ((current_templates->start->cpu_flags & CpuSVME)
4797 && current_templates->end[-1].operand_types[0] == AnyMem)
4798 {
4799 /* Memory operands of SVME insns are special in that they only allow
4800 rAX as their memory address and ignore any segment override. */
4801 unsigned RegXX;
4802
4803 /* SKINIT is even more restrictive: it always requires EAX. */
4804 if (strcmp (current_templates->start->name, "skinit") == 0)
4805 RegXX = Reg32;
4806 else if (flag_code == CODE_64BIT)
4807 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4808 else
64e74474
AM		 4809 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4810 ? Reg16
4811 : Reg32);
30123838
JB		 4812 if (!i.base_reg
4813 || !(i.base_reg->reg_type & Acc)
4814 || !(i.base_reg->reg_type & RegXX)
4815 || i.index_reg
4816 || (i.types[0] & Disp))
4817 ok = 0;
4818 }
4819 else if (flag_code == CODE_64BIT)
64e74474
AM		 4820 {
4821 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4822
4823 if ((i.base_reg
4824 && ((i.base_reg->reg_type & RegXX) == 0)
4825 && (i.base_reg->reg_type != BaseIndex
4826 || i.index_reg))
4827 || (i.index_reg
4828 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4829 != (RegXX | BaseIndex))))
4830 ok = 0;
3e73aa7c
JH		 4831 }
4832 else
4833 {
4834 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4835 {
4836 /* 16bit checks. */
4837 if ((i.base_reg
29b0f896
AM		 4838 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4839 != (Reg16 | BaseIndex)))
3e73aa7c 4840 || (i.index_reg
29b0f896
AM		 4841 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4842 != (Reg16 | BaseIndex))
4843 || !(i.base_reg
4844 && i.base_reg->reg_num < 6
4845 && i.index_reg->reg_num >= 6
4846 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4847 ok = 0;
4848 }
4849 else
e5cb08ac 4850 {
3e73aa7c
JH		 4851 /* 32bit checks. */
4852 if ((i.base_reg
4853 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4854 || (i.index_reg
29b0f896
AM		 4855 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4856 != (Reg32 | BaseIndex))))
e5cb08ac 4857 ok = 0;
3e73aa7c
JH		 4858 }
4859 }
4860 if (!ok)
24eab124
AM		 4861 {
4862#if INFER_ADDR_PREFIX
20f0a1fc 4863 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4864 {
4865 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4866 i.prefixes += 1;
b23bac36
AM		 4867 /* Change the size of any displacement too. At most one of
4868 Disp16 or Disp32 is set.
4869 FIXME. There doesn't seem to be any real need for separate
4870 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4871 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4872 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4873 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4874 fudged = 1;
24eab124
AM		 4875 goto tryprefix;
4876 }
eecb386c
AM		 4877 if (fudged)
4878 as_bad (_("`%s' is not a valid base/index expression"),
4879 operand_string);
4880 else
c388dee8 4881#endif
eecb386c
AM		 4882 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4883 operand_string,
3e73aa7c 4884 flag_code_names[flag_code]);
24eab124 4885 }
20f0a1fc 4886 return ok;
24eab124 4887}
252b5132 4888
252b5132 4889/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4890 on error. */
252b5132 4891
252b5132 4892static int
e3bb37b5 4893i386_operand (char *operand_string)
252b5132 4894{
af6bdddf
AM		 4895 const reg_entry *r;
4896 char *end_op;
24eab124 4897 char *op_string = operand_string;
252b5132 4898
24eab124 4899 if (is_space_char (*op_string))
252b5132
RH		 4900 ++op_string;
4901
24eab124 4902 /* We check for an absolute prefix (differentiating,
47926f60 4903 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4904 if (*op_string == ABSOLUTE_PREFIX)
4905 {
4906 ++op_string;
4907 if (is_space_char (*op_string))
4908 ++op_string;
4909 i.types[this_operand] |= JumpAbsolute;
4910 }
252b5132 4911
47926f60 4912 /* Check if operand is a register. */
4d1bb795 4913 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4914 {
24eab124
AM		 4915 /* Check for a segment override by searching for ':' after a
4916 segment register. */
4917 op_string = end_op;
4918 if (is_space_char (*op_string))
4919 ++op_string;
4920 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4921 {
4922 switch (r->reg_num)
4923 {
4924 case 0:
4925 i.seg[i.mem_operands] = &es;
4926 break;
4927 case 1:
4928 i.seg[i.mem_operands] = &cs;
4929 break;
4930 case 2:
4931 i.seg[i.mem_operands] = &ss;
4932 break;
4933 case 3:
4934 i.seg[i.mem_operands] = &ds;
4935 break;
4936 case 4:
4937 i.seg[i.mem_operands] = &fs;
4938 break;
4939 case 5:
4940 i.seg[i.mem_operands] = &gs;
4941 break;
4942 }
252b5132 4943
24eab124 4944 /* Skip the ':' and whitespace. */
252b5132
RH		 4945 ++op_string;
4946 if (is_space_char (*op_string))
24eab124 4947 ++op_string;
252b5132 4948
24eab124
AM		 4949 if (!is_digit_char (*op_string)
4950 && !is_identifier_char (*op_string)
4951 && *op_string != '('
4952 && *op_string != ABSOLUTE_PREFIX)
4953 {
4954 as_bad (_("bad memory operand `%s'"), op_string);
4955 return 0;
4956 }
47926f60 4957 /* Handle case of %es:*foo. */
24eab124
AM		 4958 if (*op_string == ABSOLUTE_PREFIX)
4959 {
4960 ++op_string;
4961 if (is_space_char (*op_string))
4962 ++op_string;
4963 i.types[this_operand] |= JumpAbsolute;
4964 }
4965 goto do_memory_reference;
4966 }
4967 if (*op_string)
4968 {
d0b47220 4969 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4970 return 0;
4971 }
4972 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4973 i.op[this_operand].regs = r;
24eab124
AM		 4974 i.reg_operands++;
4975 }
af6bdddf
AM		 4976 else if (*op_string == REGISTER_PREFIX)
4977 {
4978 as_bad (_("bad register name `%s'"), op_string);
4979 return 0;
4980 }
24eab124 4981 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4982 {
24eab124
AM		 4983 ++op_string;
4984 if (i.types[this_operand] & JumpAbsolute)
4985 {
d0b47220 4986 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4987 return 0;
4988 }
4989 if (!i386_immediate (op_string))
4990 return 0;
4991 }
4992 else if (is_digit_char (*op_string)
4993 || is_identifier_char (*op_string)
e5cb08ac 4994 || *op_string == '(')
24eab124 4995 {
47926f60 4996 /* This is a memory reference of some sort. */
af6bdddf 4997 char *base_string;
252b5132 4998
47926f60 4999 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5000 char *displacement_string_start;
5001 char *displacement_string_end;
252b5132 5002
24eab124 5003 do_memory_reference:
24eab124
AM		 5004 if ((i.mem_operands == 1
5005 && (current_templates->start->opcode_modifier & IsString) == 0)
5006 || i.mem_operands == 2)
5007 {
5008 as_bad (_("too many memory references for `%s'"),
5009 current_templates->start->name);
5010 return 0;
5011 }
252b5132 5012
24eab124
AM		 5013 /* Check for base index form. We detect the base index form by
5014 looking for an ')' at the end of the operand, searching
5015 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5016 after the '('. */
af6bdddf 5017 base_string = op_string + strlen (op_string);
c3332e24 5018
af6bdddf
AM		 5019 --base_string;
5020 if (is_space_char (*base_string))
5021 --base_string;
252b5132 5022
47926f60 5023 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5024 displacement_string_start = op_string;
5025 displacement_string_end = base_string + 1;
252b5132 5026
24eab124
AM		 5027 if (*base_string == ')')
5028 {
af6bdddf 5029 char *temp_string;
24eab124
AM		 5030 unsigned int parens_balanced = 1;
5031 /* We've already checked that the number of left & right ()'s are
47926f60 5032 equal, so this loop will not be infinite. */
24eab124
AM		 5033 do
5034 {
5035 base_string--;
5036 if (*base_string == ')')
5037 parens_balanced++;
5038 if (*base_string == '(')
5039 parens_balanced--;
5040 }
5041 while (parens_balanced);
c3332e24 5042
af6bdddf 5043 temp_string = base_string;
c3332e24 5044
24eab124 5045 /* Skip past '(' and whitespace. */
252b5132
RH		 5046 ++base_string;
5047 if (is_space_char (*base_string))
24eab124 5048 ++base_string;
252b5132 5049
af6bdddf 5050 if (*base_string == ','
4d1bb795 5051 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5052 {
af6bdddf 5053 displacement_string_end = temp_string;
252b5132 5054
af6bdddf 5055 i.types[this_operand] |= BaseIndex;
252b5132 5056
af6bdddf 5057 if (i.base_reg)
24eab124 5058 {
24eab124
AM		 5059 base_string = end_op;
5060 if (is_space_char (*base_string))
5061 ++base_string;
af6bdddf
AM		 5062 }
5063
5064 /* There may be an index reg or scale factor here. */
5065 if (*base_string == ',')
5066 {
5067 ++base_string;
5068 if (is_space_char (*base_string))
5069 ++base_string;
5070
4d1bb795 5071 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5072 {
af6bdddf 5073 base_string = end_op;
24eab124
AM		 5074 if (is_space_char (*base_string))
5075 ++base_string;
af6bdddf
AM		 5076 if (*base_string == ',')
5077 {
5078 ++base_string;
5079 if (is_space_char (*base_string))
5080 ++base_string;
5081 }
e5cb08ac 5082 else if (*base_string != ')')
af6bdddf
AM		 5083 {
5084 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5085 operand_string);
5086 return 0;
5087 }
24eab124 5088 }
af6bdddf 5089 else if (*base_string == REGISTER_PREFIX)
24eab124 5090 {
af6bdddf 5091 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5092 return 0;
5093 }
252b5132 5094
47926f60 5095 /* Check for scale factor. */
551c1ca1 5096 if (*base_string != ')')
af6bdddf 5097 {
551c1ca1
AM		 5098 char *end_scale = i386_scale (base_string);
5099
5100 if (!end_scale)
af6bdddf 5101 return 0;
24eab124 5102
551c1ca1 5103 base_string = end_scale;
af6bdddf
AM		 5104 if (is_space_char (*base_string))
5105 ++base_string;
5106 if (*base_string != ')')
5107 {
5108 as_bad (_("expecting `)' after scale factor in `%s'"),
5109 operand_string);
5110 return 0;
5111 }
5112 }
5113 else if (!i.index_reg)
24eab124 5114 {
af6bdddf
AM		 5115 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5116 *base_string);
24eab124
AM		 5117 return 0;
5118 }
5119 }
af6bdddf 5120 else if (*base_string != ')')
24eab124 5121 {
af6bdddf
AM		 5122 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5123 operand_string);
24eab124
AM		 5124 return 0;
5125 }
c3332e24 5126 }
af6bdddf 5127 else if (*base_string == REGISTER_PREFIX)
c3332e24 5128 {
af6bdddf 5129 as_bad (_("bad register name `%s'"), base_string);
24eab124 5130 return 0;
c3332e24 5131 }
24eab124
AM		 5132 }
5133
5134 /* If there's an expression beginning the operand, parse it,
5135 assuming displacement_string_start and
5136 displacement_string_end are meaningful. */
5137 if (displacement_string_start != displacement_string_end)
5138 {
5139 if (!i386_displacement (displacement_string_start,
5140 displacement_string_end))
5141 return 0;
5142 }
5143
5144 /* Special case for (%dx) while doing input/output op. */
5145 if (i.base_reg
5146 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5147 && i.index_reg == 0
5148 && i.log2_scale_factor == 0
5149 && i.seg[i.mem_operands] == 0
5150 && (i.types[this_operand] & Disp) == 0)
5151 {
5152 i.types[this_operand] = InOutPortReg;
5153 return 1;
5154 }
5155
eecb386c
AM		 5156 if (i386_index_check (operand_string) == 0)
5157 return 0;
24eab124
AM		 5158 i.mem_operands++;
5159 }
5160 else
ce8a8b2f
AM		 5161 {
5162 /* It's not a memory operand; argh! */
24eab124
AM		 5163 as_bad (_("invalid char %s beginning operand %d `%s'"),
5164 output_invalid (*op_string),
5165 this_operand + 1,
5166 op_string);
5167 return 0;
5168 }
47926f60 5169 return 1; /* Normal return. */
252b5132
RH		 5170}
5171\f
ee7fcc42
AM		 5172/* md_estimate_size_before_relax()
5173
5174 Called just before relax() for rs_machine_dependent frags. The x86
5175 assembler uses these frags to handle variable size jump
5176 instructions.
5177
5178 Any symbol that is now undefined will not become defined.
5179 Return the correct fr_subtype in the frag.
5180 Return the initial "guess for variable size of frag" to caller.
5181 The guess is actually the growth beyond the fixed part. Whatever
5182 we do to grow the fixed or variable part contributes to our
5183 returned value. */
5184
252b5132
RH		 5185int
5186md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5187 fragS *fragP;
5188 segT segment;
252b5132 5189{
252b5132 5190 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5191 check for un-relaxable symbols. On an ELF system, we can't relax
5192 an externally visible symbol, because it may be overridden by a
5193 shared library. */
5194 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5195#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5196 || (IS_ELF
31312f95
AM		 5197 && (S_IS_EXTERNAL (fragP->fr_symbol)
5198 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5199#endif
5200 )
252b5132 5201 {
b98ef147
AM		 5202 /* Symbol is undefined in this segment, or we need to keep a
5203 reloc so that weak symbols can be overridden. */
5204 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5205 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5206 unsigned char *opcode;
5207 int old_fr_fix;
f6af82bd 5208
ee7fcc42
AM		 5209 if (fragP->fr_var != NO_RELOC)
5210 reloc_type = fragP->fr_var;
b98ef147 5211 else if (size == 2)
f6af82bd
AM		 5212 reloc_type = BFD_RELOC_16_PCREL;
5213 else
5214 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5215
ee7fcc42
AM		 5216 old_fr_fix = fragP->fr_fix;
5217 opcode = (unsigned char *) fragP->fr_opcode;
5218
fddf5b5b 5219 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5220 {
fddf5b5b
AM		 5221 case UNCOND_JUMP:
5222 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5223 opcode[0] = 0xe9;
252b5132 5224 fragP->fr_fix += size;
062cd5e7
AS		 5225 fix_new (fragP, old_fr_fix, size,
5226 fragP->fr_symbol,
5227 fragP->fr_offset, 1,
5228 reloc_type);
252b5132
RH		 5229 break;
5230
fddf5b5b 5231 case COND_JUMP86:
412167cb
AM		 5232 if (size == 2
5233 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5234 {
5235 /* Negate the condition, and branch past an
5236 unconditional jump. */
5237 opcode[0] ^= 1;
5238 opcode[1] = 3;
5239 /* Insert an unconditional jump. */
5240 opcode[2] = 0xe9;
5241 /* We added two extra opcode bytes, and have a two byte
5242 offset. */
5243 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5244 fix_new (fragP, old_fr_fix + 2, 2,
5245 fragP->fr_symbol,
5246 fragP->fr_offset, 1,
5247 reloc_type);
fddf5b5b
AM		 5248 break;
5249 }
5250 /* Fall through. */
5251
5252 case COND_JUMP:
412167cb
AM		 5253 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5254 {
3e02c1cc
AM		 5255 fixS *fixP;
5256
412167cb 5257 fragP->fr_fix += 1;
3e02c1cc
AM		 5258 fixP = fix_new (fragP, old_fr_fix, 1,
5259 fragP->fr_symbol,
5260 fragP->fr_offset, 1,
5261 BFD_RELOC_8_PCREL);
5262 fixP->fx_signed = 1;
412167cb
AM		 5263 break;
5264 }
93c2a809 5265
24eab124 5266 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5267 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5268 opcode[1] = opcode[0] + 0x10;
f6af82bd 5269 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5270 /* We've added an opcode byte. */
5271 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5272 fix_new (fragP, old_fr_fix + 1, size,
5273 fragP->fr_symbol,
5274 fragP->fr_offset, 1,
5275 reloc_type);
252b5132 5276 break;
fddf5b5b
AM		 5277
5278 default:
5279 BAD_CASE (fragP->fr_subtype);
5280 break;
252b5132
RH		 5281 }
5282 frag_wane (fragP);
ee7fcc42 5283 return fragP->fr_fix - old_fr_fix;
252b5132 5284 }
93c2a809 5285
93c2a809
AM		 5286 /* Guess size depending on current relax state. Initially the relax
5287 state will correspond to a short jump and we return 1, because
5288 the variable part of the frag (the branch offset) is one byte
5289 long. However, we can relax a section more than once and in that
5290 case we must either set fr_subtype back to the unrelaxed state,
5291 or return the value for the appropriate branch. */
5292 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5293}
5294
47926f60
KH		 5295/* Called after relax() is finished.
5296
5297 In: Address of frag.
5298 fr_type == rs_machine_dependent.
5299 fr_subtype is what the address relaxed to.
5300
5301 Out: Any fixSs and constants are set up.
5302 Caller will turn frag into a ".space 0". */
5303
252b5132
RH		 5304void
5305md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5306 bfd *abfd ATTRIBUTE_UNUSED;
5307 segT sec ATTRIBUTE_UNUSED;
29b0f896 5308 fragS *fragP;
252b5132 5309{
29b0f896 5310 unsigned char *opcode;
252b5132 5311 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5312 offsetT target_address;
5313 offsetT opcode_address;
252b5132 5314 unsigned int extension = 0;
847f7ad4 5315 offsetT displacement_from_opcode_start;
252b5132
RH		 5316
5317 opcode = (unsigned char *) fragP->fr_opcode;
5318
47926f60 5319 /* Address we want to reach in file space. */
252b5132 5320 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5321
47926f60 5322 /* Address opcode resides at in file space. */
252b5132
RH		 5323 opcode_address = fragP->fr_address + fragP->fr_fix;
5324
47926f60 5325 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5326 displacement_from_opcode_start = target_address - opcode_address;
5327
fddf5b5b 5328 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5329 {
47926f60
KH		 5330 /* Don't have to change opcode. */
5331 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5332 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5333 }
5334 else
5335 {
5336 if (no_cond_jump_promotion
5337 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5338 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5339
fddf5b5b
AM		 5340 switch (fragP->fr_subtype)
5341 {
5342 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5343 extension = 4; /* 1 opcode + 4 displacement */
5344 opcode[0] = 0xe9;
5345 where_to_put_displacement = &opcode[1];
5346 break;
252b5132 5347
fddf5b5b
AM		 5348 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5349 extension = 2; /* 1 opcode + 2 displacement */
5350 opcode[0] = 0xe9;
5351 where_to_put_displacement = &opcode[1];
5352 break;
252b5132 5353
fddf5b5b
AM		 5354 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5355 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5356 extension = 5; /* 2 opcode + 4 displacement */
5357 opcode[1] = opcode[0] + 0x10;
5358 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5359 where_to_put_displacement = &opcode[2];
5360 break;
252b5132 5361
fddf5b5b
AM		 5362 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5363 extension = 3; /* 2 opcode + 2 displacement */
5364 opcode[1] = opcode[0] + 0x10;
5365 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5366 where_to_put_displacement = &opcode[2];
5367 break;
252b5132 5368
fddf5b5b
AM		 5369 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5370 extension = 4;
5371 opcode[0] ^= 1;
5372 opcode[1] = 3;
5373 opcode[2] = 0xe9;
5374 where_to_put_displacement = &opcode[3];
5375 break;
5376
5377 default:
5378 BAD_CASE (fragP->fr_subtype);
5379 break;
5380 }
252b5132 5381 }
fddf5b5b 5382
7b81dfbb
AJ		 5383 /* If size if less then four we are sure that the operand fits,
5384 but if it's 4, then it could be that the displacement is larger
5385 then -/+ 2GB. */
5386 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5387 && object_64bit
5388 && ((addressT) (displacement_from_opcode_start - extension
5389 + ((addressT) 1 << 31))
5390 > (((addressT) 2 << 31) - 1)))
5391 {
5392 as_bad_where (fragP->fr_file, fragP->fr_line,
5393 _("jump target out of range"));
5394 /* Make us emit 0. */
5395 displacement_from_opcode_start = extension;
5396 }
47926f60 5397 /* Now put displacement after opcode. */
252b5132
RH		 5398 md_number_to_chars ((char *) where_to_put_displacement,
5399 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5400 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5401 fragP->fr_fix += extension;
5402}
5403\f
47926f60
KH		 5404/* Size of byte displacement jmp. */
5405int md_short_jump_size = 2;
5406
5407/* Size of dword displacement jmp. */
5408int md_long_jump_size = 5;
252b5132 5409
252b5132
RH		 5410void
5411md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5412 char *ptr;
5413 addressT from_addr, to_addr;
ab9da554
ILT		 5414 fragS *frag ATTRIBUTE_UNUSED;
5415 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5416{
847f7ad4 5417 offsetT offset;
252b5132
RH		 5418
5419 offset = to_addr - (from_addr + 2);
47926f60
KH		 5420 /* Opcode for byte-disp jump. */
5421 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5422 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5423}
5424
5425void
5426md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5427 char *ptr;
5428 addressT from_addr, to_addr;
a38cf1db
AM		 5429 fragS *frag ATTRIBUTE_UNUSED;
5430 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5431{
847f7ad4 5432 offsetT offset;
252b5132 5433
a38cf1db
AM		 5434 offset = to_addr - (from_addr + 5);
5435 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5436 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5437}
5438\f
5439/* Apply a fixup (fixS) to segment data, once it has been determined
5440 by our caller that we have all the info we need to fix it up.
5441
5442 On the 386, immediates, displacements, and data pointers are all in
5443 the same (little-endian) format, so we don't need to care about which
5444 we are handling. */
5445
94f592af 5446void
55cf6793 5447md_apply_fix (fixP, valP, seg)
47926f60
KH		 5448 /* The fix we're to put in. */
5449 fixS *fixP;
47926f60 5450 /* Pointer to the value of the bits. */
c6682705 5451 valueT *valP;
47926f60
KH		 5452 /* Segment fix is from. */
5453 segT seg ATTRIBUTE_UNUSED;
252b5132 5454{
94f592af 5455 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5456 valueT value = *valP;
252b5132 5457
f86103b7 5458#if !defined (TE_Mach)
93382f6d
AM		 5459 if (fixP->fx_pcrel)
5460 {
5461 switch (fixP->fx_r_type)
5462 {
5865bb77
ILT		 5463 default:
5464 break;
5465
d6ab8113
JB		 5466 case BFD_RELOC_64:
5467 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5468 break;
93382f6d 5469 case BFD_RELOC_32:
ae8887b5 5470 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5471 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5472 break;
5473 case BFD_RELOC_16:
5474 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5475 break;
5476 case BFD_RELOC_8:
5477 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5478 break;
5479 }
5480 }
252b5132 5481
a161fe53 5482 if (fixP->fx_addsy != NULL
31312f95 5483 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5484 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5485 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5486 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5487 && !use_rela_relocations)
252b5132 5488 {
31312f95
AM		 5489 /* This is a hack. There should be a better way to handle this.
5490 This covers for the fact that bfd_install_relocation will
5491 subtract the current location (for partial_inplace, PC relative
5492 relocations); see more below. */
252b5132 5493#ifndef OBJ_AOUT
718ddfc0 5494 if (IS_ELF
252b5132
RH		 5495#ifdef TE_PE
5496 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5497#endif
5498 )
5499 value += fixP->fx_where + fixP->fx_frag->fr_address;
5500#endif
5501#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5502 if (IS_ELF)
252b5132 5503 {
6539b54b 5504 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5505
6539b54b 5506 if ((sym_seg == seg
2f66722d 5507 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5508 && sym_seg != absolute_section))
ae6063d4 5509 && !generic_force_reloc (fixP))
2f66722d
AM		 5510 {
5511 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5512 bfd_install_relocation subtracts them out again. I think
5513 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5514 it. FIXME. */
5515 value += fixP->fx_where + fixP->fx_frag->fr_address;
5516 }
252b5132
RH		 5517 }
5518#endif
5519#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5520 /* For some reason, the PE format does not store a
5521 section address offset for a PC relative symbol. */
5522 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5523 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5524 value += md_pcrel_from (fixP);
5525#endif
5526 }
5527
5528 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5529 and we must not disappoint it. */
252b5132 5530#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5531 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5532 switch (fixP->fx_r_type)
5533 {
5534 case BFD_RELOC_386_PLT32:
3e73aa7c 5535 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5536 /* Make the jump instruction point to the address of the operand. At
5537 runtime we merely add the offset to the actual PLT entry. */
5538 value = -4;
5539 break;
31312f95 5540
13ae64f3
JJ		 5541 case BFD_RELOC_386_TLS_GD:
5542 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5543 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5544 case BFD_RELOC_386_TLS_IE:
5545 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5546 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5547 case BFD_RELOC_X86_64_TLSGD:
5548 case BFD_RELOC_X86_64_TLSLD:
5549 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5550 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5551 value = 0; /* Fully resolved at runtime. No addend. */
5552 /* Fallthrough */
5553 case BFD_RELOC_386_TLS_LE:
5554 case BFD_RELOC_386_TLS_LDO_32:
5555 case BFD_RELOC_386_TLS_LE_32:
5556 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5557 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5558 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5559 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5560 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5561 break;
5562
67a4f2b7
AO		 5563 case BFD_RELOC_386_TLS_DESC_CALL:
5564 case BFD_RELOC_X86_64_TLSDESC_CALL:
5565 value = 0; /* Fully resolved at runtime. No addend. */
5566 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5567 fixP->fx_done = 0;
5568 return;
5569
00f7efb6
JJ		 5570 case BFD_RELOC_386_GOT32:
5571 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5572 value = 0; /* Fully resolved at runtime. No addend. */
5573 break;
47926f60
KH		 5574
5575 case BFD_RELOC_VTABLE_INHERIT:
5576 case BFD_RELOC_VTABLE_ENTRY:
5577 fixP->fx_done = 0;
94f592af 5578 return;
47926f60
KH		 5579
5580 default:
5581 break;
5582 }
5583#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5584 *valP = value;
f86103b7 5585#endif /* !defined (TE_Mach) */
3e73aa7c 5586
3e73aa7c 5587 /* Are we finished with this relocation now? */
c6682705 5588 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5589 fixP->fx_done = 1;
5590 else if (use_rela_relocations)
5591 {
5592 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5593 /* Remember value for tc_gen_reloc. */
5594 fixP->fx_addnumber = value;
3e73aa7c
JH		 5595 value = 0;
5596 }
f86103b7 5597
94f592af 5598 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5599}
252b5132 5600\f
252b5132
RH		 5601#define MAX_LITTLENUMS 6
5602
47926f60
KH		 5603/* Turn the string pointed to by litP into a floating point constant
5604 of type TYPE, and emit the appropriate bytes. The number of
5605 LITTLENUMS emitted is stored in *SIZEP. An error message is
5606 returned, or NULL on OK. */
5607
252b5132
RH		 5608char *
5609md_atof (type, litP, sizeP)
2ab9b79e 5610 int type;
252b5132
RH		 5611 char *litP;
5612 int *sizeP;
5613{
5614 int prec;
5615 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5616 LITTLENUM_TYPE *wordP;
5617 char *t;
5618
5619 switch (type)
5620 {
5621 case 'f':
5622 case 'F':
5623 prec = 2;
5624 break;
5625
5626 case 'd':
5627 case 'D':
5628 prec = 4;
5629 break;
5630
5631 case 'x':
5632 case 'X':
5633 prec = 5;
5634 break;
5635
5636 default:
5637 *sizeP = 0;
5638 return _("Bad call to md_atof ()");
5639 }
5640 t = atof_ieee (input_line_pointer, type, words);
5641 if (t)
5642 input_line_pointer = t;
5643
5644 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5645 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5646 the bigendian 386. */
5647 for (wordP = words + prec - 1; prec--;)
5648 {
5649 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5650 litP += sizeof (LITTLENUM_TYPE);
5651 }
5652 return 0;
5653}
5654\f
2d545b82 5655static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5656
252b5132 5657static char *
e3bb37b5 5658output_invalid (int c)
252b5132 5659{
3882b010 5660 if (ISPRINT (c))
f9f21a03
L		 5661 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5662 "'%c'", c);
252b5132 5663 else
f9f21a03 5664 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5665 "(0x%x)", (unsigned char) c);
252b5132
RH		 5666 return output_invalid_buf;
5667}
5668
af6bdddf 5669/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5670
5671static const reg_entry *
4d1bb795 5672parse_real_register (char *reg_string, char **end_op)
252b5132 5673{
af6bdddf
AM		 5674 char *s = reg_string;
5675 char *p;
252b5132
RH		 5676 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5677 const reg_entry *r;
5678
5679 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5680 if (*s == REGISTER_PREFIX)
5681 ++s;
5682
5683 if (is_space_char (*s))
5684 ++s;
5685
5686 p = reg_name_given;
af6bdddf 5687 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5688 {
5689 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5690 return (const reg_entry *) NULL;
5691 s++;
252b5132
RH		 5692 }
5693
6588847e
DN		 5694 /* For naked regs, make sure that we are not dealing with an identifier.
5695 This prevents confusing an identifier like `eax_var' with register
5696 `eax'. */
5697 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5698 return (const reg_entry *) NULL;
5699
af6bdddf 5700 *end_op = s;
252b5132
RH		 5701
5702 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5703
5f47d35b 5704 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5705 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5706 {
5f47d35b
AM		 5707 if (is_space_char (*s))
5708 ++s;
5709 if (*s == '(')
5710 {
af6bdddf 5711 ++s;
5f47d35b
AM		 5712 if (is_space_char (*s))
5713 ++s;
5714 if (*s >= '0' && *s <= '7')
5715 {
5716 r = &i386_float_regtab[*s - '0'];
af6bdddf 5717 ++s;
5f47d35b
AM		 5718 if (is_space_char (*s))
5719 ++s;
5720 if (*s == ')')
5721 {
5722 *end_op = s + 1;
5723 return r;
5724 }
5f47d35b 5725 }
47926f60 5726 /* We have "%st(" then garbage. */
5f47d35b
AM		 5727 return (const reg_entry *) NULL;
5728 }
5729 }
5730
1ae00879 5731 if (r != NULL
20f0a1fc 5732 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5733 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5734 && flag_code != CODE_64BIT)
20f0a1fc 5735 return (const reg_entry *) NULL;
1ae00879 5736
252b5132
RH		 5737 return r;
5738}
4d1bb795
JB		 5739
5740/* REG_STRING starts *before* REGISTER_PREFIX. */
5741
5742static const reg_entry *
5743parse_register (char *reg_string, char **end_op)
5744{
5745 const reg_entry *r;
5746
5747 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5748 r = parse_real_register (reg_string, end_op);
5749 else
5750 r = NULL;
5751 if (!r)
5752 {
5753 char *save = input_line_pointer;
5754 char c;
5755 symbolS *symbolP;
5756
5757 input_line_pointer = reg_string;
5758 c = get_symbol_end ();
5759 symbolP = symbol_find (reg_string);
5760 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5761 {
5762 const expressionS *e = symbol_get_value_expression (symbolP);
5763
5764 know (e->X_op == O_register);
5765 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5766 r = i386_regtab + e->X_add_number;
5767 *end_op = input_line_pointer;
5768 }
5769 *input_line_pointer = c;
5770 input_line_pointer = save;
5771 }
5772 return r;
5773}
5774
5775int
5776i386_parse_name (char *name, expressionS *e, char *nextcharP)
5777{
5778 const reg_entry *r;
5779 char *end = input_line_pointer;
5780
5781 *end = *nextcharP;
5782 r = parse_register (name, &input_line_pointer);
5783 if (r && end <= input_line_pointer)
5784 {
5785 *nextcharP = *input_line_pointer;
5786 *input_line_pointer = 0;
5787 e->X_op = O_register;
5788 e->X_add_number = r - i386_regtab;
5789 return 1;
5790 }
5791 input_line_pointer = end;
5792 *end = 0;
5793 return 0;
5794}
5795
5796void
5797md_operand (expressionS *e)
5798{
5799 if (*input_line_pointer == REGISTER_PREFIX)
5800 {
5801 char *end;
5802 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5803
5804 if (r)
5805 {
5806 e->X_op = O_register;
5807 e->X_add_number = r - i386_regtab;
5808 input_line_pointer = end;
5809 }
5810 }
5811}
5812
252b5132 5813\f
4cc782b5 5814#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5815const char *md_shortopts = "kVQ:sqn";
252b5132 5816#else
12b55ccc 5817const char *md_shortopts = "qn";
252b5132 5818#endif
6e0b89ee 5819
3e73aa7c 5820#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5821#define OPTION_64 (OPTION_MD_BASE + 1)
5822#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5823#define OPTION_MARCH (OPTION_MD_BASE + 3)
5824#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5825
99ad8390
NC		 5826struct option md_longopts[] =
5827{
3e73aa7c 5828 {"32", no_argument, NULL, OPTION_32},
99ad8390 5829#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5830 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5831#endif
b3b91714 5832 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5833 {"march", required_argument, NULL, OPTION_MARCH},
5834 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5835 {NULL, no_argument, NULL, 0}
5836};
5837size_t md_longopts_size = sizeof (md_longopts);
5838
5839int
9103f4f4 5840md_parse_option (int c, char *arg)
252b5132 5841{
9103f4f4
L		 5842 unsigned int i;
5843
252b5132
RH		 5844 switch (c)
5845 {
12b55ccc
L		 5846 case 'n':
5847 optimize_align_code = 0;
5848 break;
5849
a38cf1db
AM		 5850 case 'q':
5851 quiet_warnings = 1;
252b5132
RH		 5852 break;
5853
5854#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5855 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5856 should be emitted or not. FIXME: Not implemented. */
5857 case 'Q':
252b5132
RH		 5858 break;
5859
5860 /* -V: SVR4 argument to print version ID. */
5861 case 'V':
5862 print_version_id ();
5863 break;
5864
a38cf1db
AM		 5865 /* -k: Ignore for FreeBSD compatibility. */
5866 case 'k':
252b5132 5867 break;
4cc782b5
ILT		 5868
5869 case 's':
5870 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5871 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5872 break;
99ad8390
NC		 5873#endif
5874#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5875 case OPTION_64:
5876 {
5877 const char **list, **l;
5878
3e73aa7c
JH		 5879 list = bfd_target_list ();
5880 for (l = list; *l != NULL; l++)
8620418b 5881 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5882 || strcmp (*l, "coff-x86-64") == 0
5883 || strcmp (*l, "pe-x86-64") == 0
5884 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5885 {
5886 default_arch = "x86_64";
5887 break;
5888 }
3e73aa7c 5889 if (*l == NULL)
6e0b89ee 5890 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5891 free (list);
5892 }
5893 break;
5894#endif
252b5132 5895
6e0b89ee
AM		 5896 case OPTION_32:
5897 default_arch = "i386";
5898 break;
5899
b3b91714
AM		 5900 case OPTION_DIVIDE:
5901#ifdef SVR4_COMMENT_CHARS
5902 {
5903 char *n, *t;
5904 const char *s;
5905
5906 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5907 t = n;
5908 for (s = i386_comment_chars; *s != '\0'; s++)
5909 if (*s != '/')
5910 *t++ = *s;
5911 *t = '\0';
5912 i386_comment_chars = n;
5913 }
5914#endif
5915 break;
5916
9103f4f4
L		 5917 case OPTION_MARCH:
5918 if (*arg == '.')
5919 as_fatal (_("Invalid -march= option: `%s'"), arg);
5920 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5921 {
5922 if (strcmp (arg, cpu_arch [i].name) == 0)
5923 {
ccc9c027 5924 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5925 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5926 if (!cpu_arch_tune_set)
5927 {
5928 cpu_arch_tune = cpu_arch_isa;
5929 cpu_arch_tune_flags = cpu_arch_isa_flags;
5930 }
9103f4f4
L		 5931 break;
5932 }
5933 }
5934 if (i >= ARRAY_SIZE (cpu_arch))
5935 as_fatal (_("Invalid -march= option: `%s'"), arg);
5936 break;
5937
5938 case OPTION_MTUNE:
5939 if (*arg == '.')
5940 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5941 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5942 {
5943 if (strcmp (arg, cpu_arch [i].name) == 0)
5944 {
ccc9c027 5945 cpu_arch_tune_set = 1;
9103f4f4
L		 5946 cpu_arch_tune = cpu_arch [i].type;
5947 cpu_arch_tune_flags = cpu_arch[i].flags;
5948 break;
5949 }
5950 }
5951 if (i >= ARRAY_SIZE (cpu_arch))
5952 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5953 break;
5954
252b5132
RH		 5955 default:
5956 return 0;
5957 }
5958 return 1;
5959}
5960
5961void
5962md_show_usage (stream)
5963 FILE *stream;
5964{
4cc782b5
ILT		 5965#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5966 fprintf (stream, _("\
a38cf1db
AM		 5967 -Q ignored\n\
5968 -V print assembler version number\n\
b3b91714
AM		 5969 -k ignored\n"));
5970#endif
5971 fprintf (stream, _("\
12b55ccc 5972 -n Do not optimize code alignment\n\
b3b91714
AM		 5973 -q quieten some warnings\n"));
5974#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5975 fprintf (stream, _("\
a38cf1db 5976 -s ignored\n"));
b3b91714 5977#endif
751d281c
L		 5978#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5979 fprintf (stream, _("\
5980 --32/--64 generate 32bit/64bit code\n"));
5981#endif
b3b91714
AM		 5982#ifdef SVR4_COMMENT_CHARS
5983 fprintf (stream, _("\
5984 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5985#else
5986 fprintf (stream, _("\
b3b91714 5987 --divide ignored\n"));
4cc782b5 5988#endif
9103f4f4
L		 5989 fprintf (stream, _("\
5990 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5991 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 5992 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 5993
252b5132
RH		 5994}
5995
99ad8390
NC		 5996#if defined(TE_PEP)
5997const char *
5998x86_64_target_format (void)
5999{
6000 if (strcmp (default_arch, "x86_64") == 0)
6001 {
6002 set_code_flag (CODE_64BIT);
6003 return COFF_TARGET_FORMAT;
6004 }
6005 else if (strcmp (default_arch, "i386") == 0)
6006 {
6007 set_code_flag (CODE_32BIT);
6008 return "coff-i386";
6009 }
6010
6011 as_fatal (_("Unknown architecture"));
6012 return NULL;
6013}
6014#endif
6015
3e73aa7c
JH		 6016#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6017 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6018
6019/* Pick the target format to use. */
6020
47926f60 6021const char *
e3bb37b5 6022i386_target_format (void)
252b5132 6023{
3e73aa7c 6024 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6025 {
6026 set_code_flag (CODE_64BIT);
6027 if (cpu_arch_isa_flags == 0)
d32cad65 6028 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6029 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6030 |CpuSSE|CpuSSE2;
ccc9c027 6031 if (cpu_arch_tune_flags == 0)
d32cad65 6032 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6033 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6034 |CpuSSE|CpuSSE2;
9103f4f4 6035 }
3e73aa7c 6036 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6037 {
6038 set_code_flag (CODE_32BIT);
6039 if (cpu_arch_isa_flags == 0)
d32cad65 6040 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6041 if (cpu_arch_tune_flags == 0)
d32cad65 6042 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6043 }
3e73aa7c
JH		 6044 else
6045 as_fatal (_("Unknown architecture"));
252b5132
RH		 6046 switch (OUTPUT_FLAVOR)
6047 {
4c63da97
AM		 6048#ifdef OBJ_MAYBE_AOUT
6049 case bfd_target_aout_flavour:
47926f60 6050 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6051#endif
6052#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6053 case bfd_target_coff_flavour:
6054 return "coff-i386";
4c63da97 6055#endif
3e73aa7c 6056#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6057 case bfd_target_elf_flavour:
3e73aa7c 6058 {
e5cb08ac 6059 if (flag_code == CODE_64BIT)
4fa24527
JB		 6060 {
6061 object_64bit = 1;
6062 use_rela_relocations = 1;
6063 }
9d7cbccd 6064 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6065 }
4c63da97 6066#endif
252b5132
RH		 6067 default:
6068 abort ();
6069 return NULL;
6070 }
6071}
6072
47926f60 6073#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6074
6075#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6076void
6077i386_elf_emit_arch_note (void)
a847613f 6078{
718ddfc0 6079 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6080 {
6081 char *p;
6082 asection *seg = now_seg;
6083 subsegT subseg = now_subseg;
6084 Elf_Internal_Note i_note;
6085 Elf_External_Note e_note;
6086 asection *note_secp;
6087 int len;
6088
6089 /* Create the .note section. */
6090 note_secp = subseg_new (".note", 0);
6091 bfd_set_section_flags (stdoutput,
6092 note_secp,
6093 SEC_HAS_CONTENTS | SEC_READONLY);
6094
6095 /* Process the arch string. */
6096 len = strlen (cpu_arch_name);
6097
6098 i_note.namesz = len + 1;
6099 i_note.descsz = 0;
6100 i_note.type = NT_ARCH;
6101 p = frag_more (sizeof (e_note.namesz));
6102 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6103 p = frag_more (sizeof (e_note.descsz));
6104 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6105 p = frag_more (sizeof (e_note.type));
6106 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6107 p = frag_more (len + 1);
6108 strcpy (p, cpu_arch_name);
6109
6110 frag_align (2, 0, 0);
6111
6112 subseg_set (seg, subseg);
6113 }
6114}
6115#endif
252b5132 6116\f
252b5132
RH		 6117symbolS *
6118md_undefined_symbol (name)
6119 char *name;
6120{
18dc2407
ILT		 6121 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6122 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6123 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6124 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6125 {
6126 if (!GOT_symbol)
6127 {
6128 if (symbol_find (name))
6129 as_bad (_("GOT already in symbol table"));
6130 GOT_symbol = symbol_new (name, undefined_section,
6131 (valueT) 0, &zero_address_frag);
6132 };
6133 return GOT_symbol;
6134 }
252b5132
RH		 6135 return 0;
6136}
6137
6138/* Round up a section size to the appropriate boundary. */
47926f60 6139
252b5132
RH		 6140valueT
6141md_section_align (segment, size)
ab9da554 6142 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6143 valueT size;
6144{
4c63da97
AM		 6145#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6146 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6147 {
6148 /* For a.out, force the section size to be aligned. If we don't do
6149 this, BFD will align it for us, but it will not write out the
6150 final bytes of the section. This may be a bug in BFD, but it is
6151 easier to fix it here since that is how the other a.out targets
6152 work. */
6153 int align;
6154
6155 align = bfd_get_section_alignment (stdoutput, segment);
6156 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6157 }
252b5132
RH		 6158#endif
6159
6160 return size;
6161}
6162
6163/* On the i386, PC-relative offsets are relative to the start of the
6164 next instruction. That is, the address of the offset, plus its
6165 size, since the offset is always the last part of the insn. */
6166
6167long
e3bb37b5 6168md_pcrel_from (fixS *fixP)
252b5132
RH		 6169{
6170 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6171}
6172
6173#ifndef I386COFF
6174
6175static void
e3bb37b5 6176s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6177{
29b0f896 6178 int temp;
252b5132 6179
8a75718c
JB		 6180#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6181 if (IS_ELF)
6182 obj_elf_section_change_hook ();
6183#endif
252b5132
RH		 6184 temp = get_absolute_expression ();
6185 subseg_set (bss_section, (subsegT) temp);
6186 demand_empty_rest_of_line ();
6187}
6188
6189#endif
6190
252b5132 6191void
e3bb37b5 6192i386_validate_fix (fixS *fixp)
252b5132
RH		 6193{
6194 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6195 {
23df1078
JH		 6196 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6197 {
4fa24527 6198 if (!object_64bit)
23df1078
JH		 6199 abort ();
6200 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6201 }
6202 else
6203 {
4fa24527 6204 if (!object_64bit)
d6ab8113
JB		 6205 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6206 else
6207 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6208 }
252b5132
RH		 6209 fixp->fx_subsy = 0;
6210 }
6211}
6212
252b5132
RH		 6213arelent *
6214tc_gen_reloc (section, fixp)
ab9da554 6215 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6216 fixS *fixp;
6217{
6218 arelent *rel;
6219 bfd_reloc_code_real_type code;
6220
6221 switch (fixp->fx_r_type)
6222 {
3e73aa7c
JH		 6223 case BFD_RELOC_X86_64_PLT32:
6224 case BFD_RELOC_X86_64_GOT32:
6225 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6226 case BFD_RELOC_386_PLT32:
6227 case BFD_RELOC_386_GOT32:
6228 case BFD_RELOC_386_GOTOFF:
6229 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6230 case BFD_RELOC_386_TLS_GD:
6231 case BFD_RELOC_386_TLS_LDM:
6232 case BFD_RELOC_386_TLS_LDO_32:
6233 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6234 case BFD_RELOC_386_TLS_IE:
6235 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6236 case BFD_RELOC_386_TLS_LE_32:
6237 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6238 case BFD_RELOC_386_TLS_GOTDESC:
6239 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6240 case BFD_RELOC_X86_64_TLSGD:
6241 case BFD_RELOC_X86_64_TLSLD:
6242 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6243 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6244 case BFD_RELOC_X86_64_GOTTPOFF:
6245 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6246 case BFD_RELOC_X86_64_TPOFF64:
6247 case BFD_RELOC_X86_64_GOTOFF64:
6248 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6249 case BFD_RELOC_X86_64_GOT64:
6250 case BFD_RELOC_X86_64_GOTPCREL64:
6251 case BFD_RELOC_X86_64_GOTPC64:
6252 case BFD_RELOC_X86_64_GOTPLT64:
6253 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6254 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6255 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6256 case BFD_RELOC_RVA:
6257 case BFD_RELOC_VTABLE_ENTRY:
6258 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6259#ifdef TE_PE
6260 case BFD_RELOC_32_SECREL:
6261#endif
252b5132
RH		 6262 code = fixp->fx_r_type;
6263 break;
dbbaec26
L		 6264 case BFD_RELOC_X86_64_32S:
6265 if (!fixp->fx_pcrel)
6266 {
6267 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6268 code = fixp->fx_r_type;
6269 break;
6270 }
252b5132 6271 default:
93382f6d 6272 if (fixp->fx_pcrel)
252b5132 6273 {
93382f6d
AM		 6274 switch (fixp->fx_size)
6275 {
6276 default:
b091f402
AM		 6277 as_bad_where (fixp->fx_file, fixp->fx_line,
6278 _("can not do %d byte pc-relative relocation"),
6279 fixp->fx_size);
93382f6d
AM		 6280 code = BFD_RELOC_32_PCREL;
6281 break;
6282 case 1: code = BFD_RELOC_8_PCREL; break;
6283 case 2: code = BFD_RELOC_16_PCREL; break;
6284 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6285#ifdef BFD64
6286 case 8: code = BFD_RELOC_64_PCREL; break;
6287#endif
93382f6d
AM		 6288 }
6289 }
6290 else
6291 {
6292 switch (fixp->fx_size)
6293 {
6294 default:
b091f402
AM		 6295 as_bad_where (fixp->fx_file, fixp->fx_line,
6296 _("can not do %d byte relocation"),
6297 fixp->fx_size);
93382f6d
AM		 6298 code = BFD_RELOC_32;
6299 break;
6300 case 1: code = BFD_RELOC_8; break;
6301 case 2: code = BFD_RELOC_16; break;
6302 case 4: code = BFD_RELOC_32; break;
937149dd 6303#ifdef BFD64
3e73aa7c 6304 case 8: code = BFD_RELOC_64; break;
937149dd 6305#endif
93382f6d 6306 }
252b5132
RH		 6307 }
6308 break;
6309 }
252b5132 6310
d182319b
JB		 6311 if ((code == BFD_RELOC_32
6312 || code == BFD_RELOC_32_PCREL
6313 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6314 && GOT_symbol
6315 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6316 {
4fa24527 6317 if (!object_64bit)
d6ab8113
JB		 6318 code = BFD_RELOC_386_GOTPC;
6319 else
6320 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6321 }
7b81dfbb
AJ		 6322 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6323 && GOT_symbol
6324 && fixp->fx_addsy == GOT_symbol)
6325 {
6326 code = BFD_RELOC_X86_64_GOTPC64;
6327 }
252b5132
RH		 6328
6329 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6330 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6331 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6332
6333 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6334
3e73aa7c
JH		 6335 if (!use_rela_relocations)
6336 {
6337 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6338 vtable entry to be used in the relocation's section offset. */
6339 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6340 rel->address = fixp->fx_offset;
252b5132 6341
c6682705 6342 rel->addend = 0;
3e73aa7c
JH		 6343 }
6344 /* Use the rela in 64bit mode. */
252b5132 6345 else
3e73aa7c 6346 {
062cd5e7
AS		 6347 if (!fixp->fx_pcrel)
6348 rel->addend = fixp->fx_offset;
6349 else
6350 switch (code)
6351 {
6352 case BFD_RELOC_X86_64_PLT32:
6353 case BFD_RELOC_X86_64_GOT32:
6354 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6355 case BFD_RELOC_X86_64_TLSGD:
6356 case BFD_RELOC_X86_64_TLSLD:
6357 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6358 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6359 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6360 rel->addend = fixp->fx_offset - fixp->fx_size;
6361 break;
6362 default:
6363 rel->addend = (section->vma
6364 - fixp->fx_size
6365 + fixp->fx_addnumber
6366 + md_pcrel_from (fixp));
6367 break;
6368 }
3e73aa7c
JH		 6369 }
6370
252b5132
RH		 6371 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6372 if (rel->howto == NULL)
6373 {
6374 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6375 _("cannot represent relocation type %s"),
252b5132
RH		 6376 bfd_get_reloc_code_name (code));
6377 /* Set howto to a garbage value so that we can keep going. */
6378 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6379 assert (rel->howto != NULL);
6380 }
6381
6382 return rel;
6383}
6384
64a0c779
DN		 6385\f
6386/* Parse operands using Intel syntax. This implements a recursive descent
6387 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6388 Programmer's Guide.
6389
6390 FIXME: We do not recognize the full operand grammar defined in the MASM
6391 documentation. In particular, all the structure/union and
6392 high-level macro operands are missing.
6393
6394 Uppercase words are terminals, lower case words are non-terminals.
6395 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6396 bars '|' denote choices. Most grammar productions are implemented in
6397 functions called 'intel_<production>'.
6398
6399 Initial production is 'expr'.
6400
9306ca4a 6401 addOp + | -
64a0c779
DN		 6402
6403 alpha [a-zA-Z]
6404
9306ca4a
JB		 6405 binOp & | AND | \| | OR | ^ | XOR
6406
64a0c779
DN		 6407 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6408
6409 constant digits [[ radixOverride ]]
6410
9306ca4a 6411 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6412
6413 digits decdigit
b77a7acd
AJ		 6414 | digits decdigit
6415 | digits hexdigit
64a0c779
DN		 6416
6417 decdigit [0-9]
6418
9306ca4a
JB		 6419 e04 e04 addOp e05
6420 | e05
6421
6422 e05 e05 binOp e06
b77a7acd 6423 | e06
64a0c779
DN		 6424
6425 e06 e06 mulOp e09
b77a7acd 6426 | e09
64a0c779
DN		 6427
6428 e09 OFFSET e10
a724f0f4
JB		 6429 | SHORT e10
6430 | + e10
6431 | - e10
9306ca4a
JB		 6432 | ~ e10
6433 | NOT e10
64a0c779
DN		 6434 | e09 PTR e10
6435 | e09 : e10
6436 | e10
6437
6438 e10 e10 [ expr ]
b77a7acd 6439 | e11
64a0c779
DN		 6440
6441 e11 ( expr )
b77a7acd 6442 | [ expr ]
64a0c779
DN		 6443 | constant
6444 | dataType
6445 | id
6446 | $
6447 | register
6448
a724f0f4 6449 => expr expr cmpOp e04
9306ca4a 6450 | e04
64a0c779
DN		 6451
6452 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6453 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6454
6455 hexdigit a | b | c | d | e | f
b77a7acd 6456 | A | B | C | D | E | F
64a0c779
DN		 6457
6458 id alpha
b77a7acd 6459 | id alpha
64a0c779
DN		 6460 | id decdigit
6461
9306ca4a 6462 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6463
6464 quote " | '
6465
6466 register specialRegister
b77a7acd 6467 | gpRegister
64a0c779
DN		 6468 | byteRegister
6469
6470 segmentRegister CS | DS | ES | FS | GS | SS
6471
9306ca4a 6472 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6473 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6474 | TR3 | TR4 | TR5 | TR6 | TR7
6475
64a0c779
DN		 6476 We simplify the grammar in obvious places (e.g., register parsing is
6477 done by calling parse_register) and eliminate immediate left recursion
6478 to implement a recursive-descent parser.
6479
a724f0f4
JB		 6480 expr e04 expr'
6481
6482 expr' cmpOp e04 expr'
6483 | Empty
9306ca4a
JB		 6484
6485 e04 e05 e04'
6486
6487 e04' addOp e05 e04'
6488 | Empty
64a0c779
DN		 6489
6490 e05 e06 e05'
6491
9306ca4a 6492 e05' binOp e06 e05'
b77a7acd 6493 | Empty
64a0c779
DN		 6494
6495 e06 e09 e06'
6496
6497 e06' mulOp e09 e06'
b77a7acd 6498 | Empty
64a0c779
DN		 6499
6500 e09 OFFSET e10 e09'
a724f0f4
JB		 6501 | SHORT e10'
6502 | + e10'
6503 | - e10'
6504 | ~ e10'
6505 | NOT e10'
b77a7acd 6506 | e10 e09'
64a0c779
DN		 6507
6508 e09' PTR e10 e09'
b77a7acd 6509 | : e10 e09'
64a0c779
DN		 6510 | Empty
6511
6512 e10 e11 e10'
6513
6514 e10' [ expr ] e10'
b77a7acd 6515 | Empty
64a0c779
DN		 6516
6517 e11 ( expr )
b77a7acd 6518 | [ expr ]
64a0c779
DN		 6519 | BYTE
6520 | WORD
6521 | DWORD
9306ca4a 6522 | FWORD
64a0c779 6523 | QWORD
9306ca4a
JB		 6524 | TBYTE
6525 | OWORD
6526 | XMMWORD
64a0c779
DN		 6527 | .
6528 | $
6529 | register
6530 | id
6531 | constant */
6532
6533/* Parsing structure for the intel syntax parser. Used to implement the
6534 semantic actions for the operand grammar. */
6535struct intel_parser_s
6536 {
6537 char *op_string; /* The string being parsed. */
6538 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6539 int op_modifier; /* Operand modifier. */
64a0c779 6540 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6541 int in_offset; /* >=1 if parsing operand of offset. */
6542 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6543 const reg_entry *reg; /* Last register reference found. */
6544 char *disp; /* Displacement string being built. */
a724f0f4 6545 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6546 };
6547
6548static struct intel_parser_s intel_parser;
6549
6550/* Token structure for parsing intel syntax. */
6551struct intel_token
6552 {
6553 int code; /* Token code. */
6554 const reg_entry *reg; /* Register entry for register tokens. */
6555 char *str; /* String representation. */
6556 };
6557
6558static struct intel_token cur_token, prev_token;
6559
50705ef4
AM		 6560/* Token codes for the intel parser. Since T_SHORT is already used
6561 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6562#define T_NIL -1
6563#define T_CONST 1
6564#define T_REG 2
6565#define T_BYTE 3
6566#define T_WORD 4
9306ca4a
JB		 6567#define T_DWORD 5
6568#define T_FWORD 6
6569#define T_QWORD 7
6570#define T_TBYTE 8
6571#define T_XMMWORD 9
50705ef4 6572#undef T_SHORT
9306ca4a
JB		 6573#define T_SHORT 10
6574#define T_OFFSET 11
6575#define T_PTR 12
6576#define T_ID 13
6577#define T_SHL 14
6578#define T_SHR 15
64a0c779
DN		 6579
6580/* Prototypes for intel parser functions. */
e3bb37b5
L		 6581static int intel_match_token (int);
6582static void intel_putback_token (void);
6583static void intel_get_token (void);
6584static int intel_expr (void);
6585static int intel_e04 (void);
6586static int intel_e05 (void);
6587static int intel_e06 (void);
6588static int intel_e09 (void);
6589static int intel_e10 (void);
6590static int intel_e11 (void);
64a0c779 6591
64a0c779 6592static int
e3bb37b5 6593i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6594{
6595 int ret;
6596 char *p;
6597
a724f0f4
JB		 6598 p = intel_parser.op_string = xstrdup (operand_string);
6599 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6600
6601 for (;;)
64a0c779 6602 {
a724f0f4
JB		 6603 /* Initialize token holders. */
6604 cur_token.code = prev_token.code = T_NIL;
6605 cur_token.reg = prev_token.reg = NULL;
6606 cur_token.str = prev_token.str = NULL;
6607
6608 /* Initialize parser structure. */
6609 intel_parser.got_a_float = got_a_float;
6610 intel_parser.op_modifier = 0;
6611 intel_parser.is_mem = 0;
6612 intel_parser.in_offset = 0;
6613 intel_parser.in_bracket = 0;
6614 intel_parser.reg = NULL;
6615 intel_parser.disp[0] = '\0';
6616 intel_parser.next_operand = NULL;
6617
6618 /* Read the first token and start the parser. */
6619 intel_get_token ();
6620 ret = intel_expr ();
6621
6622 if (!ret)
6623 break;
6624
9306ca4a
JB		 6625 if (cur_token.code != T_NIL)
6626 {
6627 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6628 current_templates->start->name, cur_token.str);
6629 ret = 0;
6630 }
64a0c779
DN		 6631 /* If we found a memory reference, hand it over to i386_displacement
6632 to fill in the rest of the operand fields. */
9306ca4a 6633 else if (intel_parser.is_mem)
64a0c779
DN		 6634 {
6635 if ((i.mem_operands == 1
6636 && (current_templates->start->opcode_modifier & IsString) == 0)
6637 || i.mem_operands == 2)
6638 {
6639 as_bad (_("too many memory references for '%s'"),
6640 current_templates->start->name);
6641 ret = 0;
6642 }
6643 else
6644 {
6645 char *s = intel_parser.disp;
6646 i.mem_operands++;
6647
a724f0f4
JB		 6648 if (!quiet_warnings && intel_parser.is_mem < 0)
6649 /* See the comments in intel_bracket_expr. */
6650 as_warn (_("Treating `%s' as memory reference"), operand_string);
6651
64a0c779
DN		 6652 /* Add the displacement expression. */
6653 if (*s != '\0')
a4622f40
AM		 6654 ret = i386_displacement (s, s + strlen (s));
6655 if (ret)
a724f0f4
JB		 6656 {
6657 /* Swap base and index in 16-bit memory operands like
6658 [si+bx]. Since i386_index_check is also used in AT&T
6659 mode we have to do that here. */
6660 if (i.base_reg
6661 && i.index_reg
6662 && (i.base_reg->reg_type & Reg16)
6663 && (i.index_reg->reg_type & Reg16)
6664 && i.base_reg->reg_num >= 6
6665 && i.index_reg->reg_num < 6)
6666 {
6667 const reg_entry *base = i.index_reg;
6668
6669 i.index_reg = i.base_reg;
6670 i.base_reg = base;
6671 }
6672 ret = i386_index_check (operand_string);
6673 }
64a0c779
DN		 6674 }
6675 }
6676
6677 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6678 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6679 || intel_parser.reg == NULL)
6680 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6681
6682 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6683 ret = 0;
6684 if (!ret || !intel_parser.next_operand)
6685 break;
6686 intel_parser.op_string = intel_parser.next_operand;
6687 this_operand = i.operands++;
64a0c779
DN		 6688 }
6689
6690 free (p);
6691 free (intel_parser.disp);
6692
6693 return ret;
6694}
6695
a724f0f4
JB		 6696#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6697
6698/* expr e04 expr'
6699
6700 expr' cmpOp e04 expr'
6701 | Empty */
64a0c779 6702static int
e3bb37b5 6703intel_expr (void)
64a0c779 6704{
a724f0f4
JB		 6705 /* XXX Implement the comparison operators. */
6706 return intel_e04 ();
9306ca4a
JB		 6707}
6708
a724f0f4 6709/* e04 e05 e04'
9306ca4a 6710
a724f0f4 6711 e04' addOp e05 e04'
9306ca4a
JB		 6712 | Empty */
6713static int
e3bb37b5 6714intel_e04 (void)
9306ca4a 6715{
a724f0f4 6716 int nregs = -1;
9306ca4a 6717
a724f0f4 6718 for (;;)
9306ca4a 6719 {
a724f0f4
JB		 6720 if (!intel_e05())
6721 return 0;
9306ca4a 6722
a724f0f4
JB		 6723 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6724 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6725
a724f0f4
JB		 6726 if (cur_token.code == '+')
6727 nregs = -1;
6728 else if (cur_token.code == '-')
6729 nregs = NUM_ADDRESS_REGS;
6730 else
6731 return 1;
64a0c779 6732
a724f0f4
JB		 6733 strcat (intel_parser.disp, cur_token.str);
6734 intel_match_token (cur_token.code);
6735 }
64a0c779
DN		 6736}
6737
64a0c779
DN		 6738/* e05 e06 e05'
6739
9306ca4a 6740 e05' binOp e06 e05'
64a0c779
DN		 6741 | Empty */
6742static int
e3bb37b5 6743intel_e05 (void)
64a0c779 6744{
a724f0f4 6745 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6746
a724f0f4 6747 for (;;)
64a0c779 6748 {
a724f0f4
JB		 6749 if (!intel_e06())
6750 return 0;
6751
6752 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6753 {
6754 char str[2];
6755
6756 str[0] = cur_token.code;
6757 str[1] = 0;
6758 strcat (intel_parser.disp, str);
6759 }
6760 else
6761 break;
9306ca4a 6762
64a0c779
DN		 6763 intel_match_token (cur_token.code);
6764
a724f0f4
JB		 6765 if (nregs < 0)
6766 nregs = ~nregs;
64a0c779 6767 }
a724f0f4
JB		 6768 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6769 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6770 return 1;
4a1805b1 6771}
64a0c779
DN		 6772
6773/* e06 e09 e06'
6774
6775 e06' mulOp e09 e06'
b77a7acd 6776 | Empty */
64a0c779 6777static int
e3bb37b5 6778intel_e06 (void)
64a0c779 6779{
a724f0f4 6780 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6781
a724f0f4 6782 for (;;)
64a0c779 6783 {
a724f0f4
JB		 6784 if (!intel_e09())
6785 return 0;
9306ca4a 6786
a724f0f4
JB		 6787 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6788 {
6789 char str[2];
9306ca4a 6790
a724f0f4
JB		 6791 str[0] = cur_token.code;
6792 str[1] = 0;
6793 strcat (intel_parser.disp, str);
6794 }
6795 else if (cur_token.code == T_SHL)
6796 strcat (intel_parser.disp, "<<");
6797 else if (cur_token.code == T_SHR)
6798 strcat (intel_parser.disp, ">>");
6799 else
6800 break;
9306ca4a 6801
64e74474 6802 intel_match_token (cur_token.code);
64a0c779 6803
a724f0f4
JB		 6804 if (nregs < 0)
6805 nregs = ~nregs;
64a0c779 6806 }
a724f0f4
JB		 6807 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6808 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6809 return 1;
64a0c779
DN		 6810}
6811
a724f0f4
JB		 6812/* e09 OFFSET e09
6813 | SHORT e09
6814 | + e09
6815 | - e09
6816 | ~ e09
6817 | NOT e09
9306ca4a
JB		 6818 | e10 e09'
6819
64a0c779 6820 e09' PTR e10 e09'
b77a7acd 6821 | : e10 e09'
64a0c779
DN		 6822 | Empty */
6823static int
e3bb37b5 6824intel_e09 (void)
64a0c779 6825{
a724f0f4
JB		 6826 int nregs = ~NUM_ADDRESS_REGS;
6827 int in_offset = 0;
6828
6829 for (;;)
64a0c779 6830 {
a724f0f4
JB		 6831 /* Don't consume constants here. */
6832 if (cur_token.code == '+' || cur_token.code == '-')
6833 {
6834 /* Need to look one token ahead - if the next token
6835 is a constant, the current token is its sign. */
6836 int next_code;
6837
6838 intel_match_token (cur_token.code);
6839 next_code = cur_token.code;
6840 intel_putback_token ();
6841 if (next_code == T_CONST)
6842 break;
6843 }
6844
6845 /* e09 OFFSET e09 */
6846 if (cur_token.code == T_OFFSET)
6847 {
6848 if (!in_offset++)
6849 ++intel_parser.in_offset;
6850 }
6851
6852 /* e09 SHORT e09 */
6853 else if (cur_token.code == T_SHORT)
6854 intel_parser.op_modifier |= 1 << T_SHORT;
6855
6856 /* e09 + e09 */
6857 else if (cur_token.code == '+')
6858 strcat (intel_parser.disp, "+");
6859
6860 /* e09 - e09
6861 | ~ e09
6862 | NOT e09 */
6863 else if (cur_token.code == '-' || cur_token.code == '~')
6864 {
6865 char str[2];
64a0c779 6866
a724f0f4
JB		 6867 if (nregs < 0)
6868 nregs = ~nregs;
6869 str[0] = cur_token.code;
6870 str[1] = 0;
6871 strcat (intel_parser.disp, str);
6872 }
6873
6874 /* e09 e10 e09' */
6875 else
6876 break;
6877
6878 intel_match_token (cur_token.code);
64a0c779
DN		 6879 }
6880
a724f0f4 6881 for (;;)
9306ca4a 6882 {
a724f0f4
JB		 6883 if (!intel_e10 ())
6884 return 0;
9306ca4a 6885
a724f0f4
JB		 6886 /* e09' PTR e10 e09' */
6887 if (cur_token.code == T_PTR)
6888 {
6889 char suffix;
9306ca4a 6890
a724f0f4
JB		 6891 if (prev_token.code == T_BYTE)
6892 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6893
a724f0f4
JB		 6894 else if (prev_token.code == T_WORD)
6895 {
6896 if (current_templates->start->name[0] == 'l'
6897 && current_templates->start->name[2] == 's'
6898 && current_templates->start->name[3] == 0)
6899 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6900 else if (intel_parser.got_a_float == 2) /* "fi..." */
6901 suffix = SHORT_MNEM_SUFFIX;
6902 else
6903 suffix = WORD_MNEM_SUFFIX;
6904 }
64a0c779 6905
a724f0f4
JB		 6906 else if (prev_token.code == T_DWORD)
6907 {
6908 if (current_templates->start->name[0] == 'l'
6909 && current_templates->start->name[2] == 's'
6910 && current_templates->start->name[3] == 0)
6911 suffix = WORD_MNEM_SUFFIX;
6912 else if (flag_code == CODE_16BIT
6913 && (current_templates->start->opcode_modifier
435acd52 6914 & (Jump | JumpDword)))
a724f0f4
JB		 6915 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6916 else if (intel_parser.got_a_float == 1) /* "f..." */
6917 suffix = SHORT_MNEM_SUFFIX;
6918 else
6919 suffix = LONG_MNEM_SUFFIX;
6920 }
9306ca4a 6921
a724f0f4
JB		 6922 else if (prev_token.code == T_FWORD)
6923 {
6924 if (current_templates->start->name[0] == 'l'
6925 && current_templates->start->name[2] == 's'
6926 && current_templates->start->name[3] == 0)
6927 suffix = LONG_MNEM_SUFFIX;
6928 else if (!intel_parser.got_a_float)
6929 {
6930 if (flag_code == CODE_16BIT)
6931 add_prefix (DATA_PREFIX_OPCODE);
6932 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6933 }
6934 else
6935 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6936 }
64a0c779 6937
a724f0f4
JB		 6938 else if (prev_token.code == T_QWORD)
6939 {
6940 if (intel_parser.got_a_float == 1) /* "f..." */
6941 suffix = LONG_MNEM_SUFFIX;
6942 else
6943 suffix = QWORD_MNEM_SUFFIX;
6944 }
64a0c779 6945
a724f0f4
JB		 6946 else if (prev_token.code == T_TBYTE)
6947 {
6948 if (intel_parser.got_a_float == 1)
6949 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6950 else
6951 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6952 }
9306ca4a 6953
a724f0f4 6954 else if (prev_token.code == T_XMMWORD)
9306ca4a 6955 {
a724f0f4
JB		 6956 /* XXX ignored for now, but accepted since gcc uses it */
6957 suffix = 0;
9306ca4a 6958 }
64a0c779 6959
f16b83df 6960 else
a724f0f4
JB		 6961 {
6962 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6963 return 0;
6964 }
6965
435acd52
JB		 6966 /* Operands for jump/call using 'ptr' notation denote absolute
6967 addresses. */
6968 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6969 i.types[this_operand] |= JumpAbsolute;
6970
a724f0f4
JB		 6971 if (current_templates->start->base_opcode == 0x8d /* lea */)
6972 ;
6973 else if (!i.suffix)
6974 i.suffix = suffix;
6975 else if (i.suffix != suffix)
6976 {
6977 as_bad (_("Conflicting operand modifiers"));
6978 return 0;
6979 }
64a0c779 6980
9306ca4a
JB		 6981 }
6982
a724f0f4
JB		 6983 /* e09' : e10 e09' */
6984 else if (cur_token.code == ':')
9306ca4a 6985 {
a724f0f4
JB		 6986 if (prev_token.code != T_REG)
6987 {
6988 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6989 segment/group identifier (which we don't have), using comma
6990 as the operand separator there is even less consistent, since
6991 there all branches only have a single operand. */
6992 if (this_operand != 0
6993 || intel_parser.in_offset
6994 || intel_parser.in_bracket
6995 || (!(current_templates->start->opcode_modifier
6996 & (Jump|JumpDword|JumpInterSegment))
6997 && !(current_templates->start->operand_types[0]
6998 & JumpAbsolute)))
6999 return intel_match_token (T_NIL);
7000 /* Remember the start of the 2nd operand and terminate 1st
7001 operand here.
7002 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7003 another expression), but it gets at least the simplest case
7004 (a plain number or symbol on the left side) right. */
7005 intel_parser.next_operand = intel_parser.op_string;
7006 *--intel_parser.op_string = '\0';
7007 return intel_match_token (':');
7008 }
9306ca4a 7009 }
64a0c779 7010
a724f0f4 7011 /* e09' Empty */
64a0c779 7012 else
a724f0f4 7013 break;
64a0c779 7014
a724f0f4
JB		 7015 intel_match_token (cur_token.code);
7016
7017 }
7018
7019 if (in_offset)
7020 {
7021 --intel_parser.in_offset;
7022 if (nregs < 0)
7023 nregs = ~nregs;
7024 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7025 {
a724f0f4 7026 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7027 return 0;
7028 }
a724f0f4
JB		 7029 intel_parser.op_modifier |= 1 << T_OFFSET;
7030 }
9306ca4a 7031
a724f0f4
JB		 7032 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7033 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7034 return 1;
7035}
64a0c779 7036
a724f0f4 7037static int
e3bb37b5 7038intel_bracket_expr (void)
a724f0f4
JB		 7039{
7040 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7041 const char *start = intel_parser.op_string;
7042 int len;
7043
7044 if (i.op[this_operand].regs)
7045 return intel_match_token (T_NIL);
7046
7047 intel_match_token ('[');
7048
7049 /* Mark as a memory operand only if it's not already known to be an
7050 offset expression. If it's an offset expression, we need to keep
7051 the brace in. */
7052 if (!intel_parser.in_offset)
7053 {
7054 ++intel_parser.in_bracket;
435acd52
JB		 7055
7056 /* Operands for jump/call inside brackets denote absolute addresses. */
7057 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7058 i.types[this_operand] |= JumpAbsolute;
7059
a724f0f4
JB		 7060 /* Unfortunately gas always diverged from MASM in a respect that can't
7061 be easily fixed without risking to break code sequences likely to be
7062 encountered (the testsuite even check for this): MASM doesn't consider
7063 an expression inside brackets unconditionally as a memory reference.
7064 When that is e.g. a constant, an offset expression, or the sum of the
7065 two, this is still taken as a constant load. gas, however, always
7066 treated these as memory references. As a compromise, we'll try to make
7067 offset expressions inside brackets work the MASM way (since that's
7068 less likely to be found in real world code), but make constants alone
7069 continue to work the traditional gas way. In either case, issue a
7070 warning. */
7071 intel_parser.op_modifier &= ~was_offset;
64a0c779 7072 }
a724f0f4 7073 else
64e74474 7074 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7075
7076 /* Add a '+' to the displacement string if necessary. */
7077 if (*intel_parser.disp != '\0'
7078 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7079 strcat (intel_parser.disp, "+");
64a0c779 7080
a724f0f4
JB		 7081 if (intel_expr ()
7082 && (len = intel_parser.op_string - start - 1,
7083 intel_match_token (']')))
64a0c779 7084 {
a724f0f4
JB		 7085 /* Preserve brackets when the operand is an offset expression. */
7086 if (intel_parser.in_offset)
7087 strcat (intel_parser.disp, "]");
7088 else
7089 {
7090 --intel_parser.in_bracket;
7091 if (i.base_reg || i.index_reg)
7092 intel_parser.is_mem = 1;
7093 if (!intel_parser.is_mem)
7094 {
7095 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7096 /* Defer the warning until all of the operand was parsed. */
7097 intel_parser.is_mem = -1;
7098 else if (!quiet_warnings)
7099 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7100 }
7101 }
7102 intel_parser.op_modifier |= was_offset;
64a0c779 7103
a724f0f4 7104 return 1;
64a0c779 7105 }
a724f0f4 7106 return 0;
64a0c779
DN		 7107}
7108
7109/* e10 e11 e10'
7110
7111 e10' [ expr ] e10'
b77a7acd 7112 | Empty */
64a0c779 7113static int
e3bb37b5 7114intel_e10 (void)
64a0c779 7115{
a724f0f4
JB		 7116 if (!intel_e11 ())
7117 return 0;
64a0c779 7118
a724f0f4 7119 while (cur_token.code == '[')
64a0c779 7120 {
a724f0f4 7121 if (!intel_bracket_expr ())
21d6c4af 7122 return 0;
64a0c779
DN		 7123 }
7124
a724f0f4 7125 return 1;
64a0c779
DN		 7126}
7127
64a0c779 7128/* e11 ( expr )
b77a7acd 7129 | [ expr ]
64a0c779
DN		 7130 | BYTE
7131 | WORD
7132 | DWORD
9306ca4a 7133 | FWORD
64a0c779 7134 | QWORD
9306ca4a
JB		 7135 | TBYTE
7136 | OWORD
7137 | XMMWORD
4a1805b1 7138 | $
64a0c779
DN		 7139 | .
7140 | register
7141 | id
7142 | constant */
7143static int
e3bb37b5 7144intel_e11 (void)
64a0c779 7145{
a724f0f4 7146 switch (cur_token.code)
64a0c779 7147 {
a724f0f4
JB		 7148 /* e11 ( expr ) */
7149 case '(':
64a0c779
DN		 7150 intel_match_token ('(');
7151 strcat (intel_parser.disp, "(");
7152
7153 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7154 {
7155 strcat (intel_parser.disp, ")");
7156 return 1;
7157 }
a724f0f4 7158 return 0;
4a1805b1 7159
a724f0f4
JB		 7160 /* e11 [ expr ] */
7161 case '[':
a724f0f4 7162 return intel_bracket_expr ();
64a0c779 7163
a724f0f4
JB		 7164 /* e11 $
7165 | . */
7166 case '.':
64a0c779
DN		 7167 strcat (intel_parser.disp, cur_token.str);
7168 intel_match_token (cur_token.code);
21d6c4af
DN		 7169
7170 /* Mark as a memory operand only if it's not already known to be an
7171 offset expression. */
a724f0f4 7172 if (!intel_parser.in_offset)
21d6c4af 7173 intel_parser.is_mem = 1;
64a0c779
DN		 7174
7175 return 1;
64a0c779 7176
a724f0f4
JB		 7177 /* e11 register */
7178 case T_REG:
7179 {
7180 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7181
a724f0f4 7182 intel_match_token (T_REG);
64a0c779 7183
a724f0f4
JB		 7184 /* Check for segment change. */
7185 if (cur_token.code == ':')
7186 {
7187 if (!(reg->reg_type & (SReg2 | SReg3)))
7188 {
7189 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7190 return 0;
7191 }
7192 else if (i.seg[i.mem_operands])
7193 as_warn (_("Extra segment override ignored"));
7194 else
7195 {
7196 if (!intel_parser.in_offset)
7197 intel_parser.is_mem = 1;
7198 switch (reg->reg_num)
7199 {
7200 case 0:
7201 i.seg[i.mem_operands] = &es;
7202 break;
7203 case 1:
7204 i.seg[i.mem_operands] = &cs;
7205 break;
7206 case 2:
7207 i.seg[i.mem_operands] = &ss;
7208 break;
7209 case 3:
7210 i.seg[i.mem_operands] = &ds;
7211 break;
7212 case 4:
7213 i.seg[i.mem_operands] = &fs;
7214 break;
7215 case 5:
7216 i.seg[i.mem_operands] = &gs;
7217 break;
7218 }
7219 }
7220 }
64a0c779 7221
a724f0f4
JB		 7222 /* Not a segment register. Check for register scaling. */
7223 else if (cur_token.code == '*')
7224 {
7225 if (!intel_parser.in_bracket)
7226 {
7227 as_bad (_("Register scaling only allowed in memory operands"));
7228 return 0;
7229 }
64a0c779 7230
a724f0f4
JB		 7231 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7232 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7233 else if (i.index_reg)
7234 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7235
a724f0f4
JB		 7236 /* What follows must be a valid scale. */
7237 intel_match_token ('*');
7238 i.index_reg = reg;
7239 i.types[this_operand] |= BaseIndex;
64a0c779 7240
a724f0f4
JB		 7241 /* Set the scale after setting the register (otherwise,
7242 i386_scale will complain) */
7243 if (cur_token.code == '+' || cur_token.code == '-')
7244 {
7245 char *str, sign = cur_token.code;
7246 intel_match_token (cur_token.code);
7247 if (cur_token.code != T_CONST)
7248 {
7249 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7250 cur_token.str);
7251 return 0;
7252 }
7253 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7254 strcpy (str + 1, cur_token.str);
7255 *str = sign;
7256 if (!i386_scale (str))
7257 return 0;
7258 free (str);
7259 }
7260 else if (!i386_scale (cur_token.str))
64a0c779 7261 return 0;
a724f0f4
JB		 7262 intel_match_token (cur_token.code);
7263 }
64a0c779 7264
a724f0f4
JB		 7265 /* No scaling. If this is a memory operand, the register is either a
7266 base register (first occurrence) or an index register (second
7267 occurrence). */
7b0441f6 7268 else if (intel_parser.in_bracket)
a724f0f4 7269 {
64a0c779 7270
a724f0f4
JB		 7271 if (!i.base_reg)
7272 i.base_reg = reg;
7273 else if (!i.index_reg)
7274 i.index_reg = reg;
7275 else
7276 {
7277 as_bad (_("Too many register references in memory operand"));
7278 return 0;
7279 }
64a0c779 7280
a724f0f4
JB		 7281 i.types[this_operand] |= BaseIndex;
7282 }
4a1805b1 7283
4d1bb795
JB		 7284 /* It's neither base nor index. */
7285 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7286 {
7287 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7288 i.op[this_operand].regs = reg;
7289 i.reg_operands++;
7290 }
7291 else
7292 {
7293 as_bad (_("Invalid use of register"));
7294 return 0;
7295 }
64a0c779 7296
a724f0f4
JB		 7297 /* Since registers are not part of the displacement string (except
7298 when we're parsing offset operands), we may need to remove any
7299 preceding '+' from the displacement string. */
7300 if (*intel_parser.disp != '\0'
7301 && !intel_parser.in_offset)
7302 {
7303 char *s = intel_parser.disp;
7304 s += strlen (s) - 1;
7305 if (*s == '+')
7306 *s = '\0';
7307 }
4a1805b1 7308
a724f0f4
JB		 7309 return 1;
7310 }
7311
7312 /* e11 BYTE
7313 | WORD
7314 | DWORD
7315 | FWORD
7316 | QWORD
7317 | TBYTE
7318 | OWORD
7319 | XMMWORD */
7320 case T_BYTE:
7321 case T_WORD:
7322 case T_DWORD:
7323 case T_FWORD:
7324 case T_QWORD:
7325 case T_TBYTE:
7326 case T_XMMWORD:
7327 intel_match_token (cur_token.code);
64a0c779 7328
a724f0f4
JB		 7329 if (cur_token.code == T_PTR)
7330 return 1;
7331
7332 /* It must have been an identifier. */
7333 intel_putback_token ();
7334 cur_token.code = T_ID;
7335 /* FALLTHRU */
7336
7337 /* e11 id
7338 | constant */
7339 case T_ID:
7340 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7341 {
7342 symbolS *symbolP;
7343
a724f0f4
JB		 7344 /* The identifier represents a memory reference only if it's not
7345 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7346 symbolP = symbol_find(cur_token.str);
7347 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7348 intel_parser.is_mem = 1;
7349 }
a724f0f4 7350 /* FALLTHRU */
64a0c779 7351
a724f0f4
JB		 7352 case T_CONST:
7353 case '-':
7354 case '+':
7355 {
7356 char *save_str, sign = 0;
64a0c779 7357
a724f0f4
JB		 7358 /* Allow constants that start with `+' or `-'. */
7359 if (cur_token.code == '-' || cur_token.code == '+')
7360 {
7361 sign = cur_token.code;
7362 intel_match_token (cur_token.code);
7363 if (cur_token.code != T_CONST)
7364 {
7365 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7366 cur_token.str);
7367 return 0;
7368 }
7369 }
64a0c779 7370
a724f0f4
JB		 7371 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7372 strcpy (save_str + !!sign, cur_token.str);
7373 if (sign)
7374 *save_str = sign;
64a0c779 7375
a724f0f4
JB		 7376 /* Get the next token to check for register scaling. */
7377 intel_match_token (cur_token.code);
64a0c779 7378
a724f0f4
JB		 7379 /* Check if this constant is a scaling factor for an index register. */
7380 if (cur_token.code == '*')
7381 {
7382 if (intel_match_token ('*') && cur_token.code == T_REG)
7383 {
7384 const reg_entry *reg = cur_token.reg;
7385
7386 if (!intel_parser.in_bracket)
7387 {
7388 as_bad (_("Register scaling only allowed in memory operands"));
7389 return 0;
7390 }
7391
7392 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7393 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7394 else if (i.index_reg)
7395 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7396
7397 /* The constant is followed by `* reg', so it must be
7398 a valid scale. */
7399 i.index_reg = reg;
7400 i.types[this_operand] |= BaseIndex;
7401
7402 /* Set the scale after setting the register (otherwise,
7403 i386_scale will complain) */
7404 if (!i386_scale (save_str))
64a0c779 7405 return 0;
a724f0f4
JB		 7406 intel_match_token (T_REG);
7407
7408 /* Since registers are not part of the displacement
7409 string, we may need to remove any preceding '+' from
7410 the displacement string. */
7411 if (*intel_parser.disp != '\0')
7412 {
7413 char *s = intel_parser.disp;
7414 s += strlen (s) - 1;
7415 if (*s == '+')
7416 *s = '\0';
7417 }
7418
7419 free (save_str);
7420
7421 return 1;
7422 }
64a0c779 7423
a724f0f4
JB		 7424 /* The constant was not used for register scaling. Since we have
7425 already consumed the token following `*' we now need to put it
7426 back in the stream. */
64a0c779 7427 intel_putback_token ();
a724f0f4 7428 }
64a0c779 7429
a724f0f4
JB		 7430 /* Add the constant to the displacement string. */
7431 strcat (intel_parser.disp, save_str);
7432 free (save_str);
64a0c779 7433
a724f0f4
JB		 7434 return 1;
7435 }
64a0c779
DN		 7436 }
7437
64a0c779
DN		 7438 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7439 return 0;
7440}
7441
64a0c779
DN		 7442/* Match the given token against cur_token. If they match, read the next
7443 token from the operand string. */
7444static int
e3bb37b5 7445intel_match_token (int code)
64a0c779
DN		 7446{
7447 if (cur_token.code == code)
7448 {
7449 intel_get_token ();
7450 return 1;
7451 }
7452 else
7453 {
0477af35 7454 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7455 return 0;
7456 }
7457}
7458
64a0c779
DN		 7459/* Read a new token from intel_parser.op_string and store it in cur_token. */
7460static void
e3bb37b5 7461intel_get_token (void)
64a0c779
DN		 7462{
7463 char *end_op;
7464 const reg_entry *reg;
7465 struct intel_token new_token;
7466
7467 new_token.code = T_NIL;
7468 new_token.reg = NULL;
7469 new_token.str = NULL;
7470
4a1805b1 7471 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7472 cur_token to prev_token. */
7473 if (prev_token.str)
7474 free (prev_token.str);
7475
7476 prev_token = cur_token;
7477
7478 /* Skip whitespace. */
7479 while (is_space_char (*intel_parser.op_string))
7480 intel_parser.op_string++;
7481
7482 /* Return an empty token if we find nothing else on the line. */
7483 if (*intel_parser.op_string == '\0')
7484 {
7485 cur_token = new_token;
7486 return;
7487 }
7488
7489 /* The new token cannot be larger than the remainder of the operand
7490 string. */
a724f0f4 7491 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7492 new_token.str[0] = '\0';
7493
7494 if (strchr ("0123456789", *intel_parser.op_string))
7495 {
7496 char *p = new_token.str;
7497 char *q = intel_parser.op_string;
7498 new_token.code = T_CONST;
7499
7500 /* Allow any kind of identifier char to encompass floating point and
7501 hexadecimal numbers. */
7502 while (is_identifier_char (*q))
7503 *p++ = *q++;
7504 *p = '\0';
7505
7506 /* Recognize special symbol names [0-9][bf]. */
7507 if (strlen (intel_parser.op_string) == 2
4a1805b1 7508 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7509 || intel_parser.op_string[1] == 'f'))
7510 new_token.code = T_ID;
7511 }
7512
4d1bb795 7513 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7514 {
4d1bb795
JB		 7515 size_t len = end_op - intel_parser.op_string;
7516
64a0c779
DN		 7517 new_token.code = T_REG;
7518 new_token.reg = reg;
7519
4d1bb795
JB		 7520 memcpy (new_token.str, intel_parser.op_string, len);
7521 new_token.str[len] = '\0';
64a0c779
DN		 7522 }
7523
7524 else if (is_identifier_char (*intel_parser.op_string))
7525 {
7526 char *p = new_token.str;
7527 char *q = intel_parser.op_string;
7528
7529 /* A '.' or '$' followed by an identifier char is an identifier.
7530 Otherwise, it's operator '.' followed by an expression. */
7531 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7532 {
9306ca4a
JB		 7533 new_token.code = '.';
7534 new_token.str[0] = '.';
64a0c779
DN		 7535 new_token.str[1] = '\0';
7536 }
7537 else
7538 {
7539 while (is_identifier_char (*q) || *q == '@')
7540 *p++ = *q++;
7541 *p = '\0';
7542
9306ca4a
JB		 7543 if (strcasecmp (new_token.str, "NOT") == 0)
7544 new_token.code = '~';
7545
7546 else if (strcasecmp (new_token.str, "MOD") == 0)
7547 new_token.code = '%';
7548
7549 else if (strcasecmp (new_token.str, "AND") == 0)
7550 new_token.code = '&';
7551
7552 else if (strcasecmp (new_token.str, "OR") == 0)
7553 new_token.code = '|';
7554
7555 else if (strcasecmp (new_token.str, "XOR") == 0)
7556 new_token.code = '^';
7557
7558 else if (strcasecmp (new_token.str, "SHL") == 0)
7559 new_token.code = T_SHL;
7560
7561 else if (strcasecmp (new_token.str, "SHR") == 0)
7562 new_token.code = T_SHR;
7563
7564 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7565 new_token.code = T_BYTE;
7566
7567 else if (strcasecmp (new_token.str, "WORD") == 0)
7568 new_token.code = T_WORD;
7569
7570 else if (strcasecmp (new_token.str, "DWORD") == 0)
7571 new_token.code = T_DWORD;
7572
9306ca4a
JB		 7573 else if (strcasecmp (new_token.str, "FWORD") == 0)
7574 new_token.code = T_FWORD;
7575
64a0c779
DN		 7576 else if (strcasecmp (new_token.str, "QWORD") == 0)
7577 new_token.code = T_QWORD;
7578
9306ca4a
JB		 7579 else if (strcasecmp (new_token.str, "TBYTE") == 0
7580 /* XXX remove (gcc still uses it) */
7581 || strcasecmp (new_token.str, "XWORD") == 0)
7582 new_token.code = T_TBYTE;
7583
7584 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7585 || strcasecmp (new_token.str, "OWORD") == 0)
7586 new_token.code = T_XMMWORD;
64a0c779
DN		 7587
7588 else if (strcasecmp (new_token.str, "PTR") == 0)
7589 new_token.code = T_PTR;
7590
7591 else if (strcasecmp (new_token.str, "SHORT") == 0)
7592 new_token.code = T_SHORT;
7593
7594 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7595 {
7596 new_token.code = T_OFFSET;
7597
7598 /* ??? This is not mentioned in the MASM grammar but gcc
7599 makes use of it with -mintel-syntax. OFFSET may be
7600 followed by FLAT: */
7601 if (strncasecmp (q, " FLAT:", 6) == 0)
7602 strcat (new_token.str, " FLAT:");
7603 }
7604
7605 /* ??? This is not mentioned in the MASM grammar. */
7606 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7607 {
7608 new_token.code = T_OFFSET;
7609 if (*q == ':')
7610 strcat (new_token.str, ":");
7611 else
7612 as_bad (_("`:' expected"));
7613 }
64a0c779
DN		 7614
7615 else
7616 new_token.code = T_ID;
7617 }
7618 }
7619
9306ca4a
JB		 7620 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7621 {
7622 new_token.code = *intel_parser.op_string;
7623 new_token.str[0] = *intel_parser.op_string;
7624 new_token.str[1] = '\0';
7625 }
7626
7627 else if (strchr ("<>", *intel_parser.op_string)
7628 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7629 {
7630 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7631 new_token.str[0] = *intel_parser.op_string;
7632 new_token.str[1] = *intel_parser.op_string;
7633 new_token.str[2] = '\0';
7634 }
7635
64a0c779 7636 else
0477af35 7637 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7638
7639 intel_parser.op_string += strlen (new_token.str);
7640 cur_token = new_token;
7641}
7642
64a0c779
DN		 7643/* Put cur_token back into the token stream and make cur_token point to
7644 prev_token. */
7645static void
e3bb37b5 7646intel_putback_token (void)
64a0c779 7647{
a724f0f4
JB		 7648 if (cur_token.code != T_NIL)
7649 {
7650 intel_parser.op_string -= strlen (cur_token.str);
7651 free (cur_token.str);
7652 }
64a0c779 7653 cur_token = prev_token;
4a1805b1 7654
64a0c779
DN		 7655 /* Forget prev_token. */
7656 prev_token.code = T_NIL;
7657 prev_token.reg = NULL;
7658 prev_token.str = NULL;
7659}
54cfded0 7660
a4447b93 7661int
1df69f4f 7662tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7663{
7664 unsigned int regnum;
7665 unsigned int regnames_count;
089dfecd 7666 static const char *const regnames_32[] =
54cfded0 7667 {
a4447b93
RH		 7668 "eax", "ecx", "edx", "ebx",
7669 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7670 "eip", "eflags", NULL,
7671 "st0", "st1", "st2", "st3",
7672 "st4", "st5", "st6", "st7",
7673 NULL, NULL,
7674 "xmm0", "xmm1", "xmm2", "xmm3",
7675 "xmm4", "xmm5", "xmm6", "xmm7",
7676 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7677 "mm4", "mm5", "mm6", "mm7",
7678 "fcw", "fsw", "mxcsr",
7679 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7680 "tr", "ldtr"
54cfded0 7681 };
089dfecd 7682 static const char *const regnames_64[] =
54cfded0 7683 {
089dfecd
JB		 7684 "rax", "rdx", "rcx", "rbx",
7685 "rsi", "rdi", "rbp", "rsp",
7686 "r8", "r9", "r10", "r11",
54cfded0 7687 "r12", "r13", "r14", "r15",
089dfecd
JB		 7688 "rip",
7689 "xmm0", "xmm1", "xmm2", "xmm3",
7690 "xmm4", "xmm5", "xmm6", "xmm7",
7691 "xmm8", "xmm9", "xmm10", "xmm11",
7692 "xmm12", "xmm13", "xmm14", "xmm15",
7693 "st0", "st1", "st2", "st3",
7694 "st4", "st5", "st6", "st7",
7695 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7696 "mm4", "mm5", "mm6", "mm7",
7697 "rflags",
7698 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7699 "fs.base", "gs.base", NULL, NULL,
7700 "tr", "ldtr",
7701 "mxcsr", "fcw", "fsw"
54cfded0 7702 };
089dfecd 7703 const char *const *regnames;
54cfded0
AM		 7704
7705 if (flag_code == CODE_64BIT)
7706 {
7707 regnames = regnames_64;
0cea6190 7708 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7709 }
7710 else
7711 {
7712 regnames = regnames_32;
0cea6190 7713 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7714 }
7715
7716 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7717 if (regnames[regnum] != NULL
7718 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7719 return regnum;
7720
54cfded0
AM		 7721 return -1;
7722}
7723
7724void
7725tc_x86_frame_initial_instructions (void)
7726{
a4447b93
RH		 7727 static unsigned int sp_regno;
7728
7729 if (!sp_regno)
7730 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7731 ? "rsp" : "esp");
7732
7733 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7734 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7735}
d2b2c203
DJ		 7736
7737int
7738i386_elf_section_type (const char *str, size_t len)
7739{
7740 if (flag_code == CODE_64BIT
7741 && len == sizeof ("unwind") - 1
7742 && strncmp (str, "unwind", 6) == 0)
7743 return SHT_X86_64_UNWIND;
7744
7745 return -1;
7746}
bb41ade5
AM		 7747
7748#ifdef TE_PE
7749void
7750tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7751{
7752 expressionS expr;
7753
7754 expr.X_op = O_secrel;
7755 expr.X_add_symbol = symbol;
7756 expr.X_add_number = 0;
7757 emit_expr (&expr, size);
7758}
7759#endif
3b22753a
L		 7760
7761#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7762/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7763
7764int
7765x86_64_section_letter (int letter, char **ptr_msg)
7766{
7767 if (flag_code == CODE_64BIT)
7768 {
7769 if (letter == 'l')
7770 return SHF_X86_64_LARGE;
7771
7772 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7773 }
3b22753a 7774 else
64e74474 7775 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7776 return -1;
7777}
7778
7779int
7780x86_64_section_word (char *str, size_t len)
7781{
8620418b 7782 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7783 return SHF_X86_64_LARGE;
7784
7785 return -1;
7786}
7787
7788static void
7789handle_large_common (int small ATTRIBUTE_UNUSED)
7790{
7791 if (flag_code != CODE_64BIT)
7792 {
7793 s_comm_internal (0, elf_common_parse);
7794 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7795 }
7796 else
7797 {
7798 static segT lbss_section;
7799 asection *saved_com_section_ptr = elf_com_section_ptr;
7800 asection *saved_bss_section = bss_section;
7801
7802 if (lbss_section == NULL)
7803 {
7804 flagword applicable;
7805 segT seg = now_seg;
7806 subsegT subseg = now_subseg;
7807
7808 /* The .lbss section is for local .largecomm symbols. */
7809 lbss_section = subseg_new (".lbss", 0);
7810 applicable = bfd_applicable_section_flags (stdoutput);
7811 bfd_set_section_flags (stdoutput, lbss_section,
7812 applicable & SEC_ALLOC);
7813 seg_info (lbss_section)->bss = 1;
7814
7815 subseg_set (seg, subseg);
7816 }
7817
7818 elf_com_section_ptr = &_bfd_elf_large_com_section;
7819 bss_section = lbss_section;
7820
7821 s_comm_internal (0, elf_common_parse);
7822
7823 elf_com_section_ptr = saved_com_section_ptr;
7824 bss_section = saved_bss_section;
7825 }
7826}
7827#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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