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2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
131 enum processor_type type; /* arch type */
132 i386_cpu_flags flags; /* cpu feature flags */
133}
134arch_entry;
135
e3bb37b5
L		 136static void set_code_flag (int);
137static void set_16bit_gcc_code_flag (int);
138static void set_intel_syntax (int);
1efbbeb4 139static void set_intel_mnemonic (int);
db51cc60 140static void set_allow_index_reg (int);
cb19c032 141static void set_sse_check (int);
e3bb37b5 142static void set_cpu_arch (int);
6482c264 143#ifdef TE_PE
e3bb37b5 144static void pe_directive_secrel (int);
6482c264 145#endif
e3bb37b5
L		 146static void signed_cons (int);
147static char *output_invalid (int c);
ee86248c
JB		 148static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
149 const char *);
150static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
151 const char *);
a7619375 152static int i386_att_operand (char *);
e3bb37b5 153static int i386_intel_operand (char *, int);
ee86248c
JB		 154static int i386_intel_simplify (expressionS *);
155static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 156static const reg_entry *parse_register (char *, char **);
157static char *parse_insn (char *, char *);
158static char *parse_operands (char *, const char *);
159static void swap_operands (void);
4d456e3d 160static void swap_2_operands (int, int);
e3bb37b5
L		 161static void optimize_imm (void);
162static void optimize_disp (void);
d3ce72d0 163static const insn_template *match_template (void);
e3bb37b5
L		 164static int check_string (void);
165static int process_suffix (void);
166static int check_byte_reg (void);
167static int check_long_reg (void);
168static int check_qword_reg (void);
169static int check_word_reg (void);
170static int finalize_imm (void);
171static int process_operands (void);
172static const seg_entry *build_modrm_byte (void);
173static void output_insn (void);
174static void output_imm (fragS *, offsetT);
175static void output_disp (fragS *, offsetT);
29b0f896 176#ifndef I386COFF
e3bb37b5 177static void s_bss (int);
252b5132 178#endif
17d4e2a2
L		 179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
180static void handle_large_common (int small ATTRIBUTE_UNUSED);
181#endif
252b5132 182
a847613f 183static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 184
c0f3af97
L		 185/* VEX prefix. */
186typedef struct
187{
188 /* VEX prefix is either 2 byte or 3 byte. */
189 unsigned char bytes[3];
190 unsigned int length;
191 /* Destination or source register specifier. */
192 const reg_entry *register_specifier;
193} vex_prefix;
194
252b5132 195/* 'md_assemble ()' gathers together information and puts it into a
47926f60 196 i386_insn. */
252b5132 197
520dc8e8
AM		 198union i386_op
199 {
200 expressionS *disps;
201 expressionS *imms;
202 const reg_entry *regs;
203 };
204
252b5132
RH		 205struct _i386_insn
206 {
47926f60 207 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 208 insn_template tm;
252b5132 209
7d5e4556
L		 210 /* SUFFIX holds the instruction size suffix for byte, word, dword
211 or qword, if given. */
252b5132
RH		 212 char suffix;
213
47926f60 214 /* OPERANDS gives the number of given operands. */
252b5132
RH		 215 unsigned int operands;
216
217 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
218 of given register, displacement, memory operands and immediate
47926f60 219 operands. */
252b5132
RH		 220 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
221
222 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 223 use OP[i] for the corresponding operand. */
40fb9820 224 i386_operand_type types[MAX_OPERANDS];
252b5132 225
520dc8e8
AM		 226 /* Displacement expression, immediate expression, or register for each
227 operand. */
228 union i386_op op[MAX_OPERANDS];
252b5132 229
3e73aa7c
JH		 230 /* Flags for operands. */
231 unsigned int flags[MAX_OPERANDS];
232#define Operand_PCrel 1
233
252b5132 234 /* Relocation type for operand */
f86103b7 235 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 236
252b5132
RH		 237 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
238 the base index byte below. */
239 const reg_entry *base_reg;
240 const reg_entry *index_reg;
241 unsigned int log2_scale_factor;
242
243 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 244 explicit segment overrides are given. */
ce8a8b2f 245 const seg_entry *seg[2];
252b5132
RH		 246
247 /* PREFIX holds all the given prefix opcodes (usually null).
248 PREFIXES is the number of prefix opcodes. */
249 unsigned int prefixes;
250 unsigned char prefix[MAX_PREFIXES];
251
252 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 253 addressing modes of this insn are encoded. */
252b5132 254 modrm_byte rm;
3e73aa7c 255 rex_byte rex;
252b5132 256 sib_byte sib;
c0f3af97 257 vex_prefix vex;
b6169b20
L		 258
259 /* Swap operand in encoding. */
4473e004 260 unsigned int swap_operand;
252b5132
RH		 261 };
262
263typedef struct _i386_insn i386_insn;
264
265/* List of chars besides those in app.c:symbol_chars that can start an
266 operand. Used to prevent the scrubber eating vital white-space. */
32137342 267const char extra_symbol_chars[] = "*%-(["
252b5132 268#ifdef LEX_AT
32137342
NC		 269 "@"
270#endif
271#ifdef LEX_QM
272 "?"
252b5132 273#endif
32137342 274 ;
252b5132 275
29b0f896
AM		 276#if (defined (TE_I386AIX) \
277 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 278 && !defined (TE_GNU) \
29b0f896 279 && !defined (TE_LINUX) \
32137342 280 && !defined (TE_NETWARE) \
29b0f896
AM		 281 && !defined (TE_FreeBSD) \
282 && !defined (TE_NetBSD)))
252b5132 283/* This array holds the chars that always start a comment. If the
b3b91714
AM		 284 pre-processor is disabled, these aren't very useful. The option
285 --divide will remove '/' from this list. */
286const char *i386_comment_chars = "#/";
287#define SVR4_COMMENT_CHARS 1
252b5132 288#define PREFIX_SEPARATOR '\\'
252b5132 289
b3b91714
AM		 290#else
291const char *i386_comment_chars = "#";
292#define PREFIX_SEPARATOR '/'
293#endif
294
252b5132
RH		 295/* This array holds the chars that only start a comment at the beginning of
296 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 297 .line and .file directives will appear in the pre-processed output.
298 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 299 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 300 #NO_APP at the beginning of its output.
301 Also note that comments started like this one will always work if
252b5132 302 '/' isn't otherwise defined. */
b3b91714 303const char line_comment_chars[] = "#/";
252b5132 304
63a0b638 305const char line_separator_chars[] = ";";
252b5132 306
ce8a8b2f
AM		 307/* Chars that can be used to separate mant from exp in floating point
308 nums. */
252b5132
RH		 309const char EXP_CHARS[] = "eE";
310
ce8a8b2f
AM		 311/* Chars that mean this number is a floating point constant
312 As in 0f12.456
313 or 0d1.2345e12. */
252b5132
RH		 314const char FLT_CHARS[] = "fFdDxX";
315
ce8a8b2f 316/* Tables for lexical analysis. */
252b5132
RH		 317static char mnemonic_chars[256];
318static char register_chars[256];
319static char operand_chars[256];
320static char identifier_chars[256];
321static char digit_chars[256];
322
ce8a8b2f 323/* Lexical macros. */
252b5132
RH		 324#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
325#define is_operand_char(x) (operand_chars[(unsigned char) x])
326#define is_register_char(x) (register_chars[(unsigned char) x])
327#define is_space_char(x) ((x) == ' ')
328#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
329#define is_digit_char(x) (digit_chars[(unsigned char) x])
330
0234cb7c 331/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 332static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
333
334/* md_assemble() always leaves the strings it's passed unaltered. To
335 effect this we maintain a stack of saved characters that we've smashed
336 with '\0's (indicating end of strings for various sub-fields of the
47926f60 337 assembler instruction). */
252b5132 338static char save_stack[32];
ce8a8b2f 339static char *save_stack_p;
252b5132
RH		 340#define END_STRING_AND_SAVE(s) \
341 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
342#define RESTORE_END_STRING(s) \
343 do { *(s) = *--save_stack_p; } while (0)
344
47926f60 345/* The instruction we're assembling. */
252b5132
RH		 346static i386_insn i;
347
348/* Possible templates for current insn. */
349static const templates *current_templates;
350
31b2323c
L		 351/* Per instruction expressionS buffers: max displacements & immediates. */
352static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
353static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 354
47926f60 355/* Current operand we are working on. */
ee86248c 356static int this_operand = -1;
252b5132 357
3e73aa7c
JH		 358/* We support four different modes. FLAG_CODE variable is used to distinguish
359 these. */
360
361enum flag_code {
362 CODE_32BIT,
363 CODE_16BIT,
364 CODE_64BIT };
365
366static enum flag_code flag_code;
4fa24527 367static unsigned int object_64bit;
3e73aa7c
JH		 368static int use_rela_relocations = 0;
369
370/* The names used to print error messages. */
b77a7acd 371static const char *flag_code_names[] =
3e73aa7c
JH		 372 {
373 "32",
374 "16",
375 "64"
376 };
252b5132 377
47926f60
KH		 378/* 1 for intel syntax,
379 0 if att syntax. */
380static int intel_syntax = 0;
252b5132 381
1efbbeb4
L		 382/* 1 for intel mnemonic,
383 0 if att mnemonic. */
384static int intel_mnemonic = !SYSV386_COMPAT;
385
5209009a 386/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 387static int old_gcc = OLDGCC_COMPAT;
388
a60de03c
JB		 389/* 1 if pseudo registers are permitted. */
390static int allow_pseudo_reg = 0;
391
47926f60
KH		 392/* 1 if register prefix % not required. */
393static int allow_naked_reg = 0;
252b5132 394
ba104c83 395/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 396static int allow_index_reg = 0;
397
daf50ae7
L		 398static enum
399 {
400 sse_check_none = 0,
401 sse_check_warning,
402 sse_check_error
403 }
404sse_check;
405
2ca3ace5
L		 406/* Register prefix used for error message. */
407static const char *register_prefix = "%";
408
47926f60
KH		 409/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
410 leave, push, and pop instructions so that gcc has the same stack
411 frame as in 32 bit mode. */
412static char stackop_size = '\0';
eecb386c 413
12b55ccc
L		 414/* Non-zero to optimize code alignment. */
415int optimize_align_code = 1;
416
47926f60
KH		 417/* Non-zero to quieten some warnings. */
418static int quiet_warnings = 0;
a38cf1db 419
47926f60
KH		 420/* CPU name. */
421static const char *cpu_arch_name = NULL;
6305a203 422static char *cpu_sub_arch_name = NULL;
a38cf1db 423
47926f60 424/* CPU feature flags. */
40fb9820
L		 425static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
426
ccc9c027
L		 427/* If we have selected a cpu we are generating instructions for. */
428static int cpu_arch_tune_set = 0;
429
9103f4f4 430/* Cpu we are generating instructions for. */
fbf3f584 431enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 432
433/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 434static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 435
ccc9c027 436/* CPU instruction set architecture used. */
fbf3f584 437enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 438
9103f4f4 439/* CPU feature flags of instruction set architecture used. */
fbf3f584 440i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 441
fddf5b5b
AM		 442/* If set, conditional jumps are not automatically promoted to handle
443 larger than a byte offset. */
444static unsigned int no_cond_jump_promotion = 0;
445
c0f3af97
L		 446/* Encode SSE instructions with VEX prefix. */
447static unsigned int sse2avx;
448
29b0f896 449/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 450static symbolS *GOT_symbol;
29b0f896 451
a4447b93
RH		 452/* The dwarf2 return column, adjusted for 32 or 64 bit. */
453unsigned int x86_dwarf2_return_column;
454
455/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
456int x86_cie_data_alignment;
457
252b5132 458/* Interface to relax_segment.
fddf5b5b
AM		 459 There are 3 major relax states for 386 jump insns because the
460 different types of jumps add different sizes to frags when we're
461 figuring out what sort of jump to choose to reach a given label. */
252b5132 462
47926f60 463/* Types. */
93c2a809
AM		 464#define UNCOND_JUMP 0
465#define COND_JUMP 1
466#define COND_JUMP86 2
fddf5b5b 467
47926f60 468/* Sizes. */
252b5132
RH		 469#define CODE16 1
470#define SMALL 0
29b0f896 471#define SMALL16 (SMALL | CODE16)
252b5132 472#define BIG 2
29b0f896 473#define BIG16 (BIG | CODE16)
252b5132
RH		 474
475#ifndef INLINE
476#ifdef __GNUC__
477#define INLINE __inline__
478#else
479#define INLINE
480#endif
481#endif
482
fddf5b5b
AM		 483#define ENCODE_RELAX_STATE(type, size) \
484 ((relax_substateT) (((type) << 2) | (size)))
485#define TYPE_FROM_RELAX_STATE(s) \
486 ((s) >> 2)
487#define DISP_SIZE_FROM_RELAX_STATE(s) \
488 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 489
490/* This table is used by relax_frag to promote short jumps to long
491 ones where necessary. SMALL (short) jumps may be promoted to BIG
492 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
493 don't allow a short jump in a 32 bit code segment to be promoted to
494 a 16 bit offset jump because it's slower (requires data size
495 prefix), and doesn't work, unless the destination is in the bottom
496 64k of the code segment (The top 16 bits of eip are zeroed). */
497
498const relax_typeS md_relax_table[] =
499{
24eab124
AM		 500 /* The fields are:
501 1) most positive reach of this state,
502 2) most negative reach of this state,
93c2a809 503 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 504 4) which index into the table to try if we can't fit into this one. */
252b5132 505
fddf5b5b 506 /* UNCOND_JUMP states. */
93c2a809
AM		 507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
508 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
509 /* dword jmp adds 4 bytes to frag:
510 0 extra opcode bytes, 4 displacement bytes. */
252b5132 511 {0, 0, 4, 0},
93c2a809
AM		 512 /* word jmp adds 2 byte2 to frag:
513 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 514 {0, 0, 2, 0},
515
93c2a809
AM		 516 /* COND_JUMP states. */
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
518 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
519 /* dword conditionals adds 5 bytes to frag:
520 1 extra opcode byte, 4 displacement bytes. */
521 {0, 0, 5, 0},
fddf5b5b 522 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 523 1 extra opcode byte, 2 displacement bytes. */
524 {0, 0, 3, 0},
525
526 /* COND_JUMP86 states. */
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
529 /* dword conditionals adds 5 bytes to frag:
530 1 extra opcode byte, 4 displacement bytes. */
531 {0, 0, 5, 0},
532 /* word conditionals add 4 bytes to frag:
533 1 displacement byte and a 3 byte long branch insn. */
534 {0, 0, 4, 0}
252b5132
RH		 535};
536
9103f4f4
L		 537static const arch_entry cpu_arch[] =
538{
6305a203
L		 539 { "generic32", PROCESSOR_GENERIC32,
540 CPU_GENERIC32_FLAGS },
541 { "generic64", PROCESSOR_GENERIC64,
542 CPU_GENERIC64_FLAGS },
543 { "i8086", PROCESSOR_UNKNOWN,
544 CPU_NONE_FLAGS },
545 { "i186", PROCESSOR_UNKNOWN,
546 CPU_I186_FLAGS },
547 { "i286", PROCESSOR_UNKNOWN,
548 CPU_I286_FLAGS },
549 { "i386", PROCESSOR_I386,
550 CPU_I386_FLAGS },
551 { "i486", PROCESSOR_I486,
552 CPU_I486_FLAGS },
553 { "i586", PROCESSOR_PENTIUM,
554 CPU_I586_FLAGS },
555 { "i686", PROCESSOR_PENTIUMPRO,
556 CPU_I686_FLAGS },
557 { "pentium", PROCESSOR_PENTIUM,
558 CPU_I586_FLAGS },
559 { "pentiumpro", PROCESSOR_PENTIUMPRO,
560 CPU_I686_FLAGS },
561 { "pentiumii", PROCESSOR_PENTIUMPRO,
562 CPU_P2_FLAGS },
563 { "pentiumiii",PROCESSOR_PENTIUMPRO,
564 CPU_P3_FLAGS },
565 { "pentium4", PROCESSOR_PENTIUM4,
566 CPU_P4_FLAGS },
567 { "prescott", PROCESSOR_NOCONA,
568 CPU_CORE_FLAGS },
569 { "nocona", PROCESSOR_NOCONA,
570 CPU_NOCONA_FLAGS },
571 { "yonah", PROCESSOR_CORE,
572 CPU_CORE_FLAGS },
573 { "core", PROCESSOR_CORE,
574 CPU_CORE_FLAGS },
575 { "merom", PROCESSOR_CORE2,
576 CPU_CORE2_FLAGS },
577 { "core2", PROCESSOR_CORE2,
578 CPU_CORE2_FLAGS },
bd5295b2
L		 579 { "corei7", PROCESSOR_COREI7,
580 CPU_COREI7_FLAGS },
3632d14b 581 { "l1om", PROCESSOR_L1OM,
8a9036a4 582 CPU_L1OM_FLAGS },
6305a203
L		 583 { "k6", PROCESSOR_K6,
584 CPU_K6_FLAGS },
585 { "k6_2", PROCESSOR_K6,
586 CPU_K6_2_FLAGS },
587 { "athlon", PROCESSOR_ATHLON,
588 CPU_ATHLON_FLAGS },
589 { "sledgehammer", PROCESSOR_K8,
590 CPU_K8_FLAGS },
591 { "opteron", PROCESSOR_K8,
592 CPU_K8_FLAGS },
593 { "k8", PROCESSOR_K8,
594 CPU_K8_FLAGS },
595 { "amdfam10", PROCESSOR_AMDFAM10,
596 CPU_AMDFAM10_FLAGS },
309d3373
JB		 597 { ".8087", PROCESSOR_UNKNOWN,
598 CPU_8087_FLAGS },
599 { ".287", PROCESSOR_UNKNOWN,
600 CPU_287_FLAGS },
601 { ".387", PROCESSOR_UNKNOWN,
602 CPU_387_FLAGS },
603 { ".no87", PROCESSOR_UNKNOWN,
604 CPU_ANY87_FLAGS },
6305a203
L		 605 { ".mmx", PROCESSOR_UNKNOWN,
606 CPU_MMX_FLAGS },
309d3373
JB		 607 { ".nommx", PROCESSOR_UNKNOWN,
608 CPU_3DNOWA_FLAGS },
6305a203
L		 609 { ".sse", PROCESSOR_UNKNOWN,
610 CPU_SSE_FLAGS },
611 { ".sse2", PROCESSOR_UNKNOWN,
612 CPU_SSE2_FLAGS },
613 { ".sse3", PROCESSOR_UNKNOWN,
614 CPU_SSE3_FLAGS },
615 { ".ssse3", PROCESSOR_UNKNOWN,
616 CPU_SSSE3_FLAGS },
617 { ".sse4.1", PROCESSOR_UNKNOWN,
618 CPU_SSE4_1_FLAGS },
619 { ".sse4.2", PROCESSOR_UNKNOWN,
620 CPU_SSE4_2_FLAGS },
621 { ".sse4", PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS },
309d3373
JB		 623 { ".nosse", PROCESSOR_UNKNOWN,
624 CPU_ANY_SSE_FLAGS },
c0f3af97
L		 625 { ".avx", PROCESSOR_UNKNOWN,
626 CPU_AVX_FLAGS },
309d3373
JB		 627 { ".noavx", PROCESSOR_UNKNOWN,
628 CPU_ANY_AVX_FLAGS },
6305a203
L		 629 { ".vmx", PROCESSOR_UNKNOWN,
630 CPU_VMX_FLAGS },
631 { ".smx", PROCESSOR_UNKNOWN,
632 CPU_SMX_FLAGS },
f03fe4c1
L		 633 { ".xsave", PROCESSOR_UNKNOWN,
634 CPU_XSAVE_FLAGS },
c0f3af97
L		 635 { ".aes", PROCESSOR_UNKNOWN,
636 CPU_AES_FLAGS },
594ab6a3
L		 637 { ".pclmul", PROCESSOR_UNKNOWN,
638 CPU_PCLMUL_FLAGS },
c0f3af97 639 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 640 CPU_PCLMUL_FLAGS },
c0f3af97
L		 641 { ".fma", PROCESSOR_UNKNOWN,
642 CPU_FMA_FLAGS },
922d8de8
DR		 643 { ".fma4", PROCESSOR_UNKNOWN,
644 CPU_FMA4_FLAGS },
5dd85c99
SP		 645 { ".xop", PROCESSOR_UNKNOWN,
646 CPU_XOP_FLAGS },
f88c9eb0
SP		 647 { ".lwp", PROCESSOR_UNKNOWN,
648 CPU_LWP_FLAGS },
f1f8f695
L		 649 { ".movbe", PROCESSOR_UNKNOWN,
650 CPU_MOVBE_FLAGS },
651 { ".ept", PROCESSOR_UNKNOWN,
652 CPU_EPT_FLAGS },
bd5295b2
L		 653 { ".clflush", PROCESSOR_UNKNOWN,
654 CPU_CLFLUSH_FLAGS },
655 { ".syscall", PROCESSOR_UNKNOWN,
656 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 657 { ".rdtscp", PROCESSOR_UNKNOWN,
658 CPU_RDTSCP_FLAGS },
6305a203
L		 659 { ".3dnow", PROCESSOR_UNKNOWN,
660 CPU_3DNOW_FLAGS },
661 { ".3dnowa", PROCESSOR_UNKNOWN,
662 CPU_3DNOWA_FLAGS },
663 { ".padlock", PROCESSOR_UNKNOWN,
664 CPU_PADLOCK_FLAGS },
665 { ".pacifica", PROCESSOR_UNKNOWN,
666 CPU_SVME_FLAGS },
667 { ".svme", PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS },
669 { ".sse4a", PROCESSOR_UNKNOWN,
670 CPU_SSE4A_FLAGS },
671 { ".abm", PROCESSOR_UNKNOWN,
672 CPU_ABM_FLAGS },
e413e4e9
AM		 673};
674
704209c0 675#ifdef I386COFF
a6c24e68
NC		 676/* Like s_lcomm_internal in gas/read.c but the alignment string
677 is allowed to be optional. */
678
679static symbolS *
680pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
681{
682 addressT align = 0;
683
684 SKIP_WHITESPACE ();
685
7ab9ffdd 686 if (needs_align
a6c24e68
NC		 687 && *input_line_pointer == ',')
688 {
689 align = parse_align (needs_align - 1);
7ab9ffdd 690
a6c24e68
NC		 691 if (align == (addressT) -1)
692 return NULL;
693 }
694 else
695 {
696 if (size >= 8)
697 align = 3;
698 else if (size >= 4)
699 align = 2;
700 else if (size >= 2)
701 align = 1;
702 else
703 align = 0;
704 }
705
706 bss_alloc (symbolP, size, align);
707 return symbolP;
708}
709
704209c0 710static void
a6c24e68
NC		 711pe_lcomm (int needs_align)
712{
713 s_comm_internal (needs_align * 2, pe_lcomm_internal);
714}
704209c0 715#endif
a6c24e68 716
29b0f896
AM		 717const pseudo_typeS md_pseudo_table[] =
718{
719#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
720 {"align", s_align_bytes, 0},
721#else
722 {"align", s_align_ptwo, 0},
723#endif
724 {"arch", set_cpu_arch, 0},
725#ifndef I386COFF
726 {"bss", s_bss, 0},
a6c24e68
NC		 727#else
728 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 729#endif
730 {"ffloat", float_cons, 'f'},
731 {"dfloat", float_cons, 'd'},
732 {"tfloat", float_cons, 'x'},
733 {"value", cons, 2},
d182319b 734 {"slong", signed_cons, 4},
29b0f896
AM		 735 {"noopt", s_ignore, 0},
736 {"optim", s_ignore, 0},
737 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
738 {"code16", set_code_flag, CODE_16BIT},
739 {"code32", set_code_flag, CODE_32BIT},
740 {"code64", set_code_flag, CODE_64BIT},
741 {"intel_syntax", set_intel_syntax, 1},
742 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 743 {"intel_mnemonic", set_intel_mnemonic, 1},
744 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 745 {"allow_index_reg", set_allow_index_reg, 1},
746 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 747 {"sse_check", set_sse_check, 0},
3b22753a
L		 748#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
749 {"largecomm", handle_large_common, 0},
07a53e5c 750#else
e3bb37b5 751 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 752 {"loc", dwarf2_directive_loc, 0},
753 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 754#endif
6482c264
NC		 755#ifdef TE_PE
756 {"secrel32", pe_directive_secrel, 0},
757#endif
29b0f896
AM		 758 {0, 0, 0}
759};
760
761/* For interface with expression (). */
762extern char *input_line_pointer;
763
764/* Hash table for instruction mnemonic lookup. */
765static struct hash_control *op_hash;
766
767/* Hash table for register lookup. */
768static struct hash_control *reg_hash;
769\f
252b5132 770void
e3bb37b5 771i386_align_code (fragS *fragP, int count)
252b5132 772{
ce8a8b2f
AM		 773 /* Various efficient no-op patterns for aligning code labels.
774 Note: Don't try to assemble the instructions in the comments.
775 0L and 0w are not legal. */
252b5132
RH		 776 static const char f32_1[] =
777 {0x90}; /* nop */
778 static const char f32_2[] =
ccc9c027 779 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 780 static const char f32_3[] =
781 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
782 static const char f32_4[] =
783 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
784 static const char f32_5[] =
785 {0x90, /* nop */
786 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
787 static const char f32_6[] =
788 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
789 static const char f32_7[] =
790 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
791 static const char f32_8[] =
792 {0x90, /* nop */
793 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
794 static const char f32_9[] =
795 {0x89,0xf6, /* movl %esi,%esi */
796 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
797 static const char f32_10[] =
798 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
799 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
800 static const char f32_11[] =
801 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
802 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
803 static const char f32_12[] =
804 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
805 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
806 static const char f32_13[] =
807 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
808 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
809 static const char f32_14[] =
810 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
811 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 812 static const char f16_3[] =
813 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 814 static const char f16_4[] =
815 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
816 static const char f16_5[] =
817 {0x90, /* nop */
818 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
819 static const char f16_6[] =
820 {0x89,0xf6, /* mov %si,%si */
821 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
822 static const char f16_7[] =
823 {0x8d,0x74,0x00, /* lea 0(%si),%si */
824 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
825 static const char f16_8[] =
826 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
827 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 828 static const char jump_31[] =
829 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
830 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
831 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 833 static const char *const f32_patt[] = {
834 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 835 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 836 };
837 static const char *const f16_patt[] = {
76bc74dc 838 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 839 };
ccc9c027
L		 840 /* nopl (%[re]ax) */
841 static const char alt_3[] =
842 {0x0f,0x1f,0x00};
843 /* nopl 0(%[re]ax) */
844 static const char alt_4[] =
845 {0x0f,0x1f,0x40,0x00};
846 /* nopl 0(%[re]ax,%[re]ax,1) */
847 static const char alt_5[] =
848 {0x0f,0x1f,0x44,0x00,0x00};
849 /* nopw 0(%[re]ax,%[re]ax,1) */
850 static const char alt_6[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00};
852 /* nopl 0L(%[re]ax) */
853 static const char alt_7[] =
854 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 /* nopl 0L(%[re]ax,%[re]ax,1) */
856 static const char alt_8[] =
857 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 /* nopw 0L(%[re]ax,%[re]ax,1) */
859 static const char alt_9[] =
860 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
861 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
862 static const char alt_10[] =
863 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_long_11[] =
867 {0x66,
868 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 /* data16
870 data16
871 nopw %cs:0L(%[re]ax,%[re]ax,1) */
872 static const char alt_long_12[] =
873 {0x66,
874 0x66,
875 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
876 /* data16
877 data16
878 data16
879 nopw %cs:0L(%[re]ax,%[re]ax,1) */
880 static const char alt_long_13[] =
881 {0x66,
882 0x66,
883 0x66,
884 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
885 /* data16
886 data16
887 data16
888 data16
889 nopw %cs:0L(%[re]ax,%[re]ax,1) */
890 static const char alt_long_14[] =
891 {0x66,
892 0x66,
893 0x66,
894 0x66,
895 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 /* data16
897 data16
898 data16
899 data16
900 data16
901 nopw %cs:0L(%[re]ax,%[re]ax,1) */
902 static const char alt_long_15[] =
903 {0x66,
904 0x66,
905 0x66,
906 0x66,
907 0x66,
908 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
909 /* nopl 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_11[] =
912 {0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
915 nopw 0(%[re]ax,%[re]ax,1) */
916 static const char alt_short_12[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x66,0x0f,0x1f,0x44,0x00,0x00};
919 /* nopw 0(%[re]ax,%[re]ax,1)
920 nopl 0L(%[re]ax) */
921 static const char alt_short_13[] =
922 {0x66,0x0f,0x1f,0x44,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
924 /* nopl 0L(%[re]ax)
925 nopl 0L(%[re]ax) */
926 static const char alt_short_14[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
929 /* nopl 0L(%[re]ax)
930 nopl 0L(%[re]ax,%[re]ax,1) */
931 static const char alt_short_15[] =
932 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
933 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
934 static const char *const alt_short_patt[] = {
935 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
936 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
937 alt_short_14, alt_short_15
938 };
939 static const char *const alt_long_patt[] = {
940 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
941 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
942 alt_long_14, alt_long_15
943 };
252b5132 944
76bc74dc
L		 945 /* Only align for at least a positive non-zero boundary. */
946 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 947 return;
3e73aa7c 948
ccc9c027
L		 949 /* We need to decide which NOP sequence to use for 32bit and
950 64bit. When -mtune= is used:
4eed87de 951
76bc74dc
L		 952 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
953 PROCESSOR_GENERIC32, f32_patt will be used.
954 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 955 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
956 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 957 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
958 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 959
76bc74dc
L		 960 When -mtune= isn't used, alt_long_patt will be used if
961 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
962 be used.
ccc9c027
L		 963
964 When -march= or .arch is used, we can't use anything beyond
965 cpu_arch_isa_flags. */
966
967 if (flag_code == CODE_16BIT)
968 {
ccc9c027 969 if (count > 8)
33fef721 970 {
76bc74dc
L		 971 memcpy (fragP->fr_literal + fragP->fr_fix,
972 jump_31, count);
973 /* Adjust jump offset. */
974 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 975 }
76bc74dc
L		 976 else
977 memcpy (fragP->fr_literal + fragP->fr_fix,
978 f16_patt[count - 1], count);
252b5132 979 }
33fef721 980 else
ccc9c027
L		 981 {
982 const char *const *patt = NULL;
983
fbf3f584 984 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 985 {
986 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
987 switch (cpu_arch_tune)
988 {
989 case PROCESSOR_UNKNOWN:
990 /* We use cpu_arch_isa_flags to check if we SHOULD
991 optimize for Cpu686. */
fbf3f584 992 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 993 patt = alt_long_patt;
ccc9c027
L		 994 else
995 patt = f32_patt;
996 break;
ccc9c027
L		 997 case PROCESSOR_PENTIUMPRO:
998 case PROCESSOR_PENTIUM4:
999 case PROCESSOR_NOCONA:
ef05d495 1000 case PROCESSOR_CORE:
76bc74dc 1001 case PROCESSOR_CORE2:
bd5295b2 1002 case PROCESSOR_COREI7:
3632d14b 1003 case PROCESSOR_L1OM:
76bc74dc
L		 1004 case PROCESSOR_GENERIC64:
1005 patt = alt_long_patt;
1006 break;
ccc9c027
L		 1007 case PROCESSOR_K6:
1008 case PROCESSOR_ATHLON:
1009 case PROCESSOR_K8:
4eed87de 1010 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1011 patt = alt_short_patt;
1012 break;
76bc74dc 1013 case PROCESSOR_I386:
ccc9c027
L		 1014 case PROCESSOR_I486:
1015 case PROCESSOR_PENTIUM:
1016 case PROCESSOR_GENERIC32:
1017 patt = f32_patt;
1018 break;
4eed87de 1019 }
ccc9c027
L		 1020 }
1021 else
1022 {
fbf3f584 1023 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1024 {
1025 case PROCESSOR_UNKNOWN:
e6a14101 1026 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1027 PROCESSOR_UNKNOWN. */
1028 abort ();
1029 break;
1030
76bc74dc 1031 case PROCESSOR_I386:
ccc9c027
L		 1032 case PROCESSOR_I486:
1033 case PROCESSOR_PENTIUM:
ccc9c027
L		 1034 case PROCESSOR_K6:
1035 case PROCESSOR_ATHLON:
1036 case PROCESSOR_K8:
4eed87de 1037 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1038 case PROCESSOR_GENERIC32:
1039 /* We use cpu_arch_isa_flags to check if we CAN optimize
1040 for Cpu686. */
fbf3f584 1041 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1042 patt = alt_short_patt;
1043 else
1044 patt = f32_patt;
1045 break;
76bc74dc
L		 1046 case PROCESSOR_PENTIUMPRO:
1047 case PROCESSOR_PENTIUM4:
1048 case PROCESSOR_NOCONA:
1049 case PROCESSOR_CORE:
ef05d495 1050 case PROCESSOR_CORE2:
bd5295b2 1051 case PROCESSOR_COREI7:
3632d14b 1052 case PROCESSOR_L1OM:
fbf3f584 1053 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1054 patt = alt_long_patt;
1055 else
1056 patt = f32_patt;
1057 break;
1058 case PROCESSOR_GENERIC64:
76bc74dc 1059 patt = alt_long_patt;
ccc9c027 1060 break;
4eed87de 1061 }
ccc9c027
L		 1062 }
1063
76bc74dc
L		 1064 if (patt == f32_patt)
1065 {
1066 /* If the padding is less than 15 bytes, we use the normal
1067 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1068 its offset. */
1069 int limit;
76ba9986 1070
711eedef
L		 1071 /* For 64bit, the limit is 3 bytes. */
1072 if (flag_code == CODE_64BIT
1073 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1074 limit = 3;
1075 else
1076 limit = 15;
1077 if (count < limit)
76bc74dc
L		 1078 memcpy (fragP->fr_literal + fragP->fr_fix,
1079 patt[count - 1], count);
1080 else
1081 {
1082 memcpy (fragP->fr_literal + fragP->fr_fix,
1083 jump_31, count);
1084 /* Adjust jump offset. */
1085 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1086 }
1087 }
1088 else
1089 {
1090 /* Maximum length of an instruction is 15 byte. If the
1091 padding is greater than 15 bytes and we don't use jump,
1092 we have to break it into smaller pieces. */
1093 int padding = count;
1094 while (padding > 15)
1095 {
1096 padding -= 15;
1097 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1098 patt [14], 15);
1099 }
1100
1101 if (padding)
1102 memcpy (fragP->fr_literal + fragP->fr_fix,
1103 patt [padding - 1], padding);
1104 }
ccc9c027 1105 }
33fef721 1106 fragP->fr_var = count;
252b5132
RH		 1107}
1108
c6fb90c8 1109static INLINE int
0dfbf9d7 1110operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1111{
0dfbf9d7 1112 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1113 {
1114 case 3:
0dfbf9d7 1115 if (x->array[2])
c6fb90c8
L		 1116 return 0;
1117 case 2:
0dfbf9d7 1118 if (x->array[1])
c6fb90c8
L		 1119 return 0;
1120 case 1:
0dfbf9d7 1121 return !x->array[0];
c6fb90c8
L		 1122 default:
1123 abort ();
1124 }
40fb9820
L		 1125}
1126
c6fb90c8 1127static INLINE void
0dfbf9d7 1128operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1129{
0dfbf9d7 1130 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1131 {
1132 case 3:
0dfbf9d7 1133 x->array[2] = v;
c6fb90c8 1134 case 2:
0dfbf9d7 1135 x->array[1] = v;
c6fb90c8 1136 case 1:
0dfbf9d7 1137 x->array[0] = v;
c6fb90c8
L		 1138 break;
1139 default:
1140 abort ();
1141 }
1142}
40fb9820 1143
c6fb90c8 1144static INLINE int
0dfbf9d7
L		 1145operand_type_equal (const union i386_operand_type *x,
1146 const union i386_operand_type *y)
c6fb90c8 1147{
0dfbf9d7 1148 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1149 {
1150 case 3:
0dfbf9d7 1151 if (x->array[2] != y->array[2])
c6fb90c8
L		 1152 return 0;
1153 case 2:
0dfbf9d7 1154 if (x->array[1] != y->array[1])
c6fb90c8
L		 1155 return 0;
1156 case 1:
0dfbf9d7 1157 return x->array[0] == y->array[0];
c6fb90c8
L		 1158 break;
1159 default:
1160 abort ();
1161 }
1162}
40fb9820 1163
0dfbf9d7
L		 1164static INLINE int
1165cpu_flags_all_zero (const union i386_cpu_flags *x)
1166{
1167 switch (ARRAY_SIZE(x->array))
1168 {
1169 case 3:
1170 if (x->array[2])
1171 return 0;
1172 case 2:
1173 if (x->array[1])
1174 return 0;
1175 case 1:
1176 return !x->array[0];
1177 default:
1178 abort ();
1179 }
1180}
1181
1182static INLINE void
1183cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1184{
1185 switch (ARRAY_SIZE(x->array))
1186 {
1187 case 3:
1188 x->array[2] = v;
1189 case 2:
1190 x->array[1] = v;
1191 case 1:
1192 x->array[0] = v;
1193 break;
1194 default:
1195 abort ();
1196 }
1197}
1198
1199static INLINE int
1200cpu_flags_equal (const union i386_cpu_flags *x,
1201 const union i386_cpu_flags *y)
1202{
1203 switch (ARRAY_SIZE(x->array))
1204 {
1205 case 3:
1206 if (x->array[2] != y->array[2])
1207 return 0;
1208 case 2:
1209 if (x->array[1] != y->array[1])
1210 return 0;
1211 case 1:
1212 return x->array[0] == y->array[0];
1213 break;
1214 default:
1215 abort ();
1216 }
1217}
c6fb90c8
L		 1218
1219static INLINE int
1220cpu_flags_check_cpu64 (i386_cpu_flags f)
1221{
1222 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1223 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1224}
1225
c6fb90c8
L		 1226static INLINE i386_cpu_flags
1227cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1228{
c6fb90c8
L		 1229 switch (ARRAY_SIZE (x.array))
1230 {
1231 case 3:
1232 x.array [2] &= y.array [2];
1233 case 2:
1234 x.array [1] &= y.array [1];
1235 case 1:
1236 x.array [0] &= y.array [0];
1237 break;
1238 default:
1239 abort ();
1240 }
1241 return x;
1242}
40fb9820 1243
c6fb90c8
L		 1244static INLINE i386_cpu_flags
1245cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1246{
c6fb90c8 1247 switch (ARRAY_SIZE (x.array))
40fb9820 1248 {
c6fb90c8
L		 1249 case 3:
1250 x.array [2] |= y.array [2];
1251 case 2:
1252 x.array [1] |= y.array [1];
1253 case 1:
1254 x.array [0] |= y.array [0];
40fb9820
L		 1255 break;
1256 default:
1257 abort ();
1258 }
40fb9820
L		 1259 return x;
1260}
1261
309d3373
JB		 1262static INLINE i386_cpu_flags
1263cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1264{
1265 switch (ARRAY_SIZE (x.array))
1266 {
1267 case 3:
1268 x.array [2] &= ~y.array [2];
1269 case 2:
1270 x.array [1] &= ~y.array [1];
1271 case 1:
1272 x.array [0] &= ~y.array [0];
1273 break;
1274 default:
1275 abort ();
1276 }
1277 return x;
1278}
1279
c0f3af97
L		 1280#define CPU_FLAGS_ARCH_MATCH 0x1
1281#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1282#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1283#define CPU_FLAGS_PCLMUL_MATCH 0x8
1284#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1285
a5ff0eb2 1286#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1287 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1288 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1289#define CPU_FLAGS_PERFECT_MATCH \
1290 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1291
1292/* Return CPU flags match bits. */
3629bb00 1293
40fb9820 1294static int
d3ce72d0 1295cpu_flags_match (const insn_template *t)
40fb9820 1296{
c0f3af97
L		 1297 i386_cpu_flags x = t->cpu_flags;
1298 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1299
1300 x.bitfield.cpu64 = 0;
1301 x.bitfield.cpuno64 = 0;
1302
0dfbf9d7 1303 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1304 {
1305 /* This instruction is available on all archs. */
1306 match |= CPU_FLAGS_32BIT_MATCH;
1307 }
3629bb00
L		 1308 else
1309 {
c0f3af97 1310 /* This instruction is available only on some archs. */
3629bb00
L		 1311 i386_cpu_flags cpu = cpu_arch_flags;
1312
1313 cpu.bitfield.cpu64 = 0;
1314 cpu.bitfield.cpuno64 = 0;
1315 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1316 if (!cpu_flags_all_zero (&cpu))
1317 {
a5ff0eb2
L		 1318 if (x.bitfield.cpuavx)
1319 {
ce2f5b3c 1320 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1321 if (cpu.bitfield.cpuavx)
1322 {
1323 /* Check SSE2AVX. */
1324 if (!t->opcode_modifier.sse2avx|| sse2avx)
1325 {
1326 match |= (CPU_FLAGS_ARCH_MATCH
1327 | CPU_FLAGS_AVX_MATCH);
1328 /* Check AES. */
1329 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1330 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1331 /* Check PCLMUL. */
1332 if (!x.bitfield.cpupclmul
1333 || cpu.bitfield.cpupclmul)
1334 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1335 }
1336 }
1337 else
1338 match |= CPU_FLAGS_ARCH_MATCH;
1339 }
1340 else
c0f3af97
L		 1341 match |= CPU_FLAGS_32BIT_MATCH;
1342 }
3629bb00 1343 }
c0f3af97 1344 return match;
40fb9820
L		 1345}
1346
c6fb90c8
L		 1347static INLINE i386_operand_type
1348operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1349{
c6fb90c8
L		 1350 switch (ARRAY_SIZE (x.array))
1351 {
1352 case 3:
1353 x.array [2] &= y.array [2];
1354 case 2:
1355 x.array [1] &= y.array [1];
1356 case 1:
1357 x.array [0] &= y.array [0];
1358 break;
1359 default:
1360 abort ();
1361 }
1362 return x;
40fb9820
L		 1363}
1364
c6fb90c8
L		 1365static INLINE i386_operand_type
1366operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1367{
c6fb90c8 1368 switch (ARRAY_SIZE (x.array))
40fb9820 1369 {
c6fb90c8
L		 1370 case 3:
1371 x.array [2] |= y.array [2];
1372 case 2:
1373 x.array [1] |= y.array [1];
1374 case 1:
1375 x.array [0] |= y.array [0];
40fb9820
L		 1376 break;
1377 default:
1378 abort ();
1379 }
c6fb90c8
L		 1380 return x;
1381}
40fb9820 1382
c6fb90c8
L		 1383static INLINE i386_operand_type
1384operand_type_xor (i386_operand_type x, i386_operand_type y)
1385{
1386 switch (ARRAY_SIZE (x.array))
1387 {
1388 case 3:
1389 x.array [2] ^= y.array [2];
1390 case 2:
1391 x.array [1] ^= y.array [1];
1392 case 1:
1393 x.array [0] ^= y.array [0];
1394 break;
1395 default:
1396 abort ();
1397 }
40fb9820
L		 1398 return x;
1399}
1400
1401static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1402static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1403static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1404static const i386_operand_type inoutportreg
1405 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1406static const i386_operand_type reg16_inoutportreg
1407 = OPERAND_TYPE_REG16_INOUTPORTREG;
1408static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1409static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1410static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1411static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1412static const i386_operand_type anydisp
1413 = OPERAND_TYPE_ANYDISP;
40fb9820 1414static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1415static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1416static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1417static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1418static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1419static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1420static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1421static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1422static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1423static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1424static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1425
1426enum operand_type
1427{
1428 reg,
40fb9820
L		 1429 imm,
1430 disp,
1431 anymem
1432};
1433
c6fb90c8 1434static INLINE int
40fb9820
L		 1435operand_type_check (i386_operand_type t, enum operand_type c)
1436{
1437 switch (c)
1438 {
1439 case reg:
1440 return (t.bitfield.reg8
1441 || t.bitfield.reg16
1442 || t.bitfield.reg32
1443 || t.bitfield.reg64);
1444
40fb9820
L		 1445 case imm:
1446 return (t.bitfield.imm8
1447 || t.bitfield.imm8s
1448 || t.bitfield.imm16
1449 || t.bitfield.imm32
1450 || t.bitfield.imm32s
1451 || t.bitfield.imm64);
1452
1453 case disp:
1454 return (t.bitfield.disp8
1455 || t.bitfield.disp16
1456 || t.bitfield.disp32
1457 || t.bitfield.disp32s
1458 || t.bitfield.disp64);
1459
1460 case anymem:
1461 return (t.bitfield.disp8
1462 || t.bitfield.disp16
1463 || t.bitfield.disp32
1464 || t.bitfield.disp32s
1465 || t.bitfield.disp64
1466 || t.bitfield.baseindex);
1467
1468 default:
1469 abort ();
1470 }
2cfe26b6
AM		 1471
1472 return 0;
40fb9820
L		 1473}
1474
5c07affc
L		 1475/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1476 operand J for instruction template T. */
1477
1478static INLINE int
d3ce72d0 1479match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1480{
1481 return !((i.types[j].bitfield.byte
1482 && !t->operand_types[j].bitfield.byte)
1483 || (i.types[j].bitfield.word
1484 && !t->operand_types[j].bitfield.word)
1485 || (i.types[j].bitfield.dword
1486 && !t->operand_types[j].bitfield.dword)
1487 || (i.types[j].bitfield.qword
1488 && !t->operand_types[j].bitfield.qword));
1489}
1490
1491/* Return 1 if there is no conflict in any size on operand J for
1492 instruction template T. */
1493
1494static INLINE int
d3ce72d0 1495match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1496{
1497 return (match_reg_size (t, j)
1498 && !((i.types[j].bitfield.unspecified
1499 && !t->operand_types[j].bitfield.unspecified)
1500 || (i.types[j].bitfield.fword
1501 && !t->operand_types[j].bitfield.fword)
1502 || (i.types[j].bitfield.tbyte
1503 && !t->operand_types[j].bitfield.tbyte)
1504 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1505 && !t->operand_types[j].bitfield.xmmword)
1506 || (i.types[j].bitfield.ymmword
1507 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1508}
1509
1510/* Return 1 if there is no size conflict on any operands for
1511 instruction template T. */
1512
1513static INLINE int
d3ce72d0 1514operand_size_match (const insn_template *t)
5c07affc
L		 1515{
1516 unsigned int j;
1517 int match = 1;
1518
1519 /* Don't check jump instructions. */
1520 if (t->opcode_modifier.jump
1521 || t->opcode_modifier.jumpbyte
1522 || t->opcode_modifier.jumpdword
1523 || t->opcode_modifier.jumpintersegment)
1524 return match;
1525
1526 /* Check memory and accumulator operand size. */
1527 for (j = 0; j < i.operands; j++)
1528 {
1529 if (t->operand_types[j].bitfield.anysize)
1530 continue;
1531
1532 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1533 {
1534 match = 0;
1535 break;
1536 }
1537
1538 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1539 {
1540 match = 0;
1541 break;
1542 }
1543 }
1544
1545 if (match
1546 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1547 return match;
1548
1549 /* Check reverse. */
9c2799c2 1550 gas_assert (i.operands == 2);
5c07affc
L		 1551
1552 match = 1;
1553 for (j = 0; j < 2; j++)
1554 {
1555 if (t->operand_types[j].bitfield.acc
1556 && !match_reg_size (t, j ? 0 : 1))
1557 {
1558 match = 0;
1559 break;
1560 }
1561
1562 if (i.types[j].bitfield.mem
1563 && !match_mem_size (t, j ? 0 : 1))
1564 {
1565 match = 0;
1566 break;
1567 }
1568 }
1569
1570 return match;
1571}
1572
c6fb90c8 1573static INLINE int
40fb9820
L		 1574operand_type_match (i386_operand_type overlap,
1575 i386_operand_type given)
1576{
1577 i386_operand_type temp = overlap;
1578
1579 temp.bitfield.jumpabsolute = 0;
7d5e4556 1580 temp.bitfield.unspecified = 0;
5c07affc
L		 1581 temp.bitfield.byte = 0;
1582 temp.bitfield.word = 0;
1583 temp.bitfield.dword = 0;
1584 temp.bitfield.fword = 0;
1585 temp.bitfield.qword = 0;
1586 temp.bitfield.tbyte = 0;
1587 temp.bitfield.xmmword = 0;
c0f3af97 1588 temp.bitfield.ymmword = 0;
0dfbf9d7 1589 if (operand_type_all_zero (&temp))
40fb9820
L		 1590 return 0;
1591
1592 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1593 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1594}
1595
7d5e4556 1596/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1597 unless the expected operand type register overlap is null.
1598 Note that Acc in a template matches every size of reg. */
1599
c6fb90c8 1600static INLINE int
40fb9820
L		 1601operand_type_register_match (i386_operand_type m0,
1602 i386_operand_type g0,
1603 i386_operand_type t0,
1604 i386_operand_type m1,
1605 i386_operand_type g1,
1606 i386_operand_type t1)
1607{
1608 if (!operand_type_check (g0, reg))
1609 return 1;
1610
1611 if (!operand_type_check (g1, reg))
1612 return 1;
1613
1614 if (g0.bitfield.reg8 == g1.bitfield.reg8
1615 && g0.bitfield.reg16 == g1.bitfield.reg16
1616 && g0.bitfield.reg32 == g1.bitfield.reg32
1617 && g0.bitfield.reg64 == g1.bitfield.reg64)
1618 return 1;
1619
1620 if (m0.bitfield.acc)
1621 {
1622 t0.bitfield.reg8 = 1;
1623 t0.bitfield.reg16 = 1;
1624 t0.bitfield.reg32 = 1;
1625 t0.bitfield.reg64 = 1;
1626 }
1627
1628 if (m1.bitfield.acc)
1629 {
1630 t1.bitfield.reg8 = 1;
1631 t1.bitfield.reg16 = 1;
1632 t1.bitfield.reg32 = 1;
1633 t1.bitfield.reg64 = 1;
1634 }
1635
1636 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1637 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1638 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1639 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1640}
1641
252b5132 1642static INLINE unsigned int
40fb9820 1643mode_from_disp_size (i386_operand_type t)
252b5132 1644{
40fb9820
L		 1645 if (t.bitfield.disp8)
1646 return 1;
1647 else if (t.bitfield.disp16
1648 || t.bitfield.disp32
1649 || t.bitfield.disp32s)
1650 return 2;
1651 else
1652 return 0;
252b5132
RH		 1653}
1654
1655static INLINE int
e3bb37b5 1656fits_in_signed_byte (offsetT num)
252b5132
RH		 1657{
1658 return (num >= -128) && (num <= 127);
47926f60 1659}
252b5132
RH		 1660
1661static INLINE int
e3bb37b5 1662fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1663{
1664 return (num & 0xff) == num;
47926f60 1665}
252b5132
RH		 1666
1667static INLINE int
e3bb37b5 1668fits_in_unsigned_word (offsetT num)
252b5132
RH		 1669{
1670 return (num & 0xffff) == num;
47926f60 1671}
252b5132
RH		 1672
1673static INLINE int
e3bb37b5 1674fits_in_signed_word (offsetT num)
252b5132
RH		 1675{
1676 return (-32768 <= num) && (num <= 32767);
47926f60 1677}
2a962e6d 1678
3e73aa7c 1679static INLINE int
e3bb37b5 1680fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1681{
1682#ifndef BFD64
1683 return 1;
1684#else
1685 return (!(((offsetT) -1 << 31) & num)
1686 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1687#endif
1688} /* fits_in_signed_long() */
2a962e6d 1689
3e73aa7c 1690static INLINE int
e3bb37b5 1691fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1692{
1693#ifndef BFD64
1694 return 1;
1695#else
1696 return (num & (((offsetT) 2 << 31) - 1)) == num;
1697#endif
1698} /* fits_in_unsigned_long() */
252b5132 1699
40fb9820 1700static i386_operand_type
e3bb37b5 1701smallest_imm_type (offsetT num)
252b5132 1702{
40fb9820 1703 i386_operand_type t;
7ab9ffdd 1704
0dfbf9d7 1705 operand_type_set (&t, 0);
40fb9820
L		 1706 t.bitfield.imm64 = 1;
1707
1708 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1709 {
1710 /* This code is disabled on the 486 because all the Imm1 forms
1711 in the opcode table are slower on the i486. They're the
1712 versions with the implicitly specified single-position
1713 displacement, which has another syntax if you really want to
1714 use that form. */
40fb9820
L		 1715 t.bitfield.imm1 = 1;
1716 t.bitfield.imm8 = 1;
1717 t.bitfield.imm8s = 1;
1718 t.bitfield.imm16 = 1;
1719 t.bitfield.imm32 = 1;
1720 t.bitfield.imm32s = 1;
1721 }
1722 else if (fits_in_signed_byte (num))
1723 {
1724 t.bitfield.imm8 = 1;
1725 t.bitfield.imm8s = 1;
1726 t.bitfield.imm16 = 1;
1727 t.bitfield.imm32 = 1;
1728 t.bitfield.imm32s = 1;
1729 }
1730 else if (fits_in_unsigned_byte (num))
1731 {
1732 t.bitfield.imm8 = 1;
1733 t.bitfield.imm16 = 1;
1734 t.bitfield.imm32 = 1;
1735 t.bitfield.imm32s = 1;
1736 }
1737 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1738 {
1739 t.bitfield.imm16 = 1;
1740 t.bitfield.imm32 = 1;
1741 t.bitfield.imm32s = 1;
1742 }
1743 else if (fits_in_signed_long (num))
1744 {
1745 t.bitfield.imm32 = 1;
1746 t.bitfield.imm32s = 1;
1747 }
1748 else if (fits_in_unsigned_long (num))
1749 t.bitfield.imm32 = 1;
1750
1751 return t;
47926f60 1752}
252b5132 1753
847f7ad4 1754static offsetT
e3bb37b5 1755offset_in_range (offsetT val, int size)
847f7ad4 1756{
508866be 1757 addressT mask;
ba2adb93 1758
847f7ad4
AM		 1759 switch (size)
1760 {
508866be
L		 1761 case 1: mask = ((addressT) 1 << 8) - 1; break;
1762 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1763 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1764#ifdef BFD64
1765 case 8: mask = ((addressT) 2 << 63) - 1; break;
1766#endif
47926f60 1767 default: abort ();
847f7ad4
AM		 1768 }
1769
9de868bf
L		 1770#ifdef BFD64
1771 /* If BFD64, sign extend val for 32bit address mode. */
1772 if (flag_code != CODE_64BIT
1773 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1774 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1775 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1776#endif
ba2adb93 1777
47926f60 1778 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1779 {
1780 char buf1[40], buf2[40];
1781
1782 sprint_value (buf1, val);
1783 sprint_value (buf2, val & mask);
1784 as_warn (_("%s shortened to %s"), buf1, buf2);
1785 }
1786 return val & mask;
1787}
1788
c32fa91d
L		 1789enum PREFIX_GROUP
1790{
1791 PREFIX_EXIST = 0,
1792 PREFIX_LOCK,
1793 PREFIX_REP,
1794 PREFIX_OTHER
1795};
1796
1797/* Returns
1798 a. PREFIX_EXIST if attempting to add a prefix where one from the
1799 same class already exists.
1800 b. PREFIX_LOCK if lock prefix is added.
1801 c. PREFIX_REP if rep/repne prefix is added.
1802 d. PREFIX_OTHER if other prefix is added.
1803 */
1804
1805static enum PREFIX_GROUP
e3bb37b5 1806add_prefix (unsigned int prefix)
252b5132 1807{
c32fa91d 1808 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1809 unsigned int q;
252b5132 1810
29b0f896
AM		 1811 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1812 && flag_code == CODE_64BIT)
b1905489 1813 {
161a04f6
L		 1814 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1815 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1816 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1817 ret = PREFIX_EXIST;
b1905489
JB		 1818 q = REX_PREFIX;
1819 }
3e73aa7c 1820 else
b1905489
JB		 1821 {
1822 switch (prefix)
1823 {
1824 default:
1825 abort ();
1826
1827 case CS_PREFIX_OPCODE:
1828 case DS_PREFIX_OPCODE:
1829 case ES_PREFIX_OPCODE:
1830 case FS_PREFIX_OPCODE:
1831 case GS_PREFIX_OPCODE:
1832 case SS_PREFIX_OPCODE:
1833 q = SEG_PREFIX;
1834 break;
1835
1836 case REPNE_PREFIX_OPCODE:
1837 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1838 q = REP_PREFIX;
1839 ret = PREFIX_REP;
1840 break;
1841
b1905489 1842 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1843 q = LOCK_PREFIX;
1844 ret = PREFIX_LOCK;
b1905489
JB		 1845 break;
1846
1847 case FWAIT_OPCODE:
1848 q = WAIT_PREFIX;
1849 break;
1850
1851 case ADDR_PREFIX_OPCODE:
1852 q = ADDR_PREFIX;
1853 break;
1854
1855 case DATA_PREFIX_OPCODE:
1856 q = DATA_PREFIX;
1857 break;
1858 }
1859 if (i.prefix[q] != 0)
c32fa91d 1860 ret = PREFIX_EXIST;
b1905489 1861 }
252b5132 1862
b1905489 1863 if (ret)
252b5132 1864 {
b1905489
JB		 1865 if (!i.prefix[q])
1866 ++i.prefixes;
1867 i.prefix[q] |= prefix;
252b5132 1868 }
b1905489
JB		 1869 else
1870 as_bad (_("same type of prefix used twice"));
252b5132 1871
252b5132
RH		 1872 return ret;
1873}
1874
1875static void
e3bb37b5 1876set_code_flag (int value)
eecb386c 1877{
1e9cc1c2 1878 flag_code = (enum flag_code) value;
40fb9820
L		 1879 if (flag_code == CODE_64BIT)
1880 {
1881 cpu_arch_flags.bitfield.cpu64 = 1;
1882 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1883 }
1884 else
1885 {
1886 cpu_arch_flags.bitfield.cpu64 = 0;
1887 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1888 }
1889 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1890 {
1891 as_bad (_("64bit mode not supported on this CPU."));
1892 }
40fb9820 1893 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1894 {
1895 as_bad (_("32bit mode not supported on this CPU."));
1896 }
eecb386c
AM		 1897 stackop_size = '\0';
1898}
1899
1900static void
e3bb37b5 1901set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1902{
1e9cc1c2 1903 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1904 if (flag_code != CODE_16BIT)
1905 abort ();
1906 cpu_arch_flags.bitfield.cpu64 = 0;
1907 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1908 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1909}
1910
1911static void
e3bb37b5 1912set_intel_syntax (int syntax_flag)
252b5132
RH		 1913{
1914 /* Find out if register prefixing is specified. */
1915 int ask_naked_reg = 0;
1916
1917 SKIP_WHITESPACE ();
29b0f896 1918 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1919 {
1920 char *string = input_line_pointer;
1921 int e = get_symbol_end ();
1922
47926f60 1923 if (strcmp (string, "prefix") == 0)
252b5132 1924 ask_naked_reg = 1;
47926f60 1925 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1926 ask_naked_reg = -1;
1927 else
d0b47220 1928 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1929 *input_line_pointer = e;
1930 }
1931 demand_empty_rest_of_line ();
c3332e24 1932
252b5132
RH		 1933 intel_syntax = syntax_flag;
1934
1935 if (ask_naked_reg == 0)
f86103b7
AM		 1936 allow_naked_reg = (intel_syntax
1937 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1938 else
1939 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1940
ee86248c 1941 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1942
e4a3b5a4 1943 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1944 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1945 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1946}
1947
1efbbeb4
L		 1948static void
1949set_intel_mnemonic (int mnemonic_flag)
1950{
e1d4d893 1951 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1952}
1953
db51cc60
L		 1954static void
1955set_allow_index_reg (int flag)
1956{
1957 allow_index_reg = flag;
1958}
1959
cb19c032
L		 1960static void
1961set_sse_check (int dummy ATTRIBUTE_UNUSED)
1962{
1963 SKIP_WHITESPACE ();
1964
1965 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1966 {
1967 char *string = input_line_pointer;
1968 int e = get_symbol_end ();
1969
1970 if (strcmp (string, "none") == 0)
1971 sse_check = sse_check_none;
1972 else if (strcmp (string, "warning") == 0)
1973 sse_check = sse_check_warning;
1974 else if (strcmp (string, "error") == 0)
1975 sse_check = sse_check_error;
1976 else
1977 as_bad (_("bad argument to sse_check directive."));
1978 *input_line_pointer = e;
1979 }
1980 else
1981 as_bad (_("missing argument for sse_check directive"));
1982
1983 demand_empty_rest_of_line ();
1984}
1985
8a9036a4
L		 1986static void
1987check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1988 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1989{
1990#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1991 static const char *arch;
1992
1993 /* Intel LIOM is only supported on ELF. */
1994 if (!IS_ELF)
1995 return;
1996
1997 if (!arch)
1998 {
1999 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2000 use default_arch. */
2001 arch = cpu_arch_name;
2002 if (!arch)
2003 arch = default_arch;
2004 }
2005
3632d14b 2006 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2007 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2008 || new_flag.bitfield.cpul1om)
8a9036a4 2009 return;
76ba9986 2010
8a9036a4
L		 2011 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2012#endif
2013}
2014
e413e4e9 2015static void
e3bb37b5 2016set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2017{
47926f60 2018 SKIP_WHITESPACE ();
e413e4e9 2019
29b0f896 2020 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2021 {
2022 char *string = input_line_pointer;
2023 int e = get_symbol_end ();
9103f4f4 2024 unsigned int i;
40fb9820 2025 i386_cpu_flags flags;
e413e4e9 2026
9103f4f4 2027 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 2028 {
2029 if (strcmp (string, cpu_arch[i].name) == 0)
2030 {
8a9036a4
L		 2031 check_cpu_arch_compatible (string, cpu_arch[i].flags);
2032
5c6af06e
JB		 2033 if (*string != '.')
2034 {
2035 cpu_arch_name = cpu_arch[i].name;
2036 cpu_sub_arch_name = NULL;
40fb9820
L		 2037 cpu_arch_flags = cpu_arch[i].flags;
2038 if (flag_code == CODE_64BIT)
2039 {
2040 cpu_arch_flags.bitfield.cpu64 = 1;
2041 cpu_arch_flags.bitfield.cpuno64 = 0;
2042 }
2043 else
2044 {
2045 cpu_arch_flags.bitfield.cpu64 = 0;
2046 cpu_arch_flags.bitfield.cpuno64 = 1;
2047 }
ccc9c027 2048 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 2049 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 2050 if (!cpu_arch_tune_set)
2051 {
2052 cpu_arch_tune = cpu_arch_isa;
2053 cpu_arch_tune_flags = cpu_arch_isa_flags;
2054 }
5c6af06e
JB		 2055 break;
2056 }
40fb9820 2057
309d3373
JB		 2058 if (strncmp (string + 1, "no", 2))
2059 flags = cpu_flags_or (cpu_arch_flags,
2060 cpu_arch[i].flags);
2061 else
2062 flags = cpu_flags_and_not (cpu_arch_flags,
2063 cpu_arch[i].flags);
0dfbf9d7 2064 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2065 {
6305a203
L		 2066 if (cpu_sub_arch_name)
2067 {
2068 char *name = cpu_sub_arch_name;
2069 cpu_sub_arch_name = concat (name,
2070 cpu_arch[i].name,
1bf57e9f 2071 (const char *) NULL);
6305a203
L		 2072 free (name);
2073 }
2074 else
2075 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2076 cpu_arch_flags = flags;
5c6af06e
JB		 2077 }
2078 *input_line_pointer = e;
2079 demand_empty_rest_of_line ();
2080 return;
e413e4e9
AM		 2081 }
2082 }
9103f4f4 2083 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2084 as_bad (_("no such architecture: `%s'"), string);
2085
2086 *input_line_pointer = e;
2087 }
2088 else
2089 as_bad (_("missing cpu architecture"));
2090
fddf5b5b
AM		 2091 no_cond_jump_promotion = 0;
2092 if (*input_line_pointer == ','
29b0f896 2093 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2094 {
2095 char *string = ++input_line_pointer;
2096 int e = get_symbol_end ();
2097
2098 if (strcmp (string, "nojumps") == 0)
2099 no_cond_jump_promotion = 1;
2100 else if (strcmp (string, "jumps") == 0)
2101 ;
2102 else
2103 as_bad (_("no such architecture modifier: `%s'"), string);
2104
2105 *input_line_pointer = e;
2106 }
2107
e413e4e9
AM		 2108 demand_empty_rest_of_line ();
2109}
2110
8a9036a4
L		 2111enum bfd_architecture
2112i386_arch (void)
2113{
3632d14b 2114 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2115 {
2116 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2117 || flag_code != CODE_64BIT)
2118 as_fatal (_("Intel L1OM is 64bit ELF only"));
2119 return bfd_arch_l1om;
2120 }
2121 else
2122 return bfd_arch_i386;
2123}
2124
b9d79e03
JH		 2125unsigned long
2126i386_mach ()
2127{
2128 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2129 {
3632d14b 2130 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2131 {
2132 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2133 as_fatal (_("Intel L1OM is 64bit ELF only"));
2134 return bfd_mach_l1om;
2135 }
2136 else
2137 return bfd_mach_x86_64;
2138 }
b9d79e03
JH		 2139 else if (!strcmp (default_arch, "i386"))
2140 return bfd_mach_i386_i386;
2141 else
2142 as_fatal (_("Unknown architecture"));
2143}
b9d79e03 2144\f
252b5132
RH		 2145void
2146md_begin ()
2147{
2148 const char *hash_err;
2149
47926f60 2150 /* Initialize op_hash hash table. */
252b5132
RH		 2151 op_hash = hash_new ();
2152
2153 {
d3ce72d0 2154 const insn_template *optab;
29b0f896 2155 templates *core_optab;
252b5132 2156
47926f60
KH		 2157 /* Setup for loop. */
2158 optab = i386_optab;
252b5132
RH		 2159 core_optab = (templates *) xmalloc (sizeof (templates));
2160 core_optab->start = optab;
2161
2162 while (1)
2163 {
2164 ++optab;
2165 if (optab->name == NULL
2166 || strcmp (optab->name, (optab - 1)->name) != 0)
2167 {
2168 /* different name --> ship out current template list;
47926f60 2169 add to hash table; & begin anew. */
252b5132
RH		 2170 core_optab->end = optab;
2171 hash_err = hash_insert (op_hash,
2172 (optab - 1)->name,
5a49b8ac 2173 (void *) core_optab);
252b5132
RH		 2174 if (hash_err)
2175 {
252b5132
RH		 2176 as_fatal (_("Internal Error: Can't hash %s: %s"),
2177 (optab - 1)->name,
2178 hash_err);
2179 }
2180 if (optab->name == NULL)
2181 break;
2182 core_optab = (templates *) xmalloc (sizeof (templates));
2183 core_optab->start = optab;
2184 }
2185 }
2186 }
2187
47926f60 2188 /* Initialize reg_hash hash table. */
252b5132
RH		 2189 reg_hash = hash_new ();
2190 {
29b0f896 2191 const reg_entry *regtab;
c3fe08fa 2192 unsigned int regtab_size = i386_regtab_size;
252b5132 2193
c3fe08fa 2194 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2195 {
5a49b8ac 2196 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2197 if (hash_err)
3e73aa7c
JH		 2198 as_fatal (_("Internal Error: Can't hash %s: %s"),
2199 regtab->reg_name,
2200 hash_err);
252b5132
RH		 2201 }
2202 }
2203
47926f60 2204 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2205 {
29b0f896
AM		 2206 int c;
2207 char *p;
252b5132
RH		 2208
2209 for (c = 0; c < 256; c++)
2210 {
3882b010 2211 if (ISDIGIT (c))
252b5132
RH		 2212 {
2213 digit_chars[c] = c;
2214 mnemonic_chars[c] = c;
2215 register_chars[c] = c;
2216 operand_chars[c] = c;
2217 }
3882b010 2218 else if (ISLOWER (c))
252b5132
RH		 2219 {
2220 mnemonic_chars[c] = c;
2221 register_chars[c] = c;
2222 operand_chars[c] = c;
2223 }
3882b010 2224 else if (ISUPPER (c))
252b5132 2225 {
3882b010 2226 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2227 register_chars[c] = mnemonic_chars[c];
2228 operand_chars[c] = c;
2229 }
2230
3882b010 2231 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2232 identifier_chars[c] = c;
2233 else if (c >= 128)
2234 {
2235 identifier_chars[c] = c;
2236 operand_chars[c] = c;
2237 }
2238 }
2239
2240#ifdef LEX_AT
2241 identifier_chars['@'] = '@';
32137342
NC		 2242#endif
2243#ifdef LEX_QM
2244 identifier_chars['?'] = '?';
2245 operand_chars['?'] = '?';
252b5132 2246#endif
252b5132 2247 digit_chars['-'] = '-';
c0f3af97 2248 mnemonic_chars['_'] = '_';
791fe849 2249 mnemonic_chars['-'] = '-';
0003779b 2250 mnemonic_chars['.'] = '.';
252b5132
RH		 2251 identifier_chars['_'] = '_';
2252 identifier_chars['.'] = '.';
2253
2254 for (p = operand_special_chars; *p != '\0'; p++)
2255 operand_chars[(unsigned char) *p] = *p;
2256 }
2257
2258#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2259 if (IS_ELF)
252b5132
RH		 2260 {
2261 record_alignment (text_section, 2);
2262 record_alignment (data_section, 2);
2263 record_alignment (bss_section, 2);
2264 }
2265#endif
a4447b93
RH		 2266
2267 if (flag_code == CODE_64BIT)
2268 {
2269 x86_dwarf2_return_column = 16;
2270 x86_cie_data_alignment = -8;
2271 }
2272 else
2273 {
2274 x86_dwarf2_return_column = 8;
2275 x86_cie_data_alignment = -4;
2276 }
252b5132
RH		 2277}
2278
2279void
e3bb37b5 2280i386_print_statistics (FILE *file)
252b5132
RH		 2281{
2282 hash_print_statistics (file, "i386 opcode", op_hash);
2283 hash_print_statistics (file, "i386 register", reg_hash);
2284}
2285\f
252b5132
RH		 2286#ifdef DEBUG386
2287
ce8a8b2f 2288/* Debugging routines for md_assemble. */
d3ce72d0 2289static void pte (insn_template *);
40fb9820 2290static void pt (i386_operand_type);
e3bb37b5
L		 2291static void pe (expressionS *);
2292static void ps (symbolS *);
252b5132
RH		 2293
2294static void
e3bb37b5 2295pi (char *line, i386_insn *x)
252b5132 2296{
09f131f2 2297 unsigned int i;
252b5132
RH		 2298
2299 fprintf (stdout, "%s: template ", line);
2300 pte (&x->tm);
09f131f2
JH		 2301 fprintf (stdout, " address: base %s index %s scale %x\n",
2302 x->base_reg ? x->base_reg->reg_name : "none",
2303 x->index_reg ? x->index_reg->reg_name : "none",
2304 x->log2_scale_factor);
2305 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2306 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2307 fprintf (stdout, " sib: base %x index %x scale %x\n",
2308 x->sib.base, x->sib.index, x->sib.scale);
2309 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2310 (x->rex & REX_W) != 0,
2311 (x->rex & REX_R) != 0,
2312 (x->rex & REX_X) != 0,
2313 (x->rex & REX_B) != 0);
252b5132
RH		 2314 for (i = 0; i < x->operands; i++)
2315 {
2316 fprintf (stdout, " #%d: ", i + 1);
2317 pt (x->types[i]);
2318 fprintf (stdout, "\n");
40fb9820
L		 2319 if (x->types[i].bitfield.reg8
2320 || x->types[i].bitfield.reg16
2321 || x->types[i].bitfield.reg32
2322 || x->types[i].bitfield.reg64
2323 || x->types[i].bitfield.regmmx
2324 || x->types[i].bitfield.regxmm
c0f3af97 2325 || x->types[i].bitfield.regymm
40fb9820
L		 2326 || x->types[i].bitfield.sreg2
2327 || x->types[i].bitfield.sreg3
2328 || x->types[i].bitfield.control
2329 || x->types[i].bitfield.debug
2330 || x->types[i].bitfield.test)
520dc8e8 2331 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2332 if (operand_type_check (x->types[i], imm))
520dc8e8 2333 pe (x->op[i].imms);
40fb9820 2334 if (operand_type_check (x->types[i], disp))
520dc8e8 2335 pe (x->op[i].disps);
252b5132
RH		 2336 }
2337}
2338
2339static void
d3ce72d0 2340pte (insn_template *t)
252b5132 2341{
09f131f2 2342 unsigned int i;
252b5132 2343 fprintf (stdout, " %d operands ", t->operands);
47926f60 2344 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2345 if (t->extension_opcode != None)
2346 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2347 if (t->opcode_modifier.d)
252b5132 2348 fprintf (stdout, "D");
40fb9820 2349 if (t->opcode_modifier.w)
252b5132
RH		 2350 fprintf (stdout, "W");
2351 fprintf (stdout, "\n");
2352 for (i = 0; i < t->operands; i++)
2353 {
2354 fprintf (stdout, " #%d type ", i + 1);
2355 pt (t->operand_types[i]);
2356 fprintf (stdout, "\n");
2357 }
2358}
2359
2360static void
e3bb37b5 2361pe (expressionS *e)
252b5132 2362{
24eab124 2363 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2364 fprintf (stdout, " add_number %ld (%lx)\n",
2365 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2366 if (e->X_add_symbol)
2367 {
2368 fprintf (stdout, " add_symbol ");
2369 ps (e->X_add_symbol);
2370 fprintf (stdout, "\n");
2371 }
2372 if (e->X_op_symbol)
2373 {
2374 fprintf (stdout, " op_symbol ");
2375 ps (e->X_op_symbol);
2376 fprintf (stdout, "\n");
2377 }
2378}
2379
2380static void
e3bb37b5 2381ps (symbolS *s)
252b5132
RH		 2382{
2383 fprintf (stdout, "%s type %s%s",
2384 S_GET_NAME (s),
2385 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2386 segment_name (S_GET_SEGMENT (s)));
2387}
2388
7b81dfbb 2389static struct type_name
252b5132 2390 {
40fb9820
L		 2391 i386_operand_type mask;
2392 const char *name;
252b5132 2393 }
7b81dfbb 2394const type_names[] =
252b5132 2395{
40fb9820
L		 2396 { OPERAND_TYPE_REG8, "r8" },
2397 { OPERAND_TYPE_REG16, "r16" },
2398 { OPERAND_TYPE_REG32, "r32" },
2399 { OPERAND_TYPE_REG64, "r64" },
2400 { OPERAND_TYPE_IMM8, "i8" },
2401 { OPERAND_TYPE_IMM8, "i8s" },
2402 { OPERAND_TYPE_IMM16, "i16" },
2403 { OPERAND_TYPE_IMM32, "i32" },
2404 { OPERAND_TYPE_IMM32S, "i32s" },
2405 { OPERAND_TYPE_IMM64, "i64" },
2406 { OPERAND_TYPE_IMM1, "i1" },
2407 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2408 { OPERAND_TYPE_DISP8, "d8" },
2409 { OPERAND_TYPE_DISP16, "d16" },
2410 { OPERAND_TYPE_DISP32, "d32" },
2411 { OPERAND_TYPE_DISP32S, "d32s" },
2412 { OPERAND_TYPE_DISP64, "d64" },
2413 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2414 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2415 { OPERAND_TYPE_CONTROL, "control reg" },
2416 { OPERAND_TYPE_TEST, "test reg" },
2417 { OPERAND_TYPE_DEBUG, "debug reg" },
2418 { OPERAND_TYPE_FLOATREG, "FReg" },
2419 { OPERAND_TYPE_FLOATACC, "FAcc" },
2420 { OPERAND_TYPE_SREG2, "SReg2" },
2421 { OPERAND_TYPE_SREG3, "SReg3" },
2422 { OPERAND_TYPE_ACC, "Acc" },
2423 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2424 { OPERAND_TYPE_REGMMX, "rMMX" },
2425 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2426 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2427 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2428};
2429
2430static void
40fb9820 2431pt (i386_operand_type t)
252b5132 2432{
40fb9820 2433 unsigned int j;
c6fb90c8 2434 i386_operand_type a;
252b5132 2435
40fb9820 2436 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2437 {
2438 a = operand_type_and (t, type_names[j].mask);
0349dc08 2439 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2440 fprintf (stdout, "%s, ", type_names[j].name);
2441 }
252b5132
RH		 2442 fflush (stdout);
2443}
2444
2445#endif /* DEBUG386 */
2446\f
252b5132 2447static bfd_reloc_code_real_type
3956db08 2448reloc (unsigned int size,
64e74474
AM		 2449 int pcrel,
2450 int sign,
2451 bfd_reloc_code_real_type other)
252b5132 2452{
47926f60 2453 if (other != NO_RELOC)
3956db08
JB		 2454 {
2455 reloc_howto_type *reloc;
2456
2457 if (size == 8)
2458 switch (other)
2459 {
64e74474
AM		 2460 case BFD_RELOC_X86_64_GOT32:
2461 return BFD_RELOC_X86_64_GOT64;
2462 break;
2463 case BFD_RELOC_X86_64_PLTOFF64:
2464 return BFD_RELOC_X86_64_PLTOFF64;
2465 break;
2466 case BFD_RELOC_X86_64_GOTPC32:
2467 other = BFD_RELOC_X86_64_GOTPC64;
2468 break;
2469 case BFD_RELOC_X86_64_GOTPCREL:
2470 other = BFD_RELOC_X86_64_GOTPCREL64;
2471 break;
2472 case BFD_RELOC_X86_64_TPOFF32:
2473 other = BFD_RELOC_X86_64_TPOFF64;
2474 break;
2475 case BFD_RELOC_X86_64_DTPOFF32:
2476 other = BFD_RELOC_X86_64_DTPOFF64;
2477 break;
2478 default:
2479 break;
3956db08 2480 }
e05278af
JB		 2481
2482 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2483 if (size == 4 && flag_code != CODE_64BIT)
2484 sign = -1;
2485
3956db08
JB		 2486 reloc = bfd_reloc_type_lookup (stdoutput, other);
2487 if (!reloc)
2488 as_bad (_("unknown relocation (%u)"), other);
2489 else if (size != bfd_get_reloc_size (reloc))
2490 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2491 bfd_get_reloc_size (reloc),
2492 size);
2493 else if (pcrel && !reloc->pc_relative)
2494 as_bad (_("non-pc-relative relocation for pc-relative field"));
2495 else if ((reloc->complain_on_overflow == complain_overflow_signed
2496 && !sign)
2497 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2498 && sign > 0))
3956db08
JB		 2499 as_bad (_("relocated field and relocation type differ in signedness"));
2500 else
2501 return other;
2502 return NO_RELOC;
2503 }
252b5132
RH		 2504
2505 if (pcrel)
2506 {
3e73aa7c 2507 if (!sign)
3956db08 2508 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2509 switch (size)
2510 {
2511 case 1: return BFD_RELOC_8_PCREL;
2512 case 2: return BFD_RELOC_16_PCREL;
2513 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2514 case 8: return BFD_RELOC_64_PCREL;
252b5132 2515 }
3956db08 2516 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2517 }
2518 else
2519 {
3956db08 2520 if (sign > 0)
e5cb08ac 2521 switch (size)
3e73aa7c
JH		 2522 {
2523 case 4: return BFD_RELOC_X86_64_32S;
2524 }
2525 else
2526 switch (size)
2527 {
2528 case 1: return BFD_RELOC_8;
2529 case 2: return BFD_RELOC_16;
2530 case 4: return BFD_RELOC_32;
2531 case 8: return BFD_RELOC_64;
2532 }
3956db08
JB		 2533 as_bad (_("cannot do %s %u byte relocation"),
2534 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2535 }
2536
0cc9e1d3 2537 return NO_RELOC;
252b5132
RH		 2538}
2539
47926f60
KH		 2540/* Here we decide which fixups can be adjusted to make them relative to
2541 the beginning of the section instead of the symbol. Basically we need
2542 to make sure that the dynamic relocations are done correctly, so in
2543 some cases we force the original symbol to be used. */
2544
252b5132 2545int
e3bb37b5 2546tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2547{
6d249963 2548#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2549 if (!IS_ELF)
31312f95
AM		 2550 return 1;
2551
a161fe53
AM		 2552 /* Don't adjust pc-relative references to merge sections in 64-bit
2553 mode. */
2554 if (use_rela_relocations
2555 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2556 && fixP->fx_pcrel)
252b5132 2557 return 0;
31312f95 2558
8d01d9a9
AJ		 2559 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2560 and changed later by validate_fix. */
2561 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2562 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2563 return 0;
2564
ce8a8b2f 2565 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2566 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2567 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2568 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2569 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2570 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2571 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2572 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2573 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2574 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2575 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2576 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2577 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2578 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2579 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2580 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2581 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2582 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2583 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2584 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2585 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2586 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2587 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2588 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2589 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2590 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2591 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2592 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2593 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2594 return 0;
31312f95 2595#endif
252b5132
RH		 2596 return 1;
2597}
252b5132 2598
b4cac588 2599static int
e3bb37b5 2600intel_float_operand (const char *mnemonic)
252b5132 2601{
9306ca4a
JB		 2602 /* Note that the value returned is meaningful only for opcodes with (memory)
2603 operands, hence the code here is free to improperly handle opcodes that
2604 have no operands (for better performance and smaller code). */
2605
2606 if (mnemonic[0] != 'f')
2607 return 0; /* non-math */
2608
2609 switch (mnemonic[1])
2610 {
2611 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2612 the fs segment override prefix not currently handled because no
2613 call path can make opcodes without operands get here */
2614 case 'i':
2615 return 2 /* integer op */;
2616 case 'l':
2617 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2618 return 3; /* fldcw/fldenv */
2619 break;
2620 case 'n':
2621 if (mnemonic[2] != 'o' /* fnop */)
2622 return 3; /* non-waiting control op */
2623 break;
2624 case 'r':
2625 if (mnemonic[2] == 's')
2626 return 3; /* frstor/frstpm */
2627 break;
2628 case 's':
2629 if (mnemonic[2] == 'a')
2630 return 3; /* fsave */
2631 if (mnemonic[2] == 't')
2632 {
2633 switch (mnemonic[3])
2634 {
2635 case 'c': /* fstcw */
2636 case 'd': /* fstdw */
2637 case 'e': /* fstenv */
2638 case 's': /* fsts[gw] */
2639 return 3;
2640 }
2641 }
2642 break;
2643 case 'x':
2644 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2645 return 0; /* fxsave/fxrstor are not really math ops */
2646 break;
2647 }
252b5132 2648
9306ca4a 2649 return 1;
252b5132
RH		 2650}
2651
c0f3af97
L		 2652/* Build the VEX prefix. */
2653
2654static void
d3ce72d0 2655build_vex_prefix (const insn_template *t)
c0f3af97
L		 2656{
2657 unsigned int register_specifier;
2658 unsigned int implied_prefix;
2659 unsigned int vector_length;
2660
2661 /* Check register specifier. */
2662 if (i.vex.register_specifier)
2663 {
2664 register_specifier = i.vex.register_specifier->reg_num;
2665 if ((i.vex.register_specifier->reg_flags & RegRex))
2666 register_specifier += 8;
2667 register_specifier = ~register_specifier & 0xf;
2668 }
2669 else
2670 register_specifier = 0xf;
2671
fa99fab2
L		 2672 /* Use 2-byte VEX prefix by swappping destination and source
2673 operand. */
2674 if (!i.swap_operand
2675 && i.operands == i.reg_operands
2676 && i.tm.opcode_modifier.vex0f
2677 && i.tm.opcode_modifier.s
2678 && i.rex == REX_B)
2679 {
2680 unsigned int xchg = i.operands - 1;
2681 union i386_op temp_op;
2682 i386_operand_type temp_type;
2683
2684 temp_type = i.types[xchg];
2685 i.types[xchg] = i.types[0];
2686 i.types[0] = temp_type;
2687 temp_op = i.op[xchg];
2688 i.op[xchg] = i.op[0];
2689 i.op[0] = temp_op;
2690
9c2799c2 2691 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2692
2693 i.rex = REX_R;
2694 xchg = i.rm.regmem;
2695 i.rm.regmem = i.rm.reg;
2696 i.rm.reg = xchg;
2697
2698 /* Use the next insn. */
2699 i.tm = t[1];
2700 }
2701
2bf05e57 2702 vector_length = i.tm.opcode_modifier.vex == 2 ? 1 : 0;
c0f3af97
L		 2703
2704 switch ((i.tm.base_opcode >> 8) & 0xff)
2705 {
2706 case 0:
2707 implied_prefix = 0;
2708 break;
2709 case DATA_PREFIX_OPCODE:
2710 implied_prefix = 1;
2711 break;
2712 case REPE_PREFIX_OPCODE:
2713 implied_prefix = 2;
2714 break;
2715 case REPNE_PREFIX_OPCODE:
2716 implied_prefix = 3;
2717 break;
2718 default:
2719 abort ();
2720 }
2721
2722 /* Use 2-byte VEX prefix if possible. */
2723 if (i.tm.opcode_modifier.vex0f
2724 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2725 {
2726 /* 2-byte VEX prefix. */
2727 unsigned int r;
2728
2729 i.vex.length = 2;
2730 i.vex.bytes[0] = 0xc5;
2731
2732 /* Check the REX.R bit. */
2733 r = (i.rex & REX_R) ? 0 : 1;
2734 i.vex.bytes[1] = (r << 7
2735 | register_specifier << 3
2736 | vector_length << 2
2737 | implied_prefix);
2738 }
2739 else
2740 {
2741 /* 3-byte VEX prefix. */
2742 unsigned int m, w;
2743
f88c9eb0
SP		 2744 i.vex.length = 3;
2745 i.vex.bytes[0] = 0xc4;
2746
c0f3af97
L		 2747 if (i.tm.opcode_modifier.vex0f)
2748 m = 0x1;
2749 else if (i.tm.opcode_modifier.vex0f38)
2750 m = 0x2;
2751 else if (i.tm.opcode_modifier.vex0f3a)
2752 m = 0x3;
5dd85c99
SP		 2753 else if (i.tm.opcode_modifier.xop08)
2754 {
2755 m = 0x8;
2756 i.vex.bytes[0] = 0x8f;
2757 }
f88c9eb0
SP		 2758 else if (i.tm.opcode_modifier.xop09)
2759 {
2760 m = 0x9;
2761 i.vex.bytes[0] = 0x8f;
2762 }
2763 else if (i.tm.opcode_modifier.xop0a)
2764 {
2765 m = 0xa;
2766 i.vex.bytes[0] = 0x8f;
2767 }
c0f3af97
L		 2768 else
2769 abort ();
2770
c0f3af97
L		 2771 /* The high 3 bits of the second VEX byte are 1's compliment
2772 of RXB bits from REX. */
2773 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2774
2775 /* Check the REX.W bit. */
2776 w = (i.rex & REX_W) ? 1 : 0;
2777 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2778 {
2779 if (w)
2780 abort ();
2781
2782 if (i.tm.opcode_modifier.vexw1)
2783 w = 1;
2784 }
2785
2786 i.vex.bytes[2] = (w << 7
2787 | register_specifier << 3
2788 | vector_length << 2
2789 | implied_prefix);
2790 }
2791}
2792
65da13b5
L		 2793static void
2794process_immext (void)
2795{
2796 expressionS *exp;
2797
2798 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2799 {
1fed0ba1
L		 2800 /* SSE3 Instructions have the fixed operands with an opcode
2801 suffix which is coded in the same place as an 8-bit immediate
2802 field would be. Here we check those operands and remove them
2803 afterwards. */
65da13b5
L		 2804 unsigned int x;
2805
2806 for (x = 0; x < i.operands; x++)
2807 if (i.op[x].regs->reg_num != x)
2808 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2809 register_prefix, i.op[x].regs->reg_name, x + 1,
2810 i.tm.name);
2811
2812 i.operands = 0;
65da13b5
L		 2813 }
2814
c0f3af97 2815 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2816 which is coded in the same place as an 8-bit immediate field
2817 would be. Here we fake an 8-bit immediate operand from the
2818 opcode suffix stored in tm.extension_opcode.
2819
c1e679ec 2820 AVX instructions also use this encoding, for some of
c0f3af97 2821 3 argument instructions. */
65da13b5 2822
9c2799c2 2823 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2824 && (i.operands <= 2
2825 || (i.tm.opcode_modifier.vex
2826 && i.operands <= 4)));
65da13b5
L		 2827
2828 exp = &im_expressions[i.imm_operands++];
2829 i.op[i.operands].imms = exp;
2830 i.types[i.operands] = imm8;
2831 i.operands++;
2832 exp->X_op = O_constant;
2833 exp->X_add_number = i.tm.extension_opcode;
2834 i.tm.extension_opcode = None;
2835}
2836
252b5132
RH		 2837/* This is the guts of the machine-dependent assembler. LINE points to a
2838 machine dependent instruction. This function is supposed to emit
2839 the frags/bytes it assembles to. */
2840
2841void
65da13b5 2842md_assemble (char *line)
252b5132 2843{
40fb9820 2844 unsigned int j;
252b5132 2845 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2846 const insn_template *t;
252b5132 2847
47926f60 2848 /* Initialize globals. */
252b5132
RH		 2849 memset (&i, '\0', sizeof (i));
2850 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2851 i.reloc[j] = NO_RELOC;
252b5132
RH		 2852 memset (disp_expressions, '\0', sizeof (disp_expressions));
2853 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2854 save_stack_p = save_stack;
252b5132
RH		 2855
2856 /* First parse an instruction mnemonic & call i386_operand for the operands.
2857 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2858 start of a (possibly prefixed) mnemonic. */
252b5132 2859
29b0f896
AM		 2860 line = parse_insn (line, mnemonic);
2861 if (line == NULL)
2862 return;
252b5132 2863
29b0f896 2864 line = parse_operands (line, mnemonic);
ee86248c 2865 this_operand = -1;
29b0f896
AM		 2866 if (line == NULL)
2867 return;
252b5132 2868
29b0f896
AM		 2869 /* Now we've parsed the mnemonic into a set of templates, and have the
2870 operands at hand. */
2871
2872 /* All intel opcodes have reversed operands except for "bound" and
2873 "enter". We also don't reverse intersegment "jmp" and "call"
2874 instructions with 2 immediate operands so that the immediate segment
050dfa73 2875 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2876 if (intel_syntax
2877 && i.operands > 1
29b0f896 2878 && (strcmp (mnemonic, "bound") != 0)
30123838 2879 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2880 && !(operand_type_check (i.types[0], imm)
2881 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2882 swap_operands ();
2883
ec56d5c0
JB		 2884 /* The order of the immediates should be reversed
2885 for 2 immediates extrq and insertq instructions */
2886 if (i.imm_operands == 2
2887 && (strcmp (mnemonic, "extrq") == 0
2888 || strcmp (mnemonic, "insertq") == 0))
2889 swap_2_operands (0, 1);
2890
29b0f896
AM		 2891 if (i.imm_operands)
2892 optimize_imm ();
2893
b300c311
L		 2894 /* Don't optimize displacement for movabs since it only takes 64bit
2895 displacement. */
2896 if (i.disp_operands
2897 && (flag_code != CODE_64BIT
2898 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2899 optimize_disp ();
2900
2901 /* Next, we find a template that matches the given insn,
2902 making sure the overlap of the given operands types is consistent
2903 with the template operand types. */
252b5132 2904
fa99fab2 2905 if (!(t = match_template ()))
29b0f896 2906 return;
252b5132 2907
daf50ae7 2908 if (sse_check != sse_check_none
81f8a913 2909 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2910 && (i.tm.cpu_flags.bitfield.cpusse
2911 || i.tm.cpu_flags.bitfield.cpusse2
2912 || i.tm.cpu_flags.bitfield.cpusse3
2913 || i.tm.cpu_flags.bitfield.cpussse3
2914 || i.tm.cpu_flags.bitfield.cpusse4_1
2915 || i.tm.cpu_flags.bitfield.cpusse4_2))
2916 {
2917 (sse_check == sse_check_warning
2918 ? as_warn
2919 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2920 }
2921
321fd21e
L		 2922 /* Zap movzx and movsx suffix. The suffix has been set from
2923 "word ptr" or "byte ptr" on the source operand in Intel syntax
2924 or extracted from mnemonic in AT&T syntax. But we'll use
2925 the destination register to choose the suffix for encoding. */
2926 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2927 {
321fd21e
L		 2928 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2929 there is no suffix, the default will be byte extension. */
2930 if (i.reg_operands != 2
2931 && !i.suffix
7ab9ffdd 2932 && intel_syntax)
321fd21e
L		 2933 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2934
2935 i.suffix = 0;
cd61ebfe 2936 }
24eab124 2937
40fb9820 2938 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2939 if (!add_prefix (FWAIT_OPCODE))
2940 return;
252b5132 2941
c1ba0266
L		 2942 /* Check for lock without a lockable instruction. Destination operand
2943 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2944 if (i.prefix[LOCK_PREFIX]
2945 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2946 || i.mem_operands == 0
2947 || (i.tm.base_opcode != 0x86
2948 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2949 {
2950 as_bad (_("expecting lockable instruction after `lock'"));
2951 return;
2952 }
2953
29b0f896 2954 /* Check string instruction segment overrides. */
40fb9820 2955 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2956 {
2957 if (!check_string ())
5dd0794d 2958 return;
fc0763e6 2959 i.disp_operands = 0;
29b0f896 2960 }
5dd0794d 2961
29b0f896
AM		 2962 if (!process_suffix ())
2963 return;
e413e4e9 2964
bc0844ae
L		 2965 /* Update operand types. */
2966 for (j = 0; j < i.operands; j++)
2967 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2968
29b0f896
AM		 2969 /* Make still unresolved immediate matches conform to size of immediate
2970 given in i.suffix. */
2971 if (!finalize_imm ())
2972 return;
252b5132 2973
40fb9820 2974 if (i.types[0].bitfield.imm1)
29b0f896 2975 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2976
9afe6eb8
L		 2977 /* We only need to check those implicit registers for instructions
2978 with 3 operands or less. */
2979 if (i.operands <= 3)
2980 for (j = 0; j < i.operands; j++)
2981 if (i.types[j].bitfield.inoutportreg
2982 || i.types[j].bitfield.shiftcount
2983 || i.types[j].bitfield.acc
2984 || i.types[j].bitfield.floatacc)
2985 i.reg_operands--;
40fb9820 2986
c0f3af97
L		 2987 /* ImmExt should be processed after SSE2AVX. */
2988 if (!i.tm.opcode_modifier.sse2avx
2989 && i.tm.opcode_modifier.immext)
65da13b5 2990 process_immext ();
252b5132 2991
29b0f896
AM		 2992 /* For insns with operands there are more diddles to do to the opcode. */
2993 if (i.operands)
2994 {
2995 if (!process_operands ())
2996 return;
2997 }
40fb9820 2998 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2999 {
3000 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3001 as_warn (_("translating to `%sp'"), i.tm.name);
3002 }
252b5132 3003
c0f3af97 3004 if (i.tm.opcode_modifier.vex)
fa99fab2 3005 build_vex_prefix (t);
c0f3af97 3006
5dd85c99
SP		 3007 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3008 instructions may define INT_OPCODE as well, so avoid this corner
3009 case for those instructions that use MODRM. */
3010 if (i.tm.base_opcode == INT_OPCODE
3011 && i.op[0].imms->X_add_number == 3
3012 && !i.tm.opcode_modifier.modrm)
29b0f896
AM		 3013 {
3014 i.tm.base_opcode = INT3_OPCODE;
3015 i.imm_operands = 0;
3016 }
252b5132 3017
40fb9820
L		 3018 if ((i.tm.opcode_modifier.jump
3019 || i.tm.opcode_modifier.jumpbyte
3020 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3021 && i.op[0].disps->X_op == O_constant)
3022 {
3023 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3024 the absolute address given by the constant. Since ix86 jumps and
3025 calls are pc relative, we need to generate a reloc. */
3026 i.op[0].disps->X_add_symbol = &abs_symbol;
3027 i.op[0].disps->X_op = O_symbol;
3028 }
252b5132 3029
40fb9820 3030 if (i.tm.opcode_modifier.rex64)
161a04f6 3031 i.rex |= REX_W;
252b5132 3032
29b0f896
AM		 3033 /* For 8 bit registers we need an empty rex prefix. Also if the
3034 instruction already has a prefix, we need to convert old
3035 registers to new ones. */
773f551c 3036
40fb9820 3037 if ((i.types[0].bitfield.reg8
29b0f896 3038 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3039 || (i.types[1].bitfield.reg8
29b0f896 3040 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3041 || ((i.types[0].bitfield.reg8
3042 || i.types[1].bitfield.reg8)
29b0f896
AM		 3043 && i.rex != 0))
3044 {
3045 int x;
726c5dcd 3046
29b0f896
AM		 3047 i.rex |= REX_OPCODE;
3048 for (x = 0; x < 2; x++)
3049 {
3050 /* Look for 8 bit operand that uses old registers. */
40fb9820 3051 if (i.types[x].bitfield.reg8
29b0f896 3052 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3053 {
29b0f896
AM		 3054 /* In case it is "hi" register, give up. */
3055 if (i.op[x].regs->reg_num > 3)
a540244d 3056 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3057 "instruction requiring REX prefix."),
a540244d 3058 register_prefix, i.op[x].regs->reg_name);
773f551c 3059
29b0f896
AM		 3060 /* Otherwise it is equivalent to the extended register.
3061 Since the encoding doesn't change this is merely
3062 cosmetic cleanup for debug output. */
3063
3064 i.op[x].regs = i.op[x].regs + 8;
773f551c 3065 }
29b0f896
AM		 3066 }
3067 }
773f551c 3068
7ab9ffdd 3069 if (i.rex != 0)
29b0f896
AM		 3070 add_prefix (REX_OPCODE | i.rex);
3071
3072 /* We are ready to output the insn. */
3073 output_insn ();
3074}
3075
3076static char *
e3bb37b5 3077parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3078{
3079 char *l = line;
3080 char *token_start = l;
3081 char *mnem_p;
5c6af06e 3082 int supported;
d3ce72d0 3083 const insn_template *t;
b6169b20 3084 char *dot_p = NULL;
29b0f896
AM		 3085
3086 /* Non-zero if we found a prefix only acceptable with string insns. */
3087 const char *expecting_string_instruction = NULL;
45288df1 3088
29b0f896
AM		 3089 while (1)
3090 {
3091 mnem_p = mnemonic;
3092 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3093 {
b6169b20
L		 3094 if (*mnem_p == '.')
3095 dot_p = mnem_p;
29b0f896
AM		 3096 mnem_p++;
3097 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3098 {
29b0f896
AM		 3099 as_bad (_("no such instruction: `%s'"), token_start);
3100 return NULL;
3101 }
3102 l++;
3103 }
3104 if (!is_space_char (*l)
3105 && *l != END_OF_INSN
e44823cf
JB		 3106 && (intel_syntax
3107 || (*l != PREFIX_SEPARATOR
3108 && *l != ',')))
29b0f896
AM		 3109 {
3110 as_bad (_("invalid character %s in mnemonic"),
3111 output_invalid (*l));
3112 return NULL;
3113 }
3114 if (token_start == l)
3115 {
e44823cf 3116 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3117 as_bad (_("expecting prefix; got nothing"));
3118 else
3119 as_bad (_("expecting mnemonic; got nothing"));
3120 return NULL;
3121 }
45288df1 3122
29b0f896 3123 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3124 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3125
29b0f896
AM		 3126 if (*l != END_OF_INSN
3127 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3128 && current_templates
40fb9820 3129 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3130 {
c6fb90c8 3131 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3132 {
3133 as_bad ((flag_code != CODE_64BIT
3134 ? _("`%s' is only supported in 64-bit mode")
3135 : _("`%s' is not supported in 64-bit mode")),
3136 current_templates->start->name);
3137 return NULL;
3138 }
29b0f896
AM		 3139 /* If we are in 16-bit mode, do not allow addr16 or data16.
3140 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3141 if ((current_templates->start->opcode_modifier.size16
3142 || current_templates->start->opcode_modifier.size32)
29b0f896 3143 && flag_code != CODE_64BIT
40fb9820 3144 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3145 ^ (flag_code == CODE_16BIT)))
3146 {
3147 as_bad (_("redundant %s prefix"),
3148 current_templates->start->name);
3149 return NULL;
45288df1 3150 }
29b0f896
AM		 3151 /* Add prefix, checking for repeated prefixes. */
3152 switch (add_prefix (current_templates->start->base_opcode))
3153 {
c32fa91d 3154 case PREFIX_EXIST:
29b0f896 3155 return NULL;
c32fa91d 3156 case PREFIX_REP:
29b0f896
AM		 3157 expecting_string_instruction = current_templates->start->name;
3158 break;
c32fa91d
L		 3159 default:
3160 break;
29b0f896
AM		 3161 }
3162 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3163 token_start = ++l;
3164 }
3165 else
3166 break;
3167 }
45288df1 3168
30a55f88 3169 if (!current_templates)
b6169b20 3170 {
30a55f88
L		 3171 /* Check if we should swap operand in encoding. */
3172 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3173 i.swap_operand = 1;
3174 else
3175 goto check_suffix;
3176 mnem_p = dot_p;
3177 *dot_p = '\0';
d3ce72d0 3178 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3179 }
3180
29b0f896
AM		 3181 if (!current_templates)
3182 {
b6169b20 3183check_suffix:
29b0f896
AM		 3184 /* See if we can get a match by trimming off a suffix. */
3185 switch (mnem_p[-1])
3186 {
3187 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3188 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3189 i.suffix = SHORT_MNEM_SUFFIX;
3190 else
29b0f896
AM		 3191 case BYTE_MNEM_SUFFIX:
3192 case QWORD_MNEM_SUFFIX:
3193 i.suffix = mnem_p[-1];
3194 mnem_p[-1] = '\0';
d3ce72d0
NC		 3195 current_templates = (const templates *) hash_find (op_hash,
3196 mnemonic);
29b0f896
AM		 3197 break;
3198 case SHORT_MNEM_SUFFIX:
3199 case LONG_MNEM_SUFFIX:
3200 if (!intel_syntax)
3201 {
3202 i.suffix = mnem_p[-1];
3203 mnem_p[-1] = '\0';
d3ce72d0
NC		 3204 current_templates = (const templates *) hash_find (op_hash,
3205 mnemonic);
29b0f896
AM		 3206 }
3207 break;
252b5132 3208
29b0f896
AM		 3209 /* Intel Syntax. */
3210 case 'd':
3211 if (intel_syntax)
3212 {
9306ca4a 3213 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3214 i.suffix = SHORT_MNEM_SUFFIX;
3215 else
3216 i.suffix = LONG_MNEM_SUFFIX;
3217 mnem_p[-1] = '\0';
d3ce72d0
NC		 3218 current_templates = (const templates *) hash_find (op_hash,
3219 mnemonic);
29b0f896
AM		 3220 }
3221 break;
3222 }
3223 if (!current_templates)
3224 {
3225 as_bad (_("no such instruction: `%s'"), token_start);
3226 return NULL;
3227 }
3228 }
252b5132 3229
40fb9820
L		 3230 if (current_templates->start->opcode_modifier.jump
3231 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3232 {
3233 /* Check for a branch hint. We allow ",pt" and ",pn" for
3234 predict taken and predict not taken respectively.
3235 I'm not sure that branch hints actually do anything on loop
3236 and jcxz insns (JumpByte) for current Pentium4 chips. They
3237 may work in the future and it doesn't hurt to accept them
3238 now. */
3239 if (l[0] == ',' && l[1] == 'p')
3240 {
3241 if (l[2] == 't')
3242 {
3243 if (!add_prefix (DS_PREFIX_OPCODE))
3244 return NULL;
3245 l += 3;
3246 }
3247 else if (l[2] == 'n')
3248 {
3249 if (!add_prefix (CS_PREFIX_OPCODE))
3250 return NULL;
3251 l += 3;
3252 }
3253 }
3254 }
3255 /* Any other comma loses. */
3256 if (*l == ',')
3257 {
3258 as_bad (_("invalid character %s in mnemonic"),
3259 output_invalid (*l));
3260 return NULL;
3261 }
252b5132 3262
29b0f896 3263 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3264 supported = 0;
3265 for (t = current_templates->start; t < current_templates->end; ++t)
3266 {
c0f3af97
L		 3267 supported |= cpu_flags_match (t);
3268 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3269 goto skip;
5c6af06e 3270 }
3629bb00 3271
c0f3af97 3272 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3273 {
3274 as_bad (flag_code == CODE_64BIT
3275 ? _("`%s' is not supported in 64-bit mode")
3276 : _("`%s' is only supported in 64-bit mode"),
3277 current_templates->start->name);
3278 return NULL;
3279 }
c0f3af97 3280 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3281 {
3629bb00 3282 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3283 current_templates->start->name,
41aacd83 3284 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3285 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3286 return NULL;
29b0f896 3287 }
3629bb00
L		 3288
3289skip:
3290 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3291 && (flag_code != CODE_16BIT))
29b0f896
AM		 3292 {
3293 as_warn (_("use .code16 to ensure correct addressing mode"));
3294 }
252b5132 3295
29b0f896 3296 /* Check for rep/repne without a string instruction. */
f41bbced 3297 if (expecting_string_instruction)
29b0f896 3298 {
f41bbced
JB		 3299 static templates override;
3300
3301 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3302 if (t->opcode_modifier.isstring)
f41bbced
JB		 3303 break;
3304 if (t >= current_templates->end)
3305 {
3306 as_bad (_("expecting string instruction after `%s'"),
64e74474 3307 expecting_string_instruction);
f41bbced
JB		 3308 return NULL;
3309 }
3310 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3311 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3312 break;
3313 override.end = t;
3314 current_templates = &override;
29b0f896 3315 }
252b5132 3316
29b0f896
AM		 3317 return l;
3318}
252b5132 3319
29b0f896 3320static char *
e3bb37b5 3321parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3322{
3323 char *token_start;
3138f287 3324
29b0f896
AM		 3325 /* 1 if operand is pending after ','. */
3326 unsigned int expecting_operand = 0;
252b5132 3327
29b0f896
AM		 3328 /* Non-zero if operand parens not balanced. */
3329 unsigned int paren_not_balanced;
3330
3331 while (*l != END_OF_INSN)
3332 {
3333 /* Skip optional white space before operand. */
3334 if (is_space_char (*l))
3335 ++l;
3336 if (!is_operand_char (*l) && *l != END_OF_INSN)
3337 {
3338 as_bad (_("invalid character %s before operand %d"),
3339 output_invalid (*l),
3340 i.operands + 1);
3341 return NULL;
3342 }
3343 token_start = l; /* after white space */
3344 paren_not_balanced = 0;
3345 while (paren_not_balanced || *l != ',')
3346 {
3347 if (*l == END_OF_INSN)
3348 {
3349 if (paren_not_balanced)
3350 {
3351 if (!intel_syntax)
3352 as_bad (_("unbalanced parenthesis in operand %d."),
3353 i.operands + 1);
3354 else
3355 as_bad (_("unbalanced brackets in operand %d."),
3356 i.operands + 1);
3357 return NULL;
3358 }
3359 else
3360 break; /* we are done */
3361 }
3362 else if (!is_operand_char (*l) && !is_space_char (*l))
3363 {
3364 as_bad (_("invalid character %s in operand %d"),
3365 output_invalid (*l),
3366 i.operands + 1);
3367 return NULL;
3368 }
3369 if (!intel_syntax)
3370 {
3371 if (*l == '(')
3372 ++paren_not_balanced;
3373 if (*l == ')')
3374 --paren_not_balanced;
3375 }
3376 else
3377 {
3378 if (*l == '[')
3379 ++paren_not_balanced;
3380 if (*l == ']')
3381 --paren_not_balanced;
3382 }
3383 l++;
3384 }
3385 if (l != token_start)
3386 { /* Yes, we've read in another operand. */
3387 unsigned int operand_ok;
3388 this_operand = i.operands++;
7d5e4556 3389 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3390 if (i.operands > MAX_OPERANDS)
3391 {
3392 as_bad (_("spurious operands; (%d operands/instruction max)"),
3393 MAX_OPERANDS);
3394 return NULL;
3395 }
3396 /* Now parse operand adding info to 'i' as we go along. */
3397 END_STRING_AND_SAVE (l);
3398
3399 if (intel_syntax)
3400 operand_ok =
3401 i386_intel_operand (token_start,
3402 intel_float_operand (mnemonic));
3403 else
a7619375 3404 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3405
3406 RESTORE_END_STRING (l);
3407 if (!operand_ok)
3408 return NULL;
3409 }
3410 else
3411 {
3412 if (expecting_operand)
3413 {
3414 expecting_operand_after_comma:
3415 as_bad (_("expecting operand after ','; got nothing"));
3416 return NULL;
3417 }
3418 if (*l == ',')
3419 {
3420 as_bad (_("expecting operand before ','; got nothing"));
3421 return NULL;
3422 }
3423 }
7f3f1ea2 3424
29b0f896
AM		 3425 /* Now *l must be either ',' or END_OF_INSN. */
3426 if (*l == ',')
3427 {
3428 if (*++l == END_OF_INSN)
3429 {
3430 /* Just skip it, if it's \n complain. */
3431 goto expecting_operand_after_comma;
3432 }
3433 expecting_operand = 1;
3434 }
3435 }
3436 return l;
3437}
7f3f1ea2 3438
050dfa73 3439static void
4d456e3d 3440swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3441{
3442 union i386_op temp_op;
40fb9820 3443 i386_operand_type temp_type;
050dfa73 3444 enum bfd_reloc_code_real temp_reloc;
4eed87de 3445
050dfa73
MM		 3446 temp_type = i.types[xchg2];
3447 i.types[xchg2] = i.types[xchg1];
3448 i.types[xchg1] = temp_type;
3449 temp_op = i.op[xchg2];
3450 i.op[xchg2] = i.op[xchg1];
3451 i.op[xchg1] = temp_op;
3452 temp_reloc = i.reloc[xchg2];
3453 i.reloc[xchg2] = i.reloc[xchg1];
3454 i.reloc[xchg1] = temp_reloc;
3455}
3456
29b0f896 3457static void
e3bb37b5 3458swap_operands (void)
29b0f896 3459{
b7c61d9a 3460 switch (i.operands)
050dfa73 3461 {
c0f3af97 3462 case 5:
b7c61d9a 3463 case 4:
4d456e3d 3464 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3465 case 3:
3466 case 2:
4d456e3d 3467 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3468 break;
3469 default:
3470 abort ();
29b0f896 3471 }
29b0f896
AM		 3472
3473 if (i.mem_operands == 2)
3474 {
3475 const seg_entry *temp_seg;
3476 temp_seg = i.seg[0];
3477 i.seg[0] = i.seg[1];
3478 i.seg[1] = temp_seg;
3479 }
3480}
252b5132 3481
29b0f896
AM		 3482/* Try to ensure constant immediates are represented in the smallest
3483 opcode possible. */
3484static void
e3bb37b5 3485optimize_imm (void)
29b0f896
AM		 3486{
3487 char guess_suffix = 0;
3488 int op;
252b5132 3489
29b0f896
AM		 3490 if (i.suffix)
3491 guess_suffix = i.suffix;
3492 else if (i.reg_operands)
3493 {
3494 /* Figure out a suffix from the last register operand specified.
3495 We can't do this properly yet, ie. excluding InOutPortReg,
3496 but the following works for instructions with immediates.
3497 In any case, we can't set i.suffix yet. */
3498 for (op = i.operands; --op >= 0;)
40fb9820 3499 if (i.types[op].bitfield.reg8)
7ab9ffdd 3500 {
40fb9820
L		 3501 guess_suffix = BYTE_MNEM_SUFFIX;
3502 break;
3503 }
3504 else if (i.types[op].bitfield.reg16)
252b5132 3505 {
40fb9820
L		 3506 guess_suffix = WORD_MNEM_SUFFIX;
3507 break;
3508 }
3509 else if (i.types[op].bitfield.reg32)
3510 {
3511 guess_suffix = LONG_MNEM_SUFFIX;
3512 break;
3513 }
3514 else if (i.types[op].bitfield.reg64)
3515 {
3516 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3517 break;
252b5132 3518 }
29b0f896
AM		 3519 }
3520 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3521 guess_suffix = WORD_MNEM_SUFFIX;
3522
3523 for (op = i.operands; --op >= 0;)
40fb9820 3524 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3525 {
3526 switch (i.op[op].imms->X_op)
252b5132 3527 {
29b0f896
AM		 3528 case O_constant:
3529 /* If a suffix is given, this operand may be shortened. */
3530 switch (guess_suffix)
252b5132 3531 {
29b0f896 3532 case LONG_MNEM_SUFFIX:
40fb9820
L		 3533 i.types[op].bitfield.imm32 = 1;
3534 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3535 break;
3536 case WORD_MNEM_SUFFIX:
40fb9820
L		 3537 i.types[op].bitfield.imm16 = 1;
3538 i.types[op].bitfield.imm32 = 1;
3539 i.types[op].bitfield.imm32s = 1;
3540 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3541 break;
3542 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3543 i.types[op].bitfield.imm8 = 1;
3544 i.types[op].bitfield.imm8s = 1;
3545 i.types[op].bitfield.imm16 = 1;
3546 i.types[op].bitfield.imm32 = 1;
3547 i.types[op].bitfield.imm32s = 1;
3548 i.types[op].bitfield.imm64 = 1;
29b0f896 3549 break;
252b5132 3550 }
252b5132 3551
29b0f896
AM		 3552 /* If this operand is at most 16 bits, convert it
3553 to a signed 16 bit number before trying to see
3554 whether it will fit in an even smaller size.
3555 This allows a 16-bit operand such as $0xffe0 to
3556 be recognised as within Imm8S range. */
40fb9820 3557 if ((i.types[op].bitfield.imm16)
29b0f896 3558 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3559 {
29b0f896
AM		 3560 i.op[op].imms->X_add_number =
3561 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3562 }
40fb9820 3563 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3564 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3565 == 0))
3566 {
3567 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3568 ^ ((offsetT) 1 << 31))
3569 - ((offsetT) 1 << 31));
3570 }
40fb9820 3571 i.types[op]
c6fb90c8
L		 3572 = operand_type_or (i.types[op],
3573 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3574
29b0f896
AM		 3575 /* We must avoid matching of Imm32 templates when 64bit
3576 only immediate is available. */
3577 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3578 i.types[op].bitfield.imm32 = 0;
29b0f896 3579 break;
252b5132 3580
29b0f896
AM		 3581 case O_absent:
3582 case O_register:
3583 abort ();
3584
3585 /* Symbols and expressions. */
3586 default:
9cd96992
JB		 3587 /* Convert symbolic operand to proper sizes for matching, but don't
3588 prevent matching a set of insns that only supports sizes other
3589 than those matching the insn suffix. */
3590 {
40fb9820 3591 i386_operand_type mask, allowed;
d3ce72d0 3592 const insn_template *t;
9cd96992 3593
0dfbf9d7
L		 3594 operand_type_set (&mask, 0);
3595 operand_type_set (&allowed, 0);
40fb9820 3596
4eed87de
AM		 3597 for (t = current_templates->start;
3598 t < current_templates->end;
3599 ++t)
c6fb90c8
L		 3600 allowed = operand_type_or (allowed,
3601 t->operand_types[op]);
9cd96992
JB		 3602 switch (guess_suffix)
3603 {
3604 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3605 mask.bitfield.imm64 = 1;
3606 mask.bitfield.imm32s = 1;
9cd96992
JB		 3607 break;
3608 case LONG_MNEM_SUFFIX:
40fb9820 3609 mask.bitfield.imm32 = 1;
9cd96992
JB		 3610 break;
3611 case WORD_MNEM_SUFFIX:
40fb9820 3612 mask.bitfield.imm16 = 1;
9cd96992
JB		 3613 break;
3614 case BYTE_MNEM_SUFFIX:
40fb9820 3615 mask.bitfield.imm8 = 1;
9cd96992
JB		 3616 break;
3617 default:
9cd96992
JB		 3618 break;
3619 }
c6fb90c8 3620 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3621 if (!operand_type_all_zero (&allowed))
c6fb90c8 3622 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3623 }
29b0f896 3624 break;
252b5132 3625 }
29b0f896
AM		 3626 }
3627}
47926f60 3628
29b0f896
AM		 3629/* Try to use the smallest displacement type too. */
3630static void
e3bb37b5 3631optimize_disp (void)
29b0f896
AM		 3632{
3633 int op;
3e73aa7c 3634
29b0f896 3635 for (op = i.operands; --op >= 0;)
40fb9820 3636 if (operand_type_check (i.types[op], disp))
252b5132 3637 {
b300c311 3638 if (i.op[op].disps->X_op == O_constant)
252b5132 3639 {
b300c311 3640 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3641
40fb9820 3642 if (i.types[op].bitfield.disp16
b300c311
L		 3643 && (disp & ~(offsetT) 0xffff) == 0)
3644 {
3645 /* If this operand is at most 16 bits, convert
3646 to a signed 16 bit number and don't use 64bit
3647 displacement. */
3648 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3649 i.types[op].bitfield.disp64 = 0;
b300c311 3650 }
40fb9820 3651 if (i.types[op].bitfield.disp32
b300c311
L		 3652 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3653 {
3654 /* If this operand is at most 32 bits, convert
3655 to a signed 32 bit number and don't use 64bit
3656 displacement. */
3657 disp &= (((offsetT) 2 << 31) - 1);
3658 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3659 i.types[op].bitfield.disp64 = 0;
b300c311 3660 }
40fb9820 3661 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3662 {
40fb9820
L		 3663 i.types[op].bitfield.disp8 = 0;
3664 i.types[op].bitfield.disp16 = 0;
3665 i.types[op].bitfield.disp32 = 0;
3666 i.types[op].bitfield.disp32s = 0;
3667 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3668 i.op[op].disps = 0;
3669 i.disp_operands--;
3670 }
3671 else if (flag_code == CODE_64BIT)
3672 {
3673 if (fits_in_signed_long (disp))
28a9d8f5 3674 {
40fb9820
L		 3675 i.types[op].bitfield.disp64 = 0;
3676 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3677 }
0e1147d9
L		 3678 if (i.prefix[ADDR_PREFIX]
3679 && fits_in_unsigned_long (disp))
40fb9820 3680 i.types[op].bitfield.disp32 = 1;
b300c311 3681 }
40fb9820
L		 3682 if ((i.types[op].bitfield.disp32
3683 || i.types[op].bitfield.disp32s
3684 || i.types[op].bitfield.disp16)
b300c311 3685 && fits_in_signed_byte (disp))
40fb9820 3686 i.types[op].bitfield.disp8 = 1;
252b5132 3687 }
67a4f2b7
AO		 3688 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3689 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3690 {
3691 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3692 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3693 i.types[op].bitfield.disp8 = 0;
3694 i.types[op].bitfield.disp16 = 0;
3695 i.types[op].bitfield.disp32 = 0;
3696 i.types[op].bitfield.disp32s = 0;
3697 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3698 }
3699 else
b300c311 3700 /* We only support 64bit displacement on constants. */
40fb9820 3701 i.types[op].bitfield.disp64 = 0;
252b5132 3702 }
29b0f896
AM		 3703}
3704
d3ce72d0 3705static const insn_template *
e3bb37b5 3706match_template (void)
29b0f896
AM		 3707{
3708 /* Points to template once we've found it. */
d3ce72d0 3709 const insn_template *t;
40fb9820 3710 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3711 i386_operand_type overlap4;
29b0f896 3712 unsigned int found_reverse_match;
40fb9820
L		 3713 i386_opcode_modifier suffix_check;
3714 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3715 int addr_prefix_disp;
a5c311ca 3716 unsigned int j;
3629bb00 3717 unsigned int found_cpu_match;
45664ddb 3718 unsigned int check_register;
29b0f896 3719
c0f3af97
L		 3720#if MAX_OPERANDS != 5
3721# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3722#endif
3723
29b0f896 3724 found_reverse_match = 0;
539e75ad 3725 addr_prefix_disp = -1;
40fb9820
L		 3726
3727 memset (&suffix_check, 0, sizeof (suffix_check));
3728 if (i.suffix == BYTE_MNEM_SUFFIX)
3729 suffix_check.no_bsuf = 1;
3730 else if (i.suffix == WORD_MNEM_SUFFIX)
3731 suffix_check.no_wsuf = 1;
3732 else if (i.suffix == SHORT_MNEM_SUFFIX)
3733 suffix_check.no_ssuf = 1;
3734 else if (i.suffix == LONG_MNEM_SUFFIX)
3735 suffix_check.no_lsuf = 1;
3736 else if (i.suffix == QWORD_MNEM_SUFFIX)
3737 suffix_check.no_qsuf = 1;
3738 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3739 suffix_check.no_ldsuf = 1;
29b0f896 3740
45aa61fe 3741 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3742 {
539e75ad
L		 3743 addr_prefix_disp = -1;
3744
29b0f896
AM		 3745 /* Must have right number of operands. */
3746 if (i.operands != t->operands)
3747 continue;
3748
50aecf8c 3749 /* Check processor support. */
c0f3af97
L		 3750 found_cpu_match = (cpu_flags_match (t)
3751 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3752 if (!found_cpu_match)
3753 continue;
3754
e1d4d893
L		 3755 /* Check old gcc support. */
3756 if (!old_gcc && t->opcode_modifier.oldgcc)
3757 continue;
3758
3759 /* Check AT&T mnemonic. */
3760 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3761 continue;
3762
5c07affc
L		 3763 /* Check AT&T syntax Intel syntax. */
3764 if ((intel_syntax && t->opcode_modifier.attsyntax)
3765 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3766 continue;
3767
20592a94 3768 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3769 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3770 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3771 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3772 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3773 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3774 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3775 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3776 continue;
3777
5c07affc 3778 if (!operand_size_match (t))
7d5e4556 3779 continue;
539e75ad 3780
5c07affc
L		 3781 for (j = 0; j < MAX_OPERANDS; j++)
3782 operand_types[j] = t->operand_types[j];
3783
45aa61fe
AM		 3784 /* In general, don't allow 64-bit operands in 32-bit mode. */
3785 if (i.suffix == QWORD_MNEM_SUFFIX
3786 && flag_code != CODE_64BIT
3787 && (intel_syntax
40fb9820 3788 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3789 && !intel_float_operand (t->name))
3790 : intel_float_operand (t->name) != 2)
40fb9820 3791 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3792 && !operand_types[0].bitfield.regxmm
3793 && !operand_types[0].bitfield.regymm)
40fb9820 3794 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3795 && !!operand_types[t->operands > 1].bitfield.regxmm
3796 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3797 && (t->base_opcode != 0x0fc7
3798 || t->extension_opcode != 1 /* cmpxchg8b */))
3799 continue;
3800
192dc9c6
JB		 3801 /* In general, don't allow 32-bit operands on pre-386. */
3802 else if (i.suffix == LONG_MNEM_SUFFIX
3803 && !cpu_arch_flags.bitfield.cpui386
3804 && (intel_syntax
3805 ? (!t->opcode_modifier.ignoresize
3806 && !intel_float_operand (t->name))
3807 : intel_float_operand (t->name) != 2)
3808 && ((!operand_types[0].bitfield.regmmx
3809 && !operand_types[0].bitfield.regxmm)
3810 || (!operand_types[t->operands > 1].bitfield.regmmx
3811 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3812 continue;
3813
29b0f896 3814 /* Do not verify operands when there are none. */
50aecf8c 3815 else
29b0f896 3816 {
c6fb90c8 3817 if (!t->operands)
2dbab7d5
L		 3818 /* We've found a match; break out of loop. */
3819 break;
29b0f896 3820 }
252b5132 3821
539e75ad
L		 3822 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3823 into Disp32/Disp16/Disp32 operand. */
3824 if (i.prefix[ADDR_PREFIX] != 0)
3825 {
40fb9820 3826 /* There should be only one Disp operand. */
539e75ad
L		 3827 switch (flag_code)
3828 {
3829 case CODE_16BIT:
40fb9820
L		 3830 for (j = 0; j < MAX_OPERANDS; j++)
3831 {
3832 if (operand_types[j].bitfield.disp16)
3833 {
3834 addr_prefix_disp = j;
3835 operand_types[j].bitfield.disp32 = 1;
3836 operand_types[j].bitfield.disp16 = 0;
3837 break;
3838 }
3839 }
539e75ad
L		 3840 break;
3841 case CODE_32BIT:
40fb9820
L		 3842 for (j = 0; j < MAX_OPERANDS; j++)
3843 {
3844 if (operand_types[j].bitfield.disp32)
3845 {
3846 addr_prefix_disp = j;
3847 operand_types[j].bitfield.disp32 = 0;
3848 operand_types[j].bitfield.disp16 = 1;
3849 break;
3850 }
3851 }
539e75ad
L		 3852 break;
3853 case CODE_64BIT:
40fb9820
L		 3854 for (j = 0; j < MAX_OPERANDS; j++)
3855 {
3856 if (operand_types[j].bitfield.disp64)
3857 {
3858 addr_prefix_disp = j;
3859 operand_types[j].bitfield.disp64 = 0;
3860 operand_types[j].bitfield.disp32 = 1;
3861 break;
3862 }
3863 }
539e75ad
L		 3864 break;
3865 }
539e75ad
L		 3866 }
3867
45664ddb
L		 3868 /* We check register size only if size of operands can be
3869 encoded the canonical way. */
3870 check_register = t->opcode_modifier.w;
c6fb90c8 3871 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3872 switch (t->operands)
3873 {
3874 case 1:
40fb9820 3875 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3876 continue;
3877 break;
3878 case 2:
8b38ad71
L		 3879 /* xchg %eax, %eax is a special case. It is an aliase for nop
3880 only in 32bit mode and we can use opcode 0x90. In 64bit
3881 mode, we can't use 0x90 for xchg %eax, %eax since it should
3882 zero-extend %eax to %rax. */
3883 if (flag_code == CODE_64BIT
3884 && t->base_opcode == 0x90
0dfbf9d7
L		 3885 && operand_type_equal (&i.types [0], &acc32)
3886 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3887 continue;
b6169b20
L		 3888 if (i.swap_operand)
3889 {
3890 /* If we swap operand in encoding, we either match
3891 the next one or reverse direction of operands. */
3892 if (t->opcode_modifier.s)
3893 continue;
3894 else if (t->opcode_modifier.d)
3895 goto check_reverse;
3896 }
3897
29b0f896 3898 case 3:
fa99fab2
L		 3899 /* If we swap operand in encoding, we match the next one. */
3900 if (i.swap_operand && t->opcode_modifier.s)
3901 continue;
f48ff2ae 3902 case 4:
c0f3af97 3903 case 5:
c6fb90c8 3904 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3905 if (!operand_type_match (overlap0, i.types[0])
3906 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3907 || (check_register
3908 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3909 operand_types[0],
3910 overlap1, i.types[1],
3911 operand_types[1])))
29b0f896
AM		 3912 {
3913 /* Check if other direction is valid ... */
40fb9820 3914 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3915 continue;
3916
b6169b20 3917check_reverse:
29b0f896 3918 /* Try reversing direction of operands. */
c6fb90c8
L		 3919 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3920 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3921 if (!operand_type_match (overlap0, i.types[0])
3922 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3923 || (check_register
3924 && !operand_type_register_match (overlap0,
3925 i.types[0],
3926 operand_types[1],
3927 overlap1,
3928 i.types[1],
3929 operand_types[0])))
29b0f896
AM		 3930 {
3931 /* Does not match either direction. */
3932 continue;
3933 }
3934 /* found_reverse_match holds which of D or FloatDR
3935 we've found. */
40fb9820 3936 if (t->opcode_modifier.d)
8a2ed489 3937 found_reverse_match = Opcode_D;
40fb9820 3938 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3939 found_reverse_match = Opcode_FloatD;
3940 else
3941 found_reverse_match = 0;
40fb9820 3942 if (t->opcode_modifier.floatr)
8a2ed489 3943 found_reverse_match |= Opcode_FloatR;
29b0f896 3944 }
f48ff2ae 3945 else
29b0f896 3946 {
f48ff2ae 3947 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3948 switch (t->operands)
3949 {
c0f3af97
L		 3950 case 5:
3951 overlap4 = operand_type_and (i.types[4],
3952 operand_types[4]);
d1cbb4db 3953 case 4:
c6fb90c8
L		 3954 overlap3 = operand_type_and (i.types[3],
3955 operand_types[3]);
d1cbb4db 3956 case 3:
c6fb90c8
L		 3957 overlap2 = operand_type_and (i.types[2],
3958 operand_types[2]);
d1cbb4db
L		 3959 break;
3960 }
29b0f896 3961
f48ff2ae
L		 3962 switch (t->operands)
3963 {
c0f3af97
L		 3964 case 5:
3965 if (!operand_type_match (overlap4, i.types[4])
3966 || !operand_type_register_match (overlap3,
3967 i.types[3],
3968 operand_types[3],
3969 overlap4,
3970 i.types[4],
3971 operand_types[4]))
3972 continue;
f48ff2ae 3973 case 4:
40fb9820 3974 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3975 || (check_register
3976 && !operand_type_register_match (overlap2,
3977 i.types[2],
3978 operand_types[2],
3979 overlap3,
3980 i.types[3],
3981 operand_types[3])))
f48ff2ae
L		 3982 continue;
3983 case 3:
3984 /* Here we make use of the fact that there are no
3985 reverse match 3 operand instructions, and all 3
3986 operand instructions only need to be checked for
3987 register consistency between operands 2 and 3. */
40fb9820 3988 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3989 || (check_register
3990 && !operand_type_register_match (overlap1,
3991 i.types[1],
3992 operand_types[1],
3993 overlap2,
3994 i.types[2],
3995 operand_types[2])))
f48ff2ae
L		 3996 continue;
3997 break;
3998 }
29b0f896 3999 }
f48ff2ae 4000 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4001 slip through to break. */
4002 }
3629bb00 4003 if (!found_cpu_match)
29b0f896
AM		 4004 {
4005 found_reverse_match = 0;
4006 continue;
4007 }
c0f3af97 4008
29b0f896
AM		 4009 /* We've found a match; break out of loop. */
4010 break;
4011 }
4012
4013 if (t == current_templates->end)
4014 {
4015 /* We found no match. */
95f283e8
L		 4016 if (intel_syntax)
4017 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4018 current_templates->start->name);
4019 else
4020 as_bad (_("suffix or operands invalid for `%s'"),
4021 current_templates->start->name);
fa99fab2 4022 return NULL;
29b0f896 4023 }
252b5132 4024
29b0f896
AM		 4025 if (!quiet_warnings)
4026 {
4027 if (!intel_syntax
40fb9820
L		 4028 && (i.types[0].bitfield.jumpabsolute
4029 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4030 {
4031 as_warn (_("indirect %s without `*'"), t->name);
4032 }
4033
40fb9820
L		 4034 if (t->opcode_modifier.isprefix
4035 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4036 {
4037 /* Warn them that a data or address size prefix doesn't
4038 affect assembly of the next line of code. */
4039 as_warn (_("stand-alone `%s' prefix"), t->name);
4040 }
4041 }
4042
4043 /* Copy the template we found. */
4044 i.tm = *t;
539e75ad
L		 4045
4046 if (addr_prefix_disp != -1)
4047 i.tm.operand_types[addr_prefix_disp]
4048 = operand_types[addr_prefix_disp];
4049
29b0f896
AM		 4050 if (found_reverse_match)
4051 {
4052 /* If we found a reverse match we must alter the opcode
4053 direction bit. found_reverse_match holds bits to change
4054 (different for int & float insns). */
4055
4056 i.tm.base_opcode ^= found_reverse_match;
4057
539e75ad
L		 4058 i.tm.operand_types[0] = operand_types[1];
4059 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4060 }
4061
fa99fab2 4062 return t;
29b0f896
AM		 4063}
4064
4065static int
e3bb37b5 4066check_string (void)
29b0f896 4067{
40fb9820
L		 4068 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4069 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4070 {
4071 if (i.seg[0] != NULL && i.seg[0] != &es)
4072 {
a87af027 4073 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4074 i.tm.name,
a87af027
JB		 4075 mem_op + 1,
4076 register_prefix);
29b0f896
AM		 4077 return 0;
4078 }
4079 /* There's only ever one segment override allowed per instruction.
4080 This instruction possibly has a legal segment override on the
4081 second operand, so copy the segment to where non-string
4082 instructions store it, allowing common code. */
4083 i.seg[0] = i.seg[1];
4084 }
40fb9820 4085 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4086 {
4087 if (i.seg[1] != NULL && i.seg[1] != &es)
4088 {
a87af027 4089 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4090 i.tm.name,
a87af027
JB		 4091 mem_op + 2,
4092 register_prefix);
29b0f896
AM		 4093 return 0;
4094 }
4095 }
4096 return 1;
4097}
4098
4099static int
543613e9 4100process_suffix (void)
29b0f896
AM		 4101{
4102 /* If matched instruction specifies an explicit instruction mnemonic
4103 suffix, use it. */
40fb9820
L		 4104 if (i.tm.opcode_modifier.size16)
4105 i.suffix = WORD_MNEM_SUFFIX;
4106 else if (i.tm.opcode_modifier.size32)
4107 i.suffix = LONG_MNEM_SUFFIX;
4108 else if (i.tm.opcode_modifier.size64)
4109 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4110 else if (i.reg_operands)
4111 {
4112 /* If there's no instruction mnemonic suffix we try to invent one
4113 based on register operands. */
4114 if (!i.suffix)
4115 {
4116 /* We take i.suffix from the last register operand specified,
4117 Destination register type is more significant than source
381d071f
L		 4118 register type. crc32 in SSE4.2 prefers source register
4119 type. */
4120 if (i.tm.base_opcode == 0xf20f38f1)
4121 {
40fb9820
L		 4122 if (i.types[0].bitfield.reg16)
4123 i.suffix = WORD_MNEM_SUFFIX;
4124 else if (i.types[0].bitfield.reg32)
4125 i.suffix = LONG_MNEM_SUFFIX;
4126 else if (i.types[0].bitfield.reg64)
4127 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4128 }
9344ff29 4129 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4130 {
40fb9820 4131 if (i.types[0].bitfield.reg8)
20592a94
L		 4132 i.suffix = BYTE_MNEM_SUFFIX;
4133 }
381d071f
L		 4134
4135 if (!i.suffix)
4136 {
4137 int op;
4138
20592a94
L		 4139 if (i.tm.base_opcode == 0xf20f38f1
4140 || i.tm.base_opcode == 0xf20f38f0)
4141 {
4142 /* We have to know the operand size for crc32. */
4143 as_bad (_("ambiguous memory operand size for `%s`"),
4144 i.tm.name);
4145 return 0;
4146 }
4147
381d071f 4148 for (op = i.operands; --op >= 0;)
40fb9820 4149 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4150 {
40fb9820
L		 4151 if (i.types[op].bitfield.reg8)
4152 {
4153 i.suffix = BYTE_MNEM_SUFFIX;
4154 break;
4155 }
4156 else if (i.types[op].bitfield.reg16)
4157 {
4158 i.suffix = WORD_MNEM_SUFFIX;
4159 break;
4160 }
4161 else if (i.types[op].bitfield.reg32)
4162 {
4163 i.suffix = LONG_MNEM_SUFFIX;
4164 break;
4165 }
4166 else if (i.types[op].bitfield.reg64)
4167 {
4168 i.suffix = QWORD_MNEM_SUFFIX;
4169 break;
4170 }
381d071f
L		 4171 }
4172 }
29b0f896
AM		 4173 }
4174 else if (i.suffix == BYTE_MNEM_SUFFIX)
4175 {
4176 if (!check_byte_reg ())
4177 return 0;
4178 }
4179 else if (i.suffix == LONG_MNEM_SUFFIX)
4180 {
4181 if (!check_long_reg ())
4182 return 0;
4183 }
4184 else if (i.suffix == QWORD_MNEM_SUFFIX)
4185 {
955e1e6a
L		 4186 if (intel_syntax
4187 && i.tm.opcode_modifier.ignoresize
4188 && i.tm.opcode_modifier.no_qsuf)
4189 i.suffix = 0;
4190 else if (!check_qword_reg ())
29b0f896
AM		 4191 return 0;
4192 }
4193 else if (i.suffix == WORD_MNEM_SUFFIX)
4194 {
4195 if (!check_word_reg ())
4196 return 0;
4197 }
c0f3af97
L		 4198 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4199 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4200 {
c0f3af97 4201 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4202 should check if it is a valid suffix. */
4203 }
40fb9820 4204 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4205 /* Do nothing if the instruction is going to ignore the prefix. */
4206 ;
4207 else
4208 abort ();
4209 }
40fb9820 4210 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4211 && !i.suffix
4212 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4213 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4214 {
4215 i.suffix = stackop_size;
4216 }
9306ca4a
JB		 4217 else if (intel_syntax
4218 && !i.suffix
40fb9820
L		 4219 && (i.tm.operand_types[0].bitfield.jumpabsolute
4220 || i.tm.opcode_modifier.jumpbyte
4221 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4222 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4223 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4224 {
4225 switch (flag_code)
4226 {
4227 case CODE_64BIT:
40fb9820 4228 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4229 {
4230 i.suffix = QWORD_MNEM_SUFFIX;
4231 break;
4232 }
4233 case CODE_32BIT:
40fb9820 4234 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4235 i.suffix = LONG_MNEM_SUFFIX;
4236 break;
4237 case CODE_16BIT:
40fb9820 4238 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4239 i.suffix = WORD_MNEM_SUFFIX;
4240 break;
4241 }
4242 }
252b5132 4243
9306ca4a 4244 if (!i.suffix)
29b0f896 4245 {
9306ca4a
JB		 4246 if (!intel_syntax)
4247 {
40fb9820 4248 if (i.tm.opcode_modifier.w)
9306ca4a 4249 {
4eed87de
AM		 4250 as_bad (_("no instruction mnemonic suffix given and "
4251 "no register operands; can't size instruction"));
9306ca4a
JB		 4252 return 0;
4253 }
4254 }
4255 else
4256 {
40fb9820 4257 unsigned int suffixes;
7ab9ffdd 4258
40fb9820
L		 4259 suffixes = !i.tm.opcode_modifier.no_bsuf;
4260 if (!i.tm.opcode_modifier.no_wsuf)
4261 suffixes |= 1 << 1;
4262 if (!i.tm.opcode_modifier.no_lsuf)
4263 suffixes |= 1 << 2;
fc4adea1 4264 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4265 suffixes |= 1 << 3;
4266 if (!i.tm.opcode_modifier.no_ssuf)
4267 suffixes |= 1 << 4;
4268 if (!i.tm.opcode_modifier.no_qsuf)
4269 suffixes |= 1 << 5;
4270
4271 /* There are more than suffix matches. */
4272 if (i.tm.opcode_modifier.w
9306ca4a 4273 || ((suffixes & (suffixes - 1))
40fb9820
L		 4274 && !i.tm.opcode_modifier.defaultsize
4275 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4276 {
4277 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4278 return 0;
4279 }
4280 }
29b0f896 4281 }
252b5132 4282
9306ca4a
JB		 4283 /* Change the opcode based on the operand size given by i.suffix;
4284 We don't need to change things for byte insns. */
4285
582d5edd
L		 4286 if (i.suffix
4287 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4288 && i.suffix != XMMWORD_MNEM_SUFFIX
4289 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4290 {
4291 /* It's not a byte, select word/dword operation. */
40fb9820 4292 if (i.tm.opcode_modifier.w)
29b0f896 4293 {
40fb9820 4294 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4295 i.tm.base_opcode |= 8;
4296 else
4297 i.tm.base_opcode |= 1;
4298 }
0f3f3d8b 4299
29b0f896
AM		 4300 /* Now select between word & dword operations via the operand
4301 size prefix, except for instructions that will ignore this
4302 prefix anyway. */
ca61edf2 4303 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4304 {
ca61edf2
L		 4305 /* The address size override prefix changes the size of the
4306 first operand. */
40fb9820
L		 4307 if ((flag_code == CODE_32BIT
4308 && i.op->regs[0].reg_type.bitfield.reg16)
4309 || (flag_code != CODE_32BIT
4310 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4311 if (!add_prefix (ADDR_PREFIX_OPCODE))
4312 return 0;
4313 }
4314 else if (i.suffix != QWORD_MNEM_SUFFIX
4315 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4316 && !i.tm.opcode_modifier.ignoresize
4317 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4318 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4319 || (flag_code == CODE_64BIT
40fb9820 4320 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4321 {
4322 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4323
40fb9820 4324 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4325 prefix = ADDR_PREFIX_OPCODE;
252b5132 4326
29b0f896
AM		 4327 if (!add_prefix (prefix))
4328 return 0;
24eab124 4329 }
252b5132 4330
29b0f896
AM		 4331 /* Set mode64 for an operand. */
4332 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4333 && flag_code == CODE_64BIT
40fb9820 4334 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4335 {
4336 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4337 need rex64. cmpxchg8b is also a special case. */
4338 if (! (i.operands == 2
4339 && i.tm.base_opcode == 0x90
4340 && i.tm.extension_opcode == None
0dfbf9d7
L		 4341 && operand_type_equal (&i.types [0], &acc64)
4342 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4343 && ! (i.operands == 1
4344 && i.tm.base_opcode == 0xfc7
4345 && i.tm.extension_opcode == 1
40fb9820
L		 4346 && !operand_type_check (i.types [0], reg)
4347 && operand_type_check (i.types [0], anymem)))
f6bee062 4348 i.rex |= REX_W;
46e883c5 4349 }
3e73aa7c 4350
29b0f896
AM		 4351 /* Size floating point instruction. */
4352 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4353 if (i.tm.opcode_modifier.floatmf)
543613e9 4354 i.tm.base_opcode ^= 4;
29b0f896 4355 }
7ecd2f8b 4356
29b0f896
AM		 4357 return 1;
4358}
3e73aa7c 4359
29b0f896 4360static int
543613e9 4361check_byte_reg (void)
29b0f896
AM		 4362{
4363 int op;
543613e9 4364
29b0f896
AM		 4365 for (op = i.operands; --op >= 0;)
4366 {
4367 /* If this is an eight bit register, it's OK. If it's the 16 or
4368 32 bit version of an eight bit register, we will just use the
4369 low portion, and that's OK too. */
40fb9820 4370 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4371 continue;
4372
ca61edf2
L		 4373 /* Don't generate this warning if not needed. */
4374 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4375 continue;
4376
9344ff29
L		 4377 /* crc32 doesn't generate this warning. */
4378 if (i.tm.base_opcode == 0xf20f38f0)
4379 continue;
4380
40fb9820
L		 4381 if ((i.types[op].bitfield.reg16
4382 || i.types[op].bitfield.reg32
4383 || i.types[op].bitfield.reg64)
4384 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4385 {
4386 /* Prohibit these changes in the 64bit mode, since the
4387 lowering is more complicated. */
4388 if (flag_code == CODE_64BIT
40fb9820 4389 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4390 {
2ca3ace5
L		 4391 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4392 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4393 i.suffix);
4394 return 0;
4395 }
4396#if REGISTER_WARNINGS
4397 if (!quiet_warnings
40fb9820 4398 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4399 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4400 register_prefix,
40fb9820 4401 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4402 ? REGNAM_AL - REGNAM_AX
4403 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4404 register_prefix,
29b0f896
AM		 4405 i.op[op].regs->reg_name,
4406 i.suffix);
4407#endif
4408 continue;
4409 }
4410 /* Any other register is bad. */
40fb9820
L		 4411 if (i.types[op].bitfield.reg16
4412 || i.types[op].bitfield.reg32
4413 || i.types[op].bitfield.reg64
4414 || i.types[op].bitfield.regmmx
4415 || i.types[op].bitfield.regxmm
c0f3af97 4416 || i.types[op].bitfield.regymm
40fb9820
L		 4417 || i.types[op].bitfield.sreg2
4418 || i.types[op].bitfield.sreg3
4419 || i.types[op].bitfield.control
4420 || i.types[op].bitfield.debug
4421 || i.types[op].bitfield.test
4422 || i.types[op].bitfield.floatreg
4423 || i.types[op].bitfield.floatacc)
29b0f896 4424 {
a540244d
L		 4425 as_bad (_("`%s%s' not allowed with `%s%c'"),
4426 register_prefix,
29b0f896
AM		 4427 i.op[op].regs->reg_name,
4428 i.tm.name,
4429 i.suffix);
4430 return 0;
4431 }
4432 }
4433 return 1;
4434}
4435
4436static int
e3bb37b5 4437check_long_reg (void)
29b0f896
AM		 4438{
4439 int op;
4440
4441 for (op = i.operands; --op >= 0;)
4442 /* Reject eight bit registers, except where the template requires
4443 them. (eg. movzb) */
40fb9820
L		 4444 if (i.types[op].bitfield.reg8
4445 && (i.tm.operand_types[op].bitfield.reg16
4446 || i.tm.operand_types[op].bitfield.reg32
4447 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4448 {
a540244d
L		 4449 as_bad (_("`%s%s' not allowed with `%s%c'"),
4450 register_prefix,
29b0f896
AM		 4451 i.op[op].regs->reg_name,
4452 i.tm.name,
4453 i.suffix);
4454 return 0;
4455 }
4456 /* Warn if the e prefix on a general reg is missing. */
4457 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4458 && i.types[op].bitfield.reg16
4459 && (i.tm.operand_types[op].bitfield.reg32
4460 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4461 {
4462 /* Prohibit these changes in the 64bit mode, since the
4463 lowering is more complicated. */
4464 if (flag_code == CODE_64BIT)
252b5132 4465 {
2ca3ace5
L		 4466 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4467 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4468 i.suffix);
4469 return 0;
252b5132 4470 }
29b0f896
AM		 4471#if REGISTER_WARNINGS
4472 else
a540244d
L		 4473 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4474 register_prefix,
29b0f896 4475 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4476 register_prefix,
29b0f896
AM		 4477 i.op[op].regs->reg_name,
4478 i.suffix);
4479#endif
252b5132 4480 }
29b0f896 4481 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4482 else if (i.types[op].bitfield.reg64
4483 && (i.tm.operand_types[op].bitfield.reg32
4484 || i.tm.operand_types[op].bitfield.acc))
252b5132 4485 {
34828aad 4486 if (intel_syntax
ca61edf2 4487 && i.tm.opcode_modifier.toqword
40fb9820 4488 && !i.types[0].bitfield.regxmm)
34828aad 4489 {
ca61edf2 4490 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4491 i.suffix = QWORD_MNEM_SUFFIX;
4492 }
4493 else
4494 {
4495 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4496 register_prefix, i.op[op].regs->reg_name,
4497 i.suffix);
4498 return 0;
4499 }
29b0f896
AM		 4500 }
4501 return 1;
4502}
252b5132 4503
29b0f896 4504static int
e3bb37b5 4505check_qword_reg (void)
29b0f896
AM		 4506{
4507 int op;
252b5132 4508
29b0f896
AM		 4509 for (op = i.operands; --op >= 0; )
4510 /* Reject eight bit registers, except where the template requires
4511 them. (eg. movzb) */
40fb9820
L		 4512 if (i.types[op].bitfield.reg8
4513 && (i.tm.operand_types[op].bitfield.reg16
4514 || i.tm.operand_types[op].bitfield.reg32
4515 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4516 {
a540244d
L		 4517 as_bad (_("`%s%s' not allowed with `%s%c'"),
4518 register_prefix,
29b0f896
AM		 4519 i.op[op].regs->reg_name,
4520 i.tm.name,
4521 i.suffix);
4522 return 0;
4523 }
4524 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4525 else if ((i.types[op].bitfield.reg16
4526 || i.types[op].bitfield.reg32)
4527 && (i.tm.operand_types[op].bitfield.reg32
4528 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4529 {
4530 /* Prohibit these changes in the 64bit mode, since the
4531 lowering is more complicated. */
34828aad 4532 if (intel_syntax
ca61edf2 4533 && i.tm.opcode_modifier.todword
40fb9820 4534 && !i.types[0].bitfield.regxmm)
34828aad 4535 {
ca61edf2 4536 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4537 i.suffix = LONG_MNEM_SUFFIX;
4538 }
4539 else
4540 {
4541 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4542 register_prefix, i.op[op].regs->reg_name,
4543 i.suffix);
4544 return 0;
4545 }
252b5132 4546 }
29b0f896
AM		 4547 return 1;
4548}
252b5132 4549
29b0f896 4550static int
e3bb37b5 4551check_word_reg (void)
29b0f896
AM		 4552{
4553 int op;
4554 for (op = i.operands; --op >= 0;)
4555 /* Reject eight bit registers, except where the template requires
4556 them. (eg. movzb) */
40fb9820
L		 4557 if (i.types[op].bitfield.reg8
4558 && (i.tm.operand_types[op].bitfield.reg16
4559 || i.tm.operand_types[op].bitfield.reg32
4560 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4561 {
a540244d
L		 4562 as_bad (_("`%s%s' not allowed with `%s%c'"),
4563 register_prefix,
29b0f896
AM		 4564 i.op[op].regs->reg_name,
4565 i.tm.name,
4566 i.suffix);
4567 return 0;
4568 }
4569 /* Warn if the e prefix on a general reg is present. */
4570 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4571 && i.types[op].bitfield.reg32
4572 && (i.tm.operand_types[op].bitfield.reg16
4573 || i.tm.operand_types[op].bitfield.acc))
252b5132 4574 {
29b0f896
AM		 4575 /* Prohibit these changes in the 64bit mode, since the
4576 lowering is more complicated. */
4577 if (flag_code == CODE_64BIT)
252b5132 4578 {
2ca3ace5
L		 4579 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4580 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4581 i.suffix);
4582 return 0;
252b5132 4583 }
29b0f896
AM		 4584 else
4585#if REGISTER_WARNINGS
a540244d
L		 4586 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4587 register_prefix,
29b0f896 4588 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4589 register_prefix,
29b0f896
AM		 4590 i.op[op].regs->reg_name,
4591 i.suffix);
4592#endif
4593 }
4594 return 1;
4595}
252b5132 4596
29b0f896 4597static int
40fb9820 4598update_imm (unsigned int j)
29b0f896 4599{
bc0844ae 4600 i386_operand_type overlap = i.types[j];
40fb9820
L		 4601 if ((overlap.bitfield.imm8
4602 || overlap.bitfield.imm8s
4603 || overlap.bitfield.imm16
4604 || overlap.bitfield.imm32
4605 || overlap.bitfield.imm32s
4606 || overlap.bitfield.imm64)
0dfbf9d7
L		 4607 && !operand_type_equal (&overlap, &imm8)
4608 && !operand_type_equal (&overlap, &imm8s)
4609 && !operand_type_equal (&overlap, &imm16)
4610 && !operand_type_equal (&overlap, &imm32)
4611 && !operand_type_equal (&overlap, &imm32s)
4612 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4613 {
4614 if (i.suffix)
4615 {
40fb9820
L		 4616 i386_operand_type temp;
4617
0dfbf9d7 4618 operand_type_set (&temp, 0);
7ab9ffdd 4619 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4620 {
4621 temp.bitfield.imm8 = overlap.bitfield.imm8;
4622 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4623 }
4624 else if (i.suffix == WORD_MNEM_SUFFIX)
4625 temp.bitfield.imm16 = overlap.bitfield.imm16;
4626 else if (i.suffix == QWORD_MNEM_SUFFIX)
4627 {
4628 temp.bitfield.imm64 = overlap.bitfield.imm64;
4629 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4630 }
4631 else
4632 temp.bitfield.imm32 = overlap.bitfield.imm32;
4633 overlap = temp;
29b0f896 4634 }
0dfbf9d7
L		 4635 else if (operand_type_equal (&overlap, &imm16_32_32s)
4636 || operand_type_equal (&overlap, &imm16_32)
4637 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4638 {
40fb9820 4639 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4640 overlap = imm16;
40fb9820 4641 else
65da13b5 4642 overlap = imm32s;
29b0f896 4643 }
0dfbf9d7
L		 4644 if (!operand_type_equal (&overlap, &imm8)
4645 && !operand_type_equal (&overlap, &imm8s)
4646 && !operand_type_equal (&overlap, &imm16)
4647 && !operand_type_equal (&overlap, &imm32)
4648 && !operand_type_equal (&overlap, &imm32s)
4649 && !operand_type_equal (&overlap, &imm64))
29b0f896 4650 {
4eed87de
AM		 4651 as_bad (_("no instruction mnemonic suffix given; "
4652 "can't determine immediate size"));
29b0f896
AM		 4653 return 0;
4654 }
4655 }
40fb9820 4656 i.types[j] = overlap;
29b0f896 4657
40fb9820
L		 4658 return 1;
4659}
4660
4661static int
4662finalize_imm (void)
4663{
bc0844ae 4664 unsigned int j, n;
29b0f896 4665
bc0844ae
L		 4666 /* Update the first 2 immediate operands. */
4667 n = i.operands > 2 ? 2 : i.operands;
4668 if (n)
4669 {
4670 for (j = 0; j < n; j++)
4671 if (update_imm (j) == 0)
4672 return 0;
40fb9820 4673
bc0844ae
L		 4674 /* The 3rd operand can't be immediate operand. */
4675 gas_assert (operand_type_check (i.types[2], imm) == 0);
4676 }
29b0f896
AM		 4677
4678 return 1;
4679}
4680
c0f3af97
L		 4681static int
4682bad_implicit_operand (int xmm)
4683{
4684 const char *reg = xmm ? "xmm0" : "ymm0";
4685 if (intel_syntax)
4686 as_bad (_("the last operand of `%s' must be `%s%s'"),
4687 i.tm.name, register_prefix, reg);
4688 else
4689 as_bad (_("the first operand of `%s' must be `%s%s'"),
4690 i.tm.name, register_prefix, reg);
4691 return 0;
4692}
4693
29b0f896 4694static int
e3bb37b5 4695process_operands (void)
29b0f896
AM		 4696{
4697 /* Default segment register this instruction will use for memory
4698 accesses. 0 means unknown. This is only for optimizing out
4699 unnecessary segment overrides. */
4700 const seg_entry *default_seg = 0;
4701
c0f3af97
L		 4702 if (i.tm.opcode_modifier.sse2avx
4703 && (i.tm.opcode_modifier.vexnds
4704 || i.tm.opcode_modifier.vexndd))
29b0f896 4705 {
c0f3af97
L		 4706 unsigned int dup = i.operands;
4707 unsigned int dest = dup - 1;
9fcfb3d7
L		 4708 unsigned int j;
4709
c0f3af97 4710 /* The destination must be an xmm register. */
9c2799c2 4711 gas_assert (i.reg_operands
7ab9ffdd
L		 4712 && MAX_OPERANDS > dup
4713 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4714
4715 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4716 {
c0f3af97 4717 /* The first operand is implicit and must be xmm0. */
9c2799c2 4718 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4719 if (i.op[0].regs->reg_num != 0)
4720 return bad_implicit_operand (1);
4721
4722 if (i.tm.opcode_modifier.vex3sources)
4723 {
4724 /* Keep xmm0 for instructions with VEX prefix and 3
4725 sources. */
4726 goto duplicate;
4727 }
e2ec9d29 4728 else
c0f3af97
L		 4729 {
4730 /* We remove the first xmm0 and keep the number of
4731 operands unchanged, which in fact duplicates the
4732 destination. */
4733 for (j = 1; j < i.operands; j++)
4734 {
4735 i.op[j - 1] = i.op[j];
4736 i.types[j - 1] = i.types[j];
4737 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4738 }
4739 }
4740 }
4741 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4742 {
9c2799c2 4743 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4744 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4745
4746 /* Add the implicit xmm0 for instructions with VEX prefix
4747 and 3 sources. */
4748 for (j = i.operands; j > 0; j--)
4749 {
4750 i.op[j] = i.op[j - 1];
4751 i.types[j] = i.types[j - 1];
4752 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4753 }
4754 i.op[0].regs
4755 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4756 i.types[0] = regxmm;
c0f3af97
L		 4757 i.tm.operand_types[0] = regxmm;
4758
4759 i.operands += 2;
4760 i.reg_operands += 2;
4761 i.tm.operands += 2;
4762
4763 dup++;
4764 dest++;
4765 i.op[dup] = i.op[dest];
4766 i.types[dup] = i.types[dest];
4767 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4768 }
c0f3af97
L		 4769 else
4770 {
4771duplicate:
4772 i.operands++;
4773 i.reg_operands++;
4774 i.tm.operands++;
4775
4776 i.op[dup] = i.op[dest];
4777 i.types[dup] = i.types[dest];
4778 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4779 }
4780
4781 if (i.tm.opcode_modifier.immext)
4782 process_immext ();
4783 }
4784 else if (i.tm.opcode_modifier.firstxmm0)
4785 {
4786 unsigned int j;
4787
4788 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4789 gas_assert (i.reg_operands
7ab9ffdd
L		 4790 && (operand_type_equal (&i.types[0], &regxmm)
4791 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4792 if (i.op[0].regs->reg_num != 0)
4793 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4794
4795 for (j = 1; j < i.operands; j++)
4796 {
4797 i.op[j - 1] = i.op[j];
4798 i.types[j - 1] = i.types[j];
4799
4800 /* We need to adjust fields in i.tm since they are used by
4801 build_modrm_byte. */
4802 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4803 }
4804
e2ec9d29
L		 4805 i.operands--;
4806 i.reg_operands--;
e2ec9d29
L		 4807 i.tm.operands--;
4808 }
4809 else if (i.tm.opcode_modifier.regkludge)
4810 {
4811 /* The imul $imm, %reg instruction is converted into
4812 imul $imm, %reg, %reg, and the clr %reg instruction
4813 is converted into xor %reg, %reg. */
4814
4815 unsigned int first_reg_op;
4816
4817 if (operand_type_check (i.types[0], reg))
4818 first_reg_op = 0;
4819 else
4820 first_reg_op = 1;
4821 /* Pretend we saw the extra register operand. */
9c2799c2 4822 gas_assert (i.reg_operands == 1
7ab9ffdd 4823 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4824 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4825 i.types[first_reg_op + 1] = i.types[first_reg_op];
4826 i.operands++;
4827 i.reg_operands++;
29b0f896
AM		 4828 }
4829
40fb9820 4830 if (i.tm.opcode_modifier.shortform)
29b0f896 4831 {
40fb9820
L		 4832 if (i.types[0].bitfield.sreg2
4833 || i.types[0].bitfield.sreg3)
29b0f896 4834 {
4eed87de
AM		 4835 if (i.tm.base_opcode == POP_SEG_SHORT
4836 && i.op[0].regs->reg_num == 1)
29b0f896 4837 {
a87af027 4838 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4839 return 0;
29b0f896 4840 }
4eed87de
AM		 4841 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4842 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4843 i.rex |= REX_B;
4eed87de
AM		 4844 }
4845 else
4846 {
7ab9ffdd 4847 /* The register or float register operand is in operand
85f10a01 4848 0 or 1. */
40fb9820 4849 unsigned int op;
7ab9ffdd
L		 4850
4851 if (i.types[0].bitfield.floatreg
4852 || operand_type_check (i.types[0], reg))
4853 op = 0;
4854 else
4855 op = 1;
4eed87de
AM		 4856 /* Register goes in low 3 bits of opcode. */
4857 i.tm.base_opcode |= i.op[op].regs->reg_num;
4858 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4859 i.rex |= REX_B;
40fb9820 4860 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4861 {
4eed87de
AM		 4862 /* Warn about some common errors, but press on regardless.
4863 The first case can be generated by gcc (<= 2.8.1). */
4864 if (i.operands == 2)
4865 {
4866 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4867 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4868 register_prefix, i.op[!intel_syntax].regs->reg_name,
4869 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4870 }
4871 else
4872 {
4873 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4874 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4875 register_prefix, i.op[0].regs->reg_name);
4eed87de 4876 }
29b0f896
AM		 4877 }
4878 }
4879 }
40fb9820 4880 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4881 {
4882 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4883 must be put into the modrm byte). Now, we make the modrm and
4884 index base bytes based on all the info we've collected. */
29b0f896
AM		 4885
4886 default_seg = build_modrm_byte ();
4887 }
8a2ed489 4888 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4889 {
4890 default_seg = &ds;
4891 }
40fb9820 4892 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4893 {
4894 /* For the string instructions that allow a segment override
4895 on one of their operands, the default segment is ds. */
4896 default_seg = &ds;
4897 }
4898
75178d9d
L		 4899 if (i.tm.base_opcode == 0x8d /* lea */
4900 && i.seg[0]
4901 && !quiet_warnings)
30123838 4902 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4903
4904 /* If a segment was explicitly specified, and the specified segment
4905 is not the default, use an opcode prefix to select it. If we
4906 never figured out what the default segment is, then default_seg
4907 will be zero at this point, and the specified segment prefix will
4908 always be used. */
29b0f896
AM		 4909 if ((i.seg[0]) && (i.seg[0] != default_seg))
4910 {
4911 if (!add_prefix (i.seg[0]->seg_prefix))
4912 return 0;
4913 }
4914 return 1;
4915}
4916
4917static const seg_entry *
e3bb37b5 4918build_modrm_byte (void)
29b0f896
AM		 4919{
4920 const seg_entry *default_seg = 0;
c0f3af97 4921 unsigned int source, dest;
5dd85c99 4922 int vex_3_sources, vex_2_sources;
c0f3af97
L		 4923
4924 /* The first operand of instructions with VEX prefix and 3 sources
4925 must be VEX_Imm4. */
4926 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5dd85c99 4927 vex_2_sources = i.tm.opcode_modifier.vex2sources;
c0f3af97
L		 4928 if (vex_3_sources)
4929 {
4930 unsigned int nds, reg;
4c2c6516 4931 expressionS *exp;
c0f3af97 4932
922d8de8
DR		 4933 if (i.tm.opcode_modifier.veximmext
4934 && i.tm.opcode_modifier.immext)
4935 {
4936 dest = i.operands - 2;
4937 gas_assert (dest == 3);
4938 }
4939 else
0bfee649 4940 dest = i.operands - 1;
c0f3af97 4941 nds = dest - 1;
922d8de8 4942
76ba9986
L		 4943 /* This instruction must have 4 register operands
4944 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4945 It must have VexNDS and VexImmExt. */
4946 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4947 || (i.reg_operands == 3 && i.mem_operands == 1))
4948 && i.tm.opcode_modifier.vexnds
4949 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4950 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4951 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4952
0bfee649
L		 4953 /* Generate an 8bit immediate operand to encode the register
4954 operand. */
4c2c6516 4955 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4956 i.op[i.operands].imms = exp;
4957 i.types[i.operands] = imm8;
4958 i.operands++;
922d8de8
DR		 4959 /* If VexW1 is set, the first operand is the source and
4960 the second operand is encoded in the immediate operand. */
4961 if (i.tm.opcode_modifier.vexw1)
4962 {
4963 source = 0;
4964 reg = 1;
4965 }
4966 else
4967 {
4968 source = 1;
4969 reg = 0;
76ba9986 4970 }
922d8de8
DR		 4971 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4972 || operand_type_equal (&i.tm.operand_types[reg],
76ba9986 4973 &regymm))
922d8de8 4974 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4975 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4976 &regymm)));
0bfee649
L		 4977 exp->X_op = O_constant;
4978 exp->X_add_number
922d8de8 4979 = ((i.op[reg].regs->reg_num
76ba9986 4980 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4981 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4982 }
4983 else
4984 source = dest = 0;
29b0f896
AM		 4985
4986 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4987 implicit registers do not count. If there are 3 register
4988 operands, it must be a instruction with VexNDS. For a
4989 instruction with VexNDD, the destination register is encoded
4990 in VEX prefix. If there are 4 register operands, it must be
4991 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4992 if (i.mem_operands == 0
4993 && ((i.reg_operands == 2
f88c9eb0
SP		 4994 && !i.tm.opcode_modifier.vexndd
4995 && !i.tm.opcode_modifier.vexlwp)
7ab9ffdd
L		 4996 || (i.reg_operands == 3
4997 && i.tm.opcode_modifier.vexnds)
4998 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4999 {
cab737b9
L		 5000 switch (i.operands)
5001 {
5002 case 2:
5003 source = 0;
5004 break;
5005 case 3:
c81128dc
L		 5006 /* When there are 3 operands, one of them may be immediate,
5007 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5008 the first operand must be shift count register (cl) or it
5009 is an instruction with VexNDS. */
9c2799c2 5010 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 5011 || (i.imm_operands == 0
5012 && (i.tm.opcode_modifier.vexnds
5013 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5014 if (operand_type_check (i.types[0], imm)
5015 || i.types[0].bitfield.shiftcount)
5016 source = 1;
5017 else
5018 source = 0;
cab737b9
L		 5019 break;
5020 case 4:
368d64cc
L		 5021 /* When there are 4 operands, the first two must be 8bit
5022 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5023 one.
5024
5025 For instructions with VexNDS, if the first operand
5026 an imm8, the source operand is the 2nd one. If the last
5027 operand is imm8, the source operand is the first one. */
9c2799c2 5028 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5029 && i.types[0].bitfield.imm8
5030 && i.types[1].bitfield.imm8)
5031 || (i.tm.opcode_modifier.vexnds
5032 && i.imm_operands == 1
5033 && (i.types[0].bitfield.imm8
5034 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 5035 if (i.tm.opcode_modifier.vexnds)
5036 {
5037 if (i.types[0].bitfield.imm8)
5038 source = 1;
5039 else
5040 source = 0;
5041 }
5042 else
5043 source = 2;
5044 break;
5045 case 5:
cab737b9
L		 5046 break;
5047 default:
5048 abort ();
5049 }
5050
c0f3af97
L		 5051 if (!vex_3_sources)
5052 {
5053 dest = source + 1;
5054
5055 if (i.tm.opcode_modifier.vexnds)
5056 {
5057 /* For instructions with VexNDS, the register-only
5058 source operand must be XMM or YMM register. It is
fa99fab2
L		 5059 encoded in VEX prefix. We need to clear RegMem bit
5060 before calling operand_type_equal. */
5061 i386_operand_type op = i.tm.operand_types[dest];
5062 op.bitfield.regmem = 0;
c0f3af97 5063 if ((dest + 1) >= i.operands
fa99fab2
L		 5064 || (!operand_type_equal (&op, &regxmm)
5065 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5066 abort ();
5067 i.vex.register_specifier = i.op[dest].regs;
5068 dest++;
5069 }
5070 }
29b0f896
AM		 5071
5072 i.rm.mode = 3;
5073 /* One of the register operands will be encoded in the i.tm.reg
5074 field, the other in the combined i.tm.mode and i.tm.regmem
5075 fields. If no form of this instruction supports a memory
5076 destination operand, then we assume the source operand may
5077 sometimes be a memory operand and so we need to store the
5078 destination in the i.rm.reg field. */
40fb9820
L		 5079 if (!i.tm.operand_types[dest].bitfield.regmem
5080 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5081 {
5082 i.rm.reg = i.op[dest].regs->reg_num;
5083 i.rm.regmem = i.op[source].regs->reg_num;
5084 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5085 i.rex |= REX_R;
29b0f896 5086 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5087 i.rex |= REX_B;
29b0f896
AM		 5088 }
5089 else
5090 {
5091 i.rm.reg = i.op[source].regs->reg_num;
5092 i.rm.regmem = i.op[dest].regs->reg_num;
5093 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5094 i.rex |= REX_B;
29b0f896 5095 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5096 i.rex |= REX_R;
29b0f896 5097 }
161a04f6 5098 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5099 {
40fb9820
L		 5100 if (!i.types[0].bitfield.control
5101 && !i.types[1].bitfield.control)
c4a530c5 5102 abort ();
161a04f6 5103 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5104 add_prefix (LOCK_PREFIX_OPCODE);
5105 }
29b0f896
AM		 5106 }
5107 else
5108 { /* If it's not 2 reg operands... */
c0f3af97
L		 5109 unsigned int mem;
5110
29b0f896
AM		 5111 if (i.mem_operands)
5112 {
5113 unsigned int fake_zero_displacement = 0;
99018f42 5114 unsigned int op;
4eed87de 5115
7ab9ffdd
L		 5116 for (op = 0; op < i.operands; op++)
5117 if (operand_type_check (i.types[op], anymem))
5118 break;
7ab9ffdd 5119 gas_assert (op < i.operands);
29b0f896
AM		 5120
5121 default_seg = &ds;
5122
5123 if (i.base_reg == 0)
5124 {
5125 i.rm.mode = 0;
5126 if (!i.disp_operands)
5127 fake_zero_displacement = 1;
5128 if (i.index_reg == 0)
5129 {
5130 /* Operand is just <disp> */
20f0a1fc 5131 if (flag_code == CODE_64BIT)
29b0f896
AM		 5132 {
5133 /* 64bit mode overwrites the 32bit absolute
5134 addressing by RIP relative addressing and
5135 absolute addressing is encoded by one of the
5136 redundant SIB forms. */
5137 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5138 i.sib.base = NO_BASE_REGISTER;
5139 i.sib.index = NO_INDEX_REGISTER;
fc225355 5140 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5141 ? disp32s : disp32);
20f0a1fc 5142 }
fc225355
L		 5143 else if ((flag_code == CODE_16BIT)
5144 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5145 {
5146 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5147 i.types[op] = disp16;
20f0a1fc
NC		 5148 }
5149 else
5150 {
5151 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5152 i.types[op] = disp32;
29b0f896
AM		 5153 }
5154 }
5155 else /* !i.base_reg && i.index_reg */
5156 {
db51cc60
L		 5157 if (i.index_reg->reg_num == RegEiz
5158 || i.index_reg->reg_num == RegRiz)
5159 i.sib.index = NO_INDEX_REGISTER;
5160 else
5161 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5162 i.sib.base = NO_BASE_REGISTER;
5163 i.sib.scale = i.log2_scale_factor;
5164 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5165 i.types[op].bitfield.disp8 = 0;
5166 i.types[op].bitfield.disp16 = 0;
5167 i.types[op].bitfield.disp64 = 0;
29b0f896 5168 if (flag_code != CODE_64BIT)
40fb9820
L		 5169 {
5170 /* Must be 32 bit */
5171 i.types[op].bitfield.disp32 = 1;
5172 i.types[op].bitfield.disp32s = 0;
5173 }
29b0f896 5174 else
40fb9820
L		 5175 {
5176 i.types[op].bitfield.disp32 = 0;
5177 i.types[op].bitfield.disp32s = 1;
5178 }
29b0f896 5179 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5180 i.rex |= REX_X;
29b0f896
AM		 5181 }
5182 }
5183 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5184 else if (i.base_reg->reg_num == RegRip ||
5185 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5186 {
5187 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5188 i.types[op].bitfield.disp8 = 0;
5189 i.types[op].bitfield.disp16 = 0;
5190 i.types[op].bitfield.disp32 = 0;
5191 i.types[op].bitfield.disp32s = 1;
5192 i.types[op].bitfield.disp64 = 0;
71903a11 5193 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5194 if (! i.disp_operands)
5195 fake_zero_displacement = 1;
29b0f896 5196 }
40fb9820 5197 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5198 {
5199 switch (i.base_reg->reg_num)
5200 {
5201 case 3: /* (%bx) */
5202 if (i.index_reg == 0)
5203 i.rm.regmem = 7;
5204 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5205 i.rm.regmem = i.index_reg->reg_num - 6;
5206 break;
5207 case 5: /* (%bp) */
5208 default_seg = &ss;
5209 if (i.index_reg == 0)
5210 {
5211 i.rm.regmem = 6;
40fb9820 5212 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5213 {
5214 /* fake (%bp) into 0(%bp) */
40fb9820 5215 i.types[op].bitfield.disp8 = 1;
252b5132 5216 fake_zero_displacement = 1;
29b0f896
AM		 5217 }
5218 }
5219 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5220 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5221 break;
5222 default: /* (%si) -> 4 or (%di) -> 5 */
5223 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5224 }
5225 i.rm.mode = mode_from_disp_size (i.types[op]);
5226 }
5227 else /* i.base_reg and 32/64 bit mode */
5228 {
5229 if (flag_code == CODE_64BIT
40fb9820
L		 5230 && operand_type_check (i.types[op], disp))
5231 {
5232 i386_operand_type temp;
0dfbf9d7 5233 operand_type_set (&temp, 0);
40fb9820
L		 5234 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5235 i.types[op] = temp;
5236 if (i.prefix[ADDR_PREFIX] == 0)
5237 i.types[op].bitfield.disp32s = 1;
5238 else
5239 i.types[op].bitfield.disp32 = 1;
5240 }
20f0a1fc 5241
29b0f896
AM		 5242 i.rm.regmem = i.base_reg->reg_num;
5243 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5244 i.rex |= REX_B;
29b0f896
AM		 5245 i.sib.base = i.base_reg->reg_num;
5246 /* x86-64 ignores REX prefix bit here to avoid decoder
5247 complications. */
5248 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5249 {
5250 default_seg = &ss;
5251 if (i.disp_operands == 0)
5252 {
5253 fake_zero_displacement = 1;
40fb9820 5254 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5255 }
5256 }
5257 else if (i.base_reg->reg_num == ESP_REG_NUM)
5258 {
5259 default_seg = &ss;
5260 }
5261 i.sib.scale = i.log2_scale_factor;
5262 if (i.index_reg == 0)
5263 {
5264 /* <disp>(%esp) becomes two byte modrm with no index
5265 register. We've already stored the code for esp
5266 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5267 Any base register besides %esp will not use the
5268 extra modrm byte. */
5269 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5270 }
5271 else
5272 {
db51cc60
L		 5273 if (i.index_reg->reg_num == RegEiz
5274 || i.index_reg->reg_num == RegRiz)
5275 i.sib.index = NO_INDEX_REGISTER;
5276 else
5277 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5278 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5279 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5280 i.rex |= REX_X;
29b0f896 5281 }
67a4f2b7
AO		 5282
5283 if (i.disp_operands
5284 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5285 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5286 i.rm.mode = 0;
5287 else
5288 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5289 }
252b5132 5290
29b0f896
AM		 5291 if (fake_zero_displacement)
5292 {
5293 /* Fakes a zero displacement assuming that i.types[op]
5294 holds the correct displacement size. */
5295 expressionS *exp;
5296
9c2799c2 5297 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5298 exp = &disp_expressions[i.disp_operands++];
5299 i.op[op].disps = exp;
5300 exp->X_op = O_constant;
5301 exp->X_add_number = 0;
5302 exp->X_add_symbol = (symbolS *) 0;
5303 exp->X_op_symbol = (symbolS *) 0;
5304 }
c0f3af97
L		 5305
5306 mem = op;
29b0f896 5307 }
c0f3af97
L		 5308 else
5309 mem = ~0;
252b5132 5310
5dd85c99
SP		 5311 if (vex_2_sources)
5312 {
5313 if (operand_type_check (i.types[0], imm))
5314 i.vex.register_specifier = NULL;
5315 else
5316 {
5317 /* VEX.vvvv encodes one of the sources when the first
5318 operand is not an immediate. */
5319 if (i.tm.opcode_modifier.vexw0)
5320 i.vex.register_specifier = i.op[0].regs;
5321 else
5322 i.vex.register_specifier = i.op[1].regs;
5323 }
5324
5325 /* Destination is a XMM register encoded in the ModRM.reg
5326 and VEX.R bit. */
5327 i.rm.reg = i.op[2].regs->reg_num;
5328 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5329 i.rex |= REX_R;
5330
5331 /* ModRM.rm and VEX.B encodes the other source. */
5332 if (!i.mem_operands)
5333 {
5334 i.rm.mode = 3;
5335
5336 if (i.tm.opcode_modifier.vexw0)
5337 i.rm.regmem = i.op[1].regs->reg_num;
5338 else
5339 i.rm.regmem = i.op[0].regs->reg_num;
5340
5341 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5342 i.rex |= REX_B;
5343 }
5344 }
5345 else if (i.tm.opcode_modifier.vexlwp)
f88c9eb0
SP		 5346 {
5347 i.vex.register_specifier = i.op[2].regs;
5348 if (!i.mem_operands)
5349 {
5350 i.rm.mode = 3;
5351 i.rm.regmem = i.op[1].regs->reg_num;
5352 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5353 i.rex |= REX_B;
5354 }
5355 }
29b0f896
AM		 5356 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5357 (if any) based on i.tm.extension_opcode. Again, we must be
5358 careful to make sure that segment/control/debug/test/MMX
5359 registers are coded into the i.rm.reg field. */
f88c9eb0 5360 else if (i.reg_operands)
29b0f896 5361 {
99018f42 5362 unsigned int op;
7ab9ffdd
L		 5363 unsigned int vex_reg = ~0;
5364
5365 for (op = 0; op < i.operands; op++)
5366 if (i.types[op].bitfield.reg8
5367 || i.types[op].bitfield.reg16
5368 || i.types[op].bitfield.reg32
5369 || i.types[op].bitfield.reg64
5370 || i.types[op].bitfield.regmmx
5371 || i.types[op].bitfield.regxmm
5372 || i.types[op].bitfield.regymm
5373 || i.types[op].bitfield.sreg2
5374 || i.types[op].bitfield.sreg3
5375 || i.types[op].bitfield.control
5376 || i.types[op].bitfield.debug
5377 || i.types[op].bitfield.test)
5378 break;
c0209578 5379
7ab9ffdd
L		 5380 if (vex_3_sources)
5381 op = dest;
5382 else if (i.tm.opcode_modifier.vexnds)
5383 {
5384 /* For instructions with VexNDS, the register-only
5385 source operand is encoded in VEX prefix. */
5386 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5387
7ab9ffdd 5388 if (op > mem)
c0f3af97 5389 {
7ab9ffdd
L		 5390 vex_reg = op++;
5391 gas_assert (op < i.operands);
c0f3af97
L		 5392 }
5393 else
c0f3af97 5394 {
7ab9ffdd
L		 5395 vex_reg = op + 1;
5396 gas_assert (vex_reg < i.operands);
c0f3af97 5397 }
7ab9ffdd
L		 5398 }
5399 else if (i.tm.opcode_modifier.vexndd)
5400 {
5401 /* For instructions with VexNDD, there should be
5402 no memory operand and the register destination
5403 is encoded in VEX prefix. */
5404 gas_assert (i.mem_operands == 0
5405 && (op + 2) == i.operands);
5406 vex_reg = op + 1;
5407 }
5408 else
5409 gas_assert (op < i.operands);
99018f42 5410
7ab9ffdd
L		 5411 if (vex_reg != (unsigned int) ~0)
5412 {
5413 gas_assert (i.reg_operands == 2);
5414
5415 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5416 &regxmm)
7ab9ffdd
L		 5417 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5418 &regymm))
5419 abort ();
f88c9eb0 5420
7ab9ffdd
L		 5421 i.vex.register_specifier = i.op[vex_reg].regs;
5422 }
5423
1b9f0c97
L		 5424 /* Don't set OP operand twice. */
5425 if (vex_reg != op)
7ab9ffdd 5426 {
1b9f0c97
L		 5427 /* If there is an extension opcode to put here, the
5428 register number must be put into the regmem field. */
5429 if (i.tm.extension_opcode != None)
5430 {
5431 i.rm.regmem = i.op[op].regs->reg_num;
5432 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5433 i.rex |= REX_B;
5434 }
5435 else
5436 {
5437 i.rm.reg = i.op[op].regs->reg_num;
5438 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5439 i.rex |= REX_R;
5440 }
7ab9ffdd 5441 }
252b5132 5442
29b0f896
AM		 5443 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5444 must set it to 3 to indicate this is a register operand
5445 in the regmem field. */
5446 if (!i.mem_operands)
5447 i.rm.mode = 3;
5448 }
252b5132 5449
29b0f896 5450 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5451 if (i.tm.extension_opcode != None)
29b0f896
AM		 5452 i.rm.reg = i.tm.extension_opcode;
5453 }
5454 return default_seg;
5455}
252b5132 5456
29b0f896 5457static void
e3bb37b5 5458output_branch (void)
29b0f896
AM		 5459{
5460 char *p;
5461 int code16;
5462 int prefix;
5463 relax_substateT subtype;
5464 symbolS *sym;
5465 offsetT off;
5466
5467 code16 = 0;
5468 if (flag_code == CODE_16BIT)
5469 code16 = CODE16;
5470
5471 prefix = 0;
5472 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5473 {
29b0f896
AM		 5474 prefix = 1;
5475 i.prefixes -= 1;
5476 code16 ^= CODE16;
252b5132 5477 }
29b0f896
AM		 5478 /* Pentium4 branch hints. */
5479 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5480 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5481 {
29b0f896
AM		 5482 prefix++;
5483 i.prefixes--;
5484 }
5485 if (i.prefix[REX_PREFIX] != 0)
5486 {
5487 prefix++;
5488 i.prefixes--;
2f66722d
AM		 5489 }
5490
29b0f896
AM		 5491 if (i.prefixes != 0 && !intel_syntax)
5492 as_warn (_("skipping prefixes on this instruction"));
5493
5494 /* It's always a symbol; End frag & setup for relax.
5495 Make sure there is enough room in this frag for the largest
5496 instruction we may generate in md_convert_frag. This is 2
5497 bytes for the opcode and room for the prefix and largest
5498 displacement. */
5499 frag_grow (prefix + 2 + 4);
5500 /* Prefix and 1 opcode byte go in fr_fix. */
5501 p = frag_more (prefix + 1);
5502 if (i.prefix[DATA_PREFIX] != 0)
5503 *p++ = DATA_PREFIX_OPCODE;
5504 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5505 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5506 *p++ = i.prefix[SEG_PREFIX];
5507 if (i.prefix[REX_PREFIX] != 0)
5508 *p++ = i.prefix[REX_PREFIX];
5509 *p = i.tm.base_opcode;
5510
5511 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5512 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5513 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5514 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5515 else
5516 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5517 subtype |= code16;
3e73aa7c 5518
29b0f896
AM		 5519 sym = i.op[0].disps->X_add_symbol;
5520 off = i.op[0].disps->X_add_number;
3e73aa7c 5521
29b0f896
AM		 5522 if (i.op[0].disps->X_op != O_constant
5523 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5524 {
29b0f896
AM		 5525 /* Handle complex expressions. */
5526 sym = make_expr_symbol (i.op[0].disps);
5527 off = 0;
5528 }
3e73aa7c 5529
29b0f896
AM		 5530 /* 1 possible extra opcode + 4 byte displacement go in var part.
5531 Pass reloc in fr_var. */
5532 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5533}
3e73aa7c 5534
29b0f896 5535static void
e3bb37b5 5536output_jump (void)
29b0f896
AM		 5537{
5538 char *p;
5539 int size;
3e02c1cc 5540 fixS *fixP;
29b0f896 5541
40fb9820 5542 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5543 {
5544 /* This is a loop or jecxz type instruction. */
5545 size = 1;
5546 if (i.prefix[ADDR_PREFIX] != 0)
5547 {
5548 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5549 i.prefixes -= 1;
5550 }
5551 /* Pentium4 branch hints. */
5552 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5553 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5554 {
5555 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5556 i.prefixes--;
3e73aa7c
JH		 5557 }
5558 }
29b0f896
AM		 5559 else
5560 {
5561 int code16;
3e73aa7c 5562
29b0f896
AM		 5563 code16 = 0;
5564 if (flag_code == CODE_16BIT)
5565 code16 = CODE16;
3e73aa7c 5566
29b0f896
AM		 5567 if (i.prefix[DATA_PREFIX] != 0)
5568 {
5569 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5570 i.prefixes -= 1;
5571 code16 ^= CODE16;
5572 }
252b5132 5573
29b0f896
AM		 5574 size = 4;
5575 if (code16)
5576 size = 2;
5577 }
9fcc94b6 5578
29b0f896
AM		 5579 if (i.prefix[REX_PREFIX] != 0)
5580 {
5581 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5582 i.prefixes -= 1;
5583 }
252b5132 5584
29b0f896
AM		 5585 if (i.prefixes != 0 && !intel_syntax)
5586 as_warn (_("skipping prefixes on this instruction"));
e0890092 5587
29b0f896
AM		 5588 p = frag_more (1 + size);
5589 *p++ = i.tm.base_opcode;
e0890092 5590
3e02c1cc
AM		 5591 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5592 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5593
5594 /* All jumps handled here are signed, but don't use a signed limit
5595 check for 32 and 16 bit jumps as we want to allow wrap around at
5596 4G and 64k respectively. */
5597 if (size == 1)
5598 fixP->fx_signed = 1;
29b0f896 5599}
e0890092 5600
29b0f896 5601static void
e3bb37b5 5602output_interseg_jump (void)
29b0f896
AM		 5603{
5604 char *p;
5605 int size;
5606 int prefix;
5607 int code16;
252b5132 5608
29b0f896
AM		 5609 code16 = 0;
5610 if (flag_code == CODE_16BIT)
5611 code16 = CODE16;
a217f122 5612
29b0f896
AM		 5613 prefix = 0;
5614 if (i.prefix[DATA_PREFIX] != 0)
5615 {
5616 prefix = 1;
5617 i.prefixes -= 1;
5618 code16 ^= CODE16;
5619 }
5620 if (i.prefix[REX_PREFIX] != 0)
5621 {
5622 prefix++;
5623 i.prefixes -= 1;
5624 }
252b5132 5625
29b0f896
AM		 5626 size = 4;
5627 if (code16)
5628 size = 2;
252b5132 5629
29b0f896
AM		 5630 if (i.prefixes != 0 && !intel_syntax)
5631 as_warn (_("skipping prefixes on this instruction"));
252b5132 5632
29b0f896
AM		 5633 /* 1 opcode; 2 segment; offset */
5634 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5635
29b0f896
AM		 5636 if (i.prefix[DATA_PREFIX] != 0)
5637 *p++ = DATA_PREFIX_OPCODE;
252b5132 5638
29b0f896
AM		 5639 if (i.prefix[REX_PREFIX] != 0)
5640 *p++ = i.prefix[REX_PREFIX];
252b5132 5641
29b0f896
AM		 5642 *p++ = i.tm.base_opcode;
5643 if (i.op[1].imms->X_op == O_constant)
5644 {
5645 offsetT n = i.op[1].imms->X_add_number;
252b5132 5646
29b0f896
AM		 5647 if (size == 2
5648 && !fits_in_unsigned_word (n)
5649 && !fits_in_signed_word (n))
5650 {
5651 as_bad (_("16-bit jump out of range"));
5652 return;
5653 }
5654 md_number_to_chars (p, n, size);
5655 }
5656 else
5657 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5658 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5659 if (i.op[0].imms->X_op != O_constant)
5660 as_bad (_("can't handle non absolute segment in `%s'"),
5661 i.tm.name);
5662 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5663}
a217f122 5664
29b0f896 5665static void
e3bb37b5 5666output_insn (void)
29b0f896 5667{
2bbd9c25
JJ		 5668 fragS *insn_start_frag;
5669 offsetT insn_start_off;
5670
29b0f896
AM		 5671 /* Tie dwarf2 debug info to the address at the start of the insn.
5672 We can't do this after the insn has been output as the current
5673 frag may have been closed off. eg. by frag_var. */
5674 dwarf2_emit_insn (0);
5675
2bbd9c25
JJ		 5676 insn_start_frag = frag_now;
5677 insn_start_off = frag_now_fix ();
5678
29b0f896 5679 /* Output jumps. */
40fb9820 5680 if (i.tm.opcode_modifier.jump)
29b0f896 5681 output_branch ();
40fb9820
L		 5682 else if (i.tm.opcode_modifier.jumpbyte
5683 || i.tm.opcode_modifier.jumpdword)
29b0f896 5684 output_jump ();
40fb9820 5685 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5686 output_interseg_jump ();
5687 else
5688 {
5689 /* Output normal instructions here. */
5690 char *p;
5691 unsigned char *q;
47465058 5692 unsigned int j;
331d2d0d 5693 unsigned int prefix;
4dffcebc 5694
c0f3af97
L		 5695 /* Since the VEX prefix contains the implicit prefix, we don't
5696 need the explicit prefix. */
5697 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5698 {
c0f3af97 5699 switch (i.tm.opcode_length)
bc4bd9ab 5700 {
c0f3af97
L		 5701 case 3:
5702 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5703 {
c0f3af97
L		 5704 prefix = (i.tm.base_opcode >> 24) & 0xff;
5705 goto check_prefix;
5706 }
5707 break;
5708 case 2:
5709 if ((i.tm.base_opcode & 0xff0000) != 0)
5710 {
5711 prefix = (i.tm.base_opcode >> 16) & 0xff;
5712 if (i.tm.cpu_flags.bitfield.cpupadlock)
5713 {
4dffcebc 5714check_prefix:
c0f3af97 5715 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5716 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5717 != REPE_PREFIX_OPCODE))
5718 add_prefix (prefix);
5719 }
5720 else
4dffcebc
L		 5721 add_prefix (prefix);
5722 }
c0f3af97
L		 5723 break;
5724 case 1:
5725 break;
5726 default:
5727 abort ();
bc4bd9ab 5728 }
c0f3af97
L		 5729
5730 /* The prefix bytes. */
5731 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5732 if (*q)
5733 FRAG_APPEND_1_CHAR (*q);
0f10071e 5734 }
252b5132 5735
c0f3af97
L		 5736 if (i.tm.opcode_modifier.vex)
5737 {
5738 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5739 if (*q)
5740 switch (j)
5741 {
5742 case REX_PREFIX:
5743 /* REX byte is encoded in VEX prefix. */
5744 break;
5745 case SEG_PREFIX:
5746 case ADDR_PREFIX:
5747 FRAG_APPEND_1_CHAR (*q);
5748 break;
5749 default:
5750 /* There should be no other prefixes for instructions
5751 with VEX prefix. */
5752 abort ();
5753 }
5754
5755 /* Now the VEX prefix. */
5756 p = frag_more (i.vex.length);
5757 for (j = 0; j < i.vex.length; j++)
5758 p[j] = i.vex.bytes[j];
5759 }
252b5132 5760
29b0f896 5761 /* Now the opcode; be careful about word order here! */
4dffcebc 5762 if (i.tm.opcode_length == 1)
29b0f896
AM		 5763 {
5764 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5765 }
5766 else
5767 {
4dffcebc 5768 switch (i.tm.opcode_length)
331d2d0d 5769 {
4dffcebc 5770 case 3:
331d2d0d
L		 5771 p = frag_more (3);
5772 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5773 break;
5774 case 2:
5775 p = frag_more (2);
5776 break;
5777 default:
5778 abort ();
5779 break;
331d2d0d 5780 }
0f10071e 5781
29b0f896
AM		 5782 /* Put out high byte first: can't use md_number_to_chars! */
5783 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5784 *p = i.tm.base_opcode & 0xff;
5785 }
3e73aa7c 5786
29b0f896 5787 /* Now the modrm byte and sib byte (if present). */
40fb9820 5788 if (i.tm.opcode_modifier.modrm)
29b0f896 5789 {
4a3523fa
L		 5790 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5791 | i.rm.reg << 3
5792 | i.rm.mode << 6));
29b0f896
AM		 5793 /* If i.rm.regmem == ESP (4)
5794 && i.rm.mode != (Register mode)
5795 && not 16 bit
5796 ==> need second modrm byte. */
5797 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5798 && i.rm.mode != 3
40fb9820 5799 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5800 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5801 | i.sib.index << 3
5802 | i.sib.scale << 6));
29b0f896 5803 }
3e73aa7c 5804
29b0f896 5805 if (i.disp_operands)
2bbd9c25 5806 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5807
29b0f896 5808 if (i.imm_operands)
2bbd9c25 5809 output_imm (insn_start_frag, insn_start_off);
29b0f896 5810 }
252b5132 5811
29b0f896
AM		 5812#ifdef DEBUG386
5813 if (flag_debug)
5814 {
7b81dfbb 5815 pi ("" /*line*/, &i);
29b0f896
AM		 5816 }
5817#endif /* DEBUG386 */
5818}
252b5132 5819
e205caa7
L		 5820/* Return the size of the displacement operand N. */
5821
5822static int
5823disp_size (unsigned int n)
5824{
5825 int size = 4;
40fb9820
L		 5826 if (i.types[n].bitfield.disp64)
5827 size = 8;
5828 else if (i.types[n].bitfield.disp8)
5829 size = 1;
5830 else if (i.types[n].bitfield.disp16)
5831 size = 2;
e205caa7
L		 5832 return size;
5833}
5834
5835/* Return the size of the immediate operand N. */
5836
5837static int
5838imm_size (unsigned int n)
5839{
5840 int size = 4;
40fb9820
L		 5841 if (i.types[n].bitfield.imm64)
5842 size = 8;
5843 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5844 size = 1;
5845 else if (i.types[n].bitfield.imm16)
5846 size = 2;
e205caa7
L		 5847 return size;
5848}
5849
29b0f896 5850static void
64e74474 5851output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5852{
5853 char *p;
5854 unsigned int n;
252b5132 5855
29b0f896
AM		 5856 for (n = 0; n < i.operands; n++)
5857 {
40fb9820 5858 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5859 {
5860 if (i.op[n].disps->X_op == O_constant)
5861 {
e205caa7 5862 int size = disp_size (n);
29b0f896 5863 offsetT val;
252b5132 5864
29b0f896
AM		 5865 val = offset_in_range (i.op[n].disps->X_add_number,
5866 size);
5867 p = frag_more (size);
5868 md_number_to_chars (p, val, size);
5869 }
5870 else
5871 {
f86103b7 5872 enum bfd_reloc_code_real reloc_type;
e205caa7 5873 int size = disp_size (n);
40fb9820 5874 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5875 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5876
e205caa7 5877 /* We can't have 8 bit displacement here. */
9c2799c2 5878 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5879
29b0f896
AM		 5880 /* The PC relative address is computed relative
5881 to the instruction boundary, so in case immediate
5882 fields follows, we need to adjust the value. */
5883 if (pcrel && i.imm_operands)
5884 {
29b0f896 5885 unsigned int n1;
e205caa7 5886 int sz = 0;
252b5132 5887
29b0f896 5888 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5889 if (operand_type_check (i.types[n1], imm))
252b5132 5890 {
e205caa7
L		 5891 /* Only one immediate is allowed for PC
5892 relative address. */
9c2799c2 5893 gas_assert (sz == 0);
e205caa7
L		 5894 sz = imm_size (n1);
5895 i.op[n].disps->X_add_number -= sz;
252b5132 5896 }
29b0f896 5897 /* We should find the immediate. */
9c2799c2 5898 gas_assert (sz != 0);
29b0f896 5899 }
520dc8e8 5900
29b0f896 5901 p = frag_more (size);
2bbd9c25 5902 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5903 if (GOT_symbol
2bbd9c25 5904 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5905 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5906 || reloc_type == BFD_RELOC_X86_64_32S
5907 || (reloc_type == BFD_RELOC_64
5908 && object_64bit))
d6ab8113
JB		 5909 && (i.op[n].disps->X_op == O_symbol
5910 || (i.op[n].disps->X_op == O_add
5911 && ((symbol_get_value_expression
5912 (i.op[n].disps->X_op_symbol)->X_op)
5913 == O_subtract))))
5914 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5915 {
5916 offsetT add;
5917
5918 if (insn_start_frag == frag_now)
5919 add = (p - frag_now->fr_literal) - insn_start_off;
5920 else
5921 {
5922 fragS *fr;
5923
5924 add = insn_start_frag->fr_fix - insn_start_off;
5925 for (fr = insn_start_frag->fr_next;
5926 fr && fr != frag_now; fr = fr->fr_next)
5927 add += fr->fr_fix;
5928 add += p - frag_now->fr_literal;
5929 }
5930
4fa24527 5931 if (!object_64bit)
7b81dfbb
AJ		 5932 {
5933 reloc_type = BFD_RELOC_386_GOTPC;
5934 i.op[n].imms->X_add_number += add;
5935 }
5936 else if (reloc_type == BFD_RELOC_64)
5937 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5938 else
7b81dfbb
AJ		 5939 /* Don't do the adjustment for x86-64, as there
5940 the pcrel addressing is relative to the _next_
5941 insn, and that is taken care of in other code. */
d6ab8113 5942 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5943 }
062cd5e7 5944 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5945 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5946 }
5947 }
5948 }
5949}
252b5132 5950
29b0f896 5951static void
64e74474 5952output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5953{
5954 char *p;
5955 unsigned int n;
252b5132 5956
29b0f896
AM		 5957 for (n = 0; n < i.operands; n++)
5958 {
40fb9820 5959 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5960 {
5961 if (i.op[n].imms->X_op == O_constant)
5962 {
e205caa7 5963 int size = imm_size (n);
29b0f896 5964 offsetT val;
b4cac588 5965
29b0f896
AM		 5966 val = offset_in_range (i.op[n].imms->X_add_number,
5967 size);
5968 p = frag_more (size);
5969 md_number_to_chars (p, val, size);
5970 }
5971 else
5972 {
5973 /* Not absolute_section.
5974 Need a 32-bit fixup (don't support 8bit
5975 non-absolute imms). Try to support other
5976 sizes ... */
f86103b7 5977 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5978 int size = imm_size (n);
5979 int sign;
29b0f896 5980
40fb9820 5981 if (i.types[n].bitfield.imm32s
a7d61044 5982 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5983 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5984 sign = 1;
e205caa7
L		 5985 else
5986 sign = 0;
520dc8e8 5987
29b0f896
AM		 5988 p = frag_more (size);
5989 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5990
2bbd9c25
JJ		 5991 /* This is tough to explain. We end up with this one if we
5992 * have operands that look like
5993 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5994 * obtain the absolute address of the GOT, and it is strongly
5995 * preferable from a performance point of view to avoid using
5996 * a runtime relocation for this. The actual sequence of
5997 * instructions often look something like:
5998 *
5999 * call .L66
6000 * .L66:
6001 * popl %ebx
6002 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6003 *
6004 * The call and pop essentially return the absolute address
6005 * of the label .L66 and store it in %ebx. The linker itself
6006 * will ultimately change the first operand of the addl so
6007 * that %ebx points to the GOT, but to keep things simple, the
6008 * .o file must have this operand set so that it generates not
6009 * the absolute address of .L66, but the absolute address of
6010 * itself. This allows the linker itself simply treat a GOTPC
6011 * relocation as asking for a pcrel offset to the GOT to be
6012 * added in, and the addend of the relocation is stored in the
6013 * operand field for the instruction itself.
6014 *
6015 * Our job here is to fix the operand so that it would add
6016 * the correct offset so that %ebx would point to itself. The
6017 * thing that is tricky is that .-.L66 will point to the
6018 * beginning of the instruction, so we need to further modify
6019 * the operand so that it will point to itself. There are
6020 * other cases where you have something like:
6021 *
6022 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6023 *
6024 * and here no correction would be required. Internally in
6025 * the assembler we treat operands of this form as not being
6026 * pcrel since the '.' is explicitly mentioned, and I wonder
6027 * whether it would simplify matters to do it this way. Who
6028 * knows. In earlier versions of the PIC patches, the
6029 * pcrel_adjust field was used to store the correction, but
6030 * since the expression is not pcrel, I felt it would be
6031 * confusing to do it this way. */
6032
d6ab8113 6033 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6034 || reloc_type == BFD_RELOC_X86_64_32S
6035 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6036 && GOT_symbol
6037 && GOT_symbol == i.op[n].imms->X_add_symbol
6038 && (i.op[n].imms->X_op == O_symbol
6039 || (i.op[n].imms->X_op == O_add
6040 && ((symbol_get_value_expression
6041 (i.op[n].imms->X_op_symbol)->X_op)
6042 == O_subtract))))
6043 {
2bbd9c25
JJ		 6044 offsetT add;
6045
6046 if (insn_start_frag == frag_now)
6047 add = (p - frag_now->fr_literal) - insn_start_off;
6048 else
6049 {
6050 fragS *fr;
6051
6052 add = insn_start_frag->fr_fix - insn_start_off;
6053 for (fr = insn_start_frag->fr_next;
6054 fr && fr != frag_now; fr = fr->fr_next)
6055 add += fr->fr_fix;
6056 add += p - frag_now->fr_literal;
6057 }
6058
4fa24527 6059 if (!object_64bit)
d6ab8113 6060 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6061 else if (size == 4)
d6ab8113 6062 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6063 else if (size == 8)
6064 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6065 i.op[n].imms->X_add_number += add;
29b0f896 6066 }
29b0f896
AM		 6067 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6068 i.op[n].imms, 0, reloc_type);
6069 }
6070 }
6071 }
252b5132
RH		 6072}
6073\f
d182319b
JB		 6074/* x86_cons_fix_new is called via the expression parsing code when a
6075 reloc is needed. We use this hook to get the correct .got reloc. */
6076static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6077static int cons_sign = -1;
6078
6079void
e3bb37b5 6080x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6081 expressionS *exp)
d182319b
JB		 6082{
6083 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6084
6085 got_reloc = NO_RELOC;
6086
6087#ifdef TE_PE
6088 if (exp->X_op == O_secrel)
6089 {
6090 exp->X_op = O_symbol;
6091 r = BFD_RELOC_32_SECREL;
6092 }
6093#endif
6094
6095 fix_new_exp (frag, off, len, exp, 0, r);
6096}
6097
718ddfc0
JB		 6098#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6099# define lex_got(reloc, adjust, types) NULL
6100#else
f3c180ae
AM		 6101/* Parse operands of the form
6102 <symbol>@GOTOFF+<nnn>
6103 and similar .plt or .got references.
6104
6105 If we find one, set up the correct relocation in RELOC and copy the
6106 input string, minus the `@GOTOFF' into a malloc'd buffer for
6107 parsing by the calling routine. Return this buffer, and if ADJUST
6108 is non-null set it to the length of the string we removed from the
6109 input line. Otherwise return NULL. */
6110static char *
3956db08 6111lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6112 int *adjust,
40fb9820 6113 i386_operand_type *types)
f3c180ae 6114{
7b81dfbb
AJ		 6115 /* Some of the relocations depend on the size of what field is to
6116 be relocated. But in our callers i386_immediate and i386_displacement
6117 we don't yet know the operand size (this will be set by insn
6118 matching). Hence we record the word32 relocation here,
6119 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6120 static const struct {
6121 const char *str;
4fa24527 6122 const enum bfd_reloc_code_real rel[2];
40fb9820 6123 const i386_operand_type types64;
f3c180ae 6124 } gotrel[] = {
1e9cc1c2 6125 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6126 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6127 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6128 { "PLT", { BFD_RELOC_386_PLT32,
6129 BFD_RELOC_X86_64_PLT32 },
40fb9820 6130 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6131 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6132 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6133 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6134 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6135 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6136 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6137 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6138 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6139 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6140 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6141 BFD_RELOC_X86_64_TLSGD },
40fb9820 6142 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6143 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6144 _dummy_first_bfd_reloc_code_real },
40fb9820 6145 OPERAND_TYPE_NONE },
1e9cc1c2 6146 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6147 BFD_RELOC_X86_64_TLSLD },
40fb9820 6148 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6149 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6150 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6151 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6152 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6153 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6154 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6155 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6156 _dummy_first_bfd_reloc_code_real },
40fb9820 6157 OPERAND_TYPE_NONE },
4eed87de
AM		 6158 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6159 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6160
40fb9820 6161 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6162 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6163 _dummy_first_bfd_reloc_code_real },
40fb9820 6164 OPERAND_TYPE_NONE },
4eed87de 6165 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6166 _dummy_first_bfd_reloc_code_real },
40fb9820 6167 OPERAND_TYPE_NONE },
4eed87de
AM		 6168 { "GOT", { BFD_RELOC_386_GOT32,
6169 BFD_RELOC_X86_64_GOT32 },
40fb9820 6170 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6171 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6172 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6173 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6174 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6175 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6176 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6177 };
6178 char *cp;
6179 unsigned int j;
6180
718ddfc0
JB		 6181 if (!IS_ELF)
6182 return NULL;
6183
f3c180ae 6184 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6185 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6186 return NULL;
6187
47465058 6188 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6189 {
6190 int len;
6191
6192 len = strlen (gotrel[j].str);
28f81592 6193 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6194 {
4fa24527 6195 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6196 {
28f81592
AM		 6197 int first, second;
6198 char *tmpbuf, *past_reloc;
f3c180ae 6199
4fa24527 6200 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6201 if (adjust)
6202 *adjust = len;
f3c180ae 6203
3956db08
JB		 6204 if (types)
6205 {
6206 if (flag_code != CODE_64BIT)
40fb9820
L		 6207 {
6208 types->bitfield.imm32 = 1;
6209 types->bitfield.disp32 = 1;
6210 }
3956db08
JB		 6211 else
6212 *types = gotrel[j].types64;
6213 }
6214
f3c180ae
AM		 6215 if (GOT_symbol == NULL)
6216 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6217
28f81592 6218 /* The length of the first part of our input line. */
f3c180ae 6219 first = cp - input_line_pointer;
28f81592
AM		 6220
6221 /* The second part goes from after the reloc token until
67c11a9b 6222 (and including) an end_of_line char or comma. */
28f81592 6223 past_reloc = cp + 1 + len;
67c11a9b
AM		 6224 cp = past_reloc;
6225 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6226 ++cp;
6227 second = cp + 1 - past_reloc;
28f81592
AM		 6228
6229 /* Allocate and copy string. The trailing NUL shouldn't
6230 be necessary, but be safe. */
1e9cc1c2 6231 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6232 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6233 if (second != 0 && *past_reloc != ' ')
6234 /* Replace the relocation token with ' ', so that
6235 errors like foo@GOTOFF1 will be detected. */
6236 tmpbuf[first++] = ' ';
6237 memcpy (tmpbuf + first, past_reloc, second);
6238 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6239 return tmpbuf;
6240 }
6241
4fa24527
JB		 6242 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6243 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6244 return NULL;
6245 }
6246 }
6247
6248 /* Might be a symbol version string. Don't as_bad here. */
6249 return NULL;
6250}
6251
f3c180ae 6252void
e3bb37b5 6253x86_cons (expressionS *exp, int size)
f3c180ae 6254{
ee86248c
JB		 6255 intel_syntax = -intel_syntax;
6256
4fa24527 6257 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6258 {
6259 /* Handle @GOTOFF and the like in an expression. */
6260 char *save;
6261 char *gotfree_input_line;
6262 int adjust;
6263
6264 save = input_line_pointer;
3956db08 6265 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6266 if (gotfree_input_line)
6267 input_line_pointer = gotfree_input_line;
6268
6269 expression (exp);
6270
6271 if (gotfree_input_line)
6272 {
6273 /* expression () has merrily parsed up to the end of line,
6274 or a comma - in the wrong buffer. Transfer how far
6275 input_line_pointer has moved to the right buffer. */
6276 input_line_pointer = (save
6277 + (input_line_pointer - gotfree_input_line)
6278 + adjust);
6279 free (gotfree_input_line);
3992d3b7
AM		 6280 if (exp->X_op == O_constant
6281 || exp->X_op == O_absent
6282 || exp->X_op == O_illegal
6283 || exp->X_op == O_register
6284 || exp->X_op == O_big)
6285 {
6286 char c = *input_line_pointer;
6287 *input_line_pointer = 0;
6288 as_bad (_("missing or invalid expression `%s'"), save);
6289 *input_line_pointer = c;
6290 }
f3c180ae
AM		 6291 }
6292 }
6293 else
6294 expression (exp);
ee86248c
JB		 6295
6296 intel_syntax = -intel_syntax;
6297
6298 if (intel_syntax)
6299 i386_intel_simplify (exp);
f3c180ae
AM		 6300}
6301#endif
6302
9f32dd5b
L		 6303static void
6304signed_cons (int size)
6482c264 6305{
d182319b
JB		 6306 if (flag_code == CODE_64BIT)
6307 cons_sign = 1;
6308 cons (size);
6309 cons_sign = -1;
6482c264
NC		 6310}
6311
d182319b 6312#ifdef TE_PE
6482c264
NC		 6313static void
6314pe_directive_secrel (dummy)
6315 int dummy ATTRIBUTE_UNUSED;
6316{
6317 expressionS exp;
6318
6319 do
6320 {
6321 expression (&exp);
6322 if (exp.X_op == O_symbol)
6323 exp.X_op = O_secrel;
6324
6325 emit_expr (&exp, 4);
6326 }
6327 while (*input_line_pointer++ == ',');
6328
6329 input_line_pointer--;
6330 demand_empty_rest_of_line ();
6331}
6482c264
NC		 6332#endif
6333
252b5132 6334static int
70e41ade 6335i386_immediate (char *imm_start)
252b5132
RH		 6336{
6337 char *save_input_line_pointer;
f3c180ae 6338 char *gotfree_input_line;
252b5132 6339 segT exp_seg = 0;
47926f60 6340 expressionS *exp;
40fb9820
L		 6341 i386_operand_type types;
6342
0dfbf9d7 6343 operand_type_set (&types, ~0);
252b5132
RH		 6344
6345 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6346 {
31b2323c
L		 6347 as_bad (_("at most %d immediate operands are allowed"),
6348 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6349 return 0;
6350 }
6351
6352 exp = &im_expressions[i.imm_operands++];
520dc8e8 6353 i.op[this_operand].imms = exp;
252b5132
RH		 6354
6355 if (is_space_char (*imm_start))
6356 ++imm_start;
6357
6358 save_input_line_pointer = input_line_pointer;
6359 input_line_pointer = imm_start;
6360
3956db08 6361 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6362 if (gotfree_input_line)
6363 input_line_pointer = gotfree_input_line;
252b5132
RH		 6364
6365 exp_seg = expression (exp);
6366
83183c0c 6367 SKIP_WHITESPACE ();
252b5132 6368 if (*input_line_pointer)
f3c180ae 6369 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6370
6371 input_line_pointer = save_input_line_pointer;
f3c180ae 6372 if (gotfree_input_line)
ee86248c
JB		 6373 {
6374 free (gotfree_input_line);
6375
6376 if (exp->X_op == O_constant || exp->X_op == O_register)
6377 exp->X_op = O_illegal;
6378 }
6379
6380 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6381}
252b5132 6382
ee86248c
JB		 6383static int
6384i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6385 i386_operand_type types, const char *imm_start)
6386{
6387 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6388 {
313c53d1
L		 6389 if (imm_start)
6390 as_bad (_("missing or invalid immediate expression `%s'"),
6391 imm_start);
3992d3b7 6392 return 0;
252b5132 6393 }
3e73aa7c 6394 else if (exp->X_op == O_constant)
252b5132 6395 {
47926f60 6396 /* Size it properly later. */
40fb9820 6397 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6398 /* If BFD64, sign extend val. */
4eed87de
AM		 6399 if (!use_rela_relocations
6400 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6401 exp->X_add_number
6402 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6403 }
4c63da97 6404#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6405 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6406 && exp_seg != absolute_section
47926f60 6407 && exp_seg != text_section
24eab124
AM		 6408 && exp_seg != data_section
6409 && exp_seg != bss_section
6410 && exp_seg != undefined_section
f86103b7 6411 && !bfd_is_com_section (exp_seg))
252b5132 6412 {
d0b47220 6413 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6414 return 0;
6415 }
6416#endif
bb8f5920
L		 6417 else if (!intel_syntax && exp->X_op == O_register)
6418 {
313c53d1
L		 6419 if (imm_start)
6420 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6421 return 0;
6422 }
252b5132
RH		 6423 else
6424 {
6425 /* This is an address. The size of the address will be
24eab124 6426 determined later, depending on destination register,
3e73aa7c 6427 suffix, or the default for the section. */
40fb9820
L		 6428 i.types[this_operand].bitfield.imm8 = 1;
6429 i.types[this_operand].bitfield.imm16 = 1;
6430 i.types[this_operand].bitfield.imm32 = 1;
6431 i.types[this_operand].bitfield.imm32s = 1;
6432 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6433 i.types[this_operand] = operand_type_and (i.types[this_operand],
6434 types);
252b5132
RH		 6435 }
6436
6437 return 1;
6438}
6439
551c1ca1 6440static char *
e3bb37b5 6441i386_scale (char *scale)
252b5132 6442{
551c1ca1
AM		 6443 offsetT val;
6444 char *save = input_line_pointer;
252b5132 6445
551c1ca1
AM		 6446 input_line_pointer = scale;
6447 val = get_absolute_expression ();
6448
6449 switch (val)
252b5132 6450 {
551c1ca1 6451 case 1:
252b5132
RH		 6452 i.log2_scale_factor = 0;
6453 break;
551c1ca1 6454 case 2:
252b5132
RH		 6455 i.log2_scale_factor = 1;
6456 break;
551c1ca1 6457 case 4:
252b5132
RH		 6458 i.log2_scale_factor = 2;
6459 break;
551c1ca1 6460 case 8:
252b5132
RH		 6461 i.log2_scale_factor = 3;
6462 break;
6463 default:
a724f0f4
JB		 6464 {
6465 char sep = *input_line_pointer;
6466
6467 *input_line_pointer = '\0';
6468 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6469 scale);
6470 *input_line_pointer = sep;
6471 input_line_pointer = save;
6472 return NULL;
6473 }
252b5132 6474 }
29b0f896 6475 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6476 {
6477 as_warn (_("scale factor of %d without an index register"),
24eab124 6478 1 << i.log2_scale_factor);
252b5132 6479 i.log2_scale_factor = 0;
252b5132 6480 }
551c1ca1
AM		 6481 scale = input_line_pointer;
6482 input_line_pointer = save;
6483 return scale;
252b5132
RH		 6484}
6485
252b5132 6486static int
e3bb37b5 6487i386_displacement (char *disp_start, char *disp_end)
252b5132 6488{
29b0f896 6489 expressionS *exp;
252b5132
RH		 6490 segT exp_seg = 0;
6491 char *save_input_line_pointer;
f3c180ae 6492 char *gotfree_input_line;
40fb9820
L		 6493 int override;
6494 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6495 int ret;
252b5132 6496
31b2323c
L		 6497 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6498 {
6499 as_bad (_("at most %d displacement operands are allowed"),
6500 MAX_MEMORY_OPERANDS);
6501 return 0;
6502 }
6503
0dfbf9d7 6504 operand_type_set (&bigdisp, 0);
40fb9820
L		 6505 if ((i.types[this_operand].bitfield.jumpabsolute)
6506 || (!current_templates->start->opcode_modifier.jump
6507 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6508 {
40fb9820 6509 bigdisp.bitfield.disp32 = 1;
e05278af 6510 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6511 if (flag_code == CODE_64BIT)
6512 {
6513 if (!override)
6514 {
6515 bigdisp.bitfield.disp32s = 1;
6516 bigdisp.bitfield.disp64 = 1;
6517 }
6518 }
6519 else if ((flag_code == CODE_16BIT) ^ override)
6520 {
6521 bigdisp.bitfield.disp32 = 0;
6522 bigdisp.bitfield.disp16 = 1;
6523 }
e05278af
JB		 6524 }
6525 else
6526 {
6527 /* For PC-relative branches, the width of the displacement
6528 is dependent upon data size, not address size. */
e05278af 6529 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6530 if (flag_code == CODE_64BIT)
6531 {
6532 if (override || i.suffix == WORD_MNEM_SUFFIX)
6533 bigdisp.bitfield.disp16 = 1;
6534 else
6535 {
6536 bigdisp.bitfield.disp32 = 1;
6537 bigdisp.bitfield.disp32s = 1;
6538 }
6539 }
6540 else
e05278af
JB		 6541 {
6542 if (!override)
6543 override = (i.suffix == (flag_code != CODE_16BIT
6544 ? WORD_MNEM_SUFFIX
6545 : LONG_MNEM_SUFFIX));
40fb9820
L		 6546 bigdisp.bitfield.disp32 = 1;
6547 if ((flag_code == CODE_16BIT) ^ override)
6548 {
6549 bigdisp.bitfield.disp32 = 0;
6550 bigdisp.bitfield.disp16 = 1;
6551 }
e05278af 6552 }
e05278af 6553 }
c6fb90c8
L		 6554 i.types[this_operand] = operand_type_or (i.types[this_operand],
6555 bigdisp);
252b5132
RH		 6556
6557 exp = &disp_expressions[i.disp_operands];
520dc8e8 6558 i.op[this_operand].disps = exp;
252b5132
RH		 6559 i.disp_operands++;
6560 save_input_line_pointer = input_line_pointer;
6561 input_line_pointer = disp_start;
6562 END_STRING_AND_SAVE (disp_end);
6563
6564#ifndef GCC_ASM_O_HACK
6565#define GCC_ASM_O_HACK 0
6566#endif
6567#if GCC_ASM_O_HACK
6568 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6569 if (i.types[this_operand].bitfield.baseIndex
24eab124 6570 && displacement_string_end[-1] == '+')
252b5132
RH		 6571 {
6572 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6573 constraint within gcc asm statements.
6574 For instance:
6575
6576 #define _set_tssldt_desc(n,addr,limit,type) \
6577 __asm__ __volatile__ ( \
6578 "movw %w2,%0\n\t" \
6579 "movw %w1,2+%0\n\t" \
6580 "rorl $16,%1\n\t" \
6581 "movb %b1,4+%0\n\t" \
6582 "movb %4,5+%0\n\t" \
6583 "movb $0,6+%0\n\t" \
6584 "movb %h1,7+%0\n\t" \
6585 "rorl $16,%1" \
6586 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6587
6588 This works great except that the output assembler ends
6589 up looking a bit weird if it turns out that there is
6590 no offset. You end up producing code that looks like:
6591
6592 #APP
6593 movw $235,(%eax)
6594 movw %dx,2+(%eax)
6595 rorl $16,%edx
6596 movb %dl,4+(%eax)
6597 movb $137,5+(%eax)
6598 movb $0,6+(%eax)
6599 movb %dh,7+(%eax)
6600 rorl $16,%edx
6601 #NO_APP
6602
47926f60 6603 So here we provide the missing zero. */
24eab124
AM		 6604
6605 *displacement_string_end = '0';
252b5132
RH		 6606 }
6607#endif
3956db08 6608 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6609 if (gotfree_input_line)
6610 input_line_pointer = gotfree_input_line;
252b5132 6611
24eab124 6612 exp_seg = expression (exp);
252b5132 6613
636c26b0
AM		 6614 SKIP_WHITESPACE ();
6615 if (*input_line_pointer)
6616 as_bad (_("junk `%s' after expression"), input_line_pointer);
6617#if GCC_ASM_O_HACK
6618 RESTORE_END_STRING (disp_end + 1);
6619#endif
636c26b0 6620 input_line_pointer = save_input_line_pointer;
636c26b0 6621 if (gotfree_input_line)
ee86248c
JB		 6622 {
6623 free (gotfree_input_line);
6624
6625 if (exp->X_op == O_constant || exp->X_op == O_register)
6626 exp->X_op = O_illegal;
6627 }
6628
6629 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6630
6631 RESTORE_END_STRING (disp_end);
6632
6633 return ret;
6634}
6635
6636static int
6637i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6638 i386_operand_type types, const char *disp_start)
6639{
6640 i386_operand_type bigdisp;
6641 int ret = 1;
636c26b0 6642
24eab124
AM		 6643 /* We do this to make sure that the section symbol is in
6644 the symbol table. We will ultimately change the relocation
47926f60 6645 to be relative to the beginning of the section. */
1ae12ab7 6646 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6647 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6648 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6649 {
636c26b0 6650 if (exp->X_op != O_symbol)
3992d3b7 6651 goto inv_disp;
636c26b0 6652
e5cb08ac 6653 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6654 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6655 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6656 exp->X_op = O_subtract;
6657 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6658 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6659 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6660 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6661 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6662 else
29b0f896 6663 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6664 }
252b5132 6665
3992d3b7
AM		 6666 else if (exp->X_op == O_absent
6667 || exp->X_op == O_illegal
ee86248c 6668 || exp->X_op == O_big)
2daf4fd8 6669 {
3992d3b7
AM		 6670 inv_disp:
6671 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6672 disp_start);
3992d3b7 6673 ret = 0;
2daf4fd8
AM		 6674 }
6675
0e1147d9
L		 6676 else if (flag_code == CODE_64BIT
6677 && !i.prefix[ADDR_PREFIX]
6678 && exp->X_op == O_constant)
6679 {
6680 /* Since displacement is signed extended to 64bit, don't allow
6681 disp32 and turn off disp32s if they are out of range. */
6682 i.types[this_operand].bitfield.disp32 = 0;
6683 if (!fits_in_signed_long (exp->X_add_number))
6684 {
6685 i.types[this_operand].bitfield.disp32s = 0;
6686 if (i.types[this_operand].bitfield.baseindex)
6687 {
6688 as_bad (_("0x%lx out range of signed 32bit displacement"),
6689 (long) exp->X_add_number);
6690 ret = 0;
6691 }
6692 }
6693 }
6694
4c63da97 6695#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6696 else if (exp->X_op != O_constant
6697 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6698 && exp_seg != absolute_section
6699 && exp_seg != text_section
6700 && exp_seg != data_section
6701 && exp_seg != bss_section
6702 && exp_seg != undefined_section
6703 && !bfd_is_com_section (exp_seg))
24eab124 6704 {
d0b47220 6705 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6706 ret = 0;
24eab124 6707 }
252b5132 6708#endif
3956db08 6709
40fb9820
L		 6710 /* Check if this is a displacement only operand. */
6711 bigdisp = i.types[this_operand];
6712 bigdisp.bitfield.disp8 = 0;
6713 bigdisp.bitfield.disp16 = 0;
6714 bigdisp.bitfield.disp32 = 0;
6715 bigdisp.bitfield.disp32s = 0;
6716 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6717 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6718 i.types[this_operand] = operand_type_and (i.types[this_operand],
6719 types);
3956db08 6720
3992d3b7 6721 return ret;
252b5132
RH		 6722}
6723
eecb386c 6724/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6725 Return 1 on success, 0 on a failure. */
6726
252b5132 6727static int
e3bb37b5 6728i386_index_check (const char *operand_string)
252b5132 6729{
3e73aa7c 6730 int ok;
fc0763e6 6731 const char *kind = "base/index";
24eab124 6732#if INFER_ADDR_PREFIX
eecb386c
AM		 6733 int fudged = 0;
6734
24eab124
AM		 6735 tryprefix:
6736#endif
3e73aa7c 6737 ok = 1;
fc0763e6
JB		 6738 if (current_templates->start->opcode_modifier.isstring
6739 && !current_templates->start->opcode_modifier.immext
6740 && (current_templates->end[-1].opcode_modifier.isstring
6741 || i.mem_operands))
6742 {
6743 /* Memory operands of string insns are special in that they only allow
6744 a single register (rDI, rSI, or rBX) as their memory address. */
6745 unsigned int expected;
6746
6747 kind = "string address";
6748
6749 if (current_templates->start->opcode_modifier.w)
6750 {
6751 i386_operand_type type = current_templates->end[-1].operand_types[0];
6752
6753 if (!type.bitfield.baseindex
6754 || ((!i.mem_operands != !intel_syntax)
6755 && current_templates->end[-1].operand_types[1]
6756 .bitfield.baseindex))
6757 type = current_templates->end[-1].operand_types[1];
6758 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6759 }
6760 else
6761 expected = 3 /* rBX */;
6762
6763 if (!i.base_reg || i.index_reg
6764 || operand_type_check (i.types[this_operand], disp))
6765 ok = -1;
6766 else if (!(flag_code == CODE_64BIT
6767 ? i.prefix[ADDR_PREFIX]
6768 ? i.base_reg->reg_type.bitfield.reg32
6769 : i.base_reg->reg_type.bitfield.reg64
6770 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6771 ? i.base_reg->reg_type.bitfield.reg32
6772 : i.base_reg->reg_type.bitfield.reg16))
6773 ok = 0;
6774 else if (i.base_reg->reg_num != expected)
6775 ok = -1;
6776
6777 if (ok < 0)
6778 {
6779 unsigned int j;
6780
6781 for (j = 0; j < i386_regtab_size; ++j)
6782 if ((flag_code == CODE_64BIT
6783 ? i.prefix[ADDR_PREFIX]
6784 ? i386_regtab[j].reg_type.bitfield.reg32
6785 : i386_regtab[j].reg_type.bitfield.reg64
6786 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6787 ? i386_regtab[j].reg_type.bitfield.reg32
6788 : i386_regtab[j].reg_type.bitfield.reg16)
6789 && i386_regtab[j].reg_num == expected)
6790 break;
9c2799c2 6791 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6792 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6793 operand_string,
6794 intel_syntax ? '[' : '(',
6795 register_prefix,
6796 i386_regtab[j].reg_name,
6797 intel_syntax ? ']' : ')');
6798 ok = 1;
6799 }
6800 }
6801 else if (flag_code == CODE_64BIT)
64e74474 6802 {
64e74474 6803 if ((i.base_reg
40fb9820
L		 6804 && ((i.prefix[ADDR_PREFIX] == 0
6805 && !i.base_reg->reg_type.bitfield.reg64)
6806 || (i.prefix[ADDR_PREFIX]
6807 && !i.base_reg->reg_type.bitfield.reg32))
6808 && (i.index_reg
9a04903e
JB		 6809 || i.base_reg->reg_num !=
6810 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6811 || (i.index_reg
40fb9820
L		 6812 && (!i.index_reg->reg_type.bitfield.baseindex
6813 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6814 && i.index_reg->reg_num != RegRiz
6815 && !i.index_reg->reg_type.bitfield.reg64
6816 )
40fb9820 6817 || (i.prefix[ADDR_PREFIX]
db51cc60 6818 && i.index_reg->reg_num != RegEiz
40fb9820 6819 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6820 ok = 0;
3e73aa7c
JH		 6821 }
6822 else
6823 {
6824 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6825 {
6826 /* 16bit checks. */
6827 if ((i.base_reg
40fb9820
L		 6828 && (!i.base_reg->reg_type.bitfield.reg16
6829 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6830 || (i.index_reg
40fb9820
L		 6831 && (!i.index_reg->reg_type.bitfield.reg16
6832 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6833 || !(i.base_reg
6834 && i.base_reg->reg_num < 6
6835 && i.index_reg->reg_num >= 6
6836 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6837 ok = 0;
6838 }
6839 else
e5cb08ac 6840 {
3e73aa7c
JH		 6841 /* 32bit checks. */
6842 if ((i.base_reg
40fb9820 6843 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6844 || (i.index_reg
db51cc60
L		 6845 && ((!i.index_reg->reg_type.bitfield.reg32
6846 && i.index_reg->reg_num != RegEiz)
40fb9820 6847 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6848 ok = 0;
3e73aa7c
JH		 6849 }
6850 }
6851 if (!ok)
24eab124
AM		 6852 {
6853#if INFER_ADDR_PREFIX
fc0763e6 6854 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6855 {
6856 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6857 i.prefixes += 1;
b23bac36
AM		 6858 /* Change the size of any displacement too. At most one of
6859 Disp16 or Disp32 is set.
6860 FIXME. There doesn't seem to be any real need for separate
6861 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6862 Removing them would probably clean up the code quite a lot. */
4eed87de 6863 if (flag_code != CODE_64BIT
40fb9820
L		 6864 && (i.types[this_operand].bitfield.disp16
6865 || i.types[this_operand].bitfield.disp32))
6866 i.types[this_operand]
c6fb90c8 6867 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6868 fudged = 1;
24eab124
AM		 6869 goto tryprefix;
6870 }
eecb386c 6871 if (fudged)
fc0763e6
JB		 6872 as_bad (_("`%s' is not a valid %s expression"),
6873 operand_string,
6874 kind);
eecb386c 6875 else
c388dee8 6876#endif
fc0763e6 6877 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6878 operand_string,
fc0763e6
JB		 6879 flag_code_names[i.prefix[ADDR_PREFIX]
6880 ? flag_code == CODE_32BIT
6881 ? CODE_16BIT
6882 : CODE_32BIT
6883 : flag_code],
6884 kind);
24eab124 6885 }
20f0a1fc 6886 return ok;
24eab124 6887}
252b5132 6888
fc0763e6 6889/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6890 on error. */
252b5132 6891
252b5132 6892static int
a7619375 6893i386_att_operand (char *operand_string)
252b5132 6894{
af6bdddf
AM		 6895 const reg_entry *r;
6896 char *end_op;
24eab124 6897 char *op_string = operand_string;
252b5132 6898
24eab124 6899 if (is_space_char (*op_string))
252b5132
RH		 6900 ++op_string;
6901
24eab124 6902 /* We check for an absolute prefix (differentiating,
47926f60 6903 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6904 if (*op_string == ABSOLUTE_PREFIX)
6905 {
6906 ++op_string;
6907 if (is_space_char (*op_string))
6908 ++op_string;
40fb9820 6909 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6910 }
252b5132 6911
47926f60 6912 /* Check if operand is a register. */
4d1bb795 6913 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6914 {
40fb9820
L		 6915 i386_operand_type temp;
6916
24eab124
AM		 6917 /* Check for a segment override by searching for ':' after a
6918 segment register. */
6919 op_string = end_op;
6920 if (is_space_char (*op_string))
6921 ++op_string;
40fb9820
L		 6922 if (*op_string == ':'
6923 && (r->reg_type.bitfield.sreg2
6924 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6925 {
6926 switch (r->reg_num)
6927 {
6928 case 0:
6929 i.seg[i.mem_operands] = &es;
6930 break;
6931 case 1:
6932 i.seg[i.mem_operands] = &cs;
6933 break;
6934 case 2:
6935 i.seg[i.mem_operands] = &ss;
6936 break;
6937 case 3:
6938 i.seg[i.mem_operands] = &ds;
6939 break;
6940 case 4:
6941 i.seg[i.mem_operands] = &fs;
6942 break;
6943 case 5:
6944 i.seg[i.mem_operands] = &gs;
6945 break;
6946 }
252b5132 6947
24eab124 6948 /* Skip the ':' and whitespace. */
252b5132
RH		 6949 ++op_string;
6950 if (is_space_char (*op_string))
24eab124 6951 ++op_string;
252b5132 6952
24eab124
AM		 6953 if (!is_digit_char (*op_string)
6954 && !is_identifier_char (*op_string)
6955 && *op_string != '('
6956 && *op_string != ABSOLUTE_PREFIX)
6957 {
6958 as_bad (_("bad memory operand `%s'"), op_string);
6959 return 0;
6960 }
47926f60 6961 /* Handle case of %es:*foo. */
24eab124
AM		 6962 if (*op_string == ABSOLUTE_PREFIX)
6963 {
6964 ++op_string;
6965 if (is_space_char (*op_string))
6966 ++op_string;
40fb9820 6967 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6968 }
6969 goto do_memory_reference;
6970 }
6971 if (*op_string)
6972 {
d0b47220 6973 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6974 return 0;
6975 }
40fb9820
L		 6976 temp = r->reg_type;
6977 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6978 i.types[this_operand] = operand_type_or (i.types[this_operand],
6979 temp);
7d5e4556 6980 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6981 i.op[this_operand].regs = r;
24eab124
AM		 6982 i.reg_operands++;
6983 }
af6bdddf
AM		 6984 else if (*op_string == REGISTER_PREFIX)
6985 {
6986 as_bad (_("bad register name `%s'"), op_string);
6987 return 0;
6988 }
24eab124 6989 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6990 {
24eab124 6991 ++op_string;
40fb9820 6992 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6993 {
d0b47220 6994 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6995 return 0;
6996 }
6997 if (!i386_immediate (op_string))
6998 return 0;
6999 }
7000 else if (is_digit_char (*op_string)
7001 || is_identifier_char (*op_string)
e5cb08ac 7002 || *op_string == '(')
24eab124 7003 {
47926f60 7004 /* This is a memory reference of some sort. */
af6bdddf 7005 char *base_string;
252b5132 7006
47926f60 7007 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7008 char *displacement_string_start;
7009 char *displacement_string_end;
252b5132 7010
24eab124 7011 do_memory_reference:
24eab124 7012 if ((i.mem_operands == 1
40fb9820 7013 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7014 || i.mem_operands == 2)
7015 {
7016 as_bad (_("too many memory references for `%s'"),
7017 current_templates->start->name);
7018 return 0;
7019 }
252b5132 7020
24eab124
AM		 7021 /* Check for base index form. We detect the base index form by
7022 looking for an ')' at the end of the operand, searching
7023 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7024 after the '('. */
af6bdddf 7025 base_string = op_string + strlen (op_string);
c3332e24 7026
af6bdddf
AM		 7027 --base_string;
7028 if (is_space_char (*base_string))
7029 --base_string;
252b5132 7030
47926f60 7031 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7032 displacement_string_start = op_string;
7033 displacement_string_end = base_string + 1;
252b5132 7034
24eab124
AM		 7035 if (*base_string == ')')
7036 {
af6bdddf 7037 char *temp_string;
24eab124
AM		 7038 unsigned int parens_balanced = 1;
7039 /* We've already checked that the number of left & right ()'s are
47926f60 7040 equal, so this loop will not be infinite. */
24eab124
AM		 7041 do
7042 {
7043 base_string--;
7044 if (*base_string == ')')
7045 parens_balanced++;
7046 if (*base_string == '(')
7047 parens_balanced--;
7048 }
7049 while (parens_balanced);
c3332e24 7050
af6bdddf 7051 temp_string = base_string;
c3332e24 7052
24eab124 7053 /* Skip past '(' and whitespace. */
252b5132
RH		 7054 ++base_string;
7055 if (is_space_char (*base_string))
24eab124 7056 ++base_string;
252b5132 7057
af6bdddf 7058 if (*base_string == ','
4eed87de
AM		 7059 || ((i.base_reg = parse_register (base_string, &end_op))
7060 != NULL))
252b5132 7061 {
af6bdddf 7062 displacement_string_end = temp_string;
252b5132 7063
40fb9820 7064 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7065
af6bdddf 7066 if (i.base_reg)
24eab124 7067 {
24eab124
AM		 7068 base_string = end_op;
7069 if (is_space_char (*base_string))
7070 ++base_string;
af6bdddf
AM		 7071 }
7072
7073 /* There may be an index reg or scale factor here. */
7074 if (*base_string == ',')
7075 {
7076 ++base_string;
7077 if (is_space_char (*base_string))
7078 ++base_string;
7079
4eed87de
AM		 7080 if ((i.index_reg = parse_register (base_string, &end_op))
7081 != NULL)
24eab124 7082 {
af6bdddf 7083 base_string = end_op;
24eab124
AM		 7084 if (is_space_char (*base_string))
7085 ++base_string;
af6bdddf
AM		 7086 if (*base_string == ',')
7087 {
7088 ++base_string;
7089 if (is_space_char (*base_string))
7090 ++base_string;
7091 }
e5cb08ac 7092 else if (*base_string != ')')
af6bdddf 7093 {
4eed87de
AM		 7094 as_bad (_("expecting `,' or `)' "
7095 "after index register in `%s'"),
af6bdddf
AM		 7096 operand_string);
7097 return 0;
7098 }
24eab124 7099 }
af6bdddf 7100 else if (*base_string == REGISTER_PREFIX)
24eab124 7101 {
af6bdddf 7102 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7103 return 0;
7104 }
252b5132 7105
47926f60 7106 /* Check for scale factor. */
551c1ca1 7107 if (*base_string != ')')
af6bdddf 7108 {
551c1ca1
AM		 7109 char *end_scale = i386_scale (base_string);
7110
7111 if (!end_scale)
af6bdddf 7112 return 0;
24eab124 7113
551c1ca1 7114 base_string = end_scale;
af6bdddf
AM		 7115 if (is_space_char (*base_string))
7116 ++base_string;
7117 if (*base_string != ')')
7118 {
4eed87de
AM		 7119 as_bad (_("expecting `)' "
7120 "after scale factor in `%s'"),
af6bdddf
AM		 7121 operand_string);
7122 return 0;
7123 }
7124 }
7125 else if (!i.index_reg)
24eab124 7126 {
4eed87de
AM		 7127 as_bad (_("expecting index register or scale factor "
7128 "after `,'; got '%c'"),
af6bdddf 7129 *base_string);
24eab124
AM		 7130 return 0;
7131 }
7132 }
af6bdddf 7133 else if (*base_string != ')')
24eab124 7134 {
4eed87de
AM		 7135 as_bad (_("expecting `,' or `)' "
7136 "after base register in `%s'"),
af6bdddf 7137 operand_string);
24eab124
AM		 7138 return 0;
7139 }
c3332e24 7140 }
af6bdddf 7141 else if (*base_string == REGISTER_PREFIX)
c3332e24 7142 {
af6bdddf 7143 as_bad (_("bad register name `%s'"), base_string);
24eab124 7144 return 0;
c3332e24 7145 }
24eab124
AM		 7146 }
7147
7148 /* If there's an expression beginning the operand, parse it,
7149 assuming displacement_string_start and
7150 displacement_string_end are meaningful. */
7151 if (displacement_string_start != displacement_string_end)
7152 {
7153 if (!i386_displacement (displacement_string_start,
7154 displacement_string_end))
7155 return 0;
7156 }
7157
7158 /* Special case for (%dx) while doing input/output op. */
7159 if (i.base_reg
0dfbf9d7
L		 7160 && operand_type_equal (&i.base_reg->reg_type,
7161 &reg16_inoutportreg)
24eab124
AM		 7162 && i.index_reg == 0
7163 && i.log2_scale_factor == 0
7164 && i.seg[i.mem_operands] == 0
40fb9820 7165 && !operand_type_check (i.types[this_operand], disp))
24eab124 7166 {
65da13b5 7167 i.types[this_operand] = inoutportreg;
24eab124
AM		 7168 return 1;
7169 }
7170
eecb386c
AM		 7171 if (i386_index_check (operand_string) == 0)
7172 return 0;
5c07affc 7173 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7174 i.mem_operands++;
7175 }
7176 else
ce8a8b2f
AM		 7177 {
7178 /* It's not a memory operand; argh! */
24eab124
AM		 7179 as_bad (_("invalid char %s beginning operand %d `%s'"),
7180 output_invalid (*op_string),
7181 this_operand + 1,
7182 op_string);
7183 return 0;
7184 }
47926f60 7185 return 1; /* Normal return. */
252b5132
RH		 7186}
7187\f
ee7fcc42
AM		 7188/* md_estimate_size_before_relax()
7189
7190 Called just before relax() for rs_machine_dependent frags. The x86
7191 assembler uses these frags to handle variable size jump
7192 instructions.
7193
7194 Any symbol that is now undefined will not become defined.
7195 Return the correct fr_subtype in the frag.
7196 Return the initial "guess for variable size of frag" to caller.
7197 The guess is actually the growth beyond the fixed part. Whatever
7198 we do to grow the fixed or variable part contributes to our
7199 returned value. */
7200
252b5132
RH		 7201int
7202md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7203 fragS *fragP;
7204 segT segment;
252b5132 7205{
252b5132 7206 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7207 check for un-relaxable symbols. On an ELF system, we can't relax
7208 an externally visible symbol, because it may be overridden by a
7209 shared library. */
7210 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7211#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7212 || (IS_ELF
31312f95 7213 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7214 || S_IS_WEAK (fragP->fr_symbol)
7215 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7216 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7217#endif
7218#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7219 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7220 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7221#endif
7222 )
252b5132 7223 {
b98ef147
AM		 7224 /* Symbol is undefined in this segment, or we need to keep a
7225 reloc so that weak symbols can be overridden. */
7226 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7227 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7228 unsigned char *opcode;
7229 int old_fr_fix;
f6af82bd 7230
ee7fcc42 7231 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7232 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7233 else if (size == 2)
f6af82bd
AM		 7234 reloc_type = BFD_RELOC_16_PCREL;
7235 else
7236 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7237
ee7fcc42
AM		 7238 old_fr_fix = fragP->fr_fix;
7239 opcode = (unsigned char *) fragP->fr_opcode;
7240
fddf5b5b 7241 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7242 {
fddf5b5b
AM		 7243 case UNCOND_JUMP:
7244 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7245 opcode[0] = 0xe9;
252b5132 7246 fragP->fr_fix += size;
062cd5e7
AS		 7247 fix_new (fragP, old_fr_fix, size,
7248 fragP->fr_symbol,
7249 fragP->fr_offset, 1,
7250 reloc_type);
252b5132
RH		 7251 break;
7252
fddf5b5b 7253 case COND_JUMP86:
412167cb
AM		 7254 if (size == 2
7255 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7256 {
7257 /* Negate the condition, and branch past an
7258 unconditional jump. */
7259 opcode[0] ^= 1;
7260 opcode[1] = 3;
7261 /* Insert an unconditional jump. */
7262 opcode[2] = 0xe9;
7263 /* We added two extra opcode bytes, and have a two byte
7264 offset. */
7265 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7266 fix_new (fragP, old_fr_fix + 2, 2,
7267 fragP->fr_symbol,
7268 fragP->fr_offset, 1,
7269 reloc_type);
fddf5b5b
AM		 7270 break;
7271 }
7272 /* Fall through. */
7273
7274 case COND_JUMP:
412167cb
AM		 7275 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7276 {
3e02c1cc
AM		 7277 fixS *fixP;
7278
412167cb 7279 fragP->fr_fix += 1;
3e02c1cc
AM		 7280 fixP = fix_new (fragP, old_fr_fix, 1,
7281 fragP->fr_symbol,
7282 fragP->fr_offset, 1,
7283 BFD_RELOC_8_PCREL);
7284 fixP->fx_signed = 1;
412167cb
AM		 7285 break;
7286 }
93c2a809 7287
24eab124 7288 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7289 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7290 opcode[1] = opcode[0] + 0x10;
f6af82bd 7291 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7292 /* We've added an opcode byte. */
7293 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7294 fix_new (fragP, old_fr_fix + 1, size,
7295 fragP->fr_symbol,
7296 fragP->fr_offset, 1,
7297 reloc_type);
252b5132 7298 break;
fddf5b5b
AM		 7299
7300 default:
7301 BAD_CASE (fragP->fr_subtype);
7302 break;
252b5132
RH		 7303 }
7304 frag_wane (fragP);
ee7fcc42 7305 return fragP->fr_fix - old_fr_fix;
252b5132 7306 }
93c2a809 7307
93c2a809
AM		 7308 /* Guess size depending on current relax state. Initially the relax
7309 state will correspond to a short jump and we return 1, because
7310 the variable part of the frag (the branch offset) is one byte
7311 long. However, we can relax a section more than once and in that
7312 case we must either set fr_subtype back to the unrelaxed state,
7313 or return the value for the appropriate branch. */
7314 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7315}
7316
47926f60
KH		 7317/* Called after relax() is finished.
7318
7319 In: Address of frag.
7320 fr_type == rs_machine_dependent.
7321 fr_subtype is what the address relaxed to.
7322
7323 Out: Any fixSs and constants are set up.
7324 Caller will turn frag into a ".space 0". */
7325
252b5132
RH		 7326void
7327md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7328 bfd *abfd ATTRIBUTE_UNUSED;
7329 segT sec ATTRIBUTE_UNUSED;
29b0f896 7330 fragS *fragP;
252b5132 7331{
29b0f896 7332 unsigned char *opcode;
252b5132 7333 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7334 offsetT target_address;
7335 offsetT opcode_address;
252b5132 7336 unsigned int extension = 0;
847f7ad4 7337 offsetT displacement_from_opcode_start;
252b5132
RH		 7338
7339 opcode = (unsigned char *) fragP->fr_opcode;
7340
47926f60 7341 /* Address we want to reach in file space. */
252b5132 7342 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7343
47926f60 7344 /* Address opcode resides at in file space. */
252b5132
RH		 7345 opcode_address = fragP->fr_address + fragP->fr_fix;
7346
47926f60 7347 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7348 displacement_from_opcode_start = target_address - opcode_address;
7349
fddf5b5b 7350 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7351 {
47926f60
KH		 7352 /* Don't have to change opcode. */
7353 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7354 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7355 }
7356 else
7357 {
7358 if (no_cond_jump_promotion
7359 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7360 as_warn_where (fragP->fr_file, fragP->fr_line,
7361 _("long jump required"));
252b5132 7362
fddf5b5b
AM		 7363 switch (fragP->fr_subtype)
7364 {
7365 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7366 extension = 4; /* 1 opcode + 4 displacement */
7367 opcode[0] = 0xe9;
7368 where_to_put_displacement = &opcode[1];
7369 break;
252b5132 7370
fddf5b5b
AM		 7371 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7372 extension = 2; /* 1 opcode + 2 displacement */
7373 opcode[0] = 0xe9;
7374 where_to_put_displacement = &opcode[1];
7375 break;
252b5132 7376
fddf5b5b
AM		 7377 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7378 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7379 extension = 5; /* 2 opcode + 4 displacement */
7380 opcode[1] = opcode[0] + 0x10;
7381 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7382 where_to_put_displacement = &opcode[2];
7383 break;
252b5132 7384
fddf5b5b
AM		 7385 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7386 extension = 3; /* 2 opcode + 2 displacement */
7387 opcode[1] = opcode[0] + 0x10;
7388 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7389 where_to_put_displacement = &opcode[2];
7390 break;
252b5132 7391
fddf5b5b
AM		 7392 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7393 extension = 4;
7394 opcode[0] ^= 1;
7395 opcode[1] = 3;
7396 opcode[2] = 0xe9;
7397 where_to_put_displacement = &opcode[3];
7398 break;
7399
7400 default:
7401 BAD_CASE (fragP->fr_subtype);
7402 break;
7403 }
252b5132 7404 }
fddf5b5b 7405
7b81dfbb
AJ		 7406 /* If size if less then four we are sure that the operand fits,
7407 but if it's 4, then it could be that the displacement is larger
7408 then -/+ 2GB. */
7409 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7410 && object_64bit
7411 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7412 + ((addressT) 1 << 31))
7413 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7414 {
7415 as_bad_where (fragP->fr_file, fragP->fr_line,
7416 _("jump target out of range"));
7417 /* Make us emit 0. */
7418 displacement_from_opcode_start = extension;
7419 }
47926f60 7420 /* Now put displacement after opcode. */
252b5132
RH		 7421 md_number_to_chars ((char *) where_to_put_displacement,
7422 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7423 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7424 fragP->fr_fix += extension;
7425}
7426\f
252b5132
RH		 7427/* Apply a fixup (fixS) to segment data, once it has been determined
7428 by our caller that we have all the info we need to fix it up.
7429
7430 On the 386, immediates, displacements, and data pointers are all in
7431 the same (little-endian) format, so we don't need to care about which
7432 we are handling. */
7433
94f592af 7434void
55cf6793 7435md_apply_fix (fixP, valP, seg)
47926f60
KH		 7436 /* The fix we're to put in. */
7437 fixS *fixP;
47926f60 7438 /* Pointer to the value of the bits. */
c6682705 7439 valueT *valP;
47926f60
KH		 7440 /* Segment fix is from. */
7441 segT seg ATTRIBUTE_UNUSED;
252b5132 7442{
94f592af 7443 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7444 valueT value = *valP;
252b5132 7445
f86103b7 7446#if !defined (TE_Mach)
93382f6d
AM		 7447 if (fixP->fx_pcrel)
7448 {
7449 switch (fixP->fx_r_type)
7450 {
5865bb77
ILT		 7451 default:
7452 break;
7453
d6ab8113
JB		 7454 case BFD_RELOC_64:
7455 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7456 break;
93382f6d 7457 case BFD_RELOC_32:
ae8887b5 7458 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7459 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7460 break;
7461 case BFD_RELOC_16:
7462 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7463 break;
7464 case BFD_RELOC_8:
7465 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7466 break;
7467 }
7468 }
252b5132 7469
a161fe53 7470 if (fixP->fx_addsy != NULL
31312f95 7471 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7472 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7473 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7474 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7475 && !use_rela_relocations)
252b5132 7476 {
31312f95
AM		 7477 /* This is a hack. There should be a better way to handle this.
7478 This covers for the fact that bfd_install_relocation will
7479 subtract the current location (for partial_inplace, PC relative
7480 relocations); see more below. */
252b5132 7481#ifndef OBJ_AOUT
718ddfc0 7482 if (IS_ELF
252b5132
RH		 7483#ifdef TE_PE
7484 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7485#endif
7486 )
7487 value += fixP->fx_where + fixP->fx_frag->fr_address;
7488#endif
7489#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7490 if (IS_ELF)
252b5132 7491 {
6539b54b 7492 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7493
6539b54b 7494 if ((sym_seg == seg
2f66722d 7495 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7496 && sym_seg != absolute_section))
af65af87 7497 && !generic_force_reloc (fixP))
2f66722d
AM		 7498 {
7499 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7500 bfd_install_relocation subtracts them out again. I think
7501 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7502 it. FIXME. */
7503 value += fixP->fx_where + fixP->fx_frag->fr_address;
7504 }
252b5132
RH		 7505 }
7506#endif
7507#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7508 /* For some reason, the PE format does not store a
7509 section address offset for a PC relative symbol. */
7510 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7511 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7512 value += md_pcrel_from (fixP);
7513#endif
7514 }
fbeb56a4
DK		 7515#if defined (OBJ_COFF) && defined (TE_PE)
7516 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7517 {
7518 value -= S_GET_VALUE (fixP->fx_addsy);
7519 }
7520#endif
252b5132
RH		 7521
7522 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7523 and we must not disappoint it. */
252b5132 7524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7525 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7526 switch (fixP->fx_r_type)
7527 {
7528 case BFD_RELOC_386_PLT32:
3e73aa7c 7529 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7530 /* Make the jump instruction point to the address of the operand. At
7531 runtime we merely add the offset to the actual PLT entry. */
7532 value = -4;
7533 break;
31312f95 7534
13ae64f3
JJ		 7535 case BFD_RELOC_386_TLS_GD:
7536 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7537 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7538 case BFD_RELOC_386_TLS_IE:
7539 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7540 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7541 case BFD_RELOC_X86_64_TLSGD:
7542 case BFD_RELOC_X86_64_TLSLD:
7543 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7544 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7545 value = 0; /* Fully resolved at runtime. No addend. */
7546 /* Fallthrough */
7547 case BFD_RELOC_386_TLS_LE:
7548 case BFD_RELOC_386_TLS_LDO_32:
7549 case BFD_RELOC_386_TLS_LE_32:
7550 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7551 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7552 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7553 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7554 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7555 break;
7556
67a4f2b7
AO		 7557 case BFD_RELOC_386_TLS_DESC_CALL:
7558 case BFD_RELOC_X86_64_TLSDESC_CALL:
7559 value = 0; /* Fully resolved at runtime. No addend. */
7560 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7561 fixP->fx_done = 0;
7562 return;
7563
00f7efb6
JJ		 7564 case BFD_RELOC_386_GOT32:
7565 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7566 value = 0; /* Fully resolved at runtime. No addend. */
7567 break;
47926f60
KH		 7568
7569 case BFD_RELOC_VTABLE_INHERIT:
7570 case BFD_RELOC_VTABLE_ENTRY:
7571 fixP->fx_done = 0;
94f592af 7572 return;
47926f60
KH		 7573
7574 default:
7575 break;
7576 }
7577#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7578 *valP = value;
f86103b7 7579#endif /* !defined (TE_Mach) */
3e73aa7c 7580
3e73aa7c 7581 /* Are we finished with this relocation now? */
c6682705 7582 if (fixP->fx_addsy == NULL)
3e73aa7c 7583 fixP->fx_done = 1;
fbeb56a4
DK		 7584#if defined (OBJ_COFF) && defined (TE_PE)
7585 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7586 {
7587 fixP->fx_done = 0;
7588 /* Remember value for tc_gen_reloc. */
7589 fixP->fx_addnumber = value;
7590 /* Clear out the frag for now. */
7591 value = 0;
7592 }
7593#endif
3e73aa7c
JH		 7594 else if (use_rela_relocations)
7595 {
7596 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7597 /* Remember value for tc_gen_reloc. */
7598 fixP->fx_addnumber = value;
3e73aa7c
JH		 7599 value = 0;
7600 }
f86103b7 7601
94f592af 7602 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7603}
252b5132 7604\f
252b5132 7605char *
499ac353 7606md_atof (int type, char *litP, int *sizeP)
252b5132 7607{
499ac353
NC		 7608 /* This outputs the LITTLENUMs in REVERSE order;
7609 in accord with the bigendian 386. */
7610 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7611}
7612\f
2d545b82 7613static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7614
252b5132 7615static char *
e3bb37b5 7616output_invalid (int c)
252b5132 7617{
3882b010 7618 if (ISPRINT (c))
f9f21a03
L		 7619 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7620 "'%c'", c);
252b5132 7621 else
f9f21a03 7622 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7623 "(0x%x)", (unsigned char) c);
252b5132
RH		 7624 return output_invalid_buf;
7625}
7626
af6bdddf 7627/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7628
7629static const reg_entry *
4d1bb795 7630parse_real_register (char *reg_string, char **end_op)
252b5132 7631{
af6bdddf
AM		 7632 char *s = reg_string;
7633 char *p;
252b5132
RH		 7634 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7635 const reg_entry *r;
7636
7637 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7638 if (*s == REGISTER_PREFIX)
7639 ++s;
7640
7641 if (is_space_char (*s))
7642 ++s;
7643
7644 p = reg_name_given;
af6bdddf 7645 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7646 {
7647 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7648 return (const reg_entry *) NULL;
7649 s++;
252b5132
RH		 7650 }
7651
6588847e
DN		 7652 /* For naked regs, make sure that we are not dealing with an identifier.
7653 This prevents confusing an identifier like `eax_var' with register
7654 `eax'. */
7655 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7656 return (const reg_entry *) NULL;
7657
af6bdddf 7658 *end_op = s;
252b5132
RH		 7659
7660 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7661
5f47d35b 7662 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7663 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7664 {
5f47d35b
AM		 7665 if (is_space_char (*s))
7666 ++s;
7667 if (*s == '(')
7668 {
af6bdddf 7669 ++s;
5f47d35b
AM		 7670 if (is_space_char (*s))
7671 ++s;
7672 if (*s >= '0' && *s <= '7')
7673 {
db557034 7674 int fpr = *s - '0';
af6bdddf 7675 ++s;
5f47d35b
AM		 7676 if (is_space_char (*s))
7677 ++s;
7678 if (*s == ')')
7679 {
7680 *end_op = s + 1;
1e9cc1c2 7681 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7682 know (r);
7683 return r + fpr;
5f47d35b 7684 }
5f47d35b 7685 }
47926f60 7686 /* We have "%st(" then garbage. */
5f47d35b
AM		 7687 return (const reg_entry *) NULL;
7688 }
7689 }
7690
a60de03c
JB		 7691 if (r == NULL || allow_pseudo_reg)
7692 return r;
7693
0dfbf9d7 7694 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7695 return (const reg_entry *) NULL;
7696
192dc9c6
JB		 7697 if ((r->reg_type.bitfield.reg32
7698 || r->reg_type.bitfield.sreg3
7699 || r->reg_type.bitfield.control
7700 || r->reg_type.bitfield.debug
7701 || r->reg_type.bitfield.test)
7702 && !cpu_arch_flags.bitfield.cpui386)
7703 return (const reg_entry *) NULL;
7704
309d3373
JB		 7705 if (r->reg_type.bitfield.floatreg
7706 && !cpu_arch_flags.bitfield.cpu8087
7707 && !cpu_arch_flags.bitfield.cpu287
7708 && !cpu_arch_flags.bitfield.cpu387)
7709 return (const reg_entry *) NULL;
7710
192dc9c6
JB		 7711 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7712 return (const reg_entry *) NULL;
7713
7714 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7715 return (const reg_entry *) NULL;
7716
40f12533
L		 7717 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7718 return (const reg_entry *) NULL;
7719
db51cc60 7720 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7721 if (!allow_index_reg
db51cc60
L		 7722 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7723 return (const reg_entry *) NULL;
7724
a60de03c
JB		 7725 if (((r->reg_flags & (RegRex64 | RegRex))
7726 || r->reg_type.bitfield.reg64)
40fb9820 7727 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7728 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7729 && flag_code != CODE_64BIT)
20f0a1fc 7730 return (const reg_entry *) NULL;
1ae00879 7731
b7240065
JB		 7732 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7733 return (const reg_entry *) NULL;
7734
252b5132
RH		 7735 return r;
7736}
4d1bb795
JB		 7737
7738/* REG_STRING starts *before* REGISTER_PREFIX. */
7739
7740static const reg_entry *
7741parse_register (char *reg_string, char **end_op)
7742{
7743 const reg_entry *r;
7744
7745 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7746 r = parse_real_register (reg_string, end_op);
7747 else
7748 r = NULL;
7749 if (!r)
7750 {
7751 char *save = input_line_pointer;
7752 char c;
7753 symbolS *symbolP;
7754
7755 input_line_pointer = reg_string;
7756 c = get_symbol_end ();
7757 symbolP = symbol_find (reg_string);
7758 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7759 {
7760 const expressionS *e = symbol_get_value_expression (symbolP);
7761
7762 know (e->X_op == O_register);
4eed87de 7763 know (e->X_add_number >= 0
c3fe08fa 7764 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7765 r = i386_regtab + e->X_add_number;
7766 *end_op = input_line_pointer;
7767 }
7768 *input_line_pointer = c;
7769 input_line_pointer = save;
7770 }
7771 return r;
7772}
7773
7774int
7775i386_parse_name (char *name, expressionS *e, char *nextcharP)
7776{
7777 const reg_entry *r;
7778 char *end = input_line_pointer;
7779
7780 *end = *nextcharP;
7781 r = parse_register (name, &input_line_pointer);
7782 if (r && end <= input_line_pointer)
7783 {
7784 *nextcharP = *input_line_pointer;
7785 *input_line_pointer = 0;
7786 e->X_op = O_register;
7787 e->X_add_number = r - i386_regtab;
7788 return 1;
7789 }
7790 input_line_pointer = end;
7791 *end = 0;
ee86248c 7792 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7793}
7794
7795void
7796md_operand (expressionS *e)
7797{
ee86248c
JB		 7798 char *end;
7799 const reg_entry *r;
4d1bb795 7800
ee86248c
JB		 7801 switch (*input_line_pointer)
7802 {
7803 case REGISTER_PREFIX:
7804 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7805 if (r)
7806 {
7807 e->X_op = O_register;
7808 e->X_add_number = r - i386_regtab;
7809 input_line_pointer = end;
7810 }
ee86248c
JB		 7811 break;
7812
7813 case '[':
9c2799c2 7814 gas_assert (intel_syntax);
ee86248c
JB		 7815 end = input_line_pointer++;
7816 expression (e);
7817 if (*input_line_pointer == ']')
7818 {
7819 ++input_line_pointer;
7820 e->X_op_symbol = make_expr_symbol (e);
7821 e->X_add_symbol = NULL;
7822 e->X_add_number = 0;
7823 e->X_op = O_index;
7824 }
7825 else
7826 {
7827 e->X_op = O_absent;
7828 input_line_pointer = end;
7829 }
7830 break;
4d1bb795
JB		 7831 }
7832}
7833
252b5132 7834\f
4cc782b5 7835#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7836const char *md_shortopts = "kVQ:sqn";
252b5132 7837#else
12b55ccc 7838const char *md_shortopts = "qn";
252b5132 7839#endif
6e0b89ee 7840
3e73aa7c 7841#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7842#define OPTION_64 (OPTION_MD_BASE + 1)
7843#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7844#define OPTION_MARCH (OPTION_MD_BASE + 3)
7845#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7846#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7847#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7848#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7849#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7850#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7851#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7852#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7853
99ad8390
NC		 7854struct option md_longopts[] =
7855{
3e73aa7c 7856 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7857#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7858 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7859 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7860#endif
b3b91714 7861 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7862 {"march", required_argument, NULL, OPTION_MARCH},
7863 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7864 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7865 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7866 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7867 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7868 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7869 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7870 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7871 {NULL, no_argument, NULL, 0}
7872};
7873size_t md_longopts_size = sizeof (md_longopts);
7874
7875int
9103f4f4 7876md_parse_option (int c, char *arg)
252b5132 7877{
9103f4f4 7878 unsigned int i;
6305a203 7879 char *arch, *next;
9103f4f4 7880
252b5132
RH		 7881 switch (c)
7882 {
12b55ccc
L		 7883 case 'n':
7884 optimize_align_code = 0;
7885 break;
7886
a38cf1db
AM		 7887 case 'q':
7888 quiet_warnings = 1;
252b5132
RH		 7889 break;
7890
7891#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7892 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7893 should be emitted or not. FIXME: Not implemented. */
7894 case 'Q':
252b5132
RH		 7895 break;
7896
7897 /* -V: SVR4 argument to print version ID. */
7898 case 'V':
7899 print_version_id ();
7900 break;
7901
a38cf1db
AM		 7902 /* -k: Ignore for FreeBSD compatibility. */
7903 case 'k':
252b5132 7904 break;
4cc782b5
ILT		 7905
7906 case 's':
7907 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7908 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7909 break;
99ad8390 7910#endif
321098a5
L		 7911#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7912 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7913 case OPTION_64:
7914 {
7915 const char **list, **l;
7916
3e73aa7c
JH		 7917 list = bfd_target_list ();
7918 for (l = list; *l != NULL; l++)
8620418b 7919 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7920 || strcmp (*l, "coff-x86-64") == 0
7921 || strcmp (*l, "pe-x86-64") == 0
7922 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7923 {
7924 default_arch = "x86_64";
7925 break;
7926 }
3e73aa7c 7927 if (*l == NULL)
6e0b89ee 7928 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7929 free (list);
7930 }
7931 break;
7932#endif
252b5132 7933
6e0b89ee
AM		 7934 case OPTION_32:
7935 default_arch = "i386";
7936 break;
7937
b3b91714
AM		 7938 case OPTION_DIVIDE:
7939#ifdef SVR4_COMMENT_CHARS
7940 {
7941 char *n, *t;
7942 const char *s;
7943
7944 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7945 t = n;
7946 for (s = i386_comment_chars; *s != '\0'; s++)
7947 if (*s != '/')
7948 *t++ = *s;
7949 *t = '\0';
7950 i386_comment_chars = n;
7951 }
7952#endif
7953 break;
7954
9103f4f4 7955 case OPTION_MARCH:
6305a203
L		 7956 arch = xstrdup (arg);
7957 do
9103f4f4 7958 {
6305a203
L		 7959 if (*arch == '.')
7960 as_fatal (_("Invalid -march= option: `%s'"), arg);
7961 next = strchr (arch, '+');
7962 if (next)
7963 *next++ = '\0';
7964 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7965 {
6305a203 7966 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7967 {
6305a203
L		 7968 /* Processor. */
7969 cpu_arch_name = cpu_arch[i].name;
7970 cpu_sub_arch_name = NULL;
7971 cpu_arch_flags = cpu_arch[i].flags;
7972 cpu_arch_isa = cpu_arch[i].type;
7973 cpu_arch_isa_flags = cpu_arch[i].flags;
7974 if (!cpu_arch_tune_set)
7975 {
7976 cpu_arch_tune = cpu_arch_isa;
7977 cpu_arch_tune_flags = cpu_arch_isa_flags;
7978 }
7979 break;
7980 }
7981 else if (*cpu_arch [i].name == '.'
7982 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7983 {
7984 /* ISA entension. */
7985 i386_cpu_flags flags;
309d3373
JB		 7986
7987 if (strncmp (arch, "no", 2))
7988 flags = cpu_flags_or (cpu_arch_flags,
7989 cpu_arch[i].flags);
7990 else
7991 flags = cpu_flags_and_not (cpu_arch_flags,
7992 cpu_arch[i].flags);
0dfbf9d7 7993 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7994 {
7995 if (cpu_sub_arch_name)
7996 {
7997 char *name = cpu_sub_arch_name;
7998 cpu_sub_arch_name = concat (name,
7999 cpu_arch[i].name,
1bf57e9f 8000 (const char *) NULL);
6305a203
L		 8001 free (name);
8002 }
8003 else
8004 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8005 cpu_arch_flags = flags;
8006 }
8007 break;
ccc9c027 8008 }
9103f4f4 8009 }
6305a203
L		 8010
8011 if (i >= ARRAY_SIZE (cpu_arch))
8012 as_fatal (_("Invalid -march= option: `%s'"), arg);
8013
8014 arch = next;
9103f4f4 8015 }
6305a203 8016 while (next != NULL );
9103f4f4
L		 8017 break;
8018
8019 case OPTION_MTUNE:
8020 if (*arg == '.')
8021 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8022 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8023 {
8024 if (strcmp (arg, cpu_arch [i].name) == 0)
8025 {
ccc9c027 8026 cpu_arch_tune_set = 1;
9103f4f4
L		 8027 cpu_arch_tune = cpu_arch [i].type;
8028 cpu_arch_tune_flags = cpu_arch[i].flags;
8029 break;
8030 }
8031 }
8032 if (i >= ARRAY_SIZE (cpu_arch))
8033 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8034 break;
8035
1efbbeb4
L		 8036 case OPTION_MMNEMONIC:
8037 if (strcasecmp (arg, "att") == 0)
8038 intel_mnemonic = 0;
8039 else if (strcasecmp (arg, "intel") == 0)
8040 intel_mnemonic = 1;
8041 else
8042 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8043 break;
8044
8045 case OPTION_MSYNTAX:
8046 if (strcasecmp (arg, "att") == 0)
8047 intel_syntax = 0;
8048 else if (strcasecmp (arg, "intel") == 0)
8049 intel_syntax = 1;
8050 else
8051 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8052 break;
8053
8054 case OPTION_MINDEX_REG:
8055 allow_index_reg = 1;
8056 break;
8057
8058 case OPTION_MNAKED_REG:
8059 allow_naked_reg = 1;
8060 break;
8061
8062 case OPTION_MOLD_GCC:
8063 old_gcc = 1;
1efbbeb4
L		 8064 break;
8065
c0f3af97
L		 8066 case OPTION_MSSE2AVX:
8067 sse2avx = 1;
8068 break;
8069
daf50ae7
L		 8070 case OPTION_MSSE_CHECK:
8071 if (strcasecmp (arg, "error") == 0)
8072 sse_check = sse_check_error;
8073 else if (strcasecmp (arg, "warning") == 0)
8074 sse_check = sse_check_warning;
8075 else if (strcasecmp (arg, "none") == 0)
8076 sse_check = sse_check_none;
8077 else
8078 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8079 break;
8080
252b5132
RH		 8081 default:
8082 return 0;
8083 }
8084 return 1;
8085}
8086
8087void
8088md_show_usage (stream)
8089 FILE *stream;
8090{
4cc782b5
ILT		 8091#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8092 fprintf (stream, _("\
a38cf1db
AM		 8093 -Q ignored\n\
8094 -V print assembler version number\n\
b3b91714
AM		 8095 -k ignored\n"));
8096#endif
8097 fprintf (stream, _("\
12b55ccc 8098 -n Do not optimize code alignment\n\
b3b91714
AM		 8099 -q quieten some warnings\n"));
8100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8101 fprintf (stream, _("\
a38cf1db 8102 -s ignored\n"));
b3b91714 8103#endif
321098a5
L		 8104#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8105 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8106 fprintf (stream, _("\
8107 --32/--64 generate 32bit/64bit code\n"));
8108#endif
b3b91714
AM		 8109#ifdef SVR4_COMMENT_CHARS
8110 fprintf (stream, _("\
8111 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8112#else
8113 fprintf (stream, _("\
b3b91714 8114 --divide ignored\n"));
4cc782b5 8115#endif
9103f4f4 8116 fprintf (stream, _("\
6305a203
L		 8117 -march=CPU[,+EXTENSION...]\n\
8118 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8119 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8120 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8121 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8122 amdfam10, generic32, generic64\n\
599121aa 8123 EXTENSION is combination of:\n\
309d3373
JB		 8124 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8125 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8126 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 8127 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
f0ae4a24 8128 svme, abm, padlock, fma4, xop, lwp\n"));
6305a203 8129 fprintf (stream, _("\
2cb4f3d5
L		 8130 -mtune=CPU optimize for CPU, CPU is one of:\n\
8131 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8132 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8133 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8134 amdfam10, generic32, generic64\n"));
ba104c83 8135 fprintf (stream, _("\
c0f3af97
L		 8136 -msse2avx encode SSE instructions with VEX prefix\n"));
8137 fprintf (stream, _("\
daf50ae7
L		 8138 -msse-check=[none|error|warning]\n\
8139 check SSE instructions\n"));
8140 fprintf (stream, _("\
ba104c83
L		 8141 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8142 fprintf (stream, _("\
8143 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8144 fprintf (stream, _("\
8145 -mindex-reg support pseudo index registers\n"));
8146 fprintf (stream, _("\
8147 -mnaked-reg don't require `%%' prefix for registers\n"));
8148 fprintf (stream, _("\
8149 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8150}
8151
3e73aa7c 8152#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8153 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8154 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8155
8156/* Pick the target format to use. */
8157
47926f60 8158const char *
e3bb37b5 8159i386_target_format (void)
252b5132 8160{
3e73aa7c 8161 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8162 {
8163 set_code_flag (CODE_64BIT);
0dfbf9d7 8164 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8165 {
8166 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8167 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8168 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8169 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8170 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8171 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8172 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8173 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8174 cpu_arch_isa_flags.bitfield.cpusse = 1;
8175 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8176 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8177 }
0dfbf9d7 8178 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8179 {
8180 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8181 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8182 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8183 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8184 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8185 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8186 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8187 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8188 cpu_arch_tune_flags.bitfield.cpusse = 1;
8189 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8190 }
9103f4f4 8191 }
3e73aa7c 8192 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8193 {
8194 set_code_flag (CODE_32BIT);
0dfbf9d7 8195 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8196 {
8197 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8198 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8199 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8200 }
0dfbf9d7 8201 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8202 {
8203 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8204 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8205 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8206 }
9103f4f4 8207 }
3e73aa7c
JH		 8208 else
8209 as_fatal (_("Unknown architecture"));
252b5132
RH		 8210 switch (OUTPUT_FLAVOR)
8211 {
9384f2ff 8212#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8213 case bfd_target_aout_flavour:
47926f60 8214 return AOUT_TARGET_FORMAT;
4c63da97 8215#endif
9384f2ff
AM		 8216#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8217# if defined (TE_PE) || defined (TE_PEP)
8218 case bfd_target_coff_flavour:
8219 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8220# elif defined (TE_GO32)
0561d57c
JK		 8221 case bfd_target_coff_flavour:
8222 return "coff-go32";
9384f2ff 8223# else
252b5132
RH		 8224 case bfd_target_coff_flavour:
8225 return "coff-i386";
9384f2ff 8226# endif
4c63da97 8227#endif
3e73aa7c 8228#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8229 case bfd_target_elf_flavour:
3e73aa7c 8230 {
e5cb08ac 8231 if (flag_code == CODE_64BIT)
4fa24527
JB		 8232 {
8233 object_64bit = 1;
8234 use_rela_relocations = 1;
8235 }
3632d14b 8236 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8237 {
8238 if (flag_code != CODE_64BIT)
8239 as_fatal (_("Intel L1OM is 64bit only"));
8240 return ELF_TARGET_L1OM_FORMAT;
8241 }
8242 else
8243 return (flag_code == CODE_64BIT
8244 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8245 }
e57f8c65
TG		 8246#endif
8247#if defined (OBJ_MACH_O)
8248 case bfd_target_mach_o_flavour:
8249 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8250#endif
252b5132
RH		 8251 default:
8252 abort ();
8253 return NULL;
8254 }
8255}
8256
47926f60 8257#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8258
8259#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8260void
8261i386_elf_emit_arch_note (void)
a847613f 8262{
718ddfc0 8263 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8264 {
8265 char *p;
8266 asection *seg = now_seg;
8267 subsegT subseg = now_subseg;
8268 Elf_Internal_Note i_note;
8269 Elf_External_Note e_note;
8270 asection *note_secp;
8271 int len;
8272
8273 /* Create the .note section. */
8274 note_secp = subseg_new (".note", 0);
8275 bfd_set_section_flags (stdoutput,
8276 note_secp,
8277 SEC_HAS_CONTENTS | SEC_READONLY);
8278
8279 /* Process the arch string. */
8280 len = strlen (cpu_arch_name);
8281
8282 i_note.namesz = len + 1;
8283 i_note.descsz = 0;
8284 i_note.type = NT_ARCH;
8285 p = frag_more (sizeof (e_note.namesz));
8286 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8287 p = frag_more (sizeof (e_note.descsz));
8288 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8289 p = frag_more (sizeof (e_note.type));
8290 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8291 p = frag_more (len + 1);
8292 strcpy (p, cpu_arch_name);
8293
8294 frag_align (2, 0, 0);
8295
8296 subseg_set (seg, subseg);
8297 }
8298}
8299#endif
252b5132 8300\f
252b5132
RH		 8301symbolS *
8302md_undefined_symbol (name)
8303 char *name;
8304{
18dc2407
ILT		 8305 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8306 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8307 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8308 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8309 {
8310 if (!GOT_symbol)
8311 {
8312 if (symbol_find (name))
8313 as_bad (_("GOT already in symbol table"));
8314 GOT_symbol = symbol_new (name, undefined_section,
8315 (valueT) 0, &zero_address_frag);
8316 };
8317 return GOT_symbol;
8318 }
252b5132
RH		 8319 return 0;
8320}
8321
8322/* Round up a section size to the appropriate boundary. */
47926f60 8323
252b5132
RH		 8324valueT
8325md_section_align (segment, size)
ab9da554 8326 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8327 valueT size;
8328{
4c63da97
AM		 8329#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8330 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8331 {
8332 /* For a.out, force the section size to be aligned. If we don't do
8333 this, BFD will align it for us, but it will not write out the
8334 final bytes of the section. This may be a bug in BFD, but it is
8335 easier to fix it here since that is how the other a.out targets
8336 work. */
8337 int align;
8338
8339 align = bfd_get_section_alignment (stdoutput, segment);
8340 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8341 }
252b5132
RH		 8342#endif
8343
8344 return size;
8345}
8346
8347/* On the i386, PC-relative offsets are relative to the start of the
8348 next instruction. That is, the address of the offset, plus its
8349 size, since the offset is always the last part of the insn. */
8350
8351long
e3bb37b5 8352md_pcrel_from (fixS *fixP)
252b5132
RH		 8353{
8354 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8355}
8356
8357#ifndef I386COFF
8358
8359static void
e3bb37b5 8360s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8361{
29b0f896 8362 int temp;
252b5132 8363
8a75718c
JB		 8364#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8365 if (IS_ELF)
8366 obj_elf_section_change_hook ();
8367#endif
252b5132
RH		 8368 temp = get_absolute_expression ();
8369 subseg_set (bss_section, (subsegT) temp);
8370 demand_empty_rest_of_line ();
8371}
8372
8373#endif
8374
252b5132 8375void
e3bb37b5 8376i386_validate_fix (fixS *fixp)
252b5132
RH		 8377{
8378 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8379 {
23df1078
JH		 8380 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8381 {
4fa24527 8382 if (!object_64bit)
23df1078
JH		 8383 abort ();
8384 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8385 }
8386 else
8387 {
4fa24527 8388 if (!object_64bit)
d6ab8113
JB		 8389 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8390 else
8391 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8392 }
252b5132
RH		 8393 fixp->fx_subsy = 0;
8394 }
8395}
8396
252b5132
RH		 8397arelent *
8398tc_gen_reloc (section, fixp)
ab9da554 8399 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8400 fixS *fixp;
8401{
8402 arelent *rel;
8403 bfd_reloc_code_real_type code;
8404
8405 switch (fixp->fx_r_type)
8406 {
3e73aa7c
JH		 8407 case BFD_RELOC_X86_64_PLT32:
8408 case BFD_RELOC_X86_64_GOT32:
8409 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8410 case BFD_RELOC_386_PLT32:
8411 case BFD_RELOC_386_GOT32:
8412 case BFD_RELOC_386_GOTOFF:
8413 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8414 case BFD_RELOC_386_TLS_GD:
8415 case BFD_RELOC_386_TLS_LDM:
8416 case BFD_RELOC_386_TLS_LDO_32:
8417 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8418 case BFD_RELOC_386_TLS_IE:
8419 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8420 case BFD_RELOC_386_TLS_LE_32:
8421 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8422 case BFD_RELOC_386_TLS_GOTDESC:
8423 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8424 case BFD_RELOC_X86_64_TLSGD:
8425 case BFD_RELOC_X86_64_TLSLD:
8426 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8427 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8428 case BFD_RELOC_X86_64_GOTTPOFF:
8429 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8430 case BFD_RELOC_X86_64_TPOFF64:
8431 case BFD_RELOC_X86_64_GOTOFF64:
8432 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8433 case BFD_RELOC_X86_64_GOT64:
8434 case BFD_RELOC_X86_64_GOTPCREL64:
8435 case BFD_RELOC_X86_64_GOTPC64:
8436 case BFD_RELOC_X86_64_GOTPLT64:
8437 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8438 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8439 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8440 case BFD_RELOC_RVA:
8441 case BFD_RELOC_VTABLE_ENTRY:
8442 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8443#ifdef TE_PE
8444 case BFD_RELOC_32_SECREL:
8445#endif
252b5132
RH		 8446 code = fixp->fx_r_type;
8447 break;
dbbaec26
L		 8448 case BFD_RELOC_X86_64_32S:
8449 if (!fixp->fx_pcrel)
8450 {
8451 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8452 code = fixp->fx_r_type;
8453 break;
8454 }
252b5132 8455 default:
93382f6d 8456 if (fixp->fx_pcrel)
252b5132 8457 {
93382f6d
AM		 8458 switch (fixp->fx_size)
8459 {
8460 default:
b091f402
AM		 8461 as_bad_where (fixp->fx_file, fixp->fx_line,
8462 _("can not do %d byte pc-relative relocation"),
8463 fixp->fx_size);
93382f6d
AM		 8464 code = BFD_RELOC_32_PCREL;
8465 break;
8466 case 1: code = BFD_RELOC_8_PCREL; break;
8467 case 2: code = BFD_RELOC_16_PCREL; break;
8468 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8469#ifdef BFD64
8470 case 8: code = BFD_RELOC_64_PCREL; break;
8471#endif
93382f6d
AM		 8472 }
8473 }
8474 else
8475 {
8476 switch (fixp->fx_size)
8477 {
8478 default:
b091f402
AM		 8479 as_bad_where (fixp->fx_file, fixp->fx_line,
8480 _("can not do %d byte relocation"),
8481 fixp->fx_size);
93382f6d
AM		 8482 code = BFD_RELOC_32;
8483 break;
8484 case 1: code = BFD_RELOC_8; break;
8485 case 2: code = BFD_RELOC_16; break;
8486 case 4: code = BFD_RELOC_32; break;
937149dd 8487#ifdef BFD64
3e73aa7c 8488 case 8: code = BFD_RELOC_64; break;
937149dd 8489#endif
93382f6d 8490 }
252b5132
RH		 8491 }
8492 break;
8493 }
252b5132 8494
d182319b
JB		 8495 if ((code == BFD_RELOC_32
8496 || code == BFD_RELOC_32_PCREL
8497 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8498 && GOT_symbol
8499 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8500 {
4fa24527 8501 if (!object_64bit)
d6ab8113
JB		 8502 code = BFD_RELOC_386_GOTPC;
8503 else
8504 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8505 }
7b81dfbb
AJ		 8506 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8507 && GOT_symbol
8508 && fixp->fx_addsy == GOT_symbol)
8509 {
8510 code = BFD_RELOC_X86_64_GOTPC64;
8511 }
252b5132
RH		 8512
8513 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8514 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8515 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8516
8517 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8518
3e73aa7c
JH		 8519 if (!use_rela_relocations)
8520 {
8521 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8522 vtable entry to be used in the relocation's section offset. */
8523 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8524 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8525#if defined (OBJ_COFF) && defined (TE_PE)
8526 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8527 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8528 else
8529#endif
c6682705 8530 rel->addend = 0;
3e73aa7c
JH		 8531 }
8532 /* Use the rela in 64bit mode. */
252b5132 8533 else
3e73aa7c 8534 {
062cd5e7
AS		 8535 if (!fixp->fx_pcrel)
8536 rel->addend = fixp->fx_offset;
8537 else
8538 switch (code)
8539 {
8540 case BFD_RELOC_X86_64_PLT32:
8541 case BFD_RELOC_X86_64_GOT32:
8542 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8543 case BFD_RELOC_X86_64_TLSGD:
8544 case BFD_RELOC_X86_64_TLSLD:
8545 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8546 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8547 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8548 rel->addend = fixp->fx_offset - fixp->fx_size;
8549 break;
8550 default:
8551 rel->addend = (section->vma
8552 - fixp->fx_size
8553 + fixp->fx_addnumber
8554 + md_pcrel_from (fixp));
8555 break;
8556 }
3e73aa7c
JH		 8557 }
8558
252b5132
RH		 8559 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8560 if (rel->howto == NULL)
8561 {
8562 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8563 _("cannot represent relocation type %s"),
252b5132
RH		 8564 bfd_get_reloc_code_name (code));
8565 /* Set howto to a garbage value so that we can keep going. */
8566 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8567 gas_assert (rel->howto != NULL);
252b5132
RH		 8568 }
8569
8570 return rel;
8571}
8572
ee86248c 8573#include "tc-i386-intel.c"
54cfded0 8574
a60de03c
JB		 8575void
8576tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8577{
a60de03c
JB		 8578 int saved_naked_reg;
8579 char saved_register_dot;
54cfded0 8580
a60de03c
JB		 8581 saved_naked_reg = allow_naked_reg;
8582 allow_naked_reg = 1;
8583 saved_register_dot = register_chars['.'];
8584 register_chars['.'] = '.';
8585 allow_pseudo_reg = 1;
8586 expression_and_evaluate (exp);
8587 allow_pseudo_reg = 0;
8588 register_chars['.'] = saved_register_dot;
8589 allow_naked_reg = saved_naked_reg;
8590
8591 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8592 {
a60de03c
JB		 8593 if ((addressT) exp->X_add_number < i386_regtab_size)
8594 {
8595 exp->X_op = O_constant;
8596 exp->X_add_number = i386_regtab[exp->X_add_number]
8597 .dw2_regnum[flag_code >> 1];
8598 }
8599 else
8600 exp->X_op = O_illegal;
54cfded0 8601 }
54cfded0
AM		 8602}
8603
8604void
8605tc_x86_frame_initial_instructions (void)
8606{
a60de03c
JB		 8607 static unsigned int sp_regno[2];
8608
8609 if (!sp_regno[flag_code >> 1])
8610 {
8611 char *saved_input = input_line_pointer;
8612 char sp[][4] = {"esp", "rsp"};
8613 expressionS exp;
a4447b93 8614
a60de03c
JB		 8615 input_line_pointer = sp[flag_code >> 1];
8616 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8617 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8618 sp_regno[flag_code >> 1] = exp.X_add_number;
8619 input_line_pointer = saved_input;
8620 }
a4447b93 8621
a60de03c 8622 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8623 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8624}
d2b2c203
DJ		 8625
8626int
8627i386_elf_section_type (const char *str, size_t len)
8628{
8629 if (flag_code == CODE_64BIT
8630 && len == sizeof ("unwind") - 1
8631 && strncmp (str, "unwind", 6) == 0)
8632 return SHT_X86_64_UNWIND;
8633
8634 return -1;
8635}
bb41ade5 8636
ad5fec3b
EB		 8637#ifdef TE_SOLARIS
8638void
8639i386_solaris_fix_up_eh_frame (segT sec)
8640{
8641 if (flag_code == CODE_64BIT)
8642 elf_section_type (sec) = SHT_X86_64_UNWIND;
8643}
8644#endif
8645
bb41ade5
AM		 8646#ifdef TE_PE
8647void
8648tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8649{
8650 expressionS expr;
8651
8652 expr.X_op = O_secrel;
8653 expr.X_add_symbol = symbol;
8654 expr.X_add_number = 0;
8655 emit_expr (&expr, size);
8656}
8657#endif
3b22753a
L		 8658
8659#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8660/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8661
01e1a5bc 8662bfd_vma
3b22753a
L		 8663x86_64_section_letter (int letter, char **ptr_msg)
8664{
8665 if (flag_code == CODE_64BIT)
8666 {
8667 if (letter == 'l')
8668 return SHF_X86_64_LARGE;
8669
8670 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8671 }
3b22753a 8672 else
64e74474 8673 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8674 return -1;
8675}
8676
01e1a5bc 8677bfd_vma
3b22753a
L		 8678x86_64_section_word (char *str, size_t len)
8679{
8620418b 8680 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8681 return SHF_X86_64_LARGE;
8682
8683 return -1;
8684}
8685
8686static void
8687handle_large_common (int small ATTRIBUTE_UNUSED)
8688{
8689 if (flag_code != CODE_64BIT)
8690 {
8691 s_comm_internal (0, elf_common_parse);
8692 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8693 }
8694 else
8695 {
8696 static segT lbss_section;
8697 asection *saved_com_section_ptr = elf_com_section_ptr;
8698 asection *saved_bss_section = bss_section;
8699
8700 if (lbss_section == NULL)
8701 {
8702 flagword applicable;
8703 segT seg = now_seg;
8704 subsegT subseg = now_subseg;
8705
8706 /* The .lbss section is for local .largecomm symbols. */
8707 lbss_section = subseg_new (".lbss", 0);
8708 applicable = bfd_applicable_section_flags (stdoutput);
8709 bfd_set_section_flags (stdoutput, lbss_section,
8710 applicable & SEC_ALLOC);
8711 seg_info (lbss_section)->bss = 1;
8712
8713 subseg_set (seg, subseg);
8714 }
8715
8716 elf_com_section_ptr = &_bfd_elf_large_com_section;
8717 bss_section = lbss_section;
8718
8719 s_comm_internal (0, elf_common_parse);
8720
8721 elf_com_section_ptr = saved_com_section_ptr;
8722 bss_section = saved_bss_section;
8723 }
8724}
8725#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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