2007-03-30 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
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23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH
37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM
43#endif
44
252b5132
RH
45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM
53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM
57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L
65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L
72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L
81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L
99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM
108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
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115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH
118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH
125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH
130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH
134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM
136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH
140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH
156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH
167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC
176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM
183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM
197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH
202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM
214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH
216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM
218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
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221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH
224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH
231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH
239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH
247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH
253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L
258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH
262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH
265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH
273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH
276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH
280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
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286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH
290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L
293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH
296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L
301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
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KH
304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
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KH
307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L
314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L
317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L
323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L
326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM
329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH
336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM
348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH
353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH
358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM
367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH
373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM
384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH
398 {0, 0, 2, 0},
399
93c2a809
AM
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM
407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH
419};
420
9103f4f4
L
421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L
427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L
452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L
455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L
464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L
477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L
480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L
483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L
488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L
491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L
499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L
501 {".3dnow", PROCESSOR_UNKNOWN,
502 CpuMMX|Cpu3dnow},
503 {".3dnowa", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
505 {".padlock", PROCESSOR_UNKNOWN,
506 CpuPadLock},
507 {".pacifica", PROCESSOR_UNKNOWN,
508 CpuSVME},
509 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM
510 CpuSVME},
511 {".sse4a", PROCESSOR_UNKNOWN,
512 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
513 {".abm", PROCESSOR_UNKNOWN,
514 CpuABM}
e413e4e9
AM
515};
516
29b0f896
AM
517const pseudo_typeS md_pseudo_table[] =
518{
519#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
520 {"align", s_align_bytes, 0},
521#else
522 {"align", s_align_ptwo, 0},
523#endif
524 {"arch", set_cpu_arch, 0},
525#ifndef I386COFF
526 {"bss", s_bss, 0},
527#endif
528 {"ffloat", float_cons, 'f'},
529 {"dfloat", float_cons, 'd'},
530 {"tfloat", float_cons, 'x'},
531 {"value", cons, 2},
d182319b 532 {"slong", signed_cons, 4},
29b0f896
AM
533 {"noopt", s_ignore, 0},
534 {"optim", s_ignore, 0},
535 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
536 {"code16", set_code_flag, CODE_16BIT},
537 {"code32", set_code_flag, CODE_32BIT},
538 {"code64", set_code_flag, CODE_64BIT},
539 {"intel_syntax", set_intel_syntax, 1},
540 {"att_syntax", set_intel_syntax, 0},
3b22753a
L
541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
542 {"largecomm", handle_large_common, 0},
07a53e5c 543#else
e3bb37b5 544 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH
545 {"loc", dwarf2_directive_loc, 0},
546 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 547#endif
6482c264
NC
548#ifdef TE_PE
549 {"secrel32", pe_directive_secrel, 0},
550#endif
29b0f896
AM
551 {0, 0, 0}
552};
553
554/* For interface with expression (). */
555extern char *input_line_pointer;
556
557/* Hash table for instruction mnemonic lookup. */
558static struct hash_control *op_hash;
559
560/* Hash table for register lookup. */
561static struct hash_control *reg_hash;
562\f
252b5132 563void
e3bb37b5 564i386_align_code (fragS *fragP, int count)
252b5132 565{
ce8a8b2f
AM
566 /* Various efficient no-op patterns for aligning code labels.
567 Note: Don't try to assemble the instructions in the comments.
568 0L and 0w are not legal. */
252b5132
RH
569 static const char f32_1[] =
570 {0x90}; /* nop */
571 static const char f32_2[] =
ccc9c027 572 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH
573 static const char f32_3[] =
574 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
575 static const char f32_4[] =
576 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
577 static const char f32_5[] =
578 {0x90, /* nop */
579 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
580 static const char f32_6[] =
581 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
582 static const char f32_7[] =
583 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
584 static const char f32_8[] =
585 {0x90, /* nop */
586 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
587 static const char f32_9[] =
588 {0x89,0xf6, /* movl %esi,%esi */
589 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
590 static const char f32_10[] =
591 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
592 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
593 static const char f32_11[] =
594 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_12[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
598 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
599 static const char f32_13[] =
600 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_14[] =
603 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_15[] =
606 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
607 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM
608 static const char f16_3[] =
609 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH
610 static const char f16_4[] =
611 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
612 static const char f16_5[] =
613 {0x90, /* nop */
614 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_6[] =
616 {0x89,0xf6, /* mov %si,%si */
617 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
618 static const char f16_7[] =
619 {0x8d,0x74,0x00, /* lea 0(%si),%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_8[] =
622 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
627 };
628 static const char *const f16_patt[] = {
c3332e24 629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH
630 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
631 };
ccc9c027
L
632 /* nopl (%[re]ax) */
633 static const char alt_3[] =
634 {0x0f,0x1f,0x00};
635 /* nopl 0(%[re]ax) */
636 static const char alt_4[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* data16
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11[] =
659 {0x66,
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
661 /* data16
662 data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12[] =
665 {0x66,
666 0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 data16
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13[] =
673 {0x66,
674 0x66,
675 0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 data16
680 data16
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14[] =
683 {0x66,
684 0x66,
685 0x66,
686 0x66,
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 /* data16
689 data16
690 data16
691 data16
692 data16
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15[] =
695 {0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
712 nopl 0L(%[re]ax) */
713 static const char alt_short_13[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
716 /* nopl 0L(%[re]ax)
717 nopl 0L(%[re]ax) */
718 static const char alt_short_14[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 /* nopl 0L(%[re]ax)
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt[] = {
727 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
728 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
729 alt_short_14, alt_short_15
730 };
731 static const char *const alt_long_patt[] = {
732 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
733 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
734 alt_long_14, alt_long_15
735 };
252b5132 736
33fef721
JH
737 if (count <= 0 || count > 15)
738 return;
3e73aa7c 739
ccc9c027
L
740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
4eed87de 742
ccc9c027
L
743 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
744 f32_patt will be used.
4eed87de
AM
745 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
746 0x66 prefix will be used.
ef05d495 747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L
750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
751
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
762 if (count > 8)
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
765 }
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 767 {
33fef721
JH
768 int i;
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
772 int pos = 0;
773
ccc9c027 774 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 775 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 776 for (i = 0; i < remains; i++)
252b5132 777 {
33fef721
JH
778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
780 pos += len + 1;
781 }
782 for (; i < nnops; i++)
783 {
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
786 pos += len;
252b5132 787 }
252b5132 788 }
33fef721 789 else
ccc9c027
L
790 {
791 const char *const *patt = NULL;
792
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
794 {
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
797 {
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
803 else
804 patt = f32_patt;
805 break;
ef05d495 806 case PROCESSOR_CORE2:
ccc9c027
L
807 patt = alt_long_patt;
808 break;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
ef05d495 812 case PROCESSOR_CORE:
ccc9c027
L
813 case PROCESSOR_K6:
814 case PROCESSOR_ATHLON:
815 case PROCESSOR_K8:
816 case PROCESSOR_GENERIC64:
4eed87de 817 case PROCESSOR_AMDFAM10:
ccc9c027
L
818 patt = alt_short_patt;
819 break;
820 case PROCESSOR_I486:
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
823 patt = f32_patt;
824 break;
4eed87de 825 }
ccc9c027
L
826 }
827 else
828 {
829 switch (cpu_arch_tune)
830 {
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
834 abort ();
835 break;
836
837 case PROCESSOR_I486:
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
ef05d495 842 case PROCESSOR_CORE:
ccc9c027
L
843 case PROCESSOR_K6:
844 case PROCESSOR_ATHLON:
845 case PROCESSOR_K8:
4eed87de 846 case PROCESSOR_AMDFAM10:
ccc9c027
L
847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
849 for Cpu686. */
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
852 else
853 patt = f32_patt;
854 break;
ef05d495 855 case PROCESSOR_CORE2:
ccc9c027
L
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
863 break;
4eed87de 864 }
ccc9c027
L
865 }
866
33fef721 867 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L
868 patt[count - 1], count);
869 }
33fef721 870 fragP->fr_var = count;
252b5132
RH
871}
872
252b5132 873static INLINE unsigned int
e3bb37b5 874mode_from_disp_size (unsigned int t)
252b5132 875{
3e73aa7c 876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH
877}
878
879static INLINE int
e3bb37b5 880fits_in_signed_byte (offsetT num)
252b5132
RH
881{
882 return (num >= -128) && (num <= 127);
47926f60 883}
252b5132
RH
884
885static INLINE int
e3bb37b5 886fits_in_unsigned_byte (offsetT num)
252b5132
RH
887{
888 return (num & 0xff) == num;
47926f60 889}
252b5132
RH
890
891static INLINE int
e3bb37b5 892fits_in_unsigned_word (offsetT num)
252b5132
RH
893{
894 return (num & 0xffff) == num;
47926f60 895}
252b5132
RH
896
897static INLINE int
e3bb37b5 898fits_in_signed_word (offsetT num)
252b5132
RH
899{
900 return (-32768 <= num) && (num <= 32767);
47926f60 901}
2a962e6d 902
3e73aa7c 903static INLINE int
e3bb37b5 904fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH
905{
906#ifndef BFD64
907 return 1;
908#else
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
911#endif
912} /* fits_in_signed_long() */
2a962e6d 913
3e73aa7c 914static INLINE int
e3bb37b5 915fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH
916{
917#ifndef BFD64
918 return 1;
919#else
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
921#endif
922} /* fits_in_unsigned_long() */
252b5132 923
1509aa9a 924static unsigned int
e3bb37b5 925smallest_imm_type (offsetT num)
252b5132 926{
d32cad65 927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM
928 {
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
933 use that form. */
934 if (num == 1)
3e73aa7c 935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 936 }
252b5132 937 return (fits_in_signed_byte (num)
3e73aa7c 938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 939 : fits_in_unsigned_byte (num)
3e73aa7c 940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH
942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
946 ? (Imm32 | Imm64)
947 : Imm64);
47926f60 948}
252b5132 949
847f7ad4 950static offsetT
e3bb37b5 951offset_in_range (offsetT val, int size)
847f7ad4 952{
508866be 953 addressT mask;
ba2adb93 954
847f7ad4
AM
955 switch (size)
956 {
508866be
L
957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 959 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH
960#ifdef BFD64
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
962#endif
47926f60 963 default: abort ();
847f7ad4
AM
964 }
965
ba2adb93 966 /* If BFD64, sign extend val. */
3e73aa7c
JH
967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 970
47926f60 971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM
972 {
973 char buf1[40], buf2[40];
974
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
978 }
979 return val & mask;
980}
981
252b5132
RH
982/* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
984 added. */
985static int
e3bb37b5 986add_prefix (unsigned int prefix)
252b5132
RH
987{
988 int ret = 1;
b1905489 989 unsigned int q;
252b5132 990
29b0f896
AM
991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
b1905489 993 {
161a04f6
L
994 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
995 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
996 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB
997 ret = 0;
998 q = REX_PREFIX;
999 }
3e73aa7c 1000 else
b1905489
JB
1001 {
1002 switch (prefix)
1003 {
1004 default:
1005 abort ();
1006
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1013 q = SEG_PREFIX;
1014 break;
1015
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1018 ret = 2;
1019 /* fall thru */
1020 case LOCK_PREFIX_OPCODE:
1021 q = LOCKREP_PREFIX;
1022 break;
1023
1024 case FWAIT_OPCODE:
1025 q = WAIT_PREFIX;
1026 break;
1027
1028 case ADDR_PREFIX_OPCODE:
1029 q = ADDR_PREFIX;
1030 break;
1031
1032 case DATA_PREFIX_OPCODE:
1033 q = DATA_PREFIX;
1034 break;
1035 }
1036 if (i.prefix[q] != 0)
1037 ret = 0;
1038 }
252b5132 1039
b1905489 1040 if (ret)
252b5132 1041 {
b1905489
JB
1042 if (!i.prefix[q])
1043 ++i.prefixes;
1044 i.prefix[q] |= prefix;
252b5132 1045 }
b1905489
JB
1046 else
1047 as_bad (_("same type of prefix used twice"));
252b5132 1048
252b5132
RH
1049 return ret;
1050}
1051
1052static void
e3bb37b5 1053set_code_flag (int value)
eecb386c 1054{
3e73aa7c
JH
1055 flag_code = value;
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1059 {
1060 as_bad (_("64bit mode not supported on this CPU."));
1061 }
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1063 {
1064 as_bad (_("32bit mode not supported on this CPU."));
1065 }
eecb386c
AM
1066 stackop_size = '\0';
1067}
1068
1069static void
e3bb37b5 1070set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1071{
3e73aa7c
JH
1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1075 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH
1076}
1077
1078static void
e3bb37b5 1079set_intel_syntax (int syntax_flag)
252b5132
RH
1080{
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1083
1084 SKIP_WHITESPACE ();
29b0f896 1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH
1086 {
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1089
47926f60 1090 if (strcmp (string, "prefix") == 0)
252b5132 1091 ask_naked_reg = 1;
47926f60 1092 else if (strcmp (string, "noprefix") == 0)
252b5132
RH
1093 ask_naked_reg = -1;
1094 else
d0b47220 1095 as_bad (_("bad argument to syntax directive."));
252b5132
RH
1096 *input_line_pointer = e;
1097 }
1098 demand_empty_rest_of_line ();
c3332e24 1099
252b5132
RH
1100 intel_syntax = syntax_flag;
1101
1102 if (ask_naked_reg == 0)
f86103b7
AM
1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH
1105 else
1106 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1107
e4a3b5a4 1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1110 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH
1111}
1112
e413e4e9 1113static void
e3bb37b5 1114set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1115{
47926f60 1116 SKIP_WHITESPACE ();
e413e4e9 1117
29b0f896 1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM
1119 {
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
9103f4f4 1122 unsigned int i;
e413e4e9 1123
9103f4f4 1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM
1125 {
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1127 {
5c6af06e
JB
1128 if (*string != '.')
1129 {
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM
1133 | (flag_code == CODE_64BIT
1134 ? Cpu64 : CpuNo64));
ccc9c027 1135 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1136 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L
1137 if (!cpu_arch_tune_set)
1138 {
1139 cpu_arch_tune = cpu_arch_isa;
1140 cpu_arch_tune_flags = cpu_arch_isa_flags;
1141 }
5c6af06e
JB
1142 break;
1143 }
1144 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1145 {
1146 cpu_sub_arch_name = cpu_arch[i].name;
1147 cpu_arch_flags |= cpu_arch[i].flags;
1148 }
1149 *input_line_pointer = e;
1150 demand_empty_rest_of_line ();
1151 return;
e413e4e9
AM
1152 }
1153 }
9103f4f4 1154 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM
1155 as_bad (_("no such architecture: `%s'"), string);
1156
1157 *input_line_pointer = e;
1158 }
1159 else
1160 as_bad (_("missing cpu architecture"));
1161
fddf5b5b
AM
1162 no_cond_jump_promotion = 0;
1163 if (*input_line_pointer == ','
29b0f896 1164 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM
1165 {
1166 char *string = ++input_line_pointer;
1167 int e = get_symbol_end ();
1168
1169 if (strcmp (string, "nojumps") == 0)
1170 no_cond_jump_promotion = 1;
1171 else if (strcmp (string, "jumps") == 0)
1172 ;
1173 else
1174 as_bad (_("no such architecture modifier: `%s'"), string);
1175
1176 *input_line_pointer = e;
1177 }
1178
e413e4e9
AM
1179 demand_empty_rest_of_line ();
1180}
1181
b9d79e03
JH
1182unsigned long
1183i386_mach ()
1184{
1185 if (!strcmp (default_arch, "x86_64"))
1186 return bfd_mach_x86_64;
1187 else if (!strcmp (default_arch, "i386"))
1188 return bfd_mach_i386_i386;
1189 else
1190 as_fatal (_("Unknown architecture"));
1191}
b9d79e03 1192\f
252b5132
RH
1193void
1194md_begin ()
1195{
1196 const char *hash_err;
1197
47926f60 1198 /* Initialize op_hash hash table. */
252b5132
RH
1199 op_hash = hash_new ();
1200
1201 {
29b0f896
AM
1202 const template *optab;
1203 templates *core_optab;
252b5132 1204
47926f60
KH
1205 /* Setup for loop. */
1206 optab = i386_optab;
252b5132
RH
1207 core_optab = (templates *) xmalloc (sizeof (templates));
1208 core_optab->start = optab;
1209
1210 while (1)
1211 {
1212 ++optab;
1213 if (optab->name == NULL
1214 || strcmp (optab->name, (optab - 1)->name) != 0)
1215 {
1216 /* different name --> ship out current template list;
47926f60 1217 add to hash table; & begin anew. */
252b5132
RH
1218 core_optab->end = optab;
1219 hash_err = hash_insert (op_hash,
1220 (optab - 1)->name,
1221 (PTR) core_optab);
1222 if (hash_err)
1223 {
252b5132
RH
1224 as_fatal (_("Internal Error: Can't hash %s: %s"),
1225 (optab - 1)->name,
1226 hash_err);
1227 }
1228 if (optab->name == NULL)
1229 break;
1230 core_optab = (templates *) xmalloc (sizeof (templates));
1231 core_optab->start = optab;
1232 }
1233 }
1234 }
1235
47926f60 1236 /* Initialize reg_hash hash table. */
252b5132
RH
1237 reg_hash = hash_new ();
1238 {
29b0f896 1239 const reg_entry *regtab;
c3fe08fa 1240 unsigned int regtab_size = i386_regtab_size;
252b5132 1241
c3fe08fa 1242 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH
1243 {
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1245 if (hash_err)
3e73aa7c
JH
1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1247 regtab->reg_name,
1248 hash_err);
252b5132
RH
1249 }
1250 }
1251
47926f60 1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1253 {
29b0f896
AM
1254 int c;
1255 char *p;
252b5132
RH
1256
1257 for (c = 0; c < 256; c++)
1258 {
3882b010 1259 if (ISDIGIT (c))
252b5132
RH
1260 {
1261 digit_chars[c] = c;
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1265 }
3882b010 1266 else if (ISLOWER (c))
252b5132
RH
1267 {
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISUPPER (c))
252b5132 1273 {
3882b010 1274 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH
1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1277 }
1278
3882b010 1279 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH
1280 identifier_chars[c] = c;
1281 else if (c >= 128)
1282 {
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1285 }
1286 }
1287
1288#ifdef LEX_AT
1289 identifier_chars['@'] = '@';
32137342
NC
1290#endif
1291#ifdef LEX_QM
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
252b5132 1294#endif
252b5132 1295 digit_chars['-'] = '-';
791fe849 1296 mnemonic_chars['-'] = '-';
0003779b 1297 mnemonic_chars['.'] = '.';
252b5132
RH
1298 identifier_chars['_'] = '_';
1299 identifier_chars['.'] = '.';
1300
1301 for (p = operand_special_chars; *p != '\0'; p++)
1302 operand_chars[(unsigned char) *p] = *p;
1303 }
1304
1305#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1306 if (IS_ELF)
252b5132
RH
1307 {
1308 record_alignment (text_section, 2);
1309 record_alignment (data_section, 2);
1310 record_alignment (bss_section, 2);
1311 }
1312#endif
a4447b93
RH
1313
1314 if (flag_code == CODE_64BIT)
1315 {
1316 x86_dwarf2_return_column = 16;
1317 x86_cie_data_alignment = -8;
1318 }
1319 else
1320 {
1321 x86_dwarf2_return_column = 8;
1322 x86_cie_data_alignment = -4;
1323 }
252b5132
RH
1324}
1325
1326void
e3bb37b5 1327i386_print_statistics (FILE *file)
252b5132
RH
1328{
1329 hash_print_statistics (file, "i386 opcode", op_hash);
1330 hash_print_statistics (file, "i386 register", reg_hash);
1331}
1332\f
252b5132
RH
1333#ifdef DEBUG386
1334
ce8a8b2f 1335/* Debugging routines for md_assemble. */
e3bb37b5
L
1336static void pte (template *);
1337static void pt (unsigned int);
1338static void pe (expressionS *);
1339static void ps (symbolS *);
252b5132
RH
1340
1341static void
e3bb37b5 1342pi (char *line, i386_insn *x)
252b5132 1343{
09f131f2 1344 unsigned int i;
252b5132
RH
1345
1346 fprintf (stdout, "%s: template ", line);
1347 pte (&x->tm);
09f131f2
JH
1348 fprintf (stdout, " address: base %s index %s scale %x\n",
1349 x->base_reg ? x->base_reg->reg_name : "none",
1350 x->index_reg ? x->index_reg->reg_name : "none",
1351 x->log2_scale_factor);
1352 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1353 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH
1354 fprintf (stdout, " sib: base %x index %x scale %x\n",
1355 x->sib.base, x->sib.index, x->sib.scale);
1356 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L
1357 (x->rex & REX_W) != 0,
1358 (x->rex & REX_R) != 0,
1359 (x->rex & REX_X) != 0,
1360 (x->rex & REX_B) != 0);
252b5132
RH
1361 for (i = 0; i < x->operands; i++)
1362 {
1363 fprintf (stdout, " #%d: ", i + 1);
1364 pt (x->types[i]);
1365 fprintf (stdout, "\n");
1366 if (x->types[i]
3f4438ab 1367 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1368 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1369 if (x->types[i] & Imm)
520dc8e8 1370 pe (x->op[i].imms);
252b5132 1371 if (x->types[i] & Disp)
520dc8e8 1372 pe (x->op[i].disps);
252b5132
RH
1373 }
1374}
1375
1376static void
e3bb37b5 1377pte (template *t)
252b5132 1378{
09f131f2 1379 unsigned int i;
252b5132 1380 fprintf (stdout, " %d operands ", t->operands);
47926f60 1381 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH
1382 if (t->extension_opcode != None)
1383 fprintf (stdout, "ext %x ", t->extension_opcode);
1384 if (t->opcode_modifier & D)
1385 fprintf (stdout, "D");
1386 if (t->opcode_modifier & W)
1387 fprintf (stdout, "W");
1388 fprintf (stdout, "\n");
1389 for (i = 0; i < t->operands; i++)
1390 {
1391 fprintf (stdout, " #%d type ", i + 1);
1392 pt (t->operand_types[i]);
1393 fprintf (stdout, "\n");
1394 }
1395}
1396
1397static void
e3bb37b5 1398pe (expressionS *e)
252b5132 1399{
24eab124 1400 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM
1401 fprintf (stdout, " add_number %ld (%lx)\n",
1402 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH
1403 if (e->X_add_symbol)
1404 {
1405 fprintf (stdout, " add_symbol ");
1406 ps (e->X_add_symbol);
1407 fprintf (stdout, "\n");
1408 }
1409 if (e->X_op_symbol)
1410 {
1411 fprintf (stdout, " op_symbol ");
1412 ps (e->X_op_symbol);
1413 fprintf (stdout, "\n");
1414 }
1415}
1416
1417static void
e3bb37b5 1418ps (symbolS *s)
252b5132
RH
1419{
1420 fprintf (stdout, "%s type %s%s",
1421 S_GET_NAME (s),
1422 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1423 segment_name (S_GET_SEGMENT (s)));
1424}
1425
7b81dfbb 1426static struct type_name
252b5132
RH
1427 {
1428 unsigned int mask;
1429 char *tname;
1430 }
7b81dfbb 1431const type_names[] =
252b5132
RH
1432{
1433 { Reg8, "r8" },
1434 { Reg16, "r16" },
1435 { Reg32, "r32" },
09f131f2 1436 { Reg64, "r64" },
252b5132
RH
1437 { Imm8, "i8" },
1438 { Imm8S, "i8s" },
1439 { Imm16, "i16" },
1440 { Imm32, "i32" },
09f131f2
JH
1441 { Imm32S, "i32s" },
1442 { Imm64, "i64" },
252b5132
RH
1443 { Imm1, "i1" },
1444 { BaseIndex, "BaseIndex" },
1445 { Disp8, "d8" },
1446 { Disp16, "d16" },
1447 { Disp32, "d32" },
09f131f2
JH
1448 { Disp32S, "d32s" },
1449 { Disp64, "d64" },
252b5132
RH
1450 { InOutPortReg, "InOutPortReg" },
1451 { ShiftCount, "ShiftCount" },
1452 { Control, "control reg" },
1453 { Test, "test reg" },
1454 { Debug, "debug reg" },
1455 { FloatReg, "FReg" },
1456 { FloatAcc, "FAcc" },
1457 { SReg2, "SReg2" },
1458 { SReg3, "SReg3" },
1459 { Acc, "Acc" },
1460 { JumpAbsolute, "Jump Absolute" },
1461 { RegMMX, "rMMX" },
3f4438ab 1462 { RegXMM, "rXMM" },
252b5132
RH
1463 { EsSeg, "es" },
1464 { 0, "" }
1465};
1466
1467static void
1468pt (t)
1469 unsigned int t;
1470{
29b0f896 1471 const struct type_name *ty;
252b5132 1472
09f131f2
JH
1473 for (ty = type_names; ty->mask; ty++)
1474 if (t & ty->mask)
1475 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH
1476 fflush (stdout);
1477}
1478
1479#endif /* DEBUG386 */
1480\f
252b5132 1481static bfd_reloc_code_real_type
3956db08 1482reloc (unsigned int size,
64e74474
AM
1483 int pcrel,
1484 int sign,
1485 bfd_reloc_code_real_type other)
252b5132 1486{
47926f60 1487 if (other != NO_RELOC)
3956db08
JB
1488 {
1489 reloc_howto_type *reloc;
1490
1491 if (size == 8)
1492 switch (other)
1493 {
64e74474
AM
1494 case BFD_RELOC_X86_64_GOT32:
1495 return BFD_RELOC_X86_64_GOT64;
1496 break;
1497 case BFD_RELOC_X86_64_PLTOFF64:
1498 return BFD_RELOC_X86_64_PLTOFF64;
1499 break;
1500 case BFD_RELOC_X86_64_GOTPC32:
1501 other = BFD_RELOC_X86_64_GOTPC64;
1502 break;
1503 case BFD_RELOC_X86_64_GOTPCREL:
1504 other = BFD_RELOC_X86_64_GOTPCREL64;
1505 break;
1506 case BFD_RELOC_X86_64_TPOFF32:
1507 other = BFD_RELOC_X86_64_TPOFF64;
1508 break;
1509 case BFD_RELOC_X86_64_DTPOFF32:
1510 other = BFD_RELOC_X86_64_DTPOFF64;
1511 break;
1512 default:
1513 break;
3956db08 1514 }
e05278af
JB
1515
1516 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1517 if (size == 4 && flag_code != CODE_64BIT)
1518 sign = -1;
1519
3956db08
JB
1520 reloc = bfd_reloc_type_lookup (stdoutput, other);
1521 if (!reloc)
1522 as_bad (_("unknown relocation (%u)"), other);
1523 else if (size != bfd_get_reloc_size (reloc))
1524 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1525 bfd_get_reloc_size (reloc),
1526 size);
1527 else if (pcrel && !reloc->pc_relative)
1528 as_bad (_("non-pc-relative relocation for pc-relative field"));
1529 else if ((reloc->complain_on_overflow == complain_overflow_signed
1530 && !sign)
1531 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1532 && sign > 0))
3956db08
JB
1533 as_bad (_("relocated field and relocation type differ in signedness"));
1534 else
1535 return other;
1536 return NO_RELOC;
1537 }
252b5132
RH
1538
1539 if (pcrel)
1540 {
3e73aa7c 1541 if (!sign)
3956db08 1542 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH
1543 switch (size)
1544 {
1545 case 1: return BFD_RELOC_8_PCREL;
1546 case 2: return BFD_RELOC_16_PCREL;
1547 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1548 case 8: return BFD_RELOC_64_PCREL;
252b5132 1549 }
3956db08 1550 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH
1551 }
1552 else
1553 {
3956db08 1554 if (sign > 0)
e5cb08ac 1555 switch (size)
3e73aa7c
JH
1556 {
1557 case 4: return BFD_RELOC_X86_64_32S;
1558 }
1559 else
1560 switch (size)
1561 {
1562 case 1: return BFD_RELOC_8;
1563 case 2: return BFD_RELOC_16;
1564 case 4: return BFD_RELOC_32;
1565 case 8: return BFD_RELOC_64;
1566 }
3956db08
JB
1567 as_bad (_("cannot do %s %u byte relocation"),
1568 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH
1569 }
1570
bfb32b52 1571 abort ();
252b5132
RH
1572 return BFD_RELOC_NONE;
1573}
1574
47926f60
KH
1575/* Here we decide which fixups can be adjusted to make them relative to
1576 the beginning of the section instead of the symbol. Basically we need
1577 to make sure that the dynamic relocations are done correctly, so in
1578 some cases we force the original symbol to be used. */
1579
252b5132 1580int
e3bb37b5 1581tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1582{
6d249963 1583#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1584 if (!IS_ELF)
31312f95
AM
1585 return 1;
1586
a161fe53
AM
1587 /* Don't adjust pc-relative references to merge sections in 64-bit
1588 mode. */
1589 if (use_rela_relocations
1590 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1591 && fixP->fx_pcrel)
252b5132 1592 return 0;
31312f95 1593
8d01d9a9
AJ
1594 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1595 and changed later by validate_fix. */
1596 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1597 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1598 return 0;
1599
ce8a8b2f 1600 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH
1601 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1602 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1603 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1626 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1628 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1629 return 0;
31312f95 1630#endif
252b5132
RH
1631 return 1;
1632}
252b5132 1633
b4cac588 1634static int
e3bb37b5 1635intel_float_operand (const char *mnemonic)
252b5132 1636{
9306ca4a
JB
1637 /* Note that the value returned is meaningful only for opcodes with (memory)
1638 operands, hence the code here is free to improperly handle opcodes that
1639 have no operands (for better performance and smaller code). */
1640
1641 if (mnemonic[0] != 'f')
1642 return 0; /* non-math */
1643
1644 switch (mnemonic[1])
1645 {
1646 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1647 the fs segment override prefix not currently handled because no
1648 call path can make opcodes without operands get here */
1649 case 'i':
1650 return 2 /* integer op */;
1651 case 'l':
1652 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1653 return 3; /* fldcw/fldenv */
1654 break;
1655 case 'n':
1656 if (mnemonic[2] != 'o' /* fnop */)
1657 return 3; /* non-waiting control op */
1658 break;
1659 case 'r':
1660 if (mnemonic[2] == 's')
1661 return 3; /* frstor/frstpm */
1662 break;
1663 case 's':
1664 if (mnemonic[2] == 'a')
1665 return 3; /* fsave */
1666 if (mnemonic[2] == 't')
1667 {
1668 switch (mnemonic[3])
1669 {
1670 case 'c': /* fstcw */
1671 case 'd': /* fstdw */
1672 case 'e': /* fstenv */
1673 case 's': /* fsts[gw] */
1674 return 3;
1675 }
1676 }
1677 break;
1678 case 'x':
1679 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1680 return 0; /* fxsave/fxrstor are not really math ops */
1681 break;
1682 }
252b5132 1683
9306ca4a 1684 return 1;
252b5132
RH
1685}
1686
1687/* This is the guts of the machine-dependent assembler. LINE points to a
1688 machine dependent instruction. This function is supposed to emit
1689 the frags/bytes it assembles to. */
1690
1691void
1692md_assemble (line)
1693 char *line;
1694{
252b5132 1695 int j;
252b5132
RH
1696 char mnemonic[MAX_MNEM_SIZE];
1697
47926f60 1698 /* Initialize globals. */
252b5132
RH
1699 memset (&i, '\0', sizeof (i));
1700 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1701 i.reloc[j] = NO_RELOC;
252b5132
RH
1702 memset (disp_expressions, '\0', sizeof (disp_expressions));
1703 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1704 save_stack_p = save_stack;
252b5132
RH
1705
1706 /* First parse an instruction mnemonic & call i386_operand for the operands.
1707 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1708 start of a (possibly prefixed) mnemonic. */
252b5132 1709
29b0f896
AM
1710 line = parse_insn (line, mnemonic);
1711 if (line == NULL)
1712 return;
252b5132 1713
29b0f896
AM
1714 line = parse_operands (line, mnemonic);
1715 if (line == NULL)
1716 return;
252b5132 1717
4eed87de 1718 /* The order of the immediates should be reversed
050dfa73 1719 for 2 immediates extrq and insertq instructions */
4d456e3d
L
1720 if ((i.imm_operands == 2)
1721 && ((strcmp (mnemonic, "extrq") == 0)
1722 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1723 {
4eed87de
AM
1724 swap_2_operands (0, 1);
1725 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM
1726 have to be reversed even though they have two immediate operands.
1727 */
1728 if (intel_syntax)
1729 swap_operands ();
1730 }
1731
29b0f896
AM
1732 /* Now we've parsed the mnemonic into a set of templates, and have the
1733 operands at hand. */
1734
1735 /* All intel opcodes have reversed operands except for "bound" and
1736 "enter". We also don't reverse intersegment "jmp" and "call"
1737 instructions with 2 immediate operands so that the immediate segment
050dfa73 1738 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L
1739 if (intel_syntax
1740 && i.operands > 1
29b0f896 1741 && (strcmp (mnemonic, "bound") != 0)
30123838 1742 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM
1743 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1744 swap_operands ();
1745
1746 if (i.imm_operands)
1747 optimize_imm ();
1748
b300c311
L
1749 /* Don't optimize displacement for movabs since it only takes 64bit
1750 displacement. */
1751 if (i.disp_operands
1752 && (flag_code != CODE_64BIT
1753 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM
1754 optimize_disp ();
1755
1756 /* Next, we find a template that matches the given insn,
1757 making sure the overlap of the given operands types is consistent
1758 with the template operand types. */
252b5132 1759
29b0f896
AM
1760 if (!match_template ())
1761 return;
252b5132 1762
cd61ebfe
AM
1763 if (intel_syntax)
1764 {
1765 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1766 if (SYSV386_COMPAT
1767 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1768 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM
1769
1770 /* Zap movzx and movsx suffix. The suffix may have been set from
1771 "word ptr" or "byte ptr" on the source operand, but we'll use
1772 the suffix later to choose the destination register. */
1773 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB
1774 {
1775 if (i.reg_operands < 2
1776 && !i.suffix
1777 && (~i.tm.opcode_modifier
1778 & (No_bSuf
1779 | No_wSuf
1780 | No_lSuf
1781 | No_sSuf
1782 | No_xSuf
1783 | No_qSuf)))
1784 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1785
1786 i.suffix = 0;
1787 }
cd61ebfe 1788 }
24eab124 1789
29b0f896
AM
1790 if (i.tm.opcode_modifier & FWait)
1791 if (!add_prefix (FWAIT_OPCODE))
1792 return;
252b5132 1793
29b0f896
AM
1794 /* Check string instruction segment overrides. */
1795 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1796 {
1797 if (!check_string ())
5dd0794d 1798 return;
29b0f896 1799 }
5dd0794d 1800
29b0f896
AM
1801 if (!process_suffix ())
1802 return;
e413e4e9 1803
29b0f896
AM
1804 /* Make still unresolved immediate matches conform to size of immediate
1805 given in i.suffix. */
1806 if (!finalize_imm ())
1807 return;
252b5132 1808
29b0f896
AM
1809 if (i.types[0] & Imm1)
1810 i.imm_operands = 0; /* kludge for shift insns. */
1811 if (i.types[0] & ImplicitRegister)
1812 i.reg_operands--;
1813 if (i.types[1] & ImplicitRegister)
1814 i.reg_operands--;
1815 if (i.types[2] & ImplicitRegister)
1816 i.reg_operands--;
252b5132 1817
29b0f896
AM
1818 if (i.tm.opcode_modifier & ImmExt)
1819 {
02fc3089
L
1820 expressionS *exp;
1821
b7d9ef37 1822 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1823 {
b7d9ef37 1824 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L
1825 operands with an opcode suffix which is coded in the same
1826 place as an 8-bit immediate field would be. Here we check
1827 those operands and remove them afterwards. */
1828 unsigned int x;
1829
a4622f40 1830 for (x = 0; x < i.operands; x++)
ca164297
L
1831 if (i.op[x].regs->reg_num != x)
1832 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1833 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L
1834 i.operands = 0;
1835 }
1836
29b0f896
AM
1837 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1838 opcode suffix which is coded in the same place as an 8-bit
1839 immediate field would be. Here we fake an 8-bit immediate
1840 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1841
29b0f896 1842 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1843
29b0f896
AM
1844 exp = &im_expressions[i.imm_operands++];
1845 i.op[i.operands].imms = exp;
1846 i.types[i.operands++] = Imm8;
1847 exp->X_op = O_constant;
1848 exp->X_add_number = i.tm.extension_opcode;
1849 i.tm.extension_opcode = None;
1850 }
252b5132 1851
29b0f896
AM
1852 /* For insns with operands there are more diddles to do to the opcode. */
1853 if (i.operands)
1854 {
1855 if (!process_operands ())
1856 return;
1857 }
1858 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1859 {
1860 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1861 as_warn (_("translating to `%sp'"), i.tm.name);
1862 }
252b5132 1863
29b0f896
AM
1864 /* Handle conversion of 'int $3' --> special int3 insn. */
1865 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1866 {
1867 i.tm.base_opcode = INT3_OPCODE;
1868 i.imm_operands = 0;
1869 }
252b5132 1870
29b0f896
AM
1871 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1872 && i.op[0].disps->X_op == O_constant)
1873 {
1874 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1875 the absolute address given by the constant. Since ix86 jumps and
1876 calls are pc relative, we need to generate a reloc. */
1877 i.op[0].disps->X_add_symbol = &abs_symbol;
1878 i.op[0].disps->X_op = O_symbol;
1879 }
252b5132 1880
29b0f896 1881 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1882 i.rex |= REX_W;
252b5132 1883
29b0f896
AM
1884 /* For 8 bit registers we need an empty rex prefix. Also if the
1885 instruction already has a prefix, we need to convert old
1886 registers to new ones. */
773f551c 1887
29b0f896
AM
1888 if (((i.types[0] & Reg8) != 0
1889 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1890 || ((i.types[1] & Reg8) != 0
1891 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1892 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1893 && i.rex != 0))
1894 {
1895 int x;
726c5dcd 1896
29b0f896
AM
1897 i.rex |= REX_OPCODE;
1898 for (x = 0; x < 2; x++)
1899 {
1900 /* Look for 8 bit operand that uses old registers. */
1901 if ((i.types[x] & Reg8) != 0
1902 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1903 {
29b0f896
AM
1904 /* In case it is "hi" register, give up. */
1905 if (i.op[x].regs->reg_num > 3)
4eed87de
AM
1906 as_bad (_("can't encode register '%%%s' in an "
1907 "instruction requiring REX prefix."),
29b0f896 1908 i.op[x].regs->reg_name);
773f551c 1909
29b0f896
AM
1910 /* Otherwise it is equivalent to the extended register.
1911 Since the encoding doesn't change this is merely
1912 cosmetic cleanup for debug output. */
1913
1914 i.op[x].regs = i.op[x].regs + 8;
773f551c 1915 }
29b0f896
AM
1916 }
1917 }
773f551c 1918
29b0f896
AM
1919 if (i.rex != 0)
1920 add_prefix (REX_OPCODE | i.rex);
1921
1922 /* We are ready to output the insn. */
1923 output_insn ();
1924}
1925
1926static char *
e3bb37b5 1927parse_insn (char *line, char *mnemonic)
29b0f896
AM
1928{
1929 char *l = line;
1930 char *token_start = l;
1931 char *mnem_p;
5c6af06e
JB
1932 int supported;
1933 const template *t;
29b0f896
AM
1934
1935 /* Non-zero if we found a prefix only acceptable with string insns. */
1936 const char *expecting_string_instruction = NULL;
45288df1 1937
29b0f896
AM
1938 while (1)
1939 {
1940 mnem_p = mnemonic;
1941 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1942 {
1943 mnem_p++;
1944 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1945 {
29b0f896
AM
1946 as_bad (_("no such instruction: `%s'"), token_start);
1947 return NULL;
1948 }
1949 l++;
1950 }
1951 if (!is_space_char (*l)
1952 && *l != END_OF_INSN
e44823cf
JB
1953 && (intel_syntax
1954 || (*l != PREFIX_SEPARATOR
1955 && *l != ',')))
29b0f896
AM
1956 {
1957 as_bad (_("invalid character %s in mnemonic"),
1958 output_invalid (*l));
1959 return NULL;
1960 }
1961 if (token_start == l)
1962 {
e44823cf 1963 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM
1964 as_bad (_("expecting prefix; got nothing"));
1965 else
1966 as_bad (_("expecting mnemonic; got nothing"));
1967 return NULL;
1968 }
45288df1 1969
29b0f896
AM
1970 /* Look up instruction (or prefix) via hash table. */
1971 current_templates = hash_find (op_hash, mnemonic);
47926f60 1972
29b0f896
AM
1973 if (*l != END_OF_INSN
1974 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1975 && current_templates
1976 && (current_templates->start->opcode_modifier & IsPrefix))
1977 {
2dd88dca
JB
1978 if (current_templates->start->cpu_flags
1979 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1980 {
1981 as_bad ((flag_code != CODE_64BIT
1982 ? _("`%s' is only supported in 64-bit mode")
1983 : _("`%s' is not supported in 64-bit mode")),
1984 current_templates->start->name);
1985 return NULL;
1986 }
29b0f896
AM
1987 /* If we are in 16-bit mode, do not allow addr16 or data16.
1988 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1989 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1990 && flag_code != CODE_64BIT
1991 && (((current_templates->start->opcode_modifier & Size32) != 0)
1992 ^ (flag_code == CODE_16BIT)))
1993 {
1994 as_bad (_("redundant %s prefix"),
1995 current_templates->start->name);
1996 return NULL;
45288df1 1997 }
29b0f896
AM
1998 /* Add prefix, checking for repeated prefixes. */
1999 switch (add_prefix (current_templates->start->base_opcode))
2000 {
2001 case 0:
2002 return NULL;
2003 case 2:
2004 expecting_string_instruction = current_templates->start->name;
2005 break;
2006 }
2007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2008 token_start = ++l;
2009 }
2010 else
2011 break;
2012 }
45288df1 2013
29b0f896
AM
2014 if (!current_templates)
2015 {
2016 /* See if we can get a match by trimming off a suffix. */
2017 switch (mnem_p[-1])
2018 {
2019 case WORD_MNEM_SUFFIX:
9306ca4a
JB
2020 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2021 i.suffix = SHORT_MNEM_SUFFIX;
2022 else
29b0f896
AM
2023 case BYTE_MNEM_SUFFIX:
2024 case QWORD_MNEM_SUFFIX:
2025 i.suffix = mnem_p[-1];
2026 mnem_p[-1] = '\0';
2027 current_templates = hash_find (op_hash, mnemonic);
2028 break;
2029 case SHORT_MNEM_SUFFIX:
2030 case LONG_MNEM_SUFFIX:
2031 if (!intel_syntax)
2032 {
2033 i.suffix = mnem_p[-1];
2034 mnem_p[-1] = '\0';
2035 current_templates = hash_find (op_hash, mnemonic);
2036 }
2037 break;
252b5132 2038
29b0f896
AM
2039 /* Intel Syntax. */
2040 case 'd':
2041 if (intel_syntax)
2042 {
9306ca4a 2043 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM
2044 i.suffix = SHORT_MNEM_SUFFIX;
2045 else
2046 i.suffix = LONG_MNEM_SUFFIX;
2047 mnem_p[-1] = '\0';
2048 current_templates = hash_find (op_hash, mnemonic);
2049 }
2050 break;
2051 }
2052 if (!current_templates)
2053 {
2054 as_bad (_("no such instruction: `%s'"), token_start);
2055 return NULL;
2056 }
2057 }
252b5132 2058
29b0f896
AM
2059 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2060 {
2061 /* Check for a branch hint. We allow ",pt" and ",pn" for
2062 predict taken and predict not taken respectively.
2063 I'm not sure that branch hints actually do anything on loop
2064 and jcxz insns (JumpByte) for current Pentium4 chips. They
2065 may work in the future and it doesn't hurt to accept them
2066 now. */
2067 if (l[0] == ',' && l[1] == 'p')
2068 {
2069 if (l[2] == 't')
2070 {
2071 if (!add_prefix (DS_PREFIX_OPCODE))
2072 return NULL;
2073 l += 3;
2074 }
2075 else if (l[2] == 'n')
2076 {
2077 if (!add_prefix (CS_PREFIX_OPCODE))
2078 return NULL;
2079 l += 3;
2080 }
2081 }
2082 }
2083 /* Any other comma loses. */
2084 if (*l == ',')
2085 {
2086 as_bad (_("invalid character %s in mnemonic"),
2087 output_invalid (*l));
2088 return NULL;
2089 }
252b5132 2090
29b0f896 2091 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB
2092 supported = 0;
2093 for (t = current_templates->start; t < current_templates->end; ++t)
2094 {
2095 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2096 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2097 supported |= 1;
5c6af06e 2098 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2099 supported |= 2;
5c6af06e
JB
2100 }
2101 if (!(supported & 2))
2102 {
2103 as_bad (flag_code == CODE_64BIT
2104 ? _("`%s' is not supported in 64-bit mode")
2105 : _("`%s' is only supported in 64-bit mode"),
2106 current_templates->start->name);
2107 return NULL;
2108 }
2109 if (!(supported & 1))
29b0f896 2110 {
5c6af06e
JB
2111 as_warn (_("`%s' is not supported on `%s%s'"),
2112 current_templates->start->name,
2113 cpu_arch_name,
2114 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM
2115 }
2116 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2117 {
2118 as_warn (_("use .code16 to ensure correct addressing mode"));
2119 }
252b5132 2120
29b0f896 2121 /* Check for rep/repne without a string instruction. */
f41bbced 2122 if (expecting_string_instruction)
29b0f896 2123 {
f41bbced
JB
2124 static templates override;
2125
2126 for (t = current_templates->start; t < current_templates->end; ++t)
2127 if (t->opcode_modifier & IsString)
2128 break;
2129 if (t >= current_templates->end)
2130 {
2131 as_bad (_("expecting string instruction after `%s'"),
64e74474 2132 expecting_string_instruction);
f41bbced
JB
2133 return NULL;
2134 }
2135 for (override.start = t; t < current_templates->end; ++t)
2136 if (!(t->opcode_modifier & IsString))
2137 break;
2138 override.end = t;
2139 current_templates = &override;
29b0f896 2140 }
252b5132 2141
29b0f896
AM
2142 return l;
2143}
252b5132 2144
29b0f896 2145static char *
e3bb37b5 2146parse_operands (char *l, const char *mnemonic)
29b0f896
AM
2147{
2148 char *token_start;
3138f287 2149
29b0f896
AM
2150 /* 1 if operand is pending after ','. */
2151 unsigned int expecting_operand = 0;
252b5132 2152
29b0f896
AM
2153 /* Non-zero if operand parens not balanced. */
2154 unsigned int paren_not_balanced;
2155
2156 while (*l != END_OF_INSN)
2157 {
2158 /* Skip optional white space before operand. */
2159 if (is_space_char (*l))
2160 ++l;
2161 if (!is_operand_char (*l) && *l != END_OF_INSN)
2162 {
2163 as_bad (_("invalid character %s before operand %d"),
2164 output_invalid (*l),
2165 i.operands + 1);
2166 return NULL;
2167 }
2168 token_start = l; /* after white space */
2169 paren_not_balanced = 0;
2170 while (paren_not_balanced || *l != ',')
2171 {
2172 if (*l == END_OF_INSN)
2173 {
2174 if (paren_not_balanced)
2175 {
2176 if (!intel_syntax)
2177 as_bad (_("unbalanced parenthesis in operand %d."),
2178 i.operands + 1);
2179 else
2180 as_bad (_("unbalanced brackets in operand %d."),
2181 i.operands + 1);
2182 return NULL;
2183 }
2184 else
2185 break; /* we are done */
2186 }
2187 else if (!is_operand_char (*l) && !is_space_char (*l))
2188 {
2189 as_bad (_("invalid character %s in operand %d"),
2190 output_invalid (*l),
2191 i.operands + 1);
2192 return NULL;
2193 }
2194 if (!intel_syntax)
2195 {
2196 if (*l == '(')
2197 ++paren_not_balanced;
2198 if (*l == ')')
2199 --paren_not_balanced;
2200 }
2201 else
2202 {
2203 if (*l == '[')
2204 ++paren_not_balanced;
2205 if (*l == ']')
2206 --paren_not_balanced;
2207 }
2208 l++;
2209 }
2210 if (l != token_start)
2211 { /* Yes, we've read in another operand. */
2212 unsigned int operand_ok;
2213 this_operand = i.operands++;
2214 if (i.operands > MAX_OPERANDS)
2215 {
2216 as_bad (_("spurious operands; (%d operands/instruction max)"),
2217 MAX_OPERANDS);
2218 return NULL;
2219 }
2220 /* Now parse operand adding info to 'i' as we go along. */
2221 END_STRING_AND_SAVE (l);
2222
2223 if (intel_syntax)
2224 operand_ok =
2225 i386_intel_operand (token_start,
2226 intel_float_operand (mnemonic));
2227 else
2228 operand_ok = i386_operand (token_start);
2229
2230 RESTORE_END_STRING (l);
2231 if (!operand_ok)
2232 return NULL;
2233 }
2234 else
2235 {
2236 if (expecting_operand)
2237 {
2238 expecting_operand_after_comma:
2239 as_bad (_("expecting operand after ','; got nothing"));
2240 return NULL;
2241 }
2242 if (*l == ',')
2243 {
2244 as_bad (_("expecting operand before ','; got nothing"));
2245 return NULL;
2246 }
2247 }
7f3f1ea2 2248
29b0f896
AM
2249 /* Now *l must be either ',' or END_OF_INSN. */
2250 if (*l == ',')
2251 {
2252 if (*++l == END_OF_INSN)
2253 {
2254 /* Just skip it, if it's \n complain. */
2255 goto expecting_operand_after_comma;
2256 }
2257 expecting_operand = 1;
2258 }
2259 }
2260 return l;
2261}
7f3f1ea2 2262
050dfa73 2263static void
4d456e3d 2264swap_2_operands (int xchg1, int xchg2)
050dfa73
MM
2265{
2266 union i386_op temp_op;
2267 unsigned int temp_type;
2268 enum bfd_reloc_code_real temp_reloc;
4eed87de 2269
050dfa73
MM
2270 temp_type = i.types[xchg2];
2271 i.types[xchg2] = i.types[xchg1];
2272 i.types[xchg1] = temp_type;
2273 temp_op = i.op[xchg2];
2274 i.op[xchg2] = i.op[xchg1];
2275 i.op[xchg1] = temp_op;
2276 temp_reloc = i.reloc[xchg2];
2277 i.reloc[xchg2] = i.reloc[xchg1];
2278 i.reloc[xchg1] = temp_reloc;
2279}
2280
29b0f896 2281static void
e3bb37b5 2282swap_operands (void)
29b0f896 2283{
b7c61d9a 2284 switch (i.operands)
050dfa73 2285 {
b7c61d9a 2286 case 4:
4d456e3d 2287 swap_2_operands (1, i.operands - 2);
b7c61d9a
L
2288 case 3:
2289 case 2:
4d456e3d 2290 swap_2_operands (0, i.operands - 1);
b7c61d9a
L
2291 break;
2292 default:
2293 abort ();
29b0f896 2294 }
29b0f896
AM
2295
2296 if (i.mem_operands == 2)
2297 {
2298 const seg_entry *temp_seg;
2299 temp_seg = i.seg[0];
2300 i.seg[0] = i.seg[1];
2301 i.seg[1] = temp_seg;
2302 }
2303}
252b5132 2304
29b0f896
AM
2305/* Try to ensure constant immediates are represented in the smallest
2306 opcode possible. */
2307static void
e3bb37b5 2308optimize_imm (void)
29b0f896
AM
2309{
2310 char guess_suffix = 0;
2311 int op;
252b5132 2312
29b0f896
AM
2313 if (i.suffix)
2314 guess_suffix = i.suffix;
2315 else if (i.reg_operands)
2316 {
2317 /* Figure out a suffix from the last register operand specified.
2318 We can't do this properly yet, ie. excluding InOutPortReg,
2319 but the following works for instructions with immediates.
2320 In any case, we can't set i.suffix yet. */
2321 for (op = i.operands; --op >= 0;)
2322 if (i.types[op] & Reg)
252b5132 2323 {
29b0f896
AM
2324 if (i.types[op] & Reg8)
2325 guess_suffix = BYTE_MNEM_SUFFIX;
2326 else if (i.types[op] & Reg16)
2327 guess_suffix = WORD_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg32)
2329 guess_suffix = LONG_MNEM_SUFFIX;
2330 else if (i.types[op] & Reg64)
2331 guess_suffix = QWORD_MNEM_SUFFIX;
2332 break;
252b5132 2333 }
29b0f896
AM
2334 }
2335 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2336 guess_suffix = WORD_MNEM_SUFFIX;
2337
2338 for (op = i.operands; --op >= 0;)
2339 if (i.types[op] & Imm)
2340 {
2341 switch (i.op[op].imms->X_op)
252b5132 2342 {
29b0f896
AM
2343 case O_constant:
2344 /* If a suffix is given, this operand may be shortened. */
2345 switch (guess_suffix)
252b5132 2346 {
29b0f896
AM
2347 case LONG_MNEM_SUFFIX:
2348 i.types[op] |= Imm32 | Imm64;
2349 break;
2350 case WORD_MNEM_SUFFIX:
2351 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2352 break;
2353 case BYTE_MNEM_SUFFIX:
2354 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2355 break;
252b5132 2356 }
252b5132 2357
29b0f896
AM
2358 /* If this operand is at most 16 bits, convert it
2359 to a signed 16 bit number before trying to see
2360 whether it will fit in an even smaller size.
2361 This allows a 16-bit operand such as $0xffe0 to
2362 be recognised as within Imm8S range. */
2363 if ((i.types[op] & Imm16)
2364 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2365 {
29b0f896
AM
2366 i.op[op].imms->X_add_number =
2367 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2368 }
2369 if ((i.types[op] & Imm32)
2370 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2371 == 0))
2372 {
2373 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2374 ^ ((offsetT) 1 << 31))
2375 - ((offsetT) 1 << 31));
2376 }
2377 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2378
29b0f896
AM
2379 /* We must avoid matching of Imm32 templates when 64bit
2380 only immediate is available. */
2381 if (guess_suffix == QWORD_MNEM_SUFFIX)
2382 i.types[op] &= ~Imm32;
2383 break;
252b5132 2384
29b0f896
AM
2385 case O_absent:
2386 case O_register:
2387 abort ();
2388
2389 /* Symbols and expressions. */
2390 default:
9cd96992
JB
2391 /* Convert symbolic operand to proper sizes for matching, but don't
2392 prevent matching a set of insns that only supports sizes other
2393 than those matching the insn suffix. */
2394 {
2395 unsigned int mask, allowed = 0;
2396 const template *t;
2397
4eed87de
AM
2398 for (t = current_templates->start;
2399 t < current_templates->end;
2400 ++t)
2401 allowed |= t->operand_types[op];
9cd96992
JB
2402 switch (guess_suffix)
2403 {
2404 case QWORD_MNEM_SUFFIX:
2405 mask = Imm64 | Imm32S;
2406 break;
2407 case LONG_MNEM_SUFFIX:
2408 mask = Imm32;
2409 break;
2410 case WORD_MNEM_SUFFIX:
2411 mask = Imm16;
2412 break;
2413 case BYTE_MNEM_SUFFIX:
2414 mask = Imm8;
2415 break;
2416 default:
2417 mask = 0;
2418 break;
2419 }
64e74474
AM
2420 if (mask & allowed)
2421 i.types[op] &= mask;
9cd96992 2422 }
29b0f896 2423 break;
252b5132 2424 }
29b0f896
AM
2425 }
2426}
47926f60 2427
29b0f896
AM
2428/* Try to use the smallest displacement type too. */
2429static void
e3bb37b5 2430optimize_disp (void)
29b0f896
AM
2431{
2432 int op;
3e73aa7c 2433
29b0f896 2434 for (op = i.operands; --op >= 0;)
b300c311 2435 if (i.types[op] & Disp)
252b5132 2436 {
b300c311 2437 if (i.op[op].disps->X_op == O_constant)
252b5132 2438 {
b300c311 2439 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2440
b300c311
L
2441 if ((i.types[op] & Disp16)
2442 && (disp & ~(offsetT) 0xffff) == 0)
2443 {
2444 /* If this operand is at most 16 bits, convert
2445 to a signed 16 bit number and don't use 64bit
2446 displacement. */
2447 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2448 i.types[op] &= ~Disp64;
2449 }
2450 if ((i.types[op] & Disp32)
2451 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2452 {
2453 /* If this operand is at most 32 bits, convert
2454 to a signed 32 bit number and don't use 64bit
2455 displacement. */
2456 disp &= (((offsetT) 2 << 31) - 1);
2457 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2458 i.types[op] &= ~Disp64;
2459 }
2460 if (!disp && (i.types[op] & BaseIndex))
2461 {
2462 i.types[op] &= ~Disp;
2463 i.op[op].disps = 0;
2464 i.disp_operands--;
2465 }
2466 else if (flag_code == CODE_64BIT)
2467 {
2468 if (fits_in_signed_long (disp))
28a9d8f5
L
2469 {
2470 i.types[op] &= ~Disp64;
2471 i.types[op] |= Disp32S;
2472 }
b300c311
L
2473 if (fits_in_unsigned_long (disp))
2474 i.types[op] |= Disp32;
2475 }
2476 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2477 && fits_in_signed_byte (disp))
2478 i.types[op] |= Disp8;
252b5132 2479 }
67a4f2b7
AO
2480 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2481 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2482 {
2483 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2484 i.op[op].disps, 0, i.reloc[op]);
2485 i.types[op] &= ~Disp;
2486 }
2487 else
b300c311
L
2488 /* We only support 64bit displacement on constants. */
2489 i.types[op] &= ~Disp64;
252b5132 2490 }
29b0f896
AM
2491}
2492
2493static int
e3bb37b5 2494match_template (void)
29b0f896
AM
2495{
2496 /* Points to template once we've found it. */
2497 const template *t;
f48ff2ae 2498 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM
2499 unsigned int found_reverse_match;
2500 int suffix_check;
f48ff2ae 2501 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2502 int addr_prefix_disp;
a5c311ca 2503 unsigned int j;
29b0f896 2504
f48ff2ae
L
2505#if MAX_OPERANDS != 4
2506# error "MAX_OPERANDS must be 4."
2507#endif
2508
29b0f896
AM
2509#define MATCH(overlap, given, template) \
2510 ((overlap & ~JumpAbsolute) \
2511 && (((given) & (BaseIndex | JumpAbsolute)) \
2512 == ((overlap) & (BaseIndex | JumpAbsolute))))
2513
2514 /* If given types r0 and r1 are registers they must be of the same type
2515 unless the expected operand type register overlap is null.
2516 Note that Acc in a template matches every size of reg. */
2517#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2518 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2519 || ((g0) & Reg) == ((g1) & Reg) \
2520 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2521
2522 overlap0 = 0;
2523 overlap1 = 0;
2524 overlap2 = 0;
f48ff2ae 2525 overlap3 = 0;
29b0f896 2526 found_reverse_match = 0;
a5c311ca
L
2527 for (j = 0; j < MAX_OPERANDS; j++)
2528 operand_types [j] = 0;
539e75ad 2529 addr_prefix_disp = -1;
29b0f896
AM
2530 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2531 ? No_bSuf
2532 : (i.suffix == WORD_MNEM_SUFFIX
2533 ? No_wSuf
2534 : (i.suffix == SHORT_MNEM_SUFFIX
2535 ? No_sSuf
2536 : (i.suffix == LONG_MNEM_SUFFIX
2537 ? No_lSuf
2538 : (i.suffix == QWORD_MNEM_SUFFIX
2539 ? No_qSuf
2540 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2541 ? No_xSuf : 0))))));
2542
45aa61fe 2543 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2544 {
539e75ad
L
2545 addr_prefix_disp = -1;
2546
29b0f896
AM
2547 /* Must have right number of operands. */
2548 if (i.operands != t->operands)
2549 continue;
2550
2551 /* Check the suffix, except for some instructions in intel mode. */
2552 if ((t->opcode_modifier & suffix_check)
2553 && !(intel_syntax
9306ca4a 2554 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM
2555 continue;
2556
a5c311ca
L
2557 for (j = 0; j < MAX_OPERANDS; j++)
2558 operand_types [j] = t->operand_types [j];
539e75ad 2559
45aa61fe
AM
2560 /* In general, don't allow 64-bit operands in 32-bit mode. */
2561 if (i.suffix == QWORD_MNEM_SUFFIX
2562 && flag_code != CODE_64BIT
2563 && (intel_syntax
2564 ? (!(t->opcode_modifier & IgnoreSize)
2565 && !intel_float_operand (t->name))
2566 : intel_float_operand (t->name) != 2)
539e75ad
L
2567 && (!(operand_types[0] & (RegMMX | RegXMM))
2568 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM
2569 && (t->base_opcode != 0x0fc7
2570 || t->extension_opcode != 1 /* cmpxchg8b */))
2571 continue;
2572
29b0f896
AM
2573 /* Do not verify operands when there are none. */
2574 else if (!t->operands)
2575 {
2576 if (t->cpu_flags & ~cpu_arch_flags)
2577 continue;
2578 /* We've found a match; break out of loop. */
2579 break;
2580 }
252b5132 2581
539e75ad
L
2582 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2583 into Disp32/Disp16/Disp32 operand. */
2584 if (i.prefix[ADDR_PREFIX] != 0)
2585 {
a5c311ca 2586 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L
2587
2588 switch (flag_code)
2589 {
2590 case CODE_16BIT:
2591 DispOn = Disp32;
2592 DispOff = Disp16;
2593 break;
2594 case CODE_32BIT:
2595 DispOn = Disp16;
2596 DispOff = Disp32;
2597 break;
2598 case CODE_64BIT:
2599 DispOn = Disp32;
2600 DispOff = Disp64;
2601 break;
2602 }
2603
f48ff2ae 2604 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L
2605 {
2606 /* There should be only one Disp operand. */
2607 if ((operand_types[j] & DispOff))
2608 {
2609 addr_prefix_disp = j;
2610 operand_types[j] |= DispOn;
2611 operand_types[j] &= ~DispOff;
2612 break;
2613 }
2614 }
2615 }
2616
2617 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM
2618 switch (t->operands)
2619 {
2620 case 1:
539e75ad 2621 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM
2622 continue;
2623 break;
2624 case 2:
8b38ad71
L
2625 /* xchg %eax, %eax is a special case. It is an aliase for nop
2626 only in 32bit mode and we can use opcode 0x90. In 64bit
2627 mode, we can't use 0x90 for xchg %eax, %eax since it should
2628 zero-extend %eax to %rax. */
2629 if (flag_code == CODE_64BIT
2630 && t->base_opcode == 0x90
2631 && i.types [0] == (Acc | Reg32)
2632 && i.types [1] == (Acc | Reg32))
2633 continue;
29b0f896 2634 case 3:
f48ff2ae 2635 case 4:
539e75ad
L
2636 overlap1 = i.types[1] & operand_types[1];
2637 if (!MATCH (overlap0, i.types[0], operand_types[0])
2638 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2639 /* monitor in SSE3 is a very special case. The first
708587a4 2640 register and the second register may have different
cb712a9e
L
2641 sizes. */
2642 || !((t->base_opcode == 0x0f01
2643 && t->extension_opcode == 0xc8)
2644 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2645 operand_types[0],
cb712a9e 2646 overlap1, i.types[1],
539e75ad 2647 operand_types[1])))
29b0f896
AM
2648 {
2649 /* Check if other direction is valid ... */
2650 if ((t->opcode_modifier & (D | FloatD)) == 0)
2651 continue;
2652
2653 /* Try reversing direction of operands. */
539e75ad
L
2654 overlap0 = i.types[0] & operand_types[1];
2655 overlap1 = i.types[1] & operand_types[0];
2656 if (!MATCH (overlap0, i.types[0], operand_types[1])
2657 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2658 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2659 operand_types[1],
29b0f896 2660 overlap1, i.types[1],
539e75ad 2661 operand_types[0]))
29b0f896
AM
2662 {
2663 /* Does not match either direction. */
2664 continue;
2665 }
2666 /* found_reverse_match holds which of D or FloatDR
2667 we've found. */
8a2ed489
L
2668 if ((t->opcode_modifier & D))
2669 found_reverse_match = Opcode_D;
2670 else if ((t->opcode_modifier & FloatD))
2671 found_reverse_match = Opcode_FloatD;
2672 else
2673 found_reverse_match = 0;
2674 if ((t->opcode_modifier & FloatR))
2675 found_reverse_match |= Opcode_FloatR;
29b0f896 2676 }
f48ff2ae 2677 else
29b0f896 2678 {
f48ff2ae 2679 /* Found a forward 2 operand match here. */
d1cbb4db
L
2680 switch (t->operands)
2681 {
2682 case 4:
2683 overlap3 = i.types[3] & operand_types[3];
2684 case 3:
2685 overlap2 = i.types[2] & operand_types[2];
2686 break;
2687 }
29b0f896 2688
f48ff2ae
L
2689 switch (t->operands)
2690 {
2691 case 4:
2692 if (!MATCH (overlap3, i.types[3], operand_types[3])
2693 || !CONSISTENT_REGISTER_MATCH (overlap2,
2694 i.types[2],
2695 operand_types[2],
2696 overlap3,
2697 i.types[3],
2698 operand_types[3]))
2699 continue;
2700 case 3:
2701 /* Here we make use of the fact that there are no
2702 reverse match 3 operand instructions, and all 3
2703 operand instructions only need to be checked for
2704 register consistency between operands 2 and 3. */
2705 if (!MATCH (overlap2, i.types[2], operand_types[2])
2706 || !CONSISTENT_REGISTER_MATCH (overlap1,
2707 i.types[1],
2708 operand_types[1],
2709 overlap2,
2710 i.types[2],
2711 operand_types[2]))
2712 continue;
2713 break;
2714 }
29b0f896 2715 }
f48ff2ae 2716 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM
2717 slip through to break. */
2718 }
2719 if (t->cpu_flags & ~cpu_arch_flags)
2720 {
2721 found_reverse_match = 0;
2722 continue;
2723 }
2724 /* We've found a match; break out of loop. */
2725 break;
2726 }
2727
2728 if (t == current_templates->end)
2729 {
2730 /* We found no match. */
2731 as_bad (_("suffix or operands invalid for `%s'"),
2732 current_templates->start->name);
2733 return 0;
2734 }
252b5132 2735
29b0f896
AM
2736 if (!quiet_warnings)
2737 {
2738 if (!intel_syntax
2739 && ((i.types[0] & JumpAbsolute)
539e75ad 2740 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM
2741 {
2742 as_warn (_("indirect %s without `*'"), t->name);
2743 }
2744
2745 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2746 == (IsPrefix | IgnoreSize))
2747 {
2748 /* Warn them that a data or address size prefix doesn't
2749 affect assembly of the next line of code. */
2750 as_warn (_("stand-alone `%s' prefix"), t->name);
2751 }
2752 }
2753
2754 /* Copy the template we found. */
2755 i.tm = *t;
539e75ad
L
2756
2757 if (addr_prefix_disp != -1)
2758 i.tm.operand_types[addr_prefix_disp]
2759 = operand_types[addr_prefix_disp];
2760
29b0f896
AM
2761 if (found_reverse_match)
2762 {
2763 /* If we found a reverse match we must alter the opcode
2764 direction bit. found_reverse_match holds bits to change
2765 (different for int & float insns). */
2766
2767 i.tm.base_opcode ^= found_reverse_match;
2768
539e75ad
L
2769 i.tm.operand_types[0] = operand_types[1];
2770 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM
2771 }
2772
2773 return 1;
2774}
2775
2776static int
e3bb37b5 2777check_string (void)
29b0f896
AM
2778{
2779 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2780 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2781 {
2782 if (i.seg[0] != NULL && i.seg[0] != &es)
2783 {
2784 as_bad (_("`%s' operand %d must use `%%es' segment"),
2785 i.tm.name,
2786 mem_op + 1);
2787 return 0;
2788 }
2789 /* There's only ever one segment override allowed per instruction.
2790 This instruction possibly has a legal segment override on the
2791 second operand, so copy the segment to where non-string
2792 instructions store it, allowing common code. */
2793 i.seg[0] = i.seg[1];
2794 }
2795 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2796 {
2797 if (i.seg[1] != NULL && i.seg[1] != &es)
2798 {
2799 as_bad (_("`%s' operand %d must use `%%es' segment"),
2800 i.tm.name,
2801 mem_op + 2);
2802 return 0;
2803 }
2804 }
2805 return 1;
2806}
2807
2808static int
543613e9 2809process_suffix (void)
29b0f896
AM
2810{
2811 /* If matched instruction specifies an explicit instruction mnemonic
2812 suffix, use it. */
2813 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2814 {
2815 if (i.tm.opcode_modifier & Size16)
2816 i.suffix = WORD_MNEM_SUFFIX;
2817 else if (i.tm.opcode_modifier & Size64)
2818 i.suffix = QWORD_MNEM_SUFFIX;
2819 else
2820 i.suffix = LONG_MNEM_SUFFIX;
2821 }
2822 else if (i.reg_operands)
2823 {
2824 /* If there's no instruction mnemonic suffix we try to invent one
2825 based on register operands. */
2826 if (!i.suffix)
2827 {
2828 /* We take i.suffix from the last register operand specified,
2829 Destination register type is more significant than source
2830 register type. */
2831 int op;
543613e9 2832
29b0f896
AM
2833 for (op = i.operands; --op >= 0;)
2834 if ((i.types[op] & Reg)
2835 && !(i.tm.operand_types[op] & InOutPortReg))
2836 {
2837 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2838 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2839 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2840 LONG_MNEM_SUFFIX);
2841 break;
2842 }
2843 }
2844 else if (i.suffix == BYTE_MNEM_SUFFIX)
2845 {
2846 if (!check_byte_reg ())
2847 return 0;
2848 }
2849 else if (i.suffix == LONG_MNEM_SUFFIX)
2850 {
2851 if (!check_long_reg ())
2852 return 0;
2853 }
2854 else if (i.suffix == QWORD_MNEM_SUFFIX)
2855 {
2856 if (!check_qword_reg ())
2857 return 0;
2858 }
2859 else if (i.suffix == WORD_MNEM_SUFFIX)
2860 {
2861 if (!check_word_reg ())
2862 return 0;
2863 }
2864 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2865 /* Do nothing if the instruction is going to ignore the prefix. */
2866 ;
2867 else
2868 abort ();
2869 }
9306ca4a
JB
2870 else if ((i.tm.opcode_modifier & DefaultSize)
2871 && !i.suffix
2872 /* exclude fldenv/frstor/fsave/fstenv */
2873 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM
2874 {
2875 i.suffix = stackop_size;
2876 }
9306ca4a
JB
2877 else if (intel_syntax
2878 && !i.suffix
2879 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM
2880 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2881 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2882 && i.tm.extension_opcode <= 3)))
9306ca4a
JB
2883 {
2884 switch (flag_code)
2885 {
2886 case CODE_64BIT:
2887 if (!(i.tm.opcode_modifier & No_qSuf))
2888 {
2889 i.suffix = QWORD_MNEM_SUFFIX;
2890 break;
2891 }
2892 case CODE_32BIT:
2893 if (!(i.tm.opcode_modifier & No_lSuf))
2894 i.suffix = LONG_MNEM_SUFFIX;
2895 break;
2896 case CODE_16BIT:
2897 if (!(i.tm.opcode_modifier & No_wSuf))
2898 i.suffix = WORD_MNEM_SUFFIX;
2899 break;
2900 }
2901 }
252b5132 2902
9306ca4a 2903 if (!i.suffix)
29b0f896 2904 {
9306ca4a
JB
2905 if (!intel_syntax)
2906 {
2907 if (i.tm.opcode_modifier & W)
2908 {
4eed87de
AM
2909 as_bad (_("no instruction mnemonic suffix given and "
2910 "no register operands; can't size instruction"));
9306ca4a
JB
2911 return 0;
2912 }
2913 }
2914 else
2915 {
64e74474
AM
2916 unsigned int suffixes = (~i.tm.opcode_modifier
2917 & (No_bSuf
2918 | No_wSuf
2919 | No_lSuf
2920 | No_sSuf
2921 | No_xSuf
2922 | No_qSuf));
9306ca4a
JB
2923
2924 if ((i.tm.opcode_modifier & W)
2925 || ((suffixes & (suffixes - 1))
2926 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2927 {
2928 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2929 return 0;
2930 }
2931 }
29b0f896 2932 }
252b5132 2933
9306ca4a
JB
2934 /* Change the opcode based on the operand size given by i.suffix;
2935 We don't need to change things for byte insns. */
2936
29b0f896
AM
2937 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2938 {
2939 /* It's not a byte, select word/dword operation. */
2940 if (i.tm.opcode_modifier & W)
2941 {
2942 if (i.tm.opcode_modifier & ShortForm)
2943 i.tm.base_opcode |= 8;
2944 else
2945 i.tm.base_opcode |= 1;
2946 }
0f3f3d8b 2947
29b0f896
AM
2948 /* Now select between word & dword operations via the operand
2949 size prefix, except for instructions that will ignore this
2950 prefix anyway. */
cb712a9e
L
2951 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2952 {
2953 /* monitor in SSE3 is a very special case. The default size
2954 of AX is the size of mode. The address size override
2955 prefix will change the size of AX. */
2956 if (i.op->regs[0].reg_type &
2957 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2958 if (!add_prefix (ADDR_PREFIX_OPCODE))
2959 return 0;
2960 }
2961 else if (i.suffix != QWORD_MNEM_SUFFIX
2962 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2963 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2964 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2965 || (flag_code == CODE_64BIT
2966 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM
2967 {
2968 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2969
29b0f896
AM
2970 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2971 prefix = ADDR_PREFIX_OPCODE;
252b5132 2972
29b0f896
AM
2973 if (!add_prefix (prefix))
2974 return 0;
24eab124 2975 }
252b5132 2976
29b0f896
AM
2977 /* Set mode64 for an operand. */
2978 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2979 && flag_code == CODE_64BIT
29b0f896 2980 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L
2981 {
2982 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2983 need rex64. */
2984 if (i.operands != 2
2985 || i.types [0] != (Acc | Reg64)
2986 || i.types [1] != (Acc | Reg64)
13a1e313 2987 || i.tm.base_opcode != 0x90)
f6bee062 2988 i.rex |= REX_W;
46e883c5 2989 }
3e73aa7c 2990
29b0f896
AM
2991 /* Size floating point instruction. */
2992 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC
2993 if (i.tm.opcode_modifier & FloatMF)
2994 i.tm.base_opcode ^= 4;
29b0f896 2995 }
7ecd2f8b 2996
29b0f896
AM
2997 return 1;
2998}
3e73aa7c 2999
29b0f896 3000static int
543613e9 3001check_byte_reg (void)
29b0f896
AM
3002{
3003 int op;
543613e9 3004
29b0f896
AM
3005 for (op = i.operands; --op >= 0;)
3006 {
3007 /* If this is an eight bit register, it's OK. If it's the 16 or
3008 32 bit version of an eight bit register, we will just use the
3009 low portion, and that's OK too. */
3010 if (i.types[op] & Reg8)
3011 continue;
3012
3013 /* movzx and movsx should not generate this warning. */
3014 if (intel_syntax
3015 && (i.tm.base_opcode == 0xfb7
3016 || i.tm.base_opcode == 0xfb6
3017 || i.tm.base_opcode == 0x63
3018 || i.tm.base_opcode == 0xfbe
3019 || i.tm.base_opcode == 0xfbf))
3020 continue;
3021
65ec77d2 3022 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM
3023 {
3024 /* Prohibit these changes in the 64bit mode, since the
3025 lowering is more complicated. */
3026 if (flag_code == CODE_64BIT
3027 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3028 {
2ca3ace5
L
3029 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3030 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
3031 i.suffix);
3032 return 0;
3033 }
3034#if REGISTER_WARNINGS
3035 if (!quiet_warnings
3036 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3037 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3038 (i.op[op].regs + (i.types[op] & Reg16
3039 ? REGNAM_AL - REGNAM_AX
3040 : REGNAM_AL - REGNAM_EAX))->reg_name,
3041 i.op[op].regs->reg_name,
3042 i.suffix);
3043#endif
3044 continue;
3045 }
3046 /* Any other register is bad. */
3047 if (i.types[op] & (Reg | RegMMX | RegXMM
3048 | SReg2 | SReg3
3049 | Control | Debug | Test
3050 | FloatReg | FloatAcc))
3051 {
3052 as_bad (_("`%%%s' not allowed with `%s%c'"),
3053 i.op[op].regs->reg_name,
3054 i.tm.name,
3055 i.suffix);
3056 return 0;
3057 }
3058 }
3059 return 1;
3060}
3061
3062static int
e3bb37b5 3063check_long_reg (void)
29b0f896
AM
3064{
3065 int op;
3066
3067 for (op = i.operands; --op >= 0;)
3068 /* Reject eight bit registers, except where the template requires
3069 them. (eg. movzb) */
3070 if ((i.types[op] & Reg8) != 0
3071 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3072 {
3073 as_bad (_("`%%%s' not allowed with `%s%c'"),
3074 i.op[op].regs->reg_name,
3075 i.tm.name,
3076 i.suffix);
3077 return 0;
3078 }
3079 /* Warn if the e prefix on a general reg is missing. */
3080 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3081 && (i.types[op] & Reg16) != 0
3082 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3083 {
3084 /* Prohibit these changes in the 64bit mode, since the
3085 lowering is more complicated. */
3086 if (flag_code == CODE_64BIT)
252b5132 3087 {
2ca3ace5
L
3088 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3089 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
3090 i.suffix);
3091 return 0;
252b5132 3092 }
29b0f896
AM
3093#if REGISTER_WARNINGS
3094 else
3095 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3096 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3097 i.op[op].regs->reg_name,
3098 i.suffix);
3099#endif
252b5132 3100 }
29b0f896
AM
3101 /* Warn if the r prefix on a general reg is missing. */
3102 else if ((i.types[op] & Reg64) != 0
3103 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3104 {
2ca3ace5
L
3105 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3106 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
3107 i.suffix);
3108 return 0;
3109 }
3110 return 1;
3111}
252b5132 3112
29b0f896 3113static int
e3bb37b5 3114check_qword_reg (void)
29b0f896
AM
3115{
3116 int op;
252b5132 3117
29b0f896
AM
3118 for (op = i.operands; --op >= 0; )
3119 /* Reject eight bit registers, except where the template requires
3120 them. (eg. movzb) */
3121 if ((i.types[op] & Reg8) != 0
3122 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3123 {
3124 as_bad (_("`%%%s' not allowed with `%s%c'"),
3125 i.op[op].regs->reg_name,
3126 i.tm.name,
3127 i.suffix);
3128 return 0;
3129 }
3130 /* Warn if the e prefix on a general reg is missing. */
3131 else if (((i.types[op] & Reg16) != 0
3132 || (i.types[op] & Reg32) != 0)
3133 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3134 {
3135 /* Prohibit these changes in the 64bit mode, since the
3136 lowering is more complicated. */
2ca3ace5
L
3137 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3138 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
3139 i.suffix);
3140 return 0;
252b5132 3141 }
29b0f896
AM
3142 return 1;
3143}
252b5132 3144
29b0f896 3145static int
e3bb37b5 3146check_word_reg (void)
29b0f896
AM
3147{
3148 int op;
3149 for (op = i.operands; --op >= 0;)
3150 /* Reject eight bit registers, except where the template requires
3151 them. (eg. movzb) */
3152 if ((i.types[op] & Reg8) != 0
3153 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3154 {
3155 as_bad (_("`%%%s' not allowed with `%s%c'"),
3156 i.op[op].regs->reg_name,
3157 i.tm.name,
3158 i.suffix);
3159 return 0;
3160 }
3161 /* Warn if the e prefix on a general reg is present. */
3162 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3163 && (i.types[op] & Reg32) != 0
3164 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3165 {
29b0f896
AM
3166 /* Prohibit these changes in the 64bit mode, since the
3167 lowering is more complicated. */
3168 if (flag_code == CODE_64BIT)
252b5132 3169 {
2ca3ace5
L
3170 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3171 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
3172 i.suffix);
3173 return 0;
252b5132 3174 }
29b0f896
AM
3175 else
3176#if REGISTER_WARNINGS
3177 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3178 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3179 i.op[op].regs->reg_name,
3180 i.suffix);
3181#endif
3182 }
3183 return 1;
3184}
252b5132 3185
29b0f896 3186static int
e3bb37b5 3187finalize_imm (void)
29b0f896
AM
3188{
3189 unsigned int overlap0, overlap1, overlap2;
3190
3191 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3192 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM
3193 && overlap0 != Imm8 && overlap0 != Imm8S
3194 && overlap0 != Imm16 && overlap0 != Imm32S
3195 && overlap0 != Imm32 && overlap0 != Imm64)
3196 {
3197 if (i.suffix)
3198 {
3199 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3200 ? Imm8 | Imm8S
3201 : (i.suffix == WORD_MNEM_SUFFIX
3202 ? Imm16
3203 : (i.suffix == QWORD_MNEM_SUFFIX
3204 ? Imm64 | Imm32S
3205 : Imm32)));
3206 }
3207 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3208 || overlap0 == (Imm16 | Imm32)
3209 || overlap0 == (Imm16 | Imm32S))
3210 {
3211 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3212 ? Imm16 : Imm32S);
3213 }
3214 if (overlap0 != Imm8 && overlap0 != Imm8S
3215 && overlap0 != Imm16 && overlap0 != Imm32S
3216 && overlap0 != Imm32 && overlap0 != Imm64)
3217 {
4eed87de
AM
3218 as_bad (_("no instruction mnemonic suffix given; "
3219 "can't determine immediate size"));
29b0f896
AM
3220 return 0;
3221 }
3222 }
3223 i.types[0] = overlap0;
3224
3225 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3226 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM
3227 && overlap1 != Imm8 && overlap1 != Imm8S
3228 && overlap1 != Imm16 && overlap1 != Imm32S
3229 && overlap1 != Imm32 && overlap1 != Imm64)
3230 {
3231 if (i.suffix)
3232 {
3233 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3234 ? Imm8 | Imm8S
3235 : (i.suffix == WORD_MNEM_SUFFIX
3236 ? Imm16
3237 : (i.suffix == QWORD_MNEM_SUFFIX
3238 ? Imm64 | Imm32S
3239 : Imm32)));
3240 }
3241 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3242 || overlap1 == (Imm16 | Imm32)
3243 || overlap1 == (Imm16 | Imm32S))
3244 {
3245 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3246 ? Imm16 : Imm32S);
3247 }
3248 if (overlap1 != Imm8 && overlap1 != Imm8S
3249 && overlap1 != Imm16 && overlap1 != Imm32S
3250 && overlap1 != Imm32 && overlap1 != Imm64)
3251 {
4eed87de
AM
3252 as_bad (_("no instruction mnemonic suffix given; "
3253 "can't determine immediate size %x %c"),
3254 overlap1, i.suffix);
29b0f896
AM
3255 return 0;
3256 }
3257 }
3258 i.types[1] = overlap1;
3259
3260 overlap2 = i.types[2] & i.tm.operand_types[2];
3261 assert ((overlap2 & Imm) == 0);
3262 i.types[2] = overlap2;
3263
3264 return 1;
3265}
3266
3267static int
e3bb37b5 3268process_operands (void)
29b0f896
AM
3269{
3270 /* Default segment register this instruction will use for memory
3271 accesses. 0 means unknown. This is only for optimizing out
3272 unnecessary segment overrides. */
3273 const seg_entry *default_seg = 0;
3274
3275 /* The imul $imm, %reg instruction is converted into
3276 imul $imm, %reg, %reg, and the clr %reg instruction
3277 is converted into xor %reg, %reg. */
3278 if (i.tm.opcode_modifier & regKludge)
3279 {
3280 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3281 /* Pretend we saw the extra register operand. */
cab737b9
L
3282 assert (i.reg_operands == 1
3283 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM
3284 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3285 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L
3286 i.operands++;
3287 i.reg_operands++;
29b0f896
AM
3288 }
3289
3290 if (i.tm.opcode_modifier & ShortForm)
3291 {
4eed87de 3292 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3293 {
4eed87de
AM
3294 if (i.tm.base_opcode == POP_SEG_SHORT
3295 && i.op[0].regs->reg_num == 1)
29b0f896 3296 {
4eed87de
AM
3297 as_bad (_("you can't `pop %%cs'"));
3298 return 0;
29b0f896 3299 }
4eed87de
AM
3300 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3301 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3302 i.rex |= REX_B;
4eed87de
AM
3303 }
3304 else
3305 {
3306 /* The register or float register operand is in operand 0 or 1. */
3307 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3308 /* Register goes in low 3 bits of opcode. */
3309 i.tm.base_opcode |= i.op[op].regs->reg_num;
3310 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3311 i.rex |= REX_B;
4eed87de 3312 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3313 {
4eed87de
AM
3314 /* Warn about some common errors, but press on regardless.
3315 The first case can be generated by gcc (<= 2.8.1). */
3316 if (i.operands == 2)
3317 {
3318 /* Reversed arguments on faddp, fsubp, etc. */
3319 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3320 i.op[1].regs->reg_name,
3321 i.op[0].regs->reg_name);
3322 }
3323 else
3324 {
3325 /* Extraneous `l' suffix on fp insn. */
3326 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3327 i.op[0].regs->reg_name);
3328 }
29b0f896
AM
3329 }
3330 }
3331 }
3332 else if (i.tm.opcode_modifier & Modrm)
3333 {
3334 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM
3335 must be put into the modrm byte). Now, we make the modrm and
3336 index base bytes based on all the info we've collected. */
29b0f896
AM
3337
3338 default_seg = build_modrm_byte ();
3339 }
8a2ed489 3340 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM
3341 {
3342 default_seg = &ds;
3343 }
3344 else if ((i.tm.opcode_modifier & IsString) != 0)
3345 {
3346 /* For the string instructions that allow a segment override
3347 on one of their operands, the default segment is ds. */
3348 default_seg = &ds;
3349 }
3350
30123838
JB
3351 if ((i.tm.base_opcode == 0x8d /* lea */
3352 || (i.tm.cpu_flags & CpuSVME))
3353 && i.seg[0] && !quiet_warnings)
3354 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM
3355
3356 /* If a segment was explicitly specified, and the specified segment
3357 is not the default, use an opcode prefix to select it. If we
3358 never figured out what the default segment is, then default_seg
3359 will be zero at this point, and the specified segment prefix will
3360 always be used. */
29b0f896
AM
3361 if ((i.seg[0]) && (i.seg[0] != default_seg))
3362 {
3363 if (!add_prefix (i.seg[0]->seg_prefix))
3364 return 0;
3365 }
3366 return 1;
3367}
3368
3369static const seg_entry *
e3bb37b5 3370build_modrm_byte (void)
29b0f896
AM
3371{
3372 const seg_entry *default_seg = 0;
3373
3374 /* i.reg_operands MUST be the number of real register operands;
3375 implicit registers do not count. */
3376 if (i.reg_operands == 2)
3377 {
3378 unsigned int source, dest;
cab737b9
L
3379
3380 switch (i.operands)
3381 {
3382 case 2:
3383 source = 0;
3384 break;
3385 case 3:
c81128dc
L
3386 /* When there are 3 operands, one of them may be immediate,
3387 which may be the first or the last operand. Otherwise,
3388 the first operand must be shift count register (cl). */
3389 assert (i.imm_operands == 1
3390 || (i.imm_operands == 0
3391 && (i.types[0] & ShiftCount)));
3392 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L
3393 break;
3394 case 4:
3395 /* When there are 4 operands, the first two must be immediate
3396 operands. The source operand will be the 3rd one. */
3397 assert (i.imm_operands == 2
3398 && (i.types[0] & Imm)
3399 && (i.types[1] & Imm));
3400 source = 2;
3401 break;
3402 default:
3403 abort ();
3404 }
3405
29b0f896
AM
3406 dest = source + 1;
3407
3408 i.rm.mode = 3;
3409 /* One of the register operands will be encoded in the i.tm.reg
3410 field, the other in the combined i.tm.mode and i.tm.regmem
3411 fields. If no form of this instruction supports a memory
3412 destination operand, then we assume the source operand may
3413 sometimes be a memory operand and so we need to store the
3414 destination in the i.rm.reg field. */
e72cf3ec 3415 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM
3416 {
3417 i.rm.reg = i.op[dest].regs->reg_num;
3418 i.rm.regmem = i.op[source].regs->reg_num;
3419 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3420 i.rex |= REX_R;
29b0f896 3421 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3422 i.rex |= REX_B;
29b0f896
AM
3423 }
3424 else
3425 {
3426 i.rm.reg = i.op[source].regs->reg_num;
3427 i.rm.regmem = i.op[dest].regs->reg_num;
3428 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3429 i.rex |= REX_B;
29b0f896 3430 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3431 i.rex |= REX_R;
29b0f896 3432 }
161a04f6 3433 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB
3434 {
3435 if (!((i.types[0] | i.types[1]) & Control))
3436 abort ();
161a04f6 3437 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB
3438 add_prefix (LOCK_PREFIX_OPCODE);
3439 }
29b0f896
AM
3440 }
3441 else
3442 { /* If it's not 2 reg operands... */
3443 if (i.mem_operands)
3444 {
3445 unsigned int fake_zero_displacement = 0;
99018f42 3446 unsigned int op;
4eed87de 3447
99018f42
L
3448 for (op = 0; op < i.operands; op++)
3449 if ((i.types[op] & AnyMem))
3450 break;
3451 assert (op < i.operands);
29b0f896
AM
3452
3453 default_seg = &ds;
3454
3455 if (i.base_reg == 0)
3456 {
3457 i.rm.mode = 0;
3458 if (!i.disp_operands)
3459 fake_zero_displacement = 1;
3460 if (i.index_reg == 0)
3461 {
3462 /* Operand is just <disp> */
20f0a1fc 3463 if (flag_code == CODE_64BIT)
29b0f896
AM
3464 {
3465 /* 64bit mode overwrites the 32bit absolute
3466 addressing by RIP relative addressing and
3467 absolute addressing is encoded by one of the
3468 redundant SIB forms. */
3469 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3470 i.sib.base = NO_BASE_REGISTER;
3471 i.sib.index = NO_INDEX_REGISTER;
fc225355
L
3472 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3473 ? Disp32S : Disp32);
20f0a1fc 3474 }
fc225355
L
3475 else if ((flag_code == CODE_16BIT)
3476 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC
3477 {
3478 i.rm.regmem = NO_BASE_REGISTER_16;
3479 i.types[op] = Disp16;
3480 }
3481 else
3482 {
3483 i.rm.regmem = NO_BASE_REGISTER;
3484 i.types[op] = Disp32;
29b0f896
AM
3485 }
3486 }
3487 else /* !i.base_reg && i.index_reg */
3488 {
3489 i.sib.index = i.index_reg->reg_num;
3490 i.sib.base = NO_BASE_REGISTER;
3491 i.sib.scale = i.log2_scale_factor;
3492 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3493 i.types[op] &= ~Disp;
3494 if (flag_code != CODE_64BIT)
3495 i.types[op] |= Disp32; /* Must be 32 bit */
3496 else
3497 i.types[op] |= Disp32S;
3498 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3499 i.rex |= REX_X;
29b0f896
AM
3500 }
3501 }
3502 /* RIP addressing for 64bit mode. */
3503 else if (i.base_reg->reg_type == BaseIndex)
3504 {
3505 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3506 i.types[op] &= ~ Disp;
29b0f896 3507 i.types[op] |= Disp32S;
71903a11 3508 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC
3509 if (! i.disp_operands)
3510 fake_zero_displacement = 1;
29b0f896
AM
3511 }
3512 else if (i.base_reg->reg_type & Reg16)
3513 {
3514 switch (i.base_reg->reg_num)
3515 {
3516 case 3: /* (%bx) */
3517 if (i.index_reg == 0)
3518 i.rm.regmem = 7;
3519 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3520 i.rm.regmem = i.index_reg->reg_num - 6;
3521 break;
3522 case 5: /* (%bp) */
3523 default_seg = &ss;
3524 if (i.index_reg == 0)
3525 {
3526 i.rm.regmem = 6;
3527 if ((i.types[op] & Disp) == 0)
3528 {
3529 /* fake (%bp) into 0(%bp) */
3530 i.types[op] |= Disp8;
252b5132 3531 fake_zero_displacement = 1;
29b0f896
AM
3532 }
3533 }
3534 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3535 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3536 break;
3537 default: /* (%si) -> 4 or (%di) -> 5 */
3538 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3539 }
3540 i.rm.mode = mode_from_disp_size (i.types[op]);
3541 }
3542 else /* i.base_reg and 32/64 bit mode */
3543 {
3544 if (flag_code == CODE_64BIT
3545 && (i.types[op] & Disp))
fc225355
L
3546 i.types[op] = ((i.types[op] & Disp8)
3547 | (i.prefix[ADDR_PREFIX] == 0
3548 ? Disp32S : Disp32));
20f0a1fc 3549
29b0f896
AM
3550 i.rm.regmem = i.base_reg->reg_num;
3551 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3552 i.rex |= REX_B;
29b0f896
AM
3553 i.sib.base = i.base_reg->reg_num;
3554 /* x86-64 ignores REX prefix bit here to avoid decoder
3555 complications. */
3556 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3557 {
3558 default_seg = &ss;
3559 if (i.disp_operands == 0)
3560 {
3561 fake_zero_displacement = 1;
3562 i.types[op] |= Disp8;
3563 }
3564 }
3565 else if (i.base_reg->reg_num == ESP_REG_NUM)
3566 {
3567 default_seg = &ss;
3568 }
3569 i.sib.scale = i.log2_scale_factor;
3570 if (i.index_reg == 0)
3571 {
3572 /* <disp>(%esp) becomes two byte modrm with no index
3573 register. We've already stored the code for esp
3574 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3575 Any base register besides %esp will not use the
3576 extra modrm byte. */
3577 i.sib.index = NO_INDEX_REGISTER;
3578#if !SCALE1_WHEN_NO_INDEX
3579 /* Another case where we force the second modrm byte. */
3580 if (i.log2_scale_factor)
3581 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3582#endif
29b0f896
AM
3583 }
3584 else
3585 {
3586 i.sib.index = i.index_reg->reg_num;
3587 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3588 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3589 i.rex |= REX_X;
29b0f896 3590 }
67a4f2b7
AO
3591
3592 if (i.disp_operands
3593 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3594 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3595 i.rm.mode = 0;
3596 else
3597 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3598 }
252b5132 3599
29b0f896
AM
3600 if (fake_zero_displacement)
3601 {
3602 /* Fakes a zero displacement assuming that i.types[op]
3603 holds the correct displacement size. */
3604 expressionS *exp;
3605
3606 assert (i.op[op].disps == 0);
3607 exp = &disp_expressions[i.disp_operands++];
3608 i.op[op].disps = exp;
3609 exp->X_op = O_constant;
3610 exp->X_add_number = 0;
3611 exp->X_add_symbol = (symbolS *) 0;
3612 exp->X_op_symbol = (symbolS *) 0;
3613 }
3614 }
252b5132 3615
29b0f896
AM
3616 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3617 (if any) based on i.tm.extension_opcode. Again, we must be
3618 careful to make sure that segment/control/debug/test/MMX
3619 registers are coded into the i.rm.reg field. */
3620 if (i.reg_operands)
3621 {
99018f42
L
3622 unsigned int op;
3623
3624 for (op = 0; op < i.operands; op++)
3625 if ((i.types[op] & (Reg | RegMMX | RegXMM
3626 | SReg2 | SReg3
3627 | Control | Debug | Test)))
3628 break;
3629 assert (op < i.operands);
3630
29b0f896
AM
3631 /* If there is an extension opcode to put here, the register
3632 number must be put into the regmem field. */
3633 if (i.tm.extension_opcode != None)
3634 {
3635 i.rm.regmem = i.op[op].regs->reg_num;
3636 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3637 i.rex |= REX_B;
29b0f896
AM
3638 }
3639 else
3640 {
3641 i.rm.reg = i.op[op].regs->reg_num;
3642 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3643 i.rex |= REX_R;
29b0f896 3644 }
252b5132 3645
29b0f896
AM
3646 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3647 must set it to 3 to indicate this is a register operand
3648 in the regmem field. */
3649 if (!i.mem_operands)
3650 i.rm.mode = 3;
3651 }
252b5132 3652
29b0f896
AM
3653 /* Fill in i.rm.reg field with extension opcode (if any). */
3654 if (i.tm.extension_opcode != None)
3655 i.rm.reg = i.tm.extension_opcode;
3656 }
3657 return default_seg;
3658}
252b5132 3659
29b0f896 3660static void
e3bb37b5 3661output_branch (void)
29b0f896
AM
3662{
3663 char *p;
3664 int code16;
3665 int prefix;
3666 relax_substateT subtype;
3667 symbolS *sym;
3668 offsetT off;
3669
3670 code16 = 0;
3671 if (flag_code == CODE_16BIT)
3672 code16 = CODE16;
3673
3674 prefix = 0;
3675 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3676 {
29b0f896
AM
3677 prefix = 1;
3678 i.prefixes -= 1;
3679 code16 ^= CODE16;
252b5132 3680 }
29b0f896
AM
3681 /* Pentium4 branch hints. */
3682 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3683 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3684 {
29b0f896
AM
3685 prefix++;
3686 i.prefixes--;
3687 }
3688 if (i.prefix[REX_PREFIX] != 0)
3689 {
3690 prefix++;
3691 i.prefixes--;
2f66722d
AM
3692 }
3693
29b0f896
AM
3694 if (i.prefixes != 0 && !intel_syntax)
3695 as_warn (_("skipping prefixes on this instruction"));
3696
3697 /* It's always a symbol; End frag & setup for relax.
3698 Make sure there is enough room in this frag for the largest
3699 instruction we may generate in md_convert_frag. This is 2
3700 bytes for the opcode and room for the prefix and largest
3701 displacement. */
3702 frag_grow (prefix + 2 + 4);
3703 /* Prefix and 1 opcode byte go in fr_fix. */
3704 p = frag_more (prefix + 1);
3705 if (i.prefix[DATA_PREFIX] != 0)
3706 *p++ = DATA_PREFIX_OPCODE;
3707 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3708 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3709 *p++ = i.prefix[SEG_PREFIX];
3710 if (i.prefix[REX_PREFIX] != 0)
3711 *p++ = i.prefix[REX_PREFIX];
3712 *p = i.tm.base_opcode;
3713
3714 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3715 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3716 else if ((cpu_arch_flags & Cpu386) != 0)
3717 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3718 else
3719 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3720 subtype |= code16;
3e73aa7c 3721
29b0f896
AM
3722 sym = i.op[0].disps->X_add_symbol;
3723 off = i.op[0].disps->X_add_number;
3e73aa7c 3724
29b0f896
AM
3725 if (i.op[0].disps->X_op != O_constant
3726 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3727 {
29b0f896
AM
3728 /* Handle complex expressions. */
3729 sym = make_expr_symbol (i.op[0].disps);
3730 off = 0;
3731 }
3e73aa7c 3732
29b0f896
AM
3733 /* 1 possible extra opcode + 4 byte displacement go in var part.
3734 Pass reloc in fr_var. */
3735 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3736}
3e73aa7c 3737
29b0f896 3738static void
e3bb37b5 3739output_jump (void)
29b0f896
AM
3740{
3741 char *p;
3742 int size;
3e02c1cc 3743 fixS *fixP;
29b0f896
AM
3744
3745 if (i.tm.opcode_modifier & JumpByte)
3746 {
3747 /* This is a loop or jecxz type instruction. */
3748 size = 1;
3749 if (i.prefix[ADDR_PREFIX] != 0)
3750 {
3751 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3752 i.prefixes -= 1;
3753 }
3754 /* Pentium4 branch hints. */
3755 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3756 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3757 {
3758 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3759 i.prefixes--;
3e73aa7c
JH
3760 }
3761 }
29b0f896
AM
3762 else
3763 {
3764 int code16;
3e73aa7c 3765
29b0f896
AM
3766 code16 = 0;
3767 if (flag_code == CODE_16BIT)
3768 code16 = CODE16;
3e73aa7c 3769
29b0f896
AM
3770 if (i.prefix[DATA_PREFIX] != 0)
3771 {
3772 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3773 i.prefixes -= 1;
3774 code16 ^= CODE16;
3775 }
252b5132 3776
29b0f896
AM
3777 size = 4;
3778 if (code16)
3779 size = 2;
3780 }
9fcc94b6 3781
29b0f896
AM
3782 if (i.prefix[REX_PREFIX] != 0)
3783 {
3784 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3785 i.prefixes -= 1;
3786 }
252b5132 3787
29b0f896
AM
3788 if (i.prefixes != 0 && !intel_syntax)
3789 as_warn (_("skipping prefixes on this instruction"));
e0890092 3790
29b0f896
AM
3791 p = frag_more (1 + size);
3792 *p++ = i.tm.base_opcode;
e0890092 3793
3e02c1cc
AM
3794 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3795 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3796
3797 /* All jumps handled here are signed, but don't use a signed limit
3798 check for 32 and 16 bit jumps as we want to allow wrap around at
3799 4G and 64k respectively. */
3800 if (size == 1)
3801 fixP->fx_signed = 1;
29b0f896 3802}
e0890092 3803
29b0f896 3804static void
e3bb37b5 3805output_interseg_jump (void)
29b0f896
AM
3806{
3807 char *p;
3808 int size;
3809 int prefix;
3810 int code16;
252b5132 3811
29b0f896
AM
3812 code16 = 0;
3813 if (flag_code == CODE_16BIT)
3814 code16 = CODE16;
a217f122 3815
29b0f896
AM
3816 prefix = 0;
3817 if (i.prefix[DATA_PREFIX] != 0)
3818 {
3819 prefix = 1;
3820 i.prefixes -= 1;
3821 code16 ^= CODE16;
3822 }
3823 if (i.prefix[REX_PREFIX] != 0)
3824 {
3825 prefix++;
3826 i.prefixes -= 1;
3827 }
252b5132 3828
29b0f896
AM
3829 size = 4;
3830 if (code16)
3831 size = 2;
252b5132 3832
29b0f896
AM
3833 if (i.prefixes != 0 && !intel_syntax)
3834 as_warn (_("skipping prefixes on this instruction"));
252b5132 3835
29b0f896
AM
3836 /* 1 opcode; 2 segment; offset */
3837 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3838
29b0f896
AM
3839 if (i.prefix[DATA_PREFIX] != 0)
3840 *p++ = DATA_PREFIX_OPCODE;
252b5132 3841
29b0f896
AM
3842 if (i.prefix[REX_PREFIX] != 0)
3843 *p++ = i.prefix[REX_PREFIX];
252b5132 3844
29b0f896
AM
3845 *p++ = i.tm.base_opcode;
3846 if (i.op[1].imms->X_op == O_constant)
3847 {
3848 offsetT n = i.op[1].imms->X_add_number;
252b5132 3849
29b0f896
AM
3850 if (size == 2
3851 && !fits_in_unsigned_word (n)
3852 && !fits_in_signed_word (n))
3853 {
3854 as_bad (_("16-bit jump out of range"));
3855 return;
3856 }
3857 md_number_to_chars (p, n, size);
3858 }
3859 else
3860 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3861 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3862 if (i.op[0].imms->X_op != O_constant)
3863 as_bad (_("can't handle non absolute segment in `%s'"),
3864 i.tm.name);
3865 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3866}
a217f122 3867
29b0f896 3868static void
e3bb37b5 3869output_insn (void)
29b0f896 3870{
2bbd9c25
JJ
3871 fragS *insn_start_frag;
3872 offsetT insn_start_off;
3873
29b0f896
AM
3874 /* Tie dwarf2 debug info to the address at the start of the insn.
3875 We can't do this after the insn has been output as the current
3876 frag may have been closed off. eg. by frag_var. */
3877 dwarf2_emit_insn (0);
3878
2bbd9c25
JJ
3879 insn_start_frag = frag_now;
3880 insn_start_off = frag_now_fix ();
3881
29b0f896
AM
3882 /* Output jumps. */
3883 if (i.tm.opcode_modifier & Jump)
3884 output_branch ();
3885 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3886 output_jump ();
3887 else if (i.tm.opcode_modifier & JumpInterSegment)
3888 output_interseg_jump ();
3889 else
3890 {
3891 /* Output normal instructions here. */
3892 char *p;
3893 unsigned char *q;
331d2d0d 3894 unsigned int prefix;
252b5132 3895
ef05d495
L
3896 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3897 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3898 use one more higher byte to specify a prefix the instruction
3899 requires. */
3900 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3901 {
331d2d0d
L
3902 if (i.tm.base_opcode & 0xff000000)
3903 {
3904 prefix = (i.tm.base_opcode >> 24) & 0xff;
3905 goto check_prefix;
3906 }
3907 }
3908 else if ((i.tm.base_opcode & 0xff0000) != 0)
3909 {
3910 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK
3911 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3912 {
64e74474 3913 check_prefix:
bc4bd9ab
MK
3914 if (prefix != REPE_PREFIX_OPCODE
3915 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3916 add_prefix (prefix);
3917 }
3918 else
331d2d0d 3919 add_prefix (prefix);
0f10071e 3920 }
252b5132 3921
29b0f896
AM
3922 /* The prefix bytes. */
3923 for (q = i.prefix;
3924 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3925 q++)
3926 {
3927 if (*q)
3928 {
3929 p = frag_more (1);
3930 md_number_to_chars (p, (valueT) *q, 1);
3931 }
3932 }
252b5132 3933
29b0f896
AM
3934 /* Now the opcode; be careful about word order here! */
3935 if (fits_in_unsigned_byte (i.tm.base_opcode))
3936 {
3937 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3938 }
3939 else
3940 {
ef05d495 3941 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L
3942 {
3943 p = frag_more (3);
3944 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3945 }
3946 else
3947 p = frag_more (2);
0f10071e 3948
29b0f896
AM
3949 /* Put out high byte first: can't use md_number_to_chars! */
3950 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3951 *p = i.tm.base_opcode & 0xff;
3952 }
3e73aa7c 3953
29b0f896
AM
3954 /* Now the modrm byte and sib byte (if present). */
3955 if (i.tm.opcode_modifier & Modrm)
3956 {
3957 p = frag_more (1);
3958 md_number_to_chars (p,
3959 (valueT) (i.rm.regmem << 0
3960 | i.rm.reg << 3
3961 | i.rm.mode << 6),
3962 1);
3963 /* If i.rm.regmem == ESP (4)
3964 && i.rm.mode != (Register mode)
3965 && not 16 bit
3966 ==> need second modrm byte. */
3967 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3968 && i.rm.mode != 3
3969 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3970 {
3971 p = frag_more (1);
3972 md_number_to_chars (p,
3973 (valueT) (i.sib.base << 0
3974 | i.sib.index << 3
3975 | i.sib.scale << 6),
3976 1);
3977 }
3978 }
3e73aa7c 3979
29b0f896 3980 if (i.disp_operands)
2bbd9c25 3981 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3982
29b0f896 3983 if (i.imm_operands)
2bbd9c25 3984 output_imm (insn_start_frag, insn_start_off);
29b0f896 3985 }
252b5132 3986
29b0f896
AM
3987#ifdef DEBUG386
3988 if (flag_debug)
3989 {
7b81dfbb 3990 pi ("" /*line*/, &i);
29b0f896
AM
3991 }
3992#endif /* DEBUG386 */
3993}
252b5132 3994
29b0f896 3995static void
64e74474 3996output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM
3997{
3998 char *p;
3999 unsigned int n;
252b5132 4000
29b0f896
AM
4001 for (n = 0; n < i.operands; n++)
4002 {
4003 if (i.types[n] & Disp)
4004 {
4005 if (i.op[n].disps->X_op == O_constant)
4006 {
4007 int size;
4008 offsetT val;
252b5132 4009
29b0f896
AM
4010 size = 4;
4011 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4012 {
4013 size = 2;
4014 if (i.types[n] & Disp8)
4015 size = 1;
4016 if (i.types[n] & Disp64)
4017 size = 8;
4018 }
4019 val = offset_in_range (i.op[n].disps->X_add_number,
4020 size);
4021 p = frag_more (size);
4022 md_number_to_chars (p, val, size);
4023 }
4024 else
4025 {
f86103b7 4026 enum bfd_reloc_code_real reloc_type;
29b0f896
AM
4027 int size = 4;
4028 int sign = 0;
4029 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4030
4031 /* The PC relative address is computed relative
4032 to the instruction boundary, so in case immediate
4033 fields follows, we need to adjust the value. */
4034 if (pcrel && i.imm_operands)
4035 {
4036 int imm_size = 4;
4037 unsigned int n1;
252b5132 4038
29b0f896
AM
4039 for (n1 = 0; n1 < i.operands; n1++)
4040 if (i.types[n1] & Imm)
252b5132 4041 {
29b0f896 4042 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4043 {
29b0f896
AM
4044 imm_size = 2;
4045 if (i.types[n1] & (Imm8 | Imm8S))
4046 imm_size = 1;
4047 if (i.types[n1] & Imm64)
4048 imm_size = 8;
252b5132 4049 }
29b0f896 4050 break;
252b5132 4051 }
29b0f896
AM
4052 /* We should find the immediate. */
4053 if (n1 == i.operands)
4054 abort ();
4055 i.op[n].disps->X_add_number -= imm_size;
4056 }
520dc8e8 4057
29b0f896
AM
4058 if (i.types[n] & Disp32S)
4059 sign = 1;
3e73aa7c 4060
29b0f896
AM
4061 if (i.types[n] & (Disp16 | Disp64))
4062 {
4063 size = 2;
4064 if (i.types[n] & Disp64)
4065 size = 8;
4066 }
520dc8e8 4067
29b0f896 4068 p = frag_more (size);
2bbd9c25 4069 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4070 if (GOT_symbol
2bbd9c25 4071 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4072 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ
4073 || reloc_type == BFD_RELOC_X86_64_32S
4074 || (reloc_type == BFD_RELOC_64
4075 && object_64bit))
d6ab8113
JB
4076 && (i.op[n].disps->X_op == O_symbol
4077 || (i.op[n].disps->X_op == O_add
4078 && ((symbol_get_value_expression
4079 (i.op[n].disps->X_op_symbol)->X_op)
4080 == O_subtract))))
4081 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ
4082 {
4083 offsetT add;
4084
4085 if (insn_start_frag == frag_now)
4086 add = (p - frag_now->fr_literal) - insn_start_off;
4087 else
4088 {
4089 fragS *fr;
4090
4091 add = insn_start_frag->fr_fix - insn_start_off;
4092 for (fr = insn_start_frag->fr_next;
4093 fr && fr != frag_now; fr = fr->fr_next)
4094 add += fr->fr_fix;
4095 add += p - frag_now->fr_literal;
4096 }
4097
4fa24527 4098 if (!object_64bit)
7b81dfbb
AJ
4099 {
4100 reloc_type = BFD_RELOC_386_GOTPC;
4101 i.op[n].imms->X_add_number += add;
4102 }
4103 else if (reloc_type == BFD_RELOC_64)
4104 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4105 else
7b81dfbb
AJ
4106 /* Don't do the adjustment for x86-64, as there
4107 the pcrel addressing is relative to the _next_
4108 insn, and that is taken care of in other code. */
d6ab8113 4109 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4110 }
062cd5e7 4111 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4112 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM
4113 }
4114 }
4115 }
4116}
252b5132 4117
29b0f896 4118static void
64e74474 4119output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM
4120{
4121 char *p;
4122 unsigned int n;
252b5132 4123
29b0f896
AM
4124 for (n = 0; n < i.operands; n++)
4125 {
4126 if (i.types[n] & Imm)
4127 {
4128 if (i.op[n].imms->X_op == O_constant)
4129 {
4130 int size;
4131 offsetT val;
b4cac588 4132
29b0f896
AM
4133 size = 4;
4134 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4135 {
4136 size = 2;
4137 if (i.types[n] & (Imm8 | Imm8S))
4138 size = 1;
4139 else if (i.types[n] & Imm64)
4140 size = 8;
4141 }
4142 val = offset_in_range (i.op[n].imms->X_add_number,
4143 size);
4144 p = frag_more (size);
4145 md_number_to_chars (p, val, size);
4146 }
4147 else
4148 {
4149 /* Not absolute_section.
4150 Need a 32-bit fixup (don't support 8bit
4151 non-absolute imms). Try to support other
4152 sizes ... */
f86103b7 4153 enum bfd_reloc_code_real reloc_type;
29b0f896
AM
4154 int size = 4;
4155 int sign = 0;
4156
4157 if ((i.types[n] & (Imm32S))
a7d61044
JB
4158 && (i.suffix == QWORD_MNEM_SUFFIX
4159 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM
4160 sign = 1;
4161 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4162 {
4163 size = 2;
4164 if (i.types[n] & (Imm8 | Imm8S))
4165 size = 1;
4166 if (i.types[n] & Imm64)
4167 size = 8;
4168 }
520dc8e8 4169
29b0f896
AM
4170 p = frag_more (size);
4171 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4172
2bbd9c25
JJ
4173 /* This is tough to explain. We end up with this one if we
4174 * have operands that look like
4175 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4176 * obtain the absolute address of the GOT, and it is strongly
4177 * preferable from a performance point of view to avoid using
4178 * a runtime relocation for this. The actual sequence of
4179 * instructions often look something like:
4180 *
4181 * call .L66
4182 * .L66:
4183 * popl %ebx
4184 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4185 *
4186 * The call and pop essentially return the absolute address
4187 * of the label .L66 and store it in %ebx. The linker itself
4188 * will ultimately change the first operand of the addl so
4189 * that %ebx points to the GOT, but to keep things simple, the
4190 * .o file must have this operand set so that it generates not
4191 * the absolute address of .L66, but the absolute address of
4192 * itself. This allows the linker itself simply treat a GOTPC
4193 * relocation as asking for a pcrel offset to the GOT to be
4194 * added in, and the addend of the relocation is stored in the
4195 * operand field for the instruction itself.
4196 *
4197 * Our job here is to fix the operand so that it would add
4198 * the correct offset so that %ebx would point to itself. The
4199 * thing that is tricky is that .-.L66 will point to the
4200 * beginning of the instruction, so we need to further modify
4201 * the operand so that it will point to itself. There are
4202 * other cases where you have something like:
4203 *
4204 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4205 *
4206 * and here no correction would be required. Internally in
4207 * the assembler we treat operands of this form as not being
4208 * pcrel since the '.' is explicitly mentioned, and I wonder
4209 * whether it would simplify matters to do it this way. Who
4210 * knows. In earlier versions of the PIC patches, the
4211 * pcrel_adjust field was used to store the correction, but
4212 * since the expression is not pcrel, I felt it would be
4213 * confusing to do it this way. */
4214
d6ab8113 4215 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ
4216 || reloc_type == BFD_RELOC_X86_64_32S
4217 || reloc_type == BFD_RELOC_64)
29b0f896
AM
4218 && GOT_symbol
4219 && GOT_symbol == i.op[n].imms->X_add_symbol
4220 && (i.op[n].imms->X_op == O_symbol
4221 || (i.op[n].imms->X_op == O_add
4222 && ((symbol_get_value_expression
4223 (i.op[n].imms->X_op_symbol)->X_op)
4224 == O_subtract))))
4225 {
2bbd9c25
JJ
4226 offsetT add;
4227
4228 if (insn_start_frag == frag_now)
4229 add = (p - frag_now->fr_literal) - insn_start_off;
4230 else
4231 {
4232 fragS *fr;
4233
4234 add = insn_start_frag->fr_fix - insn_start_off;
4235 for (fr = insn_start_frag->fr_next;
4236 fr && fr != frag_now; fr = fr->fr_next)
4237 add += fr->fr_fix;
4238 add += p - frag_now->fr_literal;
4239 }
4240
4fa24527 4241 if (!object_64bit)
d6ab8113 4242 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4243 else if (size == 4)
d6ab8113 4244 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ
4245 else if (size == 8)
4246 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4247 i.op[n].imms->X_add_number += add;
29b0f896 4248 }
29b0f896
AM
4249 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4250 i.op[n].imms, 0, reloc_type);
4251 }
4252 }
4253 }
252b5132
RH
4254}
4255\f
d182319b
JB
4256/* x86_cons_fix_new is called via the expression parsing code when a
4257 reloc is needed. We use this hook to get the correct .got reloc. */
4258static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4259static int cons_sign = -1;
4260
4261void
e3bb37b5 4262x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4263 expressionS *exp)
d182319b
JB
4264{
4265 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4266
4267 got_reloc = NO_RELOC;
4268
4269#ifdef TE_PE
4270 if (exp->X_op == O_secrel)
4271 {
4272 exp->X_op = O_symbol;
4273 r = BFD_RELOC_32_SECREL;
4274 }
4275#endif
4276
4277 fix_new_exp (frag, off, len, exp, 0, r);
4278}
4279
718ddfc0
JB
4280#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4281# define lex_got(reloc, adjust, types) NULL
4282#else
f3c180ae
AM
4283/* Parse operands of the form
4284 <symbol>@GOTOFF+<nnn>
4285 and similar .plt or .got references.
4286
4287 If we find one, set up the correct relocation in RELOC and copy the
4288 input string, minus the `@GOTOFF' into a malloc'd buffer for
4289 parsing by the calling routine. Return this buffer, and if ADJUST
4290 is non-null set it to the length of the string we removed from the
4291 input line. Otherwise return NULL. */
4292static char *
3956db08 4293lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM
4294 int *adjust,
4295 unsigned int *types)
f3c180ae 4296{
7b81dfbb
AJ
4297 /* Some of the relocations depend on the size of what field is to
4298 be relocated. But in our callers i386_immediate and i386_displacement
4299 we don't yet know the operand size (this will be set by insn
4300 matching). Hence we record the word32 relocation here,
4301 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM
4302 static const struct {
4303 const char *str;
4fa24527 4304 const enum bfd_reloc_code_real rel[2];
3956db08 4305 const unsigned int types64;
f3c180ae 4306 } gotrel[] = {
4eed87de
AM
4307 { "PLTOFF", { 0,
4308 BFD_RELOC_X86_64_PLTOFF64 },
4309 Imm64 },
4310 { "PLT", { BFD_RELOC_386_PLT32,
4311 BFD_RELOC_X86_64_PLT32 },
4312 Imm32 | Imm32S | Disp32 },
4313 { "GOTPLT", { 0,
4314 BFD_RELOC_X86_64_GOTPLT64 },
4315 Imm64 | Disp64 },
4316 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4317 BFD_RELOC_X86_64_GOTOFF64 },
4318 Imm64 | Disp64 },
4319 { "GOTPCREL", { 0,
4320 BFD_RELOC_X86_64_GOTPCREL },
4321 Imm32 | Imm32S | Disp32 },
4322 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4323 BFD_RELOC_X86_64_TLSGD },
4324 Imm32 | Imm32S | Disp32 },
4325 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4326 0 },
4327 0 },
4328 { "TLSLD", { 0,
4329 BFD_RELOC_X86_64_TLSLD },
4330 Imm32 | Imm32S | Disp32 },
4331 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4332 BFD_RELOC_X86_64_GOTTPOFF },
4333 Imm32 | Imm32S | Disp32 },
4334 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4335 BFD_RELOC_X86_64_TPOFF32 },
4336 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4337 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4338 0 },
4339 0 },
4340 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4341 BFD_RELOC_X86_64_DTPOFF32 },
4342 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4343 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4344 0 },
4345 0 },
4346 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4347 0 },
4348 0 },
4349 { "GOT", { BFD_RELOC_386_GOT32,
4350 BFD_RELOC_X86_64_GOT32 },
4351 Imm32 | Imm32S | Disp32 | Imm64 },
4352 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4353 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4354 Imm32 | Imm32S | Disp32 },
4355 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4356 BFD_RELOC_X86_64_TLSDESC_CALL },
4357 Imm32 | Imm32S | Disp32 }
f3c180ae
AM
4358 };
4359 char *cp;
4360 unsigned int j;
4361
718ddfc0
JB
4362 if (!IS_ELF)
4363 return NULL;
4364
f3c180ae
AM
4365 for (cp = input_line_pointer; *cp != '@'; cp++)
4366 if (is_end_of_line[(unsigned char) *cp])
4367 return NULL;
4368
4369 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4370 {
4371 int len;
4372
4373 len = strlen (gotrel[j].str);
28f81592 4374 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4375 {
4fa24527 4376 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4377 {
28f81592
AM
4378 int first, second;
4379 char *tmpbuf, *past_reloc;
f3c180ae 4380
4fa24527 4381 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM
4382 if (adjust)
4383 *adjust = len;
f3c180ae 4384
3956db08
JB
4385 if (types)
4386 {
4387 if (flag_code != CODE_64BIT)
4eed87de 4388 *types = Imm32 | Disp32;
3956db08
JB
4389 else
4390 *types = gotrel[j].types64;
4391 }
4392
f3c180ae
AM
4393 if (GOT_symbol == NULL)
4394 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4395
4396 /* Replace the relocation token with ' ', so that
4397 errors like foo@GOTOFF1 will be detected. */
28f81592
AM
4398
4399 /* The length of the first part of our input line. */
f3c180ae 4400 first = cp - input_line_pointer;
28f81592
AM
4401
4402 /* The second part goes from after the reloc token until
4403 (and including) an end_of_line char. Don't use strlen
4404 here as the end_of_line char may not be a NUL. */
4405 past_reloc = cp + 1 + len;
4406 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4407 ;
4408 second = cp - past_reloc;
4409
4410 /* Allocate and copy string. The trailing NUL shouldn't
4411 be necessary, but be safe. */
4412 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM
4413 memcpy (tmpbuf, input_line_pointer, first);
4414 tmpbuf[first] = ' ';
28f81592
AM
4415 memcpy (tmpbuf + first + 1, past_reloc, second);
4416 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM
4417 return tmpbuf;
4418 }
4419
4fa24527
JB
4420 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4421 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM
4422 return NULL;
4423 }
4424 }
4425
4426 /* Might be a symbol version string. Don't as_bad here. */
4427 return NULL;
4428}
4429
f3c180ae 4430void
e3bb37b5 4431x86_cons (expressionS *exp, int size)
f3c180ae 4432{
4fa24527 4433 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM
4434 {
4435 /* Handle @GOTOFF and the like in an expression. */
4436 char *save;
4437 char *gotfree_input_line;
4438 int adjust;
4439
4440 save = input_line_pointer;
3956db08 4441 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM
4442 if (gotfree_input_line)
4443 input_line_pointer = gotfree_input_line;
4444
4445 expression (exp);
4446
4447 if (gotfree_input_line)
4448 {
4449 /* expression () has merrily parsed up to the end of line,
4450 or a comma - in the wrong buffer. Transfer how far
4451 input_line_pointer has moved to the right buffer. */
4452 input_line_pointer = (save
4453 + (input_line_pointer - gotfree_input_line)
4454 + adjust);
4455 free (gotfree_input_line);
4456 }
4457 }
4458 else
4459 expression (exp);
4460}
4461#endif
4462
d182319b 4463static void signed_cons (int size)
6482c264 4464{
d182319b
JB
4465 if (flag_code == CODE_64BIT)
4466 cons_sign = 1;
4467 cons (size);
4468 cons_sign = -1;
6482c264
NC
4469}
4470
d182319b 4471#ifdef TE_PE
6482c264
NC
4472static void
4473pe_directive_secrel (dummy)
4474 int dummy ATTRIBUTE_UNUSED;
4475{
4476 expressionS exp;
4477
4478 do
4479 {
4480 expression (&exp);
4481 if (exp.X_op == O_symbol)
4482 exp.X_op = O_secrel;
4483
4484 emit_expr (&exp, 4);
4485 }
4486 while (*input_line_pointer++ == ',');
4487
4488 input_line_pointer--;
4489 demand_empty_rest_of_line ();
4490}
6482c264
NC
4491#endif
4492
252b5132 4493static int
70e41ade 4494i386_immediate (char *imm_start)
252b5132
RH
4495{
4496 char *save_input_line_pointer;
f3c180ae 4497 char *gotfree_input_line;
252b5132 4498 segT exp_seg = 0;
47926f60 4499 expressionS *exp;
3956db08 4500 unsigned int types = ~0U;
252b5132
RH
4501
4502 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4503 {
31b2323c
L
4504 as_bad (_("at most %d immediate operands are allowed"),
4505 MAX_IMMEDIATE_OPERANDS);
252b5132
RH
4506 return 0;
4507 }
4508
4509 exp = &im_expressions[i.imm_operands++];
520dc8e8 4510 i.op[this_operand].imms = exp;
252b5132
RH
4511
4512 if (is_space_char (*imm_start))
4513 ++imm_start;
4514
4515 save_input_line_pointer = input_line_pointer;
4516 input_line_pointer = imm_start;
4517
3956db08 4518 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM
4519 if (gotfree_input_line)
4520 input_line_pointer = gotfree_input_line;
252b5132
RH
4521
4522 exp_seg = expression (exp);
4523
83183c0c 4524 SKIP_WHITESPACE ();
252b5132 4525 if (*input_line_pointer)
f3c180ae 4526 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH
4527
4528 input_line_pointer = save_input_line_pointer;
f3c180ae
AM
4529 if (gotfree_input_line)
4530 free (gotfree_input_line);
252b5132 4531
2daf4fd8 4532 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4533 {
47926f60 4534 /* Missing or bad expr becomes absolute 0. */
d0b47220 4535 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4536 imm_start);
252b5132
RH
4537 exp->X_op = O_constant;
4538 exp->X_add_number = 0;
4539 exp->X_add_symbol = (symbolS *) 0;
4540 exp->X_op_symbol = (symbolS *) 0;
252b5132 4541 }
3e73aa7c 4542 else if (exp->X_op == O_constant)
252b5132 4543 {
47926f60 4544 /* Size it properly later. */
3e73aa7c
JH
4545 i.types[this_operand] |= Imm64;
4546 /* If BFD64, sign extend val. */
4eed87de
AM
4547 if (!use_rela_relocations
4548 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4549 exp->X_add_number
4550 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4551 }
4c63da97 4552#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4553 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4554 && exp_seg != absolute_section
47926f60 4555 && exp_seg != text_section
24eab124
AM
4556 && exp_seg != data_section
4557 && exp_seg != bss_section
4558 && exp_seg != undefined_section
f86103b7 4559 && !bfd_is_com_section (exp_seg))
252b5132 4560 {
d0b47220 4561 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH
4562 return 0;
4563 }
4564#endif
bb8f5920
L
4565 else if (!intel_syntax && exp->X_op == O_register)
4566 {
4567 as_bad (_("illegal immediate register operand %s"), imm_start);
4568 return 0;
4569 }
252b5132
RH
4570 else
4571 {
4572 /* This is an address. The size of the address will be
24eab124 4573 determined later, depending on destination register,
3e73aa7c
JH
4574 suffix, or the default for the section. */
4575 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4576 i.types[this_operand] &= types;
252b5132
RH
4577 }
4578
4579 return 1;
4580}
4581
551c1ca1 4582static char *
e3bb37b5 4583i386_scale (char *scale)
252b5132 4584{
551c1ca1
AM
4585 offsetT val;
4586 char *save = input_line_pointer;
252b5132 4587
551c1ca1
AM
4588 input_line_pointer = scale;
4589 val = get_absolute_expression ();
4590
4591 switch (val)
252b5132 4592 {
551c1ca1 4593 case 1:
252b5132
RH
4594 i.log2_scale_factor = 0;
4595 break;
551c1ca1 4596 case 2:
252b5132
RH
4597 i.log2_scale_factor = 1;
4598 break;
551c1ca1 4599 case 4:
252b5132
RH
4600 i.log2_scale_factor = 2;
4601 break;
551c1ca1 4602 case 8:
252b5132
RH
4603 i.log2_scale_factor = 3;
4604 break;
4605 default:
a724f0f4
JB
4606 {
4607 char sep = *input_line_pointer;
4608
4609 *input_line_pointer = '\0';
4610 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4611 scale);
4612 *input_line_pointer = sep;
4613 input_line_pointer = save;
4614 return NULL;
4615 }
252b5132 4616 }
29b0f896 4617 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH
4618 {
4619 as_warn (_("scale factor of %d without an index register"),
24eab124 4620 1 << i.log2_scale_factor);
252b5132
RH
4621#if SCALE1_WHEN_NO_INDEX
4622 i.log2_scale_factor = 0;
4623#endif
4624 }
551c1ca1
AM
4625 scale = input_line_pointer;
4626 input_line_pointer = save;
4627 return scale;
252b5132
RH
4628}
4629
252b5132 4630static int
e3bb37b5 4631i386_displacement (char *disp_start, char *disp_end)
252b5132 4632{
29b0f896 4633 expressionS *exp;
252b5132
RH
4634 segT exp_seg = 0;
4635 char *save_input_line_pointer;
f3c180ae 4636 char *gotfree_input_line;
e05278af 4637 int bigdisp, override;
3956db08 4638 unsigned int types = Disp;
252b5132 4639
31b2323c
L
4640 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4641 {
4642 as_bad (_("at most %d displacement operands are allowed"),
4643 MAX_MEMORY_OPERANDS);
4644 return 0;
4645 }
4646
e05278af
JB
4647 if ((i.types[this_operand] & JumpAbsolute)
4648 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4649 {
4650 bigdisp = Disp32;
4651 override = (i.prefix[ADDR_PREFIX] != 0);
4652 }
4653 else
4654 {
4655 /* For PC-relative branches, the width of the displacement
4656 is dependent upon data size, not address size. */
4657 bigdisp = 0;
4658 override = (i.prefix[DATA_PREFIX] != 0);
4659 }
3e73aa7c 4660 if (flag_code == CODE_64BIT)
7ecd2f8b 4661 {
e05278af 4662 if (!bigdisp)
64e74474
AM
4663 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4664 ? Disp16
4665 : Disp32S | Disp32);
e05278af 4666 else if (!override)
3956db08 4667 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4668 }
e05278af
JB
4669 else
4670 {
4671 if (!bigdisp)
4672 {
4673 if (!override)
4674 override = (i.suffix == (flag_code != CODE_16BIT
4675 ? WORD_MNEM_SUFFIX
4676 : LONG_MNEM_SUFFIX));
4677 bigdisp = Disp32;
4678 }
4679 if ((flag_code == CODE_16BIT) ^ override)
4680 bigdisp = Disp16;
4681 }
252b5132
RH
4682 i.types[this_operand] |= bigdisp;
4683
4684 exp = &disp_expressions[i.disp_operands];
520dc8e8 4685 i.op[this_operand].disps = exp;
252b5132
RH
4686 i.disp_operands++;
4687 save_input_line_pointer = input_line_pointer;
4688 input_line_pointer = disp_start;
4689 END_STRING_AND_SAVE (disp_end);
4690
4691#ifndef GCC_ASM_O_HACK
4692#define GCC_ASM_O_HACK 0
4693#endif
4694#if GCC_ASM_O_HACK
4695 END_STRING_AND_SAVE (disp_end + 1);
4696 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4697 && displacement_string_end[-1] == '+')
252b5132
RH
4698 {
4699 /* This hack is to avoid a warning when using the "o"
24eab124
AM
4700 constraint within gcc asm statements.
4701 For instance:
4702
4703 #define _set_tssldt_desc(n,addr,limit,type) \
4704 __asm__ __volatile__ ( \
4705 "movw %w2,%0\n\t" \
4706 "movw %w1,2+%0\n\t" \
4707 "rorl $16,%1\n\t" \
4708 "movb %b1,4+%0\n\t" \
4709 "movb %4,5+%0\n\t" \
4710 "movb $0,6+%0\n\t" \
4711 "movb %h1,7+%0\n\t" \
4712 "rorl $16,%1" \
4713 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4714
4715 This works great except that the output assembler ends
4716 up looking a bit weird if it turns out that there is
4717 no offset. You end up producing code that looks like:
4718
4719 #APP
4720 movw $235,(%eax)
4721 movw %dx,2+(%eax)
4722 rorl $16,%edx
4723 movb %dl,4+(%eax)
4724 movb $137,5+(%eax)
4725 movb $0,6+(%eax)
4726 movb %dh,7+(%eax)
4727 rorl $16,%edx
4728 #NO_APP
4729
47926f60 4730 So here we provide the missing zero. */
24eab124
AM
4731
4732 *displacement_string_end = '0';
252b5132
RH
4733 }
4734#endif
3956db08 4735 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM
4736 if (gotfree_input_line)
4737 input_line_pointer = gotfree_input_line;
252b5132 4738
24eab124 4739 exp_seg = expression (exp);
252b5132 4740
636c26b0
AM
4741 SKIP_WHITESPACE ();
4742 if (*input_line_pointer)
4743 as_bad (_("junk `%s' after expression"), input_line_pointer);
4744#if GCC_ASM_O_HACK
4745 RESTORE_END_STRING (disp_end + 1);
4746#endif
4747 RESTORE_END_STRING (disp_end);
4748 input_line_pointer = save_input_line_pointer;
636c26b0
AM
4749 if (gotfree_input_line)
4750 free (gotfree_input_line);
636c26b0 4751
24eab124
AM
4752 /* We do this to make sure that the section symbol is in
4753 the symbol table. We will ultimately change the relocation
47926f60 4754 to be relative to the beginning of the section. */
1ae12ab7 4755 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB
4756 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4757 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4758 {
636c26b0
AM
4759 if (exp->X_op != O_symbol)
4760 {
4761 as_bad (_("bad expression used with @%s"),
4762 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4763 ? "GOTPCREL"
4764 : "GOTOFF"));
4765 return 0;
4766 }
4767
e5cb08ac 4768 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM
4769 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4770 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM
4771 exp->X_op = O_subtract;
4772 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4773 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4774 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB
4775 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4776 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4777 else
29b0f896 4778 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4779 }
252b5132 4780
2daf4fd8
AM
4781 if (exp->X_op == O_absent || exp->X_op == O_big)
4782 {
47926f60 4783 /* Missing or bad expr becomes absolute 0. */
d0b47220 4784 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM
4785 disp_start);
4786 exp->X_op = O_constant;
4787 exp->X_add_number = 0;
4788 exp->X_add_symbol = (symbolS *) 0;
4789 exp->X_op_symbol = (symbolS *) 0;
4790 }
4791
4c63da97 4792#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4793 if (exp->X_op != O_constant
45288df1 4794 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4795 && exp_seg != absolute_section
45288df1
AM
4796 && exp_seg != text_section
4797 && exp_seg != data_section
4798 && exp_seg != bss_section
31312f95 4799 && exp_seg != undefined_section
f86103b7 4800 && !bfd_is_com_section (exp_seg))
24eab124 4801 {
d0b47220 4802 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM
4803 return 0;
4804 }
252b5132 4805#endif
3956db08
JB
4806
4807 if (!(i.types[this_operand] & ~Disp))
4808 i.types[this_operand] &= types;
4809
252b5132
RH
4810 return 1;
4811}
4812
eecb386c 4813/* Make sure the memory operand we've been dealt is valid.
47926f60
KH
4814 Return 1 on success, 0 on a failure. */
4815
252b5132 4816static int
e3bb37b5 4817i386_index_check (const char *operand_string)
252b5132 4818{
3e73aa7c 4819 int ok;
24eab124 4820#if INFER_ADDR_PREFIX
eecb386c
AM
4821 int fudged = 0;
4822
24eab124
AM
4823 tryprefix:
4824#endif
3e73aa7c 4825 ok = 1;
30123838
JB
4826 if ((current_templates->start->cpu_flags & CpuSVME)
4827 && current_templates->end[-1].operand_types[0] == AnyMem)
4828 {
4829 /* Memory operands of SVME insns are special in that they only allow
4830 rAX as their memory address and ignore any segment override. */
4831 unsigned RegXX;
4832
4833 /* SKINIT is even more restrictive: it always requires EAX. */
4834 if (strcmp (current_templates->start->name, "skinit") == 0)
4835 RegXX = Reg32;
4836 else if (flag_code == CODE_64BIT)
4837 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4838 else
64e74474
AM
4839 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4840 ? Reg16
4841 : Reg32);
30123838
JB
4842 if (!i.base_reg
4843 || !(i.base_reg->reg_type & Acc)
4844 || !(i.base_reg->reg_type & RegXX)
4845 || i.index_reg
4846 || (i.types[0] & Disp))
4847 ok = 0;
4848 }
4849 else if (flag_code == CODE_64BIT)
64e74474
AM
4850 {
4851 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4852
4853 if ((i.base_reg
4854 && ((i.base_reg->reg_type & RegXX) == 0)
4855 && (i.base_reg->reg_type != BaseIndex
4856 || i.index_reg))
4857 || (i.index_reg
4858 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4859 != (RegXX | BaseIndex))))
4860 ok = 0;
3e73aa7c
JH
4861 }
4862 else
4863 {
4864 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4865 {
4866 /* 16bit checks. */
4867 if ((i.base_reg
29b0f896
AM
4868 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4869 != (Reg16 | BaseIndex)))
3e73aa7c 4870 || (i.index_reg
29b0f896
AM
4871 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4872 != (Reg16 | BaseIndex))
4873 || !(i.base_reg
4874 && i.base_reg->reg_num < 6
4875 && i.index_reg->reg_num >= 6
4876 && i.log2_scale_factor == 0))))
3e73aa7c
JH
4877 ok = 0;
4878 }
4879 else
e5cb08ac 4880 {
3e73aa7c
JH
4881 /* 32bit checks. */
4882 if ((i.base_reg
4883 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4884 || (i.index_reg
29b0f896
AM
4885 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4886 != (Reg32 | BaseIndex))))
e5cb08ac 4887 ok = 0;
3e73aa7c
JH
4888 }
4889 }
4890 if (!ok)
24eab124
AM
4891 {
4892#if INFER_ADDR_PREFIX
20f0a1fc 4893 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM
4894 {
4895 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4896 i.prefixes += 1;
b23bac36
AM
4897 /* Change the size of any displacement too. At most one of
4898 Disp16 or Disp32 is set.
4899 FIXME. There doesn't seem to be any real need for separate
4900 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4901 Removing them would probably clean up the code quite a lot. */
4eed87de
AM
4902 if (flag_code != CODE_64BIT
4903 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4904 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4905 fudged = 1;
24eab124
AM
4906 goto tryprefix;
4907 }
eecb386c
AM
4908 if (fudged)
4909 as_bad (_("`%s' is not a valid base/index expression"),
4910 operand_string);
4911 else
c388dee8 4912#endif
eecb386c
AM
4913 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4914 operand_string,
3e73aa7c 4915 flag_code_names[flag_code]);
24eab124 4916 }
20f0a1fc 4917 return ok;
24eab124 4918}
252b5132 4919
252b5132 4920/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4921 on error. */
252b5132 4922
252b5132 4923static int
e3bb37b5 4924i386_operand (char *operand_string)
252b5132 4925{
af6bdddf
AM
4926 const reg_entry *r;
4927 char *end_op;
24eab124 4928 char *op_string = operand_string;
252b5132 4929
24eab124 4930 if (is_space_char (*op_string))
252b5132
RH
4931 ++op_string;
4932
24eab124 4933 /* We check for an absolute prefix (differentiating,
47926f60 4934 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM
4935 if (*op_string == ABSOLUTE_PREFIX)
4936 {
4937 ++op_string;
4938 if (is_space_char (*op_string))
4939 ++op_string;
4940 i.types[this_operand] |= JumpAbsolute;
4941 }
252b5132 4942
47926f60 4943 /* Check if operand is a register. */
4d1bb795 4944 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4945 {
24eab124
AM
4946 /* Check for a segment override by searching for ':' after a
4947 segment register. */
4948 op_string = end_op;
4949 if (is_space_char (*op_string))
4950 ++op_string;
4951 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4952 {
4953 switch (r->reg_num)
4954 {
4955 case 0:
4956 i.seg[i.mem_operands] = &es;
4957 break;
4958 case 1:
4959 i.seg[i.mem_operands] = &cs;
4960 break;
4961 case 2:
4962 i.seg[i.mem_operands] = &ss;
4963 break;
4964 case 3:
4965 i.seg[i.mem_operands] = &ds;
4966 break;
4967 case 4:
4968 i.seg[i.mem_operands] = &fs;
4969 break;
4970 case 5:
4971 i.seg[i.mem_operands] = &gs;
4972 break;
4973 }
252b5132 4974
24eab124 4975 /* Skip the ':' and whitespace. */
252b5132
RH
4976 ++op_string;
4977 if (is_space_char (*op_string))
24eab124 4978 ++op_string;
252b5132 4979
24eab124
AM
4980 if (!is_digit_char (*op_string)
4981 && !is_identifier_char (*op_string)
4982 && *op_string != '('
4983 && *op_string != ABSOLUTE_PREFIX)
4984 {
4985 as_bad (_("bad memory operand `%s'"), op_string);
4986 return 0;
4987 }
47926f60 4988 /* Handle case of %es:*foo. */
24eab124
AM
4989 if (*op_string == ABSOLUTE_PREFIX)
4990 {
4991 ++op_string;
4992 if (is_space_char (*op_string))
4993 ++op_string;
4994 i.types[this_operand] |= JumpAbsolute;
4995 }
4996 goto do_memory_reference;
4997 }
4998 if (*op_string)
4999 {
d0b47220 5000 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM
5001 return 0;
5002 }
5003 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5004 i.op[this_operand].regs = r;
24eab124
AM
5005 i.reg_operands++;
5006 }
af6bdddf
AM
5007 else if (*op_string == REGISTER_PREFIX)
5008 {
5009 as_bad (_("bad register name `%s'"), op_string);
5010 return 0;
5011 }
24eab124 5012 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5013 {
24eab124
AM
5014 ++op_string;
5015 if (i.types[this_operand] & JumpAbsolute)
5016 {
d0b47220 5017 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM
5018 return 0;
5019 }
5020 if (!i386_immediate (op_string))
5021 return 0;
5022 }
5023 else if (is_digit_char (*op_string)
5024 || is_identifier_char (*op_string)
e5cb08ac 5025 || *op_string == '(')
24eab124 5026 {
47926f60 5027 /* This is a memory reference of some sort. */
af6bdddf 5028 char *base_string;
252b5132 5029
47926f60 5030 /* Start and end of displacement string expression (if found). */
eecb386c
AM
5031 char *displacement_string_start;
5032 char *displacement_string_end;
252b5132 5033
24eab124 5034 do_memory_reference:
24eab124
AM
5035 if ((i.mem_operands == 1
5036 && (current_templates->start->opcode_modifier & IsString) == 0)
5037 || i.mem_operands == 2)
5038 {
5039 as_bad (_("too many memory references for `%s'"),
5040 current_templates->start->name);
5041 return 0;
5042 }
252b5132 5043
24eab124
AM
5044 /* Check for base index form. We detect the base index form by
5045 looking for an ')' at the end of the operand, searching
5046 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5047 after the '('. */
af6bdddf 5048 base_string = op_string + strlen (op_string);
c3332e24 5049
af6bdddf
AM
5050 --base_string;
5051 if (is_space_char (*base_string))
5052 --base_string;
252b5132 5053
47926f60 5054 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM
5055 displacement_string_start = op_string;
5056 displacement_string_end = base_string + 1;
252b5132 5057
24eab124
AM
5058 if (*base_string == ')')
5059 {
af6bdddf 5060 char *temp_string;
24eab124
AM
5061 unsigned int parens_balanced = 1;
5062 /* We've already checked that the number of left & right ()'s are
47926f60 5063 equal, so this loop will not be infinite. */
24eab124
AM
5064 do
5065 {
5066 base_string--;
5067 if (*base_string == ')')
5068 parens_balanced++;
5069 if (*base_string == '(')
5070 parens_balanced--;
5071 }
5072 while (parens_balanced);
c3332e24 5073
af6bdddf 5074 temp_string = base_string;
c3332e24 5075
24eab124 5076 /* Skip past '(' and whitespace. */
252b5132
RH
5077 ++base_string;
5078 if (is_space_char (*base_string))
24eab124 5079 ++base_string;
252b5132 5080
af6bdddf 5081 if (*base_string == ','
4eed87de
AM
5082 || ((i.base_reg = parse_register (base_string, &end_op))
5083 != NULL))
252b5132 5084 {
af6bdddf 5085 displacement_string_end = temp_string;
252b5132 5086
af6bdddf 5087 i.types[this_operand] |= BaseIndex;
252b5132 5088
af6bdddf 5089 if (i.base_reg)
24eab124 5090 {
24eab124
AM
5091 base_string = end_op;
5092 if (is_space_char (*base_string))
5093 ++base_string;
af6bdddf
AM
5094 }
5095
5096 /* There may be an index reg or scale factor here. */
5097 if (*base_string == ',')
5098 {
5099 ++base_string;
5100 if (is_space_char (*base_string))
5101 ++base_string;
5102
4eed87de
AM
5103 if ((i.index_reg = parse_register (base_string, &end_op))
5104 != NULL)
24eab124 5105 {
af6bdddf 5106 base_string = end_op;
24eab124
AM
5107 if (is_space_char (*base_string))
5108 ++base_string;
af6bdddf
AM
5109 if (*base_string == ',')
5110 {
5111 ++base_string;
5112 if (is_space_char (*base_string))
5113 ++base_string;
5114 }
e5cb08ac 5115 else if (*base_string != ')')
af6bdddf 5116 {
4eed87de
AM
5117 as_bad (_("expecting `,' or `)' "
5118 "after index register in `%s'"),
af6bdddf
AM
5119 operand_string);
5120 return 0;
5121 }
24eab124 5122 }
af6bdddf 5123 else if (*base_string == REGISTER_PREFIX)
24eab124 5124 {
af6bdddf 5125 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM
5126 return 0;
5127 }
252b5132 5128
47926f60 5129 /* Check for scale factor. */
551c1ca1 5130 if (*base_string != ')')
af6bdddf 5131 {
551c1ca1
AM
5132 char *end_scale = i386_scale (base_string);
5133
5134 if (!end_scale)
af6bdddf 5135 return 0;
24eab124 5136
551c1ca1 5137 base_string = end_scale;
af6bdddf
AM
5138 if (is_space_char (*base_string))
5139 ++base_string;
5140 if (*base_string != ')')
5141 {
4eed87de
AM
5142 as_bad (_("expecting `)' "
5143 "after scale factor in `%s'"),
af6bdddf
AM
5144 operand_string);
5145 return 0;
5146 }
5147 }
5148 else if (!i.index_reg)
24eab124 5149 {
4eed87de
AM
5150 as_bad (_("expecting index register or scale factor "
5151 "after `,'; got '%c'"),
af6bdddf 5152 *base_string);
24eab124
AM
5153 return 0;
5154 }
5155 }
af6bdddf 5156 else if (*base_string != ')')
24eab124 5157 {
4eed87de
AM
5158 as_bad (_("expecting `,' or `)' "
5159 "after base register in `%s'"),
af6bdddf 5160 operand_string);
24eab124
AM
5161 return 0;
5162 }
c3332e24 5163 }
af6bdddf 5164 else if (*base_string == REGISTER_PREFIX)
c3332e24 5165 {
af6bdddf 5166 as_bad (_("bad register name `%s'"), base_string);
24eab124 5167 return 0;
c3332e24 5168 }
24eab124
AM
5169 }
5170
5171 /* If there's an expression beginning the operand, parse it,
5172 assuming displacement_string_start and
5173 displacement_string_end are meaningful. */
5174 if (displacement_string_start != displacement_string_end)
5175 {
5176 if (!i386_displacement (displacement_string_start,
5177 displacement_string_end))
5178 return 0;
5179 }
5180
5181 /* Special case for (%dx) while doing input/output op. */
5182 if (i.base_reg
5183 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5184 && i.index_reg == 0
5185 && i.log2_scale_factor == 0
5186 && i.seg[i.mem_operands] == 0
5187 && (i.types[this_operand] & Disp) == 0)
5188 {
5189 i.types[this_operand] = InOutPortReg;
5190 return 1;
5191 }
5192
eecb386c
AM
5193 if (i386_index_check (operand_string) == 0)
5194 return 0;
24eab124
AM
5195 i.mem_operands++;
5196 }
5197 else
ce8a8b2f
AM
5198 {
5199 /* It's not a memory operand; argh! */
24eab124
AM
5200 as_bad (_("invalid char %s beginning operand %d `%s'"),
5201 output_invalid (*op_string),
5202 this_operand + 1,
5203 op_string);
5204 return 0;
5205 }
47926f60 5206 return 1; /* Normal return. */
252b5132
RH
5207}
5208\f
ee7fcc42
AM
5209/* md_estimate_size_before_relax()
5210
5211 Called just before relax() for rs_machine_dependent frags. The x86
5212 assembler uses these frags to handle variable size jump
5213 instructions.
5214
5215 Any symbol that is now undefined will not become defined.
5216 Return the correct fr_subtype in the frag.
5217 Return the initial "guess for variable size of frag" to caller.
5218 The guess is actually the growth beyond the fixed part. Whatever
5219 we do to grow the fixed or variable part contributes to our
5220 returned value. */
5221
252b5132
RH
5222int
5223md_estimate_size_before_relax (fragP, segment)
29b0f896
AM
5224 fragS *fragP;
5225 segT segment;
252b5132 5226{
252b5132 5227 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM
5228 check for un-relaxable symbols. On an ELF system, we can't relax
5229 an externally visible symbol, because it may be overridden by a
5230 shared library. */
5231 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5232#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5233 || (IS_ELF
31312f95
AM
5234 && (S_IS_EXTERNAL (fragP->fr_symbol)
5235 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM
5236#endif
5237 )
252b5132 5238 {
b98ef147
AM
5239 /* Symbol is undefined in this segment, or we need to keep a
5240 reloc so that weak symbols can be overridden. */
5241 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5242 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM
5243 unsigned char *opcode;
5244 int old_fr_fix;
f6af82bd 5245
ee7fcc42
AM
5246 if (fragP->fr_var != NO_RELOC)
5247 reloc_type = fragP->fr_var;
b98ef147 5248 else if (size == 2)
f6af82bd
AM
5249 reloc_type = BFD_RELOC_16_PCREL;
5250 else
5251 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5252
ee7fcc42
AM
5253 old_fr_fix = fragP->fr_fix;
5254 opcode = (unsigned char *) fragP->fr_opcode;
5255
fddf5b5b 5256 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5257 {
fddf5b5b
AM
5258 case UNCOND_JUMP:
5259 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5260 opcode[0] = 0xe9;
252b5132 5261 fragP->fr_fix += size;
062cd5e7
AS
5262 fix_new (fragP, old_fr_fix, size,
5263 fragP->fr_symbol,
5264 fragP->fr_offset, 1,
5265 reloc_type);
252b5132
RH
5266 break;
5267
fddf5b5b 5268 case COND_JUMP86:
412167cb
AM
5269 if (size == 2
5270 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM
5271 {
5272 /* Negate the condition, and branch past an
5273 unconditional jump. */
5274 opcode[0] ^= 1;
5275 opcode[1] = 3;
5276 /* Insert an unconditional jump. */
5277 opcode[2] = 0xe9;
5278 /* We added two extra opcode bytes, and have a two byte
5279 offset. */
5280 fragP->fr_fix += 2 + 2;
062cd5e7
AS
5281 fix_new (fragP, old_fr_fix + 2, 2,
5282 fragP->fr_symbol,
5283 fragP->fr_offset, 1,
5284 reloc_type);
fddf5b5b
AM
5285 break;
5286 }
5287 /* Fall through. */
5288
5289 case COND_JUMP:
412167cb
AM
5290 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5291 {
3e02c1cc
AM
5292 fixS *fixP;
5293
412167cb 5294 fragP->fr_fix += 1;
3e02c1cc
AM
5295 fixP = fix_new (fragP, old_fr_fix, 1,
5296 fragP->fr_symbol,
5297 fragP->fr_offset, 1,
5298 BFD_RELOC_8_PCREL);
5299 fixP->fx_signed = 1;
412167cb
AM
5300 break;
5301 }
93c2a809 5302
24eab124 5303 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5304 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5305 opcode[1] = opcode[0] + 0x10;
f6af82bd 5306 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH
5307 /* We've added an opcode byte. */
5308 fragP->fr_fix += 1 + size;
062cd5e7
AS
5309 fix_new (fragP, old_fr_fix + 1, size,
5310 fragP->fr_symbol,
5311 fragP->fr_offset, 1,
5312 reloc_type);
252b5132 5313 break;
fddf5b5b
AM
5314
5315 default:
5316 BAD_CASE (fragP->fr_subtype);
5317 break;
252b5132
RH
5318 }
5319 frag_wane (fragP);
ee7fcc42 5320 return fragP->fr_fix - old_fr_fix;
252b5132 5321 }
93c2a809 5322
93c2a809
AM
5323 /* Guess size depending on current relax state. Initially the relax
5324 state will correspond to a short jump and we return 1, because
5325 the variable part of the frag (the branch offset) is one byte
5326 long. However, we can relax a section more than once and in that
5327 case we must either set fr_subtype back to the unrelaxed state,
5328 or return the value for the appropriate branch. */
5329 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM
5330}
5331
47926f60
KH
5332/* Called after relax() is finished.
5333
5334 In: Address of frag.
5335 fr_type == rs_machine_dependent.
5336 fr_subtype is what the address relaxed to.
5337
5338 Out: Any fixSs and constants are set up.
5339 Caller will turn frag into a ".space 0". */
5340
252b5132
RH
5341void
5342md_convert_frag (abfd, sec, fragP)
ab9da554
ILT
5343 bfd *abfd ATTRIBUTE_UNUSED;
5344 segT sec ATTRIBUTE_UNUSED;
29b0f896 5345 fragS *fragP;
252b5132 5346{
29b0f896 5347 unsigned char *opcode;
252b5132 5348 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM
5349 offsetT target_address;
5350 offsetT opcode_address;
252b5132 5351 unsigned int extension = 0;
847f7ad4 5352 offsetT displacement_from_opcode_start;
252b5132
RH
5353
5354 opcode = (unsigned char *) fragP->fr_opcode;
5355
47926f60 5356 /* Address we want to reach in file space. */
252b5132 5357 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5358
47926f60 5359 /* Address opcode resides at in file space. */
252b5132
RH
5360 opcode_address = fragP->fr_address + fragP->fr_fix;
5361
47926f60 5362 /* Displacement from opcode start to fill into instruction. */
252b5132
RH
5363 displacement_from_opcode_start = target_address - opcode_address;
5364
fddf5b5b 5365 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5366 {
47926f60
KH
5367 /* Don't have to change opcode. */
5368 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5369 where_to_put_displacement = &opcode[1];
fddf5b5b
AM
5370 }
5371 else
5372 {
5373 if (no_cond_jump_promotion
5374 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM
5375 as_warn_where (fragP->fr_file, fragP->fr_line,
5376 _("long jump required"));
252b5132 5377
fddf5b5b
AM
5378 switch (fragP->fr_subtype)
5379 {
5380 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5381 extension = 4; /* 1 opcode + 4 displacement */
5382 opcode[0] = 0xe9;
5383 where_to_put_displacement = &opcode[1];
5384 break;
252b5132 5385
fddf5b5b
AM
5386 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5387 extension = 2; /* 1 opcode + 2 displacement */
5388 opcode[0] = 0xe9;
5389 where_to_put_displacement = &opcode[1];
5390 break;
252b5132 5391
fddf5b5b
AM
5392 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5393 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5394 extension = 5; /* 2 opcode + 4 displacement */
5395 opcode[1] = opcode[0] + 0x10;
5396 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5397 where_to_put_displacement = &opcode[2];
5398 break;
252b5132 5399
fddf5b5b
AM
5400 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5401 extension = 3; /* 2 opcode + 2 displacement */
5402 opcode[1] = opcode[0] + 0x10;
5403 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5404 where_to_put_displacement = &opcode[2];
5405 break;
252b5132 5406
fddf5b5b
AM
5407 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5408 extension = 4;
5409 opcode[0] ^= 1;
5410 opcode[1] = 3;
5411 opcode[2] = 0xe9;
5412 where_to_put_displacement = &opcode[3];
5413 break;
5414
5415 default:
5416 BAD_CASE (fragP->fr_subtype);
5417 break;
5418 }
252b5132 5419 }
fddf5b5b 5420
7b81dfbb
AJ
5421 /* If size if less then four we are sure that the operand fits,
5422 but if it's 4, then it could be that the displacement is larger
5423 then -/+ 2GB. */
5424 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5425 && object_64bit
5426 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM
5427 + ((addressT) 1 << 31))
5428 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ
5429 {
5430 as_bad_where (fragP->fr_file, fragP->fr_line,
5431 _("jump target out of range"));
5432 /* Make us emit 0. */
5433 displacement_from_opcode_start = extension;
5434 }
47926f60 5435 /* Now put displacement after opcode. */
252b5132
RH
5436 md_number_to_chars ((char *) where_to_put_displacement,
5437 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5438 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH
5439 fragP->fr_fix += extension;
5440}
5441\f
47926f60
KH
5442/* Size of byte displacement jmp. */
5443int md_short_jump_size = 2;
5444
5445/* Size of dword displacement jmp. */
5446int md_long_jump_size = 5;
252b5132 5447
252b5132
RH
5448void
5449md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5450 char *ptr;
5451 addressT from_addr, to_addr;
ab9da554
ILT
5452 fragS *frag ATTRIBUTE_UNUSED;
5453 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5454{
847f7ad4 5455 offsetT offset;
252b5132
RH
5456
5457 offset = to_addr - (from_addr + 2);
47926f60
KH
5458 /* Opcode for byte-disp jump. */
5459 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH
5460 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5461}
5462
5463void
5464md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5465 char *ptr;
5466 addressT from_addr, to_addr;
a38cf1db
AM
5467 fragS *frag ATTRIBUTE_UNUSED;
5468 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5469{
847f7ad4 5470 offsetT offset;
252b5132 5471
a38cf1db
AM
5472 offset = to_addr - (from_addr + 5);
5473 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5474 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH
5475}
5476\f
5477/* Apply a fixup (fixS) to segment data, once it has been determined
5478 by our caller that we have all the info we need to fix it up.
5479
5480 On the 386, immediates, displacements, and data pointers are all in
5481 the same (little-endian) format, so we don't need to care about which
5482 we are handling. */
5483
94f592af 5484void
55cf6793 5485md_apply_fix (fixP, valP, seg)
47926f60
KH
5486 /* The fix we're to put in. */
5487 fixS *fixP;
47926f60 5488 /* Pointer to the value of the bits. */
c6682705 5489 valueT *valP;
47926f60
KH
5490 /* Segment fix is from. */
5491 segT seg ATTRIBUTE_UNUSED;
252b5132 5492{
94f592af 5493 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5494 valueT value = *valP;
252b5132 5495
f86103b7 5496#if !defined (TE_Mach)
93382f6d
AM
5497 if (fixP->fx_pcrel)
5498 {
5499 switch (fixP->fx_r_type)
5500 {
5865bb77
ILT
5501 default:
5502 break;
5503
d6ab8113
JB
5504 case BFD_RELOC_64:
5505 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5506 break;
93382f6d 5507 case BFD_RELOC_32:
ae8887b5 5508 case BFD_RELOC_X86_64_32S:
93382f6d
AM
5509 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5510 break;
5511 case BFD_RELOC_16:
5512 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5513 break;
5514 case BFD_RELOC_8:
5515 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5516 break;
5517 }
5518 }
252b5132 5519
a161fe53 5520 if (fixP->fx_addsy != NULL
31312f95 5521 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5522 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM
5523 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5524 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5525 && !use_rela_relocations)
252b5132 5526 {
31312f95
AM
5527 /* This is a hack. There should be a better way to handle this.
5528 This covers for the fact that bfd_install_relocation will
5529 subtract the current location (for partial_inplace, PC relative
5530 relocations); see more below. */
252b5132 5531#ifndef OBJ_AOUT
718ddfc0 5532 if (IS_ELF
252b5132
RH
5533#ifdef TE_PE
5534 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5535#endif
5536 )
5537 value += fixP->fx_where + fixP->fx_frag->fr_address;
5538#endif
5539#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5540 if (IS_ELF)
252b5132 5541 {
6539b54b 5542 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5543
6539b54b 5544 if ((sym_seg == seg
2f66722d 5545 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5546 && sym_seg != absolute_section))
ae6063d4 5547 && !generic_force_reloc (fixP))
2f66722d
AM
5548 {
5549 /* Yes, we add the values in twice. This is because
6539b54b
AM
5550 bfd_install_relocation subtracts them out again. I think
5551 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM
5552 it. FIXME. */
5553 value += fixP->fx_where + fixP->fx_frag->fr_address;
5554 }
252b5132
RH
5555 }
5556#endif
5557#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC
5558 /* For some reason, the PE format does not store a
5559 section address offset for a PC relative symbol. */
5560 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5561 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH
5562 value += md_pcrel_from (fixP);
5563#endif
5564 }
5565
5566 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5567 and we must not disappoint it. */
252b5132 5568#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5569 if (IS_ELF && fixP->fx_addsy)
47926f60
KH
5570 switch (fixP->fx_r_type)
5571 {
5572 case BFD_RELOC_386_PLT32:
3e73aa7c 5573 case BFD_RELOC_X86_64_PLT32:
47926f60
KH
5574 /* Make the jump instruction point to the address of the operand. At
5575 runtime we merely add the offset to the actual PLT entry. */
5576 value = -4;
5577 break;
31312f95 5578
13ae64f3
JJ
5579 case BFD_RELOC_386_TLS_GD:
5580 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5581 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ
5582 case BFD_RELOC_386_TLS_IE:
5583 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5584 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ
5585 case BFD_RELOC_X86_64_TLSGD:
5586 case BFD_RELOC_X86_64_TLSLD:
5587 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5588 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ
5589 value = 0; /* Fully resolved at runtime. No addend. */
5590 /* Fallthrough */
5591 case BFD_RELOC_386_TLS_LE:
5592 case BFD_RELOC_386_TLS_LDO_32:
5593 case BFD_RELOC_386_TLS_LE_32:
5594 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5595 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5596 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5597 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ
5598 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5599 break;
5600
67a4f2b7
AO
5601 case BFD_RELOC_386_TLS_DESC_CALL:
5602 case BFD_RELOC_X86_64_TLSDESC_CALL:
5603 value = 0; /* Fully resolved at runtime. No addend. */
5604 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5605 fixP->fx_done = 0;
5606 return;
5607
00f7efb6
JJ
5608 case BFD_RELOC_386_GOT32:
5609 case BFD_RELOC_X86_64_GOT32:
47926f60
KH
5610 value = 0; /* Fully resolved at runtime. No addend. */
5611 break;
47926f60
KH
5612
5613 case BFD_RELOC_VTABLE_INHERIT:
5614 case BFD_RELOC_VTABLE_ENTRY:
5615 fixP->fx_done = 0;
94f592af 5616 return;
47926f60
KH
5617
5618 default:
5619 break;
5620 }
5621#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5622 *valP = value;
f86103b7 5623#endif /* !defined (TE_Mach) */
3e73aa7c 5624
3e73aa7c 5625 /* Are we finished with this relocation now? */
c6682705 5626 if (fixP->fx_addsy == NULL)
3e73aa7c
JH
5627 fixP->fx_done = 1;
5628 else if (use_rela_relocations)
5629 {
5630 fixP->fx_no_overflow = 1;
062cd5e7
AS
5631 /* Remember value for tc_gen_reloc. */
5632 fixP->fx_addnumber = value;
3e73aa7c
JH
5633 value = 0;
5634 }
f86103b7 5635
94f592af 5636 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5637}
252b5132 5638\f
252b5132
RH
5639#define MAX_LITTLENUMS 6
5640
47926f60
KH
5641/* Turn the string pointed to by litP into a floating point constant
5642 of type TYPE, and emit the appropriate bytes. The number of
5643 LITTLENUMS emitted is stored in *SIZEP. An error message is
5644 returned, or NULL on OK. */
5645
252b5132
RH
5646char *
5647md_atof (type, litP, sizeP)
2ab9b79e 5648 int type;
252b5132
RH
5649 char *litP;
5650 int *sizeP;
5651{
5652 int prec;
5653 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5654 LITTLENUM_TYPE *wordP;
5655 char *t;
5656
5657 switch (type)
5658 {
5659 case 'f':
5660 case 'F':
5661 prec = 2;
5662 break;
5663
5664 case 'd':
5665 case 'D':
5666 prec = 4;
5667 break;
5668
5669 case 'x':
5670 case 'X':
5671 prec = 5;
5672 break;
5673
5674 default:
5675 *sizeP = 0;
5676 return _("Bad call to md_atof ()");
5677 }
5678 t = atof_ieee (input_line_pointer, type, words);
5679 if (t)
5680 input_line_pointer = t;
5681
5682 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5683 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5684 the bigendian 386. */
5685 for (wordP = words + prec - 1; prec--;)
5686 {
5687 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5688 litP += sizeof (LITTLENUM_TYPE);
5689 }
5690 return 0;
5691}
5692\f
2d545b82 5693static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5694
252b5132 5695static char *
e3bb37b5 5696output_invalid (int c)
252b5132 5697{
3882b010 5698 if (ISPRINT (c))
f9f21a03
L
5699 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5700 "'%c'", c);
252b5132 5701 else
f9f21a03 5702 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5703 "(0x%x)", (unsigned char) c);
252b5132
RH
5704 return output_invalid_buf;
5705}
5706
af6bdddf 5707/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH
5708
5709static const reg_entry *
4d1bb795 5710parse_real_register (char *reg_string, char **end_op)
252b5132 5711{
af6bdddf
AM
5712 char *s = reg_string;
5713 char *p;
252b5132
RH
5714 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5715 const reg_entry *r;
5716
5717 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5718 if (*s == REGISTER_PREFIX)
5719 ++s;
5720
5721 if (is_space_char (*s))
5722 ++s;
5723
5724 p = reg_name_given;
af6bdddf 5725 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH
5726 {
5727 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM
5728 return (const reg_entry *) NULL;
5729 s++;
252b5132
RH
5730 }
5731
6588847e
DN
5732 /* For naked regs, make sure that we are not dealing with an identifier.
5733 This prevents confusing an identifier like `eax_var' with register
5734 `eax'. */
5735 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5736 return (const reg_entry *) NULL;
5737
af6bdddf 5738 *end_op = s;
252b5132
RH
5739
5740 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5741
5f47d35b 5742 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5743 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5744 {
5f47d35b
AM
5745 if (is_space_char (*s))
5746 ++s;
5747 if (*s == '(')
5748 {
af6bdddf 5749 ++s;
5f47d35b
AM
5750 if (is_space_char (*s))
5751 ++s;
5752 if (*s >= '0' && *s <= '7')
5753 {
5754 r = &i386_float_regtab[*s - '0'];
af6bdddf 5755 ++s;
5f47d35b
AM
5756 if (is_space_char (*s))
5757 ++s;
5758 if (*s == ')')
5759 {
5760 *end_op = s + 1;
5761 return r;
5762 }
5f47d35b 5763 }
47926f60 5764 /* We have "%st(" then garbage. */
5f47d35b
AM
5765 return (const reg_entry *) NULL;
5766 }
5767 }
5768
1ae00879 5769 if (r != NULL
20f0a1fc 5770 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5771 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5772 && flag_code != CODE_64BIT)
20f0a1fc 5773 return (const reg_entry *) NULL;
1ae00879 5774
252b5132
RH
5775 return r;
5776}
4d1bb795
JB
5777
5778/* REG_STRING starts *before* REGISTER_PREFIX. */
5779
5780static const reg_entry *
5781parse_register (char *reg_string, char **end_op)
5782{
5783 const reg_entry *r;
5784
5785 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5786 r = parse_real_register (reg_string, end_op);
5787 else
5788 r = NULL;
5789 if (!r)
5790 {
5791 char *save = input_line_pointer;
5792 char c;
5793 symbolS *symbolP;
5794
5795 input_line_pointer = reg_string;
5796 c = get_symbol_end ();
5797 symbolP = symbol_find (reg_string);
5798 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5799 {
5800 const expressionS *e = symbol_get_value_expression (symbolP);
5801
5802 know (e->X_op == O_register);
4eed87de 5803 know (e->X_add_number >= 0
c3fe08fa 5804 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB
5805 r = i386_regtab + e->X_add_number;
5806 *end_op = input_line_pointer;
5807 }
5808 *input_line_pointer = c;
5809 input_line_pointer = save;
5810 }
5811 return r;
5812}
5813
5814int
5815i386_parse_name (char *name, expressionS *e, char *nextcharP)
5816{
5817 const reg_entry *r;
5818 char *end = input_line_pointer;
5819
5820 *end = *nextcharP;
5821 r = parse_register (name, &input_line_pointer);
5822 if (r && end <= input_line_pointer)
5823 {
5824 *nextcharP = *input_line_pointer;
5825 *input_line_pointer = 0;
5826 e->X_op = O_register;
5827 e->X_add_number = r - i386_regtab;
5828 return 1;
5829 }
5830 input_line_pointer = end;
5831 *end = 0;
5832 return 0;
5833}
5834
5835void
5836md_operand (expressionS *e)
5837{
5838 if (*input_line_pointer == REGISTER_PREFIX)
5839 {
5840 char *end;
5841 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5842
5843 if (r)
5844 {
5845 e->X_op = O_register;
5846 e->X_add_number = r - i386_regtab;
5847 input_line_pointer = end;
5848 }
5849 }
5850}
5851
252b5132 5852\f
4cc782b5 5853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5854const char *md_shortopts = "kVQ:sqn";
252b5132 5855#else
12b55ccc 5856const char *md_shortopts = "qn";
252b5132 5857#endif
6e0b89ee 5858
3e73aa7c 5859#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM
5860#define OPTION_64 (OPTION_MD_BASE + 1)
5861#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L
5862#define OPTION_MARCH (OPTION_MD_BASE + 3)
5863#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5864
99ad8390
NC
5865struct option md_longopts[] =
5866{
3e73aa7c 5867 {"32", no_argument, NULL, OPTION_32},
99ad8390 5868#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5869 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5870#endif
b3b91714 5871 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L
5872 {"march", required_argument, NULL, OPTION_MARCH},
5873 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH
5874 {NULL, no_argument, NULL, 0}
5875};
5876size_t md_longopts_size = sizeof (md_longopts);
5877
5878int
9103f4f4 5879md_parse_option (int c, char *arg)
252b5132 5880{
9103f4f4
L
5881 unsigned int i;
5882
252b5132
RH
5883 switch (c)
5884 {
12b55ccc
L
5885 case 'n':
5886 optimize_align_code = 0;
5887 break;
5888
a38cf1db
AM
5889 case 'q':
5890 quiet_warnings = 1;
252b5132
RH
5891 break;
5892
5893#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM
5894 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5895 should be emitted or not. FIXME: Not implemented. */
5896 case 'Q':
252b5132
RH
5897 break;
5898
5899 /* -V: SVR4 argument to print version ID. */
5900 case 'V':
5901 print_version_id ();
5902 break;
5903
a38cf1db
AM
5904 /* -k: Ignore for FreeBSD compatibility. */
5905 case 'k':
252b5132 5906 break;
4cc782b5
ILT
5907
5908 case 's':
5909 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5910 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5911 break;
99ad8390
NC
5912#endif
5913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH
5914 case OPTION_64:
5915 {
5916 const char **list, **l;
5917
3e73aa7c
JH
5918 list = bfd_target_list ();
5919 for (l = list; *l != NULL; l++)
8620418b 5920 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC
5921 || strcmp (*l, "coff-x86-64") == 0
5922 || strcmp (*l, "pe-x86-64") == 0
5923 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM
5924 {
5925 default_arch = "x86_64";
5926 break;
5927 }
3e73aa7c 5928 if (*l == NULL)
6e0b89ee 5929 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH
5930 free (list);
5931 }
5932 break;
5933#endif
252b5132 5934
6e0b89ee
AM
5935 case OPTION_32:
5936 default_arch = "i386";
5937 break;
5938
b3b91714
AM
5939 case OPTION_DIVIDE:
5940#ifdef SVR4_COMMENT_CHARS
5941 {
5942 char *n, *t;
5943 const char *s;
5944
5945 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5946 t = n;
5947 for (s = i386_comment_chars; *s != '\0'; s++)
5948 if (*s != '/')
5949 *t++ = *s;
5950 *t = '\0';
5951 i386_comment_chars = n;
5952 }
5953#endif
5954 break;
5955
9103f4f4
L
5956 case OPTION_MARCH:
5957 if (*arg == '.')
5958 as_fatal (_("Invalid -march= option: `%s'"), arg);
5959 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5960 {
5961 if (strcmp (arg, cpu_arch [i].name) == 0)
5962 {
ccc9c027 5963 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5964 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L
5965 if (!cpu_arch_tune_set)
5966 {
5967 cpu_arch_tune = cpu_arch_isa;
5968 cpu_arch_tune_flags = cpu_arch_isa_flags;
5969 }
9103f4f4
L
5970 break;
5971 }
5972 }
5973 if (i >= ARRAY_SIZE (cpu_arch))
5974 as_fatal (_("Invalid -march= option: `%s'"), arg);
5975 break;
5976
5977 case OPTION_MTUNE:
5978 if (*arg == '.')
5979 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5980 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5981 {
5982 if (strcmp (arg, cpu_arch [i].name) == 0)
5983 {
ccc9c027 5984 cpu_arch_tune_set = 1;
9103f4f4
L
5985 cpu_arch_tune = cpu_arch [i].type;
5986 cpu_arch_tune_flags = cpu_arch[i].flags;
5987 break;
5988 }
5989 }
5990 if (i >= ARRAY_SIZE (cpu_arch))
5991 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5992 break;
5993
252b5132
RH
5994 default:
5995 return 0;
5996 }
5997 return 1;
5998}
5999
6000void
6001md_show_usage (stream)
6002 FILE *stream;
6003{
4cc782b5
ILT
6004#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6005 fprintf (stream, _("\
a38cf1db
AM
6006 -Q ignored\n\
6007 -V print assembler version number\n\
b3b91714
AM
6008 -k ignored\n"));
6009#endif
6010 fprintf (stream, _("\
12b55ccc 6011 -n Do not optimize code alignment\n\
b3b91714
AM
6012 -q quieten some warnings\n"));
6013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6014 fprintf (stream, _("\
a38cf1db 6015 -s ignored\n"));
b3b91714 6016#endif
751d281c
L
6017#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6018 fprintf (stream, _("\
6019 --32/--64 generate 32bit/64bit code\n"));
6020#endif
b3b91714
AM
6021#ifdef SVR4_COMMENT_CHARS
6022 fprintf (stream, _("\
6023 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM
6024#else
6025 fprintf (stream, _("\
b3b91714 6026 --divide ignored\n"));
4cc782b5 6027#endif
9103f4f4
L
6028 fprintf (stream, _("\
6029 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6030 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6031 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6032
252b5132
RH
6033}
6034
99ad8390
NC
6035#if defined(TE_PEP)
6036const char *
6037x86_64_target_format (void)
6038{
6039 if (strcmp (default_arch, "x86_64") == 0)
6040 {
6041 set_code_flag (CODE_64BIT);
6042 return COFF_TARGET_FORMAT;
6043 }
6044 else if (strcmp (default_arch, "i386") == 0)
6045 {
6046 set_code_flag (CODE_32BIT);
6047 return "coff-i386";
6048 }
6049
6050 as_fatal (_("Unknown architecture"));
6051 return NULL;
6052}
6053#endif
6054
3e73aa7c
JH
6055#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6056 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH
6057
6058/* Pick the target format to use. */
6059
47926f60 6060const char *
e3bb37b5 6061i386_target_format (void)
252b5132 6062{
3e73aa7c 6063 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L
6064 {
6065 set_code_flag (CODE_64BIT);
6066 if (cpu_arch_isa_flags == 0)
d32cad65 6067 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L
6068 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6069 |CpuSSE|CpuSSE2;
ccc9c027 6070 if (cpu_arch_tune_flags == 0)
d32cad65 6071 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L
6072 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6073 |CpuSSE|CpuSSE2;
9103f4f4 6074 }
3e73aa7c 6075 else if (!strcmp (default_arch, "i386"))
9103f4f4
L
6076 {
6077 set_code_flag (CODE_32BIT);
6078 if (cpu_arch_isa_flags == 0)
d32cad65 6079 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6080 if (cpu_arch_tune_flags == 0)
d32cad65 6081 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6082 }
3e73aa7c
JH
6083 else
6084 as_fatal (_("Unknown architecture"));
252b5132
RH
6085 switch (OUTPUT_FLAVOR)
6086 {
4c63da97
AM
6087#ifdef OBJ_MAYBE_AOUT
6088 case bfd_target_aout_flavour:
47926f60 6089 return AOUT_TARGET_FORMAT;
4c63da97
AM
6090#endif
6091#ifdef OBJ_MAYBE_COFF
252b5132
RH
6092 case bfd_target_coff_flavour:
6093 return "coff-i386";
4c63da97 6094#endif
3e73aa7c 6095#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6096 case bfd_target_elf_flavour:
3e73aa7c 6097 {
e5cb08ac 6098 if (flag_code == CODE_64BIT)
4fa24527
JB
6099 {
6100 object_64bit = 1;
6101 use_rela_relocations = 1;
6102 }
9d7cbccd 6103 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6104 }
4c63da97 6105#endif
252b5132
RH
6106 default:
6107 abort ();
6108 return NULL;
6109 }
6110}
6111
47926f60 6112#endif /* OBJ_MAYBE_ more than one */
a847613f
AM
6113
6114#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L
6115void
6116i386_elf_emit_arch_note (void)
a847613f 6117{
718ddfc0 6118 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM
6119 {
6120 char *p;
6121 asection *seg = now_seg;
6122 subsegT subseg = now_subseg;
6123 Elf_Internal_Note i_note;
6124 Elf_External_Note e_note;
6125 asection *note_secp;
6126 int len;
6127
6128 /* Create the .note section. */
6129 note_secp = subseg_new (".note", 0);
6130 bfd_set_section_flags (stdoutput,
6131 note_secp,
6132 SEC_HAS_CONTENTS | SEC_READONLY);
6133
6134 /* Process the arch string. */
6135 len = strlen (cpu_arch_name);
6136
6137 i_note.namesz = len + 1;
6138 i_note.descsz = 0;
6139 i_note.type = NT_ARCH;
6140 p = frag_more (sizeof (e_note.namesz));
6141 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6142 p = frag_more (sizeof (e_note.descsz));
6143 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6144 p = frag_more (sizeof (e_note.type));
6145 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6146 p = frag_more (len + 1);
6147 strcpy (p, cpu_arch_name);
6148
6149 frag_align (2, 0, 0);
6150
6151 subseg_set (seg, subseg);
6152 }
6153}
6154#endif
252b5132 6155\f
252b5132
RH
6156symbolS *
6157md_undefined_symbol (name)
6158 char *name;
6159{
18dc2407
ILT
6160 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6161 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6162 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6163 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM
6164 {
6165 if (!GOT_symbol)
6166 {
6167 if (symbol_find (name))
6168 as_bad (_("GOT already in symbol table"));
6169 GOT_symbol = symbol_new (name, undefined_section,
6170 (valueT) 0, &zero_address_frag);
6171 };
6172 return GOT_symbol;
6173 }
252b5132
RH
6174 return 0;
6175}
6176
6177/* Round up a section size to the appropriate boundary. */
47926f60 6178
252b5132
RH
6179valueT
6180md_section_align (segment, size)
ab9da554 6181 segT segment ATTRIBUTE_UNUSED;
252b5132
RH
6182 valueT size;
6183{
4c63da97
AM
6184#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6185 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6186 {
6187 /* For a.out, force the section size to be aligned. If we don't do
6188 this, BFD will align it for us, but it will not write out the
6189 final bytes of the section. This may be a bug in BFD, but it is
6190 easier to fix it here since that is how the other a.out targets
6191 work. */
6192 int align;
6193
6194 align = bfd_get_section_alignment (stdoutput, segment);
6195 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6196 }
252b5132
RH
6197#endif
6198
6199 return size;
6200}
6201
6202/* On the i386, PC-relative offsets are relative to the start of the
6203 next instruction. That is, the address of the offset, plus its
6204 size, since the offset is always the last part of the insn. */
6205
6206long
e3bb37b5 6207md_pcrel_from (fixS *fixP)
252b5132
RH
6208{
6209 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6210}
6211
6212#ifndef I386COFF
6213
6214static void
e3bb37b5 6215s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6216{
29b0f896 6217 int temp;
252b5132 6218
8a75718c
JB
6219#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6220 if (IS_ELF)
6221 obj_elf_section_change_hook ();
6222#endif
252b5132
RH
6223 temp = get_absolute_expression ();
6224 subseg_set (bss_section, (subsegT) temp);
6225 demand_empty_rest_of_line ();
6226}
6227
6228#endif
6229
252b5132 6230void
e3bb37b5 6231i386_validate_fix (fixS *fixp)
252b5132
RH
6232{
6233 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6234 {
23df1078
JH
6235 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6236 {
4fa24527 6237 if (!object_64bit)
23df1078
JH
6238 abort ();
6239 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6240 }
6241 else
6242 {
4fa24527 6243 if (!object_64bit)
d6ab8113
JB
6244 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6245 else
6246 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6247 }
252b5132
RH
6248 fixp->fx_subsy = 0;
6249 }
6250}
6251
252b5132
RH
6252arelent *
6253tc_gen_reloc (section, fixp)
ab9da554 6254 asection *section ATTRIBUTE_UNUSED;
252b5132
RH
6255 fixS *fixp;
6256{
6257 arelent *rel;
6258 bfd_reloc_code_real_type code;
6259
6260 switch (fixp->fx_r_type)
6261 {
3e73aa7c
JH
6262 case BFD_RELOC_X86_64_PLT32:
6263 case BFD_RELOC_X86_64_GOT32:
6264 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH
6265 case BFD_RELOC_386_PLT32:
6266 case BFD_RELOC_386_GOT32:
6267 case BFD_RELOC_386_GOTOFF:
6268 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ
6269 case BFD_RELOC_386_TLS_GD:
6270 case BFD_RELOC_386_TLS_LDM:
6271 case BFD_RELOC_386_TLS_LDO_32:
6272 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ
6273 case BFD_RELOC_386_TLS_IE:
6274 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ
6275 case BFD_RELOC_386_TLS_LE_32:
6276 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO
6277 case BFD_RELOC_386_TLS_GOTDESC:
6278 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ
6279 case BFD_RELOC_X86_64_TLSGD:
6280 case BFD_RELOC_X86_64_TLSLD:
6281 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6282 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ
6283 case BFD_RELOC_X86_64_GOTTPOFF:
6284 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB
6285 case BFD_RELOC_X86_64_TPOFF64:
6286 case BFD_RELOC_X86_64_GOTOFF64:
6287 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ
6288 case BFD_RELOC_X86_64_GOT64:
6289 case BFD_RELOC_X86_64_GOTPCREL64:
6290 case BFD_RELOC_X86_64_GOTPC64:
6291 case BFD_RELOC_X86_64_GOTPLT64:
6292 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO
6293 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6294 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH
6295 case BFD_RELOC_RVA:
6296 case BFD_RELOC_VTABLE_ENTRY:
6297 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC
6298#ifdef TE_PE
6299 case BFD_RELOC_32_SECREL:
6300#endif
252b5132
RH
6301 code = fixp->fx_r_type;
6302 break;
dbbaec26
L
6303 case BFD_RELOC_X86_64_32S:
6304 if (!fixp->fx_pcrel)
6305 {
6306 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6307 code = fixp->fx_r_type;
6308 break;
6309 }
252b5132 6310 default:
93382f6d 6311 if (fixp->fx_pcrel)
252b5132 6312 {
93382f6d
AM
6313 switch (fixp->fx_size)
6314 {
6315 default:
b091f402
AM
6316 as_bad_where (fixp->fx_file, fixp->fx_line,
6317 _("can not do %d byte pc-relative relocation"),
6318 fixp->fx_size);
93382f6d
AM
6319 code = BFD_RELOC_32_PCREL;
6320 break;
6321 case 1: code = BFD_RELOC_8_PCREL; break;
6322 case 2: code = BFD_RELOC_16_PCREL; break;
6323 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB
6324#ifdef BFD64
6325 case 8: code = BFD_RELOC_64_PCREL; break;
6326#endif
93382f6d
AM
6327 }
6328 }
6329 else
6330 {
6331 switch (fixp->fx_size)
6332 {
6333 default:
b091f402
AM
6334 as_bad_where (fixp->fx_file, fixp->fx_line,
6335 _("can not do %d byte relocation"),
6336 fixp->fx_size);
93382f6d
AM
6337 code = BFD_RELOC_32;
6338 break;
6339 case 1: code = BFD_RELOC_8; break;
6340 case 2: code = BFD_RELOC_16; break;
6341 case 4: code = BFD_RELOC_32; break;
937149dd 6342#ifdef BFD64
3e73aa7c 6343 case 8: code = BFD_RELOC_64; break;
937149dd 6344#endif
93382f6d 6345 }
252b5132
RH
6346 }
6347 break;
6348 }
252b5132 6349
d182319b
JB
6350 if ((code == BFD_RELOC_32
6351 || code == BFD_RELOC_32_PCREL
6352 || code == BFD_RELOC_X86_64_32S)
252b5132
RH
6353 && GOT_symbol
6354 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6355 {
4fa24527 6356 if (!object_64bit)
d6ab8113
JB
6357 code = BFD_RELOC_386_GOTPC;
6358 else
6359 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6360 }
7b81dfbb
AJ
6361 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6362 && GOT_symbol
6363 && fixp->fx_addsy == GOT_symbol)
6364 {
6365 code = BFD_RELOC_X86_64_GOTPC64;
6366 }
252b5132
RH
6367
6368 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT
6369 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6370 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
6371
6372 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6373
3e73aa7c
JH
6374 if (!use_rela_relocations)
6375 {
6376 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6377 vtable entry to be used in the relocation's section offset. */
6378 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6379 rel->address = fixp->fx_offset;
252b5132 6380
c6682705 6381 rel->addend = 0;
3e73aa7c
JH
6382 }
6383 /* Use the rela in 64bit mode. */
252b5132 6384 else
3e73aa7c 6385 {
062cd5e7
AS
6386 if (!fixp->fx_pcrel)
6387 rel->addend = fixp->fx_offset;
6388 else
6389 switch (code)
6390 {
6391 case BFD_RELOC_X86_64_PLT32:
6392 case BFD_RELOC_X86_64_GOT32:
6393 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ
6394 case BFD_RELOC_X86_64_TLSGD:
6395 case BFD_RELOC_X86_64_TLSLD:
6396 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO
6397 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6398 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS
6399 rel->addend = fixp->fx_offset - fixp->fx_size;
6400 break;
6401 default:
6402 rel->addend = (section->vma
6403 - fixp->fx_size
6404 + fixp->fx_addnumber
6405 + md_pcrel_from (fixp));
6406 break;
6407 }
3e73aa7c
JH
6408 }
6409
252b5132
RH
6410 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6411 if (rel->howto == NULL)
6412 {
6413 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6414 _("cannot represent relocation type %s"),
252b5132
RH
6415 bfd_get_reloc_code_name (code));
6416 /* Set howto to a garbage value so that we can keep going. */
6417 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6418 assert (rel->howto != NULL);
6419 }
6420
6421 return rel;
6422}
6423
64a0c779
DN
6424\f
6425/* Parse operands using Intel syntax. This implements a recursive descent
6426 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6427 Programmer's Guide.
6428
6429 FIXME: We do not recognize the full operand grammar defined in the MASM
6430 documentation. In particular, all the structure/union and
6431 high-level macro operands are missing.
6432
6433 Uppercase words are terminals, lower case words are non-terminals.
6434 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6435 bars '|' denote choices. Most grammar productions are implemented in
6436 functions called 'intel_<production>'.
6437
6438 Initial production is 'expr'.
6439
9306ca4a 6440 addOp + | -
64a0c779
DN
6441
6442 alpha [a-zA-Z]
6443
9306ca4a
JB
6444 binOp & | AND | \| | OR | ^ | XOR
6445
64a0c779
DN
6446 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6447
6448 constant digits [[ radixOverride ]]
6449
9306ca4a 6450 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN
6451
6452 digits decdigit
b77a7acd
AJ
6453 | digits decdigit
6454 | digits hexdigit
64a0c779
DN
6455
6456 decdigit [0-9]
6457
9306ca4a
JB
6458 e04 e04 addOp e05
6459 | e05
6460
6461 e05 e05 binOp e06
b77a7acd 6462 | e06
64a0c779
DN
6463
6464 e06 e06 mulOp e09
b77a7acd 6465 | e09
64a0c779
DN
6466
6467 e09 OFFSET e10
a724f0f4
JB
6468 | SHORT e10
6469 | + e10
6470 | - e10
9306ca4a
JB
6471 | ~ e10
6472 | NOT e10
64a0c779
DN
6473 | e09 PTR e10
6474 | e09 : e10
6475 | e10
6476
6477 e10 e10 [ expr ]
b77a7acd 6478 | e11
64a0c779
DN
6479
6480 e11 ( expr )
b77a7acd 6481 | [ expr ]
64a0c779
DN
6482 | constant
6483 | dataType
6484 | id
6485 | $
6486 | register
6487
a724f0f4 6488 => expr expr cmpOp e04
9306ca4a 6489 | e04
64a0c779
DN
6490
6491 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6492 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN
6493
6494 hexdigit a | b | c | d | e | f
b77a7acd 6495 | A | B | C | D | E | F
64a0c779
DN
6496
6497 id alpha
b77a7acd 6498 | id alpha
64a0c779
DN
6499 | id decdigit
6500
9306ca4a 6501 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN
6502
6503 quote " | '
6504
6505 register specialRegister
b77a7acd 6506 | gpRegister
64a0c779
DN
6507 | byteRegister
6508
6509 segmentRegister CS | DS | ES | FS | GS | SS
6510
9306ca4a 6511 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6512 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN
6513 | TR3 | TR4 | TR5 | TR6 | TR7
6514
64a0c779
DN
6515 We simplify the grammar in obvious places (e.g., register parsing is
6516 done by calling parse_register) and eliminate immediate left recursion
6517 to implement a recursive-descent parser.
6518
a724f0f4
JB
6519 expr e04 expr'
6520
6521 expr' cmpOp e04 expr'
6522 | Empty
9306ca4a
JB
6523
6524 e04 e05 e04'
6525
6526 e04' addOp e05 e04'
6527 | Empty
64a0c779
DN
6528
6529 e05 e06 e05'
6530
9306ca4a 6531 e05' binOp e06 e05'
b77a7acd 6532 | Empty
64a0c779
DN
6533
6534 e06 e09 e06'
6535
6536 e06' mulOp e09 e06'
b77a7acd 6537 | Empty
64a0c779
DN
6538
6539 e09 OFFSET e10 e09'
a724f0f4
JB
6540 | SHORT e10'
6541 | + e10'
6542 | - e10'
6543 | ~ e10'
6544 | NOT e10'
b77a7acd 6545 | e10 e09'
64a0c779
DN
6546
6547 e09' PTR e10 e09'
b77a7acd 6548 | : e10 e09'
64a0c779
DN
6549 | Empty
6550
6551 e10 e11 e10'
6552
6553 e10' [ expr ] e10'
b77a7acd 6554 | Empty
64a0c779
DN
6555
6556 e11 ( expr )
b77a7acd 6557 | [ expr ]
64a0c779
DN
6558 | BYTE
6559 | WORD
6560 | DWORD
9306ca4a 6561 | FWORD
64a0c779 6562 | QWORD
9306ca4a
JB
6563 | TBYTE
6564 | OWORD
6565 | XMMWORD
64a0c779
DN
6566 | .
6567 | $
6568 | register
6569 | id
6570 | constant */
6571
6572/* Parsing structure for the intel syntax parser. Used to implement the
6573 semantic actions for the operand grammar. */
6574struct intel_parser_s
6575 {
6576 char *op_string; /* The string being parsed. */
6577 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6578 int op_modifier; /* Operand modifier. */
64a0c779 6579 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM
6580 int in_offset; /* >=1 if parsing operand of offset. */
6581 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN
6582 const reg_entry *reg; /* Last register reference found. */
6583 char *disp; /* Displacement string being built. */
a724f0f4 6584 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN
6585 };
6586
6587static struct intel_parser_s intel_parser;
6588
6589/* Token structure for parsing intel syntax. */
6590struct intel_token
6591 {
6592 int code; /* Token code. */
6593 const reg_entry *reg; /* Register entry for register tokens. */
6594 char *str; /* String representation. */
6595 };
6596
6597static struct intel_token cur_token, prev_token;
6598
50705ef4
AM
6599/* Token codes for the intel parser. Since T_SHORT is already used
6600 by COFF, undefine it first to prevent a warning. */
64a0c779
DN
6601#define T_NIL -1
6602#define T_CONST 1
6603#define T_REG 2
6604#define T_BYTE 3
6605#define T_WORD 4
9306ca4a
JB
6606#define T_DWORD 5
6607#define T_FWORD 6
6608#define T_QWORD 7
6609#define T_TBYTE 8
6610#define T_XMMWORD 9
50705ef4 6611#undef T_SHORT
9306ca4a
JB
6612#define T_SHORT 10
6613#define T_OFFSET 11
6614#define T_PTR 12
6615#define T_ID 13
6616#define T_SHL 14
6617#define T_SHR 15
64a0c779
DN
6618
6619/* Prototypes for intel parser functions. */
e3bb37b5
L
6620static int intel_match_token (int);
6621static void intel_putback_token (void);
6622static void intel_get_token (void);
6623static int intel_expr (void);
6624static int intel_e04 (void);
6625static int intel_e05 (void);
6626static int intel_e06 (void);
6627static int intel_e09 (void);
6628static int intel_e10 (void);
6629static int intel_e11 (void);
64a0c779 6630
64a0c779 6631static int
e3bb37b5 6632i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN
6633{
6634 int ret;
6635 char *p;
6636
a724f0f4
JB
6637 p = intel_parser.op_string = xstrdup (operand_string);
6638 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6639
6640 for (;;)
64a0c779 6641 {
a724f0f4
JB
6642 /* Initialize token holders. */
6643 cur_token.code = prev_token.code = T_NIL;
6644 cur_token.reg = prev_token.reg = NULL;
6645 cur_token.str = prev_token.str = NULL;
6646
6647 /* Initialize parser structure. */
6648 intel_parser.got_a_float = got_a_float;
6649 intel_parser.op_modifier = 0;
6650 intel_parser.is_mem = 0;
6651 intel_parser.in_offset = 0;
6652 intel_parser.in_bracket = 0;
6653 intel_parser.reg = NULL;
6654 intel_parser.disp[0] = '\0';
6655 intel_parser.next_operand = NULL;
6656
6657 /* Read the first token and start the parser. */
6658 intel_get_token ();
6659 ret = intel_expr ();
6660
6661 if (!ret)
6662 break;
6663
9306ca4a
JB
6664 if (cur_token.code != T_NIL)
6665 {
6666 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6667 current_templates->start->name, cur_token.str);
6668 ret = 0;
6669 }
64a0c779
DN
6670 /* If we found a memory reference, hand it over to i386_displacement
6671 to fill in the rest of the operand fields. */
9306ca4a 6672 else if (intel_parser.is_mem)
64a0c779
DN
6673 {
6674 if ((i.mem_operands == 1
6675 && (current_templates->start->opcode_modifier & IsString) == 0)
6676 || i.mem_operands == 2)
6677 {
6678 as_bad (_("too many memory references for '%s'"),
6679 current_templates->start->name);
6680 ret = 0;
6681 }
6682 else
6683 {
6684 char *s = intel_parser.disp;
6685 i.mem_operands++;
6686
a724f0f4
JB
6687 if (!quiet_warnings && intel_parser.is_mem < 0)
6688 /* See the comments in intel_bracket_expr. */
6689 as_warn (_("Treating `%s' as memory reference"), operand_string);
6690
64a0c779
DN
6691 /* Add the displacement expression. */
6692 if (*s != '\0')
a4622f40
AM
6693 ret = i386_displacement (s, s + strlen (s));
6694 if (ret)
a724f0f4
JB
6695 {
6696 /* Swap base and index in 16-bit memory operands like
6697 [si+bx]. Since i386_index_check is also used in AT&T
6698 mode we have to do that here. */
6699 if (i.base_reg
6700 && i.index_reg
6701 && (i.base_reg->reg_type & Reg16)
6702 && (i.index_reg->reg_type & Reg16)
6703 && i.base_reg->reg_num >= 6
6704 && i.index_reg->reg_num < 6)
6705 {
6706 const reg_entry *base = i.index_reg;
6707
6708 i.index_reg = i.base_reg;
6709 i.base_reg = base;
6710 }
6711 ret = i386_index_check (operand_string);
6712 }
64a0c779
DN
6713 }
6714 }
6715
6716 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6717 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN
6718 || intel_parser.reg == NULL)
6719 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB
6720
6721 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6722 ret = 0;
a724f0f4
JB
6723 if (!ret || !intel_parser.next_operand)
6724 break;
6725 intel_parser.op_string = intel_parser.next_operand;
6726 this_operand = i.operands++;
64a0c779
DN
6727 }
6728
6729 free (p);
6730 free (intel_parser.disp);
6731
6732 return ret;
6733}
6734
a724f0f4
JB
6735#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6736
6737/* expr e04 expr'
6738
6739 expr' cmpOp e04 expr'
6740 | Empty */
64a0c779 6741static int
e3bb37b5 6742intel_expr (void)
64a0c779 6743{
a724f0f4
JB
6744 /* XXX Implement the comparison operators. */
6745 return intel_e04 ();
9306ca4a
JB
6746}
6747
a724f0f4 6748/* e04 e05 e04'
9306ca4a 6749
a724f0f4 6750 e04' addOp e05 e04'
9306ca4a
JB
6751 | Empty */
6752static int
e3bb37b5 6753intel_e04 (void)
9306ca4a 6754{
a724f0f4 6755 int nregs = -1;
9306ca4a 6756
a724f0f4 6757 for (;;)
9306ca4a 6758 {
a724f0f4
JB
6759 if (!intel_e05())
6760 return 0;
9306ca4a 6761
a724f0f4
JB
6762 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6763 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6764
a724f0f4
JB
6765 if (cur_token.code == '+')
6766 nregs = -1;
6767 else if (cur_token.code == '-')
6768 nregs = NUM_ADDRESS_REGS;
6769 else
6770 return 1;
64a0c779 6771
a724f0f4
JB
6772 strcat (intel_parser.disp, cur_token.str);
6773 intel_match_token (cur_token.code);
6774 }
64a0c779
DN
6775}
6776
64a0c779
DN
6777/* e05 e06 e05'
6778
9306ca4a 6779 e05' binOp e06 e05'
64a0c779
DN
6780 | Empty */
6781static int
e3bb37b5 6782intel_e05 (void)
64a0c779 6783{
a724f0f4 6784 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6785
a724f0f4 6786 for (;;)
64a0c779 6787 {
a724f0f4
JB
6788 if (!intel_e06())
6789 return 0;
6790
4eed87de
AM
6791 if (cur_token.code == '&'
6792 || cur_token.code == '|'
6793 || cur_token.code == '^')
a724f0f4
JB
6794 {
6795 char str[2];
6796
6797 str[0] = cur_token.code;
6798 str[1] = 0;
6799 strcat (intel_parser.disp, str);
6800 }
6801 else
6802 break;
9306ca4a 6803
64a0c779
DN
6804 intel_match_token (cur_token.code);
6805
a724f0f4
JB
6806 if (nregs < 0)
6807 nregs = ~nregs;
64a0c779 6808 }
a724f0f4
JB
6809 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6810 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6811 return 1;
4a1805b1 6812}
64a0c779
DN
6813
6814/* e06 e09 e06'
6815
6816 e06' mulOp e09 e06'
b77a7acd 6817 | Empty */
64a0c779 6818static int
e3bb37b5 6819intel_e06 (void)
64a0c779 6820{
a724f0f4 6821 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6822
a724f0f4 6823 for (;;)
64a0c779 6824 {
a724f0f4
JB
6825 if (!intel_e09())
6826 return 0;
9306ca4a 6827
4eed87de
AM
6828 if (cur_token.code == '*'
6829 || cur_token.code == '/'
6830 || cur_token.code == '%')
a724f0f4
JB
6831 {
6832 char str[2];
9306ca4a 6833
a724f0f4
JB
6834 str[0] = cur_token.code;
6835 str[1] = 0;
6836 strcat (intel_parser.disp, str);
6837 }
6838 else if (cur_token.code == T_SHL)
6839 strcat (intel_parser.disp, "<<");
6840 else if (cur_token.code == T_SHR)
6841 strcat (intel_parser.disp, ">>");
6842 else
6843 break;
9306ca4a 6844
64e74474 6845 intel_match_token (cur_token.code);
64a0c779 6846
a724f0f4
JB
6847 if (nregs < 0)
6848 nregs = ~nregs;
64a0c779 6849 }
a724f0f4
JB
6850 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6851 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6852 return 1;
64a0c779
DN
6853}
6854
a724f0f4
JB
6855/* e09 OFFSET e09
6856 | SHORT e09
6857 | + e09
6858 | - e09
6859 | ~ e09
6860 | NOT e09
9306ca4a
JB
6861 | e10 e09'
6862
64a0c779 6863 e09' PTR e10 e09'
b77a7acd 6864 | : e10 e09'
64a0c779
DN
6865 | Empty */
6866static int
e3bb37b5 6867intel_e09 (void)
64a0c779 6868{
a724f0f4
JB
6869 int nregs = ~NUM_ADDRESS_REGS;
6870 int in_offset = 0;
6871
6872 for (;;)
64a0c779 6873 {
a724f0f4
JB
6874 /* Don't consume constants here. */
6875 if (cur_token.code == '+' || cur_token.code == '-')
6876 {
6877 /* Need to look one token ahead - if the next token
6878 is a constant, the current token is its sign. */
6879 int next_code;
6880
6881 intel_match_token (cur_token.code);
6882 next_code = cur_token.code;
6883 intel_putback_token ();
6884 if (next_code == T_CONST)
6885 break;
6886 }
6887
6888 /* e09 OFFSET e09 */
6889 if (cur_token.code == T_OFFSET)
6890 {
6891 if (!in_offset++)
6892 ++intel_parser.in_offset;
6893 }
6894
6895 /* e09 SHORT e09 */
6896 else if (cur_token.code == T_SHORT)
6897 intel_parser.op_modifier |= 1 << T_SHORT;
6898
6899 /* e09 + e09 */
6900 else if (cur_token.code == '+')
6901 strcat (intel_parser.disp, "+");
6902
6903 /* e09 - e09
6904 | ~ e09
6905 | NOT e09 */
6906 else if (cur_token.code == '-' || cur_token.code == '~')
6907 {
6908 char str[2];
64a0c779 6909
a724f0f4
JB
6910 if (nregs < 0)
6911 nregs = ~nregs;
6912 str[0] = cur_token.code;
6913 str[1] = 0;
6914 strcat (intel_parser.disp, str);
6915 }
6916
6917 /* e09 e10 e09' */
6918 else
6919 break;
6920
6921 intel_match_token (cur_token.code);
64a0c779
DN
6922 }
6923
a724f0f4 6924 for (;;)
9306ca4a 6925 {
a724f0f4
JB
6926 if (!intel_e10 ())
6927 return 0;
9306ca4a 6928
a724f0f4
JB
6929 /* e09' PTR e10 e09' */
6930 if (cur_token.code == T_PTR)
6931 {
6932 char suffix;
9306ca4a 6933
a724f0f4
JB
6934 if (prev_token.code == T_BYTE)
6935 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6936
a724f0f4
JB
6937 else if (prev_token.code == T_WORD)
6938 {
6939 if (current_templates->start->name[0] == 'l'
6940 && current_templates->start->name[2] == 's'
6941 && current_templates->start->name[3] == 0)
6942 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6943 else if (intel_parser.got_a_float == 2) /* "fi..." */
6944 suffix = SHORT_MNEM_SUFFIX;
6945 else
6946 suffix = WORD_MNEM_SUFFIX;
6947 }
64a0c779 6948
a724f0f4
JB
6949 else if (prev_token.code == T_DWORD)
6950 {
6951 if (current_templates->start->name[0] == 'l'
6952 && current_templates->start->name[2] == 's'
6953 && current_templates->start->name[3] == 0)
6954 suffix = WORD_MNEM_SUFFIX;
6955 else if (flag_code == CODE_16BIT
6956 && (current_templates->start->opcode_modifier
435acd52 6957 & (Jump | JumpDword)))
a724f0f4
JB
6958 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6959 else if (intel_parser.got_a_float == 1) /* "f..." */
6960 suffix = SHORT_MNEM_SUFFIX;
6961 else
6962 suffix = LONG_MNEM_SUFFIX;
6963 }
9306ca4a 6964
a724f0f4
JB
6965 else if (prev_token.code == T_FWORD)
6966 {
6967 if (current_templates->start->name[0] == 'l'
6968 && current_templates->start->name[2] == 's'
6969 && current_templates->start->name[3] == 0)
6970 suffix = LONG_MNEM_SUFFIX;
6971 else if (!intel_parser.got_a_float)
6972 {
6973 if (flag_code == CODE_16BIT)
6974 add_prefix (DATA_PREFIX_OPCODE);
6975 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6976 }
6977 else
6978 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6979 }
64a0c779 6980
a724f0f4
JB
6981 else if (prev_token.code == T_QWORD)
6982 {
6983 if (intel_parser.got_a_float == 1) /* "f..." */
6984 suffix = LONG_MNEM_SUFFIX;
6985 else
6986 suffix = QWORD_MNEM_SUFFIX;
6987 }
64a0c779 6988
a724f0f4
JB
6989 else if (prev_token.code == T_TBYTE)
6990 {
6991 if (intel_parser.got_a_float == 1)
6992 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6993 else
6994 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6995 }
9306ca4a 6996
a724f0f4 6997 else if (prev_token.code == T_XMMWORD)
9306ca4a 6998 {
a724f0f4
JB
6999 /* XXX ignored for now, but accepted since gcc uses it */
7000 suffix = 0;
9306ca4a 7001 }
64a0c779 7002
f16b83df 7003 else
a724f0f4
JB
7004 {
7005 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7006 return 0;
7007 }
7008
435acd52
JB
7009 /* Operands for jump/call using 'ptr' notation denote absolute
7010 addresses. */
7011 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7012 i.types[this_operand] |= JumpAbsolute;
7013
a724f0f4
JB
7014 if (current_templates->start->base_opcode == 0x8d /* lea */)
7015 ;
7016 else if (!i.suffix)
7017 i.suffix = suffix;
7018 else if (i.suffix != suffix)
7019 {
7020 as_bad (_("Conflicting operand modifiers"));
7021 return 0;
7022 }
64a0c779 7023
9306ca4a
JB
7024 }
7025
a724f0f4
JB
7026 /* e09' : e10 e09' */
7027 else if (cur_token.code == ':')
9306ca4a 7028 {
a724f0f4
JB
7029 if (prev_token.code != T_REG)
7030 {
7031 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7032 segment/group identifier (which we don't have), using comma
7033 as the operand separator there is even less consistent, since
7034 there all branches only have a single operand. */
7035 if (this_operand != 0
7036 || intel_parser.in_offset
7037 || intel_parser.in_bracket
7038 || (!(current_templates->start->opcode_modifier
7039 & (Jump|JumpDword|JumpInterSegment))
7040 && !(current_templates->start->operand_types[0]
7041 & JumpAbsolute)))
7042 return intel_match_token (T_NIL);
7043 /* Remember the start of the 2nd operand and terminate 1st
7044 operand here.
7045 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7046 another expression), but it gets at least the simplest case
7047 (a plain number or symbol on the left side) right. */
7048 intel_parser.next_operand = intel_parser.op_string;
7049 *--intel_parser.op_string = '\0';
7050 return intel_match_token (':');
7051 }
9306ca4a 7052 }
64a0c779 7053
a724f0f4 7054 /* e09' Empty */
64a0c779 7055 else
a724f0f4 7056 break;
64a0c779 7057
a724f0f4
JB
7058 intel_match_token (cur_token.code);
7059
7060 }
7061
7062 if (in_offset)
7063 {
7064 --intel_parser.in_offset;
7065 if (nregs < 0)
7066 nregs = ~nregs;
7067 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7068 {
a724f0f4 7069 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB
7070 return 0;
7071 }
a724f0f4
JB
7072 intel_parser.op_modifier |= 1 << T_OFFSET;
7073 }
9306ca4a 7074
a724f0f4
JB
7075 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7076 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7077 return 1;
7078}
64a0c779 7079
a724f0f4 7080static int
e3bb37b5 7081intel_bracket_expr (void)
a724f0f4
JB
7082{
7083 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7084 const char *start = intel_parser.op_string;
7085 int len;
7086
7087 if (i.op[this_operand].regs)
7088 return intel_match_token (T_NIL);
7089
7090 intel_match_token ('[');
7091
7092 /* Mark as a memory operand only if it's not already known to be an
7093 offset expression. If it's an offset expression, we need to keep
7094 the brace in. */
7095 if (!intel_parser.in_offset)
7096 {
7097 ++intel_parser.in_bracket;
435acd52
JB
7098
7099 /* Operands for jump/call inside brackets denote absolute addresses. */
7100 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7101 i.types[this_operand] |= JumpAbsolute;
7102
a724f0f4
JB
7103 /* Unfortunately gas always diverged from MASM in a respect that can't
7104 be easily fixed without risking to break code sequences likely to be
7105 encountered (the testsuite even check for this): MASM doesn't consider
7106 an expression inside brackets unconditionally as a memory reference.
7107 When that is e.g. a constant, an offset expression, or the sum of the
7108 two, this is still taken as a constant load. gas, however, always
7109 treated these as memory references. As a compromise, we'll try to make
7110 offset expressions inside brackets work the MASM way (since that's
7111 less likely to be found in real world code), but make constants alone
7112 continue to work the traditional gas way. In either case, issue a
7113 warning. */
7114 intel_parser.op_modifier &= ~was_offset;
64a0c779 7115 }
a724f0f4 7116 else
64e74474 7117 strcat (intel_parser.disp, "[");
a724f0f4
JB
7118
7119 /* Add a '+' to the displacement string if necessary. */
7120 if (*intel_parser.disp != '\0'
7121 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7122 strcat (intel_parser.disp, "+");
64a0c779 7123
a724f0f4
JB
7124 if (intel_expr ()
7125 && (len = intel_parser.op_string - start - 1,
7126 intel_match_token (']')))
64a0c779 7127 {
a724f0f4
JB
7128 /* Preserve brackets when the operand is an offset expression. */
7129 if (intel_parser.in_offset)
7130 strcat (intel_parser.disp, "]");
7131 else
7132 {
7133 --intel_parser.in_bracket;
7134 if (i.base_reg || i.index_reg)
7135 intel_parser.is_mem = 1;
7136 if (!intel_parser.is_mem)
7137 {
7138 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7139 /* Defer the warning until all of the operand was parsed. */
7140 intel_parser.is_mem = -1;
7141 else if (!quiet_warnings)
4eed87de
AM
7142 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7143 len, start, len, start);
a724f0f4
JB
7144 }
7145 }
7146 intel_parser.op_modifier |= was_offset;
64a0c779 7147
a724f0f4 7148 return 1;
64a0c779 7149 }
a724f0f4 7150 return 0;
64a0c779
DN
7151}
7152
7153/* e10 e11 e10'
7154
7155 e10' [ expr ] e10'
b77a7acd 7156 | Empty */
64a0c779 7157static int
e3bb37b5 7158intel_e10 (void)
64a0c779 7159{
a724f0f4
JB
7160 if (!intel_e11 ())
7161 return 0;
64a0c779 7162
a724f0f4 7163 while (cur_token.code == '[')
64a0c779 7164 {
a724f0f4 7165 if (!intel_bracket_expr ())
21d6c4af 7166 return 0;
64a0c779
DN
7167 }
7168
a724f0f4 7169 return 1;
64a0c779
DN
7170}
7171
64a0c779 7172/* e11 ( expr )
b77a7acd 7173 | [ expr ]
64a0c779
DN
7174 | BYTE
7175 | WORD
7176 | DWORD
9306ca4a 7177 | FWORD
64a0c779 7178 | QWORD
9306ca4a
JB
7179 | TBYTE
7180 | OWORD
7181 | XMMWORD
4a1805b1 7182 | $
64a0c779
DN
7183 | .
7184 | register
7185 | id
7186 | constant */
7187static int
e3bb37b5 7188intel_e11 (void)
64a0c779 7189{
a724f0f4 7190 switch (cur_token.code)
64a0c779 7191 {
a724f0f4
JB
7192 /* e11 ( expr ) */
7193 case '(':
64a0c779
DN
7194 intel_match_token ('(');
7195 strcat (intel_parser.disp, "(");
7196
7197 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH
7198 {
7199 strcat (intel_parser.disp, ")");
7200 return 1;
7201 }
a724f0f4 7202 return 0;
4a1805b1 7203
a724f0f4
JB
7204 /* e11 [ expr ] */
7205 case '[':
a724f0f4 7206 return intel_bracket_expr ();
64a0c779 7207
a724f0f4
JB
7208 /* e11 $
7209 | . */
7210 case '.':
64a0c779
DN
7211 strcat (intel_parser.disp, cur_token.str);
7212 intel_match_token (cur_token.code);
21d6c4af
DN
7213
7214 /* Mark as a memory operand only if it's not already known to be an
7215 offset expression. */
a724f0f4 7216 if (!intel_parser.in_offset)
21d6c4af 7217 intel_parser.is_mem = 1;
64a0c779
DN
7218
7219 return 1;
64a0c779 7220
a724f0f4
JB
7221 /* e11 register */
7222 case T_REG:
7223 {
7224 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7225
a724f0f4 7226 intel_match_token (T_REG);
64a0c779 7227
a724f0f4
JB
7228 /* Check for segment change. */
7229 if (cur_token.code == ':')
7230 {
7231 if (!(reg->reg_type & (SReg2 | SReg3)))
7232 {
4eed87de
AM
7233 as_bad (_("`%s' is not a valid segment register"),
7234 reg->reg_name);
a724f0f4
JB
7235 return 0;
7236 }
7237 else if (i.seg[i.mem_operands])
7238 as_warn (_("Extra segment override ignored"));
7239 else
7240 {
7241 if (!intel_parser.in_offset)
7242 intel_parser.is_mem = 1;
7243 switch (reg->reg_num)
7244 {
7245 case 0:
7246 i.seg[i.mem_operands] = &es;
7247 break;
7248 case 1:
7249 i.seg[i.mem_operands] = &cs;
7250 break;
7251 case 2:
7252 i.seg[i.mem_operands] = &ss;
7253 break;
7254 case 3:
7255 i.seg[i.mem_operands] = &ds;
7256 break;
7257 case 4:
7258 i.seg[i.mem_operands] = &fs;
7259 break;
7260 case 5:
7261 i.seg[i.mem_operands] = &gs;
7262 break;
7263 }
7264 }
7265 }
64a0c779 7266
a724f0f4
JB
7267 /* Not a segment register. Check for register scaling. */
7268 else if (cur_token.code == '*')
7269 {
7270 if (!intel_parser.in_bracket)
7271 {
7272 as_bad (_("Register scaling only allowed in memory operands"));
7273 return 0;
7274 }
64a0c779 7275
a724f0f4
JB
7276 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7277 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7278 else if (i.index_reg)
7279 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7280
a724f0f4
JB
7281 /* What follows must be a valid scale. */
7282 intel_match_token ('*');
7283 i.index_reg = reg;
7284 i.types[this_operand] |= BaseIndex;
64a0c779 7285
a724f0f4
JB
7286 /* Set the scale after setting the register (otherwise,
7287 i386_scale will complain) */
7288 if (cur_token.code == '+' || cur_token.code == '-')
7289 {
7290 char *str, sign = cur_token.code;
7291 intel_match_token (cur_token.code);
7292 if (cur_token.code != T_CONST)
7293 {
7294 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7295 cur_token.str);
7296 return 0;
7297 }
7298 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7299 strcpy (str + 1, cur_token.str);
7300 *str = sign;
7301 if (!i386_scale (str))
7302 return 0;
7303 free (str);
7304 }
7305 else if (!i386_scale (cur_token.str))
64a0c779 7306 return 0;
a724f0f4
JB
7307 intel_match_token (cur_token.code);
7308 }
64a0c779 7309
a724f0f4
JB
7310 /* No scaling. If this is a memory operand, the register is either a
7311 base register (first occurrence) or an index register (second
7312 occurrence). */
7b0441f6 7313 else if (intel_parser.in_bracket)
a724f0f4 7314 {
64a0c779 7315
a724f0f4
JB
7316 if (!i.base_reg)
7317 i.base_reg = reg;
7318 else if (!i.index_reg)
7319 i.index_reg = reg;
7320 else
7321 {
7322 as_bad (_("Too many register references in memory operand"));
7323 return 0;
7324 }
64a0c779 7325
a724f0f4
JB
7326 i.types[this_operand] |= BaseIndex;
7327 }
4a1805b1 7328
4d1bb795
JB
7329 /* It's neither base nor index. */
7330 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB
7331 {
7332 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7333 i.op[this_operand].regs = reg;
7334 i.reg_operands++;
7335 }
7336 else
7337 {
7338 as_bad (_("Invalid use of register"));
7339 return 0;
7340 }
64a0c779 7341
a724f0f4
JB
7342 /* Since registers are not part of the displacement string (except
7343 when we're parsing offset operands), we may need to remove any
7344 preceding '+' from the displacement string. */
7345 if (*intel_parser.disp != '\0'
7346 && !intel_parser.in_offset)
7347 {
7348 char *s = intel_parser.disp;
7349 s += strlen (s) - 1;
7350 if (*s == '+')
7351 *s = '\0';
7352 }
4a1805b1 7353
a724f0f4
JB
7354 return 1;
7355 }
7356
7357 /* e11 BYTE
7358 | WORD
7359 | DWORD
7360 | FWORD
7361 | QWORD
7362 | TBYTE
7363 | OWORD
7364 | XMMWORD */
7365 case T_BYTE:
7366 case T_WORD:
7367 case T_DWORD:
7368 case T_FWORD:
7369 case T_QWORD:
7370 case T_TBYTE:
7371 case T_XMMWORD:
7372 intel_match_token (cur_token.code);
64a0c779 7373
a724f0f4
JB
7374 if (cur_token.code == T_PTR)
7375 return 1;
7376
7377 /* It must have been an identifier. */
7378 intel_putback_token ();
7379 cur_token.code = T_ID;
7380 /* FALLTHRU */
7381
7382 /* e11 id
7383 | constant */
7384 case T_ID:
7385 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB
7386 {
7387 symbolS *symbolP;
7388
a724f0f4
JB
7389 /* The identifier represents a memory reference only if it's not
7390 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB
7391 symbolP = symbol_find(cur_token.str);
7392 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7393 intel_parser.is_mem = 1;
7394 }
a724f0f4 7395 /* FALLTHRU */
64a0c779 7396
a724f0f4
JB
7397 case T_CONST:
7398 case '-':
7399 case '+':
7400 {
7401 char *save_str, sign = 0;
64a0c779 7402
a724f0f4
JB
7403 /* Allow constants that start with `+' or `-'. */
7404 if (cur_token.code == '-' || cur_token.code == '+')
7405 {
7406 sign = cur_token.code;
7407 intel_match_token (cur_token.code);
7408 if (cur_token.code != T_CONST)
7409 {
7410 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7411 cur_token.str);
7412 return 0;
7413 }
7414 }
64a0c779 7415
a724f0f4
JB
7416 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7417 strcpy (save_str + !!sign, cur_token.str);
7418 if (sign)
7419 *save_str = sign;
64a0c779 7420
a724f0f4
JB
7421 /* Get the next token to check for register scaling. */
7422 intel_match_token (cur_token.code);
64a0c779 7423
4eed87de
AM
7424 /* Check if this constant is a scaling factor for an
7425 index register. */
a724f0f4
JB
7426 if (cur_token.code == '*')
7427 {
7428 if (intel_match_token ('*') && cur_token.code == T_REG)
7429 {
7430 const reg_entry *reg = cur_token.reg;
7431
7432 if (!intel_parser.in_bracket)
7433 {
4eed87de
AM
7434 as_bad (_("Register scaling only allowed "
7435 "in memory operands"));
a724f0f4
JB
7436 return 0;
7437 }
7438
4eed87de
AM
7439 /* Disallow things like [1*si].
7440 sp and esp are invalid as index. */
7441 if (reg->reg_type & Reg16)
7442 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7443 else if (i.index_reg)
4eed87de 7444 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB
7445
7446 /* The constant is followed by `* reg', so it must be
7447 a valid scale. */
7448 i.index_reg = reg;
7449 i.types[this_operand] |= BaseIndex;
7450
7451 /* Set the scale after setting the register (otherwise,
7452 i386_scale will complain) */
7453 if (!i386_scale (save_str))
64a0c779 7454 return 0;
a724f0f4
JB
7455 intel_match_token (T_REG);
7456
7457 /* Since registers are not part of the displacement
7458 string, we may need to remove any preceding '+' from
7459 the displacement string. */
7460 if (*intel_parser.disp != '\0')
7461 {
7462 char *s = intel_parser.disp;
7463 s += strlen (s) - 1;
7464 if (*s == '+')
7465 *s = '\0';
7466 }
7467
7468 free (save_str);
7469
7470 return 1;
7471 }
64a0c779 7472
a724f0f4
JB
7473 /* The constant was not used for register scaling. Since we have
7474 already consumed the token following `*' we now need to put it
7475 back in the stream. */
64a0c779 7476 intel_putback_token ();
a724f0f4 7477 }
64a0c779 7478
a724f0f4
JB
7479 /* Add the constant to the displacement string. */
7480 strcat (intel_parser.disp, save_str);
7481 free (save_str);
64a0c779 7482
a724f0f4
JB
7483 return 1;
7484 }
64a0c779
DN
7485 }
7486
64a0c779
DN
7487 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7488 return 0;
7489}
7490
64a0c779
DN
7491/* Match the given token against cur_token. If they match, read the next
7492 token from the operand string. */
7493static int
e3bb37b5 7494intel_match_token (int code)
64a0c779
DN
7495{
7496 if (cur_token.code == code)
7497 {
7498 intel_get_token ();
7499 return 1;
7500 }
7501 else
7502 {
0477af35 7503 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN
7504 return 0;
7505 }
7506}
7507
64a0c779
DN
7508/* Read a new token from intel_parser.op_string and store it in cur_token. */
7509static void
e3bb37b5 7510intel_get_token (void)
64a0c779
DN
7511{
7512 char *end_op;
7513 const reg_entry *reg;
7514 struct intel_token new_token;
7515
7516 new_token.code = T_NIL;
7517 new_token.reg = NULL;
7518 new_token.str = NULL;
7519
4a1805b1 7520 /* Free the memory allocated to the previous token and move
64a0c779
DN
7521 cur_token to prev_token. */
7522 if (prev_token.str)
7523 free (prev_token.str);
7524
7525 prev_token = cur_token;
7526
7527 /* Skip whitespace. */
7528 while (is_space_char (*intel_parser.op_string))
7529 intel_parser.op_string++;
7530
7531 /* Return an empty token if we find nothing else on the line. */
7532 if (*intel_parser.op_string == '\0')
7533 {
7534 cur_token = new_token;
7535 return;
7536 }
7537
7538 /* The new token cannot be larger than the remainder of the operand
7539 string. */
a724f0f4 7540 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN
7541 new_token.str[0] = '\0';
7542
7543 if (strchr ("0123456789", *intel_parser.op_string))
7544 {
7545 char *p = new_token.str;
7546 char *q = intel_parser.op_string;
7547 new_token.code = T_CONST;
7548
7549 /* Allow any kind of identifier char to encompass floating point and
7550 hexadecimal numbers. */
7551 while (is_identifier_char (*q))
7552 *p++ = *q++;
7553 *p = '\0';
7554
7555 /* Recognize special symbol names [0-9][bf]. */
7556 if (strlen (intel_parser.op_string) == 2
4a1805b1 7557 && (intel_parser.op_string[1] == 'b'
64a0c779
DN
7558 || intel_parser.op_string[1] == 'f'))
7559 new_token.code = T_ID;
7560 }
7561
4d1bb795 7562 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7563 {
4d1bb795
JB
7564 size_t len = end_op - intel_parser.op_string;
7565
64a0c779
DN
7566 new_token.code = T_REG;
7567 new_token.reg = reg;
7568
4d1bb795
JB
7569 memcpy (new_token.str, intel_parser.op_string, len);
7570 new_token.str[len] = '\0';
64a0c779
DN
7571 }
7572
7573 else if (is_identifier_char (*intel_parser.op_string))
7574 {
7575 char *p = new_token.str;
7576 char *q = intel_parser.op_string;
7577
7578 /* A '.' or '$' followed by an identifier char is an identifier.
7579 Otherwise, it's operator '.' followed by an expression. */
7580 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7581 {
9306ca4a
JB
7582 new_token.code = '.';
7583 new_token.str[0] = '.';
64a0c779
DN
7584 new_token.str[1] = '\0';
7585 }
7586 else
7587 {
7588 while (is_identifier_char (*q) || *q == '@')
7589 *p++ = *q++;
7590 *p = '\0';
7591
9306ca4a
JB
7592 if (strcasecmp (new_token.str, "NOT") == 0)
7593 new_token.code = '~';
7594
7595 else if (strcasecmp (new_token.str, "MOD") == 0)
7596 new_token.code = '%';
7597
7598 else if (strcasecmp (new_token.str, "AND") == 0)
7599 new_token.code = '&';
7600
7601 else if (strcasecmp (new_token.str, "OR") == 0)
7602 new_token.code = '|';
7603
7604 else if (strcasecmp (new_token.str, "XOR") == 0)
7605 new_token.code = '^';
7606
7607 else if (strcasecmp (new_token.str, "SHL") == 0)
7608 new_token.code = T_SHL;
7609
7610 else if (strcasecmp (new_token.str, "SHR") == 0)
7611 new_token.code = T_SHR;
7612
7613 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN
7614 new_token.code = T_BYTE;
7615
7616 else if (strcasecmp (new_token.str, "WORD") == 0)
7617 new_token.code = T_WORD;
7618
7619 else if (strcasecmp (new_token.str, "DWORD") == 0)
7620 new_token.code = T_DWORD;
7621
9306ca4a
JB
7622 else if (strcasecmp (new_token.str, "FWORD") == 0)
7623 new_token.code = T_FWORD;
7624
64a0c779
DN
7625 else if (strcasecmp (new_token.str, "QWORD") == 0)
7626 new_token.code = T_QWORD;
7627
9306ca4a
JB
7628 else if (strcasecmp (new_token.str, "TBYTE") == 0
7629 /* XXX remove (gcc still uses it) */
7630 || strcasecmp (new_token.str, "XWORD") == 0)
7631 new_token.code = T_TBYTE;
7632
7633 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7634 || strcasecmp (new_token.str, "OWORD") == 0)
7635 new_token.code = T_XMMWORD;
64a0c779
DN
7636
7637 else if (strcasecmp (new_token.str, "PTR") == 0)
7638 new_token.code = T_PTR;
7639
7640 else if (strcasecmp (new_token.str, "SHORT") == 0)
7641 new_token.code = T_SHORT;
7642
7643 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7644 {
7645 new_token.code = T_OFFSET;
7646
7647 /* ??? This is not mentioned in the MASM grammar but gcc
7648 makes use of it with -mintel-syntax. OFFSET may be
7649 followed by FLAT: */
7650 if (strncasecmp (q, " FLAT:", 6) == 0)
7651 strcat (new_token.str, " FLAT:");
7652 }
7653
7654 /* ??? This is not mentioned in the MASM grammar. */
7655 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB
7656 {
7657 new_token.code = T_OFFSET;
7658 if (*q == ':')
7659 strcat (new_token.str, ":");
7660 else
7661 as_bad (_("`:' expected"));
7662 }
64a0c779
DN
7663
7664 else
7665 new_token.code = T_ID;
7666 }
7667 }
7668
9306ca4a
JB
7669 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7670 {
7671 new_token.code = *intel_parser.op_string;
7672 new_token.str[0] = *intel_parser.op_string;
7673 new_token.str[1] = '\0';
7674 }
7675
7676 else if (strchr ("<>", *intel_parser.op_string)
7677 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7678 {
7679 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7680 new_token.str[0] = *intel_parser.op_string;
7681 new_token.str[1] = *intel_parser.op_string;
7682 new_token.str[2] = '\0';
7683 }
7684
64a0c779 7685 else
0477af35 7686 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN
7687
7688 intel_parser.op_string += strlen (new_token.str);
7689 cur_token = new_token;
7690}
7691
64a0c779
DN
7692/* Put cur_token back into the token stream and make cur_token point to
7693 prev_token. */
7694static void
e3bb37b5 7695intel_putback_token (void)
64a0c779 7696{
a724f0f4
JB
7697 if (cur_token.code != T_NIL)
7698 {
7699 intel_parser.op_string -= strlen (cur_token.str);
7700 free (cur_token.str);
7701 }
64a0c779 7702 cur_token = prev_token;
4a1805b1 7703
64a0c779
DN
7704 /* Forget prev_token. */
7705 prev_token.code = T_NIL;
7706 prev_token.reg = NULL;
7707 prev_token.str = NULL;
7708}
54cfded0 7709
a4447b93 7710int
1df69f4f 7711tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM
7712{
7713 unsigned int regnum;
7714 unsigned int regnames_count;
089dfecd 7715 static const char *const regnames_32[] =
54cfded0 7716 {
a4447b93
RH
7717 "eax", "ecx", "edx", "ebx",
7718 "esp", "ebp", "esi", "edi",
089dfecd
JB
7719 "eip", "eflags", NULL,
7720 "st0", "st1", "st2", "st3",
7721 "st4", "st5", "st6", "st7",
7722 NULL, NULL,
7723 "xmm0", "xmm1", "xmm2", "xmm3",
7724 "xmm4", "xmm5", "xmm6", "xmm7",
7725 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB
7726 "mm4", "mm5", "mm6", "mm7",
7727 "fcw", "fsw", "mxcsr",
7728 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7729 "tr", "ldtr"
54cfded0 7730 };
089dfecd 7731 static const char *const regnames_64[] =
54cfded0 7732 {
089dfecd
JB
7733 "rax", "rdx", "rcx", "rbx",
7734 "rsi", "rdi", "rbp", "rsp",
7735 "r8", "r9", "r10", "r11",
54cfded0 7736 "r12", "r13", "r14", "r15",
089dfecd
JB
7737 "rip",
7738 "xmm0", "xmm1", "xmm2", "xmm3",
7739 "xmm4", "xmm5", "xmm6", "xmm7",
7740 "xmm8", "xmm9", "xmm10", "xmm11",
7741 "xmm12", "xmm13", "xmm14", "xmm15",
7742 "st0", "st1", "st2", "st3",
7743 "st4", "st5", "st6", "st7",
7744 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB
7745 "mm4", "mm5", "mm6", "mm7",
7746 "rflags",
7747 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7748 "fs.base", "gs.base", NULL, NULL,
7749 "tr", "ldtr",
7750 "mxcsr", "fcw", "fsw"
54cfded0 7751 };
089dfecd 7752 const char *const *regnames;
54cfded0
AM
7753
7754 if (flag_code == CODE_64BIT)
7755 {
7756 regnames = regnames_64;
0cea6190 7757 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM
7758 }
7759 else
7760 {
7761 regnames = regnames_32;
0cea6190 7762 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM
7763 }
7764
7765 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB
7766 if (regnames[regnum] != NULL
7767 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM
7768 return regnum;
7769
54cfded0
AM
7770 return -1;
7771}
7772
7773void
7774tc_x86_frame_initial_instructions (void)
7775{
a4447b93
RH
7776 static unsigned int sp_regno;
7777
7778 if (!sp_regno)
7779 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7780 ? "rsp" : "esp");
7781
7782 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7783 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7784}
d2b2c203
DJ
7785
7786int
7787i386_elf_section_type (const char *str, size_t len)
7788{
7789 if (flag_code == CODE_64BIT
7790 && len == sizeof ("unwind") - 1
7791 && strncmp (str, "unwind", 6) == 0)
7792 return SHT_X86_64_UNWIND;
7793
7794 return -1;
7795}
bb41ade5
AM
7796
7797#ifdef TE_PE
7798void
7799tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7800{
7801 expressionS expr;
7802
7803 expr.X_op = O_secrel;
7804 expr.X_add_symbol = symbol;
7805 expr.X_add_number = 0;
7806 emit_expr (&expr, size);
7807}
7808#endif
3b22753a
L
7809
7810#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7811/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7812
7813int
7814x86_64_section_letter (int letter, char **ptr_msg)
7815{
7816 if (flag_code == CODE_64BIT)
7817 {
7818 if (letter == 'l')
7819 return SHF_X86_64_LARGE;
7820
7821 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7822 }
3b22753a 7823 else
64e74474 7824 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L
7825 return -1;
7826}
7827
7828int
7829x86_64_section_word (char *str, size_t len)
7830{
8620418b 7831 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L
7832 return SHF_X86_64_LARGE;
7833
7834 return -1;
7835}
7836
7837static void
7838handle_large_common (int small ATTRIBUTE_UNUSED)
7839{
7840 if (flag_code != CODE_64BIT)
7841 {
7842 s_comm_internal (0, elf_common_parse);
7843 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7844 }
7845 else
7846 {
7847 static segT lbss_section;
7848 asection *saved_com_section_ptr = elf_com_section_ptr;
7849 asection *saved_bss_section = bss_section;
7850
7851 if (lbss_section == NULL)
7852 {
7853 flagword applicable;
7854 segT seg = now_seg;
7855 subsegT subseg = now_subseg;
7856
7857 /* The .lbss section is for local .largecomm symbols. */
7858 lbss_section = subseg_new (".lbss", 0);
7859 applicable = bfd_applicable_section_flags (stdoutput);
7860 bfd_set_section_flags (stdoutput, lbss_section,
7861 applicable & SEC_ALLOC);
7862 seg_info (lbss_section)->bss = 1;
7863
7864 subseg_set (seg, subseg);
7865 }
7866
7867 elf_com_section_ptr = &_bfd_elf_large_com_section;
7868 bss_section = lbss_section;
7869
7870 s_comm_internal (0, elf_common_parse);
7871
7872 elf_com_section_ptr = saved_com_section_ptr;
7873 bss_section = saved_bss_section;
7874 }
7875}
7876#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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