Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
4dc85607 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
e3bb37b5 L |
58 | static void set_code_flag (int); |
59 | static void set_16bit_gcc_code_flag (int); | |
60 | static void set_intel_syntax (int); | |
1efbbeb4 | 61 | static void set_intel_mnemonic (int); |
db51cc60 | 62 | static void set_allow_index_reg (int); |
e3bb37b5 | 63 | static void set_cpu_arch (int); |
6482c264 | 64 | #ifdef TE_PE |
e3bb37b5 | 65 | static void pe_directive_secrel (int); |
6482c264 | 66 | #endif |
e3bb37b5 L |
67 | static void signed_cons (int); |
68 | static char *output_invalid (int c); | |
69 | static int i386_operand (char *); | |
70 | static int i386_intel_operand (char *, int); | |
71 | static const reg_entry *parse_register (char *, char **); | |
72 | static char *parse_insn (char *, char *); | |
73 | static char *parse_operands (char *, const char *); | |
74 | static void swap_operands (void); | |
4d456e3d | 75 | static void swap_2_operands (int, int); |
e3bb37b5 L |
76 | static void optimize_imm (void); |
77 | static void optimize_disp (void); | |
78 | static int match_template (void); | |
79 | static int check_string (void); | |
80 | static int process_suffix (void); | |
81 | static int check_byte_reg (void); | |
82 | static int check_long_reg (void); | |
83 | static int check_qword_reg (void); | |
84 | static int check_word_reg (void); | |
85 | static int finalize_imm (void); | |
85f10a01 | 86 | static void process_drex (void); |
e3bb37b5 L |
87 | static int process_operands (void); |
88 | static const seg_entry *build_modrm_byte (void); | |
89 | static void output_insn (void); | |
90 | static void output_imm (fragS *, offsetT); | |
91 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 92 | #ifndef I386COFF |
e3bb37b5 | 93 | static void s_bss (int); |
252b5132 | 94 | #endif |
17d4e2a2 L |
95 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
96 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
97 | #endif | |
252b5132 | 98 | |
a847613f | 99 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 100 | |
252b5132 | 101 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 102 | i386_insn. */ |
252b5132 | 103 | |
520dc8e8 AM |
104 | union i386_op |
105 | { | |
106 | expressionS *disps; | |
107 | expressionS *imms; | |
108 | const reg_entry *regs; | |
109 | }; | |
110 | ||
252b5132 RH |
111 | struct _i386_insn |
112 | { | |
47926f60 | 113 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
114 | template tm; |
115 | ||
116 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
117 | (e.g. 'l' for 'movl') */ | |
118 | char suffix; | |
119 | ||
47926f60 | 120 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
121 | unsigned int operands; |
122 | ||
123 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
124 | of given register, displacement, memory operands and immediate | |
47926f60 | 125 | operands. */ |
252b5132 RH |
126 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
127 | ||
128 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 129 | use OP[i] for the corresponding operand. */ |
40fb9820 | 130 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 131 | |
520dc8e8 AM |
132 | /* Displacement expression, immediate expression, or register for each |
133 | operand. */ | |
134 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 135 | |
3e73aa7c JH |
136 | /* Flags for operands. */ |
137 | unsigned int flags[MAX_OPERANDS]; | |
138 | #define Operand_PCrel 1 | |
139 | ||
252b5132 | 140 | /* Relocation type for operand */ |
f86103b7 | 141 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 142 | |
252b5132 RH |
143 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
144 | the base index byte below. */ | |
145 | const reg_entry *base_reg; | |
146 | const reg_entry *index_reg; | |
147 | unsigned int log2_scale_factor; | |
148 | ||
149 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 150 | explicit segment overrides are given. */ |
ce8a8b2f | 151 | const seg_entry *seg[2]; |
252b5132 RH |
152 | |
153 | /* PREFIX holds all the given prefix opcodes (usually null). | |
154 | PREFIXES is the number of prefix opcodes. */ | |
155 | unsigned int prefixes; | |
156 | unsigned char prefix[MAX_PREFIXES]; | |
157 | ||
158 | /* RM and SIB are the modrm byte and the sib byte where the | |
85f10a01 MM |
159 | addressing modes of this insn are encoded. DREX is the byte |
160 | added by the SSE5 instructions. */ | |
252b5132 RH |
161 | |
162 | modrm_byte rm; | |
3e73aa7c | 163 | rex_byte rex; |
252b5132 | 164 | sib_byte sib; |
85f10a01 | 165 | drex_byte drex; |
252b5132 RH |
166 | }; |
167 | ||
168 | typedef struct _i386_insn i386_insn; | |
169 | ||
170 | /* List of chars besides those in app.c:symbol_chars that can start an | |
171 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 172 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 173 | #ifdef LEX_AT |
32137342 NC |
174 | "@" |
175 | #endif | |
176 | #ifdef LEX_QM | |
177 | "?" | |
252b5132 | 178 | #endif |
32137342 | 179 | ; |
252b5132 | 180 | |
29b0f896 AM |
181 | #if (defined (TE_I386AIX) \ |
182 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 183 | && !defined (TE_GNU) \ |
29b0f896 | 184 | && !defined (TE_LINUX) \ |
32137342 | 185 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
186 | && !defined (TE_FreeBSD) \ |
187 | && !defined (TE_NetBSD))) | |
252b5132 | 188 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
189 | pre-processor is disabled, these aren't very useful. The option |
190 | --divide will remove '/' from this list. */ | |
191 | const char *i386_comment_chars = "#/"; | |
192 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 193 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 194 | |
b3b91714 AM |
195 | #else |
196 | const char *i386_comment_chars = "#"; | |
197 | #define PREFIX_SEPARATOR '/' | |
198 | #endif | |
199 | ||
252b5132 RH |
200 | /* This array holds the chars that only start a comment at the beginning of |
201 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
202 | .line and .file directives will appear in the pre-processed output. |
203 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 204 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
205 | #NO_APP at the beginning of its output. |
206 | Also note that comments started like this one will always work if | |
252b5132 | 207 | '/' isn't otherwise defined. */ |
b3b91714 | 208 | const char line_comment_chars[] = "#/"; |
252b5132 | 209 | |
63a0b638 | 210 | const char line_separator_chars[] = ";"; |
252b5132 | 211 | |
ce8a8b2f AM |
212 | /* Chars that can be used to separate mant from exp in floating point |
213 | nums. */ | |
252b5132 RH |
214 | const char EXP_CHARS[] = "eE"; |
215 | ||
ce8a8b2f AM |
216 | /* Chars that mean this number is a floating point constant |
217 | As in 0f12.456 | |
218 | or 0d1.2345e12. */ | |
252b5132 RH |
219 | const char FLT_CHARS[] = "fFdDxX"; |
220 | ||
ce8a8b2f | 221 | /* Tables for lexical analysis. */ |
252b5132 RH |
222 | static char mnemonic_chars[256]; |
223 | static char register_chars[256]; | |
224 | static char operand_chars[256]; | |
225 | static char identifier_chars[256]; | |
226 | static char digit_chars[256]; | |
227 | ||
ce8a8b2f | 228 | /* Lexical macros. */ |
252b5132 RH |
229 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
230 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
231 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
232 | #define is_space_char(x) ((x) == ' ') | |
233 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
234 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
235 | ||
0234cb7c | 236 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
237 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
238 | ||
239 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
240 | effect this we maintain a stack of saved characters that we've smashed | |
241 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 242 | assembler instruction). */ |
252b5132 | 243 | static char save_stack[32]; |
ce8a8b2f | 244 | static char *save_stack_p; |
252b5132 RH |
245 | #define END_STRING_AND_SAVE(s) \ |
246 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
247 | #define RESTORE_END_STRING(s) \ | |
248 | do { *(s) = *--save_stack_p; } while (0) | |
249 | ||
47926f60 | 250 | /* The instruction we're assembling. */ |
252b5132 RH |
251 | static i386_insn i; |
252 | ||
253 | /* Possible templates for current insn. */ | |
254 | static const templates *current_templates; | |
255 | ||
31b2323c L |
256 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
257 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
258 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 259 | |
47926f60 KH |
260 | /* Current operand we are working on. */ |
261 | static int this_operand; | |
252b5132 | 262 | |
3e73aa7c JH |
263 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
264 | these. */ | |
265 | ||
266 | enum flag_code { | |
267 | CODE_32BIT, | |
268 | CODE_16BIT, | |
269 | CODE_64BIT }; | |
270 | ||
271 | static enum flag_code flag_code; | |
4fa24527 | 272 | static unsigned int object_64bit; |
3e73aa7c JH |
273 | static int use_rela_relocations = 0; |
274 | ||
275 | /* The names used to print error messages. */ | |
b77a7acd | 276 | static const char *flag_code_names[] = |
3e73aa7c JH |
277 | { |
278 | "32", | |
279 | "16", | |
280 | "64" | |
281 | }; | |
252b5132 | 282 | |
47926f60 KH |
283 | /* 1 for intel syntax, |
284 | 0 if att syntax. */ | |
285 | static int intel_syntax = 0; | |
252b5132 | 286 | |
1efbbeb4 L |
287 | /* 1 for intel mnemonic, |
288 | 0 if att mnemonic. */ | |
289 | static int intel_mnemonic = !SYSV386_COMPAT; | |
290 | ||
5209009a | 291 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
292 | static int old_gcc = OLDGCC_COMPAT; |
293 | ||
47926f60 KH |
294 | /* 1 if register prefix % not required. */ |
295 | static int allow_naked_reg = 0; | |
252b5132 | 296 | |
ba104c83 | 297 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
298 | static int allow_index_reg = 0; |
299 | ||
2ca3ace5 L |
300 | /* Register prefix used for error message. */ |
301 | static const char *register_prefix = "%"; | |
302 | ||
47926f60 KH |
303 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
304 | leave, push, and pop instructions so that gcc has the same stack | |
305 | frame as in 32 bit mode. */ | |
306 | static char stackop_size = '\0'; | |
eecb386c | 307 | |
12b55ccc L |
308 | /* Non-zero to optimize code alignment. */ |
309 | int optimize_align_code = 1; | |
310 | ||
47926f60 KH |
311 | /* Non-zero to quieten some warnings. */ |
312 | static int quiet_warnings = 0; | |
a38cf1db | 313 | |
47926f60 KH |
314 | /* CPU name. */ |
315 | static const char *cpu_arch_name = NULL; | |
5c6af06e | 316 | static const char *cpu_sub_arch_name = NULL; |
a38cf1db | 317 | |
47926f60 | 318 | /* CPU feature flags. */ |
40fb9820 L |
319 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
320 | ||
321 | /* Bitwise NOT of cpu_arch_flags. */ | |
322 | static i386_cpu_flags cpu_arch_flags_not; | |
a38cf1db | 323 | |
ccc9c027 L |
324 | /* If we have selected a cpu we are generating instructions for. */ |
325 | static int cpu_arch_tune_set = 0; | |
326 | ||
9103f4f4 L |
327 | /* Cpu we are generating instructions for. */ |
328 | static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; | |
329 | ||
330 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 331 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 332 | |
ccc9c027 L |
333 | /* CPU instruction set architecture used. */ |
334 | static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; | |
335 | ||
9103f4f4 | 336 | /* CPU feature flags of instruction set architecture used. */ |
40fb9820 | 337 | static i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 338 | |
fddf5b5b AM |
339 | /* If set, conditional jumps are not automatically promoted to handle |
340 | larger than a byte offset. */ | |
341 | static unsigned int no_cond_jump_promotion = 0; | |
342 | ||
29b0f896 | 343 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 344 | static symbolS *GOT_symbol; |
29b0f896 | 345 | |
a4447b93 RH |
346 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
347 | unsigned int x86_dwarf2_return_column; | |
348 | ||
349 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
350 | int x86_cie_data_alignment; | |
351 | ||
252b5132 | 352 | /* Interface to relax_segment. |
fddf5b5b AM |
353 | There are 3 major relax states for 386 jump insns because the |
354 | different types of jumps add different sizes to frags when we're | |
355 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 356 | |
47926f60 | 357 | /* Types. */ |
93c2a809 AM |
358 | #define UNCOND_JUMP 0 |
359 | #define COND_JUMP 1 | |
360 | #define COND_JUMP86 2 | |
fddf5b5b | 361 | |
47926f60 | 362 | /* Sizes. */ |
252b5132 RH |
363 | #define CODE16 1 |
364 | #define SMALL 0 | |
29b0f896 | 365 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 366 | #define BIG 2 |
29b0f896 | 367 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
368 | |
369 | #ifndef INLINE | |
370 | #ifdef __GNUC__ | |
371 | #define INLINE __inline__ | |
372 | #else | |
373 | #define INLINE | |
374 | #endif | |
375 | #endif | |
376 | ||
fddf5b5b AM |
377 | #define ENCODE_RELAX_STATE(type, size) \ |
378 | ((relax_substateT) (((type) << 2) | (size))) | |
379 | #define TYPE_FROM_RELAX_STATE(s) \ | |
380 | ((s) >> 2) | |
381 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
382 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
383 | |
384 | /* This table is used by relax_frag to promote short jumps to long | |
385 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
386 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
387 | don't allow a short jump in a 32 bit code segment to be promoted to | |
388 | a 16 bit offset jump because it's slower (requires data size | |
389 | prefix), and doesn't work, unless the destination is in the bottom | |
390 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
391 | ||
392 | const relax_typeS md_relax_table[] = | |
393 | { | |
24eab124 AM |
394 | /* The fields are: |
395 | 1) most positive reach of this state, | |
396 | 2) most negative reach of this state, | |
93c2a809 | 397 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 398 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 399 | |
fddf5b5b | 400 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
401 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
402 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
403 | /* dword jmp adds 4 bytes to frag: | |
404 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 405 | {0, 0, 4, 0}, |
93c2a809 AM |
406 | /* word jmp adds 2 byte2 to frag: |
407 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
408 | {0, 0, 2, 0}, |
409 | ||
93c2a809 AM |
410 | /* COND_JUMP states. */ |
411 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
412 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
413 | /* dword conditionals adds 5 bytes to frag: | |
414 | 1 extra opcode byte, 4 displacement bytes. */ | |
415 | {0, 0, 5, 0}, | |
fddf5b5b | 416 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
417 | 1 extra opcode byte, 2 displacement bytes. */ |
418 | {0, 0, 3, 0}, | |
419 | ||
420 | /* COND_JUMP86 states. */ | |
421 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
422 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
423 | /* dword conditionals adds 5 bytes to frag: | |
424 | 1 extra opcode byte, 4 displacement bytes. */ | |
425 | {0, 0, 5, 0}, | |
426 | /* word conditionals add 4 bytes to frag: | |
427 | 1 displacement byte and a 3 byte long branch insn. */ | |
428 | {0, 0, 4, 0} | |
252b5132 RH |
429 | }; |
430 | ||
9103f4f4 L |
431 | static const arch_entry cpu_arch[] = |
432 | { | |
433 | {"generic32", PROCESSOR_GENERIC32, | |
40fb9820 | 434 | CPU_GENERIC32_FLAGS }, |
9103f4f4 | 435 | {"generic64", PROCESSOR_GENERIC64, |
40fb9820 | 436 | CPU_GENERIC64_FLAGS }, |
9103f4f4 | 437 | {"i8086", PROCESSOR_UNKNOWN, |
40fb9820 | 438 | CPU_NONE_FLAGS }, |
9103f4f4 | 439 | {"i186", PROCESSOR_UNKNOWN, |
40fb9820 | 440 | CPU_I186_FLAGS }, |
9103f4f4 | 441 | {"i286", PROCESSOR_UNKNOWN, |
40fb9820 | 442 | CPU_I286_FLAGS }, |
76bc74dc | 443 | {"i386", PROCESSOR_I386, |
40fb9820 | 444 | CPU_I386_FLAGS }, |
9103f4f4 | 445 | {"i486", PROCESSOR_I486, |
40fb9820 | 446 | CPU_I486_FLAGS }, |
9103f4f4 | 447 | {"i586", PROCESSOR_PENTIUM, |
40fb9820 | 448 | CPU_I586_FLAGS }, |
9103f4f4 | 449 | {"i686", PROCESSOR_PENTIUMPRO, |
40fb9820 | 450 | CPU_I686_FLAGS }, |
9103f4f4 | 451 | {"pentium", PROCESSOR_PENTIUM, |
40fb9820 | 452 | CPU_I586_FLAGS }, |
9103f4f4 | 453 | {"pentiumpro",PROCESSOR_PENTIUMPRO, |
40fb9820 | 454 | CPU_I686_FLAGS }, |
9103f4f4 | 455 | {"pentiumii", PROCESSOR_PENTIUMPRO, |
40fb9820 | 456 | CPU_P2_FLAGS }, |
9103f4f4 | 457 | {"pentiumiii",PROCESSOR_PENTIUMPRO, |
40fb9820 | 458 | CPU_P3_FLAGS }, |
9103f4f4 | 459 | {"pentium4", PROCESSOR_PENTIUM4, |
40fb9820 | 460 | CPU_P4_FLAGS }, |
9103f4f4 | 461 | {"prescott", PROCESSOR_NOCONA, |
40fb9820 | 462 | CPU_CORE_FLAGS }, |
9103f4f4 | 463 | {"nocona", PROCESSOR_NOCONA, |
40fb9820 | 464 | CPU_NOCONA_FLAGS }, |
ef05d495 | 465 | {"yonah", PROCESSOR_CORE, |
40fb9820 | 466 | CPU_CORE_FLAGS }, |
ef05d495 | 467 | {"core", PROCESSOR_CORE, |
40fb9820 | 468 | CPU_CORE_FLAGS }, |
ef05d495 | 469 | {"merom", PROCESSOR_CORE2, |
40fb9820 | 470 | CPU_CORE2_FLAGS }, |
ef05d495 | 471 | {"core2", PROCESSOR_CORE2, |
40fb9820 | 472 | CPU_CORE2_FLAGS }, |
9103f4f4 | 473 | {"k6", PROCESSOR_K6, |
40fb9820 | 474 | CPU_K6_FLAGS }, |
9103f4f4 | 475 | {"k6_2", PROCESSOR_K6, |
40fb9820 | 476 | CPU_K6_2_FLAGS }, |
9103f4f4 | 477 | {"athlon", PROCESSOR_ATHLON, |
40fb9820 | 478 | CPU_ATHLON_FLAGS }, |
9103f4f4 | 479 | {"sledgehammer", PROCESSOR_K8, |
40fb9820 | 480 | CPU_K8_FLAGS }, |
9103f4f4 | 481 | {"opteron", PROCESSOR_K8, |
40fb9820 | 482 | CPU_K8_FLAGS }, |
9103f4f4 | 483 | {"k8", PROCESSOR_K8, |
40fb9820 | 484 | CPU_K8_FLAGS }, |
050dfa73 | 485 | {"amdfam10", PROCESSOR_AMDFAM10, |
40fb9820 | 486 | CPU_AMDFAM10_FLAGS }, |
9103f4f4 | 487 | {".mmx", PROCESSOR_UNKNOWN, |
40fb9820 | 488 | CPU_MMX_FLAGS }, |
9103f4f4 | 489 | {".sse", PROCESSOR_UNKNOWN, |
40fb9820 | 490 | CPU_SSE_FLAGS }, |
9103f4f4 | 491 | {".sse2", PROCESSOR_UNKNOWN, |
40fb9820 | 492 | CPU_SSE2_FLAGS }, |
9103f4f4 | 493 | {".sse3", PROCESSOR_UNKNOWN, |
40fb9820 | 494 | CPU_SSE3_FLAGS }, |
ef05d495 | 495 | {".ssse3", PROCESSOR_UNKNOWN, |
40fb9820 | 496 | CPU_SSSE3_FLAGS }, |
42903f7f | 497 | {".sse4.1", PROCESSOR_UNKNOWN, |
40fb9820 | 498 | CPU_SSE4_1_FLAGS }, |
381d071f | 499 | {".sse4.2", PROCESSOR_UNKNOWN, |
40fb9820 | 500 | CPU_SSE4_2_FLAGS }, |
381d071f | 501 | {".sse4", PROCESSOR_UNKNOWN, |
40fb9820 | 502 | CPU_SSE4_2_FLAGS }, |
9103f4f4 | 503 | {".3dnow", PROCESSOR_UNKNOWN, |
40fb9820 | 504 | CPU_3DNOW_FLAGS }, |
9103f4f4 | 505 | {".3dnowa", PROCESSOR_UNKNOWN, |
40fb9820 | 506 | CPU_3DNOWA_FLAGS }, |
9103f4f4 | 507 | {".padlock", PROCESSOR_UNKNOWN, |
40fb9820 | 508 | CPU_PADLOCK_FLAGS }, |
9103f4f4 | 509 | {".pacifica", PROCESSOR_UNKNOWN, |
40fb9820 | 510 | CPU_SVME_FLAGS }, |
9103f4f4 | 511 | {".svme", PROCESSOR_UNKNOWN, |
40fb9820 | 512 | CPU_SVME_FLAGS }, |
050dfa73 | 513 | {".sse4a", PROCESSOR_UNKNOWN, |
40fb9820 | 514 | CPU_SSE4A_FLAGS }, |
050dfa73 | 515 | {".abm", PROCESSOR_UNKNOWN, |
40fb9820 | 516 | CPU_ABM_FLAGS }, |
85f10a01 MM |
517 | {".sse5", PROCESSOR_UNKNOWN, |
518 | CPU_SSE5_FLAGS }, | |
e413e4e9 AM |
519 | }; |
520 | ||
29b0f896 AM |
521 | const pseudo_typeS md_pseudo_table[] = |
522 | { | |
523 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
524 | {"align", s_align_bytes, 0}, | |
525 | #else | |
526 | {"align", s_align_ptwo, 0}, | |
527 | #endif | |
528 | {"arch", set_cpu_arch, 0}, | |
529 | #ifndef I386COFF | |
530 | {"bss", s_bss, 0}, | |
531 | #endif | |
532 | {"ffloat", float_cons, 'f'}, | |
533 | {"dfloat", float_cons, 'd'}, | |
534 | {"tfloat", float_cons, 'x'}, | |
535 | {"value", cons, 2}, | |
d182319b | 536 | {"slong", signed_cons, 4}, |
29b0f896 AM |
537 | {"noopt", s_ignore, 0}, |
538 | {"optim", s_ignore, 0}, | |
539 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
540 | {"code16", set_code_flag, CODE_16BIT}, | |
541 | {"code32", set_code_flag, CODE_32BIT}, | |
542 | {"code64", set_code_flag, CODE_64BIT}, | |
543 | {"intel_syntax", set_intel_syntax, 1}, | |
544 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
545 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
546 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
547 | {"allow_index_reg", set_allow_index_reg, 1}, |
548 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
3b22753a L |
549 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
550 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 551 | #else |
e3bb37b5 | 552 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
553 | {"loc", dwarf2_directive_loc, 0}, |
554 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 555 | #endif |
6482c264 NC |
556 | #ifdef TE_PE |
557 | {"secrel32", pe_directive_secrel, 0}, | |
558 | #endif | |
29b0f896 AM |
559 | {0, 0, 0} |
560 | }; | |
561 | ||
562 | /* For interface with expression (). */ | |
563 | extern char *input_line_pointer; | |
564 | ||
565 | /* Hash table for instruction mnemonic lookup. */ | |
566 | static struct hash_control *op_hash; | |
567 | ||
568 | /* Hash table for register lookup. */ | |
569 | static struct hash_control *reg_hash; | |
570 | \f | |
252b5132 | 571 | void |
e3bb37b5 | 572 | i386_align_code (fragS *fragP, int count) |
252b5132 | 573 | { |
ce8a8b2f AM |
574 | /* Various efficient no-op patterns for aligning code labels. |
575 | Note: Don't try to assemble the instructions in the comments. | |
576 | 0L and 0w are not legal. */ | |
252b5132 RH |
577 | static const char f32_1[] = |
578 | {0x90}; /* nop */ | |
579 | static const char f32_2[] = | |
ccc9c027 | 580 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
581 | static const char f32_3[] = |
582 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
583 | static const char f32_4[] = | |
584 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
585 | static const char f32_5[] = | |
586 | {0x90, /* nop */ | |
587 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
588 | static const char f32_6[] = | |
589 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
590 | static const char f32_7[] = | |
591 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
592 | static const char f32_8[] = | |
593 | {0x90, /* nop */ | |
594 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
595 | static const char f32_9[] = | |
596 | {0x89,0xf6, /* movl %esi,%esi */ | |
597 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
598 | static const char f32_10[] = | |
599 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
600 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
601 | static const char f32_11[] = | |
602 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
603 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
604 | static const char f32_12[] = | |
605 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
606 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
607 | static const char f32_13[] = | |
608 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
609 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
610 | static const char f32_14[] = | |
611 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
612 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
613 | static const char f16_3[] = |
614 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
615 | static const char f16_4[] = |
616 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
617 | static const char f16_5[] = | |
618 | {0x90, /* nop */ | |
619 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
620 | static const char f16_6[] = | |
621 | {0x89,0xf6, /* mov %si,%si */ | |
622 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
623 | static const char f16_7[] = | |
624 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
625 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
626 | static const char f16_8[] = | |
627 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
628 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
629 | static const char jump_31[] = |
630 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
631 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
632 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
633 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
634 | static const char *const f32_patt[] = { |
635 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 636 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
637 | }; |
638 | static const char *const f16_patt[] = { | |
76bc74dc | 639 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 640 | }; |
ccc9c027 L |
641 | /* nopl (%[re]ax) */ |
642 | static const char alt_3[] = | |
643 | {0x0f,0x1f,0x00}; | |
644 | /* nopl 0(%[re]ax) */ | |
645 | static const char alt_4[] = | |
646 | {0x0f,0x1f,0x40,0x00}; | |
647 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
648 | static const char alt_5[] = | |
649 | {0x0f,0x1f,0x44,0x00,0x00}; | |
650 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
651 | static const char alt_6[] = | |
652 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
653 | /* nopl 0L(%[re]ax) */ | |
654 | static const char alt_7[] = | |
655 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
656 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
657 | static const char alt_8[] = | |
658 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
659 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
660 | static const char alt_9[] = | |
661 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
662 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
663 | static const char alt_10[] = | |
664 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
665 | /* data16 | |
666 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
667 | static const char alt_long_11[] = | |
668 | {0x66, | |
669 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
670 | /* data16 | |
671 | data16 | |
672 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
673 | static const char alt_long_12[] = | |
674 | {0x66, | |
675 | 0x66, | |
676 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
677 | /* data16 | |
678 | data16 | |
679 | data16 | |
680 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
681 | static const char alt_long_13[] = | |
682 | {0x66, | |
683 | 0x66, | |
684 | 0x66, | |
685 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
686 | /* data16 | |
687 | data16 | |
688 | data16 | |
689 | data16 | |
690 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
691 | static const char alt_long_14[] = | |
692 | {0x66, | |
693 | 0x66, | |
694 | 0x66, | |
695 | 0x66, | |
696 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
697 | /* data16 | |
698 | data16 | |
699 | data16 | |
700 | data16 | |
701 | data16 | |
702 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
703 | static const char alt_long_15[] = | |
704 | {0x66, | |
705 | 0x66, | |
706 | 0x66, | |
707 | 0x66, | |
708 | 0x66, | |
709 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
710 | /* nopl 0(%[re]ax,%[re]ax,1) | |
711 | nopw 0(%[re]ax,%[re]ax,1) */ | |
712 | static const char alt_short_11[] = | |
713 | {0x0f,0x1f,0x44,0x00,0x00, | |
714 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
715 | /* nopw 0(%[re]ax,%[re]ax,1) | |
716 | nopw 0(%[re]ax,%[re]ax,1) */ | |
717 | static const char alt_short_12[] = | |
718 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
719 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
720 | /* nopw 0(%[re]ax,%[re]ax,1) | |
721 | nopl 0L(%[re]ax) */ | |
722 | static const char alt_short_13[] = | |
723 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
724 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
725 | /* nopl 0L(%[re]ax) | |
726 | nopl 0L(%[re]ax) */ | |
727 | static const char alt_short_14[] = | |
728 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
729 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
730 | /* nopl 0L(%[re]ax) | |
731 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
732 | static const char alt_short_15[] = | |
733 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
734 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
735 | static const char *const alt_short_patt[] = { | |
736 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
737 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
738 | alt_short_14, alt_short_15 | |
739 | }; | |
740 | static const char *const alt_long_patt[] = { | |
741 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
742 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
743 | alt_long_14, alt_long_15 | |
744 | }; | |
252b5132 | 745 | |
76bc74dc L |
746 | /* Only align for at least a positive non-zero boundary. */ |
747 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 748 | return; |
3e73aa7c | 749 | |
ccc9c027 L |
750 | /* We need to decide which NOP sequence to use for 32bit and |
751 | 64bit. When -mtune= is used: | |
4eed87de | 752 | |
76bc74dc L |
753 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
754 | PROCESSOR_GENERIC32, f32_patt will be used. | |
755 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
756 | PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64, | |
757 | alt_long_patt will be used. | |
758 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and | |
759 | PROCESSOR_AMDFAM10, alt_short_patt will be used. | |
ccc9c027 | 760 | |
76bc74dc L |
761 | When -mtune= isn't used, alt_long_patt will be used if |
762 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will | |
763 | be used. | |
ccc9c027 L |
764 | |
765 | When -march= or .arch is used, we can't use anything beyond | |
766 | cpu_arch_isa_flags. */ | |
767 | ||
768 | if (flag_code == CODE_16BIT) | |
769 | { | |
ccc9c027 | 770 | if (count > 8) |
33fef721 | 771 | { |
76bc74dc L |
772 | memcpy (fragP->fr_literal + fragP->fr_fix, |
773 | jump_31, count); | |
774 | /* Adjust jump offset. */ | |
775 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 776 | } |
76bc74dc L |
777 | else |
778 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
779 | f16_patt[count - 1], count); | |
252b5132 | 780 | } |
33fef721 | 781 | else |
ccc9c027 L |
782 | { |
783 | const char *const *patt = NULL; | |
784 | ||
785 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
786 | { | |
787 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
788 | switch (cpu_arch_tune) | |
789 | { | |
790 | case PROCESSOR_UNKNOWN: | |
791 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
792 | optimize for Cpu686. */ | |
40fb9820 | 793 | if (cpu_arch_isa_flags.bitfield.cpui686) |
76bc74dc | 794 | patt = alt_long_patt; |
ccc9c027 L |
795 | else |
796 | patt = f32_patt; | |
797 | break; | |
ccc9c027 L |
798 | case PROCESSOR_PENTIUMPRO: |
799 | case PROCESSOR_PENTIUM4: | |
800 | case PROCESSOR_NOCONA: | |
ef05d495 | 801 | case PROCESSOR_CORE: |
76bc74dc L |
802 | case PROCESSOR_CORE2: |
803 | case PROCESSOR_GENERIC64: | |
804 | patt = alt_long_patt; | |
805 | break; | |
ccc9c027 L |
806 | case PROCESSOR_K6: |
807 | case PROCESSOR_ATHLON: | |
808 | case PROCESSOR_K8: | |
4eed87de | 809 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
810 | patt = alt_short_patt; |
811 | break; | |
76bc74dc | 812 | case PROCESSOR_I386: |
ccc9c027 L |
813 | case PROCESSOR_I486: |
814 | case PROCESSOR_PENTIUM: | |
815 | case PROCESSOR_GENERIC32: | |
816 | patt = f32_patt; | |
817 | break; | |
4eed87de | 818 | } |
ccc9c027 L |
819 | } |
820 | else | |
821 | { | |
822 | switch (cpu_arch_tune) | |
823 | { | |
824 | case PROCESSOR_UNKNOWN: | |
825 | /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be | |
826 | PROCESSOR_UNKNOWN. */ | |
827 | abort (); | |
828 | break; | |
829 | ||
76bc74dc | 830 | case PROCESSOR_I386: |
ccc9c027 L |
831 | case PROCESSOR_I486: |
832 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
833 | case PROCESSOR_K6: |
834 | case PROCESSOR_ATHLON: | |
835 | case PROCESSOR_K8: | |
4eed87de | 836 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
837 | case PROCESSOR_GENERIC32: |
838 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
839 | for Cpu686. */ | |
40fb9820 | 840 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
841 | patt = alt_short_patt; |
842 | else | |
843 | patt = f32_patt; | |
844 | break; | |
76bc74dc L |
845 | case PROCESSOR_PENTIUMPRO: |
846 | case PROCESSOR_PENTIUM4: | |
847 | case PROCESSOR_NOCONA: | |
848 | case PROCESSOR_CORE: | |
ef05d495 | 849 | case PROCESSOR_CORE2: |
40fb9820 | 850 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
851 | patt = alt_long_patt; |
852 | else | |
853 | patt = f32_patt; | |
854 | break; | |
855 | case PROCESSOR_GENERIC64: | |
76bc74dc | 856 | patt = alt_long_patt; |
ccc9c027 | 857 | break; |
4eed87de | 858 | } |
ccc9c027 L |
859 | } |
860 | ||
76bc74dc L |
861 | if (patt == f32_patt) |
862 | { | |
863 | /* If the padding is less than 15 bytes, we use the normal | |
864 | ones. Otherwise, we use a jump instruction and adjust | |
865 | its offset. */ | |
866 | if (count < 15) | |
867 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
868 | patt[count - 1], count); | |
869 | else | |
870 | { | |
871 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
872 | jump_31, count); | |
873 | /* Adjust jump offset. */ | |
874 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
875 | } | |
876 | } | |
877 | else | |
878 | { | |
879 | /* Maximum length of an instruction is 15 byte. If the | |
880 | padding is greater than 15 bytes and we don't use jump, | |
881 | we have to break it into smaller pieces. */ | |
882 | int padding = count; | |
883 | while (padding > 15) | |
884 | { | |
885 | padding -= 15; | |
886 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
887 | patt [14], 15); | |
888 | } | |
889 | ||
890 | if (padding) | |
891 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
892 | patt [padding - 1], padding); | |
893 | } | |
ccc9c027 | 894 | } |
33fef721 | 895 | fragP->fr_var = count; |
252b5132 RH |
896 | } |
897 | ||
c6fb90c8 L |
898 | static INLINE int |
899 | uints_all_zero (const unsigned int *x, unsigned int size) | |
40fb9820 | 900 | { |
c6fb90c8 L |
901 | switch (size) |
902 | { | |
903 | case 3: | |
904 | if (x[2]) | |
905 | return 0; | |
906 | case 2: | |
907 | if (x[1]) | |
908 | return 0; | |
909 | case 1: | |
910 | return !x[0]; | |
911 | default: | |
912 | abort (); | |
913 | } | |
40fb9820 L |
914 | } |
915 | ||
c6fb90c8 L |
916 | static INLINE void |
917 | uints_set (unsigned int *x, unsigned int v, unsigned int size) | |
40fb9820 | 918 | { |
c6fb90c8 L |
919 | switch (size) |
920 | { | |
921 | case 3: | |
922 | x[2] = v; | |
923 | case 2: | |
924 | x[1] = v; | |
925 | case 1: | |
926 | x[0] = v; | |
927 | break; | |
928 | default: | |
929 | abort (); | |
930 | } | |
931 | } | |
40fb9820 | 932 | |
c6fb90c8 L |
933 | static INLINE int |
934 | uints_equal (const unsigned int *x, const unsigned int *y, | |
935 | unsigned int size) | |
936 | { | |
937 | switch (size) | |
938 | { | |
939 | case 3: | |
940 | if (x[2] != y [2]) | |
941 | return 0; | |
942 | case 2: | |
943 | if (x[1] != y [1]) | |
944 | return 0; | |
945 | case 1: | |
946 | return x[0] == y [0]; | |
947 | break; | |
948 | default: | |
949 | abort (); | |
950 | } | |
951 | } | |
40fb9820 | 952 | |
c6fb90c8 L |
953 | #define UINTS_ALL_ZERO(x) \ |
954 | uints_all_zero ((x).array, ARRAY_SIZE ((x).array)) | |
955 | #define UINTS_SET(x, v) \ | |
956 | uints_set ((x).array, v, ARRAY_SIZE ((x).array)) | |
957 | #define UINTS_CLEAR(x) \ | |
958 | uints_set ((x).array, 0, ARRAY_SIZE ((x).array)) | |
959 | #define UINTS_EQUAL(x, y) \ | |
960 | uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array)) | |
961 | ||
962 | static INLINE int | |
963 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
964 | { | |
965 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
966 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
967 | } |
968 | ||
c6fb90c8 | 969 | static INLINE i386_cpu_flags |
40fb9820 L |
970 | cpu_flags_not (i386_cpu_flags x) |
971 | { | |
c6fb90c8 L |
972 | switch (ARRAY_SIZE (x.array)) |
973 | { | |
974 | case 3: | |
975 | x.array [2] = ~x.array [2]; | |
976 | case 2: | |
977 | x.array [1] = ~x.array [1]; | |
978 | case 1: | |
979 | x.array [0] = ~x.array [0]; | |
980 | break; | |
981 | default: | |
982 | abort (); | |
983 | } | |
40fb9820 L |
984 | |
985 | #ifdef CpuUnused | |
986 | x.bitfield.unused = 0; | |
987 | #endif | |
988 | ||
989 | return x; | |
990 | } | |
991 | ||
c6fb90c8 L |
992 | static INLINE i386_cpu_flags |
993 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 994 | { |
c6fb90c8 L |
995 | switch (ARRAY_SIZE (x.array)) |
996 | { | |
997 | case 3: | |
998 | x.array [2] &= y.array [2]; | |
999 | case 2: | |
1000 | x.array [1] &= y.array [1]; | |
1001 | case 1: | |
1002 | x.array [0] &= y.array [0]; | |
1003 | break; | |
1004 | default: | |
1005 | abort (); | |
1006 | } | |
1007 | return x; | |
1008 | } | |
40fb9820 | 1009 | |
c6fb90c8 L |
1010 | static INLINE i386_cpu_flags |
1011 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1012 | { |
c6fb90c8 | 1013 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1014 | { |
c6fb90c8 L |
1015 | case 3: |
1016 | x.array [2] |= y.array [2]; | |
1017 | case 2: | |
1018 | x.array [1] |= y.array [1]; | |
1019 | case 1: | |
1020 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1021 | break; |
1022 | default: | |
1023 | abort (); | |
1024 | } | |
40fb9820 L |
1025 | return x; |
1026 | } | |
1027 | ||
1028 | static int | |
1029 | cpu_flags_match (i386_cpu_flags x) | |
1030 | { | |
1031 | i386_cpu_flags not = cpu_arch_flags_not; | |
1032 | ||
1033 | not.bitfield.cpu64 = 1; | |
1034 | not.bitfield.cpuno64 = 1; | |
1035 | ||
1036 | x.bitfield.cpu64 = 0; | |
1037 | x.bitfield.cpuno64 = 0; | |
1038 | ||
c6fb90c8 L |
1039 | not = cpu_flags_and (x, not); |
1040 | return UINTS_ALL_ZERO (not); | |
40fb9820 L |
1041 | } |
1042 | ||
c6fb90c8 L |
1043 | static INLINE i386_operand_type |
1044 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1045 | { |
c6fb90c8 L |
1046 | switch (ARRAY_SIZE (x.array)) |
1047 | { | |
1048 | case 3: | |
1049 | x.array [2] &= y.array [2]; | |
1050 | case 2: | |
1051 | x.array [1] &= y.array [1]; | |
1052 | case 1: | |
1053 | x.array [0] &= y.array [0]; | |
1054 | break; | |
1055 | default: | |
1056 | abort (); | |
1057 | } | |
1058 | return x; | |
40fb9820 L |
1059 | } |
1060 | ||
c6fb90c8 L |
1061 | static INLINE i386_operand_type |
1062 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1063 | { |
c6fb90c8 | 1064 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1065 | { |
c6fb90c8 L |
1066 | case 3: |
1067 | x.array [2] |= y.array [2]; | |
1068 | case 2: | |
1069 | x.array [1] |= y.array [1]; | |
1070 | case 1: | |
1071 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1072 | break; |
1073 | default: | |
1074 | abort (); | |
1075 | } | |
c6fb90c8 L |
1076 | return x; |
1077 | } | |
40fb9820 | 1078 | |
c6fb90c8 L |
1079 | static INLINE i386_operand_type |
1080 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1081 | { | |
1082 | switch (ARRAY_SIZE (x.array)) | |
1083 | { | |
1084 | case 3: | |
1085 | x.array [2] ^= y.array [2]; | |
1086 | case 2: | |
1087 | x.array [1] ^= y.array [1]; | |
1088 | case 1: | |
1089 | x.array [0] ^= y.array [0]; | |
1090 | break; | |
1091 | default: | |
1092 | abort (); | |
1093 | } | |
40fb9820 L |
1094 | return x; |
1095 | } | |
1096 | ||
1097 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1098 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1099 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
1100 | static const i386_operand_type reg16_inoutportreg | |
1101 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1102 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1103 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1104 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1105 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1106 | static const i386_operand_type anydisp | |
1107 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 L |
1108 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
1109 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; | |
1110 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1111 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1112 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1113 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1114 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1115 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1116 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1117 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1118 | ||
1119 | enum operand_type | |
1120 | { | |
1121 | reg, | |
40fb9820 L |
1122 | imm, |
1123 | disp, | |
1124 | anymem | |
1125 | }; | |
1126 | ||
c6fb90c8 | 1127 | static INLINE int |
40fb9820 L |
1128 | operand_type_check (i386_operand_type t, enum operand_type c) |
1129 | { | |
1130 | switch (c) | |
1131 | { | |
1132 | case reg: | |
1133 | return (t.bitfield.reg8 | |
1134 | || t.bitfield.reg16 | |
1135 | || t.bitfield.reg32 | |
1136 | || t.bitfield.reg64); | |
1137 | ||
40fb9820 L |
1138 | case imm: |
1139 | return (t.bitfield.imm8 | |
1140 | || t.bitfield.imm8s | |
1141 | || t.bitfield.imm16 | |
1142 | || t.bitfield.imm32 | |
1143 | || t.bitfield.imm32s | |
1144 | || t.bitfield.imm64); | |
1145 | ||
1146 | case disp: | |
1147 | return (t.bitfield.disp8 | |
1148 | || t.bitfield.disp16 | |
1149 | || t.bitfield.disp32 | |
1150 | || t.bitfield.disp32s | |
1151 | || t.bitfield.disp64); | |
1152 | ||
1153 | case anymem: | |
1154 | return (t.bitfield.disp8 | |
1155 | || t.bitfield.disp16 | |
1156 | || t.bitfield.disp32 | |
1157 | || t.bitfield.disp32s | |
1158 | || t.bitfield.disp64 | |
1159 | || t.bitfield.baseindex); | |
1160 | ||
1161 | default: | |
1162 | abort (); | |
1163 | } | |
1164 | } | |
1165 | ||
c6fb90c8 | 1166 | static INLINE int |
40fb9820 L |
1167 | operand_type_match (i386_operand_type overlap, |
1168 | i386_operand_type given) | |
1169 | { | |
1170 | i386_operand_type temp = overlap; | |
1171 | ||
1172 | temp.bitfield.jumpabsolute = 0; | |
c6fb90c8 | 1173 | if (UINTS_ALL_ZERO (temp)) |
40fb9820 L |
1174 | return 0; |
1175 | ||
1176 | return (given.bitfield.baseindex == overlap.bitfield.baseindex | |
1177 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute); | |
1178 | } | |
1179 | ||
1180 | /* If given types r0 and r1 are registers they must be of the same type | |
1181 | unless the expected operand type register overlap is null. | |
1182 | Note that Acc in a template matches every size of reg. */ | |
1183 | ||
c6fb90c8 | 1184 | static INLINE int |
40fb9820 L |
1185 | operand_type_register_match (i386_operand_type m0, |
1186 | i386_operand_type g0, | |
1187 | i386_operand_type t0, | |
1188 | i386_operand_type m1, | |
1189 | i386_operand_type g1, | |
1190 | i386_operand_type t1) | |
1191 | { | |
1192 | if (!operand_type_check (g0, reg)) | |
1193 | return 1; | |
1194 | ||
1195 | if (!operand_type_check (g1, reg)) | |
1196 | return 1; | |
1197 | ||
1198 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1199 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1200 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1201 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1202 | return 1; | |
1203 | ||
1204 | if (m0.bitfield.acc) | |
1205 | { | |
1206 | t0.bitfield.reg8 = 1; | |
1207 | t0.bitfield.reg16 = 1; | |
1208 | t0.bitfield.reg32 = 1; | |
1209 | t0.bitfield.reg64 = 1; | |
1210 | } | |
1211 | ||
1212 | if (m1.bitfield.acc) | |
1213 | { | |
1214 | t1.bitfield.reg8 = 1; | |
1215 | t1.bitfield.reg16 = 1; | |
1216 | t1.bitfield.reg32 = 1; | |
1217 | t1.bitfield.reg64 = 1; | |
1218 | } | |
1219 | ||
1220 | return (!(t0.bitfield.reg8 & t1.bitfield.reg8) | |
1221 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1222 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1223 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)); | |
1224 | } | |
1225 | ||
252b5132 | 1226 | static INLINE unsigned int |
40fb9820 | 1227 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1228 | { |
40fb9820 L |
1229 | if (t.bitfield.disp8) |
1230 | return 1; | |
1231 | else if (t.bitfield.disp16 | |
1232 | || t.bitfield.disp32 | |
1233 | || t.bitfield.disp32s) | |
1234 | return 2; | |
1235 | else | |
1236 | return 0; | |
252b5132 RH |
1237 | } |
1238 | ||
1239 | static INLINE int | |
e3bb37b5 | 1240 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1241 | { |
1242 | return (num >= -128) && (num <= 127); | |
47926f60 | 1243 | } |
252b5132 RH |
1244 | |
1245 | static INLINE int | |
e3bb37b5 | 1246 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1247 | { |
1248 | return (num & 0xff) == num; | |
47926f60 | 1249 | } |
252b5132 RH |
1250 | |
1251 | static INLINE int | |
e3bb37b5 | 1252 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1253 | { |
1254 | return (num & 0xffff) == num; | |
47926f60 | 1255 | } |
252b5132 RH |
1256 | |
1257 | static INLINE int | |
e3bb37b5 | 1258 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1259 | { |
1260 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1261 | } |
2a962e6d | 1262 | |
3e73aa7c | 1263 | static INLINE int |
e3bb37b5 | 1264 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1265 | { |
1266 | #ifndef BFD64 | |
1267 | return 1; | |
1268 | #else | |
1269 | return (!(((offsetT) -1 << 31) & num) | |
1270 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1271 | #endif | |
1272 | } /* fits_in_signed_long() */ | |
2a962e6d | 1273 | |
3e73aa7c | 1274 | static INLINE int |
e3bb37b5 | 1275 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1276 | { |
1277 | #ifndef BFD64 | |
1278 | return 1; | |
1279 | #else | |
1280 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1281 | #endif | |
1282 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1283 | |
40fb9820 | 1284 | static i386_operand_type |
e3bb37b5 | 1285 | smallest_imm_type (offsetT num) |
252b5132 | 1286 | { |
40fb9820 L |
1287 | i386_operand_type t; |
1288 | ||
c6fb90c8 | 1289 | UINTS_CLEAR (t); |
40fb9820 L |
1290 | t.bitfield.imm64 = 1; |
1291 | ||
1292 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1293 | { |
1294 | /* This code is disabled on the 486 because all the Imm1 forms | |
1295 | in the opcode table are slower on the i486. They're the | |
1296 | versions with the implicitly specified single-position | |
1297 | displacement, which has another syntax if you really want to | |
1298 | use that form. */ | |
40fb9820 L |
1299 | t.bitfield.imm1 = 1; |
1300 | t.bitfield.imm8 = 1; | |
1301 | t.bitfield.imm8s = 1; | |
1302 | t.bitfield.imm16 = 1; | |
1303 | t.bitfield.imm32 = 1; | |
1304 | t.bitfield.imm32s = 1; | |
1305 | } | |
1306 | else if (fits_in_signed_byte (num)) | |
1307 | { | |
1308 | t.bitfield.imm8 = 1; | |
1309 | t.bitfield.imm8s = 1; | |
1310 | t.bitfield.imm16 = 1; | |
1311 | t.bitfield.imm32 = 1; | |
1312 | t.bitfield.imm32s = 1; | |
1313 | } | |
1314 | else if (fits_in_unsigned_byte (num)) | |
1315 | { | |
1316 | t.bitfield.imm8 = 1; | |
1317 | t.bitfield.imm16 = 1; | |
1318 | t.bitfield.imm32 = 1; | |
1319 | t.bitfield.imm32s = 1; | |
1320 | } | |
1321 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1322 | { | |
1323 | t.bitfield.imm16 = 1; | |
1324 | t.bitfield.imm32 = 1; | |
1325 | t.bitfield.imm32s = 1; | |
1326 | } | |
1327 | else if (fits_in_signed_long (num)) | |
1328 | { | |
1329 | t.bitfield.imm32 = 1; | |
1330 | t.bitfield.imm32s = 1; | |
1331 | } | |
1332 | else if (fits_in_unsigned_long (num)) | |
1333 | t.bitfield.imm32 = 1; | |
1334 | ||
1335 | return t; | |
47926f60 | 1336 | } |
252b5132 | 1337 | |
847f7ad4 | 1338 | static offsetT |
e3bb37b5 | 1339 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1340 | { |
508866be | 1341 | addressT mask; |
ba2adb93 | 1342 | |
847f7ad4 AM |
1343 | switch (size) |
1344 | { | |
508866be L |
1345 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1346 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1347 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1348 | #ifdef BFD64 |
1349 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1350 | #endif | |
47926f60 | 1351 | default: abort (); |
847f7ad4 AM |
1352 | } |
1353 | ||
ba2adb93 | 1354 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
1355 | if (!use_rela_relocations) |
1356 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
1357 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 1358 | |
47926f60 | 1359 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1360 | { |
1361 | char buf1[40], buf2[40]; | |
1362 | ||
1363 | sprint_value (buf1, val); | |
1364 | sprint_value (buf2, val & mask); | |
1365 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1366 | } | |
1367 | return val & mask; | |
1368 | } | |
1369 | ||
252b5132 RH |
1370 | /* Returns 0 if attempting to add a prefix where one from the same |
1371 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
1372 | added. */ | |
1373 | static int | |
e3bb37b5 | 1374 | add_prefix (unsigned int prefix) |
252b5132 RH |
1375 | { |
1376 | int ret = 1; | |
b1905489 | 1377 | unsigned int q; |
252b5132 | 1378 | |
29b0f896 AM |
1379 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1380 | && flag_code == CODE_64BIT) | |
b1905489 | 1381 | { |
161a04f6 L |
1382 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1383 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1384 | && (prefix & (REX_R | REX_X | REX_B)))) | |
b1905489 JB |
1385 | ret = 0; |
1386 | q = REX_PREFIX; | |
1387 | } | |
3e73aa7c | 1388 | else |
b1905489 JB |
1389 | { |
1390 | switch (prefix) | |
1391 | { | |
1392 | default: | |
1393 | abort (); | |
1394 | ||
1395 | case CS_PREFIX_OPCODE: | |
1396 | case DS_PREFIX_OPCODE: | |
1397 | case ES_PREFIX_OPCODE: | |
1398 | case FS_PREFIX_OPCODE: | |
1399 | case GS_PREFIX_OPCODE: | |
1400 | case SS_PREFIX_OPCODE: | |
1401 | q = SEG_PREFIX; | |
1402 | break; | |
1403 | ||
1404 | case REPNE_PREFIX_OPCODE: | |
1405 | case REPE_PREFIX_OPCODE: | |
1406 | ret = 2; | |
1407 | /* fall thru */ | |
1408 | case LOCK_PREFIX_OPCODE: | |
1409 | q = LOCKREP_PREFIX; | |
1410 | break; | |
1411 | ||
1412 | case FWAIT_OPCODE: | |
1413 | q = WAIT_PREFIX; | |
1414 | break; | |
1415 | ||
1416 | case ADDR_PREFIX_OPCODE: | |
1417 | q = ADDR_PREFIX; | |
1418 | break; | |
1419 | ||
1420 | case DATA_PREFIX_OPCODE: | |
1421 | q = DATA_PREFIX; | |
1422 | break; | |
1423 | } | |
1424 | if (i.prefix[q] != 0) | |
1425 | ret = 0; | |
1426 | } | |
252b5132 | 1427 | |
b1905489 | 1428 | if (ret) |
252b5132 | 1429 | { |
b1905489 JB |
1430 | if (!i.prefix[q]) |
1431 | ++i.prefixes; | |
1432 | i.prefix[q] |= prefix; | |
252b5132 | 1433 | } |
b1905489 JB |
1434 | else |
1435 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1436 | |
252b5132 RH |
1437 | return ret; |
1438 | } | |
1439 | ||
1440 | static void | |
e3bb37b5 | 1441 | set_code_flag (int value) |
eecb386c | 1442 | { |
3e73aa7c | 1443 | flag_code = value; |
40fb9820 L |
1444 | if (flag_code == CODE_64BIT) |
1445 | { | |
1446 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1447 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
1448 | cpu_arch_flags_not.bitfield.cpu64 = 0; | |
1449 | cpu_arch_flags_not.bitfield.cpuno64 = 1; | |
1450 | } | |
1451 | else | |
1452 | { | |
1453 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1454 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1455 | cpu_arch_flags_not.bitfield.cpu64 = 1; | |
1456 | cpu_arch_flags_not.bitfield.cpuno64 = 0; | |
1457 | } | |
1458 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c JH |
1459 | { |
1460 | as_bad (_("64bit mode not supported on this CPU.")); | |
1461 | } | |
40fb9820 | 1462 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c JH |
1463 | { |
1464 | as_bad (_("32bit mode not supported on this CPU.")); | |
1465 | } | |
eecb386c AM |
1466 | stackop_size = '\0'; |
1467 | } | |
1468 | ||
1469 | static void | |
e3bb37b5 | 1470 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1471 | { |
3e73aa7c | 1472 | flag_code = new_code_flag; |
40fb9820 L |
1473 | if (flag_code != CODE_16BIT) |
1474 | abort (); | |
1475 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1476 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1477 | cpu_arch_flags_not.bitfield.cpu64 = 1; | |
1478 | cpu_arch_flags_not.bitfield.cpuno64 = 0; | |
9306ca4a | 1479 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1480 | } |
1481 | ||
1482 | static void | |
e3bb37b5 | 1483 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1484 | { |
1485 | /* Find out if register prefixing is specified. */ | |
1486 | int ask_naked_reg = 0; | |
1487 | ||
1488 | SKIP_WHITESPACE (); | |
29b0f896 | 1489 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1490 | { |
1491 | char *string = input_line_pointer; | |
1492 | int e = get_symbol_end (); | |
1493 | ||
47926f60 | 1494 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1495 | ask_naked_reg = 1; |
47926f60 | 1496 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1497 | ask_naked_reg = -1; |
1498 | else | |
d0b47220 | 1499 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1500 | *input_line_pointer = e; |
1501 | } | |
1502 | demand_empty_rest_of_line (); | |
c3332e24 | 1503 | |
252b5132 RH |
1504 | intel_syntax = syntax_flag; |
1505 | ||
1506 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1507 | allow_naked_reg = (intel_syntax |
1508 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1509 | else |
1510 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1511 | |
e4a3b5a4 | 1512 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1513 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1514 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1515 | } |
1516 | ||
1efbbeb4 L |
1517 | static void |
1518 | set_intel_mnemonic (int mnemonic_flag) | |
1519 | { | |
1520 | /* Find out if register prefixing is specified. */ | |
1521 | int ask_naked_reg = 0; | |
1522 | ||
1523 | SKIP_WHITESPACE (); | |
1524 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
1525 | { | |
1526 | char *string = input_line_pointer; | |
1527 | int e = get_symbol_end (); | |
1528 | ||
1529 | if (strcmp (string, "prefix") == 0) | |
1530 | ask_naked_reg = 1; | |
1531 | else if (strcmp (string, "noprefix") == 0) | |
1532 | ask_naked_reg = -1; | |
1533 | else | |
1534 | as_bad (_("bad argument to syntax directive.")); | |
1535 | *input_line_pointer = e; | |
1536 | } | |
1537 | demand_empty_rest_of_line (); | |
1538 | ||
1539 | /* intel_mnemonic implies intel_syntax. */ | |
1540 | intel_mnemonic = intel_syntax = mnemonic_flag; | |
1541 | ||
1542 | if (ask_naked_reg == 0) | |
1543 | allow_naked_reg = (intel_mnemonic | |
1544 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
1545 | else | |
1546 | allow_naked_reg = (ask_naked_reg < 0); | |
1547 | ||
1548 | identifier_chars['%'] = intel_mnemonic && allow_naked_reg ? '%' : 0; | |
1549 | identifier_chars['$'] = intel_mnemonic ? '$' : 0; | |
1550 | register_prefix = allow_naked_reg ? "" : "%"; | |
1551 | } | |
1552 | ||
db51cc60 L |
1553 | static void |
1554 | set_allow_index_reg (int flag) | |
1555 | { | |
1556 | allow_index_reg = flag; | |
1557 | } | |
1558 | ||
e413e4e9 | 1559 | static void |
e3bb37b5 | 1560 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1561 | { |
47926f60 | 1562 | SKIP_WHITESPACE (); |
e413e4e9 | 1563 | |
29b0f896 | 1564 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1565 | { |
1566 | char *string = input_line_pointer; | |
1567 | int e = get_symbol_end (); | |
9103f4f4 | 1568 | unsigned int i; |
40fb9820 | 1569 | i386_cpu_flags flags; |
e413e4e9 | 1570 | |
9103f4f4 | 1571 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
1572 | { |
1573 | if (strcmp (string, cpu_arch[i].name) == 0) | |
1574 | { | |
5c6af06e JB |
1575 | if (*string != '.') |
1576 | { | |
1577 | cpu_arch_name = cpu_arch[i].name; | |
1578 | cpu_sub_arch_name = NULL; | |
40fb9820 L |
1579 | cpu_arch_flags = cpu_arch[i].flags; |
1580 | if (flag_code == CODE_64BIT) | |
1581 | { | |
1582 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1583 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
1584 | } | |
1585 | else | |
1586 | { | |
1587 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1588 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1589 | } | |
1590 | cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags); | |
ccc9c027 | 1591 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 1592 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
1593 | if (!cpu_arch_tune_set) |
1594 | { | |
1595 | cpu_arch_tune = cpu_arch_isa; | |
1596 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
1597 | } | |
5c6af06e JB |
1598 | break; |
1599 | } | |
40fb9820 | 1600 | |
c6fb90c8 L |
1601 | flags = cpu_flags_or (cpu_arch_flags, |
1602 | cpu_arch[i].flags); | |
1603 | if (!UINTS_EQUAL (flags, cpu_arch_flags)) | |
5c6af06e JB |
1604 | { |
1605 | cpu_sub_arch_name = cpu_arch[i].name; | |
40fb9820 L |
1606 | cpu_arch_flags = flags; |
1607 | cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags); | |
5c6af06e JB |
1608 | } |
1609 | *input_line_pointer = e; | |
1610 | demand_empty_rest_of_line (); | |
1611 | return; | |
e413e4e9 AM |
1612 | } |
1613 | } | |
9103f4f4 | 1614 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
1615 | as_bad (_("no such architecture: `%s'"), string); |
1616 | ||
1617 | *input_line_pointer = e; | |
1618 | } | |
1619 | else | |
1620 | as_bad (_("missing cpu architecture")); | |
1621 | ||
fddf5b5b AM |
1622 | no_cond_jump_promotion = 0; |
1623 | if (*input_line_pointer == ',' | |
29b0f896 | 1624 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
1625 | { |
1626 | char *string = ++input_line_pointer; | |
1627 | int e = get_symbol_end (); | |
1628 | ||
1629 | if (strcmp (string, "nojumps") == 0) | |
1630 | no_cond_jump_promotion = 1; | |
1631 | else if (strcmp (string, "jumps") == 0) | |
1632 | ; | |
1633 | else | |
1634 | as_bad (_("no such architecture modifier: `%s'"), string); | |
1635 | ||
1636 | *input_line_pointer = e; | |
1637 | } | |
1638 | ||
e413e4e9 AM |
1639 | demand_empty_rest_of_line (); |
1640 | } | |
1641 | ||
b9d79e03 JH |
1642 | unsigned long |
1643 | i386_mach () | |
1644 | { | |
1645 | if (!strcmp (default_arch, "x86_64")) | |
1646 | return bfd_mach_x86_64; | |
1647 | else if (!strcmp (default_arch, "i386")) | |
1648 | return bfd_mach_i386_i386; | |
1649 | else | |
1650 | as_fatal (_("Unknown architecture")); | |
1651 | } | |
b9d79e03 | 1652 | \f |
252b5132 RH |
1653 | void |
1654 | md_begin () | |
1655 | { | |
1656 | const char *hash_err; | |
1657 | ||
40fb9820 L |
1658 | cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags); |
1659 | ||
47926f60 | 1660 | /* Initialize op_hash hash table. */ |
252b5132 RH |
1661 | op_hash = hash_new (); |
1662 | ||
1663 | { | |
29b0f896 AM |
1664 | const template *optab; |
1665 | templates *core_optab; | |
252b5132 | 1666 | |
47926f60 KH |
1667 | /* Setup for loop. */ |
1668 | optab = i386_optab; | |
252b5132 RH |
1669 | core_optab = (templates *) xmalloc (sizeof (templates)); |
1670 | core_optab->start = optab; | |
1671 | ||
1672 | while (1) | |
1673 | { | |
1674 | ++optab; | |
1675 | if (optab->name == NULL | |
1676 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
1677 | { | |
1678 | /* different name --> ship out current template list; | |
47926f60 | 1679 | add to hash table; & begin anew. */ |
252b5132 RH |
1680 | core_optab->end = optab; |
1681 | hash_err = hash_insert (op_hash, | |
1682 | (optab - 1)->name, | |
1683 | (PTR) core_optab); | |
1684 | if (hash_err) | |
1685 | { | |
252b5132 RH |
1686 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
1687 | (optab - 1)->name, | |
1688 | hash_err); | |
1689 | } | |
1690 | if (optab->name == NULL) | |
1691 | break; | |
1692 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
1693 | core_optab->start = optab; | |
1694 | } | |
1695 | } | |
1696 | } | |
1697 | ||
47926f60 | 1698 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
1699 | reg_hash = hash_new (); |
1700 | { | |
29b0f896 | 1701 | const reg_entry *regtab; |
c3fe08fa | 1702 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 1703 | |
c3fe08fa | 1704 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 RH |
1705 | { |
1706 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
1707 | if (hash_err) | |
3e73aa7c JH |
1708 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
1709 | regtab->reg_name, | |
1710 | hash_err); | |
252b5132 RH |
1711 | } |
1712 | } | |
1713 | ||
47926f60 | 1714 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 1715 | { |
29b0f896 AM |
1716 | int c; |
1717 | char *p; | |
252b5132 RH |
1718 | |
1719 | for (c = 0; c < 256; c++) | |
1720 | { | |
3882b010 | 1721 | if (ISDIGIT (c)) |
252b5132 RH |
1722 | { |
1723 | digit_chars[c] = c; | |
1724 | mnemonic_chars[c] = c; | |
1725 | register_chars[c] = c; | |
1726 | operand_chars[c] = c; | |
1727 | } | |
3882b010 | 1728 | else if (ISLOWER (c)) |
252b5132 RH |
1729 | { |
1730 | mnemonic_chars[c] = c; | |
1731 | register_chars[c] = c; | |
1732 | operand_chars[c] = c; | |
1733 | } | |
3882b010 | 1734 | else if (ISUPPER (c)) |
252b5132 | 1735 | { |
3882b010 | 1736 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
1737 | register_chars[c] = mnemonic_chars[c]; |
1738 | operand_chars[c] = c; | |
1739 | } | |
1740 | ||
3882b010 | 1741 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
1742 | identifier_chars[c] = c; |
1743 | else if (c >= 128) | |
1744 | { | |
1745 | identifier_chars[c] = c; | |
1746 | operand_chars[c] = c; | |
1747 | } | |
1748 | } | |
1749 | ||
1750 | #ifdef LEX_AT | |
1751 | identifier_chars['@'] = '@'; | |
32137342 NC |
1752 | #endif |
1753 | #ifdef LEX_QM | |
1754 | identifier_chars['?'] = '?'; | |
1755 | operand_chars['?'] = '?'; | |
252b5132 | 1756 | #endif |
252b5132 | 1757 | digit_chars['-'] = '-'; |
791fe849 | 1758 | mnemonic_chars['-'] = '-'; |
0003779b | 1759 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
1760 | identifier_chars['_'] = '_'; |
1761 | identifier_chars['.'] = '.'; | |
1762 | ||
1763 | for (p = operand_special_chars; *p != '\0'; p++) | |
1764 | operand_chars[(unsigned char) *p] = *p; | |
1765 | } | |
1766 | ||
1767 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 1768 | if (IS_ELF) |
252b5132 RH |
1769 | { |
1770 | record_alignment (text_section, 2); | |
1771 | record_alignment (data_section, 2); | |
1772 | record_alignment (bss_section, 2); | |
1773 | } | |
1774 | #endif | |
a4447b93 RH |
1775 | |
1776 | if (flag_code == CODE_64BIT) | |
1777 | { | |
1778 | x86_dwarf2_return_column = 16; | |
1779 | x86_cie_data_alignment = -8; | |
1780 | } | |
1781 | else | |
1782 | { | |
1783 | x86_dwarf2_return_column = 8; | |
1784 | x86_cie_data_alignment = -4; | |
1785 | } | |
252b5132 RH |
1786 | } |
1787 | ||
1788 | void | |
e3bb37b5 | 1789 | i386_print_statistics (FILE *file) |
252b5132 RH |
1790 | { |
1791 | hash_print_statistics (file, "i386 opcode", op_hash); | |
1792 | hash_print_statistics (file, "i386 register", reg_hash); | |
1793 | } | |
1794 | \f | |
252b5132 RH |
1795 | #ifdef DEBUG386 |
1796 | ||
ce8a8b2f | 1797 | /* Debugging routines for md_assemble. */ |
e3bb37b5 | 1798 | static void pte (template *); |
40fb9820 | 1799 | static void pt (i386_operand_type); |
e3bb37b5 L |
1800 | static void pe (expressionS *); |
1801 | static void ps (symbolS *); | |
252b5132 RH |
1802 | |
1803 | static void | |
e3bb37b5 | 1804 | pi (char *line, i386_insn *x) |
252b5132 | 1805 | { |
09f131f2 | 1806 | unsigned int i; |
252b5132 RH |
1807 | |
1808 | fprintf (stdout, "%s: template ", line); | |
1809 | pte (&x->tm); | |
09f131f2 JH |
1810 | fprintf (stdout, " address: base %s index %s scale %x\n", |
1811 | x->base_reg ? x->base_reg->reg_name : "none", | |
1812 | x->index_reg ? x->index_reg->reg_name : "none", | |
1813 | x->log2_scale_factor); | |
1814 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 1815 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
1816 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
1817 | x->sib.base, x->sib.index, x->sib.scale); | |
1818 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
1819 | (x->rex & REX_W) != 0, |
1820 | (x->rex & REX_R) != 0, | |
1821 | (x->rex & REX_X) != 0, | |
1822 | (x->rex & REX_B) != 0); | |
85f10a01 MM |
1823 | fprintf (stdout, " drex: reg %d rex 0x%x\n", |
1824 | x->drex.reg, x->drex.rex); | |
252b5132 RH |
1825 | for (i = 0; i < x->operands; i++) |
1826 | { | |
1827 | fprintf (stdout, " #%d: ", i + 1); | |
1828 | pt (x->types[i]); | |
1829 | fprintf (stdout, "\n"); | |
40fb9820 L |
1830 | if (x->types[i].bitfield.reg8 |
1831 | || x->types[i].bitfield.reg16 | |
1832 | || x->types[i].bitfield.reg32 | |
1833 | || x->types[i].bitfield.reg64 | |
1834 | || x->types[i].bitfield.regmmx | |
1835 | || x->types[i].bitfield.regxmm | |
1836 | || x->types[i].bitfield.sreg2 | |
1837 | || x->types[i].bitfield.sreg3 | |
1838 | || x->types[i].bitfield.control | |
1839 | || x->types[i].bitfield.debug | |
1840 | || x->types[i].bitfield.test) | |
520dc8e8 | 1841 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
40fb9820 | 1842 | if (operand_type_check (x->types[i], imm)) |
520dc8e8 | 1843 | pe (x->op[i].imms); |
40fb9820 | 1844 | if (operand_type_check (x->types[i], disp)) |
520dc8e8 | 1845 | pe (x->op[i].disps); |
252b5132 RH |
1846 | } |
1847 | } | |
1848 | ||
1849 | static void | |
e3bb37b5 | 1850 | pte (template *t) |
252b5132 | 1851 | { |
09f131f2 | 1852 | unsigned int i; |
252b5132 | 1853 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1854 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1855 | if (t->extension_opcode != None) |
1856 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 1857 | if (t->opcode_modifier.d) |
252b5132 | 1858 | fprintf (stdout, "D"); |
40fb9820 | 1859 | if (t->opcode_modifier.w) |
252b5132 RH |
1860 | fprintf (stdout, "W"); |
1861 | fprintf (stdout, "\n"); | |
1862 | for (i = 0; i < t->operands; i++) | |
1863 | { | |
1864 | fprintf (stdout, " #%d type ", i + 1); | |
1865 | pt (t->operand_types[i]); | |
1866 | fprintf (stdout, "\n"); | |
1867 | } | |
1868 | } | |
1869 | ||
1870 | static void | |
e3bb37b5 | 1871 | pe (expressionS *e) |
252b5132 | 1872 | { |
24eab124 | 1873 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1874 | fprintf (stdout, " add_number %ld (%lx)\n", |
1875 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1876 | if (e->X_add_symbol) |
1877 | { | |
1878 | fprintf (stdout, " add_symbol "); | |
1879 | ps (e->X_add_symbol); | |
1880 | fprintf (stdout, "\n"); | |
1881 | } | |
1882 | if (e->X_op_symbol) | |
1883 | { | |
1884 | fprintf (stdout, " op_symbol "); | |
1885 | ps (e->X_op_symbol); | |
1886 | fprintf (stdout, "\n"); | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | static void | |
e3bb37b5 | 1891 | ps (symbolS *s) |
252b5132 RH |
1892 | { |
1893 | fprintf (stdout, "%s type %s%s", | |
1894 | S_GET_NAME (s), | |
1895 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1896 | segment_name (S_GET_SEGMENT (s))); | |
1897 | } | |
1898 | ||
7b81dfbb | 1899 | static struct type_name |
252b5132 | 1900 | { |
40fb9820 L |
1901 | i386_operand_type mask; |
1902 | const char *name; | |
252b5132 | 1903 | } |
7b81dfbb | 1904 | const type_names[] = |
252b5132 | 1905 | { |
40fb9820 L |
1906 | { OPERAND_TYPE_REG8, "r8" }, |
1907 | { OPERAND_TYPE_REG16, "r16" }, | |
1908 | { OPERAND_TYPE_REG32, "r32" }, | |
1909 | { OPERAND_TYPE_REG64, "r64" }, | |
1910 | { OPERAND_TYPE_IMM8, "i8" }, | |
1911 | { OPERAND_TYPE_IMM8, "i8s" }, | |
1912 | { OPERAND_TYPE_IMM16, "i16" }, | |
1913 | { OPERAND_TYPE_IMM32, "i32" }, | |
1914 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
1915 | { OPERAND_TYPE_IMM64, "i64" }, | |
1916 | { OPERAND_TYPE_IMM1, "i1" }, | |
1917 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
1918 | { OPERAND_TYPE_DISP8, "d8" }, | |
1919 | { OPERAND_TYPE_DISP16, "d16" }, | |
1920 | { OPERAND_TYPE_DISP32, "d32" }, | |
1921 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
1922 | { OPERAND_TYPE_DISP64, "d64" }, | |
1923 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
1924 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
1925 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
1926 | { OPERAND_TYPE_TEST, "test reg" }, | |
1927 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
1928 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
1929 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
1930 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
1931 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
1932 | { OPERAND_TYPE_ACC, "Acc" }, | |
1933 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
1934 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
1935 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
1936 | { OPERAND_TYPE_ESSEG, "es" }, | |
252b5132 RH |
1937 | }; |
1938 | ||
1939 | static void | |
40fb9820 | 1940 | pt (i386_operand_type t) |
252b5132 | 1941 | { |
40fb9820 | 1942 | unsigned int j; |
c6fb90c8 | 1943 | i386_operand_type a; |
252b5132 | 1944 | |
40fb9820 | 1945 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
1946 | { |
1947 | a = operand_type_and (t, type_names[j].mask); | |
1948 | if (!UINTS_ALL_ZERO (a)) | |
1949 | fprintf (stdout, "%s, ", type_names[j].name); | |
1950 | } | |
252b5132 RH |
1951 | fflush (stdout); |
1952 | } | |
1953 | ||
1954 | #endif /* DEBUG386 */ | |
1955 | \f | |
252b5132 | 1956 | static bfd_reloc_code_real_type |
3956db08 | 1957 | reloc (unsigned int size, |
64e74474 AM |
1958 | int pcrel, |
1959 | int sign, | |
1960 | bfd_reloc_code_real_type other) | |
252b5132 | 1961 | { |
47926f60 | 1962 | if (other != NO_RELOC) |
3956db08 JB |
1963 | { |
1964 | reloc_howto_type *reloc; | |
1965 | ||
1966 | if (size == 8) | |
1967 | switch (other) | |
1968 | { | |
64e74474 AM |
1969 | case BFD_RELOC_X86_64_GOT32: |
1970 | return BFD_RELOC_X86_64_GOT64; | |
1971 | break; | |
1972 | case BFD_RELOC_X86_64_PLTOFF64: | |
1973 | return BFD_RELOC_X86_64_PLTOFF64; | |
1974 | break; | |
1975 | case BFD_RELOC_X86_64_GOTPC32: | |
1976 | other = BFD_RELOC_X86_64_GOTPC64; | |
1977 | break; | |
1978 | case BFD_RELOC_X86_64_GOTPCREL: | |
1979 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
1980 | break; | |
1981 | case BFD_RELOC_X86_64_TPOFF32: | |
1982 | other = BFD_RELOC_X86_64_TPOFF64; | |
1983 | break; | |
1984 | case BFD_RELOC_X86_64_DTPOFF32: | |
1985 | other = BFD_RELOC_X86_64_DTPOFF64; | |
1986 | break; | |
1987 | default: | |
1988 | break; | |
3956db08 | 1989 | } |
e05278af JB |
1990 | |
1991 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
1992 | if (size == 4 && flag_code != CODE_64BIT) | |
1993 | sign = -1; | |
1994 | ||
3956db08 JB |
1995 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
1996 | if (!reloc) | |
1997 | as_bad (_("unknown relocation (%u)"), other); | |
1998 | else if (size != bfd_get_reloc_size (reloc)) | |
1999 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
2000 | bfd_get_reloc_size (reloc), | |
2001 | size); | |
2002 | else if (pcrel && !reloc->pc_relative) | |
2003 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
2004 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
2005 | && !sign) | |
2006 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 2007 | && sign > 0)) |
3956db08 JB |
2008 | as_bad (_("relocated field and relocation type differ in signedness")); |
2009 | else | |
2010 | return other; | |
2011 | return NO_RELOC; | |
2012 | } | |
252b5132 RH |
2013 | |
2014 | if (pcrel) | |
2015 | { | |
3e73aa7c | 2016 | if (!sign) |
3956db08 | 2017 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2018 | switch (size) |
2019 | { | |
2020 | case 1: return BFD_RELOC_8_PCREL; | |
2021 | case 2: return BFD_RELOC_16_PCREL; | |
2022 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2023 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2024 | } |
3956db08 | 2025 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2026 | } |
2027 | else | |
2028 | { | |
3956db08 | 2029 | if (sign > 0) |
e5cb08ac | 2030 | switch (size) |
3e73aa7c JH |
2031 | { |
2032 | case 4: return BFD_RELOC_X86_64_32S; | |
2033 | } | |
2034 | else | |
2035 | switch (size) | |
2036 | { | |
2037 | case 1: return BFD_RELOC_8; | |
2038 | case 2: return BFD_RELOC_16; | |
2039 | case 4: return BFD_RELOC_32; | |
2040 | case 8: return BFD_RELOC_64; | |
2041 | } | |
3956db08 JB |
2042 | as_bad (_("cannot do %s %u byte relocation"), |
2043 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2044 | } |
2045 | ||
bfb32b52 | 2046 | abort (); |
252b5132 RH |
2047 | return BFD_RELOC_NONE; |
2048 | } | |
2049 | ||
47926f60 KH |
2050 | /* Here we decide which fixups can be adjusted to make them relative to |
2051 | the beginning of the section instead of the symbol. Basically we need | |
2052 | to make sure that the dynamic relocations are done correctly, so in | |
2053 | some cases we force the original symbol to be used. */ | |
2054 | ||
252b5132 | 2055 | int |
e3bb37b5 | 2056 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2057 | { |
6d249963 | 2058 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2059 | if (!IS_ELF) |
31312f95 AM |
2060 | return 1; |
2061 | ||
a161fe53 AM |
2062 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2063 | mode. */ | |
2064 | if (use_rela_relocations | |
2065 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2066 | && fixP->fx_pcrel) | |
252b5132 | 2067 | return 0; |
31312f95 | 2068 | |
8d01d9a9 AJ |
2069 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2070 | and changed later by validate_fix. */ | |
2071 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2072 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2073 | return 0; | |
2074 | ||
ce8a8b2f | 2075 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2076 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2077 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2078 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2079 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2080 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2081 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2082 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2083 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2084 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2085 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2086 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2087 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2088 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2089 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2090 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2091 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2092 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2093 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2094 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2095 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2096 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2097 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2098 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2099 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2100 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2101 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2102 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2103 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2104 | return 0; | |
31312f95 | 2105 | #endif |
252b5132 RH |
2106 | return 1; |
2107 | } | |
252b5132 | 2108 | |
b4cac588 | 2109 | static int |
e3bb37b5 | 2110 | intel_float_operand (const char *mnemonic) |
252b5132 | 2111 | { |
9306ca4a JB |
2112 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2113 | operands, hence the code here is free to improperly handle opcodes that | |
2114 | have no operands (for better performance and smaller code). */ | |
2115 | ||
2116 | if (mnemonic[0] != 'f') | |
2117 | return 0; /* non-math */ | |
2118 | ||
2119 | switch (mnemonic[1]) | |
2120 | { | |
2121 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2122 | the fs segment override prefix not currently handled because no | |
2123 | call path can make opcodes without operands get here */ | |
2124 | case 'i': | |
2125 | return 2 /* integer op */; | |
2126 | case 'l': | |
2127 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2128 | return 3; /* fldcw/fldenv */ | |
2129 | break; | |
2130 | case 'n': | |
2131 | if (mnemonic[2] != 'o' /* fnop */) | |
2132 | return 3; /* non-waiting control op */ | |
2133 | break; | |
2134 | case 'r': | |
2135 | if (mnemonic[2] == 's') | |
2136 | return 3; /* frstor/frstpm */ | |
2137 | break; | |
2138 | case 's': | |
2139 | if (mnemonic[2] == 'a') | |
2140 | return 3; /* fsave */ | |
2141 | if (mnemonic[2] == 't') | |
2142 | { | |
2143 | switch (mnemonic[3]) | |
2144 | { | |
2145 | case 'c': /* fstcw */ | |
2146 | case 'd': /* fstdw */ | |
2147 | case 'e': /* fstenv */ | |
2148 | case 's': /* fsts[gw] */ | |
2149 | return 3; | |
2150 | } | |
2151 | } | |
2152 | break; | |
2153 | case 'x': | |
2154 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2155 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2156 | break; | |
2157 | } | |
252b5132 | 2158 | |
9306ca4a | 2159 | return 1; |
252b5132 RH |
2160 | } |
2161 | ||
2162 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
2163 | machine dependent instruction. This function is supposed to emit | |
2164 | the frags/bytes it assembles to. */ | |
2165 | ||
2166 | void | |
2167 | md_assemble (line) | |
2168 | char *line; | |
2169 | { | |
40fb9820 | 2170 | unsigned int j; |
252b5132 RH |
2171 | char mnemonic[MAX_MNEM_SIZE]; |
2172 | ||
47926f60 | 2173 | /* Initialize globals. */ |
252b5132 RH |
2174 | memset (&i, '\0', sizeof (i)); |
2175 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2176 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2177 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2178 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2179 | save_stack_p = save_stack; |
252b5132 RH |
2180 | |
2181 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2182 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2183 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2184 | |
29b0f896 AM |
2185 | line = parse_insn (line, mnemonic); |
2186 | if (line == NULL) | |
2187 | return; | |
252b5132 | 2188 | |
29b0f896 AM |
2189 | line = parse_operands (line, mnemonic); |
2190 | if (line == NULL) | |
2191 | return; | |
252b5132 | 2192 | |
29b0f896 AM |
2193 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2194 | operands at hand. */ | |
2195 | ||
2196 | /* All intel opcodes have reversed operands except for "bound" and | |
2197 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2198 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2199 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2200 | if (intel_syntax |
2201 | && i.operands > 1 | |
29b0f896 | 2202 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2203 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
2204 | && !(operand_type_check (i.types[0], imm) |
2205 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
2206 | swap_operands (); |
2207 | ||
ec56d5c0 JB |
2208 | /* The order of the immediates should be reversed |
2209 | for 2 immediates extrq and insertq instructions */ | |
2210 | if (i.imm_operands == 2 | |
2211 | && (strcmp (mnemonic, "extrq") == 0 | |
2212 | || strcmp (mnemonic, "insertq") == 0)) | |
2213 | swap_2_operands (0, 1); | |
2214 | ||
29b0f896 AM |
2215 | if (i.imm_operands) |
2216 | optimize_imm (); | |
2217 | ||
b300c311 L |
2218 | /* Don't optimize displacement for movabs since it only takes 64bit |
2219 | displacement. */ | |
2220 | if (i.disp_operands | |
2221 | && (flag_code != CODE_64BIT | |
2222 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
2223 | optimize_disp (); |
2224 | ||
2225 | /* Next, we find a template that matches the given insn, | |
2226 | making sure the overlap of the given operands types is consistent | |
2227 | with the template operand types. */ | |
252b5132 | 2228 | |
29b0f896 AM |
2229 | if (!match_template ()) |
2230 | return; | |
252b5132 | 2231 | |
cd61ebfe AM |
2232 | if (intel_syntax) |
2233 | { | |
2234 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ | |
2235 | if (SYSV386_COMPAT | |
2236 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
8a2ed489 | 2237 | i.tm.base_opcode ^= Opcode_FloatR; |
cd61ebfe AM |
2238 | |
2239 | /* Zap movzx and movsx suffix. The suffix may have been set from | |
2240 | "word ptr" or "byte ptr" on the source operand, but we'll use | |
2241 | the suffix later to choose the destination register. */ | |
2242 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
9306ca4a JB |
2243 | { |
2244 | if (i.reg_operands < 2 | |
2245 | && !i.suffix | |
40fb9820 L |
2246 | && (!i.tm.opcode_modifier.no_bsuf |
2247 | || !i.tm.opcode_modifier.no_wsuf | |
2248 | || !i.tm.opcode_modifier.no_lsuf | |
2249 | || !i.tm.opcode_modifier.no_ssuf | |
7ce189b3 | 2250 | || !i.tm.opcode_modifier.no_ldsuf |
40fb9820 | 2251 | || !i.tm.opcode_modifier.no_qsuf)) |
9306ca4a JB |
2252 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
2253 | ||
2254 | i.suffix = 0; | |
2255 | } | |
cd61ebfe | 2256 | } |
24eab124 | 2257 | |
40fb9820 | 2258 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
2259 | if (!add_prefix (FWAIT_OPCODE)) |
2260 | return; | |
252b5132 | 2261 | |
29b0f896 | 2262 | /* Check string instruction segment overrides. */ |
40fb9820 | 2263 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
2264 | { |
2265 | if (!check_string ()) | |
5dd0794d | 2266 | return; |
29b0f896 | 2267 | } |
5dd0794d | 2268 | |
29b0f896 AM |
2269 | if (!process_suffix ()) |
2270 | return; | |
e413e4e9 | 2271 | |
29b0f896 AM |
2272 | /* Make still unresolved immediate matches conform to size of immediate |
2273 | given in i.suffix. */ | |
2274 | if (!finalize_imm ()) | |
2275 | return; | |
252b5132 | 2276 | |
40fb9820 | 2277 | if (i.types[0].bitfield.imm1) |
29b0f896 | 2278 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 2279 | |
40fb9820 | 2280 | for (j = 0; j < 3; j++) |
c6fb90c8 L |
2281 | if (i.types[j].bitfield.inoutportreg |
2282 | || i.types[j].bitfield.shiftcount | |
2283 | || i.types[j].bitfield.acc | |
2284 | || i.types[j].bitfield.floatacc) | |
40fb9820 L |
2285 | i.reg_operands--; |
2286 | ||
2287 | if (i.tm.opcode_modifier.immext) | |
29b0f896 | 2288 | { |
02fc3089 L |
2289 | expressionS *exp; |
2290 | ||
40fb9820 | 2291 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) |
ca164297 | 2292 | { |
b7d9ef37 | 2293 | /* Streaming SIMD extensions 3 Instructions have the fixed |
ca164297 L |
2294 | operands with an opcode suffix which is coded in the same |
2295 | place as an 8-bit immediate field would be. Here we check | |
2296 | those operands and remove them afterwards. */ | |
2297 | unsigned int x; | |
2298 | ||
a4622f40 | 2299 | for (x = 0; x < i.operands; x++) |
ca164297 | 2300 | if (i.op[x].regs->reg_num != x) |
a540244d L |
2301 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
2302 | register_prefix, | |
2303 | i.op[x].regs->reg_name, | |
2304 | x + 1, | |
2305 | i.tm.name); | |
ca164297 L |
2306 | i.operands = 0; |
2307 | } | |
2308 | ||
29b0f896 AM |
2309 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
2310 | opcode suffix which is coded in the same place as an 8-bit | |
2311 | immediate field would be. Here we fake an 8-bit immediate | |
85f10a01 MM |
2312 | operand from the opcode suffix stored in tm.extension_opcode. |
2313 | SSE5 also uses this encoding, for some of its 3 argument | |
2314 | instructions. */ | |
252b5132 | 2315 | |
85f10a01 MM |
2316 | assert (i.imm_operands == 0 |
2317 | && (i.operands <= 2 | |
2318 | || (i.tm.cpu_flags.bitfield.cpusse5 | |
2319 | && i.operands <= 3))); | |
252b5132 | 2320 | |
29b0f896 AM |
2321 | exp = &im_expressions[i.imm_operands++]; |
2322 | i.op[i.operands].imms = exp; | |
c6fb90c8 | 2323 | UINTS_CLEAR (i.types[i.operands]); |
40fb9820 L |
2324 | i.types[i.operands].bitfield.imm8 = 1; |
2325 | i.operands++; | |
29b0f896 AM |
2326 | exp->X_op = O_constant; |
2327 | exp->X_add_number = i.tm.extension_opcode; | |
2328 | i.tm.extension_opcode = None; | |
2329 | } | |
252b5132 | 2330 | |
29b0f896 AM |
2331 | /* For insns with operands there are more diddles to do to the opcode. */ |
2332 | if (i.operands) | |
2333 | { | |
2334 | if (!process_operands ()) | |
2335 | return; | |
2336 | } | |
40fb9820 | 2337 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
2338 | { |
2339 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
2340 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2341 | } | |
252b5132 | 2342 | |
29b0f896 AM |
2343 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
2344 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
2345 | { | |
2346 | i.tm.base_opcode = INT3_OPCODE; | |
2347 | i.imm_operands = 0; | |
2348 | } | |
252b5132 | 2349 | |
40fb9820 L |
2350 | if ((i.tm.opcode_modifier.jump |
2351 | || i.tm.opcode_modifier.jumpbyte | |
2352 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
2353 | && i.op[0].disps->X_op == O_constant) |
2354 | { | |
2355 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2356 | the absolute address given by the constant. Since ix86 jumps and | |
2357 | calls are pc relative, we need to generate a reloc. */ | |
2358 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
2359 | i.op[0].disps->X_op = O_symbol; | |
2360 | } | |
252b5132 | 2361 | |
40fb9820 | 2362 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 2363 | i.rex |= REX_W; |
252b5132 | 2364 | |
29b0f896 AM |
2365 | /* For 8 bit registers we need an empty rex prefix. Also if the |
2366 | instruction already has a prefix, we need to convert old | |
2367 | registers to new ones. */ | |
773f551c | 2368 | |
40fb9820 | 2369 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 2370 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 2371 | || (i.types[1].bitfield.reg8 |
29b0f896 | 2372 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
2373 | || ((i.types[0].bitfield.reg8 |
2374 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
2375 | && i.rex != 0)) |
2376 | { | |
2377 | int x; | |
726c5dcd | 2378 | |
29b0f896 AM |
2379 | i.rex |= REX_OPCODE; |
2380 | for (x = 0; x < 2; x++) | |
2381 | { | |
2382 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 2383 | if (i.types[x].bitfield.reg8 |
29b0f896 | 2384 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 2385 | { |
29b0f896 AM |
2386 | /* In case it is "hi" register, give up. */ |
2387 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 2388 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 2389 | "instruction requiring REX prefix."), |
a540244d | 2390 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 2391 | |
29b0f896 AM |
2392 | /* Otherwise it is equivalent to the extended register. |
2393 | Since the encoding doesn't change this is merely | |
2394 | cosmetic cleanup for debug output. */ | |
2395 | ||
2396 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 2397 | } |
29b0f896 AM |
2398 | } |
2399 | } | |
773f551c | 2400 | |
85f10a01 MM |
2401 | /* If the instruction has the DREX attribute (aka SSE5), don't emit a |
2402 | REX prefix. */ | |
2403 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
2404 | { | |
2405 | i.drex.rex = i.rex; | |
2406 | i.rex = 0; | |
2407 | } | |
2408 | else if (i.rex != 0) | |
29b0f896 AM |
2409 | add_prefix (REX_OPCODE | i.rex); |
2410 | ||
2411 | /* We are ready to output the insn. */ | |
2412 | output_insn (); | |
2413 | } | |
2414 | ||
2415 | static char * | |
e3bb37b5 | 2416 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
2417 | { |
2418 | char *l = line; | |
2419 | char *token_start = l; | |
2420 | char *mnem_p; | |
5c6af06e JB |
2421 | int supported; |
2422 | const template *t; | |
29b0f896 AM |
2423 | |
2424 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
2425 | const char *expecting_string_instruction = NULL; | |
45288df1 | 2426 | |
29b0f896 AM |
2427 | while (1) |
2428 | { | |
2429 | mnem_p = mnemonic; | |
2430 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
2431 | { | |
2432 | mnem_p++; | |
2433 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 2434 | { |
29b0f896 AM |
2435 | as_bad (_("no such instruction: `%s'"), token_start); |
2436 | return NULL; | |
2437 | } | |
2438 | l++; | |
2439 | } | |
2440 | if (!is_space_char (*l) | |
2441 | && *l != END_OF_INSN | |
e44823cf JB |
2442 | && (intel_syntax |
2443 | || (*l != PREFIX_SEPARATOR | |
2444 | && *l != ','))) | |
29b0f896 AM |
2445 | { |
2446 | as_bad (_("invalid character %s in mnemonic"), | |
2447 | output_invalid (*l)); | |
2448 | return NULL; | |
2449 | } | |
2450 | if (token_start == l) | |
2451 | { | |
e44823cf | 2452 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
2453 | as_bad (_("expecting prefix; got nothing")); |
2454 | else | |
2455 | as_bad (_("expecting mnemonic; got nothing")); | |
2456 | return NULL; | |
2457 | } | |
45288df1 | 2458 | |
29b0f896 AM |
2459 | /* Look up instruction (or prefix) via hash table. */ |
2460 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 2461 | |
29b0f896 AM |
2462 | if (*l != END_OF_INSN |
2463 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
2464 | && current_templates | |
40fb9820 | 2465 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 2466 | { |
c6fb90c8 | 2467 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
2468 | { |
2469 | as_bad ((flag_code != CODE_64BIT | |
2470 | ? _("`%s' is only supported in 64-bit mode") | |
2471 | : _("`%s' is not supported in 64-bit mode")), | |
2472 | current_templates->start->name); | |
2473 | return NULL; | |
2474 | } | |
29b0f896 AM |
2475 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
2476 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
2477 | if ((current_templates->start->opcode_modifier.size16 |
2478 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 2479 | && flag_code != CODE_64BIT |
40fb9820 | 2480 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
2481 | ^ (flag_code == CODE_16BIT))) |
2482 | { | |
2483 | as_bad (_("redundant %s prefix"), | |
2484 | current_templates->start->name); | |
2485 | return NULL; | |
45288df1 | 2486 | } |
29b0f896 AM |
2487 | /* Add prefix, checking for repeated prefixes. */ |
2488 | switch (add_prefix (current_templates->start->base_opcode)) | |
2489 | { | |
2490 | case 0: | |
2491 | return NULL; | |
2492 | case 2: | |
2493 | expecting_string_instruction = current_templates->start->name; | |
2494 | break; | |
2495 | } | |
2496 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
2497 | token_start = ++l; | |
2498 | } | |
2499 | else | |
2500 | break; | |
2501 | } | |
45288df1 | 2502 | |
29b0f896 AM |
2503 | if (!current_templates) |
2504 | { | |
2505 | /* See if we can get a match by trimming off a suffix. */ | |
2506 | switch (mnem_p[-1]) | |
2507 | { | |
2508 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
2509 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
2510 | i.suffix = SHORT_MNEM_SUFFIX; | |
2511 | else | |
29b0f896 AM |
2512 | case BYTE_MNEM_SUFFIX: |
2513 | case QWORD_MNEM_SUFFIX: | |
2514 | i.suffix = mnem_p[-1]; | |
2515 | mnem_p[-1] = '\0'; | |
2516 | current_templates = hash_find (op_hash, mnemonic); | |
2517 | break; | |
2518 | case SHORT_MNEM_SUFFIX: | |
2519 | case LONG_MNEM_SUFFIX: | |
2520 | if (!intel_syntax) | |
2521 | { | |
2522 | i.suffix = mnem_p[-1]; | |
2523 | mnem_p[-1] = '\0'; | |
2524 | current_templates = hash_find (op_hash, mnemonic); | |
2525 | } | |
2526 | break; | |
252b5132 | 2527 | |
29b0f896 AM |
2528 | /* Intel Syntax. */ |
2529 | case 'd': | |
2530 | if (intel_syntax) | |
2531 | { | |
9306ca4a | 2532 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
2533 | i.suffix = SHORT_MNEM_SUFFIX; |
2534 | else | |
2535 | i.suffix = LONG_MNEM_SUFFIX; | |
2536 | mnem_p[-1] = '\0'; | |
2537 | current_templates = hash_find (op_hash, mnemonic); | |
2538 | } | |
2539 | break; | |
2540 | } | |
2541 | if (!current_templates) | |
2542 | { | |
2543 | as_bad (_("no such instruction: `%s'"), token_start); | |
2544 | return NULL; | |
2545 | } | |
2546 | } | |
252b5132 | 2547 | |
40fb9820 L |
2548 | if (current_templates->start->opcode_modifier.jump |
2549 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
2550 | { |
2551 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
2552 | predict taken and predict not taken respectively. | |
2553 | I'm not sure that branch hints actually do anything on loop | |
2554 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
2555 | may work in the future and it doesn't hurt to accept them | |
2556 | now. */ | |
2557 | if (l[0] == ',' && l[1] == 'p') | |
2558 | { | |
2559 | if (l[2] == 't') | |
2560 | { | |
2561 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
2562 | return NULL; | |
2563 | l += 3; | |
2564 | } | |
2565 | else if (l[2] == 'n') | |
2566 | { | |
2567 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
2568 | return NULL; | |
2569 | l += 3; | |
2570 | } | |
2571 | } | |
2572 | } | |
2573 | /* Any other comma loses. */ | |
2574 | if (*l == ',') | |
2575 | { | |
2576 | as_bad (_("invalid character %s in mnemonic"), | |
2577 | output_invalid (*l)); | |
2578 | return NULL; | |
2579 | } | |
252b5132 | 2580 | |
29b0f896 | 2581 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
2582 | supported = 0; |
2583 | for (t = current_templates->start; t < current_templates->end; ++t) | |
2584 | { | |
40fb9820 | 2585 | if (cpu_flags_match (t->cpu_flags)) |
64e74474 | 2586 | supported |= 1; |
c6fb90c8 | 2587 | if (cpu_flags_check_cpu64 (t->cpu_flags)) |
64e74474 | 2588 | supported |= 2; |
5c6af06e JB |
2589 | } |
2590 | if (!(supported & 2)) | |
2591 | { | |
2592 | as_bad (flag_code == CODE_64BIT | |
2593 | ? _("`%s' is not supported in 64-bit mode") | |
2594 | : _("`%s' is only supported in 64-bit mode"), | |
2595 | current_templates->start->name); | |
2596 | return NULL; | |
2597 | } | |
2598 | if (!(supported & 1)) | |
29b0f896 | 2599 | { |
5c6af06e JB |
2600 | as_warn (_("`%s' is not supported on `%s%s'"), |
2601 | current_templates->start->name, | |
2602 | cpu_arch_name, | |
2603 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
29b0f896 | 2604 | } |
40fb9820 L |
2605 | else if (!cpu_arch_flags.bitfield.cpui386 |
2606 | && (flag_code != CODE_16BIT)) | |
29b0f896 AM |
2607 | { |
2608 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
2609 | } | |
252b5132 | 2610 | |
29b0f896 | 2611 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 2612 | if (expecting_string_instruction) |
29b0f896 | 2613 | { |
f41bbced JB |
2614 | static templates override; |
2615 | ||
2616 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 2617 | if (t->opcode_modifier.isstring) |
f41bbced JB |
2618 | break; |
2619 | if (t >= current_templates->end) | |
2620 | { | |
2621 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 2622 | expecting_string_instruction); |
f41bbced JB |
2623 | return NULL; |
2624 | } | |
2625 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 2626 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
2627 | break; |
2628 | override.end = t; | |
2629 | current_templates = &override; | |
29b0f896 | 2630 | } |
252b5132 | 2631 | |
29b0f896 AM |
2632 | return l; |
2633 | } | |
252b5132 | 2634 | |
29b0f896 | 2635 | static char * |
e3bb37b5 | 2636 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
2637 | { |
2638 | char *token_start; | |
3138f287 | 2639 | |
29b0f896 AM |
2640 | /* 1 if operand is pending after ','. */ |
2641 | unsigned int expecting_operand = 0; | |
252b5132 | 2642 | |
29b0f896 AM |
2643 | /* Non-zero if operand parens not balanced. */ |
2644 | unsigned int paren_not_balanced; | |
2645 | ||
2646 | while (*l != END_OF_INSN) | |
2647 | { | |
2648 | /* Skip optional white space before operand. */ | |
2649 | if (is_space_char (*l)) | |
2650 | ++l; | |
2651 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
2652 | { | |
2653 | as_bad (_("invalid character %s before operand %d"), | |
2654 | output_invalid (*l), | |
2655 | i.operands + 1); | |
2656 | return NULL; | |
2657 | } | |
2658 | token_start = l; /* after white space */ | |
2659 | paren_not_balanced = 0; | |
2660 | while (paren_not_balanced || *l != ',') | |
2661 | { | |
2662 | if (*l == END_OF_INSN) | |
2663 | { | |
2664 | if (paren_not_balanced) | |
2665 | { | |
2666 | if (!intel_syntax) | |
2667 | as_bad (_("unbalanced parenthesis in operand %d."), | |
2668 | i.operands + 1); | |
2669 | else | |
2670 | as_bad (_("unbalanced brackets in operand %d."), | |
2671 | i.operands + 1); | |
2672 | return NULL; | |
2673 | } | |
2674 | else | |
2675 | break; /* we are done */ | |
2676 | } | |
2677 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
2678 | { | |
2679 | as_bad (_("invalid character %s in operand %d"), | |
2680 | output_invalid (*l), | |
2681 | i.operands + 1); | |
2682 | return NULL; | |
2683 | } | |
2684 | if (!intel_syntax) | |
2685 | { | |
2686 | if (*l == '(') | |
2687 | ++paren_not_balanced; | |
2688 | if (*l == ')') | |
2689 | --paren_not_balanced; | |
2690 | } | |
2691 | else | |
2692 | { | |
2693 | if (*l == '[') | |
2694 | ++paren_not_balanced; | |
2695 | if (*l == ']') | |
2696 | --paren_not_balanced; | |
2697 | } | |
2698 | l++; | |
2699 | } | |
2700 | if (l != token_start) | |
2701 | { /* Yes, we've read in another operand. */ | |
2702 | unsigned int operand_ok; | |
2703 | this_operand = i.operands++; | |
2704 | if (i.operands > MAX_OPERANDS) | |
2705 | { | |
2706 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
2707 | MAX_OPERANDS); | |
2708 | return NULL; | |
2709 | } | |
2710 | /* Now parse operand adding info to 'i' as we go along. */ | |
2711 | END_STRING_AND_SAVE (l); | |
2712 | ||
2713 | if (intel_syntax) | |
2714 | operand_ok = | |
2715 | i386_intel_operand (token_start, | |
2716 | intel_float_operand (mnemonic)); | |
2717 | else | |
2718 | operand_ok = i386_operand (token_start); | |
2719 | ||
2720 | RESTORE_END_STRING (l); | |
2721 | if (!operand_ok) | |
2722 | return NULL; | |
2723 | } | |
2724 | else | |
2725 | { | |
2726 | if (expecting_operand) | |
2727 | { | |
2728 | expecting_operand_after_comma: | |
2729 | as_bad (_("expecting operand after ','; got nothing")); | |
2730 | return NULL; | |
2731 | } | |
2732 | if (*l == ',') | |
2733 | { | |
2734 | as_bad (_("expecting operand before ','; got nothing")); | |
2735 | return NULL; | |
2736 | } | |
2737 | } | |
7f3f1ea2 | 2738 | |
29b0f896 AM |
2739 | /* Now *l must be either ',' or END_OF_INSN. */ |
2740 | if (*l == ',') | |
2741 | { | |
2742 | if (*++l == END_OF_INSN) | |
2743 | { | |
2744 | /* Just skip it, if it's \n complain. */ | |
2745 | goto expecting_operand_after_comma; | |
2746 | } | |
2747 | expecting_operand = 1; | |
2748 | } | |
2749 | } | |
2750 | return l; | |
2751 | } | |
7f3f1ea2 | 2752 | |
050dfa73 | 2753 | static void |
4d456e3d | 2754 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
2755 | { |
2756 | union i386_op temp_op; | |
40fb9820 | 2757 | i386_operand_type temp_type; |
050dfa73 | 2758 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 2759 | |
050dfa73 MM |
2760 | temp_type = i.types[xchg2]; |
2761 | i.types[xchg2] = i.types[xchg1]; | |
2762 | i.types[xchg1] = temp_type; | |
2763 | temp_op = i.op[xchg2]; | |
2764 | i.op[xchg2] = i.op[xchg1]; | |
2765 | i.op[xchg1] = temp_op; | |
2766 | temp_reloc = i.reloc[xchg2]; | |
2767 | i.reloc[xchg2] = i.reloc[xchg1]; | |
2768 | i.reloc[xchg1] = temp_reloc; | |
2769 | } | |
2770 | ||
29b0f896 | 2771 | static void |
e3bb37b5 | 2772 | swap_operands (void) |
29b0f896 | 2773 | { |
b7c61d9a | 2774 | switch (i.operands) |
050dfa73 | 2775 | { |
b7c61d9a | 2776 | case 4: |
4d456e3d | 2777 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
2778 | case 3: |
2779 | case 2: | |
4d456e3d | 2780 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
2781 | break; |
2782 | default: | |
2783 | abort (); | |
29b0f896 | 2784 | } |
29b0f896 AM |
2785 | |
2786 | if (i.mem_operands == 2) | |
2787 | { | |
2788 | const seg_entry *temp_seg; | |
2789 | temp_seg = i.seg[0]; | |
2790 | i.seg[0] = i.seg[1]; | |
2791 | i.seg[1] = temp_seg; | |
2792 | } | |
2793 | } | |
252b5132 | 2794 | |
29b0f896 AM |
2795 | /* Try to ensure constant immediates are represented in the smallest |
2796 | opcode possible. */ | |
2797 | static void | |
e3bb37b5 | 2798 | optimize_imm (void) |
29b0f896 AM |
2799 | { |
2800 | char guess_suffix = 0; | |
2801 | int op; | |
252b5132 | 2802 | |
29b0f896 AM |
2803 | if (i.suffix) |
2804 | guess_suffix = i.suffix; | |
2805 | else if (i.reg_operands) | |
2806 | { | |
2807 | /* Figure out a suffix from the last register operand specified. | |
2808 | We can't do this properly yet, ie. excluding InOutPortReg, | |
2809 | but the following works for instructions with immediates. | |
2810 | In any case, we can't set i.suffix yet. */ | |
2811 | for (op = i.operands; --op >= 0;) | |
40fb9820 L |
2812 | if (i.types[op].bitfield.reg8) |
2813 | { | |
2814 | guess_suffix = BYTE_MNEM_SUFFIX; | |
2815 | break; | |
2816 | } | |
2817 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 2818 | { |
40fb9820 L |
2819 | guess_suffix = WORD_MNEM_SUFFIX; |
2820 | break; | |
2821 | } | |
2822 | else if (i.types[op].bitfield.reg32) | |
2823 | { | |
2824 | guess_suffix = LONG_MNEM_SUFFIX; | |
2825 | break; | |
2826 | } | |
2827 | else if (i.types[op].bitfield.reg64) | |
2828 | { | |
2829 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 2830 | break; |
252b5132 | 2831 | } |
29b0f896 AM |
2832 | } |
2833 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
2834 | guess_suffix = WORD_MNEM_SUFFIX; | |
2835 | ||
2836 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 2837 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
2838 | { |
2839 | switch (i.op[op].imms->X_op) | |
252b5132 | 2840 | { |
29b0f896 AM |
2841 | case O_constant: |
2842 | /* If a suffix is given, this operand may be shortened. */ | |
2843 | switch (guess_suffix) | |
252b5132 | 2844 | { |
29b0f896 | 2845 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
2846 | i.types[op].bitfield.imm32 = 1; |
2847 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
2848 | break; |
2849 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
2850 | i.types[op].bitfield.imm16 = 1; |
2851 | i.types[op].bitfield.imm32 = 1; | |
2852 | i.types[op].bitfield.imm32s = 1; | |
2853 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
2854 | break; |
2855 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
2856 | i.types[op].bitfield.imm8 = 1; |
2857 | i.types[op].bitfield.imm8s = 1; | |
2858 | i.types[op].bitfield.imm16 = 1; | |
2859 | i.types[op].bitfield.imm32 = 1; | |
2860 | i.types[op].bitfield.imm32s = 1; | |
2861 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 2862 | break; |
252b5132 | 2863 | } |
252b5132 | 2864 | |
29b0f896 AM |
2865 | /* If this operand is at most 16 bits, convert it |
2866 | to a signed 16 bit number before trying to see | |
2867 | whether it will fit in an even smaller size. | |
2868 | This allows a 16-bit operand such as $0xffe0 to | |
2869 | be recognised as within Imm8S range. */ | |
40fb9820 | 2870 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 2871 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 2872 | { |
29b0f896 AM |
2873 | i.op[op].imms->X_add_number = |
2874 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
2875 | } | |
40fb9820 | 2876 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
2877 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
2878 | == 0)) | |
2879 | { | |
2880 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
2881 | ^ ((offsetT) 1 << 31)) | |
2882 | - ((offsetT) 1 << 31)); | |
2883 | } | |
40fb9820 | 2884 | i.types[op] |
c6fb90c8 L |
2885 | = operand_type_or (i.types[op], |
2886 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 2887 | |
29b0f896 AM |
2888 | /* We must avoid matching of Imm32 templates when 64bit |
2889 | only immediate is available. */ | |
2890 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 2891 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 2892 | break; |
252b5132 | 2893 | |
29b0f896 AM |
2894 | case O_absent: |
2895 | case O_register: | |
2896 | abort (); | |
2897 | ||
2898 | /* Symbols and expressions. */ | |
2899 | default: | |
9cd96992 JB |
2900 | /* Convert symbolic operand to proper sizes for matching, but don't |
2901 | prevent matching a set of insns that only supports sizes other | |
2902 | than those matching the insn suffix. */ | |
2903 | { | |
40fb9820 | 2904 | i386_operand_type mask, allowed; |
9cd96992 JB |
2905 | const template *t; |
2906 | ||
c6fb90c8 L |
2907 | UINTS_CLEAR (mask); |
2908 | UINTS_CLEAR (allowed); | |
40fb9820 | 2909 | |
4eed87de AM |
2910 | for (t = current_templates->start; |
2911 | t < current_templates->end; | |
2912 | ++t) | |
c6fb90c8 L |
2913 | allowed = operand_type_or (allowed, |
2914 | t->operand_types[op]); | |
9cd96992 JB |
2915 | switch (guess_suffix) |
2916 | { | |
2917 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
2918 | mask.bitfield.imm64 = 1; |
2919 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
2920 | break; |
2921 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 2922 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
2923 | break; |
2924 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 2925 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
2926 | break; |
2927 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 2928 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
2929 | break; |
2930 | default: | |
9cd96992 JB |
2931 | break; |
2932 | } | |
c6fb90c8 L |
2933 | allowed = operand_type_and (mask, allowed); |
2934 | if (!UINTS_ALL_ZERO (allowed)) | |
2935 | i.types[op] = operand_type_and (i.types[op], mask); | |
9cd96992 | 2936 | } |
29b0f896 | 2937 | break; |
252b5132 | 2938 | } |
29b0f896 AM |
2939 | } |
2940 | } | |
47926f60 | 2941 | |
29b0f896 AM |
2942 | /* Try to use the smallest displacement type too. */ |
2943 | static void | |
e3bb37b5 | 2944 | optimize_disp (void) |
29b0f896 AM |
2945 | { |
2946 | int op; | |
3e73aa7c | 2947 | |
29b0f896 | 2948 | for (op = i.operands; --op >= 0;) |
40fb9820 | 2949 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 2950 | { |
b300c311 | 2951 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 2952 | { |
b300c311 | 2953 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 2954 | |
40fb9820 | 2955 | if (i.types[op].bitfield.disp16 |
b300c311 L |
2956 | && (disp & ~(offsetT) 0xffff) == 0) |
2957 | { | |
2958 | /* If this operand is at most 16 bits, convert | |
2959 | to a signed 16 bit number and don't use 64bit | |
2960 | displacement. */ | |
2961 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
40fb9820 | 2962 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 2963 | } |
40fb9820 | 2964 | if (i.types[op].bitfield.disp32 |
b300c311 L |
2965 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
2966 | { | |
2967 | /* If this operand is at most 32 bits, convert | |
2968 | to a signed 32 bit number and don't use 64bit | |
2969 | displacement. */ | |
2970 | disp &= (((offsetT) 2 << 31) - 1); | |
2971 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 2972 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 2973 | } |
40fb9820 | 2974 | if (!disp && i.types[op].bitfield.baseindex) |
b300c311 | 2975 | { |
40fb9820 L |
2976 | i.types[op].bitfield.disp8 = 0; |
2977 | i.types[op].bitfield.disp16 = 0; | |
2978 | i.types[op].bitfield.disp32 = 0; | |
2979 | i.types[op].bitfield.disp32s = 0; | |
2980 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
2981 | i.op[op].disps = 0; |
2982 | i.disp_operands--; | |
2983 | } | |
2984 | else if (flag_code == CODE_64BIT) | |
2985 | { | |
2986 | if (fits_in_signed_long (disp)) | |
28a9d8f5 | 2987 | { |
40fb9820 L |
2988 | i.types[op].bitfield.disp64 = 0; |
2989 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 2990 | } |
b300c311 | 2991 | if (fits_in_unsigned_long (disp)) |
40fb9820 | 2992 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 2993 | } |
40fb9820 L |
2994 | if ((i.types[op].bitfield.disp32 |
2995 | || i.types[op].bitfield.disp32s | |
2996 | || i.types[op].bitfield.disp16) | |
b300c311 | 2997 | && fits_in_signed_byte (disp)) |
40fb9820 | 2998 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 2999 | } |
67a4f2b7 AO |
3000 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3001 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3002 | { | |
3003 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3004 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3005 | i.types[op].bitfield.disp8 = 0; |
3006 | i.types[op].bitfield.disp16 = 0; | |
3007 | i.types[op].bitfield.disp32 = 0; | |
3008 | i.types[op].bitfield.disp32s = 0; | |
3009 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3010 | } |
3011 | else | |
b300c311 | 3012 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3013 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3014 | } |
29b0f896 AM |
3015 | } |
3016 | ||
3017 | static int | |
e3bb37b5 | 3018 | match_template (void) |
29b0f896 AM |
3019 | { |
3020 | /* Points to template once we've found it. */ | |
3021 | const template *t; | |
40fb9820 | 3022 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
29b0f896 | 3023 | unsigned int found_reverse_match; |
40fb9820 L |
3024 | i386_opcode_modifier suffix_check; |
3025 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3026 | int addr_prefix_disp; |
a5c311ca | 3027 | unsigned int j; |
c6fb90c8 | 3028 | i386_cpu_flags overlap; |
29b0f896 | 3029 | |
f48ff2ae L |
3030 | #if MAX_OPERANDS != 4 |
3031 | # error "MAX_OPERANDS must be 4." | |
3032 | #endif | |
3033 | ||
29b0f896 | 3034 | found_reverse_match = 0; |
539e75ad | 3035 | addr_prefix_disp = -1; |
40fb9820 L |
3036 | |
3037 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3038 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3039 | suffix_check.no_bsuf = 1; | |
3040 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3041 | suffix_check.no_wsuf = 1; | |
3042 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3043 | suffix_check.no_ssuf = 1; | |
3044 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3045 | suffix_check.no_lsuf = 1; | |
3046 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3047 | suffix_check.no_qsuf = 1; | |
3048 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3049 | suffix_check.no_ldsuf = 1; |
582d5edd L |
3050 | else if (i.suffix == XMMWORD_MNEM_SUFFIX) |
3051 | suffix_check.no_xsuf = 1; | |
29b0f896 | 3052 | |
45aa61fe | 3053 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3054 | { |
539e75ad L |
3055 | addr_prefix_disp = -1; |
3056 | ||
29b0f896 AM |
3057 | /* Must have right number of operands. */ |
3058 | if (i.operands != t->operands) | |
3059 | continue; | |
3060 | ||
1efbbeb4 L |
3061 | /* Check AT&T mnemonic and old gcc support. */ |
3062 | if (t->opcode_modifier.attmnemonic | |
3063 | && (intel_mnemonic | |
3064 | || (!old_gcc | |
3065 | && t->opcode_modifier.oldgcc))) | |
3066 | continue; | |
3067 | ||
3068 | /* Check Intel mnemonic. */ | |
3069 | if (!intel_mnemonic && t->opcode_modifier.intelmnemonic) | |
3070 | continue; | |
3071 | ||
20592a94 | 3072 | /* Check the suffix, except for some instructions in intel mode. */ |
567e4e96 L |
3073 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3074 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3075 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3076 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3077 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3078 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3079 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3080 | continue; |
3081 | ||
582d5edd L |
3082 | /* Check the memory size in Intel mode when it is provided if |
3083 | needed. */ | |
3084 | if (intel_syntax | |
3085 | && i.suffix | |
3086 | && t->opcode_modifier.checksize | |
3087 | && (!t->opcode_modifier.byte || !suffix_check.no_bsuf) | |
3088 | && (!t->opcode_modifier.word || !suffix_check.no_wsuf) | |
3089 | && (!t->opcode_modifier.dword || !suffix_check.no_lsuf) | |
3090 | && (!t->opcode_modifier.qword || !suffix_check.no_qsuf) | |
3091 | && (!t->opcode_modifier.xmmword || !suffix_check.no_xsuf)) | |
3092 | continue; | |
3093 | ||
a5c311ca L |
3094 | for (j = 0; j < MAX_OPERANDS; j++) |
3095 | operand_types [j] = t->operand_types [j]; | |
539e75ad | 3096 | |
45aa61fe AM |
3097 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3098 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3099 | && flag_code != CODE_64BIT | |
3100 | && (intel_syntax | |
40fb9820 | 3101 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3102 | && !intel_float_operand (t->name)) |
3103 | : intel_float_operand (t->name) != 2) | |
40fb9820 L |
3104 | && ((!operand_types[0].bitfield.regmmx |
3105 | && !operand_types[0].bitfield.regxmm) | |
3106 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3107 | && !!operand_types[t->operands > 1].bitfield.regxmm)) | |
45aa61fe AM |
3108 | && (t->base_opcode != 0x0fc7 |
3109 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3110 | continue; | |
3111 | ||
29b0f896 | 3112 | /* Do not verify operands when there are none. */ |
c6fb90c8 | 3113 | else |
29b0f896 | 3114 | { |
c6fb90c8 L |
3115 | overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not); |
3116 | if (!t->operands) | |
3117 | { | |
3118 | if (!UINTS_ALL_ZERO (overlap)) | |
3119 | continue; | |
3120 | /* We've found a match; break out of loop. */ | |
3121 | break; | |
3122 | } | |
29b0f896 | 3123 | } |
252b5132 | 3124 | |
539e75ad L |
3125 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3126 | into Disp32/Disp16/Disp32 operand. */ | |
3127 | if (i.prefix[ADDR_PREFIX] != 0) | |
3128 | { | |
40fb9820 | 3129 | /* There should be only one Disp operand. */ |
539e75ad L |
3130 | switch (flag_code) |
3131 | { | |
3132 | case CODE_16BIT: | |
40fb9820 L |
3133 | for (j = 0; j < MAX_OPERANDS; j++) |
3134 | { | |
3135 | if (operand_types[j].bitfield.disp16) | |
3136 | { | |
3137 | addr_prefix_disp = j; | |
3138 | operand_types[j].bitfield.disp32 = 1; | |
3139 | operand_types[j].bitfield.disp16 = 0; | |
3140 | break; | |
3141 | } | |
3142 | } | |
539e75ad L |
3143 | break; |
3144 | case CODE_32BIT: | |
40fb9820 L |
3145 | for (j = 0; j < MAX_OPERANDS; j++) |
3146 | { | |
3147 | if (operand_types[j].bitfield.disp32) | |
3148 | { | |
3149 | addr_prefix_disp = j; | |
3150 | operand_types[j].bitfield.disp32 = 0; | |
3151 | operand_types[j].bitfield.disp16 = 1; | |
3152 | break; | |
3153 | } | |
3154 | } | |
539e75ad L |
3155 | break; |
3156 | case CODE_64BIT: | |
40fb9820 L |
3157 | for (j = 0; j < MAX_OPERANDS; j++) |
3158 | { | |
3159 | if (operand_types[j].bitfield.disp64) | |
3160 | { | |
3161 | addr_prefix_disp = j; | |
3162 | operand_types[j].bitfield.disp64 = 0; | |
3163 | operand_types[j].bitfield.disp32 = 1; | |
3164 | break; | |
3165 | } | |
3166 | } | |
539e75ad L |
3167 | break; |
3168 | } | |
539e75ad L |
3169 | } |
3170 | ||
c6fb90c8 | 3171 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
3172 | switch (t->operands) |
3173 | { | |
3174 | case 1: | |
40fb9820 | 3175 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
3176 | continue; |
3177 | break; | |
3178 | case 2: | |
8b38ad71 L |
3179 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
3180 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
3181 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
3182 | zero-extend %eax to %rax. */ | |
3183 | if (flag_code == CODE_64BIT | |
3184 | && t->base_opcode == 0x90 | |
c6fb90c8 L |
3185 | && UINTS_EQUAL (i.types [0], acc32) |
3186 | && UINTS_EQUAL (i.types [1], acc32)) | |
8b38ad71 | 3187 | continue; |
29b0f896 | 3188 | case 3: |
f48ff2ae | 3189 | case 4: |
c6fb90c8 | 3190 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
3191 | if (!operand_type_match (overlap0, i.types[0]) |
3192 | || !operand_type_match (overlap1, i.types[1]) | |
cb712a9e | 3193 | /* monitor in SSE3 is a very special case. The first |
708587a4 | 3194 | register and the second register may have different |
26186d74 L |
3195 | sizes. The same applies to crc32 in SSE4.2. It is |
3196 | also true for invlpga, vmload, vmrun and vmsave in | |
3197 | SVME. */ | |
cb712a9e | 3198 | || !((t->base_opcode == 0x0f01 |
26186d74 L |
3199 | && (t->extension_opcode == 0xc8 |
3200 | || t->extension_opcode == 0xd8 | |
3201 | || t->extension_opcode == 0xda | |
3202 | || t->extension_opcode == 0xdb | |
3203 | || t->extension_opcode == 0xdf)) | |
381d071f | 3204 | || t->base_opcode == 0xf20f38f1 |
40fb9820 L |
3205 | || operand_type_register_match (overlap0, i.types[0], |
3206 | operand_types[0], | |
3207 | overlap1, i.types[1], | |
3208 | operand_types[1]))) | |
29b0f896 AM |
3209 | { |
3210 | /* Check if other direction is valid ... */ | |
40fb9820 | 3211 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
3212 | continue; |
3213 | ||
3214 | /* Try reversing direction of operands. */ | |
c6fb90c8 L |
3215 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
3216 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
3217 | if (!operand_type_match (overlap0, i.types[0]) |
3218 | || !operand_type_match (overlap1, i.types[1]) | |
3219 | || !operand_type_register_match (overlap0, i.types[0], | |
3220 | operand_types[1], | |
3221 | overlap1, i.types[1], | |
3222 | operand_types[0])) | |
29b0f896 AM |
3223 | { |
3224 | /* Does not match either direction. */ | |
3225 | continue; | |
3226 | } | |
3227 | /* found_reverse_match holds which of D or FloatDR | |
3228 | we've found. */ | |
40fb9820 | 3229 | if (t->opcode_modifier.d) |
8a2ed489 | 3230 | found_reverse_match = Opcode_D; |
40fb9820 | 3231 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
3232 | found_reverse_match = Opcode_FloatD; |
3233 | else | |
3234 | found_reverse_match = 0; | |
40fb9820 | 3235 | if (t->opcode_modifier.floatr) |
8a2ed489 | 3236 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 3237 | } |
f48ff2ae | 3238 | else |
29b0f896 | 3239 | { |
f48ff2ae | 3240 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
3241 | switch (t->operands) |
3242 | { | |
3243 | case 4: | |
c6fb90c8 L |
3244 | overlap3 = operand_type_and (i.types[3], |
3245 | operand_types[3]); | |
d1cbb4db | 3246 | case 3: |
c6fb90c8 L |
3247 | overlap2 = operand_type_and (i.types[2], |
3248 | operand_types[2]); | |
d1cbb4db L |
3249 | break; |
3250 | } | |
29b0f896 | 3251 | |
f48ff2ae L |
3252 | switch (t->operands) |
3253 | { | |
3254 | case 4: | |
40fb9820 L |
3255 | if (!operand_type_match (overlap3, i.types[3]) |
3256 | || !operand_type_register_match (overlap2, | |
3257 | i.types[2], | |
3258 | operand_types[2], | |
3259 | overlap3, | |
3260 | i.types[3], | |
3261 | operand_types[3])) | |
f48ff2ae L |
3262 | continue; |
3263 | case 3: | |
3264 | /* Here we make use of the fact that there are no | |
3265 | reverse match 3 operand instructions, and all 3 | |
3266 | operand instructions only need to be checked for | |
3267 | register consistency between operands 2 and 3. */ | |
40fb9820 L |
3268 | if (!operand_type_match (overlap2, i.types[2]) |
3269 | || !operand_type_register_match (overlap1, | |
3270 | i.types[1], | |
3271 | operand_types[1], | |
3272 | overlap2, | |
3273 | i.types[2], | |
3274 | operand_types[2])) | |
f48ff2ae L |
3275 | continue; |
3276 | break; | |
3277 | } | |
29b0f896 | 3278 | } |
f48ff2ae | 3279 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
3280 | slip through to break. */ |
3281 | } | |
c6fb90c8 | 3282 | if (!UINTS_ALL_ZERO (overlap)) |
29b0f896 AM |
3283 | { |
3284 | found_reverse_match = 0; | |
3285 | continue; | |
3286 | } | |
3287 | /* We've found a match; break out of loop. */ | |
3288 | break; | |
3289 | } | |
3290 | ||
3291 | if (t == current_templates->end) | |
3292 | { | |
3293 | /* We found no match. */ | |
3294 | as_bad (_("suffix or operands invalid for `%s'"), | |
3295 | current_templates->start->name); | |
3296 | return 0; | |
3297 | } | |
252b5132 | 3298 | |
29b0f896 AM |
3299 | if (!quiet_warnings) |
3300 | { | |
3301 | if (!intel_syntax | |
40fb9820 L |
3302 | && (i.types[0].bitfield.jumpabsolute |
3303 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
3304 | { |
3305 | as_warn (_("indirect %s without `*'"), t->name); | |
3306 | } | |
3307 | ||
40fb9820 L |
3308 | if (t->opcode_modifier.isprefix |
3309 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
3310 | { |
3311 | /* Warn them that a data or address size prefix doesn't | |
3312 | affect assembly of the next line of code. */ | |
3313 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
3314 | } | |
3315 | } | |
3316 | ||
3317 | /* Copy the template we found. */ | |
3318 | i.tm = *t; | |
539e75ad L |
3319 | |
3320 | if (addr_prefix_disp != -1) | |
3321 | i.tm.operand_types[addr_prefix_disp] | |
3322 | = operand_types[addr_prefix_disp]; | |
3323 | ||
29b0f896 AM |
3324 | if (found_reverse_match) |
3325 | { | |
3326 | /* If we found a reverse match we must alter the opcode | |
3327 | direction bit. found_reverse_match holds bits to change | |
3328 | (different for int & float insns). */ | |
3329 | ||
3330 | i.tm.base_opcode ^= found_reverse_match; | |
3331 | ||
539e75ad L |
3332 | i.tm.operand_types[0] = operand_types[1]; |
3333 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
3334 | } |
3335 | ||
3336 | return 1; | |
3337 | } | |
3338 | ||
3339 | static int | |
e3bb37b5 | 3340 | check_string (void) |
29b0f896 | 3341 | { |
40fb9820 L |
3342 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
3343 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
3344 | { |
3345 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
3346 | { | |
3347 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
3348 | i.tm.name, | |
3349 | mem_op + 1); | |
3350 | return 0; | |
3351 | } | |
3352 | /* There's only ever one segment override allowed per instruction. | |
3353 | This instruction possibly has a legal segment override on the | |
3354 | second operand, so copy the segment to where non-string | |
3355 | instructions store it, allowing common code. */ | |
3356 | i.seg[0] = i.seg[1]; | |
3357 | } | |
40fb9820 | 3358 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
3359 | { |
3360 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
3361 | { | |
3362 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
3363 | i.tm.name, | |
3364 | mem_op + 2); | |
3365 | return 0; | |
3366 | } | |
3367 | } | |
3368 | return 1; | |
3369 | } | |
3370 | ||
3371 | static int | |
543613e9 | 3372 | process_suffix (void) |
29b0f896 AM |
3373 | { |
3374 | /* If matched instruction specifies an explicit instruction mnemonic | |
3375 | suffix, use it. */ | |
40fb9820 L |
3376 | if (i.tm.opcode_modifier.size16) |
3377 | i.suffix = WORD_MNEM_SUFFIX; | |
3378 | else if (i.tm.opcode_modifier.size32) | |
3379 | i.suffix = LONG_MNEM_SUFFIX; | |
3380 | else if (i.tm.opcode_modifier.size64) | |
3381 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
3382 | else if (i.reg_operands) |
3383 | { | |
3384 | /* If there's no instruction mnemonic suffix we try to invent one | |
3385 | based on register operands. */ | |
3386 | if (!i.suffix) | |
3387 | { | |
3388 | /* We take i.suffix from the last register operand specified, | |
3389 | Destination register type is more significant than source | |
381d071f L |
3390 | register type. crc32 in SSE4.2 prefers source register |
3391 | type. */ | |
3392 | if (i.tm.base_opcode == 0xf20f38f1) | |
3393 | { | |
40fb9820 L |
3394 | if (i.types[0].bitfield.reg16) |
3395 | i.suffix = WORD_MNEM_SUFFIX; | |
3396 | else if (i.types[0].bitfield.reg32) | |
3397 | i.suffix = LONG_MNEM_SUFFIX; | |
3398 | else if (i.types[0].bitfield.reg64) | |
3399 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 3400 | } |
9344ff29 | 3401 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 3402 | { |
40fb9820 | 3403 | if (i.types[0].bitfield.reg8) |
20592a94 L |
3404 | i.suffix = BYTE_MNEM_SUFFIX; |
3405 | } | |
381d071f L |
3406 | |
3407 | if (!i.suffix) | |
3408 | { | |
3409 | int op; | |
3410 | ||
20592a94 L |
3411 | if (i.tm.base_opcode == 0xf20f38f1 |
3412 | || i.tm.base_opcode == 0xf20f38f0) | |
3413 | { | |
3414 | /* We have to know the operand size for crc32. */ | |
3415 | as_bad (_("ambiguous memory operand size for `%s`"), | |
3416 | i.tm.name); | |
3417 | return 0; | |
3418 | } | |
3419 | ||
381d071f | 3420 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3421 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 3422 | { |
40fb9820 L |
3423 | if (i.types[op].bitfield.reg8) |
3424 | { | |
3425 | i.suffix = BYTE_MNEM_SUFFIX; | |
3426 | break; | |
3427 | } | |
3428 | else if (i.types[op].bitfield.reg16) | |
3429 | { | |
3430 | i.suffix = WORD_MNEM_SUFFIX; | |
3431 | break; | |
3432 | } | |
3433 | else if (i.types[op].bitfield.reg32) | |
3434 | { | |
3435 | i.suffix = LONG_MNEM_SUFFIX; | |
3436 | break; | |
3437 | } | |
3438 | else if (i.types[op].bitfield.reg64) | |
3439 | { | |
3440 | i.suffix = QWORD_MNEM_SUFFIX; | |
3441 | break; | |
3442 | } | |
381d071f L |
3443 | } |
3444 | } | |
29b0f896 AM |
3445 | } |
3446 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
3447 | { | |
3448 | if (!check_byte_reg ()) | |
3449 | return 0; | |
3450 | } | |
3451 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3452 | { | |
3453 | if (!check_long_reg ()) | |
3454 | return 0; | |
3455 | } | |
3456 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3457 | { | |
955e1e6a L |
3458 | if (intel_syntax |
3459 | && i.tm.opcode_modifier.ignoresize | |
3460 | && i.tm.opcode_modifier.no_qsuf) | |
3461 | i.suffix = 0; | |
3462 | else if (!check_qword_reg ()) | |
29b0f896 AM |
3463 | return 0; |
3464 | } | |
3465 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3466 | { | |
3467 | if (!check_word_reg ()) | |
3468 | return 0; | |
3469 | } | |
582d5edd L |
3470 | else if (i.suffix == XMMWORD_MNEM_SUFFIX) |
3471 | { | |
3472 | /* Skip if the instruction has x suffix. match_template | |
3473 | should check if it is a valid suffix. */ | |
3474 | } | |
40fb9820 | 3475 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
3476 | /* Do nothing if the instruction is going to ignore the prefix. */ |
3477 | ; | |
3478 | else | |
3479 | abort (); | |
3480 | } | |
40fb9820 | 3481 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
3482 | && !i.suffix |
3483 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 3484 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
3485 | { |
3486 | i.suffix = stackop_size; | |
3487 | } | |
9306ca4a JB |
3488 | else if (intel_syntax |
3489 | && !i.suffix | |
40fb9820 L |
3490 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
3491 | || i.tm.opcode_modifier.jumpbyte | |
3492 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
3493 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
3494 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
3495 | { |
3496 | switch (flag_code) | |
3497 | { | |
3498 | case CODE_64BIT: | |
40fb9820 | 3499 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
3500 | { |
3501 | i.suffix = QWORD_MNEM_SUFFIX; | |
3502 | break; | |
3503 | } | |
3504 | case CODE_32BIT: | |
40fb9820 | 3505 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
3506 | i.suffix = LONG_MNEM_SUFFIX; |
3507 | break; | |
3508 | case CODE_16BIT: | |
40fb9820 | 3509 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
3510 | i.suffix = WORD_MNEM_SUFFIX; |
3511 | break; | |
3512 | } | |
3513 | } | |
252b5132 | 3514 | |
9306ca4a | 3515 | if (!i.suffix) |
29b0f896 | 3516 | { |
9306ca4a JB |
3517 | if (!intel_syntax) |
3518 | { | |
40fb9820 | 3519 | if (i.tm.opcode_modifier.w) |
9306ca4a | 3520 | { |
4eed87de AM |
3521 | as_bad (_("no instruction mnemonic suffix given and " |
3522 | "no register operands; can't size instruction")); | |
9306ca4a JB |
3523 | return 0; |
3524 | } | |
3525 | } | |
3526 | else | |
3527 | { | |
40fb9820 L |
3528 | unsigned int suffixes; |
3529 | ||
3530 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
3531 | if (!i.tm.opcode_modifier.no_wsuf) | |
3532 | suffixes |= 1 << 1; | |
3533 | if (!i.tm.opcode_modifier.no_lsuf) | |
3534 | suffixes |= 1 << 2; | |
fc4adea1 | 3535 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
3536 | suffixes |= 1 << 3; |
3537 | if (!i.tm.opcode_modifier.no_ssuf) | |
3538 | suffixes |= 1 << 4; | |
3539 | if (!i.tm.opcode_modifier.no_qsuf) | |
3540 | suffixes |= 1 << 5; | |
3541 | ||
3542 | /* There are more than suffix matches. */ | |
3543 | if (i.tm.opcode_modifier.w | |
9306ca4a | 3544 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
3545 | && !i.tm.opcode_modifier.defaultsize |
3546 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
3547 | { |
3548 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
3549 | return 0; | |
3550 | } | |
3551 | } | |
29b0f896 | 3552 | } |
252b5132 | 3553 | |
9306ca4a JB |
3554 | /* Change the opcode based on the operand size given by i.suffix; |
3555 | We don't need to change things for byte insns. */ | |
3556 | ||
582d5edd L |
3557 | if (i.suffix |
3558 | && i.suffix != BYTE_MNEM_SUFFIX | |
3559 | && i.suffix != XMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
3560 | { |
3561 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 3562 | if (i.tm.opcode_modifier.w) |
29b0f896 | 3563 | { |
40fb9820 | 3564 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
3565 | i.tm.base_opcode |= 8; |
3566 | else | |
3567 | i.tm.base_opcode |= 1; | |
3568 | } | |
0f3f3d8b | 3569 | |
29b0f896 AM |
3570 | /* Now select between word & dword operations via the operand |
3571 | size prefix, except for instructions that will ignore this | |
3572 | prefix anyway. */ | |
ca61edf2 | 3573 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 3574 | { |
ca61edf2 L |
3575 | /* The address size override prefix changes the size of the |
3576 | first operand. */ | |
40fb9820 L |
3577 | if ((flag_code == CODE_32BIT |
3578 | && i.op->regs[0].reg_type.bitfield.reg16) | |
3579 | || (flag_code != CODE_32BIT | |
3580 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
3581 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
3582 | return 0; | |
3583 | } | |
3584 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
3585 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
3586 | && !i.tm.opcode_modifier.ignoresize |
3587 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
3588 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
3589 | || (flag_code == CODE_64BIT | |
40fb9820 | 3590 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
3591 | { |
3592 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 3593 | |
40fb9820 | 3594 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 3595 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 3596 | |
29b0f896 AM |
3597 | if (!add_prefix (prefix)) |
3598 | return 0; | |
24eab124 | 3599 | } |
252b5132 | 3600 | |
29b0f896 AM |
3601 | /* Set mode64 for an operand. */ |
3602 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 3603 | && flag_code == CODE_64BIT |
40fb9820 | 3604 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
3605 | { |
3606 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
3607 | need rex64. cmpxchg8b is also a special case. */ |
3608 | if (! (i.operands == 2 | |
3609 | && i.tm.base_opcode == 0x90 | |
3610 | && i.tm.extension_opcode == None | |
c6fb90c8 L |
3611 | && UINTS_EQUAL (i.types [0], acc64) |
3612 | && UINTS_EQUAL (i.types [1], acc64)) | |
d9a5e5e5 L |
3613 | && ! (i.operands == 1 |
3614 | && i.tm.base_opcode == 0xfc7 | |
3615 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
3616 | && !operand_type_check (i.types [0], reg) |
3617 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 3618 | i.rex |= REX_W; |
46e883c5 | 3619 | } |
3e73aa7c | 3620 | |
29b0f896 AM |
3621 | /* Size floating point instruction. */ |
3622 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 3623 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 3624 | i.tm.base_opcode ^= 4; |
29b0f896 | 3625 | } |
7ecd2f8b | 3626 | |
29b0f896 AM |
3627 | return 1; |
3628 | } | |
3e73aa7c | 3629 | |
29b0f896 | 3630 | static int |
543613e9 | 3631 | check_byte_reg (void) |
29b0f896 AM |
3632 | { |
3633 | int op; | |
543613e9 | 3634 | |
29b0f896 AM |
3635 | for (op = i.operands; --op >= 0;) |
3636 | { | |
3637 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
3638 | 32 bit version of an eight bit register, we will just use the | |
3639 | low portion, and that's OK too. */ | |
40fb9820 | 3640 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
3641 | continue; |
3642 | ||
ca61edf2 L |
3643 | /* Don't generate this warning if not needed. */ |
3644 | if (intel_syntax && i.tm.opcode_modifier.byteokintel) | |
29b0f896 AM |
3645 | continue; |
3646 | ||
9344ff29 L |
3647 | /* crc32 doesn't generate this warning. */ |
3648 | if (i.tm.base_opcode == 0xf20f38f0) | |
3649 | continue; | |
3650 | ||
40fb9820 L |
3651 | if ((i.types[op].bitfield.reg16 |
3652 | || i.types[op].bitfield.reg32 | |
3653 | || i.types[op].bitfield.reg64) | |
3654 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
3655 | { |
3656 | /* Prohibit these changes in the 64bit mode, since the | |
3657 | lowering is more complicated. */ | |
3658 | if (flag_code == CODE_64BIT | |
40fb9820 | 3659 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 3660 | { |
2ca3ace5 L |
3661 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3662 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3663 | i.suffix); |
3664 | return 0; | |
3665 | } | |
3666 | #if REGISTER_WARNINGS | |
3667 | if (!quiet_warnings | |
40fb9820 | 3668 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
3669 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
3670 | register_prefix, | |
40fb9820 | 3671 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
3672 | ? REGNAM_AL - REGNAM_AX |
3673 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 3674 | register_prefix, |
29b0f896 AM |
3675 | i.op[op].regs->reg_name, |
3676 | i.suffix); | |
3677 | #endif | |
3678 | continue; | |
3679 | } | |
3680 | /* Any other register is bad. */ | |
40fb9820 L |
3681 | if (i.types[op].bitfield.reg16 |
3682 | || i.types[op].bitfield.reg32 | |
3683 | || i.types[op].bitfield.reg64 | |
3684 | || i.types[op].bitfield.regmmx | |
3685 | || i.types[op].bitfield.regxmm | |
3686 | || i.types[op].bitfield.sreg2 | |
3687 | || i.types[op].bitfield.sreg3 | |
3688 | || i.types[op].bitfield.control | |
3689 | || i.types[op].bitfield.debug | |
3690 | || i.types[op].bitfield.test | |
3691 | || i.types[op].bitfield.floatreg | |
3692 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 3693 | { |
a540244d L |
3694 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3695 | register_prefix, | |
29b0f896 AM |
3696 | i.op[op].regs->reg_name, |
3697 | i.tm.name, | |
3698 | i.suffix); | |
3699 | return 0; | |
3700 | } | |
3701 | } | |
3702 | return 1; | |
3703 | } | |
3704 | ||
3705 | static int | |
e3bb37b5 | 3706 | check_long_reg (void) |
29b0f896 AM |
3707 | { |
3708 | int op; | |
3709 | ||
3710 | for (op = i.operands; --op >= 0;) | |
3711 | /* Reject eight bit registers, except where the template requires | |
3712 | them. (eg. movzb) */ | |
40fb9820 L |
3713 | if (i.types[op].bitfield.reg8 |
3714 | && (i.tm.operand_types[op].bitfield.reg16 | |
3715 | || i.tm.operand_types[op].bitfield.reg32 | |
3716 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 3717 | { |
a540244d L |
3718 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3719 | register_prefix, | |
29b0f896 AM |
3720 | i.op[op].regs->reg_name, |
3721 | i.tm.name, | |
3722 | i.suffix); | |
3723 | return 0; | |
3724 | } | |
3725 | /* Warn if the e prefix on a general reg is missing. */ | |
3726 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
3727 | && i.types[op].bitfield.reg16 |
3728 | && (i.tm.operand_types[op].bitfield.reg32 | |
3729 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
3730 | { |
3731 | /* Prohibit these changes in the 64bit mode, since the | |
3732 | lowering is more complicated. */ | |
3733 | if (flag_code == CODE_64BIT) | |
252b5132 | 3734 | { |
2ca3ace5 L |
3735 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3736 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3737 | i.suffix); |
3738 | return 0; | |
252b5132 | 3739 | } |
29b0f896 AM |
3740 | #if REGISTER_WARNINGS |
3741 | else | |
a540244d L |
3742 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
3743 | register_prefix, | |
29b0f896 | 3744 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 3745 | register_prefix, |
29b0f896 AM |
3746 | i.op[op].regs->reg_name, |
3747 | i.suffix); | |
3748 | #endif | |
252b5132 | 3749 | } |
29b0f896 | 3750 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
3751 | else if (i.types[op].bitfield.reg64 |
3752 | && (i.tm.operand_types[op].bitfield.reg32 | |
3753 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 3754 | { |
34828aad | 3755 | if (intel_syntax |
ca61edf2 | 3756 | && i.tm.opcode_modifier.toqword |
40fb9820 | 3757 | && !i.types[0].bitfield.regxmm) |
34828aad | 3758 | { |
ca61edf2 | 3759 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
3760 | i.suffix = QWORD_MNEM_SUFFIX; |
3761 | } | |
3762 | else | |
3763 | { | |
3764 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
3765 | register_prefix, i.op[op].regs->reg_name, | |
3766 | i.suffix); | |
3767 | return 0; | |
3768 | } | |
29b0f896 AM |
3769 | } |
3770 | return 1; | |
3771 | } | |
252b5132 | 3772 | |
29b0f896 | 3773 | static int |
e3bb37b5 | 3774 | check_qword_reg (void) |
29b0f896 AM |
3775 | { |
3776 | int op; | |
252b5132 | 3777 | |
29b0f896 AM |
3778 | for (op = i.operands; --op >= 0; ) |
3779 | /* Reject eight bit registers, except where the template requires | |
3780 | them. (eg. movzb) */ | |
40fb9820 L |
3781 | if (i.types[op].bitfield.reg8 |
3782 | && (i.tm.operand_types[op].bitfield.reg16 | |
3783 | || i.tm.operand_types[op].bitfield.reg32 | |
3784 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 3785 | { |
a540244d L |
3786 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3787 | register_prefix, | |
29b0f896 AM |
3788 | i.op[op].regs->reg_name, |
3789 | i.tm.name, | |
3790 | i.suffix); | |
3791 | return 0; | |
3792 | } | |
3793 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
3794 | else if ((i.types[op].bitfield.reg16 |
3795 | || i.types[op].bitfield.reg32) | |
3796 | && (i.tm.operand_types[op].bitfield.reg32 | |
3797 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
3798 | { |
3799 | /* Prohibit these changes in the 64bit mode, since the | |
3800 | lowering is more complicated. */ | |
34828aad | 3801 | if (intel_syntax |
ca61edf2 | 3802 | && i.tm.opcode_modifier.todword |
40fb9820 | 3803 | && !i.types[0].bitfield.regxmm) |
34828aad | 3804 | { |
ca61edf2 | 3805 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
3806 | i.suffix = LONG_MNEM_SUFFIX; |
3807 | } | |
3808 | else | |
3809 | { | |
3810 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
3811 | register_prefix, i.op[op].regs->reg_name, | |
3812 | i.suffix); | |
3813 | return 0; | |
3814 | } | |
252b5132 | 3815 | } |
29b0f896 AM |
3816 | return 1; |
3817 | } | |
252b5132 | 3818 | |
29b0f896 | 3819 | static int |
e3bb37b5 | 3820 | check_word_reg (void) |
29b0f896 AM |
3821 | { |
3822 | int op; | |
3823 | for (op = i.operands; --op >= 0;) | |
3824 | /* Reject eight bit registers, except where the template requires | |
3825 | them. (eg. movzb) */ | |
40fb9820 L |
3826 | if (i.types[op].bitfield.reg8 |
3827 | && (i.tm.operand_types[op].bitfield.reg16 | |
3828 | || i.tm.operand_types[op].bitfield.reg32 | |
3829 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 3830 | { |
a540244d L |
3831 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3832 | register_prefix, | |
29b0f896 AM |
3833 | i.op[op].regs->reg_name, |
3834 | i.tm.name, | |
3835 | i.suffix); | |
3836 | return 0; | |
3837 | } | |
3838 | /* Warn if the e prefix on a general reg is present. */ | |
3839 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
3840 | && i.types[op].bitfield.reg32 |
3841 | && (i.tm.operand_types[op].bitfield.reg16 | |
3842 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 3843 | { |
29b0f896 AM |
3844 | /* Prohibit these changes in the 64bit mode, since the |
3845 | lowering is more complicated. */ | |
3846 | if (flag_code == CODE_64BIT) | |
252b5132 | 3847 | { |
2ca3ace5 L |
3848 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3849 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3850 | i.suffix); |
3851 | return 0; | |
252b5132 | 3852 | } |
29b0f896 AM |
3853 | else |
3854 | #if REGISTER_WARNINGS | |
a540244d L |
3855 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
3856 | register_prefix, | |
29b0f896 | 3857 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 3858 | register_prefix, |
29b0f896 AM |
3859 | i.op[op].regs->reg_name, |
3860 | i.suffix); | |
3861 | #endif | |
3862 | } | |
3863 | return 1; | |
3864 | } | |
252b5132 | 3865 | |
29b0f896 | 3866 | static int |
40fb9820 | 3867 | update_imm (unsigned int j) |
29b0f896 | 3868 | { |
40fb9820 L |
3869 | i386_operand_type overlap; |
3870 | ||
c6fb90c8 | 3871 | overlap = operand_type_and (i.types[j], i.tm.operand_types[j]); |
40fb9820 L |
3872 | if ((overlap.bitfield.imm8 |
3873 | || overlap.bitfield.imm8s | |
3874 | || overlap.bitfield.imm16 | |
3875 | || overlap.bitfield.imm32 | |
3876 | || overlap.bitfield.imm32s | |
3877 | || overlap.bitfield.imm64) | |
c6fb90c8 L |
3878 | && !UINTS_EQUAL (overlap, imm8) |
3879 | && !UINTS_EQUAL (overlap, imm8s) | |
3880 | && !UINTS_EQUAL (overlap, imm16) | |
3881 | && !UINTS_EQUAL (overlap, imm32) | |
3882 | && !UINTS_EQUAL (overlap, imm32s) | |
3883 | && !UINTS_EQUAL (overlap, imm64)) | |
29b0f896 AM |
3884 | { |
3885 | if (i.suffix) | |
3886 | { | |
40fb9820 L |
3887 | i386_operand_type temp; |
3888 | ||
c6fb90c8 | 3889 | UINTS_CLEAR (temp); |
40fb9820 L |
3890 | if (i.suffix == BYTE_MNEM_SUFFIX) |
3891 | { | |
3892 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
3893 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
3894 | } | |
3895 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3896 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
3897 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3898 | { | |
3899 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
3900 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
3901 | } | |
3902 | else | |
3903 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
3904 | overlap = temp; | |
29b0f896 | 3905 | } |
c6fb90c8 L |
3906 | else if (UINTS_EQUAL (overlap, imm16_32_32s) |
3907 | || UINTS_EQUAL (overlap, imm16_32) | |
3908 | || UINTS_EQUAL (overlap, imm16_32s)) | |
29b0f896 | 3909 | { |
c6fb90c8 | 3910 | UINTS_CLEAR (overlap); |
40fb9820 L |
3911 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
3912 | overlap.bitfield.imm16 = 1; | |
3913 | else | |
3914 | overlap.bitfield.imm32s = 1; | |
29b0f896 | 3915 | } |
c6fb90c8 L |
3916 | if (!UINTS_EQUAL (overlap, imm8) |
3917 | && !UINTS_EQUAL (overlap, imm8s) | |
3918 | && !UINTS_EQUAL (overlap, imm16) | |
3919 | && !UINTS_EQUAL (overlap, imm32) | |
3920 | && !UINTS_EQUAL (overlap, imm32s) | |
3921 | && !UINTS_EQUAL (overlap, imm64)) | |
29b0f896 | 3922 | { |
4eed87de AM |
3923 | as_bad (_("no instruction mnemonic suffix given; " |
3924 | "can't determine immediate size")); | |
29b0f896 AM |
3925 | return 0; |
3926 | } | |
3927 | } | |
40fb9820 | 3928 | i.types[j] = overlap; |
29b0f896 | 3929 | |
40fb9820 L |
3930 | return 1; |
3931 | } | |
3932 | ||
3933 | static int | |
3934 | finalize_imm (void) | |
3935 | { | |
3936 | unsigned int j; | |
29b0f896 | 3937 | |
40fb9820 L |
3938 | for (j = 0; j < 2; j++) |
3939 | if (update_imm (j) == 0) | |
3940 | return 0; | |
3941 | ||
c6fb90c8 | 3942 | i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]); |
40fb9820 | 3943 | assert (operand_type_check (i.types[2], imm) == 0); |
29b0f896 AM |
3944 | |
3945 | return 1; | |
3946 | } | |
3947 | ||
85f10a01 MM |
3948 | static void |
3949 | process_drex (void) | |
3950 | { | |
3951 | i.drex.modrm_reg = None; | |
3952 | i.drex.modrm_regmem = None; | |
3953 | ||
3954 | /* SSE5 4 operand instructions must have the destination the same as | |
3955 | one of the inputs. Figure out the destination register and cache | |
3956 | it away in the drex field, and remember which fields to use for | |
3957 | the modrm byte. */ | |
3958 | if (i.tm.opcode_modifier.drex | |
3959 | && i.tm.opcode_modifier.drexv | |
3960 | && i.operands == 4) | |
3961 | { | |
3962 | i.tm.extension_opcode = None; | |
3963 | ||
3964 | /* Case 1: 4 operand insn, dest = src1, src3 = register. */ | |
3965 | if (i.types[0].bitfield.regxmm != 0 | |
3966 | && i.types[1].bitfield.regxmm != 0 | |
3967 | && i.types[2].bitfield.regxmm != 0 | |
3968 | && i.types[3].bitfield.regxmm != 0 | |
3969 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
3970 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
3971 | { | |
3972 | /* Clear the arguments that are stored in drex. */ | |
3973 | UINTS_CLEAR (i.types[0]); | |
3974 | UINTS_CLEAR (i.types[3]); | |
3975 | i.reg_operands -= 2; | |
3976 | ||
3977 | /* There are two different ways to encode a 4 operand | |
3978 | instruction with all registers that uses OC1 set to | |
3979 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
3980 | actions of other SSE5 assemblers. Use modrm encoding 2 | |
3981 | for register/register. Include the high order bit that | |
3982 | is normally stored in the REX byte in the register | |
3983 | field. */ | |
3984 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
3985 | i.drex.modrm_reg = 2; | |
3986 | i.drex.modrm_regmem = 1; | |
3987 | i.drex.reg = (i.op[3].regs->reg_num | |
3988 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
3989 | } | |
3990 | ||
3991 | /* Case 2: 4 operand insn, dest = src1, src3 = memory. */ | |
3992 | else if (i.types[0].bitfield.regxmm != 0 | |
3993 | && i.types[1].bitfield.regxmm != 0 | |
3994 | && (i.types[2].bitfield.regxmm | |
3995 | || operand_type_check (i.types[2], anymem)) | |
3996 | && i.types[3].bitfield.regxmm != 0 | |
3997 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
3998 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
3999 | { | |
4000 | /* clear the arguments that are stored in drex */ | |
4001 | UINTS_CLEAR (i.types[0]); | |
4002 | UINTS_CLEAR (i.types[3]); | |
4003 | i.reg_operands -= 2; | |
4004 | ||
4005 | /* Specify the modrm encoding for memory addressing. Include | |
4006 | the high order bit that is normally stored in the REX byte | |
4007 | in the register field. */ | |
4008 | i.tm.extension_opcode = DREX_X1_X2_XMEM_X1; | |
4009 | i.drex.modrm_reg = 1; | |
4010 | i.drex.modrm_regmem = 2; | |
4011 | i.drex.reg = (i.op[3].regs->reg_num | |
4012 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4013 | } | |
4014 | ||
4015 | /* Case 3: 4 operand insn, dest = src1, src2 = memory. */ | |
4016 | else if (i.types[0].bitfield.regxmm != 0 | |
4017 | && operand_type_check (i.types[1], anymem) != 0 | |
4018 | && i.types[2].bitfield.regxmm != 0 | |
4019 | && i.types[3].bitfield.regxmm != 0 | |
4020 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4021 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4022 | { | |
4023 | /* Clear the arguments that are stored in drex. */ | |
4024 | UINTS_CLEAR (i.types[0]); | |
4025 | UINTS_CLEAR (i.types[3]); | |
4026 | i.reg_operands -= 2; | |
4027 | ||
4028 | /* Specify the modrm encoding for memory addressing. Include | |
4029 | the high order bit that is normally stored in the REX byte | |
4030 | in the register field. */ | |
4031 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4032 | i.drex.modrm_reg = 2; | |
4033 | i.drex.modrm_regmem = 1; | |
4034 | i.drex.reg = (i.op[3].regs->reg_num | |
4035 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4036 | } | |
4037 | ||
4038 | /* Case 4: 4 operand insn, dest = src3, src2 = register. */ | |
4039 | else if (i.types[0].bitfield.regxmm != 0 | |
4040 | && i.types[1].bitfield.regxmm != 0 | |
4041 | && i.types[2].bitfield.regxmm != 0 | |
4042 | && i.types[3].bitfield.regxmm != 0 | |
4043 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4044 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4045 | { | |
4046 | /* clear the arguments that are stored in drex */ | |
4047 | UINTS_CLEAR (i.types[2]); | |
4048 | UINTS_CLEAR (i.types[3]); | |
4049 | i.reg_operands -= 2; | |
4050 | ||
4051 | /* There are two different ways to encode a 4 operand | |
4052 | instruction with all registers that uses OC1 set to | |
4053 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4054 | actions of other SSE5 assemblers. Use modrm encoding | |
4055 | 2 for register/register. Include the high order bit that | |
4056 | is normally stored in the REX byte in the register | |
4057 | field. */ | |
4058 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4059 | i.drex.modrm_reg = 1; | |
4060 | i.drex.modrm_regmem = 0; | |
4061 | ||
4062 | /* Remember the register, including the upper bits */ | |
4063 | i.drex.reg = (i.op[3].regs->reg_num | |
4064 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4065 | } | |
4066 | ||
4067 | /* Case 5: 4 operand insn, dest = src3, src2 = memory. */ | |
4068 | else if (i.types[0].bitfield.regxmm != 0 | |
4069 | && (i.types[1].bitfield.regxmm | |
4070 | || operand_type_check (i.types[1], anymem)) | |
4071 | && i.types[2].bitfield.regxmm != 0 | |
4072 | && i.types[3].bitfield.regxmm != 0 | |
4073 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4074 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4075 | { | |
4076 | /* Clear the arguments that are stored in drex. */ | |
4077 | UINTS_CLEAR (i.types[2]); | |
4078 | UINTS_CLEAR (i.types[3]); | |
4079 | i.reg_operands -= 2; | |
4080 | ||
4081 | /* Specify the modrm encoding and remember the register | |
4082 | including the bits normally stored in the REX byte. */ | |
4083 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X2; | |
4084 | i.drex.modrm_reg = 0; | |
4085 | i.drex.modrm_regmem = 1; | |
4086 | i.drex.reg = (i.op[3].regs->reg_num | |
4087 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4088 | } | |
4089 | ||
4090 | /* Case 6: 4 operand insn, dest = src3, src1 = memory. */ | |
4091 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4092 | && i.types[1].bitfield.regxmm != 0 | |
4093 | && i.types[2].bitfield.regxmm != 0 | |
4094 | && i.types[3].bitfield.regxmm != 0 | |
4095 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4096 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4097 | { | |
4098 | /* clear the arguments that are stored in drex */ | |
4099 | UINTS_CLEAR (i.types[2]); | |
4100 | UINTS_CLEAR (i.types[3]); | |
4101 | i.reg_operands -= 2; | |
4102 | ||
4103 | /* Specify the modrm encoding and remember the register | |
4104 | including the bits normally stored in the REX byte. */ | |
4105 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4106 | i.drex.modrm_reg = 1; | |
4107 | i.drex.modrm_regmem = 0; | |
4108 | i.drex.reg = (i.op[3].regs->reg_num | |
4109 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4110 | } | |
4111 | ||
4112 | else | |
4113 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4114 | i.tm.name); | |
4115 | } | |
4116 | ||
4117 | /* SSE5 instructions with the DREX byte where the only memory operand | |
4118 | is in the 2nd argument, and the first and last xmm register must | |
4119 | match, and is encoded in the DREX byte. */ | |
4120 | else if (i.tm.opcode_modifier.drex | |
4121 | && !i.tm.opcode_modifier.drexv | |
4122 | && i.operands == 4) | |
4123 | { | |
4124 | /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */ | |
4125 | if (i.types[0].bitfield.regxmm != 0 | |
4126 | && (i.types[1].bitfield.regxmm | |
4127 | || operand_type_check(i.types[1], anymem)) | |
4128 | && i.types[2].bitfield.regxmm != 0 | |
4129 | && i.types[3].bitfield.regxmm != 0 | |
4130 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4131 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4132 | { | |
4133 | /* clear the arguments that are stored in drex */ | |
4134 | UINTS_CLEAR (i.types[0]); | |
4135 | UINTS_CLEAR (i.types[3]); | |
4136 | i.reg_operands -= 2; | |
4137 | ||
4138 | /* Specify the modrm encoding and remember the register | |
4139 | including the high bit normally stored in the REX | |
4140 | byte. */ | |
4141 | i.drex.modrm_reg = 2; | |
4142 | i.drex.modrm_regmem = 1; | |
4143 | i.drex.reg = (i.op[3].regs->reg_num | |
4144 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4145 | } | |
4146 | ||
4147 | else | |
4148 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4149 | i.tm.name); | |
4150 | } | |
4151 | ||
4152 | /* SSE5 3 operand instructions that the result is a register, being | |
4153 | either operand can be a memory operand, using OC0 to note which | |
4154 | one is the memory. */ | |
4155 | else if (i.tm.opcode_modifier.drex | |
4156 | && i.tm.opcode_modifier.drexv | |
4157 | && i.operands == 3) | |
4158 | { | |
4159 | i.tm.extension_opcode = None; | |
4160 | ||
4161 | /* Case 1: 3 operand insn, src1 = register. */ | |
4162 | if (i.types[0].bitfield.regxmm != 0 | |
4163 | && i.types[1].bitfield.regxmm != 0 | |
4164 | && i.types[2].bitfield.regxmm != 0) | |
4165 | { | |
4166 | /* Clear the arguments that are stored in drex. */ | |
4167 | UINTS_CLEAR (i.types[2]); | |
4168 | i.reg_operands--; | |
4169 | ||
4170 | /* Specify the modrm encoding and remember the register | |
4171 | including the high bit normally stored in the REX byte. */ | |
4172 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4173 | i.drex.modrm_reg = 1; | |
4174 | i.drex.modrm_regmem = 0; | |
4175 | i.drex.reg = (i.op[2].regs->reg_num | |
4176 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4177 | } | |
4178 | ||
4179 | /* Case 2: 3 operand insn, src1 = memory. */ | |
4180 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4181 | && i.types[1].bitfield.regxmm != 0 | |
4182 | && i.types[2].bitfield.regxmm != 0) | |
4183 | { | |
4184 | /* Clear the arguments that are stored in drex. */ | |
4185 | UINTS_CLEAR (i.types[2]); | |
4186 | i.reg_operands--; | |
4187 | ||
4188 | /* Specify the modrm encoding and remember the register | |
4189 | including the high bit normally stored in the REX | |
4190 | byte. */ | |
4191 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4192 | i.drex.modrm_reg = 1; | |
4193 | i.drex.modrm_regmem = 0; | |
4194 | i.drex.reg = (i.op[2].regs->reg_num | |
4195 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4196 | } | |
4197 | ||
4198 | /* Case 3: 3 operand insn, src2 = memory. */ | |
4199 | else if (i.types[0].bitfield.regxmm != 0 | |
4200 | && operand_type_check (i.types[1], anymem) != 0 | |
4201 | && i.types[2].bitfield.regxmm != 0) | |
4202 | { | |
4203 | /* Clear the arguments that are stored in drex. */ | |
4204 | UINTS_CLEAR (i.types[2]); | |
4205 | i.reg_operands--; | |
4206 | ||
4207 | /* Specify the modrm encoding and remember the register | |
4208 | including the high bit normally stored in the REX byte. */ | |
4209 | i.tm.extension_opcode = DREX_X1_XMEM_X2; | |
4210 | i.drex.modrm_reg = 0; | |
4211 | i.drex.modrm_regmem = 1; | |
4212 | i.drex.reg = (i.op[2].regs->reg_num | |
4213 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4214 | } | |
4215 | ||
4216 | else | |
4217 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4218 | i.tm.name); | |
4219 | } | |
4220 | ||
4221 | /* SSE5 4 operand instructions that are the comparison instructions | |
4222 | where the first operand is the immediate value of the comparison | |
4223 | to be done. */ | |
4224 | else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4) | |
4225 | { | |
4226 | /* Case 1: 4 operand insn, src1 = reg/memory. */ | |
4227 | if (operand_type_check (i.types[0], imm) != 0 | |
4228 | && (i.types[1].bitfield.regxmm | |
4229 | || operand_type_check (i.types[1], anymem)) | |
4230 | && i.types[2].bitfield.regxmm != 0 | |
4231 | && i.types[3].bitfield.regxmm != 0) | |
4232 | { | |
4233 | /* clear the arguments that are stored in drex */ | |
4234 | UINTS_CLEAR (i.types[3]); | |
4235 | i.reg_operands--; | |
4236 | ||
4237 | /* Specify the modrm encoding and remember the register | |
4238 | including the high bit normally stored in the REX byte. */ | |
4239 | i.drex.modrm_reg = 2; | |
4240 | i.drex.modrm_regmem = 1; | |
4241 | i.drex.reg = (i.op[3].regs->reg_num | |
4242 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4243 | } | |
4244 | ||
4245 | /* Case 2: 3 operand insn with ImmExt that places the | |
4246 | opcode_extension as an immediate argument. This is used for | |
4247 | all of the varients of comparison that supplies the appropriate | |
4248 | value as part of the instruction. */ | |
4249 | else if ((i.types[0].bitfield.regxmm | |
4250 | || operand_type_check (i.types[0], anymem)) | |
4251 | && i.types[1].bitfield.regxmm != 0 | |
4252 | && i.types[2].bitfield.regxmm != 0 | |
4253 | && operand_type_check (i.types[3], imm) != 0) | |
4254 | { | |
4255 | /* clear the arguments that are stored in drex */ | |
4256 | UINTS_CLEAR (i.types[2]); | |
4257 | i.reg_operands--; | |
4258 | ||
4259 | /* Specify the modrm encoding and remember the register | |
4260 | including the high bit normally stored in the REX byte. */ | |
4261 | i.drex.modrm_reg = 1; | |
4262 | i.drex.modrm_regmem = 0; | |
4263 | i.drex.reg = (i.op[2].regs->reg_num | |
4264 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4265 | } | |
4266 | ||
4267 | else | |
4268 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4269 | i.tm.name); | |
4270 | } | |
4271 | ||
4272 | else if (i.tm.opcode_modifier.drex | |
4273 | || i.tm.opcode_modifier.drexv | |
4274 | || i.tm.opcode_modifier.drexc) | |
4275 | as_bad (_("Internal error for the '%s' instruction"), i.tm.name); | |
4276 | } | |
4277 | ||
29b0f896 | 4278 | static int |
e3bb37b5 | 4279 | process_operands (void) |
29b0f896 AM |
4280 | { |
4281 | /* Default segment register this instruction will use for memory | |
4282 | accesses. 0 means unknown. This is only for optimizing out | |
4283 | unnecessary segment overrides. */ | |
4284 | const seg_entry *default_seg = 0; | |
4285 | ||
85f10a01 MM |
4286 | /* Handle all of the DREX munging that SSE5 needs. */ |
4287 | if (i.tm.opcode_modifier.drex | |
4288 | || i.tm.opcode_modifier.drexv | |
4289 | || i.tm.opcode_modifier.drexc) | |
4290 | process_drex (); | |
4291 | ||
e2ec9d29 | 4292 | if (i.tm.opcode_modifier.firstxmm0) |
29b0f896 | 4293 | { |
9fcfb3d7 L |
4294 | unsigned int j; |
4295 | ||
e2ec9d29 L |
4296 | /* The first operand is implicit and must be xmm0. */ |
4297 | assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm)); | |
4298 | if (i.op[0].regs->reg_num != 0) | |
4299 | { | |
4300 | if (intel_syntax) | |
4301 | as_bad (_("the last operand of `%s' must be `%sxmm0'"), | |
4302 | i.tm.name, register_prefix); | |
4303 | else | |
4304 | as_bad (_("the first operand of `%s' must be `%sxmm0'"), | |
4305 | i.tm.name, register_prefix); | |
4306 | return 0; | |
4307 | } | |
9fcfb3d7 L |
4308 | |
4309 | for (j = 1; j < i.operands; j++) | |
4310 | { | |
4311 | i.op[j - 1] = i.op[j]; | |
4312 | i.types[j - 1] = i.types[j]; | |
4313 | ||
4314 | /* We need to adjust fields in i.tm since they are used by | |
4315 | build_modrm_byte. */ | |
4316 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
4317 | } | |
4318 | ||
e2ec9d29 L |
4319 | i.operands--; |
4320 | i.reg_operands--; | |
e2ec9d29 L |
4321 | i.tm.operands--; |
4322 | } | |
4323 | else if (i.tm.opcode_modifier.regkludge) | |
4324 | { | |
4325 | /* The imul $imm, %reg instruction is converted into | |
4326 | imul $imm, %reg, %reg, and the clr %reg instruction | |
4327 | is converted into xor %reg, %reg. */ | |
4328 | ||
4329 | unsigned int first_reg_op; | |
4330 | ||
4331 | if (operand_type_check (i.types[0], reg)) | |
4332 | first_reg_op = 0; | |
4333 | else | |
4334 | first_reg_op = 1; | |
4335 | /* Pretend we saw the extra register operand. */ | |
4336 | assert (i.reg_operands == 1 | |
4337 | && i.op[first_reg_op + 1].regs == 0); | |
4338 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
4339 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
4340 | i.operands++; | |
4341 | i.reg_operands++; | |
29b0f896 AM |
4342 | } |
4343 | ||
40fb9820 | 4344 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 4345 | { |
40fb9820 L |
4346 | if (i.types[0].bitfield.sreg2 |
4347 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 4348 | { |
4eed87de AM |
4349 | if (i.tm.base_opcode == POP_SEG_SHORT |
4350 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 4351 | { |
4eed87de AM |
4352 | as_bad (_("you can't `pop %%cs'")); |
4353 | return 0; | |
29b0f896 | 4354 | } |
4eed87de AM |
4355 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
4356 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4357 | i.rex |= REX_B; |
4eed87de AM |
4358 | } |
4359 | else | |
4360 | { | |
85f10a01 MM |
4361 | /* The register or float register operand is in operand |
4362 | 0 or 1. */ | |
40fb9820 L |
4363 | unsigned int op; |
4364 | ||
4365 | if (i.types[0].bitfield.floatreg | |
4366 | || operand_type_check (i.types[0], reg)) | |
4367 | op = 0; | |
4368 | else | |
4369 | op = 1; | |
4eed87de AM |
4370 | /* Register goes in low 3 bits of opcode. */ |
4371 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
4372 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4373 | i.rex |= REX_B; |
40fb9820 | 4374 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 4375 | { |
4eed87de AM |
4376 | /* Warn about some common errors, but press on regardless. |
4377 | The first case can be generated by gcc (<= 2.8.1). */ | |
4378 | if (i.operands == 2) | |
4379 | { | |
4380 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d L |
4381 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
4382 | register_prefix, i.op[1].regs->reg_name, | |
4383 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de AM |
4384 | } |
4385 | else | |
4386 | { | |
4387 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
4388 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
4389 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 4390 | } |
29b0f896 AM |
4391 | } |
4392 | } | |
4393 | } | |
40fb9820 | 4394 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
4395 | { |
4396 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
4397 | must be put into the modrm byte). Now, we make the modrm and |
4398 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
4399 | |
4400 | default_seg = build_modrm_byte (); | |
4401 | } | |
8a2ed489 | 4402 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
4403 | { |
4404 | default_seg = &ds; | |
4405 | } | |
40fb9820 | 4406 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
4407 | { |
4408 | /* For the string instructions that allow a segment override | |
4409 | on one of their operands, the default segment is ds. */ | |
4410 | default_seg = &ds; | |
4411 | } | |
4412 | ||
75178d9d L |
4413 | if (i.tm.base_opcode == 0x8d /* lea */ |
4414 | && i.seg[0] | |
4415 | && !quiet_warnings) | |
30123838 | 4416 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
4417 | |
4418 | /* If a segment was explicitly specified, and the specified segment | |
4419 | is not the default, use an opcode prefix to select it. If we | |
4420 | never figured out what the default segment is, then default_seg | |
4421 | will be zero at this point, and the specified segment prefix will | |
4422 | always be used. */ | |
29b0f896 AM |
4423 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
4424 | { | |
4425 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
4426 | return 0; | |
4427 | } | |
4428 | return 1; | |
4429 | } | |
4430 | ||
4431 | static const seg_entry * | |
e3bb37b5 | 4432 | build_modrm_byte (void) |
29b0f896 AM |
4433 | { |
4434 | const seg_entry *default_seg = 0; | |
4435 | ||
85f10a01 MM |
4436 | /* SSE5 4 operand instructions are encoded in such a way that one of |
4437 | the inputs must match the destination register. Process_drex hides | |
4438 | the 3rd argument in the drex field, so that by the time we get | |
4439 | here, it looks to GAS as if this is a 2 operand instruction. */ | |
4440 | if ((i.tm.opcode_modifier.drex | |
4441 | || i.tm.opcode_modifier.drexv | |
b5016f89 | 4442 | || i.tm.opcode_modifier.drexc) |
85f10a01 MM |
4443 | && i.reg_operands == 2) |
4444 | { | |
4445 | const reg_entry *reg = i.op[i.drex.modrm_reg].regs; | |
4446 | const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs; | |
4447 | ||
4448 | i.rm.reg = reg->reg_num; | |
4449 | i.rm.regmem = regmem->reg_num; | |
4450 | i.rm.mode = 3; | |
4451 | if ((reg->reg_flags & RegRex) != 0) | |
4452 | i.rex |= REX_R; | |
4453 | if ((regmem->reg_flags & RegRex) != 0) | |
4454 | i.rex |= REX_B; | |
4455 | } | |
4456 | ||
29b0f896 AM |
4457 | /* i.reg_operands MUST be the number of real register operands; |
4458 | implicit registers do not count. */ | |
85f10a01 | 4459 | else if (i.reg_operands == 2) |
29b0f896 AM |
4460 | { |
4461 | unsigned int source, dest; | |
cab737b9 L |
4462 | |
4463 | switch (i.operands) | |
4464 | { | |
4465 | case 2: | |
4466 | source = 0; | |
4467 | break; | |
4468 | case 3: | |
c81128dc L |
4469 | /* When there are 3 operands, one of them may be immediate, |
4470 | which may be the first or the last operand. Otherwise, | |
4471 | the first operand must be shift count register (cl). */ | |
4472 | assert (i.imm_operands == 1 | |
4473 | || (i.imm_operands == 0 | |
40fb9820 L |
4474 | && i.types[0].bitfield.shiftcount)); |
4475 | if (operand_type_check (i.types[0], imm) | |
4476 | || i.types[0].bitfield.shiftcount) | |
4477 | source = 1; | |
4478 | else | |
4479 | source = 0; | |
cab737b9 L |
4480 | break; |
4481 | case 4: | |
368d64cc L |
4482 | /* When there are 4 operands, the first two must be 8bit |
4483 | immediate operands. The source operand will be the 3rd | |
4484 | one. */ | |
cab737b9 | 4485 | assert (i.imm_operands == 2 |
368d64cc L |
4486 | && i.types[0].bitfield.imm8 |
4487 | && i.types[1].bitfield.imm8); | |
cab737b9 L |
4488 | source = 2; |
4489 | break; | |
4490 | default: | |
4491 | abort (); | |
4492 | } | |
4493 | ||
29b0f896 AM |
4494 | dest = source + 1; |
4495 | ||
4496 | i.rm.mode = 3; | |
4497 | /* One of the register operands will be encoded in the i.tm.reg | |
4498 | field, the other in the combined i.tm.mode and i.tm.regmem | |
4499 | fields. If no form of this instruction supports a memory | |
4500 | destination operand, then we assume the source operand may | |
4501 | sometimes be a memory operand and so we need to store the | |
4502 | destination in the i.rm.reg field. */ | |
40fb9820 L |
4503 | if (!i.tm.operand_types[dest].bitfield.regmem |
4504 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
4505 | { |
4506 | i.rm.reg = i.op[dest].regs->reg_num; | |
4507 | i.rm.regmem = i.op[source].regs->reg_num; | |
4508 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4509 | i.rex |= REX_R; |
29b0f896 | 4510 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 4511 | i.rex |= REX_B; |
29b0f896 AM |
4512 | } |
4513 | else | |
4514 | { | |
4515 | i.rm.reg = i.op[source].regs->reg_num; | |
4516 | i.rm.regmem = i.op[dest].regs->reg_num; | |
4517 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4518 | i.rex |= REX_B; |
29b0f896 | 4519 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 4520 | i.rex |= REX_R; |
29b0f896 | 4521 | } |
161a04f6 | 4522 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 4523 | { |
40fb9820 L |
4524 | if (!i.types[0].bitfield.control |
4525 | && !i.types[1].bitfield.control) | |
c4a530c5 | 4526 | abort (); |
161a04f6 | 4527 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
4528 | add_prefix (LOCK_PREFIX_OPCODE); |
4529 | } | |
29b0f896 AM |
4530 | } |
4531 | else | |
4532 | { /* If it's not 2 reg operands... */ | |
4533 | if (i.mem_operands) | |
4534 | { | |
4535 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 4536 | unsigned int op; |
4eed87de | 4537 | |
85f10a01 MM |
4538 | /* This has been precalculated for SSE5 instructions |
4539 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
4540 | if (i.tm.opcode_modifier.drex |
4541 | || i.tm.opcode_modifier.drexv | |
4542 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
4543 | op = i.drex.modrm_regmem; |
4544 | else | |
4545 | { | |
c0209578 L |
4546 | for (op = 0; op < i.operands; op++) |
4547 | if (operand_type_check (i.types[op], anymem)) | |
4548 | break; | |
4549 | assert (op < i.operands); | |
85f10a01 | 4550 | } |
29b0f896 AM |
4551 | |
4552 | default_seg = &ds; | |
4553 | ||
4554 | if (i.base_reg == 0) | |
4555 | { | |
4556 | i.rm.mode = 0; | |
4557 | if (!i.disp_operands) | |
4558 | fake_zero_displacement = 1; | |
4559 | if (i.index_reg == 0) | |
4560 | { | |
4561 | /* Operand is just <disp> */ | |
20f0a1fc | 4562 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
4563 | { |
4564 | /* 64bit mode overwrites the 32bit absolute | |
4565 | addressing by RIP relative addressing and | |
4566 | absolute addressing is encoded by one of the | |
4567 | redundant SIB forms. */ | |
4568 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
4569 | i.sib.base = NO_BASE_REGISTER; | |
4570 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 4571 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 4572 | ? disp32s : disp32); |
20f0a1fc | 4573 | } |
fc225355 L |
4574 | else if ((flag_code == CODE_16BIT) |
4575 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
4576 | { |
4577 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 4578 | i.types[op] = disp16; |
20f0a1fc NC |
4579 | } |
4580 | else | |
4581 | { | |
4582 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 4583 | i.types[op] = disp32; |
29b0f896 AM |
4584 | } |
4585 | } | |
4586 | else /* !i.base_reg && i.index_reg */ | |
4587 | { | |
db51cc60 L |
4588 | if (i.index_reg->reg_num == RegEiz |
4589 | || i.index_reg->reg_num == RegRiz) | |
4590 | i.sib.index = NO_INDEX_REGISTER; | |
4591 | else | |
4592 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
4593 | i.sib.base = NO_BASE_REGISTER; |
4594 | i.sib.scale = i.log2_scale_factor; | |
4595 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
4596 | i.types[op].bitfield.disp8 = 0; |
4597 | i.types[op].bitfield.disp16 = 0; | |
4598 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 4599 | if (flag_code != CODE_64BIT) |
40fb9820 L |
4600 | { |
4601 | /* Must be 32 bit */ | |
4602 | i.types[op].bitfield.disp32 = 1; | |
4603 | i.types[op].bitfield.disp32s = 0; | |
4604 | } | |
29b0f896 | 4605 | else |
40fb9820 L |
4606 | { |
4607 | i.types[op].bitfield.disp32 = 0; | |
4608 | i.types[op].bitfield.disp32s = 1; | |
4609 | } | |
29b0f896 | 4610 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 4611 | i.rex |= REX_X; |
29b0f896 AM |
4612 | } |
4613 | } | |
4614 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
4615 | else if (i.base_reg->reg_num == RegRip || |
4616 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
4617 | { |
4618 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
4619 | i.types[op].bitfield.disp8 = 0; |
4620 | i.types[op].bitfield.disp16 = 0; | |
4621 | i.types[op].bitfield.disp32 = 0; | |
4622 | i.types[op].bitfield.disp32s = 1; | |
4623 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 4624 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
4625 | if (! i.disp_operands) |
4626 | fake_zero_displacement = 1; | |
29b0f896 | 4627 | } |
40fb9820 | 4628 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
4629 | { |
4630 | switch (i.base_reg->reg_num) | |
4631 | { | |
4632 | case 3: /* (%bx) */ | |
4633 | if (i.index_reg == 0) | |
4634 | i.rm.regmem = 7; | |
4635 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
4636 | i.rm.regmem = i.index_reg->reg_num - 6; | |
4637 | break; | |
4638 | case 5: /* (%bp) */ | |
4639 | default_seg = &ss; | |
4640 | if (i.index_reg == 0) | |
4641 | { | |
4642 | i.rm.regmem = 6; | |
40fb9820 | 4643 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
4644 | { |
4645 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 4646 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4647 | fake_zero_displacement = 1; |
29b0f896 AM |
4648 | } |
4649 | } | |
4650 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
4651 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
4652 | break; | |
4653 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
4654 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
4655 | } | |
4656 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
4657 | } | |
4658 | else /* i.base_reg and 32/64 bit mode */ | |
4659 | { | |
4660 | if (flag_code == CODE_64BIT | |
40fb9820 L |
4661 | && operand_type_check (i.types[op], disp)) |
4662 | { | |
4663 | i386_operand_type temp; | |
c6fb90c8 | 4664 | UINTS_CLEAR (temp); |
40fb9820 L |
4665 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
4666 | i.types[op] = temp; | |
4667 | if (i.prefix[ADDR_PREFIX] == 0) | |
4668 | i.types[op].bitfield.disp32s = 1; | |
4669 | else | |
4670 | i.types[op].bitfield.disp32 = 1; | |
4671 | } | |
20f0a1fc | 4672 | |
29b0f896 AM |
4673 | i.rm.regmem = i.base_reg->reg_num; |
4674 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 4675 | i.rex |= REX_B; |
29b0f896 AM |
4676 | i.sib.base = i.base_reg->reg_num; |
4677 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
4678 | complications. */ | |
4679 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
4680 | { | |
4681 | default_seg = &ss; | |
4682 | if (i.disp_operands == 0) | |
4683 | { | |
4684 | fake_zero_displacement = 1; | |
40fb9820 | 4685 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
4686 | } |
4687 | } | |
4688 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
4689 | { | |
4690 | default_seg = &ss; | |
4691 | } | |
4692 | i.sib.scale = i.log2_scale_factor; | |
4693 | if (i.index_reg == 0) | |
4694 | { | |
4695 | /* <disp>(%esp) becomes two byte modrm with no index | |
4696 | register. We've already stored the code for esp | |
4697 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
4698 | Any base register besides %esp will not use the | |
4699 | extra modrm byte. */ | |
4700 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
4701 | } |
4702 | else | |
4703 | { | |
db51cc60 L |
4704 | if (i.index_reg->reg_num == RegEiz |
4705 | || i.index_reg->reg_num == RegRiz) | |
4706 | i.sib.index = NO_INDEX_REGISTER; | |
4707 | else | |
4708 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
4709 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
4710 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 4711 | i.rex |= REX_X; |
29b0f896 | 4712 | } |
67a4f2b7 AO |
4713 | |
4714 | if (i.disp_operands | |
4715 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
4716 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
4717 | i.rm.mode = 0; | |
4718 | else | |
4719 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 4720 | } |
252b5132 | 4721 | |
29b0f896 AM |
4722 | if (fake_zero_displacement) |
4723 | { | |
4724 | /* Fakes a zero displacement assuming that i.types[op] | |
4725 | holds the correct displacement size. */ | |
4726 | expressionS *exp; | |
4727 | ||
4728 | assert (i.op[op].disps == 0); | |
4729 | exp = &disp_expressions[i.disp_operands++]; | |
4730 | i.op[op].disps = exp; | |
4731 | exp->X_op = O_constant; | |
4732 | exp->X_add_number = 0; | |
4733 | exp->X_add_symbol = (symbolS *) 0; | |
4734 | exp->X_op_symbol = (symbolS *) 0; | |
4735 | } | |
4736 | } | |
252b5132 | 4737 | |
29b0f896 AM |
4738 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
4739 | (if any) based on i.tm.extension_opcode. Again, we must be | |
4740 | careful to make sure that segment/control/debug/test/MMX | |
4741 | registers are coded into the i.rm.reg field. */ | |
4742 | if (i.reg_operands) | |
4743 | { | |
99018f42 L |
4744 | unsigned int op; |
4745 | ||
85f10a01 MM |
4746 | /* This has been precalculated for SSE5 instructions |
4747 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
4748 | if (i.tm.opcode_modifier.drex |
4749 | || i.tm.opcode_modifier.drexv | |
4750 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
4751 | { |
4752 | op = i.drex.modrm_reg; | |
4753 | i.rm.reg = i.op[op].regs->reg_num; | |
4754 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
4755 | i.rex |= REX_R; | |
4756 | } | |
4757 | else | |
4758 | { | |
c0209578 L |
4759 | for (op = 0; op < i.operands; op++) |
4760 | if (i.types[op].bitfield.reg8 | |
4761 | || i.types[op].bitfield.reg16 | |
4762 | || i.types[op].bitfield.reg32 | |
4763 | || i.types[op].bitfield.reg64 | |
4764 | || i.types[op].bitfield.regmmx | |
4765 | || i.types[op].bitfield.regxmm | |
4766 | || i.types[op].bitfield.sreg2 | |
4767 | || i.types[op].bitfield.sreg3 | |
4768 | || i.types[op].bitfield.control | |
4769 | || i.types[op].bitfield.debug | |
4770 | || i.types[op].bitfield.test) | |
4771 | break; | |
4772 | ||
4773 | assert (op < i.operands); | |
99018f42 | 4774 | |
85f10a01 MM |
4775 | /* If there is an extension opcode to put here, the |
4776 | register number must be put into the regmem field. */ | |
c0209578 L |
4777 | if (i.tm.extension_opcode != None) |
4778 | { | |
4779 | i.rm.regmem = i.op[op].regs->reg_num; | |
4780 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
4781 | i.rex |= REX_B; | |
4782 | } | |
4783 | else | |
4784 | { | |
4785 | i.rm.reg = i.op[op].regs->reg_num; | |
4786 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
4787 | i.rex |= REX_R; | |
4788 | } | |
85f10a01 | 4789 | } |
252b5132 | 4790 | |
29b0f896 AM |
4791 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
4792 | must set it to 3 to indicate this is a register operand | |
4793 | in the regmem field. */ | |
4794 | if (!i.mem_operands) | |
4795 | i.rm.mode = 3; | |
4796 | } | |
252b5132 | 4797 | |
29b0f896 | 4798 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
85f10a01 MM |
4799 | if (i.tm.extension_opcode != None |
4800 | && !(i.tm.opcode_modifier.drex | |
4801 | || i.tm.opcode_modifier.drexv | |
4802 | || i.tm.opcode_modifier.drexc)) | |
29b0f896 AM |
4803 | i.rm.reg = i.tm.extension_opcode; |
4804 | } | |
4805 | return default_seg; | |
4806 | } | |
252b5132 | 4807 | |
29b0f896 | 4808 | static void |
e3bb37b5 | 4809 | output_branch (void) |
29b0f896 AM |
4810 | { |
4811 | char *p; | |
4812 | int code16; | |
4813 | int prefix; | |
4814 | relax_substateT subtype; | |
4815 | symbolS *sym; | |
4816 | offsetT off; | |
4817 | ||
4818 | code16 = 0; | |
4819 | if (flag_code == CODE_16BIT) | |
4820 | code16 = CODE16; | |
4821 | ||
4822 | prefix = 0; | |
4823 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 4824 | { |
29b0f896 AM |
4825 | prefix = 1; |
4826 | i.prefixes -= 1; | |
4827 | code16 ^= CODE16; | |
252b5132 | 4828 | } |
29b0f896 AM |
4829 | /* Pentium4 branch hints. */ |
4830 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
4831 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 4832 | { |
29b0f896 AM |
4833 | prefix++; |
4834 | i.prefixes--; | |
4835 | } | |
4836 | if (i.prefix[REX_PREFIX] != 0) | |
4837 | { | |
4838 | prefix++; | |
4839 | i.prefixes--; | |
2f66722d AM |
4840 | } |
4841 | ||
29b0f896 AM |
4842 | if (i.prefixes != 0 && !intel_syntax) |
4843 | as_warn (_("skipping prefixes on this instruction")); | |
4844 | ||
4845 | /* It's always a symbol; End frag & setup for relax. | |
4846 | Make sure there is enough room in this frag for the largest | |
4847 | instruction we may generate in md_convert_frag. This is 2 | |
4848 | bytes for the opcode and room for the prefix and largest | |
4849 | displacement. */ | |
4850 | frag_grow (prefix + 2 + 4); | |
4851 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
4852 | p = frag_more (prefix + 1); | |
4853 | if (i.prefix[DATA_PREFIX] != 0) | |
4854 | *p++ = DATA_PREFIX_OPCODE; | |
4855 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
4856 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
4857 | *p++ = i.prefix[SEG_PREFIX]; | |
4858 | if (i.prefix[REX_PREFIX] != 0) | |
4859 | *p++ = i.prefix[REX_PREFIX]; | |
4860 | *p = i.tm.base_opcode; | |
4861 | ||
4862 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
4863 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
40fb9820 | 4864 | else if (cpu_arch_flags.bitfield.cpui386) |
29b0f896 AM |
4865 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); |
4866 | else | |
4867 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
4868 | subtype |= code16; | |
3e73aa7c | 4869 | |
29b0f896 AM |
4870 | sym = i.op[0].disps->X_add_symbol; |
4871 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 4872 | |
29b0f896 AM |
4873 | if (i.op[0].disps->X_op != O_constant |
4874 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 4875 | { |
29b0f896 AM |
4876 | /* Handle complex expressions. */ |
4877 | sym = make_expr_symbol (i.op[0].disps); | |
4878 | off = 0; | |
4879 | } | |
3e73aa7c | 4880 | |
29b0f896 AM |
4881 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
4882 | Pass reloc in fr_var. */ | |
4883 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
4884 | } | |
3e73aa7c | 4885 | |
29b0f896 | 4886 | static void |
e3bb37b5 | 4887 | output_jump (void) |
29b0f896 AM |
4888 | { |
4889 | char *p; | |
4890 | int size; | |
3e02c1cc | 4891 | fixS *fixP; |
29b0f896 | 4892 | |
40fb9820 | 4893 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
4894 | { |
4895 | /* This is a loop or jecxz type instruction. */ | |
4896 | size = 1; | |
4897 | if (i.prefix[ADDR_PREFIX] != 0) | |
4898 | { | |
4899 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
4900 | i.prefixes -= 1; | |
4901 | } | |
4902 | /* Pentium4 branch hints. */ | |
4903 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
4904 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
4905 | { | |
4906 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
4907 | i.prefixes--; | |
3e73aa7c JH |
4908 | } |
4909 | } | |
29b0f896 AM |
4910 | else |
4911 | { | |
4912 | int code16; | |
3e73aa7c | 4913 | |
29b0f896 AM |
4914 | code16 = 0; |
4915 | if (flag_code == CODE_16BIT) | |
4916 | code16 = CODE16; | |
3e73aa7c | 4917 | |
29b0f896 AM |
4918 | if (i.prefix[DATA_PREFIX] != 0) |
4919 | { | |
4920 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
4921 | i.prefixes -= 1; | |
4922 | code16 ^= CODE16; | |
4923 | } | |
252b5132 | 4924 | |
29b0f896 AM |
4925 | size = 4; |
4926 | if (code16) | |
4927 | size = 2; | |
4928 | } | |
9fcc94b6 | 4929 | |
29b0f896 AM |
4930 | if (i.prefix[REX_PREFIX] != 0) |
4931 | { | |
4932 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
4933 | i.prefixes -= 1; | |
4934 | } | |
252b5132 | 4935 | |
29b0f896 AM |
4936 | if (i.prefixes != 0 && !intel_syntax) |
4937 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 4938 | |
29b0f896 AM |
4939 | p = frag_more (1 + size); |
4940 | *p++ = i.tm.base_opcode; | |
e0890092 | 4941 | |
3e02c1cc AM |
4942 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
4943 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
4944 | ||
4945 | /* All jumps handled here are signed, but don't use a signed limit | |
4946 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
4947 | 4G and 64k respectively. */ | |
4948 | if (size == 1) | |
4949 | fixP->fx_signed = 1; | |
29b0f896 | 4950 | } |
e0890092 | 4951 | |
29b0f896 | 4952 | static void |
e3bb37b5 | 4953 | output_interseg_jump (void) |
29b0f896 AM |
4954 | { |
4955 | char *p; | |
4956 | int size; | |
4957 | int prefix; | |
4958 | int code16; | |
252b5132 | 4959 | |
29b0f896 AM |
4960 | code16 = 0; |
4961 | if (flag_code == CODE_16BIT) | |
4962 | code16 = CODE16; | |
a217f122 | 4963 | |
29b0f896 AM |
4964 | prefix = 0; |
4965 | if (i.prefix[DATA_PREFIX] != 0) | |
4966 | { | |
4967 | prefix = 1; | |
4968 | i.prefixes -= 1; | |
4969 | code16 ^= CODE16; | |
4970 | } | |
4971 | if (i.prefix[REX_PREFIX] != 0) | |
4972 | { | |
4973 | prefix++; | |
4974 | i.prefixes -= 1; | |
4975 | } | |
252b5132 | 4976 | |
29b0f896 AM |
4977 | size = 4; |
4978 | if (code16) | |
4979 | size = 2; | |
252b5132 | 4980 | |
29b0f896 AM |
4981 | if (i.prefixes != 0 && !intel_syntax) |
4982 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 4983 | |
29b0f896 AM |
4984 | /* 1 opcode; 2 segment; offset */ |
4985 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 4986 | |
29b0f896 AM |
4987 | if (i.prefix[DATA_PREFIX] != 0) |
4988 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 4989 | |
29b0f896 AM |
4990 | if (i.prefix[REX_PREFIX] != 0) |
4991 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 4992 | |
29b0f896 AM |
4993 | *p++ = i.tm.base_opcode; |
4994 | if (i.op[1].imms->X_op == O_constant) | |
4995 | { | |
4996 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 4997 | |
29b0f896 AM |
4998 | if (size == 2 |
4999 | && !fits_in_unsigned_word (n) | |
5000 | && !fits_in_signed_word (n)) | |
5001 | { | |
5002 | as_bad (_("16-bit jump out of range")); | |
5003 | return; | |
5004 | } | |
5005 | md_number_to_chars (p, n, size); | |
5006 | } | |
5007 | else | |
5008 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5009 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5010 | if (i.op[0].imms->X_op != O_constant) | |
5011 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5012 | i.tm.name); | |
5013 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5014 | } | |
a217f122 | 5015 | |
29b0f896 | 5016 | static void |
e3bb37b5 | 5017 | output_insn (void) |
29b0f896 | 5018 | { |
2bbd9c25 JJ |
5019 | fragS *insn_start_frag; |
5020 | offsetT insn_start_off; | |
5021 | ||
29b0f896 AM |
5022 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5023 | We can't do this after the insn has been output as the current | |
5024 | frag may have been closed off. eg. by frag_var. */ | |
5025 | dwarf2_emit_insn (0); | |
5026 | ||
2bbd9c25 JJ |
5027 | insn_start_frag = frag_now; |
5028 | insn_start_off = frag_now_fix (); | |
5029 | ||
29b0f896 | 5030 | /* Output jumps. */ |
40fb9820 | 5031 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5032 | output_branch (); |
40fb9820 L |
5033 | else if (i.tm.opcode_modifier.jumpbyte |
5034 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5035 | output_jump (); |
40fb9820 | 5036 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5037 | output_interseg_jump (); |
5038 | else | |
5039 | { | |
5040 | /* Output normal instructions here. */ | |
5041 | char *p; | |
5042 | unsigned char *q; | |
47465058 | 5043 | unsigned int j; |
331d2d0d | 5044 | unsigned int prefix; |
4dffcebc L |
5045 | |
5046 | switch (i.tm.opcode_length) | |
bc4bd9ab | 5047 | { |
4dffcebc | 5048 | case 3: |
331d2d0d L |
5049 | if (i.tm.base_opcode & 0xff000000) |
5050 | { | |
5051 | prefix = (i.tm.base_opcode >> 24) & 0xff; | |
5052 | goto check_prefix; | |
5053 | } | |
4dffcebc L |
5054 | break; |
5055 | case 2: | |
5056 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
bc4bd9ab | 5057 | { |
4dffcebc L |
5058 | prefix = (i.tm.base_opcode >> 16) & 0xff; |
5059 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
5060 | { | |
5061 | check_prefix: | |
5062 | if (prefix != REPE_PREFIX_OPCODE | |
5063 | || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) | |
5064 | add_prefix (prefix); | |
5065 | } | |
5066 | else | |
bc4bd9ab MK |
5067 | add_prefix (prefix); |
5068 | } | |
4dffcebc L |
5069 | break; |
5070 | case 1: | |
5071 | break; | |
5072 | default: | |
5073 | abort (); | |
0f10071e | 5074 | } |
252b5132 | 5075 | |
29b0f896 | 5076 | /* The prefix bytes. */ |
47465058 L |
5077 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) |
5078 | if (*q) | |
5079 | FRAG_APPEND_1_CHAR (*q); | |
252b5132 | 5080 | |
29b0f896 | 5081 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 5082 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
5083 | { |
5084 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
5085 | } | |
5086 | else | |
5087 | { | |
4dffcebc | 5088 | switch (i.tm.opcode_length) |
331d2d0d | 5089 | { |
4dffcebc | 5090 | case 3: |
331d2d0d L |
5091 | p = frag_more (3); |
5092 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
5093 | break; |
5094 | case 2: | |
5095 | p = frag_more (2); | |
5096 | break; | |
5097 | default: | |
5098 | abort (); | |
5099 | break; | |
331d2d0d | 5100 | } |
0f10071e | 5101 | |
29b0f896 AM |
5102 | /* Put out high byte first: can't use md_number_to_chars! */ |
5103 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
5104 | *p = i.tm.base_opcode & 0xff; | |
85f10a01 MM |
5105 | |
5106 | /* On SSE5, encode the OC1 bit in the DREX field if this | |
5107 | encoding has multiple formats. */ | |
5108 | if (i.tm.opcode_modifier.drex | |
5109 | && i.tm.opcode_modifier.drexv | |
5110 | && DREX_OC1 (i.tm.extension_opcode)) | |
5111 | *p |= DREX_OC1_MASK; | |
29b0f896 | 5112 | } |
3e73aa7c | 5113 | |
29b0f896 | 5114 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 5115 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 5116 | { |
4a3523fa L |
5117 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
5118 | | i.rm.reg << 3 | |
5119 | | i.rm.mode << 6)); | |
29b0f896 AM |
5120 | /* If i.rm.regmem == ESP (4) |
5121 | && i.rm.mode != (Register mode) | |
5122 | && not 16 bit | |
5123 | ==> need second modrm byte. */ | |
5124 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
5125 | && i.rm.mode != 3 | |
40fb9820 | 5126 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
5127 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
5128 | | i.sib.index << 3 | |
5129 | | i.sib.scale << 6)); | |
29b0f896 | 5130 | } |
3e73aa7c | 5131 | |
85f10a01 MM |
5132 | /* Write the DREX byte if needed. */ |
5133 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
5134 | { | |
5135 | p = frag_more (1); | |
5136 | *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7)); | |
5137 | ||
5138 | /* Encode the OC0 bit if this encoding has multiple | |
5139 | formats. */ | |
5140 | if ((i.tm.opcode_modifier.drex | |
5141 | || i.tm.opcode_modifier.drexv) | |
5142 | && DREX_OC0 (i.tm.extension_opcode)) | |
5143 | *p |= DREX_OC0_MASK; | |
5144 | } | |
5145 | ||
29b0f896 | 5146 | if (i.disp_operands) |
2bbd9c25 | 5147 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 5148 | |
29b0f896 | 5149 | if (i.imm_operands) |
2bbd9c25 | 5150 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 5151 | } |
252b5132 | 5152 | |
29b0f896 AM |
5153 | #ifdef DEBUG386 |
5154 | if (flag_debug) | |
5155 | { | |
7b81dfbb | 5156 | pi ("" /*line*/, &i); |
29b0f896 AM |
5157 | } |
5158 | #endif /* DEBUG386 */ | |
5159 | } | |
252b5132 | 5160 | |
e205caa7 L |
5161 | /* Return the size of the displacement operand N. */ |
5162 | ||
5163 | static int | |
5164 | disp_size (unsigned int n) | |
5165 | { | |
5166 | int size = 4; | |
40fb9820 L |
5167 | if (i.types[n].bitfield.disp64) |
5168 | size = 8; | |
5169 | else if (i.types[n].bitfield.disp8) | |
5170 | size = 1; | |
5171 | else if (i.types[n].bitfield.disp16) | |
5172 | size = 2; | |
e205caa7 L |
5173 | return size; |
5174 | } | |
5175 | ||
5176 | /* Return the size of the immediate operand N. */ | |
5177 | ||
5178 | static int | |
5179 | imm_size (unsigned int n) | |
5180 | { | |
5181 | int size = 4; | |
40fb9820 L |
5182 | if (i.types[n].bitfield.imm64) |
5183 | size = 8; | |
5184 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
5185 | size = 1; | |
5186 | else if (i.types[n].bitfield.imm16) | |
5187 | size = 2; | |
e205caa7 L |
5188 | return size; |
5189 | } | |
5190 | ||
29b0f896 | 5191 | static void |
64e74474 | 5192 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
5193 | { |
5194 | char *p; | |
5195 | unsigned int n; | |
252b5132 | 5196 | |
29b0f896 AM |
5197 | for (n = 0; n < i.operands; n++) |
5198 | { | |
40fb9820 | 5199 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
5200 | { |
5201 | if (i.op[n].disps->X_op == O_constant) | |
5202 | { | |
e205caa7 | 5203 | int size = disp_size (n); |
29b0f896 | 5204 | offsetT val; |
252b5132 | 5205 | |
29b0f896 AM |
5206 | val = offset_in_range (i.op[n].disps->X_add_number, |
5207 | size); | |
5208 | p = frag_more (size); | |
5209 | md_number_to_chars (p, val, size); | |
5210 | } | |
5211 | else | |
5212 | { | |
f86103b7 | 5213 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 5214 | int size = disp_size (n); |
40fb9820 | 5215 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
5216 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
5217 | ||
e205caa7 | 5218 | /* We can't have 8 bit displacement here. */ |
40fb9820 | 5219 | assert (!i.types[n].bitfield.disp8); |
e205caa7 | 5220 | |
29b0f896 AM |
5221 | /* The PC relative address is computed relative |
5222 | to the instruction boundary, so in case immediate | |
5223 | fields follows, we need to adjust the value. */ | |
5224 | if (pcrel && i.imm_operands) | |
5225 | { | |
29b0f896 | 5226 | unsigned int n1; |
e205caa7 | 5227 | int sz = 0; |
252b5132 | 5228 | |
29b0f896 | 5229 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 5230 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 5231 | { |
e205caa7 L |
5232 | /* Only one immediate is allowed for PC |
5233 | relative address. */ | |
5234 | assert (sz == 0); | |
5235 | sz = imm_size (n1); | |
5236 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 5237 | } |
29b0f896 | 5238 | /* We should find the immediate. */ |
e205caa7 | 5239 | assert (sz != 0); |
29b0f896 | 5240 | } |
520dc8e8 | 5241 | |
29b0f896 | 5242 | p = frag_more (size); |
2bbd9c25 | 5243 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 5244 | if (GOT_symbol |
2bbd9c25 | 5245 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 5246 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
5247 | || reloc_type == BFD_RELOC_X86_64_32S |
5248 | || (reloc_type == BFD_RELOC_64 | |
5249 | && object_64bit)) | |
d6ab8113 JB |
5250 | && (i.op[n].disps->X_op == O_symbol |
5251 | || (i.op[n].disps->X_op == O_add | |
5252 | && ((symbol_get_value_expression | |
5253 | (i.op[n].disps->X_op_symbol)->X_op) | |
5254 | == O_subtract)))) | |
5255 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
5256 | { |
5257 | offsetT add; | |
5258 | ||
5259 | if (insn_start_frag == frag_now) | |
5260 | add = (p - frag_now->fr_literal) - insn_start_off; | |
5261 | else | |
5262 | { | |
5263 | fragS *fr; | |
5264 | ||
5265 | add = insn_start_frag->fr_fix - insn_start_off; | |
5266 | for (fr = insn_start_frag->fr_next; | |
5267 | fr && fr != frag_now; fr = fr->fr_next) | |
5268 | add += fr->fr_fix; | |
5269 | add += p - frag_now->fr_literal; | |
5270 | } | |
5271 | ||
4fa24527 | 5272 | if (!object_64bit) |
7b81dfbb AJ |
5273 | { |
5274 | reloc_type = BFD_RELOC_386_GOTPC; | |
5275 | i.op[n].imms->X_add_number += add; | |
5276 | } | |
5277 | else if (reloc_type == BFD_RELOC_64) | |
5278 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 5279 | else |
7b81dfbb AJ |
5280 | /* Don't do the adjustment for x86-64, as there |
5281 | the pcrel addressing is relative to the _next_ | |
5282 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 5283 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 5284 | } |
062cd5e7 | 5285 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 5286 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
5287 | } |
5288 | } | |
5289 | } | |
5290 | } | |
252b5132 | 5291 | |
29b0f896 | 5292 | static void |
64e74474 | 5293 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
5294 | { |
5295 | char *p; | |
5296 | unsigned int n; | |
252b5132 | 5297 | |
29b0f896 AM |
5298 | for (n = 0; n < i.operands; n++) |
5299 | { | |
40fb9820 | 5300 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
5301 | { |
5302 | if (i.op[n].imms->X_op == O_constant) | |
5303 | { | |
e205caa7 | 5304 | int size = imm_size (n); |
29b0f896 | 5305 | offsetT val; |
b4cac588 | 5306 | |
29b0f896 AM |
5307 | val = offset_in_range (i.op[n].imms->X_add_number, |
5308 | size); | |
5309 | p = frag_more (size); | |
5310 | md_number_to_chars (p, val, size); | |
5311 | } | |
5312 | else | |
5313 | { | |
5314 | /* Not absolute_section. | |
5315 | Need a 32-bit fixup (don't support 8bit | |
5316 | non-absolute imms). Try to support other | |
5317 | sizes ... */ | |
f86103b7 | 5318 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
5319 | int size = imm_size (n); |
5320 | int sign; | |
29b0f896 | 5321 | |
40fb9820 | 5322 | if (i.types[n].bitfield.imm32s |
a7d61044 | 5323 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 5324 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 5325 | sign = 1; |
e205caa7 L |
5326 | else |
5327 | sign = 0; | |
520dc8e8 | 5328 | |
29b0f896 AM |
5329 | p = frag_more (size); |
5330 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 5331 | |
2bbd9c25 JJ |
5332 | /* This is tough to explain. We end up with this one if we |
5333 | * have operands that look like | |
5334 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
5335 | * obtain the absolute address of the GOT, and it is strongly | |
5336 | * preferable from a performance point of view to avoid using | |
5337 | * a runtime relocation for this. The actual sequence of | |
5338 | * instructions often look something like: | |
5339 | * | |
5340 | * call .L66 | |
5341 | * .L66: | |
5342 | * popl %ebx | |
5343 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
5344 | * | |
5345 | * The call and pop essentially return the absolute address | |
5346 | * of the label .L66 and store it in %ebx. The linker itself | |
5347 | * will ultimately change the first operand of the addl so | |
5348 | * that %ebx points to the GOT, but to keep things simple, the | |
5349 | * .o file must have this operand set so that it generates not | |
5350 | * the absolute address of .L66, but the absolute address of | |
5351 | * itself. This allows the linker itself simply treat a GOTPC | |
5352 | * relocation as asking for a pcrel offset to the GOT to be | |
5353 | * added in, and the addend of the relocation is stored in the | |
5354 | * operand field for the instruction itself. | |
5355 | * | |
5356 | * Our job here is to fix the operand so that it would add | |
5357 | * the correct offset so that %ebx would point to itself. The | |
5358 | * thing that is tricky is that .-.L66 will point to the | |
5359 | * beginning of the instruction, so we need to further modify | |
5360 | * the operand so that it will point to itself. There are | |
5361 | * other cases where you have something like: | |
5362 | * | |
5363 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
5364 | * | |
5365 | * and here no correction would be required. Internally in | |
5366 | * the assembler we treat operands of this form as not being | |
5367 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
5368 | * whether it would simplify matters to do it this way. Who | |
5369 | * knows. In earlier versions of the PIC patches, the | |
5370 | * pcrel_adjust field was used to store the correction, but | |
5371 | * since the expression is not pcrel, I felt it would be | |
5372 | * confusing to do it this way. */ | |
5373 | ||
d6ab8113 | 5374 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
5375 | || reloc_type == BFD_RELOC_X86_64_32S |
5376 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
5377 | && GOT_symbol |
5378 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
5379 | && (i.op[n].imms->X_op == O_symbol | |
5380 | || (i.op[n].imms->X_op == O_add | |
5381 | && ((symbol_get_value_expression | |
5382 | (i.op[n].imms->X_op_symbol)->X_op) | |
5383 | == O_subtract)))) | |
5384 | { | |
2bbd9c25 JJ |
5385 | offsetT add; |
5386 | ||
5387 | if (insn_start_frag == frag_now) | |
5388 | add = (p - frag_now->fr_literal) - insn_start_off; | |
5389 | else | |
5390 | { | |
5391 | fragS *fr; | |
5392 | ||
5393 | add = insn_start_frag->fr_fix - insn_start_off; | |
5394 | for (fr = insn_start_frag->fr_next; | |
5395 | fr && fr != frag_now; fr = fr->fr_next) | |
5396 | add += fr->fr_fix; | |
5397 | add += p - frag_now->fr_literal; | |
5398 | } | |
5399 | ||
4fa24527 | 5400 | if (!object_64bit) |
d6ab8113 | 5401 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 5402 | else if (size == 4) |
d6ab8113 | 5403 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
5404 | else if (size == 8) |
5405 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 5406 | i.op[n].imms->X_add_number += add; |
29b0f896 | 5407 | } |
29b0f896 AM |
5408 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5409 | i.op[n].imms, 0, reloc_type); | |
5410 | } | |
5411 | } | |
5412 | } | |
252b5132 RH |
5413 | } |
5414 | \f | |
d182319b JB |
5415 | /* x86_cons_fix_new is called via the expression parsing code when a |
5416 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
5417 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
5418 | static int cons_sign = -1; | |
5419 | ||
5420 | void | |
e3bb37b5 | 5421 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 5422 | expressionS *exp) |
d182319b JB |
5423 | { |
5424 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
5425 | ||
5426 | got_reloc = NO_RELOC; | |
5427 | ||
5428 | #ifdef TE_PE | |
5429 | if (exp->X_op == O_secrel) | |
5430 | { | |
5431 | exp->X_op = O_symbol; | |
5432 | r = BFD_RELOC_32_SECREL; | |
5433 | } | |
5434 | #endif | |
5435 | ||
5436 | fix_new_exp (frag, off, len, exp, 0, r); | |
5437 | } | |
5438 | ||
718ddfc0 JB |
5439 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
5440 | # define lex_got(reloc, adjust, types) NULL | |
5441 | #else | |
f3c180ae AM |
5442 | /* Parse operands of the form |
5443 | <symbol>@GOTOFF+<nnn> | |
5444 | and similar .plt or .got references. | |
5445 | ||
5446 | If we find one, set up the correct relocation in RELOC and copy the | |
5447 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
5448 | parsing by the calling routine. Return this buffer, and if ADJUST | |
5449 | is non-null set it to the length of the string we removed from the | |
5450 | input line. Otherwise return NULL. */ | |
5451 | static char * | |
3956db08 | 5452 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 | 5453 | int *adjust, |
40fb9820 | 5454 | i386_operand_type *types) |
f3c180ae | 5455 | { |
7b81dfbb AJ |
5456 | /* Some of the relocations depend on the size of what field is to |
5457 | be relocated. But in our callers i386_immediate and i386_displacement | |
5458 | we don't yet know the operand size (this will be set by insn | |
5459 | matching). Hence we record the word32 relocation here, | |
5460 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
5461 | static const struct { |
5462 | const char *str; | |
4fa24527 | 5463 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 5464 | const i386_operand_type types64; |
f3c180ae | 5465 | } gotrel[] = { |
4eed87de AM |
5466 | { "PLTOFF", { 0, |
5467 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 5468 | OPERAND_TYPE_IMM64 }, |
4eed87de AM |
5469 | { "PLT", { BFD_RELOC_386_PLT32, |
5470 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 5471 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5472 | { "GOTPLT", { 0, |
5473 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 5474 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
5475 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, |
5476 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 5477 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
5478 | { "GOTPCREL", { 0, |
5479 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 5480 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5481 | { "TLSGD", { BFD_RELOC_386_TLS_GD, |
5482 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 5483 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5484 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, |
5485 | 0 }, | |
40fb9820 | 5486 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5487 | { "TLSLD", { 0, |
5488 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 5489 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5490 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, |
5491 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 5492 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5493 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, |
5494 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 5495 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
5496 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, |
5497 | 0 }, | |
40fb9820 | 5498 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5499 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, |
5500 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 L |
5501 | |
5502 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
4eed87de AM |
5503 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, |
5504 | 0 }, | |
40fb9820 | 5505 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5506 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, |
5507 | 0 }, | |
40fb9820 | 5508 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5509 | { "GOT", { BFD_RELOC_386_GOT32, |
5510 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 5511 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
4eed87de AM |
5512 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, |
5513 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 5514 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5515 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, |
5516 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 5517 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
5518 | }; |
5519 | char *cp; | |
5520 | unsigned int j; | |
5521 | ||
718ddfc0 JB |
5522 | if (!IS_ELF) |
5523 | return NULL; | |
5524 | ||
f3c180ae | 5525 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 5526 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
5527 | return NULL; |
5528 | ||
47465058 | 5529 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae AM |
5530 | { |
5531 | int len; | |
5532 | ||
5533 | len = strlen (gotrel[j].str); | |
28f81592 | 5534 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 5535 | { |
4fa24527 | 5536 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 5537 | { |
28f81592 AM |
5538 | int first, second; |
5539 | char *tmpbuf, *past_reloc; | |
f3c180ae | 5540 | |
4fa24527 | 5541 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
5542 | if (adjust) |
5543 | *adjust = len; | |
f3c180ae | 5544 | |
3956db08 JB |
5545 | if (types) |
5546 | { | |
5547 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
5548 | { |
5549 | types->bitfield.imm32 = 1; | |
5550 | types->bitfield.disp32 = 1; | |
5551 | } | |
3956db08 JB |
5552 | else |
5553 | *types = gotrel[j].types64; | |
5554 | } | |
5555 | ||
f3c180ae AM |
5556 | if (GOT_symbol == NULL) |
5557 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
5558 | ||
28f81592 | 5559 | /* The length of the first part of our input line. */ |
f3c180ae | 5560 | first = cp - input_line_pointer; |
28f81592 AM |
5561 | |
5562 | /* The second part goes from after the reloc token until | |
67c11a9b | 5563 | (and including) an end_of_line char or comma. */ |
28f81592 | 5564 | past_reloc = cp + 1 + len; |
67c11a9b AM |
5565 | cp = past_reloc; |
5566 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
5567 | ++cp; | |
5568 | second = cp + 1 - past_reloc; | |
28f81592 AM |
5569 | |
5570 | /* Allocate and copy string. The trailing NUL shouldn't | |
5571 | be necessary, but be safe. */ | |
5572 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae | 5573 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
5574 | if (second != 0 && *past_reloc != ' ') |
5575 | /* Replace the relocation token with ' ', so that | |
5576 | errors like foo@GOTOFF1 will be detected. */ | |
5577 | tmpbuf[first++] = ' '; | |
5578 | memcpy (tmpbuf + first, past_reloc, second); | |
5579 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
5580 | return tmpbuf; |
5581 | } | |
5582 | ||
4fa24527 JB |
5583 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
5584 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
5585 | return NULL; |
5586 | } | |
5587 | } | |
5588 | ||
5589 | /* Might be a symbol version string. Don't as_bad here. */ | |
5590 | return NULL; | |
5591 | } | |
5592 | ||
f3c180ae | 5593 | void |
e3bb37b5 | 5594 | x86_cons (expressionS *exp, int size) |
f3c180ae | 5595 | { |
4fa24527 | 5596 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
5597 | { |
5598 | /* Handle @GOTOFF and the like in an expression. */ | |
5599 | char *save; | |
5600 | char *gotfree_input_line; | |
5601 | int adjust; | |
5602 | ||
5603 | save = input_line_pointer; | |
3956db08 | 5604 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
5605 | if (gotfree_input_line) |
5606 | input_line_pointer = gotfree_input_line; | |
5607 | ||
5608 | expression (exp); | |
5609 | ||
5610 | if (gotfree_input_line) | |
5611 | { | |
5612 | /* expression () has merrily parsed up to the end of line, | |
5613 | or a comma - in the wrong buffer. Transfer how far | |
5614 | input_line_pointer has moved to the right buffer. */ | |
5615 | input_line_pointer = (save | |
5616 | + (input_line_pointer - gotfree_input_line) | |
5617 | + adjust); | |
5618 | free (gotfree_input_line); | |
3992d3b7 AM |
5619 | if (exp->X_op == O_constant |
5620 | || exp->X_op == O_absent | |
5621 | || exp->X_op == O_illegal | |
5622 | || exp->X_op == O_register | |
5623 | || exp->X_op == O_big) | |
5624 | { | |
5625 | char c = *input_line_pointer; | |
5626 | *input_line_pointer = 0; | |
5627 | as_bad (_("missing or invalid expression `%s'"), save); | |
5628 | *input_line_pointer = c; | |
5629 | } | |
f3c180ae AM |
5630 | } |
5631 | } | |
5632 | else | |
5633 | expression (exp); | |
5634 | } | |
5635 | #endif | |
5636 | ||
d182319b | 5637 | static void signed_cons (int size) |
6482c264 | 5638 | { |
d182319b JB |
5639 | if (flag_code == CODE_64BIT) |
5640 | cons_sign = 1; | |
5641 | cons (size); | |
5642 | cons_sign = -1; | |
6482c264 NC |
5643 | } |
5644 | ||
d182319b | 5645 | #ifdef TE_PE |
6482c264 NC |
5646 | static void |
5647 | pe_directive_secrel (dummy) | |
5648 | int dummy ATTRIBUTE_UNUSED; | |
5649 | { | |
5650 | expressionS exp; | |
5651 | ||
5652 | do | |
5653 | { | |
5654 | expression (&exp); | |
5655 | if (exp.X_op == O_symbol) | |
5656 | exp.X_op = O_secrel; | |
5657 | ||
5658 | emit_expr (&exp, 4); | |
5659 | } | |
5660 | while (*input_line_pointer++ == ','); | |
5661 | ||
5662 | input_line_pointer--; | |
5663 | demand_empty_rest_of_line (); | |
5664 | } | |
6482c264 NC |
5665 | #endif |
5666 | ||
252b5132 | 5667 | static int |
70e41ade | 5668 | i386_immediate (char *imm_start) |
252b5132 RH |
5669 | { |
5670 | char *save_input_line_pointer; | |
f3c180ae | 5671 | char *gotfree_input_line; |
252b5132 | 5672 | segT exp_seg = 0; |
47926f60 | 5673 | expressionS *exp; |
40fb9820 L |
5674 | i386_operand_type types; |
5675 | ||
c6fb90c8 | 5676 | UINTS_SET (types, ~0); |
252b5132 RH |
5677 | |
5678 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
5679 | { | |
31b2323c L |
5680 | as_bad (_("at most %d immediate operands are allowed"), |
5681 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
5682 | return 0; |
5683 | } | |
5684 | ||
5685 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 5686 | i.op[this_operand].imms = exp; |
252b5132 RH |
5687 | |
5688 | if (is_space_char (*imm_start)) | |
5689 | ++imm_start; | |
5690 | ||
5691 | save_input_line_pointer = input_line_pointer; | |
5692 | input_line_pointer = imm_start; | |
5693 | ||
3956db08 | 5694 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
5695 | if (gotfree_input_line) |
5696 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
5697 | |
5698 | exp_seg = expression (exp); | |
5699 | ||
83183c0c | 5700 | SKIP_WHITESPACE (); |
252b5132 | 5701 | if (*input_line_pointer) |
f3c180ae | 5702 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
5703 | |
5704 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
5705 | if (gotfree_input_line) |
5706 | free (gotfree_input_line); | |
252b5132 | 5707 | |
3992d3b7 AM |
5708 | if (exp->X_op == O_absent |
5709 | || exp->X_op == O_illegal | |
5710 | || exp->X_op == O_big | |
5711 | || (gotfree_input_line | |
5712 | && (exp->X_op == O_constant | |
5713 | || exp->X_op == O_register))) | |
252b5132 | 5714 | { |
3992d3b7 | 5715 | as_bad (_("missing or invalid immediate expression `%s'"), |
24eab124 | 5716 | imm_start); |
3992d3b7 | 5717 | return 0; |
252b5132 | 5718 | } |
3e73aa7c | 5719 | else if (exp->X_op == O_constant) |
252b5132 | 5720 | { |
47926f60 | 5721 | /* Size it properly later. */ |
40fb9820 | 5722 | i.types[this_operand].bitfield.imm64 = 1; |
3e73aa7c | 5723 | /* If BFD64, sign extend val. */ |
4eed87de AM |
5724 | if (!use_rela_relocations |
5725 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
5726 | exp->X_add_number | |
5727 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 5728 | } |
4c63da97 | 5729 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 5730 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 5731 | && exp_seg != absolute_section |
47926f60 | 5732 | && exp_seg != text_section |
24eab124 AM |
5733 | && exp_seg != data_section |
5734 | && exp_seg != bss_section | |
5735 | && exp_seg != undefined_section | |
f86103b7 | 5736 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 5737 | { |
d0b47220 | 5738 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
5739 | return 0; |
5740 | } | |
5741 | #endif | |
bb8f5920 L |
5742 | else if (!intel_syntax && exp->X_op == O_register) |
5743 | { | |
5744 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
5745 | return 0; | |
5746 | } | |
252b5132 RH |
5747 | else |
5748 | { | |
5749 | /* This is an address. The size of the address will be | |
24eab124 | 5750 | determined later, depending on destination register, |
3e73aa7c | 5751 | suffix, or the default for the section. */ |
40fb9820 L |
5752 | i.types[this_operand].bitfield.imm8 = 1; |
5753 | i.types[this_operand].bitfield.imm16 = 1; | |
5754 | i.types[this_operand].bitfield.imm32 = 1; | |
5755 | i.types[this_operand].bitfield.imm32s = 1; | |
5756 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
5757 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
5758 | types); | |
252b5132 RH |
5759 | } |
5760 | ||
5761 | return 1; | |
5762 | } | |
5763 | ||
551c1ca1 | 5764 | static char * |
e3bb37b5 | 5765 | i386_scale (char *scale) |
252b5132 | 5766 | { |
551c1ca1 AM |
5767 | offsetT val; |
5768 | char *save = input_line_pointer; | |
252b5132 | 5769 | |
551c1ca1 AM |
5770 | input_line_pointer = scale; |
5771 | val = get_absolute_expression (); | |
5772 | ||
5773 | switch (val) | |
252b5132 | 5774 | { |
551c1ca1 | 5775 | case 1: |
252b5132 RH |
5776 | i.log2_scale_factor = 0; |
5777 | break; | |
551c1ca1 | 5778 | case 2: |
252b5132 RH |
5779 | i.log2_scale_factor = 1; |
5780 | break; | |
551c1ca1 | 5781 | case 4: |
252b5132 RH |
5782 | i.log2_scale_factor = 2; |
5783 | break; | |
551c1ca1 | 5784 | case 8: |
252b5132 RH |
5785 | i.log2_scale_factor = 3; |
5786 | break; | |
5787 | default: | |
a724f0f4 JB |
5788 | { |
5789 | char sep = *input_line_pointer; | |
5790 | ||
5791 | *input_line_pointer = '\0'; | |
5792 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5793 | scale); | |
5794 | *input_line_pointer = sep; | |
5795 | input_line_pointer = save; | |
5796 | return NULL; | |
5797 | } | |
252b5132 | 5798 | } |
29b0f896 | 5799 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
5800 | { |
5801 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 5802 | 1 << i.log2_scale_factor); |
252b5132 | 5803 | i.log2_scale_factor = 0; |
252b5132 | 5804 | } |
551c1ca1 AM |
5805 | scale = input_line_pointer; |
5806 | input_line_pointer = save; | |
5807 | return scale; | |
252b5132 RH |
5808 | } |
5809 | ||
252b5132 | 5810 | static int |
e3bb37b5 | 5811 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 5812 | { |
29b0f896 | 5813 | expressionS *exp; |
252b5132 RH |
5814 | segT exp_seg = 0; |
5815 | char *save_input_line_pointer; | |
f3c180ae | 5816 | char *gotfree_input_line; |
40fb9820 L |
5817 | int override; |
5818 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 5819 | int ret; |
252b5132 | 5820 | |
31b2323c L |
5821 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
5822 | { | |
5823 | as_bad (_("at most %d displacement operands are allowed"), | |
5824 | MAX_MEMORY_OPERANDS); | |
5825 | return 0; | |
5826 | } | |
5827 | ||
c6fb90c8 | 5828 | UINTS_CLEAR (bigdisp); |
40fb9820 L |
5829 | if ((i.types[this_operand].bitfield.jumpabsolute) |
5830 | || (!current_templates->start->opcode_modifier.jump | |
5831 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 5832 | { |
40fb9820 | 5833 | bigdisp.bitfield.disp32 = 1; |
e05278af | 5834 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
5835 | if (flag_code == CODE_64BIT) |
5836 | { | |
5837 | if (!override) | |
5838 | { | |
5839 | bigdisp.bitfield.disp32s = 1; | |
5840 | bigdisp.bitfield.disp64 = 1; | |
5841 | } | |
5842 | } | |
5843 | else if ((flag_code == CODE_16BIT) ^ override) | |
5844 | { | |
5845 | bigdisp.bitfield.disp32 = 0; | |
5846 | bigdisp.bitfield.disp16 = 1; | |
5847 | } | |
e05278af JB |
5848 | } |
5849 | else | |
5850 | { | |
5851 | /* For PC-relative branches, the width of the displacement | |
5852 | is dependent upon data size, not address size. */ | |
e05278af | 5853 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
5854 | if (flag_code == CODE_64BIT) |
5855 | { | |
5856 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
5857 | bigdisp.bitfield.disp16 = 1; | |
5858 | else | |
5859 | { | |
5860 | bigdisp.bitfield.disp32 = 1; | |
5861 | bigdisp.bitfield.disp32s = 1; | |
5862 | } | |
5863 | } | |
5864 | else | |
e05278af JB |
5865 | { |
5866 | if (!override) | |
5867 | override = (i.suffix == (flag_code != CODE_16BIT | |
5868 | ? WORD_MNEM_SUFFIX | |
5869 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
5870 | bigdisp.bitfield.disp32 = 1; |
5871 | if ((flag_code == CODE_16BIT) ^ override) | |
5872 | { | |
5873 | bigdisp.bitfield.disp32 = 0; | |
5874 | bigdisp.bitfield.disp16 = 1; | |
5875 | } | |
e05278af | 5876 | } |
e05278af | 5877 | } |
c6fb90c8 L |
5878 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
5879 | bigdisp); | |
252b5132 RH |
5880 | |
5881 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 5882 | i.op[this_operand].disps = exp; |
252b5132 RH |
5883 | i.disp_operands++; |
5884 | save_input_line_pointer = input_line_pointer; | |
5885 | input_line_pointer = disp_start; | |
5886 | END_STRING_AND_SAVE (disp_end); | |
5887 | ||
5888 | #ifndef GCC_ASM_O_HACK | |
5889 | #define GCC_ASM_O_HACK 0 | |
5890 | #endif | |
5891 | #if GCC_ASM_O_HACK | |
5892 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 5893 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 5894 | && displacement_string_end[-1] == '+') |
252b5132 RH |
5895 | { |
5896 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
5897 | constraint within gcc asm statements. |
5898 | For instance: | |
5899 | ||
5900 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
5901 | __asm__ __volatile__ ( \ | |
5902 | "movw %w2,%0\n\t" \ | |
5903 | "movw %w1,2+%0\n\t" \ | |
5904 | "rorl $16,%1\n\t" \ | |
5905 | "movb %b1,4+%0\n\t" \ | |
5906 | "movb %4,5+%0\n\t" \ | |
5907 | "movb $0,6+%0\n\t" \ | |
5908 | "movb %h1,7+%0\n\t" \ | |
5909 | "rorl $16,%1" \ | |
5910 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
5911 | ||
5912 | This works great except that the output assembler ends | |
5913 | up looking a bit weird if it turns out that there is | |
5914 | no offset. You end up producing code that looks like: | |
5915 | ||
5916 | #APP | |
5917 | movw $235,(%eax) | |
5918 | movw %dx,2+(%eax) | |
5919 | rorl $16,%edx | |
5920 | movb %dl,4+(%eax) | |
5921 | movb $137,5+(%eax) | |
5922 | movb $0,6+(%eax) | |
5923 | movb %dh,7+(%eax) | |
5924 | rorl $16,%edx | |
5925 | #NO_APP | |
5926 | ||
47926f60 | 5927 | So here we provide the missing zero. */ |
24eab124 AM |
5928 | |
5929 | *displacement_string_end = '0'; | |
252b5132 RH |
5930 | } |
5931 | #endif | |
3956db08 | 5932 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
5933 | if (gotfree_input_line) |
5934 | input_line_pointer = gotfree_input_line; | |
252b5132 | 5935 | |
24eab124 | 5936 | exp_seg = expression (exp); |
252b5132 | 5937 | |
636c26b0 AM |
5938 | SKIP_WHITESPACE (); |
5939 | if (*input_line_pointer) | |
5940 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
5941 | #if GCC_ASM_O_HACK | |
5942 | RESTORE_END_STRING (disp_end + 1); | |
5943 | #endif | |
636c26b0 | 5944 | input_line_pointer = save_input_line_pointer; |
636c26b0 AM |
5945 | if (gotfree_input_line) |
5946 | free (gotfree_input_line); | |
3992d3b7 | 5947 | ret = 1; |
636c26b0 | 5948 | |
24eab124 AM |
5949 | /* We do this to make sure that the section symbol is in |
5950 | the symbol table. We will ultimately change the relocation | |
47926f60 | 5951 | to be relative to the beginning of the section. */ |
1ae12ab7 | 5952 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
5953 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
5954 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 5955 | { |
636c26b0 | 5956 | if (exp->X_op != O_symbol) |
3992d3b7 | 5957 | goto inv_disp; |
636c26b0 | 5958 | |
e5cb08ac | 5959 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
5960 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
5961 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
5962 | exp->X_op = O_subtract; |
5963 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 5964 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 5965 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
5966 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
5967 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 5968 | else |
29b0f896 | 5969 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 5970 | } |
252b5132 | 5971 | |
3992d3b7 AM |
5972 | else if (exp->X_op == O_absent |
5973 | || exp->X_op == O_illegal | |
5974 | || exp->X_op == O_big | |
5975 | || (gotfree_input_line | |
5976 | && (exp->X_op == O_constant | |
5977 | || exp->X_op == O_register))) | |
2daf4fd8 | 5978 | { |
3992d3b7 AM |
5979 | inv_disp: |
5980 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 5981 | disp_start); |
3992d3b7 | 5982 | ret = 0; |
2daf4fd8 AM |
5983 | } |
5984 | ||
4c63da97 | 5985 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
5986 | else if (exp->X_op != O_constant |
5987 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
5988 | && exp_seg != absolute_section | |
5989 | && exp_seg != text_section | |
5990 | && exp_seg != data_section | |
5991 | && exp_seg != bss_section | |
5992 | && exp_seg != undefined_section | |
5993 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 5994 | { |
d0b47220 | 5995 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 5996 | ret = 0; |
24eab124 | 5997 | } |
252b5132 | 5998 | #endif |
3956db08 | 5999 | |
3992d3b7 AM |
6000 | RESTORE_END_STRING (disp_end); |
6001 | ||
40fb9820 L |
6002 | /* Check if this is a displacement only operand. */ |
6003 | bigdisp = i.types[this_operand]; | |
6004 | bigdisp.bitfield.disp8 = 0; | |
6005 | bigdisp.bitfield.disp16 = 0; | |
6006 | bigdisp.bitfield.disp32 = 0; | |
6007 | bigdisp.bitfield.disp32s = 0; | |
6008 | bigdisp.bitfield.disp64 = 0; | |
c6fb90c8 L |
6009 | if (UINTS_ALL_ZERO (bigdisp)) |
6010 | i.types[this_operand] = operand_type_and (i.types[this_operand], | |
6011 | types); | |
3956db08 | 6012 | |
3992d3b7 | 6013 | return ret; |
252b5132 RH |
6014 | } |
6015 | ||
eecb386c | 6016 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
6017 | Return 1 on success, 0 on a failure. */ |
6018 | ||
252b5132 | 6019 | static int |
e3bb37b5 | 6020 | i386_index_check (const char *operand_string) |
252b5132 | 6021 | { |
3e73aa7c | 6022 | int ok; |
24eab124 | 6023 | #if INFER_ADDR_PREFIX |
eecb386c AM |
6024 | int fudged = 0; |
6025 | ||
24eab124 AM |
6026 | tryprefix: |
6027 | #endif | |
3e73aa7c | 6028 | ok = 1; |
75178d9d | 6029 | if (flag_code == CODE_64BIT) |
64e74474 | 6030 | { |
64e74474 | 6031 | if ((i.base_reg |
40fb9820 L |
6032 | && ((i.prefix[ADDR_PREFIX] == 0 |
6033 | && !i.base_reg->reg_type.bitfield.reg64) | |
6034 | || (i.prefix[ADDR_PREFIX] | |
6035 | && !i.base_reg->reg_type.bitfield.reg32)) | |
6036 | && (i.index_reg | |
9a04903e JB |
6037 | || i.base_reg->reg_num != |
6038 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 6039 | || (i.index_reg |
40fb9820 L |
6040 | && (!i.index_reg->reg_type.bitfield.baseindex |
6041 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
6042 | && i.index_reg->reg_num != RegRiz |
6043 | && !i.index_reg->reg_type.bitfield.reg64 | |
6044 | ) | |
40fb9820 | 6045 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 6046 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 6047 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 6048 | ok = 0; |
3e73aa7c JH |
6049 | } |
6050 | else | |
6051 | { | |
6052 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
6053 | { | |
6054 | /* 16bit checks. */ | |
6055 | if ((i.base_reg | |
40fb9820 L |
6056 | && (!i.base_reg->reg_type.bitfield.reg16 |
6057 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 6058 | || (i.index_reg |
40fb9820 L |
6059 | && (!i.index_reg->reg_type.bitfield.reg16 |
6060 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
6061 | || !(i.base_reg |
6062 | && i.base_reg->reg_num < 6 | |
6063 | && i.index_reg->reg_num >= 6 | |
6064 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
6065 | ok = 0; |
6066 | } | |
6067 | else | |
e5cb08ac | 6068 | { |
3e73aa7c JH |
6069 | /* 32bit checks. */ |
6070 | if ((i.base_reg | |
40fb9820 | 6071 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 6072 | || (i.index_reg |
db51cc60 L |
6073 | && ((!i.index_reg->reg_type.bitfield.reg32 |
6074 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 6075 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 6076 | ok = 0; |
3e73aa7c JH |
6077 | } |
6078 | } | |
6079 | if (!ok) | |
24eab124 AM |
6080 | { |
6081 | #if INFER_ADDR_PREFIX | |
20f0a1fc | 6082 | if (i.prefix[ADDR_PREFIX] == 0) |
24eab124 AM |
6083 | { |
6084 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
6085 | i.prefixes += 1; | |
b23bac36 AM |
6086 | /* Change the size of any displacement too. At most one of |
6087 | Disp16 or Disp32 is set. | |
6088 | FIXME. There doesn't seem to be any real need for separate | |
6089 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 6090 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 6091 | if (flag_code != CODE_64BIT |
40fb9820 L |
6092 | && (i.types[this_operand].bitfield.disp16 |
6093 | || i.types[this_operand].bitfield.disp32)) | |
6094 | i.types[this_operand] | |
c6fb90c8 | 6095 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 6096 | fudged = 1; |
24eab124 AM |
6097 | goto tryprefix; |
6098 | } | |
eecb386c AM |
6099 | if (fudged) |
6100 | as_bad (_("`%s' is not a valid base/index expression"), | |
6101 | operand_string); | |
6102 | else | |
c388dee8 | 6103 | #endif |
eecb386c AM |
6104 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
6105 | operand_string, | |
3e73aa7c | 6106 | flag_code_names[flag_code]); |
24eab124 | 6107 | } |
20f0a1fc | 6108 | return ok; |
24eab124 | 6109 | } |
252b5132 | 6110 | |
252b5132 | 6111 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 6112 | on error. */ |
252b5132 | 6113 | |
252b5132 | 6114 | static int |
e3bb37b5 | 6115 | i386_operand (char *operand_string) |
252b5132 | 6116 | { |
af6bdddf AM |
6117 | const reg_entry *r; |
6118 | char *end_op; | |
24eab124 | 6119 | char *op_string = operand_string; |
252b5132 | 6120 | |
24eab124 | 6121 | if (is_space_char (*op_string)) |
252b5132 RH |
6122 | ++op_string; |
6123 | ||
24eab124 | 6124 | /* We check for an absolute prefix (differentiating, |
47926f60 | 6125 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
6126 | if (*op_string == ABSOLUTE_PREFIX) |
6127 | { | |
6128 | ++op_string; | |
6129 | if (is_space_char (*op_string)) | |
6130 | ++op_string; | |
40fb9820 | 6131 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 6132 | } |
252b5132 | 6133 | |
47926f60 | 6134 | /* Check if operand is a register. */ |
4d1bb795 | 6135 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 6136 | { |
40fb9820 L |
6137 | i386_operand_type temp; |
6138 | ||
24eab124 AM |
6139 | /* Check for a segment override by searching for ':' after a |
6140 | segment register. */ | |
6141 | op_string = end_op; | |
6142 | if (is_space_char (*op_string)) | |
6143 | ++op_string; | |
40fb9820 L |
6144 | if (*op_string == ':' |
6145 | && (r->reg_type.bitfield.sreg2 | |
6146 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
6147 | { |
6148 | switch (r->reg_num) | |
6149 | { | |
6150 | case 0: | |
6151 | i.seg[i.mem_operands] = &es; | |
6152 | break; | |
6153 | case 1: | |
6154 | i.seg[i.mem_operands] = &cs; | |
6155 | break; | |
6156 | case 2: | |
6157 | i.seg[i.mem_operands] = &ss; | |
6158 | break; | |
6159 | case 3: | |
6160 | i.seg[i.mem_operands] = &ds; | |
6161 | break; | |
6162 | case 4: | |
6163 | i.seg[i.mem_operands] = &fs; | |
6164 | break; | |
6165 | case 5: | |
6166 | i.seg[i.mem_operands] = &gs; | |
6167 | break; | |
6168 | } | |
252b5132 | 6169 | |
24eab124 | 6170 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
6171 | ++op_string; |
6172 | if (is_space_char (*op_string)) | |
24eab124 | 6173 | ++op_string; |
252b5132 | 6174 | |
24eab124 AM |
6175 | if (!is_digit_char (*op_string) |
6176 | && !is_identifier_char (*op_string) | |
6177 | && *op_string != '(' | |
6178 | && *op_string != ABSOLUTE_PREFIX) | |
6179 | { | |
6180 | as_bad (_("bad memory operand `%s'"), op_string); | |
6181 | return 0; | |
6182 | } | |
47926f60 | 6183 | /* Handle case of %es:*foo. */ |
24eab124 AM |
6184 | if (*op_string == ABSOLUTE_PREFIX) |
6185 | { | |
6186 | ++op_string; | |
6187 | if (is_space_char (*op_string)) | |
6188 | ++op_string; | |
40fb9820 | 6189 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
6190 | } |
6191 | goto do_memory_reference; | |
6192 | } | |
6193 | if (*op_string) | |
6194 | { | |
d0b47220 | 6195 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
6196 | return 0; |
6197 | } | |
40fb9820 L |
6198 | temp = r->reg_type; |
6199 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
6200 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6201 | temp); | |
520dc8e8 | 6202 | i.op[this_operand].regs = r; |
24eab124 AM |
6203 | i.reg_operands++; |
6204 | } | |
af6bdddf AM |
6205 | else if (*op_string == REGISTER_PREFIX) |
6206 | { | |
6207 | as_bad (_("bad register name `%s'"), op_string); | |
6208 | return 0; | |
6209 | } | |
24eab124 | 6210 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 6211 | { |
24eab124 | 6212 | ++op_string; |
40fb9820 | 6213 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 6214 | { |
d0b47220 | 6215 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
6216 | return 0; |
6217 | } | |
6218 | if (!i386_immediate (op_string)) | |
6219 | return 0; | |
6220 | } | |
6221 | else if (is_digit_char (*op_string) | |
6222 | || is_identifier_char (*op_string) | |
e5cb08ac | 6223 | || *op_string == '(') |
24eab124 | 6224 | { |
47926f60 | 6225 | /* This is a memory reference of some sort. */ |
af6bdddf | 6226 | char *base_string; |
252b5132 | 6227 | |
47926f60 | 6228 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
6229 | char *displacement_string_start; |
6230 | char *displacement_string_end; | |
252b5132 | 6231 | |
24eab124 | 6232 | do_memory_reference: |
24eab124 | 6233 | if ((i.mem_operands == 1 |
40fb9820 | 6234 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
6235 | || i.mem_operands == 2) |
6236 | { | |
6237 | as_bad (_("too many memory references for `%s'"), | |
6238 | current_templates->start->name); | |
6239 | return 0; | |
6240 | } | |
252b5132 | 6241 | |
24eab124 AM |
6242 | /* Check for base index form. We detect the base index form by |
6243 | looking for an ')' at the end of the operand, searching | |
6244 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
6245 | after the '('. */ | |
af6bdddf | 6246 | base_string = op_string + strlen (op_string); |
c3332e24 | 6247 | |
af6bdddf AM |
6248 | --base_string; |
6249 | if (is_space_char (*base_string)) | |
6250 | --base_string; | |
252b5132 | 6251 | |
47926f60 | 6252 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
6253 | displacement_string_start = op_string; |
6254 | displacement_string_end = base_string + 1; | |
252b5132 | 6255 | |
24eab124 AM |
6256 | if (*base_string == ')') |
6257 | { | |
af6bdddf | 6258 | char *temp_string; |
24eab124 AM |
6259 | unsigned int parens_balanced = 1; |
6260 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 6261 | equal, so this loop will not be infinite. */ |
24eab124 AM |
6262 | do |
6263 | { | |
6264 | base_string--; | |
6265 | if (*base_string == ')') | |
6266 | parens_balanced++; | |
6267 | if (*base_string == '(') | |
6268 | parens_balanced--; | |
6269 | } | |
6270 | while (parens_balanced); | |
c3332e24 | 6271 | |
af6bdddf | 6272 | temp_string = base_string; |
c3332e24 | 6273 | |
24eab124 | 6274 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
6275 | ++base_string; |
6276 | if (is_space_char (*base_string)) | |
24eab124 | 6277 | ++base_string; |
252b5132 | 6278 | |
af6bdddf | 6279 | if (*base_string == ',' |
4eed87de AM |
6280 | || ((i.base_reg = parse_register (base_string, &end_op)) |
6281 | != NULL)) | |
252b5132 | 6282 | { |
af6bdddf | 6283 | displacement_string_end = temp_string; |
252b5132 | 6284 | |
40fb9820 | 6285 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 6286 | |
af6bdddf | 6287 | if (i.base_reg) |
24eab124 | 6288 | { |
24eab124 AM |
6289 | base_string = end_op; |
6290 | if (is_space_char (*base_string)) | |
6291 | ++base_string; | |
af6bdddf AM |
6292 | } |
6293 | ||
6294 | /* There may be an index reg or scale factor here. */ | |
6295 | if (*base_string == ',') | |
6296 | { | |
6297 | ++base_string; | |
6298 | if (is_space_char (*base_string)) | |
6299 | ++base_string; | |
6300 | ||
4eed87de AM |
6301 | if ((i.index_reg = parse_register (base_string, &end_op)) |
6302 | != NULL) | |
24eab124 | 6303 | { |
af6bdddf | 6304 | base_string = end_op; |
24eab124 AM |
6305 | if (is_space_char (*base_string)) |
6306 | ++base_string; | |
af6bdddf AM |
6307 | if (*base_string == ',') |
6308 | { | |
6309 | ++base_string; | |
6310 | if (is_space_char (*base_string)) | |
6311 | ++base_string; | |
6312 | } | |
e5cb08ac | 6313 | else if (*base_string != ')') |
af6bdddf | 6314 | { |
4eed87de AM |
6315 | as_bad (_("expecting `,' or `)' " |
6316 | "after index register in `%s'"), | |
af6bdddf AM |
6317 | operand_string); |
6318 | return 0; | |
6319 | } | |
24eab124 | 6320 | } |
af6bdddf | 6321 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 6322 | { |
af6bdddf | 6323 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
6324 | return 0; |
6325 | } | |
252b5132 | 6326 | |
47926f60 | 6327 | /* Check for scale factor. */ |
551c1ca1 | 6328 | if (*base_string != ')') |
af6bdddf | 6329 | { |
551c1ca1 AM |
6330 | char *end_scale = i386_scale (base_string); |
6331 | ||
6332 | if (!end_scale) | |
af6bdddf | 6333 | return 0; |
24eab124 | 6334 | |
551c1ca1 | 6335 | base_string = end_scale; |
af6bdddf AM |
6336 | if (is_space_char (*base_string)) |
6337 | ++base_string; | |
6338 | if (*base_string != ')') | |
6339 | { | |
4eed87de AM |
6340 | as_bad (_("expecting `)' " |
6341 | "after scale factor in `%s'"), | |
af6bdddf AM |
6342 | operand_string); |
6343 | return 0; | |
6344 | } | |
6345 | } | |
6346 | else if (!i.index_reg) | |
24eab124 | 6347 | { |
4eed87de AM |
6348 | as_bad (_("expecting index register or scale factor " |
6349 | "after `,'; got '%c'"), | |
af6bdddf | 6350 | *base_string); |
24eab124 AM |
6351 | return 0; |
6352 | } | |
6353 | } | |
af6bdddf | 6354 | else if (*base_string != ')') |
24eab124 | 6355 | { |
4eed87de AM |
6356 | as_bad (_("expecting `,' or `)' " |
6357 | "after base register in `%s'"), | |
af6bdddf | 6358 | operand_string); |
24eab124 AM |
6359 | return 0; |
6360 | } | |
c3332e24 | 6361 | } |
af6bdddf | 6362 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 6363 | { |
af6bdddf | 6364 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 6365 | return 0; |
c3332e24 | 6366 | } |
24eab124 AM |
6367 | } |
6368 | ||
6369 | /* If there's an expression beginning the operand, parse it, | |
6370 | assuming displacement_string_start and | |
6371 | displacement_string_end are meaningful. */ | |
6372 | if (displacement_string_start != displacement_string_end) | |
6373 | { | |
6374 | if (!i386_displacement (displacement_string_start, | |
6375 | displacement_string_end)) | |
6376 | return 0; | |
6377 | } | |
6378 | ||
6379 | /* Special case for (%dx) while doing input/output op. */ | |
6380 | if (i.base_reg | |
c6fb90c8 | 6381 | && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg) |
24eab124 AM |
6382 | && i.index_reg == 0 |
6383 | && i.log2_scale_factor == 0 | |
6384 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 6385 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 6386 | { |
c6fb90c8 | 6387 | UINTS_CLEAR (i.types[this_operand]); |
40fb9820 | 6388 | i.types[this_operand].bitfield.inoutportreg = 1; |
24eab124 AM |
6389 | return 1; |
6390 | } | |
6391 | ||
eecb386c AM |
6392 | if (i386_index_check (operand_string) == 0) |
6393 | return 0; | |
24eab124 AM |
6394 | i.mem_operands++; |
6395 | } | |
6396 | else | |
ce8a8b2f AM |
6397 | { |
6398 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
6399 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
6400 | output_invalid (*op_string), | |
6401 | this_operand + 1, | |
6402 | op_string); | |
6403 | return 0; | |
6404 | } | |
47926f60 | 6405 | return 1; /* Normal return. */ |
252b5132 RH |
6406 | } |
6407 | \f | |
ee7fcc42 AM |
6408 | /* md_estimate_size_before_relax() |
6409 | ||
6410 | Called just before relax() for rs_machine_dependent frags. The x86 | |
6411 | assembler uses these frags to handle variable size jump | |
6412 | instructions. | |
6413 | ||
6414 | Any symbol that is now undefined will not become defined. | |
6415 | Return the correct fr_subtype in the frag. | |
6416 | Return the initial "guess for variable size of frag" to caller. | |
6417 | The guess is actually the growth beyond the fixed part. Whatever | |
6418 | we do to grow the fixed or variable part contributes to our | |
6419 | returned value. */ | |
6420 | ||
252b5132 RH |
6421 | int |
6422 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
6423 | fragS *fragP; |
6424 | segT segment; | |
252b5132 | 6425 | { |
252b5132 | 6426 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
6427 | check for un-relaxable symbols. On an ELF system, we can't relax |
6428 | an externally visible symbol, because it may be overridden by a | |
6429 | shared library. */ | |
6430 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 6431 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 6432 | || (IS_ELF |
31312f95 AM |
6433 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
6434 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
6435 | #endif |
6436 | ) | |
252b5132 | 6437 | { |
b98ef147 AM |
6438 | /* Symbol is undefined in this segment, or we need to keep a |
6439 | reloc so that weak symbols can be overridden. */ | |
6440 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 6441 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
6442 | unsigned char *opcode; |
6443 | int old_fr_fix; | |
f6af82bd | 6444 | |
ee7fcc42 AM |
6445 | if (fragP->fr_var != NO_RELOC) |
6446 | reloc_type = fragP->fr_var; | |
b98ef147 | 6447 | else if (size == 2) |
f6af82bd AM |
6448 | reloc_type = BFD_RELOC_16_PCREL; |
6449 | else | |
6450 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 6451 | |
ee7fcc42 AM |
6452 | old_fr_fix = fragP->fr_fix; |
6453 | opcode = (unsigned char *) fragP->fr_opcode; | |
6454 | ||
fddf5b5b | 6455 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 6456 | { |
fddf5b5b AM |
6457 | case UNCOND_JUMP: |
6458 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 6459 | opcode[0] = 0xe9; |
252b5132 | 6460 | fragP->fr_fix += size; |
062cd5e7 AS |
6461 | fix_new (fragP, old_fr_fix, size, |
6462 | fragP->fr_symbol, | |
6463 | fragP->fr_offset, 1, | |
6464 | reloc_type); | |
252b5132 RH |
6465 | break; |
6466 | ||
fddf5b5b | 6467 | case COND_JUMP86: |
412167cb AM |
6468 | if (size == 2 |
6469 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
6470 | { |
6471 | /* Negate the condition, and branch past an | |
6472 | unconditional jump. */ | |
6473 | opcode[0] ^= 1; | |
6474 | opcode[1] = 3; | |
6475 | /* Insert an unconditional jump. */ | |
6476 | opcode[2] = 0xe9; | |
6477 | /* We added two extra opcode bytes, and have a two byte | |
6478 | offset. */ | |
6479 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
6480 | fix_new (fragP, old_fr_fix + 2, 2, |
6481 | fragP->fr_symbol, | |
6482 | fragP->fr_offset, 1, | |
6483 | reloc_type); | |
fddf5b5b AM |
6484 | break; |
6485 | } | |
6486 | /* Fall through. */ | |
6487 | ||
6488 | case COND_JUMP: | |
412167cb AM |
6489 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
6490 | { | |
3e02c1cc AM |
6491 | fixS *fixP; |
6492 | ||
412167cb | 6493 | fragP->fr_fix += 1; |
3e02c1cc AM |
6494 | fixP = fix_new (fragP, old_fr_fix, 1, |
6495 | fragP->fr_symbol, | |
6496 | fragP->fr_offset, 1, | |
6497 | BFD_RELOC_8_PCREL); | |
6498 | fixP->fx_signed = 1; | |
412167cb AM |
6499 | break; |
6500 | } | |
93c2a809 | 6501 | |
24eab124 | 6502 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 6503 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 6504 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 6505 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
6506 | /* We've added an opcode byte. */ |
6507 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
6508 | fix_new (fragP, old_fr_fix + 1, size, |
6509 | fragP->fr_symbol, | |
6510 | fragP->fr_offset, 1, | |
6511 | reloc_type); | |
252b5132 | 6512 | break; |
fddf5b5b AM |
6513 | |
6514 | default: | |
6515 | BAD_CASE (fragP->fr_subtype); | |
6516 | break; | |
252b5132 RH |
6517 | } |
6518 | frag_wane (fragP); | |
ee7fcc42 | 6519 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 6520 | } |
93c2a809 | 6521 | |
93c2a809 AM |
6522 | /* Guess size depending on current relax state. Initially the relax |
6523 | state will correspond to a short jump and we return 1, because | |
6524 | the variable part of the frag (the branch offset) is one byte | |
6525 | long. However, we can relax a section more than once and in that | |
6526 | case we must either set fr_subtype back to the unrelaxed state, | |
6527 | or return the value for the appropriate branch. */ | |
6528 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
6529 | } |
6530 | ||
47926f60 KH |
6531 | /* Called after relax() is finished. |
6532 | ||
6533 | In: Address of frag. | |
6534 | fr_type == rs_machine_dependent. | |
6535 | fr_subtype is what the address relaxed to. | |
6536 | ||
6537 | Out: Any fixSs and constants are set up. | |
6538 | Caller will turn frag into a ".space 0". */ | |
6539 | ||
252b5132 RH |
6540 | void |
6541 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
6542 | bfd *abfd ATTRIBUTE_UNUSED; |
6543 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 6544 | fragS *fragP; |
252b5132 | 6545 | { |
29b0f896 | 6546 | unsigned char *opcode; |
252b5132 | 6547 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
6548 | offsetT target_address; |
6549 | offsetT opcode_address; | |
252b5132 | 6550 | unsigned int extension = 0; |
847f7ad4 | 6551 | offsetT displacement_from_opcode_start; |
252b5132 RH |
6552 | |
6553 | opcode = (unsigned char *) fragP->fr_opcode; | |
6554 | ||
47926f60 | 6555 | /* Address we want to reach in file space. */ |
252b5132 | 6556 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 6557 | |
47926f60 | 6558 | /* Address opcode resides at in file space. */ |
252b5132 RH |
6559 | opcode_address = fragP->fr_address + fragP->fr_fix; |
6560 | ||
47926f60 | 6561 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
6562 | displacement_from_opcode_start = target_address - opcode_address; |
6563 | ||
fddf5b5b | 6564 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 6565 | { |
47926f60 KH |
6566 | /* Don't have to change opcode. */ |
6567 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 6568 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
6569 | } |
6570 | else | |
6571 | { | |
6572 | if (no_cond_jump_promotion | |
6573 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
6574 | as_warn_where (fragP->fr_file, fragP->fr_line, |
6575 | _("long jump required")); | |
252b5132 | 6576 | |
fddf5b5b AM |
6577 | switch (fragP->fr_subtype) |
6578 | { | |
6579 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
6580 | extension = 4; /* 1 opcode + 4 displacement */ | |
6581 | opcode[0] = 0xe9; | |
6582 | where_to_put_displacement = &opcode[1]; | |
6583 | break; | |
252b5132 | 6584 | |
fddf5b5b AM |
6585 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
6586 | extension = 2; /* 1 opcode + 2 displacement */ | |
6587 | opcode[0] = 0xe9; | |
6588 | where_to_put_displacement = &opcode[1]; | |
6589 | break; | |
252b5132 | 6590 | |
fddf5b5b AM |
6591 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
6592 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
6593 | extension = 5; /* 2 opcode + 4 displacement */ | |
6594 | opcode[1] = opcode[0] + 0x10; | |
6595 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
6596 | where_to_put_displacement = &opcode[2]; | |
6597 | break; | |
252b5132 | 6598 | |
fddf5b5b AM |
6599 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
6600 | extension = 3; /* 2 opcode + 2 displacement */ | |
6601 | opcode[1] = opcode[0] + 0x10; | |
6602 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
6603 | where_to_put_displacement = &opcode[2]; | |
6604 | break; | |
252b5132 | 6605 | |
fddf5b5b AM |
6606 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
6607 | extension = 4; | |
6608 | opcode[0] ^= 1; | |
6609 | opcode[1] = 3; | |
6610 | opcode[2] = 0xe9; | |
6611 | where_to_put_displacement = &opcode[3]; | |
6612 | break; | |
6613 | ||
6614 | default: | |
6615 | BAD_CASE (fragP->fr_subtype); | |
6616 | break; | |
6617 | } | |
252b5132 | 6618 | } |
fddf5b5b | 6619 | |
7b81dfbb AJ |
6620 | /* If size if less then four we are sure that the operand fits, |
6621 | but if it's 4, then it could be that the displacement is larger | |
6622 | then -/+ 2GB. */ | |
6623 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
6624 | && object_64bit | |
6625 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
6626 | + ((addressT) 1 << 31)) |
6627 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
6628 | { |
6629 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6630 | _("jump target out of range")); | |
6631 | /* Make us emit 0. */ | |
6632 | displacement_from_opcode_start = extension; | |
6633 | } | |
47926f60 | 6634 | /* Now put displacement after opcode. */ |
252b5132 RH |
6635 | md_number_to_chars ((char *) where_to_put_displacement, |
6636 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 6637 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
6638 | fragP->fr_fix += extension; |
6639 | } | |
6640 | \f | |
252b5132 RH |
6641 | /* Apply a fixup (fixS) to segment data, once it has been determined |
6642 | by our caller that we have all the info we need to fix it up. | |
6643 | ||
6644 | On the 386, immediates, displacements, and data pointers are all in | |
6645 | the same (little-endian) format, so we don't need to care about which | |
6646 | we are handling. */ | |
6647 | ||
94f592af | 6648 | void |
55cf6793 | 6649 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
6650 | /* The fix we're to put in. */ |
6651 | fixS *fixP; | |
47926f60 | 6652 | /* Pointer to the value of the bits. */ |
c6682705 | 6653 | valueT *valP; |
47926f60 KH |
6654 | /* Segment fix is from. */ |
6655 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 6656 | { |
94f592af | 6657 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 6658 | valueT value = *valP; |
252b5132 | 6659 | |
f86103b7 | 6660 | #if !defined (TE_Mach) |
93382f6d AM |
6661 | if (fixP->fx_pcrel) |
6662 | { | |
6663 | switch (fixP->fx_r_type) | |
6664 | { | |
5865bb77 ILT |
6665 | default: |
6666 | break; | |
6667 | ||
d6ab8113 JB |
6668 | case BFD_RELOC_64: |
6669 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6670 | break; | |
93382f6d | 6671 | case BFD_RELOC_32: |
ae8887b5 | 6672 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
6673 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
6674 | break; | |
6675 | case BFD_RELOC_16: | |
6676 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6677 | break; | |
6678 | case BFD_RELOC_8: | |
6679 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
6680 | break; | |
6681 | } | |
6682 | } | |
252b5132 | 6683 | |
a161fe53 | 6684 | if (fixP->fx_addsy != NULL |
31312f95 | 6685 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 6686 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
6687 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
6688 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
6689 | && !use_rela_relocations) | |
252b5132 | 6690 | { |
31312f95 AM |
6691 | /* This is a hack. There should be a better way to handle this. |
6692 | This covers for the fact that bfd_install_relocation will | |
6693 | subtract the current location (for partial_inplace, PC relative | |
6694 | relocations); see more below. */ | |
252b5132 | 6695 | #ifndef OBJ_AOUT |
718ddfc0 | 6696 | if (IS_ELF |
252b5132 RH |
6697 | #ifdef TE_PE |
6698 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
6699 | #endif | |
6700 | ) | |
6701 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
6702 | #endif | |
6703 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 6704 | if (IS_ELF) |
252b5132 | 6705 | { |
6539b54b | 6706 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 6707 | |
6539b54b | 6708 | if ((sym_seg == seg |
2f66722d | 6709 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 6710 | && sym_seg != absolute_section)) |
ae6063d4 | 6711 | && !generic_force_reloc (fixP)) |
2f66722d AM |
6712 | { |
6713 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
6714 | bfd_install_relocation subtracts them out again. I think |
6715 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
6716 | it. FIXME. */ |
6717 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
6718 | } | |
252b5132 RH |
6719 | } |
6720 | #endif | |
6721 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
6722 | /* For some reason, the PE format does not store a |
6723 | section address offset for a PC relative symbol. */ | |
6724 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 6725 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
6726 | value += md_pcrel_from (fixP); |
6727 | #endif | |
6728 | } | |
6729 | ||
6730 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 6731 | and we must not disappoint it. */ |
252b5132 | 6732 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 6733 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
6734 | switch (fixP->fx_r_type) |
6735 | { | |
6736 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 6737 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
6738 | /* Make the jump instruction point to the address of the operand. At |
6739 | runtime we merely add the offset to the actual PLT entry. */ | |
6740 | value = -4; | |
6741 | break; | |
31312f95 | 6742 | |
13ae64f3 JJ |
6743 | case BFD_RELOC_386_TLS_GD: |
6744 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 6745 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
6746 | case BFD_RELOC_386_TLS_IE: |
6747 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 6748 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
6749 | case BFD_RELOC_X86_64_TLSGD: |
6750 | case BFD_RELOC_X86_64_TLSLD: | |
6751 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 6752 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
6753 | value = 0; /* Fully resolved at runtime. No addend. */ |
6754 | /* Fallthrough */ | |
6755 | case BFD_RELOC_386_TLS_LE: | |
6756 | case BFD_RELOC_386_TLS_LDO_32: | |
6757 | case BFD_RELOC_386_TLS_LE_32: | |
6758 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 6759 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 6760 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 6761 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
6762 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
6763 | break; | |
6764 | ||
67a4f2b7 AO |
6765 | case BFD_RELOC_386_TLS_DESC_CALL: |
6766 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
6767 | value = 0; /* Fully resolved at runtime. No addend. */ | |
6768 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6769 | fixP->fx_done = 0; | |
6770 | return; | |
6771 | ||
00f7efb6 JJ |
6772 | case BFD_RELOC_386_GOT32: |
6773 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
6774 | value = 0; /* Fully resolved at runtime. No addend. */ |
6775 | break; | |
47926f60 KH |
6776 | |
6777 | case BFD_RELOC_VTABLE_INHERIT: | |
6778 | case BFD_RELOC_VTABLE_ENTRY: | |
6779 | fixP->fx_done = 0; | |
94f592af | 6780 | return; |
47926f60 KH |
6781 | |
6782 | default: | |
6783 | break; | |
6784 | } | |
6785 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 6786 | *valP = value; |
f86103b7 | 6787 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 6788 | |
3e73aa7c | 6789 | /* Are we finished with this relocation now? */ |
c6682705 | 6790 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
6791 | fixP->fx_done = 1; |
6792 | else if (use_rela_relocations) | |
6793 | { | |
6794 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
6795 | /* Remember value for tc_gen_reloc. */ |
6796 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
6797 | value = 0; |
6798 | } | |
f86103b7 | 6799 | |
94f592af | 6800 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 6801 | } |
252b5132 | 6802 | \f |
252b5132 | 6803 | char * |
499ac353 | 6804 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 6805 | { |
499ac353 NC |
6806 | /* This outputs the LITTLENUMs in REVERSE order; |
6807 | in accord with the bigendian 386. */ | |
6808 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
6809 | } |
6810 | \f | |
2d545b82 | 6811 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 6812 | |
252b5132 | 6813 | static char * |
e3bb37b5 | 6814 | output_invalid (int c) |
252b5132 | 6815 | { |
3882b010 | 6816 | if (ISPRINT (c)) |
f9f21a03 L |
6817 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
6818 | "'%c'", c); | |
252b5132 | 6819 | else |
f9f21a03 | 6820 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 6821 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
6822 | return output_invalid_buf; |
6823 | } | |
6824 | ||
af6bdddf | 6825 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
6826 | |
6827 | static const reg_entry * | |
4d1bb795 | 6828 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 6829 | { |
af6bdddf AM |
6830 | char *s = reg_string; |
6831 | char *p; | |
252b5132 RH |
6832 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
6833 | const reg_entry *r; | |
6834 | ||
6835 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
6836 | if (*s == REGISTER_PREFIX) | |
6837 | ++s; | |
6838 | ||
6839 | if (is_space_char (*s)) | |
6840 | ++s; | |
6841 | ||
6842 | p = reg_name_given; | |
af6bdddf | 6843 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
6844 | { |
6845 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
6846 | return (const reg_entry *) NULL; |
6847 | s++; | |
252b5132 RH |
6848 | } |
6849 | ||
6588847e DN |
6850 | /* For naked regs, make sure that we are not dealing with an identifier. |
6851 | This prevents confusing an identifier like `eax_var' with register | |
6852 | `eax'. */ | |
6853 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
6854 | return (const reg_entry *) NULL; | |
6855 | ||
af6bdddf | 6856 | *end_op = s; |
252b5132 RH |
6857 | |
6858 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
6859 | ||
5f47d35b | 6860 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 6861 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 6862 | { |
5f47d35b AM |
6863 | if (is_space_char (*s)) |
6864 | ++s; | |
6865 | if (*s == '(') | |
6866 | { | |
af6bdddf | 6867 | ++s; |
5f47d35b AM |
6868 | if (is_space_char (*s)) |
6869 | ++s; | |
6870 | if (*s >= '0' && *s <= '7') | |
6871 | { | |
db557034 | 6872 | int fpr = *s - '0'; |
af6bdddf | 6873 | ++s; |
5f47d35b AM |
6874 | if (is_space_char (*s)) |
6875 | ++s; | |
6876 | if (*s == ')') | |
6877 | { | |
6878 | *end_op = s + 1; | |
db557034 AM |
6879 | r = hash_find (reg_hash, "st(0)"); |
6880 | know (r); | |
6881 | return r + fpr; | |
5f47d35b | 6882 | } |
5f47d35b | 6883 | } |
47926f60 | 6884 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
6885 | return (const reg_entry *) NULL; |
6886 | } | |
6887 | } | |
6888 | ||
db51cc60 L |
6889 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
6890 | if (r != NULL | |
6891 | && !allow_index_reg | |
6892 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) | |
6893 | return (const reg_entry *) NULL; | |
6894 | ||
1ae00879 | 6895 | if (r != NULL |
d946b91f | 6896 | && ((r->reg_flags & (RegRex64 | RegRex)) |
40fb9820 L |
6897 | || r->reg_type.bitfield.reg64) |
6898 | && (!cpu_arch_flags.bitfield.cpulm | |
c6fb90c8 | 6899 | || !UINTS_EQUAL (r->reg_type, control)) |
1ae00879 | 6900 | && flag_code != CODE_64BIT) |
20f0a1fc | 6901 | return (const reg_entry *) NULL; |
1ae00879 | 6902 | |
252b5132 RH |
6903 | return r; |
6904 | } | |
4d1bb795 JB |
6905 | |
6906 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
6907 | ||
6908 | static const reg_entry * | |
6909 | parse_register (char *reg_string, char **end_op) | |
6910 | { | |
6911 | const reg_entry *r; | |
6912 | ||
6913 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
6914 | r = parse_real_register (reg_string, end_op); | |
6915 | else | |
6916 | r = NULL; | |
6917 | if (!r) | |
6918 | { | |
6919 | char *save = input_line_pointer; | |
6920 | char c; | |
6921 | symbolS *symbolP; | |
6922 | ||
6923 | input_line_pointer = reg_string; | |
6924 | c = get_symbol_end (); | |
6925 | symbolP = symbol_find (reg_string); | |
6926 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
6927 | { | |
6928 | const expressionS *e = symbol_get_value_expression (symbolP); | |
6929 | ||
6930 | know (e->X_op == O_register); | |
4eed87de | 6931 | know (e->X_add_number >= 0 |
c3fe08fa | 6932 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
6933 | r = i386_regtab + e->X_add_number; |
6934 | *end_op = input_line_pointer; | |
6935 | } | |
6936 | *input_line_pointer = c; | |
6937 | input_line_pointer = save; | |
6938 | } | |
6939 | return r; | |
6940 | } | |
6941 | ||
6942 | int | |
6943 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
6944 | { | |
6945 | const reg_entry *r; | |
6946 | char *end = input_line_pointer; | |
6947 | ||
6948 | *end = *nextcharP; | |
6949 | r = parse_register (name, &input_line_pointer); | |
6950 | if (r && end <= input_line_pointer) | |
6951 | { | |
6952 | *nextcharP = *input_line_pointer; | |
6953 | *input_line_pointer = 0; | |
6954 | e->X_op = O_register; | |
6955 | e->X_add_number = r - i386_regtab; | |
6956 | return 1; | |
6957 | } | |
6958 | input_line_pointer = end; | |
6959 | *end = 0; | |
6960 | return 0; | |
6961 | } | |
6962 | ||
6963 | void | |
6964 | md_operand (expressionS *e) | |
6965 | { | |
6966 | if (*input_line_pointer == REGISTER_PREFIX) | |
6967 | { | |
6968 | char *end; | |
6969 | const reg_entry *r = parse_real_register (input_line_pointer, &end); | |
6970 | ||
6971 | if (r) | |
6972 | { | |
6973 | e->X_op = O_register; | |
6974 | e->X_add_number = r - i386_regtab; | |
6975 | input_line_pointer = end; | |
6976 | } | |
6977 | } | |
6978 | } | |
6979 | ||
252b5132 | 6980 | \f |
4cc782b5 | 6981 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 6982 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 6983 | #else |
12b55ccc | 6984 | const char *md_shortopts = "qn"; |
252b5132 | 6985 | #endif |
6e0b89ee | 6986 | |
3e73aa7c | 6987 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
6988 | #define OPTION_64 (OPTION_MD_BASE + 1) |
6989 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
6990 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
6991 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
6992 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
6993 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
6994 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
6995 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
6996 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
b3b91714 | 6997 | |
99ad8390 NC |
6998 | struct option md_longopts[] = |
6999 | { | |
3e73aa7c | 7000 | {"32", no_argument, NULL, OPTION_32}, |
99ad8390 | 7001 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
3e73aa7c | 7002 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 7003 | #endif |
b3b91714 | 7004 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
7005 | {"march", required_argument, NULL, OPTION_MARCH}, |
7006 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
7007 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
7008 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
7009 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
7010 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
7011 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
252b5132 RH |
7012 | {NULL, no_argument, NULL, 0} |
7013 | }; | |
7014 | size_t md_longopts_size = sizeof (md_longopts); | |
7015 | ||
7016 | int | |
9103f4f4 | 7017 | md_parse_option (int c, char *arg) |
252b5132 | 7018 | { |
9103f4f4 L |
7019 | unsigned int i; |
7020 | ||
252b5132 RH |
7021 | switch (c) |
7022 | { | |
12b55ccc L |
7023 | case 'n': |
7024 | optimize_align_code = 0; | |
7025 | break; | |
7026 | ||
a38cf1db AM |
7027 | case 'q': |
7028 | quiet_warnings = 1; | |
252b5132 RH |
7029 | break; |
7030 | ||
7031 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
7032 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
7033 | should be emitted or not. FIXME: Not implemented. */ | |
7034 | case 'Q': | |
252b5132 RH |
7035 | break; |
7036 | ||
7037 | /* -V: SVR4 argument to print version ID. */ | |
7038 | case 'V': | |
7039 | print_version_id (); | |
7040 | break; | |
7041 | ||
a38cf1db AM |
7042 | /* -k: Ignore for FreeBSD compatibility. */ |
7043 | case 'k': | |
252b5132 | 7044 | break; |
4cc782b5 ILT |
7045 | |
7046 | case 's': | |
7047 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 7048 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 7049 | break; |
99ad8390 NC |
7050 | #endif |
7051 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) | |
3e73aa7c JH |
7052 | case OPTION_64: |
7053 | { | |
7054 | const char **list, **l; | |
7055 | ||
3e73aa7c JH |
7056 | list = bfd_target_list (); |
7057 | for (l = list; *l != NULL; l++) | |
8620418b | 7058 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
7059 | || strcmp (*l, "coff-x86-64") == 0 |
7060 | || strcmp (*l, "pe-x86-64") == 0 | |
7061 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
7062 | { |
7063 | default_arch = "x86_64"; | |
7064 | break; | |
7065 | } | |
3e73aa7c | 7066 | if (*l == NULL) |
6e0b89ee | 7067 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
7068 | free (list); |
7069 | } | |
7070 | break; | |
7071 | #endif | |
252b5132 | 7072 | |
6e0b89ee AM |
7073 | case OPTION_32: |
7074 | default_arch = "i386"; | |
7075 | break; | |
7076 | ||
b3b91714 AM |
7077 | case OPTION_DIVIDE: |
7078 | #ifdef SVR4_COMMENT_CHARS | |
7079 | { | |
7080 | char *n, *t; | |
7081 | const char *s; | |
7082 | ||
7083 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
7084 | t = n; | |
7085 | for (s = i386_comment_chars; *s != '\0'; s++) | |
7086 | if (*s != '/') | |
7087 | *t++ = *s; | |
7088 | *t = '\0'; | |
7089 | i386_comment_chars = n; | |
7090 | } | |
7091 | #endif | |
7092 | break; | |
7093 | ||
9103f4f4 L |
7094 | case OPTION_MARCH: |
7095 | if (*arg == '.') | |
7096 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7097 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
7098 | { | |
7099 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
7100 | { | |
ccc9c027 | 7101 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 7102 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
7103 | if (!cpu_arch_tune_set) |
7104 | { | |
7105 | cpu_arch_tune = cpu_arch_isa; | |
7106 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
7107 | } | |
9103f4f4 L |
7108 | break; |
7109 | } | |
7110 | } | |
7111 | if (i >= ARRAY_SIZE (cpu_arch)) | |
7112 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7113 | break; | |
7114 | ||
7115 | case OPTION_MTUNE: | |
7116 | if (*arg == '.') | |
7117 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
7118 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
7119 | { | |
7120 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
7121 | { | |
ccc9c027 | 7122 | cpu_arch_tune_set = 1; |
9103f4f4 L |
7123 | cpu_arch_tune = cpu_arch [i].type; |
7124 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
7125 | break; | |
7126 | } | |
7127 | } | |
7128 | if (i >= ARRAY_SIZE (cpu_arch)) | |
7129 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
7130 | break; | |
7131 | ||
1efbbeb4 L |
7132 | case OPTION_MMNEMONIC: |
7133 | if (strcasecmp (arg, "att") == 0) | |
7134 | intel_mnemonic = 0; | |
7135 | else if (strcasecmp (arg, "intel") == 0) | |
7136 | intel_mnemonic = 1; | |
7137 | else | |
7138 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
7139 | break; | |
7140 | ||
7141 | case OPTION_MSYNTAX: | |
7142 | if (strcasecmp (arg, "att") == 0) | |
7143 | intel_syntax = 0; | |
7144 | else if (strcasecmp (arg, "intel") == 0) | |
7145 | intel_syntax = 1; | |
7146 | else | |
7147 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
7148 | break; | |
7149 | ||
7150 | case OPTION_MINDEX_REG: | |
7151 | allow_index_reg = 1; | |
7152 | break; | |
7153 | ||
7154 | case OPTION_MNAKED_REG: | |
7155 | allow_naked_reg = 1; | |
7156 | break; | |
7157 | ||
7158 | case OPTION_MOLD_GCC: | |
7159 | old_gcc = 1; | |
7160 | intel_mnemonic = 0; | |
7161 | break; | |
7162 | ||
252b5132 RH |
7163 | default: |
7164 | return 0; | |
7165 | } | |
7166 | return 1; | |
7167 | } | |
7168 | ||
7169 | void | |
7170 | md_show_usage (stream) | |
7171 | FILE *stream; | |
7172 | { | |
4cc782b5 ILT |
7173 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7174 | fprintf (stream, _("\ | |
a38cf1db AM |
7175 | -Q ignored\n\ |
7176 | -V print assembler version number\n\ | |
b3b91714 AM |
7177 | -k ignored\n")); |
7178 | #endif | |
7179 | fprintf (stream, _("\ | |
12b55ccc | 7180 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
7181 | -q quieten some warnings\n")); |
7182 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
7183 | fprintf (stream, _("\ | |
a38cf1db | 7184 | -s ignored\n")); |
b3b91714 | 7185 | #endif |
751d281c L |
7186 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
7187 | fprintf (stream, _("\ | |
7188 | --32/--64 generate 32bit/64bit code\n")); | |
7189 | #endif | |
b3b91714 AM |
7190 | #ifdef SVR4_COMMENT_CHARS |
7191 | fprintf (stream, _("\ | |
7192 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
7193 | #else |
7194 | fprintf (stream, _("\ | |
b3b91714 | 7195 | --divide ignored\n")); |
4cc782b5 | 7196 | #endif |
9103f4f4 L |
7197 | fprintf (stream, _("\ |
7198 | -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\ | |
7199 | i386, i486, pentium, pentiumpro, pentium4, nocona,\n\ | |
4eed87de | 7200 | core, core2, k6, athlon, k8, generic32, generic64\n")); |
ba104c83 L |
7201 | fprintf (stream, _("\ |
7202 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); | |
7203 | fprintf (stream, _("\ | |
7204 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
7205 | fprintf (stream, _("\ | |
7206 | -mindex-reg support pseudo index registers\n")); | |
7207 | fprintf (stream, _("\ | |
7208 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
7209 | fprintf (stream, _("\ | |
7210 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
7211 | } |
7212 | ||
3e73aa7c | 7213 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
872ce6ff | 7214 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP)) |
252b5132 RH |
7215 | |
7216 | /* Pick the target format to use. */ | |
7217 | ||
47926f60 | 7218 | const char * |
e3bb37b5 | 7219 | i386_target_format (void) |
252b5132 | 7220 | { |
3e73aa7c | 7221 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
7222 | { |
7223 | set_code_flag (CODE_64BIT); | |
c6fb90c8 | 7224 | if (UINTS_ALL_ZERO (cpu_arch_isa_flags)) |
40fb9820 L |
7225 | { |
7226 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
7227 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
7228 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
7229 | cpu_arch_isa_flags.bitfield.cpui486 = 1; | |
7230 | cpu_arch_isa_flags.bitfield.cpui586 = 1; | |
7231 | cpu_arch_isa_flags.bitfield.cpui686 = 1; | |
7232 | cpu_arch_isa_flags.bitfield.cpup4 = 1; | |
7233 | cpu_arch_isa_flags.bitfield.cpummx= 1; | |
7234 | cpu_arch_isa_flags.bitfield.cpummx2 = 1; | |
7235 | cpu_arch_isa_flags.bitfield.cpusse = 1; | |
7236 | cpu_arch_isa_flags.bitfield.cpusse2 = 1; | |
7237 | } | |
c6fb90c8 | 7238 | if (UINTS_ALL_ZERO (cpu_arch_tune_flags)) |
40fb9820 L |
7239 | { |
7240 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
7241 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
7242 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
7243 | cpu_arch_tune_flags.bitfield.cpui486 = 1; | |
7244 | cpu_arch_tune_flags.bitfield.cpui586 = 1; | |
7245 | cpu_arch_tune_flags.bitfield.cpui686 = 1; | |
7246 | cpu_arch_tune_flags.bitfield.cpup4 = 1; | |
7247 | cpu_arch_tune_flags.bitfield.cpummx= 1; | |
7248 | cpu_arch_tune_flags.bitfield.cpummx2 = 1; | |
7249 | cpu_arch_tune_flags.bitfield.cpusse = 1; | |
7250 | cpu_arch_tune_flags.bitfield.cpusse2 = 1; | |
7251 | } | |
9103f4f4 | 7252 | } |
3e73aa7c | 7253 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
7254 | { |
7255 | set_code_flag (CODE_32BIT); | |
c6fb90c8 | 7256 | if (UINTS_ALL_ZERO (cpu_arch_isa_flags)) |
40fb9820 L |
7257 | { |
7258 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
7259 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
7260 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
7261 | } | |
c6fb90c8 | 7262 | if (UINTS_ALL_ZERO (cpu_arch_tune_flags)) |
40fb9820 L |
7263 | { |
7264 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
7265 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
7266 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
7267 | } | |
9103f4f4 | 7268 | } |
3e73aa7c JH |
7269 | else |
7270 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
7271 | switch (OUTPUT_FLAVOR) |
7272 | { | |
872ce6ff L |
7273 | #ifdef TE_PEP |
7274 | case bfd_target_coff_flavour: | |
7275 | return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386"; | |
7276 | break; | |
7277 | #endif | |
4c63da97 AM |
7278 | #ifdef OBJ_MAYBE_AOUT |
7279 | case bfd_target_aout_flavour: | |
47926f60 | 7280 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
7281 | #endif |
7282 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
7283 | case bfd_target_coff_flavour: |
7284 | return "coff-i386"; | |
4c63da97 | 7285 | #endif |
3e73aa7c | 7286 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 7287 | case bfd_target_elf_flavour: |
3e73aa7c | 7288 | { |
e5cb08ac | 7289 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
7290 | { |
7291 | object_64bit = 1; | |
7292 | use_rela_relocations = 1; | |
7293 | } | |
9d7cbccd | 7294 | return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; |
3e73aa7c | 7295 | } |
4c63da97 | 7296 | #endif |
252b5132 RH |
7297 | default: |
7298 | abort (); | |
7299 | return NULL; | |
7300 | } | |
7301 | } | |
7302 | ||
47926f60 | 7303 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
7304 | |
7305 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
7306 | void |
7307 | i386_elf_emit_arch_note (void) | |
a847613f | 7308 | { |
718ddfc0 | 7309 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
7310 | { |
7311 | char *p; | |
7312 | asection *seg = now_seg; | |
7313 | subsegT subseg = now_subseg; | |
7314 | Elf_Internal_Note i_note; | |
7315 | Elf_External_Note e_note; | |
7316 | asection *note_secp; | |
7317 | int len; | |
7318 | ||
7319 | /* Create the .note section. */ | |
7320 | note_secp = subseg_new (".note", 0); | |
7321 | bfd_set_section_flags (stdoutput, | |
7322 | note_secp, | |
7323 | SEC_HAS_CONTENTS | SEC_READONLY); | |
7324 | ||
7325 | /* Process the arch string. */ | |
7326 | len = strlen (cpu_arch_name); | |
7327 | ||
7328 | i_note.namesz = len + 1; | |
7329 | i_note.descsz = 0; | |
7330 | i_note.type = NT_ARCH; | |
7331 | p = frag_more (sizeof (e_note.namesz)); | |
7332 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
7333 | p = frag_more (sizeof (e_note.descsz)); | |
7334 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
7335 | p = frag_more (sizeof (e_note.type)); | |
7336 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
7337 | p = frag_more (len + 1); | |
7338 | strcpy (p, cpu_arch_name); | |
7339 | ||
7340 | frag_align (2, 0, 0); | |
7341 | ||
7342 | subseg_set (seg, subseg); | |
7343 | } | |
7344 | } | |
7345 | #endif | |
252b5132 | 7346 | \f |
252b5132 RH |
7347 | symbolS * |
7348 | md_undefined_symbol (name) | |
7349 | char *name; | |
7350 | { | |
18dc2407 ILT |
7351 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
7352 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
7353 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
7354 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
7355 | { |
7356 | if (!GOT_symbol) | |
7357 | { | |
7358 | if (symbol_find (name)) | |
7359 | as_bad (_("GOT already in symbol table")); | |
7360 | GOT_symbol = symbol_new (name, undefined_section, | |
7361 | (valueT) 0, &zero_address_frag); | |
7362 | }; | |
7363 | return GOT_symbol; | |
7364 | } | |
252b5132 RH |
7365 | return 0; |
7366 | } | |
7367 | ||
7368 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 7369 | |
252b5132 RH |
7370 | valueT |
7371 | md_section_align (segment, size) | |
ab9da554 | 7372 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
7373 | valueT size; |
7374 | { | |
4c63da97 AM |
7375 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
7376 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
7377 | { | |
7378 | /* For a.out, force the section size to be aligned. If we don't do | |
7379 | this, BFD will align it for us, but it will not write out the | |
7380 | final bytes of the section. This may be a bug in BFD, but it is | |
7381 | easier to fix it here since that is how the other a.out targets | |
7382 | work. */ | |
7383 | int align; | |
7384 | ||
7385 | align = bfd_get_section_alignment (stdoutput, segment); | |
7386 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
7387 | } | |
252b5132 RH |
7388 | #endif |
7389 | ||
7390 | return size; | |
7391 | } | |
7392 | ||
7393 | /* On the i386, PC-relative offsets are relative to the start of the | |
7394 | next instruction. That is, the address of the offset, plus its | |
7395 | size, since the offset is always the last part of the insn. */ | |
7396 | ||
7397 | long | |
e3bb37b5 | 7398 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
7399 | { |
7400 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
7401 | } | |
7402 | ||
7403 | #ifndef I386COFF | |
7404 | ||
7405 | static void | |
e3bb37b5 | 7406 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 7407 | { |
29b0f896 | 7408 | int temp; |
252b5132 | 7409 | |
8a75718c JB |
7410 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7411 | if (IS_ELF) | |
7412 | obj_elf_section_change_hook (); | |
7413 | #endif | |
252b5132 RH |
7414 | temp = get_absolute_expression (); |
7415 | subseg_set (bss_section, (subsegT) temp); | |
7416 | demand_empty_rest_of_line (); | |
7417 | } | |
7418 | ||
7419 | #endif | |
7420 | ||
252b5132 | 7421 | void |
e3bb37b5 | 7422 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
7423 | { |
7424 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
7425 | { | |
23df1078 JH |
7426 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
7427 | { | |
4fa24527 | 7428 | if (!object_64bit) |
23df1078 JH |
7429 | abort (); |
7430 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
7431 | } | |
7432 | else | |
7433 | { | |
4fa24527 | 7434 | if (!object_64bit) |
d6ab8113 JB |
7435 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
7436 | else | |
7437 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 7438 | } |
252b5132 RH |
7439 | fixp->fx_subsy = 0; |
7440 | } | |
7441 | } | |
7442 | ||
252b5132 RH |
7443 | arelent * |
7444 | tc_gen_reloc (section, fixp) | |
ab9da554 | 7445 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
7446 | fixS *fixp; |
7447 | { | |
7448 | arelent *rel; | |
7449 | bfd_reloc_code_real_type code; | |
7450 | ||
7451 | switch (fixp->fx_r_type) | |
7452 | { | |
3e73aa7c JH |
7453 | case BFD_RELOC_X86_64_PLT32: |
7454 | case BFD_RELOC_X86_64_GOT32: | |
7455 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
7456 | case BFD_RELOC_386_PLT32: |
7457 | case BFD_RELOC_386_GOT32: | |
7458 | case BFD_RELOC_386_GOTOFF: | |
7459 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
7460 | case BFD_RELOC_386_TLS_GD: |
7461 | case BFD_RELOC_386_TLS_LDM: | |
7462 | case BFD_RELOC_386_TLS_LDO_32: | |
7463 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
7464 | case BFD_RELOC_386_TLS_IE: |
7465 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
7466 | case BFD_RELOC_386_TLS_LE_32: |
7467 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
7468 | case BFD_RELOC_386_TLS_GOTDESC: |
7469 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
7470 | case BFD_RELOC_X86_64_TLSGD: |
7471 | case BFD_RELOC_X86_64_TLSLD: | |
7472 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7473 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
7474 | case BFD_RELOC_X86_64_GOTTPOFF: |
7475 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
7476 | case BFD_RELOC_X86_64_TPOFF64: |
7477 | case BFD_RELOC_X86_64_GOTOFF64: | |
7478 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
7479 | case BFD_RELOC_X86_64_GOT64: |
7480 | case BFD_RELOC_X86_64_GOTPCREL64: | |
7481 | case BFD_RELOC_X86_64_GOTPC64: | |
7482 | case BFD_RELOC_X86_64_GOTPLT64: | |
7483 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
7484 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
7485 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
7486 | case BFD_RELOC_RVA: |
7487 | case BFD_RELOC_VTABLE_ENTRY: | |
7488 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
7489 | #ifdef TE_PE |
7490 | case BFD_RELOC_32_SECREL: | |
7491 | #endif | |
252b5132 RH |
7492 | code = fixp->fx_r_type; |
7493 | break; | |
dbbaec26 L |
7494 | case BFD_RELOC_X86_64_32S: |
7495 | if (!fixp->fx_pcrel) | |
7496 | { | |
7497 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
7498 | code = fixp->fx_r_type; | |
7499 | break; | |
7500 | } | |
252b5132 | 7501 | default: |
93382f6d | 7502 | if (fixp->fx_pcrel) |
252b5132 | 7503 | { |
93382f6d AM |
7504 | switch (fixp->fx_size) |
7505 | { | |
7506 | default: | |
b091f402 AM |
7507 | as_bad_where (fixp->fx_file, fixp->fx_line, |
7508 | _("can not do %d byte pc-relative relocation"), | |
7509 | fixp->fx_size); | |
93382f6d AM |
7510 | code = BFD_RELOC_32_PCREL; |
7511 | break; | |
7512 | case 1: code = BFD_RELOC_8_PCREL; break; | |
7513 | case 2: code = BFD_RELOC_16_PCREL; break; | |
7514 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
7515 | #ifdef BFD64 |
7516 | case 8: code = BFD_RELOC_64_PCREL; break; | |
7517 | #endif | |
93382f6d AM |
7518 | } |
7519 | } | |
7520 | else | |
7521 | { | |
7522 | switch (fixp->fx_size) | |
7523 | { | |
7524 | default: | |
b091f402 AM |
7525 | as_bad_where (fixp->fx_file, fixp->fx_line, |
7526 | _("can not do %d byte relocation"), | |
7527 | fixp->fx_size); | |
93382f6d AM |
7528 | code = BFD_RELOC_32; |
7529 | break; | |
7530 | case 1: code = BFD_RELOC_8; break; | |
7531 | case 2: code = BFD_RELOC_16; break; | |
7532 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 7533 | #ifdef BFD64 |
3e73aa7c | 7534 | case 8: code = BFD_RELOC_64; break; |
937149dd | 7535 | #endif |
93382f6d | 7536 | } |
252b5132 RH |
7537 | } |
7538 | break; | |
7539 | } | |
252b5132 | 7540 | |
d182319b JB |
7541 | if ((code == BFD_RELOC_32 |
7542 | || code == BFD_RELOC_32_PCREL | |
7543 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
7544 | && GOT_symbol |
7545 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 7546 | { |
4fa24527 | 7547 | if (!object_64bit) |
d6ab8113 JB |
7548 | code = BFD_RELOC_386_GOTPC; |
7549 | else | |
7550 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 7551 | } |
7b81dfbb AJ |
7552 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
7553 | && GOT_symbol | |
7554 | && fixp->fx_addsy == GOT_symbol) | |
7555 | { | |
7556 | code = BFD_RELOC_X86_64_GOTPC64; | |
7557 | } | |
252b5132 RH |
7558 | |
7559 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
7560 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
7561 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
7562 | |
7563 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 7564 | |
3e73aa7c JH |
7565 | if (!use_rela_relocations) |
7566 | { | |
7567 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
7568 | vtable entry to be used in the relocation's section offset. */ | |
7569 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
7570 | rel->address = fixp->fx_offset; | |
252b5132 | 7571 | |
c6682705 | 7572 | rel->addend = 0; |
3e73aa7c JH |
7573 | } |
7574 | /* Use the rela in 64bit mode. */ | |
252b5132 | 7575 | else |
3e73aa7c | 7576 | { |
062cd5e7 AS |
7577 | if (!fixp->fx_pcrel) |
7578 | rel->addend = fixp->fx_offset; | |
7579 | else | |
7580 | switch (code) | |
7581 | { | |
7582 | case BFD_RELOC_X86_64_PLT32: | |
7583 | case BFD_RELOC_X86_64_GOT32: | |
7584 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
7585 | case BFD_RELOC_X86_64_TLSGD: |
7586 | case BFD_RELOC_X86_64_TLSLD: | |
7587 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
7588 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
7589 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
7590 | rel->addend = fixp->fx_offset - fixp->fx_size; |
7591 | break; | |
7592 | default: | |
7593 | rel->addend = (section->vma | |
7594 | - fixp->fx_size | |
7595 | + fixp->fx_addnumber | |
7596 | + md_pcrel_from (fixp)); | |
7597 | break; | |
7598 | } | |
3e73aa7c JH |
7599 | } |
7600 | ||
252b5132 RH |
7601 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
7602 | if (rel->howto == NULL) | |
7603 | { | |
7604 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 7605 | _("cannot represent relocation type %s"), |
252b5132 RH |
7606 | bfd_get_reloc_code_name (code)); |
7607 | /* Set howto to a garbage value so that we can keep going. */ | |
7608 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
7609 | assert (rel->howto != NULL); | |
7610 | } | |
7611 | ||
7612 | return rel; | |
7613 | } | |
7614 | ||
64a0c779 DN |
7615 | \f |
7616 | /* Parse operands using Intel syntax. This implements a recursive descent | |
7617 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
7618 | Programmer's Guide. | |
7619 | ||
7620 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
7621 | documentation. In particular, all the structure/union and | |
7622 | high-level macro operands are missing. | |
7623 | ||
7624 | Uppercase words are terminals, lower case words are non-terminals. | |
7625 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
7626 | bars '|' denote choices. Most grammar productions are implemented in | |
7627 | functions called 'intel_<production>'. | |
7628 | ||
7629 | Initial production is 'expr'. | |
7630 | ||
9306ca4a | 7631 | addOp + | - |
64a0c779 DN |
7632 | |
7633 | alpha [a-zA-Z] | |
7634 | ||
9306ca4a JB |
7635 | binOp & | AND | \| | OR | ^ | XOR |
7636 | ||
64a0c779 DN |
7637 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
7638 | ||
7639 | constant digits [[ radixOverride ]] | |
7640 | ||
9306ca4a | 7641 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD |
64a0c779 DN |
7642 | |
7643 | digits decdigit | |
b77a7acd AJ |
7644 | | digits decdigit |
7645 | | digits hexdigit | |
64a0c779 DN |
7646 | |
7647 | decdigit [0-9] | |
7648 | ||
9306ca4a JB |
7649 | e04 e04 addOp e05 |
7650 | | e05 | |
7651 | ||
7652 | e05 e05 binOp e06 | |
b77a7acd | 7653 | | e06 |
64a0c779 DN |
7654 | |
7655 | e06 e06 mulOp e09 | |
b77a7acd | 7656 | | e09 |
64a0c779 DN |
7657 | |
7658 | e09 OFFSET e10 | |
a724f0f4 JB |
7659 | | SHORT e10 |
7660 | | + e10 | |
7661 | | - e10 | |
9306ca4a JB |
7662 | | ~ e10 |
7663 | | NOT e10 | |
64a0c779 DN |
7664 | | e09 PTR e10 |
7665 | | e09 : e10 | |
7666 | | e10 | |
7667 | ||
7668 | e10 e10 [ expr ] | |
b77a7acd | 7669 | | e11 |
64a0c779 DN |
7670 | |
7671 | e11 ( expr ) | |
b77a7acd | 7672 | | [ expr ] |
64a0c779 DN |
7673 | | constant |
7674 | | dataType | |
7675 | | id | |
7676 | | $ | |
7677 | | register | |
7678 | ||
a724f0f4 | 7679 | => expr expr cmpOp e04 |
9306ca4a | 7680 | | e04 |
64a0c779 DN |
7681 | |
7682 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 7683 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
7684 | |
7685 | hexdigit a | b | c | d | e | f | |
b77a7acd | 7686 | | A | B | C | D | E | F |
64a0c779 DN |
7687 | |
7688 | id alpha | |
b77a7acd | 7689 | | id alpha |
64a0c779 DN |
7690 | | id decdigit |
7691 | ||
9306ca4a | 7692 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
64a0c779 DN |
7693 | |
7694 | quote " | ' | |
7695 | ||
7696 | register specialRegister | |
b77a7acd | 7697 | | gpRegister |
64a0c779 DN |
7698 | | byteRegister |
7699 | ||
7700 | segmentRegister CS | DS | ES | FS | GS | SS | |
7701 | ||
9306ca4a | 7702 | specialRegister CR0 | CR2 | CR3 | CR4 |
b77a7acd | 7703 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
7704 | | TR3 | TR4 | TR5 | TR6 | TR7 |
7705 | ||
64a0c779 DN |
7706 | We simplify the grammar in obvious places (e.g., register parsing is |
7707 | done by calling parse_register) and eliminate immediate left recursion | |
7708 | to implement a recursive-descent parser. | |
7709 | ||
a724f0f4 JB |
7710 | expr e04 expr' |
7711 | ||
7712 | expr' cmpOp e04 expr' | |
7713 | | Empty | |
9306ca4a JB |
7714 | |
7715 | e04 e05 e04' | |
7716 | ||
7717 | e04' addOp e05 e04' | |
7718 | | Empty | |
64a0c779 DN |
7719 | |
7720 | e05 e06 e05' | |
7721 | ||
9306ca4a | 7722 | e05' binOp e06 e05' |
b77a7acd | 7723 | | Empty |
64a0c779 DN |
7724 | |
7725 | e06 e09 e06' | |
7726 | ||
7727 | e06' mulOp e09 e06' | |
b77a7acd | 7728 | | Empty |
64a0c779 DN |
7729 | |
7730 | e09 OFFSET e10 e09' | |
a724f0f4 JB |
7731 | | SHORT e10' |
7732 | | + e10' | |
7733 | | - e10' | |
7734 | | ~ e10' | |
7735 | | NOT e10' | |
b77a7acd | 7736 | | e10 e09' |
64a0c779 DN |
7737 | |
7738 | e09' PTR e10 e09' | |
b77a7acd | 7739 | | : e10 e09' |
64a0c779 DN |
7740 | | Empty |
7741 | ||
7742 | e10 e11 e10' | |
7743 | ||
7744 | e10' [ expr ] e10' | |
b77a7acd | 7745 | | Empty |
64a0c779 DN |
7746 | |
7747 | e11 ( expr ) | |
b77a7acd | 7748 | | [ expr ] |
64a0c779 DN |
7749 | | BYTE |
7750 | | WORD | |
7751 | | DWORD | |
9306ca4a | 7752 | | FWORD |
64a0c779 | 7753 | | QWORD |
9306ca4a JB |
7754 | | TBYTE |
7755 | | OWORD | |
7756 | | XMMWORD | |
64a0c779 DN |
7757 | | . |
7758 | | $ | |
7759 | | register | |
7760 | | id | |
7761 | | constant */ | |
7762 | ||
7763 | /* Parsing structure for the intel syntax parser. Used to implement the | |
7764 | semantic actions for the operand grammar. */ | |
7765 | struct intel_parser_s | |
7766 | { | |
7767 | char *op_string; /* The string being parsed. */ | |
7768 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 7769 | int op_modifier; /* Operand modifier. */ |
64a0c779 | 7770 | int is_mem; /* 1 if operand is memory reference. */ |
4eed87de AM |
7771 | int in_offset; /* >=1 if parsing operand of offset. */ |
7772 | int in_bracket; /* >=1 if parsing operand in brackets. */ | |
64a0c779 DN |
7773 | const reg_entry *reg; /* Last register reference found. */ |
7774 | char *disp; /* Displacement string being built. */ | |
a724f0f4 | 7775 | char *next_operand; /* Resume point when splitting operands. */ |
64a0c779 DN |
7776 | }; |
7777 | ||
7778 | static struct intel_parser_s intel_parser; | |
7779 | ||
7780 | /* Token structure for parsing intel syntax. */ | |
7781 | struct intel_token | |
7782 | { | |
7783 | int code; /* Token code. */ | |
7784 | const reg_entry *reg; /* Register entry for register tokens. */ | |
7785 | char *str; /* String representation. */ | |
7786 | }; | |
7787 | ||
7788 | static struct intel_token cur_token, prev_token; | |
7789 | ||
50705ef4 AM |
7790 | /* Token codes for the intel parser. Since T_SHORT is already used |
7791 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
7792 | #define T_NIL -1 |
7793 | #define T_CONST 1 | |
7794 | #define T_REG 2 | |
7795 | #define T_BYTE 3 | |
7796 | #define T_WORD 4 | |
9306ca4a JB |
7797 | #define T_DWORD 5 |
7798 | #define T_FWORD 6 | |
7799 | #define T_QWORD 7 | |
7800 | #define T_TBYTE 8 | |
7801 | #define T_XMMWORD 9 | |
50705ef4 | 7802 | #undef T_SHORT |
9306ca4a JB |
7803 | #define T_SHORT 10 |
7804 | #define T_OFFSET 11 | |
7805 | #define T_PTR 12 | |
7806 | #define T_ID 13 | |
7807 | #define T_SHL 14 | |
7808 | #define T_SHR 15 | |
64a0c779 DN |
7809 | |
7810 | /* Prototypes for intel parser functions. */ | |
e3bb37b5 L |
7811 | static int intel_match_token (int); |
7812 | static void intel_putback_token (void); | |
7813 | static void intel_get_token (void); | |
7814 | static int intel_expr (void); | |
7815 | static int intel_e04 (void); | |
7816 | static int intel_e05 (void); | |
7817 | static int intel_e06 (void); | |
7818 | static int intel_e09 (void); | |
7819 | static int intel_e10 (void); | |
7820 | static int intel_e11 (void); | |
64a0c779 | 7821 | |
64a0c779 | 7822 | static int |
e3bb37b5 | 7823 | i386_intel_operand (char *operand_string, int got_a_float) |
64a0c779 DN |
7824 | { |
7825 | int ret; | |
7826 | char *p; | |
7827 | ||
a724f0f4 JB |
7828 | p = intel_parser.op_string = xstrdup (operand_string); |
7829 | intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); | |
7830 | ||
7831 | for (;;) | |
64a0c779 | 7832 | { |
a724f0f4 JB |
7833 | /* Initialize token holders. */ |
7834 | cur_token.code = prev_token.code = T_NIL; | |
7835 | cur_token.reg = prev_token.reg = NULL; | |
7836 | cur_token.str = prev_token.str = NULL; | |
7837 | ||
7838 | /* Initialize parser structure. */ | |
7839 | intel_parser.got_a_float = got_a_float; | |
7840 | intel_parser.op_modifier = 0; | |
7841 | intel_parser.is_mem = 0; | |
7842 | intel_parser.in_offset = 0; | |
7843 | intel_parser.in_bracket = 0; | |
7844 | intel_parser.reg = NULL; | |
7845 | intel_parser.disp[0] = '\0'; | |
7846 | intel_parser.next_operand = NULL; | |
7847 | ||
7848 | /* Read the first token and start the parser. */ | |
7849 | intel_get_token (); | |
7850 | ret = intel_expr (); | |
7851 | ||
7852 | if (!ret) | |
7853 | break; | |
7854 | ||
9306ca4a JB |
7855 | if (cur_token.code != T_NIL) |
7856 | { | |
7857 | as_bad (_("invalid operand for '%s' ('%s' unexpected)"), | |
7858 | current_templates->start->name, cur_token.str); | |
7859 | ret = 0; | |
7860 | } | |
64a0c779 DN |
7861 | /* If we found a memory reference, hand it over to i386_displacement |
7862 | to fill in the rest of the operand fields. */ | |
9306ca4a | 7863 | else if (intel_parser.is_mem) |
64a0c779 DN |
7864 | { |
7865 | if ((i.mem_operands == 1 | |
40fb9820 | 7866 | && !current_templates->start->opcode_modifier.isstring) |
64a0c779 DN |
7867 | || i.mem_operands == 2) |
7868 | { | |
7869 | as_bad (_("too many memory references for '%s'"), | |
7870 | current_templates->start->name); | |
7871 | ret = 0; | |
7872 | } | |
7873 | else | |
7874 | { | |
7875 | char *s = intel_parser.disp; | |
7876 | i.mem_operands++; | |
7877 | ||
a724f0f4 JB |
7878 | if (!quiet_warnings && intel_parser.is_mem < 0) |
7879 | /* See the comments in intel_bracket_expr. */ | |
7880 | as_warn (_("Treating `%s' as memory reference"), operand_string); | |
7881 | ||
64a0c779 DN |
7882 | /* Add the displacement expression. */ |
7883 | if (*s != '\0') | |
a4622f40 AM |
7884 | ret = i386_displacement (s, s + strlen (s)); |
7885 | if (ret) | |
a724f0f4 JB |
7886 | { |
7887 | /* Swap base and index in 16-bit memory operands like | |
7888 | [si+bx]. Since i386_index_check is also used in AT&T | |
7889 | mode we have to do that here. */ | |
7890 | if (i.base_reg | |
7891 | && i.index_reg | |
40fb9820 L |
7892 | && i.base_reg->reg_type.bitfield.reg16 |
7893 | && i.index_reg->reg_type.bitfield.reg16 | |
a724f0f4 JB |
7894 | && i.base_reg->reg_num >= 6 |
7895 | && i.index_reg->reg_num < 6) | |
7896 | { | |
7897 | const reg_entry *base = i.index_reg; | |
7898 | ||
7899 | i.index_reg = i.base_reg; | |
7900 | i.base_reg = base; | |
7901 | } | |
7902 | ret = i386_index_check (operand_string); | |
7903 | } | |
64a0c779 DN |
7904 | } |
7905 | } | |
7906 | ||
7907 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
a724f0f4 | 7908 | else if ((intel_parser.op_modifier & (1 << T_OFFSET)) |
64a0c779 DN |
7909 | || intel_parser.reg == NULL) |
7910 | ret = i386_immediate (intel_parser.disp); | |
a724f0f4 JB |
7911 | |
7912 | if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) | |
4eed87de | 7913 | ret = 0; |
a724f0f4 JB |
7914 | if (!ret || !intel_parser.next_operand) |
7915 | break; | |
7916 | intel_parser.op_string = intel_parser.next_operand; | |
7917 | this_operand = i.operands++; | |
64a0c779 DN |
7918 | } |
7919 | ||
7920 | free (p); | |
7921 | free (intel_parser.disp); | |
7922 | ||
7923 | return ret; | |
7924 | } | |
7925 | ||
a724f0f4 JB |
7926 | #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) |
7927 | ||
7928 | /* expr e04 expr' | |
7929 | ||
7930 | expr' cmpOp e04 expr' | |
7931 | | Empty */ | |
64a0c779 | 7932 | static int |
e3bb37b5 | 7933 | intel_expr (void) |
64a0c779 | 7934 | { |
a724f0f4 JB |
7935 | /* XXX Implement the comparison operators. */ |
7936 | return intel_e04 (); | |
9306ca4a JB |
7937 | } |
7938 | ||
a724f0f4 | 7939 | /* e04 e05 e04' |
9306ca4a | 7940 | |
a724f0f4 | 7941 | e04' addOp e05 e04' |
9306ca4a JB |
7942 | | Empty */ |
7943 | static int | |
e3bb37b5 | 7944 | intel_e04 (void) |
9306ca4a | 7945 | { |
a724f0f4 | 7946 | int nregs = -1; |
9306ca4a | 7947 | |
a724f0f4 | 7948 | for (;;) |
9306ca4a | 7949 | { |
a724f0f4 JB |
7950 | if (!intel_e05()) |
7951 | return 0; | |
9306ca4a | 7952 | |
a724f0f4 JB |
7953 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
7954 | i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ | |
9306ca4a | 7955 | |
a724f0f4 JB |
7956 | if (cur_token.code == '+') |
7957 | nregs = -1; | |
7958 | else if (cur_token.code == '-') | |
7959 | nregs = NUM_ADDRESS_REGS; | |
7960 | else | |
7961 | return 1; | |
64a0c779 | 7962 | |
a724f0f4 JB |
7963 | strcat (intel_parser.disp, cur_token.str); |
7964 | intel_match_token (cur_token.code); | |
7965 | } | |
64a0c779 DN |
7966 | } |
7967 | ||
64a0c779 DN |
7968 | /* e05 e06 e05' |
7969 | ||
9306ca4a | 7970 | e05' binOp e06 e05' |
64a0c779 DN |
7971 | | Empty */ |
7972 | static int | |
e3bb37b5 | 7973 | intel_e05 (void) |
64a0c779 | 7974 | { |
a724f0f4 | 7975 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 7976 | |
a724f0f4 | 7977 | for (;;) |
64a0c779 | 7978 | { |
a724f0f4 JB |
7979 | if (!intel_e06()) |
7980 | return 0; | |
7981 | ||
4eed87de AM |
7982 | if (cur_token.code == '&' |
7983 | || cur_token.code == '|' | |
7984 | || cur_token.code == '^') | |
a724f0f4 JB |
7985 | { |
7986 | char str[2]; | |
7987 | ||
7988 | str[0] = cur_token.code; | |
7989 | str[1] = 0; | |
7990 | strcat (intel_parser.disp, str); | |
7991 | } | |
7992 | else | |
7993 | break; | |
9306ca4a | 7994 | |
64a0c779 DN |
7995 | intel_match_token (cur_token.code); |
7996 | ||
a724f0f4 JB |
7997 | if (nregs < 0) |
7998 | nregs = ~nregs; | |
64a0c779 | 7999 | } |
a724f0f4 JB |
8000 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8001 | i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ | |
8002 | return 1; | |
4a1805b1 | 8003 | } |
64a0c779 DN |
8004 | |
8005 | /* e06 e09 e06' | |
8006 | ||
8007 | e06' mulOp e09 e06' | |
b77a7acd | 8008 | | Empty */ |
64a0c779 | 8009 | static int |
e3bb37b5 | 8010 | intel_e06 (void) |
64a0c779 | 8011 | { |
a724f0f4 | 8012 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 8013 | |
a724f0f4 | 8014 | for (;;) |
64a0c779 | 8015 | { |
a724f0f4 JB |
8016 | if (!intel_e09()) |
8017 | return 0; | |
9306ca4a | 8018 | |
4eed87de AM |
8019 | if (cur_token.code == '*' |
8020 | || cur_token.code == '/' | |
8021 | || cur_token.code == '%') | |
a724f0f4 JB |
8022 | { |
8023 | char str[2]; | |
9306ca4a | 8024 | |
a724f0f4 JB |
8025 | str[0] = cur_token.code; |
8026 | str[1] = 0; | |
8027 | strcat (intel_parser.disp, str); | |
8028 | } | |
8029 | else if (cur_token.code == T_SHL) | |
8030 | strcat (intel_parser.disp, "<<"); | |
8031 | else if (cur_token.code == T_SHR) | |
8032 | strcat (intel_parser.disp, ">>"); | |
8033 | else | |
8034 | break; | |
9306ca4a | 8035 | |
64e74474 | 8036 | intel_match_token (cur_token.code); |
64a0c779 | 8037 | |
a724f0f4 JB |
8038 | if (nregs < 0) |
8039 | nregs = ~nregs; | |
64a0c779 | 8040 | } |
a724f0f4 JB |
8041 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8042 | i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ | |
8043 | return 1; | |
64a0c779 DN |
8044 | } |
8045 | ||
a724f0f4 JB |
8046 | /* e09 OFFSET e09 |
8047 | | SHORT e09 | |
8048 | | + e09 | |
8049 | | - e09 | |
8050 | | ~ e09 | |
8051 | | NOT e09 | |
9306ca4a JB |
8052 | | e10 e09' |
8053 | ||
64a0c779 | 8054 | e09' PTR e10 e09' |
b77a7acd | 8055 | | : e10 e09' |
64a0c779 DN |
8056 | | Empty */ |
8057 | static int | |
e3bb37b5 | 8058 | intel_e09 (void) |
64a0c779 | 8059 | { |
a724f0f4 JB |
8060 | int nregs = ~NUM_ADDRESS_REGS; |
8061 | int in_offset = 0; | |
8062 | ||
8063 | for (;;) | |
64a0c779 | 8064 | { |
a724f0f4 JB |
8065 | /* Don't consume constants here. */ |
8066 | if (cur_token.code == '+' || cur_token.code == '-') | |
8067 | { | |
8068 | /* Need to look one token ahead - if the next token | |
8069 | is a constant, the current token is its sign. */ | |
8070 | int next_code; | |
8071 | ||
8072 | intel_match_token (cur_token.code); | |
8073 | next_code = cur_token.code; | |
8074 | intel_putback_token (); | |
8075 | if (next_code == T_CONST) | |
8076 | break; | |
8077 | } | |
8078 | ||
8079 | /* e09 OFFSET e09 */ | |
8080 | if (cur_token.code == T_OFFSET) | |
8081 | { | |
8082 | if (!in_offset++) | |
8083 | ++intel_parser.in_offset; | |
8084 | } | |
8085 | ||
8086 | /* e09 SHORT e09 */ | |
8087 | else if (cur_token.code == T_SHORT) | |
8088 | intel_parser.op_modifier |= 1 << T_SHORT; | |
8089 | ||
8090 | /* e09 + e09 */ | |
8091 | else if (cur_token.code == '+') | |
8092 | strcat (intel_parser.disp, "+"); | |
8093 | ||
8094 | /* e09 - e09 | |
8095 | | ~ e09 | |
8096 | | NOT e09 */ | |
8097 | else if (cur_token.code == '-' || cur_token.code == '~') | |
8098 | { | |
8099 | char str[2]; | |
64a0c779 | 8100 | |
a724f0f4 JB |
8101 | if (nregs < 0) |
8102 | nregs = ~nregs; | |
8103 | str[0] = cur_token.code; | |
8104 | str[1] = 0; | |
8105 | strcat (intel_parser.disp, str); | |
8106 | } | |
8107 | ||
8108 | /* e09 e10 e09' */ | |
8109 | else | |
8110 | break; | |
8111 | ||
8112 | intel_match_token (cur_token.code); | |
64a0c779 DN |
8113 | } |
8114 | ||
a724f0f4 | 8115 | for (;;) |
9306ca4a | 8116 | { |
a724f0f4 JB |
8117 | if (!intel_e10 ()) |
8118 | return 0; | |
9306ca4a | 8119 | |
a724f0f4 JB |
8120 | /* e09' PTR e10 e09' */ |
8121 | if (cur_token.code == T_PTR) | |
8122 | { | |
8123 | char suffix; | |
9306ca4a | 8124 | |
a724f0f4 JB |
8125 | if (prev_token.code == T_BYTE) |
8126 | suffix = BYTE_MNEM_SUFFIX; | |
9306ca4a | 8127 | |
a724f0f4 JB |
8128 | else if (prev_token.code == T_WORD) |
8129 | { | |
8130 | if (current_templates->start->name[0] == 'l' | |
8131 | && current_templates->start->name[2] == 's' | |
8132 | && current_templates->start->name[3] == 0) | |
8133 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
8134 | else if (intel_parser.got_a_float == 2) /* "fi..." */ | |
8135 | suffix = SHORT_MNEM_SUFFIX; | |
8136 | else | |
8137 | suffix = WORD_MNEM_SUFFIX; | |
8138 | } | |
64a0c779 | 8139 | |
a724f0f4 JB |
8140 | else if (prev_token.code == T_DWORD) |
8141 | { | |
8142 | if (current_templates->start->name[0] == 'l' | |
8143 | && current_templates->start->name[2] == 's' | |
8144 | && current_templates->start->name[3] == 0) | |
8145 | suffix = WORD_MNEM_SUFFIX; | |
8146 | else if (flag_code == CODE_16BIT | |
40fb9820 L |
8147 | && (current_templates->start->opcode_modifier.jump |
8148 | || current_templates->start->opcode_modifier.jumpdword)) | |
a724f0f4 JB |
8149 | suffix = LONG_DOUBLE_MNEM_SUFFIX; |
8150 | else if (intel_parser.got_a_float == 1) /* "f..." */ | |
8151 | suffix = SHORT_MNEM_SUFFIX; | |
8152 | else | |
8153 | suffix = LONG_MNEM_SUFFIX; | |
8154 | } | |
9306ca4a | 8155 | |
a724f0f4 JB |
8156 | else if (prev_token.code == T_FWORD) |
8157 | { | |
8158 | if (current_templates->start->name[0] == 'l' | |
8159 | && current_templates->start->name[2] == 's' | |
8160 | && current_templates->start->name[3] == 0) | |
8161 | suffix = LONG_MNEM_SUFFIX; | |
8162 | else if (!intel_parser.got_a_float) | |
8163 | { | |
8164 | if (flag_code == CODE_16BIT) | |
8165 | add_prefix (DATA_PREFIX_OPCODE); | |
8166 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
8167 | } | |
8168 | else | |
8169 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
8170 | } | |
64a0c779 | 8171 | |
a724f0f4 JB |
8172 | else if (prev_token.code == T_QWORD) |
8173 | { | |
8174 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
8175 | suffix = LONG_MNEM_SUFFIX; | |
8176 | else | |
8177 | suffix = QWORD_MNEM_SUFFIX; | |
8178 | } | |
64a0c779 | 8179 | |
a724f0f4 JB |
8180 | else if (prev_token.code == T_TBYTE) |
8181 | { | |
8182 | if (intel_parser.got_a_float == 1) | |
8183 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
8184 | else | |
8185 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
8186 | } | |
9306ca4a | 8187 | |
a724f0f4 | 8188 | else if (prev_token.code == T_XMMWORD) |
9306ca4a | 8189 | { |
582d5edd | 8190 | suffix = XMMWORD_MNEM_SUFFIX; |
9306ca4a | 8191 | } |
64a0c779 | 8192 | |
f16b83df | 8193 | else |
a724f0f4 JB |
8194 | { |
8195 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); | |
8196 | return 0; | |
8197 | } | |
8198 | ||
435acd52 JB |
8199 | /* Operands for jump/call using 'ptr' notation denote absolute |
8200 | addresses. */ | |
40fb9820 L |
8201 | if (current_templates->start->opcode_modifier.jump |
8202 | || current_templates->start->opcode_modifier.jumpdword) | |
8203 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 8204 | |
a724f0f4 JB |
8205 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
8206 | ; | |
8207 | else if (!i.suffix) | |
8208 | i.suffix = suffix; | |
8209 | else if (i.suffix != suffix) | |
8210 | { | |
8211 | as_bad (_("Conflicting operand modifiers")); | |
8212 | return 0; | |
8213 | } | |
64a0c779 | 8214 | |
9306ca4a JB |
8215 | } |
8216 | ||
a724f0f4 JB |
8217 | /* e09' : e10 e09' */ |
8218 | else if (cur_token.code == ':') | |
9306ca4a | 8219 | { |
a724f0f4 JB |
8220 | if (prev_token.code != T_REG) |
8221 | { | |
8222 | /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a | |
8223 | segment/group identifier (which we don't have), using comma | |
8224 | as the operand separator there is even less consistent, since | |
8225 | there all branches only have a single operand. */ | |
8226 | if (this_operand != 0 | |
8227 | || intel_parser.in_offset | |
8228 | || intel_parser.in_bracket | |
40fb9820 L |
8229 | || (!current_templates->start->opcode_modifier.jump |
8230 | && !current_templates->start->opcode_modifier.jumpdword | |
8231 | && !current_templates->start->opcode_modifier.jumpintersegment | |
8232 | && !current_templates->start->operand_types[0].bitfield.jumpabsolute)) | |
a724f0f4 JB |
8233 | return intel_match_token (T_NIL); |
8234 | /* Remember the start of the 2nd operand and terminate 1st | |
8235 | operand here. | |
8236 | XXX This isn't right, yet (when SSSS:OOOO is right operand of | |
8237 | another expression), but it gets at least the simplest case | |
8238 | (a plain number or symbol on the left side) right. */ | |
8239 | intel_parser.next_operand = intel_parser.op_string; | |
8240 | *--intel_parser.op_string = '\0'; | |
8241 | return intel_match_token (':'); | |
8242 | } | |
9306ca4a | 8243 | } |
64a0c779 | 8244 | |
a724f0f4 | 8245 | /* e09' Empty */ |
64a0c779 | 8246 | else |
a724f0f4 | 8247 | break; |
64a0c779 | 8248 | |
a724f0f4 JB |
8249 | intel_match_token (cur_token.code); |
8250 | ||
8251 | } | |
8252 | ||
8253 | if (in_offset) | |
8254 | { | |
8255 | --intel_parser.in_offset; | |
8256 | if (nregs < 0) | |
8257 | nregs = ~nregs; | |
8258 | if (NUM_ADDRESS_REGS > nregs) | |
9306ca4a | 8259 | { |
a724f0f4 | 8260 | as_bad (_("Invalid operand to `OFFSET'")); |
9306ca4a JB |
8261 | return 0; |
8262 | } | |
a724f0f4 JB |
8263 | intel_parser.op_modifier |= 1 << T_OFFSET; |
8264 | } | |
9306ca4a | 8265 | |
a724f0f4 JB |
8266 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8267 | i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ | |
8268 | return 1; | |
8269 | } | |
64a0c779 | 8270 | |
a724f0f4 | 8271 | static int |
e3bb37b5 | 8272 | intel_bracket_expr (void) |
a724f0f4 JB |
8273 | { |
8274 | int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); | |
8275 | const char *start = intel_parser.op_string; | |
8276 | int len; | |
8277 | ||
8278 | if (i.op[this_operand].regs) | |
8279 | return intel_match_token (T_NIL); | |
8280 | ||
8281 | intel_match_token ('['); | |
8282 | ||
8283 | /* Mark as a memory operand only if it's not already known to be an | |
8284 | offset expression. If it's an offset expression, we need to keep | |
8285 | the brace in. */ | |
8286 | if (!intel_parser.in_offset) | |
8287 | { | |
8288 | ++intel_parser.in_bracket; | |
435acd52 JB |
8289 | |
8290 | /* Operands for jump/call inside brackets denote absolute addresses. */ | |
40fb9820 L |
8291 | if (current_templates->start->opcode_modifier.jump |
8292 | || current_templates->start->opcode_modifier.jumpdword) | |
8293 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 8294 | |
a724f0f4 JB |
8295 | /* Unfortunately gas always diverged from MASM in a respect that can't |
8296 | be easily fixed without risking to break code sequences likely to be | |
8297 | encountered (the testsuite even check for this): MASM doesn't consider | |
8298 | an expression inside brackets unconditionally as a memory reference. | |
8299 | When that is e.g. a constant, an offset expression, or the sum of the | |
8300 | two, this is still taken as a constant load. gas, however, always | |
8301 | treated these as memory references. As a compromise, we'll try to make | |
8302 | offset expressions inside brackets work the MASM way (since that's | |
8303 | less likely to be found in real world code), but make constants alone | |
8304 | continue to work the traditional gas way. In either case, issue a | |
8305 | warning. */ | |
8306 | intel_parser.op_modifier &= ~was_offset; | |
64a0c779 | 8307 | } |
a724f0f4 | 8308 | else |
64e74474 | 8309 | strcat (intel_parser.disp, "["); |
a724f0f4 JB |
8310 | |
8311 | /* Add a '+' to the displacement string if necessary. */ | |
8312 | if (*intel_parser.disp != '\0' | |
8313 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
8314 | strcat (intel_parser.disp, "+"); | |
64a0c779 | 8315 | |
a724f0f4 JB |
8316 | if (intel_expr () |
8317 | && (len = intel_parser.op_string - start - 1, | |
8318 | intel_match_token (']'))) | |
64a0c779 | 8319 | { |
a724f0f4 JB |
8320 | /* Preserve brackets when the operand is an offset expression. */ |
8321 | if (intel_parser.in_offset) | |
8322 | strcat (intel_parser.disp, "]"); | |
8323 | else | |
8324 | { | |
8325 | --intel_parser.in_bracket; | |
8326 | if (i.base_reg || i.index_reg) | |
8327 | intel_parser.is_mem = 1; | |
8328 | if (!intel_parser.is_mem) | |
8329 | { | |
8330 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
8331 | /* Defer the warning until all of the operand was parsed. */ | |
8332 | intel_parser.is_mem = -1; | |
8333 | else if (!quiet_warnings) | |
4eed87de AM |
8334 | as_warn (_("`[%.*s]' taken to mean just `%.*s'"), |
8335 | len, start, len, start); | |
a724f0f4 JB |
8336 | } |
8337 | } | |
8338 | intel_parser.op_modifier |= was_offset; | |
64a0c779 | 8339 | |
a724f0f4 | 8340 | return 1; |
64a0c779 | 8341 | } |
a724f0f4 | 8342 | return 0; |
64a0c779 DN |
8343 | } |
8344 | ||
8345 | /* e10 e11 e10' | |
8346 | ||
8347 | e10' [ expr ] e10' | |
b77a7acd | 8348 | | Empty */ |
64a0c779 | 8349 | static int |
e3bb37b5 | 8350 | intel_e10 (void) |
64a0c779 | 8351 | { |
a724f0f4 JB |
8352 | if (!intel_e11 ()) |
8353 | return 0; | |
64a0c779 | 8354 | |
a724f0f4 | 8355 | while (cur_token.code == '[') |
64a0c779 | 8356 | { |
a724f0f4 | 8357 | if (!intel_bracket_expr ()) |
21d6c4af | 8358 | return 0; |
64a0c779 DN |
8359 | } |
8360 | ||
a724f0f4 | 8361 | return 1; |
64a0c779 DN |
8362 | } |
8363 | ||
64a0c779 | 8364 | /* e11 ( expr ) |
b77a7acd | 8365 | | [ expr ] |
64a0c779 DN |
8366 | | BYTE |
8367 | | WORD | |
8368 | | DWORD | |
9306ca4a | 8369 | | FWORD |
64a0c779 | 8370 | | QWORD |
9306ca4a JB |
8371 | | TBYTE |
8372 | | OWORD | |
8373 | | XMMWORD | |
4a1805b1 | 8374 | | $ |
64a0c779 DN |
8375 | | . |
8376 | | register | |
8377 | | id | |
8378 | | constant */ | |
8379 | static int | |
e3bb37b5 | 8380 | intel_e11 (void) |
64a0c779 | 8381 | { |
a724f0f4 | 8382 | switch (cur_token.code) |
64a0c779 | 8383 | { |
a724f0f4 JB |
8384 | /* e11 ( expr ) */ |
8385 | case '(': | |
64a0c779 DN |
8386 | intel_match_token ('('); |
8387 | strcat (intel_parser.disp, "("); | |
8388 | ||
8389 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
8390 | { |
8391 | strcat (intel_parser.disp, ")"); | |
8392 | return 1; | |
8393 | } | |
a724f0f4 | 8394 | return 0; |
4a1805b1 | 8395 | |
a724f0f4 JB |
8396 | /* e11 [ expr ] */ |
8397 | case '[': | |
a724f0f4 | 8398 | return intel_bracket_expr (); |
64a0c779 | 8399 | |
a724f0f4 JB |
8400 | /* e11 $ |
8401 | | . */ | |
8402 | case '.': | |
64a0c779 DN |
8403 | strcat (intel_parser.disp, cur_token.str); |
8404 | intel_match_token (cur_token.code); | |
21d6c4af DN |
8405 | |
8406 | /* Mark as a memory operand only if it's not already known to be an | |
8407 | offset expression. */ | |
a724f0f4 | 8408 | if (!intel_parser.in_offset) |
21d6c4af | 8409 | intel_parser.is_mem = 1; |
64a0c779 DN |
8410 | |
8411 | return 1; | |
64a0c779 | 8412 | |
a724f0f4 JB |
8413 | /* e11 register */ |
8414 | case T_REG: | |
8415 | { | |
8416 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
64a0c779 | 8417 | |
a724f0f4 | 8418 | intel_match_token (T_REG); |
64a0c779 | 8419 | |
a724f0f4 JB |
8420 | /* Check for segment change. */ |
8421 | if (cur_token.code == ':') | |
8422 | { | |
40fb9820 L |
8423 | if (!reg->reg_type.bitfield.sreg2 |
8424 | && !reg->reg_type.bitfield.sreg3) | |
a724f0f4 | 8425 | { |
4eed87de AM |
8426 | as_bad (_("`%s' is not a valid segment register"), |
8427 | reg->reg_name); | |
a724f0f4 JB |
8428 | return 0; |
8429 | } | |
8430 | else if (i.seg[i.mem_operands]) | |
8431 | as_warn (_("Extra segment override ignored")); | |
8432 | else | |
8433 | { | |
8434 | if (!intel_parser.in_offset) | |
8435 | intel_parser.is_mem = 1; | |
8436 | switch (reg->reg_num) | |
8437 | { | |
8438 | case 0: | |
8439 | i.seg[i.mem_operands] = &es; | |
8440 | break; | |
8441 | case 1: | |
8442 | i.seg[i.mem_operands] = &cs; | |
8443 | break; | |
8444 | case 2: | |
8445 | i.seg[i.mem_operands] = &ss; | |
8446 | break; | |
8447 | case 3: | |
8448 | i.seg[i.mem_operands] = &ds; | |
8449 | break; | |
8450 | case 4: | |
8451 | i.seg[i.mem_operands] = &fs; | |
8452 | break; | |
8453 | case 5: | |
8454 | i.seg[i.mem_operands] = &gs; | |
8455 | break; | |
8456 | } | |
8457 | } | |
8458 | } | |
64a0c779 | 8459 | |
a724f0f4 JB |
8460 | /* Not a segment register. Check for register scaling. */ |
8461 | else if (cur_token.code == '*') | |
8462 | { | |
8463 | if (!intel_parser.in_bracket) | |
8464 | { | |
8465 | as_bad (_("Register scaling only allowed in memory operands")); | |
8466 | return 0; | |
8467 | } | |
64a0c779 | 8468 | |
40fb9820 | 8469 | if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */ |
a724f0f4 JB |
8470 | reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ |
8471 | else if (i.index_reg) | |
8472 | reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ | |
64a0c779 | 8473 | |
a724f0f4 JB |
8474 | /* What follows must be a valid scale. */ |
8475 | intel_match_token ('*'); | |
8476 | i.index_reg = reg; | |
40fb9820 | 8477 | i.types[this_operand].bitfield.baseindex = 1; |
64a0c779 | 8478 | |
a724f0f4 JB |
8479 | /* Set the scale after setting the register (otherwise, |
8480 | i386_scale will complain) */ | |
8481 | if (cur_token.code == '+' || cur_token.code == '-') | |
8482 | { | |
8483 | char *str, sign = cur_token.code; | |
8484 | intel_match_token (cur_token.code); | |
8485 | if (cur_token.code != T_CONST) | |
8486 | { | |
8487 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
8488 | cur_token.str); | |
8489 | return 0; | |
8490 | } | |
8491 | str = (char *) xmalloc (strlen (cur_token.str) + 2); | |
8492 | strcpy (str + 1, cur_token.str); | |
8493 | *str = sign; | |
8494 | if (!i386_scale (str)) | |
8495 | return 0; | |
8496 | free (str); | |
8497 | } | |
8498 | else if (!i386_scale (cur_token.str)) | |
64a0c779 | 8499 | return 0; |
a724f0f4 JB |
8500 | intel_match_token (cur_token.code); |
8501 | } | |
64a0c779 | 8502 | |
a724f0f4 JB |
8503 | /* No scaling. If this is a memory operand, the register is either a |
8504 | base register (first occurrence) or an index register (second | |
8505 | occurrence). */ | |
7b0441f6 | 8506 | else if (intel_parser.in_bracket) |
a724f0f4 | 8507 | { |
64a0c779 | 8508 | |
a724f0f4 JB |
8509 | if (!i.base_reg) |
8510 | i.base_reg = reg; | |
8511 | else if (!i.index_reg) | |
8512 | i.index_reg = reg; | |
8513 | else | |
8514 | { | |
8515 | as_bad (_("Too many register references in memory operand")); | |
8516 | return 0; | |
8517 | } | |
64a0c779 | 8518 | |
40fb9820 | 8519 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 | 8520 | } |
4a1805b1 | 8521 | |
4d1bb795 JB |
8522 | /* It's neither base nor index. */ |
8523 | else if (!intel_parser.in_offset && !intel_parser.is_mem) | |
a724f0f4 | 8524 | { |
40fb9820 L |
8525 | i386_operand_type temp = reg->reg_type; |
8526 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
8527 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8528 | temp); | |
a724f0f4 JB |
8529 | i.op[this_operand].regs = reg; |
8530 | i.reg_operands++; | |
8531 | } | |
8532 | else | |
8533 | { | |
8534 | as_bad (_("Invalid use of register")); | |
8535 | return 0; | |
8536 | } | |
64a0c779 | 8537 | |
a724f0f4 JB |
8538 | /* Since registers are not part of the displacement string (except |
8539 | when we're parsing offset operands), we may need to remove any | |
8540 | preceding '+' from the displacement string. */ | |
8541 | if (*intel_parser.disp != '\0' | |
8542 | && !intel_parser.in_offset) | |
8543 | { | |
8544 | char *s = intel_parser.disp; | |
8545 | s += strlen (s) - 1; | |
8546 | if (*s == '+') | |
8547 | *s = '\0'; | |
8548 | } | |
4a1805b1 | 8549 | |
a724f0f4 JB |
8550 | return 1; |
8551 | } | |
8552 | ||
8553 | /* e11 BYTE | |
8554 | | WORD | |
8555 | | DWORD | |
8556 | | FWORD | |
8557 | | QWORD | |
8558 | | TBYTE | |
8559 | | OWORD | |
8560 | | XMMWORD */ | |
8561 | case T_BYTE: | |
8562 | case T_WORD: | |
8563 | case T_DWORD: | |
8564 | case T_FWORD: | |
8565 | case T_QWORD: | |
8566 | case T_TBYTE: | |
8567 | case T_XMMWORD: | |
8568 | intel_match_token (cur_token.code); | |
64a0c779 | 8569 | |
a724f0f4 JB |
8570 | if (cur_token.code == T_PTR) |
8571 | return 1; | |
8572 | ||
8573 | /* It must have been an identifier. */ | |
8574 | intel_putback_token (); | |
8575 | cur_token.code = T_ID; | |
8576 | /* FALLTHRU */ | |
8577 | ||
8578 | /* e11 id | |
8579 | | constant */ | |
8580 | case T_ID: | |
8581 | if (!intel_parser.in_offset && intel_parser.is_mem <= 0) | |
9306ca4a JB |
8582 | { |
8583 | symbolS *symbolP; | |
8584 | ||
a724f0f4 JB |
8585 | /* The identifier represents a memory reference only if it's not |
8586 | preceded by an offset modifier and if it's not an equate. */ | |
9306ca4a JB |
8587 | symbolP = symbol_find(cur_token.str); |
8588 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) | |
8589 | intel_parser.is_mem = 1; | |
8590 | } | |
a724f0f4 | 8591 | /* FALLTHRU */ |
64a0c779 | 8592 | |
a724f0f4 JB |
8593 | case T_CONST: |
8594 | case '-': | |
8595 | case '+': | |
8596 | { | |
8597 | char *save_str, sign = 0; | |
64a0c779 | 8598 | |
a724f0f4 JB |
8599 | /* Allow constants that start with `+' or `-'. */ |
8600 | if (cur_token.code == '-' || cur_token.code == '+') | |
8601 | { | |
8602 | sign = cur_token.code; | |
8603 | intel_match_token (cur_token.code); | |
8604 | if (cur_token.code != T_CONST) | |
8605 | { | |
8606 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
8607 | cur_token.str); | |
8608 | return 0; | |
8609 | } | |
8610 | } | |
64a0c779 | 8611 | |
a724f0f4 JB |
8612 | save_str = (char *) xmalloc (strlen (cur_token.str) + 2); |
8613 | strcpy (save_str + !!sign, cur_token.str); | |
8614 | if (sign) | |
8615 | *save_str = sign; | |
64a0c779 | 8616 | |
a724f0f4 JB |
8617 | /* Get the next token to check for register scaling. */ |
8618 | intel_match_token (cur_token.code); | |
64a0c779 | 8619 | |
4eed87de AM |
8620 | /* Check if this constant is a scaling factor for an |
8621 | index register. */ | |
a724f0f4 JB |
8622 | if (cur_token.code == '*') |
8623 | { | |
8624 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
8625 | { | |
8626 | const reg_entry *reg = cur_token.reg; | |
8627 | ||
8628 | if (!intel_parser.in_bracket) | |
8629 | { | |
4eed87de AM |
8630 | as_bad (_("Register scaling only allowed " |
8631 | "in memory operands")); | |
a724f0f4 JB |
8632 | return 0; |
8633 | } | |
8634 | ||
4eed87de AM |
8635 | /* Disallow things like [1*si]. |
8636 | sp and esp are invalid as index. */ | |
40fb9820 | 8637 | if (reg->reg_type.bitfield.reg16) |
4eed87de | 8638 | reg = i386_regtab + REGNAM_AX + 4; |
a724f0f4 | 8639 | else if (i.index_reg) |
4eed87de | 8640 | reg = i386_regtab + REGNAM_EAX + 4; |
a724f0f4 JB |
8641 | |
8642 | /* The constant is followed by `* reg', so it must be | |
8643 | a valid scale. */ | |
8644 | i.index_reg = reg; | |
40fb9820 | 8645 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 JB |
8646 | |
8647 | /* Set the scale after setting the register (otherwise, | |
8648 | i386_scale will complain) */ | |
8649 | if (!i386_scale (save_str)) | |
64a0c779 | 8650 | return 0; |
a724f0f4 JB |
8651 | intel_match_token (T_REG); |
8652 | ||
8653 | /* Since registers are not part of the displacement | |
8654 | string, we may need to remove any preceding '+' from | |
8655 | the displacement string. */ | |
8656 | if (*intel_parser.disp != '\0') | |
8657 | { | |
8658 | char *s = intel_parser.disp; | |
8659 | s += strlen (s) - 1; | |
8660 | if (*s == '+') | |
8661 | *s = '\0'; | |
8662 | } | |
8663 | ||
8664 | free (save_str); | |
8665 | ||
8666 | return 1; | |
8667 | } | |
64a0c779 | 8668 | |
a724f0f4 JB |
8669 | /* The constant was not used for register scaling. Since we have |
8670 | already consumed the token following `*' we now need to put it | |
8671 | back in the stream. */ | |
64a0c779 | 8672 | intel_putback_token (); |
a724f0f4 | 8673 | } |
64a0c779 | 8674 | |
a724f0f4 JB |
8675 | /* Add the constant to the displacement string. */ |
8676 | strcat (intel_parser.disp, save_str); | |
8677 | free (save_str); | |
64a0c779 | 8678 | |
a724f0f4 JB |
8679 | return 1; |
8680 | } | |
64a0c779 DN |
8681 | } |
8682 | ||
64a0c779 DN |
8683 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
8684 | return 0; | |
8685 | } | |
8686 | ||
64a0c779 DN |
8687 | /* Match the given token against cur_token. If they match, read the next |
8688 | token from the operand string. */ | |
8689 | static int | |
e3bb37b5 | 8690 | intel_match_token (int code) |
64a0c779 DN |
8691 | { |
8692 | if (cur_token.code == code) | |
8693 | { | |
8694 | intel_get_token (); | |
8695 | return 1; | |
8696 | } | |
8697 | else | |
8698 | { | |
0477af35 | 8699 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
8700 | return 0; |
8701 | } | |
8702 | } | |
8703 | ||
64a0c779 DN |
8704 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
8705 | static void | |
e3bb37b5 | 8706 | intel_get_token (void) |
64a0c779 DN |
8707 | { |
8708 | char *end_op; | |
8709 | const reg_entry *reg; | |
8710 | struct intel_token new_token; | |
8711 | ||
8712 | new_token.code = T_NIL; | |
8713 | new_token.reg = NULL; | |
8714 | new_token.str = NULL; | |
8715 | ||
4a1805b1 | 8716 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
8717 | cur_token to prev_token. */ |
8718 | if (prev_token.str) | |
8719 | free (prev_token.str); | |
8720 | ||
8721 | prev_token = cur_token; | |
8722 | ||
8723 | /* Skip whitespace. */ | |
8724 | while (is_space_char (*intel_parser.op_string)) | |
8725 | intel_parser.op_string++; | |
8726 | ||
8727 | /* Return an empty token if we find nothing else on the line. */ | |
8728 | if (*intel_parser.op_string == '\0') | |
8729 | { | |
8730 | cur_token = new_token; | |
8731 | return; | |
8732 | } | |
8733 | ||
8734 | /* The new token cannot be larger than the remainder of the operand | |
8735 | string. */ | |
a724f0f4 | 8736 | new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); |
64a0c779 DN |
8737 | new_token.str[0] = '\0'; |
8738 | ||
8739 | if (strchr ("0123456789", *intel_parser.op_string)) | |
8740 | { | |
8741 | char *p = new_token.str; | |
8742 | char *q = intel_parser.op_string; | |
8743 | new_token.code = T_CONST; | |
8744 | ||
8745 | /* Allow any kind of identifier char to encompass floating point and | |
8746 | hexadecimal numbers. */ | |
8747 | while (is_identifier_char (*q)) | |
8748 | *p++ = *q++; | |
8749 | *p = '\0'; | |
8750 | ||
8751 | /* Recognize special symbol names [0-9][bf]. */ | |
8752 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 8753 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
8754 | || intel_parser.op_string[1] == 'f')) |
8755 | new_token.code = T_ID; | |
8756 | } | |
8757 | ||
4d1bb795 | 8758 | else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) |
64a0c779 | 8759 | { |
4d1bb795 JB |
8760 | size_t len = end_op - intel_parser.op_string; |
8761 | ||
64a0c779 DN |
8762 | new_token.code = T_REG; |
8763 | new_token.reg = reg; | |
8764 | ||
4d1bb795 JB |
8765 | memcpy (new_token.str, intel_parser.op_string, len); |
8766 | new_token.str[len] = '\0'; | |
64a0c779 DN |
8767 | } |
8768 | ||
8769 | else if (is_identifier_char (*intel_parser.op_string)) | |
8770 | { | |
8771 | char *p = new_token.str; | |
8772 | char *q = intel_parser.op_string; | |
8773 | ||
8774 | /* A '.' or '$' followed by an identifier char is an identifier. | |
8775 | Otherwise, it's operator '.' followed by an expression. */ | |
8776 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
8777 | { | |
9306ca4a JB |
8778 | new_token.code = '.'; |
8779 | new_token.str[0] = '.'; | |
64a0c779 DN |
8780 | new_token.str[1] = '\0'; |
8781 | } | |
8782 | else | |
8783 | { | |
8784 | while (is_identifier_char (*q) || *q == '@') | |
8785 | *p++ = *q++; | |
8786 | *p = '\0'; | |
8787 | ||
9306ca4a JB |
8788 | if (strcasecmp (new_token.str, "NOT") == 0) |
8789 | new_token.code = '~'; | |
8790 | ||
8791 | else if (strcasecmp (new_token.str, "MOD") == 0) | |
8792 | new_token.code = '%'; | |
8793 | ||
8794 | else if (strcasecmp (new_token.str, "AND") == 0) | |
8795 | new_token.code = '&'; | |
8796 | ||
8797 | else if (strcasecmp (new_token.str, "OR") == 0) | |
8798 | new_token.code = '|'; | |
8799 | ||
8800 | else if (strcasecmp (new_token.str, "XOR") == 0) | |
8801 | new_token.code = '^'; | |
8802 | ||
8803 | else if (strcasecmp (new_token.str, "SHL") == 0) | |
8804 | new_token.code = T_SHL; | |
8805 | ||
8806 | else if (strcasecmp (new_token.str, "SHR") == 0) | |
8807 | new_token.code = T_SHR; | |
8808 | ||
8809 | else if (strcasecmp (new_token.str, "BYTE") == 0) | |
64a0c779 DN |
8810 | new_token.code = T_BYTE; |
8811 | ||
8812 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
8813 | new_token.code = T_WORD; | |
8814 | ||
8815 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
8816 | new_token.code = T_DWORD; | |
8817 | ||
9306ca4a JB |
8818 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
8819 | new_token.code = T_FWORD; | |
8820 | ||
64a0c779 DN |
8821 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
8822 | new_token.code = T_QWORD; | |
8823 | ||
9306ca4a JB |
8824 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
8825 | /* XXX remove (gcc still uses it) */ | |
8826 | || strcasecmp (new_token.str, "XWORD") == 0) | |
8827 | new_token.code = T_TBYTE; | |
8828 | ||
8829 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 | |
8830 | || strcasecmp (new_token.str, "OWORD") == 0) | |
8831 | new_token.code = T_XMMWORD; | |
64a0c779 DN |
8832 | |
8833 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
8834 | new_token.code = T_PTR; | |
8835 | ||
8836 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
8837 | new_token.code = T_SHORT; | |
8838 | ||
8839 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
8840 | { | |
8841 | new_token.code = T_OFFSET; | |
8842 | ||
8843 | /* ??? This is not mentioned in the MASM grammar but gcc | |
8844 | makes use of it with -mintel-syntax. OFFSET may be | |
8845 | followed by FLAT: */ | |
8846 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
8847 | strcat (new_token.str, " FLAT:"); | |
8848 | } | |
8849 | ||
8850 | /* ??? This is not mentioned in the MASM grammar. */ | |
8851 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
a724f0f4 JB |
8852 | { |
8853 | new_token.code = T_OFFSET; | |
8854 | if (*q == ':') | |
8855 | strcat (new_token.str, ":"); | |
8856 | else | |
8857 | as_bad (_("`:' expected")); | |
8858 | } | |
64a0c779 DN |
8859 | |
8860 | else | |
8861 | new_token.code = T_ID; | |
8862 | } | |
8863 | } | |
8864 | ||
9306ca4a JB |
8865 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
8866 | { | |
8867 | new_token.code = *intel_parser.op_string; | |
8868 | new_token.str[0] = *intel_parser.op_string; | |
8869 | new_token.str[1] = '\0'; | |
8870 | } | |
8871 | ||
8872 | else if (strchr ("<>", *intel_parser.op_string) | |
8873 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
8874 | { | |
8875 | new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; | |
8876 | new_token.str[0] = *intel_parser.op_string; | |
8877 | new_token.str[1] = *intel_parser.op_string; | |
8878 | new_token.str[2] = '\0'; | |
8879 | } | |
8880 | ||
64a0c779 | 8881 | else |
0477af35 | 8882 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
8883 | |
8884 | intel_parser.op_string += strlen (new_token.str); | |
8885 | cur_token = new_token; | |
8886 | } | |
8887 | ||
64a0c779 DN |
8888 | /* Put cur_token back into the token stream and make cur_token point to |
8889 | prev_token. */ | |
8890 | static void | |
e3bb37b5 | 8891 | intel_putback_token (void) |
64a0c779 | 8892 | { |
a724f0f4 JB |
8893 | if (cur_token.code != T_NIL) |
8894 | { | |
8895 | intel_parser.op_string -= strlen (cur_token.str); | |
8896 | free (cur_token.str); | |
8897 | } | |
64a0c779 | 8898 | cur_token = prev_token; |
4a1805b1 | 8899 | |
64a0c779 DN |
8900 | /* Forget prev_token. */ |
8901 | prev_token.code = T_NIL; | |
8902 | prev_token.reg = NULL; | |
8903 | prev_token.str = NULL; | |
8904 | } | |
54cfded0 | 8905 | |
a4447b93 | 8906 | int |
1df69f4f | 8907 | tc_x86_regname_to_dw2regnum (char *regname) |
54cfded0 AM |
8908 | { |
8909 | unsigned int regnum; | |
8910 | unsigned int regnames_count; | |
089dfecd | 8911 | static const char *const regnames_32[] = |
54cfded0 | 8912 | { |
a4447b93 RH |
8913 | "eax", "ecx", "edx", "ebx", |
8914 | "esp", "ebp", "esi", "edi", | |
089dfecd JB |
8915 | "eip", "eflags", NULL, |
8916 | "st0", "st1", "st2", "st3", | |
8917 | "st4", "st5", "st6", "st7", | |
8918 | NULL, NULL, | |
8919 | "xmm0", "xmm1", "xmm2", "xmm3", | |
8920 | "xmm4", "xmm5", "xmm6", "xmm7", | |
8921 | "mm0", "mm1", "mm2", "mm3", | |
43fd16e4 JB |
8922 | "mm4", "mm5", "mm6", "mm7", |
8923 | "fcw", "fsw", "mxcsr", | |
8924 | "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, | |
8925 | "tr", "ldtr" | |
54cfded0 | 8926 | }; |
089dfecd | 8927 | static const char *const regnames_64[] = |
54cfded0 | 8928 | { |
089dfecd JB |
8929 | "rax", "rdx", "rcx", "rbx", |
8930 | "rsi", "rdi", "rbp", "rsp", | |
8931 | "r8", "r9", "r10", "r11", | |
54cfded0 | 8932 | "r12", "r13", "r14", "r15", |
089dfecd JB |
8933 | "rip", |
8934 | "xmm0", "xmm1", "xmm2", "xmm3", | |
8935 | "xmm4", "xmm5", "xmm6", "xmm7", | |
8936 | "xmm8", "xmm9", "xmm10", "xmm11", | |
8937 | "xmm12", "xmm13", "xmm14", "xmm15", | |
8938 | "st0", "st1", "st2", "st3", | |
8939 | "st4", "st5", "st6", "st7", | |
8940 | "mm0", "mm1", "mm2", "mm3", | |
43fd16e4 JB |
8941 | "mm4", "mm5", "mm6", "mm7", |
8942 | "rflags", | |
8943 | "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, | |
8944 | "fs.base", "gs.base", NULL, NULL, | |
8945 | "tr", "ldtr", | |
8946 | "mxcsr", "fcw", "fsw" | |
54cfded0 | 8947 | }; |
089dfecd | 8948 | const char *const *regnames; |
54cfded0 AM |
8949 | |
8950 | if (flag_code == CODE_64BIT) | |
8951 | { | |
8952 | regnames = regnames_64; | |
0cea6190 | 8953 | regnames_count = ARRAY_SIZE (regnames_64); |
54cfded0 AM |
8954 | } |
8955 | else | |
8956 | { | |
8957 | regnames = regnames_32; | |
0cea6190 | 8958 | regnames_count = ARRAY_SIZE (regnames_32); |
54cfded0 AM |
8959 | } |
8960 | ||
8961 | for (regnum = 0; regnum < regnames_count; regnum++) | |
089dfecd JB |
8962 | if (regnames[regnum] != NULL |
8963 | && strcmp (regname, regnames[regnum]) == 0) | |
54cfded0 AM |
8964 | return regnum; |
8965 | ||
54cfded0 AM |
8966 | return -1; |
8967 | } | |
8968 | ||
8969 | void | |
8970 | tc_x86_frame_initial_instructions (void) | |
8971 | { | |
a4447b93 RH |
8972 | static unsigned int sp_regno; |
8973 | ||
8974 | if (!sp_regno) | |
8975 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT | |
8976 | ? "rsp" : "esp"); | |
8977 | ||
8978 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); | |
8979 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 8980 | } |
d2b2c203 DJ |
8981 | |
8982 | int | |
8983 | i386_elf_section_type (const char *str, size_t len) | |
8984 | { | |
8985 | if (flag_code == CODE_64BIT | |
8986 | && len == sizeof ("unwind") - 1 | |
8987 | && strncmp (str, "unwind", 6) == 0) | |
8988 | return SHT_X86_64_UNWIND; | |
8989 | ||
8990 | return -1; | |
8991 | } | |
bb41ade5 AM |
8992 | |
8993 | #ifdef TE_PE | |
8994 | void | |
8995 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
8996 | { | |
8997 | expressionS expr; | |
8998 | ||
8999 | expr.X_op = O_secrel; | |
9000 | expr.X_add_symbol = symbol; | |
9001 | expr.X_add_number = 0; | |
9002 | emit_expr (&expr, size); | |
9003 | } | |
9004 | #endif | |
3b22753a L |
9005 | |
9006 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
9007 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
9008 | ||
9009 | int | |
9010 | x86_64_section_letter (int letter, char **ptr_msg) | |
9011 | { | |
9012 | if (flag_code == CODE_64BIT) | |
9013 | { | |
9014 | if (letter == 'l') | |
9015 | return SHF_X86_64_LARGE; | |
9016 | ||
9017 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 9018 | } |
3b22753a | 9019 | else |
64e74474 | 9020 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
9021 | return -1; |
9022 | } | |
9023 | ||
9024 | int | |
9025 | x86_64_section_word (char *str, size_t len) | |
9026 | { | |
8620418b | 9027 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
9028 | return SHF_X86_64_LARGE; |
9029 | ||
9030 | return -1; | |
9031 | } | |
9032 | ||
9033 | static void | |
9034 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
9035 | { | |
9036 | if (flag_code != CODE_64BIT) | |
9037 | { | |
9038 | s_comm_internal (0, elf_common_parse); | |
9039 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
9040 | } | |
9041 | else | |
9042 | { | |
9043 | static segT lbss_section; | |
9044 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
9045 | asection *saved_bss_section = bss_section; | |
9046 | ||
9047 | if (lbss_section == NULL) | |
9048 | { | |
9049 | flagword applicable; | |
9050 | segT seg = now_seg; | |
9051 | subsegT subseg = now_subseg; | |
9052 | ||
9053 | /* The .lbss section is for local .largecomm symbols. */ | |
9054 | lbss_section = subseg_new (".lbss", 0); | |
9055 | applicable = bfd_applicable_section_flags (stdoutput); | |
9056 | bfd_set_section_flags (stdoutput, lbss_section, | |
9057 | applicable & SEC_ALLOC); | |
9058 | seg_info (lbss_section)->bss = 1; | |
9059 | ||
9060 | subseg_set (seg, subseg); | |
9061 | } | |
9062 | ||
9063 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
9064 | bss_section = lbss_section; | |
9065 | ||
9066 | s_comm_internal (0, elf_common_parse); | |
9067 | ||
9068 | elf_com_section_ptr = saved_com_section_ptr; | |
9069 | bss_section = saved_bss_section; | |
9070 | } | |
9071 | } | |
9072 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |