[deliverable/binutils-gdb.git] / gas / config / tc-i386.h

/* tc-i386.h -- Header file for tc-i386.c
   Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
   Free Software Foundation.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

#ifndef TC_I386
#define TC_I386 1

#ifdef ANSI_PROTOTYPES
struct fix;
#endif

#define TARGET_BYTES_BIG_ENDIAN	0

#ifdef TE_LYNX
#define TARGET_FORMAT		"coff-i386-lynx"
#endif

#ifdef BFD_ASSEMBLER
/* This is used to determine relocation types in tc-i386.c.  The first
   parameter is the current relocation type, the second one is the desired
   type.  The idea is that if the original type is already some kind of PIC
   relocation, we leave it alone, otherwise we give it the desired type */

#define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
extern int tc_i386_fix_adjustable PARAMS ((struct fix *));

#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
/* This arranges for gas/write.c to not apply a relocation if
   tc_fix_adjustable() says it is not adjustable.
   The "! symbol_used_in_reloc_p" test is there specifically to cover
   the case of non-global symbols in linkonce sections.  It's the
   generally correct thing to do though;  If a reloc is going to be
   emitted against a symbol then we don't want to adjust the fixup by
   applying the reloc during assembly.  The reloc will be applied by
   the linker during final link.  */
#define TC_FIX_ADJUSTABLE(fixP) \
  (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
#endif

/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
 * It comes up in complicated expressions such as
 * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
 * the regular expressions.  The fixup specified here when used at runtime
 * implies that we should add the address of the GOT to the specified location,
 * and as a result we have simplified the expression into something we can use.
 */
#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC

/* This expression evaluates to false if the relocation is for a local object
   for which we still want to do the relocation at runtime.  True if we
   are willing to perform this relocation while building the .o file.
   This is only used for pcrel relocations, so GOTOFF does not need to be
   checked here.  I am not sure if some of the others are ever used with
   pcrel, but it is easier to be safe than sorry.  */

#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)				\
  ((FIX)->fx_r_type != BFD_RELOC_386_PLT32			\
   && (FIX)->fx_r_type != BFD_RELOC_386_GOT32			\
   && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC			\
   && ((FIX)->fx_addsy == NULL					\
       || (! S_IS_EXTERNAL ((FIX)->fx_addsy)			\
	   && ! S_IS_WEAK ((FIX)->fx_addsy)			\
	   && S_IS_DEFINED ((FIX)->fx_addsy)			\
	   && ! S_IS_COMMON ((FIX)->fx_addsy))))

#define TARGET_ARCH		bfd_arch_i386

#ifdef TE_NetBSD
#define AOUT_TARGET_FORMAT	"a.out-i386-netbsd"
#endif
#ifdef TE_386BSD
#define AOUT_TARGET_FORMAT	"a.out-i386-bsd"
#endif
#ifdef TE_LINUX
#define AOUT_TARGET_FORMAT	"a.out-i386-linux"
#endif
#ifdef TE_Mach
#define AOUT_TARGET_FORMAT	"a.out-mach3"
#endif
#ifdef TE_DYNIX
#define AOUT_TARGET_FORMAT	"a.out-i386-dynix"
#endif
#ifndef AOUT_TARGET_FORMAT
#define AOUT_TARGET_FORMAT	"a.out-i386"
#endif

#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
     || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
     || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format ()
#else
#ifdef OBJ_ELF
#define TARGET_FORMAT		"elf32-i386"
#endif
#ifdef OBJ_AOUT
#define TARGET_FORMAT		AOUT_TARGET_FORMAT
#endif
#endif

#else /* ! BFD_ASSEMBLER */

/* COFF STUFF */

#define COFF_MAGIC I386MAGIC
#define BFD_ARCH bfd_arch_i386
#define COFF_FLAGS F_AR32WR
#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
extern short tc_coff_fix2rtype PARAMS ((struct fix *));
#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
extern int tc_coff_sizemachdep PARAMS ((fragS *frag));

#ifdef TE_GO32
/* DJGPP now expects some sections to be 2**4 aligned.  */
#define SUB_SEGMENT_ALIGN(SEG)						\
  ((strcmp (obj_segment_name (SEG), ".text") == 0			\
    || strcmp (obj_segment_name (SEG), ".data") == 0			\
    || strcmp (obj_segment_name (SEG), ".bss") == 0			\
    || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0	\
    || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0	\
    || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0)	\
   ? 4									\
   : 2)
#else
#define SUB_SEGMENT_ALIGN(SEG) 2
#endif

#define TC_RVA_RELOC 7
/* Need this for PIC relocations */
#define NEED_FX_R_TYPE

#ifdef TE_386BSD
/* The BSDI linker apparently rejects objects with a machine type of
   M_386 (100).  */
#define AOUT_MACHTYPE 0
#else
#define AOUT_MACHTYPE 100
#endif

#undef REVERSE_SORT_RELOCS

#endif /* ! BFD_ASSEMBLER */

#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
extern int tc_i386_force_relocation PARAMS ((struct fix *));

#ifdef BFD_ASSEMBLER
#define NO_RELOC BFD_RELOC_NONE
#else
#define NO_RELOC 0
#endif
#define tc_coff_symbol_emit_hook(a)	;	/* not used */

#ifndef BFD_ASSEMBLER
#ifndef OBJ_AOUT
#ifndef TE_PE
#ifndef TE_GO32
/* Local labels starts with .L */
#define LOCAL_LABEL(name) (name[0] == '.' \
		 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
#endif
#endif
#endif
#endif

#define LOCAL_LABELS_FB 1

#define tc_aout_pre_write_hook(x)	{;}	/* not used */
#define tc_crawl_symbol_chain(a)	{;}	/* not used */
#define tc_headers_hook(a)		{;}	/* not used */

extern const char extra_symbol_chars[];
#define tc_symbol_chars extra_symbol_chars

#define MAX_OPERANDS 3		/* max operands per insn */
#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
#define MAX_MEMORY_OPERANDS 2	/* max memory refs per insn (string ops) */

/* Prefixes will be emitted in the order defined below.
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
   instruction, and so must come before any prefixes.  */
#define WAIT_PREFIX	0
#define LOCKREP_PREFIX	1
#define ADDR_PREFIX	2
#define DATA_PREFIX	3
#define SEG_PREFIX	4
#define MAX_PREFIXES	5	/* max prefixes per opcode */

/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
#define ABSOLUTE_PREFIX '*'

#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90

/* register numbers */
#define EBP_REG_NUM 5
#define ESP_REG_NUM 4

/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
/* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
/* index_base_byte.base for no base register addressing */
#define NO_BASE_REGISTER EBP_REG_NUM
#define NO_BASE_REGISTER_16 6

/* these are the instruction mnemonic suffixes.  */
#define WORD_MNEM_SUFFIX  'w'
#define BYTE_MNEM_SUFFIX  'b'
#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX  'l'
/* Intel Syntax */
#define LONG_DOUBLE_MNEM_SUFFIX 'x'
/* Intel Syntax */
#define DWORD_MNEM_SUFFIX 'd'

/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)

#define END_OF_INSN '\0'

/* Intel Syntax */
/* Values 0-4 map onto scale factor */
#define BYTE_PTR     0
#define WORD_PTR     1
#define DWORD_PTR    2
#define QWORD_PTR    3
#define XWORD_PTR    4
#define SHORT        5
#define OFFSET_FLAT  6
#define FLAT         7
#define NONE_FOUND   8

typedef struct
{
  /* instruction name sans width suffix ("mov" for movl insns) */
  char *name;

  /* how many operands */
  unsigned int operands;

  /* base_opcode is the fundamental opcode byte without optional
     prefix(es).  */
  unsigned int base_opcode;

  /* extension_opcode is the 3 bit extension for group <n> insns.
     This field is also used to store the 8-bit opcode suffix for the
     AMD 3DNow! instructions.
     If this template has no extension opcode (the usual case) use None */
  unsigned int extension_opcode;
#define None 0xffff		/* If no extension_opcode is possible.  */

  /* cpu feature flags */
  unsigned int cpu_flags;
#define Cpu086		  0x1	/* Any old cpu will do, 0 does the same */
#define Cpu186		  0x2	/* i186 or better required */
#define Cpu286		  0x4	/* i286 or better required */
#define Cpu386		  0x8	/* i386 or better required */
#define Cpu486		 0x10	/* i486 or better required */
#define Cpu586		 0x20	/* i585 or better required */
#define Cpu686		 0x40	/* i686 or better required */
#define CpuMMX		 0x80	/* MMX support required */
#define CpuSSE		0x100	/* Streaming SIMD extensions required */
#define Cpu3dnow	0x200	/* 3dnow! support required */

  /* the bits in opcode_modifier are used to generate the final opcode from
     the base_opcode.  These bits also are used to detect alternate forms of
     the same instruction */
  unsigned int opcode_modifier;

  /* opcode_modifier bits: */
#define W		   0x1	/* set if operands can be words or dwords
				   encoded the canonical way */
#define D		   0x2	/* D = 0 if Reg --> Regmem;
				   D = 1 if Regmem --> Reg:    MUST BE 0x2 */
#define Modrm		   0x4
#define FloatR		   0x8	/* src/dest swap for floats:   MUST BE 0x8 */
#define ShortForm	  0x10	/* register is in low 3 bits of opcode */
#define FloatMF		  0x20	/* FP insn memory format bit, sized by 0x4 */
#define Jump		  0x40	/* special case for jump insns.  */
#define JumpDword	  0x80  /* call and jump */
#define JumpByte	 0x100  /* loop and jecxz */
#define JumpInterSegment 0x200	/* special case for intersegment leaps/calls */
#define FloatD		 0x400	/* direction for float insns:  MUST BE 0x400 */
#define Seg2ShortForm	 0x800	/* encoding of load segment reg insns */
#define Seg3ShortForm	0x1000	/* fs/gs segment register insns.  */
#define Size16		0x2000	/* needs size prefix if in 32-bit mode */
#define Size32		0x4000	/* needs size prefix if in 16-bit mode */
#define IgnoreSize	0x8000  /* instruction ignores operand size prefix */
#define DefaultSize    0x10000  /* default insn size depends on mode */
#define No_bSuf	       0x20000	/* b suffix on instruction illegal */
#define No_wSuf	       0x40000	/* w suffix on instruction illegal */
#define No_lSuf	       0x80000	/* l suffix on instruction illegal */
#define No_sSuf	      0x100000	/* s suffix on instruction illegal */
#define No_dSuf       0x200000  /* d suffix on instruction illegal */
#define No_xSuf       0x400000  /* x suffix on instruction illegal */
#define FWait	      0x800000	/* instruction needs FWAIT */
#define IsString     0x1000000	/* quick test for string instructions */
#define regKludge    0x2000000	/* fake an extra reg operand for clr, imul */
#define IsPrefix     0x4000000	/* opcode is a prefix */
#define ImmExt	     0x8000000	/* instruction has extension in 8 bit imm */
#define Ugh	    0x80000000	/* deprecated fp insn, gets a warning */

  /* operand_types[i] describes the type of operand i.  This is made
     by OR'ing together all of the possible type masks.  (e.g.
     'operand_types[i] = Reg|Imm' specifies that operand i can be
     either a register or an immediate operand.  */
  unsigned int operand_types[3];

  /* operand_types[i] bits */
  /* register */
#define Reg8		   0x1	/* 8 bit reg */
#define Reg16		   0x2	/* 16 bit reg */
#define Reg32		   0x4	/* 32 bit reg */
  /* immediate */
#define Imm8		   0x8	/* 8 bit immediate */
#define Imm8S		  0x10	/* 8 bit immediate sign extended */
#define Imm16		  0x20	/* 16 bit immediate */
#define Imm32		  0x40	/* 32 bit immediate */
#define Imm1		  0x80	/* 1 bit immediate */
  /* memory */
#define BaseIndex	 0x100
  /* Disp8,16,32 are used in different ways, depending on the
     instruction.  For jumps, they specify the size of the PC relative
     displacement, for baseindex type instructions, they specify the
     size of the offset relative to the base register, and for memory
     offset instructions such as `mov 1234,%al' they specify the size of
     the offset relative to the segment base.  */
#define Disp8		 0x200	/* 8 bit displacement */
#define Disp16		 0x400	/* 16 bit displacement */
#define Disp32		 0x800	/* 32 bit displacement */
  /* specials */
#define InOutPortReg	0x1000	/* register to hold in/out port addr = dx */
#define ShiftCount	0x2000	/* register to hold shift cound = cl */
#define Control	        0x4000	/* Control register */
#define Debug	        0x8000	/* Debug register */
#define Test	       0x10000	/* Test register */
#define FloatReg       0x20000	/* Float register */
#define FloatAcc       0x40000	/* Float stack top %st(0) */
#define SReg2	       0x80000	/* 2 bit segment register */
#define SReg3	      0x100000	/* 3 bit segment register */
#define Acc	      0x200000	/* Accumulator %al or %ax or %eax */
#define JumpAbsolute  0x400000
#define RegMMX	      0x800000	/* MMX register */
#define RegXMM	     0x1000000	/* XMM registers in PIII */
#define EsSeg	     0x2000000	/* String insn operand with fixed es segment */
  /* InvMem is for instructions with a modrm byte that only allow a
     general register encoding in the i.tm.mode and i.tm.regmem fields,
     eg. control reg moves.  They really ought to support a memory form,
     but don't, so we add an InvMem flag to the register operand to
     indicate that it should be encoded in the i.tm.regmem field.  */
#define InvMem	     0x4000000

#define Reg	(Reg8|Reg16|Reg32)	/* gen'l register */
#define WordReg (Reg16|Reg32)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
#define Imm	(Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
#define Disp	(Disp8|Disp16|Disp32)	/* General displacement */
#define AnyMem	(Disp|BaseIndex|InvMem)	/* General memory */
  /* The following aliases are defined because the opcode table
     carefully specifies the allowed memory types for each instruction.
     At the moment we can only tell a memory reference size by the
     instruction suffix, so there's not much point in defining Mem8,
     Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
     the suffix directly to check memory operands.  */
#define LLongMem AnyMem		/* 64 bits (or more) */
#define LongMem AnyMem		/* 32 bit memory ref */
#define ShortMem AnyMem		/* 16 bit memory ref */
#define WordMem AnyMem		/* 16 or 32 bit memory ref */
#define ByteMem AnyMem		/* 8 bit memory ref */
}
template;

/*
  'templates' is for grouping together 'template' structures for opcodes
  of the same name.  This is only used for storing the insns in the grand
  ole hash table of insns.
  The templates themselves start at START and range up to (but not including)
  END.
  */
typedef struct
{
  const template *start;
  const template *end;
}
templates;

/* these are for register name --> number & type hash lookup */
typedef struct
{
  char *reg_name;
  unsigned int reg_type;
  unsigned int reg_num;
}
reg_entry;

typedef struct
{
  char *seg_name;
  unsigned int seg_prefix;
}
seg_entry;

/* 386 operand encoding bytes:  see 386 book for details of this.  */
typedef struct
{
  unsigned int regmem;	/* codes register or memory operand */
  unsigned int reg;	/* codes register operand (or extended opcode) */
  unsigned int mode;	/* how to interpret regmem & reg */
}
modrm_byte;

/* 386 opcode byte to code indirect addressing.  */
typedef struct
{
  unsigned base;
  unsigned index;
  unsigned scale;
}
sib_byte;

/* x86 arch names and features */
typedef struct
{
  const char *name;	/* arch name */
  unsigned int flags;	/* cpu feature flags */
}
arch_entry;

/* The name of the global offset table generated by the compiler. Allow
   this to be overridden if need be.  */
#ifndef GLOBAL_OFFSET_TABLE_NAME
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif

#ifdef BFD_ASSEMBLER
void i386_validate_fix PARAMS ((struct fix *));
#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
#endif

#endif /* TC_I386 */

#define md_operand(x)

extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table

#define md_do_align(n, fill, len, max, around)				\
if ((n) && !need_pass_2							\
    && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))		\
    && subseg_text_p (now_seg))						\
  {									\
    char *p;								\
    p = frag_var (rs_align_code, 15, 1, (relax_substateT) max,		\
		  (symbolS *) 0, (offsetT) (n), (char *) 0);		\
    *p = 0x90;								\
    goto around;							\
  }

extern void i386_align_code PARAMS ((fragS *, int));

#define HANDLE_ALIGN(fragP)						\
if (fragP->fr_type == rs_align_code) 					\
  i386_align_code (fragP, (fragP->fr_next->fr_address			\
			   - fragP->fr_address				\
			   - fragP->fr_fix));

/* call md_apply_fix3 with segment instead of md_apply_fix */
#define MD_APPLY_FIX3

void i386_print_statistics PARAMS ((FILE *));
#define tc_print_statistics i386_print_statistics

#define md_number_to_chars number_to_chars_littleendian

#ifdef SCO_ELF
#define tc_init_after_args() sco_id ()
extern void sco_id PARAMS ((void));
#endif

#define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
Commit	Line	Data
252b5132	1	/* tc-i386.h -- Header file for tc-i386.c
4c63da97	2	Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
b9e57a38	3	Free Software Foundation.
252b5132 RH	4
	5	This file is part of GAS, the GNU Assembler.
	6
	7	GAS is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	GAS is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GAS; see the file COPYING. If not, write to the Free
	19	Software Foundation, 59 Temple Place - Suite 330, Boston, MA
	20	02111-1307, USA. */
	21
	22	#ifndef TC_I386
	23	#define TC_I386 1
	24
	25	#ifdef ANSI_PROTOTYPES
	26	struct fix;
	27	#endif
	28
	29	#define TARGET_BYTES_BIG_ENDIAN 0
	30
	31	#ifdef TE_LYNX
	32	#define TARGET_FORMAT "coff-i386-lynx"
	33	#endif
	34
	35	#ifdef BFD_ASSEMBLER
	36	/* This is used to determine relocation types in tc-i386.c. The first
	37	parameter is the current relocation type, the second one is the desired
	38	type. The idea is that if the original type is already some kind of PIC
	39	relocation, we leave it alone, otherwise we give it the desired type */
	40
252b5132 RH	41	#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
	42	extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
	43
4b853faa	44	#if (defined (OBJ_MAYBE_ELF) \|\| defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_COFF) \|\| defined (OBJ_COFF)) && !defined (TE_PE)
8f36cd18	45	/* This arranges for gas/write.c to not apply a relocation if
ce8a8b2f AM	46	tc_fix_adjustable() says it is not adjustable.
	47	The "! symbol_used_in_reloc_p" test is there specifically to cover
	48	the case of non-global symbols in linkonce sections. It's the
	49	generally correct thing to do though; If a reloc is going to be
	50	emitted against a symbol then we don't want to adjust the fixup by
	51	applying the reloc during assembly. The reloc will be applied by
	52	the linker during final link. */
	53	#define TC_FIX_ADJUSTABLE(fixP) \
	54	(! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
8f36cd18 AO	55	#endif
8f36cd18 AO	56
252b5132	57	/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
4a4f25cf	58	* It comes up in complicated expressions such as
252b5132	59	* _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
4a4f25cf	60	* the regular expressions. The fixup specified here when used at runtime
252b5132 RH	61	* implies that we should add the address of the GOT to the specified location,
	62	* and as a result we have simplified the expression into something we can use.
	63	*/
	64	#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
	65
	66	/* This expression evaluates to false if the relocation is for a local object
	67	for which we still want to do the relocation at runtime. True if we
	68	are willing to perform this relocation while building the .o file.
	69	This is only used for pcrel relocations, so GOTOFF does not need to be
	70	checked here. I am not sure if some of the others are ever used with
4a4f25cf	71	pcrel, but it is easier to be safe than sorry. */
252b5132 RH	72
	73	#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
	74	((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
	75	&& (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
	76	&& (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
	77	&& ((FIX)->fx_addsy == NULL \
	78	\|\| (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
	79	&& ! S_IS_WEAK ((FIX)->fx_addsy) \
	80	&& S_IS_DEFINED ((FIX)->fx_addsy) \
	81	&& ! S_IS_COMMON ((FIX)->fx_addsy))))
	82
	83	#define TARGET_ARCH bfd_arch_i386
	84
252b5132	85	#ifdef TE_NetBSD
4c63da97	86	#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
252b5132 RH	87	#endif
252b5132 RH	88	#ifdef TE_386BSD
4c63da97	89	#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
252b5132 RH	90	#endif
252b5132 RH	91	#ifdef TE_LINUX
4c63da97	92	#define AOUT_TARGET_FORMAT "a.out-i386-linux"
252b5132 RH	93	#endif
252b5132 RH	94	#ifdef TE_Mach
4c63da97	95	#define AOUT_TARGET_FORMAT "a.out-mach3"
252b5132 RH	96	#endif
252b5132 RH	97	#ifdef TE_DYNIX
4c63da97	98	#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
252b5132	99	#endif
4c63da97 AM	100	#ifndef AOUT_TARGET_FORMAT
4c63da97 AM	101	#define AOUT_TARGET_FORMAT "a.out-i386"
252b5132	102	#endif
252b5132	103
4c63da97 AM	104	#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
	105	\|\| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
	106	\|\| (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
	107	extern const char *i386_target_format PARAMS ((void));
	108	#define TARGET_FORMAT i386_target_format ()
	109	#else
252b5132 RH	110	#ifdef OBJ_ELF
	111	#define TARGET_FORMAT "elf32-i386"
	112	#endif
4c63da97 AM	113	#ifdef OBJ_AOUT
4c63da97 AM	114	#define TARGET_FORMAT AOUT_TARGET_FORMAT
252b5132 RH	115	#endif
	116	#endif
	117
	118	#else /* ! BFD_ASSEMBLER */
	119
	120	/* COFF STUFF */
	121
	122	#define COFF_MAGIC I386MAGIC
	123	#define BFD_ARCH bfd_arch_i386
	124	#define COFF_FLAGS F_AR32WR
	125	#define TC_COUNT_RELOC(x) ((x)->fx_addsy \|\| (x)->fx_r_type==7)
	126	#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
	127	extern short tc_coff_fix2rtype PARAMS ((struct fix *));
	128	#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
	129	extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
1a1ae23e ILT	130
	131	#ifdef TE_GO32
	132	/* DJGPP now expects some sections to be 2*4 aligned. /
	133	#define SUB_SEGMENT_ALIGN(SEG) \
	134	((strcmp (obj_segment_name (SEG), ".text") == 0 \
	135	\|\| strcmp (obj_segment_name (SEG), ".data") == 0 \
da5d444c	136	\|\| strcmp (obj_segment_name (SEG), ".bss") == 0 \
1a1ae23e ILT	137	\|\| strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \
	138	\|\| strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \
	139	\|\| strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \
	140	? 4 \
	141	: 2)
	142	#else
252b5132	143	#define SUB_SEGMENT_ALIGN(SEG) 2
1a1ae23e ILT	144	#endif
1a1ae23e ILT	145
252b5132 RH	146	#define TC_RVA_RELOC 7
	147	/* Need this for PIC relocations */
	148	#define NEED_FX_R_TYPE
	149
252b5132 RH	150	#ifdef TE_386BSD
	151	/* The BSDI linker apparently rejects objects with a machine type of
	152	M_386 (100). */
	153	#define AOUT_MACHTYPE 0
	154	#else
	155	#define AOUT_MACHTYPE 100
	156	#endif
	157
	158	#undef REVERSE_SORT_RELOCS
	159
	160	#endif /* ! BFD_ASSEMBLER */
	161
	162	#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
	163	extern int tc_i386_force_relocation PARAMS ((struct fix *));
	164
	165	#ifdef BFD_ASSEMBLER
	166	#define NO_RELOC BFD_RELOC_NONE
	167	#else
	168	#define NO_RELOC 0
	169	#endif
	170	#define tc_coff_symbol_emit_hook(a) ; /* not used */
	171
	172	#ifndef BFD_ASSEMBLER
	173	#ifndef OBJ_AOUT
	174	#ifndef TE_PE
	175	#ifndef TE_GO32
	176	/* Local labels starts with .L */
	177	#define LOCAL_LABEL(name) (name[0] == '.' \
	178	&& (name[1] == 'L' \|\| name[1] == 'X' \|\| name[1] == '.'))
	179	#endif
	180	#endif
	181	#endif
	182	#endif
	183
	184	#define LOCAL_LABELS_FB 1
	185
	186	#define tc_aout_pre_write_hook(x) {;} /* not used */
	187	#define tc_crawl_symbol_chain(a) {;} /* not used */
	188	#define tc_headers_hook(a) {;} /* not used */
	189
	190	extern const char extra_symbol_chars[];
	191	#define tc_symbol_chars extra_symbol_chars
	192
	193	#define MAX_OPERANDS 3 /* max operands per insn */
	194	#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
	195	#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
	196
	197	/* Prefixes will be emitted in the order defined below.
	198	WAIT_PREFIX must be the first prefix since FWAIT is really is an
4a4f25cf	199	instruction, and so must come before any prefixes. */
252b5132 RH	200	#define WAIT_PREFIX 0
	201	#define LOCKREP_PREFIX 1
	202	#define ADDR_PREFIX 2
	203	#define DATA_PREFIX 3
	204	#define SEG_PREFIX 4
	205	#define MAX_PREFIXES 5 /* max prefixes per opcode */
	206
	207	/* we define the syntax here (modulo base,index,scale syntax) */
	208	#define REGISTER_PREFIX '%'
	209	#define IMMEDIATE_PREFIX '$'
	210	#define ABSOLUTE_PREFIX '*'
	211
	212	#define TWO_BYTE_OPCODE_ESCAPE 0x0f
	213	#define NOP_OPCODE (char) 0x90
	214
	215	/* register numbers */
	216	#define EBP_REG_NUM 5
	217	#define ESP_REG_NUM 4
	218
	219	/* modrm_byte.regmem for twobyte escape */
	220	#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
	221	/* index_base_byte.index for no index register addressing */
	222	#define NO_INDEX_REGISTER ESP_REG_NUM
	223	/* index_base_byte.base for no base register addressing */
	224	#define NO_BASE_REGISTER EBP_REG_NUM
	225	#define NO_BASE_REGISTER_16 6
	226
	227	/* these are the instruction mnemonic suffixes. */
252b5132 RH	228	#define WORD_MNEM_SUFFIX 'w'
	229	#define BYTE_MNEM_SUFFIX 'b'
	230	#define SHORT_MNEM_SUFFIX 's'
	231	#define LONG_MNEM_SUFFIX 'l'
	232	/* Intel Syntax */
	233	#define LONG_DOUBLE_MNEM_SUFFIX 'x'
	234	/* Intel Syntax */
add0c677	235	#define DWORD_MNEM_SUFFIX 'd'
252b5132 RH	236
	237	/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
	238	#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
	239	#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
	240
	241	#define END_OF_INSN '\0'
	242
	243	/* Intel Syntax */
	244	/* Values 0-4 map onto scale factor */
	245	#define BYTE_PTR 0
	246	#define WORD_PTR 1
	247	#define DWORD_PTR 2
	248	#define QWORD_PTR 3
	249	#define XWORD_PTR 4
	250	#define SHORT 5
	251	#define OFFSET_FLAT 6
	252	#define FLAT 7
	253	#define NONE_FOUND 8
252b5132	254
252b5132 RH	255	typedef struct
	256	{
	257	/* instruction name sans width suffix ("mov" for movl insns) */
	258	char *name;
	259
	260	/* how many operands */
	261	unsigned int operands;
	262
	263	/* base_opcode is the fundamental opcode byte without optional
	264	prefix(es). */
	265	unsigned int base_opcode;
	266
	267	/* extension_opcode is the 3 bit extension for group <n> insns.
	268	This field is also used to store the 8-bit opcode suffix for the
	269	AMD 3DNow! instructions.
	270	If this template has no extension opcode (the usual case) use None */
	271	unsigned int extension_opcode;
4a4f25cf	272	#define None 0xffff /* If no extension_opcode is possible. */
252b5132	273
e413e4e9 AM	274	/* cpu feature flags */
	275	unsigned int cpu_flags;
	276	#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
	277	#define Cpu186 0x2 /* i186 or better required */
	278	#define Cpu286 0x4 /* i286 or better required */
	279	#define Cpu386 0x8 /* i386 or better required */
	280	#define Cpu486 0x10 /* i486 or better required */
	281	#define Cpu586 0x20 /* i585 or better required */
	282	#define Cpu686 0x40 /* i686 or better required */
	283	#define CpuMMX 0x80 /* MMX support required */
	284	#define CpuSSE 0x100 /* Streaming SIMD extensions required */
	285	#define Cpu3dnow 0x200 /* 3dnow! support required */
	286
252b5132 RH	287	/* the bits in opcode_modifier are used to generate the final opcode from
	288	the base_opcode. These bits also are used to detect alternate forms of
	289	the same instruction */
	290	unsigned int opcode_modifier;
	291
	292	/* opcode_modifier bits: */
	293	#define W 0x1 /* set if operands can be words or dwords
	294	encoded the canonical way */
	295	#define D 0x2 /* D = 0 if Reg --> Regmem;
	296	D = 1 if Regmem --> Reg: MUST BE 0x2 */
	297	#define Modrm 0x4
252b5132 RH	298	#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
	299	#define ShortForm 0x10 /* register is in low 3 bits of opcode */
	300	#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
4a4f25cf	301	#define Jump 0x40 /* special case for jump insns. */
252b5132 RH	302	#define JumpDword 0x80 /* call and jump */
	303	#define JumpByte 0x100 /* loop and jecxz */
	304	#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
	305	#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
	306	#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
4a4f25cf	307	#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
252b5132 RH	308	#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
	309	#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
	310	#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
eecb386c AM	311	#define DefaultSize 0x10000 /* default insn size depends on mode */
	312	#define No_bSuf 0x20000 /* b suffix on instruction illegal */
	313	#define No_wSuf 0x40000 /* w suffix on instruction illegal */
	314	#define No_lSuf 0x80000 /* l suffix on instruction illegal */
	315	#define No_sSuf 0x100000 /* s suffix on instruction illegal */
	316	#define No_dSuf 0x200000 /* d suffix on instruction illegal */
	317	#define No_xSuf 0x400000 /* x suffix on instruction illegal */
	318	#define FWait 0x800000 /* instruction needs FWAIT */
	319	#define IsString 0x1000000 /* quick test for string instructions */
	320	#define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
	321	#define IsPrefix 0x4000000 /* opcode is a prefix */
	322	#define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
252b5132 RH	323	#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
	324
	325	/* operand_types[i] describes the type of operand i. This is made
	326	by OR'ing together all of the possible type masks. (e.g.
	327	'operand_types[i] = Reg\|Imm' specifies that operand i can be
e413e4e9	328	either a register or an immediate operand. */
252b5132	329	unsigned int operand_types[3];
e413e4e9 AM	330
	331	/* operand_types[i] bits */
	332	/* register */
	333	#define Reg8 0x1 /* 8 bit reg */
	334	#define Reg16 0x2 /* 16 bit reg */
	335	#define Reg32 0x4 /* 32 bit reg */
	336	/* immediate */
	337	#define Imm8 0x8 /* 8 bit immediate */
	338	#define Imm8S 0x10 /* 8 bit immediate sign extended */
	339	#define Imm16 0x20 /* 16 bit immediate */
	340	#define Imm32 0x40 /* 32 bit immediate */
	341	#define Imm1 0x80 /* 1 bit immediate */
	342	/* memory */
	343	#define BaseIndex 0x100
	344	/* Disp8,16,32 are used in different ways, depending on the
	345	instruction. For jumps, they specify the size of the PC relative
	346	displacement, for baseindex type instructions, they specify the
	347	size of the offset relative to the base register, and for memory
	348	offset instructions such as `mov 1234,%al' they specify the size of
	349	the offset relative to the segment base. */
	350	#define Disp8 0x200 /* 8 bit displacement */
	351	#define Disp16 0x400 /* 16 bit displacement */
	352	#define Disp32 0x800 /* 32 bit displacement */
	353	/* specials */
	354	#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
	355	#define ShiftCount 0x2000 /* register to hold shift cound = cl */
	356	#define Control 0x4000 /* Control register */
	357	#define Debug 0x8000 /* Debug register */
	358	#define Test 0x10000 /* Test register */
	359	#define FloatReg 0x20000 /* Float register */
	360	#define FloatAcc 0x40000 /* Float stack top %st(0) */
	361	#define SReg2 0x80000 /* 2 bit segment register */
	362	#define SReg3 0x100000 /* 3 bit segment register */
	363	#define Acc 0x200000 /* Accumulator %al or %ax or %eax */
	364	#define JumpAbsolute 0x400000
	365	#define RegMMX 0x800000 /* MMX register */
	366	#define RegXMM 0x1000000 /* XMM registers in PIII */
	367	#define EsSeg 0x2000000 /* String insn operand with fixed es segment */
	368	/* InvMem is for instructions with a modrm byte that only allow a
	369	general register encoding in the i.tm.mode and i.tm.regmem fields,
	370	eg. control reg moves. They really ought to support a memory form,
	371	but don't, so we add an InvMem flag to the register operand to
	372	indicate that it should be encoded in the i.tm.regmem field. */
	373	#define InvMem 0x4000000
	374
	375	#define Reg (Reg8\|Reg16\|Reg32) /* gen'l register */
	376	#define WordReg (Reg16\|Reg32)
	377	#define ImplicitRegister (InOutPortReg\|ShiftCount\|Acc\|FloatAcc)
	378	#define Imm (Imm8\|Imm8S\|Imm16\|Imm32) /* gen'l immediate */
	379	#define Disp (Disp8\|Disp16\|Disp32) /* General displacement */
	380	#define AnyMem (Disp\|BaseIndex\|InvMem) /* General memory */
	381	/* The following aliases are defined because the opcode table
	382	carefully specifies the allowed memory types for each instruction.
	383	At the moment we can only tell a memory reference size by the
	384	instruction suffix, so there's not much point in defining Mem8,
	385	Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
	386	the suffix directly to check memory operands. */
	387	#define LLongMem AnyMem /* 64 bits (or more) */
	388	#define LongMem AnyMem /* 32 bit memory ref */
	389	#define ShortMem AnyMem /* 16 bit memory ref */
	390	#define WordMem AnyMem /* 16 or 32 bit memory ref */
	391	#define ByteMem AnyMem /* 8 bit memory ref */
252b5132 RH	392	}
	393	template;
	394
	395	/*
	396	'templates' is for grouping together 'template' structures for opcodes
	397	of the same name. This is only used for storing the insns in the grand
	398	ole hash table of insns.
	399	The templates themselves start at START and range up to (but not including)
	400	END.
	401	*/
	402	typedef struct
e413e4e9 AM	403	{
	404	const template *start;
	405	const template *end;
	406	}
	407	templates;
252b5132 RH	408
	409	/* these are for register name --> number & type hash lookup */
	410	typedef struct
e413e4e9 AM	411	{
	412	char *reg_name;
	413	unsigned int reg_type;
	414	unsigned int reg_num;
	415	}
252b5132 RH	416	reg_entry;
	417
	418	typedef struct
e413e4e9 AM	419	{
	420	char *seg_name;
	421	unsigned int seg_prefix;
	422	}
252b5132 RH	423	seg_entry;
252b5132 RH	424
4a4f25cf	425	/* 386 operand encoding bytes: see 386 book for details of this. */
252b5132	426	typedef struct
e413e4e9 AM	427	{
	428	unsigned int regmem; /* codes register or memory operand */
	429	unsigned int reg; /* codes register operand (or extended opcode) */
	430	unsigned int mode; /* how to interpret regmem & reg */
	431	}
252b5132 RH	432	modrm_byte;
252b5132 RH	433
4a4f25cf	434	/* 386 opcode byte to code indirect addressing. */
252b5132	435	typedef struct
e413e4e9 AM	436	{
	437	unsigned base;
	438	unsigned index;
	439	unsigned scale;
	440	}
252b5132 RH	441	sib_byte;
252b5132 RH	442
e413e4e9 AM	443	/* x86 arch names and features */
	444	typedef struct
	445	{
	446	const char name; / arch name */
	447	unsigned int flags; /* cpu feature flags */
	448	}
	449	arch_entry;
	450
252b5132	451	/* The name of the global offset table generated by the compiler. Allow
4a4f25cf	452	this to be overridden if need be. */
252b5132 RH	453	#ifndef GLOBAL_OFFSET_TABLE_NAME
	454	#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
	455	#endif
	456
	457	#ifdef BFD_ASSEMBLER
	458	void i386_validate_fix PARAMS ((struct fix *));
	459	#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
	460	#endif
	461
	462	#endif /* TC_I386 */
	463
	464	#define md_operand(x)
	465
	466	extern const struct relax_type md_relax_table[];
	467	#define TC_GENERIC_RELAX_TABLE md_relax_table
	468
252b5132 RH	469	#define md_do_align(n, fill, len, max, around) \
	470	if ((n) && !need_pass_2 \
	471	&& (!(fill) \|\| ((char)*(fill) == (char)0x90 && (len) == 1)) \
b9e57a38	472	&& subseg_text_p (now_seg)) \
252b5132 RH	473	{ \
	474	char *p; \
	475	p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
	476	(symbolS ) 0, (offsetT) (n), (char ) 0); \
	477	*p = 0x90; \
	478	goto around; \
	479	}
	480
	481	extern void i386_align_code PARAMS ((fragS *, int));
	482
	483	#define HANDLE_ALIGN(fragP) \
	484	if (fragP->fr_type == rs_align_code) \
	485	i386_align_code (fragP, (fragP->fr_next->fr_address \
	486	- fragP->fr_address \
	487	- fragP->fr_fix));
	488
	489	/* call md_apply_fix3 with segment instead of md_apply_fix */
	490	#define MD_APPLY_FIX3
	491
	492	void i386_print_statistics PARAMS ((FILE *));
	493	#define tc_print_statistics i386_print_statistics
	494
	495	#define md_number_to_chars number_to_chars_littleendian
	496
	497	#ifdef SCO_ELF
	498	#define tc_init_after_args() sco_id ()
	499	extern void sco_id PARAMS ((void));
	500	#endif
	501
	502	#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */