[deliverable/binutils-gdb.git] / gas / config / tc-i386.h

/* tc-i386.h -- Header file for tc-i386.c
   Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

#ifndef TC_I386
#define TC_I386 1

#ifdef ANSI_PROTOTYPES
struct fix;
#endif

#define TARGET_BYTES_BIG_ENDIAN	0

#ifdef TE_LYNX
#define TARGET_FORMAT		"coff-i386-lynx"
#endif

#ifdef BFD_ASSEMBLER
/* This is used to determine relocation types in tc-i386.c.  The first
   parameter is the current relocation type, the second one is the desired
   type.  The idea is that if the original type is already some kind of PIC
   relocation, we leave it alone, otherwise we give it the desired type */

#define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \
	   (X) != BFD_RELOC_386_GOTOFF && \
	   (X) != BFD_RELOC_386_GOT32 && \
	   (X) != BFD_RELOC_386_GOTPC) ? Y : X)

#define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
extern int tc_i386_fix_adjustable PARAMS ((struct fix *));

/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
 * It comes up in complicated expressions such as 
 * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
 * the regular expressions.  The fixup specified here when used at runtime 
 * implies that we should add the address of the GOT to the specified location,
 * and as a result we have simplified the expression into something we can use.
 */
#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC

/* This expression evaluates to false if the relocation is for a local object
   for which we still want to do the relocation at runtime.  True if we
   are willing to perform this relocation while building the .o file.
   This is only used for pcrel relocations, so GOTOFF does not need to be
   checked here.  I am not sure if some of the others are ever used with
   pcrel, but it is easier to be safe than sorry. */

#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)				\
  ((FIX)->fx_r_type != BFD_RELOC_386_PLT32			\
   && (FIX)->fx_r_type != BFD_RELOC_386_GOT32			\
   && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC			\
   && ((FIX)->fx_addsy == NULL					\
       || (! S_IS_EXTERNAL ((FIX)->fx_addsy)			\
	   && ! S_IS_WEAK ((FIX)->fx_addsy)			\
	   && S_IS_DEFINED ((FIX)->fx_addsy)			\
	   && ! S_IS_COMMON ((FIX)->fx_addsy))))

#define TARGET_ARCH		bfd_arch_i386

#ifdef OBJ_AOUT
#ifdef TE_NetBSD
#define TARGET_FORMAT		"a.out-i386-netbsd"
#endif
#ifdef TE_386BSD
#define TARGET_FORMAT		"a.out-i386-bsd"
#endif
#ifdef TE_LINUX
#define TARGET_FORMAT		"a.out-i386-linux"
#endif
#ifdef TE_Mach
#define TARGET_FORMAT		"a.out-mach3"
#endif
#ifdef TE_DYNIX
#define TARGET_FORMAT		"a.out-i386-dynix"
#endif
#ifndef TARGET_FORMAT
#define TARGET_FORMAT		"a.out-i386"
#endif
#endif /* OBJ_AOUT */

#ifdef OBJ_ELF
#define TARGET_FORMAT		"elf32-i386"
#endif

#ifdef OBJ_MAYBE_ELF
#ifdef OBJ_MAYBE_COFF
extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format ()
#endif
#endif

#else /* ! BFD_ASSEMBLER */

/* COFF STUFF */

#define COFF_MAGIC I386MAGIC
#define BFD_ARCH bfd_arch_i386
#define COFF_FLAGS F_AR32WR
#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
#define TC_FORCE_RELOCATION(x) ((x)->fx_r_type==7)
#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
extern short tc_coff_fix2rtype PARAMS ((struct fix *));
#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
#define SUB_SEGMENT_ALIGN(SEG) 2
#define TC_RVA_RELOC 7
/* Need this for PIC relocations */
#define NEED_FX_R_TYPE


#ifdef TE_386BSD
/* The BSDI linker apparently rejects objects with a machine type of
   M_386 (100).  */
#define AOUT_MACHTYPE 0
#else
#define AOUT_MACHTYPE 100
#endif

#undef REVERSE_SORT_RELOCS

#endif /* ! BFD_ASSEMBLER */

#ifdef BFD_ASSEMBLER
#define NO_RELOC BFD_RELOC_NONE
#else
#define NO_RELOC 0
#endif
#define tc_coff_symbol_emit_hook(a)	;	/* not used */

#ifndef BFD_ASSEMBLER
#ifndef OBJ_AOUT
#ifndef TE_PE
#ifndef TE_GO32
/* Local labels starts with .L */
#define LOCAL_LABEL(name) (name[0] == '.' \
		 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
#endif
#endif
#endif
#endif

#define LOCAL_LABELS_FB 1

#define tc_aout_pre_write_hook(x)	{;}	/* not used */
#define tc_crawl_symbol_chain(a)	{;}	/* not used */
#define tc_headers_hook(a)		{;}	/* not used */

#define MAX_OPERANDS 3		/* max operands per insn */
#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
#define MAX_MEMORY_OPERANDS 2	/* max memory refs per insn (string ops) */

/* Prefixes will be emitted in the order defined below.
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
   instruction, and so must come before any prefixes. */
#define WAIT_PREFIX	0
#define LOCKREP_PREFIX	1
#define ADDR_PREFIX	2
#define DATA_PREFIX	3
#define SEG_PREFIX	4
#define MAX_PREFIXES	5	/* max prefixes per opcode */

/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
#define ABSOLUTE_PREFIX '*'

#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90

/* register numbers */
#define EBP_REG_NUM 5
#define ESP_REG_NUM 4

/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
/* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
/* index_base_byte.base for no base register addressing */
#define NO_BASE_REGISTER EBP_REG_NUM
#define NO_BASE_REGISTER_16 6

/* these are the opcode suffixes, making movl --> mov, for example */
#define DWORD_OPCODE_SUFFIX 'l'
#define WORD_OPCODE_SUFFIX  'w'
#define BYTE_OPCODE_SUFFIX  'b'
#define SHORT_OPCODE_SUFFIX 's'
#define LONG_OPCODE_SUFFIX  'l'

/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)

#define END_OF_INSN '\0'

/*
  When an operand is read in it is classified by its type.  This type includes
  all the possible ways an operand can be used.  Thus, '%eax' is both 'register
  # 0' and 'The Accumulator'.  In our language this is expressed by OR'ing
  'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
  Operands are classified so that we can match given operand types with
  the opcode table in i386-opcode.h.
  */
/* register */
#define Reg8		   0x1	/* 8 bit reg */
#define Reg16		   0x2	/* 16 bit reg */
#define Reg32		   0x4	/* 32 bit reg */
/* immediate */
#define Imm8		   0x8	/* 8 bit immediate */
#define Imm8S		  0x10	/* 8 bit immediate sign extended */
#define Imm16		  0x20	/* 16 bit immediate */
#define Imm32		  0x40	/* 32 bit immediate */
#define Imm1		  0x80	/* 1 bit immediate */
/* memory */
#define BaseIndex	 0x100
/* Disp8,16,32 are used in different ways, depending on the
   instruction.  For jumps, they specify the size of the PC relative
   displacement, for baseindex type instructions, they specify the
   size of the offset relative to the base register, and for memory
   offset instructions such as `mov 1234,%al' they specify the size of
   the offset relative to the segment base.  */
#define Disp8		 0x200	/* 8 bit displacement */
#define Disp16		 0x400	/* 16 bit displacement */
#define Disp32		 0x800	/* 32 bit displacement */
/* specials */
#define InOutPortReg	0x1000	/* register to hold in/out port addr = dx */
#define ShiftCount	0x2000	/* register to hold shift cound = cl */
#define Control	        0x4000	/* Control register */
#define Debug	        0x8000	/* Debug register */
#define Test	       0x10000	/* Test register */
#define FloatReg       0x20000	/* Float register */
#define FloatAcc       0x40000	/* Float stack top %st(0) */
#define SReg2	       0x80000	/* 2 bit segment register */
#define SReg3	      0x100000	/* 3 bit segment register */
#define Acc	      0x200000	/* Accumulator %al or %ax or %eax */
#define JumpAbsolute  0x400000
#define RegMMX	      0x800000	/* MMX register */
#define EsSeg	     0x1000000	/* String insn operand with fixed es segment */

#define Reg	(Reg8|Reg16|Reg32)	/* gen'l register */
#define WordReg (Reg16|Reg32)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
#define Imm	(Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
#define Disp	(Disp8|Disp16|Disp32)	/* General displacement */
#define AnyMem	(Disp|BaseIndex)	/* General memory */
/* The following aliases are defined because the opcode table
   carefully specifies the allowed memory types for each instruction.
   At the moment we can only tell a memory reference size by the
   instruction suffix, so there's not much point in defining Mem8,
   Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
   the suffix directly to check memory operands.  */
#define LLongMem AnyMem		/* 64 bits (or more) */
#define LongMem AnyMem		/* 32 bit memory ref */
#define ShortMem AnyMem		/* 16 bit memory ref */
#define WordMem AnyMem		/* 16 or 32 bit memory ref */
#define ByteMem AnyMem		/* 8 bit memory ref */

#define SMALLEST_DISP_TYPE(num) \
    (fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32)

typedef struct
{
  /* instruction name sans width suffix ("mov" for movl insns) */
  char *name;

  /* how many operands */
  unsigned int operands;

  /* base_opcode is the fundamental opcode byte without optional
     prefix(es).  */
  unsigned int base_opcode;

  /* extension_opcode is the 3 bit extension for group <n> insns.
     If this template has no extension opcode (the usual case) use None */
  unsigned char extension_opcode;
#define None 0xff		/* If no extension_opcode is possible. */

  /* the bits in opcode_modifier are used to generate the final opcode from
     the base_opcode.  These bits also are used to detect alternate forms of
     the same instruction */
  unsigned int opcode_modifier;

  /* opcode_modifier bits: */
#define W		   0x1	/* set if operands can be words or dwords
				   encoded the canonical way */
#define D		   0x2	/* D = 0 if Reg --> Regmem;
				   D = 1 if Regmem --> Reg:    MUST BE 0x2 */
#define Modrm		   0x4
#define ReverseRegRegmem   0x8  /* swap reg,regmem fields for 2 reg case */
#define FloatR		   0x8	/* src/dest swap for floats:   MUST BE 0x8 */
#define ShortForm	  0x10	/* register is in low 3 bits of opcode */
#define FloatMF		  0x20	/* FP insn memory format bit, sized by 0x4 */
#define Jump		  0x40	/* special case for jump insns. */
#define JumpDword	  0x80  /* call and jump */
#define JumpByte	 0x100  /* loop and jecxz */
#define JumpInterSegment 0x200	/* special case for intersegment leaps/calls */
#define FloatD		 0x400	/* direction for float insns:  MUST BE 0x400 */
#define Seg2ShortForm	 0x800	/* encoding of load segment reg insns */
#define Seg3ShortForm	0x1000	/* fs/gs segment register insns. */
#define Size16		0x2000	/* needs size prefix if in 32-bit mode */
#define Size32		0x4000	/* needs size prefix if in 16-bit mode */
#define IgnoreSize	0x8000  /* instruction ignores operand size prefix */
#define No_bSuf	       0x10000	/* b suffix on instruction illegal */
#define No_wSuf	       0x20000	/* w suffix on instruction illegal */
#define No_lSuf	       0x40000	/* l suffix on instruction illegal */
#define No_sSuf	       0x80000	/* s suffix on instruction illegal */
#define FWait	      0x100000	/* instruction needs FWAIT */
#define IsString      0x200000	/* quick test for string instructions */
#define regKludge     0x400000	/* fake an extra reg operand for clr, imul */
#define IsPrefix      0x800000	/* opcode is a prefix */
#define Ugh	    0x80000000	/* deprecated fp insn, gets a warning */

  /* operand_types[i] describes the type of operand i.  This is made
     by OR'ing together all of the possible type masks.  (e.g.
     'operand_types[i] = Reg|Imm' specifies that operand i can be
     either a register or an immediate operand */
  unsigned int operand_types[3];
}
template;

/*
  'templates' is for grouping together 'template' structures for opcodes
  of the same name.  This is only used for storing the insns in the grand
  ole hash table of insns.
  The templates themselves start at START and range up to (but not including)
  END.
  */
typedef struct
  {
    const template *start;
    const template *end;
  } templates;

/* these are for register name --> number & type hash lookup */
typedef struct
  {
    char *reg_name;
    unsigned int reg_type;
    unsigned int reg_num;
  }
reg_entry;

typedef struct
  {
    char *seg_name;
    unsigned int seg_prefix;
  }
seg_entry;

/* 386 operand encoding bytes:  see 386 book for details of this. */
typedef struct
  {
    unsigned int regmem;	/* codes register or memory operand */
    unsigned int reg;		/* codes register operand (or extended opcode) */
    unsigned int mode;		/* how to interpret regmem & reg */
  }
modrm_byte;

/* 386 opcode byte to code indirect addressing. */
typedef struct
  {
    unsigned base;
    unsigned index;
    unsigned scale;
  }
sib_byte;

/* The name of the global offset table generated by the compiler. Allow
   this to be overridden if need be. */
#ifndef GLOBAL_OFFSET_TABLE_NAME
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif

#ifdef BFD_ASSEMBLER
void i386_validate_fix PARAMS ((struct fix *));
#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
#endif

#endif /* TC_I386 */

#define md_operand(x)

extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table


extern int flag_16bit_code;

#ifdef BFD_ASSEMBLER
#define md_maybe_text() \
  ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
#else
#define md_maybe_text() \
  (now_seg != data_section && now_seg != bss_section)
#endif

#define md_do_align(n, fill, len, max, around)				\
if ((n) && !need_pass_2							\
    && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))		\
    && md_maybe_text ())						\
  {									\
    char *p;								\
    p = frag_var (rs_align_code, 15, 1, (relax_substateT) max,		\
		  (symbolS *) 0, (offsetT) (n), (char *) 0);		\
    *p = 0x90;								\
    goto around;							\
  }

extern void i386_align_code PARAMS ((fragS *, int));

#define HANDLE_ALIGN(fragP)						\
if (fragP->fr_type == rs_align_code) 					\
  i386_align_code (fragP, (fragP->fr_next->fr_address			\
			   - fragP->fr_address				\
			   - fragP->fr_fix));

/* call md_apply_fix3 with segment instead of md_apply_fix */
#define MD_APPLY_FIX3

void i386_print_statistics PARAMS ((FILE *));
#define tc_print_statistics i386_print_statistics

#define md_number_to_chars number_to_chars_littleendian

#ifdef SCO_ELF
#define tc_init_after_args() sco_id ()
extern void sco_id PARAMS ((void));
#endif

#define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */

/* end of tc-i386.h */
Commit	Line	Data
542e1629	1	/* tc-i386.h -- Header file for tc-i386.c
dddc8a82	2	Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
03678945	3
a39116f1	4	This file is part of GAS, the GNU Assembler.
03678945	5
a39116f1 RP	6	GAS is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2, or (at your option)
	9	any later version.
03678945	10
a39116f1 RP	11	GAS is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
03678945	15
a39116f1	16	You should have received a copy of the GNU General Public License
414a1069 ILT	17	along with GAS; see the file COPYING. If not, write to the Free
	18	Software Foundation, 59 Temple Place - Suite 330, Boston, MA
	19	02111-1307, USA. */
a39116f1	20
03678945	21	#ifndef TC_I386
fecd2382 RP	22	#define TC_I386 1
fecd2382 RP	23
f59fb6ca ILT	24	#ifdef ANSI_PROTOTYPES
	25	struct fix;
	26	#endif
	27
d7bf6158 ILT	28	#define TARGET_BYTES_BIG_ENDIAN 0
d7bf6158 ILT	29
03678945 KR	30	#ifdef TE_LYNX
	31	#define TARGET_FORMAT "coff-i386-lynx"
	32	#endif
	33
	34	#ifdef BFD_ASSEMBLER
	35	/* This is used to determine relocation types in tc-i386.c. The first
	36	parameter is the current relocation type, the second one is the desired
	37	type. The idea is that if the original type is already some kind of PIC
	38	relocation, we leave it alone, otherwise we give it the desired type */
	39
	40	#define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \
	41	(X) != BFD_RELOC_386_GOTOFF && \
	42	(X) != BFD_RELOC_386_GOT32 && \
	43	(X) != BFD_RELOC_386_GOTPC) ? Y : X)
	44
	45	#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
f59fb6ca	46	extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
03678945 KR	47
	48	/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
	49	* It comes up in complicated expressions such as
	50	* _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
	51	* the regular expressions. The fixup specified here when used at runtime
	52	* implies that we should add the address of the GOT to the specified location,
	53	* and as a result we have simplified the expression into something we can use.
	54	*/
	55	#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
	56
	57	/* This expression evaluates to false if the relocation is for a local object
	58	for which we still want to do the relocation at runtime. True if we
	59	are willing to perform this relocation while building the .o file.
	60	This is only used for pcrel relocations, so GOTOFF does not need to be
	61	checked here. I am not sure if some of the others are ever used with
	62	pcrel, but it is easier to be safe than sorry. */
	63
8b398c53 ILT	64	#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
	65	((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
	66	&& (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
	67	&& (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
	68	&& ((FIX)->fx_addsy == NULL \
	69	\|\| (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
	70	&& ! S_IS_WEAK ((FIX)->fx_addsy) \
	71	&& S_IS_DEFINED ((FIX)->fx_addsy) \
	72	&& ! S_IS_COMMON ((FIX)->fx_addsy))))
03678945 KR	73
03678945 KR	74	#define TARGET_ARCH bfd_arch_i386
a39116f1	75
03678945 KR	76	#ifdef OBJ_AOUT
	77	#ifdef TE_NetBSD
	78	#define TARGET_FORMAT "a.out-i386-netbsd"
	79	#endif
	80	#ifdef TE_386BSD
	81	#define TARGET_FORMAT "a.out-i386-bsd"
	82	#endif
	83	#ifdef TE_LINUX
	84	#define TARGET_FORMAT "a.out-i386-linux"
	85	#endif
	86	#ifdef TE_Mach
	87	#define TARGET_FORMAT "a.out-mach3"
	88	#endif
f59fb6ca ILT	89	#ifdef TE_DYNIX
	90	#define TARGET_FORMAT "a.out-i386-dynix"
	91	#endif
03678945 KR	92	#ifndef TARGET_FORMAT
	93	#define TARGET_FORMAT "a.out-i386"
	94	#endif
	95	#endif /* OBJ_AOUT */
542e1629	96
03678945 KR	97	#ifdef OBJ_ELF
	98	#define TARGET_FORMAT "elf32-i386"
	99	#endif
	100
f59fb6ca ILT	101	#ifdef OBJ_MAYBE_ELF
	102	#ifdef OBJ_MAYBE_COFF
	103	extern const char *i386_target_format PARAMS ((void));
	104	#define TARGET_FORMAT i386_target_format ()
	105	#endif
	106	#endif
	107
03678945 KR	108	#else /* ! BFD_ASSEMBLER */
	109
	110	/* COFF STUFF */
	111
	112	#define COFF_MAGIC I386MAGIC
	113	#define BFD_ARCH bfd_arch_i386
	114	#define COFF_FLAGS F_AR32WR
d7bf6158 ILT	115	#define TC_COUNT_RELOC(x) ((x)->fx_addsy \|\| (x)->fx_r_type==7)
d7bf6158 ILT	116	#define TC_FORCE_RELOCATION(x) ((x)->fx_r_type==7)
03678945	117	#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
f59fb6ca	118	extern short tc_coff_fix2rtype PARAMS ((struct fix *));
03678945 KR	119	#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
	120	extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
	121	#define SUB_SEGMENT_ALIGN(SEG) 2
d7bf6158	122	#define TC_RVA_RELOC 7
03678945 KR	123	/* Need this for PIC relocations */
	124	#define NEED_FX_R_TYPE
	125
d7bf6158 ILT	126
	127	#ifdef TE_386BSD
	128	/* The BSDI linker apparently rejects objects with a machine type of
	129	M_386 (100). */
	130	#define AOUT_MACHTYPE 0
	131	#else
a2a5a4fa	132	#define AOUT_MACHTYPE 100
d7bf6158 ILT	133	#endif
d7bf6158 ILT	134
03678945 KR	135	#undef REVERSE_SORT_RELOCS
	136
	137	#endif /* ! BFD_ASSEMBLER */
	138
	139	#ifdef BFD_ASSEMBLER
	140	#define NO_RELOC BFD_RELOC_NONE
	141	#else
	142	#define NO_RELOC 0
	143	#endif
	144	#define tc_coff_symbol_emit_hook(a) ; /* not used */
	145
f59fb6ca	146	#ifndef BFD_ASSEMBLER
03678945	147	#ifndef OBJ_AOUT
d7bf6158	148	#ifndef TE_PE
8b398c53	149	#ifndef TE_GO32
03678945 KR	150	/* Local labels starts with .L */
	151	#define LOCAL_LABEL(name) (name[0] == '.' \
	152	&& (name[1] == 'L' \|\| name[1] == 'X' \|\| name[1] == '.'))
03678945	153	#endif
d7bf6158	154	#endif
f59fb6ca	155	#endif
8b398c53	156	#endif
f59fb6ca	157
a2a5a4fa	158	#define LOCAL_LABELS_FB 1
03678945 KR	159
	160	#define tc_aout_pre_write_hook(x) {;} /* not used */
	161	#define tc_crawl_symbol_chain(a) {;} /* not used */
	162	#define tc_headers_hook(a) {;} /* not used */
542e1629	163
fecd2382	164	#define MAX_OPERANDS 3 /* max operands per insn */
aa56747a	165	#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
4498e3d6	166	#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
03678945	167
aa56747a ILT	168	/* Prefixes will be emitted in the order defined below.
	169	WAIT_PREFIX must be the first prefix since FWAIT is really is an
	170	instruction, and so must come before any prefixes. */
	171	#define WAIT_PREFIX 0
	172	#define LOCKREP_PREFIX 1
	173	#define ADDR_PREFIX 2
	174	#define DATA_PREFIX 3
	175	#define SEG_PREFIX 4
	176	#define MAX_PREFIXES 5 /* max prefixes per opcode */
	177
542e1629	178	/* we define the syntax here (modulo base,index,scale syntax) */
fecd2382 RP	179	#define REGISTER_PREFIX '%'
	180	#define IMMEDIATE_PREFIX '$'
	181	#define ABSOLUTE_PREFIX '*'
03678945	182
fecd2382	183	#define TWO_BYTE_OPCODE_ESCAPE 0x0f
03678945 KR	184	#define NOP_OPCODE (char) 0x90
03678945 KR	185
542e1629	186	/* register numbers */
fecd2382 RP	187	#define EBP_REG_NUM 5
fecd2382 RP	188	#define ESP_REG_NUM 4
03678945	189
542e1629	190	/* modrm_byte.regmem for twobyte escape */
fecd2382	191	#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
542e1629	192	/* index_base_byte.index for no index register addressing */
fecd2382	193	#define NO_INDEX_REGISTER ESP_REG_NUM
542e1629	194	/* index_base_byte.base for no base register addressing */
fecd2382	195	#define NO_BASE_REGISTER EBP_REG_NUM
0351b70c	196	#define NO_BASE_REGISTER_16 6
03678945	197
73a8be66	198	/* these are the opcode suffixes, making movl --> mov, for example */
fecd2382 RP	199	#define DWORD_OPCODE_SUFFIX 'l'
	200	#define WORD_OPCODE_SUFFIX 'w'
	201	#define BYTE_OPCODE_SUFFIX 'b'
73a8be66 ILT	202	#define SHORT_OPCODE_SUFFIX 's'
73a8be66 ILT	203	#define LONG_OPCODE_SUFFIX 'l'
03678945 KR	204
	205	/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
	206	#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
fecd2382 RP	207	#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
	208
	209	#define END_OF_INSN '\0'
	210
	211	/*
a39116f1 RP	212	When an operand is read in it is classified by its type. This type includes
	213	all the possible ways an operand can be used. Thus, '%eax' is both 'register
	214	# 0' and 'The Accumulator'. In our language this is expressed by OR'ing
	215	'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
	216	Operands are classified so that we can match given operand types with
	217	the opcode table in i386-opcode.h.
	218	*/
fecd2382	219	/* register */
4498e3d6 ILT	220	#define Reg8 0x1 /* 8 bit reg */
	221	#define Reg16 0x2 /* 16 bit reg */
	222	#define Reg32 0x4 /* 32 bit reg */
fecd2382	223	/* immediate */
4498e3d6 ILT	224	#define Imm8 0x8 /* 8 bit immediate */
	225	#define Imm8S 0x10 /* 8 bit immediate sign extended */
	226	#define Imm16 0x20 /* 16 bit immediate */
	227	#define Imm32 0x40 /* 32 bit immediate */
	228	#define Imm1 0x80 /* 1 bit immediate */
fecd2382	229	/* memory */
4498e3d6 ILT	230	#define BaseIndex 0x100
	231	/* Disp8,16,32 are used in different ways, depending on the
	232	instruction. For jumps, they specify the size of the PC relative
	233	displacement, for baseindex type instructions, they specify the
	234	size of the offset relative to the base register, and for memory
	235	offset instructions such as `mov 1234,%al' they specify the size of
	236	the offset relative to the segment base. */
	237	#define Disp8 0x200 /* 8 bit displacement */
	238	#define Disp16 0x400 /* 16 bit displacement */
	239	#define Disp32 0x800 /* 32 bit displacement */
fecd2382	240	/* specials */
73a8be66 ILT	241	#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
	242	#define ShiftCount 0x2000 /* register to hold shift cound = cl */
	243	#define Control 0x4000 /* Control register */
	244	#define Debug 0x8000 /* Debug register */
	245	#define Test 0x10000 /* Test register */
	246	#define FloatReg 0x20000 /* Float register */
	247	#define FloatAcc 0x40000 /* Float stack top %st(0) */
	248	#define SReg2 0x80000 /* 2 bit segment register */
	249	#define SReg3 0x100000 /* 3 bit segment register */
	250	#define Acc 0x200000 /* Accumulator %al or %ax or %eax */
	251	#define JumpAbsolute 0x400000
	252	#define RegMMX 0x800000 /* MMX register */
	253	#define EsSeg 0x1000000 /* String insn operand with fixed es segment */
4498e3d6 ILT	254
	255	#define Reg (Reg8\|Reg16\|Reg32) /* gen'l register */
	256	#define WordReg (Reg16\|Reg32)
73a8be66	257	#define ImplicitRegister (InOutPortReg\|ShiftCount\|Acc\|FloatAcc)
4498e3d6 ILT	258	#define Imm (Imm8\|Imm8S\|Imm16\|Imm32) /* gen'l immediate */
4498e3d6 ILT	259	#define Disp (Disp8\|Disp16\|Disp32) /* General displacement */
73a8be66 ILT	260	#define AnyMem (Disp\|BaseIndex) /* General memory */
	261	/* The following aliases are defined because the opcode table
	262	carefully specifies the allowed memory types for each instruction.
	263	At the moment we can only tell a memory reference size by the
	264	instruction suffix, so there's not much point in defining Mem8,
	265	Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
	266	the suffix directly to check memory operands. */
	267	#define LLongMem AnyMem /* 64 bits (or more) */
	268	#define LongMem AnyMem /* 32 bit memory ref */
	269	#define ShortMem AnyMem /* 16 bit memory ref */
	270	#define WordMem AnyMem /* 16 or 32 bit memory ref */
	271	#define ByteMem AnyMem /* 8 bit memory ref */
fecd2382	272
fecd2382	273	#define SMALLEST_DISP_TYPE(num) \
73a8be66	274	(fits_in_signed_byte(num) ? (Disp8\|Disp32) : Disp32)
fecd2382	275
03678945 KR	276	typedef struct
	277	{
	278	/* instruction name sans width suffix ("mov" for movl insns) */
	279	char *name;
	280
	281	/* how many operands */
	282	unsigned int operands;
	283
73a8be66 ILT	284	/* base_opcode is the fundamental opcode byte without optional
73a8be66 ILT	285	prefix(es). */
03678945 KR	286	unsigned int base_opcode;
	287
	288	/* extension_opcode is the 3 bit extension for group <n> insns.
	289	If this template has no extension opcode (the usual case) use None */
	290	unsigned char extension_opcode;
	291	#define None 0xff /* If no extension_opcode is possible. */
	292
	293	/* the bits in opcode_modifier are used to generate the final opcode from
	294	the base_opcode. These bits also are used to detect alternate forms of
	295	the same instruction */
	296	unsigned int opcode_modifier;
	297
	298	/* opcode_modifier bits: */
4498e3d6	299	#define W 0x1 /* set if operands can be words or dwords
73a8be66	300	encoded the canonical way */
4498e3d6 ILT	301	#define D 0x2 /* D = 0 if Reg --> Regmem;
	302	D = 1 if Regmem --> Reg: MUST BE 0x2 */
	303	#define Modrm 0x4
73a8be66 ILT	304	#define ReverseRegRegmem 0x8 /* swap reg,regmem fields for 2 reg case */
73a8be66 ILT	305	#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
4498e3d6	306	#define ShortForm 0x10 /* register is in low 3 bits of opcode */
73a8be66 ILT	307	#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
	308	#define Jump 0x40 /* special case for jump insns. */
	309	#define JumpDword 0x80 /* call and jump */
	310	#define JumpByte 0x100 /* loop and jecxz */
fecd2382	311	#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
4498e3d6	312	#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
73a8be66 ILT	313	#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
73a8be66 ILT	314	#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
284f02bb ILT	315	#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
	316	#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
	317	#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
73a8be66 ILT	318	#define No_bSuf 0x10000 /* b suffix on instruction illegal */
	319	#define No_wSuf 0x20000 /* w suffix on instruction illegal */
	320	#define No_lSuf 0x40000 /* l suffix on instruction illegal */
	321	#define No_sSuf 0x80000 /* s suffix on instruction illegal */
	322	#define FWait 0x100000 /* instruction needs FWAIT */
	323	#define IsString 0x200000 /* quick test for string instructions */
	324	#define regKludge 0x400000 /* fake an extra reg operand for clr, imul */
0351b70c	325	#define IsPrefix 0x800000 /* opcode is a prefix */
73a8be66	326	#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
03678945 KR	327
	328	/* operand_types[i] describes the type of operand i. This is made
	329	by OR'ing together all of the possible type masks. (e.g.
	330	'operand_types[i] = Reg\|Imm' specifies that operand i can be
	331	either a register or an immediate operand */
	332	unsigned int operand_types[3];
	333	}
	334	template;
fecd2382 RP	335
	336	/*
	337	'templates' is for grouping together 'template' structures for opcodes
	338	of the same name. This is only used for storing the insns in the grand
	339	ole hash table of insns.
	340	The templates themselves start at START and range up to (but not including)
	341	END.
a39116f1	342	*/
03678945 KR	343	typedef struct
03678945 KR	344	{
0351b70c ILT	345	const template *start;
0351b70c ILT	346	const template *end;
03678945	347	} templates;
fecd2382 RP	348
fecd2382 RP	349	/* these are for register name --> number & type hash lookup */
03678945 KR	350	typedef struct
	351	{
	352	char *reg_name;
	353	unsigned int reg_type;
	354	unsigned int reg_num;
	355	}
03678945 KR	356	reg_entry;
	357
	358	typedef struct
	359	{
	360	char *seg_name;
	361	unsigned int seg_prefix;
	362	}
03678945	363	seg_entry;
fecd2382	364
fecd2382	365	/* 386 operand encoding bytes: see 386 book for details of this. */
03678945 KR	366	typedef struct
03678945 KR	367	{
0351b70c ILT	368	unsigned int regmem; /* codes register or memory operand */
	369	unsigned int reg; /* codes register operand (or extended opcode) */
	370	unsigned int mode; /* how to interpret regmem & reg */
03678945	371	}
03678945	372	modrm_byte;
fecd2382 RP	373
fecd2382 RP	374	/* 386 opcode byte to code indirect addressing. */
03678945 KR	375	typedef struct
03678945 KR	376	{
0351b70c ILT	377	unsigned base;
	378	unsigned index;
	379	unsigned scale;
03678945	380	}
0351b70c	381	sib_byte;
03678945 KR	382
	383	/* The name of the global offset table generated by the compiler. Allow
	384	this to be overridden if need be. */
	385	#ifndef GLOBAL_OFFSET_TABLE_NAME
	386	#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
	387	#endif
	388
	389	#ifdef BFD_ASSEMBLER
f59fb6ca	390	void i386_validate_fix PARAMS ((struct fix *));
03678945 KR	391	#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
	392	#endif
	393
	394	#endif /* TC_I386 */
	395
	396	#define md_operand(x)
fecd2382	397
a2a5a4fa KR	398	extern const struct relax_type md_relax_table[];
	399	#define TC_GENERIC_RELAX_TABLE md_relax_table
	400
d7bf6158 ILT	401
	402	extern int flag_16bit_code;
	403
dddc8a82 ILT	404	#ifdef BFD_ASSEMBLER
	405	#define md_maybe_text() \
	406	((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
	407	#else
	408	#define md_maybe_text() \
	409	(now_seg != data_section && now_seg != bss_section)
	410	#endif
	411
d7bf6158 ILT	412	#define md_do_align(n, fill, len, max, around) \
	413	if ((n) && !need_pass_2 \
	414	&& (!(fill) \|\| ((char)*(fill) == (char)0x90 && (len) == 1)) \
dddc8a82	415	&& md_maybe_text ()) \
d7bf6158 ILT	416	{ \
	417	char *p; \
	418	p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
f59fb6ca	419	(symbolS ) 0, (offsetT) (n), (char ) 0); \
d7bf6158 ILT	420	*p = 0x90; \
	421	goto around; \
	422	}
	423
	424	extern void i386_align_code PARAMS ((fragS *, int));
	425
	426	#define HANDLE_ALIGN(fragP) \
	427	if (fragP->fr_type == rs_align_code) \
	428	i386_align_code (fragP, (fragP->fr_next->fr_address \
	429	- fragP->fr_address \
	430	- fragP->fr_fix));
	431
	432	/* call md_apply_fix3 with segment instead of md_apply_fix */
	433	#define MD_APPLY_FIX3
	434
	435	void i386_print_statistics PARAMS ((FILE *));
	436	#define tc_print_statistics i386_print_statistics
	437
	438	#define md_number_to_chars number_to_chars_littleendian
	439
	440	#ifdef SCO_ELF
	441	#define tc_init_after_args() sco_id ()
	442	extern void sco_id PARAMS ((void));
	443	#endif
	444
dddc8a82 ILT	445	#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
dddc8a82 ILT	446
fecd2382	447	/* end of tc-i386.h */