Commit | Line | Data |
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252b5132 | 1 | /* tc-i386.h -- Header file for tc-i386.c |
f7e42eb4 | 2 | Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
4dc85607 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
f7e42eb4 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 RH |
22 | |
23 | #ifndef TC_I386 | |
24 | #define TC_I386 1 | |
25 | ||
252b5132 | 26 | struct fix; |
252b5132 RH |
27 | |
28 | #define TARGET_BYTES_BIG_ENDIAN 0 | |
29 | ||
252b5132 | 30 | #define TARGET_ARCH bfd_arch_i386 |
b9d79e03 | 31 | #define TARGET_MACH (i386_mach ()) |
b7c92712 | 32 | extern unsigned long i386_mach (void); |
252b5132 | 33 | |
cac5b87b DB |
34 | #ifdef TE_FreeBSD |
35 | #define AOUT_TARGET_FORMAT "a.out-i386-freebsd" | |
36 | #endif | |
252b5132 | 37 | #ifdef TE_NetBSD |
4c63da97 | 38 | #define AOUT_TARGET_FORMAT "a.out-i386-netbsd" |
252b5132 RH |
39 | #endif |
40 | #ifdef TE_386BSD | |
4c63da97 | 41 | #define AOUT_TARGET_FORMAT "a.out-i386-bsd" |
252b5132 RH |
42 | #endif |
43 | #ifdef TE_LINUX | |
4c63da97 | 44 | #define AOUT_TARGET_FORMAT "a.out-i386-linux" |
252b5132 RH |
45 | #endif |
46 | #ifdef TE_Mach | |
4c63da97 | 47 | #define AOUT_TARGET_FORMAT "a.out-mach3" |
252b5132 RH |
48 | #endif |
49 | #ifdef TE_DYNIX | |
4c63da97 | 50 | #define AOUT_TARGET_FORMAT "a.out-i386-dynix" |
252b5132 | 51 | #endif |
4c63da97 AM |
52 | #ifndef AOUT_TARGET_FORMAT |
53 | #define AOUT_TARGET_FORMAT "a.out-i386" | |
252b5132 | 54 | #endif |
252b5132 | 55 | |
4ada7262 DB |
56 | #ifdef TE_FreeBSD |
57 | #define ELF_TARGET_FORMAT "elf32-i386-freebsd" | |
9d7cbccd | 58 | #define ELF_TARGET_FORMAT64 "elf64-x86-64-freebsd" |
eac338cf PB |
59 | #elif defined (TE_VXWORKS) |
60 | #define ELF_TARGET_FORMAT "elf32-i386-vxworks" | |
4ada7262 | 61 | #endif |
eac338cf | 62 | |
4ada7262 DB |
63 | #ifndef ELF_TARGET_FORMAT |
64 | #define ELF_TARGET_FORMAT "elf32-i386" | |
65 | #endif | |
66 | ||
9d7cbccd NC |
67 | #ifndef ELF_TARGET_FORMAT64 |
68 | #define ELF_TARGET_FORMAT64 "elf64-x86-64" | |
69 | #endif | |
70 | ||
3e73aa7c JH |
71 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
72 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 | 73 | extern const char *i386_target_format (void); |
4c63da97 AM |
74 | #define TARGET_FORMAT i386_target_format () |
75 | #else | |
252b5132 | 76 | #ifdef OBJ_ELF |
4ada7262 | 77 | #define TARGET_FORMAT ELF_TARGET_FORMAT |
252b5132 | 78 | #endif |
4c63da97 AM |
79 | #ifdef OBJ_AOUT |
80 | #define TARGET_FORMAT AOUT_TARGET_FORMAT | |
252b5132 RH |
81 | #endif |
82 | #endif | |
83 | ||
a847613f AM |
84 | #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) |
85 | #define md_end i386_elf_emit_arch_note | |
e3bb37b5 | 86 | extern void i386_elf_emit_arch_note (void); |
a847613f AM |
87 | #endif |
88 | ||
18e1d487 AM |
89 | #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 |
90 | ||
6088b00e | 91 | #define LOCAL_LABELS_FB 1 |
252b5132 RH |
92 | |
93 | extern const char extra_symbol_chars[]; | |
94 | #define tc_symbol_chars extra_symbol_chars | |
95 | ||
b3b91714 AM |
96 | extern const char *i386_comment_chars; |
97 | #define tc_comment_chars i386_comment_chars | |
98 | ||
050dfa73 MM |
99 | #define MAX_OPERANDS 4 /* max operands per insn */ |
100 | #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp, insertq, extrq) */ | |
252b5132 RH |
101 | #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ |
102 | ||
103 | /* Prefixes will be emitted in the order defined below. | |
104 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
9021ec07 L |
105 | instruction, and so must come before any prefixes. |
106 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
107 | LOCKREP_PREFIX. */ | |
252b5132 | 108 | #define WAIT_PREFIX 0 |
9021ec07 | 109 | #define SEG_PREFIX 1 |
252b5132 RH |
110 | #define ADDR_PREFIX 2 |
111 | #define DATA_PREFIX 3 | |
9021ec07 | 112 | #define LOCKREP_PREFIX 4 |
3e73aa7c JH |
113 | #define REX_PREFIX 5 /* must come last. */ |
114 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ | |
252b5132 RH |
115 | |
116 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
117 | #define REGISTER_PREFIX '%' | |
118 | #define IMMEDIATE_PREFIX '$' | |
119 | #define ABSOLUTE_PREFIX '*' | |
120 | ||
121 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f | |
122 | #define NOP_OPCODE (char) 0x90 | |
123 | ||
124 | /* register numbers */ | |
125 | #define EBP_REG_NUM 5 | |
126 | #define ESP_REG_NUM 4 | |
127 | ||
128 | /* modrm_byte.regmem for twobyte escape */ | |
129 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM | |
130 | /* index_base_byte.index for no index register addressing */ | |
131 | #define NO_INDEX_REGISTER ESP_REG_NUM | |
132 | /* index_base_byte.base for no base register addressing */ | |
133 | #define NO_BASE_REGISTER EBP_REG_NUM | |
134 | #define NO_BASE_REGISTER_16 6 | |
135 | ||
136 | /* these are the instruction mnemonic suffixes. */ | |
252b5132 RH |
137 | #define WORD_MNEM_SUFFIX 'w' |
138 | #define BYTE_MNEM_SUFFIX 'b' | |
139 | #define SHORT_MNEM_SUFFIX 's' | |
140 | #define LONG_MNEM_SUFFIX 'l' | |
3e73aa7c | 141 | #define QWORD_MNEM_SUFFIX 'q' |
252b5132 RH |
142 | /* Intel Syntax */ |
143 | #define LONG_DOUBLE_MNEM_SUFFIX 'x' | |
252b5132 RH |
144 | |
145 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ | |
146 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ | |
147 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) | |
148 | ||
149 | #define END_OF_INSN '\0' | |
150 | ||
252b5132 RH |
151 | typedef struct |
152 | { | |
153 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
154 | char *name; | |
155 | ||
156 | /* how many operands */ | |
157 | unsigned int operands; | |
158 | ||
159 | /* base_opcode is the fundamental opcode byte without optional | |
160 | prefix(es). */ | |
161 | unsigned int base_opcode; | |
162 | ||
163 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
164 | This field is also used to store the 8-bit opcode suffix for the | |
165 | AMD 3DNow! instructions. | |
166 | If this template has no extension opcode (the usual case) use None */ | |
167 | unsigned int extension_opcode; | |
4a4f25cf | 168 | #define None 0xffff /* If no extension_opcode is possible. */ |
252b5132 | 169 | |
e413e4e9 AM |
170 | /* cpu feature flags */ |
171 | unsigned int cpu_flags; | |
d32cad65 L |
172 | #define Cpu186 0x1 /* i186 or better required */ |
173 | #define Cpu286 0x2 /* i286 or better required */ | |
174 | #define Cpu386 0x4 /* i386 or better required */ | |
175 | #define Cpu486 0x8 /* i486 or better required */ | |
176 | #define Cpu586 0x10 /* i585 or better required */ | |
177 | #define Cpu686 0x20 /* i686 or better required */ | |
178 | #define CpuP4 0x40 /* Pentium4 or better required */ | |
179 | #define CpuK6 0x80 /* AMD K6 or better required*/ | |
180 | #define CpuSledgehammer 0x100 /* Sledgehammer or better required */ | |
181 | #define CpuMMX 0x200 /* MMX support required */ | |
182 | #define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */ | |
183 | #define CpuSSE 0x800 /* Streaming SIMD extensions required */ | |
184 | #define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */ | |
185 | #define Cpu3dnow 0x2000 /* 3dnow! support required */ | |
186 | #define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */ | |
187 | #define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */ | |
d32cad65 L |
188 | #define CpuPadLock 0x10000 /* VIA PadLock required */ |
189 | #define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */ | |
190 | #define CpuVMX 0x40000 /* VMX Instructions required */ | |
ef05d495 | 191 | #define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */ |
d32cad65 L |
192 | #define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */ |
193 | #define CpuABM 0x200000 /* ABM New Instructions required */ | |
3e73aa7c JH |
194 | |
195 | /* These flags are set by gas depending on the flag_code. */ | |
196 | #define Cpu64 0x4000000 /* 64bit support required */ | |
197 | #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ | |
198 | ||
199 | /* The default value for unknown CPUs - enable all features to avoid problems. */ | |
d32cad65 | 200 | #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ |
b7d9ef37 | 201 | |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ |
ef05d495 | 202 | |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a) |
e413e4e9 | 203 | |
252b5132 RH |
204 | /* the bits in opcode_modifier are used to generate the final opcode from |
205 | the base_opcode. These bits also are used to detect alternate forms of | |
206 | the same instruction */ | |
207 | unsigned int opcode_modifier; | |
208 | ||
209 | /* opcode_modifier bits: */ | |
210 | #define W 0x1 /* set if operands can be words or dwords | |
211 | encoded the canonical way */ | |
212 | #define D 0x2 /* D = 0 if Reg --> Regmem; | |
213 | D = 1 if Regmem --> Reg: MUST BE 0x2 */ | |
214 | #define Modrm 0x4 | |
252b5132 RH |
215 | #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ |
216 | #define ShortForm 0x10 /* register is in low 3 bits of opcode */ | |
217 | #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ | |
4a4f25cf | 218 | #define Jump 0x40 /* special case for jump insns. */ |
252b5132 RH |
219 | #define JumpDword 0x80 /* call and jump */ |
220 | #define JumpByte 0x100 /* loop and jecxz */ | |
221 | #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ | |
222 | #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ | |
252b5132 RH |
223 | #define Size16 0x2000 /* needs size prefix if in 32-bit mode */ |
224 | #define Size32 0x4000 /* needs size prefix if in 16-bit mode */ | |
6b2de085 | 225 | #define Size64 0x8000 /* needs size prefix if in 64-bit mode */ |
3e73aa7c JH |
226 | #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ |
227 | #define DefaultSize 0x20000 /* default insn size depends on mode */ | |
228 | #define No_bSuf 0x40000 /* b suffix on instruction illegal */ | |
229 | #define No_wSuf 0x80000 /* w suffix on instruction illegal */ | |
230 | #define No_lSuf 0x100000 /* l suffix on instruction illegal */ | |
231 | #define No_sSuf 0x200000 /* s suffix on instruction illegal */ | |
232 | #define No_qSuf 0x400000 /* q suffix on instruction illegal */ | |
233 | #define No_xSuf 0x800000 /* x suffix on instruction illegal */ | |
234 | #define FWait 0x1000000 /* instruction needs FWAIT */ | |
235 | #define IsString 0x2000000 /* quick test for string instructions */ | |
236 | #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ | |
237 | #define IsPrefix 0x8000000 /* opcode is a prefix */ | |
238 | #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ | |
239 | #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ | |
240 | #define Rex64 0x40000000 /* instruction require Rex64 prefix. */ | |
241 | #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ | |
252b5132 RH |
242 | |
243 | /* operand_types[i] describes the type of operand i. This is made | |
244 | by OR'ing together all of the possible type masks. (e.g. | |
245 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
e413e4e9 | 246 | either a register or an immediate operand. */ |
ffb08c80 | 247 | unsigned int operand_types[MAX_OPERANDS]; |
e413e4e9 AM |
248 | |
249 | /* operand_types[i] bits */ | |
250 | /* register */ | |
251 | #define Reg8 0x1 /* 8 bit reg */ | |
252 | #define Reg16 0x2 /* 16 bit reg */ | |
253 | #define Reg32 0x4 /* 32 bit reg */ | |
3e73aa7c | 254 | #define Reg64 0x8 /* 64 bit reg */ |
e413e4e9 | 255 | /* immediate */ |
3e73aa7c JH |
256 | #define Imm8 0x10 /* 8 bit immediate */ |
257 | #define Imm8S 0x20 /* 8 bit immediate sign extended */ | |
258 | #define Imm16 0x40 /* 16 bit immediate */ | |
259 | #define Imm32 0x80 /* 32 bit immediate */ | |
260 | #define Imm32S 0x100 /* 32 bit immediate sign extended */ | |
261 | #define Imm64 0x200 /* 64 bit immediate */ | |
262 | #define Imm1 0x400 /* 1 bit immediate */ | |
e413e4e9 | 263 | /* memory */ |
3e73aa7c | 264 | #define BaseIndex 0x800 |
e413e4e9 AM |
265 | /* Disp8,16,32 are used in different ways, depending on the |
266 | instruction. For jumps, they specify the size of the PC relative | |
267 | displacement, for baseindex type instructions, they specify the | |
268 | size of the offset relative to the base register, and for memory | |
269 | offset instructions such as `mov 1234,%al' they specify the size of | |
270 | the offset relative to the segment base. */ | |
3e73aa7c JH |
271 | #define Disp8 0x1000 /* 8 bit displacement */ |
272 | #define Disp16 0x2000 /* 16 bit displacement */ | |
273 | #define Disp32 0x4000 /* 32 bit displacement */ | |
274 | #define Disp32S 0x8000 /* 32 bit signed displacement */ | |
275 | #define Disp64 0x10000 /* 64 bit displacement */ | |
e413e4e9 | 276 | /* specials */ |
3e73aa7c | 277 | #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ |
87a918e2 | 278 | #define ShiftCount 0x40000 /* register to hold shift count = cl */ |
3e73aa7c JH |
279 | #define Control 0x80000 /* Control register */ |
280 | #define Debug 0x100000 /* Debug register */ | |
281 | #define Test 0x200000 /* Test register */ | |
282 | #define FloatReg 0x400000 /* Float register */ | |
283 | #define FloatAcc 0x800000 /* Float stack top %st(0) */ | |
284 | #define SReg2 0x1000000 /* 2 bit segment register */ | |
285 | #define SReg3 0x2000000 /* 3 bit segment register */ | |
286 | #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ | |
287 | #define JumpAbsolute 0x8000000 | |
288 | #define RegMMX 0x10000000 /* MMX register */ | |
289 | #define RegXMM 0x20000000 /* XMM registers in PIII */ | |
290 | #define EsSeg 0x40000000 /* String insn operand with fixed es segment */ | |
291 | ||
e413e4e9 AM |
292 | /* InvMem is for instructions with a modrm byte that only allow a |
293 | general register encoding in the i.tm.mode and i.tm.regmem fields, | |
294 | eg. control reg moves. They really ought to support a memory form, | |
295 | but don't, so we add an InvMem flag to the register operand to | |
296 | indicate that it should be encoded in the i.tm.regmem field. */ | |
3e73aa7c | 297 | #define InvMem 0x80000000 |
e413e4e9 | 298 | |
3e73aa7c JH |
299 | #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ |
300 | #define WordReg (Reg16|Reg32|Reg64) | |
e413e4e9 | 301 | #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) |
3e73aa7c JH |
302 | #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ |
303 | #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ | |
304 | #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ | |
305 | #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ | |
e413e4e9 AM |
306 | /* The following aliases are defined because the opcode table |
307 | carefully specifies the allowed memory types for each instruction. | |
308 | At the moment we can only tell a memory reference size by the | |
309 | instruction suffix, so there's not much point in defining Mem8, | |
310 | Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use | |
311 | the suffix directly to check memory operands. */ | |
312 | #define LLongMem AnyMem /* 64 bits (or more) */ | |
313 | #define LongMem AnyMem /* 32 bit memory ref */ | |
314 | #define ShortMem AnyMem /* 16 bit memory ref */ | |
eca5433b | 315 | #define WordMem AnyMem /* 16, 32 or 64 bit memory ref */ |
e413e4e9 | 316 | #define ByteMem AnyMem /* 8 bit memory ref */ |
252b5132 RH |
317 | } |
318 | template; | |
319 | ||
320 | /* | |
321 | 'templates' is for grouping together 'template' structures for opcodes | |
322 | of the same name. This is only used for storing the insns in the grand | |
323 | ole hash table of insns. | |
324 | The templates themselves start at START and range up to (but not including) | |
325 | END. | |
326 | */ | |
327 | typedef struct | |
e413e4e9 AM |
328 | { |
329 | const template *start; | |
330 | const template *end; | |
331 | } | |
332 | templates; | |
252b5132 RH |
333 | |
334 | /* these are for register name --> number & type hash lookup */ | |
335 | typedef struct | |
e413e4e9 AM |
336 | { |
337 | char *reg_name; | |
338 | unsigned int reg_type; | |
3e73aa7c JH |
339 | unsigned int reg_flags; |
340 | #define RegRex 0x1 /* Extended register. */ | |
341 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
e413e4e9 AM |
342 | unsigned int reg_num; |
343 | } | |
252b5132 RH |
344 | reg_entry; |
345 | ||
346 | typedef struct | |
e413e4e9 AM |
347 | { |
348 | char *seg_name; | |
349 | unsigned int seg_prefix; | |
350 | } | |
252b5132 RH |
351 | seg_entry; |
352 | ||
4a4f25cf | 353 | /* 386 operand encoding bytes: see 386 book for details of this. */ |
252b5132 | 354 | typedef struct |
e413e4e9 AM |
355 | { |
356 | unsigned int regmem; /* codes register or memory operand */ | |
357 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
358 | unsigned int mode; /* how to interpret regmem & reg */ | |
359 | } | |
252b5132 RH |
360 | modrm_byte; |
361 | ||
3e73aa7c | 362 | /* x86-64 extension prefix. */ |
29b0f896 AM |
363 | typedef int rex_byte; |
364 | #define REX_OPCODE 0x40 | |
365 | ||
366 | /* Indicates 64 bit operand size. */ | |
367 | #define REX_MODE64 8 | |
368 | /* High extension to reg field of modrm byte. */ | |
369 | #define REX_EXTX 4 | |
370 | /* High extension to SIB index field. */ | |
371 | #define REX_EXTY 2 | |
372 | /* High extension to base field of modrm or SIB, or reg field of opcode. */ | |
373 | #define REX_EXTZ 1 | |
3e73aa7c | 374 | |
4a4f25cf | 375 | /* 386 opcode byte to code indirect addressing. */ |
252b5132 | 376 | typedef struct |
e413e4e9 AM |
377 | { |
378 | unsigned base; | |
379 | unsigned index; | |
380 | unsigned scale; | |
381 | } | |
252b5132 RH |
382 | sib_byte; |
383 | ||
9103f4f4 L |
384 | enum processor_type |
385 | { | |
386 | PROCESSOR_UNKNOWN, | |
387 | PROCESSOR_I486, | |
388 | PROCESSOR_PENTIUM, | |
389 | PROCESSOR_PENTIUMPRO, | |
390 | PROCESSOR_PENTIUM4, | |
391 | PROCESSOR_NOCONA, | |
ef05d495 L |
392 | PROCESSOR_CORE, |
393 | PROCESSOR_CORE2, | |
9103f4f4 L |
394 | PROCESSOR_K6, |
395 | PROCESSOR_ATHLON, | |
396 | PROCESSOR_K8, | |
397 | PROCESSOR_GENERIC32, | |
050dfa73 MM |
398 | PROCESSOR_GENERIC64, |
399 | PROCESSOR_AMDFAM10 | |
9103f4f4 L |
400 | }; |
401 | ||
402 | /* x86 arch names, types and features */ | |
e413e4e9 AM |
403 | typedef struct |
404 | { | |
9103f4f4 L |
405 | const char *name; /* arch name */ |
406 | enum processor_type type; /* arch type */ | |
407 | unsigned int flags; /* cpu feature flags */ | |
e413e4e9 AM |
408 | } |
409 | arch_entry; | |
410 | ||
252b5132 | 411 | /* The name of the global offset table generated by the compiler. Allow |
4a4f25cf | 412 | this to be overridden if need be. */ |
252b5132 RH |
413 | #ifndef GLOBAL_OFFSET_TABLE_NAME |
414 | #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" | |
415 | #endif | |
416 | ||
718ddfc0 | 417 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT) |
6088b00e | 418 | #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) |
e3bb37b5 | 419 | extern void x86_cons (expressionS *, int); |
d182319b | 420 | #endif |
6088b00e AM |
421 | |
422 | #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) | |
423 | extern void x86_cons_fix_new | |
e3bb37b5 | 424 | (fragS *, unsigned int, unsigned int, expressionS *); |
6088b00e AM |
425 | |
426 | #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ | |
427 | ||
6088b00e AM |
428 | #define NO_RELOC BFD_RELOC_NONE |
429 | ||
e3bb37b5 | 430 | void i386_validate_fix (struct fix *); |
a161fe53 | 431 | #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX) |
6088b00e AM |
432 | |
433 | #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) | |
e3bb37b5 | 434 | extern int tc_i386_fix_adjustable (struct fix *); |
6088b00e | 435 | |
55cf6793 | 436 | /* Values passed to md_apply_fix don't include the symbol value. */ |
a161fe53 | 437 | #define MD_APPLY_SYM_VALUE(FIX) 0 |
3ca4bdc3 AM |
438 | |
439 | /* ELF wants external syms kept, as does PE COFF. */ | |
ae6063d4 AM |
440 | #if defined (TE_PE) && defined (STRICT_PE_FORMAT) |
441 | #define EXTERN_FORCE_RELOC \ | |
3ca4bdc3 AM |
442 | (OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
443 | || OUTPUT_FLAVOR == bfd_target_coff_flavour) | |
444 | #else | |
445 | #define EXTERN_FORCE_RELOC \ | |
446 | (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
447 | #endif |
448 | ||
a161fe53 AM |
449 | /* This expression evaluates to true if the relocation is for a local |
450 | object for which we still want to do the relocation at runtime. | |
451 | False if we are willing to perform this relocation while building | |
452 | the .o file. GOTOFF does not need to be checked here because it is | |
453 | not pcrel. I am not sure if some of the others are ever used with | |
6088b00e AM |
454 | pcrel, but it is easier to be safe than sorry. */ |
455 | ||
a161fe53 AM |
456 | #define TC_FORCE_RELOCATION_LOCAL(FIX) \ |
457 | (!(FIX)->fx_pcrel \ | |
a161fe53 AM |
458 | || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \ |
459 | || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \ | |
460 | || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \ | |
461 | || TC_FORCE_RELOCATION (FIX)) | |
6088b00e | 462 | |
4d1bb795 JB |
463 | extern int i386_parse_name (char *, expressionS *, char *); |
464 | #define md_parse_name(s, e, m, c) i386_parse_name (s, e, c) | |
252b5132 RH |
465 | |
466 | extern const struct relax_type md_relax_table[]; | |
467 | #define TC_GENERIC_RELAX_TABLE md_relax_table | |
468 | ||
12b55ccc L |
469 | extern int optimize_align_code; |
470 | ||
252b5132 | 471 | #define md_do_align(n, fill, len, max, around) \ |
12b55ccc L |
472 | if ((n) \ |
473 | && !need_pass_2 \ | |
474 | && optimize_align_code \ | |
475 | && (!(fill) \ | |
476 | || ((char)*(fill) == (char)0x90 && (len) == 1)) \ | |
b9e57a38 | 477 | && subseg_text_p (now_seg)) \ |
252b5132 | 478 | { \ |
0a9ef439 | 479 | frag_align_code ((n), (max)); \ |
252b5132 RH |
480 | goto around; \ |
481 | } | |
482 | ||
0a9ef439 RH |
483 | #define MAX_MEM_FOR_RS_ALIGN_CODE 15 |
484 | ||
e3bb37b5 | 485 | extern void i386_align_code (fragS *, int); |
252b5132 RH |
486 | |
487 | #define HANDLE_ALIGN(fragP) \ | |
488 | if (fragP->fr_type == rs_align_code) \ | |
489 | i386_align_code (fragP, (fragP->fr_next->fr_address \ | |
490 | - fragP->fr_address \ | |
491 | - fragP->fr_fix)); | |
492 | ||
e3bb37b5 | 493 | void i386_print_statistics (FILE *); |
252b5132 RH |
494 | #define tc_print_statistics i386_print_statistics |
495 | ||
496 | #define md_number_to_chars number_to_chars_littleendian | |
497 | ||
498 | #ifdef SCO_ELF | |
499 | #define tc_init_after_args() sco_id () | |
e3bb37b5 | 500 | extern void sco_id (void); |
252b5132 RH |
501 | #endif |
502 | ||
b1b7d09b AM |
503 | #define WORKING_DOT_WORD 1 |
504 | ||
54cfded0 | 505 | /* We want .cfi_* pseudo-ops for generating unwind info. */ |
a4447b93 | 506 | #define TARGET_USE_CFIPOP 1 |
54cfded0 | 507 | |
a4447b93 RH |
508 | extern unsigned int x86_dwarf2_return_column; |
509 | #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column | |
510 | ||
511 | extern int x86_cie_data_alignment; | |
512 | #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment | |
54cfded0 AM |
513 | |
514 | #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum | |
e3bb37b5 | 515 | extern int tc_x86_regname_to_dw2regnum (char *); |
54cfded0 AM |
516 | |
517 | #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions | |
e3bb37b5 | 518 | extern void tc_x86_frame_initial_instructions (void); |
54cfded0 | 519 | |
d2b2c203 | 520 | #define md_elf_section_type(str,len) i386_elf_section_type (str, len) |
e3bb37b5 | 521 | extern int i386_elf_section_type (const char *, size_t); |
d2b2c203 | 522 | |
3b22753a | 523 | /* Support for SHF_X86_64_LARGE */ |
e3bb37b5 L |
524 | extern int x86_64_section_word (char *, size_t); |
525 | extern int x86_64_section_letter (int, char **); | |
3b22753a L |
526 | #define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG) |
527 | #define md_elf_section_word(STR, LEN) x86_64_section_word (STR, LEN) | |
528 | ||
bb41ade5 AM |
529 | #ifdef TE_PE |
530 | ||
531 | #define O_secrel O_md1 | |
532 | ||
533 | #define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset | |
534 | void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int); | |
535 | ||
536 | #endif /* TE_PE */ | |
537 | ||
6088b00e | 538 | #endif /* TC_I386 */ |