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252b5132 | 1 | /* tc-i386.h -- Header file for tc-i386.c |
b9e57a38 ILT |
2 | Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 1999 |
3 | Free Software Foundation. | |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
22 | #ifndef TC_I386 | |
23 | #define TC_I386 1 | |
24 | ||
25 | #ifdef ANSI_PROTOTYPES | |
26 | struct fix; | |
27 | #endif | |
28 | ||
29 | #define TARGET_BYTES_BIG_ENDIAN 0 | |
30 | ||
31 | #ifdef TE_LYNX | |
32 | #define TARGET_FORMAT "coff-i386-lynx" | |
33 | #endif | |
34 | ||
35 | #ifdef BFD_ASSEMBLER | |
36 | /* This is used to determine relocation types in tc-i386.c. The first | |
37 | parameter is the current relocation type, the second one is the desired | |
38 | type. The idea is that if the original type is already some kind of PIC | |
39 | relocation, we leave it alone, otherwise we give it the desired type */ | |
40 | ||
41 | #define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \ | |
42 | (X) != BFD_RELOC_386_GOTOFF && \ | |
43 | (X) != BFD_RELOC_386_GOT32 && \ | |
44 | (X) != BFD_RELOC_386_GOTPC) ? Y : X) | |
45 | ||
46 | #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) | |
47 | extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); | |
48 | ||
49 | /* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE. | |
50 | * It comes up in complicated expressions such as | |
51 | * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with | |
52 | * the regular expressions. The fixup specified here when used at runtime | |
53 | * implies that we should add the address of the GOT to the specified location, | |
54 | * and as a result we have simplified the expression into something we can use. | |
55 | */ | |
56 | #define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC | |
57 | ||
58 | /* This expression evaluates to false if the relocation is for a local object | |
59 | for which we still want to do the relocation at runtime. True if we | |
60 | are willing to perform this relocation while building the .o file. | |
61 | This is only used for pcrel relocations, so GOTOFF does not need to be | |
62 | checked here. I am not sure if some of the others are ever used with | |
63 | pcrel, but it is easier to be safe than sorry. */ | |
64 | ||
65 | #define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ | |
66 | ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ | |
67 | && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ | |
68 | && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ | |
69 | && ((FIX)->fx_addsy == NULL \ | |
70 | || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ | |
71 | && ! S_IS_WEAK ((FIX)->fx_addsy) \ | |
72 | && S_IS_DEFINED ((FIX)->fx_addsy) \ | |
73 | && ! S_IS_COMMON ((FIX)->fx_addsy)))) | |
74 | ||
75 | #define TARGET_ARCH bfd_arch_i386 | |
76 | ||
77 | #ifdef OBJ_AOUT | |
78 | #ifdef TE_NetBSD | |
79 | #define TARGET_FORMAT "a.out-i386-netbsd" | |
80 | #endif | |
81 | #ifdef TE_386BSD | |
82 | #define TARGET_FORMAT "a.out-i386-bsd" | |
83 | #endif | |
84 | #ifdef TE_LINUX | |
85 | #define TARGET_FORMAT "a.out-i386-linux" | |
86 | #endif | |
87 | #ifdef TE_Mach | |
88 | #define TARGET_FORMAT "a.out-mach3" | |
89 | #endif | |
90 | #ifdef TE_DYNIX | |
91 | #define TARGET_FORMAT "a.out-i386-dynix" | |
92 | #endif | |
93 | #ifndef TARGET_FORMAT | |
94 | #define TARGET_FORMAT "a.out-i386" | |
95 | #endif | |
96 | #endif /* OBJ_AOUT */ | |
97 | ||
98 | #ifdef OBJ_ELF | |
99 | #define TARGET_FORMAT "elf32-i386" | |
100 | #endif | |
101 | ||
102 | #ifdef OBJ_MAYBE_ELF | |
103 | #ifdef OBJ_MAYBE_COFF | |
104 | extern const char *i386_target_format PARAMS ((void)); | |
105 | #define TARGET_FORMAT i386_target_format () | |
106 | #endif | |
107 | #endif | |
108 | ||
109 | #else /* ! BFD_ASSEMBLER */ | |
110 | ||
111 | /* COFF STUFF */ | |
112 | ||
113 | #define COFF_MAGIC I386MAGIC | |
114 | #define BFD_ARCH bfd_arch_i386 | |
115 | #define COFF_FLAGS F_AR32WR | |
116 | #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) | |
117 | #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) | |
118 | extern short tc_coff_fix2rtype PARAMS ((struct fix *)); | |
119 | #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag) | |
120 | extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); | |
1a1ae23e ILT |
121 | |
122 | #ifdef TE_GO32 | |
123 | /* DJGPP now expects some sections to be 2**4 aligned. */ | |
124 | #define SUB_SEGMENT_ALIGN(SEG) \ | |
125 | ((strcmp (obj_segment_name (SEG), ".text") == 0 \ | |
126 | || strcmp (obj_segment_name (SEG), ".data") == 0 \ | |
127 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ | |
128 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ | |
129 | || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ | |
130 | ? 4 \ | |
131 | : 2) | |
132 | #else | |
252b5132 | 133 | #define SUB_SEGMENT_ALIGN(SEG) 2 |
1a1ae23e ILT |
134 | #endif |
135 | ||
252b5132 RH |
136 | #define TC_RVA_RELOC 7 |
137 | /* Need this for PIC relocations */ | |
138 | #define NEED_FX_R_TYPE | |
139 | ||
140 | ||
141 | #ifdef TE_386BSD | |
142 | /* The BSDI linker apparently rejects objects with a machine type of | |
143 | M_386 (100). */ | |
144 | #define AOUT_MACHTYPE 0 | |
145 | #else | |
146 | #define AOUT_MACHTYPE 100 | |
147 | #endif | |
148 | ||
149 | #undef REVERSE_SORT_RELOCS | |
150 | ||
151 | #endif /* ! BFD_ASSEMBLER */ | |
152 | ||
153 | #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp) | |
154 | extern int tc_i386_force_relocation PARAMS ((struct fix *)); | |
155 | ||
156 | #ifdef BFD_ASSEMBLER | |
157 | #define NO_RELOC BFD_RELOC_NONE | |
158 | #else | |
159 | #define NO_RELOC 0 | |
160 | #endif | |
161 | #define tc_coff_symbol_emit_hook(a) ; /* not used */ | |
162 | ||
163 | #ifndef BFD_ASSEMBLER | |
164 | #ifndef OBJ_AOUT | |
165 | #ifndef TE_PE | |
166 | #ifndef TE_GO32 | |
167 | /* Local labels starts with .L */ | |
168 | #define LOCAL_LABEL(name) (name[0] == '.' \ | |
169 | && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) | |
170 | #endif | |
171 | #endif | |
172 | #endif | |
173 | #endif | |
174 | ||
175 | #define LOCAL_LABELS_FB 1 | |
176 | ||
177 | #define tc_aout_pre_write_hook(x) {;} /* not used */ | |
178 | #define tc_crawl_symbol_chain(a) {;} /* not used */ | |
179 | #define tc_headers_hook(a) {;} /* not used */ | |
180 | ||
181 | extern const char extra_symbol_chars[]; | |
182 | #define tc_symbol_chars extra_symbol_chars | |
183 | ||
184 | #define MAX_OPERANDS 3 /* max operands per insn */ | |
185 | #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ | |
186 | #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ | |
187 | ||
188 | /* Prefixes will be emitted in the order defined below. | |
189 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
190 | instruction, and so must come before any prefixes. */ | |
191 | #define WAIT_PREFIX 0 | |
192 | #define LOCKREP_PREFIX 1 | |
193 | #define ADDR_PREFIX 2 | |
194 | #define DATA_PREFIX 3 | |
195 | #define SEG_PREFIX 4 | |
196 | #define MAX_PREFIXES 5 /* max prefixes per opcode */ | |
197 | ||
198 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
199 | #define REGISTER_PREFIX '%' | |
200 | #define IMMEDIATE_PREFIX '$' | |
201 | #define ABSOLUTE_PREFIX '*' | |
202 | ||
203 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f | |
204 | #define NOP_OPCODE (char) 0x90 | |
205 | ||
206 | /* register numbers */ | |
207 | #define EBP_REG_NUM 5 | |
208 | #define ESP_REG_NUM 4 | |
209 | ||
210 | /* modrm_byte.regmem for twobyte escape */ | |
211 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM | |
212 | /* index_base_byte.index for no index register addressing */ | |
213 | #define NO_INDEX_REGISTER ESP_REG_NUM | |
214 | /* index_base_byte.base for no base register addressing */ | |
215 | #define NO_BASE_REGISTER EBP_REG_NUM | |
216 | #define NO_BASE_REGISTER_16 6 | |
217 | ||
218 | /* these are the instruction mnemonic suffixes. */ | |
219 | #define DWORD_MNEM_SUFFIX 'l' | |
220 | #define WORD_MNEM_SUFFIX 'w' | |
221 | #define BYTE_MNEM_SUFFIX 'b' | |
222 | #define SHORT_MNEM_SUFFIX 's' | |
223 | #define LONG_MNEM_SUFFIX 'l' | |
224 | /* Intel Syntax */ | |
225 | #define LONG_DOUBLE_MNEM_SUFFIX 'x' | |
226 | /* Intel Syntax */ | |
227 | #define INTEL_DWORD_MNEM_SUFFIX 'd' | |
228 | ||
229 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ | |
230 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ | |
231 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) | |
232 | ||
233 | #define END_OF_INSN '\0' | |
234 | ||
235 | /* Intel Syntax */ | |
236 | /* Values 0-4 map onto scale factor */ | |
237 | #define BYTE_PTR 0 | |
238 | #define WORD_PTR 1 | |
239 | #define DWORD_PTR 2 | |
240 | #define QWORD_PTR 3 | |
241 | #define XWORD_PTR 4 | |
242 | #define SHORT 5 | |
243 | #define OFFSET_FLAT 6 | |
244 | #define FLAT 7 | |
245 | #define NONE_FOUND 8 | |
246 | /* | |
247 | When an operand is read in it is classified by its type. This type includes | |
248 | all the possible ways an operand can be used. Thus, '%eax' is both 'register | |
249 | # 0' and 'The Accumulator'. In our language this is expressed by OR'ing | |
250 | 'Reg32' (any 32 bit register) and 'Acc' (the accumulator). | |
251 | Operands are classified so that we can match given operand types with | |
252 | the opcode table in opcode/i386.h. | |
253 | */ | |
254 | /* register */ | |
255 | #define Reg8 0x1 /* 8 bit reg */ | |
256 | #define Reg16 0x2 /* 16 bit reg */ | |
257 | #define Reg32 0x4 /* 32 bit reg */ | |
258 | /* immediate */ | |
259 | #define Imm8 0x8 /* 8 bit immediate */ | |
260 | #define Imm8S 0x10 /* 8 bit immediate sign extended */ | |
261 | #define Imm16 0x20 /* 16 bit immediate */ | |
262 | #define Imm32 0x40 /* 32 bit immediate */ | |
263 | #define Imm1 0x80 /* 1 bit immediate */ | |
264 | /* memory */ | |
265 | #define BaseIndex 0x100 | |
266 | /* Disp8,16,32 are used in different ways, depending on the | |
267 | instruction. For jumps, they specify the size of the PC relative | |
268 | displacement, for baseindex type instructions, they specify the | |
269 | size of the offset relative to the base register, and for memory | |
270 | offset instructions such as `mov 1234,%al' they specify the size of | |
271 | the offset relative to the segment base. */ | |
272 | #define Disp8 0x200 /* 8 bit displacement */ | |
273 | #define Disp16 0x400 /* 16 bit displacement */ | |
274 | #define Disp32 0x800 /* 32 bit displacement */ | |
275 | /* specials */ | |
276 | #define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */ | |
277 | #define ShiftCount 0x2000 /* register to hold shift cound = cl */ | |
278 | #define Control 0x4000 /* Control register */ | |
279 | #define Debug 0x8000 /* Debug register */ | |
280 | #define Test 0x10000 /* Test register */ | |
281 | #define FloatReg 0x20000 /* Float register */ | |
282 | #define FloatAcc 0x40000 /* Float stack top %st(0) */ | |
283 | #define SReg2 0x80000 /* 2 bit segment register */ | |
284 | #define SReg3 0x100000 /* 3 bit segment register */ | |
285 | #define Acc 0x200000 /* Accumulator %al or %ax or %eax */ | |
286 | #define JumpAbsolute 0x400000 | |
287 | #define RegMMX 0x800000 /* MMX register */ | |
3afcee8e AM |
288 | #define RegXMM 0x1000000 /* XMM registers in PIII */ |
289 | #define EsSeg 0x2000000 /* String insn operand with fixed es segment */ | |
290 | /* InvMem is for instructions with a modrm byte that only allow a | |
291 | general register encoding in the i.tm.mode and i.tm.regmem fields, | |
292 | eg. control reg moves. They really ought to support a memory form, | |
293 | but don't, so we add an InvMem flag to the register operand to | |
294 | indicate that it should be encoded in the i.tm.regmem field. */ | |
295 | #define InvMem 0x4000000 | |
252b5132 RH |
296 | |
297 | #define Reg (Reg8|Reg16|Reg32) /* gen'l register */ | |
298 | #define WordReg (Reg16|Reg32) | |
299 | #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) | |
300 | #define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */ | |
301 | #define Disp (Disp8|Disp16|Disp32) /* General displacement */ | |
3afcee8e | 302 | #define AnyMem (Disp|BaseIndex|InvMem) /* General memory */ |
252b5132 RH |
303 | /* The following aliases are defined because the opcode table |
304 | carefully specifies the allowed memory types for each instruction. | |
305 | At the moment we can only tell a memory reference size by the | |
306 | instruction suffix, so there's not much point in defining Mem8, | |
307 | Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use | |
308 | the suffix directly to check memory operands. */ | |
309 | #define LLongMem AnyMem /* 64 bits (or more) */ | |
310 | #define LongMem AnyMem /* 32 bit memory ref */ | |
311 | #define ShortMem AnyMem /* 16 bit memory ref */ | |
312 | #define WordMem AnyMem /* 16 or 32 bit memory ref */ | |
313 | #define ByteMem AnyMem /* 8 bit memory ref */ | |
314 | ||
315 | #define SMALLEST_DISP_TYPE(num) \ | |
316 | (fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32) | |
317 | ||
318 | typedef struct | |
319 | { | |
320 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
321 | char *name; | |
322 | ||
323 | /* how many operands */ | |
324 | unsigned int operands; | |
325 | ||
326 | /* base_opcode is the fundamental opcode byte without optional | |
327 | prefix(es). */ | |
328 | unsigned int base_opcode; | |
329 | ||
330 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
331 | This field is also used to store the 8-bit opcode suffix for the | |
332 | AMD 3DNow! instructions. | |
333 | If this template has no extension opcode (the usual case) use None */ | |
334 | unsigned int extension_opcode; | |
335 | #define None 0xffff /* If no extension_opcode is possible. */ | |
336 | ||
337 | /* the bits in opcode_modifier are used to generate the final opcode from | |
338 | the base_opcode. These bits also are used to detect alternate forms of | |
339 | the same instruction */ | |
340 | unsigned int opcode_modifier; | |
341 | ||
342 | /* opcode_modifier bits: */ | |
343 | #define W 0x1 /* set if operands can be words or dwords | |
344 | encoded the canonical way */ | |
345 | #define D 0x2 /* D = 0 if Reg --> Regmem; | |
346 | D = 1 if Regmem --> Reg: MUST BE 0x2 */ | |
347 | #define Modrm 0x4 | |
252b5132 RH |
348 | #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ |
349 | #define ShortForm 0x10 /* register is in low 3 bits of opcode */ | |
350 | #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ | |
351 | #define Jump 0x40 /* special case for jump insns. */ | |
352 | #define JumpDword 0x80 /* call and jump */ | |
353 | #define JumpByte 0x100 /* loop and jecxz */ | |
354 | #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ | |
355 | #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ | |
356 | #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ | |
357 | #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ | |
358 | #define Size16 0x2000 /* needs size prefix if in 32-bit mode */ | |
359 | #define Size32 0x4000 /* needs size prefix if in 16-bit mode */ | |
360 | #define IgnoreSize 0x8000 /* instruction ignores operand size prefix */ | |
eecb386c AM |
361 | #define DefaultSize 0x10000 /* default insn size depends on mode */ |
362 | #define No_bSuf 0x20000 /* b suffix on instruction illegal */ | |
363 | #define No_wSuf 0x40000 /* w suffix on instruction illegal */ | |
364 | #define No_lSuf 0x80000 /* l suffix on instruction illegal */ | |
365 | #define No_sSuf 0x100000 /* s suffix on instruction illegal */ | |
366 | #define No_dSuf 0x200000 /* d suffix on instruction illegal */ | |
367 | #define No_xSuf 0x400000 /* x suffix on instruction illegal */ | |
368 | #define FWait 0x800000 /* instruction needs FWAIT */ | |
369 | #define IsString 0x1000000 /* quick test for string instructions */ | |
370 | #define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */ | |
371 | #define IsPrefix 0x4000000 /* opcode is a prefix */ | |
372 | #define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */ | |
252b5132 RH |
373 | #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ |
374 | ||
375 | /* operand_types[i] describes the type of operand i. This is made | |
376 | by OR'ing together all of the possible type masks. (e.g. | |
377 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
378 | either a register or an immediate operand */ | |
379 | unsigned int operand_types[3]; | |
380 | } | |
381 | template; | |
382 | ||
383 | /* | |
384 | 'templates' is for grouping together 'template' structures for opcodes | |
385 | of the same name. This is only used for storing the insns in the grand | |
386 | ole hash table of insns. | |
387 | The templates themselves start at START and range up to (but not including) | |
388 | END. | |
389 | */ | |
390 | typedef struct | |
391 | { | |
392 | const template *start; | |
393 | const template *end; | |
394 | } templates; | |
395 | ||
396 | /* these are for register name --> number & type hash lookup */ | |
397 | typedef struct | |
398 | { | |
399 | char *reg_name; | |
400 | unsigned int reg_type; | |
401 | unsigned int reg_num; | |
402 | } | |
403 | reg_entry; | |
404 | ||
405 | typedef struct | |
406 | { | |
407 | char *seg_name; | |
408 | unsigned int seg_prefix; | |
409 | } | |
410 | seg_entry; | |
411 | ||
412 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
413 | typedef struct | |
414 | { | |
415 | unsigned int regmem; /* codes register or memory operand */ | |
416 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
417 | unsigned int mode; /* how to interpret regmem & reg */ | |
418 | } | |
419 | modrm_byte; | |
420 | ||
421 | /* 386 opcode byte to code indirect addressing. */ | |
422 | typedef struct | |
423 | { | |
424 | unsigned base; | |
425 | unsigned index; | |
426 | unsigned scale; | |
427 | } | |
428 | sib_byte; | |
429 | ||
430 | /* The name of the global offset table generated by the compiler. Allow | |
431 | this to be overridden if need be. */ | |
432 | #ifndef GLOBAL_OFFSET_TABLE_NAME | |
433 | #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" | |
434 | #endif | |
435 | ||
436 | #ifdef BFD_ASSEMBLER | |
437 | void i386_validate_fix PARAMS ((struct fix *)); | |
438 | #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) | |
439 | #endif | |
440 | ||
441 | #endif /* TC_I386 */ | |
442 | ||
443 | #define md_operand(x) | |
444 | ||
445 | extern const struct relax_type md_relax_table[]; | |
446 | #define TC_GENERIC_RELAX_TABLE md_relax_table | |
447 | ||
448 | ||
449 | extern int flag_16bit_code; | |
450 | ||
252b5132 RH |
451 | #define md_do_align(n, fill, len, max, around) \ |
452 | if ((n) && !need_pass_2 \ | |
453 | && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ | |
b9e57a38 | 454 | && subseg_text_p (now_seg)) \ |
252b5132 RH |
455 | { \ |
456 | char *p; \ | |
457 | p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \ | |
458 | (symbolS *) 0, (offsetT) (n), (char *) 0); \ | |
459 | *p = 0x90; \ | |
460 | goto around; \ | |
461 | } | |
462 | ||
463 | extern void i386_align_code PARAMS ((fragS *, int)); | |
464 | ||
465 | #define HANDLE_ALIGN(fragP) \ | |
466 | if (fragP->fr_type == rs_align_code) \ | |
467 | i386_align_code (fragP, (fragP->fr_next->fr_address \ | |
468 | - fragP->fr_address \ | |
469 | - fragP->fr_fix)); | |
470 | ||
471 | /* call md_apply_fix3 with segment instead of md_apply_fix */ | |
472 | #define MD_APPLY_FIX3 | |
473 | ||
474 | void i386_print_statistics PARAMS ((FILE *)); | |
475 | #define tc_print_statistics i386_print_statistics | |
476 | ||
477 | #define md_number_to_chars number_to_chars_littleendian | |
478 | ||
479 | #ifdef SCO_ELF | |
480 | #define tc_init_after_args() sco_id () | |
481 | extern void sco_id PARAMS ((void)); | |
482 | #endif | |
483 | ||
484 | #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ | |
485 | ||
486 | /* end of tc-i386.h */ |