[deliverable/binutils-gdb.git] / gas / config / tc-i386.h

/* tc-i386.h -- Header file for tc-i386.c
   Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
   Free Software Foundation.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

#ifndef TC_I386
#define TC_I386 1

#ifdef ANSI_PROTOTYPES
struct fix;
#endif

#define TARGET_BYTES_BIG_ENDIAN	0

#ifdef TE_LYNX
#define TARGET_FORMAT		"coff-i386-lynx"
#endif

#ifdef BFD_ASSEMBLER
/* This is used to determine relocation types in tc-i386.c.  The first
   parameter is the current relocation type, the second one is the desired
   type.  The idea is that if the original type is already some kind of PIC
   relocation, we leave it alone, otherwise we give it the desired type */

#define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
extern int tc_i386_fix_adjustable PARAMS ((struct fix *));

#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
/* This arranges for gas/write.c to not apply a relocation if
   tc_fix_adjustable() says it is not adjustable.  */
#define TC_FIX_ADJUSTABLE(fixP) tc_fix_adjustable (fixP)
#endif

/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
 * It comes up in complicated expressions such as
 * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
 * the regular expressions.  The fixup specified here when used at runtime
 * implies that we should add the address of the GOT to the specified location,
 * and as a result we have simplified the expression into something we can use.
 */
#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC

/* This expression evaluates to false if the relocation is for a local object
   for which we still want to do the relocation at runtime.  True if we
   are willing to perform this relocation while building the .o file.
   This is only used for pcrel relocations, so GOTOFF does not need to be
   checked here.  I am not sure if some of the others are ever used with
   pcrel, but it is easier to be safe than sorry.  */

#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)				\
  ((FIX)->fx_r_type != BFD_RELOC_386_PLT32			\
   && (FIX)->fx_r_type != BFD_RELOC_386_GOT32			\
   && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC			\
   && ((FIX)->fx_addsy == NULL					\
       || (! S_IS_EXTERNAL ((FIX)->fx_addsy)			\
	   && ! S_IS_WEAK ((FIX)->fx_addsy)			\
	   && S_IS_DEFINED ((FIX)->fx_addsy)			\
	   && ! S_IS_COMMON ((FIX)->fx_addsy))))

#define TARGET_ARCH		bfd_arch_i386

#ifdef TE_NetBSD
#define AOUT_TARGET_FORMAT	"a.out-i386-netbsd"
#endif
#ifdef TE_386BSD
#define AOUT_TARGET_FORMAT	"a.out-i386-bsd"
#endif
#ifdef TE_LINUX
#define AOUT_TARGET_FORMAT	"a.out-i386-linux"
#endif
#ifdef TE_Mach
#define AOUT_TARGET_FORMAT	"a.out-mach3"
#endif
#ifdef TE_DYNIX
#define AOUT_TARGET_FORMAT	"a.out-i386-dynix"
#endif
#ifndef AOUT_TARGET_FORMAT
#define AOUT_TARGET_FORMAT	"a.out-i386"
#endif

#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
     || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
     || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format ()
#else
#ifdef OBJ_ELF
#define TARGET_FORMAT		"elf32-i386"
#endif
#ifdef OBJ_AOUT
#define TARGET_FORMAT		AOUT_TARGET_FORMAT
#endif
#endif

#else /* ! BFD_ASSEMBLER */

/* COFF STUFF */

#define COFF_MAGIC I386MAGIC
#define BFD_ARCH bfd_arch_i386
#define COFF_FLAGS F_AR32WR
#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
extern short tc_coff_fix2rtype PARAMS ((struct fix *));
#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
extern int tc_coff_sizemachdep PARAMS ((fragS *frag));

#ifdef TE_GO32
/* DJGPP now expects some sections to be 2**4 aligned.  */
#define SUB_SEGMENT_ALIGN(SEG)						\
  ((strcmp (obj_segment_name (SEG), ".text") == 0			\
    || strcmp (obj_segment_name (SEG), ".data") == 0			\
    || strcmp (obj_segment_name (SEG), ".bss") == 0			\
    || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0	\
    || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0	\
    || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0)	\
   ? 4									\
   : 2)
#else
#define SUB_SEGMENT_ALIGN(SEG) 2
#endif

#define TC_RVA_RELOC 7
/* Need this for PIC relocations */
#define NEED_FX_R_TYPE

#ifdef TE_386BSD
/* The BSDI linker apparently rejects objects with a machine type of
   M_386 (100).  */
#define AOUT_MACHTYPE 0
#else
#define AOUT_MACHTYPE 100
#endif

#undef REVERSE_SORT_RELOCS

#endif /* ! BFD_ASSEMBLER */

#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
extern int tc_i386_force_relocation PARAMS ((struct fix *));

#ifdef BFD_ASSEMBLER
#define NO_RELOC BFD_RELOC_NONE
#else
#define NO_RELOC 0
#endif
#define tc_coff_symbol_emit_hook(a)	;	/* not used */

#ifndef BFD_ASSEMBLER
#ifndef OBJ_AOUT
#ifndef TE_PE
#ifndef TE_GO32
/* Local labels starts with .L */
#define LOCAL_LABEL(name) (name[0] == '.' \
		 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
#endif
#endif
#endif
#endif

#define LOCAL_LABELS_FB 1

#define tc_aout_pre_write_hook(x)	{;}	/* not used */
#define tc_crawl_symbol_chain(a)	{;}	/* not used */
#define tc_headers_hook(a)		{;}	/* not used */

extern const char extra_symbol_chars[];
#define tc_symbol_chars extra_symbol_chars

#define MAX_OPERANDS 3		/* max operands per insn */
#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
#define MAX_MEMORY_OPERANDS 2	/* max memory refs per insn (string ops) */

/* Prefixes will be emitted in the order defined below.
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
   instruction, and so must come before any prefixes.  */
#define WAIT_PREFIX	0
#define LOCKREP_PREFIX	1
#define ADDR_PREFIX	2
#define DATA_PREFIX	3
#define SEG_PREFIX	4
#define MAX_PREFIXES	5	/* max prefixes per opcode */

/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
#define ABSOLUTE_PREFIX '*'

#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90

/* register numbers */
#define EBP_REG_NUM 5
#define ESP_REG_NUM 4

/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
/* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
/* index_base_byte.base for no base register addressing */
#define NO_BASE_REGISTER EBP_REG_NUM
#define NO_BASE_REGISTER_16 6

/* these are the instruction mnemonic suffixes.  */
#define WORD_MNEM_SUFFIX  'w'
#define BYTE_MNEM_SUFFIX  'b'
#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX  'l'
/* Intel Syntax */
#define LONG_DOUBLE_MNEM_SUFFIX 'x'
/* Intel Syntax */
#define DWORD_MNEM_SUFFIX 'd'

/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)

#define END_OF_INSN '\0'

/* Intel Syntax */
/* Values 0-4 map onto scale factor */
#define BYTE_PTR     0
#define WORD_PTR     1
#define DWORD_PTR    2
#define QWORD_PTR    3
#define XWORD_PTR    4
#define SHORT        5
#define OFFSET_FLAT  6
#define FLAT         7
#define NONE_FOUND   8

typedef struct
{
  /* instruction name sans width suffix ("mov" for movl insns) */
  char *name;

  /* how many operands */
  unsigned int operands;

  /* base_opcode is the fundamental opcode byte without optional
     prefix(es).  */
  unsigned int base_opcode;

  /* extension_opcode is the 3 bit extension for group <n> insns.
     This field is also used to store the 8-bit opcode suffix for the
     AMD 3DNow! instructions.
     If this template has no extension opcode (the usual case) use None */
  unsigned int extension_opcode;
#define None 0xffff		/* If no extension_opcode is possible.  */

  /* cpu feature flags */
  unsigned int cpu_flags;
#define Cpu086		  0x1	/* Any old cpu will do, 0 does the same */
#define Cpu186		  0x2	/* i186 or better required */
#define Cpu286		  0x4	/* i286 or better required */
#define Cpu386		  0x8	/* i386 or better required */
#define Cpu486		 0x10	/* i486 or better required */
#define Cpu586		 0x20	/* i585 or better required */
#define Cpu686		 0x40	/* i686 or better required */
#define CpuMMX		 0x80	/* MMX support required */
#define CpuSSE		0x100	/* Streaming SIMD extensions required */
#define Cpu3dnow	0x200	/* 3dnow! support required */

  /* the bits in opcode_modifier are used to generate the final opcode from
     the base_opcode.  These bits also are used to detect alternate forms of
     the same instruction */
  unsigned int opcode_modifier;

  /* opcode_modifier bits: */
#define W		   0x1	/* set if operands can be words or dwords
				   encoded the canonical way */
#define D		   0x2	/* D = 0 if Reg --> Regmem;
				   D = 1 if Regmem --> Reg:    MUST BE 0x2 */
#define Modrm		   0x4
#define FloatR		   0x8	/* src/dest swap for floats:   MUST BE 0x8 */
#define ShortForm	  0x10	/* register is in low 3 bits of opcode */
#define FloatMF		  0x20	/* FP insn memory format bit, sized by 0x4 */
#define Jump		  0x40	/* special case for jump insns.  */
#define JumpDword	  0x80  /* call and jump */
#define JumpByte	 0x100  /* loop and jecxz */
#define JumpInterSegment 0x200	/* special case for intersegment leaps/calls */
#define FloatD		 0x400	/* direction for float insns:  MUST BE 0x400 */
#define Seg2ShortForm	 0x800	/* encoding of load segment reg insns */
#define Seg3ShortForm	0x1000	/* fs/gs segment register insns.  */
#define Size16		0x2000	/* needs size prefix if in 32-bit mode */
#define Size32		0x4000	/* needs size prefix if in 16-bit mode */
#define IgnoreSize	0x8000  /* instruction ignores operand size prefix */
#define DefaultSize    0x10000  /* default insn size depends on mode */
#define No_bSuf	       0x20000	/* b suffix on instruction illegal */
#define No_wSuf	       0x40000	/* w suffix on instruction illegal */
#define No_lSuf	       0x80000	/* l suffix on instruction illegal */
#define No_sSuf	      0x100000	/* s suffix on instruction illegal */
#define No_dSuf       0x200000  /* d suffix on instruction illegal */
#define No_xSuf       0x400000  /* x suffix on instruction illegal */
#define FWait	      0x800000	/* instruction needs FWAIT */
#define IsString     0x1000000	/* quick test for string instructions */
#define regKludge    0x2000000	/* fake an extra reg operand for clr, imul */
#define IsPrefix     0x4000000	/* opcode is a prefix */
#define ImmExt	     0x8000000	/* instruction has extension in 8 bit imm */
#define Ugh	    0x80000000	/* deprecated fp insn, gets a warning */

  /* operand_types[i] describes the type of operand i.  This is made
     by OR'ing together all of the possible type masks.  (e.g.
     'operand_types[i] = Reg|Imm' specifies that operand i can be
     either a register or an immediate operand.  */
  unsigned int operand_types[3];

  /* operand_types[i] bits */
  /* register */
#define Reg8		   0x1	/* 8 bit reg */
#define Reg16		   0x2	/* 16 bit reg */
#define Reg32		   0x4	/* 32 bit reg */
  /* immediate */
#define Imm8		   0x8	/* 8 bit immediate */
#define Imm8S		  0x10	/* 8 bit immediate sign extended */
#define Imm16		  0x20	/* 16 bit immediate */
#define Imm32		  0x40	/* 32 bit immediate */
#define Imm1		  0x80	/* 1 bit immediate */
  /* memory */
#define BaseIndex	 0x100
  /* Disp8,16,32 are used in different ways, depending on the
     instruction.  For jumps, they specify the size of the PC relative
     displacement, for baseindex type instructions, they specify the
     size of the offset relative to the base register, and for memory
     offset instructions such as `mov 1234,%al' they specify the size of
     the offset relative to the segment base.  */
#define Disp8		 0x200	/* 8 bit displacement */
#define Disp16		 0x400	/* 16 bit displacement */
#define Disp32		 0x800	/* 32 bit displacement */
  /* specials */
#define InOutPortReg	0x1000	/* register to hold in/out port addr = dx */
#define ShiftCount	0x2000	/* register to hold shift cound = cl */
#define Control	        0x4000	/* Control register */
#define Debug	        0x8000	/* Debug register */
#define Test	       0x10000	/* Test register */
#define FloatReg       0x20000	/* Float register */
#define FloatAcc       0x40000	/* Float stack top %st(0) */
#define SReg2	       0x80000	/* 2 bit segment register */
#define SReg3	      0x100000	/* 3 bit segment register */
#define Acc	      0x200000	/* Accumulator %al or %ax or %eax */
#define JumpAbsolute  0x400000
#define RegMMX	      0x800000	/* MMX register */
#define RegXMM	     0x1000000	/* XMM registers in PIII */
#define EsSeg	     0x2000000	/* String insn operand with fixed es segment */
  /* InvMem is for instructions with a modrm byte that only allow a
     general register encoding in the i.tm.mode and i.tm.regmem fields,
     eg. control reg moves.  They really ought to support a memory form,
     but don't, so we add an InvMem flag to the register operand to
     indicate that it should be encoded in the i.tm.regmem field.  */
#define InvMem	     0x4000000

#define Reg	(Reg8|Reg16|Reg32)	/* gen'l register */
#define WordReg (Reg16|Reg32)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
#define Imm	(Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
#define Disp	(Disp8|Disp16|Disp32)	/* General displacement */
#define AnyMem	(Disp|BaseIndex|InvMem)	/* General memory */
  /* The following aliases are defined because the opcode table
     carefully specifies the allowed memory types for each instruction.
     At the moment we can only tell a memory reference size by the
     instruction suffix, so there's not much point in defining Mem8,
     Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
     the suffix directly to check memory operands.  */
#define LLongMem AnyMem		/* 64 bits (or more) */
#define LongMem AnyMem		/* 32 bit memory ref */
#define ShortMem AnyMem		/* 16 bit memory ref */
#define WordMem AnyMem		/* 16 or 32 bit memory ref */
#define ByteMem AnyMem		/* 8 bit memory ref */
}
template;

/*
  'templates' is for grouping together 'template' structures for opcodes
  of the same name.  This is only used for storing the insns in the grand
  ole hash table of insns.
  The templates themselves start at START and range up to (but not including)
  END.
  */
typedef struct
{
  const template *start;
  const template *end;
}
templates;

/* these are for register name --> number & type hash lookup */
typedef struct
{
  char *reg_name;
  unsigned int reg_type;
  unsigned int reg_num;
}
reg_entry;

typedef struct
{
  char *seg_name;
  unsigned int seg_prefix;
}
seg_entry;

/* 386 operand encoding bytes:  see 386 book for details of this.  */
typedef struct
{
  unsigned int regmem;	/* codes register or memory operand */
  unsigned int reg;	/* codes register operand (or extended opcode) */
  unsigned int mode;	/* how to interpret regmem & reg */
}
modrm_byte;

/* 386 opcode byte to code indirect addressing.  */
typedef struct
{
  unsigned base;
  unsigned index;
  unsigned scale;
}
sib_byte;

/* x86 arch names and features */
typedef struct
{
  const char *name;	/* arch name */
  unsigned int flags;	/* cpu feature flags */
}
arch_entry;

/* The name of the global offset table generated by the compiler. Allow
   this to be overridden if need be.  */
#ifndef GLOBAL_OFFSET_TABLE_NAME
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif

#ifdef BFD_ASSEMBLER
void i386_validate_fix PARAMS ((struct fix *));
#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
#endif

#endif /* TC_I386 */

#define md_operand(x)

extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table

#define md_do_align(n, fill, len, max, around)				\
if ((n) && !need_pass_2							\
    && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))		\
    && subseg_text_p (now_seg))						\
  {									\
    char *p;								\
    p = frag_var (rs_align_code, 15, 1, (relax_substateT) max,		\
		  (symbolS *) 0, (offsetT) (n), (char *) 0);		\
    *p = 0x90;								\
    goto around;							\
  }

extern void i386_align_code PARAMS ((fragS *, int));

#define HANDLE_ALIGN(fragP)						\
if (fragP->fr_type == rs_align_code) 					\
  i386_align_code (fragP, (fragP->fr_next->fr_address			\
			   - fragP->fr_address				\
			   - fragP->fr_fix));

/* call md_apply_fix3 with segment instead of md_apply_fix */
#define MD_APPLY_FIX3

void i386_print_statistics PARAMS ((FILE *));
#define tc_print_statistics i386_print_statistics

#define md_number_to_chars number_to_chars_littleendian

#ifdef SCO_ELF
#define tc_init_after_args() sco_id ()
extern void sco_id PARAMS ((void));
#endif

#define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
Commit	Line	Data
252b5132	1	/* tc-i386.h -- Header file for tc-i386.c
4c63da97	2	Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
b9e57a38	3	Free Software Foundation.
252b5132 RH	4
	5	This file is part of GAS, the GNU Assembler.
	6
	7	GAS is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	GAS is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GAS; see the file COPYING. If not, write to the Free
	19	Software Foundation, 59 Temple Place - Suite 330, Boston, MA
	20	02111-1307, USA. */
	21
	22	#ifndef TC_I386
	23	#define TC_I386 1
	24
	25	#ifdef ANSI_PROTOTYPES
	26	struct fix;
	27	#endif
	28
	29	#define TARGET_BYTES_BIG_ENDIAN 0
	30
	31	#ifdef TE_LYNX
	32	#define TARGET_FORMAT "coff-i386-lynx"
	33	#endif
	34
	35	#ifdef BFD_ASSEMBLER
	36	/* This is used to determine relocation types in tc-i386.c. The first
	37	parameter is the current relocation type, the second one is the desired
	38	type. The idea is that if the original type is already some kind of PIC
	39	relocation, we leave it alone, otherwise we give it the desired type */
	40
252b5132 RH	41	#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
	42	extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
	43
4b853faa	44	#if (defined (OBJ_MAYBE_ELF) \|\| defined (OBJ_ELF) \|\| defined (OBJ_MAYBE_COFF) \|\| defined (OBJ_COFF)) && !defined (TE_PE)
8f36cd18 AO	45	/* This arranges for gas/write.c to not apply a relocation if
	46	tc_fix_adjustable() says it is not adjustable. */
	47	#define TC_FIX_ADJUSTABLE(fixP) tc_fix_adjustable (fixP)
	48	#endif
	49
252b5132	50	/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
4a4f25cf	51	* It comes up in complicated expressions such as
252b5132	52	* _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
4a4f25cf	53	* the regular expressions. The fixup specified here when used at runtime
252b5132 RH	54	* implies that we should add the address of the GOT to the specified location,
	55	* and as a result we have simplified the expression into something we can use.
	56	*/
	57	#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
	58
	59	/* This expression evaluates to false if the relocation is for a local object
	60	for which we still want to do the relocation at runtime. True if we
	61	are willing to perform this relocation while building the .o file.
	62	This is only used for pcrel relocations, so GOTOFF does not need to be
	63	checked here. I am not sure if some of the others are ever used with
4a4f25cf	64	pcrel, but it is easier to be safe than sorry. */
252b5132 RH	65
	66	#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
	67	((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
	68	&& (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
	69	&& (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
	70	&& ((FIX)->fx_addsy == NULL \
	71	\|\| (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
	72	&& ! S_IS_WEAK ((FIX)->fx_addsy) \
	73	&& S_IS_DEFINED ((FIX)->fx_addsy) \
	74	&& ! S_IS_COMMON ((FIX)->fx_addsy))))
	75
	76	#define TARGET_ARCH bfd_arch_i386
	77
252b5132	78	#ifdef TE_NetBSD
4c63da97	79	#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
252b5132 RH	80	#endif
252b5132 RH	81	#ifdef TE_386BSD
4c63da97	82	#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
252b5132 RH	83	#endif
252b5132 RH	84	#ifdef TE_LINUX
4c63da97	85	#define AOUT_TARGET_FORMAT "a.out-i386-linux"
252b5132 RH	86	#endif
252b5132 RH	87	#ifdef TE_Mach
4c63da97	88	#define AOUT_TARGET_FORMAT "a.out-mach3"
252b5132 RH	89	#endif
252b5132 RH	90	#ifdef TE_DYNIX
4c63da97	91	#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
252b5132	92	#endif
4c63da97 AM	93	#ifndef AOUT_TARGET_FORMAT
4c63da97 AM	94	#define AOUT_TARGET_FORMAT "a.out-i386"
252b5132	95	#endif
252b5132	96
4c63da97 AM	97	#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
	98	\|\| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
	99	\|\| (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
	100	extern const char *i386_target_format PARAMS ((void));
	101	#define TARGET_FORMAT i386_target_format ()
	102	#else
252b5132 RH	103	#ifdef OBJ_ELF
	104	#define TARGET_FORMAT "elf32-i386"
	105	#endif
4c63da97 AM	106	#ifdef OBJ_AOUT
4c63da97 AM	107	#define TARGET_FORMAT AOUT_TARGET_FORMAT
252b5132 RH	108	#endif
	109	#endif
	110
	111	#else /* ! BFD_ASSEMBLER */
	112
	113	/* COFF STUFF */
	114
	115	#define COFF_MAGIC I386MAGIC
	116	#define BFD_ARCH bfd_arch_i386
	117	#define COFF_FLAGS F_AR32WR
	118	#define TC_COUNT_RELOC(x) ((x)->fx_addsy \|\| (x)->fx_r_type==7)
	119	#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
	120	extern short tc_coff_fix2rtype PARAMS ((struct fix *));
	121	#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
	122	extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
1a1ae23e ILT	123
	124	#ifdef TE_GO32
	125	/* DJGPP now expects some sections to be 2*4 aligned. /
	126	#define SUB_SEGMENT_ALIGN(SEG) \
	127	((strcmp (obj_segment_name (SEG), ".text") == 0 \
	128	\|\| strcmp (obj_segment_name (SEG), ".data") == 0 \
da5d444c	129	\|\| strcmp (obj_segment_name (SEG), ".bss") == 0 \
1a1ae23e ILT	130	\|\| strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \
	131	\|\| strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \
	132	\|\| strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \
	133	? 4 \
	134	: 2)
	135	#else
252b5132	136	#define SUB_SEGMENT_ALIGN(SEG) 2
1a1ae23e ILT	137	#endif
1a1ae23e ILT	138
252b5132 RH	139	#define TC_RVA_RELOC 7
	140	/* Need this for PIC relocations */
	141	#define NEED_FX_R_TYPE
	142
252b5132 RH	143	#ifdef TE_386BSD
	144	/* The BSDI linker apparently rejects objects with a machine type of
	145	M_386 (100). */
	146	#define AOUT_MACHTYPE 0
	147	#else
	148	#define AOUT_MACHTYPE 100
	149	#endif
	150
	151	#undef REVERSE_SORT_RELOCS
	152
	153	#endif /* ! BFD_ASSEMBLER */
	154
	155	#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
	156	extern int tc_i386_force_relocation PARAMS ((struct fix *));
	157
	158	#ifdef BFD_ASSEMBLER
	159	#define NO_RELOC BFD_RELOC_NONE
	160	#else
	161	#define NO_RELOC 0
	162	#endif
	163	#define tc_coff_symbol_emit_hook(a) ; /* not used */
	164
	165	#ifndef BFD_ASSEMBLER
	166	#ifndef OBJ_AOUT
	167	#ifndef TE_PE
	168	#ifndef TE_GO32
	169	/* Local labels starts with .L */
	170	#define LOCAL_LABEL(name) (name[0] == '.' \
	171	&& (name[1] == 'L' \|\| name[1] == 'X' \|\| name[1] == '.'))
	172	#endif
	173	#endif
	174	#endif
	175	#endif
	176
	177	#define LOCAL_LABELS_FB 1
	178
	179	#define tc_aout_pre_write_hook(x) {;} /* not used */
	180	#define tc_crawl_symbol_chain(a) {;} /* not used */
	181	#define tc_headers_hook(a) {;} /* not used */
	182
	183	extern const char extra_symbol_chars[];
	184	#define tc_symbol_chars extra_symbol_chars
	185
	186	#define MAX_OPERANDS 3 /* max operands per insn */
	187	#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
	188	#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
	189
	190	/* Prefixes will be emitted in the order defined below.
	191	WAIT_PREFIX must be the first prefix since FWAIT is really is an
4a4f25cf	192	instruction, and so must come before any prefixes. */
252b5132 RH	193	#define WAIT_PREFIX 0
	194	#define LOCKREP_PREFIX 1
	195	#define ADDR_PREFIX 2
	196	#define DATA_PREFIX 3
	197	#define SEG_PREFIX 4
	198	#define MAX_PREFIXES 5 /* max prefixes per opcode */
	199
	200	/* we define the syntax here (modulo base,index,scale syntax) */
	201	#define REGISTER_PREFIX '%'
	202	#define IMMEDIATE_PREFIX '$'
	203	#define ABSOLUTE_PREFIX '*'
	204
	205	#define TWO_BYTE_OPCODE_ESCAPE 0x0f
	206	#define NOP_OPCODE (char) 0x90
	207
	208	/* register numbers */
	209	#define EBP_REG_NUM 5
	210	#define ESP_REG_NUM 4
	211
	212	/* modrm_byte.regmem for twobyte escape */
	213	#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
	214	/* index_base_byte.index for no index register addressing */
	215	#define NO_INDEX_REGISTER ESP_REG_NUM
	216	/* index_base_byte.base for no base register addressing */
	217	#define NO_BASE_REGISTER EBP_REG_NUM
	218	#define NO_BASE_REGISTER_16 6
	219
	220	/* these are the instruction mnemonic suffixes. */
252b5132 RH	221	#define WORD_MNEM_SUFFIX 'w'
	222	#define BYTE_MNEM_SUFFIX 'b'
	223	#define SHORT_MNEM_SUFFIX 's'
	224	#define LONG_MNEM_SUFFIX 'l'
	225	/* Intel Syntax */
	226	#define LONG_DOUBLE_MNEM_SUFFIX 'x'
	227	/* Intel Syntax */
add0c677	228	#define DWORD_MNEM_SUFFIX 'd'
252b5132 RH	229
	230	/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
	231	#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
	232	#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
	233
	234	#define END_OF_INSN '\0'
	235
	236	/* Intel Syntax */
	237	/* Values 0-4 map onto scale factor */
	238	#define BYTE_PTR 0
	239	#define WORD_PTR 1
	240	#define DWORD_PTR 2
	241	#define QWORD_PTR 3
	242	#define XWORD_PTR 4
	243	#define SHORT 5
	244	#define OFFSET_FLAT 6
	245	#define FLAT 7
	246	#define NONE_FOUND 8
252b5132	247
252b5132 RH	248	typedef struct
	249	{
	250	/* instruction name sans width suffix ("mov" for movl insns) */
	251	char *name;
	252
	253	/* how many operands */
	254	unsigned int operands;
	255
	256	/* base_opcode is the fundamental opcode byte without optional
	257	prefix(es). */
	258	unsigned int base_opcode;
	259
	260	/* extension_opcode is the 3 bit extension for group <n> insns.
	261	This field is also used to store the 8-bit opcode suffix for the
	262	AMD 3DNow! instructions.
	263	If this template has no extension opcode (the usual case) use None */
	264	unsigned int extension_opcode;
4a4f25cf	265	#define None 0xffff /* If no extension_opcode is possible. */
252b5132	266
e413e4e9 AM	267	/* cpu feature flags */
	268	unsigned int cpu_flags;
	269	#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
	270	#define Cpu186 0x2 /* i186 or better required */
	271	#define Cpu286 0x4 /* i286 or better required */
	272	#define Cpu386 0x8 /* i386 or better required */
	273	#define Cpu486 0x10 /* i486 or better required */
	274	#define Cpu586 0x20 /* i585 or better required */
	275	#define Cpu686 0x40 /* i686 or better required */
	276	#define CpuMMX 0x80 /* MMX support required */
	277	#define CpuSSE 0x100 /* Streaming SIMD extensions required */
	278	#define Cpu3dnow 0x200 /* 3dnow! support required */
	279
252b5132 RH	280	/* the bits in opcode_modifier are used to generate the final opcode from
	281	the base_opcode. These bits also are used to detect alternate forms of
	282	the same instruction */
	283	unsigned int opcode_modifier;
	284
	285	/* opcode_modifier bits: */
	286	#define W 0x1 /* set if operands can be words or dwords
	287	encoded the canonical way */
	288	#define D 0x2 /* D = 0 if Reg --> Regmem;
	289	D = 1 if Regmem --> Reg: MUST BE 0x2 */
	290	#define Modrm 0x4
252b5132 RH	291	#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
	292	#define ShortForm 0x10 /* register is in low 3 bits of opcode */
	293	#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
4a4f25cf	294	#define Jump 0x40 /* special case for jump insns. */
252b5132 RH	295	#define JumpDword 0x80 /* call and jump */
	296	#define JumpByte 0x100 /* loop and jecxz */
	297	#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
	298	#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
	299	#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
4a4f25cf	300	#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
252b5132 RH	301	#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
	302	#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
	303	#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
eecb386c AM	304	#define DefaultSize 0x10000 /* default insn size depends on mode */
	305	#define No_bSuf 0x20000 /* b suffix on instruction illegal */
	306	#define No_wSuf 0x40000 /* w suffix on instruction illegal */
	307	#define No_lSuf 0x80000 /* l suffix on instruction illegal */
	308	#define No_sSuf 0x100000 /* s suffix on instruction illegal */
	309	#define No_dSuf 0x200000 /* d suffix on instruction illegal */
	310	#define No_xSuf 0x400000 /* x suffix on instruction illegal */
	311	#define FWait 0x800000 /* instruction needs FWAIT */
	312	#define IsString 0x1000000 /* quick test for string instructions */
	313	#define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
	314	#define IsPrefix 0x4000000 /* opcode is a prefix */
	315	#define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
252b5132 RH	316	#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
	317
	318	/* operand_types[i] describes the type of operand i. This is made
	319	by OR'ing together all of the possible type masks. (e.g.
	320	'operand_types[i] = Reg\|Imm' specifies that operand i can be
e413e4e9	321	either a register or an immediate operand. */
252b5132	322	unsigned int operand_types[3];
e413e4e9 AM	323
	324	/* operand_types[i] bits */
	325	/* register */
	326	#define Reg8 0x1 /* 8 bit reg */
	327	#define Reg16 0x2 /* 16 bit reg */
	328	#define Reg32 0x4 /* 32 bit reg */
	329	/* immediate */
	330	#define Imm8 0x8 /* 8 bit immediate */
	331	#define Imm8S 0x10 /* 8 bit immediate sign extended */
	332	#define Imm16 0x20 /* 16 bit immediate */
	333	#define Imm32 0x40 /* 32 bit immediate */
	334	#define Imm1 0x80 /* 1 bit immediate */
	335	/* memory */
	336	#define BaseIndex 0x100
	337	/* Disp8,16,32 are used in different ways, depending on the
	338	instruction. For jumps, they specify the size of the PC relative
	339	displacement, for baseindex type instructions, they specify the
	340	size of the offset relative to the base register, and for memory
	341	offset instructions such as `mov 1234,%al' they specify the size of
	342	the offset relative to the segment base. */
	343	#define Disp8 0x200 /* 8 bit displacement */
	344	#define Disp16 0x400 /* 16 bit displacement */
	345	#define Disp32 0x800 /* 32 bit displacement */
	346	/* specials */
	347	#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
	348	#define ShiftCount 0x2000 /* register to hold shift cound = cl */
	349	#define Control 0x4000 /* Control register */
	350	#define Debug 0x8000 /* Debug register */
	351	#define Test 0x10000 /* Test register */
	352	#define FloatReg 0x20000 /* Float register */
	353	#define FloatAcc 0x40000 /* Float stack top %st(0) */
	354	#define SReg2 0x80000 /* 2 bit segment register */
	355	#define SReg3 0x100000 /* 3 bit segment register */
	356	#define Acc 0x200000 /* Accumulator %al or %ax or %eax */
	357	#define JumpAbsolute 0x400000
	358	#define RegMMX 0x800000 /* MMX register */
	359	#define RegXMM 0x1000000 /* XMM registers in PIII */
	360	#define EsSeg 0x2000000 /* String insn operand with fixed es segment */
	361	/* InvMem is for instructions with a modrm byte that only allow a
	362	general register encoding in the i.tm.mode and i.tm.regmem fields,
	363	eg. control reg moves. They really ought to support a memory form,
	364	but don't, so we add an InvMem flag to the register operand to
	365	indicate that it should be encoded in the i.tm.regmem field. */
	366	#define InvMem 0x4000000
	367
	368	#define Reg (Reg8\|Reg16\|Reg32) /* gen'l register */
	369	#define WordReg (Reg16\|Reg32)
	370	#define ImplicitRegister (InOutPortReg\|ShiftCount\|Acc\|FloatAcc)
	371	#define Imm (Imm8\|Imm8S\|Imm16\|Imm32) /* gen'l immediate */
	372	#define Disp (Disp8\|Disp16\|Disp32) /* General displacement */
	373	#define AnyMem (Disp\|BaseIndex\|InvMem) /* General memory */
	374	/* The following aliases are defined because the opcode table
	375	carefully specifies the allowed memory types for each instruction.
	376	At the moment we can only tell a memory reference size by the
	377	instruction suffix, so there's not much point in defining Mem8,
	378	Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
	379	the suffix directly to check memory operands. */
	380	#define LLongMem AnyMem /* 64 bits (or more) */
	381	#define LongMem AnyMem /* 32 bit memory ref */
	382	#define ShortMem AnyMem /* 16 bit memory ref */
	383	#define WordMem AnyMem /* 16 or 32 bit memory ref */
	384	#define ByteMem AnyMem /* 8 bit memory ref */
252b5132 RH	385	}
	386	template;
	387
	388	/*
	389	'templates' is for grouping together 'template' structures for opcodes
	390	of the same name. This is only used for storing the insns in the grand
	391	ole hash table of insns.
	392	The templates themselves start at START and range up to (but not including)
	393	END.
	394	*/
	395	typedef struct
e413e4e9 AM	396	{
	397	const template *start;
	398	const template *end;
	399	}
	400	templates;
252b5132 RH	401
	402	/* these are for register name --> number & type hash lookup */
	403	typedef struct
e413e4e9 AM	404	{
	405	char *reg_name;
	406	unsigned int reg_type;
	407	unsigned int reg_num;
	408	}
252b5132 RH	409	reg_entry;
	410
	411	typedef struct
e413e4e9 AM	412	{
	413	char *seg_name;
	414	unsigned int seg_prefix;
	415	}
252b5132 RH	416	seg_entry;
252b5132 RH	417
4a4f25cf	418	/* 386 operand encoding bytes: see 386 book for details of this. */
252b5132	419	typedef struct
e413e4e9 AM	420	{
	421	unsigned int regmem; /* codes register or memory operand */
	422	unsigned int reg; /* codes register operand (or extended opcode) */
	423	unsigned int mode; /* how to interpret regmem & reg */
	424	}
252b5132 RH	425	modrm_byte;
252b5132 RH	426
4a4f25cf	427	/* 386 opcode byte to code indirect addressing. */
252b5132	428	typedef struct
e413e4e9 AM	429	{
	430	unsigned base;
	431	unsigned index;
	432	unsigned scale;
	433	}
252b5132 RH	434	sib_byte;
252b5132 RH	435
e413e4e9 AM	436	/* x86 arch names and features */
	437	typedef struct
	438	{
	439	const char name; / arch name */
	440	unsigned int flags; /* cpu feature flags */
	441	}
	442	arch_entry;
	443
252b5132	444	/* The name of the global offset table generated by the compiler. Allow
4a4f25cf	445	this to be overridden if need be. */
252b5132 RH	446	#ifndef GLOBAL_OFFSET_TABLE_NAME
	447	#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
	448	#endif
	449
	450	#ifdef BFD_ASSEMBLER
	451	void i386_validate_fix PARAMS ((struct fix *));
	452	#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
	453	#endif
	454
	455	#endif /* TC_I386 */
	456
	457	#define md_operand(x)
	458
	459	extern const struct relax_type md_relax_table[];
	460	#define TC_GENERIC_RELAX_TABLE md_relax_table
	461
252b5132 RH	462	#define md_do_align(n, fill, len, max, around) \
	463	if ((n) && !need_pass_2 \
	464	&& (!(fill) \|\| ((char)*(fill) == (char)0x90 && (len) == 1)) \
b9e57a38	465	&& subseg_text_p (now_seg)) \
252b5132 RH	466	{ \
	467	char *p; \
	468	p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
	469	(symbolS ) 0, (offsetT) (n), (char ) 0); \
	470	*p = 0x90; \
	471	goto around; \
	472	}
	473
	474	extern void i386_align_code PARAMS ((fragS *, int));
	475
	476	#define HANDLE_ALIGN(fragP) \
	477	if (fragP->fr_type == rs_align_code) \
	478	i386_align_code (fragP, (fragP->fr_next->fr_address \
	479	- fragP->fr_address \
	480	- fragP->fr_fix));
	481
	482	/* call md_apply_fix3 with segment instead of md_apply_fix */
	483	#define MD_APPLY_FIX3
	484
	485	void i386_print_statistics PARAMS ((FILE *));
	486	#define tc_print_statistics i386_print_statistics
	487
	488	#define md_number_to_chars number_to_chars_littleendian
	489
	490	#ifdef SCO_ELF
	491	#define tc_init_after_args() sco_id ()
	492	extern void sco_id PARAMS ((void));
	493	#endif
	494
	495	#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */