[deliverable/binutils-gdb.git] / gas / config / tc-i386.h

/* i386.h -- Header file for i386.c
   Copyright (C) 1989, Free Software Foundation.
   
   This file is part of GAS, the GNU Assembler.
   
   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.
   
   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to
   the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */

#define TC_I386 1

#define AOUT_MACHTYPE 100
#define REVERSE_SORT_RELOCS

#define tc_crawl_symbol_chain(a)	; /* not used */
#define tc_headers_hook(a)		; /* not used */
    
#define MAX_OPERANDS 3		/* max operands per insn */
#define MAX_PREFIXES 4		/* max prefixes per opcode */
#define MAX_IMMEDIATE_OPERANDS 2 /* max immediates per insn */
#define MAX_MEMORY_OPERANDS 2	/* max memory ref per insn
				 * lcall uses 2
				 */
    /* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
#define ABSOLUTE_PREFIX '*'
#define PREFIX_SEPERATOR '/'
    
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
    
    /* register numbers */
#define EBP_REG_NUM 5
#define ESP_REG_NUM 4
    
    /* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
    /* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
    /* index_base_byte.base for no base register addressing */
#define NO_BASE_REGISTER EBP_REG_NUM
    
    /* these are the att as opcode suffixes, making movl --> mov, for example */
#define DWORD_OPCODE_SUFFIX 'l'
#define WORD_OPCODE_SUFFIX  'w'
#define BYTE_OPCODE_SUFFIX  'b'
    
    /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3                /* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)

#define END_OF_INSN '\0'

/*
  When an operand is read in it is classified by its type.  This type includes
  all the possible ways an operand can be used.  Thus, '%eax' is both 'register
  # 0' and 'The Accumulator'.  In our language this is expressed by OR'ing
  'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
  Operands are classified so that we can match given operand types with
  the opcode table in i386-opcode.h.
  */
#define Unknown 0x0
/* register */
#define Reg8    0x1		/* 8 bit reg */
#define Reg16   0x2		/* 16 bit reg */
#define Reg32   0x4		/* 32 bit reg */
#define Reg     (Reg8|Reg16|Reg32)    /* gen'l register */
#define WordReg (Reg16|Reg32)	/* for push/pop operands */
/* immediate */
#define Imm8    0x8		/* 8 bit immediate */
#define Imm8S	0x10		/* 8 bit immediate sign extended */
#define Imm16   0x20		/* 16 bit immediate */
#define Imm32   0x40		/* 32 bit immediate */
#define Imm1    0x80    	/* 1 bit immediate */
#define ImmUnknown Imm32	/* for unknown expressions */
#define Imm     (Imm8|Imm8S|Imm16|Imm32)    /* gen'l immediate */
/* memory */
#define Disp8   0x200		/* 8 bit displacement (for jumps) */
#define Disp16  0x400		/* 16 bit displacement */
#define Disp32  0x800		/* 32 bit displacement */
#define Disp    (Disp8|Disp16|Disp32) /* General displacement */
#define DispUnknown Disp32	/* for unknown size displacements */
#define Mem8    0x1000
#define Mem16   0x2000
#define Mem32   0x4000
#define BaseIndex 0x8000
#define Mem     (Disp|Mem8|Mem16|Mem32|BaseIndex) /* General memory */
#define WordMem   (Mem16|Mem32|Disp|BaseIndex)
#define ByteMem   (Mem8|Disp|BaseIndex)
/* specials */
#define InOutPortReg 0x10000	/* register to hold in/out port addr = dx */
#define ShiftCount 0x20000	/* register to hold shift cound = cl */
#define Control 0x40000		/* Control register */
#define Debug   0x80000		/* Debug register */
#define Test    0x100000		/* Test register */
#define FloatReg 0x200000	/* Float register */
#define FloatAcc 0x400000	/* Float stack top %st(0) */
#define SReg2   0x800000		/* 2 bit segment register */
#define SReg3   0x1000000		/* 3 bit segment register */
#define Acc     0x2000000		/* Accumulator %al or %ax or %eax */
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
#define JumpAbsolute 0x4000000
#define Abs8  0x08000000
#define Abs16 0x10000000
#define Abs32 0x20000000
#define Abs (Abs8|Abs16|Abs32)

#define MODE_FROM_DISP_SIZE(t) \
    ((t&(Disp8)) ? 1 : \
     ((t&(Disp32)) ? 2 : 0))

#define Byte (Reg8|Imm8|Imm8S)
#define Word (Reg16|Imm16)
#define DWord (Reg32|Imm32)

/* convert opcode suffix ('b' 'w' 'l' typically) into type specifyer */
#define OPCODE_SUFFIX_TO_TYPE(s)                 \
    (s == BYTE_OPCODE_SUFFIX ? Byte : \
     (s == WORD_OPCODE_SUFFIX ? Word : DWord))

#define FITS_IN_SIGNED_BYTE(num) ((num) >= -128 && (num) <= 127)
#define FITS_IN_UNSIGNED_BYTE(num) ((num) >= 0 && (num) <= 255)
#define FITS_IN_UNSIGNED_WORD(num) ((num) >= 0 && (num) <= 65535)
#define FITS_IN_SIGNED_WORD(num) ((num) >= -32768 && (num) <= 32767)

#define SMALLEST_DISP_TYPE(num) \
    FITS_IN_SIGNED_BYTE(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32)

#define SMALLEST_IMM_TYPE(num) \
    (num == 1) ? (Imm1|Imm8|Imm8S|Imm16|Imm32): \
    FITS_IN_SIGNED_BYTE(num) ? (Imm8S|Imm8|Imm16|Imm32) : \
    FITS_IN_UNSIGNED_BYTE(num) ? (Imm8|Imm16|Imm32): \
    (FITS_IN_SIGNED_WORD(num)||FITS_IN_UNSIGNED_WORD(num)) ? (Imm16|Imm32) : \
    (Imm32)

typedef struct {
	/* instruction name sans width suffix ("mov" for movl insns) */
	char          *name;
	
	/* how many operands */
	unsigned int    operands;
	
	/* base_opcode is the fundamental opcode byte with a optional prefix(es). */
	unsigned int    base_opcode;
	
	/* extension_opcode is the 3 bit extension for group <n> insns.
	   If this template has no extension opcode (the usual case) use None */
	unsigned char    extension_opcode;
#define None 0xff		/* If no extension_opcode is possible. */
	
	/* the bits in opcode_modifier are used to generate the final opcode from
	   the base_opcode.  These bits also are used to detect alternate forms of
	   the same instruction */
	unsigned int    opcode_modifier;
	
	/* opcode_modifier bits: */
#define W        0x1	/* set if operands are words or dwords */
#define D        0x2	/* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */
	/* direction flag for floating insns:  MUST BE 0x400 */
#define FloatD 0x400
	/* shorthand */
#define DW (D|W)
#define ShortForm 0x10		/* register is in low 3 bits of opcode */
#define ShortFormW 0x20		/* ShortForm and W bit is 0x8 */
#define Seg2ShortForm 0x40	/* encoding of load segment reg insns */
#define Seg3ShortForm 0x80	/* fs/gs segment register insns. */
#define Jump 0x100		/* special case for jump insns. */
#define JumpInterSegment 0x200	/* special case for intersegment leaps/calls */
	/* 0x400 CANNOT BE USED since it's already used by FloatD above */
#define DONT_USE 0x400
#define NoModrm 0x800
#define Modrm 0x1000
#define imulKludge 0x2000
#define JumpByte 0x4000
#define JumpDword 0x8000
#define ReverseRegRegmem 0x10000
	
	/* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the
	   instuction comes in byte, word, and dword sizes and is encoded into
	   machine code in the canonical way. */
#define COMES_IN_ALL_SIZES (W)
	
	/* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the
	   source and destination operands can be reversed by setting either
	   the D (for integer insns) or the FloatD (for floating insns) bit
	   in base_opcode. */
#define COMES_IN_BOTH_DIRECTIONS (D|FloatD)
	
	/* operand_types[i] describes the type of operand i.  This is made
	   by OR'ing together all of the possible type masks.  (e.g.
	   'operand_types[i] = Reg|Imm' specifies that operand i can be
	   either a register or an immediate operand */
	unsigned int operand_types[3];
} template;

/*
  'templates' is for grouping together 'template' structures for opcodes
  of the same name.  This is only used for storing the insns in the grand
  ole hash table of insns.
  The templates themselves start at START and range up to (but not including)
  END.
  */
typedef struct {
	template      *start;
	template      *end;
} templates;

/* these are for register name --> number & type hash lookup */
typedef struct {
	char * reg_name;
	unsigned int   reg_type;
	unsigned int   reg_num;
} reg_entry;

typedef struct {
	char * seg_name;
	unsigned int   seg_prefix;
} seg_entry;

/* these are for prefix name --> prefix code hash lookup */
typedef struct {
	char * prefix_name;
	unsigned char  prefix_code;
} prefix_entry;

/* 386 operand encoding bytes:  see 386 book for details of this. */
typedef struct {
	unsigned regmem:3;	     /* codes register or memory operand */
	unsigned reg:3;	     /* codes register operand (or extended opcode) */
	unsigned mode:2;	     /* how to interpret regmem & reg */
} modrm_byte;

/* 386 opcode byte to code indirect addressing. */
typedef struct {
	unsigned base:3;
	unsigned index:3;
	unsigned scale:2;
} base_index_byte;

/* end of tc-i386.h */
Commit	Line	Data
fecd2382 RP	1	/* i386.h -- Header file for i386.c
fecd2382 RP	2	Copyright (C) 1989, Free Software Foundation.
fecd2382	3
a39116f1 RP	4	This file is part of GAS, the GNU Assembler.
	5
	6	GAS is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2, or (at your option)
	9	any later version.
	10
	11	GAS is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with GAS; see the file COPYING. If not, write to
	18	the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
	19
fecd2382 RP	20	#define TC_I386 1
fecd2382 RP	21
a39116f1 RP	22	#define AOUT_MACHTYPE 100
	23	#define REVERSE_SORT_RELOCS
	24
fecd2382 RP	25	#define tc_crawl_symbol_chain(a) ; /* not used */
fecd2382 RP	26	#define tc_headers_hook(a) ; /* not used */
a39116f1	27
fecd2382 RP	28	#define MAX_OPERANDS 3 /* max operands per insn */
	29	#define MAX_PREFIXES 4 /* max prefixes per opcode */
	30	#define MAX_IMMEDIATE_OPERANDS 2 /* max immediates per insn */
	31	#define MAX_MEMORY_OPERANDS 2 /* max memory ref per insn
	32	* lcall uses 2
	33	*/
a39116f1	34	/* we define the syntax here (modulo base,index,scale syntax) */
fecd2382 RP	35	#define REGISTER_PREFIX '%'
	36	#define IMMEDIATE_PREFIX '$'
	37	#define ABSOLUTE_PREFIX '*'
	38	#define PREFIX_SEPERATOR '/'
a39116f1	39
fecd2382	40	#define TWO_BYTE_OPCODE_ESCAPE 0x0f
a39116f1 RP	41
a39116f1 RP	42	/* register numbers */
fecd2382 RP	43	#define EBP_REG_NUM 5
fecd2382 RP	44	#define ESP_REG_NUM 4
a39116f1 RP	45
a39116f1 RP	46	/* modrm_byte.regmem for twobyte escape */
fecd2382	47	#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
a39116f1	48	/* index_base_byte.index for no index register addressing */
fecd2382	49	#define NO_INDEX_REGISTER ESP_REG_NUM
a39116f1	50	/* index_base_byte.base for no base register addressing */
fecd2382	51	#define NO_BASE_REGISTER EBP_REG_NUM
a39116f1 RP	52
a39116f1 RP	53	/* these are the att as opcode suffixes, making movl --> mov, for example */
fecd2382 RP	54	#define DWORD_OPCODE_SUFFIX 'l'
	55	#define WORD_OPCODE_SUFFIX 'w'
	56	#define BYTE_OPCODE_SUFFIX 'b'
a39116f1 RP	57
a39116f1 RP	58	/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
fecd2382 RP	59	#define REGMEM_FIELD_HAS_REG 0x3 /* always = 0x3 */
	60	#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
	61
	62	#define END_OF_INSN '\0'
	63
	64	/*
a39116f1 RP	65	When an operand is read in it is classified by its type. This type includes
	66	all the possible ways an operand can be used. Thus, '%eax' is both 'register
	67	# 0' and 'The Accumulator'. In our language this is expressed by OR'ing
	68	'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
	69	Operands are classified so that we can match given operand types with
	70	the opcode table in i386-opcode.h.
	71	*/
fecd2382 RP	72	#define Unknown 0x0
	73	/* register */
	74	#define Reg8 0x1 /* 8 bit reg */
	75	#define Reg16 0x2 /* 16 bit reg */
	76	#define Reg32 0x4 /* 32 bit reg */
	77	#define Reg (Reg8\|Reg16\|Reg32) /* gen'l register */
	78	#define WordReg (Reg16\|Reg32) /* for push/pop operands */
	79	/* immediate */
	80	#define Imm8 0x8 /* 8 bit immediate */
	81	#define Imm8S 0x10 /* 8 bit immediate sign extended */
	82	#define Imm16 0x20 /* 16 bit immediate */
	83	#define Imm32 0x40 /* 32 bit immediate */
	84	#define Imm1 0x80 /* 1 bit immediate */
	85	#define ImmUnknown Imm32 /* for unknown expressions */
	86	#define Imm (Imm8\|Imm8S\|Imm16\|Imm32) /* gen'l immediate */
	87	/* memory */
	88	#define Disp8 0x200 /* 8 bit displacement (for jumps) */
	89	#define Disp16 0x400 /* 16 bit displacement */
	90	#define Disp32 0x800 /* 32 bit displacement */
	91	#define Disp (Disp8\|Disp16\|Disp32) /* General displacement */
	92	#define DispUnknown Disp32 /* for unknown size displacements */
	93	#define Mem8 0x1000
	94	#define Mem16 0x2000
	95	#define Mem32 0x4000
	96	#define BaseIndex 0x8000
	97	#define Mem (Disp\|Mem8\|Mem16\|Mem32\|BaseIndex) /* General memory */
	98	#define WordMem (Mem16\|Mem32\|Disp\|BaseIndex)
	99	#define ByteMem (Mem8\|Disp\|BaseIndex)
	100	/* specials */
	101	#define InOutPortReg 0x10000 /* register to hold in/out port addr = dx */
	102	#define ShiftCount 0x20000 /* register to hold shift cound = cl */
	103	#define Control 0x40000 /* Control register */
	104	#define Debug 0x80000 /* Debug register */
	105	#define Test 0x100000 /* Test register */
	106	#define FloatReg 0x200000 /* Float register */
	107	#define FloatAcc 0x400000 /* Float stack top %st(0) */
	108	#define SReg2 0x800000 /* 2 bit segment register */
	109	#define SReg3 0x1000000 /* 3 bit segment register */
	110	#define Acc 0x2000000 /* Accumulator %al or %ax or %eax */
	111	#define ImplicitRegister (InOutPortReg\|ShiftCount\|Acc\|FloatAcc)
	112	#define JumpAbsolute 0x4000000
	113	#define Abs8 0x08000000
	114	#define Abs16 0x10000000
	115	#define Abs32 0x20000000
	116	#define Abs (Abs8\|Abs16\|Abs32)
	117
	118	#define MODE_FROM_DISP_SIZE(t) \
a39116f1 RP	119	((t&(Disp8)) ? 1 : \
a39116f1 RP	120	((t&(Disp32)) ? 2 : 0))
fecd2382 RP	121
	122	#define Byte (Reg8\|Imm8\|Imm8S)
	123	#define Word (Reg16\|Imm16)
	124	#define DWord (Reg32\|Imm32)
	125
	126	/* convert opcode suffix ('b' 'w' 'l' typically) into type specifyer */
	127	#define OPCODE_SUFFIX_TO_TYPE(s) \
a39116f1 RP	128	(s == BYTE_OPCODE_SUFFIX ? Byte : \
a39116f1 RP	129	(s == WORD_OPCODE_SUFFIX ? Word : DWord))
fecd2382 RP	130
	131	#define FITS_IN_SIGNED_BYTE(num) ((num) >= -128 && (num) <= 127)
	132	#define FITS_IN_UNSIGNED_BYTE(num) ((num) >= 0 && (num) <= 255)
	133	#define FITS_IN_UNSIGNED_WORD(num) ((num) >= 0 && (num) <= 65535)
	134	#define FITS_IN_SIGNED_WORD(num) ((num) >= -32768 && (num) <= 32767)
	135
	136	#define SMALLEST_DISP_TYPE(num) \
a39116f1	137	FITS_IN_SIGNED_BYTE(num) ? (Disp8\|Disp32\|Abs8\|Abs32) : (Disp32\|Abs32)
fecd2382 RP	138
fecd2382 RP	139	#define SMALLEST_IMM_TYPE(num) \
a39116f1 RP	140	(num == 1) ? (Imm1\|Imm8\|Imm8S\|Imm16\|Imm32): \
	141	FITS_IN_SIGNED_BYTE(num) ? (Imm8S\|Imm8\|Imm16\|Imm32) : \
	142	FITS_IN_UNSIGNED_BYTE(num) ? (Imm8\|Imm16\|Imm32): \
	143	(FITS_IN_SIGNED_WORD(num)\|\|FITS_IN_UNSIGNED_WORD(num)) ? (Imm16\|Imm32) : \
	144	(Imm32)
fecd2382 RP	145
fecd2382 RP	146	typedef struct {
a39116f1 RP	147	/* instruction name sans width suffix ("mov" for movl insns) */
	148	char *name;
	149
	150	/* how many operands */
	151	unsigned int operands;
	152
	153	/* base_opcode is the fundamental opcode byte with a optional prefix(es). */
	154	unsigned int base_opcode;
	155
	156	/* extension_opcode is the 3 bit extension for group <n> insns.
	157	If this template has no extension opcode (the usual case) use None */
	158	unsigned char extension_opcode;
fecd2382	159	#define None 0xff /* If no extension_opcode is possible. */
a39116f1 RP	160
	161	/* the bits in opcode_modifier are used to generate the final opcode from
	162	the base_opcode. These bits also are used to detect alternate forms of
	163	the same instruction */
	164	unsigned int opcode_modifier;
	165
	166	/* opcode_modifier bits: */
fecd2382 RP	167	#define W 0x1 /* set if operands are words or dwords */
fecd2382 RP	168	#define D 0x2 /* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */
a39116f1	169	/* direction flag for floating insns: MUST BE 0x400 */
fecd2382	170	#define FloatD 0x400
a39116f1	171	/* shorthand */
fecd2382 RP	172	#define DW (D\|W)
	173	#define ShortForm 0x10 /* register is in low 3 bits of opcode */
	174	#define ShortFormW 0x20 /* ShortForm and W bit is 0x8 */
	175	#define Seg2ShortForm 0x40 /* encoding of load segment reg insns */
	176	#define Seg3ShortForm 0x80 /* fs/gs segment register insns. */
	177	#define Jump 0x100 /* special case for jump insns. */
	178	#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
a39116f1	179	/* 0x400 CANNOT BE USED since it's already used by FloatD above */
fecd2382 RP	180	#define DONT_USE 0x400
	181	#define NoModrm 0x800
	182	#define Modrm 0x1000
	183	#define imulKludge 0x2000
	184	#define JumpByte 0x4000
	185	#define JumpDword 0x8000
	186	#define ReverseRegRegmem 0x10000
a39116f1 RP	187
	188	/* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the
	189	instuction comes in byte, word, and dword sizes and is encoded into
	190	machine code in the canonical way. */
fecd2382	191	#define COMES_IN_ALL_SIZES (W)
a39116f1 RP	192
	193	/* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the
	194	source and destination operands can be reversed by setting either
	195	the D (for integer insns) or the FloatD (for floating insns) bit
	196	in base_opcode. */
fecd2382	197	#define COMES_IN_BOTH_DIRECTIONS (D\|FloatD)
a39116f1 RP	198
	199	/* operand_types[i] describes the type of operand i. This is made
	200	by OR'ing together all of the possible type masks. (e.g.
	201	'operand_types[i] = Reg\|Imm' specifies that operand i can be
	202	either a register or an immediate operand */
	203	unsigned int operand_types[3];
fecd2382 RP	204	} template;
	205
	206	/*
	207	'templates' is for grouping together 'template' structures for opcodes
	208	of the same name. This is only used for storing the insns in the grand
	209	ole hash table of insns.
	210	The templates themselves start at START and range up to (but not including)
	211	END.
a39116f1	212	*/
fecd2382	213	typedef struct {
a39116f1 RP	214	template *start;
a39116f1 RP	215	template *end;
fecd2382 RP	216	} templates;
	217
	218	/* these are for register name --> number & type hash lookup */
	219	typedef struct {
a39116f1 RP	220	char * reg_name;
	221	unsigned int reg_type;
	222	unsigned int reg_num;
fecd2382 RP	223	} reg_entry;
	224
	225	typedef struct {
a39116f1 RP	226	char * seg_name;
a39116f1 RP	227	unsigned int seg_prefix;
fecd2382 RP	228	} seg_entry;
	229
	230	/* these are for prefix name --> prefix code hash lookup */
	231	typedef struct {
a39116f1 RP	232	char * prefix_name;
a39116f1 RP	233	unsigned char prefix_code;
fecd2382 RP	234	} prefix_entry;
	235
	236	/* 386 operand encoding bytes: see 386 book for details of this. */
	237	typedef struct {
a39116f1 RP	238	unsigned regmem:3; /* codes register or memory operand */
	239	unsigned reg:3; /* codes register operand (or extended opcode) */
	240	unsigned mode:2; /* how to interpret regmem & reg */
fecd2382 RP	241	} modrm_byte;
	242
	243	/* 386 opcode byte to code indirect addressing. */
	244	typedef struct {
a39116f1 RP	245	unsigned base:3;
	246	unsigned index:3;
	247	unsigned scale:2;
fecd2382 RP	248	} base_index_byte;
	249
	250	/* end of tc-i386.h */