Commit | Line | Data |
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542e1629 | 1 | /* tc-i386.h -- Header file for tc-i386.c |
dddc8a82 | 2 | Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation. |
03678945 | 3 | |
a39116f1 | 4 | This file is part of GAS, the GNU Assembler. |
03678945 | 5 | |
a39116f1 RP |
6 | GAS is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
03678945 | 10 | |
a39116f1 RP |
11 | GAS is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
03678945 | 15 | |
a39116f1 | 16 | You should have received a copy of the GNU General Public License |
414a1069 ILT |
17 | along with GAS; see the file COPYING. If not, write to the Free |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
19 | 02111-1307, USA. */ | |
a39116f1 | 20 | |
03678945 | 21 | #ifndef TC_I386 |
fecd2382 RP |
22 | #define TC_I386 1 |
23 | ||
f59fb6ca ILT |
24 | #ifdef ANSI_PROTOTYPES |
25 | struct fix; | |
26 | #endif | |
27 | ||
d7bf6158 ILT |
28 | #define TARGET_BYTES_BIG_ENDIAN 0 |
29 | ||
03678945 KR |
30 | #ifdef TE_LYNX |
31 | #define TARGET_FORMAT "coff-i386-lynx" | |
32 | #endif | |
33 | ||
34 | #ifdef BFD_ASSEMBLER | |
35 | /* This is used to determine relocation types in tc-i386.c. The first | |
36 | parameter is the current relocation type, the second one is the desired | |
37 | type. The idea is that if the original type is already some kind of PIC | |
38 | relocation, we leave it alone, otherwise we give it the desired type */ | |
39 | ||
40 | #define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \ | |
41 | (X) != BFD_RELOC_386_GOTOFF && \ | |
42 | (X) != BFD_RELOC_386_GOT32 && \ | |
43 | (X) != BFD_RELOC_386_GOTPC) ? Y : X) | |
44 | ||
45 | #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) | |
f59fb6ca | 46 | extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); |
03678945 KR |
47 | |
48 | /* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE. | |
49 | * It comes up in complicated expressions such as | |
50 | * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with | |
51 | * the regular expressions. The fixup specified here when used at runtime | |
52 | * implies that we should add the address of the GOT to the specified location, | |
53 | * and as a result we have simplified the expression into something we can use. | |
54 | */ | |
55 | #define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC | |
56 | ||
57 | /* This expression evaluates to false if the relocation is for a local object | |
58 | for which we still want to do the relocation at runtime. True if we | |
59 | are willing to perform this relocation while building the .o file. | |
60 | This is only used for pcrel relocations, so GOTOFF does not need to be | |
61 | checked here. I am not sure if some of the others are ever used with | |
62 | pcrel, but it is easier to be safe than sorry. */ | |
63 | ||
8b398c53 ILT |
64 | #define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ |
65 | ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ | |
66 | && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ | |
67 | && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ | |
68 | && ((FIX)->fx_addsy == NULL \ | |
69 | || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ | |
70 | && ! S_IS_WEAK ((FIX)->fx_addsy) \ | |
71 | && S_IS_DEFINED ((FIX)->fx_addsy) \ | |
72 | && ! S_IS_COMMON ((FIX)->fx_addsy)))) | |
03678945 KR |
73 | |
74 | #define TARGET_ARCH bfd_arch_i386 | |
a39116f1 | 75 | |
03678945 KR |
76 | #ifdef OBJ_AOUT |
77 | #ifdef TE_NetBSD | |
78 | #define TARGET_FORMAT "a.out-i386-netbsd" | |
79 | #endif | |
80 | #ifdef TE_386BSD | |
81 | #define TARGET_FORMAT "a.out-i386-bsd" | |
82 | #endif | |
83 | #ifdef TE_LINUX | |
84 | #define TARGET_FORMAT "a.out-i386-linux" | |
85 | #endif | |
86 | #ifdef TE_Mach | |
87 | #define TARGET_FORMAT "a.out-mach3" | |
88 | #endif | |
f59fb6ca ILT |
89 | #ifdef TE_DYNIX |
90 | #define TARGET_FORMAT "a.out-i386-dynix" | |
91 | #endif | |
03678945 KR |
92 | #ifndef TARGET_FORMAT |
93 | #define TARGET_FORMAT "a.out-i386" | |
94 | #endif | |
95 | #endif /* OBJ_AOUT */ | |
542e1629 | 96 | |
03678945 KR |
97 | #ifdef OBJ_ELF |
98 | #define TARGET_FORMAT "elf32-i386" | |
99 | #endif | |
100 | ||
f59fb6ca ILT |
101 | #ifdef OBJ_MAYBE_ELF |
102 | #ifdef OBJ_MAYBE_COFF | |
103 | extern const char *i386_target_format PARAMS ((void)); | |
104 | #define TARGET_FORMAT i386_target_format () | |
105 | #endif | |
106 | #endif | |
107 | ||
03678945 KR |
108 | #else /* ! BFD_ASSEMBLER */ |
109 | ||
110 | /* COFF STUFF */ | |
111 | ||
112 | #define COFF_MAGIC I386MAGIC | |
113 | #define BFD_ARCH bfd_arch_i386 | |
114 | #define COFF_FLAGS F_AR32WR | |
d7bf6158 ILT |
115 | #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) |
116 | #define TC_FORCE_RELOCATION(x) ((x)->fx_r_type==7) | |
03678945 | 117 | #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) |
f59fb6ca | 118 | extern short tc_coff_fix2rtype PARAMS ((struct fix *)); |
03678945 KR |
119 | #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag) |
120 | extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); | |
121 | #define SUB_SEGMENT_ALIGN(SEG) 2 | |
d7bf6158 | 122 | #define TC_RVA_RELOC 7 |
03678945 KR |
123 | /* Need this for PIC relocations */ |
124 | #define NEED_FX_R_TYPE | |
125 | ||
d7bf6158 ILT |
126 | |
127 | #ifdef TE_386BSD | |
128 | /* The BSDI linker apparently rejects objects with a machine type of | |
129 | M_386 (100). */ | |
130 | #define AOUT_MACHTYPE 0 | |
131 | #else | |
a2a5a4fa | 132 | #define AOUT_MACHTYPE 100 |
d7bf6158 ILT |
133 | #endif |
134 | ||
03678945 KR |
135 | #undef REVERSE_SORT_RELOCS |
136 | ||
137 | #endif /* ! BFD_ASSEMBLER */ | |
138 | ||
139 | #ifdef BFD_ASSEMBLER | |
140 | #define NO_RELOC BFD_RELOC_NONE | |
141 | #else | |
142 | #define NO_RELOC 0 | |
143 | #endif | |
144 | #define tc_coff_symbol_emit_hook(a) ; /* not used */ | |
145 | ||
f59fb6ca | 146 | #ifndef BFD_ASSEMBLER |
03678945 | 147 | #ifndef OBJ_AOUT |
d7bf6158 | 148 | #ifndef TE_PE |
8b398c53 | 149 | #ifndef TE_GO32 |
03678945 KR |
150 | /* Local labels starts with .L */ |
151 | #define LOCAL_LABEL(name) (name[0] == '.' \ | |
152 | && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) | |
03678945 | 153 | #endif |
d7bf6158 | 154 | #endif |
f59fb6ca | 155 | #endif |
8b398c53 | 156 | #endif |
f59fb6ca | 157 | |
a2a5a4fa | 158 | #define LOCAL_LABELS_FB 1 |
03678945 KR |
159 | |
160 | #define tc_aout_pre_write_hook(x) {;} /* not used */ | |
161 | #define tc_crawl_symbol_chain(a) {;} /* not used */ | |
162 | #define tc_headers_hook(a) {;} /* not used */ | |
542e1629 | 163 | |
fecd2382 | 164 | #define MAX_OPERANDS 3 /* max operands per insn */ |
aa56747a | 165 | #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ |
4498e3d6 | 166 | #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ |
03678945 | 167 | |
aa56747a ILT |
168 | /* Prefixes will be emitted in the order defined below. |
169 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
170 | instruction, and so must come before any prefixes. */ | |
171 | #define WAIT_PREFIX 0 | |
172 | #define LOCKREP_PREFIX 1 | |
173 | #define ADDR_PREFIX 2 | |
174 | #define DATA_PREFIX 3 | |
175 | #define SEG_PREFIX 4 | |
176 | #define MAX_PREFIXES 5 /* max prefixes per opcode */ | |
177 | ||
542e1629 | 178 | /* we define the syntax here (modulo base,index,scale syntax) */ |
fecd2382 RP |
179 | #define REGISTER_PREFIX '%' |
180 | #define IMMEDIATE_PREFIX '$' | |
181 | #define ABSOLUTE_PREFIX '*' | |
182 | #define PREFIX_SEPERATOR '/' | |
03678945 | 183 | |
fecd2382 | 184 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f |
03678945 KR |
185 | #define NOP_OPCODE (char) 0x90 |
186 | ||
542e1629 | 187 | /* register numbers */ |
fecd2382 RP |
188 | #define EBP_REG_NUM 5 |
189 | #define ESP_REG_NUM 4 | |
03678945 | 190 | |
542e1629 | 191 | /* modrm_byte.regmem for twobyte escape */ |
fecd2382 | 192 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM |
542e1629 | 193 | /* index_base_byte.index for no index register addressing */ |
fecd2382 | 194 | #define NO_INDEX_REGISTER ESP_REG_NUM |
542e1629 | 195 | /* index_base_byte.base for no base register addressing */ |
fecd2382 | 196 | #define NO_BASE_REGISTER EBP_REG_NUM |
03678945 KR |
197 | |
198 | /* these are the att as opcode suffixes, making movl --> mov, for example */ | |
fecd2382 RP |
199 | #define DWORD_OPCODE_SUFFIX 'l' |
200 | #define WORD_OPCODE_SUFFIX 'w' | |
201 | #define BYTE_OPCODE_SUFFIX 'b' | |
03678945 KR |
202 | |
203 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ | |
204 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ | |
fecd2382 RP |
205 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) |
206 | ||
207 | #define END_OF_INSN '\0' | |
208 | ||
209 | /* | |
a39116f1 RP |
210 | When an operand is read in it is classified by its type. This type includes |
211 | all the possible ways an operand can be used. Thus, '%eax' is both 'register | |
212 | # 0' and 'The Accumulator'. In our language this is expressed by OR'ing | |
213 | 'Reg32' (any 32 bit register) and 'Acc' (the accumulator). | |
214 | Operands are classified so that we can match given operand types with | |
215 | the opcode table in i386-opcode.h. | |
216 | */ | |
fecd2382 | 217 | /* register */ |
4498e3d6 ILT |
218 | #define Reg8 0x1 /* 8 bit reg */ |
219 | #define Reg16 0x2 /* 16 bit reg */ | |
220 | #define Reg32 0x4 /* 32 bit reg */ | |
fecd2382 | 221 | /* immediate */ |
4498e3d6 ILT |
222 | #define Imm8 0x8 /* 8 bit immediate */ |
223 | #define Imm8S 0x10 /* 8 bit immediate sign extended */ | |
224 | #define Imm16 0x20 /* 16 bit immediate */ | |
225 | #define Imm32 0x40 /* 32 bit immediate */ | |
226 | #define Imm1 0x80 /* 1 bit immediate */ | |
fecd2382 | 227 | /* memory */ |
4498e3d6 ILT |
228 | #define BaseIndex 0x100 |
229 | /* Disp8,16,32 are used in different ways, depending on the | |
230 | instruction. For jumps, they specify the size of the PC relative | |
231 | displacement, for baseindex type instructions, they specify the | |
232 | size of the offset relative to the base register, and for memory | |
233 | offset instructions such as `mov 1234,%al' they specify the size of | |
234 | the offset relative to the segment base. */ | |
235 | #define Disp8 0x200 /* 8 bit displacement */ | |
236 | #define Disp16 0x400 /* 16 bit displacement */ | |
237 | #define Disp32 0x800 /* 32 bit displacement */ | |
238 | /* Mem8,16,32 are used to limit the allowed sizes of memory operands */ | |
239 | #define Mem8 0x1000 | |
240 | #define Mem16 0x2000 | |
241 | #define Mem32 0x4000 | |
fecd2382 | 242 | /* specials */ |
4498e3d6 ILT |
243 | #define InOutPortReg 0x10000 /* register to hold in/out port addr = dx */ |
244 | #define ShiftCount 0x20000 /* register to hold shift cound = cl */ | |
245 | #define Control 0x40000 /* Control register */ | |
246 | #define Debug 0x80000 /* Debug register */ | |
247 | #define Test 0x100000 /* Test register */ | |
248 | #define FloatReg 0x200000 /* Float register */ | |
249 | #define FloatAcc 0x400000 /* Float stack top %st(0) */ | |
250 | #define SReg2 0x800000 /* 2 bit segment register */ | |
251 | #define SReg3 0x1000000 /* 3 bit segment register */ | |
252 | #define Acc 0x2000000 /* Accumulator %al or %ax or %eax */ | |
fecd2382 | 253 | #define JumpAbsolute 0x4000000 |
4498e3d6 ILT |
254 | #define Abs8 0x8000000 |
255 | #define Abs16 0x10000000 | |
256 | #define Abs32 0x20000000 | |
257 | #define RegMMX 0x40000000 /* MMX register */ | |
258 | #define EsSeg 0x80000000 /* String insn operand with fixed es segment */ | |
259 | ||
260 | #define Reg (Reg8|Reg16|Reg32) /* gen'l register */ | |
261 | #define WordReg (Reg16|Reg32) | |
262 | #define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */ | |
263 | #define Disp (Disp8|Disp16|Disp32) /* General displacement */ | |
264 | #define Mem (Mem8|Mem16|Mem32|Disp|BaseIndex) /* General memory */ | |
265 | #define WordMem (Mem16|Mem32|Disp|BaseIndex) | |
266 | #define ByteMem (Mem8|Disp|BaseIndex) | |
267 | #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) | |
268 | #define Abs (Abs8|Abs16|Abs32) | |
fecd2382 | 269 | |
fecd2382 RP |
270 | #define Byte (Reg8|Imm8|Imm8S) |
271 | #define Word (Reg16|Imm16) | |
272 | #define DWord (Reg32|Imm32) | |
273 | ||
fecd2382 | 274 | #define SMALLEST_DISP_TYPE(num) \ |
542e1629 | 275 | fits_in_signed_byte(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32) |
fecd2382 | 276 | |
03678945 KR |
277 | typedef struct |
278 | { | |
279 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
280 | char *name; | |
281 | ||
282 | /* how many operands */ | |
283 | unsigned int operands; | |
284 | ||
285 | /* base_opcode is the fundamental opcode byte with a optional prefix(es). */ | |
286 | unsigned int base_opcode; | |
287 | ||
288 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
289 | If this template has no extension opcode (the usual case) use None */ | |
290 | unsigned char extension_opcode; | |
291 | #define None 0xff /* If no extension_opcode is possible. */ | |
292 | ||
293 | /* the bits in opcode_modifier are used to generate the final opcode from | |
294 | the base_opcode. These bits also are used to detect alternate forms of | |
295 | the same instruction */ | |
296 | unsigned int opcode_modifier; | |
297 | ||
298 | /* opcode_modifier bits: */ | |
4498e3d6 ILT |
299 | #define W 0x1 /* set if operands can be words or dwords |
300 | encoded the canonical way: MUST BE 0x1 */ | |
301 | #define D 0x2 /* D = 0 if Reg --> Regmem; | |
302 | D = 1 if Regmem --> Reg: MUST BE 0x2 */ | |
303 | #define Modrm 0x4 | |
304 | #define ReverseRegRegmem 0x8 | |
305 | #define ShortForm 0x10 /* register is in low 3 bits of opcode */ | |
306 | #define ShortFormW 0x20 /* ShortForm and W bit is 0x8 */ | |
307 | #define Seg2ShortForm 0x40 /* encoding of load segment reg insns */ | |
308 | #define Seg3ShortForm 0x80 /* fs/gs segment register insns. */ | |
309 | #define Jump 0x100 /* special case for jump insns. */ | |
fecd2382 | 310 | #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ |
4498e3d6 ILT |
311 | #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ |
312 | #define JumpByte 0x800 | |
313 | #define JumpDword 0x1000 | |
314 | #define FWait 0x2000 /* instruction needs FWAIT */ | |
315 | #define Data16 0x4000 /* needs data prefix if in 32-bit mode */ | |
316 | #define Data32 0x8000 /* needs data prefix if in 16-bit mode */ | |
317 | #define IsString 0x100000 /* quick test for string instructions */ | |
318 | #define regKludge 0x200000 /* fake an extra reg operand for clr, imul */ | |
319 | ||
320 | #define DW (D|W) /* shorthand */ | |
03678945 KR |
321 | |
322 | /* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the | |
323 | source and destination operands can be reversed by setting either | |
324 | the D (for integer insns) or the FloatD (for floating insns) bit | |
325 | in base_opcode. */ | |
fecd2382 | 326 | #define COMES_IN_BOTH_DIRECTIONS (D|FloatD) |
03678945 KR |
327 | |
328 | /* operand_types[i] describes the type of operand i. This is made | |
329 | by OR'ing together all of the possible type masks. (e.g. | |
330 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
331 | either a register or an immediate operand */ | |
332 | unsigned int operand_types[3]; | |
333 | } | |
334 | template; | |
fecd2382 RP |
335 | |
336 | /* | |
337 | 'templates' is for grouping together 'template' structures for opcodes | |
338 | of the same name. This is only used for storing the insns in the grand | |
339 | ole hash table of insns. | |
340 | The templates themselves start at START and range up to (but not including) | |
341 | END. | |
a39116f1 | 342 | */ |
03678945 KR |
343 | typedef struct |
344 | { | |
345 | template *start; | |
346 | template *end; | |
347 | } templates; | |
fecd2382 RP |
348 | |
349 | /* these are for register name --> number & type hash lookup */ | |
03678945 KR |
350 | typedef struct |
351 | { | |
352 | char *reg_name; | |
353 | unsigned int reg_type; | |
354 | unsigned int reg_num; | |
355 | } | |
356 | ||
357 | reg_entry; | |
358 | ||
359 | typedef struct | |
360 | { | |
361 | char *seg_name; | |
362 | unsigned int seg_prefix; | |
363 | } | |
fecd2382 | 364 | |
03678945 | 365 | seg_entry; |
fecd2382 RP |
366 | |
367 | /* these are for prefix name --> prefix code hash lookup */ | |
03678945 KR |
368 | typedef struct |
369 | { | |
370 | char *prefix_name; | |
371 | unsigned char prefix_code; | |
372 | } | |
373 | ||
374 | prefix_entry; | |
fecd2382 RP |
375 | |
376 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
03678945 KR |
377 | typedef struct |
378 | { | |
379 | unsigned regmem:3; /* codes register or memory operand */ | |
380 | unsigned reg:3; /* codes register operand (or extended opcode) */ | |
381 | unsigned mode:2; /* how to interpret regmem & reg */ | |
382 | } | |
383 | ||
384 | modrm_byte; | |
fecd2382 RP |
385 | |
386 | /* 386 opcode byte to code indirect addressing. */ | |
03678945 KR |
387 | typedef struct |
388 | { | |
389 | unsigned base:3; | |
390 | unsigned index:3; | |
391 | unsigned scale:2; | |
392 | } | |
393 | ||
394 | base_index_byte; | |
395 | ||
396 | /* The name of the global offset table generated by the compiler. Allow | |
397 | this to be overridden if need be. */ | |
398 | #ifndef GLOBAL_OFFSET_TABLE_NAME | |
399 | #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" | |
400 | #endif | |
401 | ||
402 | #ifdef BFD_ASSEMBLER | |
f59fb6ca | 403 | void i386_validate_fix PARAMS ((struct fix *)); |
03678945 KR |
404 | #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) |
405 | #endif | |
406 | ||
407 | #endif /* TC_I386 */ | |
408 | ||
409 | #define md_operand(x) | |
fecd2382 | 410 | |
a2a5a4fa KR |
411 | extern const struct relax_type md_relax_table[]; |
412 | #define TC_GENERIC_RELAX_TABLE md_relax_table | |
413 | ||
d7bf6158 ILT |
414 | |
415 | extern int flag_16bit_code; | |
416 | ||
dddc8a82 ILT |
417 | #ifdef BFD_ASSEMBLER |
418 | #define md_maybe_text() \ | |
419 | ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
420 | #else | |
421 | #define md_maybe_text() \ | |
422 | (now_seg != data_section && now_seg != bss_section) | |
423 | #endif | |
424 | ||
d7bf6158 ILT |
425 | #define md_do_align(n, fill, len, max, around) \ |
426 | if ((n) && !need_pass_2 \ | |
427 | && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ | |
dddc8a82 | 428 | && md_maybe_text ()) \ |
d7bf6158 ILT |
429 | { \ |
430 | char *p; \ | |
431 | p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \ | |
f59fb6ca | 432 | (symbolS *) 0, (offsetT) (n), (char *) 0); \ |
d7bf6158 ILT |
433 | *p = 0x90; \ |
434 | goto around; \ | |
435 | } | |
436 | ||
437 | extern void i386_align_code PARAMS ((fragS *, int)); | |
438 | ||
439 | #define HANDLE_ALIGN(fragP) \ | |
440 | if (fragP->fr_type == rs_align_code) \ | |
441 | i386_align_code (fragP, (fragP->fr_next->fr_address \ | |
442 | - fragP->fr_address \ | |
443 | - fragP->fr_fix)); | |
444 | ||
445 | /* call md_apply_fix3 with segment instead of md_apply_fix */ | |
446 | #define MD_APPLY_FIX3 | |
447 | ||
448 | void i386_print_statistics PARAMS ((FILE *)); | |
449 | #define tc_print_statistics i386_print_statistics | |
450 | ||
451 | #define md_number_to_chars number_to_chars_littleendian | |
452 | ||
453 | #ifdef SCO_ELF | |
454 | #define tc_init_after_args() sco_id () | |
455 | extern void sco_id PARAMS ((void)); | |
456 | #endif | |
457 | ||
dddc8a82 ILT |
458 | #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ |
459 | ||
fecd2382 | 460 | /* end of tc-i386.h */ |