Commit | Line | Data |
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542e1629 | 1 | /* tc-i960.c - All the i80960-specific stuff |
5ac34ac3 | 2 | Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc. |
355afbcd | 3 | |
a39116f1 | 4 | This file is part of GAS. |
355afbcd | 5 | |
a39116f1 RP |
6 | GAS is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
355afbcd | 10 | |
a39116f1 RP |
11 | GAS is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
355afbcd | 15 | |
a39116f1 RP |
16 | You should have received a copy of the GNU General Public License |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
fecd2382 | 19 | |
fecd2382 RP |
20 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
21 | ||
22 | /****************************************************************************** | |
23 | * i80690 NOTE!!!: | |
24 | * Header, symbol, and relocation info will be used on the host machine | |
25 | * only -- only executable code is actually downloaded to the i80960. | |
26 | * Therefore, leave all such information in host byte order. | |
27 | * | |
28 | * (That's a slight lie -- we DO download some header information, but | |
29 | * the downloader converts the file format and corrects the byte-ordering | |
30 | * of the relevant fields while doing so.) | |
31 | * | |
8ae35e59 ILT |
32 | * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER |
33 | * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO | |
34 | * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <== | |
35 | * | |
fecd2382 RP |
36 | ***************************************************************************** */ |
37 | ||
38 | /* There are 4 different lengths of (potentially) symbol-based displacements | |
39 | * in the 80960 instruction set, each of which could require address fix-ups | |
40 | * and (in the case of external symbols) emission of relocation directives: | |
41 | * | |
42 | * 32-bit (MEMB) | |
43 | * This is a standard length for the base assembler and requires no | |
44 | * special action. | |
45 | * | |
46 | * 13-bit (COBR) | |
47 | * This is a non-standard length, but the base assembler has a hook for | |
48 | * bit field address fixups: the fixS structure can point to a descriptor | |
49 | * of the field, in which case our md_number_to_field() routine gets called | |
50 | * to process it. | |
51 | * | |
52 | * I made the hook a little cleaner by having fix_new() (in the base | |
53 | * assembler) return a pointer to the fixS in question. And I made it a | |
54 | * little simpler by storing the field size (in this case 13) instead of | |
55 | * of a pointer to another structure: 80960 displacements are ALWAYS | |
56 | * stored in the low-order bits of a 4-byte word. | |
57 | * | |
58 | * Since the target of a COBR cannot be external, no relocation directives | |
59 | * for this size displacement have to be generated. But the base assembler | |
60 | * had to be modified to issue error messages if the symbol did turn out | |
61 | * to be external. | |
62 | * | |
63 | * 24-bit (CTRL) | |
64 | * Fixups are handled as for the 13-bit case (except that 24 is stored | |
65 | * in the fixS). | |
66 | * | |
67 | * The relocation directive generated is the same as that for the 32-bit | |
68 | * displacement, except that it's PC-relative (the 32-bit displacement | |
69 | * never is). The i80960 version of the linker needs a mod to | |
70 | * distinguish and handle the 24-bit case. | |
71 | * | |
72 | * 12-bit (MEMA) | |
73 | * MEMA formats are always promoted to MEMB (32-bit) if the displacement | |
74 | * is based on a symbol, because it could be relocated at link time. | |
75 | * The only time we use the 12-bit format is if an absolute value of | |
76 | * less than 4096 is specified, in which case we need neither a fixup nor | |
77 | * a relocation directive. | |
78 | */ | |
79 | ||
80 | #include <stdio.h> | |
81 | #include <ctype.h> | |
82 | ||
83 | #include "as.h" | |
84 | ||
85 | #include "obstack.h" | |
86 | ||
a39116f1 | 87 | #include "opcode/i960.h" |
fecd2382 | 88 | |
f3d817d8 DM |
89 | extern char *strchr (); |
90 | ||
fecd2382 RP |
91 | extern char *input_line_pointer; |
92 | extern struct hash_control *po_hash; | |
fecd2382 RP |
93 | extern char *next_object_file_charP; |
94 | ||
f3d817d8 | 95 | #if !defined (BFD_ASSEMBLER) && !defined (BFD) |
fecd2382 | 96 | #ifdef OBJ_COFF |
c47d388b | 97 | const int md_reloc_size = sizeof (struct reloc); |
fecd2382 | 98 | #else /* OBJ_COFF */ |
c47d388b | 99 | const int md_reloc_size = sizeof (struct relocation_info); |
fecd2382 | 100 | #endif /* OBJ_COFF */ |
f3d817d8 | 101 | #endif |
fecd2382 | 102 | |
a39116f1 RP |
103 | /*************************** |
104 | * Local i80960 routines * | |
105 | ************************** */ | |
fecd2382 | 106 | |
355afbcd KR |
107 | static void brcnt_emit (); /* Emit branch-prediction instrumentation code */ |
108 | static char *brlab_next (); /* Return next branch local label */ | |
109 | void brtab_emit (); /* Emit br-predict instrumentation table */ | |
110 | static void cobr_fmt (); /* Generate COBR instruction */ | |
111 | static void ctrl_fmt (); /* Generate CTRL instruction */ | |
112 | static char *emit (); /* Emit (internally) binary */ | |
113 | static int get_args (); /* Break arguments out of comma-separated list */ | |
114 | static void get_cdisp (); /* Handle COBR or CTRL displacement */ | |
115 | static char *get_ispec (); /* Find index specification string */ | |
116 | static int get_regnum (); /* Translate text to register number */ | |
117 | static int i_scan (); /* Lexical scan of instruction source */ | |
118 | static void mem_fmt (); /* Generate MEMA or MEMB instruction */ | |
119 | static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */ | |
5ac34ac3 | 120 | static void parse_expr (); /* Parse an expression */ |
355afbcd KR |
121 | static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */ |
122 | static void parse_memop (); /* Parse a memory operand */ | |
123 | static void parse_po (); /* Parse machine-dependent pseudo-op */ | |
124 | static void parse_regop (); /* Parse a register operand */ | |
125 | static void reg_fmt (); /* Generate a REG format instruction */ | |
126 | void reloc_callj (); /* Relocate a 'callj' instruction */ | |
127 | static void relax_cobr (); /* "De-optimize" cobr into compare/branch */ | |
128 | static void s_leafproc (); /* Process '.leafproc' pseudo-op */ | |
129 | static void s_sysproc (); /* Process '.sysproc' pseudo-op */ | |
130 | static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */ | |
131 | static void syntax (); /* Give syntax error */ | |
132 | static int targ_has_sfr (); /* Target chip supports spec-func register? */ | |
133 | static int targ_has_iclass (); /* Target chip supports instruction set? */ | |
134 | /* static void unlink_sym(); *//* Remove a symbol from the symbol list */ | |
fecd2382 RP |
135 | |
136 | /* See md_parse_option() for meanings of these options */ | |
09952cd9 | 137 | static char norelax; /* True if -norelax switch seen */ |
355afbcd | 138 | static char instrument_branches;/* True if -b switch seen */ |
fecd2382 RP |
139 | |
140 | /* Characters that always start a comment. | |
141 | * If the pre-processor is disabled, these aren't very useful. | |
142 | */ | |
355afbcd | 143 | const char comment_chars[] = "#"; |
fecd2382 RP |
144 | |
145 | /* Characters that only start a comment at the beginning of | |
146 | * a line. If the line seems to have the form '# 123 filename' | |
147 | * .line and .file directives will appear in the pre-processed output. | |
148 | * | |
149 | * Note that input_file.c hand checks for '#' at the beginning of the | |
150 | * first line of the input file. This is because the compiler outputs | |
151 | * #NO_APP at the beginning of its output. | |
152 | */ | |
153 | ||
154 | /* Also note that comments started like this one will always work. */ | |
155 | ||
c47d388b | 156 | const char line_comment_chars[1]; |
355afbcd | 157 | |
c47d388b | 158 | const char line_separator_chars[1]; |
fecd2382 RP |
159 | |
160 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
355afbcd | 161 | const char EXP_CHARS[] = "eE"; |
fecd2382 RP |
162 | |
163 | /* Chars that mean this number is a floating point constant, | |
164 | * as in 0f12.456 or 0d1.2345e12 | |
165 | */ | |
355afbcd | 166 | const char FLT_CHARS[] = "fFdDtT"; |
fecd2382 RP |
167 | |
168 | ||
169 | /* Table used by base assembler to relax addresses based on varying length | |
170 | * instructions. The fields are: | |
171 | * 1) most positive reach of this state, | |
172 | * 2) most negative reach of this state, | |
173 | * 3) how many bytes this mode will add to the size of the current frag | |
174 | * 4) which index into the table to try if we can't fit into this one. | |
175 | * | |
176 | * For i80960, the only application is the (de-)optimization of cobr | |
177 | * instructions into separate compare and branch instructions when a 13-bit | |
178 | * displacement won't hack it. | |
179 | */ | |
180 | const relax_typeS | |
355afbcd KR |
181 | md_relax_table[] = |
182 | { | |
183 | {0, 0, 0, 0}, /* State 0 => no more relaxation possible */ | |
184 | {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */ | |
185 | {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */ | |
186 | }; | |
fecd2382 RP |
187 | |
188 | ||
189 | /* These are the machine dependent pseudo-ops. | |
190 | * | |
191 | * This table describes all the machine specific pseudo-ops the assembler | |
192 | * has to support. The fields are: | |
193 | * pseudo-op name without dot | |
194 | * function to call to execute this pseudo-op | |
195 | * integer arg to pass to the function | |
196 | */ | |
197 | #define S_LEAFPROC 1 | |
198 | #define S_SYSPROC 2 | |
199 | ||
355afbcd KR |
200 | const pseudo_typeS md_pseudo_table[] = |
201 | { | |
202 | {"bss", s_lcomm, 1}, | |
203 | {"extended", float_cons, 't'}, | |
204 | {"leafproc", parse_po, S_LEAFPROC}, | |
205 | {"sysproc", parse_po, S_SYSPROC}, | |
09952cd9 | 206 | |
355afbcd | 207 | {"word", cons, 4}, |
80aab579 | 208 | {"quad", cons, 16}, |
09952cd9 | 209 | |
355afbcd | 210 | {0, 0, 0} |
09952cd9 | 211 | }; |
fecd2382 RP |
212 | \f |
213 | /* Macros to extract info from an 'expressionS' structure 'e' */ | |
214 | #define adds(e) e.X_add_symbol | |
fecd2382 | 215 | #define offs(e) e.X_add_number |
355afbcd KR |
216 | |
217 | ||
218 | /* Branch-prediction bits for CTRL/COBR format opcodes */ | |
219 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */ | |
220 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */ | |
221 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */ | |
222 | ||
223 | ||
224 | /* Some instruction opcodes that we need explicitly */ | |
fecd2382 RP |
225 | #define BE 0x12000000 |
226 | #define BG 0x11000000 | |
227 | #define BGE 0x13000000 | |
228 | #define BL 0x14000000 | |
229 | #define BLE 0x16000000 | |
230 | #define BNE 0x15000000 | |
231 | #define BNO 0x10000000 | |
232 | #define BO 0x17000000 | |
233 | #define CHKBIT 0x5a002700 | |
234 | #define CMPI 0x5a002080 | |
235 | #define CMPO 0x5a002000 | |
355afbcd | 236 | |
fecd2382 RP |
237 | #define B 0x08000000 |
238 | #define BAL 0x0b000000 | |
239 | #define CALL 0x09000000 | |
240 | #define CALLS 0x66003800 | |
241 | #define RET 0x0a000000 | |
355afbcd KR |
242 | |
243 | ||
244 | /* These masks are used to build up a set of MEMB mode bits. */ | |
fecd2382 RP |
245 | #define A_BIT 0x0400 |
246 | #define I_BIT 0x0800 | |
247 | #define MEMB_BIT 0x1000 | |
248 | #define D_BIT 0x2000 | |
355afbcd KR |
249 | |
250 | ||
c47d388b ME |
251 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is |
252 | used). */ | |
fecd2382 | 253 | #define MEMA_ABASE 0x2000 |
355afbcd KR |
254 | |
255 | /* Info from which a MEMA or MEMB format instruction can be generated */ | |
256 | typedef struct | |
257 | { | |
c47d388b ME |
258 | /* (First) 32 bits of instruction */ |
259 | long opcode; | |
260 | /* 0-(none), 12- or, 32-bit displacement needed */ | |
261 | int disp; | |
262 | /* The expression in the source instruction from which the | |
263 | displacement should be determined. */ | |
264 | char *e; | |
355afbcd KR |
265 | } |
266 | ||
267 | memS; | |
fecd2382 RP |
268 | |
269 | ||
270 | /* The two pieces of info we need to generate a register operand */ | |
355afbcd KR |
271 | struct regop |
272 | { | |
273 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */ | |
274 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */ | |
275 | int n; /* Register number or literal value */ | |
276 | }; | |
fecd2382 RP |
277 | |
278 | ||
279 | /* Number and assembler mnemonic for all registers that can appear in operands */ | |
355afbcd KR |
280 | static struct |
281 | { | |
282 | char *reg_name; | |
283 | int reg_num; | |
284 | } | |
285 | ||
286 | regnames[] = | |
287 | { | |
288 | { "pfp", 0 }, | |
289 | { "sp", 1 }, | |
290 | { "rip", 2 }, | |
291 | { "r3", 3 }, | |
292 | { "r4", 4 }, | |
293 | { "r5", 5 }, | |
294 | { "r6", 6 }, | |
295 | { "r7", 7 }, | |
296 | { "r8", 8 }, | |
297 | { "r9", 9 }, | |
298 | { "r10", 10 }, | |
299 | { "r11", 11 }, | |
300 | { "r12", 12 }, | |
301 | { "r13", 13 }, | |
302 | { "r14", 14 }, | |
303 | { "r15", 15 }, | |
304 | { "g0", 16 }, | |
305 | { "g1", 17 }, | |
306 | { "g2", 18 }, | |
307 | { "g3", 19 }, | |
308 | { "g4", 20 }, | |
309 | { "g5", 21 }, | |
310 | { "g6", 22 }, | |
311 | { "g7", 23 }, | |
312 | { "g8", 24 }, | |
313 | { "g9", 25 }, | |
314 | { "g10", 26 }, | |
315 | { "g11", 27 }, | |
316 | { "g12", 28 }, | |
317 | { "g13", 29 }, | |
318 | { "g14", 30 }, | |
319 | { "fp", 31 }, | |
320 | ||
321 | /* Numbers for special-function registers are for assembler internal | |
322 | use only: they are scaled back to range [0-31] for binary output. */ | |
323 | #define SF0 32 | |
324 | ||
325 | { "sf0", 32 }, | |
326 | { "sf1", 33 }, | |
327 | { "sf2", 34 }, | |
328 | { "sf3", 35 }, | |
329 | { "sf4", 36 }, | |
330 | { "sf5", 37 }, | |
331 | { "sf6", 38 }, | |
332 | { "sf7", 39 }, | |
333 | { "sf8", 40 }, | |
334 | { "sf9", 41 }, | |
335 | { "sf10", 42 }, | |
336 | { "sf11", 43 }, | |
337 | { "sf12", 44 }, | |
338 | { "sf13", 45 }, | |
339 | { "sf14", 46 }, | |
340 | { "sf15", 47 }, | |
341 | { "sf16", 48 }, | |
342 | { "sf17", 49 }, | |
343 | { "sf18", 50 }, | |
344 | { "sf19", 51 }, | |
345 | { "sf20", 52 }, | |
346 | { "sf21", 53 }, | |
347 | { "sf22", 54 }, | |
348 | { "sf23", 55 }, | |
349 | { "sf24", 56 }, | |
350 | { "sf25", 57 }, | |
351 | { "sf26", 58 }, | |
352 | { "sf27", 59 }, | |
353 | { "sf28", 60 }, | |
354 | { "sf29", 61 }, | |
355 | { "sf30", 62 }, | |
356 | { "sf31", 63 }, | |
357 | ||
358 | /* Numbers for floating point registers are for assembler internal use | |
fecd2382 RP |
359 | * only: they are scaled back to [0-3] for binary output. |
360 | */ | |
355afbcd KR |
361 | #define FP0 64 |
362 | ||
363 | { "fp0", 64 }, | |
364 | { "fp1", 65 }, | |
365 | { "fp2", 66 }, | |
366 | { "fp3", 67 }, | |
367 | ||
368 | { NULL, 0 }, /* END OF LIST */ | |
fecd2382 RP |
369 | }; |
370 | ||
371 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) | |
372 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) | |
373 | #define IS_FP_REG(n) ((n) >= FP0) | |
374 | ||
375 | /* Number and assembler mnemonic for all registers that can appear as 'abase' | |
376 | * (indirect addressing) registers. | |
377 | */ | |
355afbcd KR |
378 | static struct |
379 | { | |
380 | char *areg_name; | |
381 | int areg_num; | |
382 | } | |
383 | ||
384 | aregs[] = | |
385 | { | |
386 | { "(pfp)", 0 }, | |
387 | { "(sp)", 1 }, | |
388 | { "(rip)", 2 }, | |
389 | { "(r3)", 3 }, | |
390 | { "(r4)", 4 }, | |
391 | { "(r5)", 5 }, | |
392 | { "(r6)", 6 }, | |
393 | { "(r7)", 7 }, | |
394 | { "(r8)", 8 }, | |
395 | { "(r9)", 9 }, | |
396 | { "(r10)", 10 }, | |
397 | { "(r11)", 11 }, | |
398 | { "(r12)", 12 }, | |
399 | { "(r13)", 13 }, | |
400 | { "(r14)", 14 }, | |
401 | { "(r15)", 15 }, | |
402 | { "(g0)", 16 }, | |
403 | { "(g1)", 17 }, | |
404 | { "(g2)", 18 }, | |
405 | { "(g3)", 19 }, | |
406 | { "(g4)", 20 }, | |
407 | { "(g5)", 21 }, | |
408 | { "(g6)", 22 }, | |
409 | { "(g7)", 23 }, | |
410 | { "(g8)", 24 }, | |
411 | { "(g9)", 25 }, | |
412 | { "(g10)", 26 }, | |
413 | { "(g11)", 27 }, | |
414 | { "(g12)", 28 }, | |
415 | { "(g13)", 29 }, | |
416 | { "(g14)", 30 }, | |
417 | { "(fp)", 31 }, | |
418 | ||
419 | #define IPREL 32 | |
420 | /* For assembler internal use only: this number never appears in binary | |
421 | output. */ | |
422 | { "(ip)", IPREL }, | |
423 | ||
424 | { NULL, 0 }, /* END OF LIST */ | |
fecd2382 RP |
425 | }; |
426 | ||
427 | ||
428 | /* Hash tables */ | |
c47d388b ME |
429 | static struct hash_control *op_hash; /* Opcode mnemonics */ |
430 | static struct hash_control *reg_hash; /* Register name hash table */ | |
431 | static struct hash_control *areg_hash; /* Abase register hash table */ | |
fecd2382 RP |
432 | |
433 | ||
434 | /* Architecture for which we are assembling */ | |
435 | #define ARCH_ANY 0 /* Default: no architecture checking done */ | |
436 | #define ARCH_KA 1 | |
437 | #define ARCH_KB 2 | |
438 | #define ARCH_MC 3 | |
439 | #define ARCH_CA 4 | |
440 | int architecture = ARCH_ANY; /* Architecture requested on invocation line */ | |
c47d388b | 441 | int iclasses_seen; /* OR of instruction classes (I_* constants) |
fecd2382 RP |
442 | * for which we've actually assembled |
443 | * instructions. | |
444 | */ | |
445 | ||
446 | ||
447 | /* BRANCH-PREDICTION INSTRUMENTATION | |
448 | * | |
449 | * The following supports generation of branch-prediction instrumentation | |
450 | * (turned on by -b switch). The instrumentation collects counts | |
451 | * of branches taken/not-taken for later input to a utility that will | |
452 | * set the branch prediction bits of the instructions in accordance with | |
453 | * the behavior observed. (Note that the KX series does not have | |
454 | * brach-prediction.) | |
455 | * | |
456 | * The instrumentation consists of: | |
457 | * | |
458 | * (1) before and after each conditional branch, a call to an external | |
459 | * routine that increments and steps over an inline counter. The | |
460 | * counter itself, initialized to 0, immediately follows the call | |
461 | * instruction. For each branch, the counter following the branch | |
462 | * is the number of times the branch was not taken, and the difference | |
463 | * between the counters is the number of times it was taken. An | |
464 | * example of an instrumented conditional branch: | |
465 | * | |
466 | * call BR_CNT_FUNC | |
467 | * .word 0 | |
468 | * LBRANCH23: be label | |
469 | * call BR_CNT_FUNC | |
470 | * .word 0 | |
471 | * | |
472 | * (2) a table of pointers to the instrumented branches, so that an | |
473 | * external postprocessing routine can locate all of the counters. | |
474 | * the table begins with a 2-word header: a pointer to the next in | |
475 | * a linked list of such tables (initialized to 0); and a count | |
476 | * of the number of entries in the table (exclusive of the header. | |
477 | * | |
478 | * Note that input source code is expected to already contain calls | |
479 | * an external routine that will link the branch local table into a | |
480 | * list of such tables. | |
481 | */ | |
482 | ||
c47d388b | 483 | static int br_cnt; /* Number of branches instrumented so far. |
fecd2382 RP |
484 | * Also used to generate unique local labels |
485 | * for each instrumented branch | |
486 | */ | |
487 | ||
488 | #define BR_LABEL_BASE "LBRANCH" | |
a39116f1 RP |
489 | /* Basename of local labels on instrumented |
490 | * branches, to avoid conflict with compiler- | |
491 | * generated local labels. | |
492 | */ | |
fecd2382 RP |
493 | |
494 | #define BR_CNT_FUNC "__inc_branch" | |
a39116f1 RP |
495 | /* Name of the external routine that will |
496 | * increment (and step over) an inline counter. | |
497 | */ | |
fecd2382 RP |
498 | |
499 | #define BR_TAB_NAME "__BRANCH_TABLE__" | |
a39116f1 RP |
500 | /* Name of the table of pointers to branches. |
501 | * A local (i.e., non-external) symbol. | |
502 | */ | |
fecd2382 RP |
503 | \f |
504 | /***************************************************************************** | |
505 | * md_begin: One-time initialization. | |
506 | * | |
507 | * Set up hash tables. | |
508 | * | |
509 | **************************************************************************** */ | |
510 | void | |
355afbcd | 511 | md_begin () |
fecd2382 | 512 | { |
355afbcd KR |
513 | int i; /* Loop counter */ |
514 | const struct i960_opcode *oP; /* Pointer into opcode table */ | |
80aab579 | 515 | const char *retval; /* Value returned by hash functions */ |
355afbcd | 516 | |
f3d817d8 DM |
517 | op_hash = hash_new (); |
518 | reg_hash = hash_new (); | |
519 | areg_hash = hash_new (); | |
355afbcd | 520 | |
c47d388b ME |
521 | /* For some reason, the base assembler uses an empty string for "no |
522 | error message", instead of a NULL pointer. */ | |
f3d817d8 | 523 | retval = 0; |
355afbcd | 524 | |
80aab579 ILT |
525 | for (oP = i960_opcodes; oP->name && !retval; oP++) |
526 | retval = hash_insert (op_hash, oP->name, (PTR) oP); | |
355afbcd | 527 | |
80aab579 ILT |
528 | for (i = 0; regnames[i].reg_name && !retval; i++) |
529 | retval = hash_insert (reg_hash, regnames[i].reg_name, | |
530 | ®names[i].reg_num); | |
355afbcd | 531 | |
80aab579 ILT |
532 | for (i = 0; aregs[i].areg_name && !retval; i++) |
533 | retval = hash_insert (areg_hash, aregs[i].areg_name, | |
534 | &aregs[i].areg_num); | |
355afbcd | 535 | |
80aab579 ILT |
536 | if (retval) |
537 | as_fatal ("Hashing returned \"%s\".", retval); | |
538 | } | |
fecd2382 | 539 | |
fecd2382 RP |
540 | /***************************************************************************** |
541 | * md_assemble: Assemble an instruction | |
542 | * | |
543 | * Assumptions about the passed-in text: | |
544 | * - all comments, labels removed | |
545 | * - text is an instruction | |
546 | * - all white space compressed to single blanks | |
547 | * - all character constants have been replaced with decimal | |
548 | * | |
549 | **************************************************************************** */ | |
550 | void | |
355afbcd KR |
551 | md_assemble (textP) |
552 | char *textP; /* Source text of instruction */ | |
fecd2382 | 553 | { |
c47d388b ME |
554 | /* Parsed instruction text, containing NO whitespace: |
555 | * arg[0]->opcode mnemonic | |
556 | * arg[1-3]->operands, with char constants | |
557 | * replaced by decimal numbers | |
558 | */ | |
559 | char *args[4]; | |
560 | ||
355afbcd | 561 | int n_ops; /* Number of instruction operands */ |
355afbcd | 562 | /* Pointer to instruction description */ |
c47d388b | 563 | struct i960_opcode *oP; |
355afbcd | 564 | /* TRUE iff opcode mnemonic included branch-prediction |
c47d388b ME |
565 | * suffix (".f" or ".t") |
566 | */ | |
567 | int branch_predict; | |
568 | /* Setting of branch-prediction bit(s) to be OR'd | |
569 | * into instruction opcode of CTRL/COBR format | |
570 | * instructions. | |
571 | */ | |
572 | long bp_bits; | |
573 | ||
355afbcd KR |
574 | int n; /* Offset of last character in opcode mnemonic */ |
575 | ||
576 | static const char bp_error_msg[] = "branch prediction invalid on this opcode"; | |
577 | ||
578 | ||
579 | /* Parse instruction into opcode and operands */ | |
580 | memset (args, '\0', sizeof (args)); | |
581 | n_ops = i_scan (textP, args); | |
582 | if (n_ops == -1) | |
583 | { | |
584 | return; /* Error message already issued */ | |
585 | } | |
586 | ||
587 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */ | |
588 | if (!strcmp (args[0], "ldconst")) | |
589 | { | |
590 | n_ops = parse_ldconst (args); | |
591 | if (n_ops == -1) | |
592 | { | |
593 | return; | |
fecd2382 | 594 | } |
355afbcd | 595 | } |
09952cd9 KR |
596 | |
597 | ||
355afbcd KR |
598 | |
599 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off */ | |
600 | n = strlen (args[0]) - 1; | |
601 | branch_predict = 0; | |
602 | bp_bits = 0; | |
603 | if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')) | |
604 | { | |
605 | /* We could check here to see if the target architecture | |
c47d388b ME |
606 | * supports branch prediction, but why bother? The bit |
607 | * will just be ignored by processors that don't use it. | |
608 | */ | |
355afbcd KR |
609 | branch_predict = 1; |
610 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; | |
611 | args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */ | |
612 | } | |
613 | ||
614 | /* Look up opcode mnemonic in table and check number of operands. | |
c47d388b ME |
615 | * Check that opcode is legal for the target architecture. |
616 | * If all looks good, assemble instruction. | |
617 | */ | |
355afbcd KR |
618 | oP = (struct i960_opcode *) hash_find (op_hash, args[0]); |
619 | if (!oP || !targ_has_iclass (oP->iclass)) | |
620 | { | |
621 | as_bad ("invalid opcode, \"%s\".", args[0]); | |
622 | ||
623 | } | |
624 | else if (n_ops != oP->num_ops) | |
625 | { | |
c47d388b ME |
626 | as_bad ("improper number of operands. expecting %d, got %d", |
627 | oP->num_ops, n_ops); | |
355afbcd KR |
628 | } |
629 | else | |
630 | { | |
631 | switch (oP->format) | |
632 | { | |
633 | case FBRA: | |
634 | case CTRL: | |
635 | ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops); | |
636 | if (oP->format == FBRA) | |
637 | { | |
638 | /* Now generate a 'bno' to same arg */ | |
639 | ctrl_fmt (args[1], BNO | bp_bits, 1); | |
640 | } | |
641 | break; | |
642 | case COBR: | |
643 | case COJ: | |
644 | cobr_fmt (args, oP->opcode | bp_bits, oP); | |
645 | break; | |
646 | case REG: | |
647 | if (branch_predict) | |
648 | { | |
649 | as_warn (bp_error_msg); | |
650 | } | |
651 | reg_fmt (args, oP); | |
652 | break; | |
653 | case MEM1: | |
654 | if (args[0][0] == 'c' && args[0][1] == 'a') | |
655 | { | |
656 | if (branch_predict) | |
657 | { | |
658 | as_warn (bp_error_msg); | |
659 | } | |
660 | mem_fmt (args, oP, 1); | |
661 | break; | |
662 | } | |
663 | case MEM2: | |
664 | case MEM4: | |
665 | case MEM8: | |
666 | case MEM12: | |
667 | case MEM16: | |
668 | if (branch_predict) | |
669 | { | |
670 | as_warn (bp_error_msg); | |
671 | } | |
672 | mem_fmt (args, oP, 0); | |
673 | break; | |
674 | case CALLJ: | |
675 | if (branch_predict) | |
676 | { | |
677 | as_warn (bp_error_msg); | |
678 | } | |
f3d817d8 DM |
679 | /* Output opcode & set up "fixup" (relocation); flag |
680 | relocation as 'callj' type. */ | |
355afbcd KR |
681 | know (oP->num_ops == 1); |
682 | get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1); | |
683 | break; | |
684 | default: | |
685 | BAD_CASE (oP->format); | |
686 | break; | |
fecd2382 | 687 | } |
355afbcd KR |
688 | } |
689 | } /* md_assemble() */ | |
fecd2382 RP |
690 | |
691 | /***************************************************************************** | |
692 | * md_number_to_chars: convert a number to target byte order | |
693 | * | |
694 | **************************************************************************** */ | |
695 | void | |
355afbcd | 696 | md_number_to_chars (buf, value, n) |
f3d817d8 DM |
697 | char *buf; |
698 | valueT value; | |
699 | int n; | |
fecd2382 | 700 | { |
f3d817d8 DM |
701 | number_to_chars_littleendian (buf, value, n); |
702 | } | |
fecd2382 RP |
703 | |
704 | /***************************************************************************** | |
705 | * md_chars_to_number: convert from target byte order to host byte order. | |
706 | * | |
707 | **************************************************************************** */ | |
708 | int | |
355afbcd KR |
709 | md_chars_to_number (val, n) |
710 | unsigned char *val; /* Value in target byte order */ | |
711 | int n; /* Number of bytes in the input */ | |
fecd2382 | 712 | { |
355afbcd KR |
713 | int retval; |
714 | ||
715 | for (retval = 0; n--;) | |
716 | { | |
717 | retval <<= 8; | |
718 | retval |= val[n]; | |
719 | } | |
720 | return retval; | |
fecd2382 RP |
721 | } |
722 | ||
723 | ||
724 | #define MAX_LITTLENUMS 6 | |
725 | #define LNUM_SIZE sizeof(LITTLENUM_TYPE) | |
726 | ||
727 | /***************************************************************************** | |
728 | * md_atof: convert ascii to floating point | |
729 | * | |
730 | * Turn a string at input_line_pointer into a floating point constant of type | |
731 | * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS | |
732 | * emitted is returned at 'sizeP'. An error message is returned, or a pointer | |
733 | * to an empty message if OK. | |
734 | * | |
735 | * Note we call the i386 floating point routine, rather than complicating | |
736 | * things with more files or symbolic links. | |
737 | * | |
738 | **************************************************************************** */ | |
355afbcd KR |
739 | char * |
740 | md_atof (type, litP, sizeP) | |
741 | int type; | |
742 | char *litP; | |
743 | int *sizeP; | |
fecd2382 | 744 | { |
355afbcd KR |
745 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
746 | LITTLENUM_TYPE *wordP; | |
747 | int prec; | |
748 | char *t; | |
749 | char *atof_ieee (); | |
750 | ||
751 | switch (type) | |
752 | { | |
753 | case 'f': | |
754 | case 'F': | |
755 | prec = 2; | |
756 | break; | |
757 | ||
758 | case 'd': | |
759 | case 'D': | |
760 | prec = 4; | |
761 | break; | |
762 | ||
763 | case 't': | |
764 | case 'T': | |
765 | prec = 5; | |
766 | type = 'x'; /* That's what atof_ieee() understands */ | |
767 | break; | |
768 | ||
769 | default: | |
770 | *sizeP = 0; | |
771 | return "Bad call to md_atof()"; | |
772 | } | |
773 | ||
774 | t = atof_ieee (input_line_pointer, type, words); | |
775 | if (t) | |
776 | { | |
777 | input_line_pointer = t; | |
778 | } | |
779 | ||
780 | *sizeP = prec * LNUM_SIZE; | |
781 | ||
782 | /* Output the LITTLENUMs in REVERSE order in accord with i80960 | |
f3d817d8 DM |
783 | word-order. (Dunno why atof_ieee doesn't do it in the right |
784 | order in the first place -- probably because it's a hack of | |
785 | atof_m68k.) */ | |
355afbcd KR |
786 | |
787 | for (wordP = words + prec - 1; prec--;) | |
788 | { | |
789 | md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE); | |
790 | litP += sizeof (LITTLENUM_TYPE); | |
791 | } | |
792 | ||
f3d817d8 | 793 | return 0; |
fecd2382 RP |
794 | } |
795 | ||
796 | ||
797 | /***************************************************************************** | |
798 | * md_number_to_imm | |
799 | * | |
800 | **************************************************************************** */ | |
801 | void | |
355afbcd KR |
802 | md_number_to_imm (buf, val, n) |
803 | char *buf; | |
804 | long val; | |
805 | int n; | |
fecd2382 | 806 | { |
355afbcd | 807 | md_number_to_chars (buf, val, n); |
fecd2382 RP |
808 | } |
809 | ||
810 | ||
811 | /***************************************************************************** | |
812 | * md_number_to_disp | |
813 | * | |
814 | **************************************************************************** */ | |
815 | void | |
355afbcd KR |
816 | md_number_to_disp (buf, val, n) |
817 | char *buf; | |
818 | long val; | |
819 | int n; | |
fecd2382 | 820 | { |
355afbcd | 821 | md_number_to_chars (buf, val, n); |
fecd2382 RP |
822 | } |
823 | ||
824 | /***************************************************************************** | |
825 | * md_number_to_field: | |
826 | * | |
827 | * Stick a value (an address fixup) into a bit field of | |
828 | * previously-generated instruction. | |
829 | * | |
830 | **************************************************************************** */ | |
831 | void | |
355afbcd KR |
832 | md_number_to_field (instrP, val, bfixP) |
833 | char *instrP; /* Pointer to instruction to be fixed */ | |
834 | long val; /* Address fixup value */ | |
835 | bit_fixS *bfixP; /* Description of bit field to be fixed up */ | |
fecd2382 | 836 | { |
355afbcd KR |
837 | int numbits; /* Length of bit field to be fixed */ |
838 | long instr; /* 32-bit instruction to be fixed-up */ | |
839 | long sign; /* 0 or -1, according to sign bit of 'val' */ | |
840 | ||
841 | /* Convert instruction back to host byte order | |
fecd2382 | 842 | */ |
355afbcd KR |
843 | instr = md_chars_to_number (instrP, 4); |
844 | ||
845 | /* Surprise! -- we stored the number of bits | |
fecd2382 RP |
846 | * to be modified rather than a pointer to a structure. |
847 | */ | |
355afbcd KR |
848 | numbits = (int) bfixP; |
849 | if (numbits == 1) | |
850 | { | |
851 | /* This is a no-op, stuck here by reloc_callj() */ | |
852 | return; | |
853 | } | |
854 | ||
855 | know ((numbits == 13) || (numbits == 24)); | |
856 | ||
857 | /* Propagate sign bit of 'val' for the given number of bits. | |
fecd2382 RP |
858 | * Result should be all 0 or all 1 |
859 | */ | |
355afbcd KR |
860 | sign = val >> ((int) numbits - 1); |
861 | if (((val < 0) && (sign != -1)) | |
862 | || ((val > 0) && (sign != 0))) | |
863 | { | |
80aab579 | 864 | as_bad ("Fixup of %ld too large for field width of %d", |
355afbcd KR |
865 | val, numbits); |
866 | } | |
867 | else | |
868 | { | |
869 | /* Put bit field into instruction and write back in target | |
fecd2382 RP |
870 | * byte order. |
871 | */ | |
355afbcd KR |
872 | val &= ~(-1 << (int) numbits); /* Clear unused sign bits */ |
873 | instr |= val; | |
874 | md_number_to_chars (instrP, instr, 4); | |
875 | } | |
876 | } /* md_number_to_field() */ | |
fecd2382 | 877 | |
f3d817d8 | 878 | \f |
fecd2382 RP |
879 | /***************************************************************************** |
880 | * md_parse_option | |
881 | * Invocation line includes a switch not recognized by the base assembler. | |
882 | * See if it's a processor-specific option. For the 960, these are: | |
883 | * | |
884 | * -norelax: | |
885 | * Conditional branch instructions that require displacements | |
886 | * greater than 13 bits (or that have external targets) should | |
887 | * generate errors. The default is to replace each such | |
888 | * instruction with the corresponding compare (or chkbit) and | |
889 | * branch instructions. Note that the Intel "j" cobr directives | |
890 | * are ALWAYS "de-optimized" in this way when necessary, | |
891 | * regardless of the setting of this option. | |
892 | * | |
893 | * -b: | |
894 | * Add code to collect information about branches taken, for | |
895 | * later optimization of branch prediction bits by a separate | |
896 | * tool. COBR and CNTL format instructions have branch | |
897 | * prediction bits (in the CX architecture); if "BR" represents | |
898 | * an instruction in one of these classes, the following rep- | |
899 | * resents the code generated by the assembler: | |
900 | * | |
901 | * call <increment routine> | |
902 | * .word 0 # pre-counter | |
903 | * Label: BR | |
904 | * call <increment routine> | |
905 | * .word 0 # post-counter | |
906 | * | |
907 | * A table of all such "Labels" is also generated. | |
908 | * | |
909 | * | |
910 | * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: | |
911 | * Select the 80960 architecture. Instructions or features not | |
912 | * supported by the selected architecture cause fatal errors. | |
913 | * The default is to generate code for any instruction or feature | |
914 | * that is supported by SOME version of the 960 (even if this | |
915 | * means mixing architectures!). | |
916 | * | |
f3d817d8 DM |
917 | *****************************************************************************/ |
918 | ||
919 | CONST char *md_shortopts = "A:b"; | |
920 | struct option md_longopts[] = { | |
921 | #define OPTION_LINKRELAX (OPTION_MD_BASE) | |
922 | {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, | |
923 | #define OPTION_NORELAX (OPTION_MD_BASE + 1) | |
924 | {"norelax", no_argument, NULL, OPTION_NORELAX}, | |
925 | {NULL, no_argument, NULL, 0} | |
926 | }; | |
927 | size_t md_longopts_size = sizeof(md_longopts); | |
928 | ||
fecd2382 | 929 | int |
f3d817d8 DM |
930 | md_parse_option (c, arg) |
931 | int c; | |
932 | char *arg; | |
fecd2382 | 933 | { |
355afbcd KR |
934 | struct tabentry |
935 | { | |
936 | char *flag; | |
937 | int arch; | |
938 | }; | |
939 | static struct tabentry arch_tab[] = | |
940 | { | |
80aab579 ILT |
941 | { "KA", ARCH_KA }, |
942 | { "KB", ARCH_KB }, | |
943 | { "SA", ARCH_KA }, /* Synonym for KA */ | |
944 | { "SB", ARCH_KB }, /* Synonym for KB */ | |
945 | { "KC", ARCH_MC }, /* Synonym for MC */ | |
946 | { "MC", ARCH_MC }, | |
947 | { "CA", ARCH_CA }, | |
948 | { NULL, 0 } | |
355afbcd | 949 | }; |
f3d817d8 DM |
950 | |
951 | switch (c) | |
355afbcd | 952 | { |
f3d817d8 | 953 | case OPTION_LINKRELAX: |
355afbcd KR |
954 | linkrelax = 1; |
955 | flagseen['L'] = 1; | |
f3d817d8 DM |
956 | break; |
957 | ||
958 | case OPTION_NORELAX: | |
355afbcd | 959 | norelax = 1; |
f3d817d8 | 960 | break; |
355afbcd | 961 | |
f3d817d8 | 962 | case 'b': |
355afbcd | 963 | instrument_branches = 1; |
f3d817d8 | 964 | break; |
355afbcd | 965 | |
f3d817d8 DM |
966 | case 'A': |
967 | { | |
968 | struct tabentry *tp; | |
969 | char *p = arg; | |
970 | ||
971 | for (tp = arch_tab; tp->flag != NULL; tp++) | |
972 | { | |
973 | if (!strcmp (p, tp->flag)) | |
974 | { | |
975 | break; | |
976 | } | |
977 | } | |
978 | ||
979 | if (tp->flag == NULL) | |
980 | { | |
981 | as_bad ("invalid architecture %s", p); | |
982 | return 0; | |
983 | } | |
984 | else | |
985 | { | |
986 | architecture = tp->arch; | |
987 | } | |
988 | } | |
989 | break; | |
355afbcd | 990 | |
f3d817d8 | 991 | default: |
355afbcd KR |
992 | return 0; |
993 | } | |
f3d817d8 | 994 | |
355afbcd | 995 | return 1; |
fecd2382 RP |
996 | } |
997 | ||
f3d817d8 DM |
998 | void |
999 | md_show_usage (stream) | |
1000 | FILE *stream; | |
1001 | { | |
1002 | fprintf(stream, "\ | |
1003 | I960 options:\n\ | |
1004 | -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC\n\ | |
1005 | specify variant of 960 architecture\n\ | |
1006 | -b add code to collect statistics about branches taken\n\ | |
1007 | -linkrelax make relocatable instructions undefined (?)\n\ | |
1008 | -norelax don't alter compare-and-branch instructions for\n\ | |
1009 | long displacements\n"); | |
1010 | } | |
1011 | \f | |
1012 | ||
fecd2382 RP |
1013 | /***************************************************************************** |
1014 | * md_convert_frag: | |
1015 | * Called by base assembler after address relaxation is finished: modify | |
1016 | * variable fragments according to how much relaxation was done. | |
1017 | * | |
1018 | * If the fragment substate is still 1, a 13-bit displacement was enough | |
1019 | * to reach the symbol in question. Set up an address fixup, but otherwise | |
1020 | * leave the cobr instruction alone. | |
1021 | * | |
1022 | * If the fragment substate is 2, a 13-bit displacement was not enough. | |
1023 | * Replace the cobr with a two instructions (a compare and a branch). | |
1024 | * | |
1025 | **************************************************************************** */ | |
1026 | void | |
355afbcd KR |
1027 | md_convert_frag (headers, fragP) |
1028 | object_headers *headers; | |
1029 | fragS *fragP; | |
fecd2382 | 1030 | { |
355afbcd KR |
1031 | fixS *fixP; /* Structure describing needed address fix */ |
1032 | ||
1033 | switch (fragP->fr_subtype) | |
1034 | { | |
1035 | case 1: | |
1036 | /* LEAVE SINGLE COBR INSTRUCTION */ | |
1037 | fixP = fix_new (fragP, | |
1038 | fragP->fr_opcode - fragP->fr_literal, | |
1039 | 4, | |
1040 | fragP->fr_symbol, | |
355afbcd KR |
1041 | fragP->fr_offset, |
1042 | 1, | |
1043 | NO_RELOC); | |
1044 | ||
1045 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */ | |
1046 | break; | |
1047 | case 2: | |
1048 | /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */ | |
1049 | relax_cobr (fragP); | |
1050 | break; | |
1051 | default: | |
1052 | BAD_CASE (fragP->fr_subtype); | |
1053 | break; | |
1054 | } | |
fecd2382 RP |
1055 | } |
1056 | ||
1057 | /***************************************************************************** | |
1058 | * md_estimate_size_before_relax: How much does it look like *fragP will grow? | |
1059 | * | |
1060 | * Called by base assembler just before address relaxation. | |
1061 | * Return the amount by which the fragment will grow. | |
1062 | * | |
1063 | * Any symbol that is now undefined will not become defined; cobr's | |
1064 | * based on undefined symbols will have to be replaced with a compare | |
1065 | * instruction and a branch instruction, and the code fragment will grow | |
1066 | * by 4 bytes. | |
1067 | * | |
1068 | **************************************************************************** */ | |
1069 | int | |
355afbcd KR |
1070 | md_estimate_size_before_relax (fragP, segment_type) |
1071 | register fragS *fragP; | |
1072 | register segT segment_type; | |
fecd2382 | 1073 | { |
355afbcd | 1074 | /* If symbol is undefined in this segment, go to "relaxed" state |
fecd2382 RP |
1075 | * (compare and branch instructions instead of cobr) right now. |
1076 | */ | |
355afbcd KR |
1077 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type) |
1078 | { | |
1079 | relax_cobr (fragP); | |
1080 | return 4; | |
1081 | } | |
1082 | return 0; | |
1083 | } /* md_estimate_size_before_relax() */ | |
fecd2382 RP |
1084 | |
1085 | ||
1086 | /***************************************************************************** | |
1087 | * md_ri_to_chars: | |
1088 | * This routine exists in order to overcome machine byte-order problems | |
1089 | * when dealing with bit-field entries in the relocation_info struct. | |
1090 | * | |
1091 | * But relocation info will be used on the host machine only (only | |
1092 | * executable code is actually downloaded to the i80960). Therefore, | |
1093 | * we leave it in host byte order. | |
1094 | * | |
8ae35e59 ILT |
1095 | * The above comment is no longer true. This routine now really |
1096 | * does do the reordering (Ian Taylor 28 Aug 92). | |
1097 | * | |
fecd2382 | 1098 | **************************************************************************** */ |
355afbcd KR |
1099 | void |
1100 | md_ri_to_chars (where, ri) | |
1101 | char *where; | |
1102 | struct relocation_info *ri; | |
fecd2382 | 1103 | { |
355afbcd KR |
1104 | md_number_to_chars (where, ri->r_address, |
1105 | sizeof (ri->r_address)); | |
1106 | where[4] = ri->r_index & 0x0ff; | |
1107 | where[5] = (ri->r_index >> 8) & 0x0ff; | |
1108 | where[6] = (ri->r_index >> 16) & 0x0ff; | |
1109 | where[7] = ((ri->r_pcrel << 0) | |
1110 | | (ri->r_length << 1) | |
1111 | | (ri->r_extern << 3) | |
1112 | | (ri->r_bsr << 4) | |
1113 | | (ri->r_disp << 5) | |
1114 | | (ri->r_callj << 6)); | |
f3d817d8 | 1115 | } |
fecd2382 | 1116 | |
fecd2382 RP |
1117 | #ifndef WORKING_DOT_WORD |
1118 | ||
1119 | int md_short_jump_size = 0; | |
1120 | int md_long_jump_size = 0; | |
1121 | ||
355afbcd KR |
1122 | void |
1123 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
1124 | char *ptr; | |
c47d388b ME |
1125 | addressT from_addr; |
1126 | addressT to_addr; | |
355afbcd KR |
1127 | fragS *frag; |
1128 | symbolS *to_symbol; | |
fecd2382 | 1129 | { |
355afbcd | 1130 | as_fatal ("failed sanity check."); |
fecd2382 RP |
1131 | } |
1132 | ||
1133 | void | |
355afbcd KR |
1134 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
1135 | char *ptr; | |
c47d388b | 1136 | addressT from_addr, to_addr; |
355afbcd KR |
1137 | fragS *frag; |
1138 | symbolS *to_symbol; | |
fecd2382 | 1139 | { |
355afbcd | 1140 | as_fatal ("failed sanity check."); |
fecd2382 | 1141 | } |
355afbcd | 1142 | |
fecd2382 RP |
1143 | #endif |
1144 | \f | |
a39116f1 RP |
1145 | /************************************************************* |
1146 | * * | |
1147 | * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER * | |
1148 | * * | |
1149 | ************************************************************ */ | |
fecd2382 RP |
1150 | |
1151 | ||
1152 | ||
1153 | /***************************************************************************** | |
1154 | * brcnt_emit: Emit code to increment inline branch counter. | |
1155 | * | |
1156 | * See the comments above the declaration of 'br_cnt' for details on | |
1157 | * branch-prediction instrumentation. | |
1158 | **************************************************************************** */ | |
1159 | static void | |
355afbcd | 1160 | brcnt_emit () |
fecd2382 | 1161 | { |
355afbcd KR |
1162 | ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */ |
1163 | emit (0); /* Emit inline counter to be incremented */ | |
fecd2382 RP |
1164 | } |
1165 | ||
1166 | /***************************************************************************** | |
1167 | * brlab_next: generate the next branch local label | |
1168 | * | |
1169 | * See the comments above the declaration of 'br_cnt' for details on | |
1170 | * branch-prediction instrumentation. | |
1171 | **************************************************************************** */ | |
1172 | static char * | |
355afbcd | 1173 | brlab_next () |
fecd2382 | 1174 | { |
355afbcd KR |
1175 | static char buf[20]; |
1176 | ||
1177 | sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++); | |
1178 | return buf; | |
fecd2382 RP |
1179 | } |
1180 | ||
1181 | /***************************************************************************** | |
1182 | * brtab_emit: generate the fetch-prediction branch table. | |
1183 | * | |
1184 | * See the comments above the declaration of 'br_cnt' for details on | |
1185 | * branch-prediction instrumentation. | |
1186 | * | |
1187 | * The code emitted here would be functionally equivalent to the following | |
1188 | * example assembler source. | |
1189 | * | |
1190 | * .data | |
1191 | * .align 2 | |
1192 | * BR_TAB_NAME: | |
1193 | * .word 0 # link to next table | |
1194 | * .word 3 # length of table | |
1195 | * .word LBRANCH0 # 1st entry in table proper | |
1196 | * .word LBRANCH1 | |
1197 | * .word LBRANCH2 | |
1198 | ***************************************************************************** */ | |
1199 | void | |
355afbcd | 1200 | brtab_emit () |
fecd2382 | 1201 | { |
355afbcd KR |
1202 | int i; |
1203 | char buf[20]; | |
1204 | char *p; /* Where the binary was output to */ | |
1205 | fixS *fixP; /*->description of deferred address fixup */ | |
1206 | ||
1207 | if (!instrument_branches) | |
1208 | { | |
1209 | return; | |
1210 | } | |
1211 | ||
604633ae | 1212 | subseg_set (SEG_DATA, 0); /* .data */ |
355afbcd KR |
1213 | frag_align (2, 0); /* .align 2 */ |
1214 | record_alignment (now_seg, 2); | |
1215 | colon (BR_TAB_NAME); /* BR_TAB_NAME: */ | |
1216 | emit (0); /* .word 0 #link to next table */ | |
1217 | emit (br_cnt); /* .word n #length of table */ | |
1218 | ||
1219 | for (i = 0; i < br_cnt; i++) | |
1220 | { | |
1221 | sprintf (buf, "%s%d", BR_LABEL_BASE, i); | |
1222 | p = emit (0); | |
1223 | fixP = fix_new (frag_now, | |
1224 | p - frag_now->fr_literal, | |
1225 | 4, | |
1226 | symbol_find (buf), | |
1227 | 0, | |
1228 | 0, | |
355afbcd KR |
1229 | NO_RELOC); |
1230 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ | |
1231 | } | |
fecd2382 RP |
1232 | } |
1233 | ||
1234 | /***************************************************************************** | |
1235 | * cobr_fmt: generate a COBR-format instruction | |
1236 | * | |
1237 | **************************************************************************** */ | |
1238 | static | |
355afbcd KR |
1239 | void |
1240 | cobr_fmt (arg, opcode, oP) | |
1241 | char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ | |
1242 | long opcode; /* Opcode, with branch-prediction bits already set | |
a39116f1 RP |
1243 | * if necessary. |
1244 | */ | |
355afbcd KR |
1245 | struct i960_opcode *oP; |
1246 | /*->description of instruction */ | |
fecd2382 | 1247 | { |
355afbcd KR |
1248 | long instr; /* 32-bit instruction */ |
1249 | struct regop regop; /* Description of register operand */ | |
1250 | int n; /* Number of operands */ | |
1251 | int var_frag; /* 1 if varying length code fragment should | |
fecd2382 RP |
1252 | * be emitted; 0 if an address fix |
1253 | * should be emitted. | |
1254 | */ | |
355afbcd KR |
1255 | |
1256 | instr = opcode; | |
1257 | n = oP->num_ops; | |
1258 | ||
1259 | if (n >= 1) | |
1260 | { | |
1261 | /* First operand (if any) of a COBR is always a register | |
fecd2382 RP |
1262 | * operand. Parse it. |
1263 | */ | |
355afbcd KR |
1264 | parse_regop (®op, arg[1], oP->operand[0]); |
1265 | instr |= (regop.n << 19) | (regop.mode << 13); | |
1266 | } | |
1267 | if (n >= 2) | |
1268 | { | |
1269 | /* Second operand (if any) of a COBR is always a register | |
fecd2382 RP |
1270 | * operand. Parse it. |
1271 | */ | |
355afbcd KR |
1272 | parse_regop (®op, arg[2], oP->operand[1]); |
1273 | instr |= (regop.n << 14) | regop.special; | |
1274 | } | |
1275 | ||
1276 | ||
1277 | if (n < 3) | |
1278 | { | |
1279 | emit (instr); | |
1280 | ||
1281 | } | |
1282 | else | |
1283 | { | |
1284 | if (instrument_branches) | |
1285 | { | |
1286 | brcnt_emit (); | |
1287 | colon (brlab_next ()); | |
fecd2382 | 1288 | } |
355afbcd KR |
1289 | |
1290 | /* A third operand to a COBR is always a displacement. | |
fecd2382 RP |
1291 | * Parse it; if it's relaxable (a cobr "j" directive, or any |
1292 | * cobr other than bbs/bbc when the "-norelax" option is not in | |
1293 | * use) set up a variable code fragment; otherwise set up an | |
1294 | * address fix. | |
1295 | */ | |
355afbcd KR |
1296 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ |
1297 | get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0); | |
1298 | ||
1299 | if (instrument_branches) | |
1300 | { | |
1301 | brcnt_emit (); | |
fecd2382 | 1302 | } |
355afbcd KR |
1303 | } |
1304 | } /* cobr_fmt() */ | |
fecd2382 RP |
1305 | |
1306 | ||
1307 | /***************************************************************************** | |
1308 | * ctrl_fmt: generate a CTRL-format instruction | |
1309 | * | |
1310 | **************************************************************************** */ | |
1311 | static | |
355afbcd KR |
1312 | void |
1313 | ctrl_fmt (targP, opcode, num_ops) | |
1314 | char *targP; /* Pointer to text of lone operand (if any) */ | |
1315 | long opcode; /* Template of instruction */ | |
1316 | int num_ops; /* Number of operands */ | |
fecd2382 | 1317 | { |
355afbcd | 1318 | int instrument; /* TRUE iff we should add instrumentation to track |
fecd2382 RP |
1319 | * how often the branch is taken |
1320 | */ | |
355afbcd KR |
1321 | |
1322 | ||
1323 | if (num_ops == 0) | |
1324 | { | |
1325 | emit (opcode); /* Output opcode */ | |
1326 | } | |
1327 | else | |
1328 | { | |
1329 | ||
1330 | instrument = instrument_branches && (opcode != CALL) | |
1331 | && (opcode != B) && (opcode != RET) && (opcode != BAL); | |
1332 | ||
1333 | if (instrument) | |
1334 | { | |
1335 | brcnt_emit (); | |
1336 | colon (brlab_next ()); | |
1337 | } | |
1338 | ||
1339 | /* The operand MUST be an ip-relative displacment. Parse it | |
fecd2382 RP |
1340 | * and set up address fix for the instruction we just output. |
1341 | */ | |
355afbcd KR |
1342 | get_cdisp (targP, "CTRL", opcode, 24, 0, 0); |
1343 | ||
1344 | if (instrument) | |
1345 | { | |
1346 | brcnt_emit (); | |
fecd2382 | 1347 | } |
355afbcd KR |
1348 | } |
1349 | ||
fecd2382 RP |
1350 | } |
1351 | ||
1352 | ||
1353 | /***************************************************************************** | |
1354 | * emit: output instruction binary | |
1355 | * | |
1356 | * Output instruction binary, in target byte order, 4 bytes at a time. | |
1357 | * Return pointer to where it was placed. | |
1358 | * | |
1359 | **************************************************************************** */ | |
1360 | static | |
355afbcd KR |
1361 | char * |
1362 | emit (instr) | |
1363 | long instr; /* Word to be output, host byte order */ | |
fecd2382 | 1364 | { |
355afbcd KR |
1365 | char *toP; /* Where to output it */ |
1366 | ||
1367 | toP = frag_more (4); /* Allocate storage */ | |
1368 | md_number_to_chars (toP, instr, 4); /* Convert to target byte order */ | |
1369 | return toP; | |
fecd2382 RP |
1370 | } |
1371 | ||
1372 | ||
1373 | /***************************************************************************** | |
1374 | * get_args: break individual arguments out of comma-separated list | |
1375 | * | |
1376 | * Input assumptions: | |
1377 | * - all comments and labels have been removed | |
1378 | * - all strings of whitespace have been collapsed to a single blank. | |
1379 | * - all character constants ('x') have been replaced with decimal | |
1380 | * | |
1381 | * Output: | |
1382 | * args[0] is untouched. args[1] points to first operand, etc. All args: | |
1383 | * - are NULL-terminated | |
1384 | * - contain no whitespace | |
1385 | * | |
1386 | * Return value: | |
1387 | * Number of operands (0,1,2, or 3) or -1 on error. | |
1388 | * | |
1389 | **************************************************************************** */ | |
355afbcd KR |
1390 | static int |
1391 | get_args (p, args) | |
1392 | register char *p; /* Pointer to comma-separated operands; MUCKED BY US */ | |
1393 | char *args[]; /* Output arg: pointers to operands placed in args[1-3]. | |
a39116f1 RP |
1394 | * MUST ACCOMMODATE 4 ENTRIES (args[0-3]). |
1395 | */ | |
fecd2382 | 1396 | { |
355afbcd KR |
1397 | register int n; /* Number of operands */ |
1398 | register char *to; | |
1399 | /* char buf[4]; */ | |
1400 | /* int len; */ | |
1401 | ||
1402 | ||
1403 | /* Skip lead white space */ | |
1404 | while (*p == ' ') | |
1405 | { | |
1406 | p++; | |
1407 | } | |
1408 | ||
1409 | if (*p == '\0') | |
1410 | { | |
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | n = 1; | |
1415 | args[1] = p; | |
1416 | ||
1417 | /* Squeze blanks out by moving non-blanks toward start of string. | |
fecd2382 RP |
1418 | * Isolate operands, whenever comma is found. |
1419 | */ | |
355afbcd KR |
1420 | to = p; |
1421 | while (*p != '\0') | |
1422 | { | |
1423 | ||
1424 | if (*p == ' ') | |
1425 | { | |
1426 | p++; | |
1427 | ||
1428 | } | |
1429 | else if (*p == ',') | |
1430 | { | |
1431 | ||
1432 | /* Start of operand */ | |
1433 | if (n == 3) | |
1434 | { | |
1435 | as_bad ("too many operands"); | |
1436 | return -1; | |
1437 | } | |
1438 | *to++ = '\0'; /* Terminate argument */ | |
1439 | args[++n] = to; /* Start next argument */ | |
1440 | p++; | |
1441 | ||
fecd2382 | 1442 | } |
355afbcd KR |
1443 | else |
1444 | { | |
1445 | *to++ = *p++; | |
1446 | } | |
1447 | } | |
1448 | *to = '\0'; | |
1449 | return n; | |
fecd2382 RP |
1450 | } |
1451 | ||
1452 | ||
1453 | /***************************************************************************** | |
1454 | * get_cdisp: handle displacement for a COBR or CTRL instruction. | |
1455 | * | |
1456 | * Parse displacement for a COBR or CTRL instruction. | |
1457 | * | |
1458 | * If successful, output the instruction opcode and set up for it, | |
1459 | * depending on the arg 'var_frag', either: | |
1460 | * o an address fixup to be done when all symbol values are known, or | |
1461 | * o a varying length code fragment, with address fixup info. This | |
1462 | * will be done for cobr instructions that may have to be relaxed | |
c47d388b ME |
1463 | * in to compare/branch instructions (8 bytes) if the final |
1464 | * address displacement is greater than 13 bits. | |
fecd2382 | 1465 | * |
c47d388b | 1466 | *****************************************************************************/ |
fecd2382 | 1467 | static |
355afbcd KR |
1468 | void |
1469 | get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj) | |
c47d388b ME |
1470 | /* displacement as specified in source instruction */ |
1471 | char *dispP; | |
1472 | /* "COBR" or "CTRL" (for use in error message) */ | |
1473 | char *ifmtP; | |
1474 | /* Instruction needing the displacement */ | |
1475 | long instr; | |
1476 | /* # bits of displacement (13 for COBR, 24 for CTRL) */ | |
1477 | int numbits; | |
1478 | /* 1 if varying length code fragment should be emitted; | |
1479 | * 0 if an address fix should be emitted. | |
1480 | */ | |
1481 | int var_frag; | |
1482 | /* 1 if callj relocation should be done; else 0 */ | |
1483 | int callj; | |
fecd2382 | 1484 | { |
355afbcd KR |
1485 | expressionS e; /* Parsed expression */ |
1486 | fixS *fixP; /* Structure describing needed address fix */ | |
1487 | char *outP; /* Where instruction binary is output to */ | |
1488 | ||
1489 | fixP = NULL; | |
1490 | ||
5ac34ac3 ILT |
1491 | parse_expr (dispP, &e); |
1492 | switch (e.X_op) | |
355afbcd | 1493 | { |
5ac34ac3 | 1494 | case O_illegal: |
355afbcd | 1495 | as_bad ("expression syntax error"); |
355afbcd | 1496 | |
5ac34ac3 ILT |
1497 | case O_symbol: |
1498 | if (S_GET_SEGMENT (e.X_add_symbol) == text_section | |
1499 | || S_GET_SEGMENT (e.X_add_symbol) == undefined_section) | |
1500 | { | |
1501 | if (var_frag) | |
1502 | { | |
1503 | outP = frag_more (8); /* Allocate worst-case storage */ | |
1504 | md_number_to_chars (outP, instr, 4); | |
1505 | frag_variant (rs_machine_dependent, 4, 4, 1, | |
1506 | adds (e), offs (e), outP, 0, 0); | |
1507 | } | |
1508 | else | |
1509 | { | |
1510 | /* Set up a new fix structure, so address can be updated | |
1511 | * when all symbol values are known. | |
1512 | */ | |
1513 | outP = emit (instr); | |
1514 | fixP = fix_new (frag_now, | |
1515 | outP - frag_now->fr_literal, | |
1516 | 4, | |
1517 | adds (e), | |
1518 | offs (e), | |
1519 | 1, | |
1520 | NO_RELOC); | |
1521 | ||
f3d817d8 | 1522 | fixP->fx_tcbit = callj; |
5ac34ac3 ILT |
1523 | |
1524 | /* We want to modify a bit field when the address is | |
1525 | * known. But we don't need all the garbage in the | |
1526 | * bit_fix structure. So we're going to lie and store | |
1527 | * the number of bits affected instead of a pointer. | |
1528 | */ | |
1529 | fixP->fx_bit_fixP = (bit_fixS *) numbits; | |
1530 | } | |
355afbcd KR |
1531 | } |
1532 | else | |
5ac34ac3 | 1533 | as_bad ("attempt to branch into different segment"); |
355afbcd KR |
1534 | break; |
1535 | ||
1536 | default: | |
1537 | as_bad ("target of %s instruction must be a label", ifmtP); | |
1538 | break; | |
1539 | } | |
fecd2382 RP |
1540 | } |
1541 | ||
1542 | ||
1543 | /***************************************************************************** | |
1544 | * get_ispec: parse a memory operand for an index specification | |
1545 | * | |
1546 | * Here, an "index specification" is taken to be anything surrounded | |
1547 | * by square brackets and NOT followed by anything else. | |
1548 | * | |
1549 | * If it's found, detach it from the input string, remove the surrounding | |
1550 | * square brackets, and return a pointer to it. Otherwise, return NULL. | |
1551 | * | |
1552 | **************************************************************************** */ | |
1553 | static | |
355afbcd KR |
1554 | char * |
1555 | get_ispec (textP) | |
1556 | char *textP; /*->memory operand from source instruction, no white space */ | |
fecd2382 | 1557 | { |
355afbcd KR |
1558 | char *start; /*->start of index specification */ |
1559 | char *end; /*->end of index specification */ | |
1560 | ||
1561 | /* Find opening square bracket, if any | |
fecd2382 | 1562 | */ |
355afbcd KR |
1563 | start = strchr (textP, '['); |
1564 | ||
1565 | if (start != NULL) | |
1566 | { | |
1567 | ||
1568 | /* Eliminate '[', detach from rest of operand */ | |
1569 | *start++ = '\0'; | |
1570 | ||
1571 | end = strchr (start, ']'); | |
1572 | ||
1573 | if (end == NULL) | |
1574 | { | |
1575 | as_bad ("unmatched '['"); | |
1576 | ||
1577 | } | |
1578 | else | |
1579 | { | |
1580 | /* Eliminate ']' and make sure it was the last thing | |
fecd2382 RP |
1581 | * in the string. |
1582 | */ | |
355afbcd KR |
1583 | *end = '\0'; |
1584 | if (*(end + 1) != '\0') | |
1585 | { | |
1586 | as_bad ("garbage after index spec ignored"); | |
1587 | } | |
fecd2382 | 1588 | } |
355afbcd KR |
1589 | } |
1590 | return start; | |
fecd2382 RP |
1591 | } |
1592 | ||
1593 | /***************************************************************************** | |
1594 | * get_regnum: | |
1595 | * | |
1596 | * Look up a (suspected) register name in the register table and return the | |
1597 | * associated register number (or -1 if not found). | |
1598 | * | |
1599 | **************************************************************************** */ | |
1600 | static | |
355afbcd KR |
1601 | int |
1602 | get_regnum (regname) | |
1603 | char *regname; /* Suspected register name */ | |
fecd2382 | 1604 | { |
355afbcd KR |
1605 | int *rP; |
1606 | ||
1607 | rP = (int *) hash_find (reg_hash, regname); | |
1608 | return (rP == NULL) ? -1 : *rP; | |
fecd2382 RP |
1609 | } |
1610 | ||
1611 | ||
1612 | /***************************************************************************** | |
1613 | * i_scan: perform lexical scan of ascii assembler instruction. | |
1614 | * | |
1615 | * Input assumptions: | |
1616 | * - input string is an i80960 instruction (not a pseudo-op) | |
1617 | * - all comments and labels have been removed | |
1618 | * - all strings of whitespace have been collapsed to a single blank. | |
1619 | * | |
1620 | * Output: | |
1621 | * args[0] points to opcode, other entries point to operands. All strings: | |
1622 | * - are NULL-terminated | |
1623 | * - contain no whitespace | |
1624 | * - have character constants ('x') replaced with a decimal number | |
1625 | * | |
1626 | * Return value: | |
1627 | * Number of operands (0,1,2, or 3) or -1 on error. | |
1628 | * | |
1629 | **************************************************************************** */ | |
355afbcd KR |
1630 | static int |
1631 | i_scan (iP, args) | |
1632 | register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */ | |
1633 | char *args[]; /* Output arg: pointers to opcode and operands placed | |
a39116f1 RP |
1634 | * here. MUST ACCOMMODATE 4 ENTRIES. |
1635 | */ | |
fecd2382 | 1636 | { |
355afbcd KR |
1637 | |
1638 | /* Isolate opcode */ | |
1639 | if (*(iP) == ' ') | |
1640 | { | |
1641 | iP++; | |
1642 | } /* Skip lead space, if any */ | |
1643 | args[0] = iP; | |
1644 | for (; *iP != ' '; iP++) | |
1645 | { | |
1646 | if (*iP == '\0') | |
1647 | { | |
1648 | /* There are no operands */ | |
1649 | if (args[0] == iP) | |
1650 | { | |
1651 | /* We never moved: there was no opcode either! */ | |
1652 | as_bad ("missing opcode"); | |
1653 | return -1; | |
1654 | } | |
1655 | return 0; | |
fecd2382 | 1656 | } |
355afbcd KR |
1657 | } |
1658 | *iP++ = '\0'; /* Terminate opcode */ | |
1659 | return (get_args (iP, args)); | |
1660 | } /* i_scan() */ | |
fecd2382 RP |
1661 | |
1662 | ||
1663 | /***************************************************************************** | |
1664 | * mem_fmt: generate a MEMA- or MEMB-format instruction | |
1665 | * | |
1666 | **************************************************************************** */ | |
355afbcd KR |
1667 | static void |
1668 | mem_fmt (args, oP, callx) | |
1669 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ | |
1670 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
1671 | int callx; /* Is this a callx opcode */ | |
fecd2382 | 1672 | { |
355afbcd KR |
1673 | int i; /* Loop counter */ |
1674 | struct regop regop; /* Description of register operand */ | |
1675 | char opdesc; /* Operand descriptor byte */ | |
1676 | memS instr; /* Description of binary to be output */ | |
1677 | char *outP; /* Where the binary was output to */ | |
1678 | expressionS expr; /* Parsed expression */ | |
1679 | fixS *fixP; /*->description of deferred address fixup */ | |
1680 | ||
f3d817d8 DM |
1681 | #ifdef OBJ_COFF |
1682 | /* COFF support isn't in place yet for callx relaxing. */ | |
1683 | callx = 0; | |
1684 | #endif | |
1685 | ||
355afbcd KR |
1686 | memset (&instr, '\0', sizeof (memS)); |
1687 | instr.opcode = oP->opcode; | |
1688 | ||
1689 | /* Process operands. */ | |
1690 | for (i = 1; i <= oP->num_ops; i++) | |
1691 | { | |
1692 | opdesc = oP->operand[i - 1]; | |
1693 | ||
1694 | if (MEMOP (opdesc)) | |
1695 | { | |
1696 | parse_memop (&instr, args[i], oP->format); | |
fecd2382 | 1697 | } |
355afbcd KR |
1698 | else |
1699 | { | |
1700 | parse_regop (®op, args[i], opdesc); | |
1701 | instr.opcode |= regop.n << 19; | |
fecd2382 | 1702 | } |
355afbcd KR |
1703 | } |
1704 | ||
1705 | /* Output opcode */ | |
1706 | outP = emit (instr.opcode); | |
1707 | ||
1708 | if (instr.disp == 0) | |
1709 | { | |
1710 | return; | |
1711 | } | |
1712 | ||
1713 | /* Parse and process the displacement */ | |
5ac34ac3 ILT |
1714 | parse_expr (instr.e, &expr); |
1715 | switch (expr.X_op) | |
355afbcd | 1716 | { |
5ac34ac3 | 1717 | case O_illegal: |
355afbcd KR |
1718 | as_bad ("expression syntax error"); |
1719 | break; | |
1720 | ||
5ac34ac3 | 1721 | case O_constant: |
355afbcd KR |
1722 | if (instr.disp == 32) |
1723 | { | |
1724 | (void) emit (offs (expr)); /* Output displacement */ | |
1725 | } | |
1726 | else | |
1727 | { | |
1728 | /* 12-bit displacement */ | |
1729 | if (offs (expr) & ~0xfff) | |
1730 | { | |
1731 | /* Won't fit in 12 bits: convert already-output | |
5ac34ac3 ILT |
1732 | * instruction to MEMB format, output |
1733 | * displacement. | |
1734 | */ | |
355afbcd KR |
1735 | mema_to_memb (outP); |
1736 | (void) emit (offs (expr)); | |
1737 | } | |
1738 | else | |
1739 | { | |
1740 | /* WILL fit in 12 bits: OR into opcode and | |
5ac34ac3 ILT |
1741 | * overwrite the binary we already put out |
1742 | */ | |
355afbcd KR |
1743 | instr.opcode |= offs (expr); |
1744 | md_number_to_chars (outP, instr.opcode, 4); | |
1745 | } | |
1746 | } | |
1747 | break; | |
1748 | ||
5ac34ac3 | 1749 | default: |
355afbcd KR |
1750 | if (instr.disp == 12) |
1751 | { | |
1752 | /* Displacement is dependent on a symbol, whose value | |
c47d388b ME |
1753 | * may change at link time. We HAVE to reserve 32 bits. |
1754 | * Convert already-output opcode to MEMB format. | |
1755 | */ | |
355afbcd KR |
1756 | mema_to_memb (outP); |
1757 | } | |
1758 | ||
1759 | /* Output 0 displacement and set up address fixup for when | |
c47d388b ME |
1760 | * this symbol's value becomes known. |
1761 | */ | |
355afbcd | 1762 | outP = emit ((long) 0); |
5ac34ac3 ILT |
1763 | fixP = fix_new_exp (frag_now, |
1764 | outP - frag_now->fr_literal, | |
1765 | 4, | |
1766 | &expr, | |
1767 | 0, | |
1768 | NO_RELOC); | |
355afbcd | 1769 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ |
f3d817d8 DM |
1770 | /* Steve's linker relaxing hack. Mark this 32-bit relocation as |
1771 | being in the instruction stream, specifically as part of a callx | |
1772 | instruction. */ | |
1773 | fixP->fx_bsr = callx; | |
355afbcd | 1774 | break; |
355afbcd KR |
1775 | } |
1776 | } /* memfmt() */ | |
fecd2382 RP |
1777 | |
1778 | ||
1779 | /***************************************************************************** | |
1780 | * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. | |
1781 | * | |
1782 | * There are 2 possible MEMA formats: | |
1783 | * - displacement only | |
1784 | * - displacement + abase | |
1785 | * | |
1786 | * They are distinguished by the setting of the MEMA_ABASE bit. | |
1787 | * | |
1788 | **************************************************************************** */ | |
355afbcd KR |
1789 | static void |
1790 | mema_to_memb (opcodeP) | |
1791 | char *opcodeP; /* Where to find the opcode, in target byte order */ | |
fecd2382 | 1792 | { |
355afbcd KR |
1793 | long opcode; /* Opcode in host byte order */ |
1794 | long mode; /* Mode bits for MEMB instruction */ | |
1795 | ||
1796 | opcode = md_chars_to_number (opcodeP, 4); | |
1797 | know (!(opcode & MEMB_BIT)); | |
1798 | ||
1799 | mode = MEMB_BIT | D_BIT; | |
1800 | if (opcode & MEMA_ABASE) | |
1801 | { | |
1802 | mode |= A_BIT; | |
1803 | } | |
1804 | ||
1805 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */ | |
1806 | opcode |= mode; /* Set MEMB mode bits */ | |
1807 | ||
1808 | md_number_to_chars (opcodeP, opcode, 4); | |
1809 | } /* mema_to_memb() */ | |
fecd2382 RP |
1810 | |
1811 | ||
1812 | /***************************************************************************** | |
1813 | * parse_expr: parse an expression | |
1814 | * | |
1815 | * Use base assembler's expression parser to parse an expression. | |
1816 | * It, unfortunately, runs off a global which we have to save/restore | |
1817 | * in order to make it work for us. | |
1818 | * | |
1819 | * An empty expression string is treated as an absolute 0. | |
1820 | * | |
5ac34ac3 | 1821 | * Sets O_illegal regardless of expression evaluation if entire input |
fecd2382 RP |
1822 | * string is not consumed in the evaluation -- tolerate no dangling junk! |
1823 | * | |
1824 | **************************************************************************** */ | |
5ac34ac3 | 1825 | static void |
355afbcd KR |
1826 | parse_expr (textP, expP) |
1827 | char *textP; /* Text of expression to be parsed */ | |
1828 | expressionS *expP; /* Where to put the results of parsing */ | |
fecd2382 | 1829 | { |
355afbcd | 1830 | char *save_in; /* Save global here */ |
355afbcd KR |
1831 | symbolS *symP; |
1832 | ||
1833 | know (textP); | |
1834 | ||
1835 | if (*textP == '\0') | |
1836 | { | |
1837 | /* Treat empty string as absolute 0 */ | |
5ac34ac3 | 1838 | expP->X_add_symbol = expP->X_op_symbol = NULL; |
355afbcd | 1839 | expP->X_add_number = 0; |
604633ae | 1840 | expP->X_op = O_constant; |
355afbcd KR |
1841 | } |
1842 | else | |
1843 | { | |
1844 | save_in = input_line_pointer; /* Save global */ | |
1845 | input_line_pointer = textP; /* Make parser work for us */ | |
1846 | ||
604633ae | 1847 | (void) expression (expP); |
355afbcd KR |
1848 | if (input_line_pointer - textP != strlen (textP)) |
1849 | { | |
1850 | /* Did not consume all of the input */ | |
5ac34ac3 | 1851 | expP->X_op = O_illegal; |
355afbcd KR |
1852 | } |
1853 | symP = expP->X_add_symbol; | |
1854 | if (symP && (hash_find (reg_hash, S_GET_NAME (symP)))) | |
1855 | { | |
1856 | /* Register name in an expression */ | |
5ac34ac3 ILT |
1857 | /* FIXME: this isn't much of a check any more. */ |
1858 | expP->X_op = O_illegal; | |
fecd2382 | 1859 | } |
355afbcd KR |
1860 | |
1861 | input_line_pointer = save_in; /* Restore global */ | |
1862 | } | |
fecd2382 RP |
1863 | } |
1864 | ||
1865 | ||
1866 | /***************************************************************************** | |
1867 | * parse_ldcont: | |
1868 | * Parse and replace a 'ldconst' pseudo-instruction with an appropriate | |
1869 | * i80960 instruction. | |
1870 | * | |
1871 | * Assumes the input consists of: | |
1872 | * arg[0] opcode mnemonic ('ldconst') | |
1873 | * arg[1] first operand (constant) | |
1874 | * arg[2] name of register to be loaded | |
1875 | * | |
1876 | * Replaces opcode and/or operands as appropriate. | |
1877 | * | |
1878 | * Returns the new number of arguments, or -1 on failure. | |
1879 | * | |
1880 | **************************************************************************** */ | |
1881 | static | |
355afbcd KR |
1882 | int |
1883 | parse_ldconst (arg) | |
1884 | char *arg[]; /* See above */ | |
fecd2382 | 1885 | { |
355afbcd KR |
1886 | int n; /* Constant to be loaded */ |
1887 | int shift; /* Shift count for "shlo" instruction */ | |
1888 | static char buf[5]; /* Literal for first operand */ | |
1889 | static char buf2[5]; /* Literal for second operand */ | |
1890 | expressionS e; /* Parsed expression */ | |
1891 | ||
1892 | ||
1893 | arg[3] = NULL; /* So we can tell at the end if it got used or not */ | |
1894 | ||
5ac34ac3 ILT |
1895 | parse_expr (arg[1], &e); |
1896 | switch (e.X_op) | |
355afbcd | 1897 | { |
5ac34ac3 | 1898 | default: |
355afbcd KR |
1899 | /* We're dependent on one or more symbols -- use "lda" */ |
1900 | arg[0] = "lda"; | |
1901 | break; | |
1902 | ||
5ac34ac3 | 1903 | case O_constant: |
355afbcd | 1904 | /* Try the following mappings: |
5ac34ac3 ILT |
1905 | * ldconst 0,<reg> ->mov 0,<reg> |
1906 | * ldconst 31,<reg> ->mov 31,<reg> | |
1907 | * ldconst 32,<reg> ->addo 1,31,<reg> | |
1908 | * ldconst 62,<reg> ->addo 31,31,<reg> | |
1909 | * ldconst 64,<reg> ->shlo 8,3,<reg> | |
1910 | * ldconst -1,<reg> ->subo 1,0,<reg> | |
1911 | * ldconst -31,<reg>->subo 31,0,<reg> | |
1912 | * | |
1913 | * anthing else becomes: | |
1914 | * lda xxx,<reg> | |
1915 | */ | |
355afbcd KR |
1916 | n = offs (e); |
1917 | if ((0 <= n) && (n <= 31)) | |
1918 | { | |
1919 | arg[0] = "mov"; | |
1920 | ||
1921 | } | |
1922 | else if ((-31 <= n) && (n <= -1)) | |
1923 | { | |
1924 | arg[0] = "subo"; | |
1925 | arg[3] = arg[2]; | |
1926 | sprintf (buf, "%d", -n); | |
1927 | arg[1] = buf; | |
1928 | arg[2] = "0"; | |
1929 | ||
fecd2382 | 1930 | } |
355afbcd KR |
1931 | else if ((32 <= n) && (n <= 62)) |
1932 | { | |
1933 | arg[0] = "addo"; | |
1934 | arg[3] = arg[2]; | |
1935 | arg[1] = "31"; | |
1936 | sprintf (buf, "%d", n - 31); | |
1937 | arg[2] = buf; | |
1938 | ||
1939 | } | |
1940 | else if ((shift = shift_ok (n)) != 0) | |
1941 | { | |
1942 | arg[0] = "shlo"; | |
1943 | arg[3] = arg[2]; | |
1944 | sprintf (buf, "%d", shift); | |
1945 | arg[1] = buf; | |
1946 | sprintf (buf2, "%d", n >> shift); | |
1947 | arg[2] = buf2; | |
1948 | ||
1949 | } | |
1950 | else | |
1951 | { | |
1952 | arg[0] = "lda"; | |
1953 | } | |
1954 | break; | |
1955 | ||
5ac34ac3 | 1956 | case O_illegal: |
355afbcd KR |
1957 | as_bad ("invalid constant"); |
1958 | return -1; | |
1959 | break; | |
1960 | } | |
1961 | return (arg[3] == 0) ? 2 : 3; | |
fecd2382 RP |
1962 | } |
1963 | ||
1964 | /***************************************************************************** | |
1965 | * parse_memop: parse a memory operand | |
1966 | * | |
1967 | * This routine is based on the observation that the 4 mode bits of the | |
1968 | * MEMB format, taken individually, have fairly consistent meaning: | |
1969 | * | |
1970 | * M3 (bit 13): 1 if displacement is present (D_BIT) | |
1971 | * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) | |
1972 | * M1 (bit 11): 1 if index is present (I_BIT) | |
1973 | * M0 (bit 10): 1 if abase is present (A_BIT) | |
1974 | * | |
1975 | * So we parse the memory operand and set bits in the mode as we find | |
1976 | * things. Then at the end, if we go to MEMB format, we need only set | |
1977 | * the MEMB bit (M2) and our mode is built for us. | |
1978 | * | |
1979 | * Unfortunately, I said "fairly consistent". The exceptions: | |
1980 | * | |
1981 | * DBIA | |
1982 | * 0100 Would seem illegal, but means "abase-only". | |
1983 | * | |
1984 | * 0101 Would seem to mean "abase-only" -- it means IP-relative. | |
1985 | * Must be converted to 0100. | |
1986 | * | |
1987 | * 0110 Would seem to mean "index-only", but is reserved. | |
1988 | * We turn on the D bit and provide a 0 displacement. | |
1989 | * | |
1990 | * The other thing to observe is that we parse from the right, peeling | |
1991 | * things * off as we go: first any index spec, then any abase, then | |
1992 | * the displacement. | |
1993 | * | |
1994 | **************************************************************************** */ | |
1995 | static | |
355afbcd KR |
1996 | void |
1997 | parse_memop (memP, argP, optype) | |
1998 | memS *memP; /* Where to put the results */ | |
1999 | char *argP; /* Text of the operand to be parsed */ | |
2000 | int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */ | |
fecd2382 | 2001 | { |
355afbcd KR |
2002 | char *indexP; /* Pointer to index specification with "[]" removed */ |
2003 | char *p; /* Temp char pointer */ | |
2004 | char iprel_flag; /* True if this is an IP-relative operand */ | |
2005 | int regnum; /* Register number */ | |
2006 | int scale; /* Scale factor: 1,2,4,8, or 16. Later converted | |
fecd2382 RP |
2007 | * to internal format (0,1,2,3,4 respectively). |
2008 | */ | |
355afbcd KR |
2009 | int mode; /* MEMB mode bits */ |
2010 | int *intP; /* Pointer to register number */ | |
2011 | ||
2012 | /* The following table contains the default scale factors for each | |
c47d388b ME |
2013 | * type of memory instruction. It is accessed using (optype-MEM1) |
2014 | * as an index -- thus it assumes the 'optype' constants are assigned | |
2015 | * consecutive values, in the order they appear in this table | |
2016 | */ | |
355afbcd KR |
2017 | static int def_scale[] = |
2018 | { | |
2019 | 1, /* MEM1 */ | |
2020 | 2, /* MEM2 */ | |
2021 | 4, /* MEM4 */ | |
2022 | 8, /* MEM8 */ | |
2023 | -1, /* MEM12 -- no valid default */ | |
2024 | 16 /* MEM16 */ | |
2025 | }; | |
2026 | ||
2027 | ||
2028 | iprel_flag = mode = 0; | |
2029 | ||
2030 | /* Any index present? */ | |
2031 | indexP = get_ispec (argP); | |
2032 | if (indexP) | |
2033 | { | |
2034 | p = strchr (indexP, '*'); | |
2035 | if (p == NULL) | |
2036 | { | |
2037 | /* No explicit scale -- use default for this | |
fecd2382 RP |
2038 | *instruction type. |
2039 | */ | |
355afbcd KR |
2040 | scale = def_scale[optype - MEM1]; |
2041 | } | |
2042 | else | |
2043 | { | |
2044 | *p++ = '\0'; /* Eliminate '*' */ | |
2045 | ||
2046 | /* Now indexP->a '\0'-terminated register name, | |
fecd2382 RP |
2047 | * and p->a scale factor. |
2048 | */ | |
355afbcd KR |
2049 | |
2050 | if (!strcmp (p, "16")) | |
2051 | { | |
2052 | scale = 16; | |
2053 | } | |
2054 | else if (strchr ("1248", *p) && (p[1] == '\0')) | |
2055 | { | |
2056 | scale = *p - '0'; | |
2057 | } | |
2058 | else | |
2059 | { | |
2060 | scale = -1; | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | regnum = get_regnum (indexP); /* Get index reg. # */ | |
2065 | if (!IS_RG_REG (regnum)) | |
2066 | { | |
2067 | as_bad ("invalid index register"); | |
2068 | return; | |
fecd2382 | 2069 | } |
355afbcd KR |
2070 | |
2071 | /* Convert scale to its binary encoding */ | |
2072 | switch (scale) | |
2073 | { | |
2074 | case 1: | |
2075 | scale = 0 << 7; | |
2076 | break; | |
2077 | case 2: | |
2078 | scale = 1 << 7; | |
2079 | break; | |
2080 | case 4: | |
2081 | scale = 2 << 7; | |
2082 | break; | |
2083 | case 8: | |
2084 | scale = 3 << 7; | |
2085 | break; | |
2086 | case 16: | |
2087 | scale = 4 << 7; | |
2088 | break; | |
2089 | default: | |
2090 | as_bad ("invalid scale factor"); | |
2091 | return; | |
2092 | }; | |
2093 | ||
2094 | memP->opcode |= scale | regnum; /* Set index bits in opcode */ | |
2095 | mode |= I_BIT; /* Found a valid index spec */ | |
2096 | } | |
2097 | ||
2098 | /* Any abase (Register Indirect) specification present? */ | |
2099 | if ((p = strrchr (argP, '(')) != NULL) | |
2100 | { | |
2101 | /* "(" is there -- does it start a legal abase spec? | |
fecd2382 RP |
2102 | * (If not it could be part of a displacement expression.) |
2103 | */ | |
355afbcd KR |
2104 | intP = (int *) hash_find (areg_hash, p); |
2105 | if (intP != NULL) | |
2106 | { | |
2107 | /* Got an abase here */ | |
2108 | regnum = *intP; | |
2109 | *p = '\0'; /* discard register spec */ | |
2110 | if (regnum == IPREL) | |
2111 | { | |
2112 | /* We have to specialcase ip-rel mode */ | |
2113 | iprel_flag = 1; | |
2114 | } | |
2115 | else | |
2116 | { | |
2117 | memP->opcode |= regnum << 14; | |
2118 | mode |= A_BIT; | |
2119 | } | |
fecd2382 | 2120 | } |
355afbcd KR |
2121 | } |
2122 | ||
2123 | /* Any expression present? */ | |
2124 | memP->e = argP; | |
2125 | if (*argP != '\0') | |
2126 | { | |
2127 | mode |= D_BIT; | |
2128 | } | |
2129 | ||
2130 | /* Special-case ip-relative addressing */ | |
2131 | if (iprel_flag) | |
2132 | { | |
2133 | if (mode & I_BIT) | |
2134 | { | |
2135 | syntax (); | |
fecd2382 | 2136 | } |
355afbcd KR |
2137 | else |
2138 | { | |
2139 | memP->opcode |= 5 << 10; /* IP-relative mode */ | |
2140 | memP->disp = 32; | |
fecd2382 | 2141 | } |
355afbcd KR |
2142 | return; |
2143 | } | |
2144 | ||
2145 | /* Handle all other modes */ | |
2146 | switch (mode) | |
2147 | { | |
2148 | case D_BIT | A_BIT: | |
2149 | /* Go with MEMA instruction format for now (grow to MEMB later | |
fecd2382 RP |
2150 | * if 12 bits is not enough for the displacement). |
2151 | * MEMA format has a single mode bit: set it to indicate | |
2152 | * that abase is present. | |
2153 | */ | |
355afbcd KR |
2154 | memP->opcode |= MEMA_ABASE; |
2155 | memP->disp = 12; | |
2156 | break; | |
2157 | ||
2158 | case D_BIT: | |
2159 | /* Go with MEMA instruction format for now (grow to MEMB later | |
fecd2382 RP |
2160 | * if 12 bits is not enough for the displacement). |
2161 | */ | |
355afbcd KR |
2162 | memP->disp = 12; |
2163 | break; | |
2164 | ||
2165 | case A_BIT: | |
2166 | /* For some reason, the bit string for this mode is not | |
fecd2382 RP |
2167 | * consistent: it should be 0 (exclusive of the MEMB bit), |
2168 | * so we set it "by hand" here. | |
2169 | */ | |
355afbcd KR |
2170 | memP->opcode |= MEMB_BIT; |
2171 | break; | |
2172 | ||
2173 | case A_BIT | I_BIT: | |
2174 | /* set MEMB bit in mode, and OR in mode bits */ | |
2175 | memP->opcode |= mode | MEMB_BIT; | |
2176 | break; | |
2177 | ||
2178 | case I_BIT: | |
2179 | /* Treat missing displacement as displacement of 0 */ | |
2180 | mode |= D_BIT; | |
2181 | /*********************** | |
fecd2382 RP |
2182 | * Fall into next case * |
2183 | ********************** */ | |
355afbcd KR |
2184 | case D_BIT | A_BIT | I_BIT: |
2185 | case D_BIT | I_BIT: | |
2186 | /* set MEMB bit in mode, and OR in mode bits */ | |
2187 | memP->opcode |= mode | MEMB_BIT; | |
2188 | memP->disp = 32; | |
2189 | break; | |
2190 | ||
2191 | default: | |
2192 | syntax (); | |
2193 | break; | |
2194 | } | |
fecd2382 RP |
2195 | } |
2196 | ||
2197 | /***************************************************************************** | |
2198 | * parse_po: parse machine-dependent pseudo-op | |
2199 | * | |
2200 | * This is a top-level routine for machine-dependent pseudo-ops. It slurps | |
2201 | * up the rest of the input line, breaks out the individual arguments, | |
2202 | * and dispatches them to the correct handler. | |
2203 | **************************************************************************** */ | |
2204 | static | |
355afbcd KR |
2205 | void |
2206 | parse_po (po_num) | |
2207 | int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */ | |
fecd2382 | 2208 | { |
355afbcd | 2209 | char *args[4]; /* Pointers operands, with no embedded whitespace. |
fecd2382 RP |
2210 | * arg[0] unused. |
2211 | * arg[1-3]->operands | |
2212 | */ | |
355afbcd KR |
2213 | int n_ops; /* Number of operands */ |
2214 | char *p; /* Pointer to beginning of unparsed argument string */ | |
2215 | char eol; /* Character that indicated end of line */ | |
2216 | ||
2217 | extern char is_end_of_line[]; | |
2218 | ||
2219 | /* Advance input pointer to end of line. */ | |
2220 | p = input_line_pointer; | |
80aab579 | 2221 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
355afbcd KR |
2222 | { |
2223 | input_line_pointer++; | |
2224 | } | |
2225 | eol = *input_line_pointer; /* Save end-of-line char */ | |
2226 | *input_line_pointer = '\0'; /* Terminate argument list */ | |
2227 | ||
2228 | /* Parse out operands */ | |
2229 | n_ops = get_args (p, args); | |
2230 | if (n_ops == -1) | |
2231 | { | |
2232 | return; | |
2233 | } | |
2234 | ||
2235 | /* Dispatch to correct handler */ | |
2236 | switch (po_num) | |
2237 | { | |
2238 | case S_SYSPROC: | |
2239 | s_sysproc (n_ops, args); | |
2240 | break; | |
2241 | case S_LEAFPROC: | |
2242 | s_leafproc (n_ops, args); | |
2243 | break; | |
2244 | default: | |
2245 | BAD_CASE (po_num); | |
2246 | break; | |
2247 | } | |
2248 | ||
2249 | /* Restore eol, so line numbers get updated correctly. Base assembler | |
fecd2382 RP |
2250 | * assumes we leave input pointer pointing at char following the eol. |
2251 | */ | |
355afbcd | 2252 | *input_line_pointer++ = eol; |
fecd2382 RP |
2253 | } |
2254 | ||
2255 | /***************************************************************************** | |
2256 | * parse_regop: parse a register operand. | |
2257 | * | |
2258 | * In case of illegal operand, issue a message and return some valid | |
2259 | * information so instruction processing can continue. | |
2260 | **************************************************************************** */ | |
2261 | static | |
355afbcd KR |
2262 | void |
2263 | parse_regop (regopP, optext, opdesc) | |
2264 | struct regop *regopP; /* Where to put description of register operand */ | |
2265 | char *optext; /* Text of operand */ | |
2266 | char opdesc; /* Descriptor byte: what's legal for this operand */ | |
fecd2382 | 2267 | { |
355afbcd KR |
2268 | int n; /* Register number */ |
2269 | expressionS e; /* Parsed expression */ | |
2270 | ||
2271 | /* See if operand is a register */ | |
2272 | n = get_regnum (optext); | |
2273 | if (n >= 0) | |
2274 | { | |
2275 | if (IS_RG_REG (n)) | |
2276 | { | |
2277 | /* global or local register */ | |
2278 | if (!REG_ALIGN (opdesc, n)) | |
2279 | { | |
2280 | as_bad ("unaligned register"); | |
2281 | } | |
2282 | regopP->n = n; | |
2283 | regopP->mode = 0; | |
2284 | regopP->special = 0; | |
2285 | return; | |
2286 | } | |
2287 | else if (IS_FP_REG (n) && FP_OK (opdesc)) | |
2288 | { | |
2289 | /* Floating point register, and it's allowed */ | |
2290 | regopP->n = n - FP0; | |
2291 | regopP->mode = 1; | |
2292 | regopP->special = 0; | |
2293 | return; | |
2294 | } | |
2295 | else if (IS_SF_REG (n) && SFR_OK (opdesc)) | |
2296 | { | |
2297 | /* Special-function register, and it's allowed */ | |
2298 | regopP->n = n - SF0; | |
2299 | regopP->mode = 0; | |
2300 | regopP->special = 1; | |
2301 | if (!targ_has_sfr (regopP->n)) | |
2302 | { | |
2303 | as_bad ("no such sfr in this architecture"); | |
2304 | } | |
2305 | return; | |
2306 | } | |
2307 | } | |
2308 | else if (LIT_OK (opdesc)) | |
2309 | { | |
2310 | /* | |
fecd2382 RP |
2311 | * How about a literal? |
2312 | */ | |
355afbcd KR |
2313 | regopP->mode = 1; |
2314 | regopP->special = 0; | |
2315 | if (FP_OK (opdesc)) | |
2316 | { /* floating point literal acceptable */ | |
2317 | /* Skip over 0f, 0d, or 0e prefix */ | |
2318 | if ((optext[0] == '0') | |
2319 | && (optext[1] >= 'd') | |
2320 | && (optext[1] <= 'f')) | |
2321 | { | |
2322 | optext += 2; | |
2323 | } | |
2324 | ||
2325 | if (!strcmp (optext, "0.0") || !strcmp (optext, "0")) | |
2326 | { | |
2327 | regopP->n = 0x10; | |
2328 | return; | |
2329 | } | |
2330 | if (!strcmp (optext, "1.0") || !strcmp (optext, "1")) | |
2331 | { | |
2332 | regopP->n = 0x16; | |
2333 | return; | |
2334 | } | |
2335 | ||
fecd2382 | 2336 | } |
355afbcd KR |
2337 | else |
2338 | { /* fixed point literal acceptable */ | |
5ac34ac3 ILT |
2339 | parse_expr (optext, &e); |
2340 | if (e.X_op != O_constant | |
355afbcd KR |
2341 | || (offs (e) < 0) || (offs (e) > 31)) |
2342 | { | |
2343 | as_bad ("illegal literal"); | |
2344 | offs (e) = 0; | |
2345 | } | |
2346 | regopP->n = offs (e); | |
2347 | return; | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | /* Nothing worked */ | |
2352 | syntax (); | |
2353 | regopP->mode = 0; /* Register r0 is always a good one */ | |
2354 | regopP->n = 0; | |
2355 | regopP->special = 0; | |
2356 | } /* parse_regop() */ | |
fecd2382 RP |
2357 | |
2358 | /***************************************************************************** | |
2359 | * reg_fmt: generate a REG-format instruction | |
2360 | * | |
2361 | **************************************************************************** */ | |
355afbcd KR |
2362 | static void |
2363 | reg_fmt (args, oP) | |
2364 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ | |
2365 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
fecd2382 | 2366 | { |
355afbcd KR |
2367 | long instr; /* Binary to be output */ |
2368 | struct regop regop; /* Description of register operand */ | |
2369 | int n_ops; /* Number of operands */ | |
2370 | ||
2371 | ||
2372 | instr = oP->opcode; | |
2373 | n_ops = oP->num_ops; | |
2374 | ||
2375 | if (n_ops >= 1) | |
2376 | { | |
2377 | parse_regop (®op, args[1], oP->operand[0]); | |
2378 | ||
2379 | if ((n_ops == 1) && !(instr & M3)) | |
2380 | { | |
2381 | /* 1-operand instruction in which the dst field should | |
fecd2382 RP |
2382 | * be used (instead of src1). |
2383 | */ | |
355afbcd KR |
2384 | regop.n <<= 19; |
2385 | if (regop.special) | |
2386 | { | |
2387 | regop.mode = regop.special; | |
2388 | } | |
2389 | regop.mode <<= 13; | |
2390 | regop.special = 0; | |
2391 | } | |
2392 | else | |
2393 | { | |
2394 | /* regop.n goes in bit 0, needs no shifting */ | |
2395 | regop.mode <<= 11; | |
2396 | regop.special <<= 5; | |
fecd2382 | 2397 | } |
355afbcd KR |
2398 | instr |= regop.n | regop.mode | regop.special; |
2399 | } | |
2400 | ||
2401 | if (n_ops >= 2) | |
2402 | { | |
2403 | parse_regop (®op, args[2], oP->operand[1]); | |
2404 | ||
2405 | if ((n_ops == 2) && !(instr & M3)) | |
2406 | { | |
2407 | /* 2-operand instruction in which the dst field should | |
fecd2382 RP |
2408 | * be used instead of src2). |
2409 | */ | |
355afbcd KR |
2410 | regop.n <<= 19; |
2411 | if (regop.special) | |
2412 | { | |
2413 | regop.mode = regop.special; | |
2414 | } | |
2415 | regop.mode <<= 13; | |
2416 | regop.special = 0; | |
fecd2382 | 2417 | } |
355afbcd KR |
2418 | else |
2419 | { | |
2420 | regop.n <<= 14; | |
2421 | regop.mode <<= 12; | |
2422 | regop.special <<= 6; | |
fecd2382 | 2423 | } |
355afbcd KR |
2424 | instr |= regop.n | regop.mode | regop.special; |
2425 | } | |
2426 | if (n_ops == 3) | |
2427 | { | |
2428 | parse_regop (®op, args[3], oP->operand[2]); | |
2429 | if (regop.special) | |
2430 | { | |
2431 | regop.mode = regop.special; | |
2432 | } | |
2433 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); | |
2434 | } | |
2435 | emit (instr); | |
fecd2382 RP |
2436 | } |
2437 | ||
2438 | ||
2439 | /***************************************************************************** | |
2440 | * relax_cobr: | |
2441 | * Replace cobr instruction in a code fragment with equivalent branch and | |
2442 | * compare instructions, so it can reach beyond a 13-bit displacement. | |
2443 | * Set up an address fix/relocation for the new branch instruction. | |
2444 | * | |
2445 | **************************************************************************** */ | |
2446 | ||
2447 | /* This "conditional jump" table maps cobr instructions into equivalent | |
2448 | * compare and branch opcodes. | |
2449 | */ | |
2450 | static | |
355afbcd KR |
2451 | struct |
2452 | { | |
2453 | long compare; | |
2454 | long branch; | |
2455 | } | |
2456 | ||
2457 | coj[] = | |
2458 | { /* COBR OPCODE: */ | |
80aab579 ILT |
2459 | { CHKBIT, BNO }, /* 0x30 - bbc */ |
2460 | { CMPO, BG }, /* 0x31 - cmpobg */ | |
2461 | { CMPO, BE }, /* 0x32 - cmpobe */ | |
2462 | { CMPO, BGE }, /* 0x33 - cmpobge */ | |
2463 | { CMPO, BL }, /* 0x34 - cmpobl */ | |
2464 | { CMPO, BNE }, /* 0x35 - cmpobne */ | |
2465 | { CMPO, BLE }, /* 0x36 - cmpoble */ | |
2466 | { CHKBIT, BO }, /* 0x37 - bbs */ | |
2467 | { CMPI, BNO }, /* 0x38 - cmpibno */ | |
2468 | { CMPI, BG }, /* 0x39 - cmpibg */ | |
2469 | { CMPI, BE }, /* 0x3a - cmpibe */ | |
2470 | { CMPI, BGE }, /* 0x3b - cmpibge */ | |
2471 | { CMPI, BL }, /* 0x3c - cmpibl */ | |
2472 | { CMPI, BNE }, /* 0x3d - cmpibne */ | |
2473 | { CMPI, BLE }, /* 0x3e - cmpible */ | |
2474 | { CMPI, BO }, /* 0x3f - cmpibo */ | |
355afbcd | 2475 | }; |
fecd2382 RP |
2476 | |
2477 | static | |
355afbcd KR |
2478 | void |
2479 | relax_cobr (fragP) | |
2480 | register fragS *fragP; /* fragP->fr_opcode is assumed to point to | |
c47d388b ME |
2481 | * the cobr instruction, which comes at the |
2482 | * end of the code fragment. | |
2483 | */ | |
fecd2382 | 2484 | { |
355afbcd KR |
2485 | int opcode, src1, src2, m1, s2; |
2486 | /* Bit fields from cobr instruction */ | |
2487 | long bp_bits; /* Branch prediction bits from cobr instruction */ | |
2488 | long instr; /* A single i960 instruction */ | |
2489 | char *iP; /*->instruction to be replaced */ | |
2490 | fixS *fixP; /* Relocation that can be done at assembly time */ | |
2491 | ||
2492 | /* PICK UP & PARSE COBR INSTRUCTION */ | |
2493 | iP = fragP->fr_opcode; | |
2494 | instr = md_chars_to_number (iP, 4); | |
2495 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */ | |
2496 | src1 = (instr >> 19) & 0x1f; | |
2497 | m1 = (instr >> 13) & 1; | |
2498 | s2 = instr & 1; | |
2499 | src2 = (instr >> 14) & 0x1f; | |
2500 | bp_bits = instr & BP_MASK; | |
2501 | ||
2502 | /* GENERATE AND OUTPUT COMPARE INSTRUCTION */ | |
2503 | instr = coj[opcode].compare | |
2504 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); | |
2505 | md_number_to_chars (iP, instr, 4); | |
2506 | ||
2507 | /* OUTPUT BRANCH INSTRUCTION */ | |
2508 | md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4); | |
2509 | ||
2510 | /* SET UP ADDRESS FIXUP/RELOCATION */ | |
2511 | fixP = fix_new (fragP, | |
2512 | iP + 4 - fragP->fr_literal, | |
2513 | 4, | |
2514 | fragP->fr_symbol, | |
355afbcd KR |
2515 | fragP->fr_offset, |
2516 | 1, | |
2517 | NO_RELOC); | |
2518 | ||
2519 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */ | |
2520 | ||
2521 | fragP->fr_fix += 4; | |
2522 | frag_wane (fragP); | |
fecd2382 RP |
2523 | } |
2524 | ||
2525 | ||
2526 | /***************************************************************************** | |
2527 | * reloc_callj: Relocate a 'callj' instruction | |
2528 | * | |
2529 | * This is a "non-(GNU)-standard" machine-dependent hook. The base | |
2530 | * assembler calls it when it decides it can relocate an address at | |
2531 | * assembly time instead of emitting a relocation directive. | |
2532 | * | |
2533 | * Check to see if the relocation involves a 'callj' instruction to a: | |
2534 | * sysproc: Replace the default 'call' instruction with a 'calls' | |
2535 | * leafproc: Replace the default 'call' instruction with a 'bal'. | |
2536 | * other proc: Do nothing. | |
2537 | * | |
2538 | * See b.out.h for details on the 'n_other' field in a symbol structure. | |
2539 | * | |
2540 | * IMPORTANT!: | |
2541 | * Assumes the caller has already figured out, in the case of a leafproc, | |
2542 | * to use the 'bal' entry point, and has substituted that symbol into the | |
2543 | * passed fixup structure. | |
2544 | * | |
2545 | **************************************************************************** */ | |
355afbcd KR |
2546 | void |
2547 | reloc_callj (fixP) | |
2548 | fixS *fixP; /* Relocation that can be done at assembly time */ | |
fecd2382 | 2549 | { |
355afbcd KR |
2550 | char *where; /*->the binary for the instruction being relocated */ |
2551 | ||
f3d817d8 | 2552 | if (!fixP->fx_tcbit) |
355afbcd KR |
2553 | { |
2554 | return; | |
2555 | } /* This wasn't a callj instruction in the first place */ | |
2556 | ||
2557 | where = fixP->fx_frag->fr_literal + fixP->fx_where; | |
2558 | ||
2559 | if (TC_S_IS_SYSPROC (fixP->fx_addsy)) | |
2560 | { | |
2561 | /* Symbol is a .sysproc: replace 'call' with 'calls'. | |
fecd2382 RP |
2562 | * System procedure number is (other-1). |
2563 | */ | |
355afbcd KR |
2564 | md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4); |
2565 | ||
2566 | /* Nothing else needs to be done for this instruction. | |
fecd2382 RP |
2567 | * Make sure 'md_number_to_field()' will perform a no-op. |
2568 | */ | |
355afbcd KR |
2569 | fixP->fx_bit_fixP = (bit_fixS *) 1; |
2570 | ||
2571 | } | |
2572 | else if (TC_S_IS_CALLNAME (fixP->fx_addsy)) | |
2573 | { | |
2574 | /* Should not happen: see block comment above */ | |
2575 | as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy)); | |
2576 | ||
2577 | } | |
2578 | else if (TC_S_IS_BALNAME (fixP->fx_addsy)) | |
2579 | { | |
2580 | /* Replace 'call' with 'bal'; both instructions have | |
fecd2382 RP |
2581 | * the same format, so calling code should complete |
2582 | * relocation as if nothing happened here. | |
2583 | */ | |
355afbcd KR |
2584 | md_number_to_chars (where, BAL, 4); |
2585 | } | |
2586 | else if (TC_S_IS_BADPROC (fixP->fx_addsy)) | |
2587 | { | |
2588 | as_bad ("Looks like a proc, but can't tell what kind.\n"); | |
2589 | } /* switch on proc type */ | |
2590 | ||
2591 | /* else Symbol is neither a sysproc nor a leafproc */ | |
f3d817d8 | 2592 | } |
fecd2382 RP |
2593 | |
2594 | ||
2595 | /***************************************************************************** | |
2596 | * s_leafproc: process .leafproc pseudo-op | |
2597 | * | |
2598 | * .leafproc takes two arguments, the second one is optional: | |
2599 | * arg[1]: name of 'call' entry point to leaf procedure | |
2600 | * arg[2]: name of 'bal' entry point to leaf procedure | |
2601 | * | |
2602 | * If the two arguments are identical, or if the second one is missing, | |
2603 | * the first argument is taken to be the 'bal' entry point. | |
2604 | * | |
2605 | * If there are 2 distinct arguments, we must make sure that the 'bal' | |
2606 | * entry point immediately follows the 'call' entry point in the linked | |
2607 | * list of symbols. | |
2608 | * | |
2609 | **************************************************************************** */ | |
355afbcd KR |
2610 | static void |
2611 | s_leafproc (n_ops, args) | |
2612 | int n_ops; /* Number of operands */ | |
2613 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
fecd2382 | 2614 | { |
355afbcd KR |
2615 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */ |
2616 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */ | |
2617 | ||
2618 | if ((n_ops != 1) && (n_ops != 2)) | |
2619 | { | |
2620 | as_bad ("should have 1 or 2 operands"); | |
2621 | return; | |
2622 | } /* Check number of arguments */ | |
2623 | ||
2624 | /* Find or create symbol for 'call' entry point. */ | |
2625 | callP = symbol_find_or_make (args[1]); | |
2626 | ||
2627 | if (TC_S_IS_CALLNAME (callP)) | |
2628 | { | |
2629 | as_warn ("Redefining leafproc %s", S_GET_NAME (callP)); | |
2630 | } /* is leafproc */ | |
2631 | ||
2632 | /* If that was the only argument, use it as the 'bal' entry point. | |
fecd2382 RP |
2633 | * Otherwise, mark it as the 'call' entry point and find or create |
2634 | * another symbol for the 'bal' entry point. | |
2635 | */ | |
355afbcd KR |
2636 | if ((n_ops == 1) || !strcmp (args[1], args[2])) |
2637 | { | |
2638 | TC_S_FORCE_TO_BALNAME (callP); | |
2639 | ||
2640 | } | |
2641 | else | |
2642 | { | |
2643 | TC_S_FORCE_TO_CALLNAME (callP); | |
2644 | ||
2645 | balP = symbol_find_or_make (args[2]); | |
2646 | if (TC_S_IS_CALLNAME (balP)) | |
2647 | { | |
2648 | as_warn ("Redefining leafproc %s", S_GET_NAME (balP)); | |
2649 | } | |
2650 | TC_S_FORCE_TO_BALNAME (balP); | |
2651 | ||
2652 | tc_set_bal_of_call (callP, balP); | |
2653 | } /* if only one arg, or the args are the same */ | |
f3d817d8 | 2654 | } |
fecd2382 RP |
2655 | |
2656 | ||
2657 | /* | |
2658 | * s_sysproc: process .sysproc pseudo-op | |
2659 | * | |
2660 | * .sysproc takes two arguments: | |
2661 | * arg[1]: name of entry point to system procedure | |
2662 | * arg[2]: 'entry_num' (index) of system procedure in the range | |
2663 | * [0,31] inclusive. | |
2664 | * | |
2665 | * For [ab].out, we store the 'entrynum' in the 'n_other' field of | |
2666 | * the symbol. Since that entry is normally 0, we bias 'entrynum' | |
2667 | * by adding 1 to it. It must be unbiased before it is used. | |
2668 | */ | |
355afbcd KR |
2669 | static void |
2670 | s_sysproc (n_ops, args) | |
2671 | int n_ops; /* Number of operands */ | |
2672 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
fecd2382 | 2673 | { |
355afbcd KR |
2674 | expressionS exp; |
2675 | symbolS *symP; | |
2676 | ||
2677 | if (n_ops != 2) | |
2678 | { | |
2679 | as_bad ("should have two operands"); | |
2680 | return; | |
2681 | } /* bad arg count */ | |
2682 | ||
2683 | /* Parse "entry_num" argument and check it for validity. */ | |
5ac34ac3 ILT |
2684 | parse_expr (args[2], &exp); |
2685 | if (exp.X_op != O_constant | |
355afbcd KR |
2686 | || (offs (exp) < 0) |
2687 | || (offs (exp) > 31)) | |
2688 | { | |
2689 | as_bad ("'entry_num' must be absolute number in [0,31]"); | |
2690 | return; | |
2691 | } | |
2692 | ||
2693 | /* Find/make symbol and stick entry number (biased by +1) into it */ | |
2694 | symP = symbol_find_or_make (args[1]); | |
2695 | ||
2696 | if (TC_S_IS_SYSPROC (symP)) | |
2697 | { | |
2698 | as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP)); | |
2699 | } /* redefining */ | |
2700 | ||
2701 | TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */ | |
2702 | TC_S_FORCE_TO_SYSPROC (symP); | |
f3d817d8 | 2703 | } |
fecd2382 RP |
2704 | |
2705 | ||
2706 | /***************************************************************************** | |
2707 | * shift_ok: | |
2708 | * Determine if a "shlo" instruction can be used to implement a "ldconst". | |
2709 | * This means that some number X < 32 can be shifted left to produce the | |
2710 | * constant of interest. | |
2711 | * | |
2712 | * Return the shift count, or 0 if we can't do it. | |
2713 | * Caller calculates X by shifting original constant right 'shift' places. | |
2714 | * | |
2715 | **************************************************************************** */ | |
2716 | static | |
355afbcd KR |
2717 | int |
2718 | shift_ok (n) | |
2719 | int n; /* The constant of interest */ | |
fecd2382 | 2720 | { |
355afbcd KR |
2721 | int shift; /* The shift count */ |
2722 | ||
2723 | if (n <= 0) | |
2724 | { | |
2725 | /* Can't do it for negative numbers */ | |
2726 | return 0; | |
2727 | } | |
2728 | ||
2729 | /* Shift 'n' right until a 1 is about to be lost */ | |
2730 | for (shift = 0; (n & 1) == 0; shift++) | |
2731 | { | |
2732 | n >>= 1; | |
2733 | } | |
2734 | ||
2735 | if (n >= 32) | |
2736 | { | |
2737 | return 0; | |
2738 | } | |
2739 | return shift; | |
fecd2382 RP |
2740 | } |
2741 | ||
2742 | ||
2743 | /***************************************************************************** | |
2744 | * syntax: issue syntax error | |
2745 | * | |
2746 | **************************************************************************** */ | |
355afbcd KR |
2747 | static void |
2748 | syntax () | |
2749 | { | |
2750 | as_bad ("syntax error"); | |
2751 | } /* syntax() */ | |
fecd2382 RP |
2752 | |
2753 | ||
2754 | /***************************************************************************** | |
2755 | * targ_has_sfr: | |
2756 | * Return TRUE iff the target architecture supports the specified | |
2757 | * special-function register (sfr). | |
2758 | * | |
f3d817d8 | 2759 | *****************************************************************************/ |
fecd2382 | 2760 | static |
355afbcd KR |
2761 | int |
2762 | targ_has_sfr (n) | |
2763 | int n; /* Number (0-31) of sfr */ | |
fecd2382 | 2764 | { |
355afbcd KR |
2765 | switch (architecture) |
2766 | { | |
2767 | case ARCH_KA: | |
2768 | case ARCH_KB: | |
2769 | case ARCH_MC: | |
2770 | return 0; | |
2771 | case ARCH_CA: | |
2772 | default: | |
2773 | return ((0 <= n) && (n <= 2)); | |
2774 | } | |
fecd2382 RP |
2775 | } |
2776 | ||
2777 | ||
2778 | /***************************************************************************** | |
2779 | * targ_has_iclass: | |
2780 | * Return TRUE iff the target architecture supports the indicated | |
2781 | * class of instructions. | |
2782 | * | |
f3d817d8 | 2783 | *****************************************************************************/ |
fecd2382 | 2784 | static |
355afbcd KR |
2785 | int |
2786 | targ_has_iclass (ic) | |
2787 | int ic; /* Instruction class; one of: | |
a39116f1 RP |
2788 | * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM |
2789 | */ | |
fecd2382 | 2790 | { |
355afbcd KR |
2791 | iclasses_seen |= ic; |
2792 | switch (architecture) | |
2793 | { | |
2794 | case ARCH_KA: | |
2795 | return ic & (I_BASE | I_KX); | |
2796 | case ARCH_KB: | |
2797 | return ic & (I_BASE | I_KX | I_FP | I_DEC); | |
2798 | case ARCH_MC: | |
2799 | return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); | |
2800 | case ARCH_CA: | |
2801 | return ic & (I_BASE | I_CX | I_CASIM); | |
2802 | default: | |
2803 | if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL)) | |
2804 | && (iclasses_seen & I_CX)) | |
2805 | { | |
2806 | as_warn ("architecture of opcode conflicts with that of earlier instruction(s)"); | |
2807 | iclasses_seen &= ~ic; | |
fecd2382 | 2808 | } |
355afbcd KR |
2809 | return 1; |
2810 | } | |
fecd2382 RP |
2811 | } |
2812 | ||
2813 | ||
2814 | /* Parse an operand that is machine-specific. | |
2815 | We just return without modifying the expression if we have nothing | |
2816 | to do. */ | |
2817 | ||
2818 | /* ARGSUSED */ | |
2819 | void | |
355afbcd KR |
2820 | md_operand (expressionP) |
2821 | expressionS *expressionP; | |
fecd2382 RP |
2822 | { |
2823 | } | |
2824 | ||
2825 | /* We have no need to default values of symbols. */ | |
2826 | ||
2827 | /* ARGSUSED */ | |
355afbcd KR |
2828 | symbolS * |
2829 | md_undefined_symbol (name) | |
2830 | char *name; | |
fecd2382 | 2831 | { |
355afbcd | 2832 | return 0; |
f3d817d8 | 2833 | } |
fecd2382 RP |
2834 | |
2835 | /* Exactly what point is a PC-relative offset relative TO? | |
2836 | On the i960, they're relative to the address of the instruction, | |
2837 | which we have set up as the address of the fixup too. */ | |
2838 | long | |
355afbcd KR |
2839 | md_pcrel_from (fixP) |
2840 | fixS *fixP; | |
fecd2382 | 2841 | { |
355afbcd | 2842 | return fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
2843 | } |
2844 | ||
2845 | void | |
355afbcd KR |
2846 | md_apply_fix (fixP, val) |
2847 | fixS *fixP; | |
2848 | long val; | |
fecd2382 | 2849 | { |
355afbcd KR |
2850 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; |
2851 | ||
2852 | if (!fixP->fx_bit_fixP) | |
f3d817d8 DM |
2853 | switch (fixP->fx_im_disp) |
2854 | { | |
2855 | case 0: | |
2856 | /* For callx, we always want to write out zero, and emit a | |
2857 | symbolic relocation. */ | |
2858 | if (fixP->fx_bsr) | |
2859 | val = 0; | |
2860 | ||
2861 | fixP->fx_addnumber = val; | |
2862 | md_number_to_imm (place, val, fixP->fx_size, fixP); | |
2863 | break; | |
2864 | case 1: | |
2865 | md_number_to_disp (place, | |
2866 | (fixP->fx_pcrel | |
2867 | ? val + fixP->fx_pcrel_adjust | |
2868 | : val), | |
2869 | fixP->fx_size); | |
2870 | break; | |
2871 | case 2: /* fix requested for .long .word etc */ | |
2872 | md_number_to_chars (place, val, fixP->fx_size); | |
2873 | break; | |
2874 | default: | |
2875 | as_fatal ("Internal error in md_apply_fix() in file \"%s\"", | |
2876 | __FILE__); | |
2877 | } | |
355afbcd | 2878 | else |
f3d817d8 DM |
2879 | md_number_to_field (place, val, fixP->fx_bit_fixP); |
2880 | } | |
fecd2382 RP |
2881 | |
2882 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
355afbcd KR |
2883 | void |
2884 | tc_bout_fix_to_chars (where, fixP, segment_address_in_file) | |
2885 | char *where; | |
2886 | fixS *fixP; | |
2887 | relax_addressT segment_address_in_file; | |
fecd2382 | 2888 | { |
f3d817d8 | 2889 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
355afbcd KR |
2890 | struct relocation_info ri; |
2891 | symbolS *symbolP; | |
2892 | ||
355afbcd KR |
2893 | memset ((char *) &ri, '\0', sizeof (ri)); |
2894 | symbolP = fixP->fx_addsy; | |
2895 | know (symbolP != 0 || fixP->fx_r_type != NO_RELOC); | |
2896 | ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ | |
2897 | /* These two 'cuz of NS32K */ | |
f3d817d8 | 2898 | ri.r_callj = fixP->fx_tcbit; |
355afbcd | 2899 | if (fixP->fx_bit_fixP) |
f3d817d8 | 2900 | ri.r_length = 2; |
355afbcd | 2901 | else |
f3d817d8 | 2902 | ri.r_length = nbytes_r_length[fixP->fx_size]; |
355afbcd KR |
2903 | ri.r_pcrel = fixP->fx_pcrel; |
2904 | ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; | |
2905 | ||
2906 | if (fixP->fx_r_type != NO_RELOC) | |
2907 | { | |
2908 | switch (fixP->fx_r_type) | |
2909 | { | |
2910 | case rs_align: | |
2911 | ri.r_index = -2; | |
2912 | ri.r_pcrel = 1; | |
2913 | ri.r_length = fixP->fx_size - 1; | |
2914 | break; | |
2915 | case rs_org: | |
2916 | ri.r_index = -2; | |
2917 | ri.r_pcrel = 0; | |
2918 | break; | |
2919 | case rs_fill: | |
2920 | ri.r_index = -1; | |
2921 | break; | |
2922 | default: | |
2923 | abort (); | |
fecd2382 | 2924 | } |
355afbcd KR |
2925 | ri.r_extern = 0; |
2926 | } | |
f3d817d8 | 2927 | else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr) |
355afbcd KR |
2928 | { |
2929 | ri.r_extern = 1; | |
2930 | ri.r_index = symbolP->sy_number; | |
2931 | } | |
2932 | else | |
2933 | { | |
2934 | ri.r_extern = 0; | |
2935 | ri.r_index = S_GET_TYPE (symbolP); | |
2936 | } | |
2937 | ||
2938 | /* Output the relocation information in machine-dependent form. */ | |
2939 | md_ri_to_chars (where, &ri); | |
f3d817d8 | 2940 | } |
fecd2382 | 2941 | |
fecd2382 RP |
2942 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
2943 | ||
f3d817d8 DM |
2944 | #if defined (OBJ_COFF) && defined (BFD) |
2945 | short | |
2946 | tc_coff_fix2rtype (fixP) | |
2947 | fixS *fixP; | |
2948 | { | |
2949 | if (fixP->fx_bsr) | |
2950 | abort (); | |
2951 | ||
2952 | if (fixP->fx_pcrel == 0 && fixP->fx_size == 4) | |
2953 | return R_RELLONG; | |
2954 | ||
2955 | if (fixP->fx_pcrel != 0 && fixP->fx_size == 4) | |
2956 | return R_IPRMED; | |
2957 | ||
2958 | abort (); | |
2959 | } | |
2960 | ||
2961 | int | |
2962 | tc_coff_sizemachdep (frag) | |
2963 | fragS *frag; | |
2964 | { | |
2965 | if (frag->fr_next) | |
2966 | return frag->fr_next->fr_address - frag->fr_address; | |
2967 | else | |
2968 | return 0; | |
2969 | } | |
2970 | #endif | |
2971 | ||
2972 | /* Align an address by rounding it up to the specified boundary. */ | |
c47d388b | 2973 | valueT |
355afbcd KR |
2974 | md_section_align (seg, addr) |
2975 | segT seg; | |
c47d388b | 2976 | valueT addr; /* Address to be rounded up */ |
fecd2382 | 2977 | { |
355afbcd KR |
2978 | return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg])); |
2979 | } /* md_section_align() */ | |
fecd2382 RP |
2980 | |
2981 | #ifdef OBJ_COFF | |
355afbcd KR |
2982 | void |
2983 | tc_headers_hook (headers) | |
2984 | object_headers *headers; | |
fecd2382 | 2985 | { |
355afbcd KR |
2986 | if (iclasses_seen == I_BASE) |
2987 | { | |
2988 | headers->filehdr.f_flags |= F_I960CORE; | |
2989 | } | |
2990 | else if (iclasses_seen & I_CX) | |
2991 | { | |
2992 | headers->filehdr.f_flags |= F_I960CA; | |
2993 | } | |
2994 | else if (iclasses_seen & I_MIL) | |
2995 | { | |
2996 | headers->filehdr.f_flags |= F_I960MC; | |
2997 | } | |
2998 | else if (iclasses_seen & (I_DEC | I_FP)) | |
2999 | { | |
3000 | headers->filehdr.f_flags |= F_I960KB; | |
3001 | } | |
3002 | else | |
3003 | { | |
3004 | headers->filehdr.f_flags |= F_I960KA; | |
3005 | } /* set arch flag */ | |
3006 | ||
3007 | if (flagseen['R']) | |
3008 | { | |
3009 | headers->filehdr.f_magic = I960RWMAGIC; | |
3010 | headers->aouthdr.magic = OMAGIC; | |
3011 | } | |
3012 | else | |
3013 | { | |
3014 | headers->filehdr.f_magic = I960ROMAGIC; | |
3015 | headers->aouthdr.magic = NMAGIC; | |
3016 | } /* set magic numbers */ | |
f3d817d8 | 3017 | } |
355afbcd | 3018 | |
fecd2382 RP |
3019 | #endif /* OBJ_COFF */ |
3020 | ||
3021 | /* | |
3022 | * Things going on here: | |
3023 | * | |
3024 | * For bout, We need to assure a couple of simplifying | |
3025 | * assumptions about leafprocs for the linker: the leafproc | |
3026 | * entry symbols will be defined in the same assembly in | |
3027 | * which they're declared with the '.leafproc' directive; | |
3028 | * and if a leafproc has both 'call' and 'bal' entry points | |
3029 | * they are both global or both local. | |
3030 | * | |
3031 | * For coff, the call symbol has a second aux entry that | |
3032 | * contains the bal entry point. The bal symbol becomes a | |
3033 | * label. | |
3034 | * | |
3035 | * For coff representation, the call symbol has a second aux entry that | |
3036 | * contains the bal entry point. The bal symbol becomes a label. | |
3037 | * | |
3038 | */ | |
3039 | ||
355afbcd KR |
3040 | void |
3041 | tc_crawl_symbol_chain (headers) | |
3042 | object_headers *headers; | |
fecd2382 | 3043 | { |
355afbcd KR |
3044 | symbolS *symbolP; |
3045 | ||
3046 | for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP)) | |
3047 | { | |
fecd2382 | 3048 | #ifdef OBJ_COFF |
355afbcd KR |
3049 | if (TC_S_IS_SYSPROC (symbolP)) |
3050 | { | |
3051 | /* second aux entry already contains the sysproc number */ | |
3052 | S_SET_NUMBER_AUXILIARY (symbolP, 2); | |
3053 | S_SET_STORAGE_CLASS (symbolP, C_SCALL); | |
3054 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
3055 | continue; | |
3056 | } /* rewrite sysproc */ | |
fecd2382 | 3057 | #endif /* OBJ_COFF */ |
355afbcd KR |
3058 | |
3059 | if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP)) | |
3060 | { | |
3061 | continue; | |
3062 | } /* Not a leafproc symbol */ | |
3063 | ||
3064 | if (!S_IS_DEFINED (symbolP)) | |
3065 | { | |
3066 | as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP)); | |
3067 | } /* undefined leaf */ | |
3068 | ||
3069 | if (TC_S_IS_CALLNAME (symbolP)) | |
3070 | { | |
3071 | symbolS *balP = tc_get_bal_of_call (symbolP); | |
3072 | if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP)) | |
3073 | { | |
3074 | S_SET_EXTERNAL (symbolP); | |
3075 | S_SET_EXTERNAL (balP); | |
3076 | as_warn ("Warning: making leafproc entries %s and %s both global\n", | |
3077 | S_GET_NAME (symbolP), S_GET_NAME (balP)); | |
3078 | } /* externality mismatch */ | |
3079 | } /* if callname */ | |
3080 | } /* walk the symbol chain */ | |
f3d817d8 | 3081 | } |
fecd2382 RP |
3082 | |
3083 | /* | |
3084 | * For aout or bout, the bal immediately follows the call. | |
3085 | * | |
3086 | * For coff, we cheat and store a pointer to the bal symbol | |
3087 | * in the second aux entry of the call. | |
3088 | */ | |
3089 | ||
355afbcd KR |
3090 | #undef OBJ_ABOUT |
3091 | #ifdef OBJ_AOUT | |
3092 | #define OBJ_ABOUT | |
3093 | #endif | |
3094 | #ifdef OBJ_BOUT | |
3095 | #define OBJ_ABOUT | |
3096 | #endif | |
3097 | ||
3098 | void | |
3099 | tc_set_bal_of_call (callP, balP) | |
3100 | symbolS *callP; | |
3101 | symbolS *balP; | |
fecd2382 | 3102 | { |
355afbcd KR |
3103 | know (TC_S_IS_CALLNAME (callP)); |
3104 | know (TC_S_IS_BALNAME (balP)); | |
3105 | ||
fecd2382 | 3106 | #ifdef OBJ_COFF |
355afbcd KR |
3107 | |
3108 | callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP; | |
3109 | S_SET_NUMBER_AUXILIARY (callP, 2); | |
3110 | ||
3111 | #else /* ! OBJ_COFF */ | |
3112 | #ifdef OBJ_ABOUT | |
3113 | ||
3114 | /* If the 'bal' entry doesn't immediately follow the 'call' | |
fecd2382 RP |
3115 | * symbol, unlink it from the symbol list and re-insert it. |
3116 | */ | |
355afbcd KR |
3117 | if (symbol_next (callP) != balP) |
3118 | { | |
3119 | symbol_remove (balP, &symbol_rootP, &symbol_lastP); | |
3120 | symbol_append (balP, callP, &symbol_rootP, &symbol_lastP); | |
3121 | } /* if not in order */ | |
3122 | ||
3123 | #else /* ! OBJ_ABOUT */ | |
3124 | (as yet unwritten.); | |
3125 | #endif /* ! OBJ_ABOUT */ | |
3126 | #endif /* ! OBJ_COFF */ | |
f3d817d8 | 3127 | } |
355afbcd KR |
3128 | |
3129 | char * | |
3130 | _tc_get_bal_of_call (callP) | |
3131 | symbolS *callP; | |
fecd2382 | 3132 | { |
355afbcd KR |
3133 | symbolS *retval; |
3134 | ||
3135 | know (TC_S_IS_CALLNAME (callP)); | |
3136 | ||
fecd2382 | 3137 | #ifdef OBJ_COFF |
355afbcd | 3138 | retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry); |
fecd2382 | 3139 | #else |
355afbcd KR |
3140 | #ifdef OBJ_ABOUT |
3141 | retval = symbol_next (callP); | |
3142 | #else | |
3143 | (as yet unwritten.); | |
3144 | #endif /* ! OBJ_ABOUT */ | |
3145 | #endif /* ! OBJ_COFF */ | |
3146 | ||
3147 | know (TC_S_IS_BALNAME (retval)); | |
3148 | return ((char *) retval); | |
3149 | } /* _tc_get_bal_of_call() */ | |
3150 | ||
3151 | void | |
3152 | tc_coff_symbol_emit_hook (symbolP) | |
3153 | symbolS *symbolP; | |
fecd2382 | 3154 | { |
355afbcd KR |
3155 | if (TC_S_IS_CALLNAME (symbolP)) |
3156 | { | |
fecd2382 | 3157 | #ifdef OBJ_COFF |
355afbcd KR |
3158 | symbolS *balP = tc_get_bal_of_call (symbolP); |
3159 | ||
3160 | /* second aux entry contains the bal entry point */ | |
3161 | /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */ | |
3162 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP); | |
3163 | S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT)); | |
3164 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
3165 | /* fix up the bal symbol */ | |
3166 | S_SET_STORAGE_CLASS (balP, C_LABEL); | |
fecd2382 | 3167 | #endif /* OBJ_COFF */ |
355afbcd | 3168 | } /* only on calls */ |
f3d817d8 | 3169 | } |
fecd2382 | 3170 | |
09952cd9 KR |
3171 | void |
3172 | i960_handle_align (fragp) | |
3173 | fragS *fragp; | |
3174 | { | |
3175 | fixS *fixp; | |
09952cd9 KR |
3176 | |
3177 | if (!linkrelax) | |
3178 | return; | |
3179 | ||
f3d817d8 DM |
3180 | #ifndef OBJ_BOUT |
3181 | ||
3182 | as_bad ("option --link-relax is only supported in b.out format"); | |
3183 | linkrelax = 0; | |
3184 | return; | |
3185 | ||
3186 | #else | |
3187 | ||
09952cd9 KR |
3188 | /* The text section "ends" with another alignment reloc, to which we |
3189 | aren't adding padding. */ | |
3190 | if (fragp->fr_next == text_last_frag | |
3191 | || fragp->fr_next == data_last_frag) | |
f3d817d8 | 3192 | return; |
09952cd9 KR |
3193 | |
3194 | /* alignment directive */ | |
5ac34ac3 | 3195 | fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, |
09952cd9 | 3196 | (int) fragp->fr_type); |
f3d817d8 DM |
3197 | #endif /* OBJ_BOUT */ |
3198 | } | |
3199 | ||
3200 | int | |
3201 | i960_validate_fix (fixP, this_segment_type, add_symbolPP) | |
3202 | fixS *fixP; | |
3203 | segT this_segment_type; | |
3204 | symbolS **add_symbolPP; | |
3205 | { | |
3206 | #define add_symbolP (*add_symbolPP) | |
3207 | if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP)) | |
3208 | { | |
3209 | /* Relocation should be done via the associated 'bal' | |
3210 | entry point symbol. */ | |
3211 | ||
3212 | if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP))) | |
3213 | { | |
3214 | as_bad ("No 'bal' entry point for leafproc %s", | |
3215 | S_GET_NAME (add_symbolP)); | |
3216 | return 1; | |
3217 | } | |
3218 | fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP); | |
3219 | } | |
3220 | #if 0 | |
3221 | /* Still have to work out other conditions for these tests. */ | |
3222 | { | |
3223 | if (fixP->fx_tcbit) | |
3224 | { | |
3225 | as_bad ("callj to difference of two symbols"); | |
3226 | return 1; | |
3227 | } | |
3228 | reloc_callj (fixP); | |
3229 | if ((int) fixP->fx_bit_fixP == 13) | |
3230 | { | |
3231 | /* This is a COBR instruction. They have only a 13-bit | |
3232 | displacement and are only to be used for local branches: | |
3233 | flag as error, don't generate relocation. */ | |
3234 | as_bad ("can't use COBR format with external label"); | |
3235 | fixP->fx_addsy = NULL; /* No relocations please. */ | |
3236 | return 1; | |
3237 | } | |
3238 | } | |
3239 | #endif | |
3240 | #undef add_symbolP | |
3241 | return 0; | |
09952cd9 KR |
3242 | } |
3243 | ||
8b228fe9 | 3244 | /* end of tc-i960.c */ |