Commit | Line | Data |
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252b5132 | 1 | /* tc-i960.c - All the i80960-specific stuff |
f7e42eb4 | 2 | Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
2132e3a3 | 3 | 1999, 2000, 2001, 2002, 2003, 2005 |
252b5132 RH |
4 | Free Software Foundation, Inc. |
5 | ||
6 | This file is part of GAS. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
92774660 | 23 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
252b5132 RH |
24 | |
25 | /* There are 4 different lengths of (potentially) symbol-based displacements | |
26 | in the 80960 instruction set, each of which could require address fix-ups | |
27 | and (in the case of external symbols) emission of relocation directives: | |
28 | ||
29 | 32-bit (MEMB) | |
30 | This is a standard length for the base assembler and requires no | |
31 | special action. | |
32 | ||
33 | 13-bit (COBR) | |
34 | This is a non-standard length, but the base assembler has a | |
35 | hook for bit field address fixups: the fixS structure can | |
36 | point to a descriptor of the field, in which case our | |
37 | md_number_to_field() routine gets called to process it. | |
38 | ||
39 | I made the hook a little cleaner by having fix_new() (in the base | |
40 | assembler) return a pointer to the fixS in question. And I made it a | |
41 | little simpler by storing the field size (in this case 13) instead of | |
42 | of a pointer to another structure: 80960 displacements are ALWAYS | |
43 | stored in the low-order bits of a 4-byte word. | |
44 | ||
45 | Since the target of a COBR cannot be external, no relocation | |
46 | directives for this size displacement have to be generated. | |
47 | But the base assembler had to be modified to issue error | |
48 | messages if the symbol did turn out to be external. | |
49 | ||
50 | 24-bit (CTRL) | |
51 | Fixups are handled as for the 13-bit case (except that 24 is stored | |
52 | in the fixS). | |
53 | ||
54 | The relocation directive generated is the same as that for the 32-bit | |
55 | displacement, except that it's PC-relative (the 32-bit displacement | |
56 | never is). The i80960 version of the linker needs a mod to | |
57 | distinguish and handle the 24-bit case. | |
58 | ||
59 | 12-bit (MEMA) | |
60 | MEMA formats are always promoted to MEMB (32-bit) if the displacement | |
61 | is based on a symbol, because it could be relocated at link time. | |
62 | The only time we use the 12-bit format is if an absolute value of | |
63 | less than 4096 is specified, in which case we need neither a fixup nor | |
64 | a relocation directive. */ | |
65 | ||
66 | #include <stdio.h> | |
252b5132 RH |
67 | |
68 | #include "as.h" | |
69 | ||
3882b010 | 70 | #include "safe-ctype.h" |
252b5132 RH |
71 | #include "obstack.h" |
72 | ||
73 | #include "opcode/i960.h" | |
74 | ||
75 | #if defined (OBJ_AOUT) || defined (OBJ_BOUT) | |
76 | ||
ea1562b3 NC |
77 | #define TC_S_IS_SYSPROC(s) ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32)) |
78 | #define TC_S_IS_BALNAME(s) (S_GET_OTHER (s) == N_BALNAME) | |
79 | #define TC_S_IS_CALLNAME(s) (S_GET_OTHER (s) == N_CALLNAME) | |
80 | #define TC_S_IS_BADPROC(s) ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s)) | |
252b5132 | 81 | |
ea1562b3 NC |
82 | #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER ((s), (p) + 1)) |
83 | #define TC_S_GET_SYSPROC(s) (S_GET_OTHER (s) - 1) | |
252b5132 | 84 | |
ea1562b3 NC |
85 | #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER ((s), N_BALNAME)) |
86 | #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER ((s), N_CALLNAME)) | |
252b5132 RH |
87 | #define TC_S_FORCE_TO_SYSPROC(s) {;} |
88 | ||
89 | #else /* ! OBJ_A/BOUT */ | |
90 | #ifdef OBJ_COFF | |
91 | ||
ea1562b3 NC |
92 | #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS (s) == C_SCALL) |
93 | #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME (s)) | |
94 | #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME (s)) | |
95 | #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s)) | |
252b5132 RH |
96 | |
97 | #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p)) | |
98 | #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx) | |
99 | ||
ea1562b3 NC |
100 | #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME (s)) |
101 | #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME (s)) | |
102 | #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS ((s), C_SCALL)) | |
252b5132 RH |
103 | |
104 | #else /* ! OBJ_COFF */ | |
bedf545c ILT |
105 | #ifdef OBJ_ELF |
106 | #define TC_S_IS_SYSPROC(s) 0 | |
107 | ||
108 | #define TC_S_IS_BALNAME(s) 0 | |
109 | #define TC_S_IS_CALLNAME(s) 0 | |
110 | #define TC_S_IS_BADPROC(s) 0 | |
111 | ||
112 | #define TC_S_SET_SYSPROC(s, p) | |
ea1562b3 | 113 | #define TC_S_GET_SYSPROC(s) 0 |
bedf545c ILT |
114 | |
115 | #define TC_S_FORCE_TO_BALNAME(s) | |
116 | #define TC_S_FORCE_TO_CALLNAME(s) | |
117 | #define TC_S_FORCE_TO_SYSPROC(s) | |
118 | #else | |
119 | #error COFF, a.out, b.out, and ELF are the only supported formats. | |
120 | #endif /* ! OBJ_ELF */ | |
252b5132 RH |
121 | #endif /* ! OBJ_COFF */ |
122 | #endif /* ! OBJ_A/BOUT */ | |
123 | ||
124 | extern char *input_line_pointer; | |
125 | ||
126 | #if !defined (BFD_ASSEMBLER) && !defined (BFD) | |
127 | #ifdef OBJ_COFF | |
128 | const int md_reloc_size = sizeof (struct reloc); | |
129 | #else /* OBJ_COFF */ | |
130 | const int md_reloc_size = sizeof (struct relocation_info); | |
131 | #endif /* OBJ_COFF */ | |
132 | #endif | |
133 | ||
134 | /* Local i80960 routines. */ | |
b9195351 AM |
135 | struct memS; |
136 | struct regop; | |
137 | ||
ea1562b3 NC |
138 | /* See md_parse_option() for meanings of these options. */ |
139 | static char norelax; /* True if -norelax switch seen. */ | |
140 | static char instrument_branches; /* True if -b switch seen. */ | |
252b5132 RH |
141 | |
142 | /* Characters that always start a comment. | |
ea1562b3 | 143 | If the pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
144 | const char comment_chars[] = "#"; |
145 | ||
146 | /* Characters that only start a comment at the beginning of | |
147 | a line. If the line seems to have the form '# 123 filename' | |
148 | .line and .file directives will appear in the pre-processed output. | |
149 | ||
150 | Note that input_file.c hand checks for '#' at the beginning of the | |
151 | first line of the input file. This is because the compiler outputs | |
ea1562b3 | 152 | #NO_APP at the beginning of its output. */ |
252b5132 | 153 | |
92774660 | 154 | /* Also note that comments started like this one will always work. */ |
252b5132 | 155 | |
ea1562b3 | 156 | const char line_comment_chars[] = "#"; |
63a0b638 | 157 | const char line_separator_chars[] = ";"; |
252b5132 | 158 | |
ea1562b3 | 159 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
252b5132 RH |
160 | const char EXP_CHARS[] = "eE"; |
161 | ||
162 | /* Chars that mean this number is a floating point constant, | |
ea1562b3 | 163 | as in 0f12.456 or 0d1.2345e12. */ |
252b5132 RH |
164 | const char FLT_CHARS[] = "fFdDtT"; |
165 | ||
252b5132 RH |
166 | /* Table used by base assembler to relax addresses based on varying length |
167 | instructions. The fields are: | |
168 | 1) most positive reach of this state, | |
169 | 2) most negative reach of this state, | |
170 | 3) how many bytes this mode will add to the size of the current frag | |
171 | 4) which index into the table to try if we can't fit into this one. | |
172 | ||
173 | For i80960, the only application is the (de-)optimization of cobr | |
174 | instructions into separate compare and branch instructions when a 13-bit | |
ea1562b3 | 175 | displacement won't hack it. */ |
252b5132 RH |
176 | const relax_typeS md_relax_table[] = |
177 | { | |
ea1562b3 NC |
178 | {0, 0, 0, 0}, /* State 0 => no more relaxation possible. */ |
179 | {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr). */ | |
180 | {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl). */ | |
252b5132 RH |
181 | }; |
182 | ||
252b5132 RH |
183 | /* These are the machine dependent pseudo-ops. |
184 | ||
185 | This table describes all the machine specific pseudo-ops the assembler | |
186 | has to support. The fields are: | |
187 | pseudo-op name without dot | |
188 | function to call to execute this pseudo-op | |
ea1562b3 | 189 | integer arg to pass to the function. */ |
252b5132 RH |
190 | #define S_LEAFPROC 1 |
191 | #define S_SYSPROC 2 | |
192 | ||
ea1562b3 | 193 | /* Macros to extract info from an 'expressionS' structure 'e'. */ |
252b5132 RH |
194 | #define adds(e) e.X_add_symbol |
195 | #define offs(e) e.X_add_number | |
196 | ||
ea1562b3 NC |
197 | /* Branch-prediction bits for CTRL/COBR format opcodes. */ |
198 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit. */ | |
199 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch. */ | |
200 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch. */ | |
252b5132 | 201 | |
ea1562b3 | 202 | /* Some instruction opcodes that we need explicitly. */ |
252b5132 RH |
203 | #define BE 0x12000000 |
204 | #define BG 0x11000000 | |
205 | #define BGE 0x13000000 | |
206 | #define BL 0x14000000 | |
207 | #define BLE 0x16000000 | |
208 | #define BNE 0x15000000 | |
209 | #define BNO 0x10000000 | |
210 | #define BO 0x17000000 | |
211 | #define CHKBIT 0x5a002700 | |
212 | #define CMPI 0x5a002080 | |
213 | #define CMPO 0x5a002000 | |
214 | ||
215 | #define B 0x08000000 | |
216 | #define BAL 0x0b000000 | |
217 | #define CALL 0x09000000 | |
218 | #define CALLS 0x66003800 | |
219 | #define RET 0x0a000000 | |
220 | ||
92774660 | 221 | /* These masks are used to build up a set of MEMB mode bits. */ |
252b5132 RH |
222 | #define A_BIT 0x0400 |
223 | #define I_BIT 0x0800 | |
224 | #define MEMB_BIT 0x1000 | |
225 | #define D_BIT 0x2000 | |
226 | ||
252b5132 RH |
227 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is |
228 | used). */ | |
229 | #define MEMA_ABASE 0x2000 | |
230 | ||
ea1562b3 | 231 | /* Info from which a MEMA or MEMB format instruction can be generated. */ |
b9195351 | 232 | typedef struct memS |
252b5132 | 233 | { |
ea1562b3 | 234 | /* (First) 32 bits of instruction. */ |
252b5132 | 235 | long opcode; |
ea1562b3 | 236 | /* 0-(none), 12- or, 32-bit displacement needed. */ |
252b5132 RH |
237 | int disp; |
238 | /* The expression in the source instruction from which the | |
239 | displacement should be determined. */ | |
240 | char *e; | |
241 | } | |
252b5132 RH |
242 | memS; |
243 | ||
ea1562b3 | 244 | /* The two pieces of info we need to generate a register operand. */ |
252b5132 RH |
245 | struct regop |
246 | { | |
ea1562b3 NC |
247 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg. */ |
248 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0). */ | |
249 | int n; /* Register number or literal value. */ | |
252b5132 RH |
250 | }; |
251 | ||
252b5132 RH |
252 | /* Number and assembler mnemonic for all registers that can appear in |
253 | operands. */ | |
254 | static const struct | |
255 | { | |
256 | char *reg_name; | |
257 | int reg_num; | |
258 | } | |
259 | regnames[] = | |
260 | { | |
261 | { "pfp", 0 }, | |
262 | { "sp", 1 }, | |
263 | { "rip", 2 }, | |
264 | { "r3", 3 }, | |
265 | { "r4", 4 }, | |
266 | { "r5", 5 }, | |
267 | { "r6", 6 }, | |
268 | { "r7", 7 }, | |
269 | { "r8", 8 }, | |
270 | { "r9", 9 }, | |
271 | { "r10", 10 }, | |
272 | { "r11", 11 }, | |
273 | { "r12", 12 }, | |
274 | { "r13", 13 }, | |
275 | { "r14", 14 }, | |
276 | { "r15", 15 }, | |
277 | { "g0", 16 }, | |
278 | { "g1", 17 }, | |
279 | { "g2", 18 }, | |
280 | { "g3", 19 }, | |
281 | { "g4", 20 }, | |
282 | { "g5", 21 }, | |
283 | { "g6", 22 }, | |
284 | { "g7", 23 }, | |
285 | { "g8", 24 }, | |
286 | { "g9", 25 }, | |
287 | { "g10", 26 }, | |
288 | { "g11", 27 }, | |
289 | { "g12", 28 }, | |
290 | { "g13", 29 }, | |
291 | { "g14", 30 }, | |
292 | { "fp", 31 }, | |
293 | ||
294 | /* Numbers for special-function registers are for assembler internal | |
295 | use only: they are scaled back to range [0-31] for binary output. */ | |
296 | #define SF0 32 | |
297 | ||
298 | { "sf0", 32 }, | |
299 | { "sf1", 33 }, | |
300 | { "sf2", 34 }, | |
301 | { "sf3", 35 }, | |
302 | { "sf4", 36 }, | |
303 | { "sf5", 37 }, | |
304 | { "sf6", 38 }, | |
305 | { "sf7", 39 }, | |
306 | { "sf8", 40 }, | |
307 | { "sf9", 41 }, | |
308 | { "sf10", 42 }, | |
309 | { "sf11", 43 }, | |
310 | { "sf12", 44 }, | |
311 | { "sf13", 45 }, | |
312 | { "sf14", 46 }, | |
313 | { "sf15", 47 }, | |
314 | { "sf16", 48 }, | |
315 | { "sf17", 49 }, | |
316 | { "sf18", 50 }, | |
317 | { "sf19", 51 }, | |
318 | { "sf20", 52 }, | |
319 | { "sf21", 53 }, | |
320 | { "sf22", 54 }, | |
321 | { "sf23", 55 }, | |
322 | { "sf24", 56 }, | |
323 | { "sf25", 57 }, | |
324 | { "sf26", 58 }, | |
325 | { "sf27", 59 }, | |
326 | { "sf28", 60 }, | |
327 | { "sf29", 61 }, | |
328 | { "sf30", 62 }, | |
329 | { "sf31", 63 }, | |
330 | ||
331 | /* Numbers for floating point registers are for assembler internal | |
332 | use only: they are scaled back to [0-3] for binary output. */ | |
333 | #define FP0 64 | |
334 | ||
335 | { "fp0", 64 }, | |
336 | { "fp1", 65 }, | |
337 | { "fp2", 66 }, | |
338 | { "fp3", 67 }, | |
339 | ||
340 | { NULL, 0 }, /* END OF LIST */ | |
341 | }; | |
342 | ||
343 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) | |
344 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) | |
345 | #define IS_FP_REG(n) ((n) >= FP0) | |
346 | ||
347 | /* Number and assembler mnemonic for all registers that can appear as | |
348 | 'abase' (indirect addressing) registers. */ | |
349 | static const struct | |
ea1562b3 NC |
350 | { |
351 | char *areg_name; | |
352 | int areg_num; | |
353 | } | |
252b5132 RH |
354 | aregs[] = |
355 | { | |
356 | { "(pfp)", 0 }, | |
357 | { "(sp)", 1 }, | |
358 | { "(rip)", 2 }, | |
359 | { "(r3)", 3 }, | |
360 | { "(r4)", 4 }, | |
361 | { "(r5)", 5 }, | |
362 | { "(r6)", 6 }, | |
363 | { "(r7)", 7 }, | |
364 | { "(r8)", 8 }, | |
365 | { "(r9)", 9 }, | |
366 | { "(r10)", 10 }, | |
367 | { "(r11)", 11 }, | |
368 | { "(r12)", 12 }, | |
369 | { "(r13)", 13 }, | |
370 | { "(r14)", 14 }, | |
371 | { "(r15)", 15 }, | |
372 | { "(g0)", 16 }, | |
373 | { "(g1)", 17 }, | |
374 | { "(g2)", 18 }, | |
375 | { "(g3)", 19 }, | |
376 | { "(g4)", 20 }, | |
377 | { "(g5)", 21 }, | |
378 | { "(g6)", 22 }, | |
379 | { "(g7)", 23 }, | |
380 | { "(g8)", 24 }, | |
381 | { "(g9)", 25 }, | |
382 | { "(g10)", 26 }, | |
383 | { "(g11)", 27 }, | |
384 | { "(g12)", 28 }, | |
385 | { "(g13)", 29 }, | |
386 | { "(g14)", 30 }, | |
387 | { "(fp)", 31 }, | |
388 | ||
389 | #define IPREL 32 | |
390 | /* For assembler internal use only: this number never appears in binary | |
391 | output. */ | |
392 | { "(ip)", IPREL }, | |
393 | ||
394 | { NULL, 0 }, /* END OF LIST */ | |
395 | }; | |
396 | ||
ea1562b3 NC |
397 | /* Hash tables. */ |
398 | static struct hash_control *op_hash; /* Opcode mnemonics. */ | |
399 | static struct hash_control *reg_hash; /* Register name hash table. */ | |
400 | static struct hash_control *areg_hash; /* Abase register hash table. */ | |
252b5132 | 401 | |
ea1562b3 NC |
402 | /* Architecture for which we are assembling. */ |
403 | #define ARCH_ANY 0 /* Default: no architecture checking done. */ | |
252b5132 RH |
404 | #define ARCH_KA 1 |
405 | #define ARCH_KB 2 | |
406 | #define ARCH_MC 3 | |
407 | #define ARCH_CA 4 | |
408 | #define ARCH_JX 5 | |
409 | #define ARCH_HX 6 | |
ea1562b3 | 410 | int architecture = ARCH_ANY; /* Architecture requested on invocation line. */ |
252b5132 | 411 | int iclasses_seen; /* OR of instruction classes (I_* constants) |
ea1562b3 NC |
412 | for which we've actually assembled |
413 | instructions. */ | |
252b5132 | 414 | |
252b5132 RH |
415 | /* BRANCH-PREDICTION INSTRUMENTATION |
416 | ||
417 | The following supports generation of branch-prediction instrumentation | |
418 | (turned on by -b switch). The instrumentation collects counts | |
419 | of branches taken/not-taken for later input to a utility that will | |
420 | set the branch prediction bits of the instructions in accordance with | |
421 | the behavior observed. (Note that the KX series does not have | |
422 | brach-prediction.) | |
423 | ||
424 | The instrumentation consists of: | |
425 | ||
426 | (1) before and after each conditional branch, a call to an external | |
427 | routine that increments and steps over an inline counter. The | |
428 | counter itself, initialized to 0, immediately follows the call | |
429 | instruction. For each branch, the counter following the branch | |
430 | is the number of times the branch was not taken, and the difference | |
431 | between the counters is the number of times it was taken. An | |
432 | example of an instrumented conditional branch: | |
433 | ||
434 | call BR_CNT_FUNC | |
435 | .word 0 | |
436 | LBRANCH23: be label | |
437 | call BR_CNT_FUNC | |
438 | .word 0 | |
439 | ||
440 | (2) a table of pointers to the instrumented branches, so that an | |
441 | external postprocessing routine can locate all of the counters. | |
442 | the table begins with a 2-word header: a pointer to the next in | |
443 | a linked list of such tables (initialized to 0); and a count | |
444 | of the number of entries in the table (exclusive of the header. | |
445 | ||
446 | Note that input source code is expected to already contain calls | |
447 | an external routine that will link the branch local table into a | |
ea1562b3 | 448 | list of such tables. */ |
252b5132 RH |
449 | |
450 | /* Number of branches instrumented so far. Also used to generate | |
451 | unique local labels for each instrumented branch. */ | |
452 | static int br_cnt; | |
453 | ||
454 | #define BR_LABEL_BASE "LBRANCH" | |
455 | /* Basename of local labels on instrumented branches, to avoid | |
456 | conflict with compiler- generated local labels. */ | |
457 | ||
458 | #define BR_CNT_FUNC "__inc_branch" | |
459 | /* Name of the external routine that will increment (and step over) an | |
460 | inline counter. */ | |
461 | ||
462 | #define BR_TAB_NAME "__BRANCH_TABLE__" | |
463 | /* Name of the table of pointers to branches. A local (i.e., | |
464 | non-external) symbol. */ | |
252b5132 | 465 | |
ea1562b3 | 466 | static void ctrl_fmt (char *, long, int); |
252b5132 | 467 | |
ea1562b3 | 468 | \f |
252b5132 | 469 | void |
ea1562b3 | 470 | md_begin (void) |
252b5132 | 471 | { |
ea1562b3 NC |
472 | int i; /* Loop counter. */ |
473 | const struct i960_opcode *oP; /* Pointer into opcode table. */ | |
474 | const char *retval; /* Value returned by hash functions. */ | |
252b5132 RH |
475 | |
476 | op_hash = hash_new (); | |
477 | reg_hash = hash_new (); | |
478 | areg_hash = hash_new (); | |
479 | ||
480 | /* For some reason, the base assembler uses an empty string for "no | |
481 | error message", instead of a NULL pointer. */ | |
482 | retval = 0; | |
483 | ||
484 | for (oP = i960_opcodes; oP->name && !retval; oP++) | |
ea1562b3 | 485 | retval = hash_insert (op_hash, oP->name, (void *) oP); |
252b5132 RH |
486 | |
487 | for (i = 0; regnames[i].reg_name && !retval; i++) | |
488 | retval = hash_insert (reg_hash, regnames[i].reg_name, | |
489 | (char *) ®names[i].reg_num); | |
490 | ||
491 | for (i = 0; aregs[i].areg_name && !retval; i++) | |
492 | retval = hash_insert (areg_hash, aregs[i].areg_name, | |
493 | (char *) &aregs[i].areg_num); | |
494 | ||
495 | if (retval) | |
496 | as_fatal (_("Hashing returned \"%s\"."), retval); | |
497 | } | |
498 | ||
ea1562b3 | 499 | /* parse_expr: parse an expression |
252b5132 | 500 | |
ea1562b3 NC |
501 | Use base assembler's expression parser to parse an expression. |
502 | It, unfortunately, runs off a global which we have to save/restore | |
503 | in order to make it work for us. | |
252b5132 | 504 | |
ea1562b3 | 505 | An empty expression string is treated as an absolute 0. |
252b5132 | 506 | |
ea1562b3 NC |
507 | Sets O_illegal regardless of expression evaluation if entire input |
508 | string is not consumed in the evaluation -- tolerate no dangling junk! */ | |
252b5132 | 509 | |
ea1562b3 NC |
510 | static void |
511 | parse_expr (char *textP, /* Text of expression to be parsed. */ | |
512 | expressionS *expP) /* Where to put the results of parsing. */ | |
513 | { | |
514 | char *save_in; /* Save global here. */ | |
515 | symbolS *symP; | |
252b5132 | 516 | |
ea1562b3 | 517 | know (textP); |
252b5132 | 518 | |
ea1562b3 | 519 | if (*textP == '\0') |
252b5132 | 520 | { |
ea1562b3 NC |
521 | /* Treat empty string as absolute 0. */ |
522 | expP->X_add_symbol = expP->X_op_symbol = NULL; | |
523 | expP->X_add_number = 0; | |
524 | expP->X_op = O_constant; | |
252b5132 | 525 | } |
ea1562b3 | 526 | else |
252b5132 | 527 | { |
ea1562b3 NC |
528 | save_in = input_line_pointer; /* Save global. */ |
529 | input_line_pointer = textP; /* Make parser work for us. */ | |
252b5132 | 530 | |
ea1562b3 NC |
531 | (void) expression (expP); |
532 | if ((size_t) (input_line_pointer - textP) != strlen (textP)) | |
533 | /* Did not consume all of the input. */ | |
534 | expP->X_op = O_illegal; | |
252b5132 | 535 | |
ea1562b3 NC |
536 | symP = expP->X_add_symbol; |
537 | if (symP && (hash_find (reg_hash, S_GET_NAME (symP)))) | |
538 | /* Register name in an expression. */ | |
539 | /* FIXME: this isn't much of a check any more. */ | |
540 | expP->X_op = O_illegal; | |
252b5132 | 541 | |
ea1562b3 | 542 | input_line_pointer = save_in; /* Restore global. */ |
252b5132 | 543 | } |
ea1562b3 NC |
544 | } |
545 | ||
546 | /* emit: output instruction binary | |
547 | ||
548 | Output instruction binary, in target byte order, 4 bytes at a time. | |
549 | Return pointer to where it was placed. */ | |
550 | ||
551 | static char * | |
552 | emit (long instr) /* Word to be output, host byte order. */ | |
553 | { | |
554 | char *toP; /* Where to output it. */ | |
555 | ||
556 | toP = frag_more (4); /* Allocate storage. */ | |
557 | md_number_to_chars (toP, instr, 4); /* Convert to target byte order. */ | |
558 | return toP; | |
559 | } | |
560 | ||
561 | /* get_cdisp: handle displacement for a COBR or CTRL instruction. | |
562 | ||
563 | Parse displacement for a COBR or CTRL instruction. | |
564 | ||
565 | If successful, output the instruction opcode and set up for it, | |
566 | depending on the arg 'var_frag', either: | |
567 | o an address fixup to be done when all symbol values are known, or | |
568 | o a varying length code fragment, with address fixup info. This | |
569 | will be done for cobr instructions that may have to be relaxed | |
570 | in to compare/branch instructions (8 bytes) if the final | |
571 | address displacement is greater than 13 bits. */ | |
572 | ||
573 | static void | |
574 | get_cdisp (char *dispP, /* Displacement as specified in source instruction. */ | |
575 | char *ifmtP, /* "COBR" or "CTRL" (for use in error message). */ | |
576 | long instr, /* Instruction needing the displacement. */ | |
577 | int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */ | |
578 | int var_frag,/* 1 if varying length code fragment should be emitted; | |
579 | 0 if an address fix should be emitted. */ | |
580 | int callj) /* 1 if callj relocation should be done; else 0. */ | |
581 | { | |
582 | expressionS e; /* Parsed expression. */ | |
583 | fixS *fixP; /* Structure describing needed address fix. */ | |
584 | char *outP; /* Where instruction binary is output to. */ | |
585 | ||
586 | fixP = NULL; | |
587 | ||
588 | parse_expr (dispP, &e); | |
589 | switch (e.X_op) | |
252b5132 | 590 | { |
ea1562b3 NC |
591 | case O_illegal: |
592 | as_bad (_("expression syntax error")); | |
593 | ||
594 | case O_symbol: | |
595 | if (S_GET_SEGMENT (e.X_add_symbol) == now_seg | |
596 | || S_GET_SEGMENT (e.X_add_symbol) == undefined_section) | |
252b5132 | 597 | { |
ea1562b3 | 598 | if (var_frag) |
252b5132 | 599 | { |
ea1562b3 NC |
600 | outP = frag_more (8); /* Allocate worst-case storage. */ |
601 | md_number_to_chars (outP, instr, 4); | |
602 | frag_variant (rs_machine_dependent, 4, 4, 1, | |
603 | adds (e), offs (e), outP); | |
252b5132 | 604 | } |
ea1562b3 | 605 | else |
252b5132 | 606 | { |
ea1562b3 NC |
607 | /* Set up a new fix structure, so address can be updated |
608 | when all symbol values are known. */ | |
609 | outP = emit (instr); | |
610 | fixP = fix_new (frag_now, | |
611 | outP - frag_now->fr_literal, | |
612 | 4, | |
613 | adds (e), | |
614 | offs (e), | |
615 | 1, | |
616 | NO_RELOC); | |
617 | ||
618 | fixP->fx_tcbit = callj; | |
619 | ||
620 | /* We want to modify a bit field when the address is | |
621 | known. But we don't need all the garbage in the | |
622 | bit_fix structure. So we're going to lie and store | |
623 | the number of bits affected instead of a pointer. */ | |
624 | fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits; | |
252b5132 | 625 | } |
252b5132 | 626 | } |
ea1562b3 NC |
627 | else |
628 | as_bad (_("attempt to branch into different segment")); | |
629 | break; | |
252b5132 | 630 | |
ea1562b3 NC |
631 | default: |
632 | as_bad (_("target of %s instruction must be a label"), ifmtP); | |
633 | break; | |
634 | } | |
252b5132 RH |
635 | } |
636 | ||
b9195351 | 637 | static int |
ea1562b3 NC |
638 | md_chars_to_number (char * val, /* Value in target byte order. */ |
639 | int n) /* Number of bytes in the input. */ | |
252b5132 RH |
640 | { |
641 | int retval; | |
642 | ||
643 | for (retval = 0; n--;) | |
644 | { | |
645 | retval <<= 8; | |
2132e3a3 | 646 | retval |= (unsigned char) val[n]; |
252b5132 RH |
647 | } |
648 | return retval; | |
649 | } | |
650 | ||
ea1562b3 | 651 | /* mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. |
252b5132 | 652 | |
ea1562b3 NC |
653 | There are 2 possible MEMA formats: |
654 | - displacement only | |
655 | - displacement + abase | |
252b5132 | 656 | |
ea1562b3 | 657 | They are distinguished by the setting of the MEMA_ABASE bit. */ |
252b5132 | 658 | |
ea1562b3 NC |
659 | static void |
660 | mema_to_memb (char * opcodeP) /* Where to find the opcode, in target byte order. */ | |
252b5132 | 661 | { |
ea1562b3 NC |
662 | long opcode; /* Opcode in host byte order. */ |
663 | long mode; /* Mode bits for MEMB instruction. */ | |
252b5132 | 664 | |
ea1562b3 NC |
665 | opcode = md_chars_to_number (opcodeP, 4); |
666 | know (!(opcode & MEMB_BIT)); | |
252b5132 | 667 | |
ea1562b3 NC |
668 | mode = MEMB_BIT | D_BIT; |
669 | if (opcode & MEMA_ABASE) | |
670 | mode |= A_BIT; | |
252b5132 | 671 | |
ea1562b3 NC |
672 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits. */ |
673 | opcode |= mode; /* Set MEMB mode bits. */ | |
252b5132 | 674 | |
ea1562b3 | 675 | md_number_to_chars (opcodeP, opcode, 4); |
252b5132 RH |
676 | } |
677 | ||
ea1562b3 | 678 | /* targ_has_sfr: |
252b5132 | 679 | |
ea1562b3 NC |
680 | Return TRUE iff the target architecture supports the specified |
681 | special-function register (sfr). */ | |
252b5132 | 682 | |
ea1562b3 NC |
683 | static int |
684 | targ_has_sfr (int n) /* Number (0-31) of sfr. */ | |
252b5132 | 685 | { |
ea1562b3 NC |
686 | switch (architecture) |
687 | { | |
688 | case ARCH_KA: | |
689 | case ARCH_KB: | |
690 | case ARCH_MC: | |
691 | case ARCH_JX: | |
692 | return 0; | |
693 | case ARCH_HX: | |
694 | return ((0 <= n) && (n <= 4)); | |
695 | case ARCH_CA: | |
696 | default: | |
697 | return ((0 <= n) && (n <= 2)); | |
698 | } | |
252b5132 RH |
699 | } |
700 | ||
ea1562b3 NC |
701 | /* Look up a (suspected) register name in the register table and return the |
702 | associated register number (or -1 if not found). */ | |
703 | ||
704 | static int | |
705 | get_regnum (char *regname) /* Suspected register name. */ | |
706 | { | |
707 | int *rP; | |
252b5132 | 708 | |
ea1562b3 NC |
709 | rP = (int *) hash_find (reg_hash, regname); |
710 | return (rP == NULL) ? -1 : *rP; | |
711 | } | |
252b5132 | 712 | |
ea1562b3 | 713 | /* syntax: Issue a syntax error. */ |
b9195351 AM |
714 | |
715 | static void | |
ea1562b3 | 716 | syntax (void) |
252b5132 | 717 | { |
ea1562b3 NC |
718 | as_bad (_("syntax error")); |
719 | } | |
252b5132 | 720 | |
ea1562b3 | 721 | /* parse_regop: parse a register operand. |
252b5132 | 722 | |
ea1562b3 NC |
723 | In case of illegal operand, issue a message and return some valid |
724 | information so instruction processing can continue. */ | |
252b5132 | 725 | |
ea1562b3 NC |
726 | static void |
727 | parse_regop (struct regop *regopP, /* Where to put description of register operand. */ | |
728 | char *optext, /* Text of operand. */ | |
729 | char opdesc) /* Descriptor byte: what's legal for this operand. */ | |
730 | { | |
731 | int n; /* Register number. */ | |
732 | expressionS e; /* Parsed expression. */ | |
252b5132 | 733 | |
ea1562b3 NC |
734 | /* See if operand is a register. */ |
735 | n = get_regnum (optext); | |
736 | if (n >= 0) | |
252b5132 | 737 | { |
ea1562b3 NC |
738 | if (IS_RG_REG (n)) |
739 | { | |
740 | /* Global or local register. */ | |
741 | if (!REG_ALIGN (opdesc, n)) | |
742 | as_bad (_("unaligned register")); | |
252b5132 | 743 | |
ea1562b3 NC |
744 | regopP->n = n; |
745 | regopP->mode = 0; | |
746 | regopP->special = 0; | |
747 | return; | |
748 | } | |
749 | else if (IS_FP_REG (n) && FP_OK (opdesc)) | |
750 | { | |
751 | /* Floating point register, and it's allowed. */ | |
752 | regopP->n = n - FP0; | |
753 | regopP->mode = 1; | |
754 | regopP->special = 0; | |
755 | return; | |
756 | } | |
757 | else if (IS_SF_REG (n) && SFR_OK (opdesc)) | |
758 | { | |
759 | /* Special-function register, and it's allowed. */ | |
760 | regopP->n = n - SF0; | |
761 | regopP->mode = 0; | |
762 | regopP->special = 1; | |
763 | if (!targ_has_sfr (regopP->n)) | |
764 | as_bad (_("no such sfr in this architecture")); | |
252b5132 | 765 | |
ea1562b3 NC |
766 | return; |
767 | } | |
768 | } | |
769 | else if (LIT_OK (opdesc)) | |
770 | { | |
771 | /* How about a literal? */ | |
772 | regopP->mode = 1; | |
773 | regopP->special = 0; | |
774 | if (FP_OK (opdesc)) | |
775 | { | |
776 | /* Floating point literal acceptable. */ | |
777 | /* Skip over 0f, 0d, or 0e prefix. */ | |
778 | if ((optext[0] == '0') | |
779 | && (optext[1] >= 'd') | |
780 | && (optext[1] <= 'f')) | |
781 | optext += 2; | |
252b5132 | 782 | |
ea1562b3 NC |
783 | if (!strcmp (optext, "0.0") || !strcmp (optext, "0")) |
784 | { | |
785 | regopP->n = 0x10; | |
786 | return; | |
787 | } | |
252b5132 | 788 | |
ea1562b3 NC |
789 | if (!strcmp (optext, "1.0") || !strcmp (optext, "1")) |
790 | { | |
791 | regopP->n = 0x16; | |
792 | return; | |
793 | } | |
794 | } | |
795 | else | |
796 | { | |
797 | /* Fixed point literal acceptable. */ | |
798 | parse_expr (optext, &e); | |
799 | if (e.X_op != O_constant | |
800 | || (offs (e) < 0) || (offs (e) > 31)) | |
801 | { | |
802 | as_bad (_("illegal literal")); | |
803 | offs (e) = 0; | |
804 | } | |
805 | regopP->n = offs (e); | |
806 | return; | |
807 | } | |
808 | } | |
252b5132 | 809 | |
ea1562b3 NC |
810 | /* Nothing worked. */ |
811 | syntax (); | |
812 | regopP->mode = 0; /* Register r0 is always a good one. */ | |
813 | regopP->n = 0; | |
814 | regopP->special = 0; | |
815 | } | |
252b5132 | 816 | |
ea1562b3 NC |
817 | /* get_ispec: parse a memory operand for an index specification |
818 | ||
819 | Here, an "index specification" is taken to be anything surrounded | |
820 | by square brackets and NOT followed by anything else. | |
252b5132 | 821 | |
ea1562b3 NC |
822 | If it's found, detach it from the input string, remove the surrounding |
823 | square brackets, and return a pointer to it. Otherwise, return NULL. */ | |
252b5132 | 824 | |
ea1562b3 NC |
825 | static char * |
826 | get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */ | |
827 | ||
252b5132 | 828 | { |
ea1562b3 NC |
829 | /* Points to start of index specification. */ |
830 | char *start; | |
831 | /* Points to end of index specification. */ | |
832 | char *end; | |
252b5132 | 833 | |
ea1562b3 NC |
834 | /* Find opening square bracket, if any. */ |
835 | start = strchr (textP, '['); | |
252b5132 | 836 | |
ea1562b3 | 837 | if (start != NULL) |
252b5132 | 838 | { |
ea1562b3 NC |
839 | /* Eliminate '[', detach from rest of operand. */ |
840 | *start++ = '\0'; | |
252b5132 | 841 | |
ea1562b3 | 842 | end = strchr (start, ']'); |
252b5132 | 843 | |
ea1562b3 NC |
844 | if (end == NULL) |
845 | as_bad (_("unmatched '['")); | |
846 | else | |
847 | { | |
848 | /* Eliminate ']' and make sure it was the last thing | |
849 | in the string. */ | |
850 | *end = '\0'; | |
851 | if (*(end + 1) != '\0') | |
852 | as_bad (_("garbage after index spec ignored")); | |
853 | } | |
854 | } | |
855 | return start; | |
856 | } | |
252b5132 | 857 | |
ea1562b3 | 858 | /* parse_memop: parse a memory operand |
252b5132 | 859 | |
ea1562b3 NC |
860 | This routine is based on the observation that the 4 mode bits of the |
861 | MEMB format, taken individually, have fairly consistent meaning: | |
252b5132 | 862 | |
ea1562b3 NC |
863 | M3 (bit 13): 1 if displacement is present (D_BIT) |
864 | M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) | |
865 | M1 (bit 11): 1 if index is present (I_BIT) | |
866 | M0 (bit 10): 1 if abase is present (A_BIT) | |
252b5132 | 867 | |
ea1562b3 NC |
868 | So we parse the memory operand and set bits in the mode as we find |
869 | things. Then at the end, if we go to MEMB format, we need only set | |
870 | the MEMB bit (M2) and our mode is built for us. | |
252b5132 | 871 | |
ea1562b3 | 872 | Unfortunately, I said "fairly consistent". The exceptions: |
252b5132 | 873 | |
ea1562b3 NC |
874 | DBIA |
875 | 0100 Would seem illegal, but means "abase-only". | |
252b5132 | 876 | |
ea1562b3 NC |
877 | 0101 Would seem to mean "abase-only" -- it means IP-relative. |
878 | Must be converted to 0100. | |
252b5132 | 879 | |
ea1562b3 NC |
880 | 0110 Would seem to mean "index-only", but is reserved. |
881 | We turn on the D bit and provide a 0 displacement. | |
252b5132 | 882 | |
ea1562b3 NC |
883 | The other thing to observe is that we parse from the right, peeling |
884 | things * off as we go: first any index spec, then any abase, then | |
885 | the displacement. */ | |
252b5132 | 886 | |
ea1562b3 NC |
887 | static void |
888 | parse_memop (memS *memP, /* Where to put the results. */ | |
889 | char *argP, /* Text of the operand to be parsed. */ | |
890 | int optype) /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16. */ | |
252b5132 | 891 | { |
ea1562b3 NC |
892 | char *indexP; /* Pointer to index specification with "[]" removed. */ |
893 | char *p; /* Temp char pointer. */ | |
894 | char iprel_flag; /* True if this is an IP-relative operand. */ | |
895 | int regnum; /* Register number. */ | |
896 | /* Scale factor: 1,2,4,8, or 16. Later converted to internal format | |
897 | (0,1,2,3,4 respectively). */ | |
898 | int scale; | |
899 | int mode; /* MEMB mode bits. */ | |
900 | int *intP; /* Pointer to register number. */ | |
252b5132 | 901 | |
ea1562b3 NC |
902 | /* The following table contains the default scale factors for each |
903 | type of memory instruction. It is accessed using (optype-MEM1) | |
904 | as an index -- thus it assumes the 'optype' constants are | |
905 | assigned consecutive values, in the order they appear in this | |
906 | table. */ | |
907 | static const int def_scale[] = | |
908 | { | |
909 | 1, /* MEM1 */ | |
910 | 2, /* MEM2 */ | |
911 | 4, /* MEM4 */ | |
912 | 8, /* MEM8 */ | |
913 | -1, /* MEM12 -- no valid default */ | |
914 | 16 /* MEM16 */ | |
915 | }; | |
252b5132 | 916 | |
ea1562b3 | 917 | iprel_flag = mode = 0; |
252b5132 | 918 | |
ea1562b3 NC |
919 | /* Any index present? */ |
920 | indexP = get_ispec (argP); | |
921 | if (indexP) | |
252b5132 | 922 | { |
ea1562b3 NC |
923 | p = strchr (indexP, '*'); |
924 | if (p == NULL) | |
925 | { | |
926 | /* No explicit scale -- use default for this instruction | |
927 | type and assembler mode. */ | |
928 | if (flag_mri) | |
929 | scale = 1; | |
930 | else | |
931 | /* GNU960 compatibility */ | |
932 | scale = def_scale[optype - MEM1]; | |
933 | } | |
934 | else | |
935 | { | |
936 | *p++ = '\0'; /* Eliminate '*' */ | |
252b5132 | 937 | |
ea1562b3 NC |
938 | /* Now indexP->a '\0'-terminated register name, |
939 | and p->a scale factor. */ | |
252b5132 | 940 | |
ea1562b3 NC |
941 | if (!strcmp (p, "16")) |
942 | scale = 16; | |
943 | else if (strchr ("1248", *p) && (p[1] == '\0')) | |
944 | scale = *p - '0'; | |
945 | else | |
946 | scale = -1; | |
947 | } | |
252b5132 | 948 | |
ea1562b3 NC |
949 | regnum = get_regnum (indexP); /* Get index reg. # */ |
950 | if (!IS_RG_REG (regnum)) | |
951 | { | |
952 | as_bad (_("invalid index register")); | |
953 | return; | |
954 | } | |
252b5132 | 955 | |
ea1562b3 NC |
956 | /* Convert scale to its binary encoding. */ |
957 | switch (scale) | |
958 | { | |
959 | case 1: | |
960 | scale = 0 << 7; | |
961 | break; | |
962 | case 2: | |
963 | scale = 1 << 7; | |
964 | break; | |
965 | case 4: | |
966 | scale = 2 << 7; | |
967 | break; | |
968 | case 8: | |
969 | scale = 3 << 7; | |
970 | break; | |
971 | case 16: | |
972 | scale = 4 << 7; | |
973 | break; | |
974 | default: | |
975 | as_bad (_("invalid scale factor")); | |
976 | return; | |
977 | }; | |
bedf545c | 978 | |
ea1562b3 NC |
979 | memP->opcode |= scale | regnum; /* Set index bits in opcode. */ |
980 | mode |= I_BIT; /* Found a valid index spec. */ | |
981 | } | |
252b5132 | 982 | |
ea1562b3 NC |
983 | /* Any abase (Register Indirect) specification present? */ |
984 | if ((p = strrchr (argP, '(')) != NULL) | |
985 | { | |
986 | /* "(" is there -- does it start a legal abase spec? If not, it | |
987 | could be part of a displacement expression. */ | |
988 | intP = (int *) hash_find (areg_hash, p); | |
989 | if (intP != NULL) | |
990 | { | |
991 | /* Got an abase here. */ | |
992 | regnum = *intP; | |
993 | *p = '\0'; /* Discard register spec. */ | |
994 | if (regnum == IPREL) | |
995 | /* We have to specialcase ip-rel mode. */ | |
996 | iprel_flag = 1; | |
997 | else | |
998 | { | |
999 | memP->opcode |= regnum << 14; | |
1000 | mode |= A_BIT; | |
1001 | } | |
1002 | } | |
1003 | } | |
bedf545c | 1004 | |
ea1562b3 NC |
1005 | /* Any expression present? */ |
1006 | memP->e = argP; | |
1007 | if (*argP != '\0') | |
1008 | mode |= D_BIT; | |
252b5132 | 1009 | |
ea1562b3 NC |
1010 | /* Special-case ip-relative addressing. */ |
1011 | if (iprel_flag) | |
1012 | { | |
1013 | if (mode & I_BIT) | |
1014 | syntax (); | |
1015 | else | |
1016 | { | |
1017 | memP->opcode |= 5 << 10; /* IP-relative mode. */ | |
1018 | memP->disp = 32; | |
1019 | } | |
1020 | return; | |
1021 | } | |
252b5132 | 1022 | |
ea1562b3 NC |
1023 | /* Handle all other modes. */ |
1024 | switch (mode) | |
1025 | { | |
1026 | case D_BIT | A_BIT: | |
1027 | /* Go with MEMA instruction format for now (grow to MEMB later | |
1028 | if 12 bits is not enough for the displacement). MEMA format | |
1029 | has a single mode bit: set it to indicate that abase is | |
1030 | present. */ | |
1031 | memP->opcode |= MEMA_ABASE; | |
1032 | memP->disp = 12; | |
1033 | break; | |
252b5132 | 1034 | |
ea1562b3 NC |
1035 | case D_BIT: |
1036 | /* Go with MEMA instruction format for now (grow to MEMB later | |
1037 | if 12 bits is not enough for the displacement). */ | |
1038 | memP->disp = 12; | |
1039 | break; | |
252b5132 | 1040 | |
ea1562b3 NC |
1041 | case A_BIT: |
1042 | /* For some reason, the bit string for this mode is not | |
1043 | consistent: it should be 0 (exclusive of the MEMB bit), so we | |
1044 | set it "by hand" here. */ | |
1045 | memP->opcode |= MEMB_BIT; | |
1046 | break; | |
252b5132 | 1047 | |
ea1562b3 NC |
1048 | case A_BIT | I_BIT: |
1049 | /* set MEMB bit in mode, and OR in mode bits. */ | |
1050 | memP->opcode |= mode | MEMB_BIT; | |
1051 | break; | |
252b5132 | 1052 | |
ea1562b3 NC |
1053 | case I_BIT: |
1054 | /* Treat missing displacement as displacement of 0. */ | |
1055 | mode |= D_BIT; | |
1056 | /* Fall into next case. */ | |
1057 | case D_BIT | A_BIT | I_BIT: | |
1058 | case D_BIT | I_BIT: | |
1059 | /* Set MEMB bit in mode, and OR in mode bits. */ | |
1060 | memP->opcode |= mode | MEMB_BIT; | |
1061 | memP->disp = 32; | |
1062 | break; | |
252b5132 | 1063 | |
ea1562b3 NC |
1064 | default: |
1065 | syntax (); | |
1066 | break; | |
1067 | } | |
1068 | } | |
252b5132 | 1069 | |
ea1562b3 | 1070 | /* Generate a MEMA- or MEMB-format instruction. */ |
252b5132 | 1071 | |
ea1562b3 NC |
1072 | static void |
1073 | mem_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */ | |
1074 | struct i960_opcode *oP,/* Pointer to description of instruction. */ | |
1075 | int callx) /* Is this a callx opcode. */ | |
252b5132 | 1076 | { |
ea1562b3 NC |
1077 | int i; /* Loop counter. */ |
1078 | struct regop regop; /* Description of register operand. */ | |
1079 | char opdesc; /* Operand descriptor byte. */ | |
1080 | memS instr; /* Description of binary to be output. */ | |
1081 | char *outP; /* Where the binary was output to. */ | |
1082 | expressionS expr; /* Parsed expression. */ | |
1083 | /* ->description of deferred address fixup. */ | |
252b5132 RH |
1084 | fixS *fixP; |
1085 | ||
ea1562b3 NC |
1086 | #ifdef OBJ_COFF |
1087 | /* COFF support isn't in place yet for callx relaxing. */ | |
1088 | callx = 0; | |
1089 | #endif | |
252b5132 | 1090 | |
ea1562b3 NC |
1091 | memset (&instr, '\0', sizeof (memS)); |
1092 | instr.opcode = oP->opcode; | |
252b5132 | 1093 | |
ea1562b3 NC |
1094 | /* Process operands. */ |
1095 | for (i = 1; i <= oP->num_ops; i++) | |
252b5132 | 1096 | { |
ea1562b3 NC |
1097 | opdesc = oP->operand[i - 1]; |
1098 | ||
1099 | if (MEMOP (opdesc)) | |
1100 | parse_memop (&instr, args[i], oP->format); | |
1101 | else | |
1102 | { | |
1103 | parse_regop (®op, args[i], opdesc); | |
1104 | instr.opcode |= regop.n << 19; | |
1105 | } | |
252b5132 | 1106 | } |
252b5132 | 1107 | |
ea1562b3 NC |
1108 | /* Parse the displacement; this must be done before emitting the |
1109 | opcode, in case it is an expression using `.'. */ | |
1110 | parse_expr (instr.e, &expr); | |
252b5132 | 1111 | |
ea1562b3 NC |
1112 | /* Output opcode. */ |
1113 | outP = emit (instr.opcode); | |
252b5132 | 1114 | |
ea1562b3 NC |
1115 | if (instr.disp == 0) |
1116 | return; | |
252b5132 | 1117 | |
ea1562b3 NC |
1118 | /* Process the displacement. */ |
1119 | switch (expr.X_op) | |
252b5132 | 1120 | { |
ea1562b3 NC |
1121 | case O_illegal: |
1122 | as_bad (_("expression syntax error")); | |
1123 | break; | |
252b5132 | 1124 | |
ea1562b3 NC |
1125 | case O_constant: |
1126 | if (instr.disp == 32) | |
1127 | (void) emit (offs (expr)); /* Output displacement. */ | |
1128 | else | |
1129 | { | |
1130 | /* 12-bit displacement. */ | |
1131 | if (offs (expr) & ~0xfff) | |
1132 | { | |
1133 | /* Won't fit in 12 bits: convert already-output | |
1134 | instruction to MEMB format, output | |
1135 | displacement. */ | |
1136 | mema_to_memb (outP); | |
1137 | (void) emit (offs (expr)); | |
1138 | } | |
1139 | else | |
1140 | { | |
1141 | /* WILL fit in 12 bits: OR into opcode and | |
1142 | overwrite the binary we already put out. */ | |
1143 | instr.opcode |= offs (expr); | |
1144 | md_number_to_chars (outP, instr.opcode, 4); | |
1145 | } | |
1146 | } | |
1147 | break; | |
252b5132 | 1148 | |
ea1562b3 NC |
1149 | default: |
1150 | if (instr.disp == 12) | |
1151 | /* Displacement is dependent on a symbol, whose value | |
1152 | may change at link time. We HAVE to reserve 32 bits. | |
1153 | Convert already-output opcode to MEMB format. */ | |
1154 | mema_to_memb (outP); | |
1155 | ||
1156 | /* Output 0 displacement and set up address fixup for when | |
1157 | this symbol's value becomes known. */ | |
1158 | outP = emit ((long) 0); | |
1159 | fixP = fix_new_exp (frag_now, | |
1160 | outP - frag_now->fr_literal, | |
1161 | 4, & expr, 0, NO_RELOC); | |
1162 | /* Steve's linker relaxing hack. Mark this 32-bit relocation as | |
1163 | being in the instruction stream, specifically as part of a callx | |
1164 | instruction. */ | |
1165 | fixP->fx_bsr = callx; | |
1166 | break; | |
252b5132 | 1167 | } |
ea1562b3 NC |
1168 | } |
1169 | ||
1170 | /* targ_has_iclass: | |
1171 | ||
1172 | Return TRUE iff the target architecture supports the indicated | |
1173 | class of instructions. */ | |
1174 | ||
1175 | static int | |
1176 | targ_has_iclass (int ic) /* Instruction class; one of: | |
1177 | I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2. */ | |
1178 | { | |
1179 | iclasses_seen |= ic; | |
1180 | ||
1181 | switch (architecture) | |
252b5132 | 1182 | { |
ea1562b3 NC |
1183 | case ARCH_KA: |
1184 | return ic & (I_BASE | I_KX); | |
1185 | case ARCH_KB: | |
1186 | return ic & (I_BASE | I_KX | I_FP | I_DEC); | |
1187 | case ARCH_MC: | |
1188 | return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); | |
1189 | case ARCH_CA: | |
1190 | return ic & (I_BASE | I_CX | I_CX2 | I_CASIM); | |
1191 | case ARCH_JX: | |
1192 | return ic & (I_BASE | I_CX2 | I_JX); | |
1193 | case ARCH_HX: | |
1194 | return ic & (I_BASE | I_CX2 | I_JX | I_HX); | |
1195 | default: | |
1196 | if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL)) | |
1197 | && (iclasses_seen & (I_CX | I_CX2))) | |
252b5132 | 1198 | { |
ea1562b3 NC |
1199 | as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)")); |
1200 | iclasses_seen &= ~ic; | |
252b5132 | 1201 | } |
ea1562b3 NC |
1202 | return 1; |
1203 | } | |
1204 | } | |
252b5132 | 1205 | |
ea1562b3 NC |
1206 | /* shift_ok: |
1207 | Determine if a "shlo" instruction can be used to implement a "ldconst". | |
1208 | This means that some number X < 32 can be shifted left to produce the | |
1209 | constant of interest. | |
252b5132 | 1210 | |
ea1562b3 NC |
1211 | Return the shift count, or 0 if we can't do it. |
1212 | Caller calculates X by shifting original constant right 'shift' places. */ | |
1213 | ||
1214 | static int | |
1215 | shift_ok (int n) /* The constant of interest. */ | |
1216 | { | |
1217 | int shift; /* The shift count. */ | |
1218 | ||
1219 | if (n <= 0) | |
1220 | /* Can't do it for negative numbers. */ | |
1221 | return 0; | |
1222 | ||
1223 | /* Shift 'n' right until a 1 is about to be lost. */ | |
1224 | for (shift = 0; (n & 1) == 0; shift++) | |
1225 | n >>= 1; | |
1226 | ||
1227 | if (n >= 32) | |
1228 | return 0; | |
1229 | ||
1230 | return shift; | |
1231 | } | |
1232 | ||
1233 | /* parse_ldcont: | |
1234 | Parse and replace a 'ldconst' pseudo-instruction with an appropriate | |
1235 | i80960 instruction. | |
1236 | ||
1237 | Assumes the input consists of: | |
1238 | arg[0] opcode mnemonic ('ldconst') | |
1239 | arg[1] first operand (constant) | |
1240 | arg[2] name of register to be loaded | |
1241 | ||
1242 | Replaces opcode and/or operands as appropriate. | |
1243 | ||
1244 | Returns the new number of arguments, or -1 on failure. */ | |
1245 | ||
1246 | static int | |
1247 | parse_ldconst (char *arg[]) /* See above. */ | |
1248 | { | |
1249 | int n; /* Constant to be loaded. */ | |
1250 | int shift; /* Shift count for "shlo" instruction. */ | |
1251 | static char buf[5]; /* Literal for first operand. */ | |
1252 | static char buf2[5]; /* Literal for second operand. */ | |
1253 | expressionS e; /* Parsed expression. */ | |
1254 | ||
1255 | arg[3] = NULL; /* So we can tell at the end if it got used or not. */ | |
1256 | ||
1257 | parse_expr (arg[1], &e); | |
1258 | switch (e.X_op) | |
1259 | { | |
1260 | default: | |
1261 | /* We're dependent on one or more symbols -- use "lda". */ | |
1262 | arg[0] = "lda"; | |
1263 | break; | |
1264 | ||
1265 | case O_constant: | |
1266 | /* Try the following mappings: | |
1267 | ldconst 0,<reg> -> mov 0,<reg> | |
1268 | ldconst 31,<reg> -> mov 31,<reg> | |
1269 | ldconst 32,<reg> -> addo 1,31,<reg> | |
1270 | ldconst 62,<reg> -> addo 31,31,<reg> | |
1271 | ldconst 64,<reg> -> shlo 8,3,<reg> | |
1272 | ldconst -1,<reg> -> subo 1,0,<reg> | |
1273 | ldconst -31,<reg> -> subo 31,0,<reg> | |
1274 | ||
1275 | Anything else becomes: | |
1276 | lda xxx,<reg>. */ | |
1277 | n = offs (e); | |
1278 | if ((0 <= n) && (n <= 31)) | |
1279 | arg[0] = "mov"; | |
1280 | else if ((-31 <= n) && (n <= -1)) | |
252b5132 | 1281 | { |
ea1562b3 NC |
1282 | arg[0] = "subo"; |
1283 | arg[3] = arg[2]; | |
1284 | sprintf (buf, "%d", -n); | |
1285 | arg[1] = buf; | |
1286 | arg[2] = "0"; | |
1287 | } | |
1288 | else if ((32 <= n) && (n <= 62)) | |
1289 | { | |
1290 | arg[0] = "addo"; | |
1291 | arg[3] = arg[2]; | |
1292 | arg[1] = "31"; | |
1293 | sprintf (buf, "%d", n - 31); | |
1294 | arg[2] = buf; | |
252b5132 | 1295 | } |
ea1562b3 NC |
1296 | else if ((shift = shift_ok (n)) != 0) |
1297 | { | |
1298 | arg[0] = "shlo"; | |
1299 | arg[3] = arg[2]; | |
1300 | sprintf (buf, "%d", shift); | |
1301 | arg[1] = buf; | |
1302 | sprintf (buf2, "%d", n >> shift); | |
1303 | arg[2] = buf2; | |
1304 | } | |
1305 | else | |
1306 | arg[0] = "lda"; | |
1307 | break; | |
1308 | ||
1309 | case O_illegal: | |
1310 | as_bad (_("invalid constant")); | |
1311 | return -1; | |
1312 | break; | |
252b5132 | 1313 | } |
ea1562b3 NC |
1314 | return (arg[3] == 0) ? 2 : 3; |
1315 | } | |
252b5132 | 1316 | |
ea1562b3 | 1317 | /* reg_fmt: generate a REG-format instruction. */ |
252b5132 | 1318 | |
b9195351 | 1319 | static void |
ea1562b3 NC |
1320 | reg_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */ |
1321 | struct i960_opcode *oP)/* Pointer to description of instruction. */ | |
252b5132 | 1322 | { |
ea1562b3 NC |
1323 | long instr; /* Binary to be output. */ |
1324 | struct regop regop; /* Description of register operand. */ | |
1325 | int n_ops; /* Number of operands. */ | |
252b5132 | 1326 | |
ea1562b3 NC |
1327 | instr = oP->opcode; |
1328 | n_ops = oP->num_ops; | |
252b5132 | 1329 | |
ea1562b3 NC |
1330 | if (n_ops >= 1) |
1331 | { | |
1332 | parse_regop (®op, args[1], oP->operand[0]); | |
252b5132 | 1333 | |
ea1562b3 | 1334 | if ((n_ops == 1) && !(instr & M3)) |
252b5132 | 1335 | { |
ea1562b3 NC |
1336 | /* 1-operand instruction in which the dst field should |
1337 | be used (instead of src1). */ | |
1338 | regop.n <<= 19; | |
1339 | if (regop.special) | |
1340 | regop.mode = regop.special; | |
1341 | regop.mode <<= 13; | |
1342 | regop.special = 0; | |
252b5132 | 1343 | } |
ea1562b3 | 1344 | else |
252b5132 | 1345 | { |
ea1562b3 NC |
1346 | /* regop.n goes in bit 0, needs no shifting. */ |
1347 | regop.mode <<= 11; | |
1348 | regop.special <<= 5; | |
252b5132 | 1349 | } |
ea1562b3 | 1350 | instr |= regop.n | regop.mode | regop.special; |
252b5132 RH |
1351 | } |
1352 | ||
ea1562b3 NC |
1353 | if (n_ops >= 2) |
1354 | { | |
1355 | parse_regop (®op, args[2], oP->operand[1]); | |
252b5132 | 1356 | |
ea1562b3 NC |
1357 | if ((n_ops == 2) && !(instr & M3)) |
1358 | { | |
1359 | /* 2-operand instruction in which the dst field should | |
1360 | be used instead of src2). */ | |
1361 | regop.n <<= 19; | |
1362 | if (regop.special) | |
1363 | regop.mode = regop.special; | |
1364 | regop.mode <<= 13; | |
1365 | regop.special = 0; | |
1366 | } | |
1367 | else | |
1368 | { | |
1369 | regop.n <<= 14; | |
1370 | regop.mode <<= 12; | |
1371 | regop.special <<= 6; | |
1372 | } | |
1373 | instr |= regop.n | regop.mode | regop.special; | |
1374 | } | |
1375 | if (n_ops == 3) | |
1376 | { | |
1377 | parse_regop (®op, args[3], oP->operand[2]); | |
1378 | if (regop.special) | |
1379 | regop.mode = regop.special; | |
1380 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); | |
1381 | } | |
1382 | emit (instr); | |
252b5132 RH |
1383 | } |
1384 | ||
ea1562b3 | 1385 | /* get_args: break individual arguments out of comma-separated list |
252b5132 RH |
1386 | |
1387 | Input assumptions: | |
1388 | - all comments and labels have been removed | |
1389 | - all strings of whitespace have been collapsed to a single blank. | |
1390 | - all character constants ('x') have been replaced with decimal | |
1391 | ||
1392 | Output: | |
1393 | args[0] is untouched. args[1] points to first operand, etc. All args: | |
1394 | - are NULL-terminated | |
1395 | - contain no whitespace | |
1396 | ||
1397 | Return value: | |
ea1562b3 | 1398 | Number of operands (0,1,2, or 3) or -1 on error. */ |
252b5132 | 1399 | |
252b5132 | 1400 | static int |
ea1562b3 NC |
1401 | get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */ |
1402 | char *args[]) /* Output arg: pointers to operands placed in args[1-3]. | |
1403 | Must accommodate 4 entries (args[0-3]). */ | |
1404 | ||
252b5132 | 1405 | { |
ea1562b3 NC |
1406 | int n; /* Number of operands. */ |
1407 | char *to; | |
252b5132 | 1408 | |
ea1562b3 | 1409 | /* Skip lead white space. */ |
252b5132 | 1410 | while (*p == ' ') |
ea1562b3 | 1411 | p++; |
252b5132 RH |
1412 | |
1413 | if (*p == '\0') | |
ea1562b3 | 1414 | return 0; |
252b5132 RH |
1415 | |
1416 | n = 1; | |
1417 | args[1] = p; | |
1418 | ||
1419 | /* Squeze blanks out by moving non-blanks toward start of string. | |
ea1562b3 | 1420 | Isolate operands, whenever comma is found. */ |
252b5132 RH |
1421 | to = p; |
1422 | while (*p != '\0') | |
1423 | { | |
252b5132 | 1424 | if (*p == ' ' |
3882b010 L |
1425 | && (! ISALNUM (p[1]) |
1426 | || ! ISALNUM (p[-1]))) | |
ea1562b3 | 1427 | p++; |
252b5132 RH |
1428 | else if (*p == ',') |
1429 | { | |
ea1562b3 | 1430 | /* Start of operand. */ |
252b5132 RH |
1431 | if (n == 3) |
1432 | { | |
1433 | as_bad (_("too many operands")); | |
1434 | return -1; | |
1435 | } | |
ea1562b3 NC |
1436 | *to++ = '\0'; /* Terminate argument. */ |
1437 | args[++n] = to; /* Start next argument. */ | |
252b5132 | 1438 | p++; |
252b5132 RH |
1439 | } |
1440 | else | |
ea1562b3 | 1441 | *to++ = *p++; |
252b5132 RH |
1442 | } |
1443 | *to = '\0'; | |
1444 | return n; | |
1445 | } | |
1446 | ||
ea1562b3 | 1447 | /* i_scan: perform lexical scan of ascii assembler instruction. |
252b5132 | 1448 | |
ea1562b3 NC |
1449 | Input assumptions: |
1450 | - input string is an i80960 instruction (not a pseudo-op) | |
1451 | - all comments and labels have been removed | |
1452 | - all strings of whitespace have been collapsed to a single blank. | |
252b5132 | 1453 | |
ea1562b3 NC |
1454 | Output: |
1455 | args[0] points to opcode, other entries point to operands. All strings: | |
1456 | - are NULL-terminated | |
1457 | - contain no whitespace | |
1458 | - have character constants ('x') replaced with a decimal number | |
252b5132 RH |
1459 | |
1460 | Return value: | |
ea1562b3 | 1461 | Number of operands (0,1,2, or 3) or -1 on error. */ |
252b5132 | 1462 | |
252b5132 | 1463 | static int |
ea1562b3 NC |
1464 | i_scan (char *iP, /* Pointer to ascii instruction; Mucked by us. */ |
1465 | char *args[]) /* Output arg: pointers to opcode and operands placed here. | |
1466 | Must accommodate 4 entries. */ | |
252b5132 | 1467 | { |
ea1562b3 | 1468 | /* Isolate opcode. */ |
252b5132 | 1469 | if (*(iP) == ' ') |
ea1562b3 NC |
1470 | iP++; |
1471 | ||
252b5132 RH |
1472 | args[0] = iP; |
1473 | for (; *iP != ' '; iP++) | |
1474 | { | |
1475 | if (*iP == '\0') | |
1476 | { | |
ea1562b3 | 1477 | /* There are no operands. */ |
252b5132 RH |
1478 | if (args[0] == iP) |
1479 | { | |
ea1562b3 | 1480 | /* We never moved: there was no opcode either! */ |
252b5132 RH |
1481 | as_bad (_("missing opcode")); |
1482 | return -1; | |
1483 | } | |
1484 | return 0; | |
1485 | } | |
1486 | } | |
ea1562b3 | 1487 | *iP++ = '\0'; |
252b5132 | 1488 | return (get_args (iP, args)); |
ea1562b3 | 1489 | } |
252b5132 | 1490 | |
252b5132 | 1491 | static void |
ea1562b3 NC |
1492 | brcnt_emit (void) |
1493 | { | |
1494 | /* Emit call to "increment" routine. */ | |
1495 | ctrl_fmt (BR_CNT_FUNC, CALL, 1); | |
1496 | /* Emit inline counter to be incremented. */ | |
1497 | emit (0); | |
1498 | } | |
252b5132 | 1499 | |
ea1562b3 NC |
1500 | static char * |
1501 | brlab_next (void) | |
1502 | { | |
1503 | static char buf[20]; | |
252b5132 | 1504 | |
ea1562b3 NC |
1505 | sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++); |
1506 | return buf; | |
1507 | } | |
252b5132 | 1508 | |
ea1562b3 NC |
1509 | static void |
1510 | ctrl_fmt (char *targP, /* Pointer to text of lone operand (if any). */ | |
1511 | long opcode, /* Template of instruction. */ | |
1512 | int num_ops) /* Number of operands. */ | |
1513 | { | |
1514 | int instrument; /* TRUE iff we should add instrumentation to track | |
1515 | how often the branch is taken. */ | |
1516 | ||
1517 | if (num_ops == 0) | |
1518 | emit (opcode); /* Output opcode. */ | |
1519 | else | |
252b5132 | 1520 | { |
ea1562b3 NC |
1521 | instrument = instrument_branches && (opcode != CALL) |
1522 | && (opcode != B) && (opcode != RET) && (opcode != BAL); | |
252b5132 | 1523 | |
ea1562b3 | 1524 | if (instrument) |
252b5132 | 1525 | { |
ea1562b3 NC |
1526 | brcnt_emit (); |
1527 | colon (brlab_next ()); | |
252b5132 | 1528 | } |
ea1562b3 NC |
1529 | |
1530 | /* The operand MUST be an ip-relative displacement. Parse it | |
1531 | and set up address fix for the instruction we just output. */ | |
1532 | get_cdisp (targP, "CTRL", opcode, 24, 0, 0); | |
1533 | ||
1534 | if (instrument) | |
1535 | brcnt_emit (); | |
252b5132 | 1536 | } |
ea1562b3 | 1537 | } |
252b5132 | 1538 | |
ea1562b3 NC |
1539 | static void |
1540 | cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ | |
1541 | char *arg[], | |
1542 | /* Opcode, with branch-prediction bits already set if necessary. */ | |
1543 | long opcode, | |
1544 | /* Pointer to description of instruction. */ | |
1545 | struct i960_opcode *oP) | |
1546 | { | |
1547 | long instr; /* 32-bit instruction. */ | |
1548 | struct regop regop; /* Description of register operand. */ | |
1549 | int n; /* Number of operands. */ | |
1550 | int var_frag; /* 1 if varying length code fragment should | |
1551 | be emitted; 0 if an address fix | |
1552 | should be emitted. */ | |
252b5132 | 1553 | |
ea1562b3 NC |
1554 | instr = opcode; |
1555 | n = oP->num_ops; | |
252b5132 | 1556 | |
ea1562b3 | 1557 | if (n >= 1) |
252b5132 | 1558 | { |
ea1562b3 NC |
1559 | /* First operand (if any) of a COBR is always a register |
1560 | operand. Parse it. */ | |
1561 | parse_regop (®op, arg[1], oP->operand[0]); | |
1562 | instr |= (regop.n << 19) | (regop.mode << 13); | |
252b5132 RH |
1563 | } |
1564 | ||
ea1562b3 | 1565 | if (n >= 2) |
252b5132 | 1566 | { |
ea1562b3 NC |
1567 | /* Second operand (if any) of a COBR is always a register |
1568 | operand. Parse it. */ | |
1569 | parse_regop (®op, arg[2], oP->operand[1]); | |
1570 | instr |= (regop.n << 14) | regop.special; | |
1571 | } | |
252b5132 | 1572 | |
ea1562b3 NC |
1573 | if (n < 3) |
1574 | emit (instr); | |
1575 | else | |
1576 | { | |
1577 | if (instrument_branches) | |
252b5132 | 1578 | { |
ea1562b3 NC |
1579 | brcnt_emit (); |
1580 | colon (brlab_next ()); | |
252b5132 | 1581 | } |
252b5132 | 1582 | |
ea1562b3 NC |
1583 | /* A third operand to a COBR is always a displacement. Parse |
1584 | it; if it's relaxable (a cobr "j" directive, or any cobr | |
1585 | other than bbs/bbc when the "-norelax" option is not in use) | |
1586 | set up a variable code fragment; otherwise set up an address | |
1587 | fix. */ | |
1588 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ | |
1589 | get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0); | |
252b5132 | 1590 | |
ea1562b3 NC |
1591 | if (instrument_branches) |
1592 | brcnt_emit (); | |
252b5132 | 1593 | } |
ea1562b3 | 1594 | } |
252b5132 | 1595 | |
ea1562b3 NC |
1596 | /* Assumptions about the passed-in text: |
1597 | - all comments, labels removed | |
1598 | - text is an instruction | |
1599 | - all white space compressed to single blanks | |
1600 | - all character constants have been replaced with decimal. */ | |
252b5132 | 1601 | |
ea1562b3 NC |
1602 | void |
1603 | md_assemble (char *textP) | |
1604 | { | |
1605 | /* Parsed instruction text, containing NO whitespace: arg[0]->opcode | |
1606 | mnemonic arg[1-3]->operands, with char constants replaced by | |
1607 | decimal numbers. */ | |
1608 | char *args[4]; | |
1609 | /* Number of instruction operands. */ | |
1610 | int n_ops; | |
1611 | /* Pointer to instruction description. */ | |
1612 | struct i960_opcode *oP; | |
1613 | /* TRUE iff opcode mnemonic included branch-prediction suffix (".f" | |
1614 | or ".t"). */ | |
1615 | int branch_predict; | |
1616 | /* Setting of branch-prediction bit(s) to be OR'd into instruction | |
1617 | opcode of CTRL/COBR format instructions. */ | |
1618 | long bp_bits; | |
1619 | /* Offset of last character in opcode mnemonic. */ | |
1620 | int n; | |
1621 | const char *bp_error_msg = _("branch prediction invalid on this opcode"); | |
252b5132 | 1622 | |
ea1562b3 NC |
1623 | /* Parse instruction into opcode and operands. */ |
1624 | memset (args, '\0', sizeof (args)); | |
252b5132 | 1625 | |
ea1562b3 | 1626 | n_ops = i_scan (textP, args); |
252b5132 | 1627 | |
ea1562b3 NC |
1628 | if (n_ops == -1) |
1629 | return; /* Error message already issued. */ | |
252b5132 | 1630 | |
ea1562b3 NC |
1631 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction. */ |
1632 | if (!strcmp (args[0], "ldconst")) | |
252b5132 | 1633 | { |
ea1562b3 NC |
1634 | n_ops = parse_ldconst (args); |
1635 | if (n_ops == -1) | |
1636 | return; | |
252b5132 RH |
1637 | } |
1638 | ||
ea1562b3 NC |
1639 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off. */ |
1640 | n = strlen (args[0]) - 1; | |
1641 | branch_predict = 0; | |
1642 | bp_bits = 0; | |
252b5132 | 1643 | |
ea1562b3 | 1644 | if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')) |
252b5132 | 1645 | { |
ea1562b3 NC |
1646 | /* We could check here to see if the target architecture |
1647 | supports branch prediction, but why bother? The bit will | |
1648 | just be ignored by processors that don't use it. */ | |
1649 | branch_predict = 1; | |
1650 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; | |
1651 | args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */ | |
252b5132 | 1652 | } |
252b5132 | 1653 | |
ea1562b3 NC |
1654 | /* Look up opcode mnemonic in table and check number of operands. |
1655 | Check that opcode is legal for the target architecture. If all | |
1656 | looks good, assemble instruction. */ | |
1657 | oP = (struct i960_opcode *) hash_find (op_hash, args[0]); | |
1658 | if (!oP || !targ_has_iclass (oP->iclass)) | |
1659 | as_bad (_("invalid opcode, \"%s\"."), args[0]); | |
1660 | else if (n_ops != oP->num_ops) | |
1661 | as_bad (_("improper number of operands. expecting %d, got %d"), | |
1662 | oP->num_ops, n_ops); | |
1663 | else | |
252b5132 | 1664 | { |
ea1562b3 | 1665 | switch (oP->format) |
252b5132 | 1666 | { |
ea1562b3 NC |
1667 | case FBRA: |
1668 | case CTRL: | |
1669 | ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops); | |
1670 | if (oP->format == FBRA) | |
1671 | /* Now generate a 'bno' to same arg */ | |
1672 | ctrl_fmt (args[1], BNO | bp_bits, 1); | |
252b5132 | 1673 | break; |
ea1562b3 NC |
1674 | case COBR: |
1675 | case COJ: | |
1676 | cobr_fmt (args, oP->opcode | bp_bits, oP); | |
252b5132 | 1677 | break; |
ea1562b3 NC |
1678 | case REG: |
1679 | if (branch_predict) | |
1680 | as_warn (bp_error_msg); | |
1681 | reg_fmt (args, oP); | |
252b5132 | 1682 | break; |
ea1562b3 NC |
1683 | case MEM1: |
1684 | if (args[0][0] == 'c' && args[0][1] == 'a') | |
1685 | { | |
1686 | if (branch_predict) | |
1687 | as_warn (bp_error_msg); | |
1688 | mem_fmt (args, oP, 1); | |
1689 | break; | |
1690 | } | |
1691 | case MEM2: | |
1692 | case MEM4: | |
1693 | case MEM8: | |
1694 | case MEM12: | |
1695 | case MEM16: | |
1696 | if (branch_predict) | |
1697 | as_warn (bp_error_msg); | |
1698 | mem_fmt (args, oP, 0); | |
252b5132 | 1699 | break; |
ea1562b3 NC |
1700 | case CALLJ: |
1701 | if (branch_predict) | |
1702 | as_warn (bp_error_msg); | |
1703 | /* Output opcode & set up "fixup" (relocation); flag | |
1704 | relocation as 'callj' type. */ | |
1705 | know (oP->num_ops == 1); | |
1706 | get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1); | |
252b5132 RH |
1707 | break; |
1708 | default: | |
ea1562b3 NC |
1709 | BAD_CASE (oP->format); |
1710 | break; | |
252b5132 | 1711 | } |
252b5132 | 1712 | } |
ea1562b3 | 1713 | } |
252b5132 | 1714 | |
ea1562b3 NC |
1715 | void |
1716 | md_number_to_chars (char *buf, | |
1717 | valueT value, | |
1718 | int n) | |
1719 | { | |
1720 | number_to_chars_littleendian (buf, value, n); | |
1721 | } | |
252b5132 | 1722 | |
ea1562b3 NC |
1723 | #define MAX_LITTLENUMS 6 |
1724 | #define LNUM_SIZE sizeof (LITTLENUM_TYPE) | |
252b5132 | 1725 | |
ea1562b3 | 1726 | /* md_atof: convert ascii to floating point |
252b5132 | 1727 | |
ea1562b3 NC |
1728 | Turn a string at input_line_pointer into a floating point constant of type |
1729 | 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS | |
1730 | emitted is returned at 'sizeP'. An error message is returned, or a pointer | |
1731 | to an empty message if OK. | |
252b5132 | 1732 | |
ea1562b3 NC |
1733 | Note we call the i386 floating point routine, rather than complicating |
1734 | things with more files or symbolic links. */ | |
252b5132 | 1735 | |
ea1562b3 NC |
1736 | char * |
1737 | md_atof (int type, char *litP, int *sizeP) | |
252b5132 | 1738 | { |
ea1562b3 NC |
1739 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
1740 | LITTLENUM_TYPE *wordP; | |
1741 | int prec; | |
1742 | char *t; | |
252b5132 | 1743 | |
ea1562b3 | 1744 | switch (type) |
252b5132 | 1745 | { |
ea1562b3 NC |
1746 | case 'f': |
1747 | case 'F': | |
1748 | prec = 2; | |
1749 | break; | |
252b5132 | 1750 | |
ea1562b3 NC |
1751 | case 'd': |
1752 | case 'D': | |
1753 | prec = 4; | |
252b5132 | 1754 | break; |
ea1562b3 NC |
1755 | |
1756 | case 't': | |
1757 | case 'T': | |
1758 | prec = 5; | |
1759 | type = 'x'; /* That's what atof_ieee() understands. */ | |
252b5132 | 1760 | break; |
ea1562b3 | 1761 | |
252b5132 | 1762 | default: |
ea1562b3 NC |
1763 | *sizeP = 0; |
1764 | return _("Bad call to md_atof()"); | |
252b5132 RH |
1765 | } |
1766 | ||
ea1562b3 NC |
1767 | t = atof_ieee (input_line_pointer, type, words); |
1768 | if (t) | |
1769 | input_line_pointer = t; | |
252b5132 | 1770 | |
ea1562b3 | 1771 | *sizeP = prec * LNUM_SIZE; |
252b5132 | 1772 | |
ea1562b3 NC |
1773 | /* Output the LITTLENUMs in REVERSE order in accord with i80960 |
1774 | word-order. (Dunno why atof_ieee doesn't do it in the right | |
1775 | order in the first place -- probably because it's a hack of | |
1776 | atof_m68k.) */ | |
1777 | for (wordP = words + prec - 1; prec--;) | |
1778 | { | |
1779 | md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE); | |
1780 | litP += sizeof (LITTLENUM_TYPE); | |
252b5132 RH |
1781 | } |
1782 | ||
ea1562b3 NC |
1783 | return 0; |
1784 | } | |
252b5132 | 1785 | |
ea1562b3 NC |
1786 | static void |
1787 | md_number_to_imm (char *buf, long val, int n) | |
1788 | { | |
1789 | md_number_to_chars (buf, val, n); | |
1790 | } | |
252b5132 | 1791 | |
252b5132 | 1792 | static void |
ea1562b3 NC |
1793 | md_number_to_field (char *instrP, /* Pointer to instruction to be fixed. */ |
1794 | long val, /* Address fixup value. */ | |
1795 | bit_fixS *bfixP) /* Description of bit field to be fixed up. */ | |
252b5132 | 1796 | { |
ea1562b3 NC |
1797 | int numbits; /* Length of bit field to be fixed. */ |
1798 | long instr; /* 32-bit instruction to be fixed-up. */ | |
1799 | long sign; /* 0 or -1, according to sign bit of 'val'. */ | |
252b5132 | 1800 | |
ea1562b3 NC |
1801 | /* Convert instruction back to host byte order. */ |
1802 | instr = md_chars_to_number (instrP, 4); | |
252b5132 | 1803 | |
ea1562b3 NC |
1804 | /* Surprise! -- we stored the number of bits to be modified rather |
1805 | than a pointer to a structure. */ | |
1806 | numbits = (int) (size_t) bfixP; | |
1807 | if (numbits == 1) | |
1808 | /* This is a no-op, stuck here by reloc_callj(). */ | |
1809 | return; | |
252b5132 | 1810 | |
ea1562b3 | 1811 | know ((numbits == 13) || (numbits == 24)); |
252b5132 | 1812 | |
ea1562b3 NC |
1813 | /* Propagate sign bit of 'val' for the given number of bits. Result |
1814 | should be all 0 or all 1. */ | |
1815 | sign = val >> ((int) numbits - 1); | |
1816 | if (((val < 0) && (sign != -1)) | |
1817 | || ((val > 0) && (sign != 0))) | |
1818 | as_bad (_("Fixup of %ld too large for field width of %d"), | |
1819 | val, numbits); | |
1820 | else | |
252b5132 | 1821 | { |
ea1562b3 NC |
1822 | /* Put bit field into instruction and write back in target |
1823 | * byte order. */ | |
1824 | val &= ~(-1 << (int) numbits); /* Clear unused sign bits. */ | |
1825 | instr |= val; | |
1826 | md_number_to_chars (instrP, instr, 4); | |
252b5132 | 1827 | } |
ea1562b3 NC |
1828 | } |
1829 | \f | |
1830 | ||
1831 | /* md_parse_option | |
1832 | Invocation line includes a switch not recognized by the base assembler. | |
1833 | See if it's a processor-specific option. For the 960, these are: | |
1834 | ||
1835 | -norelax: | |
1836 | Conditional branch instructions that require displacements | |
1837 | greater than 13 bits (or that have external targets) should | |
1838 | generate errors. The default is to replace each such | |
1839 | instruction with the corresponding compare (or chkbit) and | |
1840 | branch instructions. Note that the Intel "j" cobr directives | |
1841 | are ALWAYS "de-optimized" in this way when necessary, | |
1842 | regardless of the setting of this option. | |
1843 | ||
1844 | -b: | |
1845 | Add code to collect information about branches taken, for | |
1846 | later optimization of branch prediction bits by a separate | |
1847 | tool. COBR and CNTL format instructions have branch | |
1848 | prediction bits (in the CX architecture); if "BR" represents | |
1849 | an instruction in one of these classes, the following rep- | |
1850 | resents the code generated by the assembler: | |
1851 | ||
1852 | call <increment routine> | |
1853 | .word 0 # pre-counter | |
1854 | Label: BR | |
1855 | call <increment routine> | |
1856 | .word 0 # post-counter | |
1857 | ||
1858 | A table of all such "Labels" is also generated. | |
1859 | ||
1860 | -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: | |
1861 | Select the 80960 architecture. Instructions or features not | |
1862 | supported by the selected architecture cause fatal errors. | |
1863 | The default is to generate code for any instruction or feature | |
1864 | that is supported by SOME version of the 960 (even if this | |
1865 | means mixing architectures!). */ | |
1866 | ||
1867 | const char *md_shortopts = "A:b"; | |
1868 | struct option md_longopts[] = | |
1869 | { | |
1870 | #define OPTION_LINKRELAX (OPTION_MD_BASE) | |
1871 | {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, | |
1872 | {"link-relax", no_argument, NULL, OPTION_LINKRELAX}, | |
1873 | #define OPTION_NORELAX (OPTION_MD_BASE + 1) | |
1874 | {"norelax", no_argument, NULL, OPTION_NORELAX}, | |
1875 | {"no-relax", no_argument, NULL, OPTION_NORELAX}, | |
1876 | {NULL, no_argument, NULL, 0} | |
1877 | }; | |
1878 | size_t md_longopts_size = sizeof (md_longopts); | |
1879 | ||
1880 | struct tabentry | |
1881 | { | |
1882 | char *flag; | |
1883 | int arch; | |
1884 | }; | |
1885 | static const struct tabentry arch_tab[] = | |
1886 | { | |
1887 | {"KA", ARCH_KA}, | |
1888 | {"KB", ARCH_KB}, | |
1889 | {"SA", ARCH_KA}, /* Synonym for KA. */ | |
1890 | {"SB", ARCH_KB}, /* Synonym for KB. */ | |
1891 | {"KC", ARCH_MC}, /* Synonym for MC. */ | |
1892 | {"MC", ARCH_MC}, | |
1893 | {"CA", ARCH_CA}, | |
1894 | {"JX", ARCH_JX}, | |
1895 | {"HX", ARCH_HX}, | |
1896 | {NULL, 0} | |
1897 | }; | |
1898 | ||
1899 | int | |
1900 | md_parse_option (int c, char *arg) | |
1901 | { | |
1902 | switch (c) | |
252b5132 | 1903 | { |
ea1562b3 NC |
1904 | case OPTION_LINKRELAX: |
1905 | linkrelax = 1; | |
1906 | flag_keep_locals = 1; | |
1907 | break; | |
1908 | ||
1909 | case OPTION_NORELAX: | |
1910 | norelax = 1; | |
1911 | break; | |
1912 | ||
1913 | case 'b': | |
1914 | instrument_branches = 1; | |
1915 | break; | |
1916 | ||
1917 | case 'A': | |
1918 | { | |
1919 | const struct tabentry *tp; | |
1920 | char *p = arg; | |
1921 | ||
1922 | for (tp = arch_tab; tp->flag != NULL; tp++) | |
1923 | if (!strcmp (p, tp->flag)) | |
1924 | break; | |
1925 | ||
1926 | if (tp->flag == NULL) | |
1927 | { | |
1928 | as_bad (_("invalid architecture %s"), p); | |
1929 | return 0; | |
1930 | } | |
1931 | else | |
1932 | architecture = tp->arch; | |
1933 | } | |
1934 | break; | |
1935 | ||
1936 | default: | |
1937 | return 0; | |
252b5132 | 1938 | } |
ea1562b3 NC |
1939 | |
1940 | return 1; | |
252b5132 RH |
1941 | } |
1942 | ||
ea1562b3 NC |
1943 | void |
1944 | md_show_usage (FILE *stream) | |
1945 | { | |
1946 | int i; | |
252b5132 | 1947 | |
ea1562b3 NC |
1948 | fprintf (stream, _("I960 options:\n")); |
1949 | for (i = 0; arch_tab[i].flag; i++) | |
1950 | fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag); | |
1951 | fprintf (stream, _("\n\ | |
1952 | specify variant of 960 architecture\n\ | |
1953 | -b add code to collect statistics about branches taken\n\ | |
1954 | -link-relax preserve individual alignment directives so linker\n\ | |
1955 | can do relaxing (b.out format only)\n\ | |
1956 | -no-relax don't alter compare-and-branch instructions for\n\ | |
1957 | long displacements\n")); | |
1958 | } | |
1959 | \f | |
1960 | /* relax_cobr: | |
1961 | Replace cobr instruction in a code fragment with equivalent branch and | |
1962 | compare instructions, so it can reach beyond a 13-bit displacement. | |
1963 | Set up an address fix/relocation for the new branch instruction. */ | |
252b5132 RH |
1964 | |
1965 | /* This "conditional jump" table maps cobr instructions into | |
1966 | equivalent compare and branch opcodes. */ | |
ea1562b3 | 1967 | |
252b5132 RH |
1968 | static const |
1969 | struct | |
1970 | { | |
1971 | long compare; | |
1972 | long branch; | |
1973 | } | |
1974 | ||
1975 | coj[] = | |
1976 | { /* COBR OPCODE: */ | |
1977 | { CHKBIT, BNO }, /* 0x30 - bbc */ | |
1978 | { CMPO, BG }, /* 0x31 - cmpobg */ | |
1979 | { CMPO, BE }, /* 0x32 - cmpobe */ | |
1980 | { CMPO, BGE }, /* 0x33 - cmpobge */ | |
1981 | { CMPO, BL }, /* 0x34 - cmpobl */ | |
1982 | { CMPO, BNE }, /* 0x35 - cmpobne */ | |
1983 | { CMPO, BLE }, /* 0x36 - cmpoble */ | |
1984 | { CHKBIT, BO }, /* 0x37 - bbs */ | |
1985 | { CMPI, BNO }, /* 0x38 - cmpibno */ | |
1986 | { CMPI, BG }, /* 0x39 - cmpibg */ | |
1987 | { CMPI, BE }, /* 0x3a - cmpibe */ | |
1988 | { CMPI, BGE }, /* 0x3b - cmpibge */ | |
1989 | { CMPI, BL }, /* 0x3c - cmpibl */ | |
1990 | { CMPI, BNE }, /* 0x3d - cmpibne */ | |
1991 | { CMPI, BLE }, /* 0x3e - cmpible */ | |
1992 | { CMPI, BO }, /* 0x3f - cmpibo */ | |
1993 | }; | |
1994 | ||
b9195351 | 1995 | static void |
ea1562b3 NC |
1996 | relax_cobr (fragS *fragP) /* fragP->fr_opcode is assumed to point to |
1997 | the cobr instruction, which comes at the | |
1998 | end of the code fragment. */ | |
252b5132 RH |
1999 | { |
2000 | int opcode, src1, src2, m1, s2; | |
ea1562b3 NC |
2001 | /* Bit fields from cobr instruction. */ |
2002 | long bp_bits; /* Branch prediction bits from cobr instruction. */ | |
2003 | long instr; /* A single i960 instruction. */ | |
2004 | /* ->instruction to be replaced. */ | |
252b5132 | 2005 | char *iP; |
ea1562b3 | 2006 | fixS *fixP; /* Relocation that can be done at assembly time. */ |
252b5132 | 2007 | |
ea1562b3 | 2008 | /* Pick up & parse cobr instruction. */ |
252b5132 RH |
2009 | iP = fragP->fr_opcode; |
2010 | instr = md_chars_to_number (iP, 4); | |
ea1562b3 | 2011 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index. */ |
252b5132 RH |
2012 | src1 = (instr >> 19) & 0x1f; |
2013 | m1 = (instr >> 13) & 1; | |
2014 | s2 = instr & 1; | |
2015 | src2 = (instr >> 14) & 0x1f; | |
2016 | bp_bits = instr & BP_MASK; | |
2017 | ||
ea1562b3 | 2018 | /* Generate and output compare instruction. */ |
252b5132 RH |
2019 | instr = coj[opcode].compare |
2020 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); | |
2021 | md_number_to_chars (iP, instr, 4); | |
2022 | ||
ea1562b3 | 2023 | /* Output branch instruction. */ |
252b5132 RH |
2024 | md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4); |
2025 | ||
ea1562b3 | 2026 | /* Set up address fixup/relocation. */ |
252b5132 RH |
2027 | fixP = fix_new (fragP, |
2028 | iP + 4 - fragP->fr_literal, | |
2029 | 4, | |
2030 | fragP->fr_symbol, | |
2031 | fragP->fr_offset, | |
2032 | 1, | |
2033 | NO_RELOC); | |
2034 | ||
ea1562b3 NC |
2035 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field. */ |
2036 | ||
2037 | fragP->fr_fix += 4; | |
2038 | frag_wane (fragP); | |
2039 | } | |
2040 | ||
2041 | /* md_convert_frag: | |
2042 | ||
2043 | Called by base assembler after address relaxation is finished: modify | |
2044 | variable fragments according to how much relaxation was done. | |
2045 | ||
2046 | If the fragment substate is still 1, a 13-bit displacement was enough | |
2047 | to reach the symbol in question. Set up an address fixup, but otherwise | |
2048 | leave the cobr instruction alone. | |
2049 | ||
2050 | If the fragment substate is 2, a 13-bit displacement was not enough. | |
2051 | Replace the cobr with a two instructions (a compare and a branch). */ | |
2052 | ||
2053 | #ifndef BFD_ASSEMBLER | |
2054 | void | |
2055 | md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED, | |
2056 | segT seg ATTRIBUTE_UNUSED, | |
2057 | fragS *fragP) | |
2058 | #else | |
2059 | void | |
2060 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, | |
2061 | segT sec ATTRIBUTE_UNUSED, | |
2062 | fragS *fragP) | |
2063 | #endif | |
2064 | { | |
2065 | /* Structure describing needed address fix. */ | |
2066 | fixS *fixP; | |
2067 | ||
2068 | switch (fragP->fr_subtype) | |
2069 | { | |
2070 | case 1: | |
2071 | /* Leave single cobr instruction. */ | |
2072 | fixP = fix_new (fragP, | |
2073 | fragP->fr_opcode - fragP->fr_literal, | |
2074 | 4, | |
2075 | fragP->fr_symbol, | |
2076 | fragP->fr_offset, | |
2077 | 1, | |
2078 | NO_RELOC); | |
2079 | ||
2080 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* Size of bit field. */ | |
2081 | break; | |
2082 | case 2: | |
2083 | /* Replace cobr with compare/branch instructions. */ | |
2084 | relax_cobr (fragP); | |
2085 | break; | |
2086 | default: | |
2087 | BAD_CASE (fragP->fr_subtype); | |
2088 | break; | |
2089 | } | |
2090 | } | |
2091 | ||
2092 | /* md_estimate_size_before_relax: How much does it look like *fragP will grow? | |
2093 | ||
2094 | Called by base assembler just before address relaxation. | |
2095 | Return the amount by which the fragment will grow. | |
2096 | ||
2097 | Any symbol that is now undefined will not become defined; cobr's | |
2098 | based on undefined symbols will have to be replaced with a compare | |
2099 | instruction and a branch instruction, and the code fragment will grow | |
2100 | by 4 bytes. */ | |
2101 | ||
2102 | int | |
2103 | md_estimate_size_before_relax (fragS *fragP, segT segment_type) | |
2104 | { | |
2105 | /* If symbol is undefined in this segment, go to "relaxed" state | |
2106 | (compare and branch instructions instead of cobr) right now. */ | |
2107 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type) | |
2108 | { | |
2109 | relax_cobr (fragP); | |
2110 | return 4; | |
2111 | } | |
2112 | ||
2113 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
2114 | } | |
2115 | ||
2116 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
2117 | ||
2118 | /* md_ri_to_chars: | |
2119 | This routine exists in order to overcome machine byte-order problems | |
2120 | when dealing with bit-field entries in the relocation_info struct. | |
252b5132 | 2121 | |
ea1562b3 NC |
2122 | But relocation info will be used on the host machine only (only |
2123 | executable code is actually downloaded to the i80960). Therefore, | |
2124 | we leave it in host byte order. */ | |
2125 | ||
2126 | static void | |
2127 | md_ri_to_chars (char *where, struct relocation_info *ri) | |
2128 | { | |
2129 | host_number_to_chars (where, ri->r_address, 4); | |
2130 | host_number_to_chars (where + 4, ri->r_index, 3); | |
2131 | #if WORDS_BIGENDIAN | |
2132 | where[7] = (ri->r_pcrel << 7 | |
2133 | | ri->r_length << 5 | |
2134 | | ri->r_extern << 4 | |
2135 | | ri->r_bsr << 3 | |
2136 | | ri->r_disp << 2 | |
2137 | | ri->r_callj << 1 | |
2138 | | ri->nuthin << 0); | |
2139 | #else | |
2140 | where[7] = (ri->r_pcrel << 0 | |
2141 | | ri->r_length << 1 | |
2142 | | ri->r_extern << 3 | |
2143 | | ri->r_bsr << 4 | |
2144 | | ri->r_disp << 5 | |
2145 | | ri->r_callj << 6 | |
2146 | | ri->nuthin << 7); | |
2147 | #endif | |
252b5132 RH |
2148 | } |
2149 | ||
ea1562b3 | 2150 | #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */ |
252b5132 | 2151 | |
ea1562b3 NC |
2152 | \f |
2153 | /* brtab_emit: generate the fetch-prediction branch table. | |
252b5132 | 2154 | |
ea1562b3 NC |
2155 | See the comments above the declaration of 'br_cnt' for details on |
2156 | branch-prediction instrumentation. | |
252b5132 | 2157 | |
ea1562b3 NC |
2158 | The code emitted here would be functionally equivalent to the following |
2159 | example assembler source. | |
252b5132 | 2160 | |
ea1562b3 NC |
2161 | .data |
2162 | .align 2 | |
2163 | BR_TAB_NAME: | |
2164 | .word 0 # link to next table | |
2165 | .word 3 # length of table | |
2166 | .word LBRANCH0 # 1st entry in table proper | |
2167 | .word LBRANCH1 | |
2168 | .word LBRANCH2 */ | |
252b5132 | 2169 | |
ea1562b3 NC |
2170 | void |
2171 | brtab_emit (void) | |
252b5132 | 2172 | { |
ea1562b3 NC |
2173 | int i; |
2174 | char buf[20]; | |
2175 | /* Where the binary was output to. */ | |
2176 | char *p; | |
2177 | /* Pointer to description of deferred address fixup. */ | |
2178 | fixS *fixP; | |
252b5132 | 2179 | |
ea1562b3 NC |
2180 | if (!instrument_branches) |
2181 | return; | |
252b5132 | 2182 | |
ea1562b3 NC |
2183 | subseg_set (data_section, 0); /* .data */ |
2184 | frag_align (2, 0, 0); /* .align 2 */ | |
2185 | record_alignment (now_seg, 2); | |
2186 | colon (BR_TAB_NAME); /* BR_TAB_NAME: */ | |
2187 | emit (0); /* .word 0 #link to next table */ | |
2188 | emit (br_cnt); /* .word n #length of table */ | |
252b5132 | 2189 | |
ea1562b3 | 2190 | for (i = 0; i < br_cnt; i++) |
252b5132 | 2191 | { |
ea1562b3 NC |
2192 | sprintf (buf, "%s%d", BR_LABEL_BASE, i); |
2193 | p = emit (0); | |
2194 | fixP = fix_new (frag_now, | |
2195 | p - frag_now->fr_literal, | |
2196 | 4, symbol_find (buf), 0, 0, NO_RELOC); | |
252b5132 | 2197 | } |
252b5132 RH |
2198 | } |
2199 | ||
ea1562b3 | 2200 | /* s_leafproc: process .leafproc pseudo-op |
252b5132 RH |
2201 | |
2202 | .leafproc takes two arguments, the second one is optional: | |
2203 | arg[1]: name of 'call' entry point to leaf procedure | |
2204 | arg[2]: name of 'bal' entry point to leaf procedure | |
2205 | ||
2206 | If the two arguments are identical, or if the second one is missing, | |
2207 | the first argument is taken to be the 'bal' entry point. | |
2208 | ||
2209 | If there are 2 distinct arguments, we must make sure that the 'bal' | |
2210 | entry point immediately follows the 'call' entry point in the linked | |
ea1562b3 | 2211 | list of symbols. */ |
252b5132 | 2212 | |
252b5132 | 2213 | static void |
ea1562b3 NC |
2214 | s_leafproc (int n_ops, /* Number of operands. */ |
2215 | char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */ | |
252b5132 | 2216 | { |
ea1562b3 NC |
2217 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol. */ |
2218 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol. */ | |
252b5132 RH |
2219 | |
2220 | if ((n_ops != 1) && (n_ops != 2)) | |
2221 | { | |
2222 | as_bad (_("should have 1 or 2 operands")); | |
2223 | return; | |
ea1562b3 | 2224 | } |
252b5132 | 2225 | |
92774660 | 2226 | /* Find or create symbol for 'call' entry point. */ |
252b5132 RH |
2227 | callP = symbol_find_or_make (args[1]); |
2228 | ||
2229 | if (TC_S_IS_CALLNAME (callP)) | |
ea1562b3 | 2230 | as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP)); |
252b5132 RH |
2231 | |
2232 | /* If that was the only argument, use it as the 'bal' entry point. | |
ea1562b3 NC |
2233 | Otherwise, mark it as the 'call' entry point and find or create |
2234 | another symbol for the 'bal' entry point. */ | |
252b5132 RH |
2235 | if ((n_ops == 1) || !strcmp (args[1], args[2])) |
2236 | { | |
2237 | TC_S_FORCE_TO_BALNAME (callP); | |
252b5132 RH |
2238 | } |
2239 | else | |
2240 | { | |
2241 | TC_S_FORCE_TO_CALLNAME (callP); | |
2242 | ||
2243 | balP = symbol_find_or_make (args[2]); | |
2244 | if (TC_S_IS_CALLNAME (balP)) | |
ea1562b3 NC |
2245 | as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP)); |
2246 | ||
252b5132 RH |
2247 | TC_S_FORCE_TO_BALNAME (balP); |
2248 | ||
76171f81 | 2249 | #ifndef OBJ_ELF |
252b5132 | 2250 | tc_set_bal_of_call (callP, balP); |
76171f81 | 2251 | #endif |
ea1562b3 | 2252 | } |
252b5132 RH |
2253 | } |
2254 | ||
ea1562b3 | 2255 | /* s_sysproc: process .sysproc pseudo-op |
252b5132 | 2256 | |
ea1562b3 NC |
2257 | .sysproc takes two arguments: |
2258 | arg[1]: name of entry point to system procedure | |
2259 | arg[2]: 'entry_num' (index) of system procedure in the range | |
2260 | [0,31] inclusive. | |
2261 | ||
2262 | For [ab].out, we store the 'entrynum' in the 'n_other' field of | |
2263 | the symbol. Since that entry is normally 0, we bias 'entrynum' | |
2264 | by adding 1 to it. It must be unbiased before it is used. */ | |
252b5132 | 2265 | |
252b5132 | 2266 | static void |
ea1562b3 NC |
2267 | s_sysproc (int n_ops, /* Number of operands. */ |
2268 | char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */ | |
252b5132 RH |
2269 | { |
2270 | expressionS exp; | |
2271 | symbolS *symP; | |
2272 | ||
2273 | if (n_ops != 2) | |
2274 | { | |
2275 | as_bad (_("should have two operands")); | |
2276 | return; | |
ea1562b3 | 2277 | } |
252b5132 | 2278 | |
92774660 | 2279 | /* Parse "entry_num" argument and check it for validity. */ |
252b5132 RH |
2280 | parse_expr (args[2], &exp); |
2281 | if (exp.X_op != O_constant | |
2282 | || (offs (exp) < 0) | |
2283 | || (offs (exp) > 31)) | |
2284 | { | |
2285 | as_bad (_("'entry_num' must be absolute number in [0,31]")); | |
2286 | return; | |
2287 | } | |
2288 | ||
ea1562b3 | 2289 | /* Find/make symbol and stick entry number (biased by +1) into it. */ |
252b5132 RH |
2290 | symP = symbol_find_or_make (args[1]); |
2291 | ||
2292 | if (TC_S_IS_SYSPROC (symP)) | |
ea1562b3 | 2293 | as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP)); |
252b5132 | 2294 | |
ea1562b3 | 2295 | TC_S_SET_SYSPROC (symP, offs (exp)); /* Encode entry number. */ |
252b5132 RH |
2296 | TC_S_FORCE_TO_SYSPROC (symP); |
2297 | } | |
2298 | ||
ea1562b3 | 2299 | /* parse_po: parse machine-dependent pseudo-op |
252b5132 | 2300 | |
ea1562b3 NC |
2301 | This is a top-level routine for machine-dependent pseudo-ops. It slurps |
2302 | up the rest of the input line, breaks out the individual arguments, | |
2303 | and dispatches them to the correct handler. */ | |
252b5132 | 2304 | |
ea1562b3 NC |
2305 | static void |
2306 | parse_po (int po_num) /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC. */ | |
252b5132 | 2307 | { |
ea1562b3 NC |
2308 | /* Pointers operands, with no embedded whitespace. |
2309 | arg[0] unused, arg[1-3]->operands. */ | |
2310 | char *args[4]; | |
2311 | int n_ops; /* Number of operands. */ | |
2312 | char *p; /* Pointer to beginning of unparsed argument string. */ | |
2313 | char eol; /* Character that indicated end of line. */ | |
252b5132 | 2314 | |
ea1562b3 | 2315 | extern char is_end_of_line[]; |
252b5132 | 2316 | |
ea1562b3 NC |
2317 | /* Advance input pointer to end of line. */ |
2318 | p = input_line_pointer; | |
2319 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2320 | input_line_pointer++; | |
252b5132 | 2321 | |
ea1562b3 NC |
2322 | eol = *input_line_pointer; /* Save end-of-line char. */ |
2323 | *input_line_pointer = '\0'; /* Terminate argument list. */ | |
2324 | ||
2325 | /* Parse out operands. */ | |
2326 | n_ops = get_args (p, args); | |
2327 | if (n_ops == -1) | |
2328 | return; | |
2329 | ||
2330 | /* Dispatch to correct handler. */ | |
2331 | switch (po_num) | |
252b5132 | 2332 | { |
ea1562b3 NC |
2333 | case S_SYSPROC: |
2334 | s_sysproc (n_ops, args); | |
2335 | break; | |
2336 | case S_LEAFPROC: | |
2337 | s_leafproc (n_ops, args); | |
2338 | break; | |
2339 | default: | |
2340 | BAD_CASE (po_num); | |
2341 | break; | |
252b5132 | 2342 | } |
ea1562b3 NC |
2343 | |
2344 | /* Restore eol, so line numbers get updated correctly. Base | |
2345 | assembler assumes we leave input pointer pointing at char | |
2346 | following the eol. */ | |
2347 | *input_line_pointer++ = eol; | |
252b5132 RH |
2348 | } |
2349 | ||
ea1562b3 | 2350 | /* reloc_callj: Relocate a 'callj' instruction |
252b5132 | 2351 | |
ea1562b3 NC |
2352 | This is a "non-(GNU)-standard" machine-dependent hook. The base |
2353 | assembler calls it when it decides it can relocate an address at | |
2354 | assembly time instead of emitting a relocation directive. | |
252b5132 | 2355 | |
ea1562b3 NC |
2356 | Check to see if the relocation involves a 'callj' instruction to a: |
2357 | sysproc: Replace the default 'call' instruction with a 'calls' | |
2358 | leafproc: Replace the default 'call' instruction with a 'bal'. | |
2359 | other proc: Do nothing. | |
252b5132 | 2360 | |
ea1562b3 | 2361 | See b.out.h for details on the 'n_other' field in a symbol structure. |
252b5132 | 2362 | |
ea1562b3 NC |
2363 | IMPORTANT!: |
2364 | Assumes the caller has already figured out, in the case of a leafproc, | |
2365 | to use the 'bal' entry point, and has substituted that symbol into the | |
2366 | passed fixup structure. */ | |
2367 | ||
2368 | int | |
2369 | reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */ | |
252b5132 | 2370 | { |
ea1562b3 NC |
2371 | /* Points to the binary for the instruction being relocated. */ |
2372 | char *where; | |
252b5132 | 2373 | |
ea1562b3 NC |
2374 | if (!fixP->fx_tcbit) |
2375 | /* This wasn't a callj instruction in the first place. */ | |
2376 | return 0; | |
252b5132 | 2377 | |
ea1562b3 NC |
2378 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
2379 | ||
2380 | if (TC_S_IS_SYSPROC (fixP->fx_addsy)) | |
252b5132 | 2381 | { |
ea1562b3 NC |
2382 | /* Symbol is a .sysproc: replace 'call' with 'calls'. System |
2383 | procedure number is (other-1). */ | |
2384 | md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4); | |
2385 | ||
2386 | /* Nothing else needs to be done for this instruction. Make | |
2387 | sure 'md_number_to_field()' will perform a no-op. */ | |
2388 | fixP->fx_bit_fixP = (bit_fixS *) 1; | |
2389 | } | |
2390 | else if (TC_S_IS_CALLNAME (fixP->fx_addsy)) | |
2391 | { | |
2392 | /* Should not happen: see block comment above. */ | |
2393 | as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy)); | |
2394 | } | |
2395 | else if (TC_S_IS_BALNAME (fixP->fx_addsy)) | |
2396 | { | |
2397 | /* Replace 'call' with 'bal'; both instructions have the same | |
2398 | format, so calling code should complete relocation as if | |
2399 | nothing happened here. */ | |
2400 | md_number_to_chars (where, BAL, 4); | |
252b5132 | 2401 | } |
ea1562b3 NC |
2402 | else if (TC_S_IS_BADPROC (fixP->fx_addsy)) |
2403 | as_bad (_("Looks like a proc, but can't tell what kind.\n")); | |
2404 | ||
2405 | /* Otherwise Symbol is neither a sysproc nor a leafproc. */ | |
2406 | return 0; | |
252b5132 RH |
2407 | } |
2408 | ||
2409 | /* Handle the MRI .endian pseudo-op. */ | |
2410 | ||
2411 | static void | |
ea1562b3 | 2412 | s_endian (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
2413 | { |
2414 | char *name; | |
2415 | char c; | |
2416 | ||
2417 | name = input_line_pointer; | |
2418 | c = get_symbol_end (); | |
2419 | if (strcasecmp (name, "little") == 0) | |
2420 | ; | |
2421 | else if (strcasecmp (name, "big") == 0) | |
2422 | as_bad (_("big endian mode is not supported")); | |
2423 | else | |
2424 | as_warn (_("ignoring unrecognized .endian type `%s'"), name); | |
2425 | ||
2426 | *input_line_pointer = c; | |
2427 | ||
2428 | demand_empty_rest_of_line (); | |
2429 | } | |
2430 | ||
92774660 | 2431 | /* We have no need to default values of symbols. */ |
252b5132 | 2432 | |
252b5132 | 2433 | symbolS * |
ea1562b3 | 2434 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2435 | { |
2436 | return 0; | |
2437 | } | |
2438 | ||
2439 | /* Exactly what point is a PC-relative offset relative TO? | |
2440 | On the i960, they're relative to the address of the instruction, | |
92774660 | 2441 | which we have set up as the address of the fixup too. */ |
252b5132 | 2442 | long |
ea1562b3 | 2443 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
2444 | { |
2445 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
2446 | } | |
2447 | ||
2448 | void | |
ea1562b3 NC |
2449 | md_apply_fix3 (fixS *fixP, |
2450 | valueT *valP, | |
2451 | segT seg ATTRIBUTE_UNUSED) | |
252b5132 | 2452 | { |
a161fe53 | 2453 | long val = *valP; |
252b5132 RH |
2454 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; |
2455 | ||
2456 | if (!fixP->fx_bit_fixP) | |
2457 | { | |
76171f81 | 2458 | #ifndef BFD_ASSEMBLER |
252b5132 RH |
2459 | /* For callx, we always want to write out zero, and emit a |
2460 | symbolic relocation. */ | |
2461 | if (fixP->fx_bsr) | |
2462 | val = 0; | |
2463 | ||
2464 | fixP->fx_addnumber = val; | |
bedf545c ILT |
2465 | #endif |
2466 | ||
b9195351 | 2467 | md_number_to_imm (place, val, fixP->fx_size); |
252b5132 | 2468 | } |
44f2f9d2 | 2469 | else if ((int) (size_t) fixP->fx_bit_fixP == 13 |
a161fe53 AM |
2470 | && fixP->fx_addsy != NULL |
2471 | && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section) | |
2472 | { | |
2473 | /* This is a COBR instruction. They have only a | |
2474 | 13-bit displacement and are only to be used | |
2475 | for local branches: flag as error, don't generate | |
2476 | relocation. */ | |
2477 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2478 | _("can't use COBR format with external label")); | |
2479 | fixP->fx_addsy = NULL; | |
2480 | } | |
252b5132 RH |
2481 | else |
2482 | md_number_to_field (place, val, fixP->fx_bit_fixP); | |
bedf545c | 2483 | |
a161fe53 | 2484 | if (fixP->fx_addsy == NULL) |
94f592af | 2485 | fixP->fx_done = 1; |
252b5132 RH |
2486 | } |
2487 | ||
2488 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
2489 | void | |
ea1562b3 NC |
2490 | tc_bout_fix_to_chars (char *where, |
2491 | fixS *fixP, | |
2492 | relax_addressT segment_address_in_file) | |
252b5132 RH |
2493 | { |
2494 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; | |
2495 | struct relocation_info ri; | |
2496 | symbolS *symbolP; | |
2497 | ||
2498 | memset ((char *) &ri, '\0', sizeof (ri)); | |
2499 | symbolP = fixP->fx_addsy; | |
2500 | know (symbolP != 0 || fixP->fx_r_type != NO_RELOC); | |
2501 | ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ | |
2502 | /* These two 'cuz of NS32K */ | |
2503 | ri.r_callj = fixP->fx_tcbit; | |
2504 | if (fixP->fx_bit_fixP) | |
2505 | ri.r_length = 2; | |
2506 | else | |
2507 | ri.r_length = nbytes_r_length[fixP->fx_size]; | |
2508 | ri.r_pcrel = fixP->fx_pcrel; | |
2509 | ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; | |
2510 | ||
2511 | if (fixP->fx_r_type != NO_RELOC) | |
2512 | { | |
2513 | switch (fixP->fx_r_type) | |
2514 | { | |
2515 | case rs_align: | |
2516 | ri.r_index = -2; | |
2517 | ri.r_pcrel = 1; | |
2518 | ri.r_length = fixP->fx_size - 1; | |
2519 | break; | |
2520 | case rs_org: | |
2521 | ri.r_index = -2; | |
2522 | ri.r_pcrel = 0; | |
2523 | break; | |
2524 | case rs_fill: | |
2525 | ri.r_index = -1; | |
2526 | break; | |
2527 | default: | |
2528 | abort (); | |
2529 | } | |
2530 | ri.r_extern = 0; | |
2531 | } | |
2532 | else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr) | |
2533 | { | |
2534 | ri.r_extern = 1; | |
2535 | ri.r_index = symbolP->sy_number; | |
2536 | } | |
2537 | else | |
2538 | { | |
2539 | ri.r_extern = 0; | |
2540 | ri.r_index = S_GET_TYPE (symbolP); | |
2541 | } | |
2542 | ||
92774660 | 2543 | /* Output the relocation information in machine-dependent form. */ |
252b5132 RH |
2544 | md_ri_to_chars (where, &ri); |
2545 | } | |
2546 | ||
2547 | #endif /* OBJ_AOUT or OBJ_BOUT */ | |
2548 | ||
2549 | #if defined (OBJ_COFF) && defined (BFD) | |
2550 | short | |
ea1562b3 | 2551 | tc_coff_fix2rtype (fixS *fixP) |
252b5132 RH |
2552 | { |
2553 | if (fixP->fx_bsr) | |
2554 | abort (); | |
2555 | ||
2556 | if (fixP->fx_pcrel == 0 && fixP->fx_size == 4) | |
2557 | return R_RELLONG; | |
2558 | ||
2559 | if (fixP->fx_pcrel != 0 && fixP->fx_size == 4) | |
2560 | return R_IPRMED; | |
2561 | ||
2562 | abort (); | |
2563 | return 0; | |
2564 | } | |
2565 | ||
2566 | int | |
ea1562b3 | 2567 | tc_coff_sizemachdep (fragS *frag) |
252b5132 RH |
2568 | { |
2569 | if (frag->fr_next) | |
2570 | return frag->fr_next->fr_address - frag->fr_address; | |
2571 | else | |
2572 | return 0; | |
2573 | } | |
2574 | #endif | |
2575 | ||
2576 | /* Align an address by rounding it up to the specified boundary. */ | |
ea1562b3 | 2577 | |
252b5132 | 2578 | valueT |
ea1562b3 NC |
2579 | md_section_align (segT seg, |
2580 | valueT addr) /* Address to be rounded up. */ | |
252b5132 | 2581 | { |
bedf545c | 2582 | int align; |
ea1562b3 | 2583 | |
bedf545c ILT |
2584 | #ifdef BFD_ASSEMBLER |
2585 | align = bfd_get_section_alignment (stdoutput, seg); | |
2586 | #else | |
2587 | align = section_alignment[(int) seg]; | |
2588 | #endif | |
2589 | return (addr + (1 << align) - 1) & (-1 << align); | |
2590 | } | |
252b5132 RH |
2591 | |
2592 | extern int coff_flags; | |
2593 | ||
2594 | #ifdef OBJ_COFF | |
2595 | void | |
ea1562b3 | 2596 | tc_headers_hook (object_headers *headers) |
252b5132 RH |
2597 | { |
2598 | switch (architecture) | |
2599 | { | |
2600 | case ARCH_KA: | |
2601 | coff_flags |= F_I960KA; | |
2602 | break; | |
2603 | ||
2604 | case ARCH_KB: | |
2605 | coff_flags |= F_I960KB; | |
2606 | break; | |
2607 | ||
2608 | case ARCH_MC: | |
2609 | coff_flags |= F_I960MC; | |
2610 | break; | |
2611 | ||
2612 | case ARCH_CA: | |
2613 | coff_flags |= F_I960CA; | |
2614 | break; | |
2615 | ||
2616 | case ARCH_JX: | |
2617 | coff_flags |= F_I960JX; | |
2618 | break; | |
2619 | ||
2620 | case ARCH_HX: | |
2621 | coff_flags |= F_I960HX; | |
2622 | break; | |
2623 | ||
2624 | default: | |
2625 | if (iclasses_seen == I_BASE) | |
2626 | coff_flags |= F_I960CORE; | |
2627 | else if (iclasses_seen & I_CX) | |
2628 | coff_flags |= F_I960CA; | |
2629 | else if (iclasses_seen & I_HX) | |
2630 | coff_flags |= F_I960HX; | |
2631 | else if (iclasses_seen & I_JX) | |
2632 | coff_flags |= F_I960JX; | |
2633 | else if (iclasses_seen & I_CX2) | |
2634 | coff_flags |= F_I960CA; | |
2635 | else if (iclasses_seen & I_MIL) | |
2636 | coff_flags |= F_I960MC; | |
2637 | else if (iclasses_seen & (I_DEC | I_FP)) | |
2638 | coff_flags |= F_I960KB; | |
2639 | else | |
2640 | coff_flags |= F_I960KA; | |
2641 | break; | |
2642 | } | |
2643 | ||
2644 | if (flag_readonly_data_in_text) | |
2645 | { | |
2646 | headers->filehdr.f_magic = I960RWMAGIC; | |
2647 | headers->aouthdr.magic = OMAGIC; | |
2648 | } | |
2649 | else | |
2650 | { | |
2651 | headers->filehdr.f_magic = I960ROMAGIC; | |
2652 | headers->aouthdr.magic = NMAGIC; | |
2653 | } /* set magic numbers */ | |
2654 | } | |
2655 | ||
2656 | #endif /* OBJ_COFF */ | |
2657 | ||
bedf545c ILT |
2658 | #ifndef BFD_ASSEMBLER |
2659 | ||
252b5132 RH |
2660 | /* Things going on here: |
2661 | ||
2662 | For bout, We need to assure a couple of simplifying | |
2663 | assumptions about leafprocs for the linker: the leafproc | |
2664 | entry symbols will be defined in the same assembly in | |
2665 | which they're declared with the '.leafproc' directive; | |
2666 | and if a leafproc has both 'call' and 'bal' entry points | |
2667 | they are both global or both local. | |
2668 | ||
2669 | For coff, the call symbol has a second aux entry that | |
2670 | contains the bal entry point. The bal symbol becomes a | |
2671 | label. | |
2672 | ||
2673 | For coff representation, the call symbol has a second aux entry that | |
2674 | contains the bal entry point. The bal symbol becomes a label. */ | |
2675 | ||
2676 | void | |
ea1562b3 | 2677 | tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED) |
252b5132 RH |
2678 | { |
2679 | symbolS *symbolP; | |
2680 | ||
2681 | for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP)) | |
2682 | { | |
2683 | #ifdef OBJ_COFF | |
2684 | if (TC_S_IS_SYSPROC (symbolP)) | |
2685 | { | |
ea1562b3 | 2686 | /* Second aux entry already contains the sysproc number. */ |
252b5132 RH |
2687 | S_SET_NUMBER_AUXILIARY (symbolP, 2); |
2688 | S_SET_STORAGE_CLASS (symbolP, C_SCALL); | |
2689 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
2690 | continue; | |
ea1562b3 | 2691 | } |
252b5132 RH |
2692 | #endif /* OBJ_COFF */ |
2693 | ||
2694 | if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP)) | |
ea1562b3 | 2695 | continue; |
252b5132 RH |
2696 | |
2697 | if (!S_IS_DEFINED (symbolP)) | |
ea1562b3 | 2698 | as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP)); |
252b5132 RH |
2699 | |
2700 | if (TC_S_IS_CALLNAME (symbolP)) | |
2701 | { | |
2702 | symbolS *balP = tc_get_bal_of_call (symbolP); | |
ea1562b3 | 2703 | |
252b5132 RH |
2704 | if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP)) |
2705 | { | |
2706 | S_SET_EXTERNAL (symbolP); | |
2707 | S_SET_EXTERNAL (balP); | |
2708 | as_warn (_("Warning: making leafproc entries %s and %s both global\n"), | |
2709 | S_GET_NAME (symbolP), S_GET_NAME (balP)); | |
2710 | } /* externality mismatch */ | |
2711 | } /* if callname */ | |
2712 | } /* walk the symbol chain */ | |
2713 | } | |
2714 | ||
bedf545c ILT |
2715 | #endif /* ! BFD_ASSEMBLER */ |
2716 | ||
252b5132 RH |
2717 | /* For aout or bout, the bal immediately follows the call. |
2718 | ||
2719 | For coff, we cheat and store a pointer to the bal symbol in the | |
2720 | second aux entry of the call. */ | |
2721 | ||
2722 | #undef OBJ_ABOUT | |
2723 | #ifdef OBJ_AOUT | |
2724 | #define OBJ_ABOUT | |
2725 | #endif | |
2726 | #ifdef OBJ_BOUT | |
2727 | #define OBJ_ABOUT | |
2728 | #endif | |
2729 | ||
2730 | void | |
ea1562b3 NC |
2731 | tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED, |
2732 | symbolS *balP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2733 | { |
2734 | know (TC_S_IS_CALLNAME (callP)); | |
2735 | know (TC_S_IS_BALNAME (balP)); | |
2736 | ||
2737 | #ifdef OBJ_COFF | |
2738 | ||
2739 | callP->sy_tc = balP; | |
2740 | S_SET_NUMBER_AUXILIARY (callP, 2); | |
2741 | ||
2742 | #else /* ! OBJ_COFF */ | |
2743 | #ifdef OBJ_ABOUT | |
2744 | ||
2745 | /* If the 'bal' entry doesn't immediately follow the 'call' | |
ea1562b3 | 2746 | symbol, unlink it from the symbol list and re-insert it. */ |
252b5132 RH |
2747 | if (symbol_next (callP) != balP) |
2748 | { | |
2749 | symbol_remove (balP, &symbol_rootP, &symbol_lastP); | |
2750 | symbol_append (balP, callP, &symbol_rootP, &symbol_lastP); | |
2751 | } /* if not in order */ | |
2752 | ||
2753 | #else /* ! OBJ_ABOUT */ | |
bedf545c | 2754 | as_fatal ("Only supported for a.out, b.out, or COFF"); |
252b5132 RH |
2755 | #endif /* ! OBJ_ABOUT */ |
2756 | #endif /* ! OBJ_COFF */ | |
2757 | } | |
2758 | ||
2759 | symbolS * | |
ea1562b3 | 2760 | tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED) |
252b5132 RH |
2761 | { |
2762 | symbolS *retval; | |
2763 | ||
2764 | know (TC_S_IS_CALLNAME (callP)); | |
2765 | ||
2766 | #ifdef OBJ_COFF | |
2767 | retval = callP->sy_tc; | |
2768 | #else | |
2769 | #ifdef OBJ_ABOUT | |
2770 | retval = symbol_next (callP); | |
2771 | #else | |
bedf545c | 2772 | as_fatal ("Only supported for a.out, b.out, or COFF"); |
252b5132 RH |
2773 | #endif /* ! OBJ_ABOUT */ |
2774 | #endif /* ! OBJ_COFF */ | |
2775 | ||
2776 | know (TC_S_IS_BALNAME (retval)); | |
2777 | return retval; | |
ea1562b3 | 2778 | } |
252b5132 | 2779 | |
b9195351 | 2780 | #ifdef OBJ_COFF |
252b5132 | 2781 | void |
ea1562b3 | 2782 | tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED) |
252b5132 RH |
2783 | { |
2784 | if (TC_S_IS_CALLNAME (symbolP)) | |
2785 | { | |
252b5132 RH |
2786 | symbolS *balP = tc_get_bal_of_call (symbolP); |
2787 | ||
252b5132 RH |
2788 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP); |
2789 | if (S_GET_STORAGE_CLASS (symbolP) == C_EXT) | |
2790 | S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT); | |
2791 | else | |
2792 | S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT); | |
2793 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
ea1562b3 | 2794 | /* Fix up the bal symbol. */ |
252b5132 | 2795 | S_SET_STORAGE_CLASS (balP, C_LABEL); |
ea1562b3 | 2796 | } |
252b5132 | 2797 | } |
b9195351 | 2798 | #endif /* OBJ_COFF */ |
252b5132 RH |
2799 | |
2800 | void | |
ea1562b3 | 2801 | i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED) |
252b5132 RH |
2802 | { |
2803 | if (!linkrelax) | |
2804 | return; | |
2805 | ||
2806 | #ifndef OBJ_BOUT | |
252b5132 RH |
2807 | as_bad (_("option --link-relax is only supported in b.out format")); |
2808 | linkrelax = 0; | |
2809 | return; | |
252b5132 RH |
2810 | #else |
2811 | ||
2812 | /* The text section "ends" with another alignment reloc, to which we | |
2813 | aren't adding padding. */ | |
2814 | if (fragp->fr_next == text_last_frag | |
2815 | || fragp->fr_next == data_last_frag) | |
2816 | return; | |
2817 | ||
2818 | /* alignment directive */ | |
2819 | fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, | |
2820 | (int) fragp->fr_type); | |
2821 | #endif /* OBJ_BOUT */ | |
2822 | } | |
2823 | ||
2824 | int | |
ea1562b3 | 2825 | i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED) |
252b5132 | 2826 | { |
a161fe53 | 2827 | if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy)) |
252b5132 RH |
2828 | { |
2829 | /* Relocation should be done via the associated 'bal' | |
92774660 | 2830 | entry point symbol. */ |
a161fe53 | 2831 | if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy))) |
252b5132 | 2832 | { |
a161fe53 AM |
2833 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2834 | _("No 'bal' entry point for leafproc %s"), | |
2835 | S_GET_NAME (fixP->fx_addsy)); | |
2836 | return 0; | |
252b5132 | 2837 | } |
a161fe53 | 2838 | fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy); |
252b5132 | 2839 | } |
a161fe53 AM |
2840 | |
2841 | return 1; | |
252b5132 RH |
2842 | } |
2843 | ||
bedf545c ILT |
2844 | #ifdef BFD_ASSEMBLER |
2845 | ||
2846 | /* From cgen.c: */ | |
2847 | ||
2848 | static short | |
ea1562b3 | 2849 | tc_bfd_fix2rtype (fixS *fixP) |
bedf545c | 2850 | { |
bedf545c ILT |
2851 | if (fixP->fx_pcrel == 0 && fixP->fx_size == 4) |
2852 | return BFD_RELOC_32; | |
2853 | ||
2854 | if (fixP->fx_pcrel != 0 && fixP->fx_size == 4) | |
2855 | return BFD_RELOC_24_PCREL; | |
2856 | ||
2857 | abort (); | |
2858 | return 0; | |
2859 | } | |
2860 | ||
2861 | /* Translate internal representation of relocation info to BFD target | |
2862 | format. | |
2863 | ||
2864 | FIXME: To what extent can we get all relevant targets to use this? */ | |
2865 | ||
2866 | arelent * | |
ea1562b3 | 2867 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) |
bedf545c ILT |
2868 | { |
2869 | arelent * reloc; | |
2870 | ||
ea1562b3 | 2871 | reloc = xmalloc (sizeof (arelent)); |
bedf545c | 2872 | |
ea1562b3 | 2873 | /* HACK: Is this right? */ |
bedf545c ILT |
2874 | fixP->fx_r_type = tc_bfd_fix2rtype (fixP); |
2875 | ||
2876 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
ea1562b3 | 2877 | if (reloc->howto == NULL) |
bedf545c ILT |
2878 | { |
2879 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2880 | "internal error: can't export reloc type %d (`%s')", | |
2881 | fixP->fx_r_type, | |
2882 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
2883 | return NULL; | |
2884 | } | |
2885 | ||
2886 | assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); | |
2887 | ||
ea1562b3 | 2888 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
49309057 | 2889 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); |
bedf545c ILT |
2890 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; |
2891 | reloc->addend = fixP->fx_addnumber; | |
2892 | ||
2893 | return reloc; | |
2894 | } | |
2895 | ||
2896 | /* end from cgen.c */ | |
2897 | ||
2898 | #endif /* BFD_ASSEMBLER */ | |
2899 | ||
ea1562b3 NC |
2900 | const pseudo_typeS md_pseudo_table[] = |
2901 | { | |
2902 | {"bss", s_lcomm, 1}, | |
2903 | {"endian", s_endian, 0}, | |
2904 | {"extended", float_cons, 't'}, | |
2905 | {"leafproc", parse_po, S_LEAFPROC}, | |
2906 | {"sysproc", parse_po, S_SYSPROC}, | |
2907 | ||
2908 | {"word", cons, 4}, | |
2909 | {"quad", cons, 16}, | |
2910 | ||
2911 | {0, 0, 0} | |
2912 | }; |