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252b5132 | 1 | /* tc-i960.c - All the i80960-specific stuff |
6f2750fe | 2 | Copyright (C) 1989-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
92774660 | 21 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
252b5132 RH |
22 | |
23 | /* There are 4 different lengths of (potentially) symbol-based displacements | |
24 | in the 80960 instruction set, each of which could require address fix-ups | |
25 | and (in the case of external symbols) emission of relocation directives: | |
26 | ||
27 | 32-bit (MEMB) | |
28 | This is a standard length for the base assembler and requires no | |
29 | special action. | |
30 | ||
31 | 13-bit (COBR) | |
32 | This is a non-standard length, but the base assembler has a | |
33 | hook for bit field address fixups: the fixS structure can | |
34 | point to a descriptor of the field, in which case our | |
35 | md_number_to_field() routine gets called to process it. | |
36 | ||
37 | I made the hook a little cleaner by having fix_new() (in the base | |
38 | assembler) return a pointer to the fixS in question. And I made it a | |
39 | little simpler by storing the field size (in this case 13) instead of | |
40 | of a pointer to another structure: 80960 displacements are ALWAYS | |
41 | stored in the low-order bits of a 4-byte word. | |
42 | ||
43 | Since the target of a COBR cannot be external, no relocation | |
44 | directives for this size displacement have to be generated. | |
45 | But the base assembler had to be modified to issue error | |
46 | messages if the symbol did turn out to be external. | |
47 | ||
48 | 24-bit (CTRL) | |
49 | Fixups are handled as for the 13-bit case (except that 24 is stored | |
50 | in the fixS). | |
51 | ||
52 | The relocation directive generated is the same as that for the 32-bit | |
53 | displacement, except that it's PC-relative (the 32-bit displacement | |
54 | never is). The i80960 version of the linker needs a mod to | |
55 | distinguish and handle the 24-bit case. | |
56 | ||
57 | 12-bit (MEMA) | |
58 | MEMA formats are always promoted to MEMB (32-bit) if the displacement | |
59 | is based on a symbol, because it could be relocated at link time. | |
60 | The only time we use the 12-bit format is if an absolute value of | |
61 | less than 4096 is specified, in which case we need neither a fixup nor | |
62 | a relocation directive. */ | |
63 | ||
252b5132 RH |
64 | #include "as.h" |
65 | ||
3882b010 | 66 | #include "safe-ctype.h" |
252b5132 RH |
67 | |
68 | #include "opcode/i960.h" | |
69 | ||
70 | #if defined (OBJ_AOUT) || defined (OBJ_BOUT) | |
71 | ||
ea1562b3 NC |
72 | #define TC_S_IS_SYSPROC(s) ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32)) |
73 | #define TC_S_IS_BALNAME(s) (S_GET_OTHER (s) == N_BALNAME) | |
74 | #define TC_S_IS_CALLNAME(s) (S_GET_OTHER (s) == N_CALLNAME) | |
75 | #define TC_S_IS_BADPROC(s) ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s)) | |
252b5132 | 76 | |
ea1562b3 NC |
77 | #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER ((s), (p) + 1)) |
78 | #define TC_S_GET_SYSPROC(s) (S_GET_OTHER (s) - 1) | |
252b5132 | 79 | |
ea1562b3 NC |
80 | #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER ((s), N_BALNAME)) |
81 | #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER ((s), N_CALLNAME)) | |
252b5132 RH |
82 | #define TC_S_FORCE_TO_SYSPROC(s) {;} |
83 | ||
84 | #else /* ! OBJ_A/BOUT */ | |
85 | #ifdef OBJ_COFF | |
86 | ||
ea1562b3 NC |
87 | #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS (s) == C_SCALL) |
88 | #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME (s)) | |
89 | #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME (s)) | |
90 | #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s)) | |
252b5132 RH |
91 | |
92 | #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p)) | |
93 | #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx) | |
94 | ||
ea1562b3 NC |
95 | #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME (s)) |
96 | #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME (s)) | |
97 | #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS ((s), C_SCALL)) | |
252b5132 RH |
98 | |
99 | #else /* ! OBJ_COFF */ | |
bedf545c ILT |
100 | #ifdef OBJ_ELF |
101 | #define TC_S_IS_SYSPROC(s) 0 | |
102 | ||
103 | #define TC_S_IS_BALNAME(s) 0 | |
104 | #define TC_S_IS_CALLNAME(s) 0 | |
105 | #define TC_S_IS_BADPROC(s) 0 | |
106 | ||
107 | #define TC_S_SET_SYSPROC(s, p) | |
ea1562b3 | 108 | #define TC_S_GET_SYSPROC(s) 0 |
bedf545c ILT |
109 | |
110 | #define TC_S_FORCE_TO_BALNAME(s) | |
111 | #define TC_S_FORCE_TO_CALLNAME(s) | |
112 | #define TC_S_FORCE_TO_SYSPROC(s) | |
113 | #else | |
114 | #error COFF, a.out, b.out, and ELF are the only supported formats. | |
115 | #endif /* ! OBJ_ELF */ | |
252b5132 RH |
116 | #endif /* ! OBJ_COFF */ |
117 | #endif /* ! OBJ_A/BOUT */ | |
118 | ||
119 | extern char *input_line_pointer; | |
120 | ||
252b5132 | 121 | /* Local i80960 routines. */ |
b9195351 AM |
122 | struct memS; |
123 | struct regop; | |
124 | ||
ea1562b3 NC |
125 | /* See md_parse_option() for meanings of these options. */ |
126 | static char norelax; /* True if -norelax switch seen. */ | |
127 | static char instrument_branches; /* True if -b switch seen. */ | |
252b5132 RH |
128 | |
129 | /* Characters that always start a comment. | |
ea1562b3 | 130 | If the pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
131 | const char comment_chars[] = "#"; |
132 | ||
133 | /* Characters that only start a comment at the beginning of | |
134 | a line. If the line seems to have the form '# 123 filename' | |
135 | .line and .file directives will appear in the pre-processed output. | |
136 | ||
137 | Note that input_file.c hand checks for '#' at the beginning of the | |
138 | first line of the input file. This is because the compiler outputs | |
ea1562b3 | 139 | #NO_APP at the beginning of its output. */ |
252b5132 | 140 | |
92774660 | 141 | /* Also note that comments started like this one will always work. */ |
252b5132 | 142 | |
ea1562b3 | 143 | const char line_comment_chars[] = "#"; |
63a0b638 | 144 | const char line_separator_chars[] = ";"; |
252b5132 | 145 | |
ea1562b3 | 146 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
252b5132 RH |
147 | const char EXP_CHARS[] = "eE"; |
148 | ||
149 | /* Chars that mean this number is a floating point constant, | |
ea1562b3 | 150 | as in 0f12.456 or 0d1.2345e12. */ |
252b5132 RH |
151 | const char FLT_CHARS[] = "fFdDtT"; |
152 | ||
252b5132 RH |
153 | /* Table used by base assembler to relax addresses based on varying length |
154 | instructions. The fields are: | |
155 | 1) most positive reach of this state, | |
156 | 2) most negative reach of this state, | |
157 | 3) how many bytes this mode will add to the size of the current frag | |
158 | 4) which index into the table to try if we can't fit into this one. | |
159 | ||
160 | For i80960, the only application is the (de-)optimization of cobr | |
161 | instructions into separate compare and branch instructions when a 13-bit | |
ea1562b3 | 162 | displacement won't hack it. */ |
252b5132 RH |
163 | const relax_typeS md_relax_table[] = |
164 | { | |
ea1562b3 NC |
165 | {0, 0, 0, 0}, /* State 0 => no more relaxation possible. */ |
166 | {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr). */ | |
167 | {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl). */ | |
252b5132 RH |
168 | }; |
169 | ||
252b5132 RH |
170 | /* These are the machine dependent pseudo-ops. |
171 | ||
172 | This table describes all the machine specific pseudo-ops the assembler | |
173 | has to support. The fields are: | |
174 | pseudo-op name without dot | |
175 | function to call to execute this pseudo-op | |
ea1562b3 | 176 | integer arg to pass to the function. */ |
252b5132 RH |
177 | #define S_LEAFPROC 1 |
178 | #define S_SYSPROC 2 | |
179 | ||
ea1562b3 | 180 | /* Macros to extract info from an 'expressionS' structure 'e'. */ |
252b5132 RH |
181 | #define adds(e) e.X_add_symbol |
182 | #define offs(e) e.X_add_number | |
183 | ||
ea1562b3 NC |
184 | /* Branch-prediction bits for CTRL/COBR format opcodes. */ |
185 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit. */ | |
186 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch. */ | |
187 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch. */ | |
252b5132 | 188 | |
ea1562b3 | 189 | /* Some instruction opcodes that we need explicitly. */ |
252b5132 RH |
190 | #define BE 0x12000000 |
191 | #define BG 0x11000000 | |
192 | #define BGE 0x13000000 | |
193 | #define BL 0x14000000 | |
194 | #define BLE 0x16000000 | |
195 | #define BNE 0x15000000 | |
196 | #define BNO 0x10000000 | |
197 | #define BO 0x17000000 | |
198 | #define CHKBIT 0x5a002700 | |
199 | #define CMPI 0x5a002080 | |
200 | #define CMPO 0x5a002000 | |
201 | ||
202 | #define B 0x08000000 | |
203 | #define BAL 0x0b000000 | |
204 | #define CALL 0x09000000 | |
205 | #define CALLS 0x66003800 | |
206 | #define RET 0x0a000000 | |
207 | ||
92774660 | 208 | /* These masks are used to build up a set of MEMB mode bits. */ |
252b5132 RH |
209 | #define A_BIT 0x0400 |
210 | #define I_BIT 0x0800 | |
211 | #define MEMB_BIT 0x1000 | |
212 | #define D_BIT 0x2000 | |
213 | ||
252b5132 RH |
214 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is |
215 | used). */ | |
216 | #define MEMA_ABASE 0x2000 | |
217 | ||
ea1562b3 | 218 | /* Info from which a MEMA or MEMB format instruction can be generated. */ |
b9195351 | 219 | typedef struct memS |
252b5132 | 220 | { |
ea1562b3 | 221 | /* (First) 32 bits of instruction. */ |
252b5132 | 222 | long opcode; |
ea1562b3 | 223 | /* 0-(none), 12- or, 32-bit displacement needed. */ |
252b5132 RH |
224 | int disp; |
225 | /* The expression in the source instruction from which the | |
226 | displacement should be determined. */ | |
227 | char *e; | |
228 | } | |
252b5132 RH |
229 | memS; |
230 | ||
ea1562b3 | 231 | /* The two pieces of info we need to generate a register operand. */ |
252b5132 RH |
232 | struct regop |
233 | { | |
ea1562b3 NC |
234 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg. */ |
235 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0). */ | |
236 | int n; /* Register number or literal value. */ | |
252b5132 RH |
237 | }; |
238 | ||
252b5132 RH |
239 | /* Number and assembler mnemonic for all registers that can appear in |
240 | operands. */ | |
241 | static const struct | |
242 | { | |
e0471c16 | 243 | const char *reg_name; |
252b5132 RH |
244 | int reg_num; |
245 | } | |
246 | regnames[] = | |
247 | { | |
248 | { "pfp", 0 }, | |
249 | { "sp", 1 }, | |
250 | { "rip", 2 }, | |
251 | { "r3", 3 }, | |
252 | { "r4", 4 }, | |
253 | { "r5", 5 }, | |
254 | { "r6", 6 }, | |
255 | { "r7", 7 }, | |
256 | { "r8", 8 }, | |
257 | { "r9", 9 }, | |
258 | { "r10", 10 }, | |
259 | { "r11", 11 }, | |
260 | { "r12", 12 }, | |
261 | { "r13", 13 }, | |
262 | { "r14", 14 }, | |
263 | { "r15", 15 }, | |
264 | { "g0", 16 }, | |
265 | { "g1", 17 }, | |
266 | { "g2", 18 }, | |
267 | { "g3", 19 }, | |
268 | { "g4", 20 }, | |
269 | { "g5", 21 }, | |
270 | { "g6", 22 }, | |
271 | { "g7", 23 }, | |
272 | { "g8", 24 }, | |
273 | { "g9", 25 }, | |
274 | { "g10", 26 }, | |
275 | { "g11", 27 }, | |
276 | { "g12", 28 }, | |
277 | { "g13", 29 }, | |
278 | { "g14", 30 }, | |
279 | { "fp", 31 }, | |
280 | ||
281 | /* Numbers for special-function registers are for assembler internal | |
282 | use only: they are scaled back to range [0-31] for binary output. */ | |
283 | #define SF0 32 | |
284 | ||
285 | { "sf0", 32 }, | |
286 | { "sf1", 33 }, | |
287 | { "sf2", 34 }, | |
288 | { "sf3", 35 }, | |
289 | { "sf4", 36 }, | |
290 | { "sf5", 37 }, | |
291 | { "sf6", 38 }, | |
292 | { "sf7", 39 }, | |
293 | { "sf8", 40 }, | |
294 | { "sf9", 41 }, | |
295 | { "sf10", 42 }, | |
296 | { "sf11", 43 }, | |
297 | { "sf12", 44 }, | |
298 | { "sf13", 45 }, | |
299 | { "sf14", 46 }, | |
300 | { "sf15", 47 }, | |
301 | { "sf16", 48 }, | |
302 | { "sf17", 49 }, | |
303 | { "sf18", 50 }, | |
304 | { "sf19", 51 }, | |
305 | { "sf20", 52 }, | |
306 | { "sf21", 53 }, | |
307 | { "sf22", 54 }, | |
308 | { "sf23", 55 }, | |
309 | { "sf24", 56 }, | |
310 | { "sf25", 57 }, | |
311 | { "sf26", 58 }, | |
312 | { "sf27", 59 }, | |
313 | { "sf28", 60 }, | |
314 | { "sf29", 61 }, | |
315 | { "sf30", 62 }, | |
316 | { "sf31", 63 }, | |
317 | ||
318 | /* Numbers for floating point registers are for assembler internal | |
319 | use only: they are scaled back to [0-3] for binary output. */ | |
320 | #define FP0 64 | |
321 | ||
322 | { "fp0", 64 }, | |
323 | { "fp1", 65 }, | |
324 | { "fp2", 66 }, | |
325 | { "fp3", 67 }, | |
326 | ||
327 | { NULL, 0 }, /* END OF LIST */ | |
328 | }; | |
329 | ||
330 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) | |
331 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) | |
332 | #define IS_FP_REG(n) ((n) >= FP0) | |
333 | ||
334 | /* Number and assembler mnemonic for all registers that can appear as | |
335 | 'abase' (indirect addressing) registers. */ | |
336 | static const struct | |
ea1562b3 | 337 | { |
e0471c16 | 338 | const char *areg_name; |
ea1562b3 NC |
339 | int areg_num; |
340 | } | |
252b5132 RH |
341 | aregs[] = |
342 | { | |
343 | { "(pfp)", 0 }, | |
344 | { "(sp)", 1 }, | |
345 | { "(rip)", 2 }, | |
346 | { "(r3)", 3 }, | |
347 | { "(r4)", 4 }, | |
348 | { "(r5)", 5 }, | |
349 | { "(r6)", 6 }, | |
350 | { "(r7)", 7 }, | |
351 | { "(r8)", 8 }, | |
352 | { "(r9)", 9 }, | |
353 | { "(r10)", 10 }, | |
354 | { "(r11)", 11 }, | |
355 | { "(r12)", 12 }, | |
356 | { "(r13)", 13 }, | |
357 | { "(r14)", 14 }, | |
358 | { "(r15)", 15 }, | |
359 | { "(g0)", 16 }, | |
360 | { "(g1)", 17 }, | |
361 | { "(g2)", 18 }, | |
362 | { "(g3)", 19 }, | |
363 | { "(g4)", 20 }, | |
364 | { "(g5)", 21 }, | |
365 | { "(g6)", 22 }, | |
366 | { "(g7)", 23 }, | |
367 | { "(g8)", 24 }, | |
368 | { "(g9)", 25 }, | |
369 | { "(g10)", 26 }, | |
370 | { "(g11)", 27 }, | |
371 | { "(g12)", 28 }, | |
372 | { "(g13)", 29 }, | |
373 | { "(g14)", 30 }, | |
374 | { "(fp)", 31 }, | |
375 | ||
376 | #define IPREL 32 | |
377 | /* For assembler internal use only: this number never appears in binary | |
378 | output. */ | |
379 | { "(ip)", IPREL }, | |
380 | ||
381 | { NULL, 0 }, /* END OF LIST */ | |
382 | }; | |
383 | ||
ea1562b3 NC |
384 | /* Hash tables. */ |
385 | static struct hash_control *op_hash; /* Opcode mnemonics. */ | |
386 | static struct hash_control *reg_hash; /* Register name hash table. */ | |
387 | static struct hash_control *areg_hash; /* Abase register hash table. */ | |
252b5132 | 388 | |
ea1562b3 NC |
389 | /* Architecture for which we are assembling. */ |
390 | #define ARCH_ANY 0 /* Default: no architecture checking done. */ | |
252b5132 RH |
391 | #define ARCH_KA 1 |
392 | #define ARCH_KB 2 | |
393 | #define ARCH_MC 3 | |
394 | #define ARCH_CA 4 | |
395 | #define ARCH_JX 5 | |
396 | #define ARCH_HX 6 | |
ea1562b3 | 397 | int architecture = ARCH_ANY; /* Architecture requested on invocation line. */ |
252b5132 | 398 | int iclasses_seen; /* OR of instruction classes (I_* constants) |
ea1562b3 NC |
399 | for which we've actually assembled |
400 | instructions. */ | |
252b5132 | 401 | |
252b5132 RH |
402 | /* BRANCH-PREDICTION INSTRUMENTATION |
403 | ||
404 | The following supports generation of branch-prediction instrumentation | |
405 | (turned on by -b switch). The instrumentation collects counts | |
406 | of branches taken/not-taken for later input to a utility that will | |
407 | set the branch prediction bits of the instructions in accordance with | |
408 | the behavior observed. (Note that the KX series does not have | |
409 | brach-prediction.) | |
410 | ||
411 | The instrumentation consists of: | |
412 | ||
413 | (1) before and after each conditional branch, a call to an external | |
414 | routine that increments and steps over an inline counter. The | |
415 | counter itself, initialized to 0, immediately follows the call | |
416 | instruction. For each branch, the counter following the branch | |
417 | is the number of times the branch was not taken, and the difference | |
418 | between the counters is the number of times it was taken. An | |
419 | example of an instrumented conditional branch: | |
420 | ||
421 | call BR_CNT_FUNC | |
422 | .word 0 | |
423 | LBRANCH23: be label | |
424 | call BR_CNT_FUNC | |
425 | .word 0 | |
426 | ||
427 | (2) a table of pointers to the instrumented branches, so that an | |
428 | external postprocessing routine can locate all of the counters. | |
429 | the table begins with a 2-word header: a pointer to the next in | |
430 | a linked list of such tables (initialized to 0); and a count | |
431 | of the number of entries in the table (exclusive of the header. | |
432 | ||
433 | Note that input source code is expected to already contain calls | |
434 | an external routine that will link the branch local table into a | |
ea1562b3 | 435 | list of such tables. */ |
252b5132 RH |
436 | |
437 | /* Number of branches instrumented so far. Also used to generate | |
438 | unique local labels for each instrumented branch. */ | |
439 | static int br_cnt; | |
440 | ||
441 | #define BR_LABEL_BASE "LBRANCH" | |
442 | /* Basename of local labels on instrumented branches, to avoid | |
443 | conflict with compiler- generated local labels. */ | |
444 | ||
445 | #define BR_CNT_FUNC "__inc_branch" | |
446 | /* Name of the external routine that will increment (and step over) an | |
447 | inline counter. */ | |
448 | ||
449 | #define BR_TAB_NAME "__BRANCH_TABLE__" | |
450 | /* Name of the table of pointers to branches. A local (i.e., | |
451 | non-external) symbol. */ | |
252b5132 | 452 | |
47990a6a | 453 | static void ctrl_fmt (const char *, long, int); |
252b5132 | 454 | |
ea1562b3 | 455 | \f |
252b5132 | 456 | void |
ea1562b3 | 457 | md_begin (void) |
252b5132 | 458 | { |
ea1562b3 NC |
459 | int i; /* Loop counter. */ |
460 | const struct i960_opcode *oP; /* Pointer into opcode table. */ | |
461 | const char *retval; /* Value returned by hash functions. */ | |
252b5132 RH |
462 | |
463 | op_hash = hash_new (); | |
464 | reg_hash = hash_new (); | |
465 | areg_hash = hash_new (); | |
466 | ||
467 | /* For some reason, the base assembler uses an empty string for "no | |
468 | error message", instead of a NULL pointer. */ | |
469 | retval = 0; | |
470 | ||
471 | for (oP = i960_opcodes; oP->name && !retval; oP++) | |
ea1562b3 | 472 | retval = hash_insert (op_hash, oP->name, (void *) oP); |
252b5132 RH |
473 | |
474 | for (i = 0; regnames[i].reg_name && !retval; i++) | |
475 | retval = hash_insert (reg_hash, regnames[i].reg_name, | |
476 | (char *) ®names[i].reg_num); | |
477 | ||
478 | for (i = 0; aregs[i].areg_name && !retval; i++) | |
479 | retval = hash_insert (areg_hash, aregs[i].areg_name, | |
480 | (char *) &aregs[i].areg_num); | |
481 | ||
482 | if (retval) | |
483 | as_fatal (_("Hashing returned \"%s\"."), retval); | |
484 | } | |
485 | ||
ea1562b3 | 486 | /* parse_expr: parse an expression |
252b5132 | 487 | |
ea1562b3 NC |
488 | Use base assembler's expression parser to parse an expression. |
489 | It, unfortunately, runs off a global which we have to save/restore | |
490 | in order to make it work for us. | |
252b5132 | 491 | |
ea1562b3 | 492 | An empty expression string is treated as an absolute 0. |
252b5132 | 493 | |
ea1562b3 NC |
494 | Sets O_illegal regardless of expression evaluation if entire input |
495 | string is not consumed in the evaluation -- tolerate no dangling junk! */ | |
252b5132 | 496 | |
ea1562b3 | 497 | static void |
47990a6a | 498 | parse_expr (const char *textP, /* Text of expression to be parsed. */ |
ea1562b3 NC |
499 | expressionS *expP) /* Where to put the results of parsing. */ |
500 | { | |
501 | char *save_in; /* Save global here. */ | |
502 | symbolS *symP; | |
252b5132 | 503 | |
ea1562b3 | 504 | know (textP); |
252b5132 | 505 | |
ea1562b3 | 506 | if (*textP == '\0') |
252b5132 | 507 | { |
ea1562b3 NC |
508 | /* Treat empty string as absolute 0. */ |
509 | expP->X_add_symbol = expP->X_op_symbol = NULL; | |
510 | expP->X_add_number = 0; | |
511 | expP->X_op = O_constant; | |
252b5132 | 512 | } |
ea1562b3 | 513 | else |
252b5132 | 514 | { |
ea1562b3 | 515 | save_in = input_line_pointer; /* Save global. */ |
47990a6a | 516 | input_line_pointer = (char *) textP; /* Make parser work for us. */ |
252b5132 | 517 | |
ea1562b3 NC |
518 | (void) expression (expP); |
519 | if ((size_t) (input_line_pointer - textP) != strlen (textP)) | |
520 | /* Did not consume all of the input. */ | |
521 | expP->X_op = O_illegal; | |
252b5132 | 522 | |
ea1562b3 NC |
523 | symP = expP->X_add_symbol; |
524 | if (symP && (hash_find (reg_hash, S_GET_NAME (symP)))) | |
525 | /* Register name in an expression. */ | |
526 | /* FIXME: this isn't much of a check any more. */ | |
527 | expP->X_op = O_illegal; | |
252b5132 | 528 | |
ea1562b3 | 529 | input_line_pointer = save_in; /* Restore global. */ |
252b5132 | 530 | } |
ea1562b3 NC |
531 | } |
532 | ||
533 | /* emit: output instruction binary | |
534 | ||
535 | Output instruction binary, in target byte order, 4 bytes at a time. | |
536 | Return pointer to where it was placed. */ | |
537 | ||
538 | static char * | |
539 | emit (long instr) /* Word to be output, host byte order. */ | |
540 | { | |
541 | char *toP; /* Where to output it. */ | |
542 | ||
543 | toP = frag_more (4); /* Allocate storage. */ | |
544 | md_number_to_chars (toP, instr, 4); /* Convert to target byte order. */ | |
545 | return toP; | |
546 | } | |
547 | ||
548 | /* get_cdisp: handle displacement for a COBR or CTRL instruction. | |
549 | ||
550 | Parse displacement for a COBR or CTRL instruction. | |
551 | ||
552 | If successful, output the instruction opcode and set up for it, | |
553 | depending on the arg 'var_frag', either: | |
554 | o an address fixup to be done when all symbol values are known, or | |
555 | o a varying length code fragment, with address fixup info. This | |
556 | will be done for cobr instructions that may have to be relaxed | |
557 | in to compare/branch instructions (8 bytes) if the final | |
558 | address displacement is greater than 13 bits. */ | |
559 | ||
560 | static void | |
47990a6a | 561 | get_cdisp (const char *dispP, /* Displacement as specified in source instruction. */ |
e0471c16 | 562 | const char *ifmtP, /* "COBR" or "CTRL" (for use in error message). */ |
ea1562b3 NC |
563 | long instr, /* Instruction needing the displacement. */ |
564 | int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */ | |
565 | int var_frag,/* 1 if varying length code fragment should be emitted; | |
566 | 0 if an address fix should be emitted. */ | |
3739860c | 567 | int callj) /* 1 if callj relocation should be done; else 0. */ |
ea1562b3 NC |
568 | { |
569 | expressionS e; /* Parsed expression. */ | |
570 | fixS *fixP; /* Structure describing needed address fix. */ | |
571 | char *outP; /* Where instruction binary is output to. */ | |
572 | ||
573 | fixP = NULL; | |
574 | ||
575 | parse_expr (dispP, &e); | |
576 | switch (e.X_op) | |
252b5132 | 577 | { |
ea1562b3 NC |
578 | case O_illegal: |
579 | as_bad (_("expression syntax error")); | |
580 | ||
581 | case O_symbol: | |
582 | if (S_GET_SEGMENT (e.X_add_symbol) == now_seg | |
583 | || S_GET_SEGMENT (e.X_add_symbol) == undefined_section) | |
252b5132 | 584 | { |
ea1562b3 | 585 | if (var_frag) |
252b5132 | 586 | { |
ea1562b3 NC |
587 | outP = frag_more (8); /* Allocate worst-case storage. */ |
588 | md_number_to_chars (outP, instr, 4); | |
589 | frag_variant (rs_machine_dependent, 4, 4, 1, | |
590 | adds (e), offs (e), outP); | |
252b5132 | 591 | } |
ea1562b3 | 592 | else |
252b5132 | 593 | { |
ea1562b3 NC |
594 | /* Set up a new fix structure, so address can be updated |
595 | when all symbol values are known. */ | |
596 | outP = emit (instr); | |
597 | fixP = fix_new (frag_now, | |
598 | outP - frag_now->fr_literal, | |
599 | 4, | |
600 | adds (e), | |
601 | offs (e), | |
602 | 1, | |
603 | NO_RELOC); | |
604 | ||
605 | fixP->fx_tcbit = callj; | |
606 | ||
607 | /* We want to modify a bit field when the address is | |
608 | known. But we don't need all the garbage in the | |
609 | bit_fix structure. So we're going to lie and store | |
610 | the number of bits affected instead of a pointer. */ | |
611 | fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits; | |
252b5132 | 612 | } |
252b5132 | 613 | } |
ea1562b3 NC |
614 | else |
615 | as_bad (_("attempt to branch into different segment")); | |
616 | break; | |
252b5132 | 617 | |
ea1562b3 NC |
618 | default: |
619 | as_bad (_("target of %s instruction must be a label"), ifmtP); | |
620 | break; | |
621 | } | |
252b5132 RH |
622 | } |
623 | ||
b9195351 | 624 | static int |
ea1562b3 NC |
625 | md_chars_to_number (char * val, /* Value in target byte order. */ |
626 | int n) /* Number of bytes in the input. */ | |
252b5132 RH |
627 | { |
628 | int retval; | |
629 | ||
630 | for (retval = 0; n--;) | |
631 | { | |
632 | retval <<= 8; | |
2132e3a3 | 633 | retval |= (unsigned char) val[n]; |
252b5132 RH |
634 | } |
635 | return retval; | |
636 | } | |
637 | ||
ea1562b3 | 638 | /* mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. |
252b5132 | 639 | |
ea1562b3 NC |
640 | There are 2 possible MEMA formats: |
641 | - displacement only | |
642 | - displacement + abase | |
252b5132 | 643 | |
ea1562b3 | 644 | They are distinguished by the setting of the MEMA_ABASE bit. */ |
252b5132 | 645 | |
ea1562b3 NC |
646 | static void |
647 | mema_to_memb (char * opcodeP) /* Where to find the opcode, in target byte order. */ | |
252b5132 | 648 | { |
ea1562b3 NC |
649 | long opcode; /* Opcode in host byte order. */ |
650 | long mode; /* Mode bits for MEMB instruction. */ | |
252b5132 | 651 | |
ea1562b3 NC |
652 | opcode = md_chars_to_number (opcodeP, 4); |
653 | know (!(opcode & MEMB_BIT)); | |
252b5132 | 654 | |
ea1562b3 NC |
655 | mode = MEMB_BIT | D_BIT; |
656 | if (opcode & MEMA_ABASE) | |
657 | mode |= A_BIT; | |
252b5132 | 658 | |
ea1562b3 NC |
659 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits. */ |
660 | opcode |= mode; /* Set MEMB mode bits. */ | |
252b5132 | 661 | |
ea1562b3 | 662 | md_number_to_chars (opcodeP, opcode, 4); |
252b5132 RH |
663 | } |
664 | ||
ea1562b3 | 665 | /* targ_has_sfr: |
252b5132 | 666 | |
ea1562b3 NC |
667 | Return TRUE iff the target architecture supports the specified |
668 | special-function register (sfr). */ | |
252b5132 | 669 | |
ea1562b3 NC |
670 | static int |
671 | targ_has_sfr (int n) /* Number (0-31) of sfr. */ | |
252b5132 | 672 | { |
ea1562b3 NC |
673 | switch (architecture) |
674 | { | |
675 | case ARCH_KA: | |
676 | case ARCH_KB: | |
677 | case ARCH_MC: | |
678 | case ARCH_JX: | |
679 | return 0; | |
680 | case ARCH_HX: | |
681 | return ((0 <= n) && (n <= 4)); | |
682 | case ARCH_CA: | |
683 | default: | |
684 | return ((0 <= n) && (n <= 2)); | |
685 | } | |
252b5132 RH |
686 | } |
687 | ||
ea1562b3 NC |
688 | /* Look up a (suspected) register name in the register table and return the |
689 | associated register number (or -1 if not found). */ | |
690 | ||
691 | static int | |
692 | get_regnum (char *regname) /* Suspected register name. */ | |
693 | { | |
694 | int *rP; | |
252b5132 | 695 | |
ea1562b3 NC |
696 | rP = (int *) hash_find (reg_hash, regname); |
697 | return (rP == NULL) ? -1 : *rP; | |
698 | } | |
252b5132 | 699 | |
ea1562b3 | 700 | /* syntax: Issue a syntax error. */ |
b9195351 AM |
701 | |
702 | static void | |
ea1562b3 | 703 | syntax (void) |
252b5132 | 704 | { |
ea1562b3 NC |
705 | as_bad (_("syntax error")); |
706 | } | |
252b5132 | 707 | |
ea1562b3 | 708 | /* parse_regop: parse a register operand. |
252b5132 | 709 | |
ea1562b3 NC |
710 | In case of illegal operand, issue a message and return some valid |
711 | information so instruction processing can continue. */ | |
252b5132 | 712 | |
ea1562b3 NC |
713 | static void |
714 | parse_regop (struct regop *regopP, /* Where to put description of register operand. */ | |
715 | char *optext, /* Text of operand. */ | |
716 | char opdesc) /* Descriptor byte: what's legal for this operand. */ | |
717 | { | |
718 | int n; /* Register number. */ | |
719 | expressionS e; /* Parsed expression. */ | |
252b5132 | 720 | |
ea1562b3 NC |
721 | /* See if operand is a register. */ |
722 | n = get_regnum (optext); | |
723 | if (n >= 0) | |
252b5132 | 724 | { |
ea1562b3 NC |
725 | if (IS_RG_REG (n)) |
726 | { | |
727 | /* Global or local register. */ | |
728 | if (!REG_ALIGN (opdesc, n)) | |
729 | as_bad (_("unaligned register")); | |
252b5132 | 730 | |
ea1562b3 NC |
731 | regopP->n = n; |
732 | regopP->mode = 0; | |
733 | regopP->special = 0; | |
734 | return; | |
735 | } | |
736 | else if (IS_FP_REG (n) && FP_OK (opdesc)) | |
737 | { | |
738 | /* Floating point register, and it's allowed. */ | |
739 | regopP->n = n - FP0; | |
740 | regopP->mode = 1; | |
741 | regopP->special = 0; | |
742 | return; | |
743 | } | |
744 | else if (IS_SF_REG (n) && SFR_OK (opdesc)) | |
745 | { | |
746 | /* Special-function register, and it's allowed. */ | |
747 | regopP->n = n - SF0; | |
748 | regopP->mode = 0; | |
749 | regopP->special = 1; | |
750 | if (!targ_has_sfr (regopP->n)) | |
751 | as_bad (_("no such sfr in this architecture")); | |
252b5132 | 752 | |
ea1562b3 NC |
753 | return; |
754 | } | |
755 | } | |
756 | else if (LIT_OK (opdesc)) | |
757 | { | |
758 | /* How about a literal? */ | |
759 | regopP->mode = 1; | |
760 | regopP->special = 0; | |
761 | if (FP_OK (opdesc)) | |
762 | { | |
763 | /* Floating point literal acceptable. */ | |
764 | /* Skip over 0f, 0d, or 0e prefix. */ | |
765 | if ((optext[0] == '0') | |
766 | && (optext[1] >= 'd') | |
767 | && (optext[1] <= 'f')) | |
768 | optext += 2; | |
252b5132 | 769 | |
ea1562b3 NC |
770 | if (!strcmp (optext, "0.0") || !strcmp (optext, "0")) |
771 | { | |
772 | regopP->n = 0x10; | |
773 | return; | |
774 | } | |
252b5132 | 775 | |
ea1562b3 NC |
776 | if (!strcmp (optext, "1.0") || !strcmp (optext, "1")) |
777 | { | |
778 | regopP->n = 0x16; | |
779 | return; | |
780 | } | |
781 | } | |
782 | else | |
783 | { | |
784 | /* Fixed point literal acceptable. */ | |
785 | parse_expr (optext, &e); | |
786 | if (e.X_op != O_constant | |
787 | || (offs (e) < 0) || (offs (e) > 31)) | |
788 | { | |
789 | as_bad (_("illegal literal")); | |
790 | offs (e) = 0; | |
791 | } | |
792 | regopP->n = offs (e); | |
793 | return; | |
794 | } | |
795 | } | |
252b5132 | 796 | |
ea1562b3 NC |
797 | /* Nothing worked. */ |
798 | syntax (); | |
799 | regopP->mode = 0; /* Register r0 is always a good one. */ | |
800 | regopP->n = 0; | |
801 | regopP->special = 0; | |
802 | } | |
252b5132 | 803 | |
ea1562b3 | 804 | /* get_ispec: parse a memory operand for an index specification |
3739860c | 805 | |
ea1562b3 NC |
806 | Here, an "index specification" is taken to be anything surrounded |
807 | by square brackets and NOT followed by anything else. | |
252b5132 | 808 | |
ea1562b3 NC |
809 | If it's found, detach it from the input string, remove the surrounding |
810 | square brackets, and return a pointer to it. Otherwise, return NULL. */ | |
252b5132 | 811 | |
ea1562b3 NC |
812 | static char * |
813 | get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */ | |
3739860c | 814 | |
252b5132 | 815 | { |
ea1562b3 NC |
816 | /* Points to start of index specification. */ |
817 | char *start; | |
818 | /* Points to end of index specification. */ | |
819 | char *end; | |
252b5132 | 820 | |
ea1562b3 NC |
821 | /* Find opening square bracket, if any. */ |
822 | start = strchr (textP, '['); | |
252b5132 | 823 | |
ea1562b3 | 824 | if (start != NULL) |
252b5132 | 825 | { |
ea1562b3 NC |
826 | /* Eliminate '[', detach from rest of operand. */ |
827 | *start++ = '\0'; | |
252b5132 | 828 | |
ea1562b3 | 829 | end = strchr (start, ']'); |
252b5132 | 830 | |
ea1562b3 NC |
831 | if (end == NULL) |
832 | as_bad (_("unmatched '['")); | |
833 | else | |
834 | { | |
835 | /* Eliminate ']' and make sure it was the last thing | |
836 | in the string. */ | |
837 | *end = '\0'; | |
838 | if (*(end + 1) != '\0') | |
839 | as_bad (_("garbage after index spec ignored")); | |
840 | } | |
841 | } | |
842 | return start; | |
843 | } | |
252b5132 | 844 | |
ea1562b3 | 845 | /* parse_memop: parse a memory operand |
252b5132 | 846 | |
ea1562b3 NC |
847 | This routine is based on the observation that the 4 mode bits of the |
848 | MEMB format, taken individually, have fairly consistent meaning: | |
252b5132 | 849 | |
ea1562b3 NC |
850 | M3 (bit 13): 1 if displacement is present (D_BIT) |
851 | M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) | |
852 | M1 (bit 11): 1 if index is present (I_BIT) | |
853 | M0 (bit 10): 1 if abase is present (A_BIT) | |
252b5132 | 854 | |
ea1562b3 NC |
855 | So we parse the memory operand and set bits in the mode as we find |
856 | things. Then at the end, if we go to MEMB format, we need only set | |
857 | the MEMB bit (M2) and our mode is built for us. | |
252b5132 | 858 | |
ea1562b3 | 859 | Unfortunately, I said "fairly consistent". The exceptions: |
252b5132 | 860 | |
ea1562b3 NC |
861 | DBIA |
862 | 0100 Would seem illegal, but means "abase-only". | |
252b5132 | 863 | |
ea1562b3 NC |
864 | 0101 Would seem to mean "abase-only" -- it means IP-relative. |
865 | Must be converted to 0100. | |
252b5132 | 866 | |
ea1562b3 NC |
867 | 0110 Would seem to mean "index-only", but is reserved. |
868 | We turn on the D bit and provide a 0 displacement. | |
252b5132 | 869 | |
ea1562b3 NC |
870 | The other thing to observe is that we parse from the right, peeling |
871 | things * off as we go: first any index spec, then any abase, then | |
872 | the displacement. */ | |
252b5132 | 873 | |
ea1562b3 NC |
874 | static void |
875 | parse_memop (memS *memP, /* Where to put the results. */ | |
876 | char *argP, /* Text of the operand to be parsed. */ | |
877 | int optype) /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16. */ | |
252b5132 | 878 | { |
ea1562b3 NC |
879 | char *indexP; /* Pointer to index specification with "[]" removed. */ |
880 | char *p; /* Temp char pointer. */ | |
881 | char iprel_flag; /* True if this is an IP-relative operand. */ | |
882 | int regnum; /* Register number. */ | |
883 | /* Scale factor: 1,2,4,8, or 16. Later converted to internal format | |
884 | (0,1,2,3,4 respectively). */ | |
885 | int scale; | |
886 | int mode; /* MEMB mode bits. */ | |
887 | int *intP; /* Pointer to register number. */ | |
252b5132 | 888 | |
ea1562b3 NC |
889 | /* The following table contains the default scale factors for each |
890 | type of memory instruction. It is accessed using (optype-MEM1) | |
891 | as an index -- thus it assumes the 'optype' constants are | |
892 | assigned consecutive values, in the order they appear in this | |
893 | table. */ | |
894 | static const int def_scale[] = | |
895 | { | |
896 | 1, /* MEM1 */ | |
897 | 2, /* MEM2 */ | |
898 | 4, /* MEM4 */ | |
899 | 8, /* MEM8 */ | |
900 | -1, /* MEM12 -- no valid default */ | |
901 | 16 /* MEM16 */ | |
902 | }; | |
252b5132 | 903 | |
ea1562b3 | 904 | iprel_flag = mode = 0; |
252b5132 | 905 | |
ea1562b3 NC |
906 | /* Any index present? */ |
907 | indexP = get_ispec (argP); | |
908 | if (indexP) | |
252b5132 | 909 | { |
ea1562b3 NC |
910 | p = strchr (indexP, '*'); |
911 | if (p == NULL) | |
912 | { | |
913 | /* No explicit scale -- use default for this instruction | |
914 | type and assembler mode. */ | |
915 | if (flag_mri) | |
916 | scale = 1; | |
917 | else | |
918 | /* GNU960 compatibility */ | |
919 | scale = def_scale[optype - MEM1]; | |
920 | } | |
921 | else | |
922 | { | |
923 | *p++ = '\0'; /* Eliminate '*' */ | |
252b5132 | 924 | |
ea1562b3 NC |
925 | /* Now indexP->a '\0'-terminated register name, |
926 | and p->a scale factor. */ | |
252b5132 | 927 | |
ea1562b3 NC |
928 | if (!strcmp (p, "16")) |
929 | scale = 16; | |
930 | else if (strchr ("1248", *p) && (p[1] == '\0')) | |
931 | scale = *p - '0'; | |
932 | else | |
933 | scale = -1; | |
934 | } | |
252b5132 | 935 | |
ea1562b3 NC |
936 | regnum = get_regnum (indexP); /* Get index reg. # */ |
937 | if (!IS_RG_REG (regnum)) | |
938 | { | |
939 | as_bad (_("invalid index register")); | |
940 | return; | |
941 | } | |
252b5132 | 942 | |
ea1562b3 NC |
943 | /* Convert scale to its binary encoding. */ |
944 | switch (scale) | |
945 | { | |
946 | case 1: | |
947 | scale = 0 << 7; | |
948 | break; | |
949 | case 2: | |
950 | scale = 1 << 7; | |
951 | break; | |
952 | case 4: | |
953 | scale = 2 << 7; | |
954 | break; | |
955 | case 8: | |
956 | scale = 3 << 7; | |
957 | break; | |
958 | case 16: | |
959 | scale = 4 << 7; | |
960 | break; | |
961 | default: | |
962 | as_bad (_("invalid scale factor")); | |
963 | return; | |
964 | }; | |
bedf545c | 965 | |
ea1562b3 NC |
966 | memP->opcode |= scale | regnum; /* Set index bits in opcode. */ |
967 | mode |= I_BIT; /* Found a valid index spec. */ | |
968 | } | |
252b5132 | 969 | |
ea1562b3 NC |
970 | /* Any abase (Register Indirect) specification present? */ |
971 | if ((p = strrchr (argP, '(')) != NULL) | |
972 | { | |
973 | /* "(" is there -- does it start a legal abase spec? If not, it | |
974 | could be part of a displacement expression. */ | |
975 | intP = (int *) hash_find (areg_hash, p); | |
976 | if (intP != NULL) | |
977 | { | |
978 | /* Got an abase here. */ | |
979 | regnum = *intP; | |
980 | *p = '\0'; /* Discard register spec. */ | |
981 | if (regnum == IPREL) | |
982 | /* We have to specialcase ip-rel mode. */ | |
983 | iprel_flag = 1; | |
984 | else | |
985 | { | |
986 | memP->opcode |= regnum << 14; | |
987 | mode |= A_BIT; | |
988 | } | |
989 | } | |
990 | } | |
bedf545c | 991 | |
ea1562b3 NC |
992 | /* Any expression present? */ |
993 | memP->e = argP; | |
994 | if (*argP != '\0') | |
995 | mode |= D_BIT; | |
252b5132 | 996 | |
ea1562b3 NC |
997 | /* Special-case ip-relative addressing. */ |
998 | if (iprel_flag) | |
999 | { | |
1000 | if (mode & I_BIT) | |
1001 | syntax (); | |
1002 | else | |
1003 | { | |
1004 | memP->opcode |= 5 << 10; /* IP-relative mode. */ | |
1005 | memP->disp = 32; | |
1006 | } | |
1007 | return; | |
1008 | } | |
252b5132 | 1009 | |
ea1562b3 NC |
1010 | /* Handle all other modes. */ |
1011 | switch (mode) | |
1012 | { | |
1013 | case D_BIT | A_BIT: | |
1014 | /* Go with MEMA instruction format for now (grow to MEMB later | |
1015 | if 12 bits is not enough for the displacement). MEMA format | |
1016 | has a single mode bit: set it to indicate that abase is | |
1017 | present. */ | |
1018 | memP->opcode |= MEMA_ABASE; | |
1019 | memP->disp = 12; | |
1020 | break; | |
252b5132 | 1021 | |
ea1562b3 NC |
1022 | case D_BIT: |
1023 | /* Go with MEMA instruction format for now (grow to MEMB later | |
1024 | if 12 bits is not enough for the displacement). */ | |
1025 | memP->disp = 12; | |
1026 | break; | |
252b5132 | 1027 | |
ea1562b3 NC |
1028 | case A_BIT: |
1029 | /* For some reason, the bit string for this mode is not | |
1030 | consistent: it should be 0 (exclusive of the MEMB bit), so we | |
1031 | set it "by hand" here. */ | |
1032 | memP->opcode |= MEMB_BIT; | |
1033 | break; | |
252b5132 | 1034 | |
ea1562b3 NC |
1035 | case A_BIT | I_BIT: |
1036 | /* set MEMB bit in mode, and OR in mode bits. */ | |
1037 | memP->opcode |= mode | MEMB_BIT; | |
1038 | break; | |
252b5132 | 1039 | |
ea1562b3 NC |
1040 | case I_BIT: |
1041 | /* Treat missing displacement as displacement of 0. */ | |
1042 | mode |= D_BIT; | |
1043 | /* Fall into next case. */ | |
1044 | case D_BIT | A_BIT | I_BIT: | |
1045 | case D_BIT | I_BIT: | |
1046 | /* Set MEMB bit in mode, and OR in mode bits. */ | |
1047 | memP->opcode |= mode | MEMB_BIT; | |
1048 | memP->disp = 32; | |
1049 | break; | |
252b5132 | 1050 | |
ea1562b3 NC |
1051 | default: |
1052 | syntax (); | |
1053 | break; | |
1054 | } | |
1055 | } | |
252b5132 | 1056 | |
ea1562b3 | 1057 | /* Generate a MEMA- or MEMB-format instruction. */ |
252b5132 | 1058 | |
ea1562b3 NC |
1059 | static void |
1060 | mem_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */ | |
1061 | struct i960_opcode *oP,/* Pointer to description of instruction. */ | |
1062 | int callx) /* Is this a callx opcode. */ | |
252b5132 | 1063 | { |
ea1562b3 NC |
1064 | int i; /* Loop counter. */ |
1065 | struct regop regop; /* Description of register operand. */ | |
1066 | char opdesc; /* Operand descriptor byte. */ | |
1067 | memS instr; /* Description of binary to be output. */ | |
1068 | char *outP; /* Where the binary was output to. */ | |
87975d2a | 1069 | expressionS exp; /* Parsed expression. */ |
ea1562b3 | 1070 | /* ->description of deferred address fixup. */ |
252b5132 RH |
1071 | fixS *fixP; |
1072 | ||
ea1562b3 NC |
1073 | #ifdef OBJ_COFF |
1074 | /* COFF support isn't in place yet for callx relaxing. */ | |
1075 | callx = 0; | |
1076 | #endif | |
252b5132 | 1077 | |
ea1562b3 NC |
1078 | memset (&instr, '\0', sizeof (memS)); |
1079 | instr.opcode = oP->opcode; | |
252b5132 | 1080 | |
ea1562b3 NC |
1081 | /* Process operands. */ |
1082 | for (i = 1; i <= oP->num_ops; i++) | |
252b5132 | 1083 | { |
ea1562b3 NC |
1084 | opdesc = oP->operand[i - 1]; |
1085 | ||
1086 | if (MEMOP (opdesc)) | |
1087 | parse_memop (&instr, args[i], oP->format); | |
1088 | else | |
1089 | { | |
1090 | parse_regop (®op, args[i], opdesc); | |
1091 | instr.opcode |= regop.n << 19; | |
1092 | } | |
252b5132 | 1093 | } |
252b5132 | 1094 | |
ea1562b3 NC |
1095 | /* Parse the displacement; this must be done before emitting the |
1096 | opcode, in case it is an expression using `.'. */ | |
87975d2a | 1097 | parse_expr (instr.e, &exp); |
252b5132 | 1098 | |
ea1562b3 NC |
1099 | /* Output opcode. */ |
1100 | outP = emit (instr.opcode); | |
252b5132 | 1101 | |
ea1562b3 NC |
1102 | if (instr.disp == 0) |
1103 | return; | |
252b5132 | 1104 | |
ea1562b3 | 1105 | /* Process the displacement. */ |
87975d2a | 1106 | switch (exp.X_op) |
252b5132 | 1107 | { |
ea1562b3 NC |
1108 | case O_illegal: |
1109 | as_bad (_("expression syntax error")); | |
1110 | break; | |
252b5132 | 1111 | |
ea1562b3 NC |
1112 | case O_constant: |
1113 | if (instr.disp == 32) | |
87975d2a | 1114 | (void) emit (offs (exp)); /* Output displacement. */ |
ea1562b3 NC |
1115 | else |
1116 | { | |
1117 | /* 12-bit displacement. */ | |
87975d2a | 1118 | if (offs (exp) & ~0xfff) |
ea1562b3 NC |
1119 | { |
1120 | /* Won't fit in 12 bits: convert already-output | |
1121 | instruction to MEMB format, output | |
1122 | displacement. */ | |
1123 | mema_to_memb (outP); | |
87975d2a | 1124 | (void) emit (offs (exp)); |
ea1562b3 NC |
1125 | } |
1126 | else | |
1127 | { | |
1128 | /* WILL fit in 12 bits: OR into opcode and | |
1129 | overwrite the binary we already put out. */ | |
87975d2a | 1130 | instr.opcode |= offs (exp); |
ea1562b3 NC |
1131 | md_number_to_chars (outP, instr.opcode, 4); |
1132 | } | |
1133 | } | |
1134 | break; | |
252b5132 | 1135 | |
ea1562b3 NC |
1136 | default: |
1137 | if (instr.disp == 12) | |
1138 | /* Displacement is dependent on a symbol, whose value | |
1139 | may change at link time. We HAVE to reserve 32 bits. | |
1140 | Convert already-output opcode to MEMB format. */ | |
1141 | mema_to_memb (outP); | |
1142 | ||
1143 | /* Output 0 displacement and set up address fixup for when | |
1144 | this symbol's value becomes known. */ | |
1145 | outP = emit ((long) 0); | |
1146 | fixP = fix_new_exp (frag_now, | |
1147 | outP - frag_now->fr_literal, | |
87975d2a | 1148 | 4, &exp, 0, NO_RELOC); |
ea1562b3 NC |
1149 | /* Steve's linker relaxing hack. Mark this 32-bit relocation as |
1150 | being in the instruction stream, specifically as part of a callx | |
1151 | instruction. */ | |
1152 | fixP->fx_bsr = callx; | |
1153 | break; | |
252b5132 | 1154 | } |
ea1562b3 NC |
1155 | } |
1156 | ||
1157 | /* targ_has_iclass: | |
1158 | ||
1159 | Return TRUE iff the target architecture supports the indicated | |
1160 | class of instructions. */ | |
1161 | ||
1162 | static int | |
1163 | targ_has_iclass (int ic) /* Instruction class; one of: | |
1164 | I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2. */ | |
1165 | { | |
1166 | iclasses_seen |= ic; | |
1167 | ||
1168 | switch (architecture) | |
252b5132 | 1169 | { |
ea1562b3 NC |
1170 | case ARCH_KA: |
1171 | return ic & (I_BASE | I_KX); | |
1172 | case ARCH_KB: | |
1173 | return ic & (I_BASE | I_KX | I_FP | I_DEC); | |
1174 | case ARCH_MC: | |
1175 | return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); | |
1176 | case ARCH_CA: | |
1177 | return ic & (I_BASE | I_CX | I_CX2 | I_CASIM); | |
1178 | case ARCH_JX: | |
1179 | return ic & (I_BASE | I_CX2 | I_JX); | |
1180 | case ARCH_HX: | |
1181 | return ic & (I_BASE | I_CX2 | I_JX | I_HX); | |
1182 | default: | |
1183 | if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL)) | |
1184 | && (iclasses_seen & (I_CX | I_CX2))) | |
252b5132 | 1185 | { |
ea1562b3 NC |
1186 | as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)")); |
1187 | iclasses_seen &= ~ic; | |
252b5132 | 1188 | } |
ea1562b3 NC |
1189 | return 1; |
1190 | } | |
1191 | } | |
252b5132 | 1192 | |
ea1562b3 NC |
1193 | /* shift_ok: |
1194 | Determine if a "shlo" instruction can be used to implement a "ldconst". | |
1195 | This means that some number X < 32 can be shifted left to produce the | |
1196 | constant of interest. | |
252b5132 | 1197 | |
ea1562b3 NC |
1198 | Return the shift count, or 0 if we can't do it. |
1199 | Caller calculates X by shifting original constant right 'shift' places. */ | |
1200 | ||
1201 | static int | |
1202 | shift_ok (int n) /* The constant of interest. */ | |
1203 | { | |
1204 | int shift; /* The shift count. */ | |
1205 | ||
1206 | if (n <= 0) | |
1207 | /* Can't do it for negative numbers. */ | |
1208 | return 0; | |
1209 | ||
1210 | /* Shift 'n' right until a 1 is about to be lost. */ | |
1211 | for (shift = 0; (n & 1) == 0; shift++) | |
1212 | n >>= 1; | |
1213 | ||
1214 | if (n >= 32) | |
1215 | return 0; | |
1216 | ||
1217 | return shift; | |
1218 | } | |
1219 | ||
1220 | /* parse_ldcont: | |
1221 | Parse and replace a 'ldconst' pseudo-instruction with an appropriate | |
1222 | i80960 instruction. | |
1223 | ||
1224 | Assumes the input consists of: | |
1225 | arg[0] opcode mnemonic ('ldconst') | |
1226 | arg[1] first operand (constant) | |
1227 | arg[2] name of register to be loaded | |
1228 | ||
1229 | Replaces opcode and/or operands as appropriate. | |
1230 | ||
1231 | Returns the new number of arguments, or -1 on failure. */ | |
1232 | ||
1233 | static int | |
1234 | parse_ldconst (char *arg[]) /* See above. */ | |
1235 | { | |
1236 | int n; /* Constant to be loaded. */ | |
1237 | int shift; /* Shift count for "shlo" instruction. */ | |
1238 | static char buf[5]; /* Literal for first operand. */ | |
1239 | static char buf2[5]; /* Literal for second operand. */ | |
1240 | expressionS e; /* Parsed expression. */ | |
1241 | ||
1242 | arg[3] = NULL; /* So we can tell at the end if it got used or not. */ | |
1243 | ||
1244 | parse_expr (arg[1], &e); | |
1245 | switch (e.X_op) | |
1246 | { | |
1247 | default: | |
1248 | /* We're dependent on one or more symbols -- use "lda". */ | |
e2c7dcae | 1249 | arg[0] = (char *) "lda"; |
ea1562b3 NC |
1250 | break; |
1251 | ||
1252 | case O_constant: | |
1253 | /* Try the following mappings: | |
1254 | ldconst 0,<reg> -> mov 0,<reg> | |
1255 | ldconst 31,<reg> -> mov 31,<reg> | |
1256 | ldconst 32,<reg> -> addo 1,31,<reg> | |
1257 | ldconst 62,<reg> -> addo 31,31,<reg> | |
1258 | ldconst 64,<reg> -> shlo 8,3,<reg> | |
1259 | ldconst -1,<reg> -> subo 1,0,<reg> | |
1260 | ldconst -31,<reg> -> subo 31,0,<reg> | |
3739860c | 1261 | |
ea1562b3 NC |
1262 | Anything else becomes: |
1263 | lda xxx,<reg>. */ | |
1264 | n = offs (e); | |
1265 | if ((0 <= n) && (n <= 31)) | |
e2c7dcae | 1266 | arg[0] = (char *) "mov"; |
ea1562b3 | 1267 | else if ((-31 <= n) && (n <= -1)) |
252b5132 | 1268 | { |
e2c7dcae | 1269 | arg[0] = (char *) "subo"; |
ea1562b3 NC |
1270 | arg[3] = arg[2]; |
1271 | sprintf (buf, "%d", -n); | |
1272 | arg[1] = buf; | |
e2c7dcae | 1273 | arg[2] = (char *) "0"; |
ea1562b3 NC |
1274 | } |
1275 | else if ((32 <= n) && (n <= 62)) | |
1276 | { | |
e2c7dcae | 1277 | arg[0] = (char *) "addo"; |
ea1562b3 | 1278 | arg[3] = arg[2]; |
e2c7dcae | 1279 | arg[1] = (char *) "31"; |
ea1562b3 NC |
1280 | sprintf (buf, "%d", n - 31); |
1281 | arg[2] = buf; | |
252b5132 | 1282 | } |
ea1562b3 NC |
1283 | else if ((shift = shift_ok (n)) != 0) |
1284 | { | |
e2c7dcae | 1285 | arg[0] = (char *) "shlo"; |
ea1562b3 NC |
1286 | arg[3] = arg[2]; |
1287 | sprintf (buf, "%d", shift); | |
1288 | arg[1] = buf; | |
1289 | sprintf (buf2, "%d", n >> shift); | |
1290 | arg[2] = buf2; | |
1291 | } | |
1292 | else | |
e2c7dcae | 1293 | arg[0] = (char *) "lda"; |
ea1562b3 NC |
1294 | break; |
1295 | ||
1296 | case O_illegal: | |
1297 | as_bad (_("invalid constant")); | |
1298 | return -1; | |
1299 | break; | |
252b5132 | 1300 | } |
ea1562b3 NC |
1301 | return (arg[3] == 0) ? 2 : 3; |
1302 | } | |
252b5132 | 1303 | |
ea1562b3 | 1304 | /* reg_fmt: generate a REG-format instruction. */ |
252b5132 | 1305 | |
b9195351 | 1306 | static void |
ea1562b3 NC |
1307 | reg_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */ |
1308 | struct i960_opcode *oP)/* Pointer to description of instruction. */ | |
252b5132 | 1309 | { |
ea1562b3 NC |
1310 | long instr; /* Binary to be output. */ |
1311 | struct regop regop; /* Description of register operand. */ | |
1312 | int n_ops; /* Number of operands. */ | |
252b5132 | 1313 | |
ea1562b3 NC |
1314 | instr = oP->opcode; |
1315 | n_ops = oP->num_ops; | |
252b5132 | 1316 | |
ea1562b3 NC |
1317 | if (n_ops >= 1) |
1318 | { | |
1319 | parse_regop (®op, args[1], oP->operand[0]); | |
252b5132 | 1320 | |
ea1562b3 | 1321 | if ((n_ops == 1) && !(instr & M3)) |
252b5132 | 1322 | { |
ea1562b3 NC |
1323 | /* 1-operand instruction in which the dst field should |
1324 | be used (instead of src1). */ | |
1325 | regop.n <<= 19; | |
1326 | if (regop.special) | |
1327 | regop.mode = regop.special; | |
1328 | regop.mode <<= 13; | |
1329 | regop.special = 0; | |
252b5132 | 1330 | } |
ea1562b3 | 1331 | else |
252b5132 | 1332 | { |
ea1562b3 NC |
1333 | /* regop.n goes in bit 0, needs no shifting. */ |
1334 | regop.mode <<= 11; | |
1335 | regop.special <<= 5; | |
252b5132 | 1336 | } |
ea1562b3 | 1337 | instr |= regop.n | regop.mode | regop.special; |
252b5132 RH |
1338 | } |
1339 | ||
ea1562b3 NC |
1340 | if (n_ops >= 2) |
1341 | { | |
1342 | parse_regop (®op, args[2], oP->operand[1]); | |
252b5132 | 1343 | |
ea1562b3 NC |
1344 | if ((n_ops == 2) && !(instr & M3)) |
1345 | { | |
1346 | /* 2-operand instruction in which the dst field should | |
1347 | be used instead of src2). */ | |
1348 | regop.n <<= 19; | |
1349 | if (regop.special) | |
1350 | regop.mode = regop.special; | |
1351 | regop.mode <<= 13; | |
1352 | regop.special = 0; | |
1353 | } | |
1354 | else | |
1355 | { | |
1356 | regop.n <<= 14; | |
1357 | regop.mode <<= 12; | |
1358 | regop.special <<= 6; | |
1359 | } | |
1360 | instr |= regop.n | regop.mode | regop.special; | |
1361 | } | |
1362 | if (n_ops == 3) | |
1363 | { | |
1364 | parse_regop (®op, args[3], oP->operand[2]); | |
1365 | if (regop.special) | |
1366 | regop.mode = regop.special; | |
1367 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); | |
1368 | } | |
1369 | emit (instr); | |
252b5132 RH |
1370 | } |
1371 | ||
ea1562b3 | 1372 | /* get_args: break individual arguments out of comma-separated list |
252b5132 RH |
1373 | |
1374 | Input assumptions: | |
1375 | - all comments and labels have been removed | |
1376 | - all strings of whitespace have been collapsed to a single blank. | |
1377 | - all character constants ('x') have been replaced with decimal | |
1378 | ||
1379 | Output: | |
1380 | args[0] is untouched. args[1] points to first operand, etc. All args: | |
1381 | - are NULL-terminated | |
1382 | - contain no whitespace | |
1383 | ||
1384 | Return value: | |
ea1562b3 | 1385 | Number of operands (0,1,2, or 3) or -1 on error. */ |
252b5132 | 1386 | |
252b5132 | 1387 | static int |
ea1562b3 NC |
1388 | get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */ |
1389 | char *args[]) /* Output arg: pointers to operands placed in args[1-3]. | |
1390 | Must accommodate 4 entries (args[0-3]). */ | |
1391 | ||
252b5132 | 1392 | { |
ea1562b3 NC |
1393 | int n; /* Number of operands. */ |
1394 | char *to; | |
252b5132 | 1395 | |
ea1562b3 | 1396 | /* Skip lead white space. */ |
252b5132 | 1397 | while (*p == ' ') |
ea1562b3 | 1398 | p++; |
252b5132 RH |
1399 | |
1400 | if (*p == '\0') | |
ea1562b3 | 1401 | return 0; |
252b5132 RH |
1402 | |
1403 | n = 1; | |
1404 | args[1] = p; | |
1405 | ||
1406 | /* Squeze blanks out by moving non-blanks toward start of string. | |
ea1562b3 | 1407 | Isolate operands, whenever comma is found. */ |
252b5132 RH |
1408 | to = p; |
1409 | while (*p != '\0') | |
1410 | { | |
252b5132 | 1411 | if (*p == ' ' |
3882b010 L |
1412 | && (! ISALNUM (p[1]) |
1413 | || ! ISALNUM (p[-1]))) | |
ea1562b3 | 1414 | p++; |
252b5132 RH |
1415 | else if (*p == ',') |
1416 | { | |
ea1562b3 | 1417 | /* Start of operand. */ |
252b5132 RH |
1418 | if (n == 3) |
1419 | { | |
1420 | as_bad (_("too many operands")); | |
1421 | return -1; | |
1422 | } | |
ea1562b3 NC |
1423 | *to++ = '\0'; /* Terminate argument. */ |
1424 | args[++n] = to; /* Start next argument. */ | |
252b5132 | 1425 | p++; |
252b5132 RH |
1426 | } |
1427 | else | |
ea1562b3 | 1428 | *to++ = *p++; |
252b5132 RH |
1429 | } |
1430 | *to = '\0'; | |
1431 | return n; | |
1432 | } | |
1433 | ||
ea1562b3 | 1434 | /* i_scan: perform lexical scan of ascii assembler instruction. |
252b5132 | 1435 | |
ea1562b3 NC |
1436 | Input assumptions: |
1437 | - input string is an i80960 instruction (not a pseudo-op) | |
1438 | - all comments and labels have been removed | |
1439 | - all strings of whitespace have been collapsed to a single blank. | |
252b5132 | 1440 | |
ea1562b3 NC |
1441 | Output: |
1442 | args[0] points to opcode, other entries point to operands. All strings: | |
1443 | - are NULL-terminated | |
1444 | - contain no whitespace | |
1445 | - have character constants ('x') replaced with a decimal number | |
252b5132 RH |
1446 | |
1447 | Return value: | |
ea1562b3 | 1448 | Number of operands (0,1,2, or 3) or -1 on error. */ |
252b5132 | 1449 | |
252b5132 | 1450 | static int |
ea1562b3 NC |
1451 | i_scan (char *iP, /* Pointer to ascii instruction; Mucked by us. */ |
1452 | char *args[]) /* Output arg: pointers to opcode and operands placed here. | |
1453 | Must accommodate 4 entries. */ | |
252b5132 | 1454 | { |
ea1562b3 | 1455 | /* Isolate opcode. */ |
252b5132 | 1456 | if (*(iP) == ' ') |
ea1562b3 NC |
1457 | iP++; |
1458 | ||
252b5132 RH |
1459 | args[0] = iP; |
1460 | for (; *iP != ' '; iP++) | |
1461 | { | |
1462 | if (*iP == '\0') | |
1463 | { | |
ea1562b3 | 1464 | /* There are no operands. */ |
252b5132 RH |
1465 | if (args[0] == iP) |
1466 | { | |
ea1562b3 | 1467 | /* We never moved: there was no opcode either! */ |
252b5132 RH |
1468 | as_bad (_("missing opcode")); |
1469 | return -1; | |
1470 | } | |
1471 | return 0; | |
1472 | } | |
1473 | } | |
ea1562b3 | 1474 | *iP++ = '\0'; |
252b5132 | 1475 | return (get_args (iP, args)); |
ea1562b3 | 1476 | } |
252b5132 | 1477 | |
252b5132 | 1478 | static void |
ea1562b3 NC |
1479 | brcnt_emit (void) |
1480 | { | |
1481 | /* Emit call to "increment" routine. */ | |
1482 | ctrl_fmt (BR_CNT_FUNC, CALL, 1); | |
1483 | /* Emit inline counter to be incremented. */ | |
1484 | emit (0); | |
1485 | } | |
252b5132 | 1486 | |
ea1562b3 NC |
1487 | static char * |
1488 | brlab_next (void) | |
1489 | { | |
1490 | static char buf[20]; | |
252b5132 | 1491 | |
ea1562b3 NC |
1492 | sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++); |
1493 | return buf; | |
1494 | } | |
252b5132 | 1495 | |
ea1562b3 | 1496 | static void |
47990a6a | 1497 | ctrl_fmt (const char *targP, /* Pointer to text of lone operand (if any). */ |
ea1562b3 NC |
1498 | long opcode, /* Template of instruction. */ |
1499 | int num_ops) /* Number of operands. */ | |
1500 | { | |
1501 | int instrument; /* TRUE iff we should add instrumentation to track | |
1502 | how often the branch is taken. */ | |
1503 | ||
1504 | if (num_ops == 0) | |
1505 | emit (opcode); /* Output opcode. */ | |
1506 | else | |
252b5132 | 1507 | { |
ea1562b3 NC |
1508 | instrument = instrument_branches && (opcode != CALL) |
1509 | && (opcode != B) && (opcode != RET) && (opcode != BAL); | |
252b5132 | 1510 | |
ea1562b3 | 1511 | if (instrument) |
252b5132 | 1512 | { |
ea1562b3 NC |
1513 | brcnt_emit (); |
1514 | colon (brlab_next ()); | |
252b5132 | 1515 | } |
ea1562b3 NC |
1516 | |
1517 | /* The operand MUST be an ip-relative displacement. Parse it | |
1518 | and set up address fix for the instruction we just output. */ | |
1519 | get_cdisp (targP, "CTRL", opcode, 24, 0, 0); | |
1520 | ||
1521 | if (instrument) | |
1522 | brcnt_emit (); | |
252b5132 | 1523 | } |
ea1562b3 | 1524 | } |
252b5132 | 1525 | |
ea1562b3 NC |
1526 | static void |
1527 | cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ | |
1528 | char *arg[], | |
1529 | /* Opcode, with branch-prediction bits already set if necessary. */ | |
1530 | long opcode, | |
1531 | /* Pointer to description of instruction. */ | |
1532 | struct i960_opcode *oP) | |
1533 | { | |
1534 | long instr; /* 32-bit instruction. */ | |
1535 | struct regop regop; /* Description of register operand. */ | |
1536 | int n; /* Number of operands. */ | |
1537 | int var_frag; /* 1 if varying length code fragment should | |
1538 | be emitted; 0 if an address fix | |
1539 | should be emitted. */ | |
252b5132 | 1540 | |
ea1562b3 NC |
1541 | instr = opcode; |
1542 | n = oP->num_ops; | |
252b5132 | 1543 | |
ea1562b3 | 1544 | if (n >= 1) |
252b5132 | 1545 | { |
ea1562b3 NC |
1546 | /* First operand (if any) of a COBR is always a register |
1547 | operand. Parse it. */ | |
1548 | parse_regop (®op, arg[1], oP->operand[0]); | |
1549 | instr |= (regop.n << 19) | (regop.mode << 13); | |
252b5132 RH |
1550 | } |
1551 | ||
ea1562b3 | 1552 | if (n >= 2) |
252b5132 | 1553 | { |
ea1562b3 NC |
1554 | /* Second operand (if any) of a COBR is always a register |
1555 | operand. Parse it. */ | |
1556 | parse_regop (®op, arg[2], oP->operand[1]); | |
1557 | instr |= (regop.n << 14) | regop.special; | |
1558 | } | |
252b5132 | 1559 | |
ea1562b3 NC |
1560 | if (n < 3) |
1561 | emit (instr); | |
1562 | else | |
1563 | { | |
1564 | if (instrument_branches) | |
252b5132 | 1565 | { |
ea1562b3 NC |
1566 | brcnt_emit (); |
1567 | colon (brlab_next ()); | |
252b5132 | 1568 | } |
252b5132 | 1569 | |
ea1562b3 NC |
1570 | /* A third operand to a COBR is always a displacement. Parse |
1571 | it; if it's relaxable (a cobr "j" directive, or any cobr | |
1572 | other than bbs/bbc when the "-norelax" option is not in use) | |
1573 | set up a variable code fragment; otherwise set up an address | |
1574 | fix. */ | |
1575 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ | |
1576 | get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0); | |
252b5132 | 1577 | |
ea1562b3 NC |
1578 | if (instrument_branches) |
1579 | brcnt_emit (); | |
252b5132 | 1580 | } |
ea1562b3 | 1581 | } |
252b5132 | 1582 | |
ea1562b3 NC |
1583 | /* Assumptions about the passed-in text: |
1584 | - all comments, labels removed | |
1585 | - text is an instruction | |
1586 | - all white space compressed to single blanks | |
1587 | - all character constants have been replaced with decimal. */ | |
252b5132 | 1588 | |
ea1562b3 NC |
1589 | void |
1590 | md_assemble (char *textP) | |
1591 | { | |
1592 | /* Parsed instruction text, containing NO whitespace: arg[0]->opcode | |
1593 | mnemonic arg[1-3]->operands, with char constants replaced by | |
1594 | decimal numbers. */ | |
1595 | char *args[4]; | |
1596 | /* Number of instruction operands. */ | |
1597 | int n_ops; | |
1598 | /* Pointer to instruction description. */ | |
1599 | struct i960_opcode *oP; | |
1600 | /* TRUE iff opcode mnemonic included branch-prediction suffix (".f" | |
1601 | or ".t"). */ | |
1602 | int branch_predict; | |
1603 | /* Setting of branch-prediction bit(s) to be OR'd into instruction | |
1604 | opcode of CTRL/COBR format instructions. */ | |
1605 | long bp_bits; | |
1606 | /* Offset of last character in opcode mnemonic. */ | |
1607 | int n; | |
1608 | const char *bp_error_msg = _("branch prediction invalid on this opcode"); | |
252b5132 | 1609 | |
ea1562b3 NC |
1610 | /* Parse instruction into opcode and operands. */ |
1611 | memset (args, '\0', sizeof (args)); | |
252b5132 | 1612 | |
ea1562b3 | 1613 | n_ops = i_scan (textP, args); |
252b5132 | 1614 | |
ea1562b3 NC |
1615 | if (n_ops == -1) |
1616 | return; /* Error message already issued. */ | |
252b5132 | 1617 | |
ea1562b3 NC |
1618 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction. */ |
1619 | if (!strcmp (args[0], "ldconst")) | |
252b5132 | 1620 | { |
ea1562b3 NC |
1621 | n_ops = parse_ldconst (args); |
1622 | if (n_ops == -1) | |
1623 | return; | |
252b5132 RH |
1624 | } |
1625 | ||
ea1562b3 NC |
1626 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off. */ |
1627 | n = strlen (args[0]) - 1; | |
1628 | branch_predict = 0; | |
1629 | bp_bits = 0; | |
252b5132 | 1630 | |
ea1562b3 | 1631 | if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')) |
252b5132 | 1632 | { |
ea1562b3 NC |
1633 | /* We could check here to see if the target architecture |
1634 | supports branch prediction, but why bother? The bit will | |
1635 | just be ignored by processors that don't use it. */ | |
1636 | branch_predict = 1; | |
1637 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; | |
1638 | args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */ | |
252b5132 | 1639 | } |
252b5132 | 1640 | |
ea1562b3 NC |
1641 | /* Look up opcode mnemonic in table and check number of operands. |
1642 | Check that opcode is legal for the target architecture. If all | |
1643 | looks good, assemble instruction. */ | |
1644 | oP = (struct i960_opcode *) hash_find (op_hash, args[0]); | |
1645 | if (!oP || !targ_has_iclass (oP->iclass)) | |
1646 | as_bad (_("invalid opcode, \"%s\"."), args[0]); | |
1647 | else if (n_ops != oP->num_ops) | |
1648 | as_bad (_("improper number of operands. expecting %d, got %d"), | |
1649 | oP->num_ops, n_ops); | |
1650 | else | |
252b5132 | 1651 | { |
ea1562b3 | 1652 | switch (oP->format) |
252b5132 | 1653 | { |
ea1562b3 NC |
1654 | case FBRA: |
1655 | case CTRL: | |
1656 | ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops); | |
1657 | if (oP->format == FBRA) | |
1658 | /* Now generate a 'bno' to same arg */ | |
1659 | ctrl_fmt (args[1], BNO | bp_bits, 1); | |
252b5132 | 1660 | break; |
ea1562b3 NC |
1661 | case COBR: |
1662 | case COJ: | |
1663 | cobr_fmt (args, oP->opcode | bp_bits, oP); | |
252b5132 | 1664 | break; |
ea1562b3 NC |
1665 | case REG: |
1666 | if (branch_predict) | |
20203fb9 | 1667 | as_warn ("%s", bp_error_msg); |
ea1562b3 | 1668 | reg_fmt (args, oP); |
252b5132 | 1669 | break; |
ea1562b3 NC |
1670 | case MEM1: |
1671 | if (args[0][0] == 'c' && args[0][1] == 'a') | |
1672 | { | |
1673 | if (branch_predict) | |
20203fb9 | 1674 | as_warn ("%s", bp_error_msg); |
ea1562b3 NC |
1675 | mem_fmt (args, oP, 1); |
1676 | break; | |
1677 | } | |
1678 | case MEM2: | |
1679 | case MEM4: | |
1680 | case MEM8: | |
1681 | case MEM12: | |
1682 | case MEM16: | |
1683 | if (branch_predict) | |
20203fb9 | 1684 | as_warn ("%s", bp_error_msg); |
ea1562b3 | 1685 | mem_fmt (args, oP, 0); |
252b5132 | 1686 | break; |
ea1562b3 NC |
1687 | case CALLJ: |
1688 | if (branch_predict) | |
20203fb9 | 1689 | as_warn ("%s", bp_error_msg); |
ea1562b3 NC |
1690 | /* Output opcode & set up "fixup" (relocation); flag |
1691 | relocation as 'callj' type. */ | |
1692 | know (oP->num_ops == 1); | |
1693 | get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1); | |
252b5132 RH |
1694 | break; |
1695 | default: | |
ea1562b3 NC |
1696 | BAD_CASE (oP->format); |
1697 | break; | |
252b5132 | 1698 | } |
252b5132 | 1699 | } |
ea1562b3 | 1700 | } |
252b5132 | 1701 | |
ea1562b3 NC |
1702 | void |
1703 | md_number_to_chars (char *buf, | |
1704 | valueT value, | |
1705 | int n) | |
1706 | { | |
1707 | number_to_chars_littleendian (buf, value, n); | |
1708 | } | |
252b5132 | 1709 | |
6d4af3c2 | 1710 | const char * |
ea1562b3 | 1711 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 1712 | { |
499ac353 | 1713 | return ieee_md_atof (type, litP, sizeP, FALSE); |
ea1562b3 | 1714 | } |
252b5132 | 1715 | |
ea1562b3 NC |
1716 | static void |
1717 | md_number_to_imm (char *buf, long val, int n) | |
1718 | { | |
1719 | md_number_to_chars (buf, val, n); | |
1720 | } | |
252b5132 | 1721 | |
252b5132 | 1722 | static void |
ea1562b3 NC |
1723 | md_number_to_field (char *instrP, /* Pointer to instruction to be fixed. */ |
1724 | long val, /* Address fixup value. */ | |
1725 | bit_fixS *bfixP) /* Description of bit field to be fixed up. */ | |
252b5132 | 1726 | { |
ea1562b3 NC |
1727 | int numbits; /* Length of bit field to be fixed. */ |
1728 | long instr; /* 32-bit instruction to be fixed-up. */ | |
1729 | long sign; /* 0 or -1, according to sign bit of 'val'. */ | |
252b5132 | 1730 | |
ea1562b3 NC |
1731 | /* Convert instruction back to host byte order. */ |
1732 | instr = md_chars_to_number (instrP, 4); | |
252b5132 | 1733 | |
ea1562b3 NC |
1734 | /* Surprise! -- we stored the number of bits to be modified rather |
1735 | than a pointer to a structure. */ | |
1736 | numbits = (int) (size_t) bfixP; | |
1737 | if (numbits == 1) | |
1738 | /* This is a no-op, stuck here by reloc_callj(). */ | |
1739 | return; | |
252b5132 | 1740 | |
ea1562b3 | 1741 | know ((numbits == 13) || (numbits == 24)); |
252b5132 | 1742 | |
ea1562b3 NC |
1743 | /* Propagate sign bit of 'val' for the given number of bits. Result |
1744 | should be all 0 or all 1. */ | |
1745 | sign = val >> ((int) numbits - 1); | |
1746 | if (((val < 0) && (sign != -1)) | |
1747 | || ((val > 0) && (sign != 0))) | |
1748 | as_bad (_("Fixup of %ld too large for field width of %d"), | |
1749 | val, numbits); | |
1750 | else | |
252b5132 | 1751 | { |
ea1562b3 NC |
1752 | /* Put bit field into instruction and write back in target |
1753 | * byte order. */ | |
8d3842cd | 1754 | val &= ~(-(1 << (int) numbits)); /* Clear unused sign bits. */ |
ea1562b3 NC |
1755 | instr |= val; |
1756 | md_number_to_chars (instrP, instr, 4); | |
252b5132 | 1757 | } |
ea1562b3 NC |
1758 | } |
1759 | \f | |
1760 | ||
1761 | /* md_parse_option | |
1762 | Invocation line includes a switch not recognized by the base assembler. | |
1763 | See if it's a processor-specific option. For the 960, these are: | |
1764 | ||
1765 | -norelax: | |
1766 | Conditional branch instructions that require displacements | |
1767 | greater than 13 bits (or that have external targets) should | |
1768 | generate errors. The default is to replace each such | |
1769 | instruction with the corresponding compare (or chkbit) and | |
1770 | branch instructions. Note that the Intel "j" cobr directives | |
1771 | are ALWAYS "de-optimized" in this way when necessary, | |
1772 | regardless of the setting of this option. | |
1773 | ||
1774 | -b: | |
1775 | Add code to collect information about branches taken, for | |
1776 | later optimization of branch prediction bits by a separate | |
1777 | tool. COBR and CNTL format instructions have branch | |
1778 | prediction bits (in the CX architecture); if "BR" represents | |
1779 | an instruction in one of these classes, the following rep- | |
1780 | resents the code generated by the assembler: | |
1781 | ||
1782 | call <increment routine> | |
1783 | .word 0 # pre-counter | |
1784 | Label: BR | |
1785 | call <increment routine> | |
1786 | .word 0 # post-counter | |
1787 | ||
1788 | A table of all such "Labels" is also generated. | |
1789 | ||
1790 | -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: | |
1791 | Select the 80960 architecture. Instructions or features not | |
1792 | supported by the selected architecture cause fatal errors. | |
1793 | The default is to generate code for any instruction or feature | |
1794 | that is supported by SOME version of the 960 (even if this | |
1795 | means mixing architectures!). */ | |
1796 | ||
1797 | const char *md_shortopts = "A:b"; | |
1798 | struct option md_longopts[] = | |
1799 | { | |
1800 | #define OPTION_LINKRELAX (OPTION_MD_BASE) | |
1801 | {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, | |
1802 | {"link-relax", no_argument, NULL, OPTION_LINKRELAX}, | |
1803 | #define OPTION_NORELAX (OPTION_MD_BASE + 1) | |
1804 | {"norelax", no_argument, NULL, OPTION_NORELAX}, | |
1805 | {"no-relax", no_argument, NULL, OPTION_NORELAX}, | |
1806 | {NULL, no_argument, NULL, 0} | |
1807 | }; | |
1808 | size_t md_longopts_size = sizeof (md_longopts); | |
1809 | ||
1810 | struct tabentry | |
1811 | { | |
e0471c16 | 1812 | const char *flag; |
ea1562b3 NC |
1813 | int arch; |
1814 | }; | |
1815 | static const struct tabentry arch_tab[] = | |
1816 | { | |
1817 | {"KA", ARCH_KA}, | |
1818 | {"KB", ARCH_KB}, | |
1819 | {"SA", ARCH_KA}, /* Synonym for KA. */ | |
1820 | {"SB", ARCH_KB}, /* Synonym for KB. */ | |
1821 | {"KC", ARCH_MC}, /* Synonym for MC. */ | |
1822 | {"MC", ARCH_MC}, | |
1823 | {"CA", ARCH_CA}, | |
1824 | {"JX", ARCH_JX}, | |
1825 | {"HX", ARCH_HX}, | |
1826 | {NULL, 0} | |
1827 | }; | |
1828 | ||
1829 | int | |
17b9d67d | 1830 | md_parse_option (int c, const char *arg) |
ea1562b3 NC |
1831 | { |
1832 | switch (c) | |
252b5132 | 1833 | { |
ea1562b3 NC |
1834 | case OPTION_LINKRELAX: |
1835 | linkrelax = 1; | |
1836 | flag_keep_locals = 1; | |
1837 | break; | |
1838 | ||
1839 | case OPTION_NORELAX: | |
1840 | norelax = 1; | |
1841 | break; | |
1842 | ||
1843 | case 'b': | |
1844 | instrument_branches = 1; | |
1845 | break; | |
1846 | ||
1847 | case 'A': | |
1848 | { | |
1849 | const struct tabentry *tp; | |
17b9d67d | 1850 | const char *p = arg; |
ea1562b3 NC |
1851 | |
1852 | for (tp = arch_tab; tp->flag != NULL; tp++) | |
1853 | if (!strcmp (p, tp->flag)) | |
1854 | break; | |
1855 | ||
1856 | if (tp->flag == NULL) | |
1857 | { | |
1858 | as_bad (_("invalid architecture %s"), p); | |
1859 | return 0; | |
1860 | } | |
1861 | else | |
1862 | architecture = tp->arch; | |
1863 | } | |
1864 | break; | |
1865 | ||
1866 | default: | |
1867 | return 0; | |
252b5132 | 1868 | } |
ea1562b3 NC |
1869 | |
1870 | return 1; | |
252b5132 RH |
1871 | } |
1872 | ||
ea1562b3 NC |
1873 | void |
1874 | md_show_usage (FILE *stream) | |
1875 | { | |
1876 | int i; | |
252b5132 | 1877 | |
ea1562b3 NC |
1878 | fprintf (stream, _("I960 options:\n")); |
1879 | for (i = 0; arch_tab[i].flag; i++) | |
1880 | fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag); | |
1881 | fprintf (stream, _("\n\ | |
1882 | specify variant of 960 architecture\n\ | |
1883 | -b add code to collect statistics about branches taken\n\ | |
1884 | -link-relax preserve individual alignment directives so linker\n\ | |
1885 | can do relaxing (b.out format only)\n\ | |
1886 | -no-relax don't alter compare-and-branch instructions for\n\ | |
1887 | long displacements\n")); | |
1888 | } | |
1889 | \f | |
1890 | /* relax_cobr: | |
1891 | Replace cobr instruction in a code fragment with equivalent branch and | |
1892 | compare instructions, so it can reach beyond a 13-bit displacement. | |
1893 | Set up an address fix/relocation for the new branch instruction. */ | |
252b5132 RH |
1894 | |
1895 | /* This "conditional jump" table maps cobr instructions into | |
1896 | equivalent compare and branch opcodes. */ | |
ea1562b3 | 1897 | |
252b5132 RH |
1898 | static const |
1899 | struct | |
1900 | { | |
1901 | long compare; | |
1902 | long branch; | |
1903 | } | |
1904 | ||
1905 | coj[] = | |
1906 | { /* COBR OPCODE: */ | |
1907 | { CHKBIT, BNO }, /* 0x30 - bbc */ | |
1908 | { CMPO, BG }, /* 0x31 - cmpobg */ | |
1909 | { CMPO, BE }, /* 0x32 - cmpobe */ | |
1910 | { CMPO, BGE }, /* 0x33 - cmpobge */ | |
1911 | { CMPO, BL }, /* 0x34 - cmpobl */ | |
1912 | { CMPO, BNE }, /* 0x35 - cmpobne */ | |
1913 | { CMPO, BLE }, /* 0x36 - cmpoble */ | |
1914 | { CHKBIT, BO }, /* 0x37 - bbs */ | |
1915 | { CMPI, BNO }, /* 0x38 - cmpibno */ | |
1916 | { CMPI, BG }, /* 0x39 - cmpibg */ | |
1917 | { CMPI, BE }, /* 0x3a - cmpibe */ | |
1918 | { CMPI, BGE }, /* 0x3b - cmpibge */ | |
1919 | { CMPI, BL }, /* 0x3c - cmpibl */ | |
1920 | { CMPI, BNE }, /* 0x3d - cmpibne */ | |
1921 | { CMPI, BLE }, /* 0x3e - cmpible */ | |
1922 | { CMPI, BO }, /* 0x3f - cmpibo */ | |
1923 | }; | |
1924 | ||
b9195351 | 1925 | static void |
ea1562b3 NC |
1926 | relax_cobr (fragS *fragP) /* fragP->fr_opcode is assumed to point to |
1927 | the cobr instruction, which comes at the | |
1928 | end of the code fragment. */ | |
252b5132 RH |
1929 | { |
1930 | int opcode, src1, src2, m1, s2; | |
ea1562b3 NC |
1931 | /* Bit fields from cobr instruction. */ |
1932 | long bp_bits; /* Branch prediction bits from cobr instruction. */ | |
1933 | long instr; /* A single i960 instruction. */ | |
1934 | /* ->instruction to be replaced. */ | |
252b5132 | 1935 | char *iP; |
ea1562b3 | 1936 | fixS *fixP; /* Relocation that can be done at assembly time. */ |
252b5132 | 1937 | |
ea1562b3 | 1938 | /* Pick up & parse cobr instruction. */ |
252b5132 RH |
1939 | iP = fragP->fr_opcode; |
1940 | instr = md_chars_to_number (iP, 4); | |
ea1562b3 | 1941 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index. */ |
252b5132 RH |
1942 | src1 = (instr >> 19) & 0x1f; |
1943 | m1 = (instr >> 13) & 1; | |
1944 | s2 = instr & 1; | |
1945 | src2 = (instr >> 14) & 0x1f; | |
1946 | bp_bits = instr & BP_MASK; | |
1947 | ||
ea1562b3 | 1948 | /* Generate and output compare instruction. */ |
252b5132 RH |
1949 | instr = coj[opcode].compare |
1950 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); | |
1951 | md_number_to_chars (iP, instr, 4); | |
1952 | ||
ea1562b3 | 1953 | /* Output branch instruction. */ |
252b5132 RH |
1954 | md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4); |
1955 | ||
ea1562b3 | 1956 | /* Set up address fixup/relocation. */ |
252b5132 RH |
1957 | fixP = fix_new (fragP, |
1958 | iP + 4 - fragP->fr_literal, | |
1959 | 4, | |
1960 | fragP->fr_symbol, | |
1961 | fragP->fr_offset, | |
1962 | 1, | |
1963 | NO_RELOC); | |
1964 | ||
ea1562b3 NC |
1965 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field. */ |
1966 | ||
1967 | fragP->fr_fix += 4; | |
1968 | frag_wane (fragP); | |
1969 | } | |
1970 | ||
1971 | /* md_convert_frag: | |
1972 | ||
1973 | Called by base assembler after address relaxation is finished: modify | |
1974 | variable fragments according to how much relaxation was done. | |
1975 | ||
1976 | If the fragment substate is still 1, a 13-bit displacement was enough | |
1977 | to reach the symbol in question. Set up an address fixup, but otherwise | |
1978 | leave the cobr instruction alone. | |
1979 | ||
1980 | If the fragment substate is 2, a 13-bit displacement was not enough. | |
1981 | Replace the cobr with a two instructions (a compare and a branch). */ | |
1982 | ||
ea1562b3 NC |
1983 | void |
1984 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, | |
1985 | segT sec ATTRIBUTE_UNUSED, | |
1986 | fragS *fragP) | |
ea1562b3 NC |
1987 | { |
1988 | /* Structure describing needed address fix. */ | |
1989 | fixS *fixP; | |
1990 | ||
1991 | switch (fragP->fr_subtype) | |
1992 | { | |
1993 | case 1: | |
1994 | /* Leave single cobr instruction. */ | |
1995 | fixP = fix_new (fragP, | |
1996 | fragP->fr_opcode - fragP->fr_literal, | |
1997 | 4, | |
1998 | fragP->fr_symbol, | |
1999 | fragP->fr_offset, | |
2000 | 1, | |
2001 | NO_RELOC); | |
2002 | ||
2003 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* Size of bit field. */ | |
2004 | break; | |
2005 | case 2: | |
2006 | /* Replace cobr with compare/branch instructions. */ | |
2007 | relax_cobr (fragP); | |
2008 | break; | |
2009 | default: | |
2010 | BAD_CASE (fragP->fr_subtype); | |
2011 | break; | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | /* md_estimate_size_before_relax: How much does it look like *fragP will grow? | |
2016 | ||
2017 | Called by base assembler just before address relaxation. | |
2018 | Return the amount by which the fragment will grow. | |
2019 | ||
2020 | Any symbol that is now undefined will not become defined; cobr's | |
2021 | based on undefined symbols will have to be replaced with a compare | |
2022 | instruction and a branch instruction, and the code fragment will grow | |
2023 | by 4 bytes. */ | |
2024 | ||
2025 | int | |
2026 | md_estimate_size_before_relax (fragS *fragP, segT segment_type) | |
2027 | { | |
2028 | /* If symbol is undefined in this segment, go to "relaxed" state | |
2029 | (compare and branch instructions instead of cobr) right now. */ | |
2030 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type) | |
2031 | { | |
2032 | relax_cobr (fragP); | |
2033 | return 4; | |
2034 | } | |
2035 | ||
2036 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
2037 | } | |
2038 | ||
2039 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
2040 | ||
2041 | /* md_ri_to_chars: | |
2042 | This routine exists in order to overcome machine byte-order problems | |
2043 | when dealing with bit-field entries in the relocation_info struct. | |
252b5132 | 2044 | |
ea1562b3 NC |
2045 | But relocation info will be used on the host machine only (only |
2046 | executable code is actually downloaded to the i80960). Therefore, | |
2047 | we leave it in host byte order. */ | |
2048 | ||
2049 | static void | |
2050 | md_ri_to_chars (char *where, struct relocation_info *ri) | |
2051 | { | |
2052 | host_number_to_chars (where, ri->r_address, 4); | |
2053 | host_number_to_chars (where + 4, ri->r_index, 3); | |
2054 | #if WORDS_BIGENDIAN | |
2055 | where[7] = (ri->r_pcrel << 7 | |
2056 | | ri->r_length << 5 | |
2057 | | ri->r_extern << 4 | |
2058 | | ri->r_bsr << 3 | |
2059 | | ri->r_disp << 2 | |
2060 | | ri->r_callj << 1 | |
2061 | | ri->nuthin << 0); | |
2062 | #else | |
2063 | where[7] = (ri->r_pcrel << 0 | |
2064 | | ri->r_length << 1 | |
2065 | | ri->r_extern << 3 | |
2066 | | ri->r_bsr << 4 | |
2067 | | ri->r_disp << 5 | |
2068 | | ri->r_callj << 6 | |
2069 | | ri->nuthin << 7); | |
2070 | #endif | |
252b5132 RH |
2071 | } |
2072 | ||
ea1562b3 | 2073 | #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */ |
252b5132 | 2074 | |
ea1562b3 NC |
2075 | \f |
2076 | /* brtab_emit: generate the fetch-prediction branch table. | |
252b5132 | 2077 | |
ea1562b3 NC |
2078 | See the comments above the declaration of 'br_cnt' for details on |
2079 | branch-prediction instrumentation. | |
252b5132 | 2080 | |
ea1562b3 NC |
2081 | The code emitted here would be functionally equivalent to the following |
2082 | example assembler source. | |
252b5132 | 2083 | |
ea1562b3 NC |
2084 | .data |
2085 | .align 2 | |
2086 | BR_TAB_NAME: | |
2087 | .word 0 # link to next table | |
2088 | .word 3 # length of table | |
2089 | .word LBRANCH0 # 1st entry in table proper | |
2090 | .word LBRANCH1 | |
2091 | .word LBRANCH2 */ | |
252b5132 | 2092 | |
ea1562b3 NC |
2093 | void |
2094 | brtab_emit (void) | |
252b5132 | 2095 | { |
ea1562b3 NC |
2096 | int i; |
2097 | char buf[20]; | |
2098 | /* Where the binary was output to. */ | |
2099 | char *p; | |
252b5132 | 2100 | |
ea1562b3 NC |
2101 | if (!instrument_branches) |
2102 | return; | |
252b5132 | 2103 | |
ea1562b3 NC |
2104 | subseg_set (data_section, 0); /* .data */ |
2105 | frag_align (2, 0, 0); /* .align 2 */ | |
2106 | record_alignment (now_seg, 2); | |
2107 | colon (BR_TAB_NAME); /* BR_TAB_NAME: */ | |
2108 | emit (0); /* .word 0 #link to next table */ | |
2109 | emit (br_cnt); /* .word n #length of table */ | |
252b5132 | 2110 | |
ea1562b3 | 2111 | for (i = 0; i < br_cnt; i++) |
252b5132 | 2112 | { |
ea1562b3 NC |
2113 | sprintf (buf, "%s%d", BR_LABEL_BASE, i); |
2114 | p = emit (0); | |
87975d2a AM |
2115 | fix_new (frag_now, |
2116 | p - frag_now->fr_literal, | |
2117 | 4, symbol_find (buf), 0, 0, NO_RELOC); | |
252b5132 | 2118 | } |
252b5132 RH |
2119 | } |
2120 | ||
ea1562b3 | 2121 | /* s_leafproc: process .leafproc pseudo-op |
252b5132 RH |
2122 | |
2123 | .leafproc takes two arguments, the second one is optional: | |
2124 | arg[1]: name of 'call' entry point to leaf procedure | |
2125 | arg[2]: name of 'bal' entry point to leaf procedure | |
2126 | ||
2127 | If the two arguments are identical, or if the second one is missing, | |
2128 | the first argument is taken to be the 'bal' entry point. | |
2129 | ||
2130 | If there are 2 distinct arguments, we must make sure that the 'bal' | |
2131 | entry point immediately follows the 'call' entry point in the linked | |
ea1562b3 | 2132 | list of symbols. */ |
252b5132 | 2133 | |
252b5132 | 2134 | static void |
ea1562b3 NC |
2135 | s_leafproc (int n_ops, /* Number of operands. */ |
2136 | char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */ | |
252b5132 | 2137 | { |
ea1562b3 NC |
2138 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol. */ |
2139 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol. */ | |
252b5132 RH |
2140 | |
2141 | if ((n_ops != 1) && (n_ops != 2)) | |
2142 | { | |
2143 | as_bad (_("should have 1 or 2 operands")); | |
2144 | return; | |
ea1562b3 | 2145 | } |
252b5132 | 2146 | |
92774660 | 2147 | /* Find or create symbol for 'call' entry point. */ |
252b5132 RH |
2148 | callP = symbol_find_or_make (args[1]); |
2149 | ||
2150 | if (TC_S_IS_CALLNAME (callP)) | |
ea1562b3 | 2151 | as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP)); |
252b5132 RH |
2152 | |
2153 | /* If that was the only argument, use it as the 'bal' entry point. | |
ea1562b3 NC |
2154 | Otherwise, mark it as the 'call' entry point and find or create |
2155 | another symbol for the 'bal' entry point. */ | |
252b5132 RH |
2156 | if ((n_ops == 1) || !strcmp (args[1], args[2])) |
2157 | { | |
2158 | TC_S_FORCE_TO_BALNAME (callP); | |
252b5132 RH |
2159 | } |
2160 | else | |
2161 | { | |
2162 | TC_S_FORCE_TO_CALLNAME (callP); | |
2163 | ||
2164 | balP = symbol_find_or_make (args[2]); | |
2165 | if (TC_S_IS_CALLNAME (balP)) | |
ea1562b3 NC |
2166 | as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP)); |
2167 | ||
252b5132 RH |
2168 | TC_S_FORCE_TO_BALNAME (balP); |
2169 | ||
76171f81 | 2170 | #ifndef OBJ_ELF |
252b5132 | 2171 | tc_set_bal_of_call (callP, balP); |
76171f81 | 2172 | #endif |
ea1562b3 | 2173 | } |
252b5132 RH |
2174 | } |
2175 | ||
ea1562b3 | 2176 | /* s_sysproc: process .sysproc pseudo-op |
252b5132 | 2177 | |
ea1562b3 NC |
2178 | .sysproc takes two arguments: |
2179 | arg[1]: name of entry point to system procedure | |
2180 | arg[2]: 'entry_num' (index) of system procedure in the range | |
2181 | [0,31] inclusive. | |
2182 | ||
2183 | For [ab].out, we store the 'entrynum' in the 'n_other' field of | |
2184 | the symbol. Since that entry is normally 0, we bias 'entrynum' | |
2185 | by adding 1 to it. It must be unbiased before it is used. */ | |
252b5132 | 2186 | |
252b5132 | 2187 | static void |
ea1562b3 NC |
2188 | s_sysproc (int n_ops, /* Number of operands. */ |
2189 | char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */ | |
252b5132 RH |
2190 | { |
2191 | expressionS exp; | |
2192 | symbolS *symP; | |
2193 | ||
2194 | if (n_ops != 2) | |
2195 | { | |
2196 | as_bad (_("should have two operands")); | |
2197 | return; | |
ea1562b3 | 2198 | } |
252b5132 | 2199 | |
92774660 | 2200 | /* Parse "entry_num" argument and check it for validity. */ |
252b5132 RH |
2201 | parse_expr (args[2], &exp); |
2202 | if (exp.X_op != O_constant | |
2203 | || (offs (exp) < 0) | |
2204 | || (offs (exp) > 31)) | |
2205 | { | |
2206 | as_bad (_("'entry_num' must be absolute number in [0,31]")); | |
2207 | return; | |
2208 | } | |
2209 | ||
ea1562b3 | 2210 | /* Find/make symbol and stick entry number (biased by +1) into it. */ |
252b5132 RH |
2211 | symP = symbol_find_or_make (args[1]); |
2212 | ||
2213 | if (TC_S_IS_SYSPROC (symP)) | |
ea1562b3 | 2214 | as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP)); |
252b5132 | 2215 | |
ea1562b3 | 2216 | TC_S_SET_SYSPROC (symP, offs (exp)); /* Encode entry number. */ |
252b5132 RH |
2217 | TC_S_FORCE_TO_SYSPROC (symP); |
2218 | } | |
2219 | ||
ea1562b3 | 2220 | /* parse_po: parse machine-dependent pseudo-op |
252b5132 | 2221 | |
ea1562b3 NC |
2222 | This is a top-level routine for machine-dependent pseudo-ops. It slurps |
2223 | up the rest of the input line, breaks out the individual arguments, | |
2224 | and dispatches them to the correct handler. */ | |
252b5132 | 2225 | |
ea1562b3 NC |
2226 | static void |
2227 | parse_po (int po_num) /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC. */ | |
252b5132 | 2228 | { |
ea1562b3 NC |
2229 | /* Pointers operands, with no embedded whitespace. |
2230 | arg[0] unused, arg[1-3]->operands. */ | |
2231 | char *args[4]; | |
2232 | int n_ops; /* Number of operands. */ | |
2233 | char *p; /* Pointer to beginning of unparsed argument string. */ | |
2234 | char eol; /* Character that indicated end of line. */ | |
252b5132 | 2235 | |
ea1562b3 | 2236 | extern char is_end_of_line[]; |
252b5132 | 2237 | |
ea1562b3 NC |
2238 | /* Advance input pointer to end of line. */ |
2239 | p = input_line_pointer; | |
2240 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2241 | input_line_pointer++; | |
252b5132 | 2242 | |
ea1562b3 NC |
2243 | eol = *input_line_pointer; /* Save end-of-line char. */ |
2244 | *input_line_pointer = '\0'; /* Terminate argument list. */ | |
2245 | ||
2246 | /* Parse out operands. */ | |
2247 | n_ops = get_args (p, args); | |
2248 | if (n_ops == -1) | |
2249 | return; | |
2250 | ||
2251 | /* Dispatch to correct handler. */ | |
2252 | switch (po_num) | |
252b5132 | 2253 | { |
ea1562b3 NC |
2254 | case S_SYSPROC: |
2255 | s_sysproc (n_ops, args); | |
2256 | break; | |
2257 | case S_LEAFPROC: | |
2258 | s_leafproc (n_ops, args); | |
2259 | break; | |
2260 | default: | |
2261 | BAD_CASE (po_num); | |
2262 | break; | |
252b5132 | 2263 | } |
ea1562b3 NC |
2264 | |
2265 | /* Restore eol, so line numbers get updated correctly. Base | |
2266 | assembler assumes we leave input pointer pointing at char | |
2267 | following the eol. */ | |
2268 | *input_line_pointer++ = eol; | |
252b5132 RH |
2269 | } |
2270 | ||
ea1562b3 | 2271 | /* reloc_callj: Relocate a 'callj' instruction |
252b5132 | 2272 | |
ea1562b3 NC |
2273 | This is a "non-(GNU)-standard" machine-dependent hook. The base |
2274 | assembler calls it when it decides it can relocate an address at | |
2275 | assembly time instead of emitting a relocation directive. | |
252b5132 | 2276 | |
ea1562b3 NC |
2277 | Check to see if the relocation involves a 'callj' instruction to a: |
2278 | sysproc: Replace the default 'call' instruction with a 'calls' | |
2279 | leafproc: Replace the default 'call' instruction with a 'bal'. | |
2280 | other proc: Do nothing. | |
252b5132 | 2281 | |
ea1562b3 | 2282 | See b.out.h for details on the 'n_other' field in a symbol structure. |
252b5132 | 2283 | |
ea1562b3 NC |
2284 | IMPORTANT!: |
2285 | Assumes the caller has already figured out, in the case of a leafproc, | |
2286 | to use the 'bal' entry point, and has substituted that symbol into the | |
2287 | passed fixup structure. */ | |
2288 | ||
2289 | int | |
3739860c | 2290 | reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */ |
252b5132 | 2291 | { |
ea1562b3 NC |
2292 | /* Points to the binary for the instruction being relocated. */ |
2293 | char *where; | |
252b5132 | 2294 | |
ea1562b3 NC |
2295 | if (!fixP->fx_tcbit) |
2296 | /* This wasn't a callj instruction in the first place. */ | |
2297 | return 0; | |
252b5132 | 2298 | |
ea1562b3 NC |
2299 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
2300 | ||
2301 | if (TC_S_IS_SYSPROC (fixP->fx_addsy)) | |
252b5132 | 2302 | { |
ea1562b3 NC |
2303 | /* Symbol is a .sysproc: replace 'call' with 'calls'. System |
2304 | procedure number is (other-1). */ | |
2305 | md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4); | |
2306 | ||
2307 | /* Nothing else needs to be done for this instruction. Make | |
2308 | sure 'md_number_to_field()' will perform a no-op. */ | |
2309 | fixP->fx_bit_fixP = (bit_fixS *) 1; | |
2310 | } | |
2311 | else if (TC_S_IS_CALLNAME (fixP->fx_addsy)) | |
2312 | { | |
2313 | /* Should not happen: see block comment above. */ | |
2314 | as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy)); | |
2315 | } | |
2316 | else if (TC_S_IS_BALNAME (fixP->fx_addsy)) | |
2317 | { | |
2318 | /* Replace 'call' with 'bal'; both instructions have the same | |
2319 | format, so calling code should complete relocation as if | |
2320 | nothing happened here. */ | |
2321 | md_number_to_chars (where, BAL, 4); | |
252b5132 | 2322 | } |
ea1562b3 NC |
2323 | else if (TC_S_IS_BADPROC (fixP->fx_addsy)) |
2324 | as_bad (_("Looks like a proc, but can't tell what kind.\n")); | |
2325 | ||
2326 | /* Otherwise Symbol is neither a sysproc nor a leafproc. */ | |
2327 | return 0; | |
252b5132 RH |
2328 | } |
2329 | ||
2330 | /* Handle the MRI .endian pseudo-op. */ | |
2331 | ||
2332 | static void | |
ea1562b3 | 2333 | s_endian (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
2334 | { |
2335 | char *name; | |
2336 | char c; | |
2337 | ||
d02603dc | 2338 | c = get_symbol_name (&name); |
252b5132 RH |
2339 | if (strcasecmp (name, "little") == 0) |
2340 | ; | |
2341 | else if (strcasecmp (name, "big") == 0) | |
2342 | as_bad (_("big endian mode is not supported")); | |
2343 | else | |
2344 | as_warn (_("ignoring unrecognized .endian type `%s'"), name); | |
2345 | ||
d02603dc | 2346 | (void) restore_line_pointer (c); |
252b5132 RH |
2347 | |
2348 | demand_empty_rest_of_line (); | |
2349 | } | |
2350 | ||
92774660 | 2351 | /* We have no need to default values of symbols. */ |
252b5132 | 2352 | |
252b5132 | 2353 | symbolS * |
ea1562b3 | 2354 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2355 | { |
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | /* Exactly what point is a PC-relative offset relative TO? | |
2360 | On the i960, they're relative to the address of the instruction, | |
92774660 | 2361 | which we have set up as the address of the fixup too. */ |
252b5132 | 2362 | long |
ea1562b3 | 2363 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
2364 | { |
2365 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
2366 | } | |
2367 | ||
2368 | void | |
55cf6793 | 2369 | md_apply_fix (fixS *fixP, |
ea1562b3 NC |
2370 | valueT *valP, |
2371 | segT seg ATTRIBUTE_UNUSED) | |
252b5132 | 2372 | { |
a161fe53 | 2373 | long val = *valP; |
252b5132 RH |
2374 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; |
2375 | ||
2376 | if (!fixP->fx_bit_fixP) | |
2377 | { | |
b9195351 | 2378 | md_number_to_imm (place, val, fixP->fx_size); |
252b5132 | 2379 | } |
44f2f9d2 | 2380 | else if ((int) (size_t) fixP->fx_bit_fixP == 13 |
a161fe53 AM |
2381 | && fixP->fx_addsy != NULL |
2382 | && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section) | |
2383 | { | |
2384 | /* This is a COBR instruction. They have only a | |
2385 | 13-bit displacement and are only to be used | |
2386 | for local branches: flag as error, don't generate | |
2387 | relocation. */ | |
2388 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2389 | _("can't use COBR format with external label")); | |
2390 | fixP->fx_addsy = NULL; | |
2391 | } | |
252b5132 RH |
2392 | else |
2393 | md_number_to_field (place, val, fixP->fx_bit_fixP); | |
bedf545c | 2394 | |
a161fe53 | 2395 | if (fixP->fx_addsy == NULL) |
94f592af | 2396 | fixP->fx_done = 1; |
252b5132 RH |
2397 | } |
2398 | ||
2399 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
2400 | void | |
ea1562b3 NC |
2401 | tc_bout_fix_to_chars (char *where, |
2402 | fixS *fixP, | |
2403 | relax_addressT segment_address_in_file) | |
252b5132 RH |
2404 | { |
2405 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; | |
2406 | struct relocation_info ri; | |
2407 | symbolS *symbolP; | |
2408 | ||
2409 | memset ((char *) &ri, '\0', sizeof (ri)); | |
2410 | symbolP = fixP->fx_addsy; | |
2411 | know (symbolP != 0 || fixP->fx_r_type != NO_RELOC); | |
2412 | ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ | |
2413 | /* These two 'cuz of NS32K */ | |
2414 | ri.r_callj = fixP->fx_tcbit; | |
2415 | if (fixP->fx_bit_fixP) | |
2416 | ri.r_length = 2; | |
2417 | else | |
2418 | ri.r_length = nbytes_r_length[fixP->fx_size]; | |
2419 | ri.r_pcrel = fixP->fx_pcrel; | |
2420 | ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; | |
2421 | ||
2422 | if (fixP->fx_r_type != NO_RELOC) | |
2423 | { | |
2424 | switch (fixP->fx_r_type) | |
2425 | { | |
2426 | case rs_align: | |
2427 | ri.r_index = -2; | |
2428 | ri.r_pcrel = 1; | |
2429 | ri.r_length = fixP->fx_size - 1; | |
2430 | break; | |
2431 | case rs_org: | |
2432 | ri.r_index = -2; | |
2433 | ri.r_pcrel = 0; | |
2434 | break; | |
2435 | case rs_fill: | |
2436 | ri.r_index = -1; | |
2437 | break; | |
2438 | default: | |
2439 | abort (); | |
2440 | } | |
2441 | ri.r_extern = 0; | |
2442 | } | |
2443 | else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr) | |
2444 | { | |
2445 | ri.r_extern = 1; | |
2446 | ri.r_index = symbolP->sy_number; | |
2447 | } | |
2448 | else | |
2449 | { | |
2450 | ri.r_extern = 0; | |
2451 | ri.r_index = S_GET_TYPE (symbolP); | |
2452 | } | |
2453 | ||
92774660 | 2454 | /* Output the relocation information in machine-dependent form. */ |
252b5132 RH |
2455 | md_ri_to_chars (where, &ri); |
2456 | } | |
2457 | ||
2458 | #endif /* OBJ_AOUT or OBJ_BOUT */ | |
2459 | ||
252b5132 | 2460 | /* Align an address by rounding it up to the specified boundary. */ |
ea1562b3 | 2461 | |
252b5132 | 2462 | valueT |
ea1562b3 NC |
2463 | md_section_align (segT seg, |
2464 | valueT addr) /* Address to be rounded up. */ | |
252b5132 | 2465 | { |
bedf545c | 2466 | int align; |
ea1562b3 | 2467 | |
bedf545c | 2468 | align = bfd_get_section_alignment (stdoutput, seg); |
8d3842cd | 2469 | return (addr + (1 << align) - 1) & -(1 << align); |
bedf545c | 2470 | } |
252b5132 RH |
2471 | |
2472 | extern int coff_flags; | |
2473 | ||
252b5132 RH |
2474 | /* For aout or bout, the bal immediately follows the call. |
2475 | ||
2476 | For coff, we cheat and store a pointer to the bal symbol in the | |
2477 | second aux entry of the call. */ | |
2478 | ||
2479 | #undef OBJ_ABOUT | |
2480 | #ifdef OBJ_AOUT | |
2481 | #define OBJ_ABOUT | |
2482 | #endif | |
2483 | #ifdef OBJ_BOUT | |
2484 | #define OBJ_ABOUT | |
2485 | #endif | |
2486 | ||
2487 | void | |
ea1562b3 NC |
2488 | tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED, |
2489 | symbolS *balP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2490 | { |
2491 | know (TC_S_IS_CALLNAME (callP)); | |
2492 | know (TC_S_IS_BALNAME (balP)); | |
2493 | ||
2494 | #ifdef OBJ_COFF | |
2495 | ||
2496 | callP->sy_tc = balP; | |
2497 | S_SET_NUMBER_AUXILIARY (callP, 2); | |
2498 | ||
2499 | #else /* ! OBJ_COFF */ | |
2500 | #ifdef OBJ_ABOUT | |
2501 | ||
2502 | /* If the 'bal' entry doesn't immediately follow the 'call' | |
ea1562b3 | 2503 | symbol, unlink it from the symbol list and re-insert it. */ |
252b5132 RH |
2504 | if (symbol_next (callP) != balP) |
2505 | { | |
2506 | symbol_remove (balP, &symbol_rootP, &symbol_lastP); | |
2507 | symbol_append (balP, callP, &symbol_rootP, &symbol_lastP); | |
2508 | } /* if not in order */ | |
2509 | ||
2510 | #else /* ! OBJ_ABOUT */ | |
bedf545c | 2511 | as_fatal ("Only supported for a.out, b.out, or COFF"); |
252b5132 RH |
2512 | #endif /* ! OBJ_ABOUT */ |
2513 | #endif /* ! OBJ_COFF */ | |
2514 | } | |
2515 | ||
2516 | symbolS * | |
ea1562b3 | 2517 | tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED) |
252b5132 RH |
2518 | { |
2519 | symbolS *retval; | |
2520 | ||
2521 | know (TC_S_IS_CALLNAME (callP)); | |
2522 | ||
2523 | #ifdef OBJ_COFF | |
2524 | retval = callP->sy_tc; | |
2525 | #else | |
2526 | #ifdef OBJ_ABOUT | |
2527 | retval = symbol_next (callP); | |
2528 | #else | |
bedf545c | 2529 | as_fatal ("Only supported for a.out, b.out, or COFF"); |
252b5132 RH |
2530 | #endif /* ! OBJ_ABOUT */ |
2531 | #endif /* ! OBJ_COFF */ | |
2532 | ||
2533 | know (TC_S_IS_BALNAME (retval)); | |
2534 | return retval; | |
ea1562b3 | 2535 | } |
252b5132 | 2536 | |
b9195351 | 2537 | #ifdef OBJ_COFF |
252b5132 | 2538 | void |
ea1562b3 | 2539 | tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED) |
252b5132 RH |
2540 | { |
2541 | if (TC_S_IS_CALLNAME (symbolP)) | |
2542 | { | |
252b5132 RH |
2543 | symbolS *balP = tc_get_bal_of_call (symbolP); |
2544 | ||
252b5132 RH |
2545 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP); |
2546 | if (S_GET_STORAGE_CLASS (symbolP) == C_EXT) | |
2547 | S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT); | |
2548 | else | |
2549 | S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT); | |
2550 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
ea1562b3 | 2551 | /* Fix up the bal symbol. */ |
252b5132 | 2552 | S_SET_STORAGE_CLASS (balP, C_LABEL); |
ea1562b3 | 2553 | } |
252b5132 | 2554 | } |
b9195351 | 2555 | #endif /* OBJ_COFF */ |
252b5132 RH |
2556 | |
2557 | void | |
ea1562b3 | 2558 | i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED) |
252b5132 RH |
2559 | { |
2560 | if (!linkrelax) | |
2561 | return; | |
2562 | ||
2563 | #ifndef OBJ_BOUT | |
252b5132 RH |
2564 | as_bad (_("option --link-relax is only supported in b.out format")); |
2565 | linkrelax = 0; | |
2566 | return; | |
252b5132 RH |
2567 | #else |
2568 | ||
2569 | /* The text section "ends" with another alignment reloc, to which we | |
2570 | aren't adding padding. */ | |
2571 | if (fragp->fr_next == text_last_frag | |
2572 | || fragp->fr_next == data_last_frag) | |
2573 | return; | |
2574 | ||
2575 | /* alignment directive */ | |
2576 | fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, | |
2577 | (int) fragp->fr_type); | |
2578 | #endif /* OBJ_BOUT */ | |
2579 | } | |
2580 | ||
2581 | int | |
ea1562b3 | 2582 | i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED) |
252b5132 | 2583 | { |
a161fe53 | 2584 | if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy)) |
252b5132 RH |
2585 | { |
2586 | /* Relocation should be done via the associated 'bal' | |
92774660 | 2587 | entry point symbol. */ |
a161fe53 | 2588 | if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy))) |
252b5132 | 2589 | { |
a161fe53 AM |
2590 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2591 | _("No 'bal' entry point for leafproc %s"), | |
2592 | S_GET_NAME (fixP->fx_addsy)); | |
2593 | return 0; | |
252b5132 | 2594 | } |
a161fe53 | 2595 | fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy); |
252b5132 | 2596 | } |
a161fe53 AM |
2597 | |
2598 | return 1; | |
252b5132 RH |
2599 | } |
2600 | ||
bedf545c ILT |
2601 | /* From cgen.c: */ |
2602 | ||
2603 | static short | |
ea1562b3 | 2604 | tc_bfd_fix2rtype (fixS *fixP) |
bedf545c | 2605 | { |
bedf545c ILT |
2606 | if (fixP->fx_pcrel == 0 && fixP->fx_size == 4) |
2607 | return BFD_RELOC_32; | |
2608 | ||
2609 | if (fixP->fx_pcrel != 0 && fixP->fx_size == 4) | |
2610 | return BFD_RELOC_24_PCREL; | |
2611 | ||
2612 | abort (); | |
2613 | return 0; | |
2614 | } | |
2615 | ||
2616 | /* Translate internal representation of relocation info to BFD target | |
2617 | format. | |
2618 | ||
2619 | FIXME: To what extent can we get all relevant targets to use this? */ | |
2620 | ||
2621 | arelent * | |
ea1562b3 | 2622 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) |
bedf545c ILT |
2623 | { |
2624 | arelent * reloc; | |
2625 | ||
325801bd | 2626 | reloc = XNEW (arelent); |
bedf545c | 2627 | |
ea1562b3 | 2628 | /* HACK: Is this right? */ |
bedf545c ILT |
2629 | fixP->fx_r_type = tc_bfd_fix2rtype (fixP); |
2630 | ||
2631 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
ea1562b3 | 2632 | if (reloc->howto == NULL) |
bedf545c ILT |
2633 | { |
2634 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20203fb9 | 2635 | _("internal error: can't export reloc type %d (`%s')"), |
bedf545c ILT |
2636 | fixP->fx_r_type, |
2637 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
2638 | return NULL; | |
2639 | } | |
2640 | ||
9c2799c2 | 2641 | gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); |
bedf545c | 2642 | |
325801bd | 2643 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 2644 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); |
bedf545c ILT |
2645 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; |
2646 | reloc->addend = fixP->fx_addnumber; | |
2647 | ||
2648 | return reloc; | |
2649 | } | |
2650 | ||
2651 | /* end from cgen.c */ | |
2652 | ||
ea1562b3 NC |
2653 | const pseudo_typeS md_pseudo_table[] = |
2654 | { | |
2655 | {"bss", s_lcomm, 1}, | |
2656 | {"endian", s_endian, 0}, | |
2657 | {"extended", float_cons, 't'}, | |
2658 | {"leafproc", parse_po, S_LEAFPROC}, | |
2659 | {"sysproc", parse_po, S_SYSPROC}, | |
2660 | ||
2661 | {"word", cons, 4}, | |
2662 | {"quad", cons, 16}, | |
2663 | ||
2664 | {0, 0, 0} | |
2665 | }; |