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542e1629 RP |
1 | /* tc-i960.c - All the i80960-specific stuff |
2 | Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc. | |
355afbcd | 3 | |
a39116f1 | 4 | This file is part of GAS. |
355afbcd | 5 | |
a39116f1 RP |
6 | GAS is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
355afbcd | 10 | |
a39116f1 RP |
11 | GAS is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
355afbcd | 15 | |
a39116f1 RP |
16 | You should have received a copy of the GNU General Public License |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
fecd2382 | 19 | |
fecd2382 RP |
20 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
21 | ||
22 | /****************************************************************************** | |
23 | * i80690 NOTE!!!: | |
24 | * Header, symbol, and relocation info will be used on the host machine | |
25 | * only -- only executable code is actually downloaded to the i80960. | |
26 | * Therefore, leave all such information in host byte order. | |
27 | * | |
28 | * (That's a slight lie -- we DO download some header information, but | |
29 | * the downloader converts the file format and corrects the byte-ordering | |
30 | * of the relevant fields while doing so.) | |
31 | * | |
8ae35e59 ILT |
32 | * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER |
33 | * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO | |
34 | * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <== | |
35 | * | |
fecd2382 RP |
36 | ***************************************************************************** */ |
37 | ||
38 | /* There are 4 different lengths of (potentially) symbol-based displacements | |
39 | * in the 80960 instruction set, each of which could require address fix-ups | |
40 | * and (in the case of external symbols) emission of relocation directives: | |
41 | * | |
42 | * 32-bit (MEMB) | |
43 | * This is a standard length for the base assembler and requires no | |
44 | * special action. | |
45 | * | |
46 | * 13-bit (COBR) | |
47 | * This is a non-standard length, but the base assembler has a hook for | |
48 | * bit field address fixups: the fixS structure can point to a descriptor | |
49 | * of the field, in which case our md_number_to_field() routine gets called | |
50 | * to process it. | |
51 | * | |
52 | * I made the hook a little cleaner by having fix_new() (in the base | |
53 | * assembler) return a pointer to the fixS in question. And I made it a | |
54 | * little simpler by storing the field size (in this case 13) instead of | |
55 | * of a pointer to another structure: 80960 displacements are ALWAYS | |
56 | * stored in the low-order bits of a 4-byte word. | |
57 | * | |
58 | * Since the target of a COBR cannot be external, no relocation directives | |
59 | * for this size displacement have to be generated. But the base assembler | |
60 | * had to be modified to issue error messages if the symbol did turn out | |
61 | * to be external. | |
62 | * | |
63 | * 24-bit (CTRL) | |
64 | * Fixups are handled as for the 13-bit case (except that 24 is stored | |
65 | * in the fixS). | |
66 | * | |
67 | * The relocation directive generated is the same as that for the 32-bit | |
68 | * displacement, except that it's PC-relative (the 32-bit displacement | |
69 | * never is). The i80960 version of the linker needs a mod to | |
70 | * distinguish and handle the 24-bit case. | |
71 | * | |
72 | * 12-bit (MEMA) | |
73 | * MEMA formats are always promoted to MEMB (32-bit) if the displacement | |
74 | * is based on a symbol, because it could be relocated at link time. | |
75 | * The only time we use the 12-bit format is if an absolute value of | |
76 | * less than 4096 is specified, in which case we need neither a fixup nor | |
77 | * a relocation directive. | |
78 | */ | |
79 | ||
80 | #include <stdio.h> | |
81 | #include <ctype.h> | |
82 | ||
83 | #include "as.h" | |
84 | ||
85 | #include "obstack.h" | |
86 | ||
a39116f1 | 87 | #include "opcode/i960.h" |
fecd2382 RP |
88 | |
89 | extern char *input_line_pointer; | |
90 | extern struct hash_control *po_hash; | |
fecd2382 RP |
91 | extern char *next_object_file_charP; |
92 | ||
93 | #ifdef OBJ_COFF | |
c47d388b | 94 | const int md_reloc_size = sizeof (struct reloc); |
fecd2382 | 95 | #else /* OBJ_COFF */ |
c47d388b | 96 | const int md_reloc_size = sizeof (struct relocation_info); |
fecd2382 RP |
97 | #endif /* OBJ_COFF */ |
98 | ||
a39116f1 RP |
99 | /*************************** |
100 | * Local i80960 routines * | |
101 | ************************** */ | |
fecd2382 | 102 | |
355afbcd KR |
103 | static void brcnt_emit (); /* Emit branch-prediction instrumentation code */ |
104 | static char *brlab_next (); /* Return next branch local label */ | |
105 | void brtab_emit (); /* Emit br-predict instrumentation table */ | |
106 | static void cobr_fmt (); /* Generate COBR instruction */ | |
107 | static void ctrl_fmt (); /* Generate CTRL instruction */ | |
108 | static char *emit (); /* Emit (internally) binary */ | |
109 | static int get_args (); /* Break arguments out of comma-separated list */ | |
110 | static void get_cdisp (); /* Handle COBR or CTRL displacement */ | |
111 | static char *get_ispec (); /* Find index specification string */ | |
112 | static int get_regnum (); /* Translate text to register number */ | |
113 | static int i_scan (); /* Lexical scan of instruction source */ | |
114 | static void mem_fmt (); /* Generate MEMA or MEMB instruction */ | |
115 | static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */ | |
116 | static segT parse_expr (); /* Parse an expression */ | |
117 | static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */ | |
118 | static void parse_memop (); /* Parse a memory operand */ | |
119 | static void parse_po (); /* Parse machine-dependent pseudo-op */ | |
120 | static void parse_regop (); /* Parse a register operand */ | |
121 | static void reg_fmt (); /* Generate a REG format instruction */ | |
122 | void reloc_callj (); /* Relocate a 'callj' instruction */ | |
123 | static void relax_cobr (); /* "De-optimize" cobr into compare/branch */ | |
124 | static void s_leafproc (); /* Process '.leafproc' pseudo-op */ | |
125 | static void s_sysproc (); /* Process '.sysproc' pseudo-op */ | |
126 | static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */ | |
127 | static void syntax (); /* Give syntax error */ | |
128 | static int targ_has_sfr (); /* Target chip supports spec-func register? */ | |
129 | static int targ_has_iclass (); /* Target chip supports instruction set? */ | |
130 | /* static void unlink_sym(); *//* Remove a symbol from the symbol list */ | |
fecd2382 RP |
131 | |
132 | /* See md_parse_option() for meanings of these options */ | |
09952cd9 | 133 | static char norelax; /* True if -norelax switch seen */ |
355afbcd | 134 | static char instrument_branches;/* True if -b switch seen */ |
fecd2382 RP |
135 | |
136 | /* Characters that always start a comment. | |
137 | * If the pre-processor is disabled, these aren't very useful. | |
138 | */ | |
355afbcd | 139 | const char comment_chars[] = "#"; |
fecd2382 RP |
140 | |
141 | /* Characters that only start a comment at the beginning of | |
142 | * a line. If the line seems to have the form '# 123 filename' | |
143 | * .line and .file directives will appear in the pre-processed output. | |
144 | * | |
145 | * Note that input_file.c hand checks for '#' at the beginning of the | |
146 | * first line of the input file. This is because the compiler outputs | |
147 | * #NO_APP at the beginning of its output. | |
148 | */ | |
149 | ||
150 | /* Also note that comments started like this one will always work. */ | |
151 | ||
c47d388b | 152 | const char line_comment_chars[1]; |
355afbcd | 153 | |
c47d388b | 154 | const char line_separator_chars[1]; |
fecd2382 RP |
155 | |
156 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
355afbcd | 157 | const char EXP_CHARS[] = "eE"; |
fecd2382 RP |
158 | |
159 | /* Chars that mean this number is a floating point constant, | |
160 | * as in 0f12.456 or 0d1.2345e12 | |
161 | */ | |
355afbcd | 162 | const char FLT_CHARS[] = "fFdDtT"; |
fecd2382 RP |
163 | |
164 | ||
165 | /* Table used by base assembler to relax addresses based on varying length | |
166 | * instructions. The fields are: | |
167 | * 1) most positive reach of this state, | |
168 | * 2) most negative reach of this state, | |
169 | * 3) how many bytes this mode will add to the size of the current frag | |
170 | * 4) which index into the table to try if we can't fit into this one. | |
171 | * | |
172 | * For i80960, the only application is the (de-)optimization of cobr | |
173 | * instructions into separate compare and branch instructions when a 13-bit | |
174 | * displacement won't hack it. | |
175 | */ | |
176 | const relax_typeS | |
355afbcd KR |
177 | md_relax_table[] = |
178 | { | |
179 | {0, 0, 0, 0}, /* State 0 => no more relaxation possible */ | |
180 | {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */ | |
181 | {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */ | |
182 | }; | |
fecd2382 RP |
183 | |
184 | ||
185 | /* These are the machine dependent pseudo-ops. | |
186 | * | |
187 | * This table describes all the machine specific pseudo-ops the assembler | |
188 | * has to support. The fields are: | |
189 | * pseudo-op name without dot | |
190 | * function to call to execute this pseudo-op | |
191 | * integer arg to pass to the function | |
192 | */ | |
193 | #define S_LEAFPROC 1 | |
194 | #define S_SYSPROC 2 | |
195 | ||
355afbcd KR |
196 | const pseudo_typeS md_pseudo_table[] = |
197 | { | |
198 | {"bss", s_lcomm, 1}, | |
199 | {"extended", float_cons, 't'}, | |
200 | {"leafproc", parse_po, S_LEAFPROC}, | |
201 | {"sysproc", parse_po, S_SYSPROC}, | |
09952cd9 | 202 | |
355afbcd KR |
203 | {"word", cons, 4}, |
204 | {"quad", big_cons, 16}, | |
09952cd9 | 205 | |
355afbcd | 206 | {0, 0, 0} |
09952cd9 | 207 | }; |
fecd2382 RP |
208 | \f |
209 | /* Macros to extract info from an 'expressionS' structure 'e' */ | |
210 | #define adds(e) e.X_add_symbol | |
211 | #define subs(e) e.X_subtract_symbol | |
212 | #define offs(e) e.X_add_number | |
213 | #define segs(e) e.X_seg | |
355afbcd KR |
214 | |
215 | ||
216 | /* Branch-prediction bits for CTRL/COBR format opcodes */ | |
217 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */ | |
218 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */ | |
219 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */ | |
220 | ||
221 | ||
222 | /* Some instruction opcodes that we need explicitly */ | |
fecd2382 RP |
223 | #define BE 0x12000000 |
224 | #define BG 0x11000000 | |
225 | #define BGE 0x13000000 | |
226 | #define BL 0x14000000 | |
227 | #define BLE 0x16000000 | |
228 | #define BNE 0x15000000 | |
229 | #define BNO 0x10000000 | |
230 | #define BO 0x17000000 | |
231 | #define CHKBIT 0x5a002700 | |
232 | #define CMPI 0x5a002080 | |
233 | #define CMPO 0x5a002000 | |
355afbcd | 234 | |
fecd2382 RP |
235 | #define B 0x08000000 |
236 | #define BAL 0x0b000000 | |
237 | #define CALL 0x09000000 | |
238 | #define CALLS 0x66003800 | |
239 | #define RET 0x0a000000 | |
355afbcd KR |
240 | |
241 | ||
242 | /* These masks are used to build up a set of MEMB mode bits. */ | |
fecd2382 RP |
243 | #define A_BIT 0x0400 |
244 | #define I_BIT 0x0800 | |
245 | #define MEMB_BIT 0x1000 | |
246 | #define D_BIT 0x2000 | |
355afbcd KR |
247 | |
248 | ||
c47d388b ME |
249 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is |
250 | used). */ | |
fecd2382 | 251 | #define MEMA_ABASE 0x2000 |
355afbcd KR |
252 | |
253 | /* Info from which a MEMA or MEMB format instruction can be generated */ | |
254 | typedef struct | |
255 | { | |
c47d388b ME |
256 | /* (First) 32 bits of instruction */ |
257 | long opcode; | |
258 | /* 0-(none), 12- or, 32-bit displacement needed */ | |
259 | int disp; | |
260 | /* The expression in the source instruction from which the | |
261 | displacement should be determined. */ | |
262 | char *e; | |
355afbcd KR |
263 | } |
264 | ||
265 | memS; | |
fecd2382 RP |
266 | |
267 | ||
268 | /* The two pieces of info we need to generate a register operand */ | |
355afbcd KR |
269 | struct regop |
270 | { | |
271 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */ | |
272 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */ | |
273 | int n; /* Register number or literal value */ | |
274 | }; | |
fecd2382 RP |
275 | |
276 | ||
277 | /* Number and assembler mnemonic for all registers that can appear in operands */ | |
355afbcd KR |
278 | static struct |
279 | { | |
280 | char *reg_name; | |
281 | int reg_num; | |
282 | } | |
283 | ||
284 | regnames[] = | |
285 | { | |
286 | { "pfp", 0 }, | |
287 | { "sp", 1 }, | |
288 | { "rip", 2 }, | |
289 | { "r3", 3 }, | |
290 | { "r4", 4 }, | |
291 | { "r5", 5 }, | |
292 | { "r6", 6 }, | |
293 | { "r7", 7 }, | |
294 | { "r8", 8 }, | |
295 | { "r9", 9 }, | |
296 | { "r10", 10 }, | |
297 | { "r11", 11 }, | |
298 | { "r12", 12 }, | |
299 | { "r13", 13 }, | |
300 | { "r14", 14 }, | |
301 | { "r15", 15 }, | |
302 | { "g0", 16 }, | |
303 | { "g1", 17 }, | |
304 | { "g2", 18 }, | |
305 | { "g3", 19 }, | |
306 | { "g4", 20 }, | |
307 | { "g5", 21 }, | |
308 | { "g6", 22 }, | |
309 | { "g7", 23 }, | |
310 | { "g8", 24 }, | |
311 | { "g9", 25 }, | |
312 | { "g10", 26 }, | |
313 | { "g11", 27 }, | |
314 | { "g12", 28 }, | |
315 | { "g13", 29 }, | |
316 | { "g14", 30 }, | |
317 | { "fp", 31 }, | |
318 | ||
319 | /* Numbers for special-function registers are for assembler internal | |
320 | use only: they are scaled back to range [0-31] for binary output. */ | |
321 | #define SF0 32 | |
322 | ||
323 | { "sf0", 32 }, | |
324 | { "sf1", 33 }, | |
325 | { "sf2", 34 }, | |
326 | { "sf3", 35 }, | |
327 | { "sf4", 36 }, | |
328 | { "sf5", 37 }, | |
329 | { "sf6", 38 }, | |
330 | { "sf7", 39 }, | |
331 | { "sf8", 40 }, | |
332 | { "sf9", 41 }, | |
333 | { "sf10", 42 }, | |
334 | { "sf11", 43 }, | |
335 | { "sf12", 44 }, | |
336 | { "sf13", 45 }, | |
337 | { "sf14", 46 }, | |
338 | { "sf15", 47 }, | |
339 | { "sf16", 48 }, | |
340 | { "sf17", 49 }, | |
341 | { "sf18", 50 }, | |
342 | { "sf19", 51 }, | |
343 | { "sf20", 52 }, | |
344 | { "sf21", 53 }, | |
345 | { "sf22", 54 }, | |
346 | { "sf23", 55 }, | |
347 | { "sf24", 56 }, | |
348 | { "sf25", 57 }, | |
349 | { "sf26", 58 }, | |
350 | { "sf27", 59 }, | |
351 | { "sf28", 60 }, | |
352 | { "sf29", 61 }, | |
353 | { "sf30", 62 }, | |
354 | { "sf31", 63 }, | |
355 | ||
356 | /* Numbers for floating point registers are for assembler internal use | |
fecd2382 RP |
357 | * only: they are scaled back to [0-3] for binary output. |
358 | */ | |
355afbcd KR |
359 | #define FP0 64 |
360 | ||
361 | { "fp0", 64 }, | |
362 | { "fp1", 65 }, | |
363 | { "fp2", 66 }, | |
364 | { "fp3", 67 }, | |
365 | ||
366 | { NULL, 0 }, /* END OF LIST */ | |
fecd2382 RP |
367 | }; |
368 | ||
369 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) | |
370 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) | |
371 | #define IS_FP_REG(n) ((n) >= FP0) | |
372 | ||
373 | /* Number and assembler mnemonic for all registers that can appear as 'abase' | |
374 | * (indirect addressing) registers. | |
375 | */ | |
355afbcd KR |
376 | static struct |
377 | { | |
378 | char *areg_name; | |
379 | int areg_num; | |
380 | } | |
381 | ||
382 | aregs[] = | |
383 | { | |
384 | { "(pfp)", 0 }, | |
385 | { "(sp)", 1 }, | |
386 | { "(rip)", 2 }, | |
387 | { "(r3)", 3 }, | |
388 | { "(r4)", 4 }, | |
389 | { "(r5)", 5 }, | |
390 | { "(r6)", 6 }, | |
391 | { "(r7)", 7 }, | |
392 | { "(r8)", 8 }, | |
393 | { "(r9)", 9 }, | |
394 | { "(r10)", 10 }, | |
395 | { "(r11)", 11 }, | |
396 | { "(r12)", 12 }, | |
397 | { "(r13)", 13 }, | |
398 | { "(r14)", 14 }, | |
399 | { "(r15)", 15 }, | |
400 | { "(g0)", 16 }, | |
401 | { "(g1)", 17 }, | |
402 | { "(g2)", 18 }, | |
403 | { "(g3)", 19 }, | |
404 | { "(g4)", 20 }, | |
405 | { "(g5)", 21 }, | |
406 | { "(g6)", 22 }, | |
407 | { "(g7)", 23 }, | |
408 | { "(g8)", 24 }, | |
409 | { "(g9)", 25 }, | |
410 | { "(g10)", 26 }, | |
411 | { "(g11)", 27 }, | |
412 | { "(g12)", 28 }, | |
413 | { "(g13)", 29 }, | |
414 | { "(g14)", 30 }, | |
415 | { "(fp)", 31 }, | |
416 | ||
417 | #define IPREL 32 | |
418 | /* For assembler internal use only: this number never appears in binary | |
419 | output. */ | |
420 | { "(ip)", IPREL }, | |
421 | ||
422 | { NULL, 0 }, /* END OF LIST */ | |
fecd2382 RP |
423 | }; |
424 | ||
425 | ||
426 | /* Hash tables */ | |
c47d388b ME |
427 | static struct hash_control *op_hash; /* Opcode mnemonics */ |
428 | static struct hash_control *reg_hash; /* Register name hash table */ | |
429 | static struct hash_control *areg_hash; /* Abase register hash table */ | |
fecd2382 RP |
430 | |
431 | ||
432 | /* Architecture for which we are assembling */ | |
433 | #define ARCH_ANY 0 /* Default: no architecture checking done */ | |
434 | #define ARCH_KA 1 | |
435 | #define ARCH_KB 2 | |
436 | #define ARCH_MC 3 | |
437 | #define ARCH_CA 4 | |
438 | int architecture = ARCH_ANY; /* Architecture requested on invocation line */ | |
c47d388b | 439 | int iclasses_seen; /* OR of instruction classes (I_* constants) |
fecd2382 RP |
440 | * for which we've actually assembled |
441 | * instructions. | |
442 | */ | |
443 | ||
444 | ||
445 | /* BRANCH-PREDICTION INSTRUMENTATION | |
446 | * | |
447 | * The following supports generation of branch-prediction instrumentation | |
448 | * (turned on by -b switch). The instrumentation collects counts | |
449 | * of branches taken/not-taken for later input to a utility that will | |
450 | * set the branch prediction bits of the instructions in accordance with | |
451 | * the behavior observed. (Note that the KX series does not have | |
452 | * brach-prediction.) | |
453 | * | |
454 | * The instrumentation consists of: | |
455 | * | |
456 | * (1) before and after each conditional branch, a call to an external | |
457 | * routine that increments and steps over an inline counter. The | |
458 | * counter itself, initialized to 0, immediately follows the call | |
459 | * instruction. For each branch, the counter following the branch | |
460 | * is the number of times the branch was not taken, and the difference | |
461 | * between the counters is the number of times it was taken. An | |
462 | * example of an instrumented conditional branch: | |
463 | * | |
464 | * call BR_CNT_FUNC | |
465 | * .word 0 | |
466 | * LBRANCH23: be label | |
467 | * call BR_CNT_FUNC | |
468 | * .word 0 | |
469 | * | |
470 | * (2) a table of pointers to the instrumented branches, so that an | |
471 | * external postprocessing routine can locate all of the counters. | |
472 | * the table begins with a 2-word header: a pointer to the next in | |
473 | * a linked list of such tables (initialized to 0); and a count | |
474 | * of the number of entries in the table (exclusive of the header. | |
475 | * | |
476 | * Note that input source code is expected to already contain calls | |
477 | * an external routine that will link the branch local table into a | |
478 | * list of such tables. | |
479 | */ | |
480 | ||
c47d388b | 481 | static int br_cnt; /* Number of branches instrumented so far. |
fecd2382 RP |
482 | * Also used to generate unique local labels |
483 | * for each instrumented branch | |
484 | */ | |
485 | ||
486 | #define BR_LABEL_BASE "LBRANCH" | |
a39116f1 RP |
487 | /* Basename of local labels on instrumented |
488 | * branches, to avoid conflict with compiler- | |
489 | * generated local labels. | |
490 | */ | |
fecd2382 RP |
491 | |
492 | #define BR_CNT_FUNC "__inc_branch" | |
a39116f1 RP |
493 | /* Name of the external routine that will |
494 | * increment (and step over) an inline counter. | |
495 | */ | |
fecd2382 RP |
496 | |
497 | #define BR_TAB_NAME "__BRANCH_TABLE__" | |
a39116f1 RP |
498 | /* Name of the table of pointers to branches. |
499 | * A local (i.e., non-external) symbol. | |
500 | */ | |
fecd2382 RP |
501 | \f |
502 | /***************************************************************************** | |
503 | * md_begin: One-time initialization. | |
504 | * | |
505 | * Set up hash tables. | |
506 | * | |
507 | **************************************************************************** */ | |
508 | void | |
355afbcd | 509 | md_begin () |
fecd2382 | 510 | { |
355afbcd KR |
511 | int i; /* Loop counter */ |
512 | const struct i960_opcode *oP; /* Pointer into opcode table */ | |
513 | char *retval; /* Value returned by hash functions */ | |
514 | ||
515 | if (((op_hash = hash_new ()) == 0) | |
516 | || ((reg_hash = hash_new ()) == 0) | |
517 | || ((areg_hash = hash_new ()) == 0)) | |
518 | { | |
519 | as_fatal ("virtual memory exceeded"); | |
520 | } | |
521 | ||
c47d388b ME |
522 | /* For some reason, the base assembler uses an empty string for "no |
523 | error message", instead of a NULL pointer. */ | |
524 | retval = ""; | |
355afbcd KR |
525 | |
526 | for (oP = i960_opcodes; oP->name && !*retval; oP++) | |
527 | { | |
528 | retval = hash_insert (op_hash, oP->name, oP); | |
529 | } | |
530 | ||
531 | for (i = 0; regnames[i].reg_name && !*retval; i++) | |
532 | { | |
533 | retval = hash_insert (reg_hash, regnames[i].reg_name, | |
534 | ®names[i].reg_num); | |
535 | } | |
536 | ||
537 | for (i = 0; aregs[i].areg_name && !*retval; i++) | |
538 | { | |
539 | retval = hash_insert (areg_hash, aregs[i].areg_name, | |
540 | &aregs[i].areg_num); | |
541 | } | |
542 | ||
543 | if (*retval) | |
544 | { | |
545 | as_fatal ("Hashing returned \"%s\".", retval); | |
546 | } | |
547 | } /* md_begin() */ | |
fecd2382 RP |
548 | |
549 | /***************************************************************************** | |
550 | * md_end: One-time final cleanup | |
551 | * | |
552 | * None necessary | |
553 | * | |
554 | **************************************************************************** */ | |
555 | void | |
355afbcd | 556 | md_end () |
fecd2382 RP |
557 | { |
558 | } | |
559 | ||
560 | /***************************************************************************** | |
561 | * md_assemble: Assemble an instruction | |
562 | * | |
563 | * Assumptions about the passed-in text: | |
564 | * - all comments, labels removed | |
565 | * - text is an instruction | |
566 | * - all white space compressed to single blanks | |
567 | * - all character constants have been replaced with decimal | |
568 | * | |
569 | **************************************************************************** */ | |
570 | void | |
355afbcd KR |
571 | md_assemble (textP) |
572 | char *textP; /* Source text of instruction */ | |
fecd2382 | 573 | { |
c47d388b ME |
574 | /* Parsed instruction text, containing NO whitespace: |
575 | * arg[0]->opcode mnemonic | |
576 | * arg[1-3]->operands, with char constants | |
577 | * replaced by decimal numbers | |
578 | */ | |
579 | char *args[4]; | |
580 | ||
355afbcd KR |
581 | int n_ops; /* Number of instruction operands */ |
582 | int callx; | |
355afbcd | 583 | /* Pointer to instruction description */ |
c47d388b | 584 | struct i960_opcode *oP; |
355afbcd | 585 | /* TRUE iff opcode mnemonic included branch-prediction |
c47d388b ME |
586 | * suffix (".f" or ".t") |
587 | */ | |
588 | int branch_predict; | |
589 | /* Setting of branch-prediction bit(s) to be OR'd | |
590 | * into instruction opcode of CTRL/COBR format | |
591 | * instructions. | |
592 | */ | |
593 | long bp_bits; | |
594 | ||
355afbcd KR |
595 | int n; /* Offset of last character in opcode mnemonic */ |
596 | ||
597 | static const char bp_error_msg[] = "branch prediction invalid on this opcode"; | |
598 | ||
599 | ||
600 | /* Parse instruction into opcode and operands */ | |
601 | memset (args, '\0', sizeof (args)); | |
602 | n_ops = i_scan (textP, args); | |
603 | if (n_ops == -1) | |
604 | { | |
605 | return; /* Error message already issued */ | |
606 | } | |
607 | ||
608 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */ | |
609 | if (!strcmp (args[0], "ldconst")) | |
610 | { | |
611 | n_ops = parse_ldconst (args); | |
612 | if (n_ops == -1) | |
613 | { | |
614 | return; | |
fecd2382 | 615 | } |
355afbcd | 616 | } |
09952cd9 KR |
617 | |
618 | ||
355afbcd KR |
619 | |
620 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off */ | |
621 | n = strlen (args[0]) - 1; | |
622 | branch_predict = 0; | |
623 | bp_bits = 0; | |
624 | if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')) | |
625 | { | |
626 | /* We could check here to see if the target architecture | |
c47d388b ME |
627 | * supports branch prediction, but why bother? The bit |
628 | * will just be ignored by processors that don't use it. | |
629 | */ | |
355afbcd KR |
630 | branch_predict = 1; |
631 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; | |
632 | args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */ | |
633 | } | |
634 | ||
635 | /* Look up opcode mnemonic in table and check number of operands. | |
c47d388b ME |
636 | * Check that opcode is legal for the target architecture. |
637 | * If all looks good, assemble instruction. | |
638 | */ | |
355afbcd KR |
639 | oP = (struct i960_opcode *) hash_find (op_hash, args[0]); |
640 | if (!oP || !targ_has_iclass (oP->iclass)) | |
641 | { | |
642 | as_bad ("invalid opcode, \"%s\".", args[0]); | |
643 | ||
644 | } | |
645 | else if (n_ops != oP->num_ops) | |
646 | { | |
c47d388b ME |
647 | as_bad ("improper number of operands. expecting %d, got %d", |
648 | oP->num_ops, n_ops); | |
355afbcd KR |
649 | } |
650 | else | |
651 | { | |
652 | switch (oP->format) | |
653 | { | |
654 | case FBRA: | |
655 | case CTRL: | |
656 | ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops); | |
657 | if (oP->format == FBRA) | |
658 | { | |
659 | /* Now generate a 'bno' to same arg */ | |
660 | ctrl_fmt (args[1], BNO | bp_bits, 1); | |
661 | } | |
662 | break; | |
663 | case COBR: | |
664 | case COJ: | |
665 | cobr_fmt (args, oP->opcode | bp_bits, oP); | |
666 | break; | |
667 | case REG: | |
668 | if (branch_predict) | |
669 | { | |
670 | as_warn (bp_error_msg); | |
671 | } | |
672 | reg_fmt (args, oP); | |
673 | break; | |
674 | case MEM1: | |
675 | if (args[0][0] == 'c' && args[0][1] == 'a') | |
676 | { | |
677 | if (branch_predict) | |
678 | { | |
679 | as_warn (bp_error_msg); | |
680 | } | |
681 | mem_fmt (args, oP, 1); | |
682 | break; | |
683 | } | |
684 | case MEM2: | |
685 | case MEM4: | |
686 | case MEM8: | |
687 | case MEM12: | |
688 | case MEM16: | |
689 | if (branch_predict) | |
690 | { | |
691 | as_warn (bp_error_msg); | |
692 | } | |
693 | mem_fmt (args, oP, 0); | |
694 | break; | |
695 | case CALLJ: | |
696 | if (branch_predict) | |
697 | { | |
698 | as_warn (bp_error_msg); | |
699 | } | |
700 | /* Output opcode & set up "fixup" (relocation); | |
fecd2382 RP |
701 | * flag relocation as 'callj' type. |
702 | */ | |
355afbcd KR |
703 | know (oP->num_ops == 1); |
704 | get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1); | |
705 | break; | |
706 | default: | |
707 | BAD_CASE (oP->format); | |
708 | break; | |
fecd2382 | 709 | } |
355afbcd KR |
710 | } |
711 | } /* md_assemble() */ | |
fecd2382 RP |
712 | |
713 | /***************************************************************************** | |
714 | * md_number_to_chars: convert a number to target byte order | |
715 | * | |
716 | **************************************************************************** */ | |
717 | void | |
355afbcd KR |
718 | md_number_to_chars (buf, value, n) |
719 | char *buf; /* Put output here */ | |
c47d388b | 720 | valueT value; /* The integer to be converted */ |
355afbcd | 721 | int n; /* Number of bytes to output (significant bytes |
a39116f1 RP |
722 | * in 'value') |
723 | */ | |
fecd2382 | 724 | { |
355afbcd KR |
725 | while (n--) |
726 | { | |
727 | *buf++ = value; | |
728 | value >>= 8; | |
729 | } | |
730 | ||
731 | /* XXX line number probably botched for this warning message. */ | |
732 | if (value != 0 && value != -1) | |
733 | { | |
734 | as_bad ("Displacement too long for instruction field length."); | |
735 | } | |
736 | ||
737 | return; | |
738 | } /* md_number_to_chars() */ | |
fecd2382 RP |
739 | |
740 | /***************************************************************************** | |
741 | * md_chars_to_number: convert from target byte order to host byte order. | |
742 | * | |
743 | **************************************************************************** */ | |
744 | int | |
355afbcd KR |
745 | md_chars_to_number (val, n) |
746 | unsigned char *val; /* Value in target byte order */ | |
747 | int n; /* Number of bytes in the input */ | |
fecd2382 | 748 | { |
355afbcd KR |
749 | int retval; |
750 | ||
751 | for (retval = 0; n--;) | |
752 | { | |
753 | retval <<= 8; | |
754 | retval |= val[n]; | |
755 | } | |
756 | return retval; | |
fecd2382 RP |
757 | } |
758 | ||
759 | ||
760 | #define MAX_LITTLENUMS 6 | |
761 | #define LNUM_SIZE sizeof(LITTLENUM_TYPE) | |
762 | ||
763 | /***************************************************************************** | |
764 | * md_atof: convert ascii to floating point | |
765 | * | |
766 | * Turn a string at input_line_pointer into a floating point constant of type | |
767 | * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS | |
768 | * emitted is returned at 'sizeP'. An error message is returned, or a pointer | |
769 | * to an empty message if OK. | |
770 | * | |
771 | * Note we call the i386 floating point routine, rather than complicating | |
772 | * things with more files or symbolic links. | |
773 | * | |
774 | **************************************************************************** */ | |
355afbcd KR |
775 | char * |
776 | md_atof (type, litP, sizeP) | |
777 | int type; | |
778 | char *litP; | |
779 | int *sizeP; | |
fecd2382 | 780 | { |
355afbcd KR |
781 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
782 | LITTLENUM_TYPE *wordP; | |
783 | int prec; | |
784 | char *t; | |
785 | char *atof_ieee (); | |
786 | ||
787 | switch (type) | |
788 | { | |
789 | case 'f': | |
790 | case 'F': | |
791 | prec = 2; | |
792 | break; | |
793 | ||
794 | case 'd': | |
795 | case 'D': | |
796 | prec = 4; | |
797 | break; | |
798 | ||
799 | case 't': | |
800 | case 'T': | |
801 | prec = 5; | |
802 | type = 'x'; /* That's what atof_ieee() understands */ | |
803 | break; | |
804 | ||
805 | default: | |
806 | *sizeP = 0; | |
807 | return "Bad call to md_atof()"; | |
808 | } | |
809 | ||
810 | t = atof_ieee (input_line_pointer, type, words); | |
811 | if (t) | |
812 | { | |
813 | input_line_pointer = t; | |
814 | } | |
815 | ||
816 | *sizeP = prec * LNUM_SIZE; | |
817 | ||
818 | /* Output the LITTLENUMs in REVERSE order in accord with i80960 | |
fecd2382 RP |
819 | * word-order. (Dunno why atof_ieee doesn't do it in the right |
820 | * order in the first place -- probably because it's a hack of | |
821 | * atof_m68k.) | |
822 | */ | |
355afbcd KR |
823 | |
824 | for (wordP = words + prec - 1; prec--;) | |
825 | { | |
826 | md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE); | |
827 | litP += sizeof (LITTLENUM_TYPE); | |
828 | } | |
829 | ||
830 | return ""; /* Someone should teach Dean about null pointers */ | |
fecd2382 RP |
831 | } |
832 | ||
833 | ||
834 | /***************************************************************************** | |
835 | * md_number_to_imm | |
836 | * | |
837 | **************************************************************************** */ | |
838 | void | |
355afbcd KR |
839 | md_number_to_imm (buf, val, n) |
840 | char *buf; | |
841 | long val; | |
842 | int n; | |
fecd2382 | 843 | { |
355afbcd | 844 | md_number_to_chars (buf, val, n); |
fecd2382 RP |
845 | } |
846 | ||
847 | ||
848 | /***************************************************************************** | |
849 | * md_number_to_disp | |
850 | * | |
851 | **************************************************************************** */ | |
852 | void | |
355afbcd KR |
853 | md_number_to_disp (buf, val, n) |
854 | char *buf; | |
855 | long val; | |
856 | int n; | |
fecd2382 | 857 | { |
355afbcd | 858 | md_number_to_chars (buf, val, n); |
fecd2382 RP |
859 | } |
860 | ||
861 | /***************************************************************************** | |
862 | * md_number_to_field: | |
863 | * | |
864 | * Stick a value (an address fixup) into a bit field of | |
865 | * previously-generated instruction. | |
866 | * | |
867 | **************************************************************************** */ | |
868 | void | |
355afbcd KR |
869 | md_number_to_field (instrP, val, bfixP) |
870 | char *instrP; /* Pointer to instruction to be fixed */ | |
871 | long val; /* Address fixup value */ | |
872 | bit_fixS *bfixP; /* Description of bit field to be fixed up */ | |
fecd2382 | 873 | { |
355afbcd KR |
874 | int numbits; /* Length of bit field to be fixed */ |
875 | long instr; /* 32-bit instruction to be fixed-up */ | |
876 | long sign; /* 0 or -1, according to sign bit of 'val' */ | |
877 | ||
878 | /* Convert instruction back to host byte order | |
fecd2382 | 879 | */ |
355afbcd KR |
880 | instr = md_chars_to_number (instrP, 4); |
881 | ||
882 | /* Surprise! -- we stored the number of bits | |
fecd2382 RP |
883 | * to be modified rather than a pointer to a structure. |
884 | */ | |
355afbcd KR |
885 | numbits = (int) bfixP; |
886 | if (numbits == 1) | |
887 | { | |
888 | /* This is a no-op, stuck here by reloc_callj() */ | |
889 | return; | |
890 | } | |
891 | ||
892 | know ((numbits == 13) || (numbits == 24)); | |
893 | ||
894 | /* Propagate sign bit of 'val' for the given number of bits. | |
fecd2382 RP |
895 | * Result should be all 0 or all 1 |
896 | */ | |
355afbcd KR |
897 | sign = val >> ((int) numbits - 1); |
898 | if (((val < 0) && (sign != -1)) | |
899 | || ((val > 0) && (sign != 0))) | |
900 | { | |
901 | as_bad ("Fixup of %d too large for field width of %d", | |
902 | val, numbits); | |
903 | } | |
904 | else | |
905 | { | |
906 | /* Put bit field into instruction and write back in target | |
fecd2382 RP |
907 | * byte order. |
908 | */ | |
355afbcd KR |
909 | val &= ~(-1 << (int) numbits); /* Clear unused sign bits */ |
910 | instr |= val; | |
911 | md_number_to_chars (instrP, instr, 4); | |
912 | } | |
913 | } /* md_number_to_field() */ | |
fecd2382 RP |
914 | |
915 | ||
916 | /***************************************************************************** | |
917 | * md_parse_option | |
918 | * Invocation line includes a switch not recognized by the base assembler. | |
919 | * See if it's a processor-specific option. For the 960, these are: | |
920 | * | |
921 | * -norelax: | |
922 | * Conditional branch instructions that require displacements | |
923 | * greater than 13 bits (or that have external targets) should | |
924 | * generate errors. The default is to replace each such | |
925 | * instruction with the corresponding compare (or chkbit) and | |
926 | * branch instructions. Note that the Intel "j" cobr directives | |
927 | * are ALWAYS "de-optimized" in this way when necessary, | |
928 | * regardless of the setting of this option. | |
929 | * | |
930 | * -b: | |
931 | * Add code to collect information about branches taken, for | |
932 | * later optimization of branch prediction bits by a separate | |
933 | * tool. COBR and CNTL format instructions have branch | |
934 | * prediction bits (in the CX architecture); if "BR" represents | |
935 | * an instruction in one of these classes, the following rep- | |
936 | * resents the code generated by the assembler: | |
937 | * | |
938 | * call <increment routine> | |
939 | * .word 0 # pre-counter | |
940 | * Label: BR | |
941 | * call <increment routine> | |
942 | * .word 0 # post-counter | |
943 | * | |
944 | * A table of all such "Labels" is also generated. | |
945 | * | |
946 | * | |
947 | * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: | |
948 | * Select the 80960 architecture. Instructions or features not | |
949 | * supported by the selected architecture cause fatal errors. | |
950 | * The default is to generate code for any instruction or feature | |
951 | * that is supported by SOME version of the 960 (even if this | |
952 | * means mixing architectures!). | |
953 | * | |
954 | **************************************************************************** */ | |
955 | int | |
355afbcd KR |
956 | md_parse_option (argP, cntP, vecP) |
957 | char **argP; | |
958 | int *cntP; | |
959 | char ***vecP; | |
fecd2382 | 960 | { |
355afbcd KR |
961 | char *p; |
962 | struct tabentry | |
963 | { | |
964 | char *flag; | |
965 | int arch; | |
966 | }; | |
967 | static struct tabentry arch_tab[] = | |
968 | { | |
969 | "KA", ARCH_KA, | |
970 | "KB", ARCH_KB, | |
971 | "SA", ARCH_KA, /* Synonym for KA */ | |
972 | "SB", ARCH_KB, /* Synonym for KB */ | |
973 | "KC", ARCH_MC, /* Synonym for MC */ | |
974 | "MC", ARCH_MC, | |
975 | "CA", ARCH_CA, | |
976 | NULL, 0 | |
977 | }; | |
978 | struct tabentry *tp; | |
979 | if (!strcmp (*argP, "linkrelax")) | |
980 | { | |
981 | linkrelax = 1; | |
982 | flagseen['L'] = 1; | |
983 | } | |
984 | else if (!strcmp (*argP, "norelax")) | |
985 | { | |
986 | norelax = 1; | |
987 | ||
988 | } | |
989 | else if (**argP == 'b') | |
990 | { | |
991 | instrument_branches = 1; | |
992 | ||
993 | } | |
994 | else if (**argP == 'A') | |
995 | { | |
996 | p = (*argP) + 1; | |
997 | ||
998 | for (tp = arch_tab; tp->flag != NULL; tp++) | |
999 | { | |
1000 | if (!strcmp (p, tp->flag)) | |
1001 | { | |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | if (tp->flag == NULL) | |
1007 | { | |
1008 | as_bad ("unknown architecture: %s", p); | |
fecd2382 | 1009 | } |
355afbcd KR |
1010 | else |
1011 | { | |
1012 | architecture = tp->arch; | |
1013 | } | |
1014 | } | |
1015 | else | |
1016 | { | |
1017 | /* Unknown option */ | |
1018 | (*argP)++; | |
1019 | return 0; | |
1020 | } | |
1021 | **argP = '\0'; /* Done parsing this switch */ | |
1022 | return 1; | |
fecd2382 RP |
1023 | } |
1024 | ||
1025 | /***************************************************************************** | |
1026 | * md_convert_frag: | |
1027 | * Called by base assembler after address relaxation is finished: modify | |
1028 | * variable fragments according to how much relaxation was done. | |
1029 | * | |
1030 | * If the fragment substate is still 1, a 13-bit displacement was enough | |
1031 | * to reach the symbol in question. Set up an address fixup, but otherwise | |
1032 | * leave the cobr instruction alone. | |
1033 | * | |
1034 | * If the fragment substate is 2, a 13-bit displacement was not enough. | |
1035 | * Replace the cobr with a two instructions (a compare and a branch). | |
1036 | * | |
1037 | **************************************************************************** */ | |
1038 | void | |
355afbcd KR |
1039 | md_convert_frag (headers, fragP) |
1040 | object_headers *headers; | |
1041 | fragS *fragP; | |
fecd2382 | 1042 | { |
355afbcd KR |
1043 | fixS *fixP; /* Structure describing needed address fix */ |
1044 | ||
1045 | switch (fragP->fr_subtype) | |
1046 | { | |
1047 | case 1: | |
1048 | /* LEAVE SINGLE COBR INSTRUCTION */ | |
1049 | fixP = fix_new (fragP, | |
1050 | fragP->fr_opcode - fragP->fr_literal, | |
1051 | 4, | |
1052 | fragP->fr_symbol, | |
1053 | 0, | |
1054 | fragP->fr_offset, | |
1055 | 1, | |
1056 | NO_RELOC); | |
1057 | ||
1058 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */ | |
1059 | break; | |
1060 | case 2: | |
1061 | /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */ | |
1062 | relax_cobr (fragP); | |
1063 | break; | |
1064 | default: | |
1065 | BAD_CASE (fragP->fr_subtype); | |
1066 | break; | |
1067 | } | |
fecd2382 RP |
1068 | } |
1069 | ||
1070 | /***************************************************************************** | |
1071 | * md_estimate_size_before_relax: How much does it look like *fragP will grow? | |
1072 | * | |
1073 | * Called by base assembler just before address relaxation. | |
1074 | * Return the amount by which the fragment will grow. | |
1075 | * | |
1076 | * Any symbol that is now undefined will not become defined; cobr's | |
1077 | * based on undefined symbols will have to be replaced with a compare | |
1078 | * instruction and a branch instruction, and the code fragment will grow | |
1079 | * by 4 bytes. | |
1080 | * | |
1081 | **************************************************************************** */ | |
1082 | int | |
355afbcd KR |
1083 | md_estimate_size_before_relax (fragP, segment_type) |
1084 | register fragS *fragP; | |
1085 | register segT segment_type; | |
fecd2382 | 1086 | { |
355afbcd | 1087 | /* If symbol is undefined in this segment, go to "relaxed" state |
fecd2382 RP |
1088 | * (compare and branch instructions instead of cobr) right now. |
1089 | */ | |
355afbcd KR |
1090 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type) |
1091 | { | |
1092 | relax_cobr (fragP); | |
1093 | return 4; | |
1094 | } | |
1095 | return 0; | |
1096 | } /* md_estimate_size_before_relax() */ | |
fecd2382 RP |
1097 | |
1098 | ||
1099 | /***************************************************************************** | |
1100 | * md_ri_to_chars: | |
1101 | * This routine exists in order to overcome machine byte-order problems | |
1102 | * when dealing with bit-field entries in the relocation_info struct. | |
1103 | * | |
1104 | * But relocation info will be used on the host machine only (only | |
1105 | * executable code is actually downloaded to the i80960). Therefore, | |
1106 | * we leave it in host byte order. | |
1107 | * | |
8ae35e59 ILT |
1108 | * The above comment is no longer true. This routine now really |
1109 | * does do the reordering (Ian Taylor 28 Aug 92). | |
1110 | * | |
fecd2382 | 1111 | **************************************************************************** */ |
355afbcd KR |
1112 | void |
1113 | md_ri_to_chars (where, ri) | |
1114 | char *where; | |
1115 | struct relocation_info *ri; | |
fecd2382 | 1116 | { |
355afbcd KR |
1117 | md_number_to_chars (where, ri->r_address, |
1118 | sizeof (ri->r_address)); | |
1119 | where[4] = ri->r_index & 0x0ff; | |
1120 | where[5] = (ri->r_index >> 8) & 0x0ff; | |
1121 | where[6] = (ri->r_index >> 16) & 0x0ff; | |
1122 | where[7] = ((ri->r_pcrel << 0) | |
1123 | | (ri->r_length << 1) | |
1124 | | (ri->r_extern << 3) | |
1125 | | (ri->r_bsr << 4) | |
1126 | | (ri->r_disp << 5) | |
1127 | | (ri->r_callj << 6)); | |
1128 | } /* md_ri_to_chars() */ | |
fecd2382 | 1129 | |
fecd2382 RP |
1130 | #ifndef WORKING_DOT_WORD |
1131 | ||
1132 | int md_short_jump_size = 0; | |
1133 | int md_long_jump_size = 0; | |
1134 | ||
355afbcd KR |
1135 | void |
1136 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
1137 | char *ptr; | |
c47d388b ME |
1138 | addressT from_addr; |
1139 | addressT to_addr; | |
355afbcd KR |
1140 | fragS *frag; |
1141 | symbolS *to_symbol; | |
fecd2382 | 1142 | { |
355afbcd | 1143 | as_fatal ("failed sanity check."); |
fecd2382 RP |
1144 | } |
1145 | ||
1146 | void | |
355afbcd KR |
1147 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
1148 | char *ptr; | |
c47d388b | 1149 | addressT from_addr, to_addr; |
355afbcd KR |
1150 | fragS *frag; |
1151 | symbolS *to_symbol; | |
fecd2382 | 1152 | { |
355afbcd | 1153 | as_fatal ("failed sanity check."); |
fecd2382 | 1154 | } |
355afbcd | 1155 | |
fecd2382 RP |
1156 | #endif |
1157 | \f | |
a39116f1 RP |
1158 | /************************************************************* |
1159 | * * | |
1160 | * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER * | |
1161 | * * | |
1162 | ************************************************************ */ | |
fecd2382 RP |
1163 | |
1164 | ||
1165 | ||
1166 | /***************************************************************************** | |
1167 | * brcnt_emit: Emit code to increment inline branch counter. | |
1168 | * | |
1169 | * See the comments above the declaration of 'br_cnt' for details on | |
1170 | * branch-prediction instrumentation. | |
1171 | **************************************************************************** */ | |
1172 | static void | |
355afbcd | 1173 | brcnt_emit () |
fecd2382 | 1174 | { |
355afbcd KR |
1175 | ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */ |
1176 | emit (0); /* Emit inline counter to be incremented */ | |
fecd2382 RP |
1177 | } |
1178 | ||
1179 | /***************************************************************************** | |
1180 | * brlab_next: generate the next branch local label | |
1181 | * | |
1182 | * See the comments above the declaration of 'br_cnt' for details on | |
1183 | * branch-prediction instrumentation. | |
1184 | **************************************************************************** */ | |
1185 | static char * | |
355afbcd | 1186 | brlab_next () |
fecd2382 | 1187 | { |
355afbcd KR |
1188 | static char buf[20]; |
1189 | ||
1190 | sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++); | |
1191 | return buf; | |
fecd2382 RP |
1192 | } |
1193 | ||
1194 | /***************************************************************************** | |
1195 | * brtab_emit: generate the fetch-prediction branch table. | |
1196 | * | |
1197 | * See the comments above the declaration of 'br_cnt' for details on | |
1198 | * branch-prediction instrumentation. | |
1199 | * | |
1200 | * The code emitted here would be functionally equivalent to the following | |
1201 | * example assembler source. | |
1202 | * | |
1203 | * .data | |
1204 | * .align 2 | |
1205 | * BR_TAB_NAME: | |
1206 | * .word 0 # link to next table | |
1207 | * .word 3 # length of table | |
1208 | * .word LBRANCH0 # 1st entry in table proper | |
1209 | * .word LBRANCH1 | |
1210 | * .word LBRANCH2 | |
1211 | ***************************************************************************** */ | |
1212 | void | |
355afbcd | 1213 | brtab_emit () |
fecd2382 | 1214 | { |
355afbcd KR |
1215 | int i; |
1216 | char buf[20]; | |
1217 | char *p; /* Where the binary was output to */ | |
1218 | fixS *fixP; /*->description of deferred address fixup */ | |
1219 | ||
1220 | if (!instrument_branches) | |
1221 | { | |
1222 | return; | |
1223 | } | |
1224 | ||
1225 | subseg_new (SEG_DATA, 0); /* .data */ | |
1226 | frag_align (2, 0); /* .align 2 */ | |
1227 | record_alignment (now_seg, 2); | |
1228 | colon (BR_TAB_NAME); /* BR_TAB_NAME: */ | |
1229 | emit (0); /* .word 0 #link to next table */ | |
1230 | emit (br_cnt); /* .word n #length of table */ | |
1231 | ||
1232 | for (i = 0; i < br_cnt; i++) | |
1233 | { | |
1234 | sprintf (buf, "%s%d", BR_LABEL_BASE, i); | |
1235 | p = emit (0); | |
1236 | fixP = fix_new (frag_now, | |
1237 | p - frag_now->fr_literal, | |
1238 | 4, | |
1239 | symbol_find (buf), | |
1240 | 0, | |
1241 | 0, | |
1242 | 0, | |
1243 | NO_RELOC); | |
1244 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ | |
1245 | } | |
fecd2382 RP |
1246 | } |
1247 | ||
1248 | /***************************************************************************** | |
1249 | * cobr_fmt: generate a COBR-format instruction | |
1250 | * | |
1251 | **************************************************************************** */ | |
1252 | static | |
355afbcd KR |
1253 | void |
1254 | cobr_fmt (arg, opcode, oP) | |
1255 | char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ | |
1256 | long opcode; /* Opcode, with branch-prediction bits already set | |
a39116f1 RP |
1257 | * if necessary. |
1258 | */ | |
355afbcd KR |
1259 | struct i960_opcode *oP; |
1260 | /*->description of instruction */ | |
fecd2382 | 1261 | { |
355afbcd KR |
1262 | long instr; /* 32-bit instruction */ |
1263 | struct regop regop; /* Description of register operand */ | |
1264 | int n; /* Number of operands */ | |
1265 | int var_frag; /* 1 if varying length code fragment should | |
fecd2382 RP |
1266 | * be emitted; 0 if an address fix |
1267 | * should be emitted. | |
1268 | */ | |
355afbcd KR |
1269 | |
1270 | instr = opcode; | |
1271 | n = oP->num_ops; | |
1272 | ||
1273 | if (n >= 1) | |
1274 | { | |
1275 | /* First operand (if any) of a COBR is always a register | |
fecd2382 RP |
1276 | * operand. Parse it. |
1277 | */ | |
355afbcd KR |
1278 | parse_regop (®op, arg[1], oP->operand[0]); |
1279 | instr |= (regop.n << 19) | (regop.mode << 13); | |
1280 | } | |
1281 | if (n >= 2) | |
1282 | { | |
1283 | /* Second operand (if any) of a COBR is always a register | |
fecd2382 RP |
1284 | * operand. Parse it. |
1285 | */ | |
355afbcd KR |
1286 | parse_regop (®op, arg[2], oP->operand[1]); |
1287 | instr |= (regop.n << 14) | regop.special; | |
1288 | } | |
1289 | ||
1290 | ||
1291 | if (n < 3) | |
1292 | { | |
1293 | emit (instr); | |
1294 | ||
1295 | } | |
1296 | else | |
1297 | { | |
1298 | if (instrument_branches) | |
1299 | { | |
1300 | brcnt_emit (); | |
1301 | colon (brlab_next ()); | |
fecd2382 | 1302 | } |
355afbcd KR |
1303 | |
1304 | /* A third operand to a COBR is always a displacement. | |
fecd2382 RP |
1305 | * Parse it; if it's relaxable (a cobr "j" directive, or any |
1306 | * cobr other than bbs/bbc when the "-norelax" option is not in | |
1307 | * use) set up a variable code fragment; otherwise set up an | |
1308 | * address fix. | |
1309 | */ | |
355afbcd KR |
1310 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ |
1311 | get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0); | |
1312 | ||
1313 | if (instrument_branches) | |
1314 | { | |
1315 | brcnt_emit (); | |
fecd2382 | 1316 | } |
355afbcd KR |
1317 | } |
1318 | } /* cobr_fmt() */ | |
fecd2382 RP |
1319 | |
1320 | ||
1321 | /***************************************************************************** | |
1322 | * ctrl_fmt: generate a CTRL-format instruction | |
1323 | * | |
1324 | **************************************************************************** */ | |
1325 | static | |
355afbcd KR |
1326 | void |
1327 | ctrl_fmt (targP, opcode, num_ops) | |
1328 | char *targP; /* Pointer to text of lone operand (if any) */ | |
1329 | long opcode; /* Template of instruction */ | |
1330 | int num_ops; /* Number of operands */ | |
fecd2382 | 1331 | { |
355afbcd | 1332 | int instrument; /* TRUE iff we should add instrumentation to track |
fecd2382 RP |
1333 | * how often the branch is taken |
1334 | */ | |
355afbcd KR |
1335 | |
1336 | ||
1337 | if (num_ops == 0) | |
1338 | { | |
1339 | emit (opcode); /* Output opcode */ | |
1340 | } | |
1341 | else | |
1342 | { | |
1343 | ||
1344 | instrument = instrument_branches && (opcode != CALL) | |
1345 | && (opcode != B) && (opcode != RET) && (opcode != BAL); | |
1346 | ||
1347 | if (instrument) | |
1348 | { | |
1349 | brcnt_emit (); | |
1350 | colon (brlab_next ()); | |
1351 | } | |
1352 | ||
1353 | /* The operand MUST be an ip-relative displacment. Parse it | |
fecd2382 RP |
1354 | * and set up address fix for the instruction we just output. |
1355 | */ | |
355afbcd KR |
1356 | get_cdisp (targP, "CTRL", opcode, 24, 0, 0); |
1357 | ||
1358 | if (instrument) | |
1359 | { | |
1360 | brcnt_emit (); | |
fecd2382 | 1361 | } |
355afbcd KR |
1362 | } |
1363 | ||
fecd2382 RP |
1364 | } |
1365 | ||
1366 | ||
1367 | /***************************************************************************** | |
1368 | * emit: output instruction binary | |
1369 | * | |
1370 | * Output instruction binary, in target byte order, 4 bytes at a time. | |
1371 | * Return pointer to where it was placed. | |
1372 | * | |
1373 | **************************************************************************** */ | |
1374 | static | |
355afbcd KR |
1375 | char * |
1376 | emit (instr) | |
1377 | long instr; /* Word to be output, host byte order */ | |
fecd2382 | 1378 | { |
355afbcd KR |
1379 | char *toP; /* Where to output it */ |
1380 | ||
1381 | toP = frag_more (4); /* Allocate storage */ | |
1382 | md_number_to_chars (toP, instr, 4); /* Convert to target byte order */ | |
1383 | return toP; | |
fecd2382 RP |
1384 | } |
1385 | ||
1386 | ||
1387 | /***************************************************************************** | |
1388 | * get_args: break individual arguments out of comma-separated list | |
1389 | * | |
1390 | * Input assumptions: | |
1391 | * - all comments and labels have been removed | |
1392 | * - all strings of whitespace have been collapsed to a single blank. | |
1393 | * - all character constants ('x') have been replaced with decimal | |
1394 | * | |
1395 | * Output: | |
1396 | * args[0] is untouched. args[1] points to first operand, etc. All args: | |
1397 | * - are NULL-terminated | |
1398 | * - contain no whitespace | |
1399 | * | |
1400 | * Return value: | |
1401 | * Number of operands (0,1,2, or 3) or -1 on error. | |
1402 | * | |
1403 | **************************************************************************** */ | |
355afbcd KR |
1404 | static int |
1405 | get_args (p, args) | |
1406 | register char *p; /* Pointer to comma-separated operands; MUCKED BY US */ | |
1407 | char *args[]; /* Output arg: pointers to operands placed in args[1-3]. | |
a39116f1 RP |
1408 | * MUST ACCOMMODATE 4 ENTRIES (args[0-3]). |
1409 | */ | |
fecd2382 | 1410 | { |
355afbcd KR |
1411 | register int n; /* Number of operands */ |
1412 | register char *to; | |
1413 | /* char buf[4]; */ | |
1414 | /* int len; */ | |
1415 | ||
1416 | ||
1417 | /* Skip lead white space */ | |
1418 | while (*p == ' ') | |
1419 | { | |
1420 | p++; | |
1421 | } | |
1422 | ||
1423 | if (*p == '\0') | |
1424 | { | |
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | n = 1; | |
1429 | args[1] = p; | |
1430 | ||
1431 | /* Squeze blanks out by moving non-blanks toward start of string. | |
fecd2382 RP |
1432 | * Isolate operands, whenever comma is found. |
1433 | */ | |
355afbcd KR |
1434 | to = p; |
1435 | while (*p != '\0') | |
1436 | { | |
1437 | ||
1438 | if (*p == ' ') | |
1439 | { | |
1440 | p++; | |
1441 | ||
1442 | } | |
1443 | else if (*p == ',') | |
1444 | { | |
1445 | ||
1446 | /* Start of operand */ | |
1447 | if (n == 3) | |
1448 | { | |
1449 | as_bad ("too many operands"); | |
1450 | return -1; | |
1451 | } | |
1452 | *to++ = '\0'; /* Terminate argument */ | |
1453 | args[++n] = to; /* Start next argument */ | |
1454 | p++; | |
1455 | ||
fecd2382 | 1456 | } |
355afbcd KR |
1457 | else |
1458 | { | |
1459 | *to++ = *p++; | |
1460 | } | |
1461 | } | |
1462 | *to = '\0'; | |
1463 | return n; | |
fecd2382 RP |
1464 | } |
1465 | ||
1466 | ||
1467 | /***************************************************************************** | |
1468 | * get_cdisp: handle displacement for a COBR or CTRL instruction. | |
1469 | * | |
1470 | * Parse displacement for a COBR or CTRL instruction. | |
1471 | * | |
1472 | * If successful, output the instruction opcode and set up for it, | |
1473 | * depending on the arg 'var_frag', either: | |
1474 | * o an address fixup to be done when all symbol values are known, or | |
1475 | * o a varying length code fragment, with address fixup info. This | |
1476 | * will be done for cobr instructions that may have to be relaxed | |
c47d388b ME |
1477 | * in to compare/branch instructions (8 bytes) if the final |
1478 | * address displacement is greater than 13 bits. | |
fecd2382 | 1479 | * |
c47d388b | 1480 | *****************************************************************************/ |
fecd2382 | 1481 | static |
355afbcd KR |
1482 | void |
1483 | get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj) | |
c47d388b ME |
1484 | /* displacement as specified in source instruction */ |
1485 | char *dispP; | |
1486 | /* "COBR" or "CTRL" (for use in error message) */ | |
1487 | char *ifmtP; | |
1488 | /* Instruction needing the displacement */ | |
1489 | long instr; | |
1490 | /* # bits of displacement (13 for COBR, 24 for CTRL) */ | |
1491 | int numbits; | |
1492 | /* 1 if varying length code fragment should be emitted; | |
1493 | * 0 if an address fix should be emitted. | |
1494 | */ | |
1495 | int var_frag; | |
1496 | /* 1 if callj relocation should be done; else 0 */ | |
1497 | int callj; | |
fecd2382 | 1498 | { |
355afbcd KR |
1499 | expressionS e; /* Parsed expression */ |
1500 | fixS *fixP; /* Structure describing needed address fix */ | |
1501 | char *outP; /* Where instruction binary is output to */ | |
1502 | ||
1503 | fixP = NULL; | |
1504 | ||
1505 | switch (parse_expr (dispP, &e)) | |
1506 | { | |
1507 | ||
1508 | case SEG_GOOF: | |
1509 | as_bad ("expression syntax error"); | |
1510 | break; | |
1511 | ||
1512 | case SEG_TEXT: | |
1513 | case SEG_UNKNOWN: | |
1514 | if (var_frag) | |
1515 | { | |
1516 | outP = frag_more (8); /* Allocate worst-case storage */ | |
1517 | md_number_to_chars (outP, instr, 4); | |
1518 | frag_variant (rs_machine_dependent, 4, 4, 1, | |
1519 | adds (e), offs (e), outP, 0, 0); | |
1520 | } | |
1521 | else | |
1522 | { | |
1523 | /* Set up a new fix structure, so address can be updated | |
c47d388b ME |
1524 | * when all symbol values are known. |
1525 | */ | |
355afbcd KR |
1526 | outP = emit (instr); |
1527 | fixP = fix_new (frag_now, | |
1528 | outP - frag_now->fr_literal, | |
1529 | 4, | |
1530 | adds (e), | |
1531 | 0, | |
1532 | offs (e), | |
1533 | 1, | |
1534 | NO_RELOC); | |
1535 | ||
1536 | fixP->fx_callj = callj; | |
1537 | ||
1538 | /* We want to modify a bit field when the address is | |
c47d388b ME |
1539 | * known. But we don't need all the garbage in the |
1540 | * bit_fix structure. So we're going to lie and store | |
1541 | * the number of bits affected instead of a pointer. | |
1542 | */ | |
355afbcd | 1543 | fixP->fx_bit_fixP = (bit_fixS *) numbits; |
fecd2382 | 1544 | } |
355afbcd KR |
1545 | break; |
1546 | ||
1547 | case SEG_DATA: | |
1548 | case SEG_BSS: | |
1549 | as_bad ("attempt to branch into different segment"); | |
1550 | break; | |
1551 | ||
1552 | default: | |
1553 | as_bad ("target of %s instruction must be a label", ifmtP); | |
1554 | break; | |
1555 | } | |
fecd2382 RP |
1556 | } |
1557 | ||
1558 | ||
1559 | /***************************************************************************** | |
1560 | * get_ispec: parse a memory operand for an index specification | |
1561 | * | |
1562 | * Here, an "index specification" is taken to be anything surrounded | |
1563 | * by square brackets and NOT followed by anything else. | |
1564 | * | |
1565 | * If it's found, detach it from the input string, remove the surrounding | |
1566 | * square brackets, and return a pointer to it. Otherwise, return NULL. | |
1567 | * | |
1568 | **************************************************************************** */ | |
1569 | static | |
355afbcd KR |
1570 | char * |
1571 | get_ispec (textP) | |
1572 | char *textP; /*->memory operand from source instruction, no white space */ | |
fecd2382 | 1573 | { |
355afbcd KR |
1574 | char *start; /*->start of index specification */ |
1575 | char *end; /*->end of index specification */ | |
1576 | ||
1577 | /* Find opening square bracket, if any | |
fecd2382 | 1578 | */ |
355afbcd KR |
1579 | start = strchr (textP, '['); |
1580 | ||
1581 | if (start != NULL) | |
1582 | { | |
1583 | ||
1584 | /* Eliminate '[', detach from rest of operand */ | |
1585 | *start++ = '\0'; | |
1586 | ||
1587 | end = strchr (start, ']'); | |
1588 | ||
1589 | if (end == NULL) | |
1590 | { | |
1591 | as_bad ("unmatched '['"); | |
1592 | ||
1593 | } | |
1594 | else | |
1595 | { | |
1596 | /* Eliminate ']' and make sure it was the last thing | |
fecd2382 RP |
1597 | * in the string. |
1598 | */ | |
355afbcd KR |
1599 | *end = '\0'; |
1600 | if (*(end + 1) != '\0') | |
1601 | { | |
1602 | as_bad ("garbage after index spec ignored"); | |
1603 | } | |
fecd2382 | 1604 | } |
355afbcd KR |
1605 | } |
1606 | return start; | |
fecd2382 RP |
1607 | } |
1608 | ||
1609 | /***************************************************************************** | |
1610 | * get_regnum: | |
1611 | * | |
1612 | * Look up a (suspected) register name in the register table and return the | |
1613 | * associated register number (or -1 if not found). | |
1614 | * | |
1615 | **************************************************************************** */ | |
1616 | static | |
355afbcd KR |
1617 | int |
1618 | get_regnum (regname) | |
1619 | char *regname; /* Suspected register name */ | |
fecd2382 | 1620 | { |
355afbcd KR |
1621 | int *rP; |
1622 | ||
1623 | rP = (int *) hash_find (reg_hash, regname); | |
1624 | return (rP == NULL) ? -1 : *rP; | |
fecd2382 RP |
1625 | } |
1626 | ||
1627 | ||
1628 | /***************************************************************************** | |
1629 | * i_scan: perform lexical scan of ascii assembler instruction. | |
1630 | * | |
1631 | * Input assumptions: | |
1632 | * - input string is an i80960 instruction (not a pseudo-op) | |
1633 | * - all comments and labels have been removed | |
1634 | * - all strings of whitespace have been collapsed to a single blank. | |
1635 | * | |
1636 | * Output: | |
1637 | * args[0] points to opcode, other entries point to operands. All strings: | |
1638 | * - are NULL-terminated | |
1639 | * - contain no whitespace | |
1640 | * - have character constants ('x') replaced with a decimal number | |
1641 | * | |
1642 | * Return value: | |
1643 | * Number of operands (0,1,2, or 3) or -1 on error. | |
1644 | * | |
1645 | **************************************************************************** */ | |
355afbcd KR |
1646 | static int |
1647 | i_scan (iP, args) | |
1648 | register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */ | |
1649 | char *args[]; /* Output arg: pointers to opcode and operands placed | |
a39116f1 RP |
1650 | * here. MUST ACCOMMODATE 4 ENTRIES. |
1651 | */ | |
fecd2382 | 1652 | { |
355afbcd KR |
1653 | |
1654 | /* Isolate opcode */ | |
1655 | if (*(iP) == ' ') | |
1656 | { | |
1657 | iP++; | |
1658 | } /* Skip lead space, if any */ | |
1659 | args[0] = iP; | |
1660 | for (; *iP != ' '; iP++) | |
1661 | { | |
1662 | if (*iP == '\0') | |
1663 | { | |
1664 | /* There are no operands */ | |
1665 | if (args[0] == iP) | |
1666 | { | |
1667 | /* We never moved: there was no opcode either! */ | |
1668 | as_bad ("missing opcode"); | |
1669 | return -1; | |
1670 | } | |
1671 | return 0; | |
fecd2382 | 1672 | } |
355afbcd KR |
1673 | } |
1674 | *iP++ = '\0'; /* Terminate opcode */ | |
1675 | return (get_args (iP, args)); | |
1676 | } /* i_scan() */ | |
fecd2382 RP |
1677 | |
1678 | ||
1679 | /***************************************************************************** | |
1680 | * mem_fmt: generate a MEMA- or MEMB-format instruction | |
1681 | * | |
1682 | **************************************************************************** */ | |
355afbcd KR |
1683 | static void |
1684 | mem_fmt (args, oP, callx) | |
1685 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ | |
1686 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
1687 | int callx; /* Is this a callx opcode */ | |
fecd2382 | 1688 | { |
355afbcd KR |
1689 | int i; /* Loop counter */ |
1690 | struct regop regop; /* Description of register operand */ | |
1691 | char opdesc; /* Operand descriptor byte */ | |
1692 | memS instr; /* Description of binary to be output */ | |
1693 | char *outP; /* Where the binary was output to */ | |
1694 | expressionS expr; /* Parsed expression */ | |
1695 | fixS *fixP; /*->description of deferred address fixup */ | |
1696 | ||
1697 | memset (&instr, '\0', sizeof (memS)); | |
1698 | instr.opcode = oP->opcode; | |
1699 | ||
1700 | /* Process operands. */ | |
1701 | for (i = 1; i <= oP->num_ops; i++) | |
1702 | { | |
1703 | opdesc = oP->operand[i - 1]; | |
1704 | ||
1705 | if (MEMOP (opdesc)) | |
1706 | { | |
1707 | parse_memop (&instr, args[i], oP->format); | |
fecd2382 | 1708 | } |
355afbcd KR |
1709 | else |
1710 | { | |
1711 | parse_regop (®op, args[i], opdesc); | |
1712 | instr.opcode |= regop.n << 19; | |
fecd2382 | 1713 | } |
355afbcd KR |
1714 | } |
1715 | ||
1716 | /* Output opcode */ | |
1717 | outP = emit (instr.opcode); | |
1718 | ||
1719 | if (instr.disp == 0) | |
1720 | { | |
1721 | return; | |
1722 | } | |
1723 | ||
1724 | /* Parse and process the displacement */ | |
1725 | switch (parse_expr (instr.e, &expr)) | |
1726 | { | |
1727 | ||
1728 | case SEG_GOOF: | |
1729 | as_bad ("expression syntax error"); | |
1730 | break; | |
1731 | ||
1732 | case SEG_ABSOLUTE: | |
1733 | if (instr.disp == 32) | |
1734 | { | |
1735 | (void) emit (offs (expr)); /* Output displacement */ | |
1736 | } | |
1737 | else | |
1738 | { | |
1739 | /* 12-bit displacement */ | |
1740 | if (offs (expr) & ~0xfff) | |
1741 | { | |
1742 | /* Won't fit in 12 bits: convert already-output | |
1743 | * instruction to MEMB format, output | |
1744 | * displacement. | |
1745 | */ | |
1746 | mema_to_memb (outP); | |
1747 | (void) emit (offs (expr)); | |
1748 | } | |
1749 | else | |
1750 | { | |
1751 | /* WILL fit in 12 bits: OR into opcode and | |
1752 | * overwrite the binary we already put out | |
1753 | */ | |
1754 | instr.opcode |= offs (expr); | |
1755 | md_number_to_chars (outP, instr.opcode, 4); | |
1756 | } | |
1757 | } | |
1758 | break; | |
1759 | ||
1760 | case SEG_DIFFERENCE: | |
1761 | case SEG_TEXT: | |
1762 | case SEG_DATA: | |
1763 | case SEG_BSS: | |
1764 | case SEG_UNKNOWN: | |
1765 | if (instr.disp == 12) | |
1766 | { | |
1767 | /* Displacement is dependent on a symbol, whose value | |
c47d388b ME |
1768 | * may change at link time. We HAVE to reserve 32 bits. |
1769 | * Convert already-output opcode to MEMB format. | |
1770 | */ | |
355afbcd KR |
1771 | mema_to_memb (outP); |
1772 | } | |
1773 | ||
1774 | /* Output 0 displacement and set up address fixup for when | |
c47d388b ME |
1775 | * this symbol's value becomes known. |
1776 | */ | |
355afbcd KR |
1777 | outP = emit ((long) 0); |
1778 | fixP = fix_new (frag_now, | |
1779 | outP - frag_now->fr_literal, | |
1780 | 4, | |
1781 | adds (expr), | |
1782 | subs (expr), | |
1783 | offs (expr), | |
1784 | 0, | |
1785 | NO_RELOC); | |
1786 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ | |
1787 | fixP->fx_bsr = callx; /*SAC LD RELAX HACK *//* Mark reloc as being in i stream */ | |
1788 | break; | |
1789 | ||
1790 | default: | |
1791 | BAD_CASE (segs (expr)); | |
1792 | break; | |
1793 | } | |
1794 | } /* memfmt() */ | |
fecd2382 RP |
1795 | |
1796 | ||
1797 | /***************************************************************************** | |
1798 | * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. | |
1799 | * | |
1800 | * There are 2 possible MEMA formats: | |
1801 | * - displacement only | |
1802 | * - displacement + abase | |
1803 | * | |
1804 | * They are distinguished by the setting of the MEMA_ABASE bit. | |
1805 | * | |
1806 | **************************************************************************** */ | |
355afbcd KR |
1807 | static void |
1808 | mema_to_memb (opcodeP) | |
1809 | char *opcodeP; /* Where to find the opcode, in target byte order */ | |
fecd2382 | 1810 | { |
355afbcd KR |
1811 | long opcode; /* Opcode in host byte order */ |
1812 | long mode; /* Mode bits for MEMB instruction */ | |
1813 | ||
1814 | opcode = md_chars_to_number (opcodeP, 4); | |
1815 | know (!(opcode & MEMB_BIT)); | |
1816 | ||
1817 | mode = MEMB_BIT | D_BIT; | |
1818 | if (opcode & MEMA_ABASE) | |
1819 | { | |
1820 | mode |= A_BIT; | |
1821 | } | |
1822 | ||
1823 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */ | |
1824 | opcode |= mode; /* Set MEMB mode bits */ | |
1825 | ||
1826 | md_number_to_chars (opcodeP, opcode, 4); | |
1827 | } /* mema_to_memb() */ | |
fecd2382 RP |
1828 | |
1829 | ||
1830 | /***************************************************************************** | |
1831 | * parse_expr: parse an expression | |
1832 | * | |
1833 | * Use base assembler's expression parser to parse an expression. | |
1834 | * It, unfortunately, runs off a global which we have to save/restore | |
1835 | * in order to make it work for us. | |
1836 | * | |
1837 | * An empty expression string is treated as an absolute 0. | |
1838 | * | |
1839 | * Return "segment" to which the expression evaluates. | |
1840 | * Return SEG_GOOF regardless of expression evaluation if entire input | |
1841 | * string is not consumed in the evaluation -- tolerate no dangling junk! | |
1842 | * | |
1843 | **************************************************************************** */ | |
1844 | static | |
355afbcd KR |
1845 | segT |
1846 | parse_expr (textP, expP) | |
1847 | char *textP; /* Text of expression to be parsed */ | |
1848 | expressionS *expP; /* Where to put the results of parsing */ | |
fecd2382 | 1849 | { |
355afbcd KR |
1850 | char *save_in; /* Save global here */ |
1851 | segT seg; /* Segment to which expression evaluates */ | |
1852 | symbolS *symP; | |
1853 | ||
1854 | know (textP); | |
1855 | ||
1856 | if (*textP == '\0') | |
1857 | { | |
1858 | /* Treat empty string as absolute 0 */ | |
1859 | expP->X_add_symbol = expP->X_subtract_symbol = NULL; | |
1860 | expP->X_add_number = 0; | |
1861 | seg = expP->X_seg = SEG_ABSOLUTE; | |
1862 | ||
1863 | } | |
1864 | else | |
1865 | { | |
1866 | save_in = input_line_pointer; /* Save global */ | |
1867 | input_line_pointer = textP; /* Make parser work for us */ | |
1868 | ||
1869 | seg = expression (expP); | |
1870 | if (input_line_pointer - textP != strlen (textP)) | |
1871 | { | |
1872 | /* Did not consume all of the input */ | |
1873 | seg = SEG_GOOF; | |
1874 | } | |
1875 | symP = expP->X_add_symbol; | |
1876 | if (symP && (hash_find (reg_hash, S_GET_NAME (symP)))) | |
1877 | { | |
1878 | /* Register name in an expression */ | |
1879 | seg = SEG_GOOF; | |
fecd2382 | 1880 | } |
355afbcd KR |
1881 | |
1882 | input_line_pointer = save_in; /* Restore global */ | |
1883 | } | |
1884 | return seg; | |
fecd2382 RP |
1885 | } |
1886 | ||
1887 | ||
1888 | /***************************************************************************** | |
1889 | * parse_ldcont: | |
1890 | * Parse and replace a 'ldconst' pseudo-instruction with an appropriate | |
1891 | * i80960 instruction. | |
1892 | * | |
1893 | * Assumes the input consists of: | |
1894 | * arg[0] opcode mnemonic ('ldconst') | |
1895 | * arg[1] first operand (constant) | |
1896 | * arg[2] name of register to be loaded | |
1897 | * | |
1898 | * Replaces opcode and/or operands as appropriate. | |
1899 | * | |
1900 | * Returns the new number of arguments, or -1 on failure. | |
1901 | * | |
1902 | **************************************************************************** */ | |
1903 | static | |
355afbcd KR |
1904 | int |
1905 | parse_ldconst (arg) | |
1906 | char *arg[]; /* See above */ | |
fecd2382 | 1907 | { |
355afbcd KR |
1908 | int n; /* Constant to be loaded */ |
1909 | int shift; /* Shift count for "shlo" instruction */ | |
1910 | static char buf[5]; /* Literal for first operand */ | |
1911 | static char buf2[5]; /* Literal for second operand */ | |
1912 | expressionS e; /* Parsed expression */ | |
1913 | ||
1914 | ||
1915 | arg[3] = NULL; /* So we can tell at the end if it got used or not */ | |
1916 | ||
1917 | switch (parse_expr (arg[1], &e)) | |
1918 | { | |
1919 | ||
1920 | case SEG_TEXT: | |
1921 | case SEG_DATA: | |
1922 | case SEG_BSS: | |
1923 | case SEG_UNKNOWN: | |
1924 | case SEG_DIFFERENCE: | |
1925 | /* We're dependent on one or more symbols -- use "lda" */ | |
1926 | arg[0] = "lda"; | |
1927 | break; | |
1928 | ||
1929 | case SEG_ABSOLUTE: | |
1930 | /* Try the following mappings: | |
fecd2382 RP |
1931 | * ldconst 0,<reg> ->mov 0,<reg> |
1932 | * ldconst 31,<reg> ->mov 31,<reg> | |
1933 | * ldconst 32,<reg> ->addo 1,31,<reg> | |
1934 | * ldconst 62,<reg> ->addo 31,31,<reg> | |
1935 | * ldconst 64,<reg> ->shlo 8,3,<reg> | |
1936 | * ldconst -1,<reg> ->subo 1,0,<reg> | |
1937 | * ldconst -31,<reg>->subo 31,0,<reg> | |
1938 | * | |
1939 | * anthing else becomes: | |
1940 | * lda xxx,<reg> | |
1941 | */ | |
355afbcd KR |
1942 | n = offs (e); |
1943 | if ((0 <= n) && (n <= 31)) | |
1944 | { | |
1945 | arg[0] = "mov"; | |
1946 | ||
1947 | } | |
1948 | else if ((-31 <= n) && (n <= -1)) | |
1949 | { | |
1950 | arg[0] = "subo"; | |
1951 | arg[3] = arg[2]; | |
1952 | sprintf (buf, "%d", -n); | |
1953 | arg[1] = buf; | |
1954 | arg[2] = "0"; | |
1955 | ||
fecd2382 | 1956 | } |
355afbcd KR |
1957 | else if ((32 <= n) && (n <= 62)) |
1958 | { | |
1959 | arg[0] = "addo"; | |
1960 | arg[3] = arg[2]; | |
1961 | arg[1] = "31"; | |
1962 | sprintf (buf, "%d", n - 31); | |
1963 | arg[2] = buf; | |
1964 | ||
1965 | } | |
1966 | else if ((shift = shift_ok (n)) != 0) | |
1967 | { | |
1968 | arg[0] = "shlo"; | |
1969 | arg[3] = arg[2]; | |
1970 | sprintf (buf, "%d", shift); | |
1971 | arg[1] = buf; | |
1972 | sprintf (buf2, "%d", n >> shift); | |
1973 | arg[2] = buf2; | |
1974 | ||
1975 | } | |
1976 | else | |
1977 | { | |
1978 | arg[0] = "lda"; | |
1979 | } | |
1980 | break; | |
1981 | ||
1982 | default: | |
1983 | as_bad ("invalid constant"); | |
1984 | return -1; | |
1985 | break; | |
1986 | } | |
1987 | return (arg[3] == 0) ? 2 : 3; | |
fecd2382 RP |
1988 | } |
1989 | ||
1990 | /***************************************************************************** | |
1991 | * parse_memop: parse a memory operand | |
1992 | * | |
1993 | * This routine is based on the observation that the 4 mode bits of the | |
1994 | * MEMB format, taken individually, have fairly consistent meaning: | |
1995 | * | |
1996 | * M3 (bit 13): 1 if displacement is present (D_BIT) | |
1997 | * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) | |
1998 | * M1 (bit 11): 1 if index is present (I_BIT) | |
1999 | * M0 (bit 10): 1 if abase is present (A_BIT) | |
2000 | * | |
2001 | * So we parse the memory operand and set bits in the mode as we find | |
2002 | * things. Then at the end, if we go to MEMB format, we need only set | |
2003 | * the MEMB bit (M2) and our mode is built for us. | |
2004 | * | |
2005 | * Unfortunately, I said "fairly consistent". The exceptions: | |
2006 | * | |
2007 | * DBIA | |
2008 | * 0100 Would seem illegal, but means "abase-only". | |
2009 | * | |
2010 | * 0101 Would seem to mean "abase-only" -- it means IP-relative. | |
2011 | * Must be converted to 0100. | |
2012 | * | |
2013 | * 0110 Would seem to mean "index-only", but is reserved. | |
2014 | * We turn on the D bit and provide a 0 displacement. | |
2015 | * | |
2016 | * The other thing to observe is that we parse from the right, peeling | |
2017 | * things * off as we go: first any index spec, then any abase, then | |
2018 | * the displacement. | |
2019 | * | |
2020 | **************************************************************************** */ | |
2021 | static | |
355afbcd KR |
2022 | void |
2023 | parse_memop (memP, argP, optype) | |
2024 | memS *memP; /* Where to put the results */ | |
2025 | char *argP; /* Text of the operand to be parsed */ | |
2026 | int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */ | |
fecd2382 | 2027 | { |
355afbcd KR |
2028 | char *indexP; /* Pointer to index specification with "[]" removed */ |
2029 | char *p; /* Temp char pointer */ | |
2030 | char iprel_flag; /* True if this is an IP-relative operand */ | |
2031 | int regnum; /* Register number */ | |
2032 | int scale; /* Scale factor: 1,2,4,8, or 16. Later converted | |
fecd2382 RP |
2033 | * to internal format (0,1,2,3,4 respectively). |
2034 | */ | |
355afbcd KR |
2035 | int mode; /* MEMB mode bits */ |
2036 | int *intP; /* Pointer to register number */ | |
2037 | ||
2038 | /* The following table contains the default scale factors for each | |
c47d388b ME |
2039 | * type of memory instruction. It is accessed using (optype-MEM1) |
2040 | * as an index -- thus it assumes the 'optype' constants are assigned | |
2041 | * consecutive values, in the order they appear in this table | |
2042 | */ | |
355afbcd KR |
2043 | static int def_scale[] = |
2044 | { | |
2045 | 1, /* MEM1 */ | |
2046 | 2, /* MEM2 */ | |
2047 | 4, /* MEM4 */ | |
2048 | 8, /* MEM8 */ | |
2049 | -1, /* MEM12 -- no valid default */ | |
2050 | 16 /* MEM16 */ | |
2051 | }; | |
2052 | ||
2053 | ||
2054 | iprel_flag = mode = 0; | |
2055 | ||
2056 | /* Any index present? */ | |
2057 | indexP = get_ispec (argP); | |
2058 | if (indexP) | |
2059 | { | |
2060 | p = strchr (indexP, '*'); | |
2061 | if (p == NULL) | |
2062 | { | |
2063 | /* No explicit scale -- use default for this | |
fecd2382 RP |
2064 | *instruction type. |
2065 | */ | |
355afbcd KR |
2066 | scale = def_scale[optype - MEM1]; |
2067 | } | |
2068 | else | |
2069 | { | |
2070 | *p++ = '\0'; /* Eliminate '*' */ | |
2071 | ||
2072 | /* Now indexP->a '\0'-terminated register name, | |
fecd2382 RP |
2073 | * and p->a scale factor. |
2074 | */ | |
355afbcd KR |
2075 | |
2076 | if (!strcmp (p, "16")) | |
2077 | { | |
2078 | scale = 16; | |
2079 | } | |
2080 | else if (strchr ("1248", *p) && (p[1] == '\0')) | |
2081 | { | |
2082 | scale = *p - '0'; | |
2083 | } | |
2084 | else | |
2085 | { | |
2086 | scale = -1; | |
2087 | } | |
2088 | } | |
2089 | ||
2090 | regnum = get_regnum (indexP); /* Get index reg. # */ | |
2091 | if (!IS_RG_REG (regnum)) | |
2092 | { | |
2093 | as_bad ("invalid index register"); | |
2094 | return; | |
fecd2382 | 2095 | } |
355afbcd KR |
2096 | |
2097 | /* Convert scale to its binary encoding */ | |
2098 | switch (scale) | |
2099 | { | |
2100 | case 1: | |
2101 | scale = 0 << 7; | |
2102 | break; | |
2103 | case 2: | |
2104 | scale = 1 << 7; | |
2105 | break; | |
2106 | case 4: | |
2107 | scale = 2 << 7; | |
2108 | break; | |
2109 | case 8: | |
2110 | scale = 3 << 7; | |
2111 | break; | |
2112 | case 16: | |
2113 | scale = 4 << 7; | |
2114 | break; | |
2115 | default: | |
2116 | as_bad ("invalid scale factor"); | |
2117 | return; | |
2118 | }; | |
2119 | ||
2120 | memP->opcode |= scale | regnum; /* Set index bits in opcode */ | |
2121 | mode |= I_BIT; /* Found a valid index spec */ | |
2122 | } | |
2123 | ||
2124 | /* Any abase (Register Indirect) specification present? */ | |
2125 | if ((p = strrchr (argP, '(')) != NULL) | |
2126 | { | |
2127 | /* "(" is there -- does it start a legal abase spec? | |
fecd2382 RP |
2128 | * (If not it could be part of a displacement expression.) |
2129 | */ | |
355afbcd KR |
2130 | intP = (int *) hash_find (areg_hash, p); |
2131 | if (intP != NULL) | |
2132 | { | |
2133 | /* Got an abase here */ | |
2134 | regnum = *intP; | |
2135 | *p = '\0'; /* discard register spec */ | |
2136 | if (regnum == IPREL) | |
2137 | { | |
2138 | /* We have to specialcase ip-rel mode */ | |
2139 | iprel_flag = 1; | |
2140 | } | |
2141 | else | |
2142 | { | |
2143 | memP->opcode |= regnum << 14; | |
2144 | mode |= A_BIT; | |
2145 | } | |
fecd2382 | 2146 | } |
355afbcd KR |
2147 | } |
2148 | ||
2149 | /* Any expression present? */ | |
2150 | memP->e = argP; | |
2151 | if (*argP != '\0') | |
2152 | { | |
2153 | mode |= D_BIT; | |
2154 | } | |
2155 | ||
2156 | /* Special-case ip-relative addressing */ | |
2157 | if (iprel_flag) | |
2158 | { | |
2159 | if (mode & I_BIT) | |
2160 | { | |
2161 | syntax (); | |
fecd2382 | 2162 | } |
355afbcd KR |
2163 | else |
2164 | { | |
2165 | memP->opcode |= 5 << 10; /* IP-relative mode */ | |
2166 | memP->disp = 32; | |
fecd2382 | 2167 | } |
355afbcd KR |
2168 | return; |
2169 | } | |
2170 | ||
2171 | /* Handle all other modes */ | |
2172 | switch (mode) | |
2173 | { | |
2174 | case D_BIT | A_BIT: | |
2175 | /* Go with MEMA instruction format for now (grow to MEMB later | |
fecd2382 RP |
2176 | * if 12 bits is not enough for the displacement). |
2177 | * MEMA format has a single mode bit: set it to indicate | |
2178 | * that abase is present. | |
2179 | */ | |
355afbcd KR |
2180 | memP->opcode |= MEMA_ABASE; |
2181 | memP->disp = 12; | |
2182 | break; | |
2183 | ||
2184 | case D_BIT: | |
2185 | /* Go with MEMA instruction format for now (grow to MEMB later | |
fecd2382 RP |
2186 | * if 12 bits is not enough for the displacement). |
2187 | */ | |
355afbcd KR |
2188 | memP->disp = 12; |
2189 | break; | |
2190 | ||
2191 | case A_BIT: | |
2192 | /* For some reason, the bit string for this mode is not | |
fecd2382 RP |
2193 | * consistent: it should be 0 (exclusive of the MEMB bit), |
2194 | * so we set it "by hand" here. | |
2195 | */ | |
355afbcd KR |
2196 | memP->opcode |= MEMB_BIT; |
2197 | break; | |
2198 | ||
2199 | case A_BIT | I_BIT: | |
2200 | /* set MEMB bit in mode, and OR in mode bits */ | |
2201 | memP->opcode |= mode | MEMB_BIT; | |
2202 | break; | |
2203 | ||
2204 | case I_BIT: | |
2205 | /* Treat missing displacement as displacement of 0 */ | |
2206 | mode |= D_BIT; | |
2207 | /*********************** | |
fecd2382 RP |
2208 | * Fall into next case * |
2209 | ********************** */ | |
355afbcd KR |
2210 | case D_BIT | A_BIT | I_BIT: |
2211 | case D_BIT | I_BIT: | |
2212 | /* set MEMB bit in mode, and OR in mode bits */ | |
2213 | memP->opcode |= mode | MEMB_BIT; | |
2214 | memP->disp = 32; | |
2215 | break; | |
2216 | ||
2217 | default: | |
2218 | syntax (); | |
2219 | break; | |
2220 | } | |
fecd2382 RP |
2221 | } |
2222 | ||
2223 | /***************************************************************************** | |
2224 | * parse_po: parse machine-dependent pseudo-op | |
2225 | * | |
2226 | * This is a top-level routine for machine-dependent pseudo-ops. It slurps | |
2227 | * up the rest of the input line, breaks out the individual arguments, | |
2228 | * and dispatches them to the correct handler. | |
2229 | **************************************************************************** */ | |
2230 | static | |
355afbcd KR |
2231 | void |
2232 | parse_po (po_num) | |
2233 | int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */ | |
fecd2382 | 2234 | { |
355afbcd | 2235 | char *args[4]; /* Pointers operands, with no embedded whitespace. |
fecd2382 RP |
2236 | * arg[0] unused. |
2237 | * arg[1-3]->operands | |
2238 | */ | |
355afbcd KR |
2239 | int n_ops; /* Number of operands */ |
2240 | char *p; /* Pointer to beginning of unparsed argument string */ | |
2241 | char eol; /* Character that indicated end of line */ | |
2242 | ||
2243 | extern char is_end_of_line[]; | |
2244 | ||
2245 | /* Advance input pointer to end of line. */ | |
2246 | p = input_line_pointer; | |
2247 | while (!is_end_of_line[*input_line_pointer]) | |
2248 | { | |
2249 | input_line_pointer++; | |
2250 | } | |
2251 | eol = *input_line_pointer; /* Save end-of-line char */ | |
2252 | *input_line_pointer = '\0'; /* Terminate argument list */ | |
2253 | ||
2254 | /* Parse out operands */ | |
2255 | n_ops = get_args (p, args); | |
2256 | if (n_ops == -1) | |
2257 | { | |
2258 | return; | |
2259 | } | |
2260 | ||
2261 | /* Dispatch to correct handler */ | |
2262 | switch (po_num) | |
2263 | { | |
2264 | case S_SYSPROC: | |
2265 | s_sysproc (n_ops, args); | |
2266 | break; | |
2267 | case S_LEAFPROC: | |
2268 | s_leafproc (n_ops, args); | |
2269 | break; | |
2270 | default: | |
2271 | BAD_CASE (po_num); | |
2272 | break; | |
2273 | } | |
2274 | ||
2275 | /* Restore eol, so line numbers get updated correctly. Base assembler | |
fecd2382 RP |
2276 | * assumes we leave input pointer pointing at char following the eol. |
2277 | */ | |
355afbcd | 2278 | *input_line_pointer++ = eol; |
fecd2382 RP |
2279 | } |
2280 | ||
2281 | /***************************************************************************** | |
2282 | * parse_regop: parse a register operand. | |
2283 | * | |
2284 | * In case of illegal operand, issue a message and return some valid | |
2285 | * information so instruction processing can continue. | |
2286 | **************************************************************************** */ | |
2287 | static | |
355afbcd KR |
2288 | void |
2289 | parse_regop (regopP, optext, opdesc) | |
2290 | struct regop *regopP; /* Where to put description of register operand */ | |
2291 | char *optext; /* Text of operand */ | |
2292 | char opdesc; /* Descriptor byte: what's legal for this operand */ | |
fecd2382 | 2293 | { |
355afbcd KR |
2294 | int n; /* Register number */ |
2295 | expressionS e; /* Parsed expression */ | |
2296 | ||
2297 | /* See if operand is a register */ | |
2298 | n = get_regnum (optext); | |
2299 | if (n >= 0) | |
2300 | { | |
2301 | if (IS_RG_REG (n)) | |
2302 | { | |
2303 | /* global or local register */ | |
2304 | if (!REG_ALIGN (opdesc, n)) | |
2305 | { | |
2306 | as_bad ("unaligned register"); | |
2307 | } | |
2308 | regopP->n = n; | |
2309 | regopP->mode = 0; | |
2310 | regopP->special = 0; | |
2311 | return; | |
2312 | } | |
2313 | else if (IS_FP_REG (n) && FP_OK (opdesc)) | |
2314 | { | |
2315 | /* Floating point register, and it's allowed */ | |
2316 | regopP->n = n - FP0; | |
2317 | regopP->mode = 1; | |
2318 | regopP->special = 0; | |
2319 | return; | |
2320 | } | |
2321 | else if (IS_SF_REG (n) && SFR_OK (opdesc)) | |
2322 | { | |
2323 | /* Special-function register, and it's allowed */ | |
2324 | regopP->n = n - SF0; | |
2325 | regopP->mode = 0; | |
2326 | regopP->special = 1; | |
2327 | if (!targ_has_sfr (regopP->n)) | |
2328 | { | |
2329 | as_bad ("no such sfr in this architecture"); | |
2330 | } | |
2331 | return; | |
2332 | } | |
2333 | } | |
2334 | else if (LIT_OK (opdesc)) | |
2335 | { | |
2336 | /* | |
fecd2382 RP |
2337 | * How about a literal? |
2338 | */ | |
355afbcd KR |
2339 | regopP->mode = 1; |
2340 | regopP->special = 0; | |
2341 | if (FP_OK (opdesc)) | |
2342 | { /* floating point literal acceptable */ | |
2343 | /* Skip over 0f, 0d, or 0e prefix */ | |
2344 | if ((optext[0] == '0') | |
2345 | && (optext[1] >= 'd') | |
2346 | && (optext[1] <= 'f')) | |
2347 | { | |
2348 | optext += 2; | |
2349 | } | |
2350 | ||
2351 | if (!strcmp (optext, "0.0") || !strcmp (optext, "0")) | |
2352 | { | |
2353 | regopP->n = 0x10; | |
2354 | return; | |
2355 | } | |
2356 | if (!strcmp (optext, "1.0") || !strcmp (optext, "1")) | |
2357 | { | |
2358 | regopP->n = 0x16; | |
2359 | return; | |
2360 | } | |
2361 | ||
fecd2382 | 2362 | } |
355afbcd KR |
2363 | else |
2364 | { /* fixed point literal acceptable */ | |
2365 | if ((parse_expr (optext, &e) != SEG_ABSOLUTE) | |
2366 | || (offs (e) < 0) || (offs (e) > 31)) | |
2367 | { | |
2368 | as_bad ("illegal literal"); | |
2369 | offs (e) = 0; | |
2370 | } | |
2371 | regopP->n = offs (e); | |
2372 | return; | |
2373 | } | |
2374 | } | |
2375 | ||
2376 | /* Nothing worked */ | |
2377 | syntax (); | |
2378 | regopP->mode = 0; /* Register r0 is always a good one */ | |
2379 | regopP->n = 0; | |
2380 | regopP->special = 0; | |
2381 | } /* parse_regop() */ | |
fecd2382 RP |
2382 | |
2383 | /***************************************************************************** | |
2384 | * reg_fmt: generate a REG-format instruction | |
2385 | * | |
2386 | **************************************************************************** */ | |
355afbcd KR |
2387 | static void |
2388 | reg_fmt (args, oP) | |
2389 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ | |
2390 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
fecd2382 | 2391 | { |
355afbcd KR |
2392 | long instr; /* Binary to be output */ |
2393 | struct regop regop; /* Description of register operand */ | |
2394 | int n_ops; /* Number of operands */ | |
2395 | ||
2396 | ||
2397 | instr = oP->opcode; | |
2398 | n_ops = oP->num_ops; | |
2399 | ||
2400 | if (n_ops >= 1) | |
2401 | { | |
2402 | parse_regop (®op, args[1], oP->operand[0]); | |
2403 | ||
2404 | if ((n_ops == 1) && !(instr & M3)) | |
2405 | { | |
2406 | /* 1-operand instruction in which the dst field should | |
fecd2382 RP |
2407 | * be used (instead of src1). |
2408 | */ | |
355afbcd KR |
2409 | regop.n <<= 19; |
2410 | if (regop.special) | |
2411 | { | |
2412 | regop.mode = regop.special; | |
2413 | } | |
2414 | regop.mode <<= 13; | |
2415 | regop.special = 0; | |
2416 | } | |
2417 | else | |
2418 | { | |
2419 | /* regop.n goes in bit 0, needs no shifting */ | |
2420 | regop.mode <<= 11; | |
2421 | regop.special <<= 5; | |
fecd2382 | 2422 | } |
355afbcd KR |
2423 | instr |= regop.n | regop.mode | regop.special; |
2424 | } | |
2425 | ||
2426 | if (n_ops >= 2) | |
2427 | { | |
2428 | parse_regop (®op, args[2], oP->operand[1]); | |
2429 | ||
2430 | if ((n_ops == 2) && !(instr & M3)) | |
2431 | { | |
2432 | /* 2-operand instruction in which the dst field should | |
fecd2382 RP |
2433 | * be used instead of src2). |
2434 | */ | |
355afbcd KR |
2435 | regop.n <<= 19; |
2436 | if (regop.special) | |
2437 | { | |
2438 | regop.mode = regop.special; | |
2439 | } | |
2440 | regop.mode <<= 13; | |
2441 | regop.special = 0; | |
fecd2382 | 2442 | } |
355afbcd KR |
2443 | else |
2444 | { | |
2445 | regop.n <<= 14; | |
2446 | regop.mode <<= 12; | |
2447 | regop.special <<= 6; | |
fecd2382 | 2448 | } |
355afbcd KR |
2449 | instr |= regop.n | regop.mode | regop.special; |
2450 | } | |
2451 | if (n_ops == 3) | |
2452 | { | |
2453 | parse_regop (®op, args[3], oP->operand[2]); | |
2454 | if (regop.special) | |
2455 | { | |
2456 | regop.mode = regop.special; | |
2457 | } | |
2458 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); | |
2459 | } | |
2460 | emit (instr); | |
fecd2382 RP |
2461 | } |
2462 | ||
2463 | ||
2464 | /***************************************************************************** | |
2465 | * relax_cobr: | |
2466 | * Replace cobr instruction in a code fragment with equivalent branch and | |
2467 | * compare instructions, so it can reach beyond a 13-bit displacement. | |
2468 | * Set up an address fix/relocation for the new branch instruction. | |
2469 | * | |
2470 | **************************************************************************** */ | |
2471 | ||
2472 | /* This "conditional jump" table maps cobr instructions into equivalent | |
2473 | * compare and branch opcodes. | |
2474 | */ | |
2475 | static | |
355afbcd KR |
2476 | struct |
2477 | { | |
2478 | long compare; | |
2479 | long branch; | |
2480 | } | |
2481 | ||
2482 | coj[] = | |
2483 | { /* COBR OPCODE: */ | |
2484 | CHKBIT, BNO, /* 0x30 - bbc */ | |
2485 | CMPO, BG, /* 0x31 - cmpobg */ | |
2486 | CMPO, BE, /* 0x32 - cmpobe */ | |
2487 | CMPO, BGE, /* 0x33 - cmpobge */ | |
2488 | CMPO, BL, /* 0x34 - cmpobl */ | |
2489 | CMPO, BNE, /* 0x35 - cmpobne */ | |
2490 | CMPO, BLE, /* 0x36 - cmpoble */ | |
2491 | CHKBIT, BO, /* 0x37 - bbs */ | |
2492 | CMPI, BNO, /* 0x38 - cmpibno */ | |
2493 | CMPI, BG, /* 0x39 - cmpibg */ | |
2494 | CMPI, BE, /* 0x3a - cmpibe */ | |
2495 | CMPI, BGE, /* 0x3b - cmpibge */ | |
2496 | CMPI, BL, /* 0x3c - cmpibl */ | |
2497 | CMPI, BNE, /* 0x3d - cmpibne */ | |
2498 | CMPI, BLE, /* 0x3e - cmpible */ | |
2499 | CMPI, BO, /* 0x3f - cmpibo */ | |
2500 | }; | |
fecd2382 RP |
2501 | |
2502 | static | |
355afbcd KR |
2503 | void |
2504 | relax_cobr (fragP) | |
2505 | register fragS *fragP; /* fragP->fr_opcode is assumed to point to | |
c47d388b ME |
2506 | * the cobr instruction, which comes at the |
2507 | * end of the code fragment. | |
2508 | */ | |
fecd2382 | 2509 | { |
355afbcd KR |
2510 | int opcode, src1, src2, m1, s2; |
2511 | /* Bit fields from cobr instruction */ | |
2512 | long bp_bits; /* Branch prediction bits from cobr instruction */ | |
2513 | long instr; /* A single i960 instruction */ | |
2514 | char *iP; /*->instruction to be replaced */ | |
2515 | fixS *fixP; /* Relocation that can be done at assembly time */ | |
2516 | ||
2517 | /* PICK UP & PARSE COBR INSTRUCTION */ | |
2518 | iP = fragP->fr_opcode; | |
2519 | instr = md_chars_to_number (iP, 4); | |
2520 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */ | |
2521 | src1 = (instr >> 19) & 0x1f; | |
2522 | m1 = (instr >> 13) & 1; | |
2523 | s2 = instr & 1; | |
2524 | src2 = (instr >> 14) & 0x1f; | |
2525 | bp_bits = instr & BP_MASK; | |
2526 | ||
2527 | /* GENERATE AND OUTPUT COMPARE INSTRUCTION */ | |
2528 | instr = coj[opcode].compare | |
2529 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); | |
2530 | md_number_to_chars (iP, instr, 4); | |
2531 | ||
2532 | /* OUTPUT BRANCH INSTRUCTION */ | |
2533 | md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4); | |
2534 | ||
2535 | /* SET UP ADDRESS FIXUP/RELOCATION */ | |
2536 | fixP = fix_new (fragP, | |
2537 | iP + 4 - fragP->fr_literal, | |
2538 | 4, | |
2539 | fragP->fr_symbol, | |
2540 | 0, | |
2541 | fragP->fr_offset, | |
2542 | 1, | |
2543 | NO_RELOC); | |
2544 | ||
2545 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */ | |
2546 | ||
2547 | fragP->fr_fix += 4; | |
2548 | frag_wane (fragP); | |
fecd2382 RP |
2549 | } |
2550 | ||
2551 | ||
2552 | /***************************************************************************** | |
2553 | * reloc_callj: Relocate a 'callj' instruction | |
2554 | * | |
2555 | * This is a "non-(GNU)-standard" machine-dependent hook. The base | |
2556 | * assembler calls it when it decides it can relocate an address at | |
2557 | * assembly time instead of emitting a relocation directive. | |
2558 | * | |
2559 | * Check to see if the relocation involves a 'callj' instruction to a: | |
2560 | * sysproc: Replace the default 'call' instruction with a 'calls' | |
2561 | * leafproc: Replace the default 'call' instruction with a 'bal'. | |
2562 | * other proc: Do nothing. | |
2563 | * | |
2564 | * See b.out.h for details on the 'n_other' field in a symbol structure. | |
2565 | * | |
2566 | * IMPORTANT!: | |
2567 | * Assumes the caller has already figured out, in the case of a leafproc, | |
2568 | * to use the 'bal' entry point, and has substituted that symbol into the | |
2569 | * passed fixup structure. | |
2570 | * | |
2571 | **************************************************************************** */ | |
355afbcd KR |
2572 | void |
2573 | reloc_callj (fixP) | |
2574 | fixS *fixP; /* Relocation that can be done at assembly time */ | |
fecd2382 | 2575 | { |
355afbcd KR |
2576 | char *where; /*->the binary for the instruction being relocated */ |
2577 | ||
2578 | if (!fixP->fx_callj) | |
2579 | { | |
2580 | return; | |
2581 | } /* This wasn't a callj instruction in the first place */ | |
2582 | ||
2583 | where = fixP->fx_frag->fr_literal + fixP->fx_where; | |
2584 | ||
2585 | if (TC_S_IS_SYSPROC (fixP->fx_addsy)) | |
2586 | { | |
2587 | /* Symbol is a .sysproc: replace 'call' with 'calls'. | |
fecd2382 RP |
2588 | * System procedure number is (other-1). |
2589 | */ | |
355afbcd KR |
2590 | md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4); |
2591 | ||
2592 | /* Nothing else needs to be done for this instruction. | |
fecd2382 RP |
2593 | * Make sure 'md_number_to_field()' will perform a no-op. |
2594 | */ | |
355afbcd KR |
2595 | fixP->fx_bit_fixP = (bit_fixS *) 1; |
2596 | ||
2597 | } | |
2598 | else if (TC_S_IS_CALLNAME (fixP->fx_addsy)) | |
2599 | { | |
2600 | /* Should not happen: see block comment above */ | |
2601 | as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy)); | |
2602 | ||
2603 | } | |
2604 | else if (TC_S_IS_BALNAME (fixP->fx_addsy)) | |
2605 | { | |
2606 | /* Replace 'call' with 'bal'; both instructions have | |
fecd2382 RP |
2607 | * the same format, so calling code should complete |
2608 | * relocation as if nothing happened here. | |
2609 | */ | |
355afbcd KR |
2610 | md_number_to_chars (where, BAL, 4); |
2611 | } | |
2612 | else if (TC_S_IS_BADPROC (fixP->fx_addsy)) | |
2613 | { | |
2614 | as_bad ("Looks like a proc, but can't tell what kind.\n"); | |
2615 | } /* switch on proc type */ | |
2616 | ||
2617 | /* else Symbol is neither a sysproc nor a leafproc */ | |
2618 | ||
2619 | return; | |
2620 | } /* reloc_callj() */ | |
fecd2382 RP |
2621 | |
2622 | ||
2623 | /***************************************************************************** | |
2624 | * s_leafproc: process .leafproc pseudo-op | |
2625 | * | |
2626 | * .leafproc takes two arguments, the second one is optional: | |
2627 | * arg[1]: name of 'call' entry point to leaf procedure | |
2628 | * arg[2]: name of 'bal' entry point to leaf procedure | |
2629 | * | |
2630 | * If the two arguments are identical, or if the second one is missing, | |
2631 | * the first argument is taken to be the 'bal' entry point. | |
2632 | * | |
2633 | * If there are 2 distinct arguments, we must make sure that the 'bal' | |
2634 | * entry point immediately follows the 'call' entry point in the linked | |
2635 | * list of symbols. | |
2636 | * | |
2637 | **************************************************************************** */ | |
355afbcd KR |
2638 | static void |
2639 | s_leafproc (n_ops, args) | |
2640 | int n_ops; /* Number of operands */ | |
2641 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
fecd2382 | 2642 | { |
355afbcd KR |
2643 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */ |
2644 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */ | |
2645 | ||
2646 | if ((n_ops != 1) && (n_ops != 2)) | |
2647 | { | |
2648 | as_bad ("should have 1 or 2 operands"); | |
2649 | return; | |
2650 | } /* Check number of arguments */ | |
2651 | ||
2652 | /* Find or create symbol for 'call' entry point. */ | |
2653 | callP = symbol_find_or_make (args[1]); | |
2654 | ||
2655 | if (TC_S_IS_CALLNAME (callP)) | |
2656 | { | |
2657 | as_warn ("Redefining leafproc %s", S_GET_NAME (callP)); | |
2658 | } /* is leafproc */ | |
2659 | ||
2660 | /* If that was the only argument, use it as the 'bal' entry point. | |
fecd2382 RP |
2661 | * Otherwise, mark it as the 'call' entry point and find or create |
2662 | * another symbol for the 'bal' entry point. | |
2663 | */ | |
355afbcd KR |
2664 | if ((n_ops == 1) || !strcmp (args[1], args[2])) |
2665 | { | |
2666 | TC_S_FORCE_TO_BALNAME (callP); | |
2667 | ||
2668 | } | |
2669 | else | |
2670 | { | |
2671 | TC_S_FORCE_TO_CALLNAME (callP); | |
2672 | ||
2673 | balP = symbol_find_or_make (args[2]); | |
2674 | if (TC_S_IS_CALLNAME (balP)) | |
2675 | { | |
2676 | as_warn ("Redefining leafproc %s", S_GET_NAME (balP)); | |
2677 | } | |
2678 | TC_S_FORCE_TO_BALNAME (balP); | |
2679 | ||
2680 | tc_set_bal_of_call (callP, balP); | |
2681 | } /* if only one arg, or the args are the same */ | |
2682 | ||
2683 | return; | |
2684 | } /* s_leafproc() */ | |
fecd2382 RP |
2685 | |
2686 | ||
2687 | /* | |
2688 | * s_sysproc: process .sysproc pseudo-op | |
2689 | * | |
2690 | * .sysproc takes two arguments: | |
2691 | * arg[1]: name of entry point to system procedure | |
2692 | * arg[2]: 'entry_num' (index) of system procedure in the range | |
2693 | * [0,31] inclusive. | |
2694 | * | |
2695 | * For [ab].out, we store the 'entrynum' in the 'n_other' field of | |
2696 | * the symbol. Since that entry is normally 0, we bias 'entrynum' | |
2697 | * by adding 1 to it. It must be unbiased before it is used. | |
2698 | */ | |
355afbcd KR |
2699 | static void |
2700 | s_sysproc (n_ops, args) | |
2701 | int n_ops; /* Number of operands */ | |
2702 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
fecd2382 | 2703 | { |
355afbcd KR |
2704 | expressionS exp; |
2705 | symbolS *symP; | |
2706 | ||
2707 | if (n_ops != 2) | |
2708 | { | |
2709 | as_bad ("should have two operands"); | |
2710 | return; | |
2711 | } /* bad arg count */ | |
2712 | ||
2713 | /* Parse "entry_num" argument and check it for validity. */ | |
2714 | if ((parse_expr (args[2], &exp) != SEG_ABSOLUTE) | |
2715 | || (offs (exp) < 0) | |
2716 | || (offs (exp) > 31)) | |
2717 | { | |
2718 | as_bad ("'entry_num' must be absolute number in [0,31]"); | |
2719 | return; | |
2720 | } | |
2721 | ||
2722 | /* Find/make symbol and stick entry number (biased by +1) into it */ | |
2723 | symP = symbol_find_or_make (args[1]); | |
2724 | ||
2725 | if (TC_S_IS_SYSPROC (symP)) | |
2726 | { | |
2727 | as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP)); | |
2728 | } /* redefining */ | |
2729 | ||
2730 | TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */ | |
2731 | TC_S_FORCE_TO_SYSPROC (symP); | |
2732 | ||
2733 | return; | |
2734 | } /* s_sysproc() */ | |
fecd2382 RP |
2735 | |
2736 | ||
2737 | /***************************************************************************** | |
2738 | * shift_ok: | |
2739 | * Determine if a "shlo" instruction can be used to implement a "ldconst". | |
2740 | * This means that some number X < 32 can be shifted left to produce the | |
2741 | * constant of interest. | |
2742 | * | |
2743 | * Return the shift count, or 0 if we can't do it. | |
2744 | * Caller calculates X by shifting original constant right 'shift' places. | |
2745 | * | |
2746 | **************************************************************************** */ | |
2747 | static | |
355afbcd KR |
2748 | int |
2749 | shift_ok (n) | |
2750 | int n; /* The constant of interest */ | |
fecd2382 | 2751 | { |
355afbcd KR |
2752 | int shift; /* The shift count */ |
2753 | ||
2754 | if (n <= 0) | |
2755 | { | |
2756 | /* Can't do it for negative numbers */ | |
2757 | return 0; | |
2758 | } | |
2759 | ||
2760 | /* Shift 'n' right until a 1 is about to be lost */ | |
2761 | for (shift = 0; (n & 1) == 0; shift++) | |
2762 | { | |
2763 | n >>= 1; | |
2764 | } | |
2765 | ||
2766 | if (n >= 32) | |
2767 | { | |
2768 | return 0; | |
2769 | } | |
2770 | return shift; | |
fecd2382 RP |
2771 | } |
2772 | ||
2773 | ||
2774 | /***************************************************************************** | |
2775 | * syntax: issue syntax error | |
2776 | * | |
2777 | **************************************************************************** */ | |
355afbcd KR |
2778 | static void |
2779 | syntax () | |
2780 | { | |
2781 | as_bad ("syntax error"); | |
2782 | } /* syntax() */ | |
fecd2382 RP |
2783 | |
2784 | ||
2785 | /***************************************************************************** | |
2786 | * targ_has_sfr: | |
2787 | * Return TRUE iff the target architecture supports the specified | |
2788 | * special-function register (sfr). | |
2789 | * | |
2790 | **************************************************************************** */ | |
2791 | static | |
355afbcd KR |
2792 | int |
2793 | targ_has_sfr (n) | |
2794 | int n; /* Number (0-31) of sfr */ | |
fecd2382 | 2795 | { |
355afbcd KR |
2796 | switch (architecture) |
2797 | { | |
2798 | case ARCH_KA: | |
2799 | case ARCH_KB: | |
2800 | case ARCH_MC: | |
2801 | return 0; | |
2802 | case ARCH_CA: | |
2803 | default: | |
2804 | return ((0 <= n) && (n <= 2)); | |
2805 | } | |
fecd2382 RP |
2806 | } |
2807 | ||
2808 | ||
2809 | /***************************************************************************** | |
2810 | * targ_has_iclass: | |
2811 | * Return TRUE iff the target architecture supports the indicated | |
2812 | * class of instructions. | |
2813 | * | |
2814 | **************************************************************************** */ | |
2815 | static | |
355afbcd KR |
2816 | int |
2817 | targ_has_iclass (ic) | |
2818 | int ic; /* Instruction class; one of: | |
a39116f1 RP |
2819 | * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM |
2820 | */ | |
fecd2382 | 2821 | { |
355afbcd KR |
2822 | iclasses_seen |= ic; |
2823 | switch (architecture) | |
2824 | { | |
2825 | case ARCH_KA: | |
2826 | return ic & (I_BASE | I_KX); | |
2827 | case ARCH_KB: | |
2828 | return ic & (I_BASE | I_KX | I_FP | I_DEC); | |
2829 | case ARCH_MC: | |
2830 | return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); | |
2831 | case ARCH_CA: | |
2832 | return ic & (I_BASE | I_CX | I_CASIM); | |
2833 | default: | |
2834 | if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL)) | |
2835 | && (iclasses_seen & I_CX)) | |
2836 | { | |
2837 | as_warn ("architecture of opcode conflicts with that of earlier instruction(s)"); | |
2838 | iclasses_seen &= ~ic; | |
fecd2382 | 2839 | } |
355afbcd KR |
2840 | return 1; |
2841 | } | |
fecd2382 RP |
2842 | } |
2843 | ||
2844 | ||
2845 | /* Parse an operand that is machine-specific. | |
2846 | We just return without modifying the expression if we have nothing | |
2847 | to do. */ | |
2848 | ||
2849 | /* ARGSUSED */ | |
2850 | void | |
355afbcd KR |
2851 | md_operand (expressionP) |
2852 | expressionS *expressionP; | |
fecd2382 RP |
2853 | { |
2854 | } | |
2855 | ||
2856 | /* We have no need to default values of symbols. */ | |
2857 | ||
2858 | /* ARGSUSED */ | |
355afbcd KR |
2859 | symbolS * |
2860 | md_undefined_symbol (name) | |
2861 | char *name; | |
fecd2382 | 2862 | { |
355afbcd KR |
2863 | return 0; |
2864 | } /* md_undefined_symbol() */ | |
fecd2382 RP |
2865 | |
2866 | /* Exactly what point is a PC-relative offset relative TO? | |
2867 | On the i960, they're relative to the address of the instruction, | |
2868 | which we have set up as the address of the fixup too. */ | |
2869 | long | |
355afbcd KR |
2870 | md_pcrel_from (fixP) |
2871 | fixS *fixP; | |
fecd2382 | 2872 | { |
355afbcd | 2873 | return fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
2874 | } |
2875 | ||
2876 | void | |
355afbcd KR |
2877 | md_apply_fix (fixP, val) |
2878 | fixS *fixP; | |
2879 | long val; | |
fecd2382 | 2880 | { |
355afbcd KR |
2881 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; |
2882 | ||
2883 | if (!fixP->fx_bit_fixP) | |
2884 | { | |
2885 | ||
2886 | switch (fixP->fx_im_disp) | |
2887 | { | |
2888 | case 0: | |
2889 | fixP->fx_addnumber = val; | |
2890 | md_number_to_imm (place, val, fixP->fx_size, fixP); | |
2891 | break; | |
2892 | case 1: | |
2893 | md_number_to_disp (place, | |
c47d388b ME |
2894 | (fixP->fx_pcrel |
2895 | ? val + fixP->fx_pcrel_adjust | |
2896 | : val), | |
355afbcd KR |
2897 | fixP->fx_size); |
2898 | break; | |
2899 | case 2: /* fix requested for .long .word etc */ | |
2900 | md_number_to_chars (place, val, fixP->fx_size); | |
2901 | break; | |
2902 | default: | |
c47d388b ME |
2903 | as_fatal ("Internal error in md_apply_fix() in file \"%s\"", |
2904 | __FILE__); | |
2905 | } | |
355afbcd KR |
2906 | } |
2907 | else | |
2908 | { | |
2909 | md_number_to_field (place, val, fixP->fx_bit_fixP); | |
2910 | } | |
2911 | ||
2912 | return; | |
2913 | } /* md_apply_fix() */ | |
fecd2382 RP |
2914 | |
2915 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
355afbcd KR |
2916 | void |
2917 | tc_bout_fix_to_chars (where, fixP, segment_address_in_file) | |
2918 | char *where; | |
2919 | fixS *fixP; | |
2920 | relax_addressT segment_address_in_file; | |
fecd2382 | 2921 | { |
355afbcd KR |
2922 | static unsigned char nbytes_r_length[] = |
2923 | {42, 0, 1, 42, 2}; | |
2924 | struct relocation_info ri; | |
2925 | symbolS *symbolP; | |
2926 | ||
2927 | /* JF this is for paranoia */ | |
2928 | memset ((char *) &ri, '\0', sizeof (ri)); | |
2929 | symbolP = fixP->fx_addsy; | |
2930 | know (symbolP != 0 || fixP->fx_r_type != NO_RELOC); | |
2931 | ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ | |
2932 | /* These two 'cuz of NS32K */ | |
2933 | ri.r_callj = fixP->fx_callj; | |
2934 | if (fixP->fx_bit_fixP) | |
2935 | { | |
2936 | ri.r_length = 2; | |
2937 | } | |
2938 | else | |
2939 | { | |
2940 | ri.r_length = nbytes_r_length[fixP->fx_size]; | |
2941 | } | |
2942 | ri.r_pcrel = fixP->fx_pcrel; | |
2943 | ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; | |
2944 | ||
2945 | if (fixP->fx_r_type != NO_RELOC) | |
2946 | { | |
2947 | switch (fixP->fx_r_type) | |
2948 | { | |
2949 | case rs_align: | |
2950 | ri.r_index = -2; | |
2951 | ri.r_pcrel = 1; | |
2952 | ri.r_length = fixP->fx_size - 1; | |
2953 | break; | |
2954 | case rs_org: | |
2955 | ri.r_index = -2; | |
2956 | ri.r_pcrel = 0; | |
2957 | break; | |
2958 | case rs_fill: | |
2959 | ri.r_index = -1; | |
2960 | break; | |
2961 | default: | |
2962 | abort (); | |
fecd2382 | 2963 | } |
355afbcd KR |
2964 | ri.r_extern = 0; |
2965 | } | |
2966 | else if (linkrelax || !S_IS_DEFINED (symbolP)) | |
2967 | { | |
2968 | ri.r_extern = 1; | |
2969 | ri.r_index = symbolP->sy_number; | |
2970 | } | |
2971 | else | |
2972 | { | |
2973 | ri.r_extern = 0; | |
2974 | ri.r_index = S_GET_TYPE (symbolP); | |
2975 | } | |
2976 | ||
2977 | /* Output the relocation information in machine-dependent form. */ | |
2978 | md_ri_to_chars (where, &ri); | |
2979 | ||
2980 | return; | |
2981 | } /* tc_bout_fix_to_chars() */ | |
fecd2382 | 2982 | |
fecd2382 RP |
2983 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
2984 | ||
2985 | /* Align an address by rounding it up to the specified boundary. | |
2986 | */ | |
c47d388b | 2987 | valueT |
355afbcd KR |
2988 | md_section_align (seg, addr) |
2989 | segT seg; | |
c47d388b | 2990 | valueT addr; /* Address to be rounded up */ |
fecd2382 | 2991 | { |
355afbcd KR |
2992 | return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg])); |
2993 | } /* md_section_align() */ | |
fecd2382 RP |
2994 | |
2995 | #ifdef OBJ_COFF | |
355afbcd KR |
2996 | void |
2997 | tc_headers_hook (headers) | |
2998 | object_headers *headers; | |
fecd2382 | 2999 | { |
355afbcd KR |
3000 | /* FIXME: remove this line *//* unsigned short arch_flag = 0; */ |
3001 | ||
3002 | if (iclasses_seen == I_BASE) | |
3003 | { | |
3004 | headers->filehdr.f_flags |= F_I960CORE; | |
3005 | } | |
3006 | else if (iclasses_seen & I_CX) | |
3007 | { | |
3008 | headers->filehdr.f_flags |= F_I960CA; | |
3009 | } | |
3010 | else if (iclasses_seen & I_MIL) | |
3011 | { | |
3012 | headers->filehdr.f_flags |= F_I960MC; | |
3013 | } | |
3014 | else if (iclasses_seen & (I_DEC | I_FP)) | |
3015 | { | |
3016 | headers->filehdr.f_flags |= F_I960KB; | |
3017 | } | |
3018 | else | |
3019 | { | |
3020 | headers->filehdr.f_flags |= F_I960KA; | |
3021 | } /* set arch flag */ | |
3022 | ||
3023 | if (flagseen['R']) | |
3024 | { | |
3025 | headers->filehdr.f_magic = I960RWMAGIC; | |
3026 | headers->aouthdr.magic = OMAGIC; | |
3027 | } | |
3028 | else | |
3029 | { | |
3030 | headers->filehdr.f_magic = I960ROMAGIC; | |
3031 | headers->aouthdr.magic = NMAGIC; | |
3032 | } /* set magic numbers */ | |
3033 | ||
3034 | return; | |
3035 | } /* tc_headers_hook() */ | |
3036 | ||
fecd2382 RP |
3037 | #endif /* OBJ_COFF */ |
3038 | ||
3039 | /* | |
3040 | * Things going on here: | |
3041 | * | |
3042 | * For bout, We need to assure a couple of simplifying | |
3043 | * assumptions about leafprocs for the linker: the leafproc | |
3044 | * entry symbols will be defined in the same assembly in | |
3045 | * which they're declared with the '.leafproc' directive; | |
3046 | * and if a leafproc has both 'call' and 'bal' entry points | |
3047 | * they are both global or both local. | |
3048 | * | |
3049 | * For coff, the call symbol has a second aux entry that | |
3050 | * contains the bal entry point. The bal symbol becomes a | |
3051 | * label. | |
3052 | * | |
3053 | * For coff representation, the call symbol has a second aux entry that | |
3054 | * contains the bal entry point. The bal symbol becomes a label. | |
3055 | * | |
3056 | */ | |
3057 | ||
355afbcd KR |
3058 | void |
3059 | tc_crawl_symbol_chain (headers) | |
3060 | object_headers *headers; | |
fecd2382 | 3061 | { |
355afbcd KR |
3062 | symbolS *symbolP; |
3063 | ||
3064 | for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP)) | |
3065 | { | |
fecd2382 | 3066 | #ifdef OBJ_COFF |
355afbcd KR |
3067 | if (TC_S_IS_SYSPROC (symbolP)) |
3068 | { | |
3069 | /* second aux entry already contains the sysproc number */ | |
3070 | S_SET_NUMBER_AUXILIARY (symbolP, 2); | |
3071 | S_SET_STORAGE_CLASS (symbolP, C_SCALL); | |
3072 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
3073 | continue; | |
3074 | } /* rewrite sysproc */ | |
fecd2382 | 3075 | #endif /* OBJ_COFF */ |
355afbcd KR |
3076 | |
3077 | if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP)) | |
3078 | { | |
3079 | continue; | |
3080 | } /* Not a leafproc symbol */ | |
3081 | ||
3082 | if (!S_IS_DEFINED (symbolP)) | |
3083 | { | |
3084 | as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP)); | |
3085 | } /* undefined leaf */ | |
3086 | ||
3087 | if (TC_S_IS_CALLNAME (symbolP)) | |
3088 | { | |
3089 | symbolS *balP = tc_get_bal_of_call (symbolP); | |
3090 | if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP)) | |
3091 | { | |
3092 | S_SET_EXTERNAL (symbolP); | |
3093 | S_SET_EXTERNAL (balP); | |
3094 | as_warn ("Warning: making leafproc entries %s and %s both global\n", | |
3095 | S_GET_NAME (symbolP), S_GET_NAME (balP)); | |
3096 | } /* externality mismatch */ | |
3097 | } /* if callname */ | |
3098 | } /* walk the symbol chain */ | |
3099 | ||
3100 | return; | |
3101 | } /* tc_crawl_symbol_chain() */ | |
fecd2382 RP |
3102 | |
3103 | /* | |
3104 | * For aout or bout, the bal immediately follows the call. | |
3105 | * | |
3106 | * For coff, we cheat and store a pointer to the bal symbol | |
3107 | * in the second aux entry of the call. | |
3108 | */ | |
3109 | ||
355afbcd KR |
3110 | #undef OBJ_ABOUT |
3111 | #ifdef OBJ_AOUT | |
3112 | #define OBJ_ABOUT | |
3113 | #endif | |
3114 | #ifdef OBJ_BOUT | |
3115 | #define OBJ_ABOUT | |
3116 | #endif | |
3117 | ||
3118 | void | |
3119 | tc_set_bal_of_call (callP, balP) | |
3120 | symbolS *callP; | |
3121 | symbolS *balP; | |
fecd2382 | 3122 | { |
355afbcd KR |
3123 | know (TC_S_IS_CALLNAME (callP)); |
3124 | know (TC_S_IS_BALNAME (balP)); | |
3125 | ||
fecd2382 | 3126 | #ifdef OBJ_COFF |
355afbcd KR |
3127 | |
3128 | callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP; | |
3129 | S_SET_NUMBER_AUXILIARY (callP, 2); | |
3130 | ||
3131 | #else /* ! OBJ_COFF */ | |
3132 | #ifdef OBJ_ABOUT | |
3133 | ||
3134 | /* If the 'bal' entry doesn't immediately follow the 'call' | |
fecd2382 RP |
3135 | * symbol, unlink it from the symbol list and re-insert it. |
3136 | */ | |
355afbcd KR |
3137 | if (symbol_next (callP) != balP) |
3138 | { | |
3139 | symbol_remove (balP, &symbol_rootP, &symbol_lastP); | |
3140 | symbol_append (balP, callP, &symbol_rootP, &symbol_lastP); | |
3141 | } /* if not in order */ | |
3142 | ||
3143 | #else /* ! OBJ_ABOUT */ | |
3144 | (as yet unwritten.); | |
3145 | #endif /* ! OBJ_ABOUT */ | |
3146 | #endif /* ! OBJ_COFF */ | |
3147 | ||
3148 | return; | |
3149 | } /* tc_set_bal_of_call() */ | |
3150 | ||
3151 | char * | |
3152 | _tc_get_bal_of_call (callP) | |
3153 | symbolS *callP; | |
fecd2382 | 3154 | { |
355afbcd KR |
3155 | symbolS *retval; |
3156 | ||
3157 | know (TC_S_IS_CALLNAME (callP)); | |
3158 | ||
fecd2382 | 3159 | #ifdef OBJ_COFF |
355afbcd | 3160 | retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry); |
fecd2382 | 3161 | #else |
355afbcd KR |
3162 | #ifdef OBJ_ABOUT |
3163 | retval = symbol_next (callP); | |
3164 | #else | |
3165 | (as yet unwritten.); | |
3166 | #endif /* ! OBJ_ABOUT */ | |
3167 | #endif /* ! OBJ_COFF */ | |
3168 | ||
3169 | know (TC_S_IS_BALNAME (retval)); | |
3170 | return ((char *) retval); | |
3171 | } /* _tc_get_bal_of_call() */ | |
3172 | ||
3173 | void | |
3174 | tc_coff_symbol_emit_hook (symbolP) | |
3175 | symbolS *symbolP; | |
fecd2382 | 3176 | { |
355afbcd KR |
3177 | if (TC_S_IS_CALLNAME (symbolP)) |
3178 | { | |
fecd2382 | 3179 | #ifdef OBJ_COFF |
355afbcd KR |
3180 | symbolS *balP = tc_get_bal_of_call (symbolP); |
3181 | ||
3182 | /* second aux entry contains the bal entry point */ | |
3183 | /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */ | |
3184 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP); | |
3185 | S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT)); | |
3186 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
3187 | /* fix up the bal symbol */ | |
3188 | S_SET_STORAGE_CLASS (balP, C_LABEL); | |
fecd2382 | 3189 | #endif /* OBJ_COFF */ |
355afbcd KR |
3190 | } /* only on calls */ |
3191 | ||
3192 | return; | |
3193 | } /* tc_coff_symbol_emit_hook() */ | |
fecd2382 | 3194 | |
09952cd9 KR |
3195 | void |
3196 | i960_handle_align (fragp) | |
3197 | fragS *fragp; | |
3198 | { | |
3199 | fixS *fixp; | |
3200 | segT old_seg = now_seg, this_seg; | |
3201 | int old_subseg = now_subseg; | |
3202 | int pad_size; | |
3203 | extern struct frag *text_last_frag, *data_last_frag; | |
3204 | ||
3205 | if (!linkrelax) | |
3206 | return; | |
3207 | ||
3208 | /* The text section "ends" with another alignment reloc, to which we | |
3209 | aren't adding padding. */ | |
3210 | if (fragp->fr_next == text_last_frag | |
3211 | || fragp->fr_next == data_last_frag) | |
3212 | { | |
3213 | return; | |
3214 | } | |
3215 | ||
3216 | /* alignment directive */ | |
3217 | fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, 0, | |
3218 | (int) fragp->fr_type); | |
3219 | } | |
3220 | ||
8b228fe9 | 3221 | /* end of tc-i960.c */ |