3a69b3ac |
1 | /* i960.c - All the i80960-specific stuff |
2 | Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc. |
3 | |
4 | This file is part of GAS. |
5 | |
6 | GAS is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by |
8 | the Free Software Foundation; either version 1, or (at your option) |
9 | any later version. |
10 | |
11 | GAS is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | GNU General Public License for more details. |
15 | |
16 | You should have received a copy of the GNU General Public License |
17 | along with GAS; see the file COPYING. If not, write to |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ |
19 | |
20 | /* $Id$ */ |
21 | |
22 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
23 | |
24 | /****************************************************************************** |
25 | * i80690 NOTE!!!: |
26 | * Header, symbol, and relocation info will be used on the host machine |
27 | * only -- only executable code is actually downloaded to the i80960. |
28 | * Therefore, leave all such information in host byte order. |
29 | * |
30 | * (That's a slight lie -- we DO download some header information, but |
31 | * the downloader converts the file format and corrects the byte-ordering |
32 | * of the relevant fields while doing so.) |
33 | * |
34 | ***************************************************************************** */ |
35 | |
36 | /* There are 4 different lengths of (potentially) symbol-based displacements |
37 | * in the 80960 instruction set, each of which could require address fix-ups |
38 | * and (in the case of external symbols) emission of relocation directives: |
39 | * |
40 | * 32-bit (MEMB) |
41 | * This is a standard length for the base assembler and requires no |
42 | * special action. |
43 | * |
44 | * 13-bit (COBR) |
45 | * This is a non-standard length, but the base assembler has a hook for |
46 | * bit field address fixups: the fixS structure can point to a descriptor |
47 | * of the field, in which case our md_number_to_field() routine gets called |
48 | * to process it. |
49 | * |
50 | * I made the hook a little cleaner by having fix_new() (in the base |
51 | * assembler) return a pointer to the fixS in question. And I made it a |
52 | * little simpler by storing the field size (in this case 13) instead of |
53 | * of a pointer to another structure: 80960 displacements are ALWAYS |
54 | * stored in the low-order bits of a 4-byte word. |
55 | * |
56 | * Since the target of a COBR cannot be external, no relocation directives |
57 | * for this size displacement have to be generated. But the base assembler |
58 | * had to be modified to issue error messages if the symbol did turn out |
59 | * to be external. |
60 | * |
61 | * 24-bit (CTRL) |
62 | * Fixups are handled as for the 13-bit case (except that 24 is stored |
63 | * in the fixS). |
64 | * |
65 | * The relocation directive generated is the same as that for the 32-bit |
66 | * displacement, except that it's PC-relative (the 32-bit displacement |
67 | * never is). The i80960 version of the linker needs a mod to |
68 | * distinguish and handle the 24-bit case. |
69 | * |
70 | * 12-bit (MEMA) |
71 | * MEMA formats are always promoted to MEMB (32-bit) if the displacement |
72 | * is based on a symbol, because it could be relocated at link time. |
73 | * The only time we use the 12-bit format is if an absolute value of |
74 | * less than 4096 is specified, in which case we need neither a fixup nor |
75 | * a relocation directive. |
76 | */ |
77 | |
78 | #include <stdio.h> |
79 | #include <ctype.h> |
80 | |
81 | #include "as.h" |
82 | |
83 | #include "obstack.h" |
84 | |
85 | #include "i960-opcode.h" |
86 | |
87 | extern char *input_line_pointer; |
88 | extern struct hash_control *po_hash; |
89 | extern unsigned char nbytes_r_length[]; |
90 | extern char *next_object_file_charP; |
91 | |
92 | #ifdef OBJ_COFF |
93 | int md_reloc_size = sizeof(struct reloc); |
94 | #else /* OBJ_COFF */ |
95 | int md_reloc_size = sizeof(struct relocation_info); |
96 | #endif /* OBJ_COFF */ |
97 | |
98 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) |
99 | #ifdef __STDC__ |
100 | |
101 | static void emit_machine_reloc(fixS *fixP, relax_addressT segment_address_in_file); |
102 | |
103 | #else /* __STDC__ */ |
104 | |
105 | static void emit_machine_reloc(); |
106 | |
107 | #endif /* __STDC__ */ |
108 | |
109 | void (*md_emit_relocations)() = emit_machine_reloc; |
110 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
111 | |
112 | /*************************** |
113 | * Local i80960 routines * |
114 | ************************** */ |
115 | |
116 | static void brcnt_emit(); /* Emit branch-prediction instrumentation code */ |
117 | static char * brlab_next(); /* Return next branch local label */ |
118 | void brtab_emit(); /* Emit br-predict instrumentation table */ |
119 | static void cobr_fmt(); /* Generate COBR instruction */ |
120 | static void ctrl_fmt(); /* Generate CTRL instruction */ |
121 | static char * emit(); /* Emit (internally) binary */ |
122 | static int get_args(); /* Break arguments out of comma-separated list */ |
123 | static void get_cdisp(); /* Handle COBR or CTRL displacement */ |
124 | static char * get_ispec(); /* Find index specification string */ |
125 | static int get_regnum(); /* Translate text to register number */ |
126 | static int i_scan(); /* Lexical scan of instruction source */ |
127 | static void mem_fmt(); /* Generate MEMA or MEMB instruction */ |
128 | static void mema_to_memb(); /* Convert MEMA instruction to MEMB format */ |
129 | static segT parse_expr(); /* Parse an expression */ |
130 | static int parse_ldconst();/* Parse and replace a 'ldconst' pseudo-op */ |
131 | static void parse_memop(); /* Parse a memory operand */ |
132 | static void parse_po(); /* Parse machine-dependent pseudo-op */ |
133 | static void parse_regop(); /* Parse a register operand */ |
134 | static void reg_fmt(); /* Generate a REG format instruction */ |
135 | void reloc_callj(); /* Relocate a 'callj' instruction */ |
136 | static void relax_cobr(); /* "De-optimize" cobr into compare/branch */ |
137 | static void s_leafproc(); /* Process '.leafproc' pseudo-op */ |
138 | static void s_sysproc(); /* Process '.sysproc' pseudo-op */ |
139 | static int shift_ok(); /* Will a 'shlo' substiture for a 'ldconst'? */ |
140 | static void syntax(); /* Give syntax error */ |
141 | static int targ_has_sfr(); /* Target chip supports spec-func register? */ |
142 | static int targ_has_iclass();/* Target chip supports instruction set? */ |
143 | /* static void unlink_sym(); */ /* Remove a symbol from the symbol list */ |
144 | |
145 | /* See md_parse_option() for meanings of these options */ |
146 | static char norelax = 0; /* True if -norelax switch seen */ |
147 | static char instrument_branches = 0; /* True if -b switch seen */ |
148 | |
149 | /* Characters that always start a comment. |
150 | * If the pre-processor is disabled, these aren't very useful. |
151 | */ |
152 | char comment_chars[] = "#"; |
153 | |
154 | /* Characters that only start a comment at the beginning of |
155 | * a line. If the line seems to have the form '# 123 filename' |
156 | * .line and .file directives will appear in the pre-processed output. |
157 | * |
158 | * Note that input_file.c hand checks for '#' at the beginning of the |
159 | * first line of the input file. This is because the compiler outputs |
160 | * #NO_APP at the beginning of its output. |
161 | */ |
162 | |
163 | /* Also note that comments started like this one will always work. */ |
164 | |
165 | char line_comment_chars[] = ""; |
166 | |
167 | /* Chars that can be used to separate mant from exp in floating point nums */ |
168 | char EXP_CHARS[] = "eE"; |
169 | |
170 | /* Chars that mean this number is a floating point constant, |
171 | * as in 0f12.456 or 0d1.2345e12 |
172 | */ |
173 | char FLT_CHARS[] = "fFdDtT"; |
174 | |
175 | |
176 | /* Table used by base assembler to relax addresses based on varying length |
177 | * instructions. The fields are: |
178 | * 1) most positive reach of this state, |
179 | * 2) most negative reach of this state, |
180 | * 3) how many bytes this mode will add to the size of the current frag |
181 | * 4) which index into the table to try if we can't fit into this one. |
182 | * |
183 | * For i80960, the only application is the (de-)optimization of cobr |
184 | * instructions into separate compare and branch instructions when a 13-bit |
185 | * displacement won't hack it. |
186 | */ |
187 | const relax_typeS |
188 | md_relax_table[] = { |
189 | {0, 0, 0,0}, /* State 0 => no more relaxation possible */ |
190 | {4088, -4096, 0,2}, /* State 1: conditional branch (cobr) */ |
191 | {0x800000-8,-0x800000,4,0}, /* State 2: compare (reg) & branch (ctrl) */ |
192 | }; |
193 | |
194 | |
195 | /* These are the machine dependent pseudo-ops. |
196 | * |
197 | * This table describes all the machine specific pseudo-ops the assembler |
198 | * has to support. The fields are: |
199 | * pseudo-op name without dot |
200 | * function to call to execute this pseudo-op |
201 | * integer arg to pass to the function |
202 | */ |
203 | #define S_LEAFPROC 1 |
204 | #define S_SYSPROC 2 |
205 | |
206 | const pseudo_typeS |
207 | md_pseudo_table[] = { |
208 | |
209 | { "bss", s_lcomm, 1 }, |
210 | { "extended", float_cons, 't' }, |
211 | { "leafproc", parse_po, S_LEAFPROC }, |
212 | { "sysproc", parse_po, S_SYSPROC }, |
213 | |
214 | { "word", cons, 4 }, |
215 | { "quad", big_cons, 16 }, |
216 | |
217 | { 0, 0, 0 } |
218 | }; |
219 | \f |
220 | /* Macros to extract info from an 'expressionS' structure 'e' */ |
221 | #define adds(e) e.X_add_symbol |
222 | #define subs(e) e.X_subtract_symbol |
223 | #define offs(e) e.X_add_number |
224 | #define segs(e) e.X_seg |
225 | |
226 | |
227 | /* Branch-prediction bits for CTRL/COBR format opcodes */ |
228 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */ |
229 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */ |
230 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */ |
231 | |
232 | |
233 | /* Some instruction opcodes that we need explicitly */ |
234 | #define BE 0x12000000 |
235 | #define BG 0x11000000 |
236 | #define BGE 0x13000000 |
237 | #define BL 0x14000000 |
238 | #define BLE 0x16000000 |
239 | #define BNE 0x15000000 |
240 | #define BNO 0x10000000 |
241 | #define BO 0x17000000 |
242 | #define CHKBIT 0x5a002700 |
243 | #define CMPI 0x5a002080 |
244 | #define CMPO 0x5a002000 |
245 | |
246 | #define B 0x08000000 |
247 | #define BAL 0x0b000000 |
248 | #define CALL 0x09000000 |
249 | #define CALLS 0x66003800 |
250 | #define RET 0x0a000000 |
251 | |
252 | |
253 | /* These masks are used to build up a set of MEMB mode bits. */ |
254 | #define A_BIT 0x0400 |
255 | #define I_BIT 0x0800 |
256 | #define MEMB_BIT 0x1000 |
257 | #define D_BIT 0x2000 |
258 | |
259 | |
260 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */ |
261 | #define MEMA_ABASE 0x2000 |
262 | |
263 | /* Info from which a MEMA or MEMB format instruction can be generated */ |
264 | typedef struct { |
265 | long opcode; /* (First) 32 bits of instruction */ |
266 | int disp; /* 0-(none), 12- or, 32-bit displacement needed */ |
267 | char *e; /* The expression in the source instruction from |
268 | * which the displacement should be determined |
269 | */ |
270 | } memS; |
271 | |
272 | |
273 | /* The two pieces of info we need to generate a register operand */ |
274 | struct regop { |
275 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */ |
276 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */ |
277 | int n; /* Register number or literal value */ |
278 | }; |
279 | |
280 | |
281 | /* Number and assembler mnemonic for all registers that can appear in operands */ |
282 | static struct { |
283 | char *reg_name; |
284 | int reg_num; |
285 | } regnames[] = { |
286 | { "pfp", 0 }, { "sp", 1 }, { "rip", 2 }, { "r3", 3 }, |
287 | { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, |
288 | { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, |
289 | { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 }, |
290 | { "g0", 16 }, { "g1", 17 }, { "g2", 18 }, { "g3", 19 }, |
291 | { "g4", 20 }, { "g5", 21 }, { "g6", 22 }, { "g7", 23 }, |
292 | { "g8", 24 }, { "g9", 25 }, { "g10", 26 }, { "g11", 27 }, |
293 | { "g12", 28 }, { "g13", 29 }, { "g14", 30 }, { "fp", 31 }, |
294 | |
295 | /* Numbers for special-function registers are for assembler internal |
296 | * use only: they are scaled back to range [0-31] for binary output. |
297 | */ |
298 | # define SF0 32 |
299 | |
300 | { "sf0", 32 }, { "sf1", 33 }, { "sf2", 34 }, { "sf3", 35 }, |
301 | { "sf4", 36 }, { "sf5", 37 }, { "sf6", 38 }, { "sf7", 39 }, |
302 | { "sf8", 40 }, { "sf9", 41 }, { "sf10",42 }, { "sf11",43 }, |
303 | { "sf12",44 }, { "sf13",45 }, { "sf14",46 }, { "sf15",47 }, |
304 | { "sf16",48 }, { "sf17",49 }, { "sf18",50 }, { "sf19",51 }, |
305 | { "sf20",52 }, { "sf21",53 }, { "sf22",54 }, { "sf23",55 }, |
306 | { "sf24",56 }, { "sf25",57 }, { "sf26",58 }, { "sf27",59 }, |
307 | { "sf28",60 }, { "sf29",61 }, { "sf30",62 }, { "sf31",63 }, |
308 | |
309 | /* Numbers for floating point registers are for assembler internal use |
310 | * only: they are scaled back to [0-3] for binary output. |
311 | */ |
312 | # define FP0 64 |
313 | |
314 | { "fp0", 64 }, { "fp1", 65 }, { "fp2", 66 }, { "fp3", 67 }, |
315 | |
316 | { NULL, 0 }, /* END OF LIST */ |
317 | }; |
318 | |
319 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) |
320 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) |
321 | #define IS_FP_REG(n) ((n) >= FP0) |
322 | |
323 | /* Number and assembler mnemonic for all registers that can appear as 'abase' |
324 | * (indirect addressing) registers. |
325 | */ |
326 | static struct { |
327 | char *areg_name; |
328 | int areg_num; |
329 | } aregs[] = { |
330 | { "(pfp)", 0 }, { "(sp)", 1 }, { "(rip)", 2 }, { "(r3)", 3 }, |
331 | { "(r4)", 4 }, { "(r5)", 5 }, { "(r6)", 6 }, { "(r7)", 7 }, |
332 | { "(r8)", 8 }, { "(r9)", 9 }, { "(r10)", 10 }, { "(r11)", 11 }, |
333 | { "(r12)", 12 }, { "(r13)", 13 }, { "(r14)", 14 }, { "(r15)", 15 }, |
334 | { "(g0)", 16 }, { "(g1)", 17 }, { "(g2)", 18 }, { "(g3)", 19 }, |
335 | { "(g4)", 20 }, { "(g5)", 21 }, { "(g6)", 22 }, { "(g7)", 23 }, |
336 | { "(g8)", 24 }, { "(g9)", 25 }, { "(g10)", 26 }, { "(g11)", 27 }, |
337 | { "(g12)", 28 }, { "(g13)", 29 }, { "(g14)", 30 }, { "(fp)", 31 }, |
338 | |
339 | # define IPREL 32 |
340 | /* for assembler internal use only: this number never appears in binary |
341 | * output. |
342 | */ |
343 | { "(ip)", IPREL }, |
344 | |
345 | { NULL, 0 }, /* END OF LIST */ |
346 | }; |
347 | |
348 | |
349 | /* Hash tables */ |
350 | static struct hash_control *op_hash = NULL; /* Opcode mnemonics */ |
351 | static struct hash_control *reg_hash = NULL; /* Register name hash table */ |
352 | static struct hash_control *areg_hash = NULL; /* Abase register hash table */ |
353 | |
354 | |
355 | /* Architecture for which we are assembling */ |
356 | #define ARCH_ANY 0 /* Default: no architecture checking done */ |
357 | #define ARCH_KA 1 |
358 | #define ARCH_KB 2 |
359 | #define ARCH_MC 3 |
360 | #define ARCH_CA 4 |
361 | int architecture = ARCH_ANY; /* Architecture requested on invocation line */ |
362 | int iclasses_seen = 0; /* OR of instruction classes (I_* constants) |
363 | * for which we've actually assembled |
364 | * instructions. |
365 | */ |
366 | |
367 | |
368 | /* BRANCH-PREDICTION INSTRUMENTATION |
369 | * |
370 | * The following supports generation of branch-prediction instrumentation |
371 | * (turned on by -b switch). The instrumentation collects counts |
372 | * of branches taken/not-taken for later input to a utility that will |
373 | * set the branch prediction bits of the instructions in accordance with |
374 | * the behavior observed. (Note that the KX series does not have |
375 | * brach-prediction.) |
376 | * |
377 | * The instrumentation consists of: |
378 | * |
379 | * (1) before and after each conditional branch, a call to an external |
380 | * routine that increments and steps over an inline counter. The |
381 | * counter itself, initialized to 0, immediately follows the call |
382 | * instruction. For each branch, the counter following the branch |
383 | * is the number of times the branch was not taken, and the difference |
384 | * between the counters is the number of times it was taken. An |
385 | * example of an instrumented conditional branch: |
386 | * |
387 | * call BR_CNT_FUNC |
388 | * .word 0 |
389 | * LBRANCH23: be label |
390 | * call BR_CNT_FUNC |
391 | * .word 0 |
392 | * |
393 | * (2) a table of pointers to the instrumented branches, so that an |
394 | * external postprocessing routine can locate all of the counters. |
395 | * the table begins with a 2-word header: a pointer to the next in |
396 | * a linked list of such tables (initialized to 0); and a count |
397 | * of the number of entries in the table (exclusive of the header. |
398 | * |
399 | * Note that input source code is expected to already contain calls |
400 | * an external routine that will link the branch local table into a |
401 | * list of such tables. |
402 | */ |
403 | |
404 | static int br_cnt = 0; /* Number of branches instrumented so far. |
405 | * Also used to generate unique local labels |
406 | * for each instrumented branch |
407 | */ |
408 | |
409 | #define BR_LABEL_BASE "LBRANCH" |
410 | /* Basename of local labels on instrumented |
411 | * branches, to avoid conflict with compiler- |
412 | * generated local labels. |
413 | */ |
414 | |
415 | #define BR_CNT_FUNC "__inc_branch" |
416 | /* Name of the external routine that will |
417 | * increment (and step over) an inline counter. |
418 | */ |
419 | |
420 | #define BR_TAB_NAME "__BRANCH_TABLE__" |
421 | /* Name of the table of pointers to branches. |
422 | * A local (i.e., non-external) symbol. |
423 | */ |
424 | \f |
425 | /***************************************************************************** |
426 | * md_begin: One-time initialization. |
427 | * |
428 | * Set up hash tables. |
429 | * |
430 | **************************************************************************** */ |
431 | void |
432 | md_begin() |
433 | { |
434 | int i; /* Loop counter */ |
435 | const struct i960_opcode *oP; /* Pointer into opcode table */ |
436 | char *retval; /* Value returned by hash functions */ |
437 | |
438 | if (((op_hash = hash_new()) == 0) |
439 | || ((reg_hash = hash_new()) == 0) |
440 | || ((areg_hash = hash_new()) == 0)) { |
441 | as_fatal("virtual memory exceeded"); |
442 | } |
443 | |
444 | retval = ""; /* For some reason, the base assembler uses an empty |
445 | * string for "no error message", instead of a NULL |
446 | * pointer. |
447 | */ |
448 | |
449 | for (oP=i960_opcodes; oP->name && !*retval; oP++) { |
450 | retval = hash_insert(op_hash, oP->name, oP); |
451 | } |
452 | |
453 | for (i=0; regnames[i].reg_name && !*retval; i++) { |
454 | retval = hash_insert(reg_hash, regnames[i].reg_name, |
455 | ®names[i].reg_num); |
456 | } |
457 | |
458 | for (i=0; aregs[i].areg_name && !*retval; i++){ |
459 | retval = hash_insert(areg_hash, aregs[i].areg_name, |
460 | &aregs[i].areg_num); |
461 | } |
462 | |
463 | if (*retval) { |
464 | as_fatal("Hashing returned \"%s\".", retval); |
465 | } |
466 | } /* md_begin() */ |
467 | |
468 | /***************************************************************************** |
469 | * md_end: One-time final cleanup |
470 | * |
471 | * None necessary |
472 | * |
473 | **************************************************************************** */ |
474 | void |
475 | md_end() |
476 | { |
477 | } |
478 | |
479 | /***************************************************************************** |
480 | * md_assemble: Assemble an instruction |
481 | * |
482 | * Assumptions about the passed-in text: |
483 | * - all comments, labels removed |
484 | * - text is an instruction |
485 | * - all white space compressed to single blanks |
486 | * - all character constants have been replaced with decimal |
487 | * |
488 | **************************************************************************** */ |
489 | void |
490 | md_assemble(textP) |
491 | char *textP; /* Source text of instruction */ |
492 | { |
493 | char *args[4]; /* Parsed instruction text, containing NO whitespace: |
494 | * arg[0]->opcode mnemonic |
495 | * arg[1-3]->operands, with char constants |
496 | * replaced by decimal numbers |
497 | */ |
498 | int n_ops; /* Number of instruction operands */ |
499 | |
500 | struct i960_opcode *oP; |
501 | /* Pointer to instruction description */ |
502 | int branch_predict; |
503 | /* TRUE iff opcode mnemonic included branch-prediction |
504 | * suffix (".f" or ".t") |
505 | */ |
506 | long bp_bits; /* Setting of branch-prediction bit(s) to be OR'd |
507 | * into instruction opcode of CTRL/COBR format |
508 | * instructions. |
509 | */ |
510 | int n; /* Offset of last character in opcode mnemonic */ |
511 | |
512 | static const char bp_error_msg[] = "branch prediction invalid on this opcode"; |
513 | |
514 | |
515 | /* Parse instruction into opcode and operands */ |
516 | bzero(args, sizeof(args)); |
517 | n_ops = i_scan(textP, args); |
518 | if (n_ops == -1){ |
519 | return; /* Error message already issued */ |
520 | } |
521 | |
522 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */ |
523 | if (!strcmp(args[0],"ldconst")){ |
524 | n_ops = parse_ldconst(args); |
525 | if (n_ops == -1){ |
526 | return; |
527 | } |
528 | } |
529 | |
530 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off */ |
531 | n = strlen(args[0]) - 1; |
532 | branch_predict = 0; |
533 | bp_bits = 0; |
534 | if (args[0][n-1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')){ |
535 | /* We could check here to see if the target architecture |
536 | * supports branch prediction, but why bother? The bit |
537 | * will just be ignored by processors that don't use it. |
538 | */ |
539 | branch_predict = 1; |
540 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; |
541 | args[0][n-1] = '\0'; /* Strip suffix from opcode mnemonic */ |
542 | } |
543 | |
544 | /* Look up opcode mnemonic in table and check number of operands. |
545 | * Check that opcode is legal for the target architecture. |
546 | * If all looks good, assemble instruction. |
547 | */ |
548 | oP = (struct i960_opcode *) hash_find(op_hash, args[0]); |
549 | if (!oP || !targ_has_iclass(oP->iclass)) { |
550 | as_bad("invalid opcode, \"%s\".", args[0]); |
551 | |
552 | } else if (n_ops != oP->num_ops) { |
553 | as_bad("improper number of operands. expecting %d, got %d", oP->num_ops, n_ops); |
554 | |
555 | } else { |
556 | switch (oP->format){ |
557 | case FBRA: |
558 | case CTRL: |
559 | ctrl_fmt(args[1], oP->opcode | bp_bits, oP->num_ops); |
560 | if (oP->format == FBRA){ |
561 | /* Now generate a 'bno' to same arg */ |
562 | ctrl_fmt(args[1], BNO | bp_bits, 1); |
563 | } |
564 | break; |
565 | case COBR: |
566 | case COJ: |
567 | cobr_fmt(args, oP->opcode | bp_bits, oP); |
568 | break; |
569 | case REG: |
570 | if (branch_predict){ |
571 | as_warn(bp_error_msg); |
572 | } |
573 | reg_fmt(args, oP); |
574 | break; |
575 | case MEM1: |
576 | case MEM2: |
577 | case MEM4: |
578 | case MEM8: |
579 | case MEM12: |
580 | case MEM16: |
581 | if (branch_predict){ |
582 | as_warn(bp_error_msg); |
583 | } |
584 | mem_fmt(args, oP); |
585 | break; |
586 | case CALLJ: |
587 | if (branch_predict){ |
588 | as_warn(bp_error_msg); |
589 | } |
590 | /* Output opcode & set up "fixup" (relocation); |
591 | * flag relocation as 'callj' type. |
592 | */ |
593 | know(oP->num_ops == 1); |
594 | get_cdisp(args[1], "CTRL", oP->opcode, 24, 0, 1); |
595 | break; |
596 | default: |
597 | BAD_CASE(oP->format); |
598 | break; |
599 | } |
600 | } |
601 | } /* md_assemble() */ |
602 | |
603 | /***************************************************************************** |
604 | * md_number_to_chars: convert a number to target byte order |
605 | * |
606 | **************************************************************************** */ |
607 | void |
608 | md_number_to_chars(buf, value, n) |
609 | char *buf; /* Put output here */ |
610 | long value; /* The integer to be converted */ |
611 | int n; /* Number of bytes to output (significant bytes |
612 | * in 'value') |
613 | */ |
614 | { |
615 | while (n--){ |
616 | *buf++ = value; |
617 | value >>= 8; |
618 | } |
619 | |
620 | /* XXX line number probably botched for this warning message. */ |
621 | if (value != 0 && value != -1){ |
622 | as_bad("Displacement too long for instruction field length."); |
623 | } |
624 | } /* md_number_to_chars() */ |
625 | |
626 | /***************************************************************************** |
627 | * md_chars_to_number: convert from target byte order to host byte order. |
628 | * |
629 | **************************************************************************** */ |
630 | int |
631 | md_chars_to_number(val, n) |
632 | unsigned char *val; /* Value in target byte order */ |
633 | int n; /* Number of bytes in the input */ |
634 | { |
635 | int retval; |
636 | |
637 | for (retval=0; n--;){ |
638 | retval <<= 8; |
639 | retval |= val[n]; |
640 | } |
641 | return retval; |
642 | } |
643 | |
644 | |
645 | #define MAX_LITTLENUMS 6 |
646 | #define LNUM_SIZE sizeof(LITTLENUM_TYPE) |
647 | |
648 | /***************************************************************************** |
649 | * md_atof: convert ascii to floating point |
650 | * |
651 | * Turn a string at input_line_pointer into a floating point constant of type |
652 | * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS |
653 | * emitted is returned at 'sizeP'. An error message is returned, or a pointer |
654 | * to an empty message if OK. |
655 | * |
656 | * Note we call the i386 floating point routine, rather than complicating |
657 | * things with more files or symbolic links. |
658 | * |
659 | **************************************************************************** */ |
660 | char * md_atof(type, litP, sizeP) |
661 | int type; |
662 | char *litP; |
663 | int *sizeP; |
664 | { |
665 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
666 | LITTLENUM_TYPE *wordP; |
667 | int prec; |
668 | char *t; |
669 | char *atof_ieee(); |
670 | |
671 | switch(type) { |
672 | case 'f': |
673 | case 'F': |
674 | prec = 2; |
675 | break; |
676 | |
677 | case 'd': |
678 | case 'D': |
679 | prec = 4; |
680 | break; |
681 | |
682 | case 't': |
683 | case 'T': |
684 | prec = 5; |
685 | type = 'x'; /* That's what atof_ieee() understands */ |
686 | break; |
687 | |
688 | default: |
689 | *sizeP=0; |
690 | return "Bad call to md_atof()"; |
691 | } |
692 | |
693 | t = atof_ieee(input_line_pointer, type, words); |
694 | if (t){ |
695 | input_line_pointer = t; |
696 | } |
697 | |
698 | *sizeP = prec * LNUM_SIZE; |
699 | |
700 | /* Output the LITTLENUMs in REVERSE order in accord with i80960 |
701 | * word-order. (Dunno why atof_ieee doesn't do it in the right |
702 | * order in the first place -- probably because it's a hack of |
703 | * atof_m68k.) |
704 | */ |
705 | |
706 | for(wordP = words + prec - 1; prec--;){ |
707 | md_number_to_chars(litP, (long) (*wordP--), LNUM_SIZE); |
708 | litP += sizeof(LITTLENUM_TYPE); |
709 | } |
710 | |
711 | return ""; /* Someone should teach Dean about null pointers */ |
712 | } |
713 | |
714 | |
715 | /***************************************************************************** |
716 | * md_number_to_imm |
717 | * |
718 | **************************************************************************** */ |
719 | void |
720 | md_number_to_imm(buf, val, n) |
721 | char *buf; |
722 | long val; |
723 | int n; |
724 | { |
725 | md_number_to_chars(buf, val, n); |
726 | } |
727 | |
728 | |
729 | /***************************************************************************** |
730 | * md_number_to_disp |
731 | * |
732 | **************************************************************************** */ |
733 | void |
734 | md_number_to_disp(buf, val, n) |
735 | char *buf; |
736 | long val; |
737 | int n; |
738 | { |
739 | md_number_to_chars(buf, val, n); |
740 | } |
741 | |
742 | /***************************************************************************** |
743 | * md_number_to_field: |
744 | * |
745 | * Stick a value (an address fixup) into a bit field of |
746 | * previously-generated instruction. |
747 | * |
748 | **************************************************************************** */ |
749 | void |
750 | md_number_to_field(instrP, val, bfixP) |
751 | char *instrP; /* Pointer to instruction to be fixed */ |
752 | long val; /* Address fixup value */ |
753 | bit_fixS *bfixP; /* Description of bit field to be fixed up */ |
754 | { |
755 | int numbits; /* Length of bit field to be fixed */ |
756 | long instr; /* 32-bit instruction to be fixed-up */ |
757 | long sign; /* 0 or -1, according to sign bit of 'val' */ |
758 | |
759 | /* Convert instruction back to host byte order |
760 | */ |
761 | instr = md_chars_to_number(instrP, 4); |
762 | |
763 | /* Surprise! -- we stored the number of bits |
764 | * to be modified rather than a pointer to a structure. |
765 | */ |
766 | numbits = (int)bfixP; |
767 | if (numbits == 1){ |
768 | /* This is a no-op, stuck here by reloc_callj() */ |
769 | return; |
770 | } |
771 | |
772 | know ((numbits==13) || (numbits==24)); |
773 | |
774 | /* Propagate sign bit of 'val' for the given number of bits. |
775 | * Result should be all 0 or all 1 |
776 | */ |
777 | sign = val >> ((int)numbits - 1); |
778 | if (((val < 0) && (sign != -1)) |
779 | || ((val > 0) && (sign != 0))){ |
780 | as_bad("Fixup of %d too large for field width of %d", |
781 | val, numbits); |
782 | } else { |
783 | /* Put bit field into instruction and write back in target |
784 | * byte order. |
785 | */ |
786 | val &= ~(-1 << (int)numbits); /* Clear unused sign bits */ |
787 | instr |= val; |
788 | md_number_to_chars(instrP, instr, 4); |
789 | } |
790 | } /* md_number_to_field() */ |
791 | |
792 | |
793 | /***************************************************************************** |
794 | * md_parse_option |
795 | * Invocation line includes a switch not recognized by the base assembler. |
796 | * See if it's a processor-specific option. For the 960, these are: |
797 | * |
798 | * -norelax: |
799 | * Conditional branch instructions that require displacements |
800 | * greater than 13 bits (or that have external targets) should |
801 | * generate errors. The default is to replace each such |
802 | * instruction with the corresponding compare (or chkbit) and |
803 | * branch instructions. Note that the Intel "j" cobr directives |
804 | * are ALWAYS "de-optimized" in this way when necessary, |
805 | * regardless of the setting of this option. |
806 | * |
807 | * -b: |
808 | * Add code to collect information about branches taken, for |
809 | * later optimization of branch prediction bits by a separate |
810 | * tool. COBR and CNTL format instructions have branch |
811 | * prediction bits (in the CX architecture); if "BR" represents |
812 | * an instruction in one of these classes, the following rep- |
813 | * resents the code generated by the assembler: |
814 | * |
815 | * call <increment routine> |
816 | * .word 0 # pre-counter |
817 | * Label: BR |
818 | * call <increment routine> |
819 | * .word 0 # post-counter |
820 | * |
821 | * A table of all such "Labels" is also generated. |
822 | * |
823 | * |
824 | * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: |
825 | * Select the 80960 architecture. Instructions or features not |
826 | * supported by the selected architecture cause fatal errors. |
827 | * The default is to generate code for any instruction or feature |
828 | * that is supported by SOME version of the 960 (even if this |
829 | * means mixing architectures!). |
830 | * |
831 | **************************************************************************** */ |
832 | int |
833 | md_parse_option(argP, cntP, vecP) |
834 | char **argP; |
835 | int *cntP; |
836 | char ***vecP; |
837 | { |
838 | char *p; |
839 | struct tabentry { char *flag; int arch; }; |
840 | static struct tabentry arch_tab[] = { |
841 | "KA", ARCH_KA, |
842 | "KB", ARCH_KB, |
843 | "SA", ARCH_KA, /* Synonym for KA */ |
844 | "SB", ARCH_KB, /* Synonym for KB */ |
845 | "KC", ARCH_MC, /* Synonym for MC */ |
846 | "MC", ARCH_MC, |
847 | "CA", ARCH_CA, |
848 | NULL, 0 |
849 | }; |
850 | struct tabentry *tp; |
851 | |
852 | if (!strcmp(*argP,"norelax")){ |
853 | norelax = 1; |
854 | |
855 | } else if (**argP == 'b'){ |
856 | instrument_branches = 1; |
857 | |
858 | } else if (**argP == 'A'){ |
859 | p = (*argP) + 1; |
860 | |
861 | for (tp = arch_tab; tp->flag != NULL; tp++){ |
862 | if (!strcmp(p,tp->flag)){ |
863 | break; |
864 | } |
865 | } |
866 | |
867 | if (tp->flag == NULL){ |
868 | as_bad("unknown architecture: %s", p); |
869 | } else { |
870 | architecture = tp->arch; |
871 | } |
872 | } else { |
873 | /* Unknown option */ |
874 | (*argP)++; |
875 | return 0; |
876 | } |
877 | **argP = '\0'; /* Done parsing this switch */ |
878 | return 1; |
879 | } |
880 | |
881 | /***************************************************************************** |
882 | * md_convert_frag: |
883 | * Called by base assembler after address relaxation is finished: modify |
884 | * variable fragments according to how much relaxation was done. |
885 | * |
886 | * If the fragment substate is still 1, a 13-bit displacement was enough |
887 | * to reach the symbol in question. Set up an address fixup, but otherwise |
888 | * leave the cobr instruction alone. |
889 | * |
890 | * If the fragment substate is 2, a 13-bit displacement was not enough. |
891 | * Replace the cobr with a two instructions (a compare and a branch). |
892 | * |
893 | **************************************************************************** */ |
894 | void |
895 | md_convert_frag(fragP) |
896 | fragS * fragP; |
897 | { |
898 | fixS *fixP; /* Structure describing needed address fix */ |
899 | |
900 | switch (fragP->fr_subtype){ |
901 | case 1: |
902 | /* LEAVE SINGLE COBR INSTRUCTION */ |
903 | fixP = fix_new(fragP, |
904 | fragP->fr_opcode-fragP->fr_literal, |
905 | 4, |
906 | fragP->fr_symbol, |
907 | 0, |
908 | fragP->fr_offset, |
909 | 1, |
910 | 0); |
911 | |
912 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */ |
913 | break; |
914 | case 2: |
915 | /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */ |
916 | relax_cobr(fragP); |
917 | break; |
918 | default: |
919 | BAD_CASE(fragP->fr_subtype); |
920 | break; |
921 | } |
922 | } |
923 | |
924 | /***************************************************************************** |
925 | * md_estimate_size_before_relax: How much does it look like *fragP will grow? |
926 | * |
927 | * Called by base assembler just before address relaxation. |
928 | * Return the amount by which the fragment will grow. |
929 | * |
930 | * Any symbol that is now undefined will not become defined; cobr's |
931 | * based on undefined symbols will have to be replaced with a compare |
932 | * instruction and a branch instruction, and the code fragment will grow |
933 | * by 4 bytes. |
934 | * |
935 | **************************************************************************** */ |
936 | int |
937 | md_estimate_size_before_relax(fragP, segment_type) |
938 | register fragS *fragP; |
939 | register segT segment_type; |
940 | { |
941 | /* If symbol is undefined in this segment, go to "relaxed" state |
942 | * (compare and branch instructions instead of cobr) right now. |
943 | */ |
944 | if (S_GET_SEGMENT(fragP->fr_symbol) != segment_type) { |
945 | relax_cobr(fragP); |
946 | return 4; |
947 | } |
948 | return 0; |
949 | } /* md_estimate_size_before_relax() */ |
950 | |
951 | |
952 | /***************************************************************************** |
953 | * md_ri_to_chars: |
954 | * This routine exists in order to overcome machine byte-order problems |
955 | * when dealing with bit-field entries in the relocation_info struct. |
956 | * |
957 | * But relocation info will be used on the host machine only (only |
958 | * executable code is actually downloaded to the i80960). Therefore, |
959 | * we leave it in host byte order. |
960 | * |
961 | **************************************************************************** */ |
962 | void md_ri_to_chars(the_bytes, ri) |
963 | char *the_bytes; |
964 | struct reloc_info_generic *ri; |
965 | { |
966 | struct relocation_info br; |
967 | |
968 | (void) bzero(&br, sizeof(br)); |
969 | |
970 | br.r_address = ri->r_address; |
971 | br.r_index = ri->r_index; |
972 | br.r_pcrel = ri->r_pcrel; |
973 | br.r_length = ri->r_length; |
974 | br.r_extern = ri->r_extern; |
975 | br.r_bsr = ri->r_bsr; |
976 | br.r_disp = ri->r_disp; |
977 | br.r_callj = ri->r_callj; |
978 | |
979 | *((struct relocation_info *) the_bytes) = br; |
980 | } /* md_ri_to_chars() */ |
981 | |
982 | |
983 | #ifndef WORKING_DOT_WORD |
984 | |
985 | int md_short_jump_size = 0; |
986 | int md_long_jump_size = 0; |
987 | |
988 | void md_create_short_jump(ptr, from_addr, to_addr, frag, to_symbol) |
989 | char *ptr; |
990 | long from_addr; |
991 | long to_addr; |
992 | fragS *frag; |
993 | symbolS *to_symbol; |
994 | { |
995 | abort(); |
996 | } |
997 | |
998 | void |
999 | md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol) |
1000 | char *ptr; |
1001 | long from_addr, to_addr; |
1002 | fragS *frag; |
1003 | symbolS *to_symbol; |
1004 | { |
1005 | abort(); |
1006 | } |
1007 | #endif |
1008 | \f |
1009 | /************************************************************* |
1010 | * * |
1011 | * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER * |
1012 | * * |
1013 | ************************************************************ */ |
1014 | |
1015 | |
1016 | |
1017 | /***************************************************************************** |
1018 | * brcnt_emit: Emit code to increment inline branch counter. |
1019 | * |
1020 | * See the comments above the declaration of 'br_cnt' for details on |
1021 | * branch-prediction instrumentation. |
1022 | **************************************************************************** */ |
1023 | static void |
1024 | brcnt_emit() |
1025 | { |
1026 | ctrl_fmt(BR_CNT_FUNC,CALL,1);/* Emit call to "increment" routine */ |
1027 | emit(0); /* Emit inline counter to be incremented */ |
1028 | } |
1029 | |
1030 | /***************************************************************************** |
1031 | * brlab_next: generate the next branch local label |
1032 | * |
1033 | * See the comments above the declaration of 'br_cnt' for details on |
1034 | * branch-prediction instrumentation. |
1035 | **************************************************************************** */ |
1036 | static char * |
1037 | brlab_next() |
1038 | { |
1039 | static char buf[20]; |
1040 | |
1041 | sprintf(buf, "%s%d", BR_LABEL_BASE, br_cnt++); |
1042 | return buf; |
1043 | } |
1044 | |
1045 | /***************************************************************************** |
1046 | * brtab_emit: generate the fetch-prediction branch table. |
1047 | * |
1048 | * See the comments above the declaration of 'br_cnt' for details on |
1049 | * branch-prediction instrumentation. |
1050 | * |
1051 | * The code emitted here would be functionally equivalent to the following |
1052 | * example assembler source. |
1053 | * |
1054 | * .data |
1055 | * .align 2 |
1056 | * BR_TAB_NAME: |
1057 | * .word 0 # link to next table |
1058 | * .word 3 # length of table |
1059 | * .word LBRANCH0 # 1st entry in table proper |
1060 | * .word LBRANCH1 |
1061 | * .word LBRANCH2 |
1062 | ***************************************************************************** */ |
1063 | void |
1064 | brtab_emit() |
1065 | { |
1066 | int i; |
1067 | char buf[20]; |
1068 | char *p; /* Where the binary was output to */ |
1069 | fixS *fixP; /*->description of deferred address fixup */ |
1070 | |
1071 | if (!instrument_branches){ |
1072 | return; |
1073 | } |
1074 | |
1075 | subseg_new(SEG_DATA,0); /* .data */ |
1076 | frag_align(2,0); /* .align 2 */ |
1077 | record_alignment(now_seg,2); |
1078 | colon(BR_TAB_NAME); /* BR_TAB_NAME: */ |
1079 | emit(0); /* .word 0 #link to next table */ |
1080 | emit(br_cnt); /* .word n #length of table */ |
1081 | |
1082 | for (i=0; i<br_cnt; i++){ |
1083 | sprintf(buf, "%s%d", BR_LABEL_BASE, i); |
1084 | p = emit(0); |
1085 | fixP = fix_new(frag_now, |
1086 | p - frag_now->fr_literal, |
1087 | 4, |
1088 | symbol_find(buf), |
1089 | 0, |
1090 | 0, |
1091 | 0, |
1092 | 0); |
1093 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ |
1094 | } |
1095 | } |
1096 | |
1097 | /***************************************************************************** |
1098 | * cobr_fmt: generate a COBR-format instruction |
1099 | * |
1100 | **************************************************************************** */ |
1101 | static |
1102 | void |
1103 | cobr_fmt(arg, opcode, oP) |
1104 | char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ |
1105 | long opcode; /* Opcode, with branch-prediction bits already set |
1106 | * if necessary. |
1107 | */ |
1108 | struct i960_opcode *oP; |
1109 | /*->description of instruction */ |
1110 | { |
1111 | long instr; /* 32-bit instruction */ |
1112 | struct regop regop; /* Description of register operand */ |
1113 | int n; /* Number of operands */ |
1114 | int var_frag; /* 1 if varying length code fragment should |
1115 | * be emitted; 0 if an address fix |
1116 | * should be emitted. |
1117 | */ |
1118 | |
1119 | instr = opcode; |
1120 | n = oP->num_ops; |
1121 | |
1122 | if (n >= 1) { |
1123 | /* First operand (if any) of a COBR is always a register |
1124 | * operand. Parse it. |
1125 | */ |
1126 | parse_regop(®op, arg[1], oP->operand[0]); |
1127 | instr |= (regop.n << 19) | (regop.mode << 13); |
1128 | } |
1129 | if (n >= 2) { |
1130 | /* Second operand (if any) of a COBR is always a register |
1131 | * operand. Parse it. |
1132 | */ |
1133 | parse_regop(®op, arg[2], oP->operand[1]); |
1134 | instr |= (regop.n << 14) | regop.special; |
1135 | } |
1136 | |
1137 | |
1138 | if (n < 3){ |
1139 | emit(instr); |
1140 | |
1141 | } else { |
1142 | if (instrument_branches){ |
1143 | brcnt_emit(); |
1144 | colon(brlab_next()); |
1145 | } |
1146 | |
1147 | /* A third operand to a COBR is always a displacement. |
1148 | * Parse it; if it's relaxable (a cobr "j" directive, or any |
1149 | * cobr other than bbs/bbc when the "-norelax" option is not in |
1150 | * use) set up a variable code fragment; otherwise set up an |
1151 | * address fix. |
1152 | */ |
1153 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ |
1154 | get_cdisp(arg[3], "COBR", instr, 13, var_frag, 0); |
1155 | |
1156 | if (instrument_branches){ |
1157 | brcnt_emit(); |
1158 | } |
1159 | } |
1160 | } /* cobr_fmt() */ |
1161 | |
1162 | |
1163 | /***************************************************************************** |
1164 | * ctrl_fmt: generate a CTRL-format instruction |
1165 | * |
1166 | **************************************************************************** */ |
1167 | static |
1168 | void |
1169 | ctrl_fmt(targP, opcode, num_ops) |
1170 | char *targP; /* Pointer to text of lone operand (if any) */ |
1171 | long opcode; /* Template of instruction */ |
1172 | int num_ops; /* Number of operands */ |
1173 | { |
1174 | int instrument; /* TRUE iff we should add instrumentation to track |
1175 | * how often the branch is taken |
1176 | */ |
1177 | |
1178 | |
1179 | if (num_ops == 0){ |
1180 | emit(opcode); /* Output opcode */ |
1181 | } else { |
1182 | |
1183 | instrument = instrument_branches && (opcode!=CALL) |
1184 | && (opcode!=B) && (opcode!=RET) && (opcode!=BAL); |
1185 | |
1186 | if (instrument){ |
1187 | brcnt_emit(); |
1188 | colon(brlab_next()); |
1189 | } |
1190 | |
1191 | /* The operand MUST be an ip-relative displacment. Parse it |
1192 | * and set up address fix for the instruction we just output. |
1193 | */ |
1194 | get_cdisp(targP, "CTRL", opcode, 24, 0, 0); |
1195 | |
1196 | if (instrument){ |
1197 | brcnt_emit(); |
1198 | } |
1199 | } |
1200 | |
1201 | } |
1202 | |
1203 | |
1204 | /***************************************************************************** |
1205 | * emit: output instruction binary |
1206 | * |
1207 | * Output instruction binary, in target byte order, 4 bytes at a time. |
1208 | * Return pointer to where it was placed. |
1209 | * |
1210 | **************************************************************************** */ |
1211 | static |
1212 | char * |
1213 | emit(instr) |
1214 | long instr; /* Word to be output, host byte order */ |
1215 | { |
1216 | char *toP; /* Where to output it */ |
1217 | |
1218 | toP = frag_more(4); /* Allocate storage */ |
1219 | md_number_to_chars(toP, instr, 4); /* Convert to target byte order */ |
1220 | return toP; |
1221 | } |
1222 | |
1223 | |
1224 | /***************************************************************************** |
1225 | * get_args: break individual arguments out of comma-separated list |
1226 | * |
1227 | * Input assumptions: |
1228 | * - all comments and labels have been removed |
1229 | * - all strings of whitespace have been collapsed to a single blank. |
1230 | * - all character constants ('x') have been replaced with decimal |
1231 | * |
1232 | * Output: |
1233 | * args[0] is untouched. args[1] points to first operand, etc. All args: |
1234 | * - are NULL-terminated |
1235 | * - contain no whitespace |
1236 | * |
1237 | * Return value: |
1238 | * Number of operands (0,1,2, or 3) or -1 on error. |
1239 | * |
1240 | **************************************************************************** */ |
1241 | static int get_args(p, args) |
1242 | register char *p; /* Pointer to comma-separated operands; MUCKED BY US */ |
1243 | char *args[]; /* Output arg: pointers to operands placed in args[1-3]. |
1244 | * MUST ACCOMMODATE 4 ENTRIES (args[0-3]). |
1245 | */ |
1246 | { |
1247 | register int n; /* Number of operands */ |
1248 | register char *to; |
1249 | /* char buf[4]; */ |
1250 | /* int len; */ |
1251 | |
1252 | |
1253 | /* Skip lead white space */ |
1254 | while (*p == ' '){ |
1255 | p++; |
1256 | } |
1257 | |
1258 | if (*p == '\0'){ |
1259 | return 0; |
1260 | } |
1261 | |
1262 | n = 1; |
1263 | args[1] = p; |
1264 | |
1265 | /* Squeze blanks out by moving non-blanks toward start of string. |
1266 | * Isolate operands, whenever comma is found. |
1267 | */ |
1268 | to = p; |
1269 | while (*p != '\0'){ |
1270 | |
1271 | if (*p == ' '){ |
1272 | p++; |
1273 | |
1274 | } else if (*p == ','){ |
1275 | |
1276 | /* Start of operand */ |
1277 | if (n == 3){ |
1278 | as_bad("too many operands"); |
1279 | return -1; |
1280 | } |
1281 | *to++ = '\0'; /* Terminate argument */ |
1282 | args[++n] = to; /* Start next argument */ |
1283 | p++; |
1284 | |
1285 | } else { |
1286 | *to++ = *p++; |
1287 | } |
1288 | } |
1289 | *to = '\0'; |
1290 | return n; |
1291 | } |
1292 | |
1293 | |
1294 | /***************************************************************************** |
1295 | * get_cdisp: handle displacement for a COBR or CTRL instruction. |
1296 | * |
1297 | * Parse displacement for a COBR or CTRL instruction. |
1298 | * |
1299 | * If successful, output the instruction opcode and set up for it, |
1300 | * depending on the arg 'var_frag', either: |
1301 | * o an address fixup to be done when all symbol values are known, or |
1302 | * o a varying length code fragment, with address fixup info. This |
1303 | * will be done for cobr instructions that may have to be relaxed |
1304 | * in to compare/branch instructions (8 bytes) if the final address |
1305 | * displacement is greater than 13 bits. |
1306 | * |
1307 | **************************************************************************** */ |
1308 | static |
1309 | void |
1310 | get_cdisp(dispP, ifmtP, instr, numbits, var_frag, callj) |
1311 | char *dispP; /*->displacement as specified in source instruction */ |
1312 | char *ifmtP; /*->"COBR" or "CTRL" (for use in error message) */ |
1313 | long instr; /* Instruction needing the displacement */ |
1314 | int numbits; /* # bits of displacement (13 for COBR, 24 for CTRL) */ |
1315 | int var_frag; /* 1 if varying length code fragment should be emitted; |
1316 | * 0 if an address fix should be emitted. |
1317 | */ |
1318 | int callj; /* 1 if callj relocation should be done; else 0 */ |
1319 | { |
1320 | expressionS e; /* Parsed expression */ |
1321 | fixS *fixP; /* Structure describing needed address fix */ |
1322 | char *outP; /* Where instruction binary is output to */ |
1323 | |
1324 | fixP = NULL; |
1325 | |
1326 | switch (parse_expr(dispP,&e)) { |
1327 | |
1328 | case SEG_GOOF: |
1329 | as_bad("expression syntax error"); |
1330 | break; |
1331 | |
1332 | case SEG_TEXT: |
1333 | case SEG_UNKNOWN: |
1334 | if (var_frag) { |
1335 | outP = frag_more(8); /* Allocate worst-case storage */ |
1336 | md_number_to_chars(outP, instr, 4); |
1337 | frag_variant(rs_machine_dependent, 4, 4, 1, |
1338 | adds(e), offs(e), outP, 0, 0); |
1339 | } else { |
1340 | /* Set up a new fix structure, so address can be updated |
1341 | * when all symbol values are known. |
1342 | */ |
1343 | outP = emit(instr); |
1344 | fixP = fix_new(frag_now, |
1345 | outP - frag_now->fr_literal, |
1346 | 4, |
1347 | adds(e), |
1348 | 0, |
1349 | offs(e), |
1350 | 1, |
1351 | 0); |
1352 | |
1353 | fixP->fx_callj = callj; |
1354 | |
1355 | /* We want to modify a bit field when the address is |
1356 | * known. But we don't need all the garbage in the |
1357 | * bit_fix structure. So we're going to lie and store |
1358 | * the number of bits affected instead of a pointer. |
1359 | */ |
1360 | fixP->fx_bit_fixP = (bit_fixS *) numbits; |
1361 | } |
1362 | break; |
1363 | |
1364 | case SEG_DATA: |
1365 | case SEG_BSS: |
1366 | as_bad("attempt to branch into different segment"); |
1367 | break; |
1368 | |
1369 | default: |
1370 | as_bad("target of %s instruction must be a label", ifmtP); |
1371 | break; |
1372 | } |
1373 | } |
1374 | |
1375 | |
1376 | /***************************************************************************** |
1377 | * get_ispec: parse a memory operand for an index specification |
1378 | * |
1379 | * Here, an "index specification" is taken to be anything surrounded |
1380 | * by square brackets and NOT followed by anything else. |
1381 | * |
1382 | * If it's found, detach it from the input string, remove the surrounding |
1383 | * square brackets, and return a pointer to it. Otherwise, return NULL. |
1384 | * |
1385 | **************************************************************************** */ |
1386 | static |
1387 | char * |
1388 | get_ispec(textP) |
1389 | char *textP; /*->memory operand from source instruction, no white space */ |
1390 | { |
1391 | char *start; /*->start of index specification */ |
1392 | char *end; /*->end of index specification */ |
1393 | |
1394 | /* Find opening square bracket, if any |
1395 | */ |
1396 | start = index(textP, '['); |
1397 | |
1398 | if (start != NULL){ |
1399 | |
1400 | /* Eliminate '[', detach from rest of operand */ |
1401 | *start++ = '\0'; |
1402 | |
1403 | end = index(start, ']'); |
1404 | |
1405 | if (end == NULL){ |
1406 | as_bad("unmatched '['"); |
1407 | |
1408 | } else { |
1409 | /* Eliminate ']' and make sure it was the last thing |
1410 | * in the string. |
1411 | */ |
1412 | *end = '\0'; |
1413 | if (*(end+1) != '\0'){ |
1414 | as_bad("garbage after index spec ignored"); |
1415 | } |
1416 | } |
1417 | } |
1418 | return start; |
1419 | } |
1420 | |
1421 | /***************************************************************************** |
1422 | * get_regnum: |
1423 | * |
1424 | * Look up a (suspected) register name in the register table and return the |
1425 | * associated register number (or -1 if not found). |
1426 | * |
1427 | **************************************************************************** */ |
1428 | static |
1429 | int |
1430 | get_regnum(regname) |
1431 | char *regname; /* Suspected register name */ |
1432 | { |
1433 | int *rP; |
1434 | |
1435 | rP = (int *) hash_find(reg_hash, regname); |
1436 | return (rP == NULL) ? -1 : *rP; |
1437 | } |
1438 | |
1439 | |
1440 | /***************************************************************************** |
1441 | * i_scan: perform lexical scan of ascii assembler instruction. |
1442 | * |
1443 | * Input assumptions: |
1444 | * - input string is an i80960 instruction (not a pseudo-op) |
1445 | * - all comments and labels have been removed |
1446 | * - all strings of whitespace have been collapsed to a single blank. |
1447 | * |
1448 | * Output: |
1449 | * args[0] points to opcode, other entries point to operands. All strings: |
1450 | * - are NULL-terminated |
1451 | * - contain no whitespace |
1452 | * - have character constants ('x') replaced with a decimal number |
1453 | * |
1454 | * Return value: |
1455 | * Number of operands (0,1,2, or 3) or -1 on error. |
1456 | * |
1457 | **************************************************************************** */ |
1458 | static int i_scan(iP, args) |
1459 | register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */ |
1460 | char *args[]; /* Output arg: pointers to opcode and operands placed |
1461 | * here. MUST ACCOMMODATE 4 ENTRIES. |
1462 | */ |
1463 | { |
1464 | |
1465 | /* Isolate opcode */ |
1466 | if (*(iP) == ' ') { |
1467 | iP++; |
1468 | } /* Skip lead space, if any */ |
1469 | args[0] = iP; |
1470 | for (; *iP != ' '; iP++) { |
1471 | if (*iP == '\0') { |
1472 | /* There are no operands */ |
1473 | if (args[0] == iP) { |
1474 | /* We never moved: there was no opcode either! */ |
1475 | as_bad("missing opcode"); |
1476 | return -1; |
1477 | } |
1478 | return 0; |
1479 | } |
1480 | } |
1481 | *iP++ = '\0'; /* Terminate opcode */ |
1482 | return(get_args(iP, args)); |
1483 | } /* i_scan() */ |
1484 | |
1485 | |
1486 | /***************************************************************************** |
1487 | * mem_fmt: generate a MEMA- or MEMB-format instruction |
1488 | * |
1489 | **************************************************************************** */ |
1490 | static void mem_fmt(args, oP) |
1491 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ |
1492 | struct i960_opcode *oP; /* Pointer to description of instruction */ |
1493 | { |
1494 | int i; /* Loop counter */ |
1495 | struct regop regop; /* Description of register operand */ |
1496 | char opdesc; /* Operand descriptor byte */ |
1497 | memS instr; /* Description of binary to be output */ |
1498 | char *outP; /* Where the binary was output to */ |
1499 | expressionS expr; /* Parsed expression */ |
1500 | fixS *fixP; /*->description of deferred address fixup */ |
1501 | |
1502 | bzero(&instr, sizeof(memS)); |
1503 | instr.opcode = oP->opcode; |
1504 | |
1505 | /* Process operands. */ |
1506 | for (i = 1; i <= oP->num_ops; i++){ |
1507 | opdesc = oP->operand[i-1]; |
1508 | |
1509 | if (MEMOP(opdesc)){ |
1510 | parse_memop(&instr, args[i], oP->format); |
1511 | } else { |
1512 | parse_regop(®op, args[i], opdesc); |
1513 | instr.opcode |= regop.n << 19; |
1514 | } |
1515 | } |
1516 | |
1517 | /* Output opcode */ |
1518 | outP = emit(instr.opcode); |
1519 | |
1520 | if (instr.disp == 0){ |
1521 | return; |
1522 | } |
1523 | |
1524 | /* Parse and process the displacement */ |
1525 | switch (parse_expr(instr.e,&expr)){ |
1526 | |
1527 | case SEG_GOOF: |
1528 | as_bad("expression syntax error"); |
1529 | break; |
1530 | |
1531 | case SEG_ABSOLUTE: |
1532 | if (instr.disp == 32){ |
1533 | (void) emit(offs(expr)); /* Output displacement */ |
1534 | } else { |
1535 | /* 12-bit displacement */ |
1536 | if (offs(expr) & ~0xfff){ |
1537 | /* Won't fit in 12 bits: convert already-output |
1538 | * instruction to MEMB format, output |
1539 | * displacement. |
1540 | */ |
1541 | mema_to_memb(outP); |
1542 | (void) emit(offs(expr)); |
1543 | } else { |
1544 | /* WILL fit in 12 bits: OR into opcode and |
1545 | * overwrite the binary we already put out |
1546 | */ |
1547 | instr.opcode |= offs(expr); |
1548 | md_number_to_chars(outP, instr.opcode, 4); |
1549 | } |
1550 | } |
1551 | break; |
1552 | |
1553 | case SEG_DIFFERENCE: |
1554 | case SEG_TEXT: |
1555 | case SEG_DATA: |
1556 | case SEG_BSS: |
1557 | case SEG_UNKNOWN: |
1558 | if (instr.disp == 12){ |
1559 | /* Displacement is dependent on a symbol, whose value |
1560 | * may change at link time. We HAVE to reserve 32 bits. |
1561 | * Convert already-output opcode to MEMB format. |
1562 | */ |
1563 | mema_to_memb(outP); |
1564 | } |
1565 | |
1566 | /* Output 0 displacement and set up address fixup for when |
1567 | * this symbol's value becomes known. |
1568 | */ |
1569 | outP = emit((long) 0); |
1570 | fixP = fix_new(frag_now, |
1571 | outP - frag_now->fr_literal, |
1572 | 4, |
1573 | adds(expr), |
1574 | subs(expr), |
1575 | offs(expr), |
1576 | 0, |
1577 | 0); |
1578 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ |
1579 | break; |
1580 | |
1581 | default: |
1582 | BAD_CASE(segs(expr)); |
1583 | break; |
1584 | } |
1585 | } /* memfmt() */ |
1586 | |
1587 | |
1588 | /***************************************************************************** |
1589 | * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. |
1590 | * |
1591 | * There are 2 possible MEMA formats: |
1592 | * - displacement only |
1593 | * - displacement + abase |
1594 | * |
1595 | * They are distinguished by the setting of the MEMA_ABASE bit. |
1596 | * |
1597 | **************************************************************************** */ |
1598 | static void mema_to_memb(opcodeP) |
1599 | char *opcodeP; /* Where to find the opcode, in target byte order */ |
1600 | { |
1601 | long opcode; /* Opcode in host byte order */ |
1602 | long mode; /* Mode bits for MEMB instruction */ |
1603 | |
1604 | opcode = md_chars_to_number(opcodeP, 4); |
1605 | know(!(opcode & MEMB_BIT)); |
1606 | |
1607 | mode = MEMB_BIT | D_BIT; |
1608 | if (opcode & MEMA_ABASE){ |
1609 | mode |= A_BIT; |
1610 | } |
1611 | |
1612 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */ |
1613 | opcode |= mode; /* Set MEMB mode bits */ |
1614 | |
1615 | md_number_to_chars(opcodeP, opcode, 4); |
1616 | } /* mema_to_memb() */ |
1617 | |
1618 | |
1619 | /***************************************************************************** |
1620 | * parse_expr: parse an expression |
1621 | * |
1622 | * Use base assembler's expression parser to parse an expression. |
1623 | * It, unfortunately, runs off a global which we have to save/restore |
1624 | * in order to make it work for us. |
1625 | * |
1626 | * An empty expression string is treated as an absolute 0. |
1627 | * |
1628 | * Return "segment" to which the expression evaluates. |
1629 | * Return SEG_GOOF regardless of expression evaluation if entire input |
1630 | * string is not consumed in the evaluation -- tolerate no dangling junk! |
1631 | * |
1632 | **************************************************************************** */ |
1633 | static |
1634 | segT |
1635 | parse_expr(textP, expP) |
1636 | char *textP; /* Text of expression to be parsed */ |
1637 | expressionS *expP; /* Where to put the results of parsing */ |
1638 | { |
1639 | char *save_in; /* Save global here */ |
1640 | segT seg; /* Segment to which expression evaluates */ |
1641 | symbolS *symP; |
1642 | |
1643 | know(textP); |
1644 | |
1645 | if (*textP == '\0') { |
1646 | /* Treat empty string as absolute 0 */ |
1647 | expP->X_add_symbol = expP->X_subtract_symbol = NULL; |
1648 | expP->X_add_number = 0; |
1649 | seg = expP->X_seg = SEG_ABSOLUTE; |
1650 | |
1651 | } else { |
1652 | save_in = input_line_pointer; /* Save global */ |
1653 | input_line_pointer = textP; /* Make parser work for us */ |
1654 | |
1655 | seg = expression(expP); |
1656 | if (input_line_pointer - textP != strlen(textP)) { |
1657 | /* Did not consume all of the input */ |
1658 | seg = SEG_GOOF; |
1659 | } |
1660 | symP = expP->X_add_symbol; |
1661 | if (symP && (hash_find(reg_hash, S_GET_NAME(symP)))) { |
1662 | /* Register name in an expression */ |
1663 | seg = SEG_GOOF; |
1664 | } |
1665 | |
1666 | input_line_pointer = save_in; /* Restore global */ |
1667 | } |
1668 | return seg; |
1669 | } |
1670 | |
1671 | |
1672 | /***************************************************************************** |
1673 | * parse_ldcont: |
1674 | * Parse and replace a 'ldconst' pseudo-instruction with an appropriate |
1675 | * i80960 instruction. |
1676 | * |
1677 | * Assumes the input consists of: |
1678 | * arg[0] opcode mnemonic ('ldconst') |
1679 | * arg[1] first operand (constant) |
1680 | * arg[2] name of register to be loaded |
1681 | * |
1682 | * Replaces opcode and/or operands as appropriate. |
1683 | * |
1684 | * Returns the new number of arguments, or -1 on failure. |
1685 | * |
1686 | **************************************************************************** */ |
1687 | static |
1688 | int |
1689 | parse_ldconst(arg) |
1690 | char *arg[]; /* See above */ |
1691 | { |
1692 | int n; /* Constant to be loaded */ |
1693 | int shift; /* Shift count for "shlo" instruction */ |
1694 | static char buf[5]; /* Literal for first operand */ |
1695 | static char buf2[5]; /* Literal for second operand */ |
1696 | expressionS e; /* Parsed expression */ |
1697 | |
1698 | |
1699 | arg[3] = NULL; /* So we can tell at the end if it got used or not */ |
1700 | |
1701 | switch(parse_expr(arg[1],&e)){ |
1702 | |
1703 | case SEG_TEXT: |
1704 | case SEG_DATA: |
1705 | case SEG_BSS: |
1706 | case SEG_UNKNOWN: |
1707 | case SEG_DIFFERENCE: |
1708 | /* We're dependent on one or more symbols -- use "lda" */ |
1709 | arg[0] = "lda"; |
1710 | break; |
1711 | |
1712 | case SEG_ABSOLUTE: |
1713 | /* Try the following mappings: |
1714 | * ldconst 0,<reg> ->mov 0,<reg> |
1715 | * ldconst 31,<reg> ->mov 31,<reg> |
1716 | * ldconst 32,<reg> ->addo 1,31,<reg> |
1717 | * ldconst 62,<reg> ->addo 31,31,<reg> |
1718 | * ldconst 64,<reg> ->shlo 8,3,<reg> |
1719 | * ldconst -1,<reg> ->subo 1,0,<reg> |
1720 | * ldconst -31,<reg>->subo 31,0,<reg> |
1721 | * |
1722 | * anthing else becomes: |
1723 | * lda xxx,<reg> |
1724 | */ |
1725 | n = offs(e); |
1726 | if ((0 <= n) && (n <= 31)){ |
1727 | arg[0] = "mov"; |
1728 | |
1729 | } else if ((-31 <= n) && (n <= -1)){ |
1730 | arg[0] = "subo"; |
1731 | arg[3] = arg[2]; |
1732 | sprintf(buf, "%d", -n); |
1733 | arg[1] = buf; |
1734 | arg[2] = "0"; |
1735 | |
1736 | } else if ((32 <= n) && (n <= 62)){ |
1737 | arg[0] = "addo"; |
1738 | arg[3] = arg[2]; |
1739 | arg[1] = "31"; |
1740 | sprintf(buf, "%d", n-31); |
1741 | arg[2] = buf; |
1742 | |
1743 | } else if ((shift = shift_ok(n)) != 0){ |
1744 | arg[0] = "shlo"; |
1745 | arg[3] = arg[2]; |
1746 | sprintf(buf, "%d", shift); |
1747 | arg[1] = buf; |
1748 | sprintf(buf2, "%d", n >> shift); |
1749 | arg[2] = buf2; |
1750 | |
1751 | } else { |
1752 | arg[0] = "lda"; |
1753 | } |
1754 | break; |
1755 | |
1756 | default: |
1757 | as_bad("invalid constant"); |
1758 | return -1; |
1759 | break; |
1760 | } |
1761 | return (arg[3] == 0) ? 2: 3; |
1762 | } |
1763 | |
1764 | /***************************************************************************** |
1765 | * parse_memop: parse a memory operand |
1766 | * |
1767 | * This routine is based on the observation that the 4 mode bits of the |
1768 | * MEMB format, taken individually, have fairly consistent meaning: |
1769 | * |
1770 | * M3 (bit 13): 1 if displacement is present (D_BIT) |
1771 | * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) |
1772 | * M1 (bit 11): 1 if index is present (I_BIT) |
1773 | * M0 (bit 10): 1 if abase is present (A_BIT) |
1774 | * |
1775 | * So we parse the memory operand and set bits in the mode as we find |
1776 | * things. Then at the end, if we go to MEMB format, we need only set |
1777 | * the MEMB bit (M2) and our mode is built for us. |
1778 | * |
1779 | * Unfortunately, I said "fairly consistent". The exceptions: |
1780 | * |
1781 | * DBIA |
1782 | * 0100 Would seem illegal, but means "abase-only". |
1783 | * |
1784 | * 0101 Would seem to mean "abase-only" -- it means IP-relative. |
1785 | * Must be converted to 0100. |
1786 | * |
1787 | * 0110 Would seem to mean "index-only", but is reserved. |
1788 | * We turn on the D bit and provide a 0 displacement. |
1789 | * |
1790 | * The other thing to observe is that we parse from the right, peeling |
1791 | * things * off as we go: first any index spec, then any abase, then |
1792 | * the displacement. |
1793 | * |
1794 | **************************************************************************** */ |
1795 | static |
1796 | void |
1797 | parse_memop(memP, argP, optype) |
1798 | memS *memP; /* Where to put the results */ |
1799 | char *argP; /* Text of the operand to be parsed */ |
1800 | int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */ |
1801 | { |
1802 | char *indexP; /* Pointer to index specification with "[]" removed */ |
1803 | char *p; /* Temp char pointer */ |
1804 | char iprel_flag;/* True if this is an IP-relative operand */ |
1805 | int regnum; /* Register number */ |
1806 | int scale; /* Scale factor: 1,2,4,8, or 16. Later converted |
1807 | * to internal format (0,1,2,3,4 respectively). |
1808 | */ |
1809 | int mode; /* MEMB mode bits */ |
1810 | int *intP; /* Pointer to register number */ |
1811 | |
1812 | /* The following table contains the default scale factors for each |
1813 | * type of memory instruction. It is accessed using (optype-MEM1) |
1814 | * as an index -- thus it assumes the 'optype' constants are assigned |
1815 | * consecutive values, in the order they appear in this table |
1816 | */ |
1817 | static int def_scale[] = { |
1818 | 1, /* MEM1 */ |
1819 | 2, /* MEM2 */ |
1820 | 4, /* MEM4 */ |
1821 | 8, /* MEM8 */ |
1822 | -1, /* MEM12 -- no valid default */ |
1823 | 16 /* MEM16 */ |
1824 | }; |
1825 | |
1826 | |
1827 | iprel_flag = mode = 0; |
1828 | |
1829 | /* Any index present? */ |
1830 | indexP = get_ispec(argP); |
1831 | if (indexP) { |
1832 | p = strchr(indexP, '*'); |
1833 | if (p == NULL) { |
1834 | /* No explicit scale -- use default for this |
1835 | *instruction type. |
1836 | */ |
1837 | scale = def_scale[ optype - MEM1 ]; |
1838 | } else { |
1839 | *p++ = '\0'; /* Eliminate '*' */ |
1840 | |
1841 | /* Now indexP->a '\0'-terminated register name, |
1842 | * and p->a scale factor. |
1843 | */ |
1844 | |
1845 | if (!strcmp(p,"16")){ |
1846 | scale = 16; |
1847 | } else if (strchr("1248",*p) && (p[1] == '\0')){ |
1848 | scale = *p - '0'; |
1849 | } else { |
1850 | scale = -1; |
1851 | } |
1852 | } |
1853 | |
1854 | regnum = get_regnum(indexP); /* Get index reg. # */ |
1855 | if (!IS_RG_REG(regnum)){ |
1856 | as_bad("invalid index register"); |
1857 | return; |
1858 | } |
1859 | |
1860 | /* Convert scale to its binary encoding */ |
1861 | switch (scale){ |
1862 | case 1: scale = 0 << 7; break; |
1863 | case 2: scale = 1 << 7; break; |
1864 | case 4: scale = 2 << 7; break; |
1865 | case 8: scale = 3 << 7; break; |
1866 | case 16: scale = 4 << 7; break; |
1867 | default: as_bad("invalid scale factor"); return; |
1868 | }; |
1869 | |
1870 | memP->opcode |= scale | regnum; /* Set index bits in opcode */ |
1871 | mode |= I_BIT; /* Found a valid index spec */ |
1872 | } |
1873 | |
1874 | /* Any abase (Register Indirect) specification present? */ |
1875 | if ((p = strrchr(argP,'(')) != NULL) { |
1876 | /* "(" is there -- does it start a legal abase spec? |
1877 | * (If not it could be part of a displacement expression.) |
1878 | */ |
1879 | intP = (int *) hash_find(areg_hash, p); |
1880 | if (intP != NULL){ |
1881 | /* Got an abase here */ |
1882 | regnum = *intP; |
1883 | *p = '\0'; /* discard register spec */ |
1884 | if (regnum == IPREL){ |
1885 | /* We have to specialcase ip-rel mode */ |
1886 | iprel_flag = 1; |
1887 | } else { |
1888 | memP->opcode |= regnum << 14; |
1889 | mode |= A_BIT; |
1890 | } |
1891 | } |
1892 | } |
1893 | |
1894 | /* Any expression present? */ |
1895 | memP->e = argP; |
1896 | if (*argP != '\0'){ |
1897 | mode |= D_BIT; |
1898 | } |
1899 | |
1900 | /* Special-case ip-relative addressing */ |
1901 | if (iprel_flag){ |
1902 | if (mode & I_BIT){ |
1903 | syntax(); |
1904 | } else { |
1905 | memP->opcode |= 5 << 10; /* IP-relative mode */ |
1906 | memP->disp = 32; |
1907 | } |
1908 | return; |
1909 | } |
1910 | |
1911 | /* Handle all other modes */ |
1912 | switch (mode){ |
1913 | case D_BIT | A_BIT: |
1914 | /* Go with MEMA instruction format for now (grow to MEMB later |
1915 | * if 12 bits is not enough for the displacement). |
1916 | * MEMA format has a single mode bit: set it to indicate |
1917 | * that abase is present. |
1918 | */ |
1919 | memP->opcode |= MEMA_ABASE; |
1920 | memP->disp = 12; |
1921 | break; |
1922 | |
1923 | case D_BIT: |
1924 | /* Go with MEMA instruction format for now (grow to MEMB later |
1925 | * if 12 bits is not enough for the displacement). |
1926 | */ |
1927 | memP->disp = 12; |
1928 | break; |
1929 | |
1930 | case A_BIT: |
1931 | /* For some reason, the bit string for this mode is not |
1932 | * consistent: it should be 0 (exclusive of the MEMB bit), |
1933 | * so we set it "by hand" here. |
1934 | */ |
1935 | memP->opcode |= MEMB_BIT; |
1936 | break; |
1937 | |
1938 | case A_BIT | I_BIT: |
1939 | /* set MEMB bit in mode, and OR in mode bits */ |
1940 | memP->opcode |= mode | MEMB_BIT; |
1941 | break; |
1942 | |
1943 | case I_BIT: |
1944 | /* Treat missing displacement as displacement of 0 */ |
1945 | mode |= D_BIT; |
1946 | /*********************** |
1947 | * Fall into next case * |
1948 | ********************** */ |
1949 | case D_BIT | A_BIT | I_BIT: |
1950 | case D_BIT | I_BIT: |
1951 | /* set MEMB bit in mode, and OR in mode bits */ |
1952 | memP->opcode |= mode | MEMB_BIT; |
1953 | memP->disp = 32; |
1954 | break; |
1955 | |
1956 | default: |
1957 | syntax(); |
1958 | break; |
1959 | } |
1960 | } |
1961 | |
1962 | /***************************************************************************** |
1963 | * parse_po: parse machine-dependent pseudo-op |
1964 | * |
1965 | * This is a top-level routine for machine-dependent pseudo-ops. It slurps |
1966 | * up the rest of the input line, breaks out the individual arguments, |
1967 | * and dispatches them to the correct handler. |
1968 | **************************************************************************** */ |
1969 | static |
1970 | void |
1971 | parse_po(po_num) |
1972 | int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */ |
1973 | { |
1974 | char *args[4]; /* Pointers operands, with no embedded whitespace. |
1975 | * arg[0] unused. |
1976 | * arg[1-3]->operands |
1977 | */ |
1978 | int n_ops; /* Number of operands */ |
1979 | char *p; /* Pointer to beginning of unparsed argument string */ |
1980 | char eol; /* Character that indicated end of line */ |
1981 | |
1982 | extern char is_end_of_line[]; |
1983 | |
1984 | /* Advance input pointer to end of line. */ |
1985 | p = input_line_pointer; |
1986 | while (!is_end_of_line[ *input_line_pointer ]){ |
1987 | input_line_pointer++; |
1988 | } |
1989 | eol = *input_line_pointer; /* Save end-of-line char */ |
1990 | *input_line_pointer = '\0'; /* Terminate argument list */ |
1991 | |
1992 | /* Parse out operands */ |
1993 | n_ops = get_args(p, args); |
1994 | if (n_ops == -1){ |
1995 | return; |
1996 | } |
1997 | |
1998 | /* Dispatch to correct handler */ |
1999 | switch(po_num){ |
2000 | case S_SYSPROC: s_sysproc(n_ops, args); break; |
2001 | case S_LEAFPROC: s_leafproc(n_ops, args); break; |
2002 | default: BAD_CASE(po_num); break; |
2003 | } |
2004 | |
2005 | /* Restore eol, so line numbers get updated correctly. Base assembler |
2006 | * assumes we leave input pointer pointing at char following the eol. |
2007 | */ |
2008 | *input_line_pointer++ = eol; |
2009 | } |
2010 | |
2011 | /***************************************************************************** |
2012 | * parse_regop: parse a register operand. |
2013 | * |
2014 | * In case of illegal operand, issue a message and return some valid |
2015 | * information so instruction processing can continue. |
2016 | **************************************************************************** */ |
2017 | static |
2018 | void |
2019 | parse_regop(regopP, optext, opdesc) |
2020 | struct regop *regopP; /* Where to put description of register operand */ |
2021 | char *optext; /* Text of operand */ |
2022 | char opdesc; /* Descriptor byte: what's legal for this operand */ |
2023 | { |
2024 | int n; /* Register number */ |
2025 | expressionS e; /* Parsed expression */ |
2026 | |
2027 | /* See if operand is a register */ |
2028 | n = get_regnum(optext); |
2029 | if (n >= 0){ |
2030 | if (IS_RG_REG(n)){ |
2031 | /* global or local register */ |
2032 | if (!REG_ALIGN(opdesc,n)){ |
2033 | as_bad("unaligned register"); |
2034 | } |
2035 | regopP->n = n; |
2036 | regopP->mode = 0; |
2037 | regopP->special = 0; |
2038 | return; |
2039 | } else if (IS_FP_REG(n) && FP_OK(opdesc)){ |
2040 | /* Floating point register, and it's allowed */ |
2041 | regopP->n = n - FP0; |
2042 | regopP->mode = 1; |
2043 | regopP->special = 0; |
2044 | return; |
2045 | } else if (IS_SF_REG(n) && SFR_OK(opdesc)){ |
2046 | /* Special-function register, and it's allowed */ |
2047 | regopP->n = n - SF0; |
2048 | regopP->mode = 0; |
2049 | regopP->special = 1; |
2050 | if (!targ_has_sfr(regopP->n)){ |
2051 | as_bad("no such sfr in this architecture"); |
2052 | } |
2053 | return; |
2054 | } |
2055 | } else if (LIT_OK(opdesc)){ |
2056 | /* |
2057 | * How about a literal? |
2058 | */ |
2059 | regopP->mode = 1; |
2060 | regopP->special = 0; |
2061 | if (FP_OK(opdesc)){ /* floating point literal acceptable */ |
2062 | /* Skip over 0f, 0d, or 0e prefix */ |
2063 | if ( (optext[0] == '0') |
2064 | && (optext[1] >= 'd') |
2065 | && (optext[1] <= 'f') ){ |
2066 | optext += 2; |
2067 | } |
2068 | |
2069 | if (!strcmp(optext,"0.0") || !strcmp(optext,"0") ){ |
2070 | regopP->n = 0x10; |
2071 | return; |
2072 | } |
2073 | if (!strcmp(optext,"1.0") || !strcmp(optext,"1") ){ |
2074 | regopP->n = 0x16; |
2075 | return; |
2076 | } |
2077 | |
2078 | } else { /* fixed point literal acceptable */ |
2079 | if ((parse_expr(optext,&e) != SEG_ABSOLUTE) |
2080 | || (offs(e) < 0) || (offs(e) > 31)){ |
2081 | as_bad("illegal literal"); |
2082 | offs(e) = 0; |
2083 | } |
2084 | regopP->n = offs(e); |
2085 | return; |
2086 | } |
2087 | } |
2088 | |
2089 | /* Nothing worked */ |
2090 | syntax(); |
2091 | regopP->mode = 0; /* Register r0 is always a good one */ |
2092 | regopP->n = 0; |
2093 | regopP->special = 0; |
2094 | } /* parse_regop() */ |
2095 | |
2096 | /***************************************************************************** |
2097 | * reg_fmt: generate a REG-format instruction |
2098 | * |
2099 | **************************************************************************** */ |
2100 | static void reg_fmt(args, oP) |
2101 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ |
2102 | struct i960_opcode *oP; /* Pointer to description of instruction */ |
2103 | { |
2104 | long instr; /* Binary to be output */ |
2105 | struct regop regop; /* Description of register operand */ |
2106 | int n_ops; /* Number of operands */ |
2107 | |
2108 | |
2109 | instr = oP->opcode; |
2110 | n_ops = oP->num_ops; |
2111 | |
2112 | if (n_ops >= 1){ |
2113 | parse_regop(®op, args[1], oP->operand[0]); |
2114 | |
2115 | if ((n_ops == 1) && !(instr & M3)){ |
2116 | /* 1-operand instruction in which the dst field should |
2117 | * be used (instead of src1). |
2118 | */ |
2119 | regop.n <<= 19; |
2120 | if (regop.special){ |
2121 | regop.mode = regop.special; |
2122 | } |
2123 | regop.mode <<= 13; |
2124 | regop.special = 0; |
2125 | } else { |
2126 | /* regop.n goes in bit 0, needs no shifting */ |
2127 | regop.mode <<= 11; |
2128 | regop.special <<= 5; |
2129 | } |
2130 | instr |= regop.n | regop.mode | regop.special; |
2131 | } |
2132 | |
2133 | if (n_ops >= 2) { |
2134 | parse_regop(®op, args[2], oP->operand[1]); |
2135 | |
2136 | if ((n_ops == 2) && !(instr & M3)){ |
2137 | /* 2-operand instruction in which the dst field should |
2138 | * be used instead of src2). |
2139 | */ |
2140 | regop.n <<= 19; |
2141 | if (regop.special){ |
2142 | regop.mode = regop.special; |
2143 | } |
2144 | regop.mode <<= 13; |
2145 | regop.special = 0; |
2146 | } else { |
2147 | regop.n <<= 14; |
2148 | regop.mode <<= 12; |
2149 | regop.special <<= 6; |
2150 | } |
2151 | instr |= regop.n | regop.mode | regop.special; |
2152 | } |
2153 | if (n_ops == 3){ |
2154 | parse_regop(®op, args[3], oP->operand[2]); |
2155 | if (regop.special){ |
2156 | regop.mode = regop.special; |
2157 | } |
2158 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); |
2159 | } |
2160 | emit(instr); |
2161 | } |
2162 | |
2163 | |
2164 | /***************************************************************************** |
2165 | * relax_cobr: |
2166 | * Replace cobr instruction in a code fragment with equivalent branch and |
2167 | * compare instructions, so it can reach beyond a 13-bit displacement. |
2168 | * Set up an address fix/relocation for the new branch instruction. |
2169 | * |
2170 | **************************************************************************** */ |
2171 | |
2172 | /* This "conditional jump" table maps cobr instructions into equivalent |
2173 | * compare and branch opcodes. |
2174 | */ |
2175 | static |
2176 | struct { |
2177 | long compare; |
2178 | long branch; |
2179 | } coj[] = { /* COBR OPCODE: */ |
2180 | CHKBIT, BNO, /* 0x30 - bbc */ |
2181 | CMPO, BG, /* 0x31 - cmpobg */ |
2182 | CMPO, BE, /* 0x32 - cmpobe */ |
2183 | CMPO, BGE, /* 0x33 - cmpobge */ |
2184 | CMPO, BL, /* 0x34 - cmpobl */ |
2185 | CMPO, BNE, /* 0x35 - cmpobne */ |
2186 | CMPO, BLE, /* 0x36 - cmpoble */ |
2187 | CHKBIT, BO, /* 0x37 - bbs */ |
2188 | CMPI, BNO, /* 0x38 - cmpibno */ |
2189 | CMPI, BG, /* 0x39 - cmpibg */ |
2190 | CMPI, BE, /* 0x3a - cmpibe */ |
2191 | CMPI, BGE, /* 0x3b - cmpibge */ |
2192 | CMPI, BL, /* 0x3c - cmpibl */ |
2193 | CMPI, BNE, /* 0x3d - cmpibne */ |
2194 | CMPI, BLE, /* 0x3e - cmpible */ |
2195 | CMPI, BO, /* 0x3f - cmpibo */ |
2196 | }; |
2197 | |
2198 | static |
2199 | void |
2200 | relax_cobr(fragP) |
2201 | register fragS *fragP; /* fragP->fr_opcode is assumed to point to |
2202 | * the cobr instruction, which comes at the |
2203 | * end of the code fragment. |
2204 | */ |
2205 | { |
2206 | int opcode, src1, src2, m1, s2; |
2207 | /* Bit fields from cobr instruction */ |
2208 | long bp_bits; /* Branch prediction bits from cobr instruction */ |
2209 | long instr; /* A single i960 instruction */ |
2210 | char *iP; /*->instruction to be replaced */ |
2211 | fixS *fixP; /* Relocation that can be done at assembly time */ |
2212 | |
2213 | /* PICK UP & PARSE COBR INSTRUCTION */ |
2214 | iP = fragP->fr_opcode; |
2215 | instr = md_chars_to_number(iP, 4); |
2216 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */ |
2217 | src1 = (instr >> 19) & 0x1f; |
2218 | m1 = (instr >> 13) & 1; |
2219 | s2 = instr & 1; |
2220 | src2 = (instr >> 14) & 0x1f; |
2221 | bp_bits= instr & BP_MASK; |
2222 | |
2223 | /* GENERATE AND OUTPUT COMPARE INSTRUCTION */ |
2224 | instr = coj[opcode].compare |
2225 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); |
2226 | md_number_to_chars(iP, instr, 4); |
2227 | |
2228 | /* OUTPUT BRANCH INSTRUCTION */ |
2229 | md_number_to_chars(iP+4, coj[opcode].branch | bp_bits, 4); |
2230 | |
2231 | /* SET UP ADDRESS FIXUP/RELOCATION */ |
2232 | fixP = fix_new(fragP, |
2233 | iP+4 - fragP->fr_literal, |
2234 | 4, |
2235 | fragP->fr_symbol, |
2236 | 0, |
2237 | fragP->fr_offset, |
2238 | 1, |
2239 | 0); |
2240 | |
2241 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */ |
2242 | |
2243 | fragP->fr_fix += 4; |
2244 | frag_wane(fragP); |
2245 | } |
2246 | |
2247 | |
2248 | /***************************************************************************** |
2249 | * reloc_callj: Relocate a 'callj' instruction |
2250 | * |
2251 | * This is a "non-(GNU)-standard" machine-dependent hook. The base |
2252 | * assembler calls it when it decides it can relocate an address at |
2253 | * assembly time instead of emitting a relocation directive. |
2254 | * |
2255 | * Check to see if the relocation involves a 'callj' instruction to a: |
2256 | * sysproc: Replace the default 'call' instruction with a 'calls' |
2257 | * leafproc: Replace the default 'call' instruction with a 'bal'. |
2258 | * other proc: Do nothing. |
2259 | * |
2260 | * See b.out.h for details on the 'n_other' field in a symbol structure. |
2261 | * |
2262 | * IMPORTANT!: |
2263 | * Assumes the caller has already figured out, in the case of a leafproc, |
2264 | * to use the 'bal' entry point, and has substituted that symbol into the |
2265 | * passed fixup structure. |
2266 | * |
2267 | **************************************************************************** */ |
2268 | void reloc_callj(fixP) |
2269 | fixS *fixP; /* Relocation that can be done at assembly time */ |
2270 | { |
2271 | char *where; /*->the binary for the instruction being relocated */ |
2272 | |
2273 | if (!fixP->fx_callj) { |
2274 | return; |
2275 | } /* This wasn't a callj instruction in the first place */ |
2276 | |
2277 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
2278 | |
2279 | if (TC_S_IS_SYSPROC(fixP->fx_addsy)) { |
2280 | /* Symbol is a .sysproc: replace 'call' with 'calls'. |
2281 | * System procedure number is (other-1). |
2282 | */ |
2283 | md_number_to_chars(where, CALLS|TC_S_GET_SYSPROC(fixP->fx_addsy), 4); |
2284 | |
2285 | /* Nothing else needs to be done for this instruction. |
2286 | * Make sure 'md_number_to_field()' will perform a no-op. |
2287 | */ |
2288 | fixP->fx_bit_fixP = (bit_fixS *) 1; |
2289 | |
2290 | } else if (TC_S_IS_CALLNAME(fixP->fx_addsy)) { |
2291 | /* Should not happen: see block comment above */ |
2292 | as_fatal("Trying to 'bal' to %s", S_GET_NAME(fixP->fx_addsy)); |
2293 | |
2294 | } else if (TC_S_IS_BALNAME(fixP->fx_addsy)) { |
2295 | /* Replace 'call' with 'bal'; both instructions have |
2296 | * the same format, so calling code should complete |
2297 | * relocation as if nothing happened here. |
2298 | */ |
2299 | md_number_to_chars(where, BAL, 4); |
2300 | } else if (TC_S_IS_BADPROC(fixP->fx_addsy)) { |
2301 | as_bad("Looks like a proc, but can't tell what kind.\n"); |
2302 | } /* switch on proc type */ |
2303 | |
2304 | /* else Symbol is neither a sysproc nor a leafproc */ |
2305 | |
2306 | return; |
2307 | } /* reloc_callj() */ |
2308 | |
2309 | |
2310 | /***************************************************************************** |
2311 | * s_leafproc: process .leafproc pseudo-op |
2312 | * |
2313 | * .leafproc takes two arguments, the second one is optional: |
2314 | * arg[1]: name of 'call' entry point to leaf procedure |
2315 | * arg[2]: name of 'bal' entry point to leaf procedure |
2316 | * |
2317 | * If the two arguments are identical, or if the second one is missing, |
2318 | * the first argument is taken to be the 'bal' entry point. |
2319 | * |
2320 | * If there are 2 distinct arguments, we must make sure that the 'bal' |
2321 | * entry point immediately follows the 'call' entry point in the linked |
2322 | * list of symbols. |
2323 | * |
2324 | **************************************************************************** */ |
2325 | static void s_leafproc(n_ops, args) |
2326 | int n_ops; /* Number of operands */ |
2327 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ |
2328 | { |
2329 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */ |
2330 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */ |
2331 | |
2332 | if ((n_ops != 1) && (n_ops != 2)) { |
2333 | as_bad("should have 1 or 2 operands"); |
2334 | return; |
2335 | } /* Check number of arguments */ |
2336 | |
2337 | /* Find or create symbol for 'call' entry point. */ |
2338 | callP = symbol_find_or_make(args[1]); |
2339 | |
2340 | if (TC_S_IS_CALLNAME(callP)) { |
2341 | as_warn("Redefining leafproc %s", S_GET_NAME(callP)); |
2342 | } /* is leafproc */ |
2343 | |
2344 | /* If that was the only argument, use it as the 'bal' entry point. |
2345 | * Otherwise, mark it as the 'call' entry point and find or create |
2346 | * another symbol for the 'bal' entry point. |
2347 | */ |
2348 | if ((n_ops == 1) || !strcmp(args[1],args[2])) { |
2349 | TC_S_FORCE_TO_BALNAME(callP); |
2350 | |
2351 | } else { |
2352 | TC_S_FORCE_TO_CALLNAME(callP); |
2353 | |
2354 | balP = symbol_find_or_make(args[2]); |
2355 | if (TC_S_IS_CALLNAME(balP)) { |
2356 | as_warn("Redefining leafproc %s", S_GET_NAME(balP)); |
2357 | } |
2358 | TC_S_FORCE_TO_BALNAME(balP); |
2359 | |
2360 | tc_set_bal_of_call(callP, balP); |
2361 | } /* if only one arg, or the args are the same */ |
2362 | |
2363 | return; |
2364 | } /* s_leafproc() */ |
2365 | |
2366 | |
2367 | /* |
2368 | * s_sysproc: process .sysproc pseudo-op |
2369 | * |
2370 | * .sysproc takes two arguments: |
2371 | * arg[1]: name of entry point to system procedure |
2372 | * arg[2]: 'entry_num' (index) of system procedure in the range |
2373 | * [0,31] inclusive. |
2374 | * |
2375 | * For [ab].out, we store the 'entrynum' in the 'n_other' field of |
2376 | * the symbol. Since that entry is normally 0, we bias 'entrynum' |
2377 | * by adding 1 to it. It must be unbiased before it is used. |
2378 | */ |
2379 | static void s_sysproc(n_ops, args) |
2380 | int n_ops; /* Number of operands */ |
2381 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ |
2382 | { |
2383 | expressionS exp; |
2384 | symbolS *symP; |
2385 | |
2386 | if (n_ops != 2) { |
2387 | as_bad("should have two operands"); |
2388 | return; |
2389 | } /* bad arg count */ |
2390 | |
2391 | /* Parse "entry_num" argument and check it for validity. */ |
2392 | if ((parse_expr(args[2],&exp) != SEG_ABSOLUTE) |
2393 | || (offs(exp) < 0) |
2394 | || (offs(exp) > 31)) { |
2395 | as_bad("'entry_num' must be absolute number in [0,31]"); |
2396 | return; |
2397 | } |
2398 | |
2399 | /* Find/make symbol and stick entry number (biased by +1) into it */ |
2400 | symP = symbol_find_or_make(args[1]); |
2401 | |
2402 | if (TC_S_IS_SYSPROC(symP)) { |
2403 | as_warn("Redefining entrynum for sysproc %s", S_GET_NAME(symP)); |
2404 | } /* redefining */ |
2405 | |
2406 | TC_S_SET_SYSPROC(symP, offs(exp)); /* encode entry number */ |
2407 | TC_S_FORCE_TO_SYSPROC(symP); |
2408 | |
2409 | return; |
2410 | } /* s_sysproc() */ |
2411 | |
2412 | |
2413 | /***************************************************************************** |
2414 | * shift_ok: |
2415 | * Determine if a "shlo" instruction can be used to implement a "ldconst". |
2416 | * This means that some number X < 32 can be shifted left to produce the |
2417 | * constant of interest. |
2418 | * |
2419 | * Return the shift count, or 0 if we can't do it. |
2420 | * Caller calculates X by shifting original constant right 'shift' places. |
2421 | * |
2422 | **************************************************************************** */ |
2423 | static |
2424 | int |
2425 | shift_ok(n) |
2426 | int n; /* The constant of interest */ |
2427 | { |
2428 | int shift; /* The shift count */ |
2429 | |
2430 | if (n <= 0){ |
2431 | /* Can't do it for negative numbers */ |
2432 | return 0; |
2433 | } |
2434 | |
2435 | /* Shift 'n' right until a 1 is about to be lost */ |
2436 | for (shift = 0; (n & 1) == 0; shift++){ |
2437 | n >>= 1; |
2438 | } |
2439 | |
2440 | if (n >= 32){ |
2441 | return 0; |
2442 | } |
2443 | return shift; |
2444 | } |
2445 | |
2446 | |
2447 | /***************************************************************************** |
2448 | * syntax: issue syntax error |
2449 | * |
2450 | **************************************************************************** */ |
2451 | static void syntax() { |
2452 | as_bad("syntax error"); |
2453 | } /* syntax() */ |
2454 | |
2455 | |
2456 | /***************************************************************************** |
2457 | * targ_has_sfr: |
2458 | * Return TRUE iff the target architecture supports the specified |
2459 | * special-function register (sfr). |
2460 | * |
2461 | **************************************************************************** */ |
2462 | static |
2463 | int |
2464 | targ_has_sfr(n) |
2465 | int n; /* Number (0-31) of sfr */ |
2466 | { |
2467 | switch (architecture){ |
2468 | case ARCH_KA: |
2469 | case ARCH_KB: |
2470 | case ARCH_MC: |
2471 | return 0; |
2472 | case ARCH_CA: |
2473 | default: |
2474 | return ((0<=n) && (n<=2)); |
2475 | } |
2476 | } |
2477 | |
2478 | |
2479 | /***************************************************************************** |
2480 | * targ_has_iclass: |
2481 | * Return TRUE iff the target architecture supports the indicated |
2482 | * class of instructions. |
2483 | * |
2484 | **************************************************************************** */ |
2485 | static |
2486 | int |
2487 | targ_has_iclass(ic) |
2488 | int ic; /* Instruction class; one of: |
2489 | * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM |
2490 | */ |
2491 | { |
2492 | iclasses_seen |= ic; |
2493 | switch (architecture){ |
2494 | case ARCH_KA: return ic & (I_BASE | I_KX); |
2495 | case ARCH_KB: return ic & (I_BASE | I_KX | I_FP | I_DEC); |
2496 | case ARCH_MC: return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); |
2497 | case ARCH_CA: return ic & (I_BASE | I_CX | I_CASIM); |
2498 | default: |
2499 | if ((iclasses_seen & (I_KX|I_FP|I_DEC|I_MIL)) |
2500 | && (iclasses_seen & I_CX)){ |
2501 | as_warn("architecture of opcode conflicts with that of earlier instruction(s)"); |
2502 | iclasses_seen &= ~ic; |
2503 | } |
2504 | return 1; |
2505 | } |
2506 | } |
2507 | |
2508 | |
2509 | /* Parse an operand that is machine-specific. |
2510 | We just return without modifying the expression if we have nothing |
2511 | to do. */ |
2512 | |
2513 | /* ARGSUSED */ |
2514 | void |
2515 | md_operand (expressionP) |
2516 | expressionS *expressionP; |
2517 | { |
2518 | } |
2519 | |
2520 | /* We have no need to default values of symbols. */ |
2521 | |
2522 | /* ARGSUSED */ |
2523 | symbolS *md_undefined_symbol(name) |
2524 | char *name; |
2525 | { |
2526 | return 0; |
2527 | } /* md_undefined_symbol() */ |
2528 | |
2529 | /* Exactly what point is a PC-relative offset relative TO? |
2530 | On the i960, they're relative to the address of the instruction, |
2531 | which we have set up as the address of the fixup too. */ |
2532 | long |
2533 | md_pcrel_from (fixP) |
2534 | fixS *fixP; |
2535 | { |
2536 | return fixP->fx_where + fixP->fx_frag->fr_address; |
2537 | } |
2538 | |
2539 | void |
2540 | md_apply_fix(fixP, val) |
2541 | fixS *fixP; |
2542 | long val; |
2543 | { |
2544 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; |
2545 | |
2546 | if (!fixP->fx_bit_fixP) { |
2547 | |
2548 | switch (fixP->fx_im_disp) { |
2549 | case 0: |
2550 | fixP->fx_addnumber = val; |
2551 | md_number_to_imm(place, val, fixP->fx_size, fixP); |
2552 | break; |
2553 | case 1: |
2554 | md_number_to_disp(place, |
2555 | fixP->fx_pcrel ? val + fixP->fx_pcrel_adjust : val, |
2556 | fixP->fx_size); |
2557 | break; |
2558 | case 2: /* fix requested for .long .word etc */ |
2559 | md_number_to_chars(place, val, fixP->fx_size); |
2560 | break; |
2561 | default: |
2562 | as_fatal("Internal error in md_apply_fix() in file \"%s\"", __FILE__); |
2563 | } /* OVE: maybe one ought to put _imm _disp _chars in one md-func */ |
2564 | } else { |
2565 | md_number_to_field(place, val, fixP->fx_bit_fixP); |
2566 | } |
2567 | |
2568 | return; |
2569 | } /* md_apply_fix() */ |
2570 | |
2571 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) |
2572 | /* |
2573 | * emit_relocations() |
2574 | * |
2575 | * Crawl along a fixS chain. Emit the segment's relocations. |
2576 | */ |
2577 | static void |
2578 | emit_machine_reloc (fixP, segment_address_in_file) |
2579 | register fixS * fixP; /* Fixup chain for this segment. */ |
2580 | relax_addressT segment_address_in_file; |
2581 | { |
2582 | struct reloc_info_generic ri; |
2583 | register symbolS * symbolP; |
2584 | |
2585 | /* JF this is for paranoia */ |
2586 | bzero((char *)&ri,sizeof(ri)); |
2587 | for (; fixP; fixP = fixP->fx_next) |
2588 | { |
2589 | if ((symbolP = fixP->fx_addsy) != 0) |
2590 | { |
2591 | /* These two 'cuz of NS32K */ |
2592 | ri . r_bsr = fixP->fx_bsr; |
2593 | ri . r_disp = fixP->fx_im_disp; |
2594 | |
2595 | ri . r_callj = fixP->fx_callj; |
2596 | |
2597 | ri . r_length = nbytes_r_length [fixP->fx_size]; |
2598 | ri . r_pcrel = fixP->fx_pcrel; |
2599 | ri . r_address = fixP->fx_frag->fr_address |
2600 | + fixP->fx_where |
2601 | - segment_address_in_file; |
2602 | if (!S_IS_DEFINED(symbolP)) |
2603 | { |
2604 | ri . r_extern = 1; |
2605 | ri . r_symbolnum = symbolP->sy_number; |
2606 | } |
2607 | else |
2608 | { |
2609 | ri . r_extern = 0; |
2610 | ri . r_symbolnum = S_GET_TYPE(symbolP); |
2611 | } |
2612 | |
2613 | /* Output the relocation information in machine-dependent form. */ |
2614 | md_ri_to_chars(next_object_file_charP, &ri); |
2615 | next_object_file_charP += sizeof(struct relocation_info); |
2616 | } |
2617 | } |
2618 | |
2619 | } /* emit_machine_reloc() */ |
2620 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
2621 | |
2622 | /* Align an address by rounding it up to the specified boundary. |
2623 | */ |
2624 | long md_section_align(seg, addr) |
2625 | segT seg; |
2626 | long addr; /* Address to be rounded up */ |
2627 | { |
2628 | return((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg])); |
2629 | } /* md_section_align() */ |
2630 | |
2631 | #ifdef OBJ_COFF |
2632 | void tc_headers_hook(headers) |
2633 | object_headers *headers; |
2634 | { |
2635 | unsigned short arch_flag = 0; |
2636 | |
2637 | if (iclasses_seen == I_BASE){ |
2638 | headers->filehdr.f_flags |= F_I960CORE; |
2639 | } else if (iclasses_seen & I_CX){ |
2640 | headers->filehdr.f_flags |= F_I960CA; |
2641 | } else if (iclasses_seen & I_MIL){ |
2642 | headers->filehdr.f_flags |= F_I960MC; |
2643 | } else if (iclasses_seen & (I_DEC|I_FP)){ |
2644 | headers->filehdr.f_flags |= F_I960KB; |
2645 | } else { |
2646 | headers->filehdr.f_flags |= F_I960KA; |
2647 | } /* set arch flag */ |
2648 | |
2649 | if (flagseen['R']) { |
2650 | headers->filehdr.f_magic = I960RWMAGIC; |
2651 | headers->aouthdr.magic = OMAGIC; |
2652 | } else { |
2653 | headers->filehdr.f_magic = I960ROMAGIC; |
2654 | headers->aouthdr.magic = NMAGIC; |
2655 | } /* set magic numbers */ |
2656 | |
2657 | return; |
2658 | } /* tc_headers_hook() */ |
2659 | #endif /* OBJ_COFF */ |
2660 | |
2661 | /* |
2662 | * Things going on here: |
2663 | * |
2664 | * For bout, We need to assure a couple of simplifying |
2665 | * assumptions about leafprocs for the linker: the leafproc |
2666 | * entry symbols will be defined in the same assembly in |
2667 | * which they're declared with the '.leafproc' directive; |
2668 | * and if a leafproc has both 'call' and 'bal' entry points |
2669 | * they are both global or both local. |
2670 | * |
2671 | * For coff, the call symbol has a second aux entry that |
2672 | * contains the bal entry point. The bal symbol becomes a |
2673 | * label. |
2674 | * |
2675 | * For coff representation, the call symbol has a second aux entry that |
2676 | * contains the bal entry point. The bal symbol becomes a label. |
2677 | * |
2678 | */ |
2679 | |
2680 | void tc_crawl_symbol_chain(headers) |
2681 | object_headers *headers; |
2682 | { |
2683 | symbolS *symbolP; |
2684 | |
2685 | for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next(symbolP)) { |
2686 | #ifdef OBJ_COFF |
2687 | if (TC_S_IS_SYSPROC(symbolP)) { |
2688 | /* second aux entry already contains the sysproc number */ |
2689 | S_SET_NUMBER_AUXILIARY(symbolP, 2); |
2690 | S_SET_STORAGE_CLASS(symbolP, C_SCALL); |
2691 | S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT)); |
2692 | continue; |
2693 | } /* rewrite sysproc */ |
2694 | #endif /* OBJ_COFF */ |
2695 | |
2696 | if (!TC_S_IS_BALNAME(symbolP) && !TC_S_IS_CALLNAME(symbolP)) { |
2697 | continue; |
2698 | } /* Not a leafproc symbol */ |
2699 | |
2700 | if (!S_IS_DEFINED(symbolP)) { |
2701 | as_bad("leafproc symbol '%s' undefined", S_GET_NAME(symbolP)); |
2702 | } /* undefined leaf */ |
2703 | |
2704 | if (TC_S_IS_CALLNAME(symbolP)) { |
2705 | symbolS *balP = tc_get_bal_of_call(symbolP); |
2706 | if (S_IS_EXTERNAL(symbolP) != S_IS_EXTERNAL(balP)) { |
2707 | S_SET_EXTERNAL(symbolP); |
2708 | S_SET_EXTERNAL(balP); |
2709 | as_warn("Warning: making leafproc entries %s and %s both global\n", |
2710 | S_GET_NAME(symbolP), S_GET_NAME(balP)); |
2711 | } /* externality mismatch */ |
2712 | } /* if callname */ |
2713 | } /* walk the symbol chain */ |
2714 | |
2715 | return; |
2716 | } /* tc_crawl_symbol_chain() */ |
2717 | |
2718 | /* |
2719 | * For aout or bout, the bal immediately follows the call. |
2720 | * |
2721 | * For coff, we cheat and store a pointer to the bal symbol |
2722 | * in the second aux entry of the call. |
2723 | */ |
2724 | |
2725 | void tc_set_bal_of_call(callP, balP) |
2726 | symbolS *callP; |
2727 | symbolS *balP; |
2728 | { |
2729 | know(TC_S_IS_CALLNAME(callP)); |
2730 | know(TC_S_IS_BALNAME(balP)); |
2731 | |
2732 | #ifdef OBJ_COFF |
2733 | |
2734 | callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP; |
2735 | S_SET_NUMBER_AUXILIARY(callP,2); |
2736 | |
2737 | #elif defined(OBJ_AOUT) || defined(OBJ_BOUT) |
2738 | |
2739 | /* If the 'bal' entry doesn't immediately follow the 'call' |
2740 | * symbol, unlink it from the symbol list and re-insert it. |
2741 | */ |
2742 | if (symbol_next(callP) != balP) { |
2743 | symbol_remove(balP, &symbol_rootP, &symbol_lastP); |
2744 | symbol_append(balP, callP, &symbol_rootP, &symbol_lastP); |
2745 | } /* if not in order */ |
2746 | |
2747 | #else |
2748 | (as yet unwritten.); |
2749 | #endif /* switch on OBJ_FORMAT */ |
2750 | |
2751 | return; |
2752 | } /* tc_set_bal_of_call() */ |
2753 | |
2754 | char *_tc_get_bal_of_call(callP) |
2755 | symbolS *callP; |
2756 | { |
2757 | symbolS *retval; |
2758 | |
2759 | know(TC_S_IS_CALLNAME(callP)); |
2760 | |
2761 | #ifdef OBJ_COFF |
2762 | retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry); |
2763 | #elif defined(OBJ_AOUT) || defined(OBJ_BOUT) |
2764 | retval = symbol_next(callP); |
2765 | #else |
2766 | (as yet unwritten.); |
2767 | #endif /* switch on OBJ_FORMAT */ |
2768 | |
2769 | know(TC_S_IS_BALNAME(retval)); |
2770 | return((char *) retval); |
2771 | } /* _tc_get_bal_of_call() */ |
2772 | |
2773 | void tc_coff_symbol_emit_hook(symbolP) |
2774 | symbolS *symbolP; |
2775 | { |
2776 | if (TC_S_IS_CALLNAME(symbolP)) { |
2777 | #ifdef OBJ_COFF |
2778 | symbolS *balP = tc_get_bal_of_call(symbolP); |
2779 | |
2780 | /* second aux entry contains the bal entry point */ |
2781 | /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */ |
2782 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE(balP); |
2783 | S_SET_STORAGE_CLASS(symbolP, (!SF_GET_LOCAL(symbolP) ? C_LEAFEXT : C_LEAFSTAT)); |
2784 | S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT)); |
2785 | /* fix up the bal symbol */ |
2786 | S_SET_STORAGE_CLASS(balP, C_LABEL); |
2787 | #endif /* OBJ_COFF */ |
2788 | } /* only on calls */ |
2789 | |
2790 | return; |
2791 | } /* tc_coff_symbol_emit_hook() */ |
2792 | |
2793 | /* |
2794 | * Local Variables: |
2795 | * comment-column: 0 |
2796 | * fill-column: 131 |
2797 | * End: |
2798 | */ |
2799 | |
2800 | /* end of i960.c */ |