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800eeca4 | 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
1cd8ff38 | 2 | Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
800eeca4 JW |
3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | TODO: | |
24 | ||
25 | - optional operands | |
26 | - directives: | |
27 | .alias | |
28 | .eb | |
29 | .estate | |
30 | .lb | |
31 | .popsection | |
32 | .previous | |
33 | .psr | |
34 | .pushsection | |
800eeca4 JW |
35 | - labels are wrong if automatic alignment is introduced |
36 | (e.g., checkout the second real10 definition in test-data.s) | |
37 | - DV-related stuff: | |
542d6675 KH |
38 | <reg>.safe_across_calls and any other DV-related directives I don't |
39 | have documentation for. | |
40 | verify mod-sched-brs reads/writes are checked/marked (and other | |
41 | notes) | |
800eeca4 JW |
42 | |
43 | */ | |
44 | ||
45 | #include "as.h" | |
3882b010 | 46 | #include "safe-ctype.h" |
800eeca4 JW |
47 | #include "dwarf2dbg.h" |
48 | #include "subsegs.h" | |
49 | ||
50 | #include "opcode/ia64.h" | |
51 | ||
52 | #include "elf/ia64.h" | |
53 | ||
54 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) | |
55 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) | |
56 | ||
57 | #define NUM_SLOTS 4 | |
58 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] | |
59 | #define CURR_SLOT md.slot[md.curr_slot] | |
60 | ||
61 | #define O_pseudo_fixup (O_max + 1) | |
62 | ||
63 | enum special_section | |
64 | { | |
557debba | 65 | /* IA-64 ABI section pseudo-ops. */ |
800eeca4 JW |
66 | SPECIAL_SECTION_BSS = 0, |
67 | SPECIAL_SECTION_SBSS, | |
68 | SPECIAL_SECTION_SDATA, | |
69 | SPECIAL_SECTION_RODATA, | |
70 | SPECIAL_SECTION_COMMENT, | |
71 | SPECIAL_SECTION_UNWIND, | |
557debba JW |
72 | SPECIAL_SECTION_UNWIND_INFO, |
73 | /* HPUX specific section pseudo-ops. */ | |
74 | SPECIAL_SECTION_INIT_ARRAY, | |
75 | SPECIAL_SECTION_FINI_ARRAY, | |
800eeca4 JW |
76 | }; |
77 | ||
78 | enum reloc_func | |
79 | { | |
13ae64f3 JJ |
80 | FUNC_DTP_MODULE, |
81 | FUNC_DTP_RELATIVE, | |
800eeca4 JW |
82 | FUNC_FPTR_RELATIVE, |
83 | FUNC_GP_RELATIVE, | |
84 | FUNC_LT_RELATIVE, | |
c67e42c9 | 85 | FUNC_PC_RELATIVE, |
800eeca4 JW |
86 | FUNC_PLT_RELATIVE, |
87 | FUNC_SEC_RELATIVE, | |
88 | FUNC_SEG_RELATIVE, | |
13ae64f3 | 89 | FUNC_TP_RELATIVE, |
800eeca4 JW |
90 | FUNC_LTV_RELATIVE, |
91 | FUNC_LT_FPTR_RELATIVE, | |
13ae64f3 JJ |
92 | FUNC_LT_DTP_MODULE, |
93 | FUNC_LT_DTP_RELATIVE, | |
94 | FUNC_LT_TP_RELATIVE, | |
3969b680 | 95 | FUNC_IPLT_RELOC, |
800eeca4 JW |
96 | }; |
97 | ||
98 | enum reg_symbol | |
99 | { | |
100 | REG_GR = 0, | |
101 | REG_FR = (REG_GR + 128), | |
102 | REG_AR = (REG_FR + 128), | |
103 | REG_CR = (REG_AR + 128), | |
104 | REG_P = (REG_CR + 128), | |
105 | REG_BR = (REG_P + 64), | |
106 | REG_IP = (REG_BR + 8), | |
107 | REG_CFM, | |
108 | REG_PR, | |
109 | REG_PR_ROT, | |
110 | REG_PSR, | |
111 | REG_PSR_L, | |
112 | REG_PSR_UM, | |
113 | /* The following are pseudo-registers for use by gas only. */ | |
114 | IND_CPUID, | |
115 | IND_DBR, | |
116 | IND_DTR, | |
117 | IND_ITR, | |
118 | IND_IBR, | |
119 | IND_MEM, | |
120 | IND_MSR, | |
121 | IND_PKR, | |
122 | IND_PMC, | |
123 | IND_PMD, | |
124 | IND_RR, | |
542d6675 | 125 | /* The following pseudo-registers are used for unwind directives only: */ |
e0c9811a JW |
126 | REG_PSP, |
127 | REG_PRIUNAT, | |
800eeca4 JW |
128 | REG_NUM |
129 | }; | |
130 | ||
131 | enum dynreg_type | |
132 | { | |
133 | DYNREG_GR = 0, /* dynamic general purpose register */ | |
134 | DYNREG_FR, /* dynamic floating point register */ | |
135 | DYNREG_PR, /* dynamic predicate register */ | |
136 | DYNREG_NUM_TYPES | |
137 | }; | |
138 | ||
87f8eb97 JW |
139 | enum operand_match_result |
140 | { | |
141 | OPERAND_MATCH, | |
142 | OPERAND_OUT_OF_RANGE, | |
143 | OPERAND_MISMATCH | |
144 | }; | |
145 | ||
800eeca4 JW |
146 | /* On the ia64, we can't know the address of a text label until the |
147 | instructions are packed into a bundle. To handle this, we keep | |
148 | track of the list of labels that appear in front of each | |
149 | instruction. */ | |
150 | struct label_fix | |
542d6675 KH |
151 | { |
152 | struct label_fix *next; | |
153 | struct symbol *sym; | |
154 | }; | |
800eeca4 JW |
155 | |
156 | extern int target_big_endian; | |
157 | ||
158 | /* Characters which always start a comment. */ | |
159 | const char comment_chars[] = ""; | |
160 | ||
161 | /* Characters which start a comment at the beginning of a line. */ | |
162 | const char line_comment_chars[] = "#"; | |
163 | ||
164 | /* Characters which may be used to separate multiple commands on a | |
165 | single line. */ | |
166 | const char line_separator_chars[] = ";"; | |
167 | ||
168 | /* Characters which are used to indicate an exponent in a floating | |
169 | point number. */ | |
170 | const char EXP_CHARS[] = "eE"; | |
171 | ||
172 | /* Characters which mean that a number is a floating point constant, | |
173 | as in 0d1.0. */ | |
174 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
175 | ||
542d6675 | 176 | /* ia64-specific option processing: */ |
800eeca4 | 177 | |
44f5c83a | 178 | const char *md_shortopts = "m:N:x::"; |
800eeca4 JW |
179 | |
180 | struct option md_longopts[] = | |
181 | { | |
c43c2cc5 JW |
182 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
183 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, | |
184 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) | |
185 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} | |
800eeca4 JW |
186 | }; |
187 | ||
188 | size_t md_longopts_size = sizeof (md_longopts); | |
189 | ||
190 | static struct | |
191 | { | |
192 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ | |
193 | struct hash_control *reg_hash; /* register name hash table */ | |
194 | struct hash_control *dynreg_hash; /* dynamic register hash table */ | |
195 | struct hash_control *const_hash; /* constant hash table */ | |
196 | struct hash_control *entry_hash; /* code entry hint hash table */ | |
197 | ||
198 | symbolS *regsym[REG_NUM]; | |
199 | ||
200 | /* If X_op is != O_absent, the registername for the instruction's | |
201 | qualifying predicate. If NULL, p0 is assumed for instructions | |
202 | that are predicatable. */ | |
203 | expressionS qp; | |
204 | ||
205 | unsigned int | |
197865e8 | 206 | manual_bundling : 1, |
800eeca4 JW |
207 | debug_dv: 1, |
208 | detect_dv: 1, | |
209 | explicit_mode : 1, /* which mode we're in */ | |
210 | default_explicit_mode : 1, /* which mode is the default */ | |
211 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ | |
4d5a53ff JW |
212 | auto_align : 1, |
213 | keep_pending_output : 1; | |
800eeca4 JW |
214 | |
215 | /* Each bundle consists of up to three instructions. We keep | |
216 | track of four most recent instructions so we can correctly set | |
197865e8 | 217 | the end_of_insn_group for the last instruction in a bundle. */ |
800eeca4 JW |
218 | int curr_slot; |
219 | int num_slots_in_use; | |
220 | struct slot | |
221 | { | |
222 | unsigned int | |
223 | end_of_insn_group : 1, | |
224 | manual_bundling_on : 1, | |
225 | manual_bundling_off : 1; | |
226 | signed char user_template; /* user-selected template, if any */ | |
227 | unsigned char qp_regno; /* qualifying predicate */ | |
228 | /* This duplicates a good fraction of "struct fix" but we | |
229 | can't use a "struct fix" instead since we can't call | |
230 | fix_new_exp() until we know the address of the instruction. */ | |
231 | int num_fixups; | |
232 | struct insn_fix | |
233 | { | |
234 | bfd_reloc_code_real_type code; | |
235 | enum ia64_opnd opnd; /* type of operand in need of fix */ | |
236 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ | |
237 | expressionS expr; /* the value to be inserted */ | |
238 | } | |
239 | fixup[2]; /* at most two fixups per insn */ | |
240 | struct ia64_opcode *idesc; | |
241 | struct label_fix *label_fixups; | |
f1bcba5b | 242 | struct label_fix *tag_fixups; |
800eeca4 JW |
243 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
244 | expressionS opnd[6]; | |
245 | char *src_file; | |
246 | unsigned int src_line; | |
247 | struct dwarf2_line_info debug_line; | |
248 | } | |
249 | slot[NUM_SLOTS]; | |
250 | ||
251 | segT last_text_seg; | |
252 | ||
253 | struct dynreg | |
254 | { | |
255 | struct dynreg *next; /* next dynamic register */ | |
256 | const char *name; | |
257 | unsigned short base; /* the base register number */ | |
258 | unsigned short num_regs; /* # of registers in this set */ | |
259 | } | |
260 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; | |
261 | ||
262 | flagword flags; /* ELF-header flags */ | |
263 | ||
264 | struct mem_offset { | |
265 | unsigned hint:1; /* is this hint currently valid? */ | |
266 | bfd_vma offset; /* mem.offset offset */ | |
267 | bfd_vma base; /* mem.offset base */ | |
268 | } mem_offset; | |
269 | ||
270 | int path; /* number of alt. entry points seen */ | |
271 | const char **entry_labels; /* labels of all alternate paths in | |
542d6675 | 272 | the current DV-checking block. */ |
800eeca4 | 273 | int maxpaths; /* size currently allocated for |
542d6675 | 274 | entry_labels */ |
88be23ec BS |
275 | /* Support for hardware errata workarounds. */ |
276 | ||
277 | /* Record data about the last three insn groups. */ | |
278 | struct group | |
279 | { | |
280 | /* B-step workaround. | |
281 | For each predicate register, this is set if the corresponding insn | |
282 | group conditionally sets this register with one of the affected | |
283 | instructions. */ | |
284 | int p_reg_set[64]; | |
285 | /* B-step workaround. | |
286 | For each general register, this is set if the corresponding insn | |
287 | a) is conditional one one of the predicate registers for which | |
288 | P_REG_SET is 1 in the corresponding entry of the previous group, | |
289 | b) sets this general register with one of the affected | |
290 | instructions. */ | |
291 | int g_reg_set_conditionally[128]; | |
292 | } last_groups[3]; | |
293 | int group_idx; | |
557debba JW |
294 | |
295 | int pointer_size; /* size in bytes of a pointer */ | |
296 | int pointer_size_shift; /* shift size of a pointer for alignment */ | |
800eeca4 JW |
297 | } |
298 | md; | |
299 | ||
542d6675 | 300 | /* application registers: */ |
800eeca4 | 301 | |
e0c9811a JW |
302 | #define AR_K0 0 |
303 | #define AR_K7 7 | |
304 | #define AR_RSC 16 | |
305 | #define AR_BSP 17 | |
306 | #define AR_BSPSTORE 18 | |
307 | #define AR_RNAT 19 | |
308 | #define AR_UNAT 36 | |
309 | #define AR_FPSR 40 | |
310 | #define AR_ITC 44 | |
311 | #define AR_PFS 64 | |
312 | #define AR_LC 65 | |
800eeca4 JW |
313 | |
314 | static const struct | |
315 | { | |
316 | const char *name; | |
317 | int regnum; | |
318 | } | |
319 | ar[] = | |
320 | { | |
321 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, | |
322 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, | |
323 | {"ar.rsc", 16}, {"ar.bsp", 17}, | |
324 | {"ar.bspstore", 18}, {"ar.rnat", 19}, | |
325 | {"ar.fcr", 21}, {"ar.eflag", 24}, | |
326 | {"ar.csd", 25}, {"ar.ssd", 26}, | |
327 | {"ar.cflg", 27}, {"ar.fsr", 28}, | |
328 | {"ar.fir", 29}, {"ar.fdr", 30}, | |
329 | {"ar.ccv", 32}, {"ar.unat", 36}, | |
330 | {"ar.fpsr", 40}, {"ar.itc", 44}, | |
331 | {"ar.pfs", 64}, {"ar.lc", 65}, | |
197865e8 | 332 | {"ar.ec", 66}, |
800eeca4 JW |
333 | }; |
334 | ||
335 | #define CR_IPSR 16 | |
336 | #define CR_ISR 17 | |
337 | #define CR_IIP 19 | |
338 | #define CR_IFA 20 | |
339 | #define CR_ITIR 21 | |
340 | #define CR_IIPA 22 | |
341 | #define CR_IFS 23 | |
342 | #define CR_IIM 24 | |
343 | #define CR_IHA 25 | |
344 | #define CR_IVR 65 | |
345 | #define CR_TPR 66 | |
346 | #define CR_EOI 67 | |
347 | #define CR_IRR0 68 | |
348 | #define CR_IRR3 71 | |
349 | #define CR_LRR0 80 | |
350 | #define CR_LRR1 81 | |
351 | ||
542d6675 | 352 | /* control registers: */ |
800eeca4 JW |
353 | static const struct |
354 | { | |
355 | const char *name; | |
356 | int regnum; | |
357 | } | |
358 | cr[] = | |
359 | { | |
360 | {"cr.dcr", 0}, | |
361 | {"cr.itm", 1}, | |
362 | {"cr.iva", 2}, | |
363 | {"cr.pta", 8}, | |
364 | {"cr.gpta", 9}, | |
365 | {"cr.ipsr", 16}, | |
366 | {"cr.isr", 17}, | |
367 | {"cr.iip", 19}, | |
368 | {"cr.ifa", 20}, | |
369 | {"cr.itir", 21}, | |
370 | {"cr.iipa", 22}, | |
371 | {"cr.ifs", 23}, | |
372 | {"cr.iim", 24}, | |
373 | {"cr.iha", 25}, | |
374 | {"cr.lid", 64}, | |
375 | {"cr.ivr", 65}, | |
376 | {"cr.tpr", 66}, | |
377 | {"cr.eoi", 67}, | |
378 | {"cr.irr0", 68}, | |
379 | {"cr.irr1", 69}, | |
380 | {"cr.irr2", 70}, | |
381 | {"cr.irr3", 71}, | |
382 | {"cr.itv", 72}, | |
383 | {"cr.pmv", 73}, | |
384 | {"cr.cmcv", 74}, | |
385 | {"cr.lrr0", 80}, | |
386 | {"cr.lrr1", 81} | |
387 | }; | |
388 | ||
389 | #define PSR_MFL 4 | |
390 | #define PSR_IC 13 | |
391 | #define PSR_DFL 18 | |
392 | #define PSR_CPL 32 | |
393 | ||
394 | static const struct const_desc | |
395 | { | |
396 | const char *name; | |
397 | valueT value; | |
398 | } | |
399 | const_bits[] = | |
400 | { | |
542d6675 | 401 | /* PSR constant masks: */ |
800eeca4 JW |
402 | |
403 | /* 0: reserved */ | |
404 | {"psr.be", ((valueT) 1) << 1}, | |
405 | {"psr.up", ((valueT) 1) << 2}, | |
406 | {"psr.ac", ((valueT) 1) << 3}, | |
407 | {"psr.mfl", ((valueT) 1) << 4}, | |
408 | {"psr.mfh", ((valueT) 1) << 5}, | |
409 | /* 6-12: reserved */ | |
410 | {"psr.ic", ((valueT) 1) << 13}, | |
411 | {"psr.i", ((valueT) 1) << 14}, | |
412 | {"psr.pk", ((valueT) 1) << 15}, | |
413 | /* 16: reserved */ | |
414 | {"psr.dt", ((valueT) 1) << 17}, | |
415 | {"psr.dfl", ((valueT) 1) << 18}, | |
416 | {"psr.dfh", ((valueT) 1) << 19}, | |
417 | {"psr.sp", ((valueT) 1) << 20}, | |
418 | {"psr.pp", ((valueT) 1) << 21}, | |
419 | {"psr.di", ((valueT) 1) << 22}, | |
420 | {"psr.si", ((valueT) 1) << 23}, | |
421 | {"psr.db", ((valueT) 1) << 24}, | |
422 | {"psr.lp", ((valueT) 1) << 25}, | |
423 | {"psr.tb", ((valueT) 1) << 26}, | |
424 | {"psr.rt", ((valueT) 1) << 27}, | |
425 | /* 28-31: reserved */ | |
426 | /* 32-33: cpl (current privilege level) */ | |
427 | {"psr.is", ((valueT) 1) << 34}, | |
428 | {"psr.mc", ((valueT) 1) << 35}, | |
429 | {"psr.it", ((valueT) 1) << 36}, | |
430 | {"psr.id", ((valueT) 1) << 37}, | |
431 | {"psr.da", ((valueT) 1) << 38}, | |
432 | {"psr.dd", ((valueT) 1) << 39}, | |
433 | {"psr.ss", ((valueT) 1) << 40}, | |
434 | /* 41-42: ri (restart instruction) */ | |
435 | {"psr.ed", ((valueT) 1) << 43}, | |
436 | {"psr.bn", ((valueT) 1) << 44}, | |
437 | }; | |
438 | ||
542d6675 | 439 | /* indirect register-sets/memory: */ |
800eeca4 JW |
440 | |
441 | static const struct | |
442 | { | |
443 | const char *name; | |
444 | int regnum; | |
445 | } | |
446 | indirect_reg[] = | |
447 | { | |
448 | { "CPUID", IND_CPUID }, | |
449 | { "cpuid", IND_CPUID }, | |
450 | { "dbr", IND_DBR }, | |
451 | { "dtr", IND_DTR }, | |
452 | { "itr", IND_ITR }, | |
453 | { "ibr", IND_IBR }, | |
454 | { "msr", IND_MSR }, | |
455 | { "pkr", IND_PKR }, | |
456 | { "pmc", IND_PMC }, | |
457 | { "pmd", IND_PMD }, | |
458 | { "rr", IND_RR }, | |
459 | }; | |
460 | ||
461 | /* Pseudo functions used to indicate relocation types (these functions | |
462 | start with an at sign (@). */ | |
463 | static struct | |
464 | { | |
465 | const char *name; | |
466 | enum pseudo_type | |
467 | { | |
468 | PSEUDO_FUNC_NONE, | |
469 | PSEUDO_FUNC_RELOC, | |
470 | PSEUDO_FUNC_CONST, | |
e0c9811a | 471 | PSEUDO_FUNC_REG, |
800eeca4 JW |
472 | PSEUDO_FUNC_FLOAT |
473 | } | |
474 | type; | |
475 | union | |
476 | { | |
477 | unsigned long ival; | |
478 | symbolS *sym; | |
479 | } | |
480 | u; | |
481 | } | |
482 | pseudo_func[] = | |
483 | { | |
542d6675 | 484 | /* reloc pseudo functions (these must come first!): */ |
13ae64f3 JJ |
485 | { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } }, |
486 | { "dtprel", PSEUDO_FUNC_RELOC, { 0 } }, | |
2434f565 JW |
487 | { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, |
488 | { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, | |
489 | { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
490 | { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
491 | { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
492 | { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
493 | { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
13ae64f3 | 494 | { "tprel", PSEUDO_FUNC_RELOC, { 0 } }, |
2434f565 JW |
495 | { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, |
496 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ | |
13ae64f3 JJ |
497 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */ |
498 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */ | |
499 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */ | |
3969b680 | 500 | { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, |
800eeca4 | 501 | |
542d6675 | 502 | /* mbtype4 constants: */ |
800eeca4 JW |
503 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
504 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, | |
505 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, | |
506 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, | |
507 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, | |
508 | ||
542d6675 | 509 | /* fclass constants: */ |
bf3ca999 | 510 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
800eeca4 JW |
511 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
512 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, | |
513 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, | |
514 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, | |
515 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, | |
516 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, | |
517 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, | |
518 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, | |
bf3ca999 TW |
519 | |
520 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ | |
e0c9811a | 521 | |
542d6675 | 522 | /* unwind-related constants: */ |
e0c9811a JW |
523 | { "svr4", PSEUDO_FUNC_CONST, { 0 } }, |
524 | { "hpux", PSEUDO_FUNC_CONST, { 1 } }, | |
525 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, | |
526 | ||
542d6675 | 527 | /* unwind-related registers: */ |
e0c9811a | 528 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
800eeca4 JW |
529 | }; |
530 | ||
542d6675 | 531 | /* 41-bit nop opcodes (one per unit): */ |
800eeca4 JW |
532 | static const bfd_vma nop[IA64_NUM_UNITS] = |
533 | { | |
534 | 0x0000000000LL, /* NIL => break 0 */ | |
535 | 0x0008000000LL, /* I-unit nop */ | |
536 | 0x0008000000LL, /* M-unit nop */ | |
537 | 0x4000000000LL, /* B-unit nop */ | |
538 | 0x0008000000LL, /* F-unit nop */ | |
539 | 0x0008000000LL, /* L-"unit" nop */ | |
540 | 0x0008000000LL, /* X-unit nop */ | |
541 | }; | |
542 | ||
543 | /* Can't be `const' as it's passed to input routines (which have the | |
544 | habit of setting temporary sentinels. */ | |
545 | static char special_section_name[][20] = | |
546 | { | |
547 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, | |
557debba JW |
548 | {".IA_64.unwind"}, {".IA_64.unwind_info"}, |
549 | {".init_array"}, {".fini_array"} | |
800eeca4 JW |
550 | }; |
551 | ||
579f31ac JJ |
552 | static char *special_linkonce_name[] = |
553 | { | |
554 | ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." | |
555 | }; | |
556 | ||
800eeca4 JW |
557 | /* The best template for a particular sequence of up to three |
558 | instructions: */ | |
559 | #define N IA64_NUM_TYPES | |
560 | static unsigned char best_template[N][N][N]; | |
561 | #undef N | |
562 | ||
563 | /* Resource dependencies currently in effect */ | |
564 | static struct rsrc { | |
565 | int depind; /* dependency index */ | |
566 | const struct ia64_dependency *dependency; /* actual dependency */ | |
567 | unsigned specific:1, /* is this a specific bit/regno? */ | |
568 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ | |
569 | int index; /* specific regno/bit within dependency */ | |
570 | int note; /* optional qualifying note (0 if none) */ | |
571 | #define STATE_NONE 0 | |
572 | #define STATE_STOP 1 | |
573 | #define STATE_SRLZ 2 | |
574 | int insn_srlz; /* current insn serialization state */ | |
575 | int data_srlz; /* current data serialization state */ | |
576 | int qp_regno; /* qualifying predicate for this usage */ | |
577 | char *file; /* what file marked this dependency */ | |
2434f565 | 578 | unsigned int line; /* what line marked this dependency */ |
800eeca4 | 579 | struct mem_offset mem_offset; /* optional memory offset hint */ |
7484b8e6 | 580 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
800eeca4 JW |
581 | int path; /* corresponding code entry index */ |
582 | } *regdeps = NULL; | |
583 | static int regdepslen = 0; | |
584 | static int regdepstotlen = 0; | |
585 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; | |
586 | static const char *dv_sem[] = { "none", "implied", "impliedf", | |
139368c9 | 587 | "data", "instr", "specific", "stop", "other" }; |
7484b8e6 | 588 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
800eeca4 JW |
589 | |
590 | /* Current state of PR mutexation */ | |
591 | static struct qpmutex { | |
592 | valueT prmask; | |
593 | int path; | |
594 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ | |
595 | static int qp_mutexeslen = 0; | |
596 | static int qp_mutexestotlen = 0; | |
197865e8 | 597 | static valueT qp_safe_across_calls = 0; |
800eeca4 JW |
598 | |
599 | /* Current state of PR implications */ | |
600 | static struct qp_imply { | |
601 | unsigned p1:6; | |
602 | unsigned p2:6; | |
603 | unsigned p2_branched:1; | |
604 | int path; | |
605 | } *qp_implies = NULL; | |
606 | static int qp_implieslen = 0; | |
607 | static int qp_impliestotlen = 0; | |
608 | ||
197865e8 KH |
609 | /* Keep track of static GR values so that indirect register usage can |
610 | sometimes be tracked. */ | |
800eeca4 JW |
611 | static struct gr { |
612 | unsigned known:1; | |
613 | int path; | |
614 | valueT value; | |
2434f565 | 615 | } gr_values[128] = {{ 1, 0, 0 }}; |
800eeca4 JW |
616 | |
617 | /* These are the routines required to output the various types of | |
618 | unwind records. */ | |
619 | ||
f5a30c2e JW |
620 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
621 | frag address here so that if there is a section switch in the middle of | |
622 | a function, then instructions emitted to a different section are not | |
623 | counted. Since there may be more than one frag for a function, this | |
624 | means we also need to keep track of which frag this address belongs to | |
625 | so we can compute inter-frag distances. This also nicely solves the | |
626 | problem with nops emitted for align directives, which can't easily be | |
627 | counted, but can easily be derived from frag sizes. */ | |
628 | ||
800eeca4 JW |
629 | typedef struct unw_rec_list { |
630 | unwind_record r; | |
e0c9811a | 631 | unsigned long slot_number; |
f5a30c2e | 632 | fragS *slot_frag; |
800eeca4 JW |
633 | struct unw_rec_list *next; |
634 | } unw_rec_list; | |
635 | ||
2434f565 | 636 | #define SLOT_NUM_NOT_SET (unsigned)-1 |
800eeca4 | 637 | |
6290819d NC |
638 | /* Linked list of saved prologue counts. A very poor |
639 | implementation of a map from label numbers to prologue counts. */ | |
640 | typedef struct label_prologue_count | |
641 | { | |
642 | struct label_prologue_count *next; | |
643 | unsigned long label_number; | |
644 | unsigned int prologue_count; | |
645 | } label_prologue_count; | |
646 | ||
e0c9811a JW |
647 | static struct |
648 | { | |
649 | unsigned long next_slot_number; | |
f5a30c2e | 650 | fragS *next_slot_frag; |
e0c9811a JW |
651 | |
652 | /* Maintain a list of unwind entries for the current function. */ | |
653 | unw_rec_list *list; | |
654 | unw_rec_list *tail; | |
800eeca4 | 655 | |
e0c9811a JW |
656 | /* Any unwind entires that should be attached to the current slot |
657 | that an insn is being constructed for. */ | |
658 | unw_rec_list *current_entry; | |
800eeca4 | 659 | |
e0c9811a JW |
660 | /* These are used to create the unwind table entry for this function. */ |
661 | symbolS *proc_start; | |
662 | symbolS *proc_end; | |
663 | symbolS *info; /* pointer to unwind info */ | |
664 | symbolS *personality_routine; | |
91a2ae2a RH |
665 | segT saved_text_seg; |
666 | subsegT saved_text_subseg; | |
667 | unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ | |
800eeca4 | 668 | |
e0c9811a JW |
669 | /* TRUE if processing unwind directives in a prologue region. */ |
670 | int prologue; | |
30d25259 | 671 | int prologue_mask; |
33d01f33 | 672 | unsigned int prologue_count; /* number of .prologues seen so far */ |
6290819d NC |
673 | /* Prologue counts at previous .label_state directives. */ |
674 | struct label_prologue_count * saved_prologue_counts; | |
e0c9811a | 675 | } unwind; |
800eeca4 JW |
676 | |
677 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); | |
678 | ||
542d6675 | 679 | /* Forward delarations: */ |
800eeca4 JW |
680 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
681 | static void set_section PARAMS ((char *name)); | |
682 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, | |
683 | unsigned int, unsigned int)); | |
684 | static void dot_radix PARAMS ((int)); | |
685 | static void dot_special_section PARAMS ((int)); | |
686 | static void dot_proc PARAMS ((int)); | |
687 | static void dot_fframe PARAMS ((int)); | |
688 | static void dot_vframe PARAMS ((int)); | |
150f24a2 JW |
689 | static void dot_vframesp PARAMS ((int)); |
690 | static void dot_vframepsp PARAMS ((int)); | |
800eeca4 JW |
691 | static void dot_save PARAMS ((int)); |
692 | static void dot_restore PARAMS ((int)); | |
150f24a2 JW |
693 | static void dot_restorereg PARAMS ((int)); |
694 | static void dot_restorereg_p PARAMS ((int)); | |
800eeca4 JW |
695 | static void dot_handlerdata PARAMS ((int)); |
696 | static void dot_unwentry PARAMS ((int)); | |
697 | static void dot_altrp PARAMS ((int)); | |
e0c9811a | 698 | static void dot_savemem PARAMS ((int)); |
800eeca4 JW |
699 | static void dot_saveg PARAMS ((int)); |
700 | static void dot_savef PARAMS ((int)); | |
701 | static void dot_saveb PARAMS ((int)); | |
702 | static void dot_savegf PARAMS ((int)); | |
703 | static void dot_spill PARAMS ((int)); | |
150f24a2 JW |
704 | static void dot_spillreg PARAMS ((int)); |
705 | static void dot_spillmem PARAMS ((int)); | |
706 | static void dot_spillreg_p PARAMS ((int)); | |
707 | static void dot_spillmem_p PARAMS ((int)); | |
708 | static void dot_label_state PARAMS ((int)); | |
709 | static void dot_copy_state PARAMS ((int)); | |
800eeca4 JW |
710 | static void dot_unwabi PARAMS ((int)); |
711 | static void dot_personality PARAMS ((int)); | |
712 | static void dot_body PARAMS ((int)); | |
713 | static void dot_prologue PARAMS ((int)); | |
714 | static void dot_endp PARAMS ((int)); | |
715 | static void dot_template PARAMS ((int)); | |
716 | static void dot_regstk PARAMS ((int)); | |
717 | static void dot_rot PARAMS ((int)); | |
718 | static void dot_byteorder PARAMS ((int)); | |
719 | static void dot_psr PARAMS ((int)); | |
720 | static void dot_alias PARAMS ((int)); | |
721 | static void dot_ln PARAMS ((int)); | |
722 | static char *parse_section_name PARAMS ((void)); | |
723 | static void dot_xdata PARAMS ((int)); | |
724 | static void stmt_float_cons PARAMS ((int)); | |
725 | static void stmt_cons_ua PARAMS ((int)); | |
726 | static void dot_xfloat_cons PARAMS ((int)); | |
727 | static void dot_xstringer PARAMS ((int)); | |
728 | static void dot_xdata_ua PARAMS ((int)); | |
729 | static void dot_xfloat_cons_ua PARAMS ((int)); | |
150f24a2 | 730 | static void print_prmask PARAMS ((valueT mask)); |
800eeca4 JW |
731 | static void dot_pred_rel PARAMS ((int)); |
732 | static void dot_reg_val PARAMS ((int)); | |
733 | static void dot_dv_mode PARAMS ((int)); | |
734 | static void dot_entry PARAMS ((int)); | |
735 | static void dot_mem_offset PARAMS ((int)); | |
e0c9811a | 736 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
542d6675 | 737 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
800eeca4 JW |
738 | static void declare_register_set PARAMS ((const char *, int, int)); |
739 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); | |
87f8eb97 JW |
740 | static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, |
741 | int index, | |
742 | expressionS *e)); | |
800eeca4 JW |
743 | static int parse_operand PARAMS ((expressionS *e)); |
744 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); | |
86cf98f3 | 745 | static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit)); |
800eeca4 JW |
746 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); |
747 | static void emit_one_bundle PARAMS ((void)); | |
748 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); | |
197865e8 | 749 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
800eeca4 JW |
750 | bfd_reloc_code_real_type r_type)); |
751 | static void insn_group_break PARAMS ((int, int, int)); | |
150f24a2 JW |
752 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
753 | struct rsrc *, int depind, int path)); | |
800eeca4 JW |
754 | static void add_qp_mutex PARAMS((valueT mask)); |
755 | static void add_qp_imply PARAMS((int p1, int p2)); | |
756 | static void clear_qp_branch_flag PARAMS((valueT mask)); | |
757 | static void clear_qp_mutex PARAMS((valueT mask)); | |
758 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); | |
cb5301b6 | 759 | static int has_suffix_p PARAMS((const char *, const char *)); |
800eeca4 JW |
760 | static void clear_register_values PARAMS ((void)); |
761 | static void print_dependency PARAMS ((const char *action, int depind)); | |
150f24a2 JW |
762 | static void instruction_serialization PARAMS ((void)); |
763 | static void data_serialization PARAMS ((void)); | |
764 | static void remove_marked_resource PARAMS ((struct rsrc *)); | |
800eeca4 | 765 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
150f24a2 | 766 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
800eeca4 | 767 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
150f24a2 JW |
768 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
769 | static int specify_resource PARAMS ((const struct ia64_dependency *, | |
770 | struct ia64_opcode *, int, struct rsrc [], int, int)); | |
800eeca4 JW |
771 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
772 | static void check_dependencies PARAMS((struct ia64_opcode *)); | |
773 | static void mark_resources PARAMS((struct ia64_opcode *)); | |
774 | static void update_dependencies PARAMS((struct ia64_opcode *)); | |
775 | static void note_register_values PARAMS((struct ia64_opcode *)); | |
150f24a2 JW |
776 | static int qp_mutex PARAMS ((int, int, int)); |
777 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); | |
778 | static void output_vbyte_mem PARAMS ((int, char *, char *)); | |
779 | static void count_output PARAMS ((int, char *, char *)); | |
780 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); | |
781 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); | |
800eeca4 | 782 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
150f24a2 JW |
783 | static void output_P1_format PARAMS ((vbyte_func, int)); |
784 | static void output_P2_format PARAMS ((vbyte_func, int, int)); | |
785 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); | |
786 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); | |
787 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); | |
788 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); | |
789 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); | |
790 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
791 | static void output_P9_format PARAMS ((vbyte_func, int, int)); | |
792 | static void output_P10_format PARAMS ((vbyte_func, int, int)); | |
793 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
794 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); | |
800eeca4 JW |
795 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
796 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
150f24a2 JW |
797 | static char format_ab_reg PARAMS ((int, int)); |
798 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, | |
799 | unsigned long)); | |
800 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); | |
801 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, | |
802 | unsigned long)); | |
803 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); | |
804 | static void free_list_records PARAMS ((unw_rec_list *)); | |
805 | static unw_rec_list *output_prologue PARAMS ((void)); | |
806 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); | |
807 | static unw_rec_list *output_body PARAMS ((void)); | |
808 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); | |
809 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); | |
810 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); | |
811 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); | |
812 | static unw_rec_list *output_rp_when PARAMS ((void)); | |
813 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); | |
814 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); | |
815 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); | |
816 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); | |
817 | static unw_rec_list *output_pfs_when PARAMS ((void)); | |
818 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); | |
819 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); | |
820 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); | |
821 | static unw_rec_list *output_preds_when PARAMS ((void)); | |
822 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); | |
823 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); | |
824 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); | |
825 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); | |
826 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); | |
827 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); | |
828 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); | |
829 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); | |
830 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); | |
831 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); | |
832 | static unw_rec_list *output_unat_when PARAMS ((void)); | |
833 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); | |
834 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); | |
835 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); | |
836 | static unw_rec_list *output_lc_when PARAMS ((void)); | |
837 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); | |
838 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); | |
839 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); | |
840 | static unw_rec_list *output_fpsr_when PARAMS ((void)); | |
841 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); | |
842 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); | |
843 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); | |
844 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); | |
845 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); | |
846 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); | |
847 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); | |
848 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); | |
849 | static unw_rec_list *output_bsp_when PARAMS ((void)); | |
850 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); | |
851 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); | |
852 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); | |
853 | static unw_rec_list *output_bspstore_when PARAMS ((void)); | |
854 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); | |
855 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); | |
856 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); | |
857 | static unw_rec_list *output_rnat_when PARAMS ((void)); | |
858 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); | |
859 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); | |
860 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); | |
861 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); | |
862 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); | |
863 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); | |
864 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); | |
865 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
866 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
867 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
868 | unsigned int)); | |
869 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
870 | unsigned int)); | |
871 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, | |
872 | unsigned int)); | |
873 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
874 | unsigned int, unsigned int)); | |
875 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); | |
876 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); | |
877 | static int calc_record_size PARAMS ((unw_rec_list *)); | |
878 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); | |
879 | static int count_bits PARAMS ((unsigned long)); | |
f5a30c2e JW |
880 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
881 | unsigned long, fragS *)); | |
91a2ae2a | 882 | static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); |
150f24a2 JW |
883 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
884 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); | |
885 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
886 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
91a2ae2a | 887 | static int generate_unwind_image PARAMS ((const char *)); |
6290819d NC |
888 | static unsigned int get_saved_prologue_count PARAMS ((unsigned long)); |
889 | static void save_prologue_count PARAMS ((unsigned long, unsigned int)); | |
890 | static void free_saved_prologue_counts PARAMS ((void)); | |
91a2ae2a RH |
891 | |
892 | /* Build the unwind section name by appending the (possibly stripped) | |
893 | text section NAME to the unwind PREFIX. The resulting string | |
894 | pointer is assigned to RESULT. The string is allocated on the | |
40449e9f | 895 | stack, so this must be a macro... */ |
91a2ae2a RH |
896 | #define make_unw_section_name(special, text_name, result) \ |
897 | { \ | |
86cf98f3 RH |
898 | const char *_prefix = special_section_name[special]; \ |
899 | const char *_suffix = text_name; \ | |
579f31ac JJ |
900 | size_t _prefix_len, _suffix_len; \ |
901 | char *_result; \ | |
902 | if (strncmp (text_name, ".gnu.linkonce.t.", \ | |
903 | sizeof (".gnu.linkonce.t.") - 1) == 0) \ | |
904 | { \ | |
905 | _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \ | |
906 | _suffix += sizeof (".gnu.linkonce.t.") - 1; \ | |
907 | } \ | |
908 | _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \ | |
909 | _result = alloca (_prefix_len + _suffix_len + 1); \ | |
07726851 KH |
910 | memcpy (_result, _prefix, _prefix_len); \ |
911 | memcpy (_result + _prefix_len, _suffix, _suffix_len); \ | |
579f31ac | 912 | _result[_prefix_len + _suffix_len] = '\0'; \ |
91a2ae2a RH |
913 | result = _result; \ |
914 | } \ | |
915 | while (0) | |
800eeca4 JW |
916 | |
917 | /* Determine if application register REGNUM resides in the integer | |
918 | unit (as opposed to the memory unit). */ | |
919 | static int | |
920 | ar_is_in_integer_unit (reg) | |
921 | int reg; | |
922 | { | |
923 | reg -= REG_AR; | |
924 | ||
925 | return (reg == 64 /* pfs */ | |
926 | || reg == 65 /* lc */ | |
927 | || reg == 66 /* ec */ | |
928 | /* ??? ias accepts and puts these in the integer unit. */ | |
929 | || (reg >= 112 && reg <= 127)); | |
930 | } | |
931 | ||
932 | /* Switch to section NAME and create section if necessary. It's | |
933 | rather ugly that we have to manipulate input_line_pointer but I | |
934 | don't see any other way to accomplish the same thing without | |
935 | changing obj-elf.c (which may be the Right Thing, in the end). */ | |
936 | static void | |
937 | set_section (name) | |
938 | char *name; | |
939 | { | |
940 | char *saved_input_line_pointer; | |
941 | ||
942 | saved_input_line_pointer = input_line_pointer; | |
943 | input_line_pointer = name; | |
944 | obj_elf_section (0); | |
945 | input_line_pointer = saved_input_line_pointer; | |
946 | } | |
947 | ||
d61a78a7 RH |
948 | /* Map 's' to SHF_IA_64_SHORT. */ |
949 | ||
950 | int | |
951 | ia64_elf_section_letter (letter, ptr_msg) | |
952 | int letter; | |
953 | char **ptr_msg; | |
954 | { | |
955 | if (letter == 's') | |
956 | return SHF_IA_64_SHORT; | |
957 | ||
13ae64f3 | 958 | *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S,G,T in string"); |
d61a78a7 RH |
959 | return 0; |
960 | } | |
961 | ||
800eeca4 JW |
962 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ |
963 | ||
964 | flagword | |
965 | ia64_elf_section_flags (flags, attr, type) | |
966 | flagword flags; | |
2434f565 | 967 | int attr, type ATTRIBUTE_UNUSED; |
800eeca4 JW |
968 | { |
969 | if (attr & SHF_IA_64_SHORT) | |
970 | flags |= SEC_SMALL_DATA; | |
971 | return flags; | |
972 | } | |
973 | ||
91a2ae2a RH |
974 | int |
975 | ia64_elf_section_type (str, len) | |
40449e9f KH |
976 | const char *str; |
977 | size_t len; | |
91a2ae2a | 978 | { |
1cd8ff38 | 979 | #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) |
40449e9f | 980 | |
1cd8ff38 | 981 | if (STREQ (ELF_STRING_ia64_unwind_info)) |
91a2ae2a RH |
982 | return SHT_PROGBITS; |
983 | ||
1cd8ff38 | 984 | if (STREQ (ELF_STRING_ia64_unwind_info_once)) |
579f31ac JJ |
985 | return SHT_PROGBITS; |
986 | ||
1cd8ff38 | 987 | if (STREQ (ELF_STRING_ia64_unwind)) |
91a2ae2a RH |
988 | return SHT_IA_64_UNWIND; |
989 | ||
1cd8ff38 | 990 | if (STREQ (ELF_STRING_ia64_unwind_once)) |
579f31ac JJ |
991 | return SHT_IA_64_UNWIND; |
992 | ||
1cd8ff38 NC |
993 | if (STREQ ("init_array")) |
994 | return SHT_INIT_ARRAY; | |
40449e9f | 995 | |
1cd8ff38 NC |
996 | if (STREQ ("fini_array")) |
997 | return SHT_FINI_ARRAY; | |
40449e9f | 998 | |
91a2ae2a | 999 | return -1; |
1cd8ff38 | 1000 | #undef STREQ |
91a2ae2a RH |
1001 | } |
1002 | ||
800eeca4 JW |
1003 | static unsigned int |
1004 | set_regstack (ins, locs, outs, rots) | |
1005 | unsigned int ins, locs, outs, rots; | |
1006 | { | |
542d6675 KH |
1007 | /* Size of frame. */ |
1008 | unsigned int sof; | |
800eeca4 JW |
1009 | |
1010 | sof = ins + locs + outs; | |
1011 | if (sof > 96) | |
1012 | { | |
1013 | as_bad ("Size of frame exceeds maximum of 96 registers"); | |
1014 | return 0; | |
1015 | } | |
1016 | if (rots > sof) | |
1017 | { | |
1018 | as_warn ("Size of rotating registers exceeds frame size"); | |
1019 | return 0; | |
1020 | } | |
1021 | md.in.base = REG_GR + 32; | |
1022 | md.loc.base = md.in.base + ins; | |
1023 | md.out.base = md.loc.base + locs; | |
1024 | ||
1025 | md.in.num_regs = ins; | |
1026 | md.loc.num_regs = locs; | |
1027 | md.out.num_regs = outs; | |
1028 | md.rot.num_regs = rots; | |
1029 | return sof; | |
1030 | } | |
1031 | ||
1032 | void | |
1033 | ia64_flush_insns () | |
1034 | { | |
1035 | struct label_fix *lfix; | |
1036 | segT saved_seg; | |
1037 | subsegT saved_subseg; | |
b44b1b85 | 1038 | unw_rec_list *ptr; |
800eeca4 JW |
1039 | |
1040 | if (!md.last_text_seg) | |
1041 | return; | |
1042 | ||
1043 | saved_seg = now_seg; | |
1044 | saved_subseg = now_subseg; | |
1045 | ||
1046 | subseg_set (md.last_text_seg, 0); | |
1047 | ||
1048 | while (md.num_slots_in_use > 0) | |
1049 | emit_one_bundle (); /* force out queued instructions */ | |
1050 | ||
1051 | /* In case there are labels following the last instruction, resolve | |
542d6675 | 1052 | those now: */ |
800eeca4 JW |
1053 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
1054 | { | |
1055 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
1056 | symbol_set_frag (lfix->sym, frag_now); | |
1057 | } | |
1058 | CURR_SLOT.label_fixups = 0; | |
f1bcba5b JW |
1059 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
1060 | { | |
1061 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
1062 | symbol_set_frag (lfix->sym, frag_now); | |
1063 | } | |
1064 | CURR_SLOT.tag_fixups = 0; | |
800eeca4 | 1065 | |
b44b1b85 JW |
1066 | /* In case there are unwind directives following the last instruction, |
1067 | resolve those now. We only handle body and prologue directives here. | |
1068 | Give an error for others. */ | |
1069 | for (ptr = unwind.current_entry; ptr; ptr = ptr->next) | |
1070 | { | |
1071 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr | |
1072 | || ptr->r.type == body) | |
1073 | { | |
1074 | ptr->slot_number = (unsigned long) frag_more (0); | |
1075 | ptr->slot_frag = frag_now; | |
1076 | } | |
1077 | else | |
1078 | as_bad (_("Unwind directive not followed by an instruction.")); | |
1079 | } | |
1080 | unwind.current_entry = NULL; | |
1081 | ||
800eeca4 | 1082 | subseg_set (saved_seg, saved_subseg); |
f1bcba5b JW |
1083 | |
1084 | if (md.qp.X_op == O_register) | |
1085 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
1086 | } |
1087 | ||
1088 | void | |
1089 | ia64_do_align (nbytes) | |
1090 | int nbytes; | |
1091 | { | |
1092 | char *saved_input_line_pointer = input_line_pointer; | |
1093 | ||
1094 | input_line_pointer = ""; | |
1095 | s_align_bytes (nbytes); | |
1096 | input_line_pointer = saved_input_line_pointer; | |
1097 | } | |
1098 | ||
1099 | void | |
1100 | ia64_cons_align (nbytes) | |
1101 | int nbytes; | |
1102 | { | |
1103 | if (md.auto_align) | |
1104 | { | |
1105 | char *saved_input_line_pointer = input_line_pointer; | |
1106 | input_line_pointer = ""; | |
1107 | s_align_bytes (nbytes); | |
1108 | input_line_pointer = saved_input_line_pointer; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | /* Output COUNT bytes to a memory location. */ | |
1113 | static unsigned char *vbyte_mem_ptr = NULL; | |
1114 | ||
197865e8 | 1115 | void |
800eeca4 JW |
1116 | output_vbyte_mem (count, ptr, comment) |
1117 | int count; | |
1118 | char *ptr; | |
2434f565 | 1119 | char *comment ATTRIBUTE_UNUSED; |
800eeca4 JW |
1120 | { |
1121 | int x; | |
1122 | if (vbyte_mem_ptr == NULL) | |
1123 | abort (); | |
1124 | ||
1125 | if (count == 0) | |
1126 | return; | |
1127 | for (x = 0; x < count; x++) | |
1128 | *(vbyte_mem_ptr++) = ptr[x]; | |
1129 | } | |
1130 | ||
1131 | /* Count the number of bytes required for records. */ | |
1132 | static int vbyte_count = 0; | |
197865e8 | 1133 | void |
800eeca4 JW |
1134 | count_output (count, ptr, comment) |
1135 | int count; | |
2434f565 JW |
1136 | char *ptr ATTRIBUTE_UNUSED; |
1137 | char *comment ATTRIBUTE_UNUSED; | |
800eeca4 JW |
1138 | { |
1139 | vbyte_count += count; | |
1140 | } | |
1141 | ||
1142 | static void | |
1143 | output_R1_format (f, rtype, rlen) | |
1144 | vbyte_func f; | |
1145 | unw_record_type rtype; | |
1146 | int rlen; | |
1147 | { | |
e0c9811a | 1148 | int r = 0; |
800eeca4 JW |
1149 | char byte; |
1150 | if (rlen > 0x1f) | |
1151 | { | |
1152 | output_R3_format (f, rtype, rlen); | |
1153 | return; | |
1154 | } | |
197865e8 | 1155 | |
e0c9811a JW |
1156 | if (rtype == body) |
1157 | r = 1; | |
1158 | else if (rtype != prologue) | |
1159 | as_bad ("record type is not valid"); | |
1160 | ||
800eeca4 JW |
1161 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
1162 | (*f) (1, &byte, NULL); | |
1163 | } | |
1164 | ||
1165 | static void | |
1166 | output_R2_format (f, mask, grsave, rlen) | |
1167 | vbyte_func f; | |
1168 | int mask, grsave; | |
1169 | unsigned long rlen; | |
1170 | { | |
1171 | char bytes[20]; | |
1172 | int count = 2; | |
1173 | mask = (mask & 0x0f); | |
1174 | grsave = (grsave & 0x7f); | |
1175 | ||
1176 | bytes[0] = (UNW_R2 | (mask >> 1)); | |
1177 | bytes[1] = (((mask & 0x01) << 7) | grsave); | |
1178 | count += output_leb128 (bytes + 2, rlen, 0); | |
1179 | (*f) (count, bytes, NULL); | |
1180 | } | |
1181 | ||
1182 | static void | |
1183 | output_R3_format (f, rtype, rlen) | |
1184 | vbyte_func f; | |
1185 | unw_record_type rtype; | |
1186 | unsigned long rlen; | |
1187 | { | |
e0c9811a | 1188 | int r = 0, count; |
800eeca4 JW |
1189 | char bytes[20]; |
1190 | if (rlen <= 0x1f) | |
1191 | { | |
1192 | output_R1_format (f, rtype, rlen); | |
1193 | return; | |
1194 | } | |
197865e8 | 1195 | |
e0c9811a JW |
1196 | if (rtype == body) |
1197 | r = 1; | |
1198 | else if (rtype != prologue) | |
1199 | as_bad ("record type is not valid"); | |
800eeca4 JW |
1200 | bytes[0] = (UNW_R3 | r); |
1201 | count = output_leb128 (bytes + 1, rlen, 0); | |
1202 | (*f) (count + 1, bytes, NULL); | |
1203 | } | |
1204 | ||
1205 | static void | |
1206 | output_P1_format (f, brmask) | |
1207 | vbyte_func f; | |
1208 | int brmask; | |
1209 | { | |
1210 | char byte; | |
1211 | byte = UNW_P1 | (brmask & 0x1f); | |
1212 | (*f) (1, &byte, NULL); | |
1213 | } | |
1214 | ||
1215 | static void | |
1216 | output_P2_format (f, brmask, gr) | |
1217 | vbyte_func f; | |
1218 | int brmask; | |
1219 | int gr; | |
1220 | { | |
1221 | char bytes[2]; | |
1222 | brmask = (brmask & 0x1f); | |
1223 | bytes[0] = UNW_P2 | (brmask >> 1); | |
1224 | bytes[1] = (((brmask & 1) << 7) | gr); | |
1225 | (*f) (2, bytes, NULL); | |
1226 | } | |
1227 | ||
1228 | static void | |
1229 | output_P3_format (f, rtype, reg) | |
1230 | vbyte_func f; | |
1231 | unw_record_type rtype; | |
1232 | int reg; | |
1233 | { | |
1234 | char bytes[2]; | |
e0c9811a | 1235 | int r = 0; |
800eeca4 JW |
1236 | reg = (reg & 0x7f); |
1237 | switch (rtype) | |
542d6675 | 1238 | { |
800eeca4 JW |
1239 | case psp_gr: |
1240 | r = 0; | |
1241 | break; | |
1242 | case rp_gr: | |
1243 | r = 1; | |
1244 | break; | |
1245 | case pfs_gr: | |
1246 | r = 2; | |
1247 | break; | |
1248 | case preds_gr: | |
1249 | r = 3; | |
1250 | break; | |
1251 | case unat_gr: | |
1252 | r = 4; | |
1253 | break; | |
1254 | case lc_gr: | |
1255 | r = 5; | |
1256 | break; | |
1257 | case rp_br: | |
1258 | r = 6; | |
1259 | break; | |
1260 | case rnat_gr: | |
1261 | r = 7; | |
1262 | break; | |
1263 | case bsp_gr: | |
1264 | r = 8; | |
1265 | break; | |
1266 | case bspstore_gr: | |
1267 | r = 9; | |
1268 | break; | |
1269 | case fpsr_gr: | |
1270 | r = 10; | |
1271 | break; | |
1272 | case priunat_gr: | |
1273 | r = 11; | |
1274 | break; | |
1275 | default: | |
1276 | as_bad ("Invalid record type for P3 format."); | |
542d6675 | 1277 | } |
800eeca4 JW |
1278 | bytes[0] = (UNW_P3 | (r >> 1)); |
1279 | bytes[1] = (((r & 1) << 7) | reg); | |
1280 | (*f) (2, bytes, NULL); | |
1281 | } | |
1282 | ||
800eeca4 | 1283 | static void |
e0c9811a | 1284 | output_P4_format (f, imask, imask_size) |
800eeca4 | 1285 | vbyte_func f; |
e0c9811a JW |
1286 | unsigned char *imask; |
1287 | unsigned long imask_size; | |
800eeca4 | 1288 | { |
e0c9811a JW |
1289 | imask[0] = UNW_P4; |
1290 | (*f) (imask_size, imask, NULL); | |
800eeca4 JW |
1291 | } |
1292 | ||
1293 | static void | |
1294 | output_P5_format (f, grmask, frmask) | |
1295 | vbyte_func f; | |
1296 | int grmask; | |
1297 | unsigned long frmask; | |
1298 | { | |
1299 | char bytes[4]; | |
1300 | grmask = (grmask & 0x0f); | |
1301 | ||
1302 | bytes[0] = UNW_P5; | |
1303 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); | |
1304 | bytes[2] = ((frmask & 0x0000ff00) >> 8); | |
1305 | bytes[3] = (frmask & 0x000000ff); | |
1306 | (*f) (4, bytes, NULL); | |
1307 | } | |
1308 | ||
1309 | static void | |
1310 | output_P6_format (f, rtype, rmask) | |
1311 | vbyte_func f; | |
1312 | unw_record_type rtype; | |
1313 | int rmask; | |
1314 | { | |
1315 | char byte; | |
e0c9811a | 1316 | int r = 0; |
197865e8 | 1317 | |
e0c9811a JW |
1318 | if (rtype == gr_mem) |
1319 | r = 1; | |
1320 | else if (rtype != fr_mem) | |
1321 | as_bad ("Invalid record type for format P6"); | |
800eeca4 JW |
1322 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
1323 | (*f) (1, &byte, NULL); | |
1324 | } | |
1325 | ||
1326 | static void | |
1327 | output_P7_format (f, rtype, w1, w2) | |
1328 | vbyte_func f; | |
1329 | unw_record_type rtype; | |
1330 | unsigned long w1; | |
1331 | unsigned long w2; | |
1332 | { | |
1333 | char bytes[20]; | |
1334 | int count = 1; | |
e0c9811a | 1335 | int r = 0; |
800eeca4 JW |
1336 | count += output_leb128 (bytes + 1, w1, 0); |
1337 | switch (rtype) | |
1338 | { | |
542d6675 KH |
1339 | case mem_stack_f: |
1340 | r = 0; | |
1341 | count += output_leb128 (bytes + count, w2 >> 4, 0); | |
1342 | break; | |
1343 | case mem_stack_v: | |
1344 | r = 1; | |
1345 | break; | |
1346 | case spill_base: | |
1347 | r = 2; | |
1348 | break; | |
1349 | case psp_sprel: | |
1350 | r = 3; | |
1351 | break; | |
1352 | case rp_when: | |
1353 | r = 4; | |
1354 | break; | |
1355 | case rp_psprel: | |
1356 | r = 5; | |
1357 | break; | |
1358 | case pfs_when: | |
1359 | r = 6; | |
1360 | break; | |
1361 | case pfs_psprel: | |
1362 | r = 7; | |
1363 | break; | |
1364 | case preds_when: | |
1365 | r = 8; | |
1366 | break; | |
1367 | case preds_psprel: | |
1368 | r = 9; | |
1369 | break; | |
1370 | case lc_when: | |
1371 | r = 10; | |
1372 | break; | |
1373 | case lc_psprel: | |
1374 | r = 11; | |
1375 | break; | |
1376 | case unat_when: | |
1377 | r = 12; | |
1378 | break; | |
1379 | case unat_psprel: | |
1380 | r = 13; | |
1381 | break; | |
1382 | case fpsr_when: | |
1383 | r = 14; | |
1384 | break; | |
1385 | case fpsr_psprel: | |
1386 | r = 15; | |
1387 | break; | |
1388 | default: | |
1389 | break; | |
800eeca4 JW |
1390 | } |
1391 | bytes[0] = (UNW_P7 | r); | |
1392 | (*f) (count, bytes, NULL); | |
1393 | } | |
1394 | ||
1395 | static void | |
1396 | output_P8_format (f, rtype, t) | |
1397 | vbyte_func f; | |
1398 | unw_record_type rtype; | |
1399 | unsigned long t; | |
1400 | { | |
1401 | char bytes[20]; | |
e0c9811a | 1402 | int r = 0; |
800eeca4 JW |
1403 | int count = 2; |
1404 | bytes[0] = UNW_P8; | |
1405 | switch (rtype) | |
1406 | { | |
542d6675 KH |
1407 | case rp_sprel: |
1408 | r = 1; | |
1409 | break; | |
1410 | case pfs_sprel: | |
1411 | r = 2; | |
1412 | break; | |
1413 | case preds_sprel: | |
1414 | r = 3; | |
1415 | break; | |
1416 | case lc_sprel: | |
1417 | r = 4; | |
1418 | break; | |
1419 | case unat_sprel: | |
1420 | r = 5; | |
1421 | break; | |
1422 | case fpsr_sprel: | |
1423 | r = 6; | |
1424 | break; | |
1425 | case bsp_when: | |
1426 | r = 7; | |
1427 | break; | |
1428 | case bsp_psprel: | |
1429 | r = 8; | |
1430 | break; | |
1431 | case bsp_sprel: | |
1432 | r = 9; | |
1433 | break; | |
1434 | case bspstore_when: | |
1435 | r = 10; | |
1436 | break; | |
1437 | case bspstore_psprel: | |
1438 | r = 11; | |
1439 | break; | |
1440 | case bspstore_sprel: | |
1441 | r = 12; | |
1442 | break; | |
1443 | case rnat_when: | |
1444 | r = 13; | |
1445 | break; | |
1446 | case rnat_psprel: | |
1447 | r = 14; | |
1448 | break; | |
1449 | case rnat_sprel: | |
1450 | r = 15; | |
1451 | break; | |
1452 | case priunat_when_gr: | |
1453 | r = 16; | |
1454 | break; | |
1455 | case priunat_psprel: | |
1456 | r = 17; | |
1457 | break; | |
1458 | case priunat_sprel: | |
1459 | r = 18; | |
1460 | break; | |
1461 | case priunat_when_mem: | |
1462 | r = 19; | |
1463 | break; | |
1464 | default: | |
1465 | break; | |
800eeca4 JW |
1466 | } |
1467 | bytes[1] = r; | |
1468 | count += output_leb128 (bytes + 2, t, 0); | |
1469 | (*f) (count, bytes, NULL); | |
1470 | } | |
1471 | ||
1472 | static void | |
1473 | output_P9_format (f, grmask, gr) | |
1474 | vbyte_func f; | |
1475 | int grmask; | |
1476 | int gr; | |
1477 | { | |
1478 | char bytes[3]; | |
1479 | bytes[0] = UNW_P9; | |
1480 | bytes[1] = (grmask & 0x0f); | |
1481 | bytes[2] = (gr & 0x7f); | |
1482 | (*f) (3, bytes, NULL); | |
1483 | } | |
1484 | ||
1485 | static void | |
1486 | output_P10_format (f, abi, context) | |
1487 | vbyte_func f; | |
1488 | int abi; | |
1489 | int context; | |
1490 | { | |
1491 | char bytes[3]; | |
1492 | bytes[0] = UNW_P10; | |
1493 | bytes[1] = (abi & 0xff); | |
1494 | bytes[2] = (context & 0xff); | |
1495 | (*f) (3, bytes, NULL); | |
1496 | } | |
1497 | ||
1498 | static void | |
1499 | output_B1_format (f, rtype, label) | |
1500 | vbyte_func f; | |
1501 | unw_record_type rtype; | |
1502 | unsigned long label; | |
1503 | { | |
1504 | char byte; | |
e0c9811a | 1505 | int r = 0; |
197865e8 | 1506 | if (label > 0x1f) |
800eeca4 JW |
1507 | { |
1508 | output_B4_format (f, rtype, label); | |
1509 | return; | |
1510 | } | |
e0c9811a JW |
1511 | if (rtype == copy_state) |
1512 | r = 1; | |
1513 | else if (rtype != label_state) | |
1514 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1515 | |
1516 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); | |
1517 | (*f) (1, &byte, NULL); | |
1518 | } | |
1519 | ||
1520 | static void | |
1521 | output_B2_format (f, ecount, t) | |
1522 | vbyte_func f; | |
1523 | unsigned long ecount; | |
1524 | unsigned long t; | |
1525 | { | |
1526 | char bytes[20]; | |
1527 | int count = 1; | |
1528 | if (ecount > 0x1f) | |
1529 | { | |
1530 | output_B3_format (f, ecount, t); | |
1531 | return; | |
1532 | } | |
1533 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); | |
1534 | count += output_leb128 (bytes + 1, t, 0); | |
1535 | (*f) (count, bytes, NULL); | |
1536 | } | |
1537 | ||
1538 | static void | |
1539 | output_B3_format (f, ecount, t) | |
1540 | vbyte_func f; | |
1541 | unsigned long ecount; | |
1542 | unsigned long t; | |
1543 | { | |
1544 | char bytes[20]; | |
1545 | int count = 1; | |
1546 | if (ecount <= 0x1f) | |
1547 | { | |
1548 | output_B2_format (f, ecount, t); | |
1549 | return; | |
1550 | } | |
1551 | bytes[0] = UNW_B3; | |
1552 | count += output_leb128 (bytes + 1, t, 0); | |
1553 | count += output_leb128 (bytes + count, ecount, 0); | |
1554 | (*f) (count, bytes, NULL); | |
1555 | } | |
1556 | ||
1557 | static void | |
1558 | output_B4_format (f, rtype, label) | |
1559 | vbyte_func f; | |
1560 | unw_record_type rtype; | |
1561 | unsigned long label; | |
1562 | { | |
1563 | char bytes[20]; | |
e0c9811a | 1564 | int r = 0; |
800eeca4 | 1565 | int count = 1; |
197865e8 | 1566 | if (label <= 0x1f) |
800eeca4 JW |
1567 | { |
1568 | output_B1_format (f, rtype, label); | |
1569 | return; | |
1570 | } | |
197865e8 | 1571 | |
e0c9811a JW |
1572 | if (rtype == copy_state) |
1573 | r = 1; | |
1574 | else if (rtype != label_state) | |
1575 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1576 | |
1577 | bytes[0] = (UNW_B4 | (r << 3)); | |
1578 | count += output_leb128 (bytes + 1, label, 0); | |
1579 | (*f) (count, bytes, NULL); | |
1580 | } | |
1581 | ||
1582 | static char | |
e0c9811a | 1583 | format_ab_reg (ab, reg) |
542d6675 KH |
1584 | int ab; |
1585 | int reg; | |
800eeca4 JW |
1586 | { |
1587 | int ret; | |
e0c9811a | 1588 | ab = (ab & 3); |
800eeca4 | 1589 | reg = (reg & 0x1f); |
e0c9811a | 1590 | ret = (ab << 5) | reg; |
800eeca4 JW |
1591 | return ret; |
1592 | } | |
1593 | ||
1594 | static void | |
e0c9811a | 1595 | output_X1_format (f, rtype, ab, reg, t, w1) |
800eeca4 JW |
1596 | vbyte_func f; |
1597 | unw_record_type rtype; | |
e0c9811a | 1598 | int ab, reg; |
800eeca4 JW |
1599 | unsigned long t; |
1600 | unsigned long w1; | |
1601 | { | |
1602 | char bytes[20]; | |
e0c9811a | 1603 | int r = 0; |
800eeca4 JW |
1604 | int count = 2; |
1605 | bytes[0] = UNW_X1; | |
197865e8 | 1606 | |
e0c9811a JW |
1607 | if (rtype == spill_sprel) |
1608 | r = 1; | |
1609 | else if (rtype != spill_psprel) | |
1610 | as_bad ("Invalid record type for format X1"); | |
1611 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); | |
800eeca4 JW |
1612 | count += output_leb128 (bytes + 2, t, 0); |
1613 | count += output_leb128 (bytes + count, w1, 0); | |
1614 | (*f) (count, bytes, NULL); | |
1615 | } | |
1616 | ||
1617 | static void | |
e0c9811a | 1618 | output_X2_format (f, ab, reg, x, y, treg, t) |
800eeca4 | 1619 | vbyte_func f; |
e0c9811a | 1620 | int ab, reg; |
800eeca4 JW |
1621 | int x, y, treg; |
1622 | unsigned long t; | |
1623 | { | |
1624 | char bytes[20]; | |
800eeca4 JW |
1625 | int count = 3; |
1626 | bytes[0] = UNW_X2; | |
e0c9811a | 1627 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1628 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
1629 | count += output_leb128 (bytes + 3, t, 0); | |
1630 | (*f) (count, bytes, NULL); | |
1631 | } | |
1632 | ||
1633 | static void | |
e0c9811a | 1634 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
800eeca4 JW |
1635 | vbyte_func f; |
1636 | unw_record_type rtype; | |
1637 | int qp; | |
e0c9811a | 1638 | int ab, reg; |
800eeca4 JW |
1639 | unsigned long t; |
1640 | unsigned long w1; | |
1641 | { | |
1642 | char bytes[20]; | |
e0c9811a | 1643 | int r = 0; |
800eeca4 | 1644 | int count = 3; |
e0c9811a JW |
1645 | bytes[0] = UNW_X3; |
1646 | ||
1647 | if (rtype == spill_sprel_p) | |
1648 | r = 1; | |
1649 | else if (rtype != spill_psprel_p) | |
1650 | as_bad ("Invalid record type for format X3"); | |
800eeca4 | 1651 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
e0c9811a | 1652 | bytes[2] = format_ab_reg (ab, reg); |
800eeca4 JW |
1653 | count += output_leb128 (bytes + 3, t, 0); |
1654 | count += output_leb128 (bytes + count, w1, 0); | |
1655 | (*f) (count, bytes, NULL); | |
1656 | } | |
1657 | ||
1658 | static void | |
e0c9811a | 1659 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
800eeca4 JW |
1660 | vbyte_func f; |
1661 | int qp; | |
e0c9811a | 1662 | int ab, reg; |
800eeca4 JW |
1663 | int x, y, treg; |
1664 | unsigned long t; | |
1665 | { | |
1666 | char bytes[20]; | |
800eeca4 | 1667 | int count = 4; |
e0c9811a | 1668 | bytes[0] = UNW_X4; |
800eeca4 | 1669 | bytes[1] = (qp & 0x3f); |
e0c9811a | 1670 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1671 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
1672 | count += output_leb128 (bytes + 4, t, 0); | |
1673 | (*f) (count, bytes, NULL); | |
1674 | } | |
1675 | ||
1676 | /* This function allocates a record list structure, and initializes fields. */ | |
542d6675 | 1677 | |
800eeca4 | 1678 | static unw_rec_list * |
197865e8 | 1679 | alloc_record (unw_record_type t) |
800eeca4 JW |
1680 | { |
1681 | unw_rec_list *ptr; | |
1682 | ptr = xmalloc (sizeof (*ptr)); | |
1683 | ptr->next = NULL; | |
1684 | ptr->slot_number = SLOT_NUM_NOT_SET; | |
1685 | ptr->r.type = t; | |
1686 | return ptr; | |
1687 | } | |
1688 | ||
800eeca4 | 1689 | /* This function frees an entire list of record structures. */ |
542d6675 | 1690 | |
800eeca4 JW |
1691 | void |
1692 | free_list_records (unw_rec_list *first) | |
1693 | { | |
1694 | unw_rec_list *ptr; | |
542d6675 | 1695 | for (ptr = first; ptr != NULL;) |
800eeca4 JW |
1696 | { |
1697 | unw_rec_list *tmp = ptr; | |
e0c9811a JW |
1698 | |
1699 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) | |
1700 | && tmp->r.record.r.mask.i) | |
1701 | free (tmp->r.record.r.mask.i); | |
1702 | ||
800eeca4 JW |
1703 | ptr = ptr->next; |
1704 | free (tmp); | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | static unw_rec_list * | |
1709 | output_prologue () | |
1710 | { | |
1711 | unw_rec_list *ptr = alloc_record (prologue); | |
e0c9811a | 1712 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
800eeca4 JW |
1713 | return ptr; |
1714 | } | |
1715 | ||
1716 | static unw_rec_list * | |
1717 | output_prologue_gr (saved_mask, reg) | |
1718 | unsigned int saved_mask; | |
1719 | unsigned int reg; | |
1720 | { | |
1721 | unw_rec_list *ptr = alloc_record (prologue_gr); | |
e0c9811a JW |
1722 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
1723 | ptr->r.record.r.grmask = saved_mask; | |
800eeca4 JW |
1724 | ptr->r.record.r.grsave = reg; |
1725 | return ptr; | |
1726 | } | |
1727 | ||
1728 | static unw_rec_list * | |
1729 | output_body () | |
1730 | { | |
1731 | unw_rec_list *ptr = alloc_record (body); | |
1732 | return ptr; | |
1733 | } | |
1734 | ||
1735 | static unw_rec_list * | |
1736 | output_mem_stack_f (size) | |
1737 | unsigned int size; | |
1738 | { | |
1739 | unw_rec_list *ptr = alloc_record (mem_stack_f); | |
1740 | ptr->r.record.p.size = size; | |
1741 | return ptr; | |
1742 | } | |
1743 | ||
1744 | static unw_rec_list * | |
1745 | output_mem_stack_v () | |
1746 | { | |
1747 | unw_rec_list *ptr = alloc_record (mem_stack_v); | |
1748 | return ptr; | |
1749 | } | |
1750 | ||
1751 | static unw_rec_list * | |
1752 | output_psp_gr (gr) | |
1753 | unsigned int gr; | |
1754 | { | |
1755 | unw_rec_list *ptr = alloc_record (psp_gr); | |
1756 | ptr->r.record.p.gr = gr; | |
1757 | return ptr; | |
1758 | } | |
1759 | ||
1760 | static unw_rec_list * | |
1761 | output_psp_sprel (offset) | |
1762 | unsigned int offset; | |
1763 | { | |
1764 | unw_rec_list *ptr = alloc_record (psp_sprel); | |
542d6675 | 1765 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1766 | return ptr; |
1767 | } | |
1768 | ||
1769 | static unw_rec_list * | |
1770 | output_rp_when () | |
1771 | { | |
1772 | unw_rec_list *ptr = alloc_record (rp_when); | |
1773 | return ptr; | |
1774 | } | |
1775 | ||
1776 | static unw_rec_list * | |
1777 | output_rp_gr (gr) | |
1778 | unsigned int gr; | |
1779 | { | |
1780 | unw_rec_list *ptr = alloc_record (rp_gr); | |
1781 | ptr->r.record.p.gr = gr; | |
1782 | return ptr; | |
1783 | } | |
1784 | ||
1785 | static unw_rec_list * | |
1786 | output_rp_br (br) | |
1787 | unsigned int br; | |
1788 | { | |
1789 | unw_rec_list *ptr = alloc_record (rp_br); | |
1790 | ptr->r.record.p.br = br; | |
1791 | return ptr; | |
1792 | } | |
1793 | ||
1794 | static unw_rec_list * | |
1795 | output_rp_psprel (offset) | |
1796 | unsigned int offset; | |
1797 | { | |
1798 | unw_rec_list *ptr = alloc_record (rp_psprel); | |
542d6675 | 1799 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1800 | return ptr; |
1801 | } | |
1802 | ||
1803 | static unw_rec_list * | |
1804 | output_rp_sprel (offset) | |
1805 | unsigned int offset; | |
1806 | { | |
1807 | unw_rec_list *ptr = alloc_record (rp_sprel); | |
542d6675 | 1808 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1809 | return ptr; |
1810 | } | |
1811 | ||
1812 | static unw_rec_list * | |
1813 | output_pfs_when () | |
1814 | { | |
1815 | unw_rec_list *ptr = alloc_record (pfs_when); | |
1816 | return ptr; | |
1817 | } | |
1818 | ||
1819 | static unw_rec_list * | |
1820 | output_pfs_gr (gr) | |
1821 | unsigned int gr; | |
1822 | { | |
1823 | unw_rec_list *ptr = alloc_record (pfs_gr); | |
1824 | ptr->r.record.p.gr = gr; | |
1825 | return ptr; | |
1826 | } | |
1827 | ||
1828 | static unw_rec_list * | |
1829 | output_pfs_psprel (offset) | |
1830 | unsigned int offset; | |
1831 | { | |
1832 | unw_rec_list *ptr = alloc_record (pfs_psprel); | |
542d6675 | 1833 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1834 | return ptr; |
1835 | } | |
1836 | ||
1837 | static unw_rec_list * | |
1838 | output_pfs_sprel (offset) | |
1839 | unsigned int offset; | |
1840 | { | |
1841 | unw_rec_list *ptr = alloc_record (pfs_sprel); | |
542d6675 | 1842 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1843 | return ptr; |
1844 | } | |
1845 | ||
1846 | static unw_rec_list * | |
1847 | output_preds_when () | |
1848 | { | |
1849 | unw_rec_list *ptr = alloc_record (preds_when); | |
1850 | return ptr; | |
1851 | } | |
1852 | ||
1853 | static unw_rec_list * | |
1854 | output_preds_gr (gr) | |
1855 | unsigned int gr; | |
1856 | { | |
1857 | unw_rec_list *ptr = alloc_record (preds_gr); | |
1858 | ptr->r.record.p.gr = gr; | |
1859 | return ptr; | |
1860 | } | |
1861 | ||
1862 | static unw_rec_list * | |
1863 | output_preds_psprel (offset) | |
1864 | unsigned int offset; | |
1865 | { | |
1866 | unw_rec_list *ptr = alloc_record (preds_psprel); | |
542d6675 | 1867 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1868 | return ptr; |
1869 | } | |
1870 | ||
1871 | static unw_rec_list * | |
1872 | output_preds_sprel (offset) | |
1873 | unsigned int offset; | |
1874 | { | |
1875 | unw_rec_list *ptr = alloc_record (preds_sprel); | |
542d6675 | 1876 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1877 | return ptr; |
1878 | } | |
1879 | ||
1880 | static unw_rec_list * | |
1881 | output_fr_mem (mask) | |
1882 | unsigned int mask; | |
1883 | { | |
1884 | unw_rec_list *ptr = alloc_record (fr_mem); | |
1885 | ptr->r.record.p.rmask = mask; | |
1886 | return ptr; | |
1887 | } | |
1888 | ||
1889 | static unw_rec_list * | |
1890 | output_frgr_mem (gr_mask, fr_mask) | |
1891 | unsigned int gr_mask; | |
1892 | unsigned int fr_mask; | |
1893 | { | |
1894 | unw_rec_list *ptr = alloc_record (frgr_mem); | |
1895 | ptr->r.record.p.grmask = gr_mask; | |
1896 | ptr->r.record.p.frmask = fr_mask; | |
1897 | return ptr; | |
1898 | } | |
1899 | ||
1900 | static unw_rec_list * | |
1901 | output_gr_gr (mask, reg) | |
1902 | unsigned int mask; | |
1903 | unsigned int reg; | |
1904 | { | |
1905 | unw_rec_list *ptr = alloc_record (gr_gr); | |
1906 | ptr->r.record.p.grmask = mask; | |
1907 | ptr->r.record.p.gr = reg; | |
1908 | return ptr; | |
1909 | } | |
1910 | ||
1911 | static unw_rec_list * | |
1912 | output_gr_mem (mask) | |
1913 | unsigned int mask; | |
1914 | { | |
1915 | unw_rec_list *ptr = alloc_record (gr_mem); | |
1916 | ptr->r.record.p.rmask = mask; | |
1917 | return ptr; | |
1918 | } | |
1919 | ||
1920 | static unw_rec_list * | |
1921 | output_br_mem (unsigned int mask) | |
1922 | { | |
1923 | unw_rec_list *ptr = alloc_record (br_mem); | |
1924 | ptr->r.record.p.brmask = mask; | |
1925 | return ptr; | |
1926 | } | |
1927 | ||
1928 | static unw_rec_list * | |
1929 | output_br_gr (save_mask, reg) | |
1930 | unsigned int save_mask; | |
1931 | unsigned int reg; | |
1932 | { | |
1933 | unw_rec_list *ptr = alloc_record (br_gr); | |
1934 | ptr->r.record.p.brmask = save_mask; | |
1935 | ptr->r.record.p.gr = reg; | |
1936 | return ptr; | |
1937 | } | |
1938 | ||
1939 | static unw_rec_list * | |
1940 | output_spill_base (offset) | |
1941 | unsigned int offset; | |
1942 | { | |
1943 | unw_rec_list *ptr = alloc_record (spill_base); | |
542d6675 | 1944 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1945 | return ptr; |
1946 | } | |
1947 | ||
1948 | static unw_rec_list * | |
1949 | output_unat_when () | |
1950 | { | |
1951 | unw_rec_list *ptr = alloc_record (unat_when); | |
1952 | return ptr; | |
1953 | } | |
1954 | ||
1955 | static unw_rec_list * | |
1956 | output_unat_gr (gr) | |
1957 | unsigned int gr; | |
1958 | { | |
1959 | unw_rec_list *ptr = alloc_record (unat_gr); | |
1960 | ptr->r.record.p.gr = gr; | |
1961 | return ptr; | |
1962 | } | |
1963 | ||
1964 | static unw_rec_list * | |
1965 | output_unat_psprel (offset) | |
1966 | unsigned int offset; | |
1967 | { | |
1968 | unw_rec_list *ptr = alloc_record (unat_psprel); | |
542d6675 | 1969 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1970 | return ptr; |
1971 | } | |
1972 | ||
1973 | static unw_rec_list * | |
1974 | output_unat_sprel (offset) | |
1975 | unsigned int offset; | |
1976 | { | |
1977 | unw_rec_list *ptr = alloc_record (unat_sprel); | |
542d6675 | 1978 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1979 | return ptr; |
1980 | } | |
1981 | ||
1982 | static unw_rec_list * | |
1983 | output_lc_when () | |
1984 | { | |
1985 | unw_rec_list *ptr = alloc_record (lc_when); | |
1986 | return ptr; | |
1987 | } | |
1988 | ||
1989 | static unw_rec_list * | |
1990 | output_lc_gr (gr) | |
1991 | unsigned int gr; | |
1992 | { | |
1993 | unw_rec_list *ptr = alloc_record (lc_gr); | |
1994 | ptr->r.record.p.gr = gr; | |
1995 | return ptr; | |
1996 | } | |
1997 | ||
1998 | static unw_rec_list * | |
1999 | output_lc_psprel (offset) | |
2000 | unsigned int offset; | |
2001 | { | |
2002 | unw_rec_list *ptr = alloc_record (lc_psprel); | |
542d6675 | 2003 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2004 | return ptr; |
2005 | } | |
2006 | ||
2007 | static unw_rec_list * | |
2008 | output_lc_sprel (offset) | |
2009 | unsigned int offset; | |
2010 | { | |
2011 | unw_rec_list *ptr = alloc_record (lc_sprel); | |
542d6675 | 2012 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2013 | return ptr; |
2014 | } | |
2015 | ||
2016 | static unw_rec_list * | |
2017 | output_fpsr_when () | |
2018 | { | |
2019 | unw_rec_list *ptr = alloc_record (fpsr_when); | |
2020 | return ptr; | |
2021 | } | |
2022 | ||
2023 | static unw_rec_list * | |
2024 | output_fpsr_gr (gr) | |
2025 | unsigned int gr; | |
2026 | { | |
2027 | unw_rec_list *ptr = alloc_record (fpsr_gr); | |
2028 | ptr->r.record.p.gr = gr; | |
2029 | return ptr; | |
2030 | } | |
2031 | ||
2032 | static unw_rec_list * | |
2033 | output_fpsr_psprel (offset) | |
2034 | unsigned int offset; | |
2035 | { | |
2036 | unw_rec_list *ptr = alloc_record (fpsr_psprel); | |
542d6675 | 2037 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2038 | return ptr; |
2039 | } | |
2040 | ||
2041 | static unw_rec_list * | |
2042 | output_fpsr_sprel (offset) | |
2043 | unsigned int offset; | |
2044 | { | |
2045 | unw_rec_list *ptr = alloc_record (fpsr_sprel); | |
542d6675 | 2046 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2047 | return ptr; |
2048 | } | |
2049 | ||
2050 | static unw_rec_list * | |
2051 | output_priunat_when_gr () | |
2052 | { | |
2053 | unw_rec_list *ptr = alloc_record (priunat_when_gr); | |
2054 | return ptr; | |
2055 | } | |
2056 | ||
2057 | static unw_rec_list * | |
2058 | output_priunat_when_mem () | |
2059 | { | |
2060 | unw_rec_list *ptr = alloc_record (priunat_when_mem); | |
2061 | return ptr; | |
2062 | } | |
2063 | ||
2064 | static unw_rec_list * | |
2065 | output_priunat_gr (gr) | |
2066 | unsigned int gr; | |
2067 | { | |
2068 | unw_rec_list *ptr = alloc_record (priunat_gr); | |
2069 | ptr->r.record.p.gr = gr; | |
2070 | return ptr; | |
2071 | } | |
2072 | ||
2073 | static unw_rec_list * | |
2074 | output_priunat_psprel (offset) | |
2075 | unsigned int offset; | |
2076 | { | |
2077 | unw_rec_list *ptr = alloc_record (priunat_psprel); | |
542d6675 | 2078 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2079 | return ptr; |
2080 | } | |
2081 | ||
2082 | static unw_rec_list * | |
2083 | output_priunat_sprel (offset) | |
2084 | unsigned int offset; | |
2085 | { | |
2086 | unw_rec_list *ptr = alloc_record (priunat_sprel); | |
542d6675 | 2087 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2088 | return ptr; |
2089 | } | |
2090 | ||
2091 | static unw_rec_list * | |
2092 | output_bsp_when () | |
2093 | { | |
2094 | unw_rec_list *ptr = alloc_record (bsp_when); | |
2095 | return ptr; | |
2096 | } | |
2097 | ||
2098 | static unw_rec_list * | |
2099 | output_bsp_gr (gr) | |
2100 | unsigned int gr; | |
2101 | { | |
2102 | unw_rec_list *ptr = alloc_record (bsp_gr); | |
2103 | ptr->r.record.p.gr = gr; | |
2104 | return ptr; | |
2105 | } | |
2106 | ||
2107 | static unw_rec_list * | |
2108 | output_bsp_psprel (offset) | |
2109 | unsigned int offset; | |
2110 | { | |
2111 | unw_rec_list *ptr = alloc_record (bsp_psprel); | |
542d6675 | 2112 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2113 | return ptr; |
2114 | } | |
2115 | ||
2116 | static unw_rec_list * | |
2117 | output_bsp_sprel (offset) | |
2118 | unsigned int offset; | |
2119 | { | |
2120 | unw_rec_list *ptr = alloc_record (bsp_sprel); | |
542d6675 | 2121 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2122 | return ptr; |
2123 | } | |
2124 | ||
2125 | static unw_rec_list * | |
2126 | output_bspstore_when () | |
2127 | { | |
2128 | unw_rec_list *ptr = alloc_record (bspstore_when); | |
2129 | return ptr; | |
2130 | } | |
2131 | ||
2132 | static unw_rec_list * | |
2133 | output_bspstore_gr (gr) | |
2134 | unsigned int gr; | |
2135 | { | |
2136 | unw_rec_list *ptr = alloc_record (bspstore_gr); | |
2137 | ptr->r.record.p.gr = gr; | |
2138 | return ptr; | |
2139 | } | |
2140 | ||
2141 | static unw_rec_list * | |
2142 | output_bspstore_psprel (offset) | |
2143 | unsigned int offset; | |
2144 | { | |
2145 | unw_rec_list *ptr = alloc_record (bspstore_psprel); | |
542d6675 | 2146 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2147 | return ptr; |
2148 | } | |
2149 | ||
2150 | static unw_rec_list * | |
2151 | output_bspstore_sprel (offset) | |
2152 | unsigned int offset; | |
2153 | { | |
2154 | unw_rec_list *ptr = alloc_record (bspstore_sprel); | |
542d6675 | 2155 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2156 | return ptr; |
2157 | } | |
2158 | ||
2159 | static unw_rec_list * | |
2160 | output_rnat_when () | |
2161 | { | |
2162 | unw_rec_list *ptr = alloc_record (rnat_when); | |
2163 | return ptr; | |
2164 | } | |
2165 | ||
2166 | static unw_rec_list * | |
2167 | output_rnat_gr (gr) | |
2168 | unsigned int gr; | |
2169 | { | |
2170 | unw_rec_list *ptr = alloc_record (rnat_gr); | |
2171 | ptr->r.record.p.gr = gr; | |
2172 | return ptr; | |
2173 | } | |
2174 | ||
2175 | static unw_rec_list * | |
2176 | output_rnat_psprel (offset) | |
2177 | unsigned int offset; | |
2178 | { | |
2179 | unw_rec_list *ptr = alloc_record (rnat_psprel); | |
542d6675 | 2180 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2181 | return ptr; |
2182 | } | |
2183 | ||
2184 | static unw_rec_list * | |
2185 | output_rnat_sprel (offset) | |
2186 | unsigned int offset; | |
2187 | { | |
2188 | unw_rec_list *ptr = alloc_record (rnat_sprel); | |
542d6675 | 2189 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2190 | return ptr; |
2191 | } | |
2192 | ||
2193 | static unw_rec_list * | |
e0c9811a JW |
2194 | output_unwabi (abi, context) |
2195 | unsigned long abi; | |
2196 | unsigned long context; | |
800eeca4 | 2197 | { |
e0c9811a JW |
2198 | unw_rec_list *ptr = alloc_record (unwabi); |
2199 | ptr->r.record.p.abi = abi; | |
2200 | ptr->r.record.p.context = context; | |
800eeca4 JW |
2201 | return ptr; |
2202 | } | |
2203 | ||
2204 | static unw_rec_list * | |
e0c9811a | 2205 | output_epilogue (unsigned long ecount) |
800eeca4 | 2206 | { |
e0c9811a JW |
2207 | unw_rec_list *ptr = alloc_record (epilogue); |
2208 | ptr->r.record.b.ecount = ecount; | |
800eeca4 JW |
2209 | return ptr; |
2210 | } | |
2211 | ||
2212 | static unw_rec_list * | |
e0c9811a | 2213 | output_label_state (unsigned long label) |
800eeca4 | 2214 | { |
e0c9811a JW |
2215 | unw_rec_list *ptr = alloc_record (label_state); |
2216 | ptr->r.record.b.label = label; | |
800eeca4 JW |
2217 | return ptr; |
2218 | } | |
2219 | ||
2220 | static unw_rec_list * | |
e0c9811a JW |
2221 | output_copy_state (unsigned long label) |
2222 | { | |
2223 | unw_rec_list *ptr = alloc_record (copy_state); | |
2224 | ptr->r.record.b.label = label; | |
2225 | return ptr; | |
2226 | } | |
2227 | ||
2228 | static unw_rec_list * | |
2229 | output_spill_psprel (ab, reg, offset) | |
2230 | unsigned int ab; | |
800eeca4 JW |
2231 | unsigned int reg; |
2232 | unsigned int offset; | |
2233 | { | |
2234 | unw_rec_list *ptr = alloc_record (spill_psprel); | |
e0c9811a | 2235 | ptr->r.record.x.ab = ab; |
800eeca4 | 2236 | ptr->r.record.x.reg = reg; |
542d6675 | 2237 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2238 | return ptr; |
2239 | } | |
2240 | ||
2241 | static unw_rec_list * | |
e0c9811a JW |
2242 | output_spill_sprel (ab, reg, offset) |
2243 | unsigned int ab; | |
800eeca4 JW |
2244 | unsigned int reg; |
2245 | unsigned int offset; | |
2246 | { | |
2247 | unw_rec_list *ptr = alloc_record (spill_sprel); | |
e0c9811a | 2248 | ptr->r.record.x.ab = ab; |
800eeca4 | 2249 | ptr->r.record.x.reg = reg; |
542d6675 | 2250 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2251 | return ptr; |
2252 | } | |
2253 | ||
2254 | static unw_rec_list * | |
e0c9811a JW |
2255 | output_spill_psprel_p (ab, reg, offset, predicate) |
2256 | unsigned int ab; | |
800eeca4 JW |
2257 | unsigned int reg; |
2258 | unsigned int offset; | |
2259 | unsigned int predicate; | |
2260 | { | |
2261 | unw_rec_list *ptr = alloc_record (spill_psprel_p); | |
e0c9811a | 2262 | ptr->r.record.x.ab = ab; |
800eeca4 | 2263 | ptr->r.record.x.reg = reg; |
542d6675 | 2264 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2265 | ptr->r.record.x.qp = predicate; |
2266 | return ptr; | |
2267 | } | |
2268 | ||
2269 | static unw_rec_list * | |
e0c9811a JW |
2270 | output_spill_sprel_p (ab, reg, offset, predicate) |
2271 | unsigned int ab; | |
800eeca4 JW |
2272 | unsigned int reg; |
2273 | unsigned int offset; | |
2274 | unsigned int predicate; | |
2275 | { | |
2276 | unw_rec_list *ptr = alloc_record (spill_sprel_p); | |
e0c9811a | 2277 | ptr->r.record.x.ab = ab; |
800eeca4 | 2278 | ptr->r.record.x.reg = reg; |
542d6675 | 2279 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2280 | ptr->r.record.x.qp = predicate; |
2281 | return ptr; | |
2282 | } | |
2283 | ||
2284 | static unw_rec_list * | |
e0c9811a JW |
2285 | output_spill_reg (ab, reg, targ_reg, xy) |
2286 | unsigned int ab; | |
800eeca4 JW |
2287 | unsigned int reg; |
2288 | unsigned int targ_reg; | |
2289 | unsigned int xy; | |
2290 | { | |
2291 | unw_rec_list *ptr = alloc_record (spill_reg); | |
e0c9811a | 2292 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2293 | ptr->r.record.x.reg = reg; |
2294 | ptr->r.record.x.treg = targ_reg; | |
2295 | ptr->r.record.x.xy = xy; | |
2296 | return ptr; | |
2297 | } | |
2298 | ||
2299 | static unw_rec_list * | |
e0c9811a JW |
2300 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
2301 | unsigned int ab; | |
800eeca4 JW |
2302 | unsigned int reg; |
2303 | unsigned int targ_reg; | |
2304 | unsigned int xy; | |
2305 | unsigned int predicate; | |
2306 | { | |
2307 | unw_rec_list *ptr = alloc_record (spill_reg_p); | |
e0c9811a | 2308 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2309 | ptr->r.record.x.reg = reg; |
2310 | ptr->r.record.x.treg = targ_reg; | |
2311 | ptr->r.record.x.xy = xy; | |
2312 | ptr->r.record.x.qp = predicate; | |
2313 | return ptr; | |
2314 | } | |
2315 | ||
197865e8 | 2316 | /* Given a unw_rec_list process the correct format with the |
800eeca4 | 2317 | specified function. */ |
542d6675 | 2318 | |
800eeca4 JW |
2319 | static void |
2320 | process_one_record (ptr, f) | |
2321 | unw_rec_list *ptr; | |
2322 | vbyte_func f; | |
2323 | { | |
e0c9811a JW |
2324 | unsigned long fr_mask, gr_mask; |
2325 | ||
197865e8 | 2326 | switch (ptr->r.type) |
800eeca4 | 2327 | { |
542d6675 KH |
2328 | case gr_mem: |
2329 | case fr_mem: | |
2330 | case br_mem: | |
2331 | case frgr_mem: | |
2332 | /* These are taken care of by prologue/prologue_gr. */ | |
2333 | break; | |
e0c9811a | 2334 | |
542d6675 KH |
2335 | case prologue_gr: |
2336 | case prologue: | |
2337 | if (ptr->r.type == prologue_gr) | |
2338 | output_R2_format (f, ptr->r.record.r.grmask, | |
2339 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); | |
2340 | else | |
800eeca4 | 2341 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
542d6675 KH |
2342 | |
2343 | /* Output descriptor(s) for union of register spills (if any). */ | |
2344 | gr_mask = ptr->r.record.r.mask.gr_mem; | |
2345 | fr_mask = ptr->r.record.r.mask.fr_mem; | |
2346 | if (fr_mask) | |
2347 | { | |
2348 | if ((fr_mask & ~0xfUL) == 0) | |
2349 | output_P6_format (f, fr_mem, fr_mask); | |
2350 | else | |
2351 | { | |
2352 | output_P5_format (f, gr_mask, fr_mask); | |
2353 | gr_mask = 0; | |
2354 | } | |
2355 | } | |
2356 | if (gr_mask) | |
2357 | output_P6_format (f, gr_mem, gr_mask); | |
2358 | if (ptr->r.record.r.mask.br_mem) | |
2359 | output_P1_format (f, ptr->r.record.r.mask.br_mem); | |
2360 | ||
2361 | /* output imask descriptor if necessary: */ | |
2362 | if (ptr->r.record.r.mask.i) | |
2363 | output_P4_format (f, ptr->r.record.r.mask.i, | |
2364 | ptr->r.record.r.imask_size); | |
2365 | break; | |
2366 | ||
2367 | case body: | |
2368 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); | |
2369 | break; | |
2370 | case mem_stack_f: | |
2371 | case mem_stack_v: | |
2372 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, | |
2373 | ptr->r.record.p.size); | |
2374 | break; | |
2375 | case psp_gr: | |
2376 | case rp_gr: | |
2377 | case pfs_gr: | |
2378 | case preds_gr: | |
2379 | case unat_gr: | |
2380 | case lc_gr: | |
2381 | case fpsr_gr: | |
2382 | case priunat_gr: | |
2383 | case bsp_gr: | |
2384 | case bspstore_gr: | |
2385 | case rnat_gr: | |
2386 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); | |
2387 | break; | |
2388 | case rp_br: | |
2389 | output_P3_format (f, rp_br, ptr->r.record.p.br); | |
2390 | break; | |
2391 | case psp_sprel: | |
2392 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); | |
2393 | break; | |
2394 | case rp_when: | |
2395 | case pfs_when: | |
2396 | case preds_when: | |
2397 | case unat_when: | |
2398 | case lc_when: | |
2399 | case fpsr_when: | |
2400 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); | |
2401 | break; | |
2402 | case rp_psprel: | |
2403 | case pfs_psprel: | |
2404 | case preds_psprel: | |
2405 | case unat_psprel: | |
2406 | case lc_psprel: | |
2407 | case fpsr_psprel: | |
2408 | case spill_base: | |
2409 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); | |
2410 | break; | |
2411 | case rp_sprel: | |
2412 | case pfs_sprel: | |
2413 | case preds_sprel: | |
2414 | case unat_sprel: | |
2415 | case lc_sprel: | |
2416 | case fpsr_sprel: | |
2417 | case priunat_sprel: | |
2418 | case bsp_sprel: | |
2419 | case bspstore_sprel: | |
2420 | case rnat_sprel: | |
2421 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); | |
2422 | break; | |
2423 | case gr_gr: | |
2424 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); | |
2425 | break; | |
2426 | case br_gr: | |
2427 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); | |
2428 | break; | |
2429 | case spill_mask: | |
2430 | as_bad ("spill_mask record unimplemented."); | |
2431 | break; | |
2432 | case priunat_when_gr: | |
2433 | case priunat_when_mem: | |
2434 | case bsp_when: | |
2435 | case bspstore_when: | |
2436 | case rnat_when: | |
2437 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); | |
2438 | break; | |
2439 | case priunat_psprel: | |
2440 | case bsp_psprel: | |
2441 | case bspstore_psprel: | |
2442 | case rnat_psprel: | |
2443 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); | |
2444 | break; | |
2445 | case unwabi: | |
2446 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); | |
2447 | break; | |
2448 | case epilogue: | |
2449 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); | |
2450 | break; | |
2451 | case label_state: | |
2452 | case copy_state: | |
2453 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); | |
2454 | break; | |
2455 | case spill_psprel: | |
2456 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2457 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2458 | ptr->r.record.x.pspoff); | |
2459 | break; | |
2460 | case spill_sprel: | |
2461 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2462 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2463 | ptr->r.record.x.spoff); | |
2464 | break; | |
2465 | case spill_reg: | |
2466 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2467 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, | |
2468 | ptr->r.record.x.treg, ptr->r.record.x.t); | |
2469 | break; | |
2470 | case spill_psprel_p: | |
2471 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2472 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2473 | ptr->r.record.x.t, ptr->r.record.x.pspoff); | |
2474 | break; | |
2475 | case spill_sprel_p: | |
2476 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2477 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2478 | ptr->r.record.x.t, ptr->r.record.x.spoff); | |
2479 | break; | |
2480 | case spill_reg_p: | |
2481 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, | |
2482 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, | |
2483 | ptr->r.record.x.xy, ptr->r.record.x.treg, | |
2484 | ptr->r.record.x.t); | |
2485 | break; | |
2486 | default: | |
2487 | as_bad ("record_type_not_valid"); | |
2488 | break; | |
800eeca4 JW |
2489 | } |
2490 | } | |
2491 | ||
197865e8 | 2492 | /* Given a unw_rec_list list, process all the records with |
800eeca4 JW |
2493 | the specified function. */ |
2494 | static void | |
2495 | process_unw_records (list, f) | |
2496 | unw_rec_list *list; | |
2497 | vbyte_func f; | |
2498 | { | |
2499 | unw_rec_list *ptr; | |
2500 | for (ptr = list; ptr; ptr = ptr->next) | |
2501 | process_one_record (ptr, f); | |
2502 | } | |
2503 | ||
2504 | /* Determine the size of a record list in bytes. */ | |
2505 | static int | |
2506 | calc_record_size (list) | |
2507 | unw_rec_list *list; | |
2508 | { | |
2509 | vbyte_count = 0; | |
2510 | process_unw_records (list, count_output); | |
2511 | return vbyte_count; | |
2512 | } | |
2513 | ||
e0c9811a JW |
2514 | /* Update IMASK bitmask to reflect the fact that one or more registers |
2515 | of type TYPE are saved starting at instruction with index T. If N | |
2516 | bits are set in REGMASK, it is assumed that instructions T through | |
2517 | T+N-1 save these registers. | |
2518 | ||
2519 | TYPE values: | |
2520 | 0: no save | |
2521 | 1: instruction saves next fp reg | |
2522 | 2: instruction saves next general reg | |
2523 | 3: instruction saves next branch reg */ | |
2524 | static void | |
2525 | set_imask (region, regmask, t, type) | |
2526 | unw_rec_list *region; | |
2527 | unsigned long regmask; | |
2528 | unsigned long t; | |
2529 | unsigned int type; | |
2530 | { | |
2531 | unsigned char *imask; | |
2532 | unsigned long imask_size; | |
2533 | unsigned int i; | |
2534 | int pos; | |
2535 | ||
2536 | imask = region->r.record.r.mask.i; | |
2537 | imask_size = region->r.record.r.imask_size; | |
2538 | if (!imask) | |
2539 | { | |
542d6675 | 2540 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
e0c9811a JW |
2541 | imask = xmalloc (imask_size); |
2542 | memset (imask, 0, imask_size); | |
2543 | ||
2544 | region->r.record.r.imask_size = imask_size; | |
2545 | region->r.record.r.mask.i = imask; | |
2546 | } | |
2547 | ||
542d6675 KH |
2548 | i = (t / 4) + 1; |
2549 | pos = 2 * (3 - t % 4); | |
e0c9811a JW |
2550 | while (regmask) |
2551 | { | |
2552 | if (i >= imask_size) | |
2553 | { | |
2554 | as_bad ("Ignoring attempt to spill beyond end of region"); | |
2555 | return; | |
2556 | } | |
2557 | ||
2558 | imask[i] |= (type & 0x3) << pos; | |
197865e8 | 2559 | |
e0c9811a JW |
2560 | regmask &= (regmask - 1); |
2561 | pos -= 2; | |
2562 | if (pos < 0) | |
2563 | { | |
2564 | pos = 0; | |
2565 | ++i; | |
2566 | } | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | static int | |
2571 | count_bits (unsigned long mask) | |
2572 | { | |
2573 | int n = 0; | |
2574 | ||
2575 | while (mask) | |
2576 | { | |
2577 | mask &= mask - 1; | |
2578 | ++n; | |
2579 | } | |
2580 | return n; | |
2581 | } | |
2582 | ||
f5a30c2e JW |
2583 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
2584 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag | |
2585 | containing FIRST_ADDR. */ | |
2586 | ||
e0c9811a | 2587 | unsigned long |
f5a30c2e JW |
2588 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
2589 | unsigned long slot_addr; | |
2590 | fragS *slot_frag; | |
2591 | unsigned long first_addr; | |
2592 | fragS *first_frag; | |
e0c9811a | 2593 | { |
f5a30c2e JW |
2594 | unsigned long index = 0; |
2595 | ||
2596 | /* First time we are called, the initial address and frag are invalid. */ | |
2597 | if (first_addr == 0) | |
2598 | return 0; | |
2599 | ||
2600 | /* If the two addresses are in different frags, then we need to add in | |
2601 | the remaining size of this frag, and then the entire size of intermediate | |
2602 | frags. */ | |
2603 | while (slot_frag != first_frag) | |
2604 | { | |
2605 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; | |
2606 | ||
2607 | /* Add in the full size of the frag converted to instruction slots. */ | |
2608 | index += 3 * (first_frag->fr_fix >> 4); | |
2609 | /* Subtract away the initial part before first_addr. */ | |
2610 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) | |
2611 | + ((first_addr & 0x3) - (start_addr & 0x3))); | |
e0c9811a | 2612 | |
f5a30c2e JW |
2613 | /* Move to the beginning of the next frag. */ |
2614 | first_frag = first_frag->fr_next; | |
2615 | first_addr = (unsigned long) &first_frag->fr_literal; | |
2616 | } | |
2617 | ||
2618 | /* Add in the used part of the last frag. */ | |
2619 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) | |
2620 | + ((slot_addr & 0x3) - (first_addr & 0x3))); | |
2621 | return index; | |
2622 | } | |
4a1805b1 | 2623 | |
91a2ae2a RH |
2624 | /* Optimize unwind record directives. */ |
2625 | ||
2626 | static unw_rec_list * | |
2627 | optimize_unw_records (list) | |
2628 | unw_rec_list *list; | |
2629 | { | |
2630 | if (!list) | |
2631 | return NULL; | |
2632 | ||
2633 | /* If the only unwind record is ".prologue" or ".prologue" followed | |
2634 | by ".body", then we can optimize the unwind directives away. */ | |
2635 | if (list->r.type == prologue | |
2636 | && (list->next == NULL | |
2637 | || (list->next->r.type == body && list->next->next == NULL))) | |
2638 | return NULL; | |
2639 | ||
2640 | return list; | |
2641 | } | |
2642 | ||
800eeca4 JW |
2643 | /* Given a complete record list, process any records which have |
2644 | unresolved fields, (ie length counts for a prologue). After | |
197865e8 | 2645 | this has been run, all neccessary information should be available |
800eeca4 | 2646 | within each record to generate an image. */ |
542d6675 | 2647 | |
800eeca4 JW |
2648 | static void |
2649 | fixup_unw_records (list) | |
2650 | unw_rec_list *list; | |
2651 | { | |
e0c9811a JW |
2652 | unw_rec_list *ptr, *region = 0; |
2653 | unsigned long first_addr = 0, rlen = 0, t; | |
f5a30c2e | 2654 | fragS *first_frag = 0; |
e0c9811a | 2655 | |
800eeca4 JW |
2656 | for (ptr = list; ptr; ptr = ptr->next) |
2657 | { | |
2658 | if (ptr->slot_number == SLOT_NUM_NOT_SET) | |
542d6675 | 2659 | as_bad (" Insn slot not set in unwind record."); |
f5a30c2e JW |
2660 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
2661 | first_addr, first_frag); | |
800eeca4 JW |
2662 | switch (ptr->r.type) |
2663 | { | |
542d6675 KH |
2664 | case prologue: |
2665 | case prologue_gr: | |
2666 | case body: | |
2667 | { | |
2668 | unw_rec_list *last; | |
2669 | int size, dir_len = 0; | |
2670 | unsigned long last_addr; | |
f5a30c2e | 2671 | fragS *last_frag; |
542d6675 KH |
2672 | |
2673 | first_addr = ptr->slot_number; | |
f5a30c2e | 2674 | first_frag = ptr->slot_frag; |
542d6675 KH |
2675 | ptr->slot_number = 0; |
2676 | /* Find either the next body/prologue start, or the end of | |
2677 | the list, and determine the size of the region. */ | |
2678 | last_addr = unwind.next_slot_number; | |
f5a30c2e | 2679 | last_frag = unwind.next_slot_frag; |
542d6675 KH |
2680 | for (last = ptr->next; last != NULL; last = last->next) |
2681 | if (last->r.type == prologue || last->r.type == prologue_gr | |
2682 | || last->r.type == body) | |
2683 | { | |
2684 | last_addr = last->slot_number; | |
f5a30c2e | 2685 | last_frag = last->slot_frag; |
542d6675 KH |
2686 | break; |
2687 | } | |
2688 | else if (!last->next) | |
2689 | { | |
2690 | /* In the absence of an explicit .body directive, | |
2691 | the prologue ends after the last instruction | |
2692 | covered by an unwind directive. */ | |
2693 | if (ptr->r.type != body) | |
2694 | { | |
2695 | last_addr = last->slot_number; | |
f5a30c2e | 2696 | last_frag = last->slot_frag; |
542d6675 KH |
2697 | switch (last->r.type) |
2698 | { | |
2699 | case frgr_mem: | |
2700 | dir_len = (count_bits (last->r.record.p.frmask) | |
2701 | + count_bits (last->r.record.p.grmask)); | |
2702 | break; | |
2703 | case fr_mem: | |
2704 | case gr_mem: | |
2705 | dir_len += count_bits (last->r.record.p.rmask); | |
2706 | break; | |
2707 | case br_mem: | |
2708 | case br_gr: | |
2709 | dir_len += count_bits (last->r.record.p.brmask); | |
2710 | break; | |
2711 | case gr_gr: | |
2712 | dir_len += count_bits (last->r.record.p.grmask); | |
2713 | break; | |
2714 | default: | |
2715 | dir_len = 1; | |
2716 | break; | |
2717 | } | |
2718 | } | |
2719 | break; | |
2720 | } | |
f5a30c2e JW |
2721 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
2722 | + dir_len); | |
542d6675 | 2723 | rlen = ptr->r.record.r.rlen = size; |
1e16b528 AS |
2724 | if (ptr->r.type == body) |
2725 | /* End of region. */ | |
2726 | region = 0; | |
2727 | else | |
2728 | region = ptr; | |
e0c9811a | 2729 | break; |
542d6675 KH |
2730 | } |
2731 | case epilogue: | |
2732 | ptr->r.record.b.t = rlen - 1 - t; | |
2733 | break; | |
e0c9811a | 2734 | |
542d6675 KH |
2735 | case mem_stack_f: |
2736 | case mem_stack_v: | |
2737 | case rp_when: | |
2738 | case pfs_when: | |
2739 | case preds_when: | |
2740 | case unat_when: | |
2741 | case lc_when: | |
2742 | case fpsr_when: | |
2743 | case priunat_when_gr: | |
2744 | case priunat_when_mem: | |
2745 | case bsp_when: | |
2746 | case bspstore_when: | |
2747 | case rnat_when: | |
2748 | ptr->r.record.p.t = t; | |
2749 | break; | |
e0c9811a | 2750 | |
542d6675 KH |
2751 | case spill_reg: |
2752 | case spill_sprel: | |
2753 | case spill_psprel: | |
2754 | case spill_reg_p: | |
2755 | case spill_sprel_p: | |
2756 | case spill_psprel_p: | |
2757 | ptr->r.record.x.t = t; | |
2758 | break; | |
e0c9811a | 2759 | |
542d6675 KH |
2760 | case frgr_mem: |
2761 | if (!region) | |
2762 | { | |
2763 | as_bad ("frgr_mem record before region record!\n"); | |
2764 | return; | |
2765 | } | |
2766 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; | |
2767 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; | |
2768 | set_imask (region, ptr->r.record.p.frmask, t, 1); | |
2769 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2770 | break; | |
2771 | case fr_mem: | |
2772 | if (!region) | |
2773 | { | |
2774 | as_bad ("fr_mem record before region record!\n"); | |
2775 | return; | |
2776 | } | |
2777 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; | |
2778 | set_imask (region, ptr->r.record.p.rmask, t, 1); | |
2779 | break; | |
2780 | case gr_mem: | |
2781 | if (!region) | |
2782 | { | |
2783 | as_bad ("gr_mem record before region record!\n"); | |
2784 | return; | |
2785 | } | |
2786 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; | |
2787 | set_imask (region, ptr->r.record.p.rmask, t, 2); | |
2788 | break; | |
2789 | case br_mem: | |
2790 | if (!region) | |
2791 | { | |
2792 | as_bad ("br_mem record before region record!\n"); | |
2793 | return; | |
2794 | } | |
2795 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; | |
2796 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2797 | break; | |
e0c9811a | 2798 | |
542d6675 KH |
2799 | case gr_gr: |
2800 | if (!region) | |
2801 | { | |
2802 | as_bad ("gr_gr record before region record!\n"); | |
2803 | return; | |
2804 | } | |
2805 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2806 | break; | |
2807 | case br_gr: | |
2808 | if (!region) | |
2809 | { | |
2810 | as_bad ("br_gr record before region record!\n"); | |
2811 | return; | |
2812 | } | |
2813 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2814 | break; | |
e0c9811a | 2815 | |
542d6675 KH |
2816 | default: |
2817 | break; | |
800eeca4 JW |
2818 | } |
2819 | } | |
2820 | } | |
2821 | ||
557debba JW |
2822 | /* Helper routine for output_unw_records. Emits the header for the unwind |
2823 | info. */ | |
2824 | ||
2825 | static int | |
07726851 | 2826 | setup_unwind_header (int size, unsigned char **mem) |
557debba JW |
2827 | { |
2828 | int x, extra = 0; | |
1cd8ff38 | 2829 | valueT flag_value; |
557debba JW |
2830 | |
2831 | /* pad to pointer-size boundry. */ | |
2832 | x = size % md.pointer_size; | |
2833 | if (x != 0) | |
2834 | extra = md.pointer_size - x; | |
2835 | ||
40449e9f | 2836 | /* Add 8 for the header + a pointer for the |
557debba JW |
2837 | personality offset. */ |
2838 | *mem = xmalloc (size + extra + 8 + md.pointer_size); | |
2839 | ||
2840 | /* Clear the padding area and personality. */ | |
40449e9f | 2841 | memset (*mem + 8 + size, 0, extra + md.pointer_size); |
1cd8ff38 | 2842 | |
557debba | 2843 | /* Initialize the header area. */ |
1cd8ff38 NC |
2844 | if (unwind.personality_routine) |
2845 | { | |
2846 | if (md.flags & EF_IA_64_ABI64) | |
2847 | flag_value = (bfd_vma) 3 << 32; | |
2848 | else | |
2849 | /* 32-bit unwind info block. */ | |
2850 | flag_value = (bfd_vma) 0x1003 << 32; | |
2851 | } | |
2852 | else | |
2853 | flag_value = 0; | |
557debba | 2854 | |
1cd8ff38 NC |
2855 | md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */ |
2856 | | flag_value /* U & E handler flags. */ | |
2857 | | ((size + extra) / md.pointer_size)), /* Length. */ | |
557debba JW |
2858 | 8); |
2859 | ||
2860 | return extra; | |
2861 | } | |
2862 | ||
800eeca4 JW |
2863 | /* Generate an unwind image from a record list. Returns the number of |
2864 | bytes in the resulting image. The memory image itselof is returned | |
2865 | in the 'ptr' parameter. */ | |
2866 | static int | |
2867 | output_unw_records (list, ptr) | |
2868 | unw_rec_list *list; | |
2869 | void **ptr; | |
2870 | { | |
557debba | 2871 | int size, extra; |
800eeca4 JW |
2872 | unsigned char *mem; |
2873 | ||
91a2ae2a RH |
2874 | *ptr = NULL; |
2875 | ||
2876 | list = optimize_unw_records (list); | |
800eeca4 JW |
2877 | fixup_unw_records (list); |
2878 | size = calc_record_size (list); | |
2879 | ||
91a2ae2a RH |
2880 | if (size > 0 || unwind.force_unwind_entry) |
2881 | { | |
2882 | unwind.force_unwind_entry = 0; | |
07726851 | 2883 | extra = setup_unwind_header (size, &mem); |
800eeca4 | 2884 | |
91a2ae2a | 2885 | vbyte_mem_ptr = mem + 8; |
91a2ae2a RH |
2886 | process_unw_records (list, output_vbyte_mem); |
2887 | ||
2888 | *ptr = mem; | |
2889 | ||
557debba | 2890 | size += extra + 8 + md.pointer_size; |
91a2ae2a RH |
2891 | } |
2892 | return size; | |
800eeca4 JW |
2893 | } |
2894 | ||
e0c9811a JW |
2895 | static int |
2896 | convert_expr_to_ab_reg (e, ab, regp) | |
2897 | expressionS *e; | |
2898 | unsigned int *ab; | |
2899 | unsigned int *regp; | |
2900 | { | |
2901 | unsigned int reg; | |
2902 | ||
2903 | if (e->X_op != O_register) | |
2904 | return 0; | |
2905 | ||
2906 | reg = e->X_add_number; | |
2434f565 | 2907 | if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) |
e0c9811a JW |
2908 | { |
2909 | *ab = 0; | |
2910 | *regp = reg - REG_GR; | |
2911 | } | |
2434f565 JW |
2912 | else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) |
2913 | || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) | |
e0c9811a JW |
2914 | { |
2915 | *ab = 1; | |
2916 | *regp = reg - REG_FR; | |
2917 | } | |
2434f565 | 2918 | else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) |
e0c9811a JW |
2919 | { |
2920 | *ab = 2; | |
2921 | *regp = reg - REG_BR; | |
2922 | } | |
2923 | else | |
2924 | { | |
2925 | *ab = 3; | |
2926 | switch (reg) | |
2927 | { | |
2928 | case REG_PR: *regp = 0; break; | |
2929 | case REG_PSP: *regp = 1; break; | |
2930 | case REG_PRIUNAT: *regp = 2; break; | |
2931 | case REG_BR + 0: *regp = 3; break; | |
2932 | case REG_AR + AR_BSP: *regp = 4; break; | |
2933 | case REG_AR + AR_BSPSTORE: *regp = 5; break; | |
2934 | case REG_AR + AR_RNAT: *regp = 6; break; | |
2935 | case REG_AR + AR_UNAT: *regp = 7; break; | |
2936 | case REG_AR + AR_FPSR: *regp = 8; break; | |
2937 | case REG_AR + AR_PFS: *regp = 9; break; | |
2938 | case REG_AR + AR_LC: *regp = 10; break; | |
2939 | ||
2940 | default: | |
2941 | return 0; | |
2942 | } | |
2943 | } | |
2944 | return 1; | |
197865e8 | 2945 | } |
e0c9811a JW |
2946 | |
2947 | static int | |
2948 | convert_expr_to_xy_reg (e, xy, regp) | |
2949 | expressionS *e; | |
2950 | unsigned int *xy; | |
2951 | unsigned int *regp; | |
2952 | { | |
2953 | unsigned int reg; | |
2954 | ||
2955 | if (e->X_op != O_register) | |
2956 | return 0; | |
2957 | ||
2958 | reg = e->X_add_number; | |
2959 | ||
2434f565 | 2960 | if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) |
e0c9811a JW |
2961 | { |
2962 | *xy = 0; | |
2963 | *regp = reg - REG_GR; | |
2964 | } | |
2434f565 | 2965 | else if (reg >= REG_FR && reg <= (REG_FR + 127)) |
e0c9811a JW |
2966 | { |
2967 | *xy = 1; | |
2968 | *regp = reg - REG_FR; | |
2969 | } | |
2434f565 | 2970 | else if (reg >= REG_BR && reg <= (REG_BR + 7)) |
e0c9811a JW |
2971 | { |
2972 | *xy = 2; | |
2973 | *regp = reg - REG_BR; | |
2974 | } | |
2975 | else | |
2976 | return -1; | |
2977 | return 1; | |
197865e8 | 2978 | } |
e0c9811a | 2979 | |
800eeca4 JW |
2980 | static void |
2981 | dot_radix (dummy) | |
2434f565 | 2982 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2983 | { |
2984 | int radix; | |
2985 | ||
2986 | SKIP_WHITESPACE (); | |
2987 | radix = *input_line_pointer++; | |
2988 | ||
2989 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) | |
2990 | { | |
2991 | as_bad ("Radix `%c' unsupported", *input_line_pointer); | |
542d6675 | 2992 | ignore_rest_of_line (); |
800eeca4 JW |
2993 | return; |
2994 | } | |
2995 | } | |
2996 | ||
2997 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ | |
2998 | static void | |
2999 | dot_special_section (which) | |
3000 | int which; | |
3001 | { | |
3002 | set_section ((char *) special_section_name[which]); | |
3003 | } | |
3004 | ||
3005 | static void | |
3006 | add_unwind_entry (ptr) | |
3007 | unw_rec_list *ptr; | |
3008 | { | |
e0c9811a JW |
3009 | if (unwind.tail) |
3010 | unwind.tail->next = ptr; | |
800eeca4 | 3011 | else |
e0c9811a JW |
3012 | unwind.list = ptr; |
3013 | unwind.tail = ptr; | |
800eeca4 JW |
3014 | |
3015 | /* The current entry can in fact be a chain of unwind entries. */ | |
e0c9811a JW |
3016 | if (unwind.current_entry == NULL) |
3017 | unwind.current_entry = ptr; | |
800eeca4 JW |
3018 | } |
3019 | ||
197865e8 | 3020 | static void |
800eeca4 | 3021 | dot_fframe (dummy) |
2434f565 | 3022 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3023 | { |
3024 | expressionS e; | |
e0c9811a | 3025 | |
800eeca4 | 3026 | parse_operand (&e); |
197865e8 | 3027 | |
800eeca4 JW |
3028 | if (e.X_op != O_constant) |
3029 | as_bad ("Operand to .fframe must be a constant"); | |
3030 | else | |
e0c9811a JW |
3031 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
3032 | } | |
3033 | ||
197865e8 | 3034 | static void |
e0c9811a | 3035 | dot_vframe (dummy) |
2434f565 | 3036 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3037 | { |
3038 | expressionS e; | |
3039 | unsigned reg; | |
3040 | ||
3041 | parse_operand (&e); | |
3042 | reg = e.X_add_number - REG_GR; | |
3043 | if (e.X_op == O_register && reg < 128) | |
800eeca4 | 3044 | { |
e0c9811a | 3045 | add_unwind_entry (output_mem_stack_v ()); |
30d25259 RH |
3046 | if (! (unwind.prologue_mask & 2)) |
3047 | add_unwind_entry (output_psp_gr (reg)); | |
800eeca4 | 3048 | } |
e0c9811a JW |
3049 | else |
3050 | as_bad ("First operand to .vframe must be a general register"); | |
800eeca4 JW |
3051 | } |
3052 | ||
197865e8 | 3053 | static void |
e0c9811a | 3054 | dot_vframesp (dummy) |
2434f565 | 3055 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3056 | { |
e0c9811a JW |
3057 | expressionS e; |
3058 | ||
3059 | parse_operand (&e); | |
3060 | if (e.X_op == O_constant) | |
3061 | { | |
3062 | add_unwind_entry (output_mem_stack_v ()); | |
3063 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
3064 | } | |
3065 | else | |
3066 | as_bad ("First operand to .vframesp must be a general register"); | |
3067 | } | |
3068 | ||
197865e8 | 3069 | static void |
e0c9811a | 3070 | dot_vframepsp (dummy) |
2434f565 | 3071 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3072 | { |
3073 | expressionS e; | |
3074 | ||
3075 | parse_operand (&e); | |
3076 | if (e.X_op == O_constant) | |
3077 | { | |
3078 | add_unwind_entry (output_mem_stack_v ()); | |
3079 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
3080 | } | |
3081 | else | |
3082 | as_bad ("First operand to .vframepsp must be a general register"); | |
800eeca4 JW |
3083 | } |
3084 | ||
197865e8 | 3085 | static void |
800eeca4 | 3086 | dot_save (dummy) |
2434f565 | 3087 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3088 | { |
3089 | expressionS e1, e2; | |
3090 | int sep; | |
3091 | int reg1, reg2; | |
3092 | ||
3093 | sep = parse_operand (&e1); | |
3094 | if (sep != ',') | |
3095 | as_bad ("No second operand to .save"); | |
3096 | sep = parse_operand (&e2); | |
3097 | ||
e0c9811a | 3098 | reg1 = e1.X_add_number; |
800eeca4 | 3099 | reg2 = e2.X_add_number - REG_GR; |
197865e8 | 3100 | |
800eeca4 | 3101 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3102 | if (e1.X_op == O_register) |
800eeca4 | 3103 | { |
542d6675 | 3104 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
800eeca4 JW |
3105 | { |
3106 | switch (reg1) | |
3107 | { | |
542d6675 KH |
3108 | case REG_AR + AR_BSP: |
3109 | add_unwind_entry (output_bsp_when ()); | |
3110 | add_unwind_entry (output_bsp_gr (reg2)); | |
3111 | break; | |
3112 | case REG_AR + AR_BSPSTORE: | |
3113 | add_unwind_entry (output_bspstore_when ()); | |
3114 | add_unwind_entry (output_bspstore_gr (reg2)); | |
3115 | break; | |
3116 | case REG_AR + AR_RNAT: | |
3117 | add_unwind_entry (output_rnat_when ()); | |
3118 | add_unwind_entry (output_rnat_gr (reg2)); | |
3119 | break; | |
3120 | case REG_AR + AR_UNAT: | |
3121 | add_unwind_entry (output_unat_when ()); | |
3122 | add_unwind_entry (output_unat_gr (reg2)); | |
3123 | break; | |
3124 | case REG_AR + AR_FPSR: | |
3125 | add_unwind_entry (output_fpsr_when ()); | |
3126 | add_unwind_entry (output_fpsr_gr (reg2)); | |
3127 | break; | |
3128 | case REG_AR + AR_PFS: | |
3129 | add_unwind_entry (output_pfs_when ()); | |
3130 | if (! (unwind.prologue_mask & 4)) | |
3131 | add_unwind_entry (output_pfs_gr (reg2)); | |
3132 | break; | |
3133 | case REG_AR + AR_LC: | |
3134 | add_unwind_entry (output_lc_when ()); | |
3135 | add_unwind_entry (output_lc_gr (reg2)); | |
3136 | break; | |
3137 | case REG_BR: | |
3138 | add_unwind_entry (output_rp_when ()); | |
3139 | if (! (unwind.prologue_mask & 8)) | |
3140 | add_unwind_entry (output_rp_gr (reg2)); | |
3141 | break; | |
3142 | case REG_PR: | |
3143 | add_unwind_entry (output_preds_when ()); | |
3144 | if (! (unwind.prologue_mask & 1)) | |
3145 | add_unwind_entry (output_preds_gr (reg2)); | |
3146 | break; | |
3147 | case REG_PRIUNAT: | |
3148 | add_unwind_entry (output_priunat_when_gr ()); | |
3149 | add_unwind_entry (output_priunat_gr (reg2)); | |
3150 | break; | |
3151 | default: | |
3152 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3153 | } |
3154 | } | |
3155 | else | |
3156 | as_bad (" Second operand not a valid register"); | |
3157 | } | |
3158 | else | |
e0c9811a | 3159 | as_bad ("First operand not a register"); |
800eeca4 JW |
3160 | } |
3161 | ||
197865e8 | 3162 | static void |
800eeca4 | 3163 | dot_restore (dummy) |
2434f565 | 3164 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3165 | { |
e0c9811a | 3166 | expressionS e1, e2; |
33d01f33 | 3167 | unsigned long ecount; /* # of _additional_ regions to pop */ |
e0c9811a JW |
3168 | int sep; |
3169 | ||
3170 | sep = parse_operand (&e1); | |
3171 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) | |
3172 | { | |
3173 | as_bad ("First operand to .restore must be stack pointer (sp)"); | |
3174 | return; | |
3175 | } | |
3176 | ||
3177 | if (sep == ',') | |
3178 | { | |
3179 | parse_operand (&e2); | |
33d01f33 | 3180 | if (e2.X_op != O_constant || e2.X_add_number < 0) |
e0c9811a | 3181 | { |
33d01f33 | 3182 | as_bad ("Second operand to .restore must be a constant >= 0"); |
e0c9811a JW |
3183 | return; |
3184 | } | |
33d01f33 | 3185 | ecount = e2.X_add_number; |
e0c9811a | 3186 | } |
33d01f33 JW |
3187 | else |
3188 | ecount = unwind.prologue_count - 1; | |
6290819d NC |
3189 | |
3190 | if (ecount >= unwind.prologue_count) | |
3191 | { | |
3192 | as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)", | |
3193 | ecount + 1, unwind.prologue_count); | |
3194 | return; | |
3195 | } | |
3196 | ||
e0c9811a | 3197 | add_unwind_entry (output_epilogue (ecount)); |
33d01f33 JW |
3198 | |
3199 | if (ecount < unwind.prologue_count) | |
3200 | unwind.prologue_count -= ecount + 1; | |
3201 | else | |
3202 | unwind.prologue_count = 0; | |
e0c9811a JW |
3203 | } |
3204 | ||
197865e8 | 3205 | static void |
e0c9811a | 3206 | dot_restorereg (dummy) |
2434f565 | 3207 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3208 | { |
3209 | unsigned int ab, reg; | |
3210 | expressionS e; | |
3211 | ||
3212 | parse_operand (&e); | |
3213 | ||
3214 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) | |
3215 | { | |
3216 | as_bad ("First operand to .restorereg must be a preserved register"); | |
3217 | return; | |
3218 | } | |
3219 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); | |
3220 | } | |
3221 | ||
197865e8 | 3222 | static void |
e0c9811a | 3223 | dot_restorereg_p (dummy) |
2434f565 | 3224 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3225 | { |
3226 | unsigned int qp, ab, reg; | |
3227 | expressionS e1, e2; | |
3228 | int sep; | |
3229 | ||
3230 | sep = parse_operand (&e1); | |
3231 | if (sep != ',') | |
3232 | { | |
3233 | as_bad ("No second operand to .restorereg.p"); | |
3234 | return; | |
3235 | } | |
3236 | ||
3237 | parse_operand (&e2); | |
3238 | ||
3239 | qp = e1.X_add_number - REG_P; | |
3240 | if (e1.X_op != O_register || qp > 63) | |
3241 | { | |
3242 | as_bad ("First operand to .restorereg.p must be a predicate"); | |
3243 | return; | |
3244 | } | |
3245 | ||
3246 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3247 | { | |
3248 | as_bad ("Second operand to .restorereg.p must be a preserved register"); | |
3249 | return; | |
3250 | } | |
3251 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); | |
800eeca4 JW |
3252 | } |
3253 | ||
3254 | static int | |
91a2ae2a RH |
3255 | generate_unwind_image (text_name) |
3256 | const char *text_name; | |
800eeca4 JW |
3257 | { |
3258 | int size; | |
3259 | unsigned char *unw_rec; | |
800eeca4 | 3260 | |
10850f29 JW |
3261 | /* Force out pending instructions, to make sure all unwind records have |
3262 | a valid slot_number field. */ | |
3263 | ia64_flush_insns (); | |
3264 | ||
800eeca4 | 3265 | /* Generate the unwind record. */ |
150f24a2 | 3266 | size = output_unw_records (unwind.list, (void **) &unw_rec); |
557debba JW |
3267 | if (size % md.pointer_size != 0) |
3268 | as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size); | |
6290819d | 3269 | |
800eeca4 JW |
3270 | /* If there are unwind records, switch sections, and output the info. */ |
3271 | if (size != 0) | |
3272 | { | |
800eeca4 | 3273 | unsigned char *where; |
91a2ae2a | 3274 | char *sec_name; |
800eeca4 | 3275 | expressionS exp; |
1cd8ff38 | 3276 | bfd_reloc_code_real_type reloc; |
91a2ae2a RH |
3277 | |
3278 | make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); | |
3279 | set_section (sec_name); | |
3280 | bfd_set_section_flags (stdoutput, now_seg, | |
3281 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); | |
800eeca4 | 3282 | |
557debba JW |
3283 | /* Make sure the section has 4 byte alignment for ILP32 and |
3284 | 8 byte alignment for LP64. */ | |
3285 | frag_align (md.pointer_size_shift, 0, 0); | |
3286 | record_alignment (now_seg, md.pointer_size_shift); | |
5e7474a7 | 3287 | |
800eeca4 | 3288 | /* Set expression which points to start of unwind descriptor area. */ |
e0c9811a | 3289 | unwind.info = expr_build_dot (); |
800eeca4 | 3290 | |
542d6675 | 3291 | where = (unsigned char *) frag_more (size); |
800eeca4 JW |
3292 | |
3293 | /* Issue a label for this address, and keep track of it to put it | |
3294 | in the unwind section. */ | |
3295 | ||
3296 | /* Copy the information from the unwind record into this section. The | |
3297 | data is already in the correct byte order. */ | |
3298 | memcpy (where, unw_rec, size); | |
91a2ae2a | 3299 | |
800eeca4 | 3300 | /* Add the personality address to the image. */ |
e0c9811a | 3301 | if (unwind.personality_routine != 0) |
542d6675 | 3302 | { |
40449e9f | 3303 | exp.X_op = O_symbol; |
e0c9811a | 3304 | exp.X_add_symbol = unwind.personality_routine; |
800eeca4 | 3305 | exp.X_add_number = 0; |
1cd8ff38 NC |
3306 | |
3307 | if (md.flags & EF_IA_64_BE) | |
3308 | { | |
3309 | if (md.flags & EF_IA_64_ABI64) | |
3310 | reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; | |
3311 | else | |
3312 | reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; | |
3313 | } | |
40449e9f | 3314 | else |
1cd8ff38 NC |
3315 | { |
3316 | if (md.flags & EF_IA_64_ABI64) | |
3317 | reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; | |
3318 | else | |
3319 | reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; | |
3320 | } | |
3321 | ||
3322 | fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, | |
40449e9f | 3323 | md.pointer_size, &exp, 0, reloc); |
e0c9811a | 3324 | unwind.personality_routine = 0; |
542d6675 | 3325 | } |
800eeca4 JW |
3326 | } |
3327 | ||
e0c9811a | 3328 | free_list_records (unwind.list); |
6290819d | 3329 | free_saved_prologue_counts (); |
e0c9811a | 3330 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
800eeca4 JW |
3331 | |
3332 | return size; | |
3333 | } | |
3334 | ||
197865e8 | 3335 | static void |
542d6675 | 3336 | dot_handlerdata (dummy) |
2434f565 | 3337 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3338 | { |
91a2ae2a RH |
3339 | const char *text_name = segment_name (now_seg); |
3340 | ||
3341 | /* If text section name starts with ".text" (which it should), | |
3342 | strip this prefix off. */ | |
3343 | if (strcmp (text_name, ".text") == 0) | |
3344 | text_name = ""; | |
3345 | ||
3346 | unwind.force_unwind_entry = 1; | |
3347 | ||
3348 | /* Remember which segment we're in so we can switch back after .endp */ | |
3349 | unwind.saved_text_seg = now_seg; | |
3350 | unwind.saved_text_subseg = now_subseg; | |
3351 | ||
3352 | /* Generate unwind info into unwind-info section and then leave that | |
3353 | section as the currently active one so dataXX directives go into | |
3354 | the language specific data area of the unwind info block. */ | |
3355 | generate_unwind_image (text_name); | |
e0c9811a | 3356 | demand_empty_rest_of_line (); |
800eeca4 JW |
3357 | } |
3358 | ||
197865e8 | 3359 | static void |
800eeca4 | 3360 | dot_unwentry (dummy) |
2434f565 | 3361 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3362 | { |
91a2ae2a | 3363 | unwind.force_unwind_entry = 1; |
e0c9811a | 3364 | demand_empty_rest_of_line (); |
800eeca4 JW |
3365 | } |
3366 | ||
197865e8 | 3367 | static void |
800eeca4 | 3368 | dot_altrp (dummy) |
2434f565 | 3369 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3370 | { |
e0c9811a JW |
3371 | expressionS e; |
3372 | unsigned reg; | |
3373 | ||
3374 | parse_operand (&e); | |
3375 | reg = e.X_add_number - REG_BR; | |
3376 | if (e.X_op == O_register && reg < 8) | |
3377 | add_unwind_entry (output_rp_br (reg)); | |
3378 | else | |
3379 | as_bad ("First operand not a valid branch register"); | |
800eeca4 JW |
3380 | } |
3381 | ||
197865e8 | 3382 | static void |
e0c9811a JW |
3383 | dot_savemem (psprel) |
3384 | int psprel; | |
800eeca4 JW |
3385 | { |
3386 | expressionS e1, e2; | |
3387 | int sep; | |
3388 | int reg1, val; | |
3389 | ||
3390 | sep = parse_operand (&e1); | |
3391 | if (sep != ',') | |
e0c9811a | 3392 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
800eeca4 JW |
3393 | sep = parse_operand (&e2); |
3394 | ||
e0c9811a | 3395 | reg1 = e1.X_add_number; |
800eeca4 | 3396 | val = e2.X_add_number; |
197865e8 | 3397 | |
800eeca4 | 3398 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3399 | if (e1.X_op == O_register) |
800eeca4 JW |
3400 | { |
3401 | if (e2.X_op == O_constant) | |
3402 | { | |
3403 | switch (reg1) | |
3404 | { | |
542d6675 KH |
3405 | case REG_AR + AR_BSP: |
3406 | add_unwind_entry (output_bsp_when ()); | |
3407 | add_unwind_entry ((psprel | |
3408 | ? output_bsp_psprel | |
3409 | : output_bsp_sprel) (val)); | |
3410 | break; | |
3411 | case REG_AR + AR_BSPSTORE: | |
3412 | add_unwind_entry (output_bspstore_when ()); | |
3413 | add_unwind_entry ((psprel | |
3414 | ? output_bspstore_psprel | |
3415 | : output_bspstore_sprel) (val)); | |
3416 | break; | |
3417 | case REG_AR + AR_RNAT: | |
3418 | add_unwind_entry (output_rnat_when ()); | |
3419 | add_unwind_entry ((psprel | |
3420 | ? output_rnat_psprel | |
3421 | : output_rnat_sprel) (val)); | |
3422 | break; | |
3423 | case REG_AR + AR_UNAT: | |
3424 | add_unwind_entry (output_unat_when ()); | |
3425 | add_unwind_entry ((psprel | |
3426 | ? output_unat_psprel | |
3427 | : output_unat_sprel) (val)); | |
3428 | break; | |
3429 | case REG_AR + AR_FPSR: | |
3430 | add_unwind_entry (output_fpsr_when ()); | |
3431 | add_unwind_entry ((psprel | |
3432 | ? output_fpsr_psprel | |
3433 | : output_fpsr_sprel) (val)); | |
3434 | break; | |
3435 | case REG_AR + AR_PFS: | |
3436 | add_unwind_entry (output_pfs_when ()); | |
3437 | add_unwind_entry ((psprel | |
3438 | ? output_pfs_psprel | |
3439 | : output_pfs_sprel) (val)); | |
3440 | break; | |
3441 | case REG_AR + AR_LC: | |
3442 | add_unwind_entry (output_lc_when ()); | |
3443 | add_unwind_entry ((psprel | |
3444 | ? output_lc_psprel | |
3445 | : output_lc_sprel) (val)); | |
3446 | break; | |
3447 | case REG_BR: | |
3448 | add_unwind_entry (output_rp_when ()); | |
3449 | add_unwind_entry ((psprel | |
3450 | ? output_rp_psprel | |
3451 | : output_rp_sprel) (val)); | |
3452 | break; | |
3453 | case REG_PR: | |
3454 | add_unwind_entry (output_preds_when ()); | |
3455 | add_unwind_entry ((psprel | |
3456 | ? output_preds_psprel | |
3457 | : output_preds_sprel) (val)); | |
3458 | break; | |
3459 | case REG_PRIUNAT: | |
3460 | add_unwind_entry (output_priunat_when_mem ()); | |
3461 | add_unwind_entry ((psprel | |
3462 | ? output_priunat_psprel | |
3463 | : output_priunat_sprel) (val)); | |
3464 | break; | |
3465 | default: | |
3466 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3467 | } |
3468 | } | |
3469 | else | |
3470 | as_bad (" Second operand not a valid constant"); | |
3471 | } | |
3472 | else | |
e0c9811a | 3473 | as_bad ("First operand not a register"); |
800eeca4 JW |
3474 | } |
3475 | ||
197865e8 | 3476 | static void |
800eeca4 | 3477 | dot_saveg (dummy) |
2434f565 | 3478 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3479 | { |
3480 | expressionS e1, e2; | |
3481 | int sep; | |
3482 | sep = parse_operand (&e1); | |
3483 | if (sep == ',') | |
3484 | parse_operand (&e2); | |
197865e8 | 3485 | |
800eeca4 JW |
3486 | if (e1.X_op != O_constant) |
3487 | as_bad ("First operand to .save.g must be a constant."); | |
3488 | else | |
3489 | { | |
3490 | int grmask = e1.X_add_number; | |
3491 | if (sep != ',') | |
3492 | add_unwind_entry (output_gr_mem (grmask)); | |
3493 | else | |
542d6675 | 3494 | { |
800eeca4 | 3495 | int reg = e2.X_add_number - REG_GR; |
542d6675 | 3496 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
800eeca4 JW |
3497 | add_unwind_entry (output_gr_gr (grmask, reg)); |
3498 | else | |
3499 | as_bad ("Second operand is an invalid register."); | |
3500 | } | |
3501 | } | |
3502 | } | |
3503 | ||
197865e8 | 3504 | static void |
800eeca4 | 3505 | dot_savef (dummy) |
2434f565 | 3506 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3507 | { |
e0c9811a | 3508 | expressionS e1; |
800eeca4 JW |
3509 | int sep; |
3510 | sep = parse_operand (&e1); | |
197865e8 | 3511 | |
800eeca4 JW |
3512 | if (e1.X_op != O_constant) |
3513 | as_bad ("Operand to .save.f must be a constant."); | |
3514 | else | |
e0c9811a | 3515 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
800eeca4 JW |
3516 | } |
3517 | ||
197865e8 | 3518 | static void |
800eeca4 | 3519 | dot_saveb (dummy) |
2434f565 | 3520 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3521 | { |
e0c9811a JW |
3522 | expressionS e1, e2; |
3523 | unsigned int reg; | |
3524 | unsigned char sep; | |
3525 | int brmask; | |
3526 | ||
800eeca4 | 3527 | sep = parse_operand (&e1); |
800eeca4 | 3528 | if (e1.X_op != O_constant) |
800eeca4 | 3529 | { |
e0c9811a JW |
3530 | as_bad ("First operand to .save.b must be a constant."); |
3531 | return; | |
800eeca4 | 3532 | } |
e0c9811a JW |
3533 | brmask = e1.X_add_number; |
3534 | ||
3535 | if (sep == ',') | |
3536 | { | |
3537 | sep = parse_operand (&e2); | |
3538 | reg = e2.X_add_number - REG_GR; | |
3539 | if (e2.X_op != O_register || reg > 127) | |
3540 | { | |
3541 | as_bad ("Second operand to .save.b must be a general register."); | |
3542 | return; | |
3543 | } | |
3544 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); | |
3545 | } | |
3546 | else | |
3547 | add_unwind_entry (output_br_mem (brmask)); | |
3548 | ||
3549 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3550 | ignore_rest_of_line (); | |
800eeca4 JW |
3551 | } |
3552 | ||
197865e8 | 3553 | static void |
800eeca4 | 3554 | dot_savegf (dummy) |
2434f565 | 3555 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3556 | { |
3557 | expressionS e1, e2; | |
3558 | int sep; | |
3559 | sep = parse_operand (&e1); | |
3560 | if (sep == ',') | |
3561 | parse_operand (&e2); | |
197865e8 | 3562 | |
800eeca4 JW |
3563 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
3564 | as_bad ("Both operands of .save.gf must be constants."); | |
3565 | else | |
3566 | { | |
3567 | int grmask = e1.X_add_number; | |
3568 | int frmask = e2.X_add_number; | |
3569 | add_unwind_entry (output_frgr_mem (grmask, frmask)); | |
3570 | } | |
3571 | } | |
3572 | ||
197865e8 | 3573 | static void |
800eeca4 | 3574 | dot_spill (dummy) |
2434f565 | 3575 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3576 | { |
3577 | expressionS e; | |
e0c9811a JW |
3578 | unsigned char sep; |
3579 | ||
3580 | sep = parse_operand (&e); | |
3581 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3582 | ignore_rest_of_line (); | |
197865e8 | 3583 | |
800eeca4 JW |
3584 | if (e.X_op != O_constant) |
3585 | as_bad ("Operand to .spill must be a constant"); | |
3586 | else | |
e0c9811a JW |
3587 | add_unwind_entry (output_spill_base (e.X_add_number)); |
3588 | } | |
3589 | ||
3590 | static void | |
3591 | dot_spillreg (dummy) | |
2434f565 | 3592 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3593 | { |
3594 | int sep, ab, xy, reg, treg; | |
3595 | expressionS e1, e2; | |
3596 | ||
3597 | sep = parse_operand (&e1); | |
3598 | if (sep != ',') | |
3599 | { | |
3600 | as_bad ("No second operand to .spillreg"); | |
3601 | return; | |
3602 | } | |
3603 | ||
3604 | parse_operand (&e2); | |
3605 | ||
3606 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
800eeca4 | 3607 | { |
e0c9811a JW |
3608 | as_bad ("First operand to .spillreg must be a preserved register"); |
3609 | return; | |
800eeca4 | 3610 | } |
e0c9811a JW |
3611 | |
3612 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) | |
3613 | { | |
3614 | as_bad ("Second operand to .spillreg must be a register"); | |
3615 | return; | |
3616 | } | |
3617 | ||
3618 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); | |
3619 | } | |
3620 | ||
3621 | static void | |
3622 | dot_spillmem (psprel) | |
3623 | int psprel; | |
3624 | { | |
3625 | expressionS e1, e2; | |
3626 | int sep, ab, reg; | |
3627 | ||
3628 | sep = parse_operand (&e1); | |
3629 | if (sep != ',') | |
3630 | { | |
3631 | as_bad ("Second operand missing"); | |
3632 | return; | |
3633 | } | |
3634 | ||
3635 | parse_operand (&e2); | |
3636 | ||
3637 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
3638 | { | |
3639 | as_bad ("First operand to .spill%s must be a preserved register", | |
3640 | psprel ? "psp" : "sp"); | |
3641 | return; | |
3642 | } | |
3643 | ||
3644 | if (e2.X_op != O_constant) | |
3645 | { | |
3646 | as_bad ("Second operand to .spill%s must be a constant", | |
3647 | psprel ? "psp" : "sp"); | |
3648 | return; | |
3649 | } | |
3650 | ||
3651 | if (psprel) | |
3652 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); | |
3653 | else | |
3654 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); | |
3655 | } | |
3656 | ||
3657 | static void | |
3658 | dot_spillreg_p (dummy) | |
2434f565 | 3659 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3660 | { |
3661 | int sep, ab, xy, reg, treg; | |
3662 | expressionS e1, e2, e3; | |
3663 | unsigned int qp; | |
3664 | ||
3665 | sep = parse_operand (&e1); | |
3666 | if (sep != ',') | |
3667 | { | |
3668 | as_bad ("No second and third operand to .spillreg.p"); | |
3669 | return; | |
3670 | } | |
3671 | ||
3672 | sep = parse_operand (&e2); | |
3673 | if (sep != ',') | |
3674 | { | |
3675 | as_bad ("No third operand to .spillreg.p"); | |
3676 | return; | |
3677 | } | |
3678 | ||
3679 | parse_operand (&e3); | |
3680 | ||
3681 | qp = e1.X_add_number - REG_P; | |
3682 | ||
3683 | if (e1.X_op != O_register || qp > 63) | |
3684 | { | |
3685 | as_bad ("First operand to .spillreg.p must be a predicate"); | |
3686 | return; | |
3687 | } | |
3688 | ||
3689 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3690 | { | |
3691 | as_bad ("Second operand to .spillreg.p must be a preserved register"); | |
3692 | return; | |
3693 | } | |
3694 | ||
3695 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) | |
3696 | { | |
3697 | as_bad ("Third operand to .spillreg.p must be a register"); | |
3698 | return; | |
3699 | } | |
3700 | ||
3701 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); | |
3702 | } | |
3703 | ||
3704 | static void | |
3705 | dot_spillmem_p (psprel) | |
3706 | int psprel; | |
3707 | { | |
3708 | expressionS e1, e2, e3; | |
3709 | int sep, ab, reg; | |
3710 | unsigned int qp; | |
3711 | ||
3712 | sep = parse_operand (&e1); | |
3713 | if (sep != ',') | |
3714 | { | |
3715 | as_bad ("Second operand missing"); | |
3716 | return; | |
3717 | } | |
3718 | ||
3719 | parse_operand (&e2); | |
3720 | if (sep != ',') | |
3721 | { | |
3722 | as_bad ("Second operand missing"); | |
3723 | return; | |
3724 | } | |
3725 | ||
3726 | parse_operand (&e3); | |
3727 | ||
3728 | qp = e1.X_add_number - REG_P; | |
3729 | if (e1.X_op != O_register || qp > 63) | |
3730 | { | |
3731 | as_bad ("First operand to .spill%s_p must be a predicate", | |
3732 | psprel ? "psp" : "sp"); | |
3733 | return; | |
3734 | } | |
3735 | ||
3736 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3737 | { | |
3738 | as_bad ("Second operand to .spill%s_p must be a preserved register", | |
3739 | psprel ? "psp" : "sp"); | |
3740 | return; | |
3741 | } | |
3742 | ||
3743 | if (e3.X_op != O_constant) | |
3744 | { | |
3745 | as_bad ("Third operand to .spill%s_p must be a constant", | |
3746 | psprel ? "psp" : "sp"); | |
3747 | return; | |
3748 | } | |
3749 | ||
3750 | if (psprel) | |
fa7fda74 | 3751 | add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); |
e0c9811a | 3752 | else |
fa7fda74 | 3753 | add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); |
e0c9811a JW |
3754 | } |
3755 | ||
6290819d NC |
3756 | static unsigned int |
3757 | get_saved_prologue_count (lbl) | |
3758 | unsigned long lbl; | |
3759 | { | |
3760 | label_prologue_count *lpc = unwind.saved_prologue_counts; | |
3761 | ||
3762 | while (lpc != NULL && lpc->label_number != lbl) | |
3763 | lpc = lpc->next; | |
3764 | ||
3765 | if (lpc != NULL) | |
3766 | return lpc->prologue_count; | |
3767 | ||
3768 | as_bad ("Missing .label_state %ld", lbl); | |
3769 | return 1; | |
3770 | } | |
3771 | ||
3772 | static void | |
3773 | save_prologue_count (lbl, count) | |
3774 | unsigned long lbl; | |
3775 | unsigned int count; | |
3776 | { | |
3777 | label_prologue_count *lpc = unwind.saved_prologue_counts; | |
3778 | ||
3779 | while (lpc != NULL && lpc->label_number != lbl) | |
3780 | lpc = lpc->next; | |
3781 | ||
3782 | if (lpc != NULL) | |
3783 | lpc->prologue_count = count; | |
3784 | else | |
3785 | { | |
40449e9f | 3786 | label_prologue_count *new_lpc = xmalloc (sizeof (* new_lpc)); |
6290819d NC |
3787 | |
3788 | new_lpc->next = unwind.saved_prologue_counts; | |
3789 | new_lpc->label_number = lbl; | |
3790 | new_lpc->prologue_count = count; | |
3791 | unwind.saved_prologue_counts = new_lpc; | |
3792 | } | |
3793 | } | |
3794 | ||
3795 | static void | |
3796 | free_saved_prologue_counts () | |
3797 | { | |
40449e9f KH |
3798 | label_prologue_count *lpc = unwind.saved_prologue_counts; |
3799 | label_prologue_count *next; | |
6290819d NC |
3800 | |
3801 | while (lpc != NULL) | |
3802 | { | |
3803 | next = lpc->next; | |
3804 | free (lpc); | |
3805 | lpc = next; | |
3806 | } | |
3807 | ||
3808 | unwind.saved_prologue_counts = NULL; | |
3809 | } | |
3810 | ||
e0c9811a JW |
3811 | static void |
3812 | dot_label_state (dummy) | |
2434f565 | 3813 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3814 | { |
3815 | expressionS e; | |
3816 | ||
3817 | parse_operand (&e); | |
3818 | if (e.X_op != O_constant) | |
3819 | { | |
3820 | as_bad ("Operand to .label_state must be a constant"); | |
3821 | return; | |
3822 | } | |
3823 | add_unwind_entry (output_label_state (e.X_add_number)); | |
6290819d | 3824 | save_prologue_count (e.X_add_number, unwind.prologue_count); |
e0c9811a JW |
3825 | } |
3826 | ||
3827 | static void | |
3828 | dot_copy_state (dummy) | |
2434f565 | 3829 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3830 | { |
3831 | expressionS e; | |
3832 | ||
3833 | parse_operand (&e); | |
3834 | if (e.X_op != O_constant) | |
3835 | { | |
3836 | as_bad ("Operand to .copy_state must be a constant"); | |
3837 | return; | |
3838 | } | |
3839 | add_unwind_entry (output_copy_state (e.X_add_number)); | |
6290819d | 3840 | unwind.prologue_count = get_saved_prologue_count (e.X_add_number); |
800eeca4 JW |
3841 | } |
3842 | ||
197865e8 | 3843 | static void |
800eeca4 | 3844 | dot_unwabi (dummy) |
2434f565 | 3845 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3846 | { |
e0c9811a JW |
3847 | expressionS e1, e2; |
3848 | unsigned char sep; | |
3849 | ||
3850 | sep = parse_operand (&e1); | |
3851 | if (sep != ',') | |
3852 | { | |
3853 | as_bad ("Second operand to .unwabi missing"); | |
3854 | return; | |
3855 | } | |
3856 | sep = parse_operand (&e2); | |
3857 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3858 | ignore_rest_of_line (); | |
3859 | ||
3860 | if (e1.X_op != O_constant) | |
3861 | { | |
3862 | as_bad ("First operand to .unwabi must be a constant"); | |
3863 | return; | |
3864 | } | |
3865 | ||
3866 | if (e2.X_op != O_constant) | |
3867 | { | |
3868 | as_bad ("Second operand to .unwabi must be a constant"); | |
3869 | return; | |
3870 | } | |
3871 | ||
3872 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); | |
800eeca4 JW |
3873 | } |
3874 | ||
197865e8 | 3875 | static void |
800eeca4 | 3876 | dot_personality (dummy) |
2434f565 | 3877 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3878 | { |
3879 | char *name, *p, c; | |
3880 | SKIP_WHITESPACE (); | |
3881 | name = input_line_pointer; | |
3882 | c = get_symbol_end (); | |
3883 | p = input_line_pointer; | |
e0c9811a | 3884 | unwind.personality_routine = symbol_find_or_make (name); |
91a2ae2a | 3885 | unwind.force_unwind_entry = 1; |
800eeca4 JW |
3886 | *p = c; |
3887 | SKIP_WHITESPACE (); | |
3888 | demand_empty_rest_of_line (); | |
3889 | } | |
3890 | ||
3891 | static void | |
3892 | dot_proc (dummy) | |
2434f565 | 3893 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3894 | { |
3895 | char *name, *p, c; | |
3896 | symbolS *sym; | |
3897 | ||
e0c9811a JW |
3898 | unwind.proc_start = expr_build_dot (); |
3899 | /* Parse names of main and alternate entry points and mark them as | |
542d6675 | 3900 | function symbols: */ |
800eeca4 JW |
3901 | while (1) |
3902 | { | |
3903 | SKIP_WHITESPACE (); | |
3904 | name = input_line_pointer; | |
3905 | c = get_symbol_end (); | |
3906 | p = input_line_pointer; | |
3907 | sym = symbol_find_or_make (name); | |
e0c9811a | 3908 | if (unwind.proc_start == 0) |
542d6675 | 3909 | { |
e0c9811a | 3910 | unwind.proc_start = sym; |
800eeca4 JW |
3911 | } |
3912 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; | |
3913 | *p = c; | |
3914 | SKIP_WHITESPACE (); | |
3915 | if (*input_line_pointer != ',') | |
3916 | break; | |
3917 | ++input_line_pointer; | |
3918 | } | |
3919 | demand_empty_rest_of_line (); | |
3920 | ia64_do_align (16); | |
3921 | ||
33d01f33 | 3922 | unwind.prologue_count = 0; |
e0c9811a JW |
3923 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
3924 | unwind.personality_routine = 0; | |
800eeca4 JW |
3925 | } |
3926 | ||
3927 | static void | |
3928 | dot_body (dummy) | |
2434f565 | 3929 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3930 | { |
e0c9811a | 3931 | unwind.prologue = 0; |
30d25259 RH |
3932 | unwind.prologue_mask = 0; |
3933 | ||
800eeca4 | 3934 | add_unwind_entry (output_body ()); |
e0c9811a | 3935 | demand_empty_rest_of_line (); |
800eeca4 JW |
3936 | } |
3937 | ||
3938 | static void | |
3939 | dot_prologue (dummy) | |
2434f565 | 3940 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3941 | { |
e0c9811a | 3942 | unsigned char sep; |
2434f565 | 3943 | int mask = 0, grsave = 0; |
e0c9811a | 3944 | |
e0c9811a | 3945 | if (!is_it_end_of_statement ()) |
800eeca4 JW |
3946 | { |
3947 | expressionS e1, e2; | |
800eeca4 JW |
3948 | sep = parse_operand (&e1); |
3949 | if (sep != ',') | |
3950 | as_bad ("No second operand to .prologue"); | |
3951 | sep = parse_operand (&e2); | |
e0c9811a | 3952 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
542d6675 | 3953 | ignore_rest_of_line (); |
800eeca4 JW |
3954 | |
3955 | if (e1.X_op == O_constant) | |
542d6675 | 3956 | { |
30d25259 RH |
3957 | mask = e1.X_add_number; |
3958 | ||
800eeca4 | 3959 | if (e2.X_op == O_constant) |
30d25259 RH |
3960 | grsave = e2.X_add_number; |
3961 | else if (e2.X_op == O_register | |
3962 | && (grsave = e2.X_add_number - REG_GR) < 128) | |
3963 | ; | |
800eeca4 | 3964 | else |
30d25259 RH |
3965 | as_bad ("Second operand not a constant or general register"); |
3966 | ||
3967 | add_unwind_entry (output_prologue_gr (mask, grsave)); | |
800eeca4 JW |
3968 | } |
3969 | else | |
3970 | as_bad ("First operand not a constant"); | |
3971 | } | |
3972 | else | |
3973 | add_unwind_entry (output_prologue ()); | |
30d25259 RH |
3974 | |
3975 | unwind.prologue = 1; | |
3976 | unwind.prologue_mask = mask; | |
33d01f33 | 3977 | ++unwind.prologue_count; |
800eeca4 JW |
3978 | } |
3979 | ||
3980 | static void | |
3981 | dot_endp (dummy) | |
2434f565 | 3982 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3983 | { |
3984 | expressionS e; | |
3985 | unsigned char *ptr; | |
44f5c83a | 3986 | int bytes_per_address; |
800eeca4 JW |
3987 | long where; |
3988 | segT saved_seg; | |
3989 | subsegT saved_subseg; | |
91a2ae2a | 3990 | const char *sec_name, *text_name; |
c538998c JJ |
3991 | char *name, *p, c; |
3992 | symbolS *sym; | |
800eeca4 | 3993 | |
91a2ae2a RH |
3994 | if (unwind.saved_text_seg) |
3995 | { | |
3996 | saved_seg = unwind.saved_text_seg; | |
3997 | saved_subseg = unwind.saved_text_subseg; | |
3998 | unwind.saved_text_seg = NULL; | |
3999 | } | |
4000 | else | |
4001 | { | |
4002 | saved_seg = now_seg; | |
4003 | saved_subseg = now_subseg; | |
4004 | } | |
4005 | ||
4006 | /* | |
4007 | Use a slightly ugly scheme to derive the unwind section names from | |
4008 | the text section name: | |
4009 | ||
4010 | text sect. unwind table sect. | |
4011 | name: name: comments: | |
4012 | ---------- ----------------- -------------------------------- | |
4013 | .text .IA_64.unwind | |
4014 | .text.foo .IA_64.unwind.text.foo | |
4015 | .foo .IA_64.unwind.foo | |
579f31ac JJ |
4016 | .gnu.linkonce.t.foo |
4017 | .gnu.linkonce.ia64unw.foo | |
91a2ae2a RH |
4018 | _info .IA_64.unwind_info gas issues error message (ditto) |
4019 | _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) | |
4020 | ||
4021 | This mapping is done so that: | |
4022 | ||
4023 | (a) An object file with unwind info only in .text will use | |
4024 | unwind section names .IA_64.unwind and .IA_64.unwind_info. | |
4025 | This follows the letter of the ABI and also ensures backwards | |
4026 | compatibility with older toolchains. | |
4027 | ||
4028 | (b) An object file with unwind info in multiple text sections | |
4029 | will use separate unwind sections for each text section. | |
4030 | This allows us to properly set the "sh_info" and "sh_link" | |
4031 | fields in SHT_IA_64_UNWIND as required by the ABI and also | |
4032 | lets GNU ld support programs with multiple segments | |
4033 | containing unwind info (as might be the case for certain | |
4034 | embedded applications). | |
40449e9f | 4035 | |
91a2ae2a RH |
4036 | (c) An error is issued if there would be a name clash. |
4037 | */ | |
4038 | text_name = segment_name (saved_seg); | |
4039 | if (strncmp (text_name, "_info", 5) == 0) | |
4040 | { | |
4041 | as_bad ("Illegal section name `%s' (causes unwind section name clash)", | |
4042 | text_name); | |
4043 | ignore_rest_of_line (); | |
4044 | return; | |
4045 | } | |
4046 | if (strcmp (text_name, ".text") == 0) | |
4047 | text_name = ""; | |
800eeca4 | 4048 | |
800eeca4 | 4049 | insn_group_break (1, 0, 0); |
800eeca4 | 4050 | |
91a2ae2a RH |
4051 | /* If there wasn't a .handlerdata, we haven't generated an image yet. */ |
4052 | if (!unwind.info) | |
4053 | generate_unwind_image (text_name); | |
800eeca4 | 4054 | |
91a2ae2a RH |
4055 | if (unwind.info || unwind.force_unwind_entry) |
4056 | { | |
4057 | subseg_set (md.last_text_seg, 0); | |
4058 | unwind.proc_end = expr_build_dot (); | |
5e7474a7 | 4059 | |
91a2ae2a RH |
4060 | make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); |
4061 | set_section ((char *) sec_name); | |
4062 | bfd_set_section_flags (stdoutput, now_seg, | |
4063 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); | |
5e7474a7 | 4064 | |
557debba JW |
4065 | /* Make sure that section has 4 byte alignment for ILP32 and |
4066 | 8 byte alignment for LP64. */ | |
4067 | record_alignment (now_seg, md.pointer_size_shift); | |
800eeca4 | 4068 | |
557debba JW |
4069 | /* Need space for 3 pointers for procedure start, procedure end, |
4070 | and unwind info. */ | |
4071 | ptr = frag_more (3 * md.pointer_size); | |
4072 | where = frag_now_fix () - (3 * md.pointer_size); | |
91a2ae2a | 4073 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; |
800eeca4 | 4074 | |
40449e9f | 4075 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ |
91a2ae2a RH |
4076 | e.X_op = O_pseudo_fixup; |
4077 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
4078 | e.X_add_number = 0; | |
4079 | e.X_add_symbol = unwind.proc_start; | |
4080 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); | |
800eeca4 | 4081 | |
800eeca4 JW |
4082 | e.X_op = O_pseudo_fixup; |
4083 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
4084 | e.X_add_number = 0; | |
91a2ae2a RH |
4085 | e.X_add_symbol = unwind.proc_end; |
4086 | ia64_cons_fix_new (frag_now, where + bytes_per_address, | |
4087 | bytes_per_address, &e); | |
4088 | ||
4089 | if (unwind.info) | |
4090 | { | |
4091 | e.X_op = O_pseudo_fixup; | |
4092 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
4093 | e.X_add_number = 0; | |
4094 | e.X_add_symbol = unwind.info; | |
4095 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), | |
4096 | bytes_per_address, &e); | |
4097 | } | |
4098 | else | |
4099 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, | |
4100 | bytes_per_address); | |
800eeca4 | 4101 | |
91a2ae2a | 4102 | } |
800eeca4 | 4103 | subseg_set (saved_seg, saved_subseg); |
c538998c JJ |
4104 | |
4105 | /* Parse names of main and alternate entry points and set symbol sizes. */ | |
4106 | while (1) | |
4107 | { | |
4108 | SKIP_WHITESPACE (); | |
4109 | name = input_line_pointer; | |
4110 | c = get_symbol_end (); | |
4111 | p = input_line_pointer; | |
4112 | sym = symbol_find (name); | |
4113 | if (sym && unwind.proc_start | |
4114 | && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION) | |
4115 | && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL) | |
4116 | { | |
4117 | fragS *fr = symbol_get_frag (unwind.proc_start); | |
4118 | fragS *frag = symbol_get_frag (sym); | |
4119 | ||
4120 | /* Check whether the function label is at or beyond last | |
4121 | .proc directive. */ | |
4122 | while (fr && fr != frag) | |
4123 | fr = fr->fr_next; | |
4124 | if (fr) | |
4125 | { | |
4126 | if (frag == frag_now && SEG_NORMAL (now_seg)) | |
4127 | S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); | |
4128 | else | |
4129 | { | |
4130 | symbol_get_obj (sym)->size = | |
4131 | (expressionS *) xmalloc (sizeof (expressionS)); | |
4132 | symbol_get_obj (sym)->size->X_op = O_subtract; | |
4133 | symbol_get_obj (sym)->size->X_add_symbol | |
4134 | = symbol_new (FAKE_LABEL_NAME, now_seg, | |
4135 | frag_now_fix (), frag_now); | |
4136 | symbol_get_obj (sym)->size->X_op_symbol = sym; | |
4137 | symbol_get_obj (sym)->size->X_add_number = 0; | |
4138 | } | |
4139 | } | |
4140 | } | |
4141 | *p = c; | |
4142 | SKIP_WHITESPACE (); | |
4143 | if (*input_line_pointer != ',') | |
4144 | break; | |
4145 | ++input_line_pointer; | |
4146 | } | |
4147 | demand_empty_rest_of_line (); | |
e0c9811a | 4148 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
800eeca4 JW |
4149 | } |
4150 | ||
4151 | static void | |
4152 | dot_template (template) | |
4153 | int template; | |
4154 | { | |
4155 | CURR_SLOT.user_template = template; | |
4156 | } | |
4157 | ||
4158 | static void | |
4159 | dot_regstk (dummy) | |
2434f565 | 4160 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4161 | { |
4162 | int ins, locs, outs, rots; | |
4163 | ||
4164 | if (is_it_end_of_statement ()) | |
4165 | ins = locs = outs = rots = 0; | |
4166 | else | |
4167 | { | |
4168 | ins = get_absolute_expression (); | |
4169 | if (*input_line_pointer++ != ',') | |
4170 | goto err; | |
4171 | locs = get_absolute_expression (); | |
4172 | if (*input_line_pointer++ != ',') | |
4173 | goto err; | |
4174 | outs = get_absolute_expression (); | |
4175 | if (*input_line_pointer++ != ',') | |
4176 | goto err; | |
4177 | rots = get_absolute_expression (); | |
4178 | } | |
4179 | set_regstack (ins, locs, outs, rots); | |
4180 | return; | |
4181 | ||
4182 | err: | |
4183 | as_bad ("Comma expected"); | |
4184 | ignore_rest_of_line (); | |
4185 | } | |
4186 | ||
4187 | static void | |
4188 | dot_rot (type) | |
4189 | int type; | |
4190 | { | |
4191 | unsigned num_regs, num_alloced = 0; | |
4192 | struct dynreg **drpp, *dr; | |
4193 | int ch, base_reg = 0; | |
4194 | char *name, *start; | |
4195 | size_t len; | |
4196 | ||
4197 | switch (type) | |
4198 | { | |
4199 | case DYNREG_GR: base_reg = REG_GR + 32; break; | |
4200 | case DYNREG_FR: base_reg = REG_FR + 32; break; | |
4201 | case DYNREG_PR: base_reg = REG_P + 16; break; | |
4202 | default: break; | |
4203 | } | |
4204 | ||
542d6675 | 4205 | /* First, remove existing names from hash table. */ |
800eeca4 JW |
4206 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
4207 | { | |
4208 | hash_delete (md.dynreg_hash, dr->name); | |
4209 | dr->num_regs = 0; | |
4210 | } | |
4211 | ||
4212 | drpp = &md.dynreg[type]; | |
4213 | while (1) | |
4214 | { | |
4215 | start = input_line_pointer; | |
4216 | ch = get_symbol_end (); | |
4217 | *input_line_pointer = ch; | |
4218 | len = (input_line_pointer - start); | |
4219 | ||
4220 | SKIP_WHITESPACE (); | |
4221 | if (*input_line_pointer != '[') | |
4222 | { | |
4223 | as_bad ("Expected '['"); | |
4224 | goto err; | |
4225 | } | |
4226 | ++input_line_pointer; /* skip '[' */ | |
4227 | ||
4228 | num_regs = get_absolute_expression (); | |
4229 | ||
4230 | if (*input_line_pointer++ != ']') | |
4231 | { | |
4232 | as_bad ("Expected ']'"); | |
4233 | goto err; | |
4234 | } | |
4235 | SKIP_WHITESPACE (); | |
4236 | ||
4237 | num_alloced += num_regs; | |
4238 | switch (type) | |
4239 | { | |
4240 | case DYNREG_GR: | |
4241 | if (num_alloced > md.rot.num_regs) | |
4242 | { | |
4243 | as_bad ("Used more than the declared %d rotating registers", | |
4244 | md.rot.num_regs); | |
4245 | goto err; | |
4246 | } | |
4247 | break; | |
4248 | case DYNREG_FR: | |
4249 | if (num_alloced > 96) | |
4250 | { | |
4251 | as_bad ("Used more than the available 96 rotating registers"); | |
4252 | goto err; | |
4253 | } | |
4254 | break; | |
4255 | case DYNREG_PR: | |
4256 | if (num_alloced > 48) | |
4257 | { | |
4258 | as_bad ("Used more than the available 48 rotating registers"); | |
4259 | goto err; | |
4260 | } | |
4261 | break; | |
4262 | ||
4263 | default: | |
4264 | break; | |
4265 | } | |
4266 | ||
4267 | name = obstack_alloc (¬es, len + 1); | |
4268 | memcpy (name, start, len); | |
4269 | name[len] = '\0'; | |
4270 | ||
4271 | if (!*drpp) | |
4272 | { | |
4273 | *drpp = obstack_alloc (¬es, sizeof (*dr)); | |
4274 | memset (*drpp, 0, sizeof (*dr)); | |
4275 | } | |
4276 | ||
4277 | dr = *drpp; | |
4278 | dr->name = name; | |
4279 | dr->num_regs = num_regs; | |
4280 | dr->base = base_reg; | |
4281 | drpp = &dr->next; | |
4282 | base_reg += num_regs; | |
4283 | ||
4284 | if (hash_insert (md.dynreg_hash, name, dr)) | |
4285 | { | |
4286 | as_bad ("Attempt to redefine register set `%s'", name); | |
4287 | goto err; | |
4288 | } | |
4289 | ||
4290 | if (*input_line_pointer != ',') | |
4291 | break; | |
4292 | ++input_line_pointer; /* skip comma */ | |
4293 | SKIP_WHITESPACE (); | |
4294 | } | |
4295 | demand_empty_rest_of_line (); | |
4296 | return; | |
4297 | ||
4298 | err: | |
4299 | ignore_rest_of_line (); | |
4300 | } | |
4301 | ||
4302 | static void | |
4303 | dot_byteorder (byteorder) | |
4304 | int byteorder; | |
4305 | { | |
4306 | target_big_endian = byteorder; | |
4307 | } | |
4308 | ||
4309 | static void | |
4310 | dot_psr (dummy) | |
2434f565 | 4311 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4312 | { |
4313 | char *option; | |
4314 | int ch; | |
4315 | ||
4316 | while (1) | |
4317 | { | |
4318 | option = input_line_pointer; | |
4319 | ch = get_symbol_end (); | |
4320 | if (strcmp (option, "lsb") == 0) | |
4321 | md.flags &= ~EF_IA_64_BE; | |
4322 | else if (strcmp (option, "msb") == 0) | |
4323 | md.flags |= EF_IA_64_BE; | |
4324 | else if (strcmp (option, "abi32") == 0) | |
4325 | md.flags &= ~EF_IA_64_ABI64; | |
4326 | else if (strcmp (option, "abi64") == 0) | |
4327 | md.flags |= EF_IA_64_ABI64; | |
4328 | else | |
4329 | as_bad ("Unknown psr option `%s'", option); | |
4330 | *input_line_pointer = ch; | |
4331 | ||
4332 | SKIP_WHITESPACE (); | |
4333 | if (*input_line_pointer != ',') | |
4334 | break; | |
4335 | ||
4336 | ++input_line_pointer; | |
4337 | SKIP_WHITESPACE (); | |
4338 | } | |
4339 | demand_empty_rest_of_line (); | |
4340 | } | |
4341 | ||
4342 | static void | |
4343 | dot_alias (dummy) | |
2434f565 | 4344 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4345 | { |
4346 | as_bad (".alias not implemented yet"); | |
4347 | } | |
4348 | ||
4349 | static void | |
4350 | dot_ln (dummy) | |
2434f565 | 4351 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4352 | { |
4353 | new_logical_line (0, get_absolute_expression ()); | |
4354 | demand_empty_rest_of_line (); | |
4355 | } | |
4356 | ||
542d6675 | 4357 | static char * |
800eeca4 JW |
4358 | parse_section_name () |
4359 | { | |
4360 | char *name; | |
4361 | int len; | |
4362 | ||
4363 | SKIP_WHITESPACE (); | |
4364 | if (*input_line_pointer != '"') | |
4365 | { | |
4366 | as_bad ("Missing section name"); | |
4367 | ignore_rest_of_line (); | |
4368 | return 0; | |
4369 | } | |
4370 | name = demand_copy_C_string (&len); | |
4371 | if (!name) | |
4372 | { | |
4373 | ignore_rest_of_line (); | |
4374 | return 0; | |
4375 | } | |
4376 | SKIP_WHITESPACE (); | |
4377 | if (*input_line_pointer != ',') | |
4378 | { | |
4379 | as_bad ("Comma expected after section name"); | |
4380 | ignore_rest_of_line (); | |
4381 | return 0; | |
4382 | } | |
4383 | ++input_line_pointer; /* skip comma */ | |
4384 | return name; | |
4385 | } | |
4386 | ||
4387 | static void | |
4388 | dot_xdata (size) | |
4389 | int size; | |
4390 | { | |
4391 | char *name = parse_section_name (); | |
4392 | if (!name) | |
4393 | return; | |
4394 | ||
4d5a53ff | 4395 | md.keep_pending_output = 1; |
800eeca4 JW |
4396 | set_section (name); |
4397 | cons (size); | |
4398 | obj_elf_previous (0); | |
4d5a53ff | 4399 | md.keep_pending_output = 0; |
800eeca4 JW |
4400 | } |
4401 | ||
4402 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ | |
542d6675 | 4403 | |
800eeca4 JW |
4404 | static void |
4405 | stmt_float_cons (kind) | |
4406 | int kind; | |
4407 | { | |
4408 | size_t size; | |
4409 | ||
4410 | switch (kind) | |
4411 | { | |
4412 | case 'd': size = 8; break; | |
4413 | case 'x': size = 10; break; | |
4414 | ||
4415 | case 'f': | |
4416 | default: | |
4417 | size = 4; | |
4418 | break; | |
4419 | } | |
4420 | ia64_do_align (size); | |
4421 | float_cons (kind); | |
4422 | } | |
4423 | ||
4424 | static void | |
4425 | stmt_cons_ua (size) | |
4426 | int size; | |
4427 | { | |
4428 | int saved_auto_align = md.auto_align; | |
4429 | ||
4430 | md.auto_align = 0; | |
4431 | cons (size); | |
4432 | md.auto_align = saved_auto_align; | |
4433 | } | |
4434 | ||
4435 | static void | |
4436 | dot_xfloat_cons (kind) | |
4437 | int kind; | |
4438 | { | |
4439 | char *name = parse_section_name (); | |
4440 | if (!name) | |
4441 | return; | |
4442 | ||
4d5a53ff | 4443 | md.keep_pending_output = 1; |
800eeca4 JW |
4444 | set_section (name); |
4445 | stmt_float_cons (kind); | |
4446 | obj_elf_previous (0); | |
4d5a53ff | 4447 | md.keep_pending_output = 0; |
800eeca4 JW |
4448 | } |
4449 | ||
4450 | static void | |
4451 | dot_xstringer (zero) | |
4452 | int zero; | |
4453 | { | |
4454 | char *name = parse_section_name (); | |
4455 | if (!name) | |
4456 | return; | |
4457 | ||
4d5a53ff | 4458 | md.keep_pending_output = 1; |
800eeca4 JW |
4459 | set_section (name); |
4460 | stringer (zero); | |
4461 | obj_elf_previous (0); | |
4d5a53ff | 4462 | md.keep_pending_output = 0; |
800eeca4 JW |
4463 | } |
4464 | ||
4465 | static void | |
4466 | dot_xdata_ua (size) | |
4467 | int size; | |
4468 | { | |
4469 | int saved_auto_align = md.auto_align; | |
4470 | char *name = parse_section_name (); | |
4471 | if (!name) | |
4472 | return; | |
4473 | ||
4d5a53ff | 4474 | md.keep_pending_output = 1; |
800eeca4 JW |
4475 | set_section (name); |
4476 | md.auto_align = 0; | |
4477 | cons (size); | |
4478 | md.auto_align = saved_auto_align; | |
4479 | obj_elf_previous (0); | |
4d5a53ff | 4480 | md.keep_pending_output = 0; |
800eeca4 JW |
4481 | } |
4482 | ||
4483 | static void | |
4484 | dot_xfloat_cons_ua (kind) | |
4485 | int kind; | |
4486 | { | |
4487 | int saved_auto_align = md.auto_align; | |
4488 | char *name = parse_section_name (); | |
4489 | if (!name) | |
4490 | return; | |
4491 | ||
4d5a53ff | 4492 | md.keep_pending_output = 1; |
800eeca4 JW |
4493 | set_section (name); |
4494 | md.auto_align = 0; | |
4495 | stmt_float_cons (kind); | |
4496 | md.auto_align = saved_auto_align; | |
4497 | obj_elf_previous (0); | |
4d5a53ff | 4498 | md.keep_pending_output = 0; |
800eeca4 JW |
4499 | } |
4500 | ||
4501 | /* .reg.val <regname>,value */ | |
542d6675 | 4502 | |
800eeca4 JW |
4503 | static void |
4504 | dot_reg_val (dummy) | |
2434f565 | 4505 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4506 | { |
4507 | expressionS reg; | |
4508 | ||
4509 | expression (®); | |
4510 | if (reg.X_op != O_register) | |
4511 | { | |
4512 | as_bad (_("Register name expected")); | |
4513 | ignore_rest_of_line (); | |
4514 | } | |
4515 | else if (*input_line_pointer++ != ',') | |
4516 | { | |
4517 | as_bad (_("Comma expected")); | |
4518 | ignore_rest_of_line (); | |
4519 | } | |
197865e8 | 4520 | else |
800eeca4 JW |
4521 | { |
4522 | valueT value = get_absolute_expression (); | |
4523 | int regno = reg.X_add_number; | |
542d6675 KH |
4524 | if (regno < REG_GR || regno > REG_GR + 128) |
4525 | as_warn (_("Register value annotation ignored")); | |
800eeca4 | 4526 | else |
542d6675 KH |
4527 | { |
4528 | gr_values[regno - REG_GR].known = 1; | |
4529 | gr_values[regno - REG_GR].value = value; | |
4530 | gr_values[regno - REG_GR].path = md.path; | |
4531 | } | |
800eeca4 JW |
4532 | } |
4533 | demand_empty_rest_of_line (); | |
4534 | } | |
4535 | ||
197865e8 | 4536 | /* select dv checking mode |
800eeca4 JW |
4537 | .auto |
4538 | .explicit | |
4539 | .default | |
4540 | ||
197865e8 | 4541 | A stop is inserted when changing modes |
800eeca4 | 4542 | */ |
542d6675 | 4543 | |
800eeca4 JW |
4544 | static void |
4545 | dot_dv_mode (type) | |
542d6675 | 4546 | int type; |
800eeca4 JW |
4547 | { |
4548 | if (md.manual_bundling) | |
4549 | as_warn (_("Directive invalid within a bundle")); | |
4550 | ||
4551 | if (type == 'E' || type == 'A') | |
4552 | md.mode_explicitly_set = 0; | |
4553 | else | |
4554 | md.mode_explicitly_set = 1; | |
4555 | ||
4556 | md.detect_dv = 1; | |
4557 | switch (type) | |
4558 | { | |
4559 | case 'A': | |
4560 | case 'a': | |
4561 | if (md.explicit_mode) | |
542d6675 | 4562 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4563 | md.explicit_mode = 0; |
4564 | break; | |
4565 | case 'E': | |
4566 | case 'e': | |
4567 | if (!md.explicit_mode) | |
542d6675 | 4568 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4569 | md.explicit_mode = 1; |
4570 | break; | |
4571 | default: | |
4572 | case 'd': | |
4573 | if (md.explicit_mode != md.default_explicit_mode) | |
542d6675 | 4574 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4575 | md.explicit_mode = md.default_explicit_mode; |
4576 | md.mode_explicitly_set = 0; | |
4577 | break; | |
4578 | } | |
4579 | } | |
4580 | ||
4581 | static void | |
4582 | print_prmask (mask) | |
542d6675 | 4583 | valueT mask; |
800eeca4 JW |
4584 | { |
4585 | int regno; | |
4586 | char *comma = ""; | |
542d6675 | 4587 | for (regno = 0; regno < 64; regno++) |
800eeca4 | 4588 | { |
542d6675 KH |
4589 | if (mask & ((valueT) 1 << regno)) |
4590 | { | |
4591 | fprintf (stderr, "%s p%d", comma, regno); | |
4592 | comma = ","; | |
4593 | } | |
800eeca4 JW |
4594 | } |
4595 | } | |
4596 | ||
4597 | /* | |
4598 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") | |
4599 | .pred.rel.imply p1, p2 (also .pred.rel "imply") | |
4600 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") | |
4601 | .pred.safe_across_calls p1 [, p2 [,...]] | |
4602 | */ | |
542d6675 | 4603 | |
800eeca4 JW |
4604 | static void |
4605 | dot_pred_rel (type) | |
542d6675 | 4606 | int type; |
800eeca4 JW |
4607 | { |
4608 | valueT mask = 0; | |
4609 | int count = 0; | |
4610 | int p1 = -1, p2 = -1; | |
4611 | ||
4612 | if (type == 0) | |
4613 | { | |
4614 | if (*input_line_pointer != '"') | |
542d6675 KH |
4615 | { |
4616 | as_bad (_("Missing predicate relation type")); | |
4617 | ignore_rest_of_line (); | |
4618 | return; | |
4619 | } | |
197865e8 | 4620 | else |
542d6675 KH |
4621 | { |
4622 | int len; | |
4623 | char *form = demand_copy_C_string (&len); | |
4624 | if (strcmp (form, "mutex") == 0) | |
4625 | type = 'm'; | |
4626 | else if (strcmp (form, "clear") == 0) | |
4627 | type = 'c'; | |
4628 | else if (strcmp (form, "imply") == 0) | |
4629 | type = 'i'; | |
4630 | else | |
4631 | { | |
4632 | as_bad (_("Unrecognized predicate relation type")); | |
4633 | ignore_rest_of_line (); | |
4634 | return; | |
4635 | } | |
4636 | } | |
800eeca4 | 4637 | if (*input_line_pointer == ',') |
542d6675 | 4638 | ++input_line_pointer; |
800eeca4 JW |
4639 | SKIP_WHITESPACE (); |
4640 | } | |
4641 | ||
4642 | SKIP_WHITESPACE (); | |
4643 | while (1) | |
4644 | { | |
4645 | valueT bit = 1; | |
4646 | int regno; | |
197865e8 | 4647 | |
3882b010 | 4648 | if (TOUPPER (*input_line_pointer) != 'P' |
542d6675 KH |
4649 | || (regno = atoi (++input_line_pointer)) < 0 |
4650 | || regno > 63) | |
4651 | { | |
4652 | as_bad (_("Predicate register expected")); | |
4653 | ignore_rest_of_line (); | |
4654 | return; | |
4655 | } | |
3882b010 | 4656 | while (ISDIGIT (*input_line_pointer)) |
542d6675 | 4657 | ++input_line_pointer; |
800eeca4 | 4658 | if (p1 == -1) |
542d6675 | 4659 | p1 = regno; |
800eeca4 | 4660 | else if (p2 == -1) |
542d6675 | 4661 | p2 = regno; |
800eeca4 JW |
4662 | bit <<= regno; |
4663 | if (mask & bit) | |
542d6675 KH |
4664 | as_warn (_("Duplicate predicate register ignored")); |
4665 | mask |= bit; | |
4666 | count++; | |
4667 | /* See if it's a range. */ | |
800eeca4 | 4668 | if (*input_line_pointer == '-') |
542d6675 KH |
4669 | { |
4670 | valueT stop = 1; | |
4671 | ++input_line_pointer; | |
4672 | ||
3882b010 | 4673 | if (TOUPPER (*input_line_pointer) != 'P' |
542d6675 KH |
4674 | || (regno = atoi (++input_line_pointer)) < 0 |
4675 | || regno > 63) | |
4676 | { | |
4677 | as_bad (_("Predicate register expected")); | |
4678 | ignore_rest_of_line (); | |
4679 | return; | |
4680 | } | |
3882b010 | 4681 | while (ISDIGIT (*input_line_pointer)) |
542d6675 KH |
4682 | ++input_line_pointer; |
4683 | stop <<= regno; | |
4684 | if (bit >= stop) | |
4685 | { | |
4686 | as_bad (_("Bad register range")); | |
4687 | ignore_rest_of_line (); | |
4688 | return; | |
4689 | } | |
4690 | while (bit < stop) | |
4691 | { | |
4692 | bit <<= 1; | |
4693 | mask |= bit; | |
4694 | count++; | |
4695 | } | |
4696 | SKIP_WHITESPACE (); | |
4697 | } | |
800eeca4 | 4698 | if (*input_line_pointer != ',') |
542d6675 | 4699 | break; |
800eeca4 JW |
4700 | ++input_line_pointer; |
4701 | SKIP_WHITESPACE (); | |
4702 | } | |
4703 | ||
4704 | switch (type) | |
4705 | { | |
4706 | case 'c': | |
4707 | if (count == 0) | |
542d6675 | 4708 | mask = ~(valueT) 0; |
800eeca4 | 4709 | clear_qp_mutex (mask); |
197865e8 | 4710 | clear_qp_implies (mask, (valueT) 0); |
800eeca4 JW |
4711 | break; |
4712 | case 'i': | |
4713 | if (count != 2 || p1 == -1 || p2 == -1) | |
542d6675 | 4714 | as_bad (_("Predicate source and target required")); |
800eeca4 | 4715 | else if (p1 == 0 || p2 == 0) |
542d6675 | 4716 | as_bad (_("Use of p0 is not valid in this context")); |
800eeca4 | 4717 | else |
542d6675 | 4718 | add_qp_imply (p1, p2); |
800eeca4 JW |
4719 | break; |
4720 | case 'm': | |
4721 | if (count < 2) | |
542d6675 KH |
4722 | { |
4723 | as_bad (_("At least two PR arguments expected")); | |
4724 | break; | |
4725 | } | |
800eeca4 | 4726 | else if (mask & 1) |
542d6675 KH |
4727 | { |
4728 | as_bad (_("Use of p0 is not valid in this context")); | |
4729 | break; | |
4730 | } | |
800eeca4 JW |
4731 | add_qp_mutex (mask); |
4732 | break; | |
4733 | case 's': | |
4734 | /* note that we don't override any existing relations */ | |
4735 | if (count == 0) | |
542d6675 KH |
4736 | { |
4737 | as_bad (_("At least one PR argument expected")); | |
4738 | break; | |
4739 | } | |
800eeca4 | 4740 | if (md.debug_dv) |
542d6675 KH |
4741 | { |
4742 | fprintf (stderr, "Safe across calls: "); | |
4743 | print_prmask (mask); | |
4744 | fprintf (stderr, "\n"); | |
4745 | } | |
800eeca4 JW |
4746 | qp_safe_across_calls = mask; |
4747 | break; | |
4748 | } | |
4749 | demand_empty_rest_of_line (); | |
4750 | } | |
4751 | ||
4752 | /* .entry label [, label [, ...]] | |
4753 | Hint to DV code that the given labels are to be considered entry points. | |
542d6675 KH |
4754 | Otherwise, only global labels are considered entry points. */ |
4755 | ||
800eeca4 JW |
4756 | static void |
4757 | dot_entry (dummy) | |
2434f565 | 4758 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4759 | { |
4760 | const char *err; | |
4761 | char *name; | |
4762 | int c; | |
4763 | symbolS *symbolP; | |
4764 | ||
4765 | do | |
4766 | { | |
4767 | name = input_line_pointer; | |
4768 | c = get_symbol_end (); | |
4769 | symbolP = symbol_find_or_make (name); | |
4770 | ||
4771 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); | |
4772 | if (err) | |
542d6675 KH |
4773 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
4774 | name, err); | |
800eeca4 JW |
4775 | |
4776 | *input_line_pointer = c; | |
4777 | SKIP_WHITESPACE (); | |
4778 | c = *input_line_pointer; | |
4779 | if (c == ',') | |
4780 | { | |
4781 | input_line_pointer++; | |
4782 | SKIP_WHITESPACE (); | |
4783 | if (*input_line_pointer == '\n') | |
4784 | c = '\n'; | |
4785 | } | |
4786 | } | |
4787 | while (c == ','); | |
4788 | ||
4789 | demand_empty_rest_of_line (); | |
4790 | } | |
4791 | ||
197865e8 | 4792 | /* .mem.offset offset, base |
542d6675 KH |
4793 | "base" is used to distinguish between offsets from a different base. */ |
4794 | ||
800eeca4 JW |
4795 | static void |
4796 | dot_mem_offset (dummy) | |
2434f565 | 4797 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4798 | { |
4799 | md.mem_offset.hint = 1; | |
4800 | md.mem_offset.offset = get_absolute_expression (); | |
4801 | if (*input_line_pointer != ',') | |
4802 | { | |
4803 | as_bad (_("Comma expected")); | |
4804 | ignore_rest_of_line (); | |
4805 | return; | |
4806 | } | |
4807 | ++input_line_pointer; | |
4808 | md.mem_offset.base = get_absolute_expression (); | |
4809 | demand_empty_rest_of_line (); | |
4810 | } | |
4811 | ||
542d6675 | 4812 | /* ia64-specific pseudo-ops: */ |
800eeca4 JW |
4813 | const pseudo_typeS md_pseudo_table[] = |
4814 | { | |
4815 | { "radix", dot_radix, 0 }, | |
4816 | { "lcomm", s_lcomm_bytes, 1 }, | |
4817 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, | |
4818 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, | |
4819 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, | |
4820 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, | |
4821 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, | |
4822 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, | |
4823 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, | |
557debba JW |
4824 | { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, |
4825 | { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, | |
800eeca4 JW |
4826 | { "proc", dot_proc, 0 }, |
4827 | { "body", dot_body, 0 }, | |
4828 | { "prologue", dot_prologue, 0 }, | |
2434f565 | 4829 | { "endp", dot_endp, 0 }, |
9f1838ed | 4830 | { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 }, |
2434f565 JW |
4831 | { "loc", dwarf2_directive_loc, 0 }, |
4832 | ||
4833 | { "fframe", dot_fframe, 0 }, | |
4834 | { "vframe", dot_vframe, 0 }, | |
4835 | { "vframesp", dot_vframesp, 0 }, | |
4836 | { "vframepsp", dot_vframepsp, 0 }, | |
4837 | { "save", dot_save, 0 }, | |
4838 | { "restore", dot_restore, 0 }, | |
4839 | { "restorereg", dot_restorereg, 0 }, | |
4840 | { "restorereg.p", dot_restorereg_p, 0 }, | |
4841 | { "handlerdata", dot_handlerdata, 0 }, | |
4842 | { "unwentry", dot_unwentry, 0 }, | |
4843 | { "altrp", dot_altrp, 0 }, | |
e0c9811a JW |
4844 | { "savesp", dot_savemem, 0 }, |
4845 | { "savepsp", dot_savemem, 1 }, | |
2434f565 JW |
4846 | { "save.g", dot_saveg, 0 }, |
4847 | { "save.f", dot_savef, 0 }, | |
4848 | { "save.b", dot_saveb, 0 }, | |
4849 | { "save.gf", dot_savegf, 0 }, | |
4850 | { "spill", dot_spill, 0 }, | |
4851 | { "spillreg", dot_spillreg, 0 }, | |
e0c9811a JW |
4852 | { "spillsp", dot_spillmem, 0 }, |
4853 | { "spillpsp", dot_spillmem, 1 }, | |
2434f565 | 4854 | { "spillreg.p", dot_spillreg_p, 0 }, |
e0c9811a JW |
4855 | { "spillsp.p", dot_spillmem_p, 0 }, |
4856 | { "spillpsp.p", dot_spillmem_p, 1 }, | |
2434f565 JW |
4857 | { "label_state", dot_label_state, 0 }, |
4858 | { "copy_state", dot_copy_state, 0 }, | |
4859 | { "unwabi", dot_unwabi, 0 }, | |
4860 | { "personality", dot_personality, 0 }, | |
800eeca4 | 4861 | #if 0 |
2434f565 | 4862 | { "estate", dot_estate, 0 }, |
800eeca4 JW |
4863 | #endif |
4864 | { "mii", dot_template, 0x0 }, | |
4865 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ | |
4866 | { "mlx", dot_template, 0x2 }, | |
4867 | { "mmi", dot_template, 0x4 }, | |
4868 | { "mfi", dot_template, 0x6 }, | |
4869 | { "mmf", dot_template, 0x7 }, | |
4870 | { "mib", dot_template, 0x8 }, | |
4871 | { "mbb", dot_template, 0x9 }, | |
4872 | { "bbb", dot_template, 0xb }, | |
4873 | { "mmb", dot_template, 0xc }, | |
4874 | { "mfb", dot_template, 0xe }, | |
4875 | #if 0 | |
4876 | { "lb", dot_scope, 0 }, | |
4877 | { "le", dot_scope, 1 }, | |
4878 | #endif | |
4879 | { "align", s_align_bytes, 0 }, | |
4880 | { "regstk", dot_regstk, 0 }, | |
4881 | { "rotr", dot_rot, DYNREG_GR }, | |
4882 | { "rotf", dot_rot, DYNREG_FR }, | |
4883 | { "rotp", dot_rot, DYNREG_PR }, | |
4884 | { "lsb", dot_byteorder, 0 }, | |
4885 | { "msb", dot_byteorder, 1 }, | |
4886 | { "psr", dot_psr, 0 }, | |
4887 | { "alias", dot_alias, 0 }, | |
4888 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ | |
4889 | ||
4890 | { "xdata1", dot_xdata, 1 }, | |
4891 | { "xdata2", dot_xdata, 2 }, | |
4892 | { "xdata4", dot_xdata, 4 }, | |
4893 | { "xdata8", dot_xdata, 8 }, | |
4894 | { "xreal4", dot_xfloat_cons, 'f' }, | |
4895 | { "xreal8", dot_xfloat_cons, 'd' }, | |
4896 | { "xreal10", dot_xfloat_cons, 'x' }, | |
4897 | { "xstring", dot_xstringer, 0 }, | |
4898 | { "xstringz", dot_xstringer, 1 }, | |
4899 | ||
542d6675 | 4900 | /* unaligned versions: */ |
800eeca4 JW |
4901 | { "xdata2.ua", dot_xdata_ua, 2 }, |
4902 | { "xdata4.ua", dot_xdata_ua, 4 }, | |
4903 | { "xdata8.ua", dot_xdata_ua, 8 }, | |
4904 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, | |
4905 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, | |
4906 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, | |
4907 | ||
4908 | /* annotations/DV checking support */ | |
4909 | { "entry", dot_entry, 0 }, | |
2434f565 | 4910 | { "mem.offset", dot_mem_offset, 0 }, |
800eeca4 JW |
4911 | { "pred.rel", dot_pred_rel, 0 }, |
4912 | { "pred.rel.clear", dot_pred_rel, 'c' }, | |
4913 | { "pred.rel.imply", dot_pred_rel, 'i' }, | |
4914 | { "pred.rel.mutex", dot_pred_rel, 'm' }, | |
4915 | { "pred.safe_across_calls", dot_pred_rel, 's' }, | |
2434f565 | 4916 | { "reg.val", dot_reg_val, 0 }, |
800eeca4 JW |
4917 | { "auto", dot_dv_mode, 'a' }, |
4918 | { "explicit", dot_dv_mode, 'e' }, | |
4919 | { "default", dot_dv_mode, 'd' }, | |
4920 | ||
87885043 JW |
4921 | /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. |
4922 | IA-64 aligns data allocation pseudo-ops by default, so we have to | |
4923 | tell it that these ones are supposed to be unaligned. Long term, | |
4924 | should rewrite so that only IA-64 specific data allocation pseudo-ops | |
4925 | are aligned by default. */ | |
4926 | {"2byte", stmt_cons_ua, 2}, | |
4927 | {"4byte", stmt_cons_ua, 4}, | |
4928 | {"8byte", stmt_cons_ua, 8}, | |
4929 | ||
800eeca4 JW |
4930 | { NULL, 0, 0 } |
4931 | }; | |
4932 | ||
4933 | static const struct pseudo_opcode | |
4934 | { | |
4935 | const char *name; | |
4936 | void (*handler) (int); | |
4937 | int arg; | |
4938 | } | |
4939 | pseudo_opcode[] = | |
4940 | { | |
4941 | /* these are more like pseudo-ops, but don't start with a dot */ | |
4942 | { "data1", cons, 1 }, | |
4943 | { "data2", cons, 2 }, | |
4944 | { "data4", cons, 4 }, | |
4945 | { "data8", cons, 8 }, | |
3969b680 | 4946 | { "data16", cons, 16 }, |
800eeca4 JW |
4947 | { "real4", stmt_float_cons, 'f' }, |
4948 | { "real8", stmt_float_cons, 'd' }, | |
4949 | { "real10", stmt_float_cons, 'x' }, | |
4950 | { "string", stringer, 0 }, | |
4951 | { "stringz", stringer, 1 }, | |
4952 | ||
542d6675 | 4953 | /* unaligned versions: */ |
800eeca4 JW |
4954 | { "data2.ua", stmt_cons_ua, 2 }, |
4955 | { "data4.ua", stmt_cons_ua, 4 }, | |
4956 | { "data8.ua", stmt_cons_ua, 8 }, | |
3969b680 | 4957 | { "data16.ua", stmt_cons_ua, 16 }, |
800eeca4 JW |
4958 | { "real4.ua", float_cons, 'f' }, |
4959 | { "real8.ua", float_cons, 'd' }, | |
4960 | { "real10.ua", float_cons, 'x' }, | |
4961 | }; | |
4962 | ||
4963 | /* Declare a register by creating a symbol for it and entering it in | |
4964 | the symbol table. */ | |
542d6675 KH |
4965 | |
4966 | static symbolS * | |
800eeca4 JW |
4967 | declare_register (name, regnum) |
4968 | const char *name; | |
4969 | int regnum; | |
4970 | { | |
4971 | const char *err; | |
4972 | symbolS *sym; | |
4973 | ||
4974 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); | |
4975 | ||
4976 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); | |
4977 | if (err) | |
4978 | as_fatal ("Inserting \"%s\" into register table failed: %s", | |
4979 | name, err); | |
4980 | ||
4981 | return sym; | |
4982 | } | |
4983 | ||
4984 | static void | |
4985 | declare_register_set (prefix, num_regs, base_regnum) | |
4986 | const char *prefix; | |
4987 | int num_regs; | |
4988 | int base_regnum; | |
4989 | { | |
4990 | char name[8]; | |
4991 | int i; | |
4992 | ||
4993 | for (i = 0; i < num_regs; ++i) | |
4994 | { | |
4995 | sprintf (name, "%s%u", prefix, i); | |
4996 | declare_register (name, base_regnum + i); | |
4997 | } | |
4998 | } | |
4999 | ||
5000 | static unsigned int | |
5001 | operand_width (opnd) | |
5002 | enum ia64_opnd opnd; | |
5003 | { | |
5004 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; | |
5005 | unsigned int bits = 0; | |
5006 | int i; | |
5007 | ||
5008 | bits = 0; | |
5009 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) | |
5010 | bits += odesc->field[i].bits; | |
5011 | ||
5012 | return bits; | |
5013 | } | |
5014 | ||
87f8eb97 | 5015 | static enum operand_match_result |
800eeca4 JW |
5016 | operand_match (idesc, index, e) |
5017 | const struct ia64_opcode *idesc; | |
5018 | int index; | |
5019 | expressionS *e; | |
5020 | { | |
5021 | enum ia64_opnd opnd = idesc->operands[index]; | |
5022 | int bits, relocatable = 0; | |
5023 | struct insn_fix *fix; | |
5024 | bfd_signed_vma val; | |
5025 | ||
5026 | switch (opnd) | |
5027 | { | |
542d6675 | 5028 | /* constants: */ |
800eeca4 JW |
5029 | |
5030 | case IA64_OPND_AR_CCV: | |
5031 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) | |
87f8eb97 | 5032 | return OPERAND_MATCH; |
800eeca4 JW |
5033 | break; |
5034 | ||
5035 | case IA64_OPND_AR_PFS: | |
5036 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) | |
87f8eb97 | 5037 | return OPERAND_MATCH; |
800eeca4 JW |
5038 | break; |
5039 | ||
5040 | case IA64_OPND_GR0: | |
5041 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) | |
87f8eb97 | 5042 | return OPERAND_MATCH; |
800eeca4 JW |
5043 | break; |
5044 | ||
5045 | case IA64_OPND_IP: | |
5046 | if (e->X_op == O_register && e->X_add_number == REG_IP) | |
87f8eb97 | 5047 | return OPERAND_MATCH; |
800eeca4 JW |
5048 | break; |
5049 | ||
5050 | case IA64_OPND_PR: | |
5051 | if (e->X_op == O_register && e->X_add_number == REG_PR) | |
87f8eb97 | 5052 | return OPERAND_MATCH; |
800eeca4 JW |
5053 | break; |
5054 | ||
5055 | case IA64_OPND_PR_ROT: | |
5056 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) | |
87f8eb97 | 5057 | return OPERAND_MATCH; |
800eeca4 JW |
5058 | break; |
5059 | ||
5060 | case IA64_OPND_PSR: | |
5061 | if (e->X_op == O_register && e->X_add_number == REG_PSR) | |
87f8eb97 | 5062 | return OPERAND_MATCH; |
800eeca4 JW |
5063 | break; |
5064 | ||
5065 | case IA64_OPND_PSR_L: | |
5066 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) | |
87f8eb97 | 5067 | return OPERAND_MATCH; |
800eeca4 JW |
5068 | break; |
5069 | ||
5070 | case IA64_OPND_PSR_UM: | |
5071 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) | |
87f8eb97 | 5072 | return OPERAND_MATCH; |
800eeca4 JW |
5073 | break; |
5074 | ||
5075 | case IA64_OPND_C1: | |
87f8eb97 JW |
5076 | if (e->X_op == O_constant) |
5077 | { | |
5078 | if (e->X_add_number == 1) | |
5079 | return OPERAND_MATCH; | |
5080 | else | |
5081 | return OPERAND_OUT_OF_RANGE; | |
5082 | } | |
800eeca4 JW |
5083 | break; |
5084 | ||
5085 | case IA64_OPND_C8: | |
87f8eb97 JW |
5086 | if (e->X_op == O_constant) |
5087 | { | |
5088 | if (e->X_add_number == 8) | |
5089 | return OPERAND_MATCH; | |
5090 | else | |
5091 | return OPERAND_OUT_OF_RANGE; | |
5092 | } | |
800eeca4 JW |
5093 | break; |
5094 | ||
5095 | case IA64_OPND_C16: | |
87f8eb97 JW |
5096 | if (e->X_op == O_constant) |
5097 | { | |
5098 | if (e->X_add_number == 16) | |
5099 | return OPERAND_MATCH; | |
5100 | else | |
5101 | return OPERAND_OUT_OF_RANGE; | |
5102 | } | |
800eeca4 JW |
5103 | break; |
5104 | ||
542d6675 | 5105 | /* register operands: */ |
800eeca4 JW |
5106 | |
5107 | case IA64_OPND_AR3: | |
5108 | if (e->X_op == O_register && e->X_add_number >= REG_AR | |
5109 | && e->X_add_number < REG_AR + 128) | |
87f8eb97 | 5110 | return OPERAND_MATCH; |
800eeca4 JW |
5111 | break; |
5112 | ||
5113 | case IA64_OPND_B1: | |
5114 | case IA64_OPND_B2: | |
5115 | if (e->X_op == O_register && e->X_add_number >= REG_BR | |
5116 | && e->X_add_number < REG_BR + 8) | |
87f8eb97 | 5117 | return OPERAND_MATCH; |
800eeca4 JW |
5118 | break; |
5119 | ||
5120 | case IA64_OPND_CR3: | |
5121 | if (e->X_op == O_register && e->X_add_number >= REG_CR | |
5122 | && e->X_add_number < REG_CR + 128) | |
87f8eb97 | 5123 | return OPERAND_MATCH; |
800eeca4 JW |
5124 | break; |
5125 | ||
5126 | case IA64_OPND_F1: | |
5127 | case IA64_OPND_F2: | |
5128 | case IA64_OPND_F3: | |
5129 | case IA64_OPND_F4: | |
5130 | if (e->X_op == O_register && e->X_add_number >= REG_FR | |
5131 | && e->X_add_number < REG_FR + 128) | |
87f8eb97 | 5132 | return OPERAND_MATCH; |
800eeca4 JW |
5133 | break; |
5134 | ||
5135 | case IA64_OPND_P1: | |
5136 | case IA64_OPND_P2: | |
5137 | if (e->X_op == O_register && e->X_add_number >= REG_P | |
5138 | && e->X_add_number < REG_P + 64) | |
87f8eb97 | 5139 | return OPERAND_MATCH; |
800eeca4 JW |
5140 | break; |
5141 | ||
5142 | case IA64_OPND_R1: | |
5143 | case IA64_OPND_R2: | |
5144 | case IA64_OPND_R3: | |
5145 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
5146 | && e->X_add_number < REG_GR + 128) | |
87f8eb97 | 5147 | return OPERAND_MATCH; |
800eeca4 JW |
5148 | break; |
5149 | ||
5150 | case IA64_OPND_R3_2: | |
87f8eb97 | 5151 | if (e->X_op == O_register && e->X_add_number >= REG_GR) |
40449e9f | 5152 | { |
87f8eb97 JW |
5153 | if (e->X_add_number < REG_GR + 4) |
5154 | return OPERAND_MATCH; | |
5155 | else if (e->X_add_number < REG_GR + 128) | |
5156 | return OPERAND_OUT_OF_RANGE; | |
5157 | } | |
800eeca4 JW |
5158 | break; |
5159 | ||
542d6675 | 5160 | /* indirect operands: */ |
800eeca4 JW |
5161 | case IA64_OPND_CPUID_R3: |
5162 | case IA64_OPND_DBR_R3: | |
5163 | case IA64_OPND_DTR_R3: | |
5164 | case IA64_OPND_ITR_R3: | |
5165 | case IA64_OPND_IBR_R3: | |
5166 | case IA64_OPND_MSR_R3: | |
5167 | case IA64_OPND_PKR_R3: | |
5168 | case IA64_OPND_PMC_R3: | |
5169 | case IA64_OPND_PMD_R3: | |
5170 | case IA64_OPND_RR_R3: | |
5171 | if (e->X_op == O_index && e->X_op_symbol | |
5172 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID | |
5173 | == opnd - IA64_OPND_CPUID_R3)) | |
87f8eb97 | 5174 | return OPERAND_MATCH; |
800eeca4 JW |
5175 | break; |
5176 | ||
5177 | case IA64_OPND_MR3: | |
5178 | if (e->X_op == O_index && !e->X_op_symbol) | |
87f8eb97 | 5179 | return OPERAND_MATCH; |
800eeca4 JW |
5180 | break; |
5181 | ||
542d6675 | 5182 | /* immediate operands: */ |
800eeca4 JW |
5183 | case IA64_OPND_CNT2a: |
5184 | case IA64_OPND_LEN4: | |
5185 | case IA64_OPND_LEN6: | |
5186 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 JW |
5187 | if (e->X_op == O_constant) |
5188 | { | |
5189 | if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) | |
5190 | return OPERAND_MATCH; | |
5191 | else | |
5192 | return OPERAND_OUT_OF_RANGE; | |
5193 | } | |
800eeca4 JW |
5194 | break; |
5195 | ||
5196 | case IA64_OPND_CNT2b: | |
87f8eb97 JW |
5197 | if (e->X_op == O_constant) |
5198 | { | |
5199 | if ((bfd_vma) (e->X_add_number - 1) < 3) | |
5200 | return OPERAND_MATCH; | |
5201 | else | |
5202 | return OPERAND_OUT_OF_RANGE; | |
5203 | } | |
800eeca4 JW |
5204 | break; |
5205 | ||
5206 | case IA64_OPND_CNT2c: | |
5207 | val = e->X_add_number; | |
87f8eb97 JW |
5208 | if (e->X_op == O_constant) |
5209 | { | |
5210 | if ((val == 0 || val == 7 || val == 15 || val == 16)) | |
5211 | return OPERAND_MATCH; | |
5212 | else | |
5213 | return OPERAND_OUT_OF_RANGE; | |
5214 | } | |
800eeca4 JW |
5215 | break; |
5216 | ||
5217 | case IA64_OPND_SOR: | |
5218 | /* SOR must be an integer multiple of 8 */ | |
87f8eb97 JW |
5219 | if (e->X_op == O_constant && e->X_add_number & 0x7) |
5220 | return OPERAND_OUT_OF_RANGE; | |
800eeca4 JW |
5221 | case IA64_OPND_SOF: |
5222 | case IA64_OPND_SOL: | |
87f8eb97 JW |
5223 | if (e->X_op == O_constant) |
5224 | { | |
5225 | if ((bfd_vma) e->X_add_number <= 96) | |
5226 | return OPERAND_MATCH; | |
5227 | else | |
5228 | return OPERAND_OUT_OF_RANGE; | |
5229 | } | |
800eeca4 JW |
5230 | break; |
5231 | ||
5232 | case IA64_OPND_IMMU62: | |
5233 | if (e->X_op == O_constant) | |
542d6675 | 5234 | { |
800eeca4 | 5235 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
87f8eb97 JW |
5236 | return OPERAND_MATCH; |
5237 | else | |
5238 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5239 | } |
197865e8 | 5240 | else |
542d6675 KH |
5241 | { |
5242 | /* FIXME -- need 62-bit relocation type */ | |
5243 | as_bad (_("62-bit relocation not yet implemented")); | |
5244 | } | |
800eeca4 JW |
5245 | break; |
5246 | ||
5247 | case IA64_OPND_IMMU64: | |
5248 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup | |
5249 | || e->X_op == O_subtract) | |
5250 | { | |
5251 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5252 | fix->code = BFD_RELOC_IA64_IMM64; | |
5253 | if (e->X_op != O_subtract) | |
5254 | { | |
5255 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
5256 | if (e->X_op == O_pseudo_fixup) | |
5257 | e->X_op = O_symbol; | |
5258 | } | |
5259 | ||
5260 | fix->opnd = idesc->operands[index]; | |
5261 | fix->expr = *e; | |
5262 | fix->is_pcrel = 0; | |
5263 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5264 | return OPERAND_MATCH; |
800eeca4 JW |
5265 | } |
5266 | else if (e->X_op == O_constant) | |
87f8eb97 | 5267 | return OPERAND_MATCH; |
800eeca4 JW |
5268 | break; |
5269 | ||
5270 | case IA64_OPND_CCNT5: | |
5271 | case IA64_OPND_CNT5: | |
5272 | case IA64_OPND_CNT6: | |
5273 | case IA64_OPND_CPOS6a: | |
5274 | case IA64_OPND_CPOS6b: | |
5275 | case IA64_OPND_CPOS6c: | |
5276 | case IA64_OPND_IMMU2: | |
5277 | case IA64_OPND_IMMU7a: | |
5278 | case IA64_OPND_IMMU7b: | |
800eeca4 JW |
5279 | case IA64_OPND_IMMU21: |
5280 | case IA64_OPND_IMMU24: | |
5281 | case IA64_OPND_MBTYPE4: | |
5282 | case IA64_OPND_MHTYPE8: | |
5283 | case IA64_OPND_POS6: | |
5284 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 JW |
5285 | if (e->X_op == O_constant) |
5286 | { | |
5287 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
5288 | return OPERAND_MATCH; | |
5289 | else | |
5290 | return OPERAND_OUT_OF_RANGE; | |
5291 | } | |
800eeca4 JW |
5292 | break; |
5293 | ||
bf3ca999 TW |
5294 | case IA64_OPND_IMMU9: |
5295 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 | 5296 | if (e->X_op == O_constant) |
542d6675 | 5297 | { |
87f8eb97 JW |
5298 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
5299 | { | |
5300 | int lobits = e->X_add_number & 0x3; | |
5301 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) | |
5302 | e->X_add_number |= (bfd_vma) 0x3; | |
5303 | return OPERAND_MATCH; | |
5304 | } | |
5305 | else | |
5306 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5307 | } |
bf3ca999 TW |
5308 | break; |
5309 | ||
800eeca4 JW |
5310 | case IA64_OPND_IMM44: |
5311 | /* least 16 bits must be zero */ | |
5312 | if ((e->X_add_number & 0xffff) != 0) | |
87f8eb97 JW |
5313 | /* XXX technically, this is wrong: we should not be issuing warning |
5314 | messages until we're sure this instruction pattern is going to | |
5315 | be used! */ | |
542d6675 | 5316 | as_warn (_("lower 16 bits of mask ignored")); |
800eeca4 | 5317 | |
87f8eb97 | 5318 | if (e->X_op == O_constant) |
542d6675 | 5319 | { |
87f8eb97 JW |
5320 | if (((e->X_add_number >= 0 |
5321 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) | |
5322 | || (e->X_add_number < 0 | |
5323 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) | |
542d6675 | 5324 | { |
87f8eb97 JW |
5325 | /* sign-extend */ |
5326 | if (e->X_add_number >= 0 | |
5327 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) | |
5328 | { | |
5329 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); | |
5330 | } | |
5331 | return OPERAND_MATCH; | |
542d6675 | 5332 | } |
87f8eb97 JW |
5333 | else |
5334 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5335 | } |
800eeca4 JW |
5336 | break; |
5337 | ||
5338 | case IA64_OPND_IMM17: | |
5339 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ | |
87f8eb97 | 5340 | if (e->X_op == O_constant) |
542d6675 | 5341 | { |
87f8eb97 JW |
5342 | if (((e->X_add_number >= 0 |
5343 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) | |
5344 | || (e->X_add_number < 0 | |
5345 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) | |
542d6675 | 5346 | { |
87f8eb97 JW |
5347 | /* sign-extend */ |
5348 | if (e->X_add_number >= 0 | |
5349 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) | |
5350 | { | |
5351 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); | |
5352 | } | |
5353 | return OPERAND_MATCH; | |
542d6675 | 5354 | } |
87f8eb97 JW |
5355 | else |
5356 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5357 | } |
800eeca4 JW |
5358 | break; |
5359 | ||
5360 | case IA64_OPND_IMM14: | |
5361 | case IA64_OPND_IMM22: | |
5362 | relocatable = 1; | |
5363 | case IA64_OPND_IMM1: | |
5364 | case IA64_OPND_IMM8: | |
5365 | case IA64_OPND_IMM8U4: | |
5366 | case IA64_OPND_IMM8M1: | |
5367 | case IA64_OPND_IMM8M1U4: | |
5368 | case IA64_OPND_IMM8M1U8: | |
5369 | case IA64_OPND_IMM9a: | |
5370 | case IA64_OPND_IMM9b: | |
5371 | bits = operand_width (idesc->operands[index]); | |
5372 | if (relocatable && (e->X_op == O_symbol | |
5373 | || e->X_op == O_subtract | |
5374 | || e->X_op == O_pseudo_fixup)) | |
5375 | { | |
5376 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5377 | ||
5378 | if (idesc->operands[index] == IA64_OPND_IMM14) | |
5379 | fix->code = BFD_RELOC_IA64_IMM14; | |
5380 | else | |
5381 | fix->code = BFD_RELOC_IA64_IMM22; | |
5382 | ||
5383 | if (e->X_op != O_subtract) | |
5384 | { | |
5385 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
5386 | if (e->X_op == O_pseudo_fixup) | |
5387 | e->X_op = O_symbol; | |
5388 | } | |
5389 | ||
5390 | fix->opnd = idesc->operands[index]; | |
5391 | fix->expr = *e; | |
5392 | fix->is_pcrel = 0; | |
5393 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5394 | return OPERAND_MATCH; |
800eeca4 JW |
5395 | } |
5396 | else if (e->X_op != O_constant | |
5397 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) | |
87f8eb97 | 5398 | return OPERAND_MISMATCH; |
800eeca4 JW |
5399 | |
5400 | if (opnd == IA64_OPND_IMM8M1U4) | |
5401 | { | |
5402 | /* Zero is not valid for unsigned compares that take an adjusted | |
5403 | constant immediate range. */ | |
5404 | if (e->X_add_number == 0) | |
87f8eb97 | 5405 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5406 | |
5407 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
5408 | checks will work. */ | |
5409 | val = e->X_add_number; | |
197865e8 KH |
5410 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
5411 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
5412 | val = ((val << 32) >> 32); |
5413 | ||
5414 | /* Check for 0x100000000. This is valid because | |
5415 | 0x100000000-1 is the same as ((uint32_t) -1). */ | |
5416 | if (val == ((bfd_signed_vma) 1 << 32)) | |
87f8eb97 | 5417 | return OPERAND_MATCH; |
800eeca4 JW |
5418 | |
5419 | val = val - 1; | |
5420 | } | |
5421 | else if (opnd == IA64_OPND_IMM8M1U8) | |
5422 | { | |
5423 | /* Zero is not valid for unsigned compares that take an adjusted | |
5424 | constant immediate range. */ | |
5425 | if (e->X_add_number == 0) | |
87f8eb97 | 5426 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5427 | |
5428 | /* Check for 0x10000000000000000. */ | |
5429 | if (e->X_op == O_big) | |
5430 | { | |
5431 | if (generic_bignum[0] == 0 | |
5432 | && generic_bignum[1] == 0 | |
5433 | && generic_bignum[2] == 0 | |
5434 | && generic_bignum[3] == 0 | |
5435 | && generic_bignum[4] == 1) | |
87f8eb97 | 5436 | return OPERAND_MATCH; |
800eeca4 | 5437 | else |
87f8eb97 | 5438 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5439 | } |
5440 | else | |
5441 | val = e->X_add_number - 1; | |
5442 | } | |
5443 | else if (opnd == IA64_OPND_IMM8M1) | |
5444 | val = e->X_add_number - 1; | |
5445 | else if (opnd == IA64_OPND_IMM8U4) | |
5446 | { | |
5447 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
5448 | checks will work. */ | |
5449 | val = e->X_add_number; | |
197865e8 KH |
5450 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
5451 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
5452 | val = ((val << 32) >> 32); |
5453 | } | |
5454 | else | |
5455 | val = e->X_add_number; | |
5456 | ||
2434f565 JW |
5457 | if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) |
5458 | || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) | |
87f8eb97 JW |
5459 | return OPERAND_MATCH; |
5460 | else | |
5461 | return OPERAND_OUT_OF_RANGE; | |
800eeca4 JW |
5462 | |
5463 | case IA64_OPND_INC3: | |
5464 | /* +/- 1, 4, 8, 16 */ | |
5465 | val = e->X_add_number; | |
5466 | if (val < 0) | |
5467 | val = -val; | |
87f8eb97 JW |
5468 | if (e->X_op == O_constant) |
5469 | { | |
5470 | if ((val == 1 || val == 4 || val == 8 || val == 16)) | |
5471 | return OPERAND_MATCH; | |
5472 | else | |
5473 | return OPERAND_OUT_OF_RANGE; | |
5474 | } | |
800eeca4 JW |
5475 | break; |
5476 | ||
5477 | case IA64_OPND_TGT25: | |
5478 | case IA64_OPND_TGT25b: | |
5479 | case IA64_OPND_TGT25c: | |
5480 | case IA64_OPND_TGT64: | |
5481 | if (e->X_op == O_symbol) | |
5482 | { | |
5483 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5484 | if (opnd == IA64_OPND_TGT25) | |
5485 | fix->code = BFD_RELOC_IA64_PCREL21F; | |
5486 | else if (opnd == IA64_OPND_TGT25b) | |
5487 | fix->code = BFD_RELOC_IA64_PCREL21M; | |
5488 | else if (opnd == IA64_OPND_TGT25c) | |
5489 | fix->code = BFD_RELOC_IA64_PCREL21B; | |
542d6675 | 5490 | else if (opnd == IA64_OPND_TGT64) |
c67e42c9 RH |
5491 | fix->code = BFD_RELOC_IA64_PCREL60B; |
5492 | else | |
5493 | abort (); | |
5494 | ||
800eeca4 JW |
5495 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
5496 | fix->opnd = idesc->operands[index]; | |
5497 | fix->expr = *e; | |
5498 | fix->is_pcrel = 1; | |
5499 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5500 | return OPERAND_MATCH; |
800eeca4 JW |
5501 | } |
5502 | case IA64_OPND_TAG13: | |
5503 | case IA64_OPND_TAG13b: | |
5504 | switch (e->X_op) | |
5505 | { | |
5506 | case O_constant: | |
87f8eb97 | 5507 | return OPERAND_MATCH; |
800eeca4 JW |
5508 | |
5509 | case O_symbol: | |
5510 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
fa1cb89c JW |
5511 | /* There are no external relocs for TAG13/TAG13b fields, so we |
5512 | create a dummy reloc. This will not live past md_apply_fix3. */ | |
5513 | fix->code = BFD_RELOC_UNUSED; | |
5514 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
800eeca4 JW |
5515 | fix->opnd = idesc->operands[index]; |
5516 | fix->expr = *e; | |
5517 | fix->is_pcrel = 1; | |
5518 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5519 | return OPERAND_MATCH; |
800eeca4 JW |
5520 | |
5521 | default: | |
5522 | break; | |
5523 | } | |
5524 | break; | |
5525 | ||
5526 | default: | |
5527 | break; | |
5528 | } | |
87f8eb97 | 5529 | return OPERAND_MISMATCH; |
800eeca4 JW |
5530 | } |
5531 | ||
5532 | static int | |
5533 | parse_operand (e) | |
5534 | expressionS *e; | |
5535 | { | |
5536 | int sep = '\0'; | |
5537 | ||
5538 | memset (e, 0, sizeof (*e)); | |
5539 | e->X_op = O_absent; | |
5540 | SKIP_WHITESPACE (); | |
5541 | if (*input_line_pointer != '}') | |
5542 | expression (e); | |
5543 | sep = *input_line_pointer++; | |
5544 | ||
5545 | if (sep == '}') | |
5546 | { | |
5547 | if (!md.manual_bundling) | |
5548 | as_warn ("Found '}' when manual bundling is off"); | |
5549 | else | |
5550 | CURR_SLOT.manual_bundling_off = 1; | |
5551 | md.manual_bundling = 0; | |
5552 | sep = '\0'; | |
5553 | } | |
5554 | return sep; | |
5555 | } | |
5556 | ||
5557 | /* Returns the next entry in the opcode table that matches the one in | |
5558 | IDESC, and frees the entry in IDESC. If no matching entry is | |
197865e8 | 5559 | found, NULL is returned instead. */ |
800eeca4 JW |
5560 | |
5561 | static struct ia64_opcode * | |
5562 | get_next_opcode (struct ia64_opcode *idesc) | |
5563 | { | |
5564 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); | |
5565 | ia64_free_opcode (idesc); | |
5566 | return next; | |
5567 | } | |
5568 | ||
5569 | /* Parse the operands for the opcode and find the opcode variant that | |
5570 | matches the specified operands, or NULL if no match is possible. */ | |
542d6675 KH |
5571 | |
5572 | static struct ia64_opcode * | |
800eeca4 JW |
5573 | parse_operands (idesc) |
5574 | struct ia64_opcode *idesc; | |
5575 | { | |
5576 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; | |
87f8eb97 | 5577 | int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; |
800eeca4 | 5578 | enum ia64_opnd expected_operand = IA64_OPND_NIL; |
87f8eb97 | 5579 | enum operand_match_result result; |
800eeca4 JW |
5580 | char mnemonic[129]; |
5581 | char *first_arg = 0, *end, *saved_input_pointer; | |
5582 | unsigned int sof; | |
5583 | ||
5584 | assert (strlen (idesc->name) <= 128); | |
5585 | ||
5586 | strcpy (mnemonic, idesc->name); | |
5587 | if (idesc->operands[2] == IA64_OPND_SOF) | |
5588 | { | |
5589 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we | |
5590 | can't parse the first operand until we have parsed the | |
5591 | remaining operands of the "alloc" instruction. */ | |
5592 | SKIP_WHITESPACE (); | |
5593 | first_arg = input_line_pointer; | |
5594 | end = strchr (input_line_pointer, '='); | |
5595 | if (!end) | |
5596 | { | |
5597 | as_bad ("Expected separator `='"); | |
5598 | return 0; | |
5599 | } | |
5600 | input_line_pointer = end + 1; | |
5601 | ++i; | |
5602 | ++num_outputs; | |
5603 | } | |
5604 | ||
5605 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) | |
5606 | { | |
5607 | sep = parse_operand (CURR_SLOT.opnd + i); | |
5608 | if (CURR_SLOT.opnd[i].X_op == O_absent) | |
5609 | break; | |
5610 | ||
5611 | ++num_operands; | |
5612 | ||
5613 | if (sep != '=' && sep != ',') | |
5614 | break; | |
5615 | ||
5616 | if (sep == '=') | |
5617 | { | |
5618 | if (num_outputs > 0) | |
5619 | as_bad ("Duplicate equal sign (=) in instruction"); | |
5620 | else | |
5621 | num_outputs = i + 1; | |
5622 | } | |
5623 | } | |
5624 | if (sep != '\0') | |
5625 | { | |
5626 | as_bad ("Illegal operand separator `%c'", sep); | |
5627 | return 0; | |
5628 | } | |
197865e8 | 5629 | |
800eeca4 JW |
5630 | if (idesc->operands[2] == IA64_OPND_SOF) |
5631 | { | |
5632 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ | |
5633 | know (strcmp (idesc->name, "alloc") == 0); | |
5634 | if (num_operands == 5 /* first_arg not included in this count! */ | |
5635 | && CURR_SLOT.opnd[2].X_op == O_constant | |
5636 | && CURR_SLOT.opnd[3].X_op == O_constant | |
5637 | && CURR_SLOT.opnd[4].X_op == O_constant | |
5638 | && CURR_SLOT.opnd[5].X_op == O_constant) | |
5639 | { | |
5640 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, | |
5641 | CURR_SLOT.opnd[3].X_add_number, | |
5642 | CURR_SLOT.opnd[4].X_add_number, | |
5643 | CURR_SLOT.opnd[5].X_add_number); | |
5644 | ||
542d6675 | 5645 | /* now we can parse the first arg: */ |
800eeca4 JW |
5646 | saved_input_pointer = input_line_pointer; |
5647 | input_line_pointer = first_arg; | |
5648 | sep = parse_operand (CURR_SLOT.opnd + 0); | |
5649 | if (sep != '=') | |
5650 | --num_outputs; /* force error */ | |
5651 | input_line_pointer = saved_input_pointer; | |
5652 | ||
5653 | CURR_SLOT.opnd[2].X_add_number = sof; | |
5654 | CURR_SLOT.opnd[3].X_add_number | |
5655 | = sof - CURR_SLOT.opnd[4].X_add_number; | |
5656 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; | |
5657 | } | |
5658 | } | |
5659 | ||
5660 | highest_unmatched_operand = 0; | |
87f8eb97 JW |
5661 | curr_out_of_range_pos = -1; |
5662 | error_pos = 0; | |
800eeca4 JW |
5663 | expected_operand = idesc->operands[0]; |
5664 | for (; idesc; idesc = get_next_opcode (idesc)) | |
5665 | { | |
5666 | if (num_outputs != idesc->num_outputs) | |
5667 | continue; /* mismatch in # of outputs */ | |
5668 | ||
5669 | CURR_SLOT.num_fixups = 0; | |
87f8eb97 JW |
5670 | |
5671 | /* Try to match all operands. If we see an out-of-range operand, | |
5672 | then continue trying to match the rest of the operands, since if | |
5673 | the rest match, then this idesc will give the best error message. */ | |
5674 | ||
5675 | out_of_range_pos = -1; | |
800eeca4 | 5676 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) |
87f8eb97 JW |
5677 | { |
5678 | result = operand_match (idesc, i, CURR_SLOT.opnd + i); | |
5679 | if (result != OPERAND_MATCH) | |
5680 | { | |
5681 | if (result != OPERAND_OUT_OF_RANGE) | |
5682 | break; | |
5683 | if (out_of_range_pos < 0) | |
5684 | /* remember position of the first out-of-range operand: */ | |
5685 | out_of_range_pos = i; | |
5686 | } | |
5687 | } | |
800eeca4 | 5688 | |
87f8eb97 JW |
5689 | /* If we did not match all operands, or if at least one operand was |
5690 | out-of-range, then this idesc does not match. Keep track of which | |
5691 | idesc matched the most operands before failing. If we have two | |
5692 | idescs that failed at the same position, and one had an out-of-range | |
5693 | operand, then prefer the out-of-range operand. Thus if we have | |
5694 | "add r0=0x1000000,r1" we get an error saying the constant is out | |
5695 | of range instead of an error saying that the constant should have been | |
5696 | a register. */ | |
5697 | ||
5698 | if (i != num_operands || out_of_range_pos >= 0) | |
800eeca4 | 5699 | { |
87f8eb97 JW |
5700 | if (i > highest_unmatched_operand |
5701 | || (i == highest_unmatched_operand | |
5702 | && out_of_range_pos > curr_out_of_range_pos)) | |
800eeca4 JW |
5703 | { |
5704 | highest_unmatched_operand = i; | |
87f8eb97 JW |
5705 | if (out_of_range_pos >= 0) |
5706 | { | |
5707 | expected_operand = idesc->operands[out_of_range_pos]; | |
5708 | error_pos = out_of_range_pos; | |
5709 | } | |
5710 | else | |
5711 | { | |
5712 | expected_operand = idesc->operands[i]; | |
5713 | error_pos = i; | |
5714 | } | |
5715 | curr_out_of_range_pos = out_of_range_pos; | |
800eeca4 JW |
5716 | } |
5717 | continue; | |
5718 | } | |
5719 | ||
5720 | if (num_operands < NELEMS (idesc->operands) | |
5721 | && idesc->operands[num_operands]) | |
5722 | continue; /* mismatch in number of arguments */ | |
5723 | ||
5724 | break; | |
5725 | } | |
5726 | if (!idesc) | |
5727 | { | |
5728 | if (expected_operand) | |
5729 | as_bad ("Operand %u of `%s' should be %s", | |
87f8eb97 | 5730 | error_pos + 1, mnemonic, |
800eeca4 JW |
5731 | elf64_ia64_operands[expected_operand].desc); |
5732 | else | |
5733 | as_bad ("Operand mismatch"); | |
5734 | return 0; | |
5735 | } | |
5736 | return idesc; | |
5737 | } | |
5738 | ||
88be23ec BS |
5739 | /* Keep track of state necessary to determine whether a NOP is necessary |
5740 | to avoid an erratum in A and B step Itanium chips, and return 1 if we | |
5741 | detect a case where additional NOPs may be necessary. */ | |
5742 | static int | |
5743 | errata_nop_necessary_p (slot, insn_unit) | |
5744 | struct slot *slot; | |
5745 | enum ia64_unit insn_unit; | |
5746 | { | |
5747 | int i; | |
5748 | struct group *this_group = md.last_groups + md.group_idx; | |
5749 | struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; | |
5750 | struct ia64_opcode *idesc = slot->idesc; | |
5751 | ||
5752 | /* Test whether this could be the first insn in a problematic sequence. */ | |
5753 | if (insn_unit == IA64_UNIT_F) | |
5754 | { | |
5755 | for (i = 0; i < idesc->num_outputs; i++) | |
5756 | if (idesc->operands[i] == IA64_OPND_P1 | |
5757 | || idesc->operands[i] == IA64_OPND_P2) | |
5758 | { | |
5759 | int regno = slot->opnd[i].X_add_number - REG_P; | |
3557da92 | 5760 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5761 | if (regno >= 64) |
3557da92 | 5762 | return 0; |
88be23ec BS |
5763 | this_group->p_reg_set[regno] = 1; |
5764 | } | |
5765 | } | |
5766 | ||
5767 | /* Test whether this could be the second insn in a problematic sequence. */ | |
5768 | if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 | |
5769 | && prev_group->p_reg_set[slot->qp_regno]) | |
5770 | { | |
5771 | for (i = 0; i < idesc->num_outputs; i++) | |
5772 | if (idesc->operands[i] == IA64_OPND_R1 | |
5773 | || idesc->operands[i] == IA64_OPND_R2 | |
5774 | || idesc->operands[i] == IA64_OPND_R3) | |
5775 | { | |
5776 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5777 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5778 | if (regno >= 128) |
3557da92 | 5779 | return 0; |
88be23ec BS |
5780 | if (strncmp (idesc->name, "add", 3) != 0 |
5781 | && strncmp (idesc->name, "sub", 3) != 0 | |
5782 | && strncmp (idesc->name, "shladd", 6) != 0 | |
5783 | && (idesc->flags & IA64_OPCODE_POSTINC) == 0) | |
5784 | this_group->g_reg_set_conditionally[regno] = 1; | |
5785 | } | |
5786 | } | |
5787 | ||
5788 | /* Test whether this could be the third insn in a problematic sequence. */ | |
5789 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) | |
5790 | { | |
5791 | if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ | |
5792 | idesc->operands[i] == IA64_OPND_R3 | |
5793 | /* For mov indirect. */ | |
5794 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
5795 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
5796 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
5797 | || idesc->operands[i] == IA64_OPND_PKR_R3 | |
5798 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
5799 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
5800 | || idesc->operands[i] == IA64_OPND_MSR_R3 | |
5801 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
5802 | /* For itr. */ | |
5803 | || idesc->operands[i] == IA64_OPND_ITR_R3 | |
5804 | || idesc->operands[i] == IA64_OPND_DTR_R3 | |
5805 | /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ | |
5806 | || idesc->operands[i] == IA64_OPND_MR3) | |
5807 | { | |
5808 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5809 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5810 | if (regno >= 128) |
3557da92 | 5811 | return 0; |
88be23ec BS |
5812 | if (idesc->operands[i] == IA64_OPND_R3) |
5813 | { | |
5814 | if (strcmp (idesc->name, "fc") != 0 | |
5815 | && strcmp (idesc->name, "tak") != 0 | |
5816 | && strcmp (idesc->name, "thash") != 0 | |
5817 | && strcmp (idesc->name, "tpa") != 0 | |
5818 | && strcmp (idesc->name, "ttag") != 0 | |
5819 | && strncmp (idesc->name, "ptr", 3) != 0 | |
5820 | && strncmp (idesc->name, "ptc", 3) != 0 | |
5821 | && strncmp (idesc->name, "probe", 5) != 0) | |
40449e9f | 5822 | return 0; |
88be23ec | 5823 | } |
bc805888 | 5824 | if (prev_group->g_reg_set_conditionally[regno]) |
88be23ec BS |
5825 | return 1; |
5826 | } | |
5827 | } | |
5828 | return 0; | |
5829 | } | |
5830 | ||
800eeca4 JW |
5831 | static void |
5832 | build_insn (slot, insnp) | |
5833 | struct slot *slot; | |
5834 | bfd_vma *insnp; | |
5835 | { | |
5836 | const struct ia64_operand *odesc, *o2desc; | |
5837 | struct ia64_opcode *idesc = slot->idesc; | |
5838 | bfd_signed_vma insn, val; | |
5839 | const char *err; | |
5840 | int i; | |
5841 | ||
5842 | insn = idesc->opcode | slot->qp_regno; | |
5843 | ||
5844 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) | |
5845 | { | |
c67e42c9 RH |
5846 | if (slot->opnd[i].X_op == O_register |
5847 | || slot->opnd[i].X_op == O_constant | |
5848 | || slot->opnd[i].X_op == O_index) | |
5849 | val = slot->opnd[i].X_add_number; | |
5850 | else if (slot->opnd[i].X_op == O_big) | |
800eeca4 | 5851 | { |
c67e42c9 RH |
5852 | /* This must be the value 0x10000000000000000. */ |
5853 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); | |
5854 | val = 0; | |
5855 | } | |
5856 | else | |
5857 | val = 0; | |
5858 | ||
5859 | switch (idesc->operands[i]) | |
5860 | { | |
5861 | case IA64_OPND_IMMU64: | |
800eeca4 JW |
5862 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
5863 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) | |
5864 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) | |
5865 | | (((val >> 63) & 0x1) << 36)); | |
c67e42c9 RH |
5866 | continue; |
5867 | ||
5868 | case IA64_OPND_IMMU62: | |
542d6675 KH |
5869 | val &= 0x3fffffffffffffffULL; |
5870 | if (val != slot->opnd[i].X_add_number) | |
5871 | as_warn (_("Value truncated to 62 bits")); | |
5872 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; | |
5873 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); | |
c67e42c9 | 5874 | continue; |
800eeca4 | 5875 | |
c67e42c9 RH |
5876 | case IA64_OPND_TGT64: |
5877 | val >>= 4; | |
5878 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; | |
5879 | insn |= ((((val >> 59) & 0x1) << 36) | |
5880 | | (((val >> 0) & 0xfffff) << 13)); | |
5881 | continue; | |
800eeca4 | 5882 | |
c67e42c9 RH |
5883 | case IA64_OPND_AR3: |
5884 | val -= REG_AR; | |
5885 | break; | |
5886 | ||
5887 | case IA64_OPND_B1: | |
5888 | case IA64_OPND_B2: | |
5889 | val -= REG_BR; | |
5890 | break; | |
5891 | ||
5892 | case IA64_OPND_CR3: | |
5893 | val -= REG_CR; | |
5894 | break; | |
5895 | ||
5896 | case IA64_OPND_F1: | |
5897 | case IA64_OPND_F2: | |
5898 | case IA64_OPND_F3: | |
5899 | case IA64_OPND_F4: | |
5900 | val -= REG_FR; | |
5901 | break; | |
5902 | ||
5903 | case IA64_OPND_P1: | |
5904 | case IA64_OPND_P2: | |
5905 | val -= REG_P; | |
5906 | break; | |
5907 | ||
5908 | case IA64_OPND_R1: | |
5909 | case IA64_OPND_R2: | |
5910 | case IA64_OPND_R3: | |
5911 | case IA64_OPND_R3_2: | |
5912 | case IA64_OPND_CPUID_R3: | |
5913 | case IA64_OPND_DBR_R3: | |
5914 | case IA64_OPND_DTR_R3: | |
5915 | case IA64_OPND_ITR_R3: | |
5916 | case IA64_OPND_IBR_R3: | |
5917 | case IA64_OPND_MR3: | |
5918 | case IA64_OPND_MSR_R3: | |
5919 | case IA64_OPND_PKR_R3: | |
5920 | case IA64_OPND_PMC_R3: | |
5921 | case IA64_OPND_PMD_R3: | |
197865e8 | 5922 | case IA64_OPND_RR_R3: |
c67e42c9 RH |
5923 | val -= REG_GR; |
5924 | break; | |
5925 | ||
5926 | default: | |
5927 | break; | |
5928 | } | |
5929 | ||
5930 | odesc = elf64_ia64_operands + idesc->operands[i]; | |
5931 | err = (*odesc->insert) (odesc, val, &insn); | |
5932 | if (err) | |
5933 | as_bad_where (slot->src_file, slot->src_line, | |
5934 | "Bad operand value: %s", err); | |
5935 | if (idesc->flags & IA64_OPCODE_PSEUDO) | |
5936 | { | |
5937 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) | |
5938 | && odesc == elf64_ia64_operands + IA64_OPND_F3) | |
5939 | { | |
5940 | o2desc = elf64_ia64_operands + IA64_OPND_F2; | |
5941 | (*o2desc->insert) (o2desc, val, &insn); | |
800eeca4 | 5942 | } |
c67e42c9 RH |
5943 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
5944 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a | |
5945 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) | |
800eeca4 | 5946 | { |
c67e42c9 RH |
5947 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
5948 | (*o2desc->insert) (o2desc, 64 - val, &insn); | |
800eeca4 JW |
5949 | } |
5950 | } | |
5951 | } | |
5952 | *insnp = insn; | |
5953 | } | |
5954 | ||
5955 | static void | |
5956 | emit_one_bundle () | |
5957 | { | |
5958 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; | |
5959 | unsigned int manual_bundling = 0; | |
5960 | enum ia64_unit required_unit, insn_unit = 0; | |
5961 | enum ia64_insn_type type[3], insn_type; | |
5962 | unsigned int template, orig_template; | |
542d6675 | 5963 | bfd_vma insn[3] = { -1, -1, -1 }; |
800eeca4 JW |
5964 | struct ia64_opcode *idesc; |
5965 | int end_of_insn_group = 0, user_template = -1; | |
5966 | int n, i, j, first, curr; | |
2434f565 | 5967 | unw_rec_list *ptr; |
800eeca4 JW |
5968 | bfd_vma t0 = 0, t1 = 0; |
5969 | struct label_fix *lfix; | |
5970 | struct insn_fix *ifix; | |
5971 | char mnemonic[16]; | |
5972 | fixS *fix; | |
5973 | char *f; | |
5974 | ||
5975 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; | |
5976 | know (first >= 0 & first < NUM_SLOTS); | |
5977 | n = MIN (3, md.num_slots_in_use); | |
5978 | ||
5979 | /* Determine template: user user_template if specified, best match | |
542d6675 | 5980 | otherwise: */ |
800eeca4 JW |
5981 | |
5982 | if (md.slot[first].user_template >= 0) | |
5983 | user_template = template = md.slot[first].user_template; | |
5984 | else | |
5985 | { | |
032efc85 | 5986 | /* Auto select appropriate template. */ |
800eeca4 JW |
5987 | memset (type, 0, sizeof (type)); |
5988 | curr = first; | |
5989 | for (i = 0; i < n; ++i) | |
5990 | { | |
032efc85 RH |
5991 | if (md.slot[curr].label_fixups && i != 0) |
5992 | break; | |
800eeca4 JW |
5993 | type[i] = md.slot[curr].idesc->type; |
5994 | curr = (curr + 1) % NUM_SLOTS; | |
5995 | } | |
5996 | template = best_template[type[0]][type[1]][type[2]]; | |
5997 | } | |
5998 | ||
542d6675 | 5999 | /* initialize instructions with appropriate nops: */ |
800eeca4 JW |
6000 | for (i = 0; i < 3; ++i) |
6001 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; | |
6002 | ||
6003 | f = frag_more (16); | |
6004 | ||
542d6675 | 6005 | /* now fill in slots with as many insns as possible: */ |
800eeca4 JW |
6006 | curr = first; |
6007 | idesc = md.slot[curr].idesc; | |
6008 | end_of_insn_group = 0; | |
6009 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) | |
6010 | { | |
e0c9811a JW |
6011 | /* Set the slot number for prologue/body records now as those |
6012 | refer to the current point, not the point after the | |
542d6675 | 6013 | instruction has been issued: */ |
10850f29 JW |
6014 | /* Don't try to delete prologue/body records here, as that will cause |
6015 | them to also be deleted from the master list of unwind records. */ | |
e0c9811a | 6016 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
10850f29 JW |
6017 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
6018 | || ptr->r.type == body) | |
f5a30c2e JW |
6019 | { |
6020 | ptr->slot_number = (unsigned long) f + i; | |
6021 | ptr->slot_frag = frag_now; | |
6022 | } | |
e0c9811a | 6023 | |
800eeca4 JW |
6024 | if (idesc->flags & IA64_OPCODE_SLOT2) |
6025 | { | |
6026 | if (manual_bundling && i != 2) | |
6027 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6028 | "`%s' must be last in bundle", idesc->name); | |
6029 | else | |
6030 | i = 2; | |
6031 | } | |
6032 | if (idesc->flags & IA64_OPCODE_LAST) | |
6033 | { | |
2434f565 JW |
6034 | int required_slot; |
6035 | unsigned int required_template; | |
800eeca4 JW |
6036 | |
6037 | /* If we need a stop bit after an M slot, our only choice is | |
6038 | template 5 (M;;MI). If we need a stop bit after a B | |
6039 | slot, our only choice is to place it at the end of the | |
6040 | bundle, because the only available templates are MIB, | |
6041 | MBB, BBB, MMB, and MFB. We don't handle anything other | |
6042 | than M and B slots because these are the only kind of | |
6043 | instructions that can have the IA64_OPCODE_LAST bit set. */ | |
6044 | required_template = template; | |
6045 | switch (idesc->type) | |
6046 | { | |
6047 | case IA64_TYPE_M: | |
6048 | required_slot = 0; | |
6049 | required_template = 5; | |
6050 | break; | |
6051 | ||
6052 | case IA64_TYPE_B: | |
6053 | required_slot = 2; | |
6054 | break; | |
6055 | ||
6056 | default: | |
6057 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6058 | "Internal error: don't know how to force %s to end" | |
6059 | "of instruction group", idesc->name); | |
6060 | required_slot = i; | |
6061 | break; | |
6062 | } | |
6063 | if (manual_bundling && i != required_slot) | |
6064 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6065 | "`%s' must be last in instruction group", | |
6066 | idesc->name); | |
6067 | if (required_slot < i) | |
6068 | /* Can't fit this instruction. */ | |
6069 | break; | |
6070 | ||
6071 | i = required_slot; | |
6072 | if (required_template != template) | |
6073 | { | |
6074 | /* If we switch the template, we need to reset the NOPs | |
6075 | after slot i. The slot-types of the instructions ahead | |
6076 | of i never change, so we don't need to worry about | |
6077 | changing NOPs in front of this slot. */ | |
6078 | for (j = i; j < 3; ++j) | |
6079 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; | |
6080 | } | |
6081 | template = required_template; | |
6082 | } | |
6083 | if (curr != first && md.slot[curr].label_fixups) | |
6084 | { | |
6085 | if (manual_bundling_on) | |
6086 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6087 | "Label must be first in a bundle"); | |
6088 | /* This insn must go into the first slot of a bundle. */ | |
6089 | break; | |
6090 | } | |
6091 | ||
6092 | manual_bundling_on = md.slot[curr].manual_bundling_on; | |
6093 | manual_bundling_off = md.slot[curr].manual_bundling_off; | |
6094 | ||
6095 | if (manual_bundling_on) | |
6096 | { | |
6097 | if (curr == first) | |
6098 | manual_bundling = 1; | |
6099 | else | |
6100 | break; /* need to start a new bundle */ | |
6101 | } | |
6102 | ||
6103 | if (end_of_insn_group && md.num_slots_in_use >= 1) | |
6104 | { | |
6105 | /* We need an instruction group boundary in the middle of a | |
6106 | bundle. See if we can switch to an other template with | |
6107 | an appropriate boundary. */ | |
6108 | ||
6109 | orig_template = template; | |
6110 | if (i == 1 && (user_template == 4 | |
6111 | || (user_template < 0 | |
6112 | && (ia64_templ_desc[template].exec_unit[0] | |
6113 | == IA64_UNIT_M)))) | |
6114 | { | |
6115 | template = 5; | |
6116 | end_of_insn_group = 0; | |
6117 | } | |
6118 | else if (i == 2 && (user_template == 0 | |
6119 | || (user_template < 0 | |
6120 | && (ia64_templ_desc[template].exec_unit[1] | |
6121 | == IA64_UNIT_I))) | |
6122 | /* This test makes sure we don't switch the template if | |
6123 | the next instruction is one that needs to be first in | |
6124 | an instruction group. Since all those instructions are | |
6125 | in the M group, there is no way such an instruction can | |
6126 | fit in this bundle even if we switch the template. The | |
6127 | reason we have to check for this is that otherwise we | |
6128 | may end up generating "MI;;I M.." which has the deadly | |
6129 | effect that the second M instruction is no longer the | |
6130 | first in the bundle! --davidm 99/12/16 */ | |
6131 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) | |
6132 | { | |
6133 | template = 1; | |
6134 | end_of_insn_group = 0; | |
6135 | } | |
6136 | else if (curr != first) | |
6137 | /* can't fit this insn */ | |
6138 | break; | |
6139 | ||
6140 | if (template != orig_template) | |
6141 | /* if we switch the template, we need to reset the NOPs | |
6142 | after slot i. The slot-types of the instructions ahead | |
6143 | of i never change, so we don't need to worry about | |
6144 | changing NOPs in front of this slot. */ | |
6145 | for (j = i; j < 3; ++j) | |
6146 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; | |
6147 | } | |
6148 | required_unit = ia64_templ_desc[template].exec_unit[i]; | |
6149 | ||
542d6675 | 6150 | /* resolve dynamic opcodes such as "break" and "nop": */ |
800eeca4 JW |
6151 | if (idesc->type == IA64_TYPE_DYN) |
6152 | { | |
6153 | if ((strcmp (idesc->name, "nop") == 0) | |
6154 | || (strcmp (idesc->name, "break") == 0)) | |
6155 | insn_unit = required_unit; | |
6156 | else if (strcmp (idesc->name, "chk.s") == 0) | |
6157 | { | |
6158 | insn_unit = IA64_UNIT_M; | |
6159 | if (required_unit == IA64_UNIT_I) | |
6160 | insn_unit = IA64_UNIT_I; | |
6161 | } | |
6162 | else | |
6163 | as_fatal ("emit_one_bundle: unexpected dynamic op"); | |
6164 | ||
6165 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); | |
3d56ab85 | 6166 | ia64_free_opcode (idesc); |
800eeca4 JW |
6167 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
6168 | #if 0 | |
6169 | know (!idesc->next); /* no resolved dynamic ops have collisions */ | |
6170 | #endif | |
6171 | } | |
6172 | else | |
6173 | { | |
6174 | insn_type = idesc->type; | |
6175 | insn_unit = IA64_UNIT_NIL; | |
6176 | switch (insn_type) | |
6177 | { | |
6178 | case IA64_TYPE_A: | |
6179 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) | |
6180 | insn_unit = required_unit; | |
6181 | break; | |
542d6675 | 6182 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
800eeca4 JW |
6183 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
6184 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; | |
6185 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; | |
6186 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; | |
6187 | default: break; | |
6188 | } | |
6189 | } | |
6190 | ||
6191 | if (insn_unit != required_unit) | |
6192 | { | |
6193 | if (required_unit == IA64_UNIT_L | |
542d6675 | 6194 | && insn_unit == IA64_UNIT_I |
800eeca4 JW |
6195 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
6196 | { | |
6197 | /* we got ourselves an MLX template but the current | |
197865e8 | 6198 | instruction isn't an X-unit, or an I-unit instruction |
800eeca4 JW |
6199 | that can go into the X slot of an MLX template. Duh. */ |
6200 | if (md.num_slots_in_use >= NUM_SLOTS) | |
6201 | { | |
6202 | as_bad_where (md.slot[curr].src_file, | |
6203 | md.slot[curr].src_line, | |
6204 | "`%s' can't go in X slot of " | |
6205 | "MLX template", idesc->name); | |
542d6675 | 6206 | /* drop this insn so we don't livelock: */ |
800eeca4 JW |
6207 | --md.num_slots_in_use; |
6208 | } | |
6209 | break; | |
6210 | } | |
6211 | continue; /* try next slot */ | |
6212 | } | |
6213 | ||
40449e9f KH |
6214 | { |
6215 | bfd_vma addr; | |
800eeca4 | 6216 | |
40449e9f KH |
6217 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
6218 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); | |
6219 | } | |
800eeca4 | 6220 | |
88be23ec BS |
6221 | if (errata_nop_necessary_p (md.slot + curr, insn_unit)) |
6222 | as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); | |
6223 | ||
800eeca4 JW |
6224 | build_insn (md.slot + curr, insn + i); |
6225 | ||
10850f29 JW |
6226 | /* Set slot counts for non prologue/body unwind records. */ |
6227 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) | |
6228 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr | |
6229 | && ptr->r.type != body) | |
f5a30c2e JW |
6230 | { |
6231 | ptr->slot_number = (unsigned long) f + i; | |
6232 | ptr->slot_frag = frag_now; | |
6233 | } | |
10850f29 | 6234 | md.slot[curr].unwind_record = NULL; |
10850f29 | 6235 | |
800eeca4 JW |
6236 | if (required_unit == IA64_UNIT_L) |
6237 | { | |
6238 | know (i == 1); | |
6239 | /* skip one slot for long/X-unit instructions */ | |
6240 | ++i; | |
6241 | } | |
6242 | --md.num_slots_in_use; | |
6243 | ||
542d6675 | 6244 | /* now is a good time to fix up the labels for this insn: */ |
800eeca4 JW |
6245 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
6246 | { | |
6247 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); | |
6248 | symbol_set_frag (lfix->sym, frag_now); | |
6249 | } | |
f1bcba5b JW |
6250 | /* and fix up the tags also. */ |
6251 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) | |
6252 | { | |
6253 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); | |
6254 | symbol_set_frag (lfix->sym, frag_now); | |
6255 | } | |
800eeca4 JW |
6256 | |
6257 | for (j = 0; j < md.slot[curr].num_fixups; ++j) | |
6258 | { | |
6259 | ifix = md.slot[curr].fixup + j; | |
5a080f89 | 6260 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, |
800eeca4 JW |
6261 | &ifix->expr, ifix->is_pcrel, ifix->code); |
6262 | fix->tc_fix_data.opnd = ifix->opnd; | |
6263 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); | |
6264 | fix->fx_file = md.slot[curr].src_file; | |
6265 | fix->fx_line = md.slot[curr].src_line; | |
6266 | } | |
6267 | ||
6268 | end_of_insn_group = md.slot[curr].end_of_insn_group; | |
6269 | ||
88be23ec BS |
6270 | if (end_of_insn_group) |
6271 | { | |
6272 | md.group_idx = (md.group_idx + 1) % 3; | |
6273 | memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); | |
6274 | } | |
6275 | ||
542d6675 | 6276 | /* clear slot: */ |
800eeca4 JW |
6277 | ia64_free_opcode (md.slot[curr].idesc); |
6278 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); | |
6279 | md.slot[curr].user_template = -1; | |
6280 | ||
6281 | if (manual_bundling_off) | |
6282 | { | |
6283 | manual_bundling = 0; | |
6284 | break; | |
6285 | } | |
6286 | curr = (curr + 1) % NUM_SLOTS; | |
6287 | idesc = md.slot[curr].idesc; | |
6288 | } | |
6289 | if (manual_bundling) | |
6290 | { | |
6291 | if (md.num_slots_in_use > 0) | |
6292 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6293 | "`%s' does not fit into %s template", | |
6294 | idesc->name, ia64_templ_desc[template].name); | |
6295 | else | |
6296 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6297 | "Missing '}' at end of file"); | |
6298 | } | |
6299 | know (md.num_slots_in_use < NUM_SLOTS); | |
6300 | ||
6301 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); | |
6302 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
6303 | ||
44f5c83a JW |
6304 | number_to_chars_littleendian (f + 0, t0, 8); |
6305 | number_to_chars_littleendian (f + 8, t1, 8); | |
f5a30c2e JW |
6306 | |
6307 | unwind.next_slot_number = (unsigned long) f + 16; | |
6308 | unwind.next_slot_frag = frag_now; | |
800eeca4 JW |
6309 | } |
6310 | ||
6311 | int | |
6312 | md_parse_option (c, arg) | |
6313 | int c; | |
6314 | char *arg; | |
6315 | { | |
7463c317 | 6316 | |
800eeca4 JW |
6317 | switch (c) |
6318 | { | |
c43c2cc5 | 6319 | /* Switches from the Intel assembler. */ |
44f5c83a | 6320 | case 'm': |
800eeca4 JW |
6321 | if (strcmp (arg, "ilp64") == 0 |
6322 | || strcmp (arg, "lp64") == 0 | |
6323 | || strcmp (arg, "p64") == 0) | |
6324 | { | |
6325 | md.flags |= EF_IA_64_ABI64; | |
6326 | } | |
6327 | else if (strcmp (arg, "ilp32") == 0) | |
6328 | { | |
6329 | md.flags &= ~EF_IA_64_ABI64; | |
6330 | } | |
6331 | else if (strcmp (arg, "le") == 0) | |
6332 | { | |
6333 | md.flags &= ~EF_IA_64_BE; | |
6334 | } | |
6335 | else if (strcmp (arg, "be") == 0) | |
6336 | { | |
6337 | md.flags |= EF_IA_64_BE; | |
6338 | } | |
6339 | else | |
6340 | return 0; | |
6341 | break; | |
6342 | ||
6343 | case 'N': | |
6344 | if (strcmp (arg, "so") == 0) | |
6345 | { | |
542d6675 | 6346 | /* Suppress signon message. */ |
800eeca4 JW |
6347 | } |
6348 | else if (strcmp (arg, "pi") == 0) | |
6349 | { | |
6350 | /* Reject privileged instructions. FIXME */ | |
6351 | } | |
6352 | else if (strcmp (arg, "us") == 0) | |
6353 | { | |
6354 | /* Allow union of signed and unsigned range. FIXME */ | |
6355 | } | |
6356 | else if (strcmp (arg, "close_fcalls") == 0) | |
6357 | { | |
6358 | /* Do not resolve global function calls. */ | |
6359 | } | |
6360 | else | |
6361 | return 0; | |
6362 | break; | |
6363 | ||
6364 | case 'C': | |
6365 | /* temp[="prefix"] Insert temporary labels into the object file | |
6366 | symbol table prefixed by "prefix". | |
6367 | Default prefix is ":temp:". | |
6368 | */ | |
6369 | break; | |
6370 | ||
6371 | case 'a': | |
800eeca4 JW |
6372 | /* indirect=<tgt> Assume unannotated indirect branches behavior |
6373 | according to <tgt> -- | |
6374 | exit: branch out from the current context (default) | |
6375 | labels: all labels in context may be branch targets | |
6376 | */ | |
85b40035 L |
6377 | if (strncmp (arg, "indirect=", 9) != 0) |
6378 | return 0; | |
800eeca4 JW |
6379 | break; |
6380 | ||
6381 | case 'x': | |
6382 | /* -X conflicts with an ignored option, use -x instead */ | |
6383 | md.detect_dv = 1; | |
6384 | if (!arg || strcmp (arg, "explicit") == 0) | |
542d6675 KH |
6385 | { |
6386 | /* set default mode to explicit */ | |
6387 | md.default_explicit_mode = 1; | |
6388 | break; | |
6389 | } | |
800eeca4 | 6390 | else if (strcmp (arg, "auto") == 0) |
542d6675 KH |
6391 | { |
6392 | md.default_explicit_mode = 0; | |
6393 | } | |
800eeca4 | 6394 | else if (strcmp (arg, "debug") == 0) |
542d6675 KH |
6395 | { |
6396 | md.debug_dv = 1; | |
6397 | } | |
800eeca4 | 6398 | else if (strcmp (arg, "debugx") == 0) |
542d6675 KH |
6399 | { |
6400 | md.default_explicit_mode = 1; | |
6401 | md.debug_dv = 1; | |
6402 | } | |
800eeca4 | 6403 | else |
542d6675 KH |
6404 | { |
6405 | as_bad (_("Unrecognized option '-x%s'"), arg); | |
6406 | } | |
800eeca4 JW |
6407 | break; |
6408 | ||
6409 | case 'S': | |
6410 | /* nops Print nops statistics. */ | |
6411 | break; | |
6412 | ||
c43c2cc5 JW |
6413 | /* GNU specific switches for gcc. */ |
6414 | case OPTION_MCONSTANT_GP: | |
6415 | md.flags |= EF_IA_64_CONS_GP; | |
6416 | break; | |
6417 | ||
6418 | case OPTION_MAUTO_PIC: | |
6419 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; | |
6420 | break; | |
6421 | ||
800eeca4 JW |
6422 | default: |
6423 | return 0; | |
6424 | } | |
6425 | ||
6426 | return 1; | |
6427 | } | |
6428 | ||
6429 | void | |
6430 | md_show_usage (stream) | |
6431 | FILE *stream; | |
6432 | { | |
542d6675 | 6433 | fputs (_("\ |
800eeca4 | 6434 | IA-64 options:\n\ |
6290819d NC |
6435 | --mconstant-gp mark output file as using the constant-GP model\n\ |
6436 | (sets ELF header flag EF_IA_64_CONS_GP)\n\ | |
6437 | --mauto-pic mark output file as using the constant-GP model\n\ | |
6438 | without function descriptors (sets ELF header flag\n\ | |
6439 | EF_IA_64_NOFUNCDESC_CONS_GP)\n\ | |
44f5c83a JW |
6440 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
6441 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ | |
800eeca4 JW |
6442 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
6443 | -xauto automagically remove dependency violations\n\ | |
6444 | -xdebug debug dependency violation checker\n"), | |
6445 | stream); | |
6446 | } | |
6447 | ||
acebd4ce AS |
6448 | void |
6449 | ia64_after_parse_args () | |
6450 | { | |
6451 | if (debug_type == DEBUG_STABS) | |
6452 | as_fatal (_("--gstabs is not supported for ia64")); | |
6453 | } | |
6454 | ||
44576e1f RH |
6455 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
6456 | ||
6457 | static int | |
800eeca4 JW |
6458 | match (int templ, int type, int slot) |
6459 | { | |
6460 | enum ia64_unit unit; | |
6461 | int result; | |
6462 | ||
6463 | unit = ia64_templ_desc[templ].exec_unit[slot]; | |
6464 | switch (type) | |
6465 | { | |
6466 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ | |
6467 | case IA64_TYPE_A: | |
6468 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); | |
6469 | break; | |
6470 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; | |
6471 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; | |
6472 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; | |
6473 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; | |
6474 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; | |
6475 | default: result = 0; break; | |
6476 | } | |
6477 | return result; | |
6478 | } | |
6479 | ||
44576e1f RH |
6480 | /* Add a bit of extra goodness if a nop of type F or B would fit |
6481 | in TEMPL at SLOT. */ | |
6482 | ||
6483 | static inline int | |
6484 | extra_goodness (int templ, int slot) | |
6485 | { | |
ebeeafe6 | 6486 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
44576e1f | 6487 | return 2; |
ebeeafe6 | 6488 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
44576e1f RH |
6489 | return 1; |
6490 | return 0; | |
6491 | } | |
6492 | ||
800eeca4 JW |
6493 | /* This function is called once, at assembler startup time. It sets |
6494 | up all the tables, etc. that the MD part of the assembler will need | |
6495 | that can be determined before arguments are parsed. */ | |
6496 | void | |
6497 | md_begin () | |
6498 | { | |
44f5c83a | 6499 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
800eeca4 JW |
6500 | const char *err; |
6501 | char name[8]; | |
6502 | ||
6503 | md.auto_align = 1; | |
6504 | md.explicit_mode = md.default_explicit_mode; | |
6505 | ||
6506 | bfd_set_section_alignment (stdoutput, text_section, 4); | |
6507 | ||
44f5c83a | 6508 | target_big_endian = TARGET_BYTES_BIG_ENDIAN; |
13ae64f3 JJ |
6509 | pseudo_func[FUNC_DTP_MODULE].u.sym = |
6510 | symbol_new (".<dtpmod>", undefined_section, FUNC_DTP_MODULE, | |
6511 | &zero_address_frag); | |
6512 | ||
6513 | pseudo_func[FUNC_DTP_RELATIVE].u.sym = | |
6514 | symbol_new (".<dtprel>", undefined_section, FUNC_DTP_RELATIVE, | |
6515 | &zero_address_frag); | |
6516 | ||
800eeca4 | 6517 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
542d6675 KH |
6518 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
6519 | &zero_address_frag); | |
800eeca4 JW |
6520 | |
6521 | pseudo_func[FUNC_GP_RELATIVE].u.sym = | |
542d6675 KH |
6522 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
6523 | &zero_address_frag); | |
800eeca4 JW |
6524 | |
6525 | pseudo_func[FUNC_LT_RELATIVE].u.sym = | |
542d6675 KH |
6526 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
6527 | &zero_address_frag); | |
800eeca4 | 6528 | |
c67e42c9 | 6529 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
542d6675 KH |
6530 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
6531 | &zero_address_frag); | |
c67e42c9 | 6532 | |
800eeca4 | 6533 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
542d6675 KH |
6534 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
6535 | &zero_address_frag); | |
800eeca4 JW |
6536 | |
6537 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = | |
542d6675 KH |
6538 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
6539 | &zero_address_frag); | |
800eeca4 JW |
6540 | |
6541 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = | |
542d6675 KH |
6542 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
6543 | &zero_address_frag); | |
800eeca4 | 6544 | |
13ae64f3 JJ |
6545 | pseudo_func[FUNC_TP_RELATIVE].u.sym = |
6546 | symbol_new (".<tprel>", undefined_section, FUNC_TP_RELATIVE, | |
6547 | &zero_address_frag); | |
6548 | ||
800eeca4 | 6549 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = |
542d6675 KH |
6550 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
6551 | &zero_address_frag); | |
800eeca4 JW |
6552 | |
6553 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = | |
542d6675 KH |
6554 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
6555 | &zero_address_frag); | |
800eeca4 | 6556 | |
13ae64f3 JJ |
6557 | pseudo_func[FUNC_LT_DTP_MODULE].u.sym = |
6558 | symbol_new (".<ltoff.dtpmod>", undefined_section, FUNC_LT_DTP_MODULE, | |
6559 | &zero_address_frag); | |
6560 | ||
6561 | pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym = | |
6562 | symbol_new (".<ltoff.dptrel>", undefined_section, FUNC_LT_DTP_RELATIVE, | |
6563 | &zero_address_frag); | |
6564 | ||
6565 | pseudo_func[FUNC_LT_TP_RELATIVE].u.sym = | |
6566 | symbol_new (".<ltoff.tprel>", undefined_section, FUNC_LT_TP_RELATIVE, | |
6567 | &zero_address_frag); | |
6568 | ||
3969b680 RH |
6569 | pseudo_func[FUNC_IPLT_RELOC].u.sym = |
6570 | symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC, | |
6571 | &zero_address_frag); | |
6572 | ||
197865e8 | 6573 | /* Compute the table of best templates. We compute goodness as a |
44576e1f RH |
6574 | base 4 value, in which each match counts for 3, each F counts |
6575 | for 2, each B counts for 1. This should maximize the number of | |
6576 | F and B nops in the chosen bundles, which is good because these | |
6577 | pipelines are least likely to be overcommitted. */ | |
800eeca4 JW |
6578 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
6579 | for (j = 0; j < IA64_NUM_TYPES; ++j) | |
6580 | for (k = 0; k < IA64_NUM_TYPES; ++k) | |
6581 | { | |
6582 | best = 0; | |
6583 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) | |
6584 | { | |
6585 | goodness = 0; | |
6586 | if (match (t, i, 0)) | |
6587 | { | |
6588 | if (match (t, j, 1)) | |
6589 | { | |
6590 | if (match (t, k, 2)) | |
44576e1f | 6591 | goodness = 3 + 3 + 3; |
800eeca4 | 6592 | else |
44576e1f | 6593 | goodness = 3 + 3 + extra_goodness (t, 2); |
800eeca4 JW |
6594 | } |
6595 | else if (match (t, j, 2)) | |
44576e1f | 6596 | goodness = 3 + 3 + extra_goodness (t, 1); |
800eeca4 | 6597 | else |
44576e1f RH |
6598 | { |
6599 | goodness = 3; | |
6600 | goodness += extra_goodness (t, 1); | |
6601 | goodness += extra_goodness (t, 2); | |
6602 | } | |
800eeca4 JW |
6603 | } |
6604 | else if (match (t, i, 1)) | |
6605 | { | |
6606 | if (match (t, j, 2)) | |
44576e1f | 6607 | goodness = 3 + 3; |
800eeca4 | 6608 | else |
44576e1f | 6609 | goodness = 3 + extra_goodness (t, 2); |
800eeca4 JW |
6610 | } |
6611 | else if (match (t, i, 2)) | |
44576e1f | 6612 | goodness = 3 + extra_goodness (t, 1); |
800eeca4 JW |
6613 | |
6614 | if (goodness > best) | |
6615 | { | |
6616 | best = goodness; | |
6617 | best_template[i][j][k] = t; | |
6618 | } | |
6619 | } | |
6620 | } | |
6621 | ||
6622 | for (i = 0; i < NUM_SLOTS; ++i) | |
6623 | md.slot[i].user_template = -1; | |
6624 | ||
6625 | md.pseudo_hash = hash_new (); | |
6626 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) | |
6627 | { | |
6628 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, | |
6629 | (void *) (pseudo_opcode + i)); | |
6630 | if (err) | |
6631 | as_fatal ("ia64.md_begin: can't hash `%s': %s", | |
6632 | pseudo_opcode[i].name, err); | |
6633 | } | |
6634 | ||
6635 | md.reg_hash = hash_new (); | |
6636 | md.dynreg_hash = hash_new (); | |
6637 | md.const_hash = hash_new (); | |
6638 | md.entry_hash = hash_new (); | |
6639 | ||
542d6675 | 6640 | /* general registers: */ |
800eeca4 JW |
6641 | |
6642 | total = 128; | |
6643 | for (i = 0; i < total; ++i) | |
6644 | { | |
6645 | sprintf (name, "r%d", i - REG_GR); | |
6646 | md.regsym[i] = declare_register (name, i); | |
6647 | } | |
6648 | ||
542d6675 | 6649 | /* floating point registers: */ |
800eeca4 JW |
6650 | total += 128; |
6651 | for (; i < total; ++i) | |
6652 | { | |
6653 | sprintf (name, "f%d", i - REG_FR); | |
6654 | md.regsym[i] = declare_register (name, i); | |
6655 | } | |
6656 | ||
542d6675 | 6657 | /* application registers: */ |
800eeca4 JW |
6658 | total += 128; |
6659 | ar_base = i; | |
6660 | for (; i < total; ++i) | |
6661 | { | |
6662 | sprintf (name, "ar%d", i - REG_AR); | |
6663 | md.regsym[i] = declare_register (name, i); | |
6664 | } | |
6665 | ||
542d6675 | 6666 | /* control registers: */ |
800eeca4 JW |
6667 | total += 128; |
6668 | cr_base = i; | |
6669 | for (; i < total; ++i) | |
6670 | { | |
6671 | sprintf (name, "cr%d", i - REG_CR); | |
6672 | md.regsym[i] = declare_register (name, i); | |
6673 | } | |
6674 | ||
542d6675 | 6675 | /* predicate registers: */ |
800eeca4 JW |
6676 | total += 64; |
6677 | for (; i < total; ++i) | |
6678 | { | |
6679 | sprintf (name, "p%d", i - REG_P); | |
6680 | md.regsym[i] = declare_register (name, i); | |
6681 | } | |
6682 | ||
542d6675 | 6683 | /* branch registers: */ |
800eeca4 JW |
6684 | total += 8; |
6685 | for (; i < total; ++i) | |
6686 | { | |
6687 | sprintf (name, "b%d", i - REG_BR); | |
6688 | md.regsym[i] = declare_register (name, i); | |
6689 | } | |
6690 | ||
6691 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); | |
6692 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); | |
6693 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); | |
6694 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); | |
6695 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); | |
6696 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); | |
6697 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); | |
6698 | ||
6699 | for (i = 0; i < NELEMS (indirect_reg); ++i) | |
6700 | { | |
6701 | regnum = indirect_reg[i].regnum; | |
6702 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); | |
6703 | } | |
6704 | ||
542d6675 | 6705 | /* define synonyms for application registers: */ |
800eeca4 JW |
6706 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
6707 | md.regsym[i] = declare_register (ar[i - REG_AR].name, | |
6708 | REG_AR + ar[i - REG_AR].regnum); | |
6709 | ||
542d6675 | 6710 | /* define synonyms for control registers: */ |
800eeca4 JW |
6711 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
6712 | md.regsym[i] = declare_register (cr[i - REG_CR].name, | |
6713 | REG_CR + cr[i - REG_CR].regnum); | |
6714 | ||
6715 | declare_register ("gp", REG_GR + 1); | |
6716 | declare_register ("sp", REG_GR + 12); | |
6717 | declare_register ("rp", REG_BR + 0); | |
6718 | ||
542d6675 | 6719 | /* pseudo-registers used to specify unwind info: */ |
e0c9811a JW |
6720 | declare_register ("psp", REG_PSP); |
6721 | ||
800eeca4 JW |
6722 | declare_register_set ("ret", 4, REG_GR + 8); |
6723 | declare_register_set ("farg", 8, REG_FR + 8); | |
6724 | declare_register_set ("fret", 8, REG_FR + 8); | |
6725 | ||
6726 | for (i = 0; i < NELEMS (const_bits); ++i) | |
6727 | { | |
6728 | err = hash_insert (md.const_hash, const_bits[i].name, | |
6729 | (PTR) (const_bits + i)); | |
6730 | if (err) | |
6731 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", | |
6732 | name, err); | |
6733 | } | |
6734 | ||
44f5c83a JW |
6735 | /* Set the architecture and machine depending on defaults and command line |
6736 | options. */ | |
6737 | if (md.flags & EF_IA_64_ABI64) | |
6738 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); | |
6739 | else | |
6740 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); | |
6741 | ||
6742 | if (! ok) | |
6743 | as_warn (_("Could not set architecture and machine")); | |
800eeca4 | 6744 | |
557debba JW |
6745 | /* Set the pointer size and pointer shift size depending on md.flags */ |
6746 | ||
6747 | if (md.flags & EF_IA_64_ABI64) | |
6748 | { | |
6749 | md.pointer_size = 8; /* pointers are 8 bytes */ | |
6750 | md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ | |
6751 | } | |
6752 | else | |
6753 | { | |
6754 | md.pointer_size = 4; /* pointers are 4 bytes */ | |
6755 | md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ | |
6756 | } | |
6757 | ||
800eeca4 JW |
6758 | md.mem_offset.hint = 0; |
6759 | md.path = 0; | |
6760 | md.maxpaths = 0; | |
6761 | md.entry_labels = NULL; | |
6762 | } | |
6763 | ||
44f5c83a JW |
6764 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
6765 | because that is called after md_parse_option which is where we do the | |
6766 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the | |
6767 | default endianness. */ | |
6768 | ||
6769 | void | |
6770 | ia64_init (argc, argv) | |
2434f565 JW |
6771 | int argc ATTRIBUTE_UNUSED; |
6772 | char **argv ATTRIBUTE_UNUSED; | |
44f5c83a | 6773 | { |
1cd8ff38 | 6774 | md.flags = MD_FLAGS_DEFAULT; |
44f5c83a JW |
6775 | } |
6776 | ||
6777 | /* Return a string for the target object file format. */ | |
6778 | ||
6779 | const char * | |
6780 | ia64_target_format () | |
6781 | { | |
6782 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6783 | { | |
72a76794 JW |
6784 | if (md.flags & EF_IA_64_BE) |
6785 | { | |
6786 | if (md.flags & EF_IA_64_ABI64) | |
1cd8ff38 | 6787 | #if defined(TE_AIX50) |
7463c317 | 6788 | return "elf64-ia64-aix-big"; |
1cd8ff38 NC |
6789 | #elif defined(TE_HPUX) |
6790 | return "elf64-ia64-hpux-big"; | |
7463c317 | 6791 | #else |
72a76794 | 6792 | return "elf64-ia64-big"; |
7463c317 | 6793 | #endif |
72a76794 | 6794 | else |
1cd8ff38 | 6795 | #if defined(TE_AIX50) |
7463c317 | 6796 | return "elf32-ia64-aix-big"; |
1cd8ff38 NC |
6797 | #elif defined(TE_HPUX) |
6798 | return "elf32-ia64-hpux-big"; | |
7463c317 | 6799 | #else |
72a76794 | 6800 | return "elf32-ia64-big"; |
7463c317 | 6801 | #endif |
72a76794 | 6802 | } |
44f5c83a | 6803 | else |
72a76794 JW |
6804 | { |
6805 | if (md.flags & EF_IA_64_ABI64) | |
7463c317 TW |
6806 | #ifdef TE_AIX50 |
6807 | return "elf64-ia64-aix-little"; | |
6808 | #else | |
72a76794 | 6809 | return "elf64-ia64-little"; |
7463c317 | 6810 | #endif |
72a76794 | 6811 | else |
7463c317 TW |
6812 | #ifdef TE_AIX50 |
6813 | return "elf32-ia64-aix-little"; | |
6814 | #else | |
72a76794 | 6815 | return "elf32-ia64-little"; |
7463c317 | 6816 | #endif |
72a76794 | 6817 | } |
44f5c83a JW |
6818 | } |
6819 | else | |
6820 | return "unknown-format"; | |
6821 | } | |
6822 | ||
800eeca4 JW |
6823 | void |
6824 | ia64_end_of_source () | |
6825 | { | |
542d6675 | 6826 | /* terminate insn group upon reaching end of file: */ |
800eeca4 JW |
6827 | insn_group_break (1, 0, 0); |
6828 | ||
542d6675 | 6829 | /* emits slots we haven't written yet: */ |
800eeca4 JW |
6830 | ia64_flush_insns (); |
6831 | ||
6832 | bfd_set_private_flags (stdoutput, md.flags); | |
6833 | ||
800eeca4 JW |
6834 | md.mem_offset.hint = 0; |
6835 | } | |
6836 | ||
6837 | void | |
6838 | ia64_start_line () | |
6839 | { | |
f1bcba5b JW |
6840 | if (md.qp.X_op == O_register) |
6841 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
6842 | md.qp.X_op = O_absent; |
6843 | ||
6844 | if (ignore_input ()) | |
6845 | return; | |
6846 | ||
6847 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') | |
6848 | { | |
6849 | if (md.detect_dv && !md.explicit_mode) | |
542d6675 | 6850 | as_warn (_("Explicit stops are ignored in auto mode")); |
800eeca4 | 6851 | else |
542d6675 | 6852 | insn_group_break (1, 0, 0); |
800eeca4 JW |
6853 | } |
6854 | } | |
6855 | ||
f1bcba5b JW |
6856 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
6857 | labels. */ | |
6858 | static int defining_tag = 0; | |
6859 | ||
800eeca4 JW |
6860 | int |
6861 | ia64_unrecognized_line (ch) | |
6862 | int ch; | |
6863 | { | |
6864 | switch (ch) | |
6865 | { | |
6866 | case '(': | |
6867 | expression (&md.qp); | |
6868 | if (*input_line_pointer++ != ')') | |
6869 | { | |
6870 | as_bad ("Expected ')'"); | |
6871 | return 0; | |
6872 | } | |
6873 | if (md.qp.X_op != O_register) | |
6874 | { | |
6875 | as_bad ("Qualifying predicate expected"); | |
6876 | return 0; | |
6877 | } | |
6878 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) | |
6879 | { | |
6880 | as_bad ("Predicate register expected"); | |
6881 | return 0; | |
6882 | } | |
6883 | return 1; | |
6884 | ||
6885 | case '{': | |
6886 | if (md.manual_bundling) | |
6887 | as_warn ("Found '{' when manual bundling is already turned on"); | |
6888 | else | |
6889 | CURR_SLOT.manual_bundling_on = 1; | |
6890 | md.manual_bundling = 1; | |
6891 | ||
542d6675 KH |
6892 | /* Bundling is only acceptable in explicit mode |
6893 | or when in default automatic mode. */ | |
800eeca4 | 6894 | if (md.detect_dv && !md.explicit_mode) |
542d6675 KH |
6895 | { |
6896 | if (!md.mode_explicitly_set | |
6897 | && !md.default_explicit_mode) | |
6898 | dot_dv_mode ('E'); | |
6899 | else | |
6900 | as_warn (_("Found '{' after explicit switch to automatic mode")); | |
6901 | } | |
800eeca4 JW |
6902 | return 1; |
6903 | ||
6904 | case '}': | |
6905 | if (!md.manual_bundling) | |
6906 | as_warn ("Found '}' when manual bundling is off"); | |
6907 | else | |
6908 | PREV_SLOT.manual_bundling_off = 1; | |
6909 | md.manual_bundling = 0; | |
6910 | ||
6911 | /* switch back to automatic mode, if applicable */ | |
197865e8 | 6912 | if (md.detect_dv |
542d6675 KH |
6913 | && md.explicit_mode |
6914 | && !md.mode_explicitly_set | |
6915 | && !md.default_explicit_mode) | |
6916 | dot_dv_mode ('A'); | |
800eeca4 JW |
6917 | |
6918 | /* Allow '{' to follow on the same line. We also allow ";;", but that | |
6919 | happens automatically because ';' is an end of line marker. */ | |
6920 | SKIP_WHITESPACE (); | |
6921 | if (input_line_pointer[0] == '{') | |
6922 | { | |
6923 | input_line_pointer++; | |
6924 | return ia64_unrecognized_line ('{'); | |
6925 | } | |
6926 | ||
6927 | demand_empty_rest_of_line (); | |
6928 | return 1; | |
6929 | ||
f1bcba5b JW |
6930 | case '[': |
6931 | { | |
6932 | char *s; | |
6933 | char c; | |
6934 | symbolS *tag; | |
4d5a53ff | 6935 | int temp; |
f1bcba5b JW |
6936 | |
6937 | if (md.qp.X_op == O_register) | |
6938 | { | |
6939 | as_bad ("Tag must come before qualifying predicate."); | |
6940 | return 0; | |
6941 | } | |
4d5a53ff JW |
6942 | |
6943 | /* This implements just enough of read_a_source_file in read.c to | |
6944 | recognize labels. */ | |
6945 | if (is_name_beginner (*input_line_pointer)) | |
6946 | { | |
6947 | s = input_line_pointer; | |
6948 | c = get_symbol_end (); | |
6949 | } | |
6950 | else if (LOCAL_LABELS_FB | |
3882b010 | 6951 | && ISDIGIT (*input_line_pointer)) |
4d5a53ff JW |
6952 | { |
6953 | temp = 0; | |
3882b010 | 6954 | while (ISDIGIT (*input_line_pointer)) |
4d5a53ff JW |
6955 | temp = (temp * 10) + *input_line_pointer++ - '0'; |
6956 | fb_label_instance_inc (temp); | |
6957 | s = fb_label_name (temp, 0); | |
6958 | c = *input_line_pointer; | |
6959 | } | |
6960 | else | |
6961 | { | |
6962 | s = NULL; | |
6963 | c = '\0'; | |
6964 | } | |
f1bcba5b JW |
6965 | if (c != ':') |
6966 | { | |
6967 | /* Put ':' back for error messages' sake. */ | |
6968 | *input_line_pointer++ = ':'; | |
6969 | as_bad ("Expected ':'"); | |
6970 | return 0; | |
6971 | } | |
4d5a53ff | 6972 | |
f1bcba5b JW |
6973 | defining_tag = 1; |
6974 | tag = colon (s); | |
6975 | defining_tag = 0; | |
6976 | /* Put ':' back for error messages' sake. */ | |
6977 | *input_line_pointer++ = ':'; | |
6978 | if (*input_line_pointer++ != ']') | |
6979 | { | |
6980 | as_bad ("Expected ']'"); | |
6981 | return 0; | |
6982 | } | |
6983 | if (! tag) | |
6984 | { | |
6985 | as_bad ("Tag name expected"); | |
6986 | return 0; | |
6987 | } | |
6988 | return 1; | |
6989 | } | |
6990 | ||
800eeca4 JW |
6991 | default: |
6992 | break; | |
6993 | } | |
542d6675 KH |
6994 | |
6995 | /* Not a valid line. */ | |
6996 | return 0; | |
800eeca4 JW |
6997 | } |
6998 | ||
6999 | void | |
7000 | ia64_frob_label (sym) | |
7001 | struct symbol *sym; | |
7002 | { | |
7003 | struct label_fix *fix; | |
7004 | ||
f1bcba5b JW |
7005 | /* Tags need special handling since they are not bundle breaks like |
7006 | labels. */ | |
7007 | if (defining_tag) | |
7008 | { | |
7009 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
7010 | fix->sym = sym; | |
7011 | fix->next = CURR_SLOT.tag_fixups; | |
7012 | CURR_SLOT.tag_fixups = fix; | |
7013 | ||
7014 | return; | |
7015 | } | |
7016 | ||
800eeca4 JW |
7017 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
7018 | { | |
7019 | md.last_text_seg = now_seg; | |
7020 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
7021 | fix->sym = sym; | |
7022 | fix->next = CURR_SLOT.label_fixups; | |
7023 | CURR_SLOT.label_fixups = fix; | |
7024 | ||
542d6675 | 7025 | /* Keep track of how many code entry points we've seen. */ |
800eeca4 | 7026 | if (md.path == md.maxpaths) |
542d6675 KH |
7027 | { |
7028 | md.maxpaths += 20; | |
7029 | md.entry_labels = (const char **) | |
7030 | xrealloc ((void *) md.entry_labels, | |
7031 | md.maxpaths * sizeof (char *)); | |
7032 | } | |
800eeca4 JW |
7033 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
7034 | } | |
7035 | } | |
7036 | ||
7037 | void | |
7038 | ia64_flush_pending_output () | |
7039 | { | |
4d5a53ff JW |
7040 | if (!md.keep_pending_output |
7041 | && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) | |
800eeca4 JW |
7042 | { |
7043 | /* ??? This causes many unnecessary stop bits to be emitted. | |
7044 | Unfortunately, it isn't clear if it is safe to remove this. */ | |
7045 | insn_group_break (1, 0, 0); | |
7046 | ia64_flush_insns (); | |
7047 | } | |
7048 | } | |
7049 | ||
7050 | /* Do ia64-specific expression optimization. All that's done here is | |
7051 | to transform index expressions that are either due to the indexing | |
7052 | of rotating registers or due to the indexing of indirect register | |
7053 | sets. */ | |
7054 | int | |
7055 | ia64_optimize_expr (l, op, r) | |
7056 | expressionS *l; | |
7057 | operatorT op; | |
7058 | expressionS *r; | |
7059 | { | |
7060 | unsigned num_regs; | |
7061 | ||
7062 | if (op == O_index) | |
7063 | { | |
7064 | if (l->X_op == O_register && r->X_op == O_constant) | |
7065 | { | |
7066 | num_regs = (l->X_add_number >> 16); | |
7067 | if ((unsigned) r->X_add_number >= num_regs) | |
7068 | { | |
7069 | if (!num_regs) | |
7070 | as_bad ("No current frame"); | |
7071 | else | |
7072 | as_bad ("Index out of range 0..%u", num_regs - 1); | |
7073 | r->X_add_number = 0; | |
7074 | } | |
7075 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; | |
7076 | return 1; | |
7077 | } | |
7078 | else if (l->X_op == O_register && r->X_op == O_register) | |
7079 | { | |
7080 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR | |
7081 | || l->X_add_number == IND_MEM) | |
7082 | { | |
7083 | as_bad ("Indirect register set name expected"); | |
7084 | l->X_add_number = IND_CPUID; | |
7085 | } | |
7086 | l->X_op = O_index; | |
7087 | l->X_op_symbol = md.regsym[l->X_add_number]; | |
7088 | l->X_add_number = r->X_add_number; | |
7089 | return 1; | |
7090 | } | |
7091 | } | |
7092 | return 0; | |
7093 | } | |
7094 | ||
7095 | int | |
7096 | ia64_parse_name (name, e) | |
7097 | char *name; | |
7098 | expressionS *e; | |
7099 | { | |
7100 | struct const_desc *cdesc; | |
7101 | struct dynreg *dr = 0; | |
7102 | unsigned int regnum; | |
7103 | struct symbol *sym; | |
7104 | char *end; | |
7105 | ||
542d6675 | 7106 | /* first see if NAME is a known register name: */ |
800eeca4 JW |
7107 | sym = hash_find (md.reg_hash, name); |
7108 | if (sym) | |
7109 | { | |
7110 | e->X_op = O_register; | |
7111 | e->X_add_number = S_GET_VALUE (sym); | |
7112 | return 1; | |
7113 | } | |
7114 | ||
7115 | cdesc = hash_find (md.const_hash, name); | |
7116 | if (cdesc) | |
7117 | { | |
7118 | e->X_op = O_constant; | |
7119 | e->X_add_number = cdesc->value; | |
7120 | return 1; | |
7121 | } | |
7122 | ||
542d6675 | 7123 | /* check for inN, locN, or outN: */ |
800eeca4 JW |
7124 | switch (name[0]) |
7125 | { | |
7126 | case 'i': | |
3882b010 | 7127 | if (name[1] == 'n' && ISDIGIT (name[2])) |
800eeca4 JW |
7128 | { |
7129 | dr = &md.in; | |
7130 | name += 2; | |
7131 | } | |
7132 | break; | |
7133 | ||
7134 | case 'l': | |
3882b010 | 7135 | if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) |
800eeca4 JW |
7136 | { |
7137 | dr = &md.loc; | |
7138 | name += 3; | |
7139 | } | |
7140 | break; | |
7141 | ||
7142 | case 'o': | |
3882b010 | 7143 | if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) |
800eeca4 JW |
7144 | { |
7145 | dr = &md.out; | |
7146 | name += 3; | |
7147 | } | |
7148 | break; | |
7149 | ||
7150 | default: | |
7151 | break; | |
7152 | } | |
7153 | ||
7154 | if (dr) | |
7155 | { | |
542d6675 | 7156 | /* The name is inN, locN, or outN; parse the register number. */ |
800eeca4 JW |
7157 | regnum = strtoul (name, &end, 10); |
7158 | if (end > name && *end == '\0') | |
7159 | { | |
7160 | if ((unsigned) regnum >= dr->num_regs) | |
7161 | { | |
7162 | if (!dr->num_regs) | |
7163 | as_bad ("No current frame"); | |
7164 | else | |
542d6675 KH |
7165 | as_bad ("Register number out of range 0..%u", |
7166 | dr->num_regs - 1); | |
800eeca4 JW |
7167 | regnum = 0; |
7168 | } | |
7169 | e->X_op = O_register; | |
7170 | e->X_add_number = dr->base + regnum; | |
7171 | return 1; | |
7172 | } | |
7173 | } | |
7174 | ||
7175 | if ((dr = hash_find (md.dynreg_hash, name))) | |
7176 | { | |
7177 | /* We've got ourselves the name of a rotating register set. | |
542d6675 KH |
7178 | Store the base register number in the low 16 bits of |
7179 | X_add_number and the size of the register set in the top 16 | |
7180 | bits. */ | |
800eeca4 JW |
7181 | e->X_op = O_register; |
7182 | e->X_add_number = dr->base | (dr->num_regs << 16); | |
7183 | return 1; | |
7184 | } | |
7185 | return 0; | |
7186 | } | |
7187 | ||
7188 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ | |
7189 | ||
7190 | char * | |
7191 | ia64_canonicalize_symbol_name (name) | |
7192 | char *name; | |
7193 | { | |
542d6675 KH |
7194 | size_t len = strlen (name); |
7195 | if (len > 1 && name[len - 1] == '#') | |
7196 | name[len - 1] = '\0'; | |
800eeca4 JW |
7197 | return name; |
7198 | } | |
7199 | ||
3e37788f JW |
7200 | /* Return true if idesc is a conditional branch instruction. This excludes |
7201 | the modulo scheduled branches, and br.ia. Mod-sched branches are excluded | |
7202 | because they always read/write resources regardless of the value of the | |
7203 | qualifying predicate. br.ia must always use p0, and hence is always | |
7204 | taken. Thus this function returns true for branches which can fall | |
7205 | through, and which use no resources if they do fall through. */ | |
1deb8127 | 7206 | |
800eeca4 JW |
7207 | static int |
7208 | is_conditional_branch (idesc) | |
542d6675 | 7209 | struct ia64_opcode *idesc; |
800eeca4 | 7210 | { |
1deb8127 | 7211 | /* br is a conditional branch. Everything that starts with br. except |
3e37788f JW |
7212 | br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. |
7213 | Everything that starts with brl is a conditional branch. */ | |
1deb8127 JW |
7214 | return (idesc->name[0] == 'b' && idesc->name[1] == 'r' |
7215 | && (idesc->name[2] == '\0' | |
3e37788f JW |
7216 | || (idesc->name[2] == '.' && idesc->name[3] != 'i' |
7217 | && idesc->name[3] != 'c' && idesc->name[3] != 'w') | |
7218 | || idesc->name[2] == 'l' | |
7219 | /* br.cond, br.call, br.clr */ | |
7220 | || (idesc->name[2] == '.' && idesc->name[3] == 'c' | |
7221 | && (idesc->name[4] == 'a' || idesc->name[4] == 'o' | |
7222 | || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); | |
800eeca4 JW |
7223 | } |
7224 | ||
7225 | /* Return whether the given opcode is a taken branch. If there's any doubt, | |
542d6675 KH |
7226 | returns zero. */ |
7227 | ||
800eeca4 JW |
7228 | static int |
7229 | is_taken_branch (idesc) | |
542d6675 | 7230 | struct ia64_opcode *idesc; |
800eeca4 JW |
7231 | { |
7232 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) | |
542d6675 | 7233 | || strncmp (idesc->name, "br.ia", 5) == 0); |
800eeca4 JW |
7234 | } |
7235 | ||
7236 | /* Return whether the given opcode is an interruption or rfi. If there's any | |
542d6675 KH |
7237 | doubt, returns zero. */ |
7238 | ||
800eeca4 JW |
7239 | static int |
7240 | is_interruption_or_rfi (idesc) | |
542d6675 | 7241 | struct ia64_opcode *idesc; |
800eeca4 JW |
7242 | { |
7243 | if (strcmp (idesc->name, "rfi") == 0) | |
7244 | return 1; | |
7245 | return 0; | |
7246 | } | |
7247 | ||
7248 | /* Returns the index of the given dependency in the opcode's list of chks, or | |
7249 | -1 if there is no dependency. */ | |
542d6675 | 7250 | |
800eeca4 JW |
7251 | static int |
7252 | depends_on (depind, idesc) | |
542d6675 KH |
7253 | int depind; |
7254 | struct ia64_opcode *idesc; | |
800eeca4 JW |
7255 | { |
7256 | int i; | |
7257 | const struct ia64_opcode_dependency *dep = idesc->dependencies; | |
542d6675 | 7258 | for (i = 0; i < dep->nchks; i++) |
800eeca4 | 7259 | { |
542d6675 KH |
7260 | if (depind == DEP (dep->chks[i])) |
7261 | return i; | |
800eeca4 JW |
7262 | } |
7263 | return -1; | |
7264 | } | |
7265 | ||
7266 | /* Determine a set of specific resources used for a particular resource | |
7267 | class. Returns the number of specific resources identified For those | |
7268 | cases which are not determinable statically, the resource returned is | |
197865e8 | 7269 | marked nonspecific. |
800eeca4 JW |
7270 | |
7271 | Meanings of value in 'NOTE': | |
7272 | 1) only read/write when the register number is explicitly encoded in the | |
7273 | insn. | |
7274 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only | |
197865e8 | 7275 | accesses CFM when qualifying predicate is in the rotating region. |
800eeca4 JW |
7276 | 3) general register value is used to specify an indirect register; not |
7277 | determinable statically. | |
7278 | 4) only read the given resource when bits 7:0 of the indirect index | |
7279 | register value does not match the register number of the resource; not | |
7280 | determinable statically. | |
7281 | 5) all rules are implementation specific. | |
7282 | 6) only when both the index specified by the reader and the index specified | |
7283 | by the writer have the same value in bits 63:61; not determinable | |
197865e8 | 7284 | statically. |
800eeca4 | 7285 | 7) only access the specified resource when the corresponding mask bit is |
197865e8 | 7286 | set |
800eeca4 JW |
7287 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
7288 | only read when these insns reference FR2-31 | |
7289 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only | |
7290 | written when these insns write FR32-127 | |
7291 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the | |
7292 | instruction | |
7293 | 11) The target predicates are written independently of PR[qp], but source | |
7294 | registers are only read if PR[qp] is true. Since the state of PR[qp] | |
7295 | cannot statically be determined, all source registers are marked used. | |
7296 | 12) This insn only reads the specified predicate register when that | |
7297 | register is the PR[qp]. | |
7298 | 13) This reference to ld-c only applies to teh GR whose value is loaded | |
197865e8 | 7299 | with data returned from memory, not the post-incremented address register. |
800eeca4 JW |
7300 | 14) The RSE resource includes the implementation-specific RSE internal |
7301 | state resources. At least one (and possibly more) of these resources are | |
7302 | read by each instruction listed in IC:rse-readers. At least one (and | |
7303 | possibly more) of these resources are written by each insn listed in | |
197865e8 | 7304 | IC:rse-writers. |
800eeca4 | 7305 | 15+16) Represents reserved instructions, which the assembler does not |
197865e8 | 7306 | generate. |
800eeca4 JW |
7307 | |
7308 | Memory resources (i.e. locations in memory) are *not* marked or tracked by | |
7309 | this code; there are no dependency violations based on memory access. | |
800eeca4 JW |
7310 | */ |
7311 | ||
7312 | #define MAX_SPECS 256 | |
7313 | #define DV_CHK 1 | |
7314 | #define DV_REG 0 | |
7315 | ||
7316 | static int | |
7317 | specify_resource (dep, idesc, type, specs, note, path) | |
542d6675 KH |
7318 | const struct ia64_dependency *dep; |
7319 | struct ia64_opcode *idesc; | |
7320 | int type; /* is this a DV chk or a DV reg? */ | |
7321 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ | |
7322 | int note; /* resource note for this insn's usage */ | |
7323 | int path; /* which execution path to examine */ | |
800eeca4 JW |
7324 | { |
7325 | int count = 0; | |
7326 | int i; | |
7327 | int rsrc_write = 0; | |
7328 | struct rsrc tmpl; | |
197865e8 | 7329 | |
800eeca4 JW |
7330 | if (dep->mode == IA64_DV_WAW |
7331 | || (dep->mode == IA64_DV_RAW && type == DV_REG) | |
7332 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) | |
7333 | rsrc_write = 1; | |
7334 | ||
7335 | /* template for any resources we identify */ | |
7336 | tmpl.dependency = dep; | |
7337 | tmpl.note = note; | |
7338 | tmpl.insn_srlz = tmpl.data_srlz = 0; | |
7339 | tmpl.qp_regno = CURR_SLOT.qp_regno; | |
7340 | tmpl.link_to_qp_branch = 1; | |
7341 | tmpl.mem_offset.hint = 0; | |
7342 | tmpl.specific = 1; | |
7343 | tmpl.index = 0; | |
7484b8e6 | 7344 | tmpl.cmp_type = CMP_NONE; |
800eeca4 JW |
7345 | |
7346 | #define UNHANDLED \ | |
7347 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ | |
7348 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) | |
7349 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) | |
7350 | ||
7351 | /* we don't need to track these */ | |
7352 | if (dep->semantics == IA64_DVS_NONE) | |
7353 | return 0; | |
7354 | ||
7355 | switch (dep->specifier) | |
7356 | { | |
7357 | case IA64_RS_AR_K: | |
7358 | if (note == 1) | |
542d6675 KH |
7359 | { |
7360 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7361 | { | |
7362 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7363 | if (regno >= 0 && regno <= 7) | |
7364 | { | |
7365 | specs[count] = tmpl; | |
7366 | specs[count++].index = regno; | |
7367 | } | |
7368 | } | |
7369 | } | |
800eeca4 | 7370 | else if (note == 0) |
542d6675 KH |
7371 | { |
7372 | for (i = 0; i < 8; i++) | |
7373 | { | |
7374 | specs[count] = tmpl; | |
7375 | specs[count++].index = i; | |
7376 | } | |
7377 | } | |
800eeca4 | 7378 | else |
542d6675 KH |
7379 | { |
7380 | UNHANDLED; | |
7381 | } | |
800eeca4 JW |
7382 | break; |
7383 | ||
7384 | case IA64_RS_AR_UNAT: | |
7385 | /* This is a mov =AR or mov AR= instruction. */ | |
7386 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7387 | { | |
7388 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7389 | if (regno == AR_UNAT) | |
7390 | { | |
7391 | specs[count++] = tmpl; | |
7392 | } | |
7393 | } | |
7394 | else | |
7395 | { | |
7396 | /* This is a spill/fill, or other instruction that modifies the | |
7397 | unat register. */ | |
7398 | ||
7399 | /* Unless we can determine the specific bits used, mark the whole | |
7400 | thing; bits 8:3 of the memory address indicate the bit used in | |
7401 | UNAT. The .mem.offset hint may be used to eliminate a small | |
7402 | subset of conflicts. */ | |
7403 | specs[count] = tmpl; | |
7404 | if (md.mem_offset.hint) | |
7405 | { | |
542d6675 KH |
7406 | if (md.debug_dv) |
7407 | fprintf (stderr, " Using hint for spill/fill\n"); | |
7408 | /* The index isn't actually used, just set it to something | |
7409 | approximating the bit index. */ | |
800eeca4 JW |
7410 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
7411 | specs[count].mem_offset.hint = 1; | |
7412 | specs[count].mem_offset.offset = md.mem_offset.offset; | |
7413 | specs[count++].mem_offset.base = md.mem_offset.base; | |
7414 | } | |
7415 | else | |
7416 | { | |
7417 | specs[count++].specific = 0; | |
7418 | } | |
7419 | } | |
7420 | break; | |
7421 | ||
7422 | case IA64_RS_AR: | |
7423 | if (note == 1) | |
542d6675 KH |
7424 | { |
7425 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7426 | { | |
7427 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7428 | if ((regno >= 8 && regno <= 15) | |
7429 | || (regno >= 20 && regno <= 23) | |
7430 | || (regno >= 31 && regno <= 39) | |
7431 | || (regno >= 41 && regno <= 47) | |
7432 | || (regno >= 67 && regno <= 111)) | |
7433 | { | |
7434 | specs[count] = tmpl; | |
7435 | specs[count++].index = regno; | |
7436 | } | |
7437 | } | |
7438 | } | |
800eeca4 | 7439 | else |
542d6675 KH |
7440 | { |
7441 | UNHANDLED; | |
7442 | } | |
800eeca4 JW |
7443 | break; |
7444 | ||
7445 | case IA64_RS_ARb: | |
7446 | if (note == 1) | |
542d6675 KH |
7447 | { |
7448 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7449 | { | |
7450 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7451 | if ((regno >= 48 && regno <= 63) | |
7452 | || (regno >= 112 && regno <= 127)) | |
7453 | { | |
7454 | specs[count] = tmpl; | |
7455 | specs[count++].index = regno; | |
7456 | } | |
7457 | } | |
7458 | } | |
800eeca4 | 7459 | else if (note == 0) |
542d6675 KH |
7460 | { |
7461 | for (i = 48; i < 64; i++) | |
7462 | { | |
7463 | specs[count] = tmpl; | |
7464 | specs[count++].index = i; | |
7465 | } | |
7466 | for (i = 112; i < 128; i++) | |
7467 | { | |
7468 | specs[count] = tmpl; | |
7469 | specs[count++].index = i; | |
7470 | } | |
7471 | } | |
197865e8 | 7472 | else |
542d6675 KH |
7473 | { |
7474 | UNHANDLED; | |
7475 | } | |
800eeca4 JW |
7476 | break; |
7477 | ||
7478 | case IA64_RS_BR: | |
7479 | if (note != 1) | |
542d6675 KH |
7480 | { |
7481 | UNHANDLED; | |
7482 | } | |
800eeca4 | 7483 | else |
542d6675 KH |
7484 | { |
7485 | if (rsrc_write) | |
7486 | { | |
7487 | for (i = 0; i < idesc->num_outputs; i++) | |
7488 | if (idesc->operands[i] == IA64_OPND_B1 | |
7489 | || idesc->operands[i] == IA64_OPND_B2) | |
7490 | { | |
7491 | specs[count] = tmpl; | |
7492 | specs[count++].index = | |
7493 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
7494 | } | |
7495 | } | |
7496 | else | |
7497 | { | |
40449e9f | 7498 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) |
542d6675 KH |
7499 | if (idesc->operands[i] == IA64_OPND_B1 |
7500 | || idesc->operands[i] == IA64_OPND_B2) | |
7501 | { | |
7502 | specs[count] = tmpl; | |
7503 | specs[count++].index = | |
7504 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
7505 | } | |
7506 | } | |
7507 | } | |
800eeca4 JW |
7508 | break; |
7509 | ||
7510 | case IA64_RS_CPUID: /* four or more registers */ | |
7511 | if (note == 3) | |
542d6675 KH |
7512 | { |
7513 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) | |
7514 | { | |
7515 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7516 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7517 | && KNOWN (regno)) | |
7518 | { | |
7519 | specs[count] = tmpl; | |
7520 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7521 | } | |
7522 | else | |
7523 | { | |
7524 | specs[count] = tmpl; | |
7525 | specs[count++].specific = 0; | |
7526 | } | |
7527 | } | |
7528 | } | |
800eeca4 | 7529 | else |
542d6675 KH |
7530 | { |
7531 | UNHANDLED; | |
7532 | } | |
800eeca4 JW |
7533 | break; |
7534 | ||
7535 | case IA64_RS_DBR: /* four or more registers */ | |
7536 | if (note == 3) | |
542d6675 KH |
7537 | { |
7538 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) | |
7539 | { | |
7540 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7541 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7542 | && KNOWN (regno)) | |
7543 | { | |
7544 | specs[count] = tmpl; | |
7545 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7546 | } | |
7547 | else | |
7548 | { | |
7549 | specs[count] = tmpl; | |
7550 | specs[count++].specific = 0; | |
7551 | } | |
7552 | } | |
7553 | } | |
800eeca4 | 7554 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7555 | { |
7556 | specs[count] = tmpl; | |
7557 | specs[count++].specific = 0; | |
7558 | } | |
800eeca4 | 7559 | else |
542d6675 KH |
7560 | { |
7561 | UNHANDLED; | |
7562 | } | |
800eeca4 JW |
7563 | break; |
7564 | ||
7565 | case IA64_RS_IBR: /* four or more registers */ | |
7566 | if (note == 3) | |
542d6675 KH |
7567 | { |
7568 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) | |
7569 | { | |
7570 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7571 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7572 | && KNOWN (regno)) | |
7573 | { | |
7574 | specs[count] = tmpl; | |
7575 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7576 | } | |
7577 | else | |
7578 | { | |
7579 | specs[count] = tmpl; | |
7580 | specs[count++].specific = 0; | |
7581 | } | |
7582 | } | |
7583 | } | |
800eeca4 | 7584 | else |
542d6675 KH |
7585 | { |
7586 | UNHANDLED; | |
7587 | } | |
800eeca4 JW |
7588 | break; |
7589 | ||
7590 | case IA64_RS_MSR: | |
7591 | if (note == 5) | |
7592 | { | |
7593 | /* These are implementation specific. Force all references to | |
7594 | conflict with all other references. */ | |
7595 | specs[count] = tmpl; | |
7596 | specs[count++].specific = 0; | |
7597 | } | |
7598 | else | |
7599 | { | |
7600 | UNHANDLED; | |
7601 | } | |
7602 | break; | |
7603 | ||
7604 | case IA64_RS_PKR: /* 16 or more registers */ | |
7605 | if (note == 3 || note == 4) | |
542d6675 KH |
7606 | { |
7607 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) | |
7608 | { | |
7609 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7610 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7611 | && KNOWN (regno)) | |
7612 | { | |
7613 | if (note == 3) | |
7614 | { | |
7615 | specs[count] = tmpl; | |
7616 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7617 | } | |
7618 | else | |
7619 | for (i = 0; i < NELEMS (gr_values); i++) | |
7620 | { | |
7621 | /* Uses all registers *except* the one in R3. */ | |
2434f565 | 7622 | if ((unsigned)i != (gr_values[regno].value & 0xFF)) |
542d6675 KH |
7623 | { |
7624 | specs[count] = tmpl; | |
7625 | specs[count++].index = i; | |
7626 | } | |
7627 | } | |
7628 | } | |
7629 | else | |
7630 | { | |
7631 | specs[count] = tmpl; | |
7632 | specs[count++].specific = 0; | |
7633 | } | |
7634 | } | |
7635 | } | |
7636 | else if (note == 0) | |
7637 | { | |
7638 | /* probe et al. */ | |
7639 | specs[count] = tmpl; | |
7640 | specs[count++].specific = 0; | |
7641 | } | |
7642 | break; | |
7643 | ||
7644 | case IA64_RS_PMC: /* four or more registers */ | |
7645 | if (note == 3) | |
7646 | { | |
7647 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 | |
7648 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) | |
7649 | ||
7650 | { | |
7651 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) | |
7652 | ? 1 : !rsrc_write); | |
7653 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; | |
7654 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7655 | && KNOWN (regno)) | |
7656 | { | |
7657 | specs[count] = tmpl; | |
7658 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7659 | } | |
7660 | else | |
7661 | { | |
7662 | specs[count] = tmpl; | |
7663 | specs[count++].specific = 0; | |
7664 | } | |
7665 | } | |
7666 | } | |
7667 | else | |
7668 | { | |
7669 | UNHANDLED; | |
7670 | } | |
800eeca4 JW |
7671 | break; |
7672 | ||
7673 | case IA64_RS_PMD: /* four or more registers */ | |
7674 | if (note == 3) | |
542d6675 KH |
7675 | { |
7676 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) | |
7677 | { | |
7678 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7679 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7680 | && KNOWN (regno)) | |
7681 | { | |
7682 | specs[count] = tmpl; | |
7683 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7684 | } | |
7685 | else | |
7686 | { | |
7687 | specs[count] = tmpl; | |
7688 | specs[count++].specific = 0; | |
7689 | } | |
7690 | } | |
7691 | } | |
800eeca4 | 7692 | else |
542d6675 KH |
7693 | { |
7694 | UNHANDLED; | |
7695 | } | |
800eeca4 JW |
7696 | break; |
7697 | ||
7698 | case IA64_RS_RR: /* eight registers */ | |
7699 | if (note == 6) | |
542d6675 KH |
7700 | { |
7701 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) | |
7702 | { | |
7703 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7704 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7705 | && KNOWN (regno)) | |
7706 | { | |
7707 | specs[count] = tmpl; | |
7708 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; | |
7709 | } | |
7710 | else | |
7711 | { | |
7712 | specs[count] = tmpl; | |
7713 | specs[count++].specific = 0; | |
7714 | } | |
7715 | } | |
7716 | } | |
800eeca4 | 7717 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7718 | { |
7719 | specs[count] = tmpl; | |
7720 | specs[count++].specific = 0; | |
7721 | } | |
197865e8 | 7722 | else |
542d6675 KH |
7723 | { |
7724 | UNHANDLED; | |
7725 | } | |
800eeca4 JW |
7726 | break; |
7727 | ||
7728 | case IA64_RS_CR_IRR: | |
197865e8 | 7729 | if (note == 0) |
542d6675 KH |
7730 | { |
7731 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ | |
7732 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; | |
7733 | if (rsrc_write | |
7734 | && idesc->operands[1] == IA64_OPND_CR3 | |
7735 | && regno == CR_IVR) | |
7736 | { | |
7737 | for (i = 0; i < 4; i++) | |
7738 | { | |
7739 | specs[count] = tmpl; | |
7740 | specs[count++].index = CR_IRR0 + i; | |
7741 | } | |
7742 | } | |
7743 | } | |
800eeca4 | 7744 | else if (note == 1) |
542d6675 KH |
7745 | { |
7746 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7747 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7748 | && regno >= CR_IRR0 | |
7749 | && regno <= CR_IRR3) | |
7750 | { | |
7751 | specs[count] = tmpl; | |
7752 | specs[count++].index = regno; | |
7753 | } | |
7754 | } | |
800eeca4 | 7755 | else |
542d6675 KH |
7756 | { |
7757 | UNHANDLED; | |
7758 | } | |
800eeca4 JW |
7759 | break; |
7760 | ||
7761 | case IA64_RS_CR_LRR: | |
7762 | if (note != 1) | |
542d6675 KH |
7763 | { |
7764 | UNHANDLED; | |
7765 | } | |
197865e8 | 7766 | else |
542d6675 KH |
7767 | { |
7768 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7769 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7770 | && (regno == CR_LRR0 || regno == CR_LRR1)) | |
7771 | { | |
7772 | specs[count] = tmpl; | |
7773 | specs[count++].index = regno; | |
7774 | } | |
7775 | } | |
800eeca4 JW |
7776 | break; |
7777 | ||
7778 | case IA64_RS_CR: | |
7779 | if (note == 1) | |
542d6675 KH |
7780 | { |
7781 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
7782 | { | |
7783 | specs[count] = tmpl; | |
7784 | specs[count++].index = | |
7785 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7786 | } | |
7787 | } | |
800eeca4 | 7788 | else |
542d6675 KH |
7789 | { |
7790 | UNHANDLED; | |
7791 | } | |
800eeca4 JW |
7792 | break; |
7793 | ||
7794 | case IA64_RS_FR: | |
7795 | case IA64_RS_FRb: | |
7796 | if (note != 1) | |
542d6675 KH |
7797 | { |
7798 | UNHANDLED; | |
7799 | } | |
800eeca4 | 7800 | else if (rsrc_write) |
542d6675 KH |
7801 | { |
7802 | if (dep->specifier == IA64_RS_FRb | |
7803 | && idesc->operands[0] == IA64_OPND_F1) | |
7804 | { | |
7805 | specs[count] = tmpl; | |
7806 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; | |
7807 | } | |
7808 | } | |
800eeca4 | 7809 | else |
542d6675 KH |
7810 | { |
7811 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) | |
7812 | { | |
7813 | if (idesc->operands[i] == IA64_OPND_F2 | |
7814 | || idesc->operands[i] == IA64_OPND_F3 | |
7815 | || idesc->operands[i] == IA64_OPND_F4) | |
7816 | { | |
7817 | specs[count] = tmpl; | |
7818 | specs[count++].index = | |
7819 | CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7820 | } | |
7821 | } | |
7822 | } | |
800eeca4 JW |
7823 | break; |
7824 | ||
7825 | case IA64_RS_GR: | |
7826 | if (note == 13) | |
542d6675 KH |
7827 | { |
7828 | /* This reference applies only to the GR whose value is loaded with | |
7829 | data returned from memory. */ | |
7830 | specs[count] = tmpl; | |
7831 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
7832 | } | |
800eeca4 | 7833 | else if (note == 1) |
542d6675 KH |
7834 | { |
7835 | if (rsrc_write) | |
7836 | { | |
7837 | for (i = 0; i < idesc->num_outputs; i++) | |
50b81f19 JW |
7838 | if (idesc->operands[i] == IA64_OPND_R1 |
7839 | || idesc->operands[i] == IA64_OPND_R2 | |
7840 | || idesc->operands[i] == IA64_OPND_R3) | |
7841 | { | |
7842 | specs[count] = tmpl; | |
197865e8 | 7843 | specs[count++].index = |
50b81f19 JW |
7844 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
7845 | } | |
7846 | if (idesc->flags & IA64_OPCODE_POSTINC) | |
7847 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7848 | if (idesc->operands[i] == IA64_OPND_MR3) | |
7849 | { | |
7850 | specs[count] = tmpl; | |
7851 | specs[count++].index = | |
7852 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7853 | } | |
542d6675 KH |
7854 | } |
7855 | else | |
7856 | { | |
7857 | /* Look for anything that reads a GR. */ | |
7858 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7859 | { | |
7860 | if (idesc->operands[i] == IA64_OPND_MR3 | |
7861 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
7862 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
7863 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
800eeca4 | 7864 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
542d6675 KH |
7865 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
7866 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
7867 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
7868 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
7869 | || ((i >= idesc->num_outputs) | |
7870 | && (idesc->operands[i] == IA64_OPND_R1 | |
7871 | || idesc->operands[i] == IA64_OPND_R2 | |
7872 | || idesc->operands[i] == IA64_OPND_R3 | |
50b81f19 JW |
7873 | /* addl source register. */ |
7874 | || idesc->operands[i] == IA64_OPND_R3_2))) | |
542d6675 KH |
7875 | { |
7876 | specs[count] = tmpl; | |
7877 | specs[count++].index = | |
7878 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7879 | } | |
7880 | } | |
7881 | } | |
7882 | } | |
197865e8 | 7883 | else |
542d6675 KH |
7884 | { |
7885 | UNHANDLED; | |
7886 | } | |
800eeca4 JW |
7887 | break; |
7888 | ||
139368c9 JW |
7889 | /* This is the same as IA64_RS_PRr, except that the register range is |
7890 | from 1 - 15, and there are no rotating register reads/writes here. */ | |
800eeca4 JW |
7891 | case IA64_RS_PR: |
7892 | if (note == 0) | |
542d6675 | 7893 | { |
139368c9 | 7894 | for (i = 1; i < 16; i++) |
542d6675 | 7895 | { |
139368c9 JW |
7896 | specs[count] = tmpl; |
7897 | specs[count++].index = i; | |
7898 | } | |
7899 | } | |
7900 | else if (note == 7) | |
7901 | { | |
7902 | valueT mask = 0; | |
7903 | /* Mark only those registers indicated by the mask. */ | |
7904 | if (rsrc_write) | |
7905 | { | |
7906 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7907 | for (i = 1; i < 16; i++) | |
7908 | if (mask & ((valueT) 1 << i)) | |
7909 | { | |
7910 | specs[count] = tmpl; | |
7911 | specs[count++].index = i; | |
7912 | } | |
7913 | } | |
7914 | else | |
7915 | { | |
7916 | UNHANDLED; | |
7917 | } | |
7918 | } | |
7919 | else if (note == 11) /* note 11 implies note 1 as well */ | |
7920 | { | |
7921 | if (rsrc_write) | |
7922 | { | |
7923 | for (i = 0; i < idesc->num_outputs; i++) | |
7924 | { | |
7925 | if (idesc->operands[i] == IA64_OPND_P1 | |
7926 | || idesc->operands[i] == IA64_OPND_P2) | |
7927 | { | |
7928 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
7929 | if (regno >= 1 && regno < 16) | |
7930 | { | |
7931 | specs[count] = tmpl; | |
7932 | specs[count++].index = regno; | |
7933 | } | |
7934 | } | |
7935 | } | |
7936 | } | |
7937 | else | |
7938 | { | |
7939 | UNHANDLED; | |
7940 | } | |
7941 | } | |
7942 | else if (note == 12) | |
7943 | { | |
7944 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) | |
7945 | { | |
7946 | specs[count] = tmpl; | |
7947 | specs[count++].index = CURR_SLOT.qp_regno; | |
7948 | } | |
7949 | } | |
7950 | else if (note == 1) | |
7951 | { | |
7952 | if (rsrc_write) | |
7953 | { | |
7954 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7955 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
07726851 KH |
7956 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
7957 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; | |
139368c9 JW |
7958 | |
7959 | if ((idesc->operands[0] == IA64_OPND_P1 | |
7960 | || idesc->operands[0] == IA64_OPND_P2) | |
7961 | && p1 >= 1 && p1 < 16) | |
542d6675 KH |
7962 | { |
7963 | specs[count] = tmpl; | |
139368c9 JW |
7964 | specs[count].cmp_type = |
7965 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); | |
7966 | specs[count++].index = p1; | |
7967 | } | |
7968 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7969 | || idesc->operands[1] == IA64_OPND_P2) | |
7970 | && p2 >= 1 && p2 < 16) | |
7971 | { | |
7972 | specs[count] = tmpl; | |
7973 | specs[count].cmp_type = | |
7974 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); | |
7975 | specs[count++].index = p2; | |
542d6675 KH |
7976 | } |
7977 | } | |
7978 | else | |
7979 | { | |
139368c9 | 7980 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
542d6675 KH |
7981 | { |
7982 | specs[count] = tmpl; | |
139368c9 JW |
7983 | specs[count++].index = CURR_SLOT.qp_regno; |
7984 | } | |
7985 | if (idesc->operands[1] == IA64_OPND_PR) | |
7986 | { | |
7987 | for (i = 1; i < 16; i++) | |
7988 | { | |
7989 | specs[count] = tmpl; | |
7990 | specs[count++].index = i; | |
7991 | } | |
542d6675 KH |
7992 | } |
7993 | } | |
7994 | } | |
139368c9 JW |
7995 | else |
7996 | { | |
7997 | UNHANDLED; | |
7998 | } | |
7999 | break; | |
8000 | ||
8001 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are | |
8002 | simplified cases of this. */ | |
8003 | case IA64_RS_PRr: | |
8004 | if (note == 0) | |
8005 | { | |
8006 | for (i = 16; i < 63; i++) | |
8007 | { | |
8008 | specs[count] = tmpl; | |
8009 | specs[count++].index = i; | |
8010 | } | |
8011 | } | |
800eeca4 | 8012 | else if (note == 7) |
542d6675 KH |
8013 | { |
8014 | valueT mask = 0; | |
8015 | /* Mark only those registers indicated by the mask. */ | |
8016 | if (rsrc_write | |
8017 | && idesc->operands[0] == IA64_OPND_PR) | |
8018 | { | |
8019 | mask = CURR_SLOT.opnd[2].X_add_number; | |
40449e9f | 8020 | if (mask & ((valueT) 1 << 16)) |
139368c9 JW |
8021 | for (i = 16; i < 63; i++) |
8022 | { | |
8023 | specs[count] = tmpl; | |
8024 | specs[count++].index = i; | |
8025 | } | |
542d6675 KH |
8026 | } |
8027 | else if (rsrc_write | |
8028 | && idesc->operands[0] == IA64_OPND_PR_ROT) | |
8029 | { | |
8030 | for (i = 16; i < 63; i++) | |
8031 | { | |
8032 | specs[count] = tmpl; | |
8033 | specs[count++].index = i; | |
8034 | } | |
8035 | } | |
8036 | else | |
8037 | { | |
8038 | UNHANDLED; | |
8039 | } | |
8040 | } | |
800eeca4 | 8041 | else if (note == 11) /* note 11 implies note 1 as well */ |
542d6675 KH |
8042 | { |
8043 | if (rsrc_write) | |
8044 | { | |
8045 | for (i = 0; i < idesc->num_outputs; i++) | |
8046 | { | |
8047 | if (idesc->operands[i] == IA64_OPND_P1 | |
8048 | || idesc->operands[i] == IA64_OPND_P2) | |
8049 | { | |
8050 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
139368c9 | 8051 | if (regno >= 16 && regno < 63) |
542d6675 KH |
8052 | { |
8053 | specs[count] = tmpl; | |
8054 | specs[count++].index = regno; | |
8055 | } | |
8056 | } | |
8057 | } | |
8058 | } | |
8059 | else | |
8060 | { | |
8061 | UNHANDLED; | |
8062 | } | |
8063 | } | |
800eeca4 | 8064 | else if (note == 12) |
542d6675 | 8065 | { |
139368c9 | 8066 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
8067 | { |
8068 | specs[count] = tmpl; | |
8069 | specs[count++].index = CURR_SLOT.qp_regno; | |
8070 | } | |
8071 | } | |
800eeca4 | 8072 | else if (note == 1) |
542d6675 KH |
8073 | { |
8074 | if (rsrc_write) | |
8075 | { | |
8076 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
8077 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
07726851 KH |
8078 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
8079 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; | |
7484b8e6 | 8080 | |
542d6675 KH |
8081 | if ((idesc->operands[0] == IA64_OPND_P1 |
8082 | || idesc->operands[0] == IA64_OPND_P2) | |
139368c9 | 8083 | && p1 >= 16 && p1 < 63) |
542d6675 KH |
8084 | { |
8085 | specs[count] = tmpl; | |
4a4f25cf | 8086 | specs[count].cmp_type = |
7484b8e6 | 8087 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
542d6675 KH |
8088 | specs[count++].index = p1; |
8089 | } | |
8090 | if ((idesc->operands[1] == IA64_OPND_P1 | |
8091 | || idesc->operands[1] == IA64_OPND_P2) | |
139368c9 | 8092 | && p2 >= 16 && p2 < 63) |
542d6675 KH |
8093 | { |
8094 | specs[count] = tmpl; | |
4a4f25cf | 8095 | specs[count].cmp_type = |
7484b8e6 | 8096 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
542d6675 KH |
8097 | specs[count++].index = p2; |
8098 | } | |
8099 | } | |
8100 | else | |
8101 | { | |
139368c9 | 8102 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
8103 | { |
8104 | specs[count] = tmpl; | |
8105 | specs[count++].index = CURR_SLOT.qp_regno; | |
8106 | } | |
8107 | if (idesc->operands[1] == IA64_OPND_PR) | |
8108 | { | |
139368c9 | 8109 | for (i = 16; i < 63; i++) |
542d6675 KH |
8110 | { |
8111 | specs[count] = tmpl; | |
8112 | specs[count++].index = i; | |
8113 | } | |
8114 | } | |
8115 | } | |
8116 | } | |
197865e8 | 8117 | else |
542d6675 KH |
8118 | { |
8119 | UNHANDLED; | |
8120 | } | |
800eeca4 JW |
8121 | break; |
8122 | ||
8123 | case IA64_RS_PSR: | |
197865e8 | 8124 | /* Verify that the instruction is using the PSR bit indicated in |
542d6675 | 8125 | dep->regindex. */ |
800eeca4 | 8126 | if (note == 0) |
542d6675 KH |
8127 | { |
8128 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) | |
8129 | { | |
8130 | if (dep->regindex < 6) | |
8131 | { | |
8132 | specs[count++] = tmpl; | |
8133 | } | |
8134 | } | |
8135 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) | |
8136 | { | |
8137 | if (dep->regindex < 32 | |
8138 | || dep->regindex == 35 | |
8139 | || dep->regindex == 36 | |
8140 | || (!rsrc_write && dep->regindex == PSR_CPL)) | |
8141 | { | |
8142 | specs[count++] = tmpl; | |
8143 | } | |
8144 | } | |
8145 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) | |
8146 | { | |
8147 | if (dep->regindex < 32 | |
8148 | || dep->regindex == 35 | |
8149 | || dep->regindex == 36 | |
8150 | || (rsrc_write && dep->regindex == PSR_CPL)) | |
8151 | { | |
8152 | specs[count++] = tmpl; | |
8153 | } | |
8154 | } | |
8155 | else | |
8156 | { | |
8157 | /* Several PSR bits have very specific dependencies. */ | |
8158 | switch (dep->regindex) | |
8159 | { | |
8160 | default: | |
8161 | specs[count++] = tmpl; | |
8162 | break; | |
8163 | case PSR_IC: | |
8164 | if (rsrc_write) | |
8165 | { | |
8166 | specs[count++] = tmpl; | |
8167 | } | |
8168 | else | |
8169 | { | |
8170 | /* Only certain CR accesses use PSR.ic */ | |
8171 | if (idesc->operands[0] == IA64_OPND_CR3 | |
8172 | || idesc->operands[1] == IA64_OPND_CR3) | |
8173 | { | |
8174 | int index = | |
8175 | ((idesc->operands[0] == IA64_OPND_CR3) | |
8176 | ? 0 : 1); | |
8177 | int regno = | |
8178 | CURR_SLOT.opnd[index].X_add_number - REG_CR; | |
8179 | ||
8180 | switch (regno) | |
8181 | { | |
8182 | default: | |
8183 | break; | |
8184 | case CR_ITIR: | |
8185 | case CR_IFS: | |
8186 | case CR_IIM: | |
8187 | case CR_IIP: | |
8188 | case CR_IPSR: | |
8189 | case CR_ISR: | |
8190 | case CR_IFA: | |
8191 | case CR_IHA: | |
8192 | case CR_IIPA: | |
8193 | specs[count++] = tmpl; | |
8194 | break; | |
8195 | } | |
8196 | } | |
8197 | } | |
8198 | break; | |
8199 | case PSR_CPL: | |
8200 | if (rsrc_write) | |
8201 | { | |
8202 | specs[count++] = tmpl; | |
8203 | } | |
8204 | else | |
8205 | { | |
8206 | /* Only some AR accesses use cpl */ | |
8207 | if (idesc->operands[0] == IA64_OPND_AR3 | |
8208 | || idesc->operands[1] == IA64_OPND_AR3) | |
8209 | { | |
8210 | int index = | |
8211 | ((idesc->operands[0] == IA64_OPND_AR3) | |
8212 | ? 0 : 1); | |
8213 | int regno = | |
8214 | CURR_SLOT.opnd[index].X_add_number - REG_AR; | |
8215 | ||
8216 | if (regno == AR_ITC | |
8217 | || (index == 0 | |
8218 | && (regno == AR_ITC | |
8219 | || regno == AR_RSC | |
8220 | || (regno >= AR_K0 | |
8221 | && regno <= AR_K7)))) | |
8222 | { | |
8223 | specs[count++] = tmpl; | |
8224 | } | |
8225 | } | |
8226 | else | |
8227 | { | |
8228 | specs[count++] = tmpl; | |
8229 | } | |
8230 | break; | |
8231 | } | |
8232 | } | |
8233 | } | |
8234 | } | |
800eeca4 | 8235 | else if (note == 7) |
542d6675 KH |
8236 | { |
8237 | valueT mask = 0; | |
8238 | if (idesc->operands[0] == IA64_OPND_IMMU24) | |
8239 | { | |
8240 | mask = CURR_SLOT.opnd[0].X_add_number; | |
8241 | } | |
8242 | else | |
8243 | { | |
8244 | UNHANDLED; | |
8245 | } | |
8246 | if (mask & ((valueT) 1 << dep->regindex)) | |
8247 | { | |
8248 | specs[count++] = tmpl; | |
8249 | } | |
8250 | } | |
800eeca4 | 8251 | else if (note == 8) |
542d6675 KH |
8252 | { |
8253 | int min = dep->regindex == PSR_DFL ? 2 : 32; | |
8254 | int max = dep->regindex == PSR_DFL ? 31 : 127; | |
8255 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ | |
8256 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8257 | { | |
8258 | if (idesc->operands[i] == IA64_OPND_F1 | |
8259 | || idesc->operands[i] == IA64_OPND_F2 | |
8260 | || idesc->operands[i] == IA64_OPND_F3 | |
8261 | || idesc->operands[i] == IA64_OPND_F4) | |
8262 | { | |
8263 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8264 | if (reg >= min && reg <= max) | |
8265 | { | |
8266 | specs[count++] = tmpl; | |
8267 | } | |
8268 | } | |
8269 | } | |
8270 | } | |
800eeca4 | 8271 | else if (note == 9) |
542d6675 KH |
8272 | { |
8273 | int min = dep->regindex == PSR_MFL ? 2 : 32; | |
8274 | int max = dep->regindex == PSR_MFL ? 31 : 127; | |
8275 | /* mfh is read on writes to FR32-127; mfl is read on writes to | |
8276 | FR2-31 */ | |
8277 | for (i = 0; i < idesc->num_outputs; i++) | |
8278 | { | |
8279 | if (idesc->operands[i] == IA64_OPND_F1) | |
8280 | { | |
8281 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8282 | if (reg >= min && reg <= max) | |
8283 | { | |
8284 | specs[count++] = tmpl; | |
8285 | } | |
8286 | } | |
8287 | } | |
8288 | } | |
800eeca4 | 8289 | else if (note == 10) |
542d6675 KH |
8290 | { |
8291 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8292 | { | |
8293 | if (idesc->operands[i] == IA64_OPND_R1 | |
8294 | || idesc->operands[i] == IA64_OPND_R2 | |
8295 | || idesc->operands[i] == IA64_OPND_R3) | |
8296 | { | |
8297 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8298 | if (regno >= 16 && regno <= 31) | |
8299 | { | |
8300 | specs[count++] = tmpl; | |
8301 | } | |
8302 | } | |
8303 | } | |
8304 | } | |
800eeca4 | 8305 | else |
542d6675 KH |
8306 | { |
8307 | UNHANDLED; | |
8308 | } | |
800eeca4 JW |
8309 | break; |
8310 | ||
8311 | case IA64_RS_AR_FPSR: | |
8312 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
542d6675 KH |
8313 | { |
8314 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
8315 | if (regno == AR_FPSR) | |
8316 | { | |
8317 | specs[count++] = tmpl; | |
8318 | } | |
8319 | } | |
800eeca4 | 8320 | else |
542d6675 KH |
8321 | { |
8322 | specs[count++] = tmpl; | |
8323 | } | |
800eeca4 JW |
8324 | break; |
8325 | ||
197865e8 | 8326 | case IA64_RS_ARX: |
800eeca4 JW |
8327 | /* Handle all AR[REG] resources */ |
8328 | if (note == 0 || note == 1) | |
542d6675 KH |
8329 | { |
8330 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
8331 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 | |
8332 | && regno == dep->regindex) | |
8333 | { | |
8334 | specs[count++] = tmpl; | |
8335 | } | |
8336 | /* other AR[REG] resources may be affected by AR accesses */ | |
8337 | else if (idesc->operands[0] == IA64_OPND_AR3) | |
8338 | { | |
8339 | /* AR[] writes */ | |
8340 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; | |
8341 | switch (dep->regindex) | |
8342 | { | |
8343 | default: | |
8344 | break; | |
8345 | case AR_BSP: | |
8346 | case AR_RNAT: | |
8347 | if (regno == AR_BSPSTORE) | |
8348 | { | |
8349 | specs[count++] = tmpl; | |
8350 | } | |
8351 | case AR_RSC: | |
8352 | if (!rsrc_write && | |
8353 | (regno == AR_BSPSTORE | |
8354 | || regno == AR_RNAT)) | |
8355 | { | |
8356 | specs[count++] = tmpl; | |
8357 | } | |
8358 | break; | |
8359 | } | |
8360 | } | |
8361 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
8362 | { | |
8363 | /* AR[] reads */ | |
8364 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; | |
8365 | switch (dep->regindex) | |
8366 | { | |
8367 | default: | |
8368 | break; | |
8369 | case AR_RSC: | |
8370 | if (regno == AR_BSPSTORE || regno == AR_RNAT) | |
8371 | { | |
8372 | specs[count++] = tmpl; | |
8373 | } | |
8374 | break; | |
8375 | } | |
8376 | } | |
8377 | else | |
8378 | { | |
8379 | specs[count++] = tmpl; | |
8380 | } | |
8381 | } | |
800eeca4 | 8382 | else |
542d6675 KH |
8383 | { |
8384 | UNHANDLED; | |
8385 | } | |
800eeca4 JW |
8386 | break; |
8387 | ||
8388 | case IA64_RS_CRX: | |
8389 | /* Handle all CR[REG] resources */ | |
8390 | if (note == 0 || note == 1) | |
542d6675 KH |
8391 | { |
8392 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
8393 | { | |
8394 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
8395 | if (regno == dep->regindex) | |
8396 | { | |
8397 | specs[count++] = tmpl; | |
8398 | } | |
8399 | else if (!rsrc_write) | |
8400 | { | |
8401 | /* Reads from CR[IVR] affect other resources. */ | |
8402 | if (regno == CR_IVR) | |
8403 | { | |
8404 | if ((dep->regindex >= CR_IRR0 | |
8405 | && dep->regindex <= CR_IRR3) | |
8406 | || dep->regindex == CR_TPR) | |
8407 | { | |
8408 | specs[count++] = tmpl; | |
8409 | } | |
8410 | } | |
8411 | } | |
8412 | } | |
8413 | else | |
8414 | { | |
8415 | specs[count++] = tmpl; | |
8416 | } | |
8417 | } | |
800eeca4 | 8418 | else |
542d6675 KH |
8419 | { |
8420 | UNHANDLED; | |
8421 | } | |
800eeca4 JW |
8422 | break; |
8423 | ||
8424 | case IA64_RS_INSERVICE: | |
8425 | /* look for write of EOI (67) or read of IVR (65) */ | |
8426 | if ((idesc->operands[0] == IA64_OPND_CR3 | |
542d6675 KH |
8427 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
8428 | || (idesc->operands[1] == IA64_OPND_CR3 | |
8429 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) | |
8430 | { | |
8431 | specs[count++] = tmpl; | |
8432 | } | |
800eeca4 JW |
8433 | break; |
8434 | ||
8435 | case IA64_RS_GR0: | |
8436 | if (note == 1) | |
542d6675 KH |
8437 | { |
8438 | specs[count++] = tmpl; | |
8439 | } | |
800eeca4 | 8440 | else |
542d6675 KH |
8441 | { |
8442 | UNHANDLED; | |
8443 | } | |
800eeca4 JW |
8444 | break; |
8445 | ||
8446 | case IA64_RS_CFM: | |
8447 | if (note != 2) | |
542d6675 KH |
8448 | { |
8449 | specs[count++] = tmpl; | |
8450 | } | |
800eeca4 | 8451 | else |
542d6675 KH |
8452 | { |
8453 | /* Check if any of the registers accessed are in the rotating region. | |
8454 | mov to/from pr accesses CFM only when qp_regno is in the rotating | |
8455 | region */ | |
8456 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8457 | { | |
8458 | if (idesc->operands[i] == IA64_OPND_R1 | |
8459 | || idesc->operands[i] == IA64_OPND_R2 | |
8460 | || idesc->operands[i] == IA64_OPND_R3) | |
8461 | { | |
8462 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8463 | /* Assumes that md.rot.num_regs is always valid */ | |
8464 | if (md.rot.num_regs > 0 | |
8465 | && num > 31 | |
8466 | && num < 31 + md.rot.num_regs) | |
8467 | { | |
8468 | specs[count] = tmpl; | |
8469 | specs[count++].specific = 0; | |
8470 | } | |
8471 | } | |
8472 | else if (idesc->operands[i] == IA64_OPND_F1 | |
8473 | || idesc->operands[i] == IA64_OPND_F2 | |
8474 | || idesc->operands[i] == IA64_OPND_F3 | |
8475 | || idesc->operands[i] == IA64_OPND_F4) | |
8476 | { | |
8477 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8478 | if (num > 31) | |
8479 | { | |
8480 | specs[count] = tmpl; | |
8481 | specs[count++].specific = 0; | |
8482 | } | |
8483 | } | |
8484 | else if (idesc->operands[i] == IA64_OPND_P1 | |
8485 | || idesc->operands[i] == IA64_OPND_P2) | |
8486 | { | |
8487 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8488 | if (num > 15) | |
8489 | { | |
8490 | specs[count] = tmpl; | |
8491 | specs[count++].specific = 0; | |
8492 | } | |
8493 | } | |
8494 | } | |
8495 | if (CURR_SLOT.qp_regno > 15) | |
8496 | { | |
8497 | specs[count] = tmpl; | |
8498 | specs[count++].specific = 0; | |
8499 | } | |
8500 | } | |
800eeca4 JW |
8501 | break; |
8502 | ||
139368c9 JW |
8503 | /* This is the same as IA64_RS_PRr, except simplified to account for |
8504 | the fact that there is only one register. */ | |
800eeca4 JW |
8505 | case IA64_RS_PR63: |
8506 | if (note == 0) | |
542d6675 KH |
8507 | { |
8508 | specs[count++] = tmpl; | |
8509 | } | |
139368c9 | 8510 | else if (note == 7) |
40449e9f KH |
8511 | { |
8512 | valueT mask = 0; | |
8513 | if (idesc->operands[2] == IA64_OPND_IMM17) | |
8514 | mask = CURR_SLOT.opnd[2].X_add_number; | |
8515 | if (mask & ((valueT) 1 << 63)) | |
139368c9 | 8516 | specs[count++] = tmpl; |
40449e9f | 8517 | } |
800eeca4 | 8518 | else if (note == 11) |
542d6675 KH |
8519 | { |
8520 | if ((idesc->operands[0] == IA64_OPND_P1 | |
8521 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) | |
8522 | || (idesc->operands[1] == IA64_OPND_P2 | |
8523 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) | |
8524 | { | |
8525 | specs[count++] = tmpl; | |
8526 | } | |
8527 | } | |
800eeca4 | 8528 | else if (note == 12) |
542d6675 KH |
8529 | { |
8530 | if (CURR_SLOT.qp_regno == 63) | |
8531 | { | |
8532 | specs[count++] = tmpl; | |
8533 | } | |
8534 | } | |
800eeca4 | 8535 | else if (note == 1) |
542d6675 KH |
8536 | { |
8537 | if (rsrc_write) | |
8538 | { | |
40449e9f KH |
8539 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
8540 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
07726851 KH |
8541 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
8542 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; | |
7484b8e6 | 8543 | |
4a4f25cf | 8544 | if (p1 == 63 |
7484b8e6 TW |
8545 | && (idesc->operands[0] == IA64_OPND_P1 |
8546 | || idesc->operands[0] == IA64_OPND_P2)) | |
8547 | { | |
40449e9f | 8548 | specs[count] = tmpl; |
4a4f25cf | 8549 | specs[count++].cmp_type = |
7484b8e6 TW |
8550 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
8551 | } | |
8552 | if (p2 == 63 | |
8553 | && (idesc->operands[1] == IA64_OPND_P1 | |
8554 | || idesc->operands[1] == IA64_OPND_P2)) | |
8555 | { | |
40449e9f | 8556 | specs[count] = tmpl; |
4a4f25cf | 8557 | specs[count++].cmp_type = |
7484b8e6 TW |
8558 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
8559 | } | |
542d6675 KH |
8560 | } |
8561 | else | |
8562 | { | |
8563 | if (CURR_SLOT.qp_regno == 63) | |
8564 | { | |
8565 | specs[count++] = tmpl; | |
8566 | } | |
8567 | } | |
8568 | } | |
800eeca4 | 8569 | else |
542d6675 KH |
8570 | { |
8571 | UNHANDLED; | |
8572 | } | |
800eeca4 JW |
8573 | break; |
8574 | ||
8575 | case IA64_RS_RSE: | |
8576 | /* FIXME we can identify some individual RSE written resources, but RSE | |
542d6675 KH |
8577 | read resources have not yet been completely identified, so for now |
8578 | treat RSE as a single resource */ | |
800eeca4 | 8579 | if (strncmp (idesc->name, "mov", 3) == 0) |
542d6675 KH |
8580 | { |
8581 | if (rsrc_write) | |
8582 | { | |
8583 | if (idesc->operands[0] == IA64_OPND_AR3 | |
8584 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) | |
8585 | { | |
8586 | specs[count] = tmpl; | |
8587 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ | |
8588 | } | |
8589 | } | |
8590 | else | |
8591 | { | |
8592 | if (idesc->operands[0] == IA64_OPND_AR3) | |
8593 | { | |
8594 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE | |
8595 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) | |
8596 | { | |
8597 | specs[count++] = tmpl; | |
8598 | } | |
8599 | } | |
8600 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
8601 | { | |
8602 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP | |
8603 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE | |
8604 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) | |
8605 | { | |
8606 | specs[count++] = tmpl; | |
8607 | } | |
8608 | } | |
8609 | } | |
8610 | } | |
197865e8 | 8611 | else |
542d6675 KH |
8612 | { |
8613 | specs[count++] = tmpl; | |
8614 | } | |
800eeca4 JW |
8615 | break; |
8616 | ||
8617 | case IA64_RS_ANY: | |
8618 | /* FIXME -- do any of these need to be non-specific? */ | |
8619 | specs[count++] = tmpl; | |
8620 | break; | |
8621 | ||
8622 | default: | |
8623 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); | |
8624 | break; | |
8625 | } | |
8626 | ||
8627 | return count; | |
8628 | } | |
8629 | ||
8630 | /* Clear branch flags on marked resources. This breaks the link between the | |
542d6675 KH |
8631 | QP of the marking instruction and a subsequent branch on the same QP. */ |
8632 | ||
800eeca4 JW |
8633 | static void |
8634 | clear_qp_branch_flag (mask) | |
542d6675 | 8635 | valueT mask; |
800eeca4 JW |
8636 | { |
8637 | int i; | |
542d6675 | 8638 | for (i = 0; i < regdepslen; i++) |
800eeca4 | 8639 | { |
197865e8 | 8640 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
800eeca4 | 8641 | if ((bit & mask) != 0) |
542d6675 KH |
8642 | { |
8643 | regdeps[i].link_to_qp_branch = 0; | |
8644 | } | |
800eeca4 JW |
8645 | } |
8646 | } | |
8647 | ||
197865e8 | 8648 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
800eeca4 | 8649 | |
542d6675 KH |
8650 | Any changes to a PR clears the mutex relations which include that PR. */ |
8651 | ||
800eeca4 JW |
8652 | static void |
8653 | clear_qp_mutex (mask) | |
542d6675 | 8654 | valueT mask; |
800eeca4 JW |
8655 | { |
8656 | int i; | |
8657 | ||
8658 | i = 0; | |
8659 | while (i < qp_mutexeslen) | |
8660 | { | |
8661 | if ((qp_mutexes[i].prmask & mask) != 0) | |
542d6675 KH |
8662 | { |
8663 | if (md.debug_dv) | |
8664 | { | |
8665 | fprintf (stderr, " Clearing mutex relation"); | |
8666 | print_prmask (qp_mutexes[i].prmask); | |
8667 | fprintf (stderr, "\n"); | |
8668 | } | |
8669 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; | |
8670 | } | |
800eeca4 | 8671 | else |
542d6675 | 8672 | ++i; |
800eeca4 JW |
8673 | } |
8674 | } | |
8675 | ||
8676 | /* Clear implies relations which contain PRs in the given masks. | |
8677 | P1_MASK indicates the source of the implies relation, while P2_MASK | |
542d6675 KH |
8678 | indicates the implied PR. */ |
8679 | ||
800eeca4 JW |
8680 | static void |
8681 | clear_qp_implies (p1_mask, p2_mask) | |
542d6675 KH |
8682 | valueT p1_mask; |
8683 | valueT p2_mask; | |
800eeca4 JW |
8684 | { |
8685 | int i; | |
8686 | ||
8687 | i = 0; | |
8688 | while (i < qp_implieslen) | |
8689 | { | |
197865e8 | 8690 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
542d6675 KH |
8691 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
8692 | { | |
8693 | if (md.debug_dv) | |
8694 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", | |
8695 | qp_implies[i].p1, qp_implies[i].p2); | |
8696 | qp_implies[i] = qp_implies[--qp_implieslen]; | |
8697 | } | |
197865e8 | 8698 | else |
542d6675 | 8699 | ++i; |
800eeca4 JW |
8700 | } |
8701 | } | |
8702 | ||
542d6675 KH |
8703 | /* Add the PRs specified to the list of implied relations. */ |
8704 | ||
800eeca4 JW |
8705 | static void |
8706 | add_qp_imply (p1, p2) | |
542d6675 | 8707 | int p1, p2; |
800eeca4 JW |
8708 | { |
8709 | valueT mask; | |
8710 | valueT bit; | |
8711 | int i; | |
8712 | ||
542d6675 | 8713 | /* p0 is not meaningful here. */ |
800eeca4 JW |
8714 | if (p1 == 0 || p2 == 0) |
8715 | abort (); | |
8716 | ||
8717 | if (p1 == p2) | |
8718 | return; | |
8719 | ||
542d6675 KH |
8720 | /* If it exists already, ignore it. */ |
8721 | for (i = 0; i < qp_implieslen; i++) | |
800eeca4 | 8722 | { |
197865e8 | 8723 | if (qp_implies[i].p1 == p1 |
542d6675 KH |
8724 | && qp_implies[i].p2 == p2 |
8725 | && qp_implies[i].path == md.path | |
8726 | && !qp_implies[i].p2_branched) | |
8727 | return; | |
800eeca4 JW |
8728 | } |
8729 | ||
8730 | if (qp_implieslen == qp_impliestotlen) | |
8731 | { | |
8732 | qp_impliestotlen += 20; | |
8733 | qp_implies = (struct qp_imply *) | |
542d6675 KH |
8734 | xrealloc ((void *) qp_implies, |
8735 | qp_impliestotlen * sizeof (struct qp_imply)); | |
800eeca4 JW |
8736 | } |
8737 | if (md.debug_dv) | |
8738 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); | |
8739 | qp_implies[qp_implieslen].p1 = p1; | |
8740 | qp_implies[qp_implieslen].p2 = p2; | |
8741 | qp_implies[qp_implieslen].path = md.path; | |
8742 | qp_implies[qp_implieslen++].p2_branched = 0; | |
8743 | ||
8744 | /* Add in the implied transitive relations; for everything that p2 implies, | |
8745 | make p1 imply that, too; for everything that implies p1, make it imply p2 | |
197865e8 | 8746 | as well. */ |
542d6675 | 8747 | for (i = 0; i < qp_implieslen; i++) |
800eeca4 JW |
8748 | { |
8749 | if (qp_implies[i].p1 == p2) | |
542d6675 | 8750 | add_qp_imply (p1, qp_implies[i].p2); |
800eeca4 | 8751 | if (qp_implies[i].p2 == p1) |
542d6675 | 8752 | add_qp_imply (qp_implies[i].p1, p2); |
800eeca4 JW |
8753 | } |
8754 | /* Add in mutex relations implied by this implies relation; for each mutex | |
197865e8 KH |
8755 | relation containing p2, duplicate it and replace p2 with p1. */ |
8756 | bit = (valueT) 1 << p1; | |
8757 | mask = (valueT) 1 << p2; | |
542d6675 | 8758 | for (i = 0; i < qp_mutexeslen; i++) |
800eeca4 JW |
8759 | { |
8760 | if (qp_mutexes[i].prmask & mask) | |
542d6675 | 8761 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
800eeca4 JW |
8762 | } |
8763 | } | |
8764 | ||
800eeca4 JW |
8765 | /* Add the PRs specified in the mask to the mutex list; this means that only |
8766 | one of the PRs can be true at any time. PR0 should never be included in | |
8767 | the mask. */ | |
542d6675 | 8768 | |
800eeca4 JW |
8769 | static void |
8770 | add_qp_mutex (mask) | |
542d6675 | 8771 | valueT mask; |
800eeca4 JW |
8772 | { |
8773 | if (mask & 0x1) | |
8774 | abort (); | |
8775 | ||
8776 | if (qp_mutexeslen == qp_mutexestotlen) | |
8777 | { | |
8778 | qp_mutexestotlen += 20; | |
8779 | qp_mutexes = (struct qpmutex *) | |
542d6675 KH |
8780 | xrealloc ((void *) qp_mutexes, |
8781 | qp_mutexestotlen * sizeof (struct qpmutex)); | |
800eeca4 JW |
8782 | } |
8783 | if (md.debug_dv) | |
8784 | { | |
8785 | fprintf (stderr, " Registering mutex on"); | |
8786 | print_prmask (mask); | |
8787 | fprintf (stderr, "\n"); | |
8788 | } | |
8789 | qp_mutexes[qp_mutexeslen].path = md.path; | |
8790 | qp_mutexes[qp_mutexeslen++].prmask = mask; | |
8791 | } | |
8792 | ||
cb5301b6 RH |
8793 | static int |
8794 | has_suffix_p (name, suffix) | |
40449e9f KH |
8795 | const char *name; |
8796 | const char *suffix; | |
cb5301b6 RH |
8797 | { |
8798 | size_t namelen = strlen (name); | |
8799 | size_t sufflen = strlen (suffix); | |
8800 | ||
8801 | if (namelen <= sufflen) | |
8802 | return 0; | |
8803 | return strcmp (name + namelen - sufflen, suffix) == 0; | |
8804 | } | |
8805 | ||
800eeca4 JW |
8806 | static void |
8807 | clear_register_values () | |
8808 | { | |
8809 | int i; | |
8810 | if (md.debug_dv) | |
8811 | fprintf (stderr, " Clearing register values\n"); | |
542d6675 | 8812 | for (i = 1; i < NELEMS (gr_values); i++) |
800eeca4 JW |
8813 | gr_values[i].known = 0; |
8814 | } | |
8815 | ||
8816 | /* Keep track of register values/changes which affect DV tracking. | |
8817 | ||
8818 | optimization note: should add a flag to classes of insns where otherwise we | |
542d6675 | 8819 | have to examine a group of strings to identify them. */ |
800eeca4 | 8820 | |
800eeca4 JW |
8821 | static void |
8822 | note_register_values (idesc) | |
542d6675 | 8823 | struct ia64_opcode *idesc; |
800eeca4 JW |
8824 | { |
8825 | valueT qp_changemask = 0; | |
8826 | int i; | |
8827 | ||
542d6675 KH |
8828 | /* Invalidate values for registers being written to. */ |
8829 | for (i = 0; i < idesc->num_outputs; i++) | |
800eeca4 | 8830 | { |
197865e8 | 8831 | if (idesc->operands[i] == IA64_OPND_R1 |
542d6675 KH |
8832 | || idesc->operands[i] == IA64_OPND_R2 |
8833 | || idesc->operands[i] == IA64_OPND_R3) | |
8834 | { | |
8835 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8836 | if (regno > 0 && regno < NELEMS (gr_values)) | |
8837 | gr_values[regno].known = 0; | |
8838 | } | |
50b81f19 JW |
8839 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
8840 | { | |
8841 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8842 | if (regno > 0 && regno < 4) | |
8843 | gr_values[regno].known = 0; | |
8844 | } | |
197865e8 | 8845 | else if (idesc->operands[i] == IA64_OPND_P1 |
542d6675 KH |
8846 | || idesc->operands[i] == IA64_OPND_P2) |
8847 | { | |
8848 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8849 | qp_changemask |= (valueT) 1 << regno; | |
8850 | } | |
800eeca4 | 8851 | else if (idesc->operands[i] == IA64_OPND_PR) |
542d6675 KH |
8852 | { |
8853 | if (idesc->operands[2] & (valueT) 0x10000) | |
8854 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; | |
8855 | else | |
8856 | qp_changemask = idesc->operands[2]; | |
8857 | break; | |
8858 | } | |
800eeca4 | 8859 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
542d6675 KH |
8860 | { |
8861 | if (idesc->operands[1] & ((valueT) 1 << 43)) | |
8862 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; | |
8863 | else | |
8864 | qp_changemask = idesc->operands[1]; | |
8865 | qp_changemask &= ~(valueT) 0xFFFF; | |
8866 | break; | |
8867 | } | |
8868 | } | |
8869 | ||
8870 | /* Always clear qp branch flags on any PR change. */ | |
8871 | /* FIXME there may be exceptions for certain compares. */ | |
800eeca4 JW |
8872 | clear_qp_branch_flag (qp_changemask); |
8873 | ||
542d6675 | 8874 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
800eeca4 JW |
8875 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
8876 | { | |
197865e8 | 8877 | qp_changemask |= ~(valueT) 0xFFFF; |
800eeca4 | 8878 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
542d6675 KH |
8879 | { |
8880 | for (i = 32; i < 32 + md.rot.num_regs; i++) | |
8881 | gr_values[i].known = 0; | |
8882 | } | |
800eeca4 JW |
8883 | clear_qp_mutex (qp_changemask); |
8884 | clear_qp_implies (qp_changemask, qp_changemask); | |
8885 | } | |
542d6675 KH |
8886 | /* After a call, all register values are undefined, except those marked |
8887 | as "safe". */ | |
800eeca4 | 8888 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
542d6675 | 8889 | || strncmp (idesc->name, "brl.call", 7) == 0) |
800eeca4 | 8890 | { |
56d27c17 | 8891 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
800eeca4 JW |
8892 | clear_register_values (); |
8893 | clear_qp_mutex (~qp_safe_across_calls); | |
8894 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); | |
8895 | clear_qp_branch_flag (~qp_safe_across_calls); | |
8896 | } | |
e9718fe1 | 8897 | else if (is_interruption_or_rfi (idesc) |
542d6675 | 8898 | || is_taken_branch (idesc)) |
e9718fe1 TW |
8899 | { |
8900 | clear_register_values (); | |
197865e8 KH |
8901 | clear_qp_mutex (~(valueT) 0); |
8902 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); | |
e9718fe1 | 8903 | } |
542d6675 | 8904 | /* Look for mutex and implies relations. */ |
197865e8 | 8905 | else if ((idesc->operands[0] == IA64_OPND_P1 |
542d6675 KH |
8906 | || idesc->operands[0] == IA64_OPND_P2) |
8907 | && (idesc->operands[1] == IA64_OPND_P1 | |
8908 | || idesc->operands[1] == IA64_OPND_P2)) | |
800eeca4 JW |
8909 | { |
8910 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
197865e8 KH |
8911 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
8912 | valueT p1mask = (valueT) 1 << p1; | |
8913 | valueT p2mask = (valueT) 1 << p2; | |
800eeca4 | 8914 | |
542d6675 | 8915 | /* If one of the PRs is PR0, we can't really do anything. */ |
800eeca4 | 8916 | if (p1 == 0 || p2 == 0) |
542d6675 KH |
8917 | { |
8918 | if (md.debug_dv) | |
8919 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); | |
8920 | } | |
800eeca4 | 8921 | /* In general, clear mutexes and implies which include P1 or P2, |
542d6675 | 8922 | with the following exceptions. */ |
cb5301b6 RH |
8923 | else if (has_suffix_p (idesc->name, ".or.andcm") |
8924 | || has_suffix_p (idesc->name, ".and.orcm")) | |
542d6675 KH |
8925 | { |
8926 | add_qp_mutex (p1mask | p2mask); | |
8927 | clear_qp_implies (p2mask, p1mask); | |
8928 | } | |
cb5301b6 RH |
8929 | else if (has_suffix_p (idesc->name, ".andcm") |
8930 | || has_suffix_p (idesc->name, ".and")) | |
542d6675 KH |
8931 | { |
8932 | clear_qp_implies (0, p1mask | p2mask); | |
8933 | } | |
cb5301b6 RH |
8934 | else if (has_suffix_p (idesc->name, ".orcm") |
8935 | || has_suffix_p (idesc->name, ".or")) | |
542d6675 KH |
8936 | { |
8937 | clear_qp_mutex (p1mask | p2mask); | |
8938 | clear_qp_implies (p1mask | p2mask, 0); | |
8939 | } | |
800eeca4 | 8940 | else |
542d6675 KH |
8941 | { |
8942 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); | |
cb5301b6 | 8943 | if (has_suffix_p (idesc->name, ".unc")) |
542d6675 KH |
8944 | { |
8945 | add_qp_mutex (p1mask | p2mask); | |
8946 | if (CURR_SLOT.qp_regno != 0) | |
8947 | { | |
8948 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, | |
8949 | CURR_SLOT.qp_regno); | |
8950 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, | |
8951 | CURR_SLOT.qp_regno); | |
8952 | } | |
8953 | } | |
8954 | else if (CURR_SLOT.qp_regno == 0) | |
8955 | { | |
8956 | add_qp_mutex (p1mask | p2mask); | |
8957 | } | |
8958 | else | |
8959 | { | |
8960 | clear_qp_mutex (p1mask | p2mask); | |
8961 | } | |
8962 | } | |
8963 | } | |
8964 | /* Look for mov imm insns into GRs. */ | |
800eeca4 | 8965 | else if (idesc->operands[0] == IA64_OPND_R1 |
542d6675 KH |
8966 | && (idesc->operands[1] == IA64_OPND_IMM22 |
8967 | || idesc->operands[1] == IA64_OPND_IMMU64) | |
8968 | && (strcmp (idesc->name, "mov") == 0 | |
8969 | || strcmp (idesc->name, "movl") == 0)) | |
800eeca4 JW |
8970 | { |
8971 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
542d6675 KH |
8972 | if (regno > 0 && regno < NELEMS (gr_values)) |
8973 | { | |
8974 | gr_values[regno].known = 1; | |
8975 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; | |
8976 | gr_values[regno].path = md.path; | |
8977 | if (md.debug_dv) | |
2434f565 JW |
8978 | { |
8979 | fprintf (stderr, " Know gr%d = ", regno); | |
8980 | fprintf_vma (stderr, gr_values[regno].value); | |
8981 | fputs ("\n", stderr); | |
8982 | } | |
542d6675 | 8983 | } |
800eeca4 | 8984 | } |
197865e8 | 8985 | else |
800eeca4 JW |
8986 | { |
8987 | clear_qp_mutex (qp_changemask); | |
8988 | clear_qp_implies (qp_changemask, qp_changemask); | |
8989 | } | |
8990 | } | |
8991 | ||
542d6675 KH |
8992 | /* Return whether the given predicate registers are currently mutex. */ |
8993 | ||
800eeca4 JW |
8994 | static int |
8995 | qp_mutex (p1, p2, path) | |
542d6675 KH |
8996 | int p1; |
8997 | int p2; | |
8998 | int path; | |
800eeca4 JW |
8999 | { |
9000 | int i; | |
9001 | valueT mask; | |
9002 | ||
9003 | if (p1 != p2) | |
9004 | { | |
542d6675 KH |
9005 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
9006 | for (i = 0; i < qp_mutexeslen; i++) | |
9007 | { | |
9008 | if (qp_mutexes[i].path >= path | |
9009 | && (qp_mutexes[i].prmask & mask) == mask) | |
9010 | return 1; | |
9011 | } | |
800eeca4 JW |
9012 | } |
9013 | return 0; | |
9014 | } | |
9015 | ||
9016 | /* Return whether the given resource is in the given insn's list of chks | |
9017 | Return 1 if the conflict is absolutely determined, 2 if it's a potential | |
542d6675 KH |
9018 | conflict. */ |
9019 | ||
800eeca4 JW |
9020 | static int |
9021 | resources_match (rs, idesc, note, qp_regno, path) | |
542d6675 KH |
9022 | struct rsrc *rs; |
9023 | struct ia64_opcode *idesc; | |
9024 | int note; | |
9025 | int qp_regno; | |
9026 | int path; | |
800eeca4 JW |
9027 | { |
9028 | struct rsrc specs[MAX_SPECS]; | |
9029 | int count; | |
9030 | ||
9031 | /* If the marked resource's qp_regno and the given qp_regno are mutex, | |
9032 | we don't need to check. One exception is note 11, which indicates that | |
9033 | target predicates are written regardless of PR[qp]. */ | |
197865e8 | 9034 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
800eeca4 JW |
9035 | && note != 11) |
9036 | return 0; | |
9037 | ||
9038 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); | |
9039 | while (count-- > 0) | |
9040 | { | |
9041 | /* UNAT checking is a bit more specific than other resources */ | |
9042 | if (rs->dependency->specifier == IA64_RS_AR_UNAT | |
542d6675 KH |
9043 | && specs[count].mem_offset.hint |
9044 | && rs->mem_offset.hint) | |
9045 | { | |
9046 | if (rs->mem_offset.base == specs[count].mem_offset.base) | |
9047 | { | |
9048 | if (((rs->mem_offset.offset >> 3) & 0x3F) == | |
9049 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) | |
9050 | return 1; | |
9051 | else | |
9052 | continue; | |
9053 | } | |
9054 | } | |
800eeca4 | 9055 | |
7484b8e6 | 9056 | /* Skip apparent PR write conflicts where both writes are an AND or both |
4a4f25cf | 9057 | writes are an OR. */ |
7484b8e6 | 9058 | if (rs->dependency->specifier == IA64_RS_PR |
afa680f8 | 9059 | || rs->dependency->specifier == IA64_RS_PRr |
7484b8e6 TW |
9060 | || rs->dependency->specifier == IA64_RS_PR63) |
9061 | { | |
9062 | if (specs[count].cmp_type != CMP_NONE | |
9063 | && specs[count].cmp_type == rs->cmp_type) | |
9064 | { | |
9065 | if (md.debug_dv) | |
9066 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", | |
9067 | dv_mode[rs->dependency->mode], | |
afa680f8 | 9068 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 TW |
9069 | specs[count].index : 63); |
9070 | continue; | |
9071 | } | |
9072 | if (md.debug_dv) | |
4a4f25cf | 9073 | fprintf (stderr, |
7484b8e6 TW |
9074 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
9075 | dv_mode[rs->dependency->mode], | |
4a4f25cf | 9076 | dv_cmp_type[rs->cmp_type], |
7484b8e6 | 9077 | dv_cmp_type[specs[count].cmp_type], |
afa680f8 | 9078 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 | 9079 | specs[count].index : 63); |
4a4f25cf | 9080 | |
7484b8e6 TW |
9081 | } |
9082 | ||
800eeca4 | 9083 | /* If either resource is not specific, conservatively assume a conflict |
197865e8 | 9084 | */ |
800eeca4 | 9085 | if (!specs[count].specific || !rs->specific) |
542d6675 | 9086 | return 2; |
800eeca4 | 9087 | else if (specs[count].index == rs->index) |
542d6675 | 9088 | return 1; |
800eeca4 JW |
9089 | } |
9090 | #if 0 | |
9091 | if (md.debug_dv) | |
9092 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); | |
9093 | #endif | |
9094 | ||
9095 | return 0; | |
9096 | } | |
9097 | ||
9098 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then | |
9099 | insert a stop to create the break. Update all resource dependencies | |
9100 | appropriately. If QP_REGNO is non-zero, only apply the break to resources | |
9101 | which use the same QP_REGNO and have the link_to_qp_branch flag set. | |
9102 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current | |
542d6675 | 9103 | instruction. */ |
800eeca4 JW |
9104 | |
9105 | static void | |
9106 | insn_group_break (insert_stop, qp_regno, save_current) | |
542d6675 KH |
9107 | int insert_stop; |
9108 | int qp_regno; | |
9109 | int save_current; | |
800eeca4 JW |
9110 | { |
9111 | int i; | |
9112 | ||
9113 | if (insert_stop && md.num_slots_in_use > 0) | |
9114 | PREV_SLOT.end_of_insn_group = 1; | |
9115 | ||
9116 | if (md.debug_dv) | |
9117 | { | |
197865e8 | 9118 | fprintf (stderr, " Insn group break%s", |
542d6675 | 9119 | (insert_stop ? " (w/stop)" : "")); |
800eeca4 | 9120 | if (qp_regno != 0) |
542d6675 | 9121 | fprintf (stderr, " effective for QP=%d", qp_regno); |
800eeca4 JW |
9122 | fprintf (stderr, "\n"); |
9123 | } | |
9124 | ||
9125 | i = 0; | |
9126 | while (i < regdepslen) | |
9127 | { | |
9128 | const struct ia64_dependency *dep = regdeps[i].dependency; | |
9129 | ||
9130 | if (qp_regno != 0 | |
542d6675 KH |
9131 | && regdeps[i].qp_regno != qp_regno) |
9132 | { | |
9133 | ++i; | |
9134 | continue; | |
9135 | } | |
800eeca4 JW |
9136 | |
9137 | if (save_current | |
542d6675 KH |
9138 | && CURR_SLOT.src_file == regdeps[i].file |
9139 | && CURR_SLOT.src_line == regdeps[i].line) | |
9140 | { | |
9141 | ++i; | |
9142 | continue; | |
9143 | } | |
800eeca4 JW |
9144 | |
9145 | /* clear dependencies which are automatically cleared by a stop, or | |
542d6675 | 9146 | those that have reached the appropriate state of insn serialization */ |
800eeca4 | 9147 | if (dep->semantics == IA64_DVS_IMPLIED |
542d6675 KH |
9148 | || dep->semantics == IA64_DVS_IMPLIEDF |
9149 | || regdeps[i].insn_srlz == STATE_SRLZ) | |
9150 | { | |
9151 | print_dependency ("Removing", i); | |
9152 | regdeps[i] = regdeps[--regdepslen]; | |
9153 | } | |
800eeca4 | 9154 | else |
542d6675 KH |
9155 | { |
9156 | if (dep->semantics == IA64_DVS_DATA | |
9157 | || dep->semantics == IA64_DVS_INSTR | |
800eeca4 | 9158 | || dep->semantics == IA64_DVS_SPECIFIC) |
542d6675 KH |
9159 | { |
9160 | if (regdeps[i].insn_srlz == STATE_NONE) | |
9161 | regdeps[i].insn_srlz = STATE_STOP; | |
9162 | if (regdeps[i].data_srlz == STATE_NONE) | |
9163 | regdeps[i].data_srlz = STATE_STOP; | |
9164 | } | |
9165 | ++i; | |
9166 | } | |
800eeca4 JW |
9167 | } |
9168 | } | |
9169 | ||
542d6675 KH |
9170 | /* Add the given resource usage spec to the list of active dependencies. */ |
9171 | ||
197865e8 | 9172 | static void |
800eeca4 | 9173 | mark_resource (idesc, dep, spec, depind, path) |
2434f565 JW |
9174 | struct ia64_opcode *idesc ATTRIBUTE_UNUSED; |
9175 | const struct ia64_dependency *dep ATTRIBUTE_UNUSED; | |
542d6675 KH |
9176 | struct rsrc *spec; |
9177 | int depind; | |
9178 | int path; | |
800eeca4 JW |
9179 | { |
9180 | if (regdepslen == regdepstotlen) | |
9181 | { | |
9182 | regdepstotlen += 20; | |
9183 | regdeps = (struct rsrc *) | |
542d6675 | 9184 | xrealloc ((void *) regdeps, |
bc805888 | 9185 | regdepstotlen * sizeof (struct rsrc)); |
800eeca4 JW |
9186 | } |
9187 | ||
9188 | regdeps[regdepslen] = *spec; | |
9189 | regdeps[regdepslen].depind = depind; | |
9190 | regdeps[regdepslen].path = path; | |
9191 | regdeps[regdepslen].file = CURR_SLOT.src_file; | |
9192 | regdeps[regdepslen].line = CURR_SLOT.src_line; | |
9193 | ||
9194 | print_dependency ("Adding", regdepslen); | |
9195 | ||
9196 | ++regdepslen; | |
9197 | } | |
9198 | ||
9199 | static void | |
9200 | print_dependency (action, depind) | |
542d6675 KH |
9201 | const char *action; |
9202 | int depind; | |
800eeca4 JW |
9203 | { |
9204 | if (md.debug_dv) | |
9205 | { | |
197865e8 | 9206 | fprintf (stderr, " %s %s '%s'", |
542d6675 KH |
9207 | action, dv_mode[(regdeps[depind].dependency)->mode], |
9208 | (regdeps[depind].dependency)->name); | |
800eeca4 | 9209 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
542d6675 | 9210 | fprintf (stderr, " (%d)", regdeps[depind].index); |
800eeca4 | 9211 | if (regdeps[depind].mem_offset.hint) |
2434f565 JW |
9212 | { |
9213 | fputs (" ", stderr); | |
9214 | fprintf_vma (stderr, regdeps[depind].mem_offset.base); | |
9215 | fputs ("+", stderr); | |
9216 | fprintf_vma (stderr, regdeps[depind].mem_offset.offset); | |
9217 | } | |
800eeca4 JW |
9218 | fprintf (stderr, "\n"); |
9219 | } | |
9220 | } | |
9221 | ||
9222 | static void | |
9223 | instruction_serialization () | |
9224 | { | |
9225 | int i; | |
9226 | if (md.debug_dv) | |
9227 | fprintf (stderr, " Instruction serialization\n"); | |
542d6675 | 9228 | for (i = 0; i < regdepslen; i++) |
800eeca4 JW |
9229 | if (regdeps[i].insn_srlz == STATE_STOP) |
9230 | regdeps[i].insn_srlz = STATE_SRLZ; | |
9231 | } | |
9232 | ||
9233 | static void | |
9234 | data_serialization () | |
9235 | { | |
9236 | int i = 0; | |
9237 | if (md.debug_dv) | |
9238 | fprintf (stderr, " Data serialization\n"); | |
9239 | while (i < regdepslen) | |
9240 | { | |
9241 | if (regdeps[i].data_srlz == STATE_STOP | |
542d6675 KH |
9242 | /* Note: as of 991210, all "other" dependencies are cleared by a |
9243 | data serialization. This might change with new tables */ | |
9244 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) | |
9245 | { | |
9246 | print_dependency ("Removing", i); | |
9247 | regdeps[i] = regdeps[--regdepslen]; | |
9248 | } | |
800eeca4 | 9249 | else |
542d6675 | 9250 | ++i; |
800eeca4 JW |
9251 | } |
9252 | } | |
9253 | ||
542d6675 KH |
9254 | /* Insert stops and serializations as needed to avoid DVs. */ |
9255 | ||
800eeca4 JW |
9256 | static void |
9257 | remove_marked_resource (rs) | |
542d6675 | 9258 | struct rsrc *rs; |
800eeca4 JW |
9259 | { |
9260 | switch (rs->dependency->semantics) | |
9261 | { | |
9262 | case IA64_DVS_SPECIFIC: | |
9263 | if (md.debug_dv) | |
9264 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); | |
197865e8 | 9265 | /* ...fall through... */ |
800eeca4 JW |
9266 | case IA64_DVS_INSTR: |
9267 | if (md.debug_dv) | |
542d6675 | 9268 | fprintf (stderr, "Inserting instr serialization\n"); |
800eeca4 | 9269 | if (rs->insn_srlz < STATE_STOP) |
542d6675 | 9270 | insn_group_break (1, 0, 0); |
800eeca4 | 9271 | if (rs->insn_srlz < STATE_SRLZ) |
542d6675 KH |
9272 | { |
9273 | int oldqp = CURR_SLOT.qp_regno; | |
9274 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
9275 | /* Manually jam a srlz.i insn into the stream */ | |
9276 | CURR_SLOT.qp_regno = 0; | |
9277 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); | |
9278 | instruction_serialization (); | |
9279 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9280 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9281 | emit_one_bundle (); | |
9282 | CURR_SLOT.qp_regno = oldqp; | |
9283 | CURR_SLOT.idesc = oldidesc; | |
9284 | } | |
800eeca4 JW |
9285 | insn_group_break (1, 0, 0); |
9286 | break; | |
9287 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all | |
542d6675 KH |
9288 | "other" types of DV are eliminated |
9289 | by a data serialization */ | |
800eeca4 JW |
9290 | case IA64_DVS_DATA: |
9291 | if (md.debug_dv) | |
542d6675 | 9292 | fprintf (stderr, "Inserting data serialization\n"); |
800eeca4 | 9293 | if (rs->data_srlz < STATE_STOP) |
542d6675 | 9294 | insn_group_break (1, 0, 0); |
800eeca4 | 9295 | { |
542d6675 KH |
9296 | int oldqp = CURR_SLOT.qp_regno; |
9297 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
9298 | /* Manually jam a srlz.d insn into the stream */ | |
9299 | CURR_SLOT.qp_regno = 0; | |
9300 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); | |
9301 | data_serialization (); | |
9302 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9303 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9304 | emit_one_bundle (); | |
9305 | CURR_SLOT.qp_regno = oldqp; | |
9306 | CURR_SLOT.idesc = oldidesc; | |
800eeca4 JW |
9307 | } |
9308 | break; | |
9309 | case IA64_DVS_IMPLIED: | |
9310 | case IA64_DVS_IMPLIEDF: | |
9311 | if (md.debug_dv) | |
542d6675 | 9312 | fprintf (stderr, "Inserting stop\n"); |
800eeca4 JW |
9313 | insn_group_break (1, 0, 0); |
9314 | break; | |
9315 | default: | |
9316 | break; | |
9317 | } | |
9318 | } | |
9319 | ||
9320 | /* Check the resources used by the given opcode against the current dependency | |
197865e8 | 9321 | list. |
800eeca4 JW |
9322 | |
9323 | The check is run once for each execution path encountered. In this case, | |
9324 | a unique execution path is the sequence of instructions following a code | |
9325 | entry point, e.g. the following has three execution paths, one starting | |
9326 | at L0, one at L1, and one at L2. | |
197865e8 | 9327 | |
800eeca4 JW |
9328 | L0: nop |
9329 | L1: add | |
9330 | L2: add | |
197865e8 | 9331 | br.ret |
800eeca4 | 9332 | */ |
542d6675 | 9333 | |
800eeca4 JW |
9334 | static void |
9335 | check_dependencies (idesc) | |
542d6675 | 9336 | struct ia64_opcode *idesc; |
800eeca4 JW |
9337 | { |
9338 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
9339 | int path; | |
9340 | int i; | |
9341 | ||
9342 | /* Note that the number of marked resources may change within the | |
197865e8 | 9343 | loop if in auto mode. */ |
800eeca4 JW |
9344 | i = 0; |
9345 | while (i < regdepslen) | |
9346 | { | |
9347 | struct rsrc *rs = ®deps[i]; | |
9348 | const struct ia64_dependency *dep = rs->dependency; | |
9349 | int chkind; | |
9350 | int note; | |
9351 | int start_over = 0; | |
9352 | ||
9353 | if (dep->semantics == IA64_DVS_NONE | |
542d6675 KH |
9354 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
9355 | { | |
9356 | ++i; | |
9357 | continue; | |
9358 | } | |
9359 | ||
9360 | note = NOTE (opdeps->chks[chkind]); | |
9361 | ||
9362 | /* Check this resource against each execution path seen thus far. */ | |
9363 | for (path = 0; path <= md.path; path++) | |
9364 | { | |
9365 | int matchtype; | |
9366 | ||
9367 | /* If the dependency wasn't on the path being checked, ignore it. */ | |
9368 | if (rs->path < path) | |
9369 | continue; | |
9370 | ||
9371 | /* If the QP for this insn implies a QP which has branched, don't | |
9372 | bother checking. Ed. NOTE: I don't think this check is terribly | |
9373 | useful; what's the point of generating code which will only be | |
9374 | reached if its QP is zero? | |
9375 | This code was specifically inserted to handle the following code, | |
9376 | based on notes from Intel's DV checking code, where p1 implies p2. | |
9377 | ||
9378 | mov r4 = 2 | |
9379 | (p2) br.cond L | |
9380 | (p1) mov r4 = 7 | |
9381 | */ | |
9382 | if (CURR_SLOT.qp_regno != 0) | |
9383 | { | |
9384 | int skip = 0; | |
9385 | int implies; | |
9386 | for (implies = 0; implies < qp_implieslen; implies++) | |
9387 | { | |
9388 | if (qp_implies[implies].path >= path | |
9389 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno | |
9390 | && qp_implies[implies].p2_branched) | |
9391 | { | |
9392 | skip = 1; | |
9393 | break; | |
9394 | } | |
9395 | } | |
9396 | if (skip) | |
9397 | continue; | |
9398 | } | |
9399 | ||
9400 | if ((matchtype = resources_match (rs, idesc, note, | |
9401 | CURR_SLOT.qp_regno, path)) != 0) | |
9402 | { | |
9403 | char msg[1024]; | |
9404 | char pathmsg[256] = ""; | |
9405 | char indexmsg[256] = ""; | |
9406 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); | |
9407 | ||
9408 | if (path != 0) | |
9409 | sprintf (pathmsg, " when entry is at label '%s'", | |
9410 | md.entry_labels[path - 1]); | |
9411 | if (rs->specific && rs->index != 0) | |
9412 | sprintf (indexmsg, ", specific resource number is %d", | |
9413 | rs->index); | |
9414 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", | |
9415 | idesc->name, | |
9416 | (certain ? "violates" : "may violate"), | |
9417 | dv_mode[dep->mode], dep->name, | |
9418 | dv_sem[dep->semantics], | |
9419 | pathmsg, indexmsg); | |
9420 | ||
9421 | if (md.explicit_mode) | |
9422 | { | |
9423 | as_warn ("%s", msg); | |
9424 | if (path < md.path) | |
9425 | as_warn (_("Only the first path encountering the conflict " | |
9426 | "is reported")); | |
9427 | as_warn_where (rs->file, rs->line, | |
9428 | _("This is the location of the " | |
9429 | "conflicting usage")); | |
9430 | /* Don't bother checking other paths, to avoid duplicating | |
9431 | the same warning */ | |
9432 | break; | |
9433 | } | |
9434 | else | |
9435 | { | |
9436 | if (md.debug_dv) | |
9437 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); | |
9438 | ||
9439 | remove_marked_resource (rs); | |
9440 | ||
9441 | /* since the set of dependencies has changed, start over */ | |
9442 | /* FIXME -- since we're removing dvs as we go, we | |
9443 | probably don't really need to start over... */ | |
9444 | start_over = 1; | |
9445 | break; | |
9446 | } | |
9447 | } | |
9448 | } | |
800eeca4 | 9449 | if (start_over) |
542d6675 | 9450 | i = 0; |
800eeca4 | 9451 | else |
542d6675 | 9452 | ++i; |
800eeca4 JW |
9453 | } |
9454 | } | |
9455 | ||
542d6675 KH |
9456 | /* Register new dependencies based on the given opcode. */ |
9457 | ||
800eeca4 JW |
9458 | static void |
9459 | mark_resources (idesc) | |
542d6675 | 9460 | struct ia64_opcode *idesc; |
800eeca4 JW |
9461 | { |
9462 | int i; | |
9463 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
9464 | int add_only_qp_reads = 0; | |
9465 | ||
9466 | /* A conditional branch only uses its resources if it is taken; if it is | |
9467 | taken, we stop following that path. The other branch types effectively | |
9468 | *always* write their resources. If it's not taken, register only QP | |
197865e8 | 9469 | reads. */ |
800eeca4 JW |
9470 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
9471 | { | |
9472 | add_only_qp_reads = 1; | |
9473 | } | |
9474 | ||
9475 | if (md.debug_dv) | |
9476 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); | |
9477 | ||
542d6675 | 9478 | for (i = 0; i < opdeps->nregs; i++) |
800eeca4 JW |
9479 | { |
9480 | const struct ia64_dependency *dep; | |
9481 | struct rsrc specs[MAX_SPECS]; | |
9482 | int note; | |
9483 | int path; | |
9484 | int count; | |
197865e8 | 9485 | |
800eeca4 | 9486 | dep = ia64_find_dependency (opdeps->regs[i]); |
542d6675 | 9487 | note = NOTE (opdeps->regs[i]); |
800eeca4 JW |
9488 | |
9489 | if (add_only_qp_reads | |
542d6675 KH |
9490 | && !(dep->mode == IA64_DV_WAR |
9491 | && (dep->specifier == IA64_RS_PR | |
139368c9 | 9492 | || dep->specifier == IA64_RS_PRr |
542d6675 KH |
9493 | || dep->specifier == IA64_RS_PR63))) |
9494 | continue; | |
800eeca4 JW |
9495 | |
9496 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); | |
9497 | ||
9498 | #if 0 | |
9499 | if (md.debug_dv && !count) | |
542d6675 KH |
9500 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
9501 | dv_mode[dep->mode], dep->name, md.path); | |
800eeca4 | 9502 | #endif |
197865e8 | 9503 | |
800eeca4 | 9504 | while (count-- > 0) |
542d6675 KH |
9505 | { |
9506 | mark_resource (idesc, dep, &specs[count], | |
9507 | DEP (opdeps->regs[i]), md.path); | |
9508 | } | |
800eeca4 JW |
9509 | |
9510 | /* The execution path may affect register values, which may in turn | |
542d6675 | 9511 | affect which indirect-access resources are accessed. */ |
800eeca4 | 9512 | switch (dep->specifier) |
542d6675 KH |
9513 | { |
9514 | default: | |
9515 | break; | |
9516 | case IA64_RS_CPUID: | |
9517 | case IA64_RS_DBR: | |
9518 | case IA64_RS_IBR: | |
800eeca4 | 9519 | case IA64_RS_MSR: |
542d6675 KH |
9520 | case IA64_RS_PKR: |
9521 | case IA64_RS_PMC: | |
9522 | case IA64_RS_PMD: | |
9523 | case IA64_RS_RR: | |
9524 | for (path = 0; path < md.path; path++) | |
9525 | { | |
9526 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); | |
9527 | while (count-- > 0) | |
9528 | mark_resource (idesc, dep, &specs[count], | |
9529 | DEP (opdeps->regs[i]), path); | |
9530 | } | |
9531 | break; | |
9532 | } | |
9533 | } | |
9534 | } | |
9535 | ||
9536 | /* Remove dependencies when they no longer apply. */ | |
9537 | ||
800eeca4 JW |
9538 | static void |
9539 | update_dependencies (idesc) | |
542d6675 | 9540 | struct ia64_opcode *idesc; |
800eeca4 JW |
9541 | { |
9542 | int i; | |
9543 | ||
9544 | if (strcmp (idesc->name, "srlz.i") == 0) | |
9545 | { | |
9546 | instruction_serialization (); | |
9547 | } | |
9548 | else if (strcmp (idesc->name, "srlz.d") == 0) | |
9549 | { | |
9550 | data_serialization (); | |
9551 | } | |
9552 | else if (is_interruption_or_rfi (idesc) | |
542d6675 | 9553 | || is_taken_branch (idesc)) |
800eeca4 | 9554 | { |
542d6675 KH |
9555 | /* Although technically the taken branch doesn't clear dependencies |
9556 | which require a srlz.[id], we don't follow the branch; the next | |
9557 | instruction is assumed to start with a clean slate. */ | |
800eeca4 | 9558 | regdepslen = 0; |
800eeca4 JW |
9559 | md.path = 0; |
9560 | } | |
9561 | else if (is_conditional_branch (idesc) | |
542d6675 | 9562 | && CURR_SLOT.qp_regno != 0) |
800eeca4 JW |
9563 | { |
9564 | int is_call = strstr (idesc->name, ".call") != NULL; | |
9565 | ||
542d6675 KH |
9566 | for (i = 0; i < qp_implieslen; i++) |
9567 | { | |
9568 | /* If the conditional branch's predicate is implied by the predicate | |
9569 | in an existing dependency, remove that dependency. */ | |
9570 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) | |
9571 | { | |
9572 | int depind = 0; | |
9573 | /* Note that this implied predicate takes a branch so that if | |
9574 | a later insn generates a DV but its predicate implies this | |
9575 | one, we can avoid the false DV warning. */ | |
9576 | qp_implies[i].p2_branched = 1; | |
9577 | while (depind < regdepslen) | |
9578 | { | |
9579 | if (regdeps[depind].qp_regno == qp_implies[i].p1) | |
9580 | { | |
9581 | print_dependency ("Removing", depind); | |
9582 | regdeps[depind] = regdeps[--regdepslen]; | |
9583 | } | |
9584 | else | |
9585 | ++depind; | |
9586 | } | |
9587 | } | |
9588 | } | |
800eeca4 | 9589 | /* Any marked resources which have this same predicate should be |
542d6675 KH |
9590 | cleared, provided that the QP hasn't been modified between the |
9591 | marking instruction and the branch. */ | |
800eeca4 | 9592 | if (is_call) |
542d6675 KH |
9593 | { |
9594 | insn_group_break (0, CURR_SLOT.qp_regno, 1); | |
9595 | } | |
800eeca4 | 9596 | else |
542d6675 KH |
9597 | { |
9598 | i = 0; | |
9599 | while (i < regdepslen) | |
9600 | { | |
9601 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno | |
9602 | && regdeps[i].link_to_qp_branch | |
9603 | && (regdeps[i].file != CURR_SLOT.src_file | |
9604 | || regdeps[i].line != CURR_SLOT.src_line)) | |
9605 | { | |
9606 | /* Treat like a taken branch */ | |
9607 | print_dependency ("Removing", i); | |
9608 | regdeps[i] = regdeps[--regdepslen]; | |
9609 | } | |
9610 | else | |
9611 | ++i; | |
9612 | } | |
9613 | } | |
800eeca4 JW |
9614 | } |
9615 | } | |
9616 | ||
9617 | /* Examine the current instruction for dependency violations. */ | |
542d6675 | 9618 | |
800eeca4 JW |
9619 | static int |
9620 | check_dv (idesc) | |
542d6675 | 9621 | struct ia64_opcode *idesc; |
800eeca4 JW |
9622 | { |
9623 | if (md.debug_dv) | |
9624 | { | |
197865e8 | 9625 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
542d6675 KH |
9626 | idesc->name, CURR_SLOT.src_line, |
9627 | idesc->dependencies->nchks, | |
9628 | idesc->dependencies->nregs); | |
800eeca4 JW |
9629 | } |
9630 | ||
197865e8 | 9631 | /* Look through the list of currently marked resources; if the current |
800eeca4 | 9632 | instruction has the dependency in its chks list which uses that resource, |
542d6675 | 9633 | check against the specific resources used. */ |
800eeca4 JW |
9634 | check_dependencies (idesc); |
9635 | ||
542d6675 KH |
9636 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
9637 | then add them to the list of marked resources. */ | |
800eeca4 JW |
9638 | mark_resources (idesc); |
9639 | ||
9640 | /* There are several types of dependency semantics, and each has its own | |
197865e8 KH |
9641 | requirements for being cleared |
9642 | ||
800eeca4 JW |
9643 | Instruction serialization (insns separated by interruption, rfi, or |
9644 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. | |
9645 | ||
9646 | Data serialization (instruction serialization, or writer + srlz.d + | |
9647 | reader, where writer and srlz.d are in separate groups) clears | |
9648 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to | |
9649 | always be the case). | |
9650 | ||
9651 | Instruction group break (groups separated by stop, taken branch, | |
9652 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. | |
9653 | */ | |
9654 | update_dependencies (idesc); | |
9655 | ||
9656 | /* Sometimes, knowing a register value allows us to avoid giving a false DV | |
197865e8 | 9657 | warning. Keep track of as many as possible that are useful. */ |
800eeca4 JW |
9658 | note_register_values (idesc); |
9659 | ||
197865e8 | 9660 | /* We don't need or want this anymore. */ |
800eeca4 JW |
9661 | md.mem_offset.hint = 0; |
9662 | ||
9663 | return 0; | |
9664 | } | |
9665 | ||
9666 | /* Translate one line of assembly. Pseudo ops and labels do not show | |
9667 | here. */ | |
9668 | void | |
9669 | md_assemble (str) | |
9670 | char *str; | |
9671 | { | |
9672 | char *saved_input_line_pointer, *mnemonic; | |
9673 | const struct pseudo_opcode *pdesc; | |
9674 | struct ia64_opcode *idesc; | |
9675 | unsigned char qp_regno; | |
9676 | unsigned int flags; | |
9677 | int ch; | |
9678 | ||
9679 | saved_input_line_pointer = input_line_pointer; | |
9680 | input_line_pointer = str; | |
9681 | ||
542d6675 | 9682 | /* extract the opcode (mnemonic): */ |
800eeca4 JW |
9683 | |
9684 | mnemonic = input_line_pointer; | |
9685 | ch = get_symbol_end (); | |
9686 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); | |
9687 | if (pdesc) | |
9688 | { | |
9689 | *input_line_pointer = ch; | |
9690 | (*pdesc->handler) (pdesc->arg); | |
9691 | goto done; | |
9692 | } | |
9693 | ||
542d6675 | 9694 | /* Find the instruction descriptor matching the arguments. */ |
800eeca4 JW |
9695 | |
9696 | idesc = ia64_find_opcode (mnemonic); | |
9697 | *input_line_pointer = ch; | |
9698 | if (!idesc) | |
9699 | { | |
9700 | as_bad ("Unknown opcode `%s'", mnemonic); | |
9701 | goto done; | |
9702 | } | |
9703 | ||
9704 | idesc = parse_operands (idesc); | |
9705 | if (!idesc) | |
9706 | goto done; | |
9707 | ||
542d6675 | 9708 | /* Handle the dynamic ops we can handle now: */ |
800eeca4 JW |
9709 | if (idesc->type == IA64_TYPE_DYN) |
9710 | { | |
9711 | if (strcmp (idesc->name, "add") == 0) | |
9712 | { | |
9713 | if (CURR_SLOT.opnd[2].X_op == O_register | |
9714 | && CURR_SLOT.opnd[2].X_add_number < 4) | |
9715 | mnemonic = "addl"; | |
9716 | else | |
9717 | mnemonic = "adds"; | |
3d56ab85 | 9718 | ia64_free_opcode (idesc); |
800eeca4 JW |
9719 | idesc = ia64_find_opcode (mnemonic); |
9720 | #if 0 | |
9721 | know (!idesc->next); | |
9722 | #endif | |
9723 | } | |
9724 | else if (strcmp (idesc->name, "mov") == 0) | |
9725 | { | |
9726 | enum ia64_opnd opnd1, opnd2; | |
9727 | int rop; | |
9728 | ||
9729 | opnd1 = idesc->operands[0]; | |
9730 | opnd2 = idesc->operands[1]; | |
9731 | if (opnd1 == IA64_OPND_AR3) | |
9732 | rop = 0; | |
9733 | else if (opnd2 == IA64_OPND_AR3) | |
9734 | rop = 1; | |
9735 | else | |
9736 | abort (); | |
9737 | if (CURR_SLOT.opnd[rop].X_op == O_register | |
9738 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) | |
9739 | mnemonic = "mov.i"; | |
9740 | else | |
9741 | mnemonic = "mov.m"; | |
3d56ab85 | 9742 | ia64_free_opcode (idesc); |
800eeca4 JW |
9743 | idesc = ia64_find_opcode (mnemonic); |
9744 | while (idesc != NULL | |
9745 | && (idesc->operands[0] != opnd1 | |
9746 | || idesc->operands[1] != opnd2)) | |
9747 | idesc = get_next_opcode (idesc); | |
9748 | } | |
9749 | } | |
9750 | ||
9751 | qp_regno = 0; | |
9752 | if (md.qp.X_op == O_register) | |
f1bcba5b JW |
9753 | { |
9754 | qp_regno = md.qp.X_add_number - REG_P; | |
9755 | md.qp.X_op = O_absent; | |
9756 | } | |
800eeca4 JW |
9757 | |
9758 | flags = idesc->flags; | |
9759 | ||
9760 | if ((flags & IA64_OPCODE_FIRST) != 0) | |
9761 | insn_group_break (1, 0, 0); | |
9762 | ||
9763 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) | |
9764 | { | |
9765 | as_bad ("`%s' cannot be predicated", idesc->name); | |
9766 | goto done; | |
9767 | } | |
9768 | ||
542d6675 | 9769 | /* Build the instruction. */ |
800eeca4 JW |
9770 | CURR_SLOT.qp_regno = qp_regno; |
9771 | CURR_SLOT.idesc = idesc; | |
9772 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); | |
4dc7ead9 | 9773 | dwarf2_where (&CURR_SLOT.debug_line); |
800eeca4 JW |
9774 | |
9775 | /* Add unwind entry, if there is one. */ | |
e0c9811a | 9776 | if (unwind.current_entry) |
800eeca4 | 9777 | { |
e0c9811a JW |
9778 | CURR_SLOT.unwind_record = unwind.current_entry; |
9779 | unwind.current_entry = NULL; | |
800eeca4 JW |
9780 | } |
9781 | ||
542d6675 | 9782 | /* Check for dependency violations. */ |
800eeca4 | 9783 | if (md.detect_dv) |
542d6675 | 9784 | check_dv (idesc); |
800eeca4 JW |
9785 | |
9786 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9787 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9788 | emit_one_bundle (); | |
9789 | ||
9790 | if ((flags & IA64_OPCODE_LAST) != 0) | |
9791 | insn_group_break (1, 0, 0); | |
9792 | ||
9793 | md.last_text_seg = now_seg; | |
9794 | ||
9795 | done: | |
9796 | input_line_pointer = saved_input_line_pointer; | |
9797 | } | |
9798 | ||
9799 | /* Called when symbol NAME cannot be found in the symbol table. | |
9800 | Should be used for dynamic valued symbols only. */ | |
542d6675 KH |
9801 | |
9802 | symbolS * | |
800eeca4 | 9803 | md_undefined_symbol (name) |
2434f565 | 9804 | char *name ATTRIBUTE_UNUSED; |
800eeca4 JW |
9805 | { |
9806 | return 0; | |
9807 | } | |
9808 | ||
9809 | /* Called for any expression that can not be recognized. When the | |
9810 | function is called, `input_line_pointer' will point to the start of | |
9811 | the expression. */ | |
542d6675 | 9812 | |
800eeca4 JW |
9813 | void |
9814 | md_operand (e) | |
9815 | expressionS *e; | |
9816 | { | |
9817 | enum pseudo_type pseudo_type; | |
e0c9811a | 9818 | const char *name; |
800eeca4 JW |
9819 | size_t len; |
9820 | int ch, i; | |
9821 | ||
9822 | switch (*input_line_pointer) | |
9823 | { | |
9824 | case '@': | |
542d6675 | 9825 | /* Find what relocation pseudo-function we're dealing with. */ |
800eeca4 JW |
9826 | pseudo_type = 0; |
9827 | ch = *++input_line_pointer; | |
9828 | for (i = 0; i < NELEMS (pseudo_func); ++i) | |
9829 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) | |
9830 | { | |
9831 | len = strlen (pseudo_func[i].name); | |
9832 | if (strncmp (pseudo_func[i].name + 1, | |
9833 | input_line_pointer + 1, len - 1) == 0 | |
9834 | && !is_part_of_name (input_line_pointer[len])) | |
9835 | { | |
9836 | input_line_pointer += len; | |
9837 | pseudo_type = pseudo_func[i].type; | |
9838 | break; | |
9839 | } | |
9840 | } | |
9841 | switch (pseudo_type) | |
9842 | { | |
9843 | case PSEUDO_FUNC_RELOC: | |
9844 | SKIP_WHITESPACE (); | |
9845 | if (*input_line_pointer != '(') | |
9846 | { | |
9847 | as_bad ("Expected '('"); | |
9848 | goto err; | |
9849 | } | |
542d6675 KH |
9850 | /* Skip '('. */ |
9851 | ++input_line_pointer; | |
800eeca4 JW |
9852 | expression (e); |
9853 | if (*input_line_pointer++ != ')') | |
9854 | { | |
9855 | as_bad ("Missing ')'"); | |
9856 | goto err; | |
9857 | } | |
9858 | if (e->X_op != O_symbol) | |
9859 | { | |
9860 | if (e->X_op != O_pseudo_fixup) | |
9861 | { | |
9862 | as_bad ("Not a symbolic expression"); | |
9863 | goto err; | |
9864 | } | |
13ae64f3 JJ |
9865 | if (i != FUNC_LT_RELATIVE) |
9866 | { | |
9867 | as_bad ("Illegal combination of relocation functions"); | |
9868 | goto err; | |
9869 | } | |
9870 | switch (S_GET_VALUE (e->X_op_symbol)) | |
800eeca4 | 9871 | { |
13ae64f3 JJ |
9872 | case FUNC_FPTR_RELATIVE: |
9873 | i = FUNC_LT_FPTR_RELATIVE; break; | |
9874 | case FUNC_DTP_MODULE: | |
9875 | i = FUNC_LT_DTP_MODULE; break; | |
9876 | case FUNC_DTP_RELATIVE: | |
9877 | i = FUNC_LT_DTP_RELATIVE; break; | |
9878 | case FUNC_TP_RELATIVE: | |
9879 | i = FUNC_LT_TP_RELATIVE; break; | |
9880 | default: | |
800eeca4 JW |
9881 | as_bad ("Illegal combination of relocation functions"); |
9882 | goto err; | |
9883 | } | |
9884 | } | |
542d6675 KH |
9885 | /* Make sure gas doesn't get rid of local symbols that are used |
9886 | in relocs. */ | |
800eeca4 JW |
9887 | e->X_op = O_pseudo_fixup; |
9888 | e->X_op_symbol = pseudo_func[i].u.sym; | |
9889 | break; | |
9890 | ||
9891 | case PSEUDO_FUNC_CONST: | |
9892 | e->X_op = O_constant; | |
9893 | e->X_add_number = pseudo_func[i].u.ival; | |
9894 | break; | |
9895 | ||
e0c9811a JW |
9896 | case PSEUDO_FUNC_REG: |
9897 | e->X_op = O_register; | |
9898 | e->X_add_number = pseudo_func[i].u.ival; | |
9899 | break; | |
9900 | ||
800eeca4 | 9901 | default: |
e0c9811a JW |
9902 | name = input_line_pointer - 1; |
9903 | get_symbol_end (); | |
9904 | as_bad ("Unknown pseudo function `%s'", name); | |
800eeca4 JW |
9905 | goto err; |
9906 | } | |
9907 | break; | |
9908 | ||
9909 | case '[': | |
9910 | ++input_line_pointer; | |
9911 | expression (e); | |
9912 | if (*input_line_pointer != ']') | |
9913 | { | |
9914 | as_bad ("Closing bracket misssing"); | |
9915 | goto err; | |
9916 | } | |
9917 | else | |
9918 | { | |
9919 | if (e->X_op != O_register) | |
9920 | as_bad ("Register expected as index"); | |
9921 | ||
9922 | ++input_line_pointer; | |
9923 | e->X_op = O_index; | |
9924 | } | |
9925 | break; | |
9926 | ||
9927 | default: | |
9928 | break; | |
9929 | } | |
9930 | return; | |
9931 | ||
9932 | err: | |
9933 | ignore_rest_of_line (); | |
9934 | } | |
9935 | ||
9936 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with | |
9937 | a section symbol plus some offset. For relocs involving @fptr(), | |
9938 | directives we don't want such adjustments since we need to have the | |
9939 | original symbol's name in the reloc. */ | |
9940 | int | |
9941 | ia64_fix_adjustable (fix) | |
9942 | fixS *fix; | |
9943 | { | |
9944 | /* Prevent all adjustments to global symbols */ | |
9945 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) | |
9946 | return 0; | |
9947 | ||
9948 | switch (fix->fx_r_type) | |
9949 | { | |
9950 | case BFD_RELOC_IA64_FPTR64I: | |
9951 | case BFD_RELOC_IA64_FPTR32MSB: | |
9952 | case BFD_RELOC_IA64_FPTR32LSB: | |
9953 | case BFD_RELOC_IA64_FPTR64MSB: | |
9954 | case BFD_RELOC_IA64_FPTR64LSB: | |
9955 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9956 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9957 | return 0; | |
9958 | default: | |
9959 | break; | |
9960 | } | |
9961 | ||
9962 | return 1; | |
9963 | } | |
9964 | ||
9965 | int | |
9966 | ia64_force_relocation (fix) | |
9967 | fixS *fix; | |
9968 | { | |
9969 | switch (fix->fx_r_type) | |
9970 | { | |
9971 | case BFD_RELOC_IA64_FPTR64I: | |
9972 | case BFD_RELOC_IA64_FPTR32MSB: | |
9973 | case BFD_RELOC_IA64_FPTR32LSB: | |
9974 | case BFD_RELOC_IA64_FPTR64MSB: | |
9975 | case BFD_RELOC_IA64_FPTR64LSB: | |
9976 | ||
9977 | case BFD_RELOC_IA64_LTOFF22: | |
9978 | case BFD_RELOC_IA64_LTOFF64I: | |
9979 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9980 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9981 | case BFD_RELOC_IA64_PLTOFF22: | |
9982 | case BFD_RELOC_IA64_PLTOFF64I: | |
9983 | case BFD_RELOC_IA64_PLTOFF64MSB: | |
9984 | case BFD_RELOC_IA64_PLTOFF64LSB: | |
9985 | return 1; | |
9986 | ||
9987 | default: | |
a161fe53 | 9988 | break; |
800eeca4 | 9989 | } |
a161fe53 AM |
9990 | |
9991 | return S_FORCE_RELOC (fix->fx_addsy); | |
800eeca4 JW |
9992 | } |
9993 | ||
9994 | /* Decide from what point a pc-relative relocation is relative to, | |
9995 | relative to the pc-relative fixup. Er, relatively speaking. */ | |
9996 | long | |
9997 | ia64_pcrel_from_section (fix, sec) | |
9998 | fixS *fix; | |
9999 | segT sec; | |
10000 | { | |
10001 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; | |
197865e8 | 10002 | |
800eeca4 JW |
10003 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
10004 | off &= ~0xfUL; | |
10005 | ||
10006 | return off; | |
10007 | } | |
10008 | ||
10009 | /* This is called whenever some data item (not an instruction) needs a | |
10010 | fixup. We pick the right reloc code depending on the byteorder | |
10011 | currently in effect. */ | |
10012 | void | |
10013 | ia64_cons_fix_new (f, where, nbytes, exp) | |
10014 | fragS *f; | |
10015 | int where; | |
10016 | int nbytes; | |
10017 | expressionS *exp; | |
10018 | { | |
10019 | bfd_reloc_code_real_type code; | |
10020 | fixS *fix; | |
10021 | ||
10022 | switch (nbytes) | |
10023 | { | |
10024 | /* There are no reloc for 8 and 16 bit quantities, but we allow | |
10025 | them here since they will work fine as long as the expression | |
10026 | is fully defined at the end of the pass over the source file. */ | |
10027 | case 1: code = BFD_RELOC_8; break; | |
10028 | case 2: code = BFD_RELOC_16; break; | |
10029 | case 4: | |
10030 | if (target_big_endian) | |
10031 | code = BFD_RELOC_IA64_DIR32MSB; | |
10032 | else | |
10033 | code = BFD_RELOC_IA64_DIR32LSB; | |
10034 | break; | |
10035 | ||
10036 | case 8: | |
40449e9f | 10037 | /* In 32-bit mode, data8 could mean function descriptors too. */ |
5f44c186 | 10038 | if (exp->X_op == O_pseudo_fixup |
40449e9f KH |
10039 | && exp->X_op_symbol |
10040 | && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC | |
10041 | && !(md.flags & EF_IA_64_ABI64)) | |
10042 | { | |
10043 | if (target_big_endian) | |
10044 | code = BFD_RELOC_IA64_IPLTMSB; | |
10045 | else | |
10046 | code = BFD_RELOC_IA64_IPLTLSB; | |
10047 | exp->X_op = O_symbol; | |
10048 | break; | |
10049 | } | |
10050 | else | |
10051 | { | |
10052 | if (target_big_endian) | |
10053 | code = BFD_RELOC_IA64_DIR64MSB; | |
10054 | else | |
10055 | code = BFD_RELOC_IA64_DIR64LSB; | |
10056 | break; | |
10057 | } | |
800eeca4 | 10058 | |
3969b680 RH |
10059 | case 16: |
10060 | if (exp->X_op == O_pseudo_fixup | |
10061 | && exp->X_op_symbol | |
10062 | && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) | |
10063 | { | |
10064 | if (target_big_endian) | |
10065 | code = BFD_RELOC_IA64_IPLTMSB; | |
10066 | else | |
10067 | code = BFD_RELOC_IA64_IPLTLSB; | |
10068 | ||
10069 | exp->X_op = O_symbol; | |
10070 | break; | |
10071 | } | |
10072 | /* FALLTHRU */ | |
10073 | ||
800eeca4 JW |
10074 | default: |
10075 | as_bad ("Unsupported fixup size %d", nbytes); | |
10076 | ignore_rest_of_line (); | |
10077 | return; | |
10078 | } | |
10079 | if (exp->X_op == O_pseudo_fixup) | |
10080 | { | |
10081 | /* ??? */ | |
10082 | exp->X_op = O_symbol; | |
10083 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); | |
10084 | } | |
3969b680 | 10085 | |
800eeca4 JW |
10086 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); |
10087 | /* We need to store the byte order in effect in case we're going | |
10088 | to fix an 8 or 16 bit relocation (for which there no real | |
94f592af | 10089 | relocs available). See md_apply_fix3(). */ |
800eeca4 JW |
10090 | fix->tc_fix_data.bigendian = target_big_endian; |
10091 | } | |
10092 | ||
10093 | /* Return the actual relocation we wish to associate with the pseudo | |
10094 | reloc described by SYM and R_TYPE. SYM should be one of the | |
197865e8 | 10095 | symbols in the pseudo_func array, or NULL. */ |
800eeca4 JW |
10096 | |
10097 | static bfd_reloc_code_real_type | |
10098 | ia64_gen_real_reloc_type (sym, r_type) | |
10099 | struct symbol *sym; | |
10100 | bfd_reloc_code_real_type r_type; | |
10101 | { | |
10102 | bfd_reloc_code_real_type new = 0; | |
10103 | ||
10104 | if (sym == NULL) | |
10105 | { | |
10106 | return r_type; | |
10107 | } | |
10108 | ||
10109 | switch (S_GET_VALUE (sym)) | |
10110 | { | |
10111 | case FUNC_FPTR_RELATIVE: | |
10112 | switch (r_type) | |
10113 | { | |
10114 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; | |
10115 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; | |
10116 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; | |
10117 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; | |
10118 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; | |
10119 | default: break; | |
10120 | } | |
10121 | break; | |
10122 | ||
10123 | case FUNC_GP_RELATIVE: | |
10124 | switch (r_type) | |
10125 | { | |
10126 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; | |
10127 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; | |
10128 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; | |
10129 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; | |
10130 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; | |
10131 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; | |
10132 | default: break; | |
10133 | } | |
10134 | break; | |
10135 | ||
10136 | case FUNC_LT_RELATIVE: | |
10137 | switch (r_type) | |
10138 | { | |
10139 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; | |
10140 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; | |
10141 | default: break; | |
10142 | } | |
10143 | break; | |
10144 | ||
c67e42c9 RH |
10145 | case FUNC_PC_RELATIVE: |
10146 | switch (r_type) | |
10147 | { | |
10148 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; | |
10149 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; | |
10150 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; | |
10151 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; | |
10152 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; | |
10153 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; | |
10154 | default: break; | |
10155 | } | |
10156 | break; | |
10157 | ||
800eeca4 JW |
10158 | case FUNC_PLT_RELATIVE: |
10159 | switch (r_type) | |
10160 | { | |
10161 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; | |
10162 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; | |
10163 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; | |
10164 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; | |
10165 | default: break; | |
10166 | } | |
10167 | break; | |
10168 | ||
10169 | case FUNC_SEC_RELATIVE: | |
10170 | switch (r_type) | |
10171 | { | |
10172 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; | |
10173 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; | |
10174 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; | |
10175 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; | |
10176 | default: break; | |
10177 | } | |
10178 | break; | |
10179 | ||
10180 | case FUNC_SEG_RELATIVE: | |
10181 | switch (r_type) | |
10182 | { | |
10183 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; | |
10184 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; | |
10185 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; | |
10186 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; | |
10187 | default: break; | |
10188 | } | |
10189 | break; | |
10190 | ||
10191 | case FUNC_LTV_RELATIVE: | |
10192 | switch (r_type) | |
10193 | { | |
10194 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; | |
10195 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; | |
10196 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; | |
10197 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; | |
10198 | default: break; | |
10199 | } | |
10200 | break; | |
10201 | ||
10202 | case FUNC_LT_FPTR_RELATIVE: | |
10203 | switch (r_type) | |
10204 | { | |
10205 | case BFD_RELOC_IA64_IMM22: | |
10206 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; | |
10207 | case BFD_RELOC_IA64_IMM64: | |
10208 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; | |
10209 | default: | |
10210 | break; | |
10211 | } | |
10212 | break; | |
3969b680 | 10213 | |
13ae64f3 JJ |
10214 | case FUNC_TP_RELATIVE: |
10215 | switch (r_type) | |
10216 | { | |
10217 | case BFD_RELOC_IA64_IMM14: | |
10218 | new = BFD_RELOC_IA64_TPREL14; break; | |
10219 | case BFD_RELOC_IA64_IMM22: | |
10220 | new = BFD_RELOC_IA64_TPREL22; break; | |
10221 | case BFD_RELOC_IA64_IMM64: | |
10222 | new = BFD_RELOC_IA64_TPREL64I; break; | |
10223 | default: | |
10224 | break; | |
10225 | } | |
10226 | break; | |
10227 | ||
10228 | case FUNC_LT_TP_RELATIVE: | |
10229 | switch (r_type) | |
10230 | { | |
10231 | case BFD_RELOC_IA64_IMM22: | |
10232 | new = BFD_RELOC_IA64_LTOFF_TPREL22; break; | |
10233 | default: | |
10234 | break; | |
10235 | } | |
10236 | break; | |
10237 | ||
10238 | case FUNC_LT_DTP_MODULE: | |
10239 | switch (r_type) | |
10240 | { | |
10241 | case BFD_RELOC_IA64_IMM22: | |
10242 | new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break; | |
10243 | default: | |
10244 | break; | |
10245 | } | |
10246 | break; | |
10247 | ||
10248 | case FUNC_DTP_RELATIVE: | |
10249 | switch (r_type) | |
10250 | { | |
10251 | case BFD_RELOC_IA64_IMM14: | |
10252 | new = BFD_RELOC_IA64_DTPREL14; break; | |
10253 | case BFD_RELOC_IA64_IMM22: | |
10254 | new = BFD_RELOC_IA64_DTPREL22; break; | |
10255 | case BFD_RELOC_IA64_IMM64: | |
10256 | new = BFD_RELOC_IA64_DTPREL64I; break; | |
10257 | default: | |
10258 | break; | |
10259 | } | |
10260 | break; | |
10261 | ||
10262 | case FUNC_LT_DTP_RELATIVE: | |
10263 | switch (r_type) | |
10264 | { | |
10265 | case BFD_RELOC_IA64_IMM22: | |
10266 | new = BFD_RELOC_IA64_LTOFF_DTPREL22; break; | |
10267 | default: | |
10268 | break; | |
10269 | } | |
10270 | break; | |
10271 | ||
40449e9f KH |
10272 | case FUNC_IPLT_RELOC: |
10273 | break; | |
1cd8ff38 | 10274 | |
800eeca4 JW |
10275 | default: |
10276 | abort (); | |
10277 | } | |
10278 | /* Hmmmm. Should this ever occur? */ | |
10279 | if (new) | |
10280 | return new; | |
10281 | else | |
10282 | return r_type; | |
10283 | } | |
10284 | ||
10285 | /* Here is where generate the appropriate reloc for pseudo relocation | |
10286 | functions. */ | |
10287 | void | |
10288 | ia64_validate_fix (fix) | |
10289 | fixS *fix; | |
10290 | { | |
10291 | switch (fix->fx_r_type) | |
10292 | { | |
10293 | case BFD_RELOC_IA64_FPTR64I: | |
10294 | case BFD_RELOC_IA64_FPTR32MSB: | |
10295 | case BFD_RELOC_IA64_FPTR64LSB: | |
10296 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
10297 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
10298 | if (fix->fx_offset != 0) | |
10299 | as_bad_where (fix->fx_file, fix->fx_line, | |
10300 | "No addend allowed in @fptr() relocation"); | |
10301 | break; | |
10302 | default: | |
10303 | break; | |
10304 | } | |
10305 | ||
10306 | return; | |
10307 | } | |
10308 | ||
10309 | static void | |
10310 | fix_insn (fix, odesc, value) | |
10311 | fixS *fix; | |
10312 | const struct ia64_operand *odesc; | |
10313 | valueT value; | |
10314 | { | |
10315 | bfd_vma insn[3], t0, t1, control_bits; | |
10316 | const char *err; | |
10317 | char *fixpos; | |
10318 | long slot; | |
10319 | ||
10320 | slot = fix->fx_where & 0x3; | |
10321 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); | |
10322 | ||
c67e42c9 | 10323 | /* Bundles are always in little-endian byte order */ |
800eeca4 JW |
10324 | t0 = bfd_getl64 (fixpos); |
10325 | t1 = bfd_getl64 (fixpos + 8); | |
10326 | control_bits = t0 & 0x1f; | |
10327 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; | |
10328 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); | |
10329 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; | |
10330 | ||
c67e42c9 RH |
10331 | err = NULL; |
10332 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) | |
800eeca4 | 10333 | { |
c67e42c9 RH |
10334 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
10335 | insn[2] |= (((value & 0x7f) << 13) | |
10336 | | (((value >> 7) & 0x1ff) << 27) | |
10337 | | (((value >> 16) & 0x1f) << 22) | |
10338 | | (((value >> 21) & 0x1) << 21) | |
10339 | | (((value >> 63) & 0x1) << 36)); | |
800eeca4 | 10340 | } |
c67e42c9 RH |
10341 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
10342 | { | |
10343 | if (value & ~0x3fffffffffffffffULL) | |
10344 | err = "integer operand out of range"; | |
10345 | insn[1] = (value >> 21) & 0x1ffffffffffLL; | |
10346 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); | |
10347 | } | |
10348 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) | |
10349 | { | |
10350 | value >>= 4; | |
10351 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; | |
10352 | insn[2] |= ((((value >> 59) & 0x1) << 36) | |
10353 | | (((value >> 0) & 0xfffff) << 13)); | |
10354 | } | |
10355 | else | |
10356 | err = (*odesc->insert) (odesc, value, insn + slot); | |
10357 | ||
10358 | if (err) | |
10359 | as_bad_where (fix->fx_file, fix->fx_line, err); | |
800eeca4 JW |
10360 | |
10361 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); | |
10362 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
44f5c83a JW |
10363 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
10364 | number_to_chars_littleendian (fixpos + 8, t1, 8); | |
800eeca4 JW |
10365 | } |
10366 | ||
10367 | /* Attempt to simplify or even eliminate a fixup. The return value is | |
10368 | ignored; perhaps it was once meaningful, but now it is historical. | |
10369 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. | |
10370 | ||
10371 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry | |
197865e8 | 10372 | (if possible). */ |
94f592af NC |
10373 | |
10374 | void | |
10375 | md_apply_fix3 (fix, valP, seg) | |
800eeca4 | 10376 | fixS *fix; |
40449e9f | 10377 | valueT *valP; |
2434f565 | 10378 | segT seg ATTRIBUTE_UNUSED; |
800eeca4 JW |
10379 | { |
10380 | char *fixpos; | |
40449e9f | 10381 | valueT value = *valP; |
800eeca4 JW |
10382 | int adjust = 0; |
10383 | ||
10384 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; | |
10385 | ||
10386 | if (fix->fx_pcrel) | |
10387 | { | |
10388 | switch (fix->fx_r_type) | |
10389 | { | |
10390 | case BFD_RELOC_IA64_DIR32MSB: | |
10391 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; | |
10392 | adjust = 1; | |
10393 | break; | |
10394 | ||
10395 | case BFD_RELOC_IA64_DIR32LSB: | |
10396 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; | |
10397 | adjust = 1; | |
10398 | break; | |
10399 | ||
10400 | case BFD_RELOC_IA64_DIR64MSB: | |
10401 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; | |
10402 | adjust = 1; | |
10403 | break; | |
10404 | ||
10405 | case BFD_RELOC_IA64_DIR64LSB: | |
10406 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; | |
10407 | adjust = 1; | |
10408 | break; | |
10409 | ||
10410 | default: | |
10411 | break; | |
10412 | } | |
10413 | } | |
10414 | if (fix->fx_addsy) | |
10415 | { | |
fa1cb89c | 10416 | if (fix->fx_r_type == (int) BFD_RELOC_UNUSED) |
800eeca4 | 10417 | { |
fa1cb89c JW |
10418 | /* This must be a TAG13 or TAG13b operand. There are no external |
10419 | relocs defined for them, so we must give an error. */ | |
800eeca4 JW |
10420 | as_bad_where (fix->fx_file, fix->fx_line, |
10421 | "%s must have a constant value", | |
10422 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); | |
fa1cb89c | 10423 | fix->fx_done = 1; |
94f592af | 10424 | return; |
800eeca4 JW |
10425 | } |
10426 | ||
10427 | /* ??? This is a hack copied from tc-i386.c to make PCREL relocs | |
542d6675 | 10428 | work. There should be a better way to handle this. */ |
800eeca4 JW |
10429 | if (adjust) |
10430 | fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; | |
10431 | } | |
10432 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) | |
10433 | { | |
10434 | if (fix->tc_fix_data.bigendian) | |
10435 | number_to_chars_bigendian (fixpos, value, fix->fx_size); | |
10436 | else | |
10437 | number_to_chars_littleendian (fixpos, value, fix->fx_size); | |
10438 | fix->fx_done = 1; | |
800eeca4 JW |
10439 | } |
10440 | else | |
10441 | { | |
10442 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); | |
10443 | fix->fx_done = 1; | |
800eeca4 | 10444 | } |
800eeca4 JW |
10445 | } |
10446 | ||
10447 | /* Generate the BFD reloc to be stuck in the object file from the | |
10448 | fixup used internally in the assembler. */ | |
542d6675 KH |
10449 | |
10450 | arelent * | |
800eeca4 | 10451 | tc_gen_reloc (sec, fixp) |
2434f565 | 10452 | asection *sec ATTRIBUTE_UNUSED; |
800eeca4 JW |
10453 | fixS *fixp; |
10454 | { | |
10455 | arelent *reloc; | |
10456 | ||
10457 | reloc = xmalloc (sizeof (*reloc)); | |
10458 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
10459 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
10460 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10461 | reloc->addend = fixp->fx_offset; | |
10462 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
10463 | ||
10464 | if (!reloc->howto) | |
10465 | { | |
10466 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10467 | "Cannot represent %s relocation in object file", | |
10468 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
10469 | } | |
10470 | return reloc; | |
10471 | } | |
10472 | ||
10473 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10474 | of type TYPE, and store the appropriate bytes in *LIT. The number |
10475 | of LITTLENUMS emitted is stored in *SIZE. An error message is | |
800eeca4 JW |
10476 | returned, or NULL on OK. */ |
10477 | ||
10478 | #define MAX_LITTLENUMS 5 | |
10479 | ||
542d6675 | 10480 | char * |
800eeca4 JW |
10481 | md_atof (type, lit, size) |
10482 | int type; | |
10483 | char *lit; | |
10484 | int *size; | |
10485 | { | |
10486 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
10487 | LITTLENUM_TYPE *word; | |
10488 | char *t; | |
10489 | int prec; | |
10490 | ||
10491 | switch (type) | |
10492 | { | |
10493 | /* IEEE floats */ | |
10494 | case 'f': | |
10495 | case 'F': | |
10496 | case 's': | |
10497 | case 'S': | |
10498 | prec = 2; | |
10499 | break; | |
10500 | ||
10501 | case 'd': | |
10502 | case 'D': | |
10503 | case 'r': | |
10504 | case 'R': | |
10505 | prec = 4; | |
10506 | break; | |
10507 | ||
10508 | case 'x': | |
10509 | case 'X': | |
10510 | case 'p': | |
10511 | case 'P': | |
10512 | prec = 5; | |
10513 | break; | |
10514 | ||
10515 | default: | |
10516 | *size = 0; | |
10517 | return "Bad call to MD_ATOF()"; | |
10518 | } | |
10519 | t = atof_ieee (input_line_pointer, type, words); | |
10520 | if (t) | |
10521 | input_line_pointer = t; | |
10522 | *size = prec * sizeof (LITTLENUM_TYPE); | |
10523 | ||
10524 | for (word = words + prec - 1; prec--;) | |
10525 | { | |
10526 | md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); | |
10527 | lit += sizeof (LITTLENUM_TYPE); | |
10528 | } | |
10529 | return 0; | |
10530 | } | |
10531 | ||
10532 | /* Round up a section's size to the appropriate boundary. */ | |
10533 | valueT | |
10534 | md_section_align (seg, size) | |
10535 | segT seg; | |
10536 | valueT size; | |
10537 | { | |
10538 | int align = bfd_get_section_alignment (stdoutput, seg); | |
197865e8 | 10539 | valueT mask = ((valueT) 1 << align) - 1; |
800eeca4 JW |
10540 | |
10541 | return (size + mask) & ~mask; | |
10542 | } | |
10543 | ||
10544 | /* Handle ia64 specific semantics of the align directive. */ | |
10545 | ||
0a9ef439 | 10546 | void |
800eeca4 | 10547 | ia64_md_do_align (n, fill, len, max) |
91a2ae2a RH |
10548 | int n ATTRIBUTE_UNUSED; |
10549 | const char *fill ATTRIBUTE_UNUSED; | |
2434f565 | 10550 | int len ATTRIBUTE_UNUSED; |
91a2ae2a | 10551 | int max ATTRIBUTE_UNUSED; |
800eeca4 | 10552 | { |
0a9ef439 | 10553 | if (subseg_text_p (now_seg)) |
800eeca4 | 10554 | ia64_flush_insns (); |
0a9ef439 | 10555 | } |
800eeca4 | 10556 | |
0a9ef439 RH |
10557 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
10558 | of an rs_align_code fragment. */ | |
800eeca4 | 10559 | |
0a9ef439 RH |
10560 | void |
10561 | ia64_handle_align (fragp) | |
10562 | fragS *fragp; | |
10563 | { | |
10564 | /* Use mfi bundle of nops with no stop bits. */ | |
10565 | static const unsigned char be_nop[] | |
10566 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, | |
10567 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; | |
10568 | static const unsigned char le_nop[] | |
10569 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, | |
10570 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; | |
10571 | ||
10572 | int bytes; | |
10573 | char *p; | |
10574 | ||
10575 | if (fragp->fr_type != rs_align_code) | |
10576 | return; | |
10577 | ||
10578 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
10579 | p = fragp->fr_literal + fragp->fr_fix; | |
10580 | ||
10581 | /* Make sure we are on a 16-byte boundary, in case someone has been | |
10582 | putting data into a text section. */ | |
10583 | if (bytes & 15) | |
10584 | { | |
10585 | int fix = bytes & 15; | |
10586 | memset (p, 0, fix); | |
10587 | p += fix; | |
10588 | bytes -= fix; | |
10589 | fragp->fr_fix += fix; | |
800eeca4 JW |
10590 | } |
10591 | ||
0a9ef439 RH |
10592 | memcpy (p, (target_big_endian ? be_nop : le_nop), 16); |
10593 | fragp->fr_var = 16; | |
800eeca4 | 10594 | } |