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[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
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800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
e0c9811a 2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
c67e42c9 78 FUNC_PC_RELATIVE,
800eeca4
JW		 79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
e0c9811a
JW		 113 /* The following pseudo-registers are used for unwind directives only: */
114 REG_PSP,
115 REG_PRIUNAT,
800eeca4
JW		 116 REG_NUM
117 };
118
119enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127/* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131struct label_fix
132 {
133 struct label_fix *next;
134 struct symbol *sym;
135 };
136
137extern int target_big_endian;
138
139/* Characters which always start a comment. */
140const char comment_chars[] = "";
141
142/* Characters which start a comment at the beginning of a line. */
143const char line_comment_chars[] = "#";
144
145/* Characters which may be used to separate multiple commands on a
146 single line. */
147const char line_separator_chars[] = ";";
148
149/* Characters which are used to indicate an exponent in a floating
150 point number. */
151const char EXP_CHARS[] = "eE";
152
153/* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
157/* ia64-specific option processing: */
158
159const char *md_shortopts = "M:N:x::";
160
161struct option md_longopts[] =
162 {
163 { NULL, no_argument, NULL, 0}
164 };
165
166size_t md_longopts_size = sizeof (md_longopts);
167
168static struct
169 {
170 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
171 struct hash_control *reg_hash; /* register name hash table */
172 struct hash_control *dynreg_hash; /* dynamic register hash table */
173 struct hash_control *const_hash; /* constant hash table */
174 struct hash_control *entry_hash; /* code entry hint hash table */
175
176 symbolS *regsym[REG_NUM];
177
178 /* If X_op is != O_absent, the registername for the instruction's
179 qualifying predicate. If NULL, p0 is assumed for instructions
180 that are predicatable. */
181 expressionS qp;
182
183 unsigned int
184 manual_bundling : 1,
185 debug_dv: 1,
186 detect_dv: 1,
187 explicit_mode : 1, /* which mode we're in */
188 default_explicit_mode : 1, /* which mode is the default */
189 mode_explicitly_set : 1, /* was the current mode explicitly set? */
190 auto_align : 1;
191
192 /* Each bundle consists of up to three instructions. We keep
193 track of four most recent instructions so we can correctly set
194 the end_of_insn_group for the last instruction in a bundle. */
195 int curr_slot;
196 int num_slots_in_use;
197 struct slot
198 {
199 unsigned int
200 end_of_insn_group : 1,
201 manual_bundling_on : 1,
202 manual_bundling_off : 1;
203 signed char user_template; /* user-selected template, if any */
204 unsigned char qp_regno; /* qualifying predicate */
205 /* This duplicates a good fraction of "struct fix" but we
206 can't use a "struct fix" instead since we can't call
207 fix_new_exp() until we know the address of the instruction. */
208 int num_fixups;
209 struct insn_fix
210 {
211 bfd_reloc_code_real_type code;
212 enum ia64_opnd opnd; /* type of operand in need of fix */
213 unsigned int is_pcrel : 1; /* is operand pc-relative? */
214 expressionS expr; /* the value to be inserted */
215 }
216 fixup[2]; /* at most two fixups per insn */
217 struct ia64_opcode *idesc;
218 struct label_fix *label_fixups;
219 struct unw_rec_list *unwind_record; /* Unwind directive. */
220 expressionS opnd[6];
221 char *src_file;
222 unsigned int src_line;
223 struct dwarf2_line_info debug_line;
224 }
225 slot[NUM_SLOTS];
226
227 segT last_text_seg;
228
229 struct dynreg
230 {
231 struct dynreg *next; /* next dynamic register */
232 const char *name;
233 unsigned short base; /* the base register number */
234 unsigned short num_regs; /* # of registers in this set */
235 }
236 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
237
238 flagword flags; /* ELF-header flags */
239
240 struct mem_offset {
241 unsigned hint:1; /* is this hint currently valid? */
242 bfd_vma offset; /* mem.offset offset */
243 bfd_vma base; /* mem.offset base */
244 } mem_offset;
245
246 int path; /* number of alt. entry points seen */
247 const char **entry_labels; /* labels of all alternate paths in
248 the current DV-checking block. */
249 int maxpaths; /* size currently allocated for
250 entry_labels */
251 }
252md;
253
254/* application registers: */
255
e0c9811a
JW		 256#define AR_K0 0
257#define AR_K7 7
258#define AR_RSC 16
259#define AR_BSP 17
260#define AR_BSPSTORE 18
261#define AR_RNAT 19
262#define AR_UNAT 36
263#define AR_FPSR 40
264#define AR_ITC 44
265#define AR_PFS 64
266#define AR_LC 65
800eeca4
JW		 267
268static const struct
269 {
270 const char *name;
271 int regnum;
272 }
273ar[] =
274 {
275 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
276 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
277 {"ar.rsc", 16}, {"ar.bsp", 17},
278 {"ar.bspstore", 18}, {"ar.rnat", 19},
279 {"ar.fcr", 21}, {"ar.eflag", 24},
280 {"ar.csd", 25}, {"ar.ssd", 26},
281 {"ar.cflg", 27}, {"ar.fsr", 28},
282 {"ar.fir", 29}, {"ar.fdr", 30},
283 {"ar.ccv", 32}, {"ar.unat", 36},
284 {"ar.fpsr", 40}, {"ar.itc", 44},
285 {"ar.pfs", 64}, {"ar.lc", 65},
286 {"ar.ec", 66},
287 };
288
289#define CR_IPSR 16
290#define CR_ISR 17
291#define CR_IIP 19
292#define CR_IFA 20
293#define CR_ITIR 21
294#define CR_IIPA 22
295#define CR_IFS 23
296#define CR_IIM 24
297#define CR_IHA 25
298#define CR_IVR 65
299#define CR_TPR 66
300#define CR_EOI 67
301#define CR_IRR0 68
302#define CR_IRR3 71
303#define CR_LRR0 80
304#define CR_LRR1 81
305
306/* control registers: */
307static const struct
308 {
309 const char *name;
310 int regnum;
311 }
312cr[] =
313 {
314 {"cr.dcr", 0},
315 {"cr.itm", 1},
316 {"cr.iva", 2},
317 {"cr.pta", 8},
318 {"cr.gpta", 9},
319 {"cr.ipsr", 16},
320 {"cr.isr", 17},
321 {"cr.iip", 19},
322 {"cr.ifa", 20},
323 {"cr.itir", 21},
324 {"cr.iipa", 22},
325 {"cr.ifs", 23},
326 {"cr.iim", 24},
327 {"cr.iha", 25},
328 {"cr.lid", 64},
329 {"cr.ivr", 65},
330 {"cr.tpr", 66},
331 {"cr.eoi", 67},
332 {"cr.irr0", 68},
333 {"cr.irr1", 69},
334 {"cr.irr2", 70},
335 {"cr.irr3", 71},
336 {"cr.itv", 72},
337 {"cr.pmv", 73},
338 {"cr.cmcv", 74},
339 {"cr.lrr0", 80},
340 {"cr.lrr1", 81}
341 };
342
343#define PSR_MFL 4
344#define PSR_IC 13
345#define PSR_DFL 18
346#define PSR_CPL 32
347
348static const struct const_desc
349 {
350 const char *name;
351 valueT value;
352 }
353const_bits[] =
354 {
355 /* PSR constant masks: */
356
357 /* 0: reserved */
358 {"psr.be", ((valueT) 1) << 1},
359 {"psr.up", ((valueT) 1) << 2},
360 {"psr.ac", ((valueT) 1) << 3},
361 {"psr.mfl", ((valueT) 1) << 4},
362 {"psr.mfh", ((valueT) 1) << 5},
363 /* 6-12: reserved */
364 {"psr.ic", ((valueT) 1) << 13},
365 {"psr.i", ((valueT) 1) << 14},
366 {"psr.pk", ((valueT) 1) << 15},
367 /* 16: reserved */
368 {"psr.dt", ((valueT) 1) << 17},
369 {"psr.dfl", ((valueT) 1) << 18},
370 {"psr.dfh", ((valueT) 1) << 19},
371 {"psr.sp", ((valueT) 1) << 20},
372 {"psr.pp", ((valueT) 1) << 21},
373 {"psr.di", ((valueT) 1) << 22},
374 {"psr.si", ((valueT) 1) << 23},
375 {"psr.db", ((valueT) 1) << 24},
376 {"psr.lp", ((valueT) 1) << 25},
377 {"psr.tb", ((valueT) 1) << 26},
378 {"psr.rt", ((valueT) 1) << 27},
379 /* 28-31: reserved */
380 /* 32-33: cpl (current privilege level) */
381 {"psr.is", ((valueT) 1) << 34},
382 {"psr.mc", ((valueT) 1) << 35},
383 {"psr.it", ((valueT) 1) << 36},
384 {"psr.id", ((valueT) 1) << 37},
385 {"psr.da", ((valueT) 1) << 38},
386 {"psr.dd", ((valueT) 1) << 39},
387 {"psr.ss", ((valueT) 1) << 40},
388 /* 41-42: ri (restart instruction) */
389 {"psr.ed", ((valueT) 1) << 43},
390 {"psr.bn", ((valueT) 1) << 44},
391 };
392
393/* indirect register-sets/memory: */
394
395static const struct
396 {
397 const char *name;
398 int regnum;
399 }
400indirect_reg[] =
401 {
402 { "CPUID", IND_CPUID },
403 { "cpuid", IND_CPUID },
404 { "dbr", IND_DBR },
405 { "dtr", IND_DTR },
406 { "itr", IND_ITR },
407 { "ibr", IND_IBR },
408 { "msr", IND_MSR },
409 { "pkr", IND_PKR },
410 { "pmc", IND_PMC },
411 { "pmd", IND_PMD },
412 { "rr", IND_RR },
413 };
414
415/* Pseudo functions used to indicate relocation types (these functions
416 start with an at sign (@). */
417static struct
418 {
419 const char *name;
420 enum pseudo_type
421 {
422 PSEUDO_FUNC_NONE,
423 PSEUDO_FUNC_RELOC,
424 PSEUDO_FUNC_CONST,
e0c9811a 425 PSEUDO_FUNC_REG,
800eeca4
JW		 426 PSEUDO_FUNC_FLOAT
427 }
428 type;
429 union
430 {
431 unsigned long ival;
432 symbolS *sym;
433 }
434 u;
435 }
436pseudo_func[] =
437 {
438 /* reloc pseudo functions (these must come first!): */
439 { "fptr", PSEUDO_FUNC_RELOC },
440 { "gprel", PSEUDO_FUNC_RELOC },
441 { "ltoff", PSEUDO_FUNC_RELOC },
c67e42c9 442 { "pcrel", PSEUDO_FUNC_RELOC },
800eeca4
JW		 443 { "pltoff", PSEUDO_FUNC_RELOC },
444 { "secrel", PSEUDO_FUNC_RELOC },
445 { "segrel", PSEUDO_FUNC_RELOC },
446 { "ltv", PSEUDO_FUNC_RELOC },
447 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
448
449 /* mbtype4 constants: */
450 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
451 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
452 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
453 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
454 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
455
456 /* fclass constants: */
bf3ca999 457 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 458 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
459 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
460 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
461 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
462 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
463 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
464 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
465 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 466
467 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a
JW		 468
469 /* unwind-related constants: */
470 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
471 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
472 { "nt", PSEUDO_FUNC_CONST, { 2 } },
473
474 /* unwind-related registers: */
475 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 476 };
477
478/* 41-bit nop opcodes (one per unit): */
479static const bfd_vma nop[IA64_NUM_UNITS] =
480 {
481 0x0000000000LL, /* NIL => break 0 */
482 0x0008000000LL, /* I-unit nop */
483 0x0008000000LL, /* M-unit nop */
484 0x4000000000LL, /* B-unit nop */
485 0x0008000000LL, /* F-unit nop */
486 0x0008000000LL, /* L-"unit" nop */
487 0x0008000000LL, /* X-unit nop */
488 };
489
490/* Can't be `const' as it's passed to input routines (which have the
491 habit of setting temporary sentinels. */
492static char special_section_name[][20] =
493 {
494 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
495 {".IA_64.unwind"}, {".IA_64.unwind_info"}
496 };
497
498/* The best template for a particular sequence of up to three
499 instructions: */
500#define N IA64_NUM_TYPES
501static unsigned char best_template[N][N][N];
502#undef N
503
504/* Resource dependencies currently in effect */
505static struct rsrc {
506 int depind; /* dependency index */
507 const struct ia64_dependency *dependency; /* actual dependency */
508 unsigned specific:1, /* is this a specific bit/regno? */
509 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
510 int index; /* specific regno/bit within dependency */
511 int note; /* optional qualifying note (0 if none) */
512#define STATE_NONE 0
513#define STATE_STOP 1
514#define STATE_SRLZ 2
515 int insn_srlz; /* current insn serialization state */
516 int data_srlz; /* current data serialization state */
517 int qp_regno; /* qualifying predicate for this usage */
518 char *file; /* what file marked this dependency */
519 int line; /* what line marked this dependency */
520 struct mem_offset mem_offset; /* optional memory offset hint */
521 int path; /* corresponding code entry index */
522} *regdeps = NULL;
523static int regdepslen = 0;
524static int regdepstotlen = 0;
525static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
526static const char *dv_sem[] = { "none", "implied", "impliedf",
527 "data", "instr", "specific", "other" };
528
529/* Current state of PR mutexation */
530static struct qpmutex {
531 valueT prmask;
532 int path;
533} *qp_mutexes = NULL; /* QP mutex bitmasks */
534static int qp_mutexeslen = 0;
535static int qp_mutexestotlen = 0;
536static valueT qp_safe_across_calls = 0;
537
538/* Current state of PR implications */
539static struct qp_imply {
540 unsigned p1:6;
541 unsigned p2:6;
542 unsigned p2_branched:1;
543 int path;
544} *qp_implies = NULL;
545static int qp_implieslen = 0;
546static int qp_impliestotlen = 0;
547
548/* Keep track of static GR values so that indirect register usage can
549 sometimes be tracked. */
550static struct gr {
551 unsigned known:1;
552 int path;
553 valueT value;
554} gr_values[128] = {{ 1, 0 }};
555
556/* These are the routines required to output the various types of
557 unwind records. */
558
559typedef struct unw_rec_list {
560 unwind_record r;
e0c9811a 561 unsigned long slot_number;
800eeca4
JW		 562 struct unw_rec_list *next;
563} unw_rec_list;
564
565#define SLOT_NUM_NOT_SET -1
566
e0c9811a
JW		 567static struct
568{
569 unsigned long next_slot_number;
570
571 /* Maintain a list of unwind entries for the current function. */
572 unw_rec_list *list;
573 unw_rec_list *tail;
800eeca4 574
e0c9811a
JW		 575 /* Any unwind entires that should be attached to the current slot
576 that an insn is being constructed for. */
577 unw_rec_list *current_entry;
800eeca4 578
e0c9811a
JW		 579 /* These are used to create the unwind table entry for this function. */
580 symbolS *proc_start;
581 symbolS *proc_end;
582 symbolS *info; /* pointer to unwind info */
583 symbolS *personality_routine;
800eeca4 584
e0c9811a
JW		 585 /* TRUE if processing unwind directives in a prologue region. */
586 int prologue;
587} unwind;
800eeca4
JW		 588
589typedef void (*vbyte_func) PARAMS ((int, char *, char *));
590
591/* Forward delarations: */
592static int ar_is_in_integer_unit PARAMS ((int regnum));
593static void set_section PARAMS ((char *name));
594static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
595 unsigned int, unsigned int));
596static void dot_radix PARAMS ((int));
597static void dot_special_section PARAMS ((int));
598static void dot_proc PARAMS ((int));
599static void dot_fframe PARAMS ((int));
600static void dot_vframe PARAMS ((int));
601static void dot_save PARAMS ((int));
602static void dot_restore PARAMS ((int));
603static void dot_handlerdata PARAMS ((int));
604static void dot_unwentry PARAMS ((int));
605static void dot_altrp PARAMS ((int));
e0c9811a 606static void dot_savemem PARAMS ((int));
800eeca4
JW		 607static void dot_saveg PARAMS ((int));
608static void dot_savef PARAMS ((int));
609static void dot_saveb PARAMS ((int));
610static void dot_savegf PARAMS ((int));
611static void dot_spill PARAMS ((int));
612static void dot_unwabi PARAMS ((int));
613static void dot_personality PARAMS ((int));
614static void dot_body PARAMS ((int));
615static void dot_prologue PARAMS ((int));
616static void dot_endp PARAMS ((int));
617static void dot_template PARAMS ((int));
618static void dot_regstk PARAMS ((int));
619static void dot_rot PARAMS ((int));
620static void dot_byteorder PARAMS ((int));
621static void dot_psr PARAMS ((int));
622static void dot_alias PARAMS ((int));
623static void dot_ln PARAMS ((int));
624static char *parse_section_name PARAMS ((void));
625static void dot_xdata PARAMS ((int));
626static void stmt_float_cons PARAMS ((int));
627static void stmt_cons_ua PARAMS ((int));
628static void dot_xfloat_cons PARAMS ((int));
629static void dot_xstringer PARAMS ((int));
630static void dot_xdata_ua PARAMS ((int));
631static void dot_xfloat_cons_ua PARAMS ((int));
632static void dot_pred_rel PARAMS ((int));
633static void dot_reg_val PARAMS ((int));
634static void dot_dv_mode PARAMS ((int));
635static void dot_entry PARAMS ((int));
636static void dot_mem_offset PARAMS ((int));
e0c9811a 637static void add_unwind_entry PARAMS((unw_rec_list *ptr));
800eeca4
JW		 638static symbolS* declare_register PARAMS ((const char *name, int regnum));
639static void declare_register_set PARAMS ((const char *, int, int));
640static unsigned int operand_width PARAMS ((enum ia64_opnd));
641static int operand_match PARAMS ((const struct ia64_opcode *idesc,
642 int index, expressionS *e));
643static int parse_operand PARAMS ((expressionS *e));
644static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
645static void build_insn PARAMS ((struct slot *, bfd_vma *));
646static void emit_one_bundle PARAMS ((void));
647static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
648static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
649 bfd_reloc_code_real_type r_type));
650static void insn_group_break PARAMS ((int, int, int));
651static void add_qp_mutex PARAMS((valueT mask));
652static void add_qp_imply PARAMS((int p1, int p2));
653static void clear_qp_branch_flag PARAMS((valueT mask));
654static void clear_qp_mutex PARAMS((valueT mask));
655static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
656static void clear_register_values PARAMS ((void));
657static void print_dependency PARAMS ((const char *action, int depind));
658static int is_conditional_branch PARAMS ((struct ia64_opcode *));
659static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
660static int check_dv PARAMS((struct ia64_opcode *idesc));
661static void check_dependencies PARAMS((struct ia64_opcode *));
662static void mark_resources PARAMS((struct ia64_opcode *));
663static void update_dependencies PARAMS((struct ia64_opcode *));
664static void note_register_values PARAMS((struct ia64_opcode *));
665static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
666static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
667static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
668
669/* Determine if application register REGNUM resides in the integer
670 unit (as opposed to the memory unit). */
671static int
672ar_is_in_integer_unit (reg)
673 int reg;
674{
675 reg -= REG_AR;
676
677 return (reg == 64 /* pfs */
678 || reg == 65 /* lc */
679 || reg == 66 /* ec */
680 /* ??? ias accepts and puts these in the integer unit. */
681 || (reg >= 112 && reg <= 127));
682}
683
684/* Switch to section NAME and create section if necessary. It's
685 rather ugly that we have to manipulate input_line_pointer but I
686 don't see any other way to accomplish the same thing without
687 changing obj-elf.c (which may be the Right Thing, in the end). */
688static void
689set_section (name)
690 char *name;
691{
692 char *saved_input_line_pointer;
693
694 saved_input_line_pointer = input_line_pointer;
695 input_line_pointer = name;
696 obj_elf_section (0);
697 input_line_pointer = saved_input_line_pointer;
698}
699
700/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
701
702flagword
703ia64_elf_section_flags (flags, attr, type)
704 flagword flags;
705 int attr, type;
706{
707 if (attr & SHF_IA_64_SHORT)
708 flags |= SEC_SMALL_DATA;
709 return flags;
710}
711
712static unsigned int
713set_regstack (ins, locs, outs, rots)
714 unsigned int ins, locs, outs, rots;
715{
716 unsigned int sof; /* size of frame */
717
718 sof = ins + locs + outs;
719 if (sof > 96)
720 {
721 as_bad ("Size of frame exceeds maximum of 96 registers");
722 return 0;
723 }
724 if (rots > sof)
725 {
726 as_warn ("Size of rotating registers exceeds frame size");
727 return 0;
728 }
729 md.in.base = REG_GR + 32;
730 md.loc.base = md.in.base + ins;
731 md.out.base = md.loc.base + locs;
732
733 md.in.num_regs = ins;
734 md.loc.num_regs = locs;
735 md.out.num_regs = outs;
736 md.rot.num_regs = rots;
737 return sof;
738}
739
740void
741ia64_flush_insns ()
742{
743 struct label_fix *lfix;
744 segT saved_seg;
745 subsegT saved_subseg;
746
747 if (!md.last_text_seg)
748 return;
749
750 saved_seg = now_seg;
751 saved_subseg = now_subseg;
752
753 subseg_set (md.last_text_seg, 0);
754
755 while (md.num_slots_in_use > 0)
756 emit_one_bundle (); /* force out queued instructions */
757
758 /* In case there are labels following the last instruction, resolve
759 those now: */
760 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
761 {
762 S_SET_VALUE (lfix->sym, frag_now_fix ());
763 symbol_set_frag (lfix->sym, frag_now);
764 }
765 CURR_SLOT.label_fixups = 0;
766
767 subseg_set (saved_seg, saved_subseg);
768}
769
770void
771ia64_do_align (nbytes)
772 int nbytes;
773{
774 char *saved_input_line_pointer = input_line_pointer;
775
776 input_line_pointer = "";
777 s_align_bytes (nbytes);
778 input_line_pointer = saved_input_line_pointer;
779}
780
781void
782ia64_cons_align (nbytes)
783 int nbytes;
784{
785 if (md.auto_align)
786 {
787 char *saved_input_line_pointer = input_line_pointer;
788 input_line_pointer = "";
789 s_align_bytes (nbytes);
790 input_line_pointer = saved_input_line_pointer;
791 }
792}
793
794/* Output COUNT bytes to a memory location. */
795static unsigned char *vbyte_mem_ptr = NULL;
796
797void
798output_vbyte_mem (count, ptr, comment)
799 int count;
800 char *ptr;
801 char *comment;
802{
803 int x;
804 if (vbyte_mem_ptr == NULL)
805 abort ();
806
807 if (count == 0)
808 return;
809 for (x = 0; x < count; x++)
810 *(vbyte_mem_ptr++) = ptr[x];
811}
812
813/* Count the number of bytes required for records. */
814static int vbyte_count = 0;
815void
816count_output (count, ptr, comment)
817 int count;
818 char *ptr;
819 char *comment;
820{
821 vbyte_count += count;
822}
823
824static void
825output_R1_format (f, rtype, rlen)
826 vbyte_func f;
827 unw_record_type rtype;
828 int rlen;
829{
e0c9811a 830 int r = 0;
800eeca4
JW		 831 char byte;
832 if (rlen > 0x1f)
833 {
834 output_R3_format (f, rtype, rlen);
835 return;
836 }
800eeca4 837
e0c9811a
JW		 838 if (rtype == body)
839 r = 1;
840 else if (rtype != prologue)
841 as_bad ("record type is not valid");
842
800eeca4
JW		 843 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
844 (*f) (1, &byte, NULL);
845}
846
847static void
848output_R2_format (f, mask, grsave, rlen)
849 vbyte_func f;
850 int mask, grsave;
851 unsigned long rlen;
852{
853 char bytes[20];
854 int count = 2;
855 mask = (mask & 0x0f);
856 grsave = (grsave & 0x7f);
857
858 bytes[0] = (UNW_R2 | (mask >> 1));
859 bytes[1] = (((mask & 0x01) << 7) | grsave);
860 count += output_leb128 (bytes + 2, rlen, 0);
861 (*f) (count, bytes, NULL);
862}
863
864static void
865output_R3_format (f, rtype, rlen)
866 vbyte_func f;
867 unw_record_type rtype;
868 unsigned long rlen;
869{
e0c9811a 870 int r = 0, count;
800eeca4
JW		 871 char bytes[20];
872 if (rlen <= 0x1f)
873 {
874 output_R1_format (f, rtype, rlen);
875 return;
876 }
e0c9811a
JW		 877
878 if (rtype == body)
879 r = 1;
880 else if (rtype != prologue)
881 as_bad ("record type is not valid");
800eeca4
JW		 882 bytes[0] = (UNW_R3 | r);
883 count = output_leb128 (bytes + 1, rlen, 0);
884 (*f) (count + 1, bytes, NULL);
885}
886
887static void
888output_P1_format (f, brmask)
889 vbyte_func f;
890 int brmask;
891{
892 char byte;
893 byte = UNW_P1 | (brmask & 0x1f);
894 (*f) (1, &byte, NULL);
895}
896
897static void
898output_P2_format (f, brmask, gr)
899 vbyte_func f;
900 int brmask;
901 int gr;
902{
903 char bytes[2];
904 brmask = (brmask & 0x1f);
905 bytes[0] = UNW_P2 | (brmask >> 1);
906 bytes[1] = (((brmask & 1) << 7) | gr);
907 (*f) (2, bytes, NULL);
908}
909
910static void
911output_P3_format (f, rtype, reg)
912 vbyte_func f;
913 unw_record_type rtype;
914 int reg;
915{
916 char bytes[2];
e0c9811a 917 int r = 0;
800eeca4
JW		 918 reg = (reg & 0x7f);
919 switch (rtype)
920 {
921 case psp_gr:
922 r = 0;
923 break;
924 case rp_gr:
925 r = 1;
926 break;
927 case pfs_gr:
928 r = 2;
929 break;
930 case preds_gr:
931 r = 3;
932 break;
933 case unat_gr:
934 r = 4;
935 break;
936 case lc_gr:
937 r = 5;
938 break;
939 case rp_br:
940 r = 6;
941 break;
942 case rnat_gr:
943 r = 7;
944 break;
945 case bsp_gr:
946 r = 8;
947 break;
948 case bspstore_gr:
949 r = 9;
950 break;
951 case fpsr_gr:
952 r = 10;
953 break;
954 case priunat_gr:
955 r = 11;
956 break;
957 default:
958 as_bad ("Invalid record type for P3 format.");
959 }
960 bytes[0] = (UNW_P3 | (r >> 1));
961 bytes[1] = (((r & 1) << 7) | reg);
962 (*f) (2, bytes, NULL);
963}
964
965
966static void
e0c9811a 967output_P4_format (f, imask, imask_size)
800eeca4 968 vbyte_func f;
e0c9811a
JW		 969 unsigned char *imask;
970 unsigned long imask_size;
800eeca4 971{
e0c9811a
JW		 972 imask[0] = UNW_P4;
973 (*f) (imask_size, imask, NULL);
800eeca4
JW		 974}
975
976static void
977output_P5_format (f, grmask, frmask)
978 vbyte_func f;
979 int grmask;
980 unsigned long frmask;
981{
982 char bytes[4];
983 grmask = (grmask & 0x0f);
984
985 bytes[0] = UNW_P5;
986 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
987 bytes[2] = ((frmask & 0x0000ff00) >> 8);
988 bytes[3] = (frmask & 0x000000ff);
989 (*f) (4, bytes, NULL);
990}
991
992static void
993output_P6_format (f, rtype, rmask)
994 vbyte_func f;
995 unw_record_type rtype;
996 int rmask;
997{
998 char byte;
e0c9811a
JW		 999 int r = 0;
1000
1001 if (rtype == gr_mem)
1002 r = 1;
1003 else if (rtype != fr_mem)
1004 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1005 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1006 (*f) (1, &byte, NULL);
1007}
1008
1009static void
1010output_P7_format (f, rtype, w1, w2)
1011 vbyte_func f;
1012 unw_record_type rtype;
1013 unsigned long w1;
1014 unsigned long w2;
1015{
1016 char bytes[20];
1017 int count = 1;
e0c9811a 1018 int r = 0;
800eeca4
JW		 1019 count += output_leb128 (bytes + 1, w1, 0);
1020 switch (rtype)
1021 {
1022 case mem_stack_f:
e4c58b25
JW		 1023 r = 0;
1024 count += output_leb128 (bytes + count, w2 >> 4, 0);
800eeca4
JW		 1025 break;
1026 case mem_stack_v:
1027 r = 1;
1028 break;
1029 case spill_base:
1030 r = 2;
1031 break;
1032 case psp_sprel:
1033 r = 3;
1034 break;
1035 case rp_when:
1036 r = 4;
1037 break;
1038 case rp_psprel:
1039 r = 5;
1040 break;
1041 case pfs_when:
1042 r = 6;
1043 break;
1044 case pfs_psprel:
1045 r = 7;
1046 break;
1047 case preds_when:
1048 r = 8;
1049 break;
1050 case preds_psprel:
1051 r = 9;
1052 break;
1053 case lc_when:
1054 r = 10;
1055 break;
1056 case lc_psprel:
1057 r = 11;
1058 break;
1059 case unat_when:
1060 r = 12;
1061 break;
1062 case unat_psprel:
1063 r = 13;
1064 break;
1065 case fpsr_when:
1066 r = 14;
1067 break;
1068 case fpsr_psprel:
1069 r = 15;
1070 break;
e0c9811a
JW		 1071 default:
1072 break;
800eeca4
JW		 1073 }
1074 bytes[0] = (UNW_P7 | r);
1075 (*f) (count, bytes, NULL);
1076}
1077
1078static void
1079output_P8_format (f, rtype, t)
1080 vbyte_func f;
1081 unw_record_type rtype;
1082 unsigned long t;
1083{
1084 char bytes[20];
e0c9811a 1085 int r = 0;
800eeca4
JW		 1086 int count = 2;
1087 bytes[0] = UNW_P8;
1088 switch (rtype)
1089 {
1090 case rp_sprel:
1091 r = 1;
1092 break;
1093 case pfs_sprel:
1094 r = 2;
1095 break;
1096 case preds_sprel:
1097 r = 3;
1098 break;
1099 case lc_sprel:
1100 r = 4;
1101 break;
1102 case unat_sprel:
1103 r = 5;
1104 break;
1105 case fpsr_sprel:
1106 r = 6;
1107 break;
1108 case bsp_when:
1109 r = 7;
1110 break;
1111 case bsp_psprel:
1112 r = 8;
1113 break;
1114 case bsp_sprel:
1115 r = 9;
1116 break;
1117 case bspstore_when:
1118 r = 10;
1119 break;
1120 case bspstore_psprel:
1121 r = 11;
1122 break;
1123 case bspstore_sprel:
1124 r = 12;
1125 break;
1126 case rnat_when:
1127 r = 13;
1128 break;
1129 case rnat_psprel:
1130 r = 14;
1131 break;
1132 case rnat_sprel:
1133 r = 15;
1134 break;
1135 case priunat_when_gr:
1136 r = 16;
1137 break;
1138 case priunat_psprel:
1139 r = 17;
1140 break;
1141 case priunat_sprel:
1142 r = 18;
1143 break;
1144 case priunat_when_mem:
1145 r = 19;
1146 break;
e0c9811a
JW		 1147 default:
1148 break;
800eeca4
JW		 1149 }
1150 bytes[1] = r;
1151 count += output_leb128 (bytes + 2, t, 0);
1152 (*f) (count, bytes, NULL);
1153}
1154
1155static void
1156output_P9_format (f, grmask, gr)
1157 vbyte_func f;
1158 int grmask;
1159 int gr;
1160{
1161 char bytes[3];
1162 bytes[0] = UNW_P9;
1163 bytes[1] = (grmask & 0x0f);
1164 bytes[2] = (gr & 0x7f);
1165 (*f) (3, bytes, NULL);
1166}
1167
1168static void
1169output_P10_format (f, abi, context)
1170 vbyte_func f;
1171 int abi;
1172 int context;
1173{
1174 char bytes[3];
1175 bytes[0] = UNW_P10;
1176 bytes[1] = (abi & 0xff);
1177 bytes[2] = (context & 0xff);
1178 (*f) (3, bytes, NULL);
1179}
1180
1181static void
1182output_B1_format (f, rtype, label)
1183 vbyte_func f;
1184 unw_record_type rtype;
1185 unsigned long label;
1186{
1187 char byte;
e0c9811a 1188 int r = 0;
800eeca4
JW		 1189 if (label > 0x1f)
1190 {
1191 output_B4_format (f, rtype, label);
1192 return;
1193 }
e0c9811a
JW		 1194 if (rtype == copy_state)
1195 r = 1;
1196 else if (rtype != label_state)
1197 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1198
1199 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1200 (*f) (1, &byte, NULL);
1201}
1202
1203static void
1204output_B2_format (f, ecount, t)
1205 vbyte_func f;
1206 unsigned long ecount;
1207 unsigned long t;
1208{
1209 char bytes[20];
1210 int count = 1;
1211 if (ecount > 0x1f)
1212 {
1213 output_B3_format (f, ecount, t);
1214 return;
1215 }
1216 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1217 count += output_leb128 (bytes + 1, t, 0);
1218 (*f) (count, bytes, NULL);
1219}
1220
1221static void
1222output_B3_format (f, ecount, t)
1223 vbyte_func f;
1224 unsigned long ecount;
1225 unsigned long t;
1226{
1227 char bytes[20];
1228 int count = 1;
1229 if (ecount <= 0x1f)
1230 {
1231 output_B2_format (f, ecount, t);
1232 return;
1233 }
1234 bytes[0] = UNW_B3;
1235 count += output_leb128 (bytes + 1, t, 0);
1236 count += output_leb128 (bytes + count, ecount, 0);
1237 (*f) (count, bytes, NULL);
1238}
1239
1240static void
1241output_B4_format (f, rtype, label)
1242 vbyte_func f;
1243 unw_record_type rtype;
1244 unsigned long label;
1245{
1246 char bytes[20];
e0c9811a 1247 int r = 0;
800eeca4
JW		 1248 int count = 1;
1249 if (label <= 0x1f)
1250 {
1251 output_B1_format (f, rtype, label);
1252 return;
1253 }
e0c9811a
JW		 1254
1255 if (rtype == copy_state)
1256 r = 1;
1257 else if (rtype != label_state)
1258 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1259
1260 bytes[0] = (UNW_B4 | (r << 3));
1261 count += output_leb128 (bytes + 1, label, 0);
1262 (*f) (count, bytes, NULL);
1263}
1264
1265static char
e0c9811a
JW		 1266format_ab_reg (ab, reg)
1267 int ab;
800eeca4
JW		 1268 int reg;
1269{
1270 int ret;
e0c9811a 1271 ab = (ab & 3);
800eeca4 1272 reg = (reg & 0x1f);
e0c9811a 1273 ret = (ab << 5) | reg;
800eeca4
JW		 1274 return ret;
1275}
1276
1277static void
e0c9811a 1278output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1279 vbyte_func f;
1280 unw_record_type rtype;
e0c9811a 1281 int ab, reg;
800eeca4
JW		 1282 unsigned long t;
1283 unsigned long w1;
1284{
1285 char bytes[20];
e0c9811a 1286 int r = 0;
800eeca4
JW		 1287 int count = 2;
1288 bytes[0] = UNW_X1;
e0c9811a
JW		 1289
1290 if (rtype == spill_sprel)
1291 r = 1;
1292 else if (rtype != spill_psprel)
1293 as_bad ("Invalid record type for format X1");
1294 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1295 count += output_leb128 (bytes + 2, t, 0);
1296 count += output_leb128 (bytes + count, w1, 0);
1297 (*f) (count, bytes, NULL);
1298}
1299
1300static void
e0c9811a 1301output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1302 vbyte_func f;
e0c9811a 1303 int ab, reg;
800eeca4
JW		 1304 int x, y, treg;
1305 unsigned long t;
1306{
1307 char bytes[20];
800eeca4
JW		 1308 int count = 3;
1309 bytes[0] = UNW_X2;
e0c9811a 1310 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1311 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1312 count += output_leb128 (bytes + 3, t, 0);
1313 (*f) (count, bytes, NULL);
1314}
1315
1316static void
e0c9811a 1317output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1318 vbyte_func f;
1319 unw_record_type rtype;
1320 int qp;
e0c9811a 1321 int ab, reg;
800eeca4
JW		 1322 unsigned long t;
1323 unsigned long w1;
1324{
1325 char bytes[20];
e0c9811a 1326 int r = 0;
800eeca4 1327 int count = 3;
e0c9811a
JW		 1328 bytes[0] = UNW_X3;
1329
1330 if (rtype == spill_sprel_p)
1331 r = 1;
1332 else if (rtype != spill_psprel_p)
1333 as_bad ("Invalid record type for format X3");
800eeca4 1334 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1335 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1336 count += output_leb128 (bytes + 3, t, 0);
1337 count += output_leb128 (bytes + count, w1, 0);
1338 (*f) (count, bytes, NULL);
1339}
1340
1341static void
e0c9811a 1342output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1343 vbyte_func f;
1344 int qp;
e0c9811a 1345 int ab, reg;
800eeca4
JW		 1346 int x, y, treg;
1347 unsigned long t;
1348{
1349 char bytes[20];
800eeca4 1350 int count = 4;
e0c9811a 1351 bytes[0] = UNW_X4;
800eeca4 1352 bytes[1] = (qp & 0x3f);
e0c9811a 1353 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1354 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1355 count += output_leb128 (bytes + 4, t, 0);
1356 (*f) (count, bytes, NULL);
1357}
1358
1359/* This function allocates a record list structure, and initializes fields. */
1360static unw_rec_list *
1361alloc_record (unw_record_type t)
1362{
1363 unw_rec_list *ptr;
1364 ptr = xmalloc (sizeof (*ptr));
1365 ptr->next = NULL;
1366 ptr->slot_number = SLOT_NUM_NOT_SET;
1367 ptr->r.type = t;
1368 return ptr;
1369}
1370
800eeca4
JW		 1371/* This function frees an entire list of record structures. */
1372void
1373free_list_records (unw_rec_list *first)
1374{
1375 unw_rec_list *ptr;
1376 for (ptr = first; ptr != NULL; )
1377 {
1378 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1379
1380 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1381 && tmp->r.record.r.mask.i)
1382 free (tmp->r.record.r.mask.i);
1383
800eeca4
JW		 1384 ptr = ptr->next;
1385 free (tmp);
1386 }
1387}
1388
1389static unw_rec_list *
1390output_prologue ()
1391{
1392 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1393 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1394 return ptr;
1395}
1396
1397static unw_rec_list *
1398output_prologue_gr (saved_mask, reg)
1399 unsigned int saved_mask;
1400 unsigned int reg;
1401{
1402 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1403 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1404 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1405 ptr->r.record.r.grsave = reg;
1406 return ptr;
1407}
1408
1409static unw_rec_list *
1410output_body ()
1411{
1412 unw_rec_list *ptr = alloc_record (body);
1413 return ptr;
1414}
1415
1416static unw_rec_list *
1417output_mem_stack_f (size)
1418 unsigned int size;
1419{
1420 unw_rec_list *ptr = alloc_record (mem_stack_f);
1421 ptr->r.record.p.size = size;
1422 return ptr;
1423}
1424
1425static unw_rec_list *
1426output_mem_stack_v ()
1427{
1428 unw_rec_list *ptr = alloc_record (mem_stack_v);
1429 return ptr;
1430}
1431
1432static unw_rec_list *
1433output_psp_gr (gr)
1434 unsigned int gr;
1435{
1436 unw_rec_list *ptr = alloc_record (psp_gr);
1437 ptr->r.record.p.gr = gr;
1438 return ptr;
1439}
1440
1441static unw_rec_list *
1442output_psp_sprel (offset)
1443 unsigned int offset;
1444{
1445 unw_rec_list *ptr = alloc_record (psp_sprel);
e0c9811a 1446 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1447 return ptr;
1448}
1449
1450static unw_rec_list *
1451output_rp_when ()
1452{
1453 unw_rec_list *ptr = alloc_record (rp_when);
1454 return ptr;
1455}
1456
1457static unw_rec_list *
1458output_rp_gr (gr)
1459 unsigned int gr;
1460{
1461 unw_rec_list *ptr = alloc_record (rp_gr);
1462 ptr->r.record.p.gr = gr;
1463 return ptr;
1464}
1465
1466static unw_rec_list *
1467output_rp_br (br)
1468 unsigned int br;
1469{
1470 unw_rec_list *ptr = alloc_record (rp_br);
1471 ptr->r.record.p.br = br;
1472 return ptr;
1473}
1474
1475static unw_rec_list *
1476output_rp_psprel (offset)
1477 unsigned int offset;
1478{
1479 unw_rec_list *ptr = alloc_record (rp_psprel);
e0c9811a 1480 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1481 return ptr;
1482}
1483
1484static unw_rec_list *
1485output_rp_sprel (offset)
1486 unsigned int offset;
1487{
1488 unw_rec_list *ptr = alloc_record (rp_sprel);
e0c9811a 1489 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1490 return ptr;
1491}
1492
1493static unw_rec_list *
1494output_pfs_when ()
1495{
1496 unw_rec_list *ptr = alloc_record (pfs_when);
1497 return ptr;
1498}
1499
1500static unw_rec_list *
1501output_pfs_gr (gr)
1502 unsigned int gr;
1503{
1504 unw_rec_list *ptr = alloc_record (pfs_gr);
1505 ptr->r.record.p.gr = gr;
1506 return ptr;
1507}
1508
1509static unw_rec_list *
1510output_pfs_psprel (offset)
1511 unsigned int offset;
1512{
1513 unw_rec_list *ptr = alloc_record (pfs_psprel);
e0c9811a 1514 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1515 return ptr;
1516}
1517
1518static unw_rec_list *
1519output_pfs_sprel (offset)
1520 unsigned int offset;
1521{
1522 unw_rec_list *ptr = alloc_record (pfs_sprel);
e0c9811a 1523 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1524 return ptr;
1525}
1526
1527static unw_rec_list *
1528output_preds_when ()
1529{
1530 unw_rec_list *ptr = alloc_record (preds_when);
1531 return ptr;
1532}
1533
1534static unw_rec_list *
1535output_preds_gr (gr)
1536 unsigned int gr;
1537{
1538 unw_rec_list *ptr = alloc_record (preds_gr);
1539 ptr->r.record.p.gr = gr;
1540 return ptr;
1541}
1542
1543static unw_rec_list *
1544output_preds_psprel (offset)
1545 unsigned int offset;
1546{
1547 unw_rec_list *ptr = alloc_record (preds_psprel);
e0c9811a 1548 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1549 return ptr;
1550}
1551
1552static unw_rec_list *
1553output_preds_sprel (offset)
1554 unsigned int offset;
1555{
1556 unw_rec_list *ptr = alloc_record (preds_sprel);
e0c9811a 1557 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1558 return ptr;
1559}
1560
1561static unw_rec_list *
1562output_fr_mem (mask)
1563 unsigned int mask;
1564{
1565 unw_rec_list *ptr = alloc_record (fr_mem);
1566 ptr->r.record.p.rmask = mask;
1567 return ptr;
1568}
1569
1570static unw_rec_list *
1571output_frgr_mem (gr_mask, fr_mask)
1572 unsigned int gr_mask;
1573 unsigned int fr_mask;
1574{
1575 unw_rec_list *ptr = alloc_record (frgr_mem);
1576 ptr->r.record.p.grmask = gr_mask;
1577 ptr->r.record.p.frmask = fr_mask;
1578 return ptr;
1579}
1580
1581static unw_rec_list *
1582output_gr_gr (mask, reg)
1583 unsigned int mask;
1584 unsigned int reg;
1585{
1586 unw_rec_list *ptr = alloc_record (gr_gr);
1587 ptr->r.record.p.grmask = mask;
1588 ptr->r.record.p.gr = reg;
1589 return ptr;
1590}
1591
1592static unw_rec_list *
1593output_gr_mem (mask)
1594 unsigned int mask;
1595{
1596 unw_rec_list *ptr = alloc_record (gr_mem);
1597 ptr->r.record.p.rmask = mask;
1598 return ptr;
1599}
1600
1601static unw_rec_list *
1602output_br_mem (unsigned int mask)
1603{
1604 unw_rec_list *ptr = alloc_record (br_mem);
1605 ptr->r.record.p.brmask = mask;
1606 return ptr;
1607}
1608
1609static unw_rec_list *
1610output_br_gr (save_mask, reg)
1611 unsigned int save_mask;
1612 unsigned int reg;
1613{
1614 unw_rec_list *ptr = alloc_record (br_gr);
1615 ptr->r.record.p.brmask = save_mask;
1616 ptr->r.record.p.gr = reg;
1617 return ptr;
1618}
1619
1620static unw_rec_list *
1621output_spill_base (offset)
1622 unsigned int offset;
1623{
1624 unw_rec_list *ptr = alloc_record (spill_base);
e0c9811a 1625 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1626 return ptr;
1627}
1628
1629static unw_rec_list *
1630output_unat_when ()
1631{
1632 unw_rec_list *ptr = alloc_record (unat_when);
1633 return ptr;
1634}
1635
1636static unw_rec_list *
1637output_unat_gr (gr)
1638 unsigned int gr;
1639{
1640 unw_rec_list *ptr = alloc_record (unat_gr);
1641 ptr->r.record.p.gr = gr;
1642 return ptr;
1643}
1644
1645static unw_rec_list *
1646output_unat_psprel (offset)
1647 unsigned int offset;
1648{
1649 unw_rec_list *ptr = alloc_record (unat_psprel);
e0c9811a 1650 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1651 return ptr;
1652}
1653
1654static unw_rec_list *
1655output_unat_sprel (offset)
1656 unsigned int offset;
1657{
1658 unw_rec_list *ptr = alloc_record (unat_sprel);
e0c9811a 1659 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1660 return ptr;
1661}
1662
1663static unw_rec_list *
1664output_lc_when ()
1665{
1666 unw_rec_list *ptr = alloc_record (lc_when);
1667 return ptr;
1668}
1669
1670static unw_rec_list *
1671output_lc_gr (gr)
1672 unsigned int gr;
1673{
1674 unw_rec_list *ptr = alloc_record (lc_gr);
1675 ptr->r.record.p.gr = gr;
1676 return ptr;
1677}
1678
1679static unw_rec_list *
1680output_lc_psprel (offset)
1681 unsigned int offset;
1682{
1683 unw_rec_list *ptr = alloc_record (lc_psprel);
e0c9811a 1684 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1685 return ptr;
1686}
1687
1688static unw_rec_list *
1689output_lc_sprel (offset)
1690 unsigned int offset;
1691{
1692 unw_rec_list *ptr = alloc_record (lc_sprel);
e0c9811a 1693 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1694 return ptr;
1695}
1696
1697static unw_rec_list *
1698output_fpsr_when ()
1699{
1700 unw_rec_list *ptr = alloc_record (fpsr_when);
1701 return ptr;
1702}
1703
1704static unw_rec_list *
1705output_fpsr_gr (gr)
1706 unsigned int gr;
1707{
1708 unw_rec_list *ptr = alloc_record (fpsr_gr);
1709 ptr->r.record.p.gr = gr;
1710 return ptr;
1711}
1712
1713static unw_rec_list *
1714output_fpsr_psprel (offset)
1715 unsigned int offset;
1716{
1717 unw_rec_list *ptr = alloc_record (fpsr_psprel);
e0c9811a 1718 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1719 return ptr;
1720}
1721
1722static unw_rec_list *
1723output_fpsr_sprel (offset)
1724 unsigned int offset;
1725{
1726 unw_rec_list *ptr = alloc_record (fpsr_sprel);
e0c9811a 1727 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1728 return ptr;
1729}
1730
1731static unw_rec_list *
1732output_priunat_when_gr ()
1733{
1734 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1735 return ptr;
1736}
1737
1738static unw_rec_list *
1739output_priunat_when_mem ()
1740{
1741 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1742 return ptr;
1743}
1744
1745static unw_rec_list *
1746output_priunat_gr (gr)
1747 unsigned int gr;
1748{
1749 unw_rec_list *ptr = alloc_record (priunat_gr);
1750 ptr->r.record.p.gr = gr;
1751 return ptr;
1752}
1753
1754static unw_rec_list *
1755output_priunat_psprel (offset)
1756 unsigned int offset;
1757{
1758 unw_rec_list *ptr = alloc_record (priunat_psprel);
e0c9811a 1759 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1760 return ptr;
1761}
1762
1763static unw_rec_list *
1764output_priunat_sprel (offset)
1765 unsigned int offset;
1766{
1767 unw_rec_list *ptr = alloc_record (priunat_sprel);
e0c9811a 1768 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1769 return ptr;
1770}
1771
1772static unw_rec_list *
1773output_bsp_when ()
1774{
1775 unw_rec_list *ptr = alloc_record (bsp_when);
1776 return ptr;
1777}
1778
1779static unw_rec_list *
1780output_bsp_gr (gr)
1781 unsigned int gr;
1782{
1783 unw_rec_list *ptr = alloc_record (bsp_gr);
1784 ptr->r.record.p.gr = gr;
1785 return ptr;
1786}
1787
1788static unw_rec_list *
1789output_bsp_psprel (offset)
1790 unsigned int offset;
1791{
1792 unw_rec_list *ptr = alloc_record (bsp_psprel);
e0c9811a 1793 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1794 return ptr;
1795}
1796
1797static unw_rec_list *
1798output_bsp_sprel (offset)
1799 unsigned int offset;
1800{
1801 unw_rec_list *ptr = alloc_record (bsp_sprel);
e0c9811a 1802 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1803 return ptr;
1804}
1805
1806static unw_rec_list *
1807output_bspstore_when ()
1808{
1809 unw_rec_list *ptr = alloc_record (bspstore_when);
1810 return ptr;
1811}
1812
1813static unw_rec_list *
1814output_bspstore_gr (gr)
1815 unsigned int gr;
1816{
1817 unw_rec_list *ptr = alloc_record (bspstore_gr);
1818 ptr->r.record.p.gr = gr;
1819 return ptr;
1820}
1821
1822static unw_rec_list *
1823output_bspstore_psprel (offset)
1824 unsigned int offset;
1825{
1826 unw_rec_list *ptr = alloc_record (bspstore_psprel);
e0c9811a 1827 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1828 return ptr;
1829}
1830
1831static unw_rec_list *
1832output_bspstore_sprel (offset)
1833 unsigned int offset;
1834{
1835 unw_rec_list *ptr = alloc_record (bspstore_sprel);
e0c9811a 1836 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1837 return ptr;
1838}
1839
1840static unw_rec_list *
1841output_rnat_when ()
1842{
1843 unw_rec_list *ptr = alloc_record (rnat_when);
1844 return ptr;
1845}
1846
1847static unw_rec_list *
1848output_rnat_gr (gr)
1849 unsigned int gr;
1850{
1851 unw_rec_list *ptr = alloc_record (rnat_gr);
1852 ptr->r.record.p.gr = gr;
1853 return ptr;
1854}
1855
1856static unw_rec_list *
1857output_rnat_psprel (offset)
1858 unsigned int offset;
1859{
1860 unw_rec_list *ptr = alloc_record (rnat_psprel);
e0c9811a 1861 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1862 return ptr;
1863}
1864
1865static unw_rec_list *
1866output_rnat_sprel (offset)
1867 unsigned int offset;
1868{
1869 unw_rec_list *ptr = alloc_record (rnat_sprel);
e0c9811a 1870 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1871 return ptr;
1872}
1873
1874static unw_rec_list *
e0c9811a
JW		 1875output_unwabi (abi, context)
1876 unsigned long abi;
1877 unsigned long context;
800eeca4 1878{
e0c9811a
JW		 1879 unw_rec_list *ptr = alloc_record (unwabi);
1880 ptr->r.record.p.abi = abi;
1881 ptr->r.record.p.context = context;
800eeca4
JW		 1882 return ptr;
1883}
1884
1885static unw_rec_list *
e0c9811a 1886output_epilogue (unsigned long ecount)
800eeca4 1887{
e0c9811a
JW		 1888 unw_rec_list *ptr = alloc_record (epilogue);
1889 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 1890 return ptr;
1891}
1892
1893static unw_rec_list *
e0c9811a 1894output_label_state (unsigned long label)
800eeca4 1895{
e0c9811a
JW		 1896 unw_rec_list *ptr = alloc_record (label_state);
1897 ptr->r.record.b.label = label;
800eeca4
JW		 1898 return ptr;
1899}
1900
1901static unw_rec_list *
e0c9811a
JW		 1902output_copy_state (unsigned long label)
1903{
1904 unw_rec_list *ptr = alloc_record (copy_state);
1905 ptr->r.record.b.label = label;
1906 return ptr;
1907}
1908
1909static unw_rec_list *
1910output_spill_psprel (ab, reg, offset)
1911 unsigned int ab;
800eeca4
JW		 1912 unsigned int reg;
1913 unsigned int offset;
1914{
1915 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 1916 ptr->r.record.x.ab = ab;
800eeca4 1917 ptr->r.record.x.reg = reg;
e0c9811a 1918 ptr->r.record.x.pspoff = offset/4;
800eeca4
JW		 1919 return ptr;
1920}
1921
1922static unw_rec_list *
e0c9811a
JW		 1923output_spill_sprel (ab, reg, offset)
1924 unsigned int ab;
800eeca4
JW		 1925 unsigned int reg;
1926 unsigned int offset;
1927{
1928 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 1929 ptr->r.record.x.ab = ab;
800eeca4 1930 ptr->r.record.x.reg = reg;
e0c9811a 1931 ptr->r.record.x.spoff = offset/4;
800eeca4
JW		 1932 return ptr;
1933}
1934
1935static unw_rec_list *
e0c9811a
JW		 1936output_spill_psprel_p (ab, reg, offset, predicate)
1937 unsigned int ab;
800eeca4
JW		 1938 unsigned int reg;
1939 unsigned int offset;
1940 unsigned int predicate;
1941{
1942 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 1943 ptr->r.record.x.ab = ab;
800eeca4 1944 ptr->r.record.x.reg = reg;
e0c9811a 1945 ptr->r.record.x.pspoff = offset/4;
800eeca4
JW		 1946 ptr->r.record.x.qp = predicate;
1947 return ptr;
1948}
1949
1950static unw_rec_list *
e0c9811a
JW		 1951output_spill_sprel_p (ab, reg, offset, predicate)
1952 unsigned int ab;
800eeca4
JW		 1953 unsigned int reg;
1954 unsigned int offset;
1955 unsigned int predicate;
1956{
1957 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 1958 ptr->r.record.x.ab = ab;
800eeca4 1959 ptr->r.record.x.reg = reg;
e0c9811a 1960 ptr->r.record.x.spoff = offset/4;
800eeca4
JW		 1961 ptr->r.record.x.qp = predicate;
1962 return ptr;
1963}
1964
1965static unw_rec_list *
e0c9811a
JW		 1966output_spill_reg (ab, reg, targ_reg, xy)
1967 unsigned int ab;
800eeca4
JW		 1968 unsigned int reg;
1969 unsigned int targ_reg;
1970 unsigned int xy;
1971{
1972 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 1973 ptr->r.record.x.ab = ab;
800eeca4
JW		 1974 ptr->r.record.x.reg = reg;
1975 ptr->r.record.x.treg = targ_reg;
1976 ptr->r.record.x.xy = xy;
1977 return ptr;
1978}
1979
1980static unw_rec_list *
e0c9811a
JW		 1981output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
1982 unsigned int ab;
800eeca4
JW		 1983 unsigned int reg;
1984 unsigned int targ_reg;
1985 unsigned int xy;
1986 unsigned int predicate;
1987{
1988 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 1989 ptr->r.record.x.ab = ab;
800eeca4
JW		 1990 ptr->r.record.x.reg = reg;
1991 ptr->r.record.x.treg = targ_reg;
1992 ptr->r.record.x.xy = xy;
1993 ptr->r.record.x.qp = predicate;
1994 return ptr;
1995}
1996
1997/* Given a unw_rec_list process the correct format with the
1998 specified function. */
1999static void
2000process_one_record (ptr, f)
2001 unw_rec_list *ptr;
2002 vbyte_func f;
2003{
e0c9811a
JW		 2004 unsigned long fr_mask, gr_mask;
2005
800eeca4
JW		 2006 switch (ptr->r.type)
2007 {
e0c9811a
JW		 2008 case gr_mem:
2009 case fr_mem:
2010 case br_mem:
2011 case frgr_mem:
2012 /* these are taken care of by prologue/prologue_gr */
2013 break;
2014
2015 case prologue_gr:
800eeca4 2016 case prologue:
e0c9811a
JW		 2017 if (ptr->r.type == prologue_gr)
2018 output_R2_format (f, ptr->r.record.r.grmask,
2019 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2020 else
2021 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2022
2023 /* output descriptor(s) for union of register spills (if any): */
2024 gr_mask = ptr->r.record.r.mask.gr_mem;
2025 fr_mask = ptr->r.record.r.mask.fr_mem;
2026 if (fr_mask)
2027 {
2028 if ((fr_mask & ~0xfUL) == 0)
2029 output_P6_format (f, fr_mem, fr_mask);
2030 else
2031 {
2032 output_P5_format (f, gr_mask, fr_mask);
2033 gr_mask = 0;
2034 }
2035 }
2036 if (gr_mask)
2037 output_P6_format (f, gr_mem, gr_mask);
2038 if (ptr->r.record.r.mask.br_mem)
2039 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2040
2041 /* output imask descriptor if necessary: */
2042 if (ptr->r.record.r.mask.i)
2043 output_P4_format (f, ptr->r.record.r.mask.i,
2044 ptr->r.record.r.imask_size);
2045 break;
2046
800eeca4
JW		 2047 case body:
2048 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2049 break;
800eeca4
JW		 2050 case mem_stack_f:
2051 case mem_stack_v:
2052 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2053 ptr->r.record.p.size);
2054 break;
2055 case psp_gr:
2056 case rp_gr:
2057 case pfs_gr:
2058 case preds_gr:
2059 case unat_gr:
2060 case lc_gr:
2061 case fpsr_gr:
2062 case priunat_gr:
2063 case bsp_gr:
2064 case bspstore_gr:
2065 case rnat_gr:
2066 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2067 break;
2068 case rp_br:
2069 output_P3_format (f, rp_br, ptr->r.record.p.br);
2070 break;
2071 case psp_sprel:
2072 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2073 break;
2074 case rp_when:
2075 case pfs_when:
2076 case preds_when:
2077 case unat_when:
2078 case lc_when:
2079 case fpsr_when:
2080 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2081 break;
2082 case rp_psprel:
2083 case pfs_psprel:
2084 case preds_psprel:
2085 case unat_psprel:
2086 case lc_psprel:
2087 case fpsr_psprel:
2088 case spill_base:
2089 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2090 break;
2091 case rp_sprel:
2092 case pfs_sprel:
2093 case preds_sprel:
2094 case unat_sprel:
2095 case lc_sprel:
2096 case fpsr_sprel:
2097 case priunat_sprel:
2098 case bsp_sprel:
2099 case bspstore_sprel:
2100 case rnat_sprel:
2101 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2102 break;
800eeca4
JW		 2103 case gr_gr:
2104 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2105 break;
800eeca4
JW		 2106 case br_gr:
2107 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2108 break;
2109 case spill_mask:
2110 as_bad ("spill_mask record unimplemented.");
2111 break;
2112 case priunat_when_gr:
2113 case priunat_when_mem:
2114 case bsp_when:
2115 case bspstore_when:
2116 case rnat_when:
2117 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2118 break;
2119 case priunat_psprel:
2120 case bsp_psprel:
2121 case bspstore_psprel:
2122 case rnat_psprel:
2123 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2124 break;
e0c9811a
JW		 2125 case unwabi:
2126 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2127 break;
800eeca4 2128 case epilogue:
e0c9811a 2129 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
800eeca4
JW		 2130 break;
2131 case label_state:
800eeca4 2132 case copy_state:
e0c9811a 2133 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
800eeca4
JW		 2134 break;
2135 case spill_psprel:
e0c9811a
JW		 2136 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2137 ptr->r.record.x.reg, ptr->r.record.x.t,
2138 ptr->r.record.x.pspoff);
2139 break;
800eeca4 2140 case spill_sprel:
e0c9811a
JW		 2141 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2142 ptr->r.record.x.reg, ptr->r.record.x.t,
2143 ptr->r.record.x.spoff);
2144 break;
800eeca4 2145 case spill_reg:
e0c9811a
JW		 2146 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2147 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2148 ptr->r.record.x.treg, ptr->r.record.x.t);
2149 break;
800eeca4 2150 case spill_psprel_p:
e0c9811a
JW		 2151 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2152 ptr->r.record.x.ab, ptr->r.record.x.reg,
2153 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2154 break;
800eeca4 2155 case spill_sprel_p:
e0c9811a
JW		 2156 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2157 ptr->r.record.x.ab, ptr->r.record.x.reg,
2158 ptr->r.record.x.t, ptr->r.record.x.spoff);
2159 break;
800eeca4 2160 case spill_reg_p:
e0c9811a
JW		 2161 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2162 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2163 ptr->r.record.x.xy, ptr->r.record.x.treg,
2164 ptr->r.record.x.t);
800eeca4
JW		 2165 break;
2166 default:
2167 as_bad ("record_type_not_valid");
2168 break;
2169 }
2170}
2171
2172/* Given a unw_rec_list list, process all the records with
2173 the specified function. */
2174static void
2175process_unw_records (list, f)
2176 unw_rec_list *list;
2177 vbyte_func f;
2178{
2179 unw_rec_list *ptr;
2180 for (ptr = list; ptr; ptr = ptr->next)
2181 process_one_record (ptr, f);
2182}
2183
2184/* Determine the size of a record list in bytes. */
2185static int
2186calc_record_size (list)
2187 unw_rec_list *list;
2188{
2189 vbyte_count = 0;
2190 process_unw_records (list, count_output);
2191 return vbyte_count;
2192}
2193
e0c9811a
JW		 2194/* Update IMASK bitmask to reflect the fact that one or more registers
2195 of type TYPE are saved starting at instruction with index T. If N
2196 bits are set in REGMASK, it is assumed that instructions T through
2197 T+N-1 save these registers.
2198
2199 TYPE values:
2200 0: no save
2201 1: instruction saves next fp reg
2202 2: instruction saves next general reg
2203 3: instruction saves next branch reg */
2204static void
2205set_imask (region, regmask, t, type)
2206 unw_rec_list *region;
2207 unsigned long regmask;
2208 unsigned long t;
2209 unsigned int type;
2210{
2211 unsigned char *imask;
2212 unsigned long imask_size;
2213 unsigned int i;
2214 int pos;
2215
2216 imask = region->r.record.r.mask.i;
2217 imask_size = region->r.record.r.imask_size;
2218 if (!imask)
2219 {
2220 imask_size = (region->r.record.r.rlen*2 + 7)/8 + 1;
2221 imask = xmalloc (imask_size);
2222 memset (imask, 0, imask_size);
2223
2224 region->r.record.r.imask_size = imask_size;
2225 region->r.record.r.mask.i = imask;
2226 }
2227
2228 i = (t/4) + 1;
2229 pos = 2*(3 - t%4);
2230 while (regmask)
2231 {
2232 if (i >= imask_size)
2233 {
2234 as_bad ("Ignoring attempt to spill beyond end of region");
2235 return;
2236 }
2237
2238 imask[i] |= (type & 0x3) << pos;
2239
2240 regmask &= (regmask - 1);
2241 pos -= 2;
2242 if (pos < 0)
2243 {
2244 pos = 0;
2245 ++i;
2246 }
2247 }
2248}
2249
2250static int
2251count_bits (unsigned long mask)
2252{
2253 int n = 0;
2254
2255 while (mask)
2256 {
2257 mask &= mask - 1;
2258 ++n;
2259 }
2260 return n;
2261}
2262
2263unsigned long
2264slot_index (unsigned long slot_addr, unsigned long first_addr)
2265{
2266 return (3*((slot_addr >> 4) - (first_addr >> 4))
2267 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2268}
2269
800eeca4
JW		 2270/* Given a complete record list, process any records which have
2271 unresolved fields, (ie length counts for a prologue). After
2272 this has been run, all neccessary information should be available
2273 within each record to generate an image. */
2274static void
2275fixup_unw_records (list)
2276 unw_rec_list *list;
2277{
e0c9811a
JW		 2278 unw_rec_list *ptr, *region = 0;
2279 unsigned long first_addr = 0, rlen = 0, t;
2280
800eeca4
JW		 2281 for (ptr = list; ptr; ptr = ptr->next)
2282 {
2283 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2284 as_bad (" Insn slot not set in unwind record.");
e0c9811a 2285 t = slot_index (ptr->slot_number, first_addr);
800eeca4
JW		 2286 switch (ptr->r.type)
2287 {
2288 case prologue:
2289 case prologue_gr:
2290 case body:
2291 {
2292 unw_rec_list *last;
e0c9811a 2293 int size, dir_len = 0;
800eeca4 2294 unsigned long last_addr;
e0c9811a 2295
800eeca4
JW		 2296 first_addr = ptr->slot_number;
2297 ptr->slot_number = 0;
2298 /* Find either the next body/prologue start, or the end of
2299 the list, and determine the size of the region. */
e0c9811a
JW		 2300 last_addr = unwind.next_slot_number;
2301 for (last = ptr->next; last != NULL; last = last->next)
2302 if (last->r.type == prologue || last->r.type == prologue_gr
2303 || last->r.type == body)
800eeca4 2304 {
e0c9811a 2305 last_addr = last->slot_number;
800eeca4
JW		 2306 break;
2307 }
e0c9811a
JW		 2308 else if (!last->next)
2309 {
2310 /* In the absence of an explicit .body directive,
2311 the prologue ends after the last instruction
2312 covered by an unwind directive. */
2313 if (ptr->r.type != body)
2314 {
2315 last_addr = last->slot_number;
2316 switch (last->r.type)
2317 {
2318 case frgr_mem:
2319 dir_len = (count_bits (last->r.record.p.frmask)
2320 + count_bits (last->r.record.p.grmask));
2321 break;
2322 case fr_mem:
2323 case gr_mem:
2324 dir_len += count_bits (last->r.record.p.rmask);
2325 break;
2326 case br_mem:
2327 case br_gr:
2328 dir_len += count_bits (last->r.record.p.brmask);
2329 break;
2330 case gr_gr:
2331 dir_len += count_bits (last->r.record.p.grmask);
2332 break;
2333 default:
2334 dir_len = 1;
2335 break;
2336 }
2337 }
2338 break;
2339 }
2340 size = slot_index (last_addr, first_addr) + dir_len;
2341 rlen = ptr->r.record.r.rlen = size;
2342 region = ptr;
800eeca4
JW		 2343 break;
2344 }
e0c9811a
JW		 2345 case epilogue:
2346 ptr->r.record.b.t = rlen - 1 - t;
2347 break;
2348
800eeca4
JW		 2349 case mem_stack_f:
2350 case mem_stack_v:
2351 case rp_when:
2352 case pfs_when:
2353 case preds_when:
2354 case unat_when:
2355 case lc_when:
2356 case fpsr_when:
2357 case priunat_when_gr:
2358 case priunat_when_mem:
2359 case bsp_when:
2360 case bspstore_when:
2361 case rnat_when:
e0c9811a
JW		 2362 ptr->r.record.p.t = t;
2363 break;
2364
2365 case spill_reg:
2366 case spill_sprel:
2367 case spill_psprel:
2368 case spill_reg_p:
2369 case spill_sprel_p:
2370 case spill_psprel_p:
2371 ptr->r.record.x.t = t;
2372 break;
2373
2374 case frgr_mem:
2375 if (!region)
2376 {
2377 as_bad ("frgr_mem record before region record!\n");
2378 return;
2379 }
2380 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2381 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2382 set_imask (region, ptr->r.record.p.frmask, t, 1);
2383 set_imask (region, ptr->r.record.p.grmask, t, 2);
2384 break;
2385 case fr_mem:
2386 if (!region)
2387 {
2388 as_bad ("fr_mem record before region record!\n");
2389 return;
2390 }
2391 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2392 set_imask (region, ptr->r.record.p.rmask, t, 1);
2393 break;
2394 case gr_mem:
2395 if (!region)
2396 {
2397 as_bad ("gr_mem record before region record!\n");
2398 return;
2399 }
2400 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2401 set_imask (region, ptr->r.record.p.rmask, t, 2);
2402 break;
2403 case br_mem:
2404 if (!region)
2405 {
2406 as_bad ("br_mem record before region record!\n");
2407 return;
2408 }
2409 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2410 set_imask (region, ptr->r.record.p.brmask, t, 3);
2411 break;
2412
2413 case gr_gr:
2414 if (!region)
2415 {
2416 as_bad ("gr_gr record before region record!\n");
2417 return;
2418 }
2419 set_imask (region, ptr->r.record.p.grmask, t, 2);
2420 break;
2421 case br_gr:
2422 if (!region)
2423 {
2424 as_bad ("br_gr record before region record!\n");
2425 return;
2426 }
2427 set_imask (region, ptr->r.record.p.brmask, t, 3);
2428 break;
2429
2430 default:
2431 break;
800eeca4
JW		 2432 }
2433 }
2434}
2435
2436/* Generate an unwind image from a record list. Returns the number of
2437 bytes in the resulting image. The memory image itselof is returned
2438 in the 'ptr' parameter. */
2439static int
2440output_unw_records (list, ptr)
2441 unw_rec_list *list;
2442 void **ptr;
2443{
2444 int size, x, extra = 0;
2445 unsigned char *mem;
2446
2447 fixup_unw_records (list);
2448 size = calc_record_size (list);
2449
2450 /* pad to 8 byte boundry. */
2451 x = size % 8;
2452 if (x != 0)
2453 extra = 8 - x;
2454 /* Add 8 for the header + 8 more bytes for the personality offset. */
2455 mem = xmalloc (size + extra + 16);
2456
2457 vbyte_mem_ptr = mem + 8;
2458 /* Clear the padding area and personality. */
2459 memset (mem + 8 + size, 0 , extra + 8);
2460 /* Initialize the header area. */
e4c58b25
JW		 2461 md_number_to_chars (mem, ( ((bfd_vma) 1 << 48) /* version */
2462 | ((bfd_vma) 3 << 32) /* U & E handler flags */
2463 | ((size + extra) / 8)), /* length (dwords) */
2464 8);
800eeca4
JW		 2465
2466 process_unw_records (list, output_vbyte_mem);
2467
2468 *ptr = mem;
2469 return size + extra + 16;
2470}
2471
e0c9811a
JW		 2472static int
2473convert_expr_to_ab_reg (e, ab, regp)
2474 expressionS *e;
2475 unsigned int *ab;
2476 unsigned int *regp;
2477{
2478 unsigned int reg;
2479
2480 if (e->X_op != O_register)
2481 return 0;
2482
2483 reg = e->X_add_number;
2484 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2485 {
2486 *ab = 0;
2487 *regp = reg - REG_GR;
2488 }
2489 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2490 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2491 {
2492 *ab = 1;
2493 *regp = reg - REG_FR;
2494 }
2495 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2496 {
2497 *ab = 2;
2498 *regp = reg - REG_BR;
2499 }
2500 else
2501 {
2502 *ab = 3;
2503 switch (reg)
2504 {
2505 case REG_PR: *regp = 0; break;
2506 case REG_PSP: *regp = 1; break;
2507 case REG_PRIUNAT: *regp = 2; break;
2508 case REG_BR + 0: *regp = 3; break;
2509 case REG_AR + AR_BSP: *regp = 4; break;
2510 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2511 case REG_AR + AR_RNAT: *regp = 6; break;
2512 case REG_AR + AR_UNAT: *regp = 7; break;
2513 case REG_AR + AR_FPSR: *regp = 8; break;
2514 case REG_AR + AR_PFS: *regp = 9; break;
2515 case REG_AR + AR_LC: *regp = 10; break;
2516
2517 default:
2518 return 0;
2519 }
2520 }
2521 return 1;
2522}
2523
2524static int
2525convert_expr_to_xy_reg (e, xy, regp)
2526 expressionS *e;
2527 unsigned int *xy;
2528 unsigned int *regp;
2529{
2530 unsigned int reg;
2531
2532 if (e->X_op != O_register)
2533 return 0;
2534
2535 reg = e->X_add_number;
2536
2537 if (reg >= REG_GR && reg <= REG_GR + 127)
2538 {
2539 *xy = 0;
2540 *regp = reg - REG_GR;
2541 }
2542 else if (reg >= REG_FR && reg <= REG_FR + 127)
2543 {
2544 *xy = 1;
2545 *regp = reg - REG_FR;
2546 }
2547 else if (reg >= REG_BR && reg <= REG_BR + 7)
2548 {
2549 *xy = 2;
2550 *regp = reg - REG_BR;
2551 }
2552 else
2553 return -1;
2554 return 1;
2555}
2556
800eeca4
JW		 2557static void
2558dot_radix (dummy)
2559 int dummy;
2560{
2561 int radix;
2562
2563 SKIP_WHITESPACE ();
2564 radix = *input_line_pointer++;
2565
2566 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2567 {
2568 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2569 ignore_rest_of_line ();
2570 return;
2571 }
2572}
2573
2574/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2575static void
2576dot_special_section (which)
2577 int which;
2578{
2579 set_section ((char *) special_section_name[which]);
2580}
2581
2582static void
2583add_unwind_entry (ptr)
2584 unw_rec_list *ptr;
2585{
e0c9811a
JW		 2586 if (unwind.tail)
2587 unwind.tail->next = ptr;
800eeca4 2588 else
e0c9811a
JW		 2589 unwind.list = ptr;
2590 unwind.tail = ptr;
800eeca4
JW		 2591
2592 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2593 if (unwind.current_entry == NULL)
2594 unwind.current_entry = ptr;
800eeca4
JW		 2595}
2596
2597static void
2598dot_fframe (dummy)
2599 int dummy;
2600{
2601 expressionS e;
e0c9811a 2602
800eeca4
JW		 2603 parse_operand (&e);
2604
2605 if (e.X_op != O_constant)
2606 as_bad ("Operand to .fframe must be a constant");
2607 else
e0c9811a
JW		 2608 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2609}
2610
2611static void
2612dot_vframe (dummy)
2613 int dummy;
2614{
2615 expressionS e;
2616 unsigned reg;
2617
2618 parse_operand (&e);
2619 reg = e.X_add_number - REG_GR;
2620 if (e.X_op == O_register && reg < 128)
800eeca4 2621 {
e0c9811a
JW		 2622 add_unwind_entry (output_mem_stack_v ());
2623 add_unwind_entry (output_psp_gr (reg));
800eeca4 2624 }
e0c9811a
JW		 2625 else
2626 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2627}
2628
2629static void
e0c9811a 2630dot_vframesp (dummy)
800eeca4
JW		 2631 int dummy;
2632{
e0c9811a
JW		 2633 expressionS e;
2634
2635 parse_operand (&e);
2636 if (e.X_op == O_constant)
2637 {
2638 add_unwind_entry (output_mem_stack_v ());
2639 add_unwind_entry (output_psp_sprel (e.X_add_number));
2640 }
2641 else
2642 as_bad ("First operand to .vframesp must be a general register");
2643}
2644
2645static void
2646dot_vframepsp (dummy)
2647 int dummy;
2648{
2649 expressionS e;
2650
2651 parse_operand (&e);
2652 if (e.X_op == O_constant)
2653 {
2654 add_unwind_entry (output_mem_stack_v ());
2655 add_unwind_entry (output_psp_sprel (e.X_add_number));
2656 }
2657 else
2658 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 2659}
2660
2661static void
2662dot_save (dummy)
2663 int dummy;
2664{
2665 expressionS e1, e2;
2666 int sep;
2667 int reg1, reg2;
2668
2669 sep = parse_operand (&e1);
2670 if (sep != ',')
2671 as_bad ("No second operand to .save");
2672 sep = parse_operand (&e2);
2673
e0c9811a 2674 reg1 = e1.X_add_number;
800eeca4
JW		 2675 reg2 = e2.X_add_number - REG_GR;
2676
2677 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2678 if (e1.X_op == O_register)
800eeca4
JW		 2679 {
2680 if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
2681 {
2682 switch (reg1)
2683 {
e0c9811a 2684 case REG_AR + AR_BSP:
800eeca4
JW		 2685 add_unwind_entry (output_bsp_when ());
2686 add_unwind_entry (output_bsp_gr (reg2));
2687 break;
e0c9811a 2688 case REG_AR + AR_BSPSTORE:
800eeca4
JW		 2689 add_unwind_entry (output_bspstore_when ());
2690 add_unwind_entry (output_bspstore_gr (reg2));
2691 break;
e0c9811a 2692 case REG_AR + AR_RNAT:
800eeca4
JW		 2693 add_unwind_entry (output_rnat_when ());
2694 add_unwind_entry (output_rnat_gr (reg2));
2695 break;
e0c9811a 2696 case REG_AR+AR_UNAT:
800eeca4
JW		 2697 add_unwind_entry (output_unat_when ());
2698 add_unwind_entry (output_unat_gr (reg2));
2699 break;
e0c9811a 2700 case REG_AR+AR_FPSR:
800eeca4
JW		 2701 add_unwind_entry (output_fpsr_when ());
2702 add_unwind_entry (output_fpsr_gr (reg2));
2703 break;
e0c9811a 2704 case REG_AR+AR_PFS:
800eeca4
JW		 2705 add_unwind_entry (output_pfs_when ());
2706 add_unwind_entry (output_pfs_gr (reg2));
2707 break;
e0c9811a 2708 case REG_AR+AR_LC:
800eeca4
JW		 2709 add_unwind_entry (output_lc_when ());
2710 add_unwind_entry (output_lc_gr (reg2));
2711 break;
e0c9811a 2712 case REG_BR:
800eeca4
JW		 2713 add_unwind_entry (output_rp_when ());
2714 add_unwind_entry (output_rp_gr (reg2));
2715 break;
e0c9811a
JW		 2716 case REG_PR:
2717 add_unwind_entry (output_preds_when ());
2718 add_unwind_entry (output_preds_gr (reg2));
2719 break;
2720 case REG_PRIUNAT:
2721 add_unwind_entry (output_priunat_when_gr ());
2722 add_unwind_entry (output_priunat_gr (reg2));
2723 break;
800eeca4 2724 default:
e0c9811a 2725 as_bad ("First operand not a valid register");
800eeca4
JW		 2726 }
2727 }
2728 else
2729 as_bad (" Second operand not a valid register");
2730 }
2731 else
e0c9811a 2732 as_bad ("First operand not a register");
800eeca4
JW		 2733}
2734
2735static void
2736dot_restore (dummy)
2737 int dummy;
2738{
e0c9811a
JW		 2739 expressionS e1, e2;
2740 unsigned long ecount = 0;
2741 int sep;
2742
2743 sep = parse_operand (&e1);
2744 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2745 {
2746 as_bad ("First operand to .restore must be stack pointer (sp)");
2747 return;
2748 }
2749
2750 if (sep == ',')
2751 {
2752 parse_operand (&e2);
2753 if (e1.X_op != O_constant)
2754 {
2755 as_bad ("Second operand to .restore must be constant");
2756 return;
2757 }
2758 ecount = e1.X_op;
2759 }
2760 add_unwind_entry (output_epilogue (ecount));
2761}
2762
2763static void
2764dot_restorereg (dummy)
2765 int dummy;
2766{
2767 unsigned int ab, reg;
2768 expressionS e;
2769
2770 parse_operand (&e);
2771
2772 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2773 {
2774 as_bad ("First operand to .restorereg must be a preserved register");
2775 return;
2776 }
2777 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2778}
2779
2780static void
2781dot_restorereg_p (dummy)
2782 int dummy;
2783{
2784 unsigned int qp, ab, reg;
2785 expressionS e1, e2;
2786 int sep;
2787
2788 sep = parse_operand (&e1);
2789 if (sep != ',')
2790 {
2791 as_bad ("No second operand to .restorereg.p");
2792 return;
2793 }
2794
2795 parse_operand (&e2);
2796
2797 qp = e1.X_add_number - REG_P;
2798 if (e1.X_op != O_register || qp > 63)
2799 {
2800 as_bad ("First operand to .restorereg.p must be a predicate");
2801 return;
2802 }
2803
2804 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2805 {
2806 as_bad ("Second operand to .restorereg.p must be a preserved register");
2807 return;
2808 }
2809 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 2810}
2811
2812static int
2813generate_unwind_image ()
2814{
2815 int size;
2816 unsigned char *unw_rec;
800eeca4
JW		 2817
2818 /* Generate the unwind record. */
e0c9811a
JW		 2819 size = output_unw_records (unwind.list, &unw_rec);
2820 if (size % 8 != 0)
2821 as_bad ("Unwind record is not a multiple of 8 bytes.");
800eeca4
JW		 2822
2823 /* If there are unwind records, switch sections, and output the info. */
2824 if (size != 0)
2825 {
800eeca4 2826 unsigned char *where;
800eeca4 2827 expressionS exp;
800eeca4
JW		 2828 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2829
2830 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 2831 unwind.info = expr_build_dot ();
800eeca4
JW		 2832
2833 where = (unsigned char *)frag_more (size);
2834
2835 /* Issue a label for this address, and keep track of it to put it
2836 in the unwind section. */
2837
2838 /* Copy the information from the unwind record into this section. The
2839 data is already in the correct byte order. */
2840 memcpy (where, unw_rec, size);
2841 /* Add the personality address to the image. */
e0c9811a 2842 if (unwind.personality_routine != 0)
800eeca4
JW		 2843 {
2844 exp.X_op = O_symbol;
e0c9811a 2845 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 2846 exp.X_add_number = 0;
2847 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
2848 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 2849 unwind.personality_routine = 0;
800eeca4
JW		 2850 }
2851 obj_elf_previous (0);
2852 }
2853
e0c9811a
JW		 2854 free_list_records (unwind.list);
2855 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 2856
2857 return size;
2858}
2859
2860static void
2861dot_handlerdata (dummy)
2862 int dummy;
2863{
2864 generate_unwind_image ();
e0c9811a 2865 demand_empty_rest_of_line ();
800eeca4
JW		 2866}
2867
2868static void
2869dot_unwentry (dummy)
2870 int dummy;
2871{
e0c9811a 2872 demand_empty_rest_of_line ();
800eeca4
JW		 2873}
2874
2875static void
2876dot_altrp (dummy)
2877 int dummy;
2878{
e0c9811a
JW		 2879 expressionS e;
2880 unsigned reg;
2881
2882 parse_operand (&e);
2883 reg = e.X_add_number - REG_BR;
2884 if (e.X_op == O_register && reg < 8)
2885 add_unwind_entry (output_rp_br (reg));
2886 else
2887 as_bad ("First operand not a valid branch register");
800eeca4
JW		 2888}
2889
2890static void
e0c9811a
JW		 2891dot_savemem (psprel)
2892 int psprel;
800eeca4
JW		 2893{
2894 expressionS e1, e2;
2895 int sep;
2896 int reg1, val;
2897
2898 sep = parse_operand (&e1);
2899 if (sep != ',')
e0c9811a 2900 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 2901 sep = parse_operand (&e2);
2902
e0c9811a 2903 reg1 = e1.X_add_number;
800eeca4
JW		 2904 val = e2.X_add_number;
2905
2906 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2907 if (e1.X_op == O_register)
800eeca4
JW		 2908 {
2909 if (e2.X_op == O_constant)
2910 {
2911 switch (reg1)
2912 {
e0c9811a 2913 case REG_AR + AR_BSP:
800eeca4 2914 add_unwind_entry (output_bsp_when ());
e0c9811a
JW		 2915 add_unwind_entry ((psprel
2916 ? output_bsp_psprel
2917 : output_bsp_sprel) (val));
800eeca4 2918 break;
e0c9811a 2919 case REG_AR + AR_BSPSTORE:
800eeca4 2920 add_unwind_entry (output_bspstore_when ());
e0c9811a
JW		 2921 add_unwind_entry ((psprel
2922 ? output_bspstore_psprel
2923 : output_bspstore_sprel) (val));
800eeca4 2924 break;
e0c9811a 2925 case REG_AR + AR_RNAT:
800eeca4 2926 add_unwind_entry (output_rnat_when ());
e0c9811a
JW		 2927 add_unwind_entry ((psprel
2928 ? output_rnat_psprel
2929 : output_rnat_sprel) (val));
800eeca4 2930 break;
e0c9811a 2931 case REG_AR + AR_UNAT:
800eeca4 2932 add_unwind_entry (output_unat_when ());
e0c9811a
JW		 2933 add_unwind_entry ((psprel
2934 ? output_unat_psprel
2935 : output_unat_sprel) (val));
800eeca4 2936 break;
e0c9811a 2937 case REG_AR + AR_FPSR:
800eeca4 2938 add_unwind_entry (output_fpsr_when ());
e0c9811a
JW		 2939 add_unwind_entry ((psprel
2940 ? output_fpsr_psprel
2941 : output_fpsr_sprel) (val));
800eeca4 2942 break;
e0c9811a 2943 case REG_AR + AR_PFS:
800eeca4 2944 add_unwind_entry (output_pfs_when ());
e0c9811a
JW		 2945 add_unwind_entry ((psprel
2946 ? output_pfs_psprel
2947 : output_pfs_sprel) (val));
800eeca4 2948 break;
e0c9811a 2949 case REG_AR + AR_LC:
800eeca4 2950 add_unwind_entry (output_lc_when ());
e0c9811a
JW		 2951 add_unwind_entry ((psprel
2952 ? output_lc_psprel
2953 : output_lc_sprel) (val));
800eeca4 2954 break;
e0c9811a 2955 case REG_BR:
800eeca4 2956 add_unwind_entry (output_rp_when ());
e0c9811a
JW		 2957 add_unwind_entry ((psprel
2958 ? output_rp_psprel
2959 : output_rp_sprel) (val));
800eeca4 2960 break;
e0c9811a 2961 case REG_PR:
800eeca4 2962 add_unwind_entry (output_preds_when ());
e0c9811a
JW		 2963 add_unwind_entry ((psprel
2964 ? output_preds_psprel
2965 : output_preds_sprel) (val));
2966 break;
2967 case REG_PRIUNAT:
2968 add_unwind_entry (output_priunat_when_mem ());
2969 add_unwind_entry ((psprel
2970 ? output_priunat_psprel
2971 : output_priunat_sprel) (val));
800eeca4
JW		 2972 break;
2973 default:
e0c9811a 2974 as_bad ("First operand not a valid register");
800eeca4
JW		 2975 }
2976 }
2977 else
2978 as_bad (" Second operand not a valid constant");
2979 }
2980 else
e0c9811a 2981 as_bad ("First operand not a register");
800eeca4
JW		 2982}
2983
2984static void
2985dot_saveg (dummy)
2986 int dummy;
2987{
2988 expressionS e1, e2;
2989 int sep;
2990 sep = parse_operand (&e1);
2991 if (sep == ',')
2992 parse_operand (&e2);
2993
2994 if (e1.X_op != O_constant)
2995 as_bad ("First operand to .save.g must be a constant.");
2996 else
2997 {
2998 int grmask = e1.X_add_number;
2999 if (sep != ',')
3000 add_unwind_entry (output_gr_mem (grmask));
3001 else
3002 {
3003 int reg = e2.X_add_number - REG_GR;
3004 if (e2.X_op == O_register && reg >=0 && reg < 128)
3005 add_unwind_entry (output_gr_gr (grmask, reg));
3006 else
3007 as_bad ("Second operand is an invalid register.");
3008 }
3009 }
3010}
3011
3012static void
3013dot_savef (dummy)
3014 int dummy;
3015{
e0c9811a 3016 expressionS e1;
800eeca4
JW		 3017 int sep;
3018 sep = parse_operand (&e1);
3019
3020 if (e1.X_op != O_constant)
3021 as_bad ("Operand to .save.f must be a constant.");
3022 else
e0c9811a 3023 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3024}
3025
3026static void
3027dot_saveb (dummy)
3028 int dummy;
3029{
e0c9811a
JW		 3030 expressionS e1, e2;
3031 unsigned int reg;
3032 unsigned char sep;
3033 int brmask;
3034
800eeca4 3035 sep = parse_operand (&e1);
800eeca4 3036 if (e1.X_op != O_constant)
800eeca4 3037 {
e0c9811a
JW		 3038 as_bad ("First operand to .save.b must be a constant.");
3039 return;
800eeca4 3040 }
e0c9811a
JW		 3041 brmask = e1.X_add_number;
3042
3043 if (sep == ',')
3044 {
3045 sep = parse_operand (&e2);
3046 reg = e2.X_add_number - REG_GR;
3047 if (e2.X_op != O_register || reg > 127)
3048 {
3049 as_bad ("Second operand to .save.b must be a general register.");
3050 return;
3051 }
3052 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3053 }
3054 else
3055 add_unwind_entry (output_br_mem (brmask));
3056
3057 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3058 ignore_rest_of_line ();
800eeca4
JW		 3059}
3060
3061static void
3062dot_savegf (dummy)
3063 int dummy;
3064{
3065 expressionS e1, e2;
3066 int sep;
3067 sep = parse_operand (&e1);
3068 if (sep == ',')
3069 parse_operand (&e2);
3070
3071 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3072 as_bad ("Both operands of .save.gf must be constants.");
3073 else
3074 {
3075 int grmask = e1.X_add_number;
3076 int frmask = e2.X_add_number;
3077 add_unwind_entry (output_frgr_mem (grmask, frmask));
3078 }
3079}
3080
3081static void
3082dot_spill (dummy)
3083 int dummy;
3084{
3085 expressionS e;
e0c9811a
JW		 3086 unsigned char sep;
3087
3088 sep = parse_operand (&e);
3089 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3090 ignore_rest_of_line ();
800eeca4
JW		 3091
3092 if (e.X_op != O_constant)
3093 as_bad ("Operand to .spill must be a constant");
3094 else
e0c9811a
JW		 3095 add_unwind_entry (output_spill_base (e.X_add_number));
3096}
3097
3098static void
3099dot_spillreg (dummy)
3100 int dummy;
3101{
3102 int sep, ab, xy, reg, treg;
3103 expressionS e1, e2;
3104
3105 sep = parse_operand (&e1);
3106 if (sep != ',')
3107 {
3108 as_bad ("No second operand to .spillreg");
3109 return;
3110 }
3111
3112 parse_operand (&e2);
3113
3114 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3115 {
e0c9811a
JW		 3116 as_bad ("First operand to .spillreg must be a preserved register");
3117 return;
800eeca4 3118 }
e0c9811a
JW		 3119
3120 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3121 {
3122 as_bad ("Second operand to .spillreg must be a register");
3123 return;
3124 }
3125
3126 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3127}
3128
3129static void
3130dot_spillmem (psprel)
3131 int psprel;
3132{
3133 expressionS e1, e2;
3134 int sep, ab, reg;
3135
3136 sep = parse_operand (&e1);
3137 if (sep != ',')
3138 {
3139 as_bad ("Second operand missing");
3140 return;
3141 }
3142
3143 parse_operand (&e2);
3144
3145 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3146 {
3147 as_bad ("First operand to .spill%s must be a preserved register",
3148 psprel ? "psp" : "sp");
3149 return;
3150 }
3151
3152 if (e2.X_op != O_constant)
3153 {
3154 as_bad ("Second operand to .spill%s must be a constant",
3155 psprel ? "psp" : "sp");
3156 return;
3157 }
3158
3159 if (psprel)
3160 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3161 else
3162 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3163}
3164
3165static void
3166dot_spillreg_p (dummy)
3167 int dummy;
3168{
3169 int sep, ab, xy, reg, treg;
3170 expressionS e1, e2, e3;
3171 unsigned int qp;
3172
3173 sep = parse_operand (&e1);
3174 if (sep != ',')
3175 {
3176 as_bad ("No second and third operand to .spillreg.p");
3177 return;
3178 }
3179
3180 sep = parse_operand (&e2);
3181 if (sep != ',')
3182 {
3183 as_bad ("No third operand to .spillreg.p");
3184 return;
3185 }
3186
3187 parse_operand (&e3);
3188
3189 qp = e1.X_add_number - REG_P;
3190
3191 if (e1.X_op != O_register || qp > 63)
3192 {
3193 as_bad ("First operand to .spillreg.p must be a predicate");
3194 return;
3195 }
3196
3197 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3198 {
3199 as_bad ("Second operand to .spillreg.p must be a preserved register");
3200 return;
3201 }
3202
3203 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3204 {
3205 as_bad ("Third operand to .spillreg.p must be a register");
3206 return;
3207 }
3208
3209 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3210}
3211
3212static void
3213dot_spillmem_p (psprel)
3214 int psprel;
3215{
3216 expressionS e1, e2, e3;
3217 int sep, ab, reg;
3218 unsigned int qp;
3219
3220 sep = parse_operand (&e1);
3221 if (sep != ',')
3222 {
3223 as_bad ("Second operand missing");
3224 return;
3225 }
3226
3227 parse_operand (&e2);
3228 if (sep != ',')
3229 {
3230 as_bad ("Second operand missing");
3231 return;
3232 }
3233
3234 parse_operand (&e3);
3235
3236 qp = e1.X_add_number - REG_P;
3237 if (e1.X_op != O_register || qp > 63)
3238 {
3239 as_bad ("First operand to .spill%s_p must be a predicate",
3240 psprel ? "psp" : "sp");
3241 return;
3242 }
3243
3244 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3245 {
3246 as_bad ("Second operand to .spill%s_p must be a preserved register",
3247 psprel ? "psp" : "sp");
3248 return;
3249 }
3250
3251 if (e3.X_op != O_constant)
3252 {
3253 as_bad ("Third operand to .spill%s_p must be a constant",
3254 psprel ? "psp" : "sp");
3255 return;
3256 }
3257
3258 if (psprel)
3259 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3260 else
3261 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3262}
3263
3264static void
3265dot_label_state (dummy)
3266 int dummy;
3267{
3268 expressionS e;
3269
3270 parse_operand (&e);
3271 if (e.X_op != O_constant)
3272 {
3273 as_bad ("Operand to .label_state must be a constant");
3274 return;
3275 }
3276 add_unwind_entry (output_label_state (e.X_add_number));
3277}
3278
3279static void
3280dot_copy_state (dummy)
3281 int dummy;
3282{
3283 expressionS e;
3284
3285 parse_operand (&e);
3286 if (e.X_op != O_constant)
3287 {
3288 as_bad ("Operand to .copy_state must be a constant");
3289 return;
3290 }
3291 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3292}
3293
3294static void
3295dot_unwabi (dummy)
3296 int dummy;
3297{
e0c9811a
JW		 3298 expressionS e1, e2;
3299 unsigned char sep;
3300
3301 sep = parse_operand (&e1);
3302 if (sep != ',')
3303 {
3304 as_bad ("Second operand to .unwabi missing");
3305 return;
3306 }
3307 sep = parse_operand (&e2);
3308 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3309 ignore_rest_of_line ();
3310
3311 if (e1.X_op != O_constant)
3312 {
3313 as_bad ("First operand to .unwabi must be a constant");
3314 return;
3315 }
3316
3317 if (e2.X_op != O_constant)
3318 {
3319 as_bad ("Second operand to .unwabi must be a constant");
3320 return;
3321 }
3322
3323 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3324}
3325
3326static void
3327dot_personality (dummy)
3328 int dummy;
3329{
3330 char *name, *p, c;
3331 SKIP_WHITESPACE ();
3332 name = input_line_pointer;
3333 c = get_symbol_end ();
3334 p = input_line_pointer;
e0c9811a 3335 unwind.personality_routine = symbol_find_or_make (name);
800eeca4
JW		 3336 *p = c;
3337 SKIP_WHITESPACE ();
3338 demand_empty_rest_of_line ();
3339}
3340
3341static void
3342dot_proc (dummy)
3343 int dummy;
3344{
3345 char *name, *p, c;
3346 symbolS *sym;
3347
e0c9811a
JW		 3348 unwind.proc_start = expr_build_dot ();
3349 /* Parse names of main and alternate entry points and mark them as
800eeca4
JW		 3350 function symbols: */
3351 while (1)
3352 {
3353 SKIP_WHITESPACE ();
3354 name = input_line_pointer;
3355 c = get_symbol_end ();
3356 p = input_line_pointer;
3357 sym = symbol_find_or_make (name);
e0c9811a 3358 if (unwind.proc_start == 0)
800eeca4 3359 {
e0c9811a 3360 unwind.proc_start = sym;
800eeca4
JW		 3361 }
3362 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3363 *p = c;
3364 SKIP_WHITESPACE ();
3365 if (*input_line_pointer != ',')
3366 break;
3367 ++input_line_pointer;
3368 }
3369 demand_empty_rest_of_line ();
3370 ia64_do_align (16);
3371
e0c9811a
JW		 3372 unwind.list = unwind.tail = unwind.current_entry = NULL;
3373 unwind.personality_routine = 0;
800eeca4
JW		 3374}
3375
3376static void
3377dot_body (dummy)
3378 int dummy;
3379{
e0c9811a 3380 unwind.prologue = 0;
800eeca4 3381 add_unwind_entry (output_body ());
e0c9811a 3382 demand_empty_rest_of_line ();
800eeca4
JW		 3383}
3384
3385static void
3386dot_prologue (dummy)
3387 int dummy;
3388{
e0c9811a
JW		 3389 unsigned char sep;
3390
3391 unwind.prologue = 1;
3392 if (!is_it_end_of_statement ())
800eeca4
JW		 3393 {
3394 expressionS e1, e2;
800eeca4
JW		 3395 sep = parse_operand (&e1);
3396 if (sep != ',')
3397 as_bad ("No second operand to .prologue");
3398 sep = parse_operand (&e2);
e0c9811a
JW		 3399 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3400 ignore_rest_of_line ();
800eeca4
JW		 3401
3402 if (e1.X_op == O_constant)
3403 {
3404 if (e2.X_op == O_constant)
3405 {
3406 int mask = e1.X_add_number;
3407 int reg = e2.X_add_number;
3408 add_unwind_entry (output_prologue_gr (mask, reg));
3409 }
3410 else
3411 as_bad ("Second operand not a constant");
3412 }
3413 else
3414 as_bad ("First operand not a constant");
3415 }
3416 else
3417 add_unwind_entry (output_prologue ());
3418}
3419
3420static void
3421dot_endp (dummy)
3422 int dummy;
3423{
3424 expressionS e;
3425 unsigned char *ptr;
800eeca4
JW		 3426 long where;
3427 segT saved_seg;
3428 subsegT saved_subseg;
3429
3430 saved_seg = now_seg;
3431 saved_subseg = now_subseg;
3432
3433 expression (&e);
3434 demand_empty_rest_of_line ();
3435
3436 insn_group_break (1, 0, 0);
3437 ia64_flush_insns ();
3438
3439 /* If there was a .handlerdata, we haven't generated an image yet. */
e0c9811a 3440 if (unwind.info == 0)
800eeca4
JW		 3441 {
3442 generate_unwind_image ();
3443 }
3444
3445 subseg_set (md.last_text_seg, 0);
e0c9811a 3446 unwind.proc_end = expr_build_dot ();
800eeca4
JW		 3447
3448 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3449 ptr = frag_more (24);
3450 where = frag_now_fix () - 24;
3451
3452 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3453 e.X_op = O_pseudo_fixup;
3454 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3455 e.X_add_number = 0;
e0c9811a 3456 e.X_add_symbol = unwind.proc_start;
800eeca4
JW		 3457 ia64_cons_fix_new (frag_now, where, 8, &e);
3458
3459 e.X_op = O_pseudo_fixup;
3460 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3461 e.X_add_number = 0;
e0c9811a 3462 e.X_add_symbol = unwind.proc_end;
800eeca4
JW		 3463 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
3464
e0c9811a 3465 if (unwind.info != 0)
800eeca4
JW		 3466 {
3467 e.X_op = O_pseudo_fixup;
3468 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3469 e.X_add_number = 0;
e0c9811a 3470 e.X_add_symbol = unwind.info;
800eeca4
JW		 3471 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
3472 }
3473 else
3474 md_number_to_chars (ptr + 16, 0, 8);
3475
3476 subseg_set (saved_seg, saved_subseg);
e0c9811a 3477 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3478}
3479
3480static void
3481dot_template (template)
3482 int template;
3483{
3484 CURR_SLOT.user_template = template;
3485}
3486
3487static void
3488dot_regstk (dummy)
3489 int dummy;
3490{
3491 int ins, locs, outs, rots;
3492
3493 if (is_it_end_of_statement ())
3494 ins = locs = outs = rots = 0;
3495 else
3496 {
3497 ins = get_absolute_expression ();
3498 if (*input_line_pointer++ != ',')
3499 goto err;
3500 locs = get_absolute_expression ();
3501 if (*input_line_pointer++ != ',')
3502 goto err;
3503 outs = get_absolute_expression ();
3504 if (*input_line_pointer++ != ',')
3505 goto err;
3506 rots = get_absolute_expression ();
3507 }
3508 set_regstack (ins, locs, outs, rots);
3509 return;
3510
3511 err:
3512 as_bad ("Comma expected");
3513 ignore_rest_of_line ();
3514}
3515
3516static void
3517dot_rot (type)
3518 int type;
3519{
3520 unsigned num_regs, num_alloced = 0;
3521 struct dynreg **drpp, *dr;
3522 int ch, base_reg = 0;
3523 char *name, *start;
3524 size_t len;
3525
3526 switch (type)
3527 {
3528 case DYNREG_GR: base_reg = REG_GR + 32; break;
3529 case DYNREG_FR: base_reg = REG_FR + 32; break;
3530 case DYNREG_PR: base_reg = REG_P + 16; break;
3531 default: break;
3532 }
3533
3534 /* first, remove existing names from hash table: */
3535 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3536 {
3537 hash_delete (md.dynreg_hash, dr->name);
3538 dr->num_regs = 0;
3539 }
3540
3541 drpp = &md.dynreg[type];
3542 while (1)
3543 {
3544 start = input_line_pointer;
3545 ch = get_symbol_end ();
3546 *input_line_pointer = ch;
3547 len = (input_line_pointer - start);
3548
3549 SKIP_WHITESPACE ();
3550 if (*input_line_pointer != '[')
3551 {
3552 as_bad ("Expected '['");
3553 goto err;
3554 }
3555 ++input_line_pointer; /* skip '[' */
3556
3557 num_regs = get_absolute_expression ();
3558
3559 if (*input_line_pointer++ != ']')
3560 {
3561 as_bad ("Expected ']'");
3562 goto err;
3563 }
3564 SKIP_WHITESPACE ();
3565
3566 num_alloced += num_regs;
3567 switch (type)
3568 {
3569 case DYNREG_GR:
3570 if (num_alloced > md.rot.num_regs)
3571 {
3572 as_bad ("Used more than the declared %d rotating registers",
3573 md.rot.num_regs);
3574 goto err;
3575 }
3576 break;
3577 case DYNREG_FR:
3578 if (num_alloced > 96)
3579 {
3580 as_bad ("Used more than the available 96 rotating registers");
3581 goto err;
3582 }
3583 break;
3584 case DYNREG_PR:
3585 if (num_alloced > 48)
3586 {
3587 as_bad ("Used more than the available 48 rotating registers");
3588 goto err;
3589 }
3590 break;
3591
3592 default:
3593 break;
3594 }
3595
3596 name = obstack_alloc (&notes, len + 1);
3597 memcpy (name, start, len);
3598 name[len] = '\0';
3599
3600 if (!*drpp)
3601 {
3602 *drpp = obstack_alloc (&notes, sizeof (*dr));
3603 memset (*drpp, 0, sizeof (*dr));
3604 }
3605
3606 dr = *drpp;
3607 dr->name = name;
3608 dr->num_regs = num_regs;
3609 dr->base = base_reg;
3610 drpp = &dr->next;
3611 base_reg += num_regs;
3612
3613 if (hash_insert (md.dynreg_hash, name, dr))
3614 {
3615 as_bad ("Attempt to redefine register set `%s'", name);
3616 goto err;
3617 }
3618
3619 if (*input_line_pointer != ',')
3620 break;
3621 ++input_line_pointer; /* skip comma */
3622 SKIP_WHITESPACE ();
3623 }
3624 demand_empty_rest_of_line ();
3625 return;
3626
3627 err:
3628 ignore_rest_of_line ();
3629}
3630
3631static void
3632dot_byteorder (byteorder)
3633 int byteorder;
3634{
3635 target_big_endian = byteorder;
3636}
3637
3638static void
3639dot_psr (dummy)
3640 int dummy;
3641{
3642 char *option;
3643 int ch;
3644
3645 while (1)
3646 {
3647 option = input_line_pointer;
3648 ch = get_symbol_end ();
3649 if (strcmp (option, "lsb") == 0)
3650 md.flags &= ~EF_IA_64_BE;
3651 else if (strcmp (option, "msb") == 0)
3652 md.flags |= EF_IA_64_BE;
3653 else if (strcmp (option, "abi32") == 0)
3654 md.flags &= ~EF_IA_64_ABI64;
3655 else if (strcmp (option, "abi64") == 0)
3656 md.flags |= EF_IA_64_ABI64;
3657 else
3658 as_bad ("Unknown psr option `%s'", option);
3659 *input_line_pointer = ch;
3660
3661 SKIP_WHITESPACE ();
3662 if (*input_line_pointer != ',')
3663 break;
3664
3665 ++input_line_pointer;
3666 SKIP_WHITESPACE ();
3667 }
3668 demand_empty_rest_of_line ();
3669}
3670
3671static void
3672dot_alias (dummy)
3673 int dummy;
3674{
3675 as_bad (".alias not implemented yet");
3676}
3677
3678static void
3679dot_ln (dummy)
3680 int dummy;
3681{
3682 new_logical_line (0, get_absolute_expression ());
3683 demand_empty_rest_of_line ();
3684}
3685
3686static char*
3687parse_section_name ()
3688{
3689 char *name;
3690 int len;
3691
3692 SKIP_WHITESPACE ();
3693 if (*input_line_pointer != '"')
3694 {
3695 as_bad ("Missing section name");
3696 ignore_rest_of_line ();
3697 return 0;
3698 }
3699 name = demand_copy_C_string (&len);
3700 if (!name)
3701 {
3702 ignore_rest_of_line ();
3703 return 0;
3704 }
3705 SKIP_WHITESPACE ();
3706 if (*input_line_pointer != ',')
3707 {
3708 as_bad ("Comma expected after section name");
3709 ignore_rest_of_line ();
3710 return 0;
3711 }
3712 ++input_line_pointer; /* skip comma */
3713 return name;
3714}
3715
3716static void
3717dot_xdata (size)
3718 int size;
3719{
3720 char *name = parse_section_name ();
3721 if (!name)
3722 return;
3723
3724 set_section (name);
3725 cons (size);
3726 obj_elf_previous (0);
3727}
3728
3729/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3730static void
3731stmt_float_cons (kind)
3732 int kind;
3733{
3734 size_t size;
3735
3736 switch (kind)
3737 {
3738 case 'd': size = 8; break;
3739 case 'x': size = 10; break;
3740
3741 case 'f':
3742 default:
3743 size = 4;
3744 break;
3745 }
3746 ia64_do_align (size);
3747 float_cons (kind);
3748}
3749
3750static void
3751stmt_cons_ua (size)
3752 int size;
3753{
3754 int saved_auto_align = md.auto_align;
3755
3756 md.auto_align = 0;
3757 cons (size);
3758 md.auto_align = saved_auto_align;
3759}
3760
3761static void
3762dot_xfloat_cons (kind)
3763 int kind;
3764{
3765 char *name = parse_section_name ();
3766 if (!name)
3767 return;
3768
3769 set_section (name);
3770 stmt_float_cons (kind);
3771 obj_elf_previous (0);
3772}
3773
3774static void
3775dot_xstringer (zero)
3776 int zero;
3777{
3778 char *name = parse_section_name ();
3779 if (!name)
3780 return;
3781
3782 set_section (name);
3783 stringer (zero);
3784 obj_elf_previous (0);
3785}
3786
3787static void
3788dot_xdata_ua (size)
3789 int size;
3790{
3791 int saved_auto_align = md.auto_align;
3792 char *name = parse_section_name ();
3793 if (!name)
3794 return;
3795
3796 set_section (name);
3797 md.auto_align = 0;
3798 cons (size);
3799 md.auto_align = saved_auto_align;
3800 obj_elf_previous (0);
3801}
3802
3803static void
3804dot_xfloat_cons_ua (kind)
3805 int kind;
3806{
3807 int saved_auto_align = md.auto_align;
3808 char *name = parse_section_name ();
3809 if (!name)
3810 return;
3811
3812 set_section (name);
3813 md.auto_align = 0;
3814 stmt_float_cons (kind);
3815 md.auto_align = saved_auto_align;
3816 obj_elf_previous (0);
3817}
3818
3819/* .reg.val <regname>,value */
3820static void
3821dot_reg_val (dummy)
3822 int dummy;
3823{
3824 expressionS reg;
3825
3826 expression (&reg);
3827 if (reg.X_op != O_register)
3828 {
3829 as_bad (_("Register name expected"));
3830 ignore_rest_of_line ();
3831 }
3832 else if (*input_line_pointer++ != ',')
3833 {
3834 as_bad (_("Comma expected"));
3835 ignore_rest_of_line ();
3836 }
3837 else
3838 {
3839 valueT value = get_absolute_expression ();
3840 int regno = reg.X_add_number;
3841 if (regno < REG_GR || regno > REG_GR+128)
3842 as_warn (_("Register value annotation ignored"));
3843 else
3844 {
3845 gr_values[regno-REG_GR].known = 1;
3846 gr_values[regno-REG_GR].value = value;
3847 gr_values[regno-REG_GR].path = md.path;
3848 }
3849 }
3850 demand_empty_rest_of_line ();
3851}
3852
3853/* select dv checking mode
3854 .auto
3855 .explicit
3856 .default
3857
3858 A stop is inserted when changing modes
3859 */
3860static void
3861dot_dv_mode (type)
3862 int type;
3863{
3864 if (md.manual_bundling)
3865 as_warn (_("Directive invalid within a bundle"));
3866
3867 if (type == 'E' || type == 'A')
3868 md.mode_explicitly_set = 0;
3869 else
3870 md.mode_explicitly_set = 1;
3871
3872 md.detect_dv = 1;
3873 switch (type)
3874 {
3875 case 'A':
3876 case 'a':
3877 if (md.explicit_mode)
3878 insn_group_break (1, 0, 0);
3879 md.explicit_mode = 0;
3880 break;
3881 case 'E':
3882 case 'e':
3883 if (!md.explicit_mode)
3884 insn_group_break (1, 0, 0);
3885 md.explicit_mode = 1;
3886 break;
3887 default:
3888 case 'd':
3889 if (md.explicit_mode != md.default_explicit_mode)
3890 insn_group_break (1, 0, 0);
3891 md.explicit_mode = md.default_explicit_mode;
3892 md.mode_explicitly_set = 0;
3893 break;
3894 }
3895}
3896
3897static void
3898print_prmask (mask)
3899 valueT mask;
3900{
3901 int regno;
3902 char *comma = "";
3903 for (regno = 0;regno < 64;regno++)
3904 {
3905 if (mask & ((valueT)1<<regno))
3906 {
3907 fprintf (stderr, "%s p%d", comma, regno);
3908 comma = ",";
3909 }
3910 }
3911}
3912
3913/*
3914 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
3915 .pred.rel.imply p1, p2 (also .pred.rel "imply")
3916 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
3917 .pred.safe_across_calls p1 [, p2 [,...]]
3918 */
3919static void
3920dot_pred_rel (type)
3921 int type;
3922{
3923 valueT mask = 0;
3924 int count = 0;
3925 int p1 = -1, p2 = -1;
3926
3927 if (type == 0)
3928 {
3929 if (*input_line_pointer != '"')
3930 {
3931 as_bad (_("Missing predicate relation type"));
3932 ignore_rest_of_line ();
3933 return;
3934 }
3935 else
3936 {
3937 int len;
3938 char *form = demand_copy_C_string (&len);
3939 if (strcmp (form, "mutex") == 0)
3940 type = 'm';
3941 else if (strcmp (form, "clear") == 0)
3942 type = 'c';
3943 else if (strcmp (form, "imply") == 0)
3944 type = 'i';
3945 else
3946 {
3947 as_bad (_("Unrecognized predicate relation type"));
3948 ignore_rest_of_line ();
3949 return;
3950 }
3951 }
3952 if (*input_line_pointer == ',')
3953 ++input_line_pointer;
3954 SKIP_WHITESPACE ();
3955 }
3956
3957 SKIP_WHITESPACE ();
3958 while (1)
3959 {
3960 valueT bit = 1;
3961 int regno;
3962
3963 if (toupper (*input_line_pointer) != 'P'
3964 || (regno = atoi (++input_line_pointer)) < 0
3965 || regno > 63)
3966 {
3967 as_bad (_("Predicate register expected"));
3968 ignore_rest_of_line ();
3969 return;
3970 }
3971 while (isdigit (*input_line_pointer))
3972 ++input_line_pointer;
3973 if (p1 == -1)
3974 p1 = regno;
3975 else if (p2 == -1)
3976 p2 = regno;
3977 bit <<= regno;
3978 if (mask & bit)
3979 as_warn (_("Duplicate predicate register ignored"));
3980 mask |= bit; count++;
3981 /* see if it's a range */
3982 if (*input_line_pointer == '-')
3983 {
3984 valueT stop = 1;
3985 ++input_line_pointer;
3986
3987 if (toupper (*input_line_pointer) != 'P'
3988 || (regno = atoi (++input_line_pointer)) < 0
3989 || regno > 63)
3990 {
3991 as_bad (_("Predicate register expected"));
3992 ignore_rest_of_line ();
3993 return;
3994 }
3995 while (isdigit (*input_line_pointer))
3996 ++input_line_pointer;
3997 stop <<= regno;
3998 if (bit >= stop)
3999 {
4000 as_bad (_("Bad register range"));
4001 ignore_rest_of_line ();
4002 return;
4003 }
4004 while (bit < stop)
4005 {
4006 bit <<= 1;
4007 mask |= bit; count++;
4008 }
4009 SKIP_WHITESPACE ();
4010 }
4011 if (*input_line_pointer != ',')
4012 break;
4013 ++input_line_pointer;
4014 SKIP_WHITESPACE ();
4015 }
4016
4017 switch (type)
4018 {
4019 case 'c':
4020 if (count == 0)
4021 mask = ~(valueT)0;
4022 clear_qp_mutex (mask);
4023 clear_qp_implies (mask, (valueT)0);
4024 break;
4025 case 'i':
4026 if (count != 2 || p1 == -1 || p2 == -1)
4027 as_bad (_("Predicate source and target required"));
4028 else if (p1 == 0 || p2 == 0)
4029 as_bad (_("Use of p0 is not valid in this context"));
4030 else
4031 add_qp_imply (p1, p2);
4032 break;
4033 case 'm':
4034 if (count < 2)
4035 {
4036 as_bad (_("At least two PR arguments expected"));
4037 break;
4038 }
4039 else if (mask & 1)
4040 {
4041 as_bad (_("Use of p0 is not valid in this context"));
4042 break;
4043 }
4044 add_qp_mutex (mask);
4045 break;
4046 case 's':
4047 /* note that we don't override any existing relations */
4048 if (count == 0)
4049 {
4050 as_bad (_("At least one PR argument expected"));
4051 break;
4052 }
4053 if (md.debug_dv)
4054 {
4055 fprintf (stderr, "Safe across calls: ");
4056 print_prmask (mask);
4057 fprintf (stderr, "\n");
4058 }
4059 qp_safe_across_calls = mask;
4060 break;
4061 }
4062 demand_empty_rest_of_line ();
4063}
4064
4065/* .entry label [, label [, ...]]
4066 Hint to DV code that the given labels are to be considered entry points.
4067 Otherwise, only global labels are considered entry points.
4068 */
4069static void
4070dot_entry (dummy)
4071 int dummy;
4072{
4073 const char *err;
4074 char *name;
4075 int c;
4076 symbolS *symbolP;
4077
4078 do
4079 {
4080 name = input_line_pointer;
4081 c = get_symbol_end ();
4082 symbolP = symbol_find_or_make (name);
4083
4084 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4085 if (err)
4086 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4087 name, err);
4088
4089 *input_line_pointer = c;
4090 SKIP_WHITESPACE ();
4091 c = *input_line_pointer;
4092 if (c == ',')
4093 {
4094 input_line_pointer++;
4095 SKIP_WHITESPACE ();
4096 if (*input_line_pointer == '\n')
4097 c = '\n';
4098 }
4099 }
4100 while (c == ',');
4101
4102 demand_empty_rest_of_line ();
4103}
4104
4105/* .mem.offset offset, base
4106 "base" is used to distinguish between offsets from a different base.
4107 */
4108static void
4109dot_mem_offset (dummy)
4110 int dummy;
4111{
4112 md.mem_offset.hint = 1;
4113 md.mem_offset.offset = get_absolute_expression ();
4114 if (*input_line_pointer != ',')
4115 {
4116 as_bad (_("Comma expected"));
4117 ignore_rest_of_line ();
4118 return;
4119 }
4120 ++input_line_pointer;
4121 md.mem_offset.base = get_absolute_expression ();
4122 demand_empty_rest_of_line ();
4123}
4124
4125/* ia64-specific pseudo-ops: */
4126const pseudo_typeS md_pseudo_table[] =
4127 {
4128 { "radix", dot_radix, 0 },
4129 { "lcomm", s_lcomm_bytes, 1 },
4130 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4131 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4132 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4133 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4134 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4135 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4136 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4137 { "proc", dot_proc, 0 },
4138 { "body", dot_body, 0 },
4139 { "prologue", dot_prologue, 0 },
4140 { "endp", dot_endp },
4141 { "file", dwarf2_directive_file },
4142 { "loc", dwarf2_directive_loc },
4143
4144 { "fframe", dot_fframe },
4145 { "vframe", dot_vframe },
e0c9811a
JW		 4146 { "vframesp", dot_vframesp },
4147 { "vframepsp", dot_vframepsp },
800eeca4
JW		 4148 { "save", dot_save },
4149 { "restore", dot_restore },
e0c9811a
JW		 4150 { "restorereg", dot_restorereg },
4151 { "restorereg.p", dot_restorereg_p },
800eeca4
JW		 4152 { "handlerdata", dot_handlerdata },
4153 { "unwentry", dot_unwentry },
e0c9811a
JW		 4154 { "altrp", dot_altrp },
4155 { "savesp", dot_savemem, 0 },
4156 { "savepsp", dot_savemem, 1 },
800eeca4
JW		 4157 { "save.g", dot_saveg },
4158 { "save.f", dot_savef },
4159 { "save.b", dot_saveb },
4160 { "save.gf", dot_savegf },
4161 { "spill", dot_spill },
e0c9811a
JW		 4162 { "spillreg", dot_spillreg },
4163 { "spillsp", dot_spillmem, 0 },
4164 { "spillpsp", dot_spillmem, 1 },
4165 { "spillreg.p", dot_spillreg_p },
4166 { "spillsp.p", dot_spillmem_p, 0 },
4167 { "spillpsp.p", dot_spillmem_p, 1 },
4168 { "label_state", dot_label_state },
4169 { "copy_state", dot_copy_state },
800eeca4
JW		 4170 { "unwabi", dot_unwabi },
4171 { "personality", dot_personality },
4172#if 0
4173 { "estate", dot_estate },
4174#endif
4175 { "mii", dot_template, 0x0 },
4176 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4177 { "mlx", dot_template, 0x2 },
4178 { "mmi", dot_template, 0x4 },
4179 { "mfi", dot_template, 0x6 },
4180 { "mmf", dot_template, 0x7 },
4181 { "mib", dot_template, 0x8 },
4182 { "mbb", dot_template, 0x9 },
4183 { "bbb", dot_template, 0xb },
4184 { "mmb", dot_template, 0xc },
4185 { "mfb", dot_template, 0xe },
4186#if 0
4187 { "lb", dot_scope, 0 },
4188 { "le", dot_scope, 1 },
4189#endif
4190 { "align", s_align_bytes, 0 },
4191 { "regstk", dot_regstk, 0 },
4192 { "rotr", dot_rot, DYNREG_GR },
4193 { "rotf", dot_rot, DYNREG_FR },
4194 { "rotp", dot_rot, DYNREG_PR },
4195 { "lsb", dot_byteorder, 0 },
4196 { "msb", dot_byteorder, 1 },
4197 { "psr", dot_psr, 0 },
4198 { "alias", dot_alias, 0 },
4199 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4200
4201 { "xdata1", dot_xdata, 1 },
4202 { "xdata2", dot_xdata, 2 },
4203 { "xdata4", dot_xdata, 4 },
4204 { "xdata8", dot_xdata, 8 },
4205 { "xreal4", dot_xfloat_cons, 'f' },
4206 { "xreal8", dot_xfloat_cons, 'd' },
4207 { "xreal10", dot_xfloat_cons, 'x' },
4208 { "xstring", dot_xstringer, 0 },
4209 { "xstringz", dot_xstringer, 1 },
4210
4211 /* unaligned versions: */
4212 { "xdata2.ua", dot_xdata_ua, 2 },
4213 { "xdata4.ua", dot_xdata_ua, 4 },
4214 { "xdata8.ua", dot_xdata_ua, 8 },
4215 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4216 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4217 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4218
4219 /* annotations/DV checking support */
4220 { "entry", dot_entry, 0 },
4221 { "mem.offset", dot_mem_offset },
4222 { "pred.rel", dot_pred_rel, 0 },
4223 { "pred.rel.clear", dot_pred_rel, 'c' },
4224 { "pred.rel.imply", dot_pred_rel, 'i' },
4225 { "pred.rel.mutex", dot_pred_rel, 'm' },
4226 { "pred.safe_across_calls", dot_pred_rel, 's' },
4227 { "reg.val", dot_reg_val },
4228 { "auto", dot_dv_mode, 'a' },
4229 { "explicit", dot_dv_mode, 'e' },
4230 { "default", dot_dv_mode, 'd' },
4231
4232 { NULL, 0, 0 }
4233 };
4234
4235static const struct pseudo_opcode
4236 {
4237 const char *name;
4238 void (*handler) (int);
4239 int arg;
4240 }
4241pseudo_opcode[] =
4242 {
4243 /* these are more like pseudo-ops, but don't start with a dot */
4244 { "data1", cons, 1 },
4245 { "data2", cons, 2 },
4246 { "data4", cons, 4 },
4247 { "data8", cons, 8 },
4248 { "real4", stmt_float_cons, 'f' },
4249 { "real8", stmt_float_cons, 'd' },
4250 { "real10", stmt_float_cons, 'x' },
4251 { "string", stringer, 0 },
4252 { "stringz", stringer, 1 },
4253
4254 /* unaligned versions: */
4255 { "data2.ua", stmt_cons_ua, 2 },
4256 { "data4.ua", stmt_cons_ua, 4 },
4257 { "data8.ua", stmt_cons_ua, 8 },
4258 { "real4.ua", float_cons, 'f' },
4259 { "real8.ua", float_cons, 'd' },
4260 { "real10.ua", float_cons, 'x' },
4261 };
4262
4263/* Declare a register by creating a symbol for it and entering it in
4264 the symbol table. */
4265static symbolS*
4266declare_register (name, regnum)
4267 const char *name;
4268 int regnum;
4269{
4270 const char *err;
4271 symbolS *sym;
4272
4273 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4274
4275 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4276 if (err)
4277 as_fatal ("Inserting \"%s\" into register table failed: %s",
4278 name, err);
4279
4280 return sym;
4281}
4282
4283static void
4284declare_register_set (prefix, num_regs, base_regnum)
4285 const char *prefix;
4286 int num_regs;
4287 int base_regnum;
4288{
4289 char name[8];
4290 int i;
4291
4292 for (i = 0; i < num_regs; ++i)
4293 {
4294 sprintf (name, "%s%u", prefix, i);
4295 declare_register (name, base_regnum + i);
4296 }
4297}
4298
4299static unsigned int
4300operand_width (opnd)
4301 enum ia64_opnd opnd;
4302{
4303 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4304 unsigned int bits = 0;
4305 int i;
4306
4307 bits = 0;
4308 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4309 bits += odesc->field[i].bits;
4310
4311 return bits;
4312}
4313
4314static int
4315operand_match (idesc, index, e)
4316 const struct ia64_opcode *idesc;
4317 int index;
4318 expressionS *e;
4319{
4320 enum ia64_opnd opnd = idesc->operands[index];
4321 int bits, relocatable = 0;
4322 struct insn_fix *fix;
4323 bfd_signed_vma val;
4324
4325 switch (opnd)
4326 {
4327 /* constants: */
4328
4329 case IA64_OPND_AR_CCV:
4330 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4331 return 1;
4332 break;
4333
4334 case IA64_OPND_AR_PFS:
4335 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4336 return 1;
4337 break;
4338
4339 case IA64_OPND_GR0:
4340 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4341 return 1;
4342 break;
4343
4344 case IA64_OPND_IP:
4345 if (e->X_op == O_register && e->X_add_number == REG_IP)
4346 return 1;
4347 break;
4348
4349 case IA64_OPND_PR:
4350 if (e->X_op == O_register && e->X_add_number == REG_PR)
4351 return 1;
4352 break;
4353
4354 case IA64_OPND_PR_ROT:
4355 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4356 return 1;
4357 break;
4358
4359 case IA64_OPND_PSR:
4360 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4361 return 1;
4362 break;
4363
4364 case IA64_OPND_PSR_L:
4365 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4366 return 1;
4367 break;
4368
4369 case IA64_OPND_PSR_UM:
4370 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4371 return 1;
4372 break;
4373
4374 case IA64_OPND_C1:
4375 if (e->X_op == O_constant && e->X_add_number == 1)
4376 return 1;
4377 break;
4378
4379 case IA64_OPND_C8:
4380 if (e->X_op == O_constant && e->X_add_number == 8)
4381 return 1;
4382 break;
4383
4384 case IA64_OPND_C16:
4385 if (e->X_op == O_constant && e->X_add_number == 16)
4386 return 1;
4387 break;
4388
4389 /* register operands: */
4390
4391 case IA64_OPND_AR3:
4392 if (e->X_op == O_register && e->X_add_number >= REG_AR
4393 && e->X_add_number < REG_AR + 128)
4394 return 1;
4395 break;
4396
4397 case IA64_OPND_B1:
4398 case IA64_OPND_B2:
4399 if (e->X_op == O_register && e->X_add_number >= REG_BR
4400 && e->X_add_number < REG_BR + 8)
4401 return 1;
4402 break;
4403
4404 case IA64_OPND_CR3:
4405 if (e->X_op == O_register && e->X_add_number >= REG_CR
4406 && e->X_add_number < REG_CR + 128)
4407 return 1;
4408 break;
4409
4410 case IA64_OPND_F1:
4411 case IA64_OPND_F2:
4412 case IA64_OPND_F3:
4413 case IA64_OPND_F4:
4414 if (e->X_op == O_register && e->X_add_number >= REG_FR
4415 && e->X_add_number < REG_FR + 128)
4416 return 1;
4417 break;
4418
4419 case IA64_OPND_P1:
4420 case IA64_OPND_P2:
4421 if (e->X_op == O_register && e->X_add_number >= REG_P
4422 && e->X_add_number < REG_P + 64)
4423 return 1;
4424 break;
4425
4426 case IA64_OPND_R1:
4427 case IA64_OPND_R2:
4428 case IA64_OPND_R3:
4429 if (e->X_op == O_register && e->X_add_number >= REG_GR
4430 && e->X_add_number < REG_GR + 128)
4431 return 1;
4432 break;
4433
4434 case IA64_OPND_R3_2:
4435 if (e->X_op == O_register && e->X_add_number >= REG_GR
4436 && e->X_add_number < REG_GR + 4)
4437 return 1;
4438 break;
4439
4440 /* indirect operands: */
4441 case IA64_OPND_CPUID_R3:
4442 case IA64_OPND_DBR_R3:
4443 case IA64_OPND_DTR_R3:
4444 case IA64_OPND_ITR_R3:
4445 case IA64_OPND_IBR_R3:
4446 case IA64_OPND_MSR_R3:
4447 case IA64_OPND_PKR_R3:
4448 case IA64_OPND_PMC_R3:
4449 case IA64_OPND_PMD_R3:
4450 case IA64_OPND_RR_R3:
4451 if (e->X_op == O_index && e->X_op_symbol
4452 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4453 == opnd - IA64_OPND_CPUID_R3))
4454 return 1;
4455 break;
4456
4457 case IA64_OPND_MR3:
4458 if (e->X_op == O_index && !e->X_op_symbol)
4459 return 1;
4460 break;
4461
4462 /* immediate operands: */
4463 case IA64_OPND_CNT2a:
4464 case IA64_OPND_LEN4:
4465 case IA64_OPND_LEN6:
4466 bits = operand_width (idesc->operands[index]);
4467 if (e->X_op == O_constant
4468 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4469 return 1;
4470 break;
4471
4472 case IA64_OPND_CNT2b:
4473 if (e->X_op == O_constant
4474 && (bfd_vma) (e->X_add_number - 1) < 3)
4475 return 1;
4476 break;
4477
4478 case IA64_OPND_CNT2c:
4479 val = e->X_add_number;
4480 if (e->X_op == O_constant
4481 && (val == 0 || val == 7 || val == 15 || val == 16))
4482 return 1;
4483 break;
4484
4485 case IA64_OPND_SOR:
4486 /* SOR must be an integer multiple of 8 */
4487 if (e->X_add_number & 0x7)
4488 break;
4489 case IA64_OPND_SOF:
4490 case IA64_OPND_SOL:
4491 if (e->X_op == O_constant &&
4492 (bfd_vma) e->X_add_number <= 96)
4493 return 1;
4494 break;
4495
4496 case IA64_OPND_IMMU62:
4497 if (e->X_op == O_constant)
4498 {
4499 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4500 return 1;
4501 }
4502 else
4503 {
4504 /* FIXME -- need 62-bit relocation type */
4505 as_bad (_("62-bit relocation not yet implemented"));
4506 }
4507 break;
4508
4509 case IA64_OPND_IMMU64:
4510 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4511 || e->X_op == O_subtract)
4512 {
4513 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4514 fix->code = BFD_RELOC_IA64_IMM64;
4515 if (e->X_op != O_subtract)
4516 {
4517 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4518 if (e->X_op == O_pseudo_fixup)
4519 e->X_op = O_symbol;
4520 }
4521
4522 fix->opnd = idesc->operands[index];
4523 fix->expr = *e;
4524 fix->is_pcrel = 0;
4525 ++CURR_SLOT.num_fixups;
4526 return 1;
4527 }
4528 else if (e->X_op == O_constant)
4529 return 1;
4530 break;
4531
4532 case IA64_OPND_CCNT5:
4533 case IA64_OPND_CNT5:
4534 case IA64_OPND_CNT6:
4535 case IA64_OPND_CPOS6a:
4536 case IA64_OPND_CPOS6b:
4537 case IA64_OPND_CPOS6c:
4538 case IA64_OPND_IMMU2:
4539 case IA64_OPND_IMMU7a:
4540 case IA64_OPND_IMMU7b:
800eeca4
JW		 4541 case IA64_OPND_IMMU21:
4542 case IA64_OPND_IMMU24:
4543 case IA64_OPND_MBTYPE4:
4544 case IA64_OPND_MHTYPE8:
4545 case IA64_OPND_POS6:
4546 bits = operand_width (idesc->operands[index]);
4547 if (e->X_op == O_constant
4548 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4549 return 1;
4550 break;
4551
bf3ca999
TW		 4552 case IA64_OPND_IMMU9:
4553 bits = operand_width (idesc->operands[index]);
4554 if (e->X_op == O_constant
4555 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4556 {
4557 int lobits = e->X_add_number & 0x3;
4558 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4559 e->X_add_number |= (bfd_vma)0x3;
4560 return 1;
4561 }
4562 break;
4563
800eeca4
JW		 4564 case IA64_OPND_IMM44:
4565 /* least 16 bits must be zero */
4566 if ((e->X_add_number & 0xffff) != 0)
4567 as_warn (_("lower 16 bits of mask ignored"));
4568
4569 if (e->X_op == O_constant
4570 && ((e->X_add_number >= 0
4571 && e->X_add_number < ((bfd_vma) 1 << 44))
4572 || (e->X_add_number < 0
4573 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
4574 {
4575 /* sign-extend */
4576 if (e->X_add_number >= 0
4577 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4578 {
4579 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4580 }
4581 return 1;
4582 }
4583 break;
4584
4585 case IA64_OPND_IMM17:
4586 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4587 if (e->X_op == O_constant
4588 && ((e->X_add_number >= 0
4589 && e->X_add_number < ((bfd_vma) 1 << 17))
4590 || (e->X_add_number < 0
4591 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
4592 {
4593 /* sign-extend */
4594 if (e->X_add_number >= 0
4595 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4596 {
4597 e->X_add_number |= ~(((bfd_vma)1 << 17) - 1);
4598 }
4599 return 1;
4600 }
4601 break;
4602
4603 case IA64_OPND_IMM14:
4604 case IA64_OPND_IMM22:
4605 relocatable = 1;
4606 case IA64_OPND_IMM1:
4607 case IA64_OPND_IMM8:
4608 case IA64_OPND_IMM8U4:
4609 case IA64_OPND_IMM8M1:
4610 case IA64_OPND_IMM8M1U4:
4611 case IA64_OPND_IMM8M1U8:
4612 case IA64_OPND_IMM9a:
4613 case IA64_OPND_IMM9b:
4614 bits = operand_width (idesc->operands[index]);
4615 if (relocatable && (e->X_op == O_symbol
4616 || e->X_op == O_subtract
4617 || e->X_op == O_pseudo_fixup))
4618 {
4619 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4620
4621 if (idesc->operands[index] == IA64_OPND_IMM14)
4622 fix->code = BFD_RELOC_IA64_IMM14;
4623 else
4624 fix->code = BFD_RELOC_IA64_IMM22;
4625
4626 if (e->X_op != O_subtract)
4627 {
4628 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4629 if (e->X_op == O_pseudo_fixup)
4630 e->X_op = O_symbol;
4631 }
4632
4633 fix->opnd = idesc->operands[index];
4634 fix->expr = *e;
4635 fix->is_pcrel = 0;
4636 ++CURR_SLOT.num_fixups;
4637 return 1;
4638 }
4639 else if (e->X_op != O_constant
4640 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4641 return 0;
4642
4643 if (opnd == IA64_OPND_IMM8M1U4)
4644 {
4645 /* Zero is not valid for unsigned compares that take an adjusted
4646 constant immediate range. */
4647 if (e->X_add_number == 0)
4648 return 0;
4649
4650 /* Sign-extend 32-bit unsigned numbers, so that the following range
4651 checks will work. */
4652 val = e->X_add_number;
4653 if (((val & (~(bfd_vma)0 << 32)) == 0)
4654 && ((val & ((bfd_vma)1 << 31)) != 0))
4655 val = ((val << 32) >> 32);
4656
4657 /* Check for 0x100000000. This is valid because
4658 0x100000000-1 is the same as ((uint32_t) -1). */
4659 if (val == ((bfd_signed_vma) 1 << 32))
4660 return 1;
4661
4662 val = val - 1;
4663 }
4664 else if (opnd == IA64_OPND_IMM8M1U8)
4665 {
4666 /* Zero is not valid for unsigned compares that take an adjusted
4667 constant immediate range. */
4668 if (e->X_add_number == 0)
4669 return 0;
4670
4671 /* Check for 0x10000000000000000. */
4672 if (e->X_op == O_big)
4673 {
4674 if (generic_bignum[0] == 0
4675 && generic_bignum[1] == 0
4676 && generic_bignum[2] == 0
4677 && generic_bignum[3] == 0
4678 && generic_bignum[4] == 1)
4679 return 1;
4680 else
4681 return 0;
4682 }
4683 else
4684 val = e->X_add_number - 1;
4685 }
4686 else if (opnd == IA64_OPND_IMM8M1)
4687 val = e->X_add_number - 1;
4688 else if (opnd == IA64_OPND_IMM8U4)
4689 {
4690 /* Sign-extend 32-bit unsigned numbers, so that the following range
4691 checks will work. */
4692 val = e->X_add_number;
4693 if (((val & (~(bfd_vma)0 << 32)) == 0)
4694 && ((val & ((bfd_vma)1 << 31)) != 0))
4695 val = ((val << 32) >> 32);
4696 }
4697 else
4698 val = e->X_add_number;
4699
4700 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4701 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4702 return 1;
4703 break;
4704
4705 case IA64_OPND_INC3:
4706 /* +/- 1, 4, 8, 16 */
4707 val = e->X_add_number;
4708 if (val < 0)
4709 val = -val;
4710 if (e->X_op == O_constant
4711 && (val == 1 || val == 4 || val == 8 || val == 16))
4712 return 1;
4713 break;
4714
4715 case IA64_OPND_TGT25:
4716 case IA64_OPND_TGT25b:
4717 case IA64_OPND_TGT25c:
4718 case IA64_OPND_TGT64:
4719 if (e->X_op == O_symbol)
4720 {
4721 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4722 if (opnd == IA64_OPND_TGT25)
4723 fix->code = BFD_RELOC_IA64_PCREL21F;
4724 else if (opnd == IA64_OPND_TGT25b)
4725 fix->code = BFD_RELOC_IA64_PCREL21M;
4726 else if (opnd == IA64_OPND_TGT25c)
4727 fix->code = BFD_RELOC_IA64_PCREL21B;
c67e42c9
RH		 4728 else if (opnd == IA64_OPND_TGT64)
4729 fix->code = BFD_RELOC_IA64_PCREL60B;
4730 else
4731 abort ();
4732
800eeca4
JW		 4733 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4734 fix->opnd = idesc->operands[index];
4735 fix->expr = *e;
4736 fix->is_pcrel = 1;
4737 ++CURR_SLOT.num_fixups;
4738 return 1;
4739 }
4740 case IA64_OPND_TAG13:
4741 case IA64_OPND_TAG13b:
4742 switch (e->X_op)
4743 {
4744 case O_constant:
4745 return 1;
4746
4747 case O_symbol:
4748 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4749 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4750 fix->opnd = idesc->operands[index];
4751 fix->expr = *e;
4752 fix->is_pcrel = 1;
4753 ++CURR_SLOT.num_fixups;
4754 return 1;
4755
4756 default:
4757 break;
4758 }
4759 break;
4760
4761 default:
4762 break;
4763 }
4764 return 0;
4765}
4766
4767static int
4768parse_operand (e)
4769 expressionS *e;
4770{
4771 int sep = '\0';
4772
4773 memset (e, 0, sizeof (*e));
4774 e->X_op = O_absent;
4775 SKIP_WHITESPACE ();
4776 if (*input_line_pointer != '}')
4777 expression (e);
4778 sep = *input_line_pointer++;
4779
4780 if (sep == '}')
4781 {
4782 if (!md.manual_bundling)
4783 as_warn ("Found '}' when manual bundling is off");
4784 else
4785 CURR_SLOT.manual_bundling_off = 1;
4786 md.manual_bundling = 0;
4787 sep = '\0';
4788 }
4789 return sep;
4790}
4791
4792/* Returns the next entry in the opcode table that matches the one in
4793 IDESC, and frees the entry in IDESC. If no matching entry is
4794 found, NULL is returned instead. */
4795
4796static struct ia64_opcode *
4797get_next_opcode (struct ia64_opcode *idesc)
4798{
4799 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4800 ia64_free_opcode (idesc);
4801 return next;
4802}
4803
4804/* Parse the operands for the opcode and find the opcode variant that
4805 matches the specified operands, or NULL if no match is possible. */
4806static struct ia64_opcode*
4807parse_operands (idesc)
4808 struct ia64_opcode *idesc;
4809{
4810 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4811 int sep = 0;
4812 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4813 char mnemonic[129];
4814 char *first_arg = 0, *end, *saved_input_pointer;
4815 unsigned int sof;
4816
4817 assert (strlen (idesc->name) <= 128);
4818
4819 strcpy (mnemonic, idesc->name);
4820 if (idesc->operands[2] == IA64_OPND_SOF)
4821 {
4822 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4823 can't parse the first operand until we have parsed the
4824 remaining operands of the "alloc" instruction. */
4825 SKIP_WHITESPACE ();
4826 first_arg = input_line_pointer;
4827 end = strchr (input_line_pointer, '=');
4828 if (!end)
4829 {
4830 as_bad ("Expected separator `='");
4831 return 0;
4832 }
4833 input_line_pointer = end + 1;
4834 ++i;
4835 ++num_outputs;
4836 }
4837
4838 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
4839 {
4840 sep = parse_operand (CURR_SLOT.opnd + i);
4841 if (CURR_SLOT.opnd[i].X_op == O_absent)
4842 break;
4843
4844 ++num_operands;
4845
4846 if (sep != '=' && sep != ',')
4847 break;
4848
4849 if (sep == '=')
4850 {
4851 if (num_outputs > 0)
4852 as_bad ("Duplicate equal sign (=) in instruction");
4853 else
4854 num_outputs = i + 1;
4855 }
4856 }
4857 if (sep != '\0')
4858 {
4859 as_bad ("Illegal operand separator `%c'", sep);
4860 return 0;
4861 }
4862
4863 if (idesc->operands[2] == IA64_OPND_SOF)
4864 {
4865 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
4866 know (strcmp (idesc->name, "alloc") == 0);
4867 if (num_operands == 5 /* first_arg not included in this count! */
4868 && CURR_SLOT.opnd[2].X_op == O_constant
4869 && CURR_SLOT.opnd[3].X_op == O_constant
4870 && CURR_SLOT.opnd[4].X_op == O_constant
4871 && CURR_SLOT.opnd[5].X_op == O_constant)
4872 {
4873 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
4874 CURR_SLOT.opnd[3].X_add_number,
4875 CURR_SLOT.opnd[4].X_add_number,
4876 CURR_SLOT.opnd[5].X_add_number);
4877
4878 /* now we can parse the first arg: */
4879 saved_input_pointer = input_line_pointer;
4880 input_line_pointer = first_arg;
4881 sep = parse_operand (CURR_SLOT.opnd + 0);
4882 if (sep != '=')
4883 --num_outputs; /* force error */
4884 input_line_pointer = saved_input_pointer;
4885
4886 CURR_SLOT.opnd[2].X_add_number = sof;
4887 CURR_SLOT.opnd[3].X_add_number
4888 = sof - CURR_SLOT.opnd[4].X_add_number;
4889 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
4890 }
4891 }
4892
4893 highest_unmatched_operand = 0;
4894 expected_operand = idesc->operands[0];
4895 for (; idesc; idesc = get_next_opcode (idesc))
4896 {
4897 if (num_outputs != idesc->num_outputs)
4898 continue; /* mismatch in # of outputs */
4899
4900 CURR_SLOT.num_fixups = 0;
4901 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
4902 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
4903 break;
4904
4905 if (i != num_operands)
4906 {
4907 if (i > highest_unmatched_operand)
4908 {
4909 highest_unmatched_operand = i;
4910 expected_operand = idesc->operands[i];
4911 }
4912 continue;
4913 }
4914
4915 if (num_operands < NELEMS (idesc->operands)
4916 && idesc->operands[num_operands])
4917 continue; /* mismatch in number of arguments */
4918
4919 break;
4920 }
4921 if (!idesc)
4922 {
4923 if (expected_operand)
4924 as_bad ("Operand %u of `%s' should be %s",
4925 highest_unmatched_operand + 1, mnemonic,
4926 elf64_ia64_operands[expected_operand].desc);
4927 else
4928 as_bad ("Operand mismatch");
4929 return 0;
4930 }
4931 return idesc;
4932}
4933
4934static void
4935build_insn (slot, insnp)
4936 struct slot *slot;
4937 bfd_vma *insnp;
4938{
4939 const struct ia64_operand *odesc, *o2desc;
4940 struct ia64_opcode *idesc = slot->idesc;
4941 bfd_signed_vma insn, val;
4942 const char *err;
4943 int i;
4944
4945 insn = idesc->opcode | slot->qp_regno;
4946
4947 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
4948 {
c67e42c9
RH		 4949 if (slot->opnd[i].X_op == O_register
4950 || slot->opnd[i].X_op == O_constant
4951 || slot->opnd[i].X_op == O_index)
4952 val = slot->opnd[i].X_add_number;
4953 else if (slot->opnd[i].X_op == O_big)
800eeca4 4954 {
c67e42c9
RH		 4955 /* This must be the value 0x10000000000000000. */
4956 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
4957 val = 0;
4958 }
4959 else
4960 val = 0;
4961
4962 switch (idesc->operands[i])
4963 {
4964 case IA64_OPND_IMMU64:
800eeca4
JW		 4965 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
4966 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
4967 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
4968 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 4969 continue;
4970
4971 case IA64_OPND_IMMU62:
4972 val &= 0x3fffffffffffffffULL;
800eeca4
JW		 4973 if (val != slot->opnd[i].X_add_number)
4974 as_warn (_("Value truncated to 62 bits"));
4975 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
4976 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 4977 continue;
800eeca4 4978
c67e42c9
RH		 4979 case IA64_OPND_TGT64:
4980 val >>= 4;
4981 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
4982 insn |= ((((val >> 59) & 0x1) << 36)
4983 | (((val >> 0) & 0xfffff) << 13));
4984 continue;
800eeca4 4985
c67e42c9
RH		 4986 case IA64_OPND_AR3:
4987 val -= REG_AR;
4988 break;
4989
4990 case IA64_OPND_B1:
4991 case IA64_OPND_B2:
4992 val -= REG_BR;
4993 break;
4994
4995 case IA64_OPND_CR3:
4996 val -= REG_CR;
4997 break;
4998
4999 case IA64_OPND_F1:
5000 case IA64_OPND_F2:
5001 case IA64_OPND_F3:
5002 case IA64_OPND_F4:
5003 val -= REG_FR;
5004 break;
5005
5006 case IA64_OPND_P1:
5007 case IA64_OPND_P2:
5008 val -= REG_P;
5009 break;
5010
5011 case IA64_OPND_R1:
5012 case IA64_OPND_R2:
5013 case IA64_OPND_R3:
5014 case IA64_OPND_R3_2:
5015 case IA64_OPND_CPUID_R3:
5016 case IA64_OPND_DBR_R3:
5017 case IA64_OPND_DTR_R3:
5018 case IA64_OPND_ITR_R3:
5019 case IA64_OPND_IBR_R3:
5020 case IA64_OPND_MR3:
5021 case IA64_OPND_MSR_R3:
5022 case IA64_OPND_PKR_R3:
5023 case IA64_OPND_PMC_R3:
5024 case IA64_OPND_PMD_R3:
5025 case IA64_OPND_RR_R3:
5026 val -= REG_GR;
5027 break;
5028
5029 default:
5030 break;
5031 }
5032
5033 odesc = elf64_ia64_operands + idesc->operands[i];
5034 err = (*odesc->insert) (odesc, val, &insn);
5035 if (err)
5036 as_bad_where (slot->src_file, slot->src_line,
5037 "Bad operand value: %s", err);
5038 if (idesc->flags & IA64_OPCODE_PSEUDO)
5039 {
5040 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5041 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5042 {
5043 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5044 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5045 }
c67e42c9
RH		 5046 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5047 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5048 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5049 {
c67e42c9
RH		 5050 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5051 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5052 }
5053 }
5054 }
5055 *insnp = insn;
5056}
5057
5058static void
5059emit_one_bundle ()
5060{
5061 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5062 unsigned int manual_bundling = 0;
5063 enum ia64_unit required_unit, insn_unit = 0;
5064 enum ia64_insn_type type[3], insn_type;
5065 unsigned int template, orig_template;
5066 bfd_vma insn[3] = {-1, -1, -1};
5067 struct ia64_opcode *idesc;
5068 int end_of_insn_group = 0, user_template = -1;
5069 int n, i, j, first, curr;
e0c9811a 5070 unw_rec_list *ptr, *prev;
800eeca4
JW		 5071 bfd_vma t0 = 0, t1 = 0;
5072 struct label_fix *lfix;
5073 struct insn_fix *ifix;
5074 char mnemonic[16];
5075 fixS *fix;
5076 char *f;
5077
5078 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5079 know (first >= 0 & first < NUM_SLOTS);
5080 n = MIN (3, md.num_slots_in_use);
5081
5082 /* Determine template: user user_template if specified, best match
5083 otherwise: */
5084
5085 if (md.slot[first].user_template >= 0)
5086 user_template = template = md.slot[first].user_template;
5087 else
5088 {
5089 /* auto select appropriate template */
5090 memset (type, 0, sizeof (type));
5091 curr = first;
5092 for (i = 0; i < n; ++i)
5093 {
5094 type[i] = md.slot[curr].idesc->type;
5095 curr = (curr + 1) % NUM_SLOTS;
5096 }
5097 template = best_template[type[0]][type[1]][type[2]];
5098 }
5099
5100 /* initialize instructions with appropriate nops: */
5101 for (i = 0; i < 3; ++i)
5102 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5103
5104 f = frag_more (16);
5105
5106 /* now fill in slots with as many insns as possible: */
5107 curr = first;
5108 idesc = md.slot[curr].idesc;
5109 end_of_insn_group = 0;
5110 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5111 {
e0c9811a
JW		 5112 /* Set the slot number for prologue/body records now as those
5113 refer to the current point, not the point after the
5114 instruction has been issued: */
5115 prev = 0;
5116 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5117 {
5118 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5119 || ptr->r.type == body)
5120 {
5121 ptr->slot_number = (unsigned long) f + i;
5122 if (prev)
5123 prev->next = ptr->next;
5124 else
5125 md.slot[curr].unwind_record = ptr->next;
5126 }
5127 else
5128 prev = ptr;
5129 }
5130
800eeca4
JW		 5131 if (idesc->flags & IA64_OPCODE_SLOT2)
5132 {
5133 if (manual_bundling && i != 2)
5134 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5135 "`%s' must be last in bundle", idesc->name);
5136 else
5137 i = 2;
5138 }
5139 if (idesc->flags & IA64_OPCODE_LAST)
5140 {
5141 int required_slot, required_template;
5142
5143 /* If we need a stop bit after an M slot, our only choice is
5144 template 5 (M;;MI). If we need a stop bit after a B
5145 slot, our only choice is to place it at the end of the
5146 bundle, because the only available templates are MIB,
5147 MBB, BBB, MMB, and MFB. We don't handle anything other
5148 than M and B slots because these are the only kind of
5149 instructions that can have the IA64_OPCODE_LAST bit set. */
5150 required_template = template;
5151 switch (idesc->type)
5152 {
5153 case IA64_TYPE_M:
5154 required_slot = 0;
5155 required_template = 5;
5156 break;
5157
5158 case IA64_TYPE_B:
5159 required_slot = 2;
5160 break;
5161
5162 default:
5163 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5164 "Internal error: don't know how to force %s to end"
5165 "of instruction group", idesc->name);
5166 required_slot = i;
5167 break;
5168 }
5169 if (manual_bundling && i != required_slot)
5170 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5171 "`%s' must be last in instruction group",
5172 idesc->name);
5173 if (required_slot < i)
5174 /* Can't fit this instruction. */
5175 break;
5176
5177 i = required_slot;
5178 if (required_template != template)
5179 {
5180 /* If we switch the template, we need to reset the NOPs
5181 after slot i. The slot-types of the instructions ahead
5182 of i never change, so we don't need to worry about
5183 changing NOPs in front of this slot. */
5184 for (j = i; j < 3; ++j)
5185 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5186 }
5187 template = required_template;
5188 }
5189 if (curr != first && md.slot[curr].label_fixups)
5190 {
5191 if (manual_bundling_on)
5192 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5193 "Label must be first in a bundle");
5194 /* This insn must go into the first slot of a bundle. */
5195 break;
5196 }
5197
5198 manual_bundling_on = md.slot[curr].manual_bundling_on;
5199 manual_bundling_off = md.slot[curr].manual_bundling_off;
5200
5201 if (manual_bundling_on)
5202 {
5203 if (curr == first)
5204 manual_bundling = 1;
5205 else
5206 break; /* need to start a new bundle */
5207 }
5208
5209 if (end_of_insn_group && md.num_slots_in_use >= 1)
5210 {
5211 /* We need an instruction group boundary in the middle of a
5212 bundle. See if we can switch to an other template with
5213 an appropriate boundary. */
5214
5215 orig_template = template;
5216 if (i == 1 && (user_template == 4
5217 || (user_template < 0
5218 && (ia64_templ_desc[template].exec_unit[0]
5219 == IA64_UNIT_M))))
5220 {
5221 template = 5;
5222 end_of_insn_group = 0;
5223 }
5224 else if (i == 2 && (user_template == 0
5225 || (user_template < 0
5226 && (ia64_templ_desc[template].exec_unit[1]
5227 == IA64_UNIT_I)))
5228 /* This test makes sure we don't switch the template if
5229 the next instruction is one that needs to be first in
5230 an instruction group. Since all those instructions are
5231 in the M group, there is no way such an instruction can
5232 fit in this bundle even if we switch the template. The
5233 reason we have to check for this is that otherwise we
5234 may end up generating "MI;;I M.." which has the deadly
5235 effect that the second M instruction is no longer the
5236 first in the bundle! --davidm 99/12/16 */
5237 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5238 {
5239 template = 1;
5240 end_of_insn_group = 0;
5241 }
5242 else if (curr != first)
5243 /* can't fit this insn */
5244 break;
5245
5246 if (template != orig_template)
5247 /* if we switch the template, we need to reset the NOPs
5248 after slot i. The slot-types of the instructions ahead
5249 of i never change, so we don't need to worry about
5250 changing NOPs in front of this slot. */
5251 for (j = i; j < 3; ++j)
5252 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5253 }
5254 required_unit = ia64_templ_desc[template].exec_unit[i];
5255
5256 /* resolve dynamic opcodes such as "break" and "nop": */
5257 if (idesc->type == IA64_TYPE_DYN)
5258 {
5259 if ((strcmp (idesc->name, "nop") == 0)
5260 || (strcmp (idesc->name, "break") == 0))
5261 insn_unit = required_unit;
5262 else if (strcmp (idesc->name, "chk.s") == 0)
5263 {
5264 insn_unit = IA64_UNIT_M;
5265 if (required_unit == IA64_UNIT_I)
5266 insn_unit = IA64_UNIT_I;
5267 }
5268 else
5269 as_fatal ("emit_one_bundle: unexpected dynamic op");
5270
5271 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
5272 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5273#if 0
5274 know (!idesc->next); /* no resolved dynamic ops have collisions */
5275#endif
5276 }
5277 else
5278 {
5279 insn_type = idesc->type;
5280 insn_unit = IA64_UNIT_NIL;
5281 switch (insn_type)
5282 {
5283 case IA64_TYPE_A:
5284 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5285 insn_unit = required_unit;
5286 break;
5287 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5288 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5289 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5290 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5291 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5292 default: break;
5293 }
5294 }
5295
5296 if (insn_unit != required_unit)
5297 {
5298 if (required_unit == IA64_UNIT_L
5299 && insn_unit == IA64_UNIT_I
5300 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5301 {
5302 /* we got ourselves an MLX template but the current
5303 instruction isn't an X-unit, or an I-unit instruction
5304 that can go into the X slot of an MLX template. Duh. */
5305 if (md.num_slots_in_use >= NUM_SLOTS)
5306 {
5307 as_bad_where (md.slot[curr].src_file,
5308 md.slot[curr].src_line,
5309 "`%s' can't go in X slot of "
5310 "MLX template", idesc->name);
5311 /* drop this insn so we don't livelock: */
5312 --md.num_slots_in_use;
5313 }
5314 break;
5315 }
5316 continue; /* try next slot */
5317 }
5318
5319 if (debug_type == DEBUG_DWARF2)
5320 {
5321 bfd_vma addr;
5322
5323 addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
5324 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5325 }
5326
5327 build_insn (md.slot + curr, insn + i);
5328
5329 /* Set slot counts for unwind records. */
5330 while (md.slot[curr].unwind_record)
5331 {
e0c9811a 5332 md.slot[curr].unwind_record->slot_number = (unsigned long) f + i;
800eeca4
JW		 5333 md.slot[curr].unwind_record = md.slot[curr].unwind_record->next;
5334 }
e0c9811a 5335 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
800eeca4
JW		 5336 if (required_unit == IA64_UNIT_L)
5337 {
5338 know (i == 1);
5339 /* skip one slot for long/X-unit instructions */
5340 ++i;
5341 }
5342 --md.num_slots_in_use;
5343
5344 /* now is a good time to fix up the labels for this insn: */
5345 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5346 {
5347 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5348 symbol_set_frag (lfix->sym, frag_now);
5349 }
5350
5351 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5352 {
5353 ifix = md.slot[curr].fixup + j;
5354 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5355 &ifix->expr, ifix->is_pcrel, ifix->code);
5356 fix->tc_fix_data.opnd = ifix->opnd;
5357 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5358 fix->fx_file = md.slot[curr].src_file;
5359 fix->fx_line = md.slot[curr].src_line;
5360 }
5361
5362 end_of_insn_group = md.slot[curr].end_of_insn_group;
5363
5364 /* clear slot: */
5365 ia64_free_opcode (md.slot[curr].idesc);
5366 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5367 md.slot[curr].user_template = -1;
5368
5369 if (manual_bundling_off)
5370 {
5371 manual_bundling = 0;
5372 break;
5373 }
5374 curr = (curr + 1) % NUM_SLOTS;
5375 idesc = md.slot[curr].idesc;
5376 }
5377 if (manual_bundling)
5378 {
5379 if (md.num_slots_in_use > 0)
5380 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5381 "`%s' does not fit into %s template",
5382 idesc->name, ia64_templ_desc[template].name);
5383 else
5384 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5385 "Missing '}' at end of file");
5386 }
5387 know (md.num_slots_in_use < NUM_SLOTS);
5388
5389 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5390 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5391
5392 md_number_to_chars (f + 0, t0, 8);
5393 md_number_to_chars (f + 8, t1, 8);
5394}
5395
5396int
5397md_parse_option (c, arg)
5398 int c;
5399 char *arg;
5400{
5401 /* Switches from the Intel assembler. */
5402 switch (c)
5403 {
5404 case 'M':
5405 if (strcmp (arg, "ilp64") == 0
5406 || strcmp (arg, "lp64") == 0
5407 || strcmp (arg, "p64") == 0)
5408 {
5409 md.flags |= EF_IA_64_ABI64;
5410 }
5411 else if (strcmp (arg, "ilp32") == 0)
5412 {
5413 md.flags &= ~EF_IA_64_ABI64;
5414 }
5415 else if (strcmp (arg, "le") == 0)
5416 {
5417 md.flags &= ~EF_IA_64_BE;
5418 }
5419 else if (strcmp (arg, "be") == 0)
5420 {
5421 md.flags |= EF_IA_64_BE;
5422 }
5423 else
5424 return 0;
5425 break;
5426
5427 case 'N':
5428 if (strcmp (arg, "so") == 0)
5429 {
5430 /* Suppress signon message. */
5431 }
5432 else if (strcmp (arg, "pi") == 0)
5433 {
5434 /* Reject privileged instructions. FIXME */
5435 }
5436 else if (strcmp (arg, "us") == 0)
5437 {
5438 /* Allow union of signed and unsigned range. FIXME */
5439 }
5440 else if (strcmp (arg, "close_fcalls") == 0)
5441 {
5442 /* Do not resolve global function calls. */
5443 }
5444 else
5445 return 0;
5446 break;
5447
5448 case 'C':
5449 /* temp[="prefix"] Insert temporary labels into the object file
5450 symbol table prefixed by "prefix".
5451 Default prefix is ":temp:".
5452 */
5453 break;
5454
5455 case 'a':
5456 /* ??? Conflicts with gas' listing option. */
5457 /* indirect=<tgt> Assume unannotated indirect branches behavior
5458 according to <tgt> --
5459 exit: branch out from the current context (default)
5460 labels: all labels in context may be branch targets
5461 */
5462 break;
5463
5464 case 'x':
5465 /* -X conflicts with an ignored option, use -x instead */
5466 md.detect_dv = 1;
5467 if (!arg || strcmp (arg, "explicit") == 0)
5468 {
5469 /* set default mode to explicit */
5470 md.default_explicit_mode = 1;
5471 break;
5472 }
5473 else if (strcmp (arg, "auto") == 0)
5474 {
5475 md.default_explicit_mode = 0;
5476 }
5477 else if (strcmp (arg, "debug") == 0)
5478 {
5479 md.debug_dv = 1;
5480 }
5481 else if (strcmp (arg, "debugx") == 0)
5482 {
5483 md.default_explicit_mode = 1;
5484 md.debug_dv = 1;
5485 }
5486 else
5487 {
5488 as_bad (_("Unrecognized option '-x%s'"), arg);
5489 }
5490 break;
5491
5492 case 'S':
5493 /* nops Print nops statistics. */
5494 break;
5495
5496 default:
5497 return 0;
5498 }
5499
5500 return 1;
5501}
5502
5503void
5504md_show_usage (stream)
5505 FILE *stream;
5506{
5507 fputs(_("\
5508IA-64 options:\n\
5509 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5510 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5511 -x | -xexplicit turn on dependency violation checking (default)\n\
5512 -xauto automagically remove dependency violations\n\
5513 -xdebug debug dependency violation checker\n"),
5514 stream);
5515}
5516
5517static inline int
5518match (int templ, int type, int slot)
5519{
5520 enum ia64_unit unit;
5521 int result;
5522
5523 unit = ia64_templ_desc[templ].exec_unit[slot];
5524 switch (type)
5525 {
5526 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5527 case IA64_TYPE_A:
5528 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5529 break;
5530 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5531 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5532 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5533 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5534 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5535 default: result = 0; break;
5536 }
5537 return result;
5538}
5539
5540/* This function is called once, at assembler startup time. It sets
5541 up all the tables, etc. that the MD part of the assembler will need
5542 that can be determined before arguments are parsed. */
5543void
5544md_begin ()
5545{
5546 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
5547 const char *err;
5548 char name[8];
5549
5550 md.auto_align = 1;
5551 md.explicit_mode = md.default_explicit_mode;
5552
5553 bfd_set_section_alignment (stdoutput, text_section, 4);
5554
5555 target_big_endian = 0;
5556 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
5557 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5558 &zero_address_frag);
5559
5560 pseudo_func[FUNC_GP_RELATIVE].u.sym =
5561 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5562 &zero_address_frag);
5563
5564 pseudo_func[FUNC_LT_RELATIVE].u.sym =
5565 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5566 &zero_address_frag);
5567
c67e42c9
RH		 5568 pseudo_func[FUNC_PC_RELATIVE].u.sym =
5569 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5570 &zero_address_frag);
5571
800eeca4
JW		 5572 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
5573 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5574 &zero_address_frag);
5575
5576 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
5577 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5578 &zero_address_frag);
5579
5580 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
5581 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5582 &zero_address_frag);
5583
5584 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
5585 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5586 &zero_address_frag);
5587
5588 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
5589 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5590 &zero_address_frag);
5591
5592 /* compute the table of best templates: */
5593 for (i = 0; i < IA64_NUM_TYPES; ++i)
5594 for (j = 0; j < IA64_NUM_TYPES; ++j)
5595 for (k = 0; k < IA64_NUM_TYPES; ++k)
5596 {
5597 best = 0;
5598 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5599 {
5600 goodness = 0;
5601 if (match (t, i, 0))
5602 {
5603 if (match (t, j, 1))
5604 {
5605 if (match (t, k, 2))
5606 goodness = 3;
5607 else
5608 goodness = 2;
5609 }
5610 else if (match (t, j, 2))
5611 goodness = 2;
5612 else
5613 goodness = 1;
5614 }
5615 else if (match (t, i, 1))
5616 {
5617 if (match (t, j, 2))
5618 goodness = 2;
5619 else
5620 goodness = 1;
5621 }
5622 else if (match (t, i, 2))
5623 goodness = 1;
5624
5625 if (goodness > best)
5626 {
5627 best = goodness;
5628 best_template[i][j][k] = t;
5629 }
5630 }
5631 }
5632
5633 for (i = 0; i < NUM_SLOTS; ++i)
5634 md.slot[i].user_template = -1;
5635
5636 md.pseudo_hash = hash_new ();
5637 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5638 {
5639 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5640 (void *) (pseudo_opcode + i));
5641 if (err)
5642 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5643 pseudo_opcode[i].name, err);
5644 }
5645
5646 md.reg_hash = hash_new ();
5647 md.dynreg_hash = hash_new ();
5648 md.const_hash = hash_new ();
5649 md.entry_hash = hash_new ();
5650
5651 /* general registers: */
5652
5653 total = 128;
5654 for (i = 0; i < total; ++i)
5655 {
5656 sprintf (name, "r%d", i - REG_GR);
5657 md.regsym[i] = declare_register (name, i);
5658 }
5659
5660 /* floating point registers: */
5661 total += 128;
5662 for (; i < total; ++i)
5663 {
5664 sprintf (name, "f%d", i - REG_FR);
5665 md.regsym[i] = declare_register (name, i);
5666 }
5667
5668 /* application registers: */
5669 total += 128;
5670 ar_base = i;
5671 for (; i < total; ++i)
5672 {
5673 sprintf (name, "ar%d", i - REG_AR);
5674 md.regsym[i] = declare_register (name, i);
5675 }
5676
5677 /* control registers: */
5678 total += 128;
5679 cr_base = i;
5680 for (; i < total; ++i)
5681 {
5682 sprintf (name, "cr%d", i - REG_CR);
5683 md.regsym[i] = declare_register (name, i);
5684 }
5685
5686 /* predicate registers: */
5687 total += 64;
5688 for (; i < total; ++i)
5689 {
5690 sprintf (name, "p%d", i - REG_P);
5691 md.regsym[i] = declare_register (name, i);
5692 }
5693
5694 /* branch registers: */
5695 total += 8;
5696 for (; i < total; ++i)
5697 {
5698 sprintf (name, "b%d", i - REG_BR);
5699 md.regsym[i] = declare_register (name, i);
5700 }
5701
5702 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5703 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5704 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5705 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5706 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5707 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5708 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5709
5710 for (i = 0; i < NELEMS (indirect_reg); ++i)
5711 {
5712 regnum = indirect_reg[i].regnum;
5713 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5714 }
5715
5716 /* define synonyms for application registers: */
5717 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5718 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5719 REG_AR + ar[i - REG_AR].regnum);
5720
5721 /* define synonyms for control registers: */
5722 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5723 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5724 REG_CR + cr[i - REG_CR].regnum);
5725
5726 declare_register ("gp", REG_GR + 1);
5727 declare_register ("sp", REG_GR + 12);
5728 declare_register ("rp", REG_BR + 0);
5729
e0c9811a
JW		 5730 /* pseudo-registers used to specify unwind info: */
5731 declare_register ("psp", REG_PSP);
5732
800eeca4
JW		 5733 declare_register_set ("ret", 4, REG_GR + 8);
5734 declare_register_set ("farg", 8, REG_FR + 8);
5735 declare_register_set ("fret", 8, REG_FR + 8);
5736
5737 for (i = 0; i < NELEMS (const_bits); ++i)
5738 {
5739 err = hash_insert (md.const_hash, const_bits[i].name,
5740 (PTR) (const_bits + i));
5741 if (err)
5742 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5743 name, err);
5744 }
5745
5746 /* Default to 64-bit mode. */
5747 md.flags = EF_IA_64_ABI64;
5748
5749 md.mem_offset.hint = 0;
5750 md.path = 0;
5751 md.maxpaths = 0;
5752 md.entry_labels = NULL;
5753}
5754
5755void
5756ia64_end_of_source ()
5757{
5758 /* terminate insn group upon reaching end of file: */
5759 insn_group_break (1, 0, 0);
5760
5761 /* emits slots we haven't written yet: */
5762 ia64_flush_insns ();
5763
5764 bfd_set_private_flags (stdoutput, md.flags);
5765
5766 if (debug_type == DEBUG_DWARF2)
5767 dwarf2_finish ();
5768
5769 md.mem_offset.hint = 0;
5770}
5771
5772void
5773ia64_start_line ()
5774{
5775 md.qp.X_op = O_absent;
5776
5777 if (ignore_input ())
5778 return;
5779
5780 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
5781 {
5782 if (md.detect_dv && !md.explicit_mode)
5783 as_warn (_("Explicit stops are ignored in auto mode"));
5784 else
5785 insn_group_break (1, 0, 0);
5786 }
5787}
5788
5789int
5790ia64_unrecognized_line (ch)
5791 int ch;
5792{
5793 switch (ch)
5794 {
5795 case '(':
5796 expression (&md.qp);
5797 if (*input_line_pointer++ != ')')
5798 {
5799 as_bad ("Expected ')'");
5800 return 0;
5801 }
5802 if (md.qp.X_op != O_register)
5803 {
5804 as_bad ("Qualifying predicate expected");
5805 return 0;
5806 }
5807 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
5808 {
5809 as_bad ("Predicate register expected");
5810 return 0;
5811 }
5812 return 1;
5813
5814 case '{':
5815 if (md.manual_bundling)
5816 as_warn ("Found '{' when manual bundling is already turned on");
5817 else
5818 CURR_SLOT.manual_bundling_on = 1;
5819 md.manual_bundling = 1;
5820
5821 /* bundling is only acceptable in explicit mode
5822 or when in default automatic mode */
5823 if (md.detect_dv && !md.explicit_mode)
5824 {
5825 if (!md.mode_explicitly_set
5826 && !md.default_explicit_mode)
5827 dot_dv_mode ('E');
5828 else
5829 as_warn (_("Found '{' after explicit switch to automatic mode"));
5830 }
5831 return 1;
5832
5833 case '}':
5834 if (!md.manual_bundling)
5835 as_warn ("Found '}' when manual bundling is off");
5836 else
5837 PREV_SLOT.manual_bundling_off = 1;
5838 md.manual_bundling = 0;
5839
5840 /* switch back to automatic mode, if applicable */
5841 if (md.detect_dv
5842 && md.explicit_mode
5843 && !md.mode_explicitly_set
5844 && !md.default_explicit_mode)
5845 dot_dv_mode ('A');
5846
5847 /* Allow '{' to follow on the same line. We also allow ";;", but that
5848 happens automatically because ';' is an end of line marker. */
5849 SKIP_WHITESPACE ();
5850 if (input_line_pointer[0] == '{')
5851 {
5852 input_line_pointer++;
5853 return ia64_unrecognized_line ('{');
5854 }
5855
5856 demand_empty_rest_of_line ();
5857 return 1;
5858
5859 default:
5860 break;
5861 }
5862 return 0; /* not a valid line */
5863}
5864
5865void
5866ia64_frob_label (sym)
5867 struct symbol *sym;
5868{
5869 struct label_fix *fix;
5870
5871 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
5872 {
5873 md.last_text_seg = now_seg;
5874 fix = obstack_alloc (&notes, sizeof (*fix));
5875 fix->sym = sym;
5876 fix->next = CURR_SLOT.label_fixups;
5877 CURR_SLOT.label_fixups = fix;
5878
5879 /* keep track of how many code entry points we've seen */
5880 if (md.path == md.maxpaths)
5881 {
5882 md.maxpaths += 20;
5883 md.entry_labels = (const char **)
5884 xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
5885 }
5886 md.entry_labels[md.path++] = S_GET_NAME (sym);
5887 }
5888}
5889
5890void
5891ia64_flush_pending_output ()
5892{
5893 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
5894 {
5895 /* ??? This causes many unnecessary stop bits to be emitted.
5896 Unfortunately, it isn't clear if it is safe to remove this. */
5897 insn_group_break (1, 0, 0);
5898 ia64_flush_insns ();
5899 }
5900}
5901
5902/* Do ia64-specific expression optimization. All that's done here is
5903 to transform index expressions that are either due to the indexing
5904 of rotating registers or due to the indexing of indirect register
5905 sets. */
5906int
5907ia64_optimize_expr (l, op, r)
5908 expressionS *l;
5909 operatorT op;
5910 expressionS *r;
5911{
5912 unsigned num_regs;
5913
5914 if (op == O_index)
5915 {
5916 if (l->X_op == O_register && r->X_op == O_constant)
5917 {
5918 num_regs = (l->X_add_number >> 16);
5919 if ((unsigned) r->X_add_number >= num_regs)
5920 {
5921 if (!num_regs)
5922 as_bad ("No current frame");
5923 else
5924 as_bad ("Index out of range 0..%u", num_regs - 1);
5925 r->X_add_number = 0;
5926 }
5927 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
5928 return 1;
5929 }
5930 else if (l->X_op == O_register && r->X_op == O_register)
5931 {
5932 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
5933 || l->X_add_number == IND_MEM)
5934 {
5935 as_bad ("Indirect register set name expected");
5936 l->X_add_number = IND_CPUID;
5937 }
5938 l->X_op = O_index;
5939 l->X_op_symbol = md.regsym[l->X_add_number];
5940 l->X_add_number = r->X_add_number;
5941 return 1;
5942 }
5943 }
5944 return 0;
5945}
5946
5947int
5948ia64_parse_name (name, e)
5949 char *name;
5950 expressionS *e;
5951{
5952 struct const_desc *cdesc;
5953 struct dynreg *dr = 0;
5954 unsigned int regnum;
5955 struct symbol *sym;
5956 char *end;
5957
5958 /* first see if NAME is a known register name: */
5959 sym = hash_find (md.reg_hash, name);
5960 if (sym)
5961 {
5962 e->X_op = O_register;
5963 e->X_add_number = S_GET_VALUE (sym);
5964 return 1;
5965 }
5966
5967 cdesc = hash_find (md.const_hash, name);
5968 if (cdesc)
5969 {
5970 e->X_op = O_constant;
5971 e->X_add_number = cdesc->value;
5972 return 1;
5973 }
5974
5975 /* check for inN, locN, or outN: */
5976 switch (name[0])
5977 {
5978 case 'i':
5979 if (name[1] == 'n' && isdigit (name[2]))
5980 {
5981 dr = &md.in;
5982 name += 2;
5983 }
5984 break;
5985
5986 case 'l':
5987 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
5988 {
5989 dr = &md.loc;
5990 name += 3;
5991 }
5992 break;
5993
5994 case 'o':
5995 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
5996 {
5997 dr = &md.out;
5998 name += 3;
5999 }
6000 break;
6001
6002 default:
6003 break;
6004 }
6005
6006 if (dr)
6007 {
6008 /* the name is inN, locN, or outN; parse the register number: */
6009 regnum = strtoul (name, &end, 10);
6010 if (end > name && *end == '\0')
6011 {
6012 if ((unsigned) regnum >= dr->num_regs)
6013 {
6014 if (!dr->num_regs)
6015 as_bad ("No current frame");
6016 else
6017 as_bad ("Register number out of range 0..%u", dr->num_regs-1);
6018 regnum = 0;
6019 }
6020 e->X_op = O_register;
6021 e->X_add_number = dr->base + regnum;
6022 return 1;
6023 }
6024 }
6025
6026 if ((dr = hash_find (md.dynreg_hash, name)))
6027 {
6028 /* We've got ourselves the name of a rotating register set.
6029 Store the base register number in the low 16 bits of
6030 X_add_number and the size of the register set in the top 16
6031 bits. */
6032 e->X_op = O_register;
6033 e->X_add_number = dr->base | (dr->num_regs << 16);
6034 return 1;
6035 }
6036 return 0;
6037}
6038
6039/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6040
6041char *
6042ia64_canonicalize_symbol_name (name)
6043 char *name;
6044{
6045 size_t len = strlen(name);
6046 if (len > 1 && name[len-1] == '#')
6047 name[len-1] = '\0';
6048 return name;
6049}
6050
6051static int
6052is_conditional_branch (idesc)
6053 struct ia64_opcode *idesc;
6054{
6055 return (strncmp (idesc->name, "br", 2) == 0
6056 && (strcmp (idesc->name, "br") == 0
6057 || strncmp (idesc->name, "br.cond", 7) == 0
6058 || strncmp (idesc->name, "br.call", 7) == 0
6059 || strncmp (idesc->name, "br.ret", 6) == 0
6060 || strcmp (idesc->name, "brl") == 0
6061 || strncmp (idesc->name, "brl.cond", 7) == 0
6062 || strncmp (idesc->name, "brl.call", 7) == 0
6063 || strncmp (idesc->name, "brl.ret", 6) == 0));
6064}
6065
6066/* Return whether the given opcode is a taken branch. If there's any doubt,
6067 returns zero */
6068static int
6069is_taken_branch (idesc)
6070 struct ia64_opcode *idesc;
6071{
6072 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6073 || strncmp (idesc->name, "br.ia", 5) == 0);
6074}
6075
6076/* Return whether the given opcode is an interruption or rfi. If there's any
6077 doubt, returns zero */
6078static int
6079is_interruption_or_rfi (idesc)
6080 struct ia64_opcode *idesc;
6081{
6082 if (strcmp (idesc->name, "rfi") == 0)
6083 return 1;
6084 return 0;
6085}
6086
6087/* Returns the index of the given dependency in the opcode's list of chks, or
6088 -1 if there is no dependency. */
6089static int
6090depends_on (depind, idesc)
6091 int depind;
6092 struct ia64_opcode *idesc;
6093{
6094 int i;
6095 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6096 for (i = 0;i < dep->nchks; i++)
6097 {
6098 if (depind == DEP(dep->chks[i]))
6099 return i;
6100 }
6101 return -1;
6102}
6103
6104/* Determine a set of specific resources used for a particular resource
6105 class. Returns the number of specific resources identified For those
6106 cases which are not determinable statically, the resource returned is
6107 marked nonspecific.
6108
6109 Meanings of value in 'NOTE':
6110 1) only read/write when the register number is explicitly encoded in the
6111 insn.
6112 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6113 accesses CFM when qualifying predicate is in the rotating region.
6114 3) general register value is used to specify an indirect register; not
6115 determinable statically.
6116 4) only read the given resource when bits 7:0 of the indirect index
6117 register value does not match the register number of the resource; not
6118 determinable statically.
6119 5) all rules are implementation specific.
6120 6) only when both the index specified by the reader and the index specified
6121 by the writer have the same value in bits 63:61; not determinable
6122 statically.
6123 7) only access the specified resource when the corresponding mask bit is
6124 set
6125 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6126 only read when these insns reference FR2-31
6127 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6128 written when these insns write FR32-127
6129 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6130 instruction
6131 11) The target predicates are written independently of PR[qp], but source
6132 registers are only read if PR[qp] is true. Since the state of PR[qp]
6133 cannot statically be determined, all source registers are marked used.
6134 12) This insn only reads the specified predicate register when that
6135 register is the PR[qp].
6136 13) This reference to ld-c only applies to teh GR whose value is loaded
6137 with data returned from memory, not the post-incremented address register.
6138 14) The RSE resource includes the implementation-specific RSE internal
6139 state resources. At least one (and possibly more) of these resources are
6140 read by each instruction listed in IC:rse-readers. At least one (and
6141 possibly more) of these resources are written by each insn listed in
6142 IC:rse-writers.
6143 15+16) Represents reserved instructions, which the assembler does not
6144 generate.
6145
6146 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6147 this code; there are no dependency violations based on memory access.
6148
6149*/
6150
6151#define MAX_SPECS 256
6152#define DV_CHK 1
6153#define DV_REG 0
6154
6155static int
6156specify_resource (dep, idesc, type, specs, note, path)
6157 const struct ia64_dependency *dep;
6158 struct ia64_opcode *idesc;
6159 int type; /* is this a DV chk or a DV reg? */
6160 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6161 int note; /* resource note for this insn's usage */
6162 int path; /* which execution path to examine */
6163{
6164 int count = 0;
6165 int i;
6166 int rsrc_write = 0;
6167 struct rsrc tmpl;
6168
6169 if (dep->mode == IA64_DV_WAW
6170 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6171 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6172 rsrc_write = 1;
6173
6174 /* template for any resources we identify */
6175 tmpl.dependency = dep;
6176 tmpl.note = note;
6177 tmpl.insn_srlz = tmpl.data_srlz = 0;
6178 tmpl.qp_regno = CURR_SLOT.qp_regno;
6179 tmpl.link_to_qp_branch = 1;
6180 tmpl.mem_offset.hint = 0;
6181 tmpl.specific = 1;
6182 tmpl.index = 0;
6183
6184#define UNHANDLED \
6185as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6186dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6187#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6188
6189 /* we don't need to track these */
6190 if (dep->semantics == IA64_DVS_NONE)
6191 return 0;
6192
6193 switch (dep->specifier)
6194 {
6195 case IA64_RS_AR_K:
6196 if (note == 1)
6197 {
6198 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6199 {
6200 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6201 if (regno >= 0 && regno <= 7)
6202 {
6203 specs[count] = tmpl;
6204 specs[count++].index = regno;
6205 }
6206 }
6207 }
6208 else if (note == 0)
6209 {
6210 for(i=0;i < 8;i++)
6211 {
6212 specs[count] = tmpl;
6213 specs[count++].index = i;
6214 }
6215 }
6216 else
6217 {
6218 UNHANDLED;
6219 }
6220 break;
6221
6222 case IA64_RS_AR_UNAT:
6223 /* This is a mov =AR or mov AR= instruction. */
6224 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6225 {
6226 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6227 if (regno == AR_UNAT)
6228 {
6229 specs[count++] = tmpl;
6230 }
6231 }
6232 else
6233 {
6234 /* This is a spill/fill, or other instruction that modifies the
6235 unat register. */
6236
6237 /* Unless we can determine the specific bits used, mark the whole
6238 thing; bits 8:3 of the memory address indicate the bit used in
6239 UNAT. The .mem.offset hint may be used to eliminate a small
6240 subset of conflicts. */
6241 specs[count] = tmpl;
6242 if (md.mem_offset.hint)
6243 {
6244 if (md.debug_dv)
6245 fprintf (stderr, " Using hint for spill/fill\n");
6246 /* the index isn't actually used, just set it to something
6247 approximating the bit index */
6248 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6249 specs[count].mem_offset.hint = 1;
6250 specs[count].mem_offset.offset = md.mem_offset.offset;
6251 specs[count++].mem_offset.base = md.mem_offset.base;
6252 }
6253 else
6254 {
6255 specs[count++].specific = 0;
6256 }
6257 }
6258 break;
6259
6260 case IA64_RS_AR:
6261 if (note == 1)
6262 {
6263 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6264 {
6265 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6266 if ((regno >= 8 && regno <= 15)
6267 || (regno >= 20 && regno <= 23)
6268 || (regno >= 31 && regno <= 39)
6269 || (regno >= 41 && regno <= 47)
6270 || (regno >= 67 && regno <= 111))
6271 {
6272 specs[count] = tmpl;
6273 specs[count++].index = regno;
6274 }
6275 }
6276 }
6277 else
6278 {
6279 UNHANDLED;
6280 }
6281 break;
6282
6283 case IA64_RS_ARb:
6284 if (note == 1)
6285 {
6286 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6287 {
6288 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6289 if ((regno >= 48 && regno <= 63)
6290 || (regno >= 112 && regno <= 127))
6291 {
6292 specs[count] = tmpl;
6293 specs[count++].index = regno;
6294 }
6295 }
6296 }
6297 else if (note == 0)
6298 {
6299 for (i=48;i < 64;i++)
6300 {
6301 specs[count] = tmpl;
6302 specs[count++].index = i;
6303 }
6304 for (i=112;i < 128;i++)
6305 {
6306 specs[count] = tmpl;
6307 specs[count++].index = i;
6308 }
6309 }
6310 else
6311 {
6312 UNHANDLED;
6313 }
6314 break;
6315
6316 case IA64_RS_BR:
6317 if (note != 1)
6318 {
6319 UNHANDLED;
6320 }
6321 else
6322 {
6323 if (rsrc_write)
6324 {
6325 for (i=0;i < idesc->num_outputs;i++)
6326 if (idesc->operands[i] == IA64_OPND_B1
6327 || idesc->operands[i] == IA64_OPND_B2)
6328 {
6329 specs[count] = tmpl;
6330 specs[count++].index =
6331 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6332 }
6333 }
6334 else
6335 {
6336 for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6337 if (idesc->operands[i] == IA64_OPND_B1
6338 || idesc->operands[i] == IA64_OPND_B2)
6339 {
6340 specs[count] = tmpl;
6341 specs[count++].index =
6342 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6343 }
6344 }
6345 }
6346 break;
6347
6348 case IA64_RS_CPUID: /* four or more registers */
6349 if (note == 3)
6350 {
6351 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6352 {
6353 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6354 if (regno >= 0 && regno < NELEMS(gr_values)
6355 && KNOWN(regno))
6356 {
6357 specs[count] = tmpl;
6358 specs[count++].index = gr_values[regno].value & 0xFF;
6359 }
6360 else
6361 {
6362 specs[count] = tmpl;
6363 specs[count++].specific = 0;
6364 }
6365 }
6366 }
6367 else
6368 {
6369 UNHANDLED;
6370 }
6371 break;
6372
6373 case IA64_RS_DBR: /* four or more registers */
6374 if (note == 3)
6375 {
6376 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6377 {
6378 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6379 if (regno >= 0 && regno < NELEMS(gr_values)
6380 && KNOWN(regno))
6381 {
6382 specs[count] = tmpl;
6383 specs[count++].index = gr_values[regno].value & 0xFF;
6384 }
6385 else
6386 {
6387 specs[count] = tmpl;
6388 specs[count++].specific = 0;
6389 }
6390 }
6391 }
6392 else if (note == 0 && !rsrc_write)
6393 {
6394 specs[count] = tmpl;
6395 specs[count++].specific = 0;
6396 }
6397 else
6398 {
6399 UNHANDLED;
6400 }
6401 break;
6402
6403 case IA64_RS_IBR: /* four or more registers */
6404 if (note == 3)
6405 {
6406 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6407 {
6408 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6409 if (regno >= 0 && regno < NELEMS(gr_values)
6410 && KNOWN(regno))
6411 {
6412 specs[count] = tmpl;
6413 specs[count++].index = gr_values[regno].value & 0xFF;
6414 }
6415 else
6416 {
6417 specs[count] = tmpl;
6418 specs[count++].specific = 0;
6419 }
6420 }
6421 }
6422 else
6423 {
6424 UNHANDLED;
6425 }
6426 break;
6427
6428 case IA64_RS_MSR:
6429 if (note == 5)
6430 {
6431 /* These are implementation specific. Force all references to
6432 conflict with all other references. */
6433 specs[count] = tmpl;
6434 specs[count++].specific = 0;
6435 }
6436 else
6437 {
6438 UNHANDLED;
6439 }
6440 break;
6441
6442 case IA64_RS_PKR: /* 16 or more registers */
6443 if (note == 3 || note == 4)
6444 {
6445 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6446 {
6447 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6448 if (regno >= 0 && regno < NELEMS(gr_values)
6449 && KNOWN(regno))
6450 {
6451 if (note == 3)
6452 {
6453 specs[count] = tmpl;
6454 specs[count++].index = gr_values[regno].value & 0xFF;
6455 }
6456 else for (i=0;i < NELEMS(gr_values);i++)
6457 {
6458 /* uses all registers *except* the one in R3 */
6459 if (i != (gr_values[regno].value & 0xFF))
6460 {
6461 specs[count] = tmpl;
6462 specs[count++].index = i;
6463 }
6464 }
6465 }
6466 else
6467 {
6468 specs[count] = tmpl;
6469 specs[count++].specific = 0;
6470 }
6471 }
6472 }
6473 else if (note == 0)
6474 {
6475 /* probe et al. */
6476 specs[count] = tmpl;
6477 specs[count++].specific = 0;
6478 }
6479 break;
6480
6481 case IA64_RS_PMC: /* four or more registers */
6482 if (note == 3)
6483 {
6484 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6485 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6486
6487 {
6488 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6489 ? 1 : !rsrc_write);
6490 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6491 if (regno >= 0 && regno < NELEMS(gr_values)
6492 && KNOWN(regno))
6493 {
6494 specs[count] = tmpl;
6495 specs[count++].index = gr_values[regno].value & 0xFF;
6496 }
6497 else
6498 {
6499 specs[count] = tmpl;
6500 specs[count++].specific = 0;
6501 }
6502 }
6503 }
6504 else
6505 {
6506 UNHANDLED;
6507 }
6508 break;
6509
6510 case IA64_RS_PMD: /* four or more registers */
6511 if (note == 3)
6512 {
6513 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6514 {
6515 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6516 if (regno >= 0 && regno < NELEMS(gr_values)
6517 && KNOWN(regno))
6518 {
6519 specs[count] = tmpl;
6520 specs[count++].index = gr_values[regno].value & 0xFF;
6521 }
6522 else
6523 {
6524 specs[count] = tmpl;
6525 specs[count++].specific = 0;
6526 }
6527 }
6528 }
6529 else
6530 {
6531 UNHANDLED;
6532 }
6533 break;
6534
6535 case IA64_RS_RR: /* eight registers */
6536 if (note == 6)
6537 {
6538 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6539 {
6540 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6541 if (regno >= 0 && regno < NELEMS(gr_values)
6542 && KNOWN(regno))
6543 {
6544 specs[count] = tmpl;
6545 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6546 }
6547 else
6548 {
6549 specs[count] = tmpl;
6550 specs[count++].specific = 0;
6551 }
6552 }
6553 }
6554 else if (note == 0 && !rsrc_write)
6555 {
6556 specs[count] = tmpl;
6557 specs[count++].specific = 0;
6558 }
6559 else
6560 {
6561 UNHANDLED;
6562 }
6563 break;
6564
6565 case IA64_RS_CR_IRR:
6566 if (note == 0)
6567 {
6568 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6569 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6570 if (rsrc_write
6571 && idesc->operands[1] == IA64_OPND_CR3
6572 && regno == CR_IVR)
6573 {
6574 for(i=0;i < 4;i++)
6575 {
6576 specs[count] = tmpl;
6577 specs[count++].index = CR_IRR0 + i;
6578 }
6579 }
6580 }
6581 else if (note == 1)
6582 {
6583 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6584 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6585 && regno >= CR_IRR0
6586 && regno <= CR_IRR3)
6587 {
6588 specs[count] = tmpl;
6589 specs[count++].index = regno;
6590 }
6591 }
6592 else
6593 {
6594 UNHANDLED;
6595 }
6596 break;
6597
6598 case IA64_RS_CR_LRR:
6599 if (note != 1)
6600 {
6601 UNHANDLED;
6602 }
6603 else
6604 {
6605 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6606 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6607 && (regno == CR_LRR0 || regno == CR_LRR1))
6608 {
6609 specs[count] = tmpl;
6610 specs[count++].index = regno;
6611 }
6612 }
6613 break;
6614
6615 case IA64_RS_CR:
6616 if (note == 1)
6617 {
6618 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6619 {
6620 specs[count] = tmpl;
6621 specs[count++].index =
6622 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6623 }
6624 }
6625 else
6626 {
6627 UNHANDLED;
6628 }
6629 break;
6630
6631 case IA64_RS_FR:
6632 case IA64_RS_FRb:
6633 if (note != 1)
6634 {
6635 UNHANDLED;
6636 }
6637 else if (rsrc_write)
6638 {
6639 if (dep->specifier == IA64_RS_FRb
6640 && idesc->operands[0] == IA64_OPND_F1)
6641 {
6642 specs[count] = tmpl;
6643 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6644 }
6645 }
6646 else
6647 {
6648 for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6649 {
6650 if (idesc->operands[i] == IA64_OPND_F2
6651 || idesc->operands[i] == IA64_OPND_F3
6652 || idesc->operands[i] == IA64_OPND_F4)
6653 {
6654 specs[count] = tmpl;
6655 specs[count++].index =
6656 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6657 }
6658 }
6659 }
6660 break;
6661
6662 case IA64_RS_GR:
6663 if (note == 13)
6664 {
6665 /* This reference applies only to the GR whose value is loaded with
6666 data returned from memory */
6667 specs[count] = tmpl;
6668 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6669 }
6670 else if (note == 1)
6671 {
6672 if (rsrc_write)
6673 {
6674 for (i=0;i < idesc->num_outputs;i++)
6675 {
6676 if (idesc->operands[i] == IA64_OPND_R1
6677 || idesc->operands[i] == IA64_OPND_R2
6678 || idesc->operands[i] == IA64_OPND_R3)
6679 {
6680 specs[count] = tmpl;
6681 specs[count++].index =
6682 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6683 }
6684 }
6685 }
6686 else
6687 {
6688 /* Look for anything that reads a GR */
6689 for (i=0;i < NELEMS(idesc->operands);i++)
6690 {
6691 if (idesc->operands[i] == IA64_OPND_MR3
6692 || idesc->operands[i] == IA64_OPND_CPUID_R3
6693 || idesc->operands[i] == IA64_OPND_DBR_R3
6694 || idesc->operands[i] == IA64_OPND_IBR_R3
6695 || idesc->operands[i] == IA64_OPND_MSR_R3
6696 || idesc->operands[i] == IA64_OPND_PKR_R3
6697 || idesc->operands[i] == IA64_OPND_PMC_R3
6698 || idesc->operands[i] == IA64_OPND_PMD_R3
6699 || idesc->operands[i] == IA64_OPND_RR_R3
6700 || ((i >= idesc->num_outputs)
6701 && (idesc->operands[i] == IA64_OPND_R1
6702 || idesc->operands[i] == IA64_OPND_R2
6703 || idesc->operands[i] == IA64_OPND_R3)))
6704 {
6705 specs[count] = tmpl;
6706 specs[count++].index =
6707 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6708 }
6709 }
6710 }
6711 }
6712 else
6713 {
6714 UNHANDLED;
6715 }
6716 break;
6717
6718 case IA64_RS_PR:
6719 if (note == 0)
6720 {
6721 if (idesc->operands[0] == IA64_OPND_PR_ROT)
6722 {
6723 for (i=16;i < 63;i++)
6724 {
6725 specs[count] = tmpl;
6726 specs[count++].index = i;
6727 }
6728 }
6729 else
6730 {
6731 for (i=1;i < 63;i++)
6732 {
6733 specs[count] = tmpl;
6734 specs[count++].index = i;
6735 }
6736 }
6737 }
6738 else if (note == 7)
6739 {
6740 valueT mask = 0;
6741 /* mark only those registers indicated by the mask */
6742 if (rsrc_write
6743 && idesc->operands[0] == IA64_OPND_PR)
6744 {
6745 mask = CURR_SLOT.opnd[2].X_add_number;
6746 if (mask & ((valueT)1<<16))
6747 mask |= ~(valueT)0xffff;
6748 for (i=1;i < 63;i++)
6749 {
6750 if (mask & ((valueT)1<<i))
6751 {
6752 specs[count] = tmpl;
6753 specs[count++].index = i;
6754 }
6755 }
6756 }
6757 else if (rsrc_write
6758 && idesc->operands[0] == IA64_OPND_PR_ROT)
6759 {
6760 for (i=16;i < 63;i++)
6761 {
6762 specs[count] = tmpl;
6763 specs[count++].index = i;
6764 }
6765 }
6766 else
6767 {
6768 UNHANDLED;
6769 }
6770 }
6771 else if (note == 11) /* note 11 implies note 1 as well */
6772 {
6773 if (rsrc_write)
6774 {
6775 for (i=0;i < idesc->num_outputs;i++)
6776 {
6777 if (idesc->operands[i] == IA64_OPND_P1
6778 || idesc->operands[i] == IA64_OPND_P2)
6779 {
6780 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
6781 if (regno != 0)
6782 {
6783 specs[count] = tmpl;
6784 specs[count++].index = regno;
6785 }
6786 }
6787 }
6788 }
6789 else
6790 {
6791 UNHANDLED;
6792 }
6793 }
6794 else if (note == 12)
6795 {
6796 if (CURR_SLOT.qp_regno != 0)
6797 {
6798 specs[count] = tmpl;
6799 specs[count++].index = CURR_SLOT.qp_regno;
6800 }
6801 }
6802 else if (note == 1)
6803 {
6804 if (rsrc_write)
6805 {
6806 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
6807 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
6808 if ((idesc->operands[0] == IA64_OPND_P1
6809 || idesc->operands[0] == IA64_OPND_P2)
6810 && p1 != 0 && p1 != 63)
6811 {
6812 specs[count] = tmpl;
6813 specs[count++].index = p1;
6814 }
6815 if ((idesc->operands[1] == IA64_OPND_P1
6816 || idesc->operands[1] == IA64_OPND_P2)
6817 && p2 != 0 && p2 != 63)
6818 {
6819 specs[count] = tmpl;
6820 specs[count++].index = p2;
6821 }
6822 }
6823 else
6824 {
6825 if (CURR_SLOT.qp_regno != 0)
6826 {
6827 specs[count] = tmpl;
6828 specs[count++].index = CURR_SLOT.qp_regno;
6829 }
6830 if (idesc->operands[1] == IA64_OPND_PR)
6831 {
6832 for (i=1;i < 63;i++)
6833 {
6834 specs[count] = tmpl;
6835 specs[count++].index = i;
6836 }
6837 }
6838 }
6839 }
6840 else
6841 {
6842 UNHANDLED;
6843 }
6844 break;
6845
6846 case IA64_RS_PSR:
6847 /* Verify that the instruction is using the PSR bit indicated in
6848 dep->regindex */
6849 if (note == 0)
6850 {
6851 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
6852 {
6853 if (dep->regindex < 6)
6854 {
6855 specs[count++] = tmpl;
6856 }
6857 }
6858 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
6859 {
6860 if (dep->regindex < 32
6861 || dep->regindex == 35
6862 || dep->regindex == 36
6863 || (!rsrc_write && dep->regindex == PSR_CPL))
6864 {
6865 specs[count++] = tmpl;
6866 }
6867 }
6868 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
6869 {
6870 if (dep->regindex < 32
6871 || dep->regindex == 35
6872 || dep->regindex == 36
6873 || (rsrc_write && dep->regindex == PSR_CPL))
6874 {
6875 specs[count++] = tmpl;
6876 }
6877 }
6878 else
6879 {
6880 /* Several PSR bits have very specific dependencies. */
6881 switch (dep->regindex)
6882 {
6883 default:
6884 specs[count++] = tmpl;
6885 break;
6886 case PSR_IC:
6887 if (rsrc_write)
6888 {
6889 specs[count++] = tmpl;
6890 }
6891 else
6892 {
6893 /* Only certain CR accesses use PSR.ic */
6894 if (idesc->operands[0] == IA64_OPND_CR3
6895 || idesc->operands[1] == IA64_OPND_CR3)
6896 {
6897 int index =
6898 ((idesc->operands[0] == IA64_OPND_CR3)
6899 ? 0 : 1);
6900 int regno =
6901 CURR_SLOT.opnd[index].X_add_number - REG_CR;
6902
6903 switch (regno)
6904 {
6905 default:
6906 break;
6907 case CR_ITIR:
6908 case CR_IFS:
6909 case CR_IIM:
6910 case CR_IIP:
6911 case CR_IPSR:
6912 case CR_ISR:
6913 case CR_IFA:
6914 case CR_IHA:
6915 case CR_IIPA:
6916 specs[count++] = tmpl;
6917 break;
6918 }
6919 }
6920 }
6921 break;
6922 case PSR_CPL:
6923 if (rsrc_write)
6924 {
6925 specs[count++] = tmpl;
6926 }
6927 else
6928 {
6929 /* Only some AR accesses use cpl */
6930 if (idesc->operands[0] == IA64_OPND_AR3
6931 || idesc->operands[1] == IA64_OPND_AR3)
6932 {
6933 int index =
6934 ((idesc->operands[0] == IA64_OPND_AR3)
6935 ? 0 : 1);
6936 int regno =
6937 CURR_SLOT.opnd[index].X_add_number - REG_AR;
6938
6939 if (regno == AR_ITC
6940 || (index == 0
6941 && (regno == AR_ITC
6942 || regno == AR_RSC
6943 || (regno >= AR_K0
6944 && regno <= AR_K7))))
6945 {
6946 specs[count++] = tmpl;
6947 }
6948 }
6949 else
6950 {
6951 specs[count++] = tmpl;
6952 }
6953 break;
6954 }
6955 }
6956 }
6957 }
6958 else if (note == 7)
6959 {
6960 valueT mask = 0;
6961 if (idesc->operands[0] == IA64_OPND_IMMU24)
6962 {
6963 mask = CURR_SLOT.opnd[0].X_add_number;
6964 }
6965 else
6966 {
6967 UNHANDLED;
6968 }
6969 if (mask & ((valueT)1<<dep->regindex))
6970 {
6971 specs[count++] = tmpl;
6972 }
6973 }
6974 else if (note == 8)
6975 {
6976 int min = dep->regindex == PSR_DFL ? 2 : 32;
6977 int max = dep->regindex == PSR_DFL ? 31 : 127;
6978 /* dfh is read on FR32-127; dfl is read on FR2-31 */
6979 for (i=0;i < NELEMS(idesc->operands);i++)
6980 {
6981 if (idesc->operands[i] == IA64_OPND_F1
6982 || idesc->operands[i] == IA64_OPND_F2
6983 || idesc->operands[i] == IA64_OPND_F3
6984 || idesc->operands[i] == IA64_OPND_F4)
6985 {
6986 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
6987 if (reg >= min && reg <= max)
6988 {
6989 specs[count++] = tmpl;
6990 }
6991 }
6992 }
6993 }
6994 else if (note == 9)
6995 {
6996 int min = dep->regindex == PSR_MFL ? 2 : 32;
6997 int max = dep->regindex == PSR_MFL ? 31 : 127;
6998 /* mfh is read on writes to FR32-127; mfl is read on writes to
6999 FR2-31 */
7000 for (i=0;i < idesc->num_outputs;i++)
7001 {
7002 if (idesc->operands[i] == IA64_OPND_F1)
7003 {
7004 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7005 if (reg >= min && reg <= max)
7006 {
7007 specs[count++] = tmpl;
7008 }
7009 }
7010 }
7011 }
7012 else if (note == 10)
7013 {
7014 for (i=0;i < NELEMS(idesc->operands);i++)
7015 {
7016 if (idesc->operands[i] == IA64_OPND_R1
7017 || idesc->operands[i] == IA64_OPND_R2
7018 || idesc->operands[i] == IA64_OPND_R3)
7019 {
7020 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7021 if (regno >= 16 && regno <= 31)
7022 {
7023 specs[count++] = tmpl;
7024 }
7025 }
7026 }
7027 }
7028 else
7029 {
7030 UNHANDLED;
7031 }
7032 break;
7033
7034 case IA64_RS_AR_FPSR:
7035 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7036 {
7037 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7038 if (regno == AR_FPSR)
7039 {
7040 specs[count++] = tmpl;
7041 }
7042 }
7043 else
7044 {
7045 specs[count++] = tmpl;
7046 }
7047 break;
7048
7049 case IA64_RS_ARX:
7050 /* Handle all AR[REG] resources */
7051 if (note == 0 || note == 1)
7052 {
7053 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7054 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7055 && regno == dep->regindex)
7056 {
7057 specs[count++] = tmpl;
7058 }
7059 /* other AR[REG] resources may be affected by AR accesses */
7060 else if (idesc->operands[0] == IA64_OPND_AR3)
7061 {
7062 /* AR[] writes */
7063 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7064 switch (dep->regindex)
7065 {
7066 default:
7067 break;
7068 case AR_BSP:
7069 case AR_RNAT:
7070 if (regno == AR_BSPSTORE)
7071 {
7072 specs[count++] = tmpl;
7073 }
7074 case AR_RSC:
7075 if (!rsrc_write &&
7076 (regno == AR_BSPSTORE
7077 || regno == AR_RNAT))
7078 {
7079 specs[count++] = tmpl;
7080 }
7081 break;
7082 }
7083 }
7084 else if (idesc->operands[1] == IA64_OPND_AR3)
7085 {
7086 /* AR[] reads */
7087 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7088 switch (dep->regindex)
7089 {
7090 default:
7091 break;
7092 case AR_RSC:
7093 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7094 {
7095 specs[count++] = tmpl;
7096 }
7097 break;
7098 }
7099 }
7100 else
7101 {
7102 specs[count++] = tmpl;
7103 }
7104 }
7105 else
7106 {
7107 UNHANDLED;
7108 }
7109 break;
7110
7111 case IA64_RS_CRX:
7112 /* Handle all CR[REG] resources */
7113 if (note == 0 || note == 1)
7114 {
7115 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7116 {
7117 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7118 if (regno == dep->regindex)
7119 {
7120 specs[count++] = tmpl;
7121 }
7122 else if (!rsrc_write)
7123 {
7124 /* Reads from CR[IVR] affect other resources. */
7125 if (regno == CR_IVR)
7126 {
7127 if ((dep->regindex >= CR_IRR0
7128 && dep->regindex <= CR_IRR3)
7129 || dep->regindex == CR_TPR)
7130 {
7131 specs[count++] = tmpl;
7132 }
7133 }
7134 }
7135 }
7136 else
7137 {
7138 specs[count++] = tmpl;
7139 }
7140 }
7141 else
7142 {
7143 UNHANDLED;
7144 }
7145 break;
7146
7147 case IA64_RS_INSERVICE:
7148 /* look for write of EOI (67) or read of IVR (65) */
7149 if ((idesc->operands[0] == IA64_OPND_CR3
7150 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7151 || (idesc->operands[1] == IA64_OPND_CR3
7152 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7153 {
7154 specs[count++] = tmpl;
7155 }
7156 break;
7157
7158 case IA64_RS_GR0:
7159 if (note == 1)
7160 {
7161 specs[count++] = tmpl;
7162 }
7163 else
7164 {
7165 UNHANDLED;
7166 }
7167 break;
7168
7169 case IA64_RS_CFM:
7170 if (note != 2)
7171 {
7172 specs[count++] = tmpl;
7173 }
7174 else
7175 {
7176 /* Check if any of the registers accessed are in the rotating region.
7177 mov to/from pr accesses CFM only when qp_regno is in the rotating
7178 region */
7179 for (i=0;i < NELEMS(idesc->operands);i++)
7180 {
7181 if (idesc->operands[i] == IA64_OPND_R1
7182 || idesc->operands[i] == IA64_OPND_R2
7183 || idesc->operands[i] == IA64_OPND_R3)
7184 {
7185 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7186 /* Assumes that md.rot.num_regs is always valid */
7187 if (md.rot.num_regs > 0
7188 && num > 31
7189 && num < 31 + md.rot.num_regs)
7190 {
7191 specs[count] = tmpl;
7192 specs[count++].specific = 0;
7193 }
7194 }
7195 else if (idesc->operands[i] == IA64_OPND_F1
7196 || idesc->operands[i] == IA64_OPND_F2
7197 || idesc->operands[i] == IA64_OPND_F3
7198 || idesc->operands[i] == IA64_OPND_F4)
7199 {
7200 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7201 if (num > 31)
7202 {
7203 specs[count] = tmpl;
7204 specs[count++].specific = 0;
7205 }
7206 }
7207 else if (idesc->operands[i] == IA64_OPND_P1
7208 || idesc->operands[i] == IA64_OPND_P2)
7209 {
7210 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7211 if (num > 15)
7212 {
7213 specs[count] = tmpl;
7214 specs[count++].specific = 0;
7215 }
7216 }
7217 }
7218 if (CURR_SLOT.qp_regno > 15)
7219 {
7220 specs[count] = tmpl;
7221 specs[count++].specific = 0;
7222 }
7223 }
7224 break;
7225
7226 case IA64_RS_PR63:
7227 if (note == 0)
7228 {
7229 specs[count++] = tmpl;
7230 }
7231 else if (note == 11)
7232 {
7233 if ((idesc->operands[0] == IA64_OPND_P1
7234 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7235 || (idesc->operands[1] == IA64_OPND_P2
7236 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7237 {
7238 specs[count++] = tmpl;
7239 }
7240 }
7241 else if (note == 12)
7242 {
7243 if (CURR_SLOT.qp_regno == 63)
7244 {
7245 specs[count++] = tmpl;
7246 }
7247 }
7248 else if (note == 7)
7249 {
7250 valueT mask = 0;
7251 if (idesc->operands[2] == IA64_OPND_IMM17)
7252 mask = CURR_SLOT.opnd[2].X_add_number;
7253 if (mask & ((valueT)1<<63))
7254 {
7255 specs[count++] = tmpl;
7256 }
7257 }
7258 else if (note == 1)
7259 {
7260 if (rsrc_write)
7261 {
7262 for (i=0;i < idesc->num_outputs;i++)
7263 if ((idesc->operands[i] == IA64_OPND_P1
7264 || idesc->operands[i] == IA64_OPND_P2)
7265 && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
7266 {
7267 specs[count++] = tmpl;
7268 }
7269 }
7270 else
7271 {
7272 if (CURR_SLOT.qp_regno == 63)
7273 {
7274 specs[count++] = tmpl;
7275 }
7276 }
7277 }
7278 else
7279 {
7280 UNHANDLED;
7281 }
7282 break;
7283
7284 case IA64_RS_RSE:
7285 /* FIXME we can identify some individual RSE written resources, but RSE
7286 read resources have not yet been completely identified, so for now
7287 treat RSE as a single resource */
7288 if (strncmp (idesc->name, "mov", 3) == 0)
7289 {
7290 if (rsrc_write)
7291 {
7292 if (idesc->operands[0] == IA64_OPND_AR3
7293 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7294 {
7295 specs[count] = tmpl;
7296 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7297 }
7298 }
7299 else
7300 {
7301 if (idesc->operands[0] == IA64_OPND_AR3)
7302 {
7303 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7304 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7305 {
7306 specs[count++] = tmpl;
7307 }
7308 }
7309 else if (idesc->operands[1] == IA64_OPND_AR3)
7310 {
7311 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7312 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7313 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7314 {
7315 specs[count++] = tmpl;
7316 }
7317 }
7318 }
7319 }
7320 else
7321 {
7322 specs[count++] = tmpl;
7323 }
7324 break;
7325
7326 case IA64_RS_ANY:
7327 /* FIXME -- do any of these need to be non-specific? */
7328 specs[count++] = tmpl;
7329 break;
7330
7331 default:
7332 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7333 break;
7334 }
7335
7336 return count;
7337}
7338
7339/* Clear branch flags on marked resources. This breaks the link between the
7340 QP of the marking instruction and a subsequent branch on the same QP.
7341*/
7342static void
7343clear_qp_branch_flag (mask)
7344 valueT mask;
7345{
7346 int i;
7347 for (i = 0;i < regdepslen;i++)
7348 {
7349 valueT bit = ((valueT)1 << regdeps[i].qp_regno);
7350 if ((bit & mask) != 0)
7351 {
7352 regdeps[i].link_to_qp_branch = 0;
7353 }
7354 }
7355}
7356
7357/* Remove any mutexes which contain any of the PRs indicated in the mask.
7358
7359 Any changes to a PR clears the mutex relations which include that PR.
7360*/
7361static void
7362clear_qp_mutex (mask)
7363 valueT mask;
7364{
7365 int i;
7366
7367 i = 0;
7368 while (i < qp_mutexeslen)
7369 {
7370 if ((qp_mutexes[i].prmask & mask) != 0)
7371 {
7372 if (md.debug_dv)
7373 {
7374 fprintf (stderr, " Clearing mutex relation");
7375 print_prmask (qp_mutexes[i].prmask);
7376 fprintf (stderr, "\n");
7377 }
7378 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7379 }
7380 else
7381 ++i;
7382 }
7383}
7384
7385/* Clear implies relations which contain PRs in the given masks.
7386 P1_MASK indicates the source of the implies relation, while P2_MASK
7387 indicates the implied PR.
7388*/
7389static void
7390clear_qp_implies (p1_mask, p2_mask)
7391 valueT p1_mask;
7392 valueT p2_mask;
7393{
7394 int i;
7395
7396 i = 0;
7397 while (i < qp_implieslen)
7398 {
7399 if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0
7400 || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0)
7401 {
7402 if (md.debug_dv)
7403 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7404 qp_implies[i].p1, qp_implies[i].p2);
7405 qp_implies[i] = qp_implies[--qp_implieslen];
7406 }
7407 else
7408 ++i;
7409 }
7410}
7411
7412/* add the PRs specified to the list of implied relations */
7413static void
7414add_qp_imply (p1, p2)
7415 int p1, p2;
7416{
7417 valueT mask;
7418 valueT bit;
7419 int i;
7420
7421 /* p0 is not meaningful here */
7422 if (p1 == 0 || p2 == 0)
7423 abort ();
7424
7425 if (p1 == p2)
7426 return;
7427
7428 /* if it exists already, ignore it */
7429 for (i=0;i < qp_implieslen;i++)
7430 {
7431 if (qp_implies[i].p1 == p1
7432 && qp_implies[i].p2 == p2
7433 && qp_implies[i].path == md.path
7434 && !qp_implies[i].p2_branched)
7435 return;
7436 }
7437
7438 if (qp_implieslen == qp_impliestotlen)
7439 {
7440 qp_impliestotlen += 20;
7441 qp_implies = (struct qp_imply *)
7442 xrealloc ((void *)qp_implies,
7443 qp_impliestotlen * sizeof (struct qp_imply));
7444 }
7445 if (md.debug_dv)
7446 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7447 qp_implies[qp_implieslen].p1 = p1;
7448 qp_implies[qp_implieslen].p2 = p2;
7449 qp_implies[qp_implieslen].path = md.path;
7450 qp_implies[qp_implieslen++].p2_branched = 0;
7451
7452 /* Add in the implied transitive relations; for everything that p2 implies,
7453 make p1 imply that, too; for everything that implies p1, make it imply p2
7454 as well. */
7455 for (i=0;i < qp_implieslen;i++)
7456 {
7457 if (qp_implies[i].p1 == p2)
7458 add_qp_imply (p1, qp_implies[i].p2);
7459 if (qp_implies[i].p2 == p1)
7460 add_qp_imply (qp_implies[i].p1, p2);
7461 }
7462 /* Add in mutex relations implied by this implies relation; for each mutex
7463 relation containing p2, duplicate it and replace p2 with p1. */
7464 bit = (valueT)1 << p1;
7465 mask = (valueT)1 << p2;
7466 for (i=0;i < qp_mutexeslen;i++)
7467 {
7468 if (qp_mutexes[i].prmask & mask)
7469 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
7470 }
7471}
7472
7473
7474/* Add the PRs specified in the mask to the mutex list; this means that only
7475 one of the PRs can be true at any time. PR0 should never be included in
7476 the mask. */
7477static void
7478add_qp_mutex (mask)
7479 valueT mask;
7480{
7481 if (mask & 0x1)
7482 abort ();
7483
7484 if (qp_mutexeslen == qp_mutexestotlen)
7485 {
7486 qp_mutexestotlen += 20;
7487 qp_mutexes = (struct qpmutex *)
7488 xrealloc ((void *)qp_mutexes,
7489 qp_mutexestotlen * sizeof (struct qpmutex));
7490 }
7491 if (md.debug_dv)
7492 {
7493 fprintf (stderr, " Registering mutex on");
7494 print_prmask (mask);
7495 fprintf (stderr, "\n");
7496 }
7497 qp_mutexes[qp_mutexeslen].path = md.path;
7498 qp_mutexes[qp_mutexeslen++].prmask = mask;
7499}
7500
7501static void
7502clear_register_values ()
7503{
7504 int i;
7505 if (md.debug_dv)
7506 fprintf (stderr, " Clearing register values\n");
7507 for (i=1;i < NELEMS(gr_values);i++)
7508 gr_values[i].known = 0;
7509}
7510
7511/* Keep track of register values/changes which affect DV tracking.
7512
7513 optimization note: should add a flag to classes of insns where otherwise we
7514 have to examine a group of strings to identify them.
7515
7516 */
7517static void
7518note_register_values (idesc)
7519 struct ia64_opcode *idesc;
7520{
7521 valueT qp_changemask = 0;
7522 int i;
7523
7524 /* invalidate values for registers being written to */
7525 for (i=0;i < idesc->num_outputs;i++)
7526 {
7527 if (idesc->operands[i] == IA64_OPND_R1
7528 || idesc->operands[i] == IA64_OPND_R2
7529 || idesc->operands[i] == IA64_OPND_R3)
7530 {
7531 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7532 if (regno > 0 && regno < NELEMS(gr_values))
7533 gr_values[regno].known = 0;
7534 }
7535 else if (idesc->operands[i] == IA64_OPND_P1
7536 || idesc->operands[i] == IA64_OPND_P2)
7537 {
7538 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7539 qp_changemask |= (valueT)1 << regno;
7540 }
7541 else if (idesc->operands[i] == IA64_OPND_PR)
7542 {
7543 if (idesc->operands[2] & (valueT)0x10000)
7544 qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2];
7545 else
7546 qp_changemask = idesc->operands[2];
7547 break;
7548 }
7549 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
7550 {
7551 if (idesc->operands[1] & ((valueT)1 << 43))
7552 qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1];
7553 else
7554 qp_changemask = idesc->operands[1];
7555 qp_changemask &= ~(valueT)0xFFFF;
7556 break;
7557 }
7558 }
7559
7560 /* Always clear qp branch flags on any PR change */
7561 /* FIXME there may be exceptions for certain compares */
7562 clear_qp_branch_flag (qp_changemask);
7563
7564 /* invalidate rotating registers on insns which affect RRBs in CFM */
7565 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
7566 {
7567 qp_changemask |= ~(valueT)0xFFFF;
7568 if (strcmp (idesc->name, "clrrrb.pr") != 0)
7569 {
7570 for (i=32;i < 32+md.rot.num_regs;i++)
7571 gr_values[i].known = 0;
7572 }
7573 clear_qp_mutex (qp_changemask);
7574 clear_qp_implies (qp_changemask, qp_changemask);
7575 }
7576 /* after a call, all register values are undefined, except those marked
7577 as "safe" */
7578 else if (strncmp (idesc->name, "br.call", 6) == 0
7579 || strncmp (idesc->name, "brl.call", 7) == 0)
7580 {
7581 // FIXME keep GR values which are marked as "safe_across_calls"
7582 clear_register_values ();
7583 clear_qp_mutex (~qp_safe_across_calls);
7584 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
7585 clear_qp_branch_flag (~qp_safe_across_calls);
7586 }
7587 /* Look for mutex and implies relations */
7588 else if ((idesc->operands[0] == IA64_OPND_P1
7589 || idesc->operands[0] == IA64_OPND_P2)
7590 && (idesc->operands[1] == IA64_OPND_P1
7591 || idesc->operands[1] == IA64_OPND_P2))
7592 {
7593 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7594 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7595 valueT p1mask = (valueT)1 << p1;
7596 valueT p2mask = (valueT)1 << p2;
7597
7598 /* if one of the PRs is PR0, we can't really do anything */
7599 if (p1 == 0 || p2 == 0)
7600 {
7601 if (md.debug_dv)
7602 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
7603 }
7604 /* In general, clear mutexes and implies which include P1 or P2,
7605 with the following exceptions */
7606 else if (strstr (idesc->name, ".or.andcm") != NULL)
7607 {
7608 add_qp_mutex (p1mask | p2mask);
7609 clear_qp_implies (p2mask, p1mask);
7610 }
7611 else if (strstr (idesc->name, ".and.orcm") != NULL)
7612 {
7613 add_qp_mutex (p1mask | p2mask);
7614 clear_qp_implies (p1mask, p2mask);
7615 }
7616 else if (strstr (idesc->name, ".and") != NULL)
7617 {
7618 clear_qp_implies (0, p1mask | p2mask);
7619 }
7620 else if (strstr (idesc->name, ".or") != NULL)
7621 {
7622 clear_qp_mutex (p1mask | p2mask);
7623 clear_qp_implies (p1mask | p2mask, 0);
7624 }
7625 else
7626 {
7627 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
7628 if (strstr (idesc->name, ".unc") != NULL)
7629 {
7630 add_qp_mutex (p1mask | p2mask);
7631 if (CURR_SLOT.qp_regno != 0)
7632 {
7633 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
7634 CURR_SLOT.qp_regno);
7635 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
7636 CURR_SLOT.qp_regno);
7637 }
7638 }
7639 else if (CURR_SLOT.qp_regno == 0)
7640 {
7641 add_qp_mutex (p1mask | p2mask);
7642 }
7643 else
7644 {
7645 clear_qp_mutex (p1mask | p2mask);
7646 }
7647 }
7648 }
7649 /* Look for mov imm insns into GRs */
7650 else if (idesc->operands[0] == IA64_OPND_R1
7651 && (idesc->operands[1] == IA64_OPND_IMM22
7652 || idesc->operands[1] == IA64_OPND_IMMU64)
7653 && (strcmp(idesc->name, "mov") == 0
7654 || strcmp(idesc->name, "movl") == 0))
7655 {
7656 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7657 if (regno > 0 && regno < NELEMS(gr_values))
7658 {
7659 gr_values[regno].known = 1;
7660 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
7661 gr_values[regno].path = md.path;
7662 if (md.debug_dv)
7663 fprintf (stderr, " Know gr%d = 0x%llx\n",
7664 regno, gr_values[regno].value);
7665 }
7666 }
7667 else
7668 {
7669 clear_qp_mutex (qp_changemask);
7670 clear_qp_implies (qp_changemask, qp_changemask);
7671 }
7672}
7673
7674/* Return whether the given predicate registers are currently mutex */
7675static int
7676qp_mutex (p1, p2, path)
7677 int p1;
7678 int p2;
7679 int path;
7680{
7681 int i;
7682 valueT mask;
7683
7684 if (p1 != p2)
7685 {
7686 mask = ((valueT)1<<p1) | (valueT)1<<p2;
7687 for (i=0;i < qp_mutexeslen;i++)
7688 {
7689 if (qp_mutexes[i].path >= path
7690 && (qp_mutexes[i].prmask & mask) == mask)
7691 return 1;
7692 }
7693 }
7694 return 0;
7695}
7696
7697/* Return whether the given resource is in the given insn's list of chks
7698 Return 1 if the conflict is absolutely determined, 2 if it's a potential
7699 conflict.
7700 */
7701static int
7702resources_match (rs, idesc, note, qp_regno, path)
7703 struct rsrc *rs;
7704 struct ia64_opcode *idesc;
7705 int note;
7706 int qp_regno;
7707 int path;
7708{
7709 struct rsrc specs[MAX_SPECS];
7710 int count;
7711
7712 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7713 we don't need to check. One exception is note 11, which indicates that
7714 target predicates are written regardless of PR[qp]. */
7715 if (qp_mutex (rs->qp_regno, qp_regno, path)
7716 && note != 11)
7717 return 0;
7718
7719 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
7720 while (count-- > 0)
7721 {
7722 /* UNAT checking is a bit more specific than other resources */
7723 if (rs->dependency->specifier == IA64_RS_AR_UNAT
7724 && specs[count].mem_offset.hint
7725 && rs->mem_offset.hint)
7726 {
7727 if (rs->mem_offset.base == specs[count].mem_offset.base)
7728 {
7729 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
7730 ((specs[count].mem_offset.offset >> 3) & 0x3F))
7731 return 1;
7732 else
7733 continue;
7734 }
7735 }
7736
7737 /* If either resource is not specific, conservatively assume a conflict
7738 */
7739 if (!specs[count].specific || !rs->specific)
7740 return 2;
7741 else if (specs[count].index == rs->index)
7742 return 1;
7743 }
7744#if 0
7745 if (md.debug_dv)
7746 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
7747#endif
7748
7749 return 0;
7750}
7751
7752/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7753 insert a stop to create the break. Update all resource dependencies
7754 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7755 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7756 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
7757 instruction.
7758*/
7759
7760static void
7761insn_group_break (insert_stop, qp_regno, save_current)
7762 int insert_stop;
7763 int qp_regno;
7764 int save_current;
7765{
7766 int i;
7767
7768 if (insert_stop && md.num_slots_in_use > 0)
7769 PREV_SLOT.end_of_insn_group = 1;
7770
7771 if (md.debug_dv)
7772 {
7773 fprintf (stderr, " Insn group break%s",
7774 (insert_stop ? " (w/stop)" : ""));
7775 if (qp_regno != 0)
7776 fprintf (stderr, " effective for QP=%d", qp_regno);
7777 fprintf (stderr, "\n");
7778 }
7779
7780 i = 0;
7781 while (i < regdepslen)
7782 {
7783 const struct ia64_dependency *dep = regdeps[i].dependency;
7784
7785 if (qp_regno != 0
7786 && regdeps[i].qp_regno != qp_regno)
7787 {
7788 ++i;
7789 continue;
7790 }
7791
7792 if (save_current
7793 && CURR_SLOT.src_file == regdeps[i].file
7794 && CURR_SLOT.src_line == regdeps[i].line)
7795 {
7796 ++i;
7797 continue;
7798 }
7799
7800 /* clear dependencies which are automatically cleared by a stop, or
7801 those that have reached the appropriate state of insn serialization */
7802 if (dep->semantics == IA64_DVS_IMPLIED
7803 || dep->semantics == IA64_DVS_IMPLIEDF
7804 || regdeps[i].insn_srlz == STATE_SRLZ)
7805 {
7806 print_dependency ("Removing", i);
7807 regdeps[i] = regdeps[--regdepslen];
7808 }
7809 else
7810 {
7811 if (dep->semantics == IA64_DVS_DATA
7812 || dep->semantics == IA64_DVS_INSTR
7813 || dep->semantics == IA64_DVS_SPECIFIC)
7814 {
7815 if (regdeps[i].insn_srlz == STATE_NONE)
7816 regdeps[i].insn_srlz = STATE_STOP;
7817 if (regdeps[i].data_srlz == STATE_NONE)
7818 regdeps[i].data_srlz = STATE_STOP;
7819 }
7820 ++i;
7821 }
7822 }
7823}
7824
7825/* Add the given resource usage spec to the list of active dependencies */
7826static void
7827mark_resource (idesc, dep, spec, depind, path)
7828 struct ia64_opcode *idesc;
7829 const struct ia64_dependency *dep;
7830 struct rsrc *spec;
7831 int depind;
7832 int path;
7833{
7834 if (regdepslen == regdepstotlen)
7835 {
7836 regdepstotlen += 20;
7837 regdeps = (struct rsrc *)
7838 xrealloc ((void *)regdeps,
7839 regdepstotlen * sizeof(struct rsrc));
7840 }
7841
7842 regdeps[regdepslen] = *spec;
7843 regdeps[regdepslen].depind = depind;
7844 regdeps[regdepslen].path = path;
7845 regdeps[regdepslen].file = CURR_SLOT.src_file;
7846 regdeps[regdepslen].line = CURR_SLOT.src_line;
7847
7848 print_dependency ("Adding", regdepslen);
7849
7850 ++regdepslen;
7851}
7852
7853static void
7854print_dependency (action, depind)
7855 const char *action;
7856 int depind;
7857{
7858 if (md.debug_dv)
7859 {
7860 fprintf (stderr, " %s %s '%s'",
7861 action, dv_mode[(regdeps[depind].dependency)->mode],
7862 (regdeps[depind].dependency)->name);
7863 if (regdeps[depind].specific && regdeps[depind].index != 0)
7864 fprintf (stderr, " (%d)", regdeps[depind].index);
7865 if (regdeps[depind].mem_offset.hint)
7866 fprintf (stderr, " 0x%llx+0x%llx",
7867 regdeps[depind].mem_offset.base,
7868 regdeps[depind].mem_offset.offset);
7869 fprintf (stderr, "\n");
7870 }
7871}
7872
7873static void
7874instruction_serialization ()
7875{
7876 int i;
7877 if (md.debug_dv)
7878 fprintf (stderr, " Instruction serialization\n");
7879 for (i=0;i < regdepslen;i++)
7880 if (regdeps[i].insn_srlz == STATE_STOP)
7881 regdeps[i].insn_srlz = STATE_SRLZ;
7882}
7883
7884static void
7885data_serialization ()
7886{
7887 int i = 0;
7888 if (md.debug_dv)
7889 fprintf (stderr, " Data serialization\n");
7890 while (i < regdepslen)
7891 {
7892 if (regdeps[i].data_srlz == STATE_STOP
7893 /* Note: as of 991210, all "other" dependencies are cleared by a
7894 data serialization. This might change with new tables */
7895 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
7896 {
7897 print_dependency ("Removing", i);
7898 regdeps[i] = regdeps[--regdepslen];
7899 }
7900 else
7901 ++i;
7902 }
7903}
7904
7905/* Insert stops and serializations as needed to avoid DVs */
7906static void
7907remove_marked_resource (rs)
7908 struct rsrc *rs;
7909{
7910 switch (rs->dependency->semantics)
7911 {
7912 case IA64_DVS_SPECIFIC:
7913 if (md.debug_dv)
7914 fprintf (stderr, "Implementation-specific, assume worst case...\n");
7915 /* ...fall through... */
7916 case IA64_DVS_INSTR:
7917 if (md.debug_dv)
7918 fprintf (stderr, "Inserting instr serialization\n");
7919 if (rs->insn_srlz < STATE_STOP)
7920 insn_group_break (1, 0, 0);
7921 if (rs->insn_srlz < STATE_SRLZ)
7922 {
7923 int oldqp = CURR_SLOT.qp_regno;
7924 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
7925 /* Manually jam a srlz.i insn into the stream */
7926 CURR_SLOT.qp_regno = 0;
7927 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
7928 instruction_serialization ();
7929 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
7930 if (++md.num_slots_in_use >= NUM_SLOTS)
7931 emit_one_bundle ();
7932 CURR_SLOT.qp_regno = oldqp;
7933 CURR_SLOT.idesc = oldidesc;
7934 }
7935 insn_group_break (1, 0, 0);
7936 break;
7937 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
7938 "other" types of DV are eliminated
7939 by a data serialization */
7940 case IA64_DVS_DATA:
7941 if (md.debug_dv)
7942 fprintf (stderr, "Inserting data serialization\n");
7943 if (rs->data_srlz < STATE_STOP)
7944 insn_group_break (1, 0, 0);
7945 {
7946 int oldqp = CURR_SLOT.qp_regno;
7947 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
7948 /* Manually jam a srlz.d insn into the stream */
7949 CURR_SLOT.qp_regno = 0;
7950 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
7951 data_serialization ();
7952 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
7953 if (++md.num_slots_in_use >= NUM_SLOTS)
7954 emit_one_bundle ();
7955 CURR_SLOT.qp_regno = oldqp;
7956 CURR_SLOT.idesc = oldidesc;
7957 }
7958 break;
7959 case IA64_DVS_IMPLIED:
7960 case IA64_DVS_IMPLIEDF:
7961 if (md.debug_dv)
7962 fprintf (stderr, "Inserting stop\n");
7963 insn_group_break (1, 0, 0);
7964 break;
7965 default:
7966 break;
7967 }
7968}
7969
7970/* Check the resources used by the given opcode against the current dependency
7971 list.
7972
7973 The check is run once for each execution path encountered. In this case,
7974 a unique execution path is the sequence of instructions following a code
7975 entry point, e.g. the following has three execution paths, one starting
7976 at L0, one at L1, and one at L2.
7977
7978 L0: nop
7979 L1: add
7980 L2: add
7981 br.ret
7982*/
7983static void
7984check_dependencies (idesc)
7985 struct ia64_opcode *idesc;
7986{
7987 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
7988 int path;
7989 int i;
7990
7991 /* Note that the number of marked resources may change within the
7992 loop if in auto mode. */
7993 i = 0;
7994 while (i < regdepslen)
7995 {
7996 struct rsrc *rs = &regdeps[i];
7997 const struct ia64_dependency *dep = rs->dependency;
7998 int chkind;
7999 int note;
8000 int start_over = 0;
8001
8002 if (dep->semantics == IA64_DVS_NONE
8003 || (chkind = depends_on (rs->depind, idesc)) == -1)
8004 {
8005 ++i; continue;
8006 }
8007
8008 note = NOTE(opdeps->chks[chkind]);
8009
8010 /* Check this resource against each execution path seen thus far */
8011 for (path=0;path <= md.path;path++)
8012 {
8013 int matchtype;
8014
8015 /* If the dependency wasn't on the path being checked, ignore it */
8016 if (rs->path < path)
8017 continue;
8018
8019 /* If the QP for this insn implies a QP which has branched, don't
8020 bother checking. Ed. NOTE: I don't think this check is terribly
8021 useful; what's the point of generating code which will only be
8022 reached if its QP is zero?
8023 This code was specifically inserted to handle the following code,
8024 based on notes from Intel's DV checking code, where p1 implies p2.
8025
8026 mov r4 = 2
8027 (p2) br.cond L
8028 (p1) mov r4 = 7
8029
8030 */
8031 if (CURR_SLOT.qp_regno != 0)
8032 {
8033 int skip = 0;
8034 int implies;
8035 for (implies=0;implies < qp_implieslen;implies++)
8036 {
8037 if (qp_implies[implies].path >= path
8038 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8039 && qp_implies[implies].p2_branched)
8040 {
8041 skip = 1;
8042 break;
8043 }
8044 }
8045 if (skip)
8046 continue;
8047 }
8048
8049 if ((matchtype = resources_match (rs, idesc, note,
8050 CURR_SLOT.qp_regno, path)) != 0)
8051 {
8052 char msg[1024];
8053 char pathmsg[256] = "";
8054 char indexmsg[256] = "";
8055 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8056
8057 if (path != 0)
8058 sprintf (pathmsg, " when entry is at label '%s'",
8059 md.entry_labels[path-1]);
8060 if (rs->specific && rs->index != 0)
8061 sprintf (indexmsg, ", specific resource number is %d",
8062 rs->index);
8063 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8064 idesc->name,
8065 (certain ? "violates" : "may violate"),
8066 dv_mode[dep->mode], dep->name,
8067 dv_sem[dep->semantics],
8068 pathmsg, indexmsg);
8069
8070 if (md.explicit_mode)
8071 {
8072 as_warn ("%s", msg);
8073 if (path < md.path)
8074 as_warn (_("Only the first path encountering the conflict "
8075 "is reported"));
8076 as_warn_where (rs->file, rs->line,
8077 _("This is the location of the "
8078 "conflicting usage"));
8079 /* Don't bother checking other paths, to avoid duplicating
8080 the same warning */
8081 break;
8082 }
8083 else
8084 {
8085 if (md.debug_dv)
8086 fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8087
8088 remove_marked_resource (rs);
8089
8090 /* since the set of dependencies has changed, start over */
8091 /* FIXME -- since we're removing dvs as we go, we
8092 probably don't really need to start over... */
8093 start_over = 1;
8094 break;
8095 }
8096 }
8097 }
8098 if (start_over)
8099 i = 0;
8100 else
8101 ++i;
8102 }
8103}
8104
8105/* register new dependencies based on the given opcode */
8106static void
8107mark_resources (idesc)
8108 struct ia64_opcode *idesc;
8109{
8110 int i;
8111 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8112 int add_only_qp_reads = 0;
8113
8114 /* A conditional branch only uses its resources if it is taken; if it is
8115 taken, we stop following that path. The other branch types effectively
8116 *always* write their resources. If it's not taken, register only QP
8117 reads. */
8118 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8119 {
8120 add_only_qp_reads = 1;
8121 }
8122
8123 if (md.debug_dv)
8124 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8125
8126 for (i=0;i < opdeps->nregs;i++)
8127 {
8128 const struct ia64_dependency *dep;
8129 struct rsrc specs[MAX_SPECS];
8130 int note;
8131 int path;
8132 int count;
8133
8134 dep = ia64_find_dependency (opdeps->regs[i]);
8135 note = NOTE(opdeps->regs[i]);
8136
8137 if (add_only_qp_reads
8138 && !(dep->mode == IA64_DV_WAR
8139 && (dep->specifier == IA64_RS_PR
8140 || dep->specifier == IA64_RS_PR63)))
8141 continue;
8142
8143 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8144
8145#if 0
8146 if (md.debug_dv && !count)
8147 fprintf (stderr, " No %s %s usage found (path %d)\n",
8148 dv_mode[dep->mode], dep->name, md.path);
8149#endif
8150
8151 while (count-- > 0)
8152 {
8153 mark_resource (idesc, dep, &specs[count],
8154 DEP(opdeps->regs[i]), md.path);
8155 }
8156
8157 /* The execution path may affect register values, which may in turn
8158 affect which indirect-access resources are accessed. */
8159 switch (dep->specifier)
8160 {
8161 default:
8162 break;
8163 case IA64_RS_CPUID:
8164 case IA64_RS_DBR:
8165 case IA64_RS_IBR:
8166 case IA64_RS_MSR:
8167 case IA64_RS_PKR:
8168 case IA64_RS_PMC:
8169 case IA64_RS_PMD:
8170 case IA64_RS_RR:
8171 for (path=0;path < md.path;path++)
8172 {
8173 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8174 while (count-- > 0)
8175 mark_resource (idesc, dep, &specs[count],
8176 DEP(opdeps->regs[i]), path);
8177 }
8178 break;
8179 }
8180 }
8181}
8182
8183/* remove dependencies when they no longer apply */
8184static void
8185update_dependencies (idesc)
8186 struct ia64_opcode *idesc;
8187{
8188 int i;
8189
8190 if (strcmp (idesc->name, "srlz.i") == 0)
8191 {
8192 instruction_serialization ();
8193 }
8194 else if (strcmp (idesc->name, "srlz.d") == 0)
8195 {
8196 data_serialization ();
8197 }
8198 else if (is_interruption_or_rfi (idesc)
8199 || is_taken_branch (idesc))
8200 {
8201 /* although technically the taken branch doesn't clear dependencies
8202 which require a srlz.[id], we don't follow the branch; the next
8203 instruction is assumed to start with a clean slate */
8204 regdepslen = 0;
8205 clear_register_values ();
8206 clear_qp_mutex (~(valueT)0);
8207 clear_qp_implies (~(valueT)0, ~(valueT)0);
8208 md.path = 0;
8209 }
8210 else if (is_conditional_branch (idesc)
8211 && CURR_SLOT.qp_regno != 0)
8212 {
8213 int is_call = strstr (idesc->name, ".call") != NULL;
8214
8215 for (i=0;i < qp_implieslen;i++)
8216 {
8217 /* if the conditional branch's predicate is implied by the predicate
8218 in an existing dependency, remove that dependency */
8219 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8220 {
8221 int depind = 0;
8222 /* note that this implied predicate takes a branch so that if
8223 a later insn generates a DV but its predicate implies this
8224 one, we can avoid the false DV warning */
8225 qp_implies[i].p2_branched = 1;
8226 while (depind < regdepslen)
8227 {
8228 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8229 {
8230 print_dependency ("Removing", depind);
8231 regdeps[depind] = regdeps[--regdepslen];
8232 }
8233 else
8234 ++depind;
8235 }
8236 }
8237 }
8238 /* Any marked resources which have this same predicate should be
8239 cleared, provided that the QP hasn't been modified between the
8240 marking instruction and the branch.
8241 */
8242 if (is_call)
8243 {
8244 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8245 }
8246 else
8247 {
8248 i = 0;
8249 while (i < regdepslen)
8250 {
8251 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8252 && regdeps[i].link_to_qp_branch
8253 && (regdeps[i].file != CURR_SLOT.src_file
8254 || regdeps[i].line != CURR_SLOT.src_line))
8255 {
8256 /* Treat like a taken branch */
8257 print_dependency ("Removing", i);
8258 regdeps[i] = regdeps[--regdepslen];
8259 }
8260 else
8261 ++i;
8262 }
8263 }
8264 }
8265}
8266
8267/* Examine the current instruction for dependency violations. */
8268static int
8269check_dv (idesc)
8270 struct ia64_opcode *idesc;
8271{
8272 if (md.debug_dv)
8273 {
8274 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
8275 idesc->name, CURR_SLOT.src_line,
8276 idesc->dependencies->nchks,
8277 idesc->dependencies->nregs);
8278 }
8279
8280 /* Look through the list of currently marked resources; if the current
8281 instruction has the dependency in its chks list which uses that resource,
8282 check against the specific resources used.
8283 */
8284 check_dependencies (idesc);
8285
8286 /*
8287 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8288 then add them to the list of marked resources.
8289 */
8290 mark_resources (idesc);
8291
8292 /* There are several types of dependency semantics, and each has its own
8293 requirements for being cleared
8294
8295 Instruction serialization (insns separated by interruption, rfi, or
8296 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8297
8298 Data serialization (instruction serialization, or writer + srlz.d +
8299 reader, where writer and srlz.d are in separate groups) clears
8300 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8301 always be the case).
8302
8303 Instruction group break (groups separated by stop, taken branch,
8304 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8305 */
8306 update_dependencies (idesc);
8307
8308 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8309 warning. Keep track of as many as possible that are useful. */
8310 note_register_values (idesc);
8311
8312 /* We don't need or want this anymore. */
8313 md.mem_offset.hint = 0;
8314
8315 return 0;
8316}
8317
8318/* Translate one line of assembly. Pseudo ops and labels do not show
8319 here. */
8320void
8321md_assemble (str)
8322 char *str;
8323{
8324 char *saved_input_line_pointer, *mnemonic;
8325 const struct pseudo_opcode *pdesc;
8326 struct ia64_opcode *idesc;
8327 unsigned char qp_regno;
8328 unsigned int flags;
8329 int ch;
8330
8331 saved_input_line_pointer = input_line_pointer;
8332 input_line_pointer = str;
8333
8334 /* extract the opcode (mnemonic): */
8335
8336 mnemonic = input_line_pointer;
8337 ch = get_symbol_end ();
8338 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8339 if (pdesc)
8340 {
8341 *input_line_pointer = ch;
8342 (*pdesc->handler) (pdesc->arg);
8343 goto done;
8344 }
8345
8346 /* find the instruction descriptor matching the arguments: */
8347
8348 idesc = ia64_find_opcode (mnemonic);
8349 *input_line_pointer = ch;
8350 if (!idesc)
8351 {
8352 as_bad ("Unknown opcode `%s'", mnemonic);
8353 goto done;
8354 }
8355
8356 idesc = parse_operands (idesc);
8357 if (!idesc)
8358 goto done;
8359
8360 /* Handle the dynamic ops we can handle now: */
8361 if (idesc->type == IA64_TYPE_DYN)
8362 {
8363 if (strcmp (idesc->name, "add") == 0)
8364 {
8365 if (CURR_SLOT.opnd[2].X_op == O_register
8366 && CURR_SLOT.opnd[2].X_add_number < 4)
8367 mnemonic = "addl";
8368 else
8369 mnemonic = "adds";
8370 idesc = ia64_find_opcode (mnemonic);
8371#if 0
8372 know (!idesc->next);
8373#endif
8374 }
8375 else if (strcmp (idesc->name, "mov") == 0)
8376 {
8377 enum ia64_opnd opnd1, opnd2;
8378 int rop;
8379
8380 opnd1 = idesc->operands[0];
8381 opnd2 = idesc->operands[1];
8382 if (opnd1 == IA64_OPND_AR3)
8383 rop = 0;
8384 else if (opnd2 == IA64_OPND_AR3)
8385 rop = 1;
8386 else
8387 abort ();
8388 if (CURR_SLOT.opnd[rop].X_op == O_register
8389 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8390 mnemonic = "mov.i";
8391 else
8392 mnemonic = "mov.m";
8393 idesc = ia64_find_opcode (mnemonic);
8394 while (idesc != NULL
8395 && (idesc->operands[0] != opnd1
8396 || idesc->operands[1] != opnd2))
8397 idesc = get_next_opcode (idesc);
8398 }
8399 }
8400
8401 qp_regno = 0;
8402 if (md.qp.X_op == O_register)
8403 qp_regno = md.qp.X_add_number - REG_P;
8404
8405 flags = idesc->flags;
8406
8407 if ((flags & IA64_OPCODE_FIRST) != 0)
8408 insn_group_break (1, 0, 0);
8409
8410 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8411 {
8412 as_bad ("`%s' cannot be predicated", idesc->name);
8413 goto done;
8414 }
8415
8416 /* build the instruction: */
8417 CURR_SLOT.qp_regno = qp_regno;
8418 CURR_SLOT.idesc = idesc;
8419 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8420 if (debug_type == DEBUG_DWARF2)
8421 dwarf2_where (&CURR_SLOT.debug_line);
8422
8423 /* Add unwind entry, if there is one. */
e0c9811a 8424 if (unwind.current_entry)
800eeca4 8425 {
e0c9811a
JW		 8426 CURR_SLOT.unwind_record = unwind.current_entry;
8427 unwind.current_entry = NULL;
800eeca4
JW		 8428 }
8429
8430 /* check for dependency violations */
8431 if (md.detect_dv)
8432 check_dv(idesc);
8433
8434 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8435 if (++md.num_slots_in_use >= NUM_SLOTS)
8436 emit_one_bundle ();
8437
8438 if ((flags & IA64_OPCODE_LAST) != 0)
8439 insn_group_break (1, 0, 0);
8440
8441 md.last_text_seg = now_seg;
8442
8443 done:
8444 input_line_pointer = saved_input_line_pointer;
8445}
8446
8447/* Called when symbol NAME cannot be found in the symbol table.
8448 Should be used for dynamic valued symbols only. */
8449symbolS*
8450md_undefined_symbol (name)
8451 char *name;
8452{
8453 return 0;
8454}
8455
8456/* Called for any expression that can not be recognized. When the
8457 function is called, `input_line_pointer' will point to the start of
8458 the expression. */
8459void
8460md_operand (e)
8461 expressionS *e;
8462{
8463 enum pseudo_type pseudo_type;
e0c9811a 8464 const char *name;
800eeca4
JW		 8465 size_t len;
8466 int ch, i;
8467
8468 switch (*input_line_pointer)
8469 {
8470 case '@':
8471 /* find what relocation pseudo-function we're dealing with: */
8472 pseudo_type = 0;
8473 ch = *++input_line_pointer;
8474 for (i = 0; i < NELEMS (pseudo_func); ++i)
8475 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8476 {
8477 len = strlen (pseudo_func[i].name);
8478 if (strncmp (pseudo_func[i].name + 1,
8479 input_line_pointer + 1, len - 1) == 0
8480 && !is_part_of_name (input_line_pointer[len]))
8481 {
8482 input_line_pointer += len;
8483 pseudo_type = pseudo_func[i].type;
8484 break;
8485 }
8486 }
8487 switch (pseudo_type)
8488 {
8489 case PSEUDO_FUNC_RELOC:
8490 SKIP_WHITESPACE ();
8491 if (*input_line_pointer != '(')
8492 {
8493 as_bad ("Expected '('");
8494 goto err;
8495 }
8496 ++input_line_pointer; /* skip '(' */
8497 expression (e);
8498 if (*input_line_pointer++ != ')')
8499 {
8500 as_bad ("Missing ')'");
8501 goto err;
8502 }
8503 if (e->X_op != O_symbol)
8504 {
8505 if (e->X_op != O_pseudo_fixup)
8506 {
8507 as_bad ("Not a symbolic expression");
8508 goto err;
8509 }
8510 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8511 && i == FUNC_LT_RELATIVE)
8512 i = FUNC_LT_FPTR_RELATIVE;
8513 else
8514 {
8515 as_bad ("Illegal combination of relocation functions");
8516 goto err;
8517 }
8518 }
8519 /* make sure gas doesn't get rid of local symbols that are used
8520 in relocs: */
8521 e->X_op = O_pseudo_fixup;
8522 e->X_op_symbol = pseudo_func[i].u.sym;
8523 break;
8524
8525 case PSEUDO_FUNC_CONST:
8526 e->X_op = O_constant;
8527 e->X_add_number = pseudo_func[i].u.ival;
8528 break;
8529
e0c9811a
JW		 8530 case PSEUDO_FUNC_REG:
8531 e->X_op = O_register;
8532 e->X_add_number = pseudo_func[i].u.ival;
8533 break;
8534
800eeca4 8535 default:
e0c9811a
JW		 8536 name = input_line_pointer - 1;
8537 get_symbol_end ();
8538 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 8539 goto err;
8540 }
8541 break;
8542
8543 case '[':
8544 ++input_line_pointer;
8545 expression (e);
8546 if (*input_line_pointer != ']')
8547 {
8548 as_bad ("Closing bracket misssing");
8549 goto err;
8550 }
8551 else
8552 {
8553 if (e->X_op != O_register)
8554 as_bad ("Register expected as index");
8555
8556 ++input_line_pointer;
8557 e->X_op = O_index;
8558 }
8559 break;
8560
8561 default:
8562 break;
8563 }
8564 return;
8565
8566 err:
8567 ignore_rest_of_line ();
8568}
8569
8570/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8571 a section symbol plus some offset. For relocs involving @fptr(),
8572 directives we don't want such adjustments since we need to have the
8573 original symbol's name in the reloc. */
8574int
8575ia64_fix_adjustable (fix)
8576 fixS *fix;
8577{
8578 /* Prevent all adjustments to global symbols */
8579 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
8580 return 0;
8581
8582 switch (fix->fx_r_type)
8583 {
8584 case BFD_RELOC_IA64_FPTR64I:
8585 case BFD_RELOC_IA64_FPTR32MSB:
8586 case BFD_RELOC_IA64_FPTR32LSB:
8587 case BFD_RELOC_IA64_FPTR64MSB:
8588 case BFD_RELOC_IA64_FPTR64LSB:
8589 case BFD_RELOC_IA64_LTOFF_FPTR22:
8590 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8591 return 0;
8592 default:
8593 break;
8594 }
8595
8596 return 1;
8597}
8598
8599int
8600ia64_force_relocation (fix)
8601 fixS *fix;
8602{
8603 switch (fix->fx_r_type)
8604 {
8605 case BFD_RELOC_IA64_FPTR64I:
8606 case BFD_RELOC_IA64_FPTR32MSB:
8607 case BFD_RELOC_IA64_FPTR32LSB:
8608 case BFD_RELOC_IA64_FPTR64MSB:
8609 case BFD_RELOC_IA64_FPTR64LSB:
8610
8611 case BFD_RELOC_IA64_LTOFF22:
8612 case BFD_RELOC_IA64_LTOFF64I:
8613 case BFD_RELOC_IA64_LTOFF_FPTR22:
8614 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8615 case BFD_RELOC_IA64_PLTOFF22:
8616 case BFD_RELOC_IA64_PLTOFF64I:
8617 case BFD_RELOC_IA64_PLTOFF64MSB:
8618 case BFD_RELOC_IA64_PLTOFF64LSB:
8619 return 1;
8620
8621 default:
8622 return 0;
8623 }
8624 return 0;
8625}
8626
8627/* Decide from what point a pc-relative relocation is relative to,
8628 relative to the pc-relative fixup. Er, relatively speaking. */
8629long
8630ia64_pcrel_from_section (fix, sec)
8631 fixS *fix;
8632 segT sec;
8633{
8634 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
8635
8636 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
8637 off &= ~0xfUL;
8638
8639 return off;
8640}
8641
8642/* This is called whenever some data item (not an instruction) needs a
8643 fixup. We pick the right reloc code depending on the byteorder
8644 currently in effect. */
8645void
8646ia64_cons_fix_new (f, where, nbytes, exp)
8647 fragS *f;
8648 int where;
8649 int nbytes;
8650 expressionS *exp;
8651{
8652 bfd_reloc_code_real_type code;
8653 fixS *fix;
8654
8655 switch (nbytes)
8656 {
8657 /* There are no reloc for 8 and 16 bit quantities, but we allow
8658 them here since they will work fine as long as the expression
8659 is fully defined at the end of the pass over the source file. */
8660 case 1: code = BFD_RELOC_8; break;
8661 case 2: code = BFD_RELOC_16; break;
8662 case 4:
8663 if (target_big_endian)
8664 code = BFD_RELOC_IA64_DIR32MSB;
8665 else
8666 code = BFD_RELOC_IA64_DIR32LSB;
8667 break;
8668
8669 case 8:
8670 if (target_big_endian)
8671 code = BFD_RELOC_IA64_DIR64MSB;
8672 else
8673 code = BFD_RELOC_IA64_DIR64LSB;
8674 break;
8675
8676 default:
8677 as_bad ("Unsupported fixup size %d", nbytes);
8678 ignore_rest_of_line ();
8679 return;
8680 }
8681 if (exp->X_op == O_pseudo_fixup)
8682 {
8683 /* ??? */
8684 exp->X_op = O_symbol;
8685 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
8686 }
8687 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
8688 /* We need to store the byte order in effect in case we're going
8689 to fix an 8 or 16 bit relocation (for which there no real
8690 relocs available). See md_apply_fix(). */
8691 fix->tc_fix_data.bigendian = target_big_endian;
8692}
8693
8694/* Return the actual relocation we wish to associate with the pseudo
8695 reloc described by SYM and R_TYPE. SYM should be one of the
8696 symbols in the pseudo_func array, or NULL. */
8697
8698static bfd_reloc_code_real_type
8699ia64_gen_real_reloc_type (sym, r_type)
8700 struct symbol *sym;
8701 bfd_reloc_code_real_type r_type;
8702{
8703 bfd_reloc_code_real_type new = 0;
8704
8705 if (sym == NULL)
8706 {
8707 return r_type;
8708 }
8709
8710 switch (S_GET_VALUE (sym))
8711 {
8712 case FUNC_FPTR_RELATIVE:
8713 switch (r_type)
8714 {
8715 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
8716 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
8717 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
8718 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
8719 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
8720 default: break;
8721 }
8722 break;
8723
8724 case FUNC_GP_RELATIVE:
8725 switch (r_type)
8726 {
8727 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
8728 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
8729 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
8730 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
8731 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
8732 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
8733 default: break;
8734 }
8735 break;
8736
8737 case FUNC_LT_RELATIVE:
8738 switch (r_type)
8739 {
8740 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
8741 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
8742 default: break;
8743 }
8744 break;
8745
c67e42c9
RH		 8746 case FUNC_PC_RELATIVE:
8747 switch (r_type)
8748 {
8749 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
8750 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
8751 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
8752 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
8753 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
8754 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
8755 default: break;
8756 }
8757 break;
8758
800eeca4
JW		 8759 case FUNC_PLT_RELATIVE:
8760 switch (r_type)
8761 {
8762 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
8763 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
8764 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
8765 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
8766 default: break;
8767 }
8768 break;
8769
8770 case FUNC_SEC_RELATIVE:
8771 switch (r_type)
8772 {
8773 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
8774 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
8775 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
8776 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
8777 default: break;
8778 }
8779 break;
8780
8781 case FUNC_SEG_RELATIVE:
8782 switch (r_type)
8783 {
8784 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
8785 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
8786 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
8787 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
8788 default: break;
8789 }
8790 break;
8791
8792 case FUNC_LTV_RELATIVE:
8793 switch (r_type)
8794 {
8795 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
8796 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
8797 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
8798 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
8799 default: break;
8800 }
8801 break;
8802
8803 case FUNC_LT_FPTR_RELATIVE:
8804 switch (r_type)
8805 {
8806 case BFD_RELOC_IA64_IMM22:
8807 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
8808 case BFD_RELOC_IA64_IMM64:
8809 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
8810 default:
8811 break;
8812 }
8813 break;
8814 default:
8815 abort ();
8816 }
8817 /* Hmmmm. Should this ever occur? */
8818 if (new)
8819 return new;
8820 else
8821 return r_type;
8822}
8823
8824/* Here is where generate the appropriate reloc for pseudo relocation
8825 functions. */
8826void
8827ia64_validate_fix (fix)
8828 fixS *fix;
8829{
8830 switch (fix->fx_r_type)
8831 {
8832 case BFD_RELOC_IA64_FPTR64I:
8833 case BFD_RELOC_IA64_FPTR32MSB:
8834 case BFD_RELOC_IA64_FPTR64LSB:
8835 case BFD_RELOC_IA64_LTOFF_FPTR22:
8836 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8837 if (fix->fx_offset != 0)
8838 as_bad_where (fix->fx_file, fix->fx_line,
8839 "No addend allowed in @fptr() relocation");
8840 break;
8841 default:
8842 break;
8843 }
8844
8845 return;
8846}
8847
8848static void
8849fix_insn (fix, odesc, value)
8850 fixS *fix;
8851 const struct ia64_operand *odesc;
8852 valueT value;
8853{
8854 bfd_vma insn[3], t0, t1, control_bits;
8855 const char *err;
8856 char *fixpos;
8857 long slot;
8858
8859 slot = fix->fx_where & 0x3;
8860 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
8861
c67e42c9 8862 /* Bundles are always in little-endian byte order */
800eeca4
JW		 8863 t0 = bfd_getl64 (fixpos);
8864 t1 = bfd_getl64 (fixpos + 8);
8865 control_bits = t0 & 0x1f;
8866 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
8867 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
8868 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
8869
c67e42c9
RH		 8870 err = NULL;
8871 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 8872 {
c67e42c9
RH		 8873 insn[1] = (value >> 22) & 0x1ffffffffffLL;
8874 insn[2] |= (((value & 0x7f) << 13)
8875 | (((value >> 7) & 0x1ff) << 27)
8876 | (((value >> 16) & 0x1f) << 22)
8877 | (((value >> 21) & 0x1) << 21)
8878 | (((value >> 63) & 0x1) << 36));
800eeca4 8879 }
c67e42c9
RH		 8880 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
8881 {
8882 if (value & ~0x3fffffffffffffffULL)
8883 err = "integer operand out of range";
8884 insn[1] = (value >> 21) & 0x1ffffffffffLL;
8885 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
8886 }
8887 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
8888 {
8889 value >>= 4;
8890 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
8891 insn[2] |= ((((value >> 59) & 0x1) << 36)
8892 | (((value >> 0) & 0xfffff) << 13));
8893 }
8894 else
8895 err = (*odesc->insert) (odesc, value, insn + slot);
8896
8897 if (err)
8898 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 8899
8900 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
8901 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
8902 md_number_to_chars (fixpos + 0, t0, 8);
8903 md_number_to_chars (fixpos + 8, t1, 8);
800eeca4
JW		 8904}
8905
8906/* Attempt to simplify or even eliminate a fixup. The return value is
8907 ignored; perhaps it was once meaningful, but now it is historical.
8908 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
8909
8910 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
8911 (if possible). */
8912int
8913md_apply_fix3 (fix, valuep, seg)
8914 fixS *fix;
8915 valueT *valuep;
8916 segT seg;
8917{
8918 char *fixpos;
8919 valueT value = *valuep;
8920 int adjust = 0;
8921
8922 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
8923
8924 if (fix->fx_pcrel)
8925 {
8926 switch (fix->fx_r_type)
8927 {
8928 case BFD_RELOC_IA64_DIR32MSB:
8929 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
8930 adjust = 1;
8931 break;
8932
8933 case BFD_RELOC_IA64_DIR32LSB:
8934 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
8935 adjust = 1;
8936 break;
8937
8938 case BFD_RELOC_IA64_DIR64MSB:
8939 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
8940 adjust = 1;
8941 break;
8942
8943 case BFD_RELOC_IA64_DIR64LSB:
8944 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
8945 adjust = 1;
8946 break;
8947
8948 default:
8949 break;
8950 }
8951 }
8952 if (fix->fx_addsy)
8953 {
8954 switch (fix->fx_r_type)
8955 {
8956 case 0:
8957 as_bad_where (fix->fx_file, fix->fx_line,
8958 "%s must have a constant value",
8959 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
8960 break;
8961
8962 default:
8963 break;
8964 }
8965
8966 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
8967 work. There should be a better way to handle this. */
8968 if (adjust)
8969 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
8970 }
8971 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
8972 {
8973 if (fix->tc_fix_data.bigendian)
8974 number_to_chars_bigendian (fixpos, value, fix->fx_size);
8975 else
8976 number_to_chars_littleendian (fixpos, value, fix->fx_size);
8977 fix->fx_done = 1;
8978 return 1;
8979 }
8980 else
8981 {
8982 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
8983 fix->fx_done = 1;
8984 return 1;
8985 }
8986 return 1;
8987}
8988
8989/* Generate the BFD reloc to be stuck in the object file from the
8990 fixup used internally in the assembler. */
8991arelent*
8992tc_gen_reloc (sec, fixp)
8993 asection *sec;
8994 fixS *fixp;
8995{
8996 arelent *reloc;
8997
8998 reloc = xmalloc (sizeof (*reloc));
8999 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9000 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9001 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9002 reloc->addend = fixp->fx_offset;
9003 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9004
9005 if (!reloc->howto)
9006 {
9007 as_bad_where (fixp->fx_file, fixp->fx_line,
9008 "Cannot represent %s relocation in object file",
9009 bfd_get_reloc_code_name (fixp->fx_r_type));
9010 }
9011 return reloc;
9012}
9013
9014/* Turn a string in input_line_pointer into a floating point constant
9015 of type type, and store the appropriate bytes in *lit. The number
9016 of LITTLENUMS emitted is stored in *size. An error message is
9017 returned, or NULL on OK. */
9018
9019#define MAX_LITTLENUMS 5
9020
9021char*
9022md_atof (type, lit, size)
9023 int type;
9024 char *lit;
9025 int *size;
9026{
9027 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9028 LITTLENUM_TYPE *word;
9029 char *t;
9030 int prec;
9031
9032 switch (type)
9033 {
9034 /* IEEE floats */
9035 case 'f':
9036 case 'F':
9037 case 's':
9038 case 'S':
9039 prec = 2;
9040 break;
9041
9042 case 'd':
9043 case 'D':
9044 case 'r':
9045 case 'R':
9046 prec = 4;
9047 break;
9048
9049 case 'x':
9050 case 'X':
9051 case 'p':
9052 case 'P':
9053 prec = 5;
9054 break;
9055
9056 default:
9057 *size = 0;
9058 return "Bad call to MD_ATOF()";
9059 }
9060 t = atof_ieee (input_line_pointer, type, words);
9061 if (t)
9062 input_line_pointer = t;
9063 *size = prec * sizeof (LITTLENUM_TYPE);
9064
9065 for (word = words + prec - 1; prec--;)
9066 {
9067 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9068 lit += sizeof (LITTLENUM_TYPE);
9069 }
9070 return 0;
9071}
9072
9073/* Round up a section's size to the appropriate boundary. */
9074valueT
9075md_section_align (seg, size)
9076 segT seg;
9077 valueT size;
9078{
9079 int align = bfd_get_section_alignment (stdoutput, seg);
9080 valueT mask = ((valueT)1 << align) - 1;
9081
9082 return (size + mask) & ~mask;
9083}
9084
9085/* Handle ia64 specific semantics of the align directive. */
9086
9087int
9088ia64_md_do_align (n, fill, len, max)
9089 int n;
9090 const char *fill;
9091 int len;
9092 int max;
9093{
9094 /* Fill any pending bundle with nops. */
9095 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9096 ia64_flush_insns ();
9097
9098 /* When we align code in a text section, emit a bundle of 3 nops instead of
9099 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9100 N is log base 2 of the requested alignment. */
9101 if (fill == NULL
9102 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9103 && n > 4)
9104 {
9105 /* Use mfi bundle of nops with no stop bits. */
9106 static const unsigned char be_nop[]
9107 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9108 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9109 static const unsigned char le_nop[]
9110 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9111 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9112
9113 /* Make sure we are on a 16-byte boundary, in case someone has been
9114 putting data into a text section. */
9115 frag_align (4, 0, 0);
9116
9117 if (target_big_endian)
9118 frag_align_pattern (n, be_nop, 16, max);
9119 else
9120 frag_align_pattern (n, le_nop, 16, max);
9121 return 1;
9122 }
9123
9124 return 0;
9125}
GDB Binutils - Deliverables
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