* s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to
[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
CommitLineData
800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
b3dfd7fe 2 Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
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35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
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38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
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42
43 */
44
45#include "as.h"
3882b010 46#include "safe-ctype.h"
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47#include "dwarf2dbg.h"
48#include "subsegs.h"
49
50#include "opcode/ia64.h"
51
52#include "elf/ia64.h"
53
54#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55#define MIN(a,b) ((a) < (b) ? (a) : (b))
56
57#define NUM_SLOTS 4
58#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59#define CURR_SLOT md.slot[md.curr_slot]
60
61#define O_pseudo_fixup (O_max + 1)
62
63enum special_section
64 {
557debba 65 /* IA-64 ABI section pseudo-ops. */
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66 SPECIAL_SECTION_BSS = 0,
67 SPECIAL_SECTION_SBSS,
68 SPECIAL_SECTION_SDATA,
69 SPECIAL_SECTION_RODATA,
70 SPECIAL_SECTION_COMMENT,
71 SPECIAL_SECTION_UNWIND,
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72 SPECIAL_SECTION_UNWIND_INFO,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY,
75 SPECIAL_SECTION_FINI_ARRAY,
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76 };
77
78enum reloc_func
79 {
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80 FUNC_DTP_MODULE,
81 FUNC_DTP_RELATIVE,
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82 FUNC_FPTR_RELATIVE,
83 FUNC_GP_RELATIVE,
84 FUNC_LT_RELATIVE,
fa2c7eff 85 FUNC_LT_RELATIVE_X,
c67e42c9 86 FUNC_PC_RELATIVE,
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87 FUNC_PLT_RELATIVE,
88 FUNC_SEC_RELATIVE,
89 FUNC_SEG_RELATIVE,
13ae64f3 90 FUNC_TP_RELATIVE,
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91 FUNC_LTV_RELATIVE,
92 FUNC_LT_FPTR_RELATIVE,
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93 FUNC_LT_DTP_MODULE,
94 FUNC_LT_DTP_RELATIVE,
95 FUNC_LT_TP_RELATIVE,
3969b680 96 FUNC_IPLT_RELOC,
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97 };
98
99enum reg_symbol
100 {
101 REG_GR = 0,
102 REG_FR = (REG_GR + 128),
103 REG_AR = (REG_FR + 128),
104 REG_CR = (REG_AR + 128),
105 REG_P = (REG_CR + 128),
106 REG_BR = (REG_P + 64),
107 REG_IP = (REG_BR + 8),
108 REG_CFM,
109 REG_PR,
110 REG_PR_ROT,
111 REG_PSR,
112 REG_PSR_L,
113 REG_PSR_UM,
114 /* The following are pseudo-registers for use by gas only. */
115 IND_CPUID,
116 IND_DBR,
117 IND_DTR,
118 IND_ITR,
119 IND_IBR,
120 IND_MEM,
121 IND_MSR,
122 IND_PKR,
123 IND_PMC,
124 IND_PMD,
125 IND_RR,
542d6675 126 /* The following pseudo-registers are used for unwind directives only: */
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127 REG_PSP,
128 REG_PRIUNAT,
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129 REG_NUM
130 };
131
132enum dynreg_type
133 {
134 DYNREG_GR = 0, /* dynamic general purpose register */
135 DYNREG_FR, /* dynamic floating point register */
136 DYNREG_PR, /* dynamic predicate register */
137 DYNREG_NUM_TYPES
138 };
139
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140enum operand_match_result
141 {
142 OPERAND_MATCH,
143 OPERAND_OUT_OF_RANGE,
144 OPERAND_MISMATCH
145 };
146
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147/* On the ia64, we can't know the address of a text label until the
148 instructions are packed into a bundle. To handle this, we keep
149 track of the list of labels that appear in front of each
150 instruction. */
151struct label_fix
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152{
153 struct label_fix *next;
154 struct symbol *sym;
155};
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156
157extern int target_big_endian;
158
159/* Characters which always start a comment. */
160const char comment_chars[] = "";
161
162/* Characters which start a comment at the beginning of a line. */
163const char line_comment_chars[] = "#";
164
165/* Characters which may be used to separate multiple commands on a
166 single line. */
167const char line_separator_chars[] = ";";
168
169/* Characters which are used to indicate an exponent in a floating
170 point number. */
171const char EXP_CHARS[] = "eE";
172
173/* Characters which mean that a number is a floating point constant,
174 as in 0d1.0. */
175const char FLT_CHARS[] = "rRsSfFdDxXpP";
176
542d6675 177/* ia64-specific option processing: */
800eeca4 178
44f5c83a 179const char *md_shortopts = "m:N:x::";
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180
181struct option md_longopts[] =
182 {
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183#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
184 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
185#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
186 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
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187 };
188
189size_t md_longopts_size = sizeof (md_longopts);
190
191static struct
192 {
193 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
194 struct hash_control *reg_hash; /* register name hash table */
195 struct hash_control *dynreg_hash; /* dynamic register hash table */
196 struct hash_control *const_hash; /* constant hash table */
197 struct hash_control *entry_hash; /* code entry hint hash table */
198
199 symbolS *regsym[REG_NUM];
200
201 /* If X_op is != O_absent, the registername for the instruction's
202 qualifying predicate. If NULL, p0 is assumed for instructions
203 that are predicatable. */
204 expressionS qp;
205
206 unsigned int
197865e8 207 manual_bundling : 1,
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208 debug_dv: 1,
209 detect_dv: 1,
210 explicit_mode : 1, /* which mode we're in */
211 default_explicit_mode : 1, /* which mode is the default */
212 mode_explicitly_set : 1, /* was the current mode explicitly set? */
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213 auto_align : 1,
214 keep_pending_output : 1;
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215
216 /* Each bundle consists of up to three instructions. We keep
217 track of four most recent instructions so we can correctly set
197865e8 218 the end_of_insn_group for the last instruction in a bundle. */
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219 int curr_slot;
220 int num_slots_in_use;
221 struct slot
222 {
223 unsigned int
224 end_of_insn_group : 1,
225 manual_bundling_on : 1,
226 manual_bundling_off : 1;
227 signed char user_template; /* user-selected template, if any */
228 unsigned char qp_regno; /* qualifying predicate */
229 /* This duplicates a good fraction of "struct fix" but we
230 can't use a "struct fix" instead since we can't call
231 fix_new_exp() until we know the address of the instruction. */
232 int num_fixups;
233 struct insn_fix
234 {
235 bfd_reloc_code_real_type code;
236 enum ia64_opnd opnd; /* type of operand in need of fix */
237 unsigned int is_pcrel : 1; /* is operand pc-relative? */
238 expressionS expr; /* the value to be inserted */
239 }
240 fixup[2]; /* at most two fixups per insn */
241 struct ia64_opcode *idesc;
242 struct label_fix *label_fixups;
f1bcba5b 243 struct label_fix *tag_fixups;
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244 struct unw_rec_list *unwind_record; /* Unwind directive. */
245 expressionS opnd[6];
246 char *src_file;
247 unsigned int src_line;
248 struct dwarf2_line_info debug_line;
249 }
250 slot[NUM_SLOTS];
251
252 segT last_text_seg;
253
254 struct dynreg
255 {
256 struct dynreg *next; /* next dynamic register */
257 const char *name;
258 unsigned short base; /* the base register number */
259 unsigned short num_regs; /* # of registers in this set */
260 }
261 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
262
263 flagword flags; /* ELF-header flags */
264
265 struct mem_offset {
266 unsigned hint:1; /* is this hint currently valid? */
267 bfd_vma offset; /* mem.offset offset */
268 bfd_vma base; /* mem.offset base */
269 } mem_offset;
270
271 int path; /* number of alt. entry points seen */
272 const char **entry_labels; /* labels of all alternate paths in
542d6675 273 the current DV-checking block. */
800eeca4 274 int maxpaths; /* size currently allocated for
542d6675 275 entry_labels */
88be23ec
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276 /* Support for hardware errata workarounds. */
277
278 /* Record data about the last three insn groups. */
279 struct group
280 {
281 /* B-step workaround.
282 For each predicate register, this is set if the corresponding insn
283 group conditionally sets this register with one of the affected
284 instructions. */
285 int p_reg_set[64];
286 /* B-step workaround.
287 For each general register, this is set if the corresponding insn
288 a) is conditional one one of the predicate registers for which
289 P_REG_SET is 1 in the corresponding entry of the previous group,
290 b) sets this general register with one of the affected
291 instructions. */
292 int g_reg_set_conditionally[128];
293 } last_groups[3];
294 int group_idx;
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295
296 int pointer_size; /* size in bytes of a pointer */
297 int pointer_size_shift; /* shift size of a pointer for alignment */
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298 }
299md;
300
542d6675 301/* application registers: */
800eeca4 302
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303#define AR_K0 0
304#define AR_K7 7
305#define AR_RSC 16
306#define AR_BSP 17
307#define AR_BSPSTORE 18
308#define AR_RNAT 19
309#define AR_UNAT 36
310#define AR_FPSR 40
311#define AR_ITC 44
312#define AR_PFS 64
313#define AR_LC 65
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314
315static const struct
316 {
317 const char *name;
318 int regnum;
319 }
320ar[] =
321 {
322 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
323 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
324 {"ar.rsc", 16}, {"ar.bsp", 17},
325 {"ar.bspstore", 18}, {"ar.rnat", 19},
326 {"ar.fcr", 21}, {"ar.eflag", 24},
327 {"ar.csd", 25}, {"ar.ssd", 26},
328 {"ar.cflg", 27}, {"ar.fsr", 28},
329 {"ar.fir", 29}, {"ar.fdr", 30},
330 {"ar.ccv", 32}, {"ar.unat", 36},
331 {"ar.fpsr", 40}, {"ar.itc", 44},
332 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 333 {"ar.ec", 66},
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334 };
335
336#define CR_IPSR 16
337#define CR_ISR 17
338#define CR_IIP 19
339#define CR_IFA 20
340#define CR_ITIR 21
341#define CR_IIPA 22
342#define CR_IFS 23
343#define CR_IIM 24
344#define CR_IHA 25
345#define CR_IVR 65
346#define CR_TPR 66
347#define CR_EOI 67
348#define CR_IRR0 68
349#define CR_IRR3 71
350#define CR_LRR0 80
351#define CR_LRR1 81
352
542d6675 353/* control registers: */
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354static const struct
355 {
356 const char *name;
357 int regnum;
358 }
359cr[] =
360 {
361 {"cr.dcr", 0},
362 {"cr.itm", 1},
363 {"cr.iva", 2},
364 {"cr.pta", 8},
365 {"cr.gpta", 9},
366 {"cr.ipsr", 16},
367 {"cr.isr", 17},
368 {"cr.iip", 19},
369 {"cr.ifa", 20},
370 {"cr.itir", 21},
371 {"cr.iipa", 22},
372 {"cr.ifs", 23},
373 {"cr.iim", 24},
374 {"cr.iha", 25},
375 {"cr.lid", 64},
376 {"cr.ivr", 65},
377 {"cr.tpr", 66},
378 {"cr.eoi", 67},
379 {"cr.irr0", 68},
380 {"cr.irr1", 69},
381 {"cr.irr2", 70},
382 {"cr.irr3", 71},
383 {"cr.itv", 72},
384 {"cr.pmv", 73},
385 {"cr.cmcv", 74},
386 {"cr.lrr0", 80},
387 {"cr.lrr1", 81}
388 };
389
390#define PSR_MFL 4
391#define PSR_IC 13
392#define PSR_DFL 18
393#define PSR_CPL 32
394
395static const struct const_desc
396 {
397 const char *name;
398 valueT value;
399 }
400const_bits[] =
401 {
542d6675 402 /* PSR constant masks: */
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403
404 /* 0: reserved */
405 {"psr.be", ((valueT) 1) << 1},
406 {"psr.up", ((valueT) 1) << 2},
407 {"psr.ac", ((valueT) 1) << 3},
408 {"psr.mfl", ((valueT) 1) << 4},
409 {"psr.mfh", ((valueT) 1) << 5},
410 /* 6-12: reserved */
411 {"psr.ic", ((valueT) 1) << 13},
412 {"psr.i", ((valueT) 1) << 14},
413 {"psr.pk", ((valueT) 1) << 15},
414 /* 16: reserved */
415 {"psr.dt", ((valueT) 1) << 17},
416 {"psr.dfl", ((valueT) 1) << 18},
417 {"psr.dfh", ((valueT) 1) << 19},
418 {"psr.sp", ((valueT) 1) << 20},
419 {"psr.pp", ((valueT) 1) << 21},
420 {"psr.di", ((valueT) 1) << 22},
421 {"psr.si", ((valueT) 1) << 23},
422 {"psr.db", ((valueT) 1) << 24},
423 {"psr.lp", ((valueT) 1) << 25},
424 {"psr.tb", ((valueT) 1) << 26},
425 {"psr.rt", ((valueT) 1) << 27},
426 /* 28-31: reserved */
427 /* 32-33: cpl (current privilege level) */
428 {"psr.is", ((valueT) 1) << 34},
429 {"psr.mc", ((valueT) 1) << 35},
430 {"psr.it", ((valueT) 1) << 36},
431 {"psr.id", ((valueT) 1) << 37},
432 {"psr.da", ((valueT) 1) << 38},
433 {"psr.dd", ((valueT) 1) << 39},
434 {"psr.ss", ((valueT) 1) << 40},
435 /* 41-42: ri (restart instruction) */
436 {"psr.ed", ((valueT) 1) << 43},
437 {"psr.bn", ((valueT) 1) << 44},
438 };
439
542d6675 440/* indirect register-sets/memory: */
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441
442static const struct
443 {
444 const char *name;
445 int regnum;
446 }
447indirect_reg[] =
448 {
449 { "CPUID", IND_CPUID },
450 { "cpuid", IND_CPUID },
451 { "dbr", IND_DBR },
452 { "dtr", IND_DTR },
453 { "itr", IND_ITR },
454 { "ibr", IND_IBR },
455 { "msr", IND_MSR },
456 { "pkr", IND_PKR },
457 { "pmc", IND_PMC },
458 { "pmd", IND_PMD },
459 { "rr", IND_RR },
460 };
461
462/* Pseudo functions used to indicate relocation types (these functions
463 start with an at sign (@). */
464static struct
465 {
466 const char *name;
467 enum pseudo_type
468 {
469 PSEUDO_FUNC_NONE,
470 PSEUDO_FUNC_RELOC,
471 PSEUDO_FUNC_CONST,
e0c9811a 472 PSEUDO_FUNC_REG,
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473 PSEUDO_FUNC_FLOAT
474 }
475 type;
476 union
477 {
478 unsigned long ival;
479 symbolS *sym;
480 }
481 u;
482 }
483pseudo_func[] =
484 {
542d6675 485 /* reloc pseudo functions (these must come first!): */
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486 { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } },
487 { "dtprel", PSEUDO_FUNC_RELOC, { 0 } },
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488 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
489 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
490 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
fa2c7eff 491 { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } },
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492 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
493 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
494 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
495 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
13ae64f3 496 { "tprel", PSEUDO_FUNC_RELOC, { 0 } },
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497 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
498 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
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499 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */
500 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */
501 { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */
3969b680 502 { "iplt", PSEUDO_FUNC_RELOC, { 0 } },
800eeca4 503
542d6675 504 /* mbtype4 constants: */
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505 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
506 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
507 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
508 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
509 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
510
542d6675 511 /* fclass constants: */
bf3ca999 512 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
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513 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
514 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
515 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
516 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
517 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
518 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
519 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
520 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
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521
522 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a 523
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524 /* hint constants: */
525 { "pause", PSEUDO_FUNC_CONST, { 0x0 } },
526
542d6675 527 /* unwind-related constants: */
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528 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
529 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
530 { "nt", PSEUDO_FUNC_CONST, { 2 } },
531
542d6675 532 /* unwind-related registers: */
e0c9811a 533 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
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534 };
535
542d6675 536/* 41-bit nop opcodes (one per unit): */
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537static const bfd_vma nop[IA64_NUM_UNITS] =
538 {
539 0x0000000000LL, /* NIL => break 0 */
540 0x0008000000LL, /* I-unit nop */
541 0x0008000000LL, /* M-unit nop */
542 0x4000000000LL, /* B-unit nop */
543 0x0008000000LL, /* F-unit nop */
544 0x0008000000LL, /* L-"unit" nop */
545 0x0008000000LL, /* X-unit nop */
546 };
547
548/* Can't be `const' as it's passed to input routines (which have the
549 habit of setting temporary sentinels. */
550static char special_section_name[][20] =
551 {
552 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
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553 {".IA_64.unwind"}, {".IA_64.unwind_info"},
554 {".init_array"}, {".fini_array"}
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555 };
556
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557static char *special_linkonce_name[] =
558 {
559 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
560 };
561
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562/* The best template for a particular sequence of up to three
563 instructions: */
564#define N IA64_NUM_TYPES
565static unsigned char best_template[N][N][N];
566#undef N
567
568/* Resource dependencies currently in effect */
569static struct rsrc {
570 int depind; /* dependency index */
571 const struct ia64_dependency *dependency; /* actual dependency */
572 unsigned specific:1, /* is this a specific bit/regno? */
573 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
574 int index; /* specific regno/bit within dependency */
575 int note; /* optional qualifying note (0 if none) */
576#define STATE_NONE 0
577#define STATE_STOP 1
578#define STATE_SRLZ 2
579 int insn_srlz; /* current insn serialization state */
580 int data_srlz; /* current data serialization state */
581 int qp_regno; /* qualifying predicate for this usage */
582 char *file; /* what file marked this dependency */
2434f565 583 unsigned int line; /* what line marked this dependency */
800eeca4 584 struct mem_offset mem_offset; /* optional memory offset hint */
7484b8e6 585 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
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586 int path; /* corresponding code entry index */
587} *regdeps = NULL;
588static int regdepslen = 0;
589static int regdepstotlen = 0;
590static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
591static const char *dv_sem[] = { "none", "implied", "impliedf",
139368c9 592 "data", "instr", "specific", "stop", "other" };
7484b8e6 593static const char *dv_cmp_type[] = { "none", "OR", "AND" };
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594
595/* Current state of PR mutexation */
596static struct qpmutex {
597 valueT prmask;
598 int path;
599} *qp_mutexes = NULL; /* QP mutex bitmasks */
600static int qp_mutexeslen = 0;
601static int qp_mutexestotlen = 0;
197865e8 602static valueT qp_safe_across_calls = 0;
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603
604/* Current state of PR implications */
605static struct qp_imply {
606 unsigned p1:6;
607 unsigned p2:6;
608 unsigned p2_branched:1;
609 int path;
610} *qp_implies = NULL;
611static int qp_implieslen = 0;
612static int qp_impliestotlen = 0;
613
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614/* Keep track of static GR values so that indirect register usage can
615 sometimes be tracked. */
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616static struct gr {
617 unsigned known:1;
618 int path;
619 valueT value;
2434f565 620} gr_values[128] = {{ 1, 0, 0 }};
800eeca4
JW
621
622/* These are the routines required to output the various types of
623 unwind records. */
624
f5a30c2e
JW
625/* A slot_number is a frag address plus the slot index (0-2). We use the
626 frag address here so that if there is a section switch in the middle of
627 a function, then instructions emitted to a different section are not
628 counted. Since there may be more than one frag for a function, this
629 means we also need to keep track of which frag this address belongs to
630 so we can compute inter-frag distances. This also nicely solves the
631 problem with nops emitted for align directives, which can't easily be
632 counted, but can easily be derived from frag sizes. */
633
800eeca4
JW
634typedef struct unw_rec_list {
635 unwind_record r;
e0c9811a 636 unsigned long slot_number;
f5a30c2e 637 fragS *slot_frag;
800eeca4
JW
638 struct unw_rec_list *next;
639} unw_rec_list;
640
2434f565 641#define SLOT_NUM_NOT_SET (unsigned)-1
800eeca4 642
6290819d
NC
643/* Linked list of saved prologue counts. A very poor
644 implementation of a map from label numbers to prologue counts. */
645typedef struct label_prologue_count
646{
647 struct label_prologue_count *next;
648 unsigned long label_number;
649 unsigned int prologue_count;
650} label_prologue_count;
651
e0c9811a
JW
652static struct
653{
654 unsigned long next_slot_number;
f5a30c2e 655 fragS *next_slot_frag;
e0c9811a
JW
656
657 /* Maintain a list of unwind entries for the current function. */
658 unw_rec_list *list;
659 unw_rec_list *tail;
800eeca4 660
e0c9811a
JW
661 /* Any unwind entires that should be attached to the current slot
662 that an insn is being constructed for. */
663 unw_rec_list *current_entry;
800eeca4 664
e0c9811a
JW
665 /* These are used to create the unwind table entry for this function. */
666 symbolS *proc_start;
667 symbolS *proc_end;
668 symbolS *info; /* pointer to unwind info */
669 symbolS *personality_routine;
91a2ae2a
RH
670 segT saved_text_seg;
671 subsegT saved_text_subseg;
672 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */
800eeca4 673
e0c9811a
JW
674 /* TRUE if processing unwind directives in a prologue region. */
675 int prologue;
30d25259 676 int prologue_mask;
33d01f33 677 unsigned int prologue_count; /* number of .prologues seen so far */
6290819d
NC
678 /* Prologue counts at previous .label_state directives. */
679 struct label_prologue_count * saved_prologue_counts;
e0c9811a 680} unwind;
800eeca4
JW
681
682typedef void (*vbyte_func) PARAMS ((int, char *, char *));
683
542d6675 684/* Forward delarations: */
800eeca4
JW
685static int ar_is_in_integer_unit PARAMS ((int regnum));
686static void set_section PARAMS ((char *name));
687static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
688 unsigned int, unsigned int));
689static void dot_radix PARAMS ((int));
690static void dot_special_section PARAMS ((int));
691static void dot_proc PARAMS ((int));
692static void dot_fframe PARAMS ((int));
693static void dot_vframe PARAMS ((int));
150f24a2
JW
694static void dot_vframesp PARAMS ((int));
695static void dot_vframepsp PARAMS ((int));
800eeca4
JW
696static void dot_save PARAMS ((int));
697static void dot_restore PARAMS ((int));
150f24a2
JW
698static void dot_restorereg PARAMS ((int));
699static void dot_restorereg_p PARAMS ((int));
800eeca4
JW
700static void dot_handlerdata PARAMS ((int));
701static void dot_unwentry PARAMS ((int));
702static void dot_altrp PARAMS ((int));
e0c9811a 703static void dot_savemem PARAMS ((int));
800eeca4
JW
704static void dot_saveg PARAMS ((int));
705static void dot_savef PARAMS ((int));
706static void dot_saveb PARAMS ((int));
707static void dot_savegf PARAMS ((int));
708static void dot_spill PARAMS ((int));
150f24a2
JW
709static void dot_spillreg PARAMS ((int));
710static void dot_spillmem PARAMS ((int));
711static void dot_spillreg_p PARAMS ((int));
712static void dot_spillmem_p PARAMS ((int));
713static void dot_label_state PARAMS ((int));
714static void dot_copy_state PARAMS ((int));
800eeca4
JW
715static void dot_unwabi PARAMS ((int));
716static void dot_personality PARAMS ((int));
717static void dot_body PARAMS ((int));
718static void dot_prologue PARAMS ((int));
719static void dot_endp PARAMS ((int));
720static void dot_template PARAMS ((int));
721static void dot_regstk PARAMS ((int));
722static void dot_rot PARAMS ((int));
723static void dot_byteorder PARAMS ((int));
724static void dot_psr PARAMS ((int));
725static void dot_alias PARAMS ((int));
726static void dot_ln PARAMS ((int));
727static char *parse_section_name PARAMS ((void));
728static void dot_xdata PARAMS ((int));
729static void stmt_float_cons PARAMS ((int));
730static void stmt_cons_ua PARAMS ((int));
731static void dot_xfloat_cons PARAMS ((int));
732static void dot_xstringer PARAMS ((int));
733static void dot_xdata_ua PARAMS ((int));
734static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 735static void print_prmask PARAMS ((valueT mask));
800eeca4
JW
736static void dot_pred_rel PARAMS ((int));
737static void dot_reg_val PARAMS ((int));
738static void dot_dv_mode PARAMS ((int));
739static void dot_entry PARAMS ((int));
740static void dot_mem_offset PARAMS ((int));
e0c9811a 741static void add_unwind_entry PARAMS((unw_rec_list *ptr));
542d6675 742static symbolS *declare_register PARAMS ((const char *name, int regnum));
800eeca4
JW
743static void declare_register_set PARAMS ((const char *, int, int));
744static unsigned int operand_width PARAMS ((enum ia64_opnd));
87f8eb97
JW
745static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
746 int index,
747 expressionS *e));
800eeca4
JW
748static int parse_operand PARAMS ((expressionS *e));
749static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
86cf98f3 750static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit));
800eeca4
JW
751static void build_insn PARAMS ((struct slot *, bfd_vma *));
752static void emit_one_bundle PARAMS ((void));
753static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 754static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW
755 bfd_reloc_code_real_type r_type));
756static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW
757static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
758 struct rsrc *, int depind, int path));
800eeca4
JW
759static void add_qp_mutex PARAMS((valueT mask));
760static void add_qp_imply PARAMS((int p1, int p2));
761static void clear_qp_branch_flag PARAMS((valueT mask));
762static void clear_qp_mutex PARAMS((valueT mask));
763static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
cb5301b6 764static int has_suffix_p PARAMS((const char *, const char *));
800eeca4
JW
765static void clear_register_values PARAMS ((void));
766static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW
767static void instruction_serialization PARAMS ((void));
768static void data_serialization PARAMS ((void));
769static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 770static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 771static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 772static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW
773static int depends_on PARAMS ((int, struct ia64_opcode *));
774static int specify_resource PARAMS ((const struct ia64_dependency *,
775 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW
776static int check_dv PARAMS((struct ia64_opcode *idesc));
777static void check_dependencies PARAMS((struct ia64_opcode *));
778static void mark_resources PARAMS((struct ia64_opcode *));
779static void update_dependencies PARAMS((struct ia64_opcode *));
780static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW
781static int qp_mutex PARAMS ((int, int, int));
782static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
783static void output_vbyte_mem PARAMS ((int, char *, char *));
784static void count_output PARAMS ((int, char *, char *));
785static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
786static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 787static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW
788static void output_P1_format PARAMS ((vbyte_func, int));
789static void output_P2_format PARAMS ((vbyte_func, int, int));
790static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
791static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
792static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
793static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
794static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
795static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
796static void output_P9_format PARAMS ((vbyte_func, int, int));
797static void output_P10_format PARAMS ((vbyte_func, int, int));
798static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
799static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW
800static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
801static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW
802static char format_ab_reg PARAMS ((int, int));
803static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
804 unsigned long));
805static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
806static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
807 unsigned long));
808static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
809static void free_list_records PARAMS ((unw_rec_list *));
810static unw_rec_list *output_prologue PARAMS ((void));
811static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
812static unw_rec_list *output_body PARAMS ((void));
813static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
814static unw_rec_list *output_mem_stack_v PARAMS ((void));
815static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
816static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
817static unw_rec_list *output_rp_when PARAMS ((void));
818static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
819static unw_rec_list *output_rp_br PARAMS ((unsigned int));
820static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
821static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
822static unw_rec_list *output_pfs_when PARAMS ((void));
823static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
824static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
825static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
826static unw_rec_list *output_preds_when PARAMS ((void));
827static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
828static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
829static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
830static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
831static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
832static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
833static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
834static unw_rec_list *output_br_mem PARAMS ((unsigned int));
835static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
836static unw_rec_list *output_spill_base PARAMS ((unsigned int));
837static unw_rec_list *output_unat_when PARAMS ((void));
838static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
839static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
840static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
841static unw_rec_list *output_lc_when PARAMS ((void));
842static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
843static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
844static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
845static unw_rec_list *output_fpsr_when PARAMS ((void));
846static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
847static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
848static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
849static unw_rec_list *output_priunat_when_gr PARAMS ((void));
850static unw_rec_list *output_priunat_when_mem PARAMS ((void));
851static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
852static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
853static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
854static unw_rec_list *output_bsp_when PARAMS ((void));
855static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
856static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
857static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
858static unw_rec_list *output_bspstore_when PARAMS ((void));
859static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
860static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
861static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
862static unw_rec_list *output_rnat_when PARAMS ((void));
863static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
864static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
865static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
866static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
867static unw_rec_list *output_epilogue PARAMS ((unsigned long));
868static unw_rec_list *output_label_state PARAMS ((unsigned long));
869static unw_rec_list *output_copy_state PARAMS ((unsigned long));
870static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
871static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
872static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
873 unsigned int));
874static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
875 unsigned int));
876static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
877 unsigned int));
878static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
879 unsigned int, unsigned int));
880static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
881static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
882static int calc_record_size PARAMS ((unw_rec_list *));
883static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
884static int count_bits PARAMS ((unsigned long));
f5a30c2e
JW
885static unsigned long slot_index PARAMS ((unsigned long, fragS *,
886 unsigned long, fragS *));
91a2ae2a 887static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
150f24a2
JW
888static void fixup_unw_records PARAMS ((unw_rec_list *));
889static int output_unw_records PARAMS ((unw_rec_list *, void **));
890static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
891static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
91a2ae2a 892static int generate_unwind_image PARAMS ((const char *));
6290819d
NC
893static unsigned int get_saved_prologue_count PARAMS ((unsigned long));
894static void save_prologue_count PARAMS ((unsigned long, unsigned int));
895static void free_saved_prologue_counts PARAMS ((void));
91a2ae2a
RH
896
897/* Build the unwind section name by appending the (possibly stripped)
898 text section NAME to the unwind PREFIX. The resulting string
899 pointer is assigned to RESULT. The string is allocated on the
40449e9f 900 stack, so this must be a macro... */
91a2ae2a
RH
901#define make_unw_section_name(special, text_name, result) \
902 { \
86cf98f3
RH
903 const char *_prefix = special_section_name[special]; \
904 const char *_suffix = text_name; \
579f31ac
JJ
905 size_t _prefix_len, _suffix_len; \
906 char *_result; \
907 if (strncmp (text_name, ".gnu.linkonce.t.", \
908 sizeof (".gnu.linkonce.t.") - 1) == 0) \
909 { \
910 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
911 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
912 } \
913 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
914 _result = alloca (_prefix_len + _suffix_len + 1); \
07726851
KH
915 memcpy (_result, _prefix, _prefix_len); \
916 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
579f31ac 917 _result[_prefix_len + _suffix_len] = '\0'; \
91a2ae2a
RH
918 result = _result; \
919 } \
920while (0)
800eeca4
JW
921
922/* Determine if application register REGNUM resides in the integer
923 unit (as opposed to the memory unit). */
924static int
925ar_is_in_integer_unit (reg)
926 int reg;
927{
928 reg -= REG_AR;
929
930 return (reg == 64 /* pfs */
931 || reg == 65 /* lc */
932 || reg == 66 /* ec */
933 /* ??? ias accepts and puts these in the integer unit. */
934 || (reg >= 112 && reg <= 127));
935}
936
937/* Switch to section NAME and create section if necessary. It's
938 rather ugly that we have to manipulate input_line_pointer but I
939 don't see any other way to accomplish the same thing without
940 changing obj-elf.c (which may be the Right Thing, in the end). */
941static void
942set_section (name)
943 char *name;
944{
945 char *saved_input_line_pointer;
946
947 saved_input_line_pointer = input_line_pointer;
948 input_line_pointer = name;
949 obj_elf_section (0);
950 input_line_pointer = saved_input_line_pointer;
951}
952
d61a78a7
RH
953/* Map 's' to SHF_IA_64_SHORT. */
954
955int
956ia64_elf_section_letter (letter, ptr_msg)
957 int letter;
958 char **ptr_msg;
959{
960 if (letter == 's')
961 return SHF_IA_64_SHORT;
962
13ae64f3 963 *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S,G,T in string");
d61a78a7
RH
964 return 0;
965}
966
800eeca4
JW
967/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
968
969flagword
970ia64_elf_section_flags (flags, attr, type)
971 flagword flags;
2434f565 972 int attr, type ATTRIBUTE_UNUSED;
800eeca4
JW
973{
974 if (attr & SHF_IA_64_SHORT)
975 flags |= SEC_SMALL_DATA;
976 return flags;
977}
978
91a2ae2a
RH
979int
980ia64_elf_section_type (str, len)
40449e9f
KH
981 const char *str;
982 size_t len;
91a2ae2a 983{
1cd8ff38 984#define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0))
40449e9f 985
1cd8ff38 986 if (STREQ (ELF_STRING_ia64_unwind_info))
91a2ae2a
RH
987 return SHT_PROGBITS;
988
1cd8ff38 989 if (STREQ (ELF_STRING_ia64_unwind_info_once))
579f31ac
JJ
990 return SHT_PROGBITS;
991
1cd8ff38 992 if (STREQ (ELF_STRING_ia64_unwind))
91a2ae2a
RH
993 return SHT_IA_64_UNWIND;
994
1cd8ff38 995 if (STREQ (ELF_STRING_ia64_unwind_once))
579f31ac
JJ
996 return SHT_IA_64_UNWIND;
997
1cd8ff38
NC
998 if (STREQ ("init_array"))
999 return SHT_INIT_ARRAY;
40449e9f 1000
1cd8ff38
NC
1001 if (STREQ ("fini_array"))
1002 return SHT_FINI_ARRAY;
40449e9f 1003
91a2ae2a 1004 return -1;
1cd8ff38 1005#undef STREQ
91a2ae2a
RH
1006}
1007
800eeca4
JW
1008static unsigned int
1009set_regstack (ins, locs, outs, rots)
1010 unsigned int ins, locs, outs, rots;
1011{
542d6675
KH
1012 /* Size of frame. */
1013 unsigned int sof;
800eeca4
JW
1014
1015 sof = ins + locs + outs;
1016 if (sof > 96)
1017 {
1018 as_bad ("Size of frame exceeds maximum of 96 registers");
1019 return 0;
1020 }
1021 if (rots > sof)
1022 {
1023 as_warn ("Size of rotating registers exceeds frame size");
1024 return 0;
1025 }
1026 md.in.base = REG_GR + 32;
1027 md.loc.base = md.in.base + ins;
1028 md.out.base = md.loc.base + locs;
1029
1030 md.in.num_regs = ins;
1031 md.loc.num_regs = locs;
1032 md.out.num_regs = outs;
1033 md.rot.num_regs = rots;
1034 return sof;
1035}
1036
1037void
1038ia64_flush_insns ()
1039{
1040 struct label_fix *lfix;
1041 segT saved_seg;
1042 subsegT saved_subseg;
b44b1b85 1043 unw_rec_list *ptr;
800eeca4
JW
1044
1045 if (!md.last_text_seg)
1046 return;
1047
1048 saved_seg = now_seg;
1049 saved_subseg = now_subseg;
1050
1051 subseg_set (md.last_text_seg, 0);
1052
1053 while (md.num_slots_in_use > 0)
1054 emit_one_bundle (); /* force out queued instructions */
1055
1056 /* In case there are labels following the last instruction, resolve
542d6675 1057 those now: */
800eeca4
JW
1058 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
1059 {
1060 S_SET_VALUE (lfix->sym, frag_now_fix ());
1061 symbol_set_frag (lfix->sym, frag_now);
1062 }
1063 CURR_SLOT.label_fixups = 0;
f1bcba5b
JW
1064 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
1065 {
1066 S_SET_VALUE (lfix->sym, frag_now_fix ());
1067 symbol_set_frag (lfix->sym, frag_now);
1068 }
1069 CURR_SLOT.tag_fixups = 0;
800eeca4 1070
b44b1b85
JW
1071 /* In case there are unwind directives following the last instruction,
1072 resolve those now. We only handle body and prologue directives here.
1073 Give an error for others. */
1074 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
1075 {
1076 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
1077 || ptr->r.type == body)
1078 {
1079 ptr->slot_number = (unsigned long) frag_more (0);
1080 ptr->slot_frag = frag_now;
1081 }
1082 else
1083 as_bad (_("Unwind directive not followed by an instruction."));
1084 }
1085 unwind.current_entry = NULL;
1086
800eeca4 1087 subseg_set (saved_seg, saved_subseg);
f1bcba5b
JW
1088
1089 if (md.qp.X_op == O_register)
1090 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW
1091}
1092
1093void
1094ia64_do_align (nbytes)
1095 int nbytes;
1096{
1097 char *saved_input_line_pointer = input_line_pointer;
1098
1099 input_line_pointer = "";
1100 s_align_bytes (nbytes);
1101 input_line_pointer = saved_input_line_pointer;
1102}
1103
1104void
1105ia64_cons_align (nbytes)
1106 int nbytes;
1107{
1108 if (md.auto_align)
1109 {
1110 char *saved_input_line_pointer = input_line_pointer;
1111 input_line_pointer = "";
1112 s_align_bytes (nbytes);
1113 input_line_pointer = saved_input_line_pointer;
1114 }
1115}
1116
1117/* Output COUNT bytes to a memory location. */
1118static unsigned char *vbyte_mem_ptr = NULL;
1119
197865e8 1120void
800eeca4
JW
1121output_vbyte_mem (count, ptr, comment)
1122 int count;
1123 char *ptr;
2434f565 1124 char *comment ATTRIBUTE_UNUSED;
800eeca4
JW
1125{
1126 int x;
1127 if (vbyte_mem_ptr == NULL)
1128 abort ();
1129
1130 if (count == 0)
1131 return;
1132 for (x = 0; x < count; x++)
1133 *(vbyte_mem_ptr++) = ptr[x];
1134}
1135
1136/* Count the number of bytes required for records. */
1137static int vbyte_count = 0;
197865e8 1138void
800eeca4
JW
1139count_output (count, ptr, comment)
1140 int count;
2434f565
JW
1141 char *ptr ATTRIBUTE_UNUSED;
1142 char *comment ATTRIBUTE_UNUSED;
800eeca4
JW
1143{
1144 vbyte_count += count;
1145}
1146
1147static void
1148output_R1_format (f, rtype, rlen)
1149 vbyte_func f;
1150 unw_record_type rtype;
1151 int rlen;
1152{
e0c9811a 1153 int r = 0;
800eeca4
JW
1154 char byte;
1155 if (rlen > 0x1f)
1156 {
1157 output_R3_format (f, rtype, rlen);
1158 return;
1159 }
197865e8 1160
e0c9811a
JW
1161 if (rtype == body)
1162 r = 1;
1163 else if (rtype != prologue)
1164 as_bad ("record type is not valid");
1165
800eeca4
JW
1166 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1167 (*f) (1, &byte, NULL);
1168}
1169
1170static void
1171output_R2_format (f, mask, grsave, rlen)
1172 vbyte_func f;
1173 int mask, grsave;
1174 unsigned long rlen;
1175{
1176 char bytes[20];
1177 int count = 2;
1178 mask = (mask & 0x0f);
1179 grsave = (grsave & 0x7f);
1180
1181 bytes[0] = (UNW_R2 | (mask >> 1));
1182 bytes[1] = (((mask & 0x01) << 7) | grsave);
1183 count += output_leb128 (bytes + 2, rlen, 0);
1184 (*f) (count, bytes, NULL);
1185}
1186
1187static void
1188output_R3_format (f, rtype, rlen)
1189 vbyte_func f;
1190 unw_record_type rtype;
1191 unsigned long rlen;
1192{
e0c9811a 1193 int r = 0, count;
800eeca4
JW
1194 char bytes[20];
1195 if (rlen <= 0x1f)
1196 {
1197 output_R1_format (f, rtype, rlen);
1198 return;
1199 }
197865e8 1200
e0c9811a
JW
1201 if (rtype == body)
1202 r = 1;
1203 else if (rtype != prologue)
1204 as_bad ("record type is not valid");
800eeca4
JW
1205 bytes[0] = (UNW_R3 | r);
1206 count = output_leb128 (bytes + 1, rlen, 0);
1207 (*f) (count + 1, bytes, NULL);
1208}
1209
1210static void
1211output_P1_format (f, brmask)
1212 vbyte_func f;
1213 int brmask;
1214{
1215 char byte;
1216 byte = UNW_P1 | (brmask & 0x1f);
1217 (*f) (1, &byte, NULL);
1218}
1219
1220static void
1221output_P2_format (f, brmask, gr)
1222 vbyte_func f;
1223 int brmask;
1224 int gr;
1225{
1226 char bytes[2];
1227 brmask = (brmask & 0x1f);
1228 bytes[0] = UNW_P2 | (brmask >> 1);
1229 bytes[1] = (((brmask & 1) << 7) | gr);
1230 (*f) (2, bytes, NULL);
1231}
1232
1233static void
1234output_P3_format (f, rtype, reg)
1235 vbyte_func f;
1236 unw_record_type rtype;
1237 int reg;
1238{
1239 char bytes[2];
e0c9811a 1240 int r = 0;
800eeca4
JW
1241 reg = (reg & 0x7f);
1242 switch (rtype)
542d6675 1243 {
800eeca4
JW
1244 case psp_gr:
1245 r = 0;
1246 break;
1247 case rp_gr:
1248 r = 1;
1249 break;
1250 case pfs_gr:
1251 r = 2;
1252 break;
1253 case preds_gr:
1254 r = 3;
1255 break;
1256 case unat_gr:
1257 r = 4;
1258 break;
1259 case lc_gr:
1260 r = 5;
1261 break;
1262 case rp_br:
1263 r = 6;
1264 break;
1265 case rnat_gr:
1266 r = 7;
1267 break;
1268 case bsp_gr:
1269 r = 8;
1270 break;
1271 case bspstore_gr:
1272 r = 9;
1273 break;
1274 case fpsr_gr:
1275 r = 10;
1276 break;
1277 case priunat_gr:
1278 r = 11;
1279 break;
1280 default:
1281 as_bad ("Invalid record type for P3 format.");
542d6675 1282 }
800eeca4
JW
1283 bytes[0] = (UNW_P3 | (r >> 1));
1284 bytes[1] = (((r & 1) << 7) | reg);
1285 (*f) (2, bytes, NULL);
1286}
1287
800eeca4 1288static void
e0c9811a 1289output_P4_format (f, imask, imask_size)
800eeca4 1290 vbyte_func f;
e0c9811a
JW
1291 unsigned char *imask;
1292 unsigned long imask_size;
800eeca4 1293{
e0c9811a
JW
1294 imask[0] = UNW_P4;
1295 (*f) (imask_size, imask, NULL);
800eeca4
JW
1296}
1297
1298static void
1299output_P5_format (f, grmask, frmask)
1300 vbyte_func f;
1301 int grmask;
1302 unsigned long frmask;
1303{
1304 char bytes[4];
1305 grmask = (grmask & 0x0f);
1306
1307 bytes[0] = UNW_P5;
1308 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1309 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1310 bytes[3] = (frmask & 0x000000ff);
1311 (*f) (4, bytes, NULL);
1312}
1313
1314static void
1315output_P6_format (f, rtype, rmask)
1316 vbyte_func f;
1317 unw_record_type rtype;
1318 int rmask;
1319{
1320 char byte;
e0c9811a 1321 int r = 0;
197865e8 1322
e0c9811a
JW
1323 if (rtype == gr_mem)
1324 r = 1;
1325 else if (rtype != fr_mem)
1326 as_bad ("Invalid record type for format P6");
800eeca4
JW
1327 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1328 (*f) (1, &byte, NULL);
1329}
1330
1331static void
1332output_P7_format (f, rtype, w1, w2)
1333 vbyte_func f;
1334 unw_record_type rtype;
1335 unsigned long w1;
1336 unsigned long w2;
1337{
1338 char bytes[20];
1339 int count = 1;
e0c9811a 1340 int r = 0;
800eeca4
JW
1341 count += output_leb128 (bytes + 1, w1, 0);
1342 switch (rtype)
1343 {
542d6675
KH
1344 case mem_stack_f:
1345 r = 0;
1346 count += output_leb128 (bytes + count, w2 >> 4, 0);
1347 break;
1348 case mem_stack_v:
1349 r = 1;
1350 break;
1351 case spill_base:
1352 r = 2;
1353 break;
1354 case psp_sprel:
1355 r = 3;
1356 break;
1357 case rp_when:
1358 r = 4;
1359 break;
1360 case rp_psprel:
1361 r = 5;
1362 break;
1363 case pfs_when:
1364 r = 6;
1365 break;
1366 case pfs_psprel:
1367 r = 7;
1368 break;
1369 case preds_when:
1370 r = 8;
1371 break;
1372 case preds_psprel:
1373 r = 9;
1374 break;
1375 case lc_when:
1376 r = 10;
1377 break;
1378 case lc_psprel:
1379 r = 11;
1380 break;
1381 case unat_when:
1382 r = 12;
1383 break;
1384 case unat_psprel:
1385 r = 13;
1386 break;
1387 case fpsr_when:
1388 r = 14;
1389 break;
1390 case fpsr_psprel:
1391 r = 15;
1392 break;
1393 default:
1394 break;
800eeca4
JW
1395 }
1396 bytes[0] = (UNW_P7 | r);
1397 (*f) (count, bytes, NULL);
1398}
1399
1400static void
1401output_P8_format (f, rtype, t)
1402 vbyte_func f;
1403 unw_record_type rtype;
1404 unsigned long t;
1405{
1406 char bytes[20];
e0c9811a 1407 int r = 0;
800eeca4
JW
1408 int count = 2;
1409 bytes[0] = UNW_P8;
1410 switch (rtype)
1411 {
542d6675
KH
1412 case rp_sprel:
1413 r = 1;
1414 break;
1415 case pfs_sprel:
1416 r = 2;
1417 break;
1418 case preds_sprel:
1419 r = 3;
1420 break;
1421 case lc_sprel:
1422 r = 4;
1423 break;
1424 case unat_sprel:
1425 r = 5;
1426 break;
1427 case fpsr_sprel:
1428 r = 6;
1429 break;
1430 case bsp_when:
1431 r = 7;
1432 break;
1433 case bsp_psprel:
1434 r = 8;
1435 break;
1436 case bsp_sprel:
1437 r = 9;
1438 break;
1439 case bspstore_when:
1440 r = 10;
1441 break;
1442 case bspstore_psprel:
1443 r = 11;
1444 break;
1445 case bspstore_sprel:
1446 r = 12;
1447 break;
1448 case rnat_when:
1449 r = 13;
1450 break;
1451 case rnat_psprel:
1452 r = 14;
1453 break;
1454 case rnat_sprel:
1455 r = 15;
1456 break;
1457 case priunat_when_gr:
1458 r = 16;
1459 break;
1460 case priunat_psprel:
1461 r = 17;
1462 break;
1463 case priunat_sprel:
1464 r = 18;
1465 break;
1466 case priunat_when_mem:
1467 r = 19;
1468 break;
1469 default:
1470 break;
800eeca4
JW
1471 }
1472 bytes[1] = r;
1473 count += output_leb128 (bytes + 2, t, 0);
1474 (*f) (count, bytes, NULL);
1475}
1476
1477static void
1478output_P9_format (f, grmask, gr)
1479 vbyte_func f;
1480 int grmask;
1481 int gr;
1482{
1483 char bytes[3];
1484 bytes[0] = UNW_P9;
1485 bytes[1] = (grmask & 0x0f);
1486 bytes[2] = (gr & 0x7f);
1487 (*f) (3, bytes, NULL);
1488}
1489
1490static void
1491output_P10_format (f, abi, context)
1492 vbyte_func f;
1493 int abi;
1494 int context;
1495{
1496 char bytes[3];
1497 bytes[0] = UNW_P10;
1498 bytes[1] = (abi & 0xff);
1499 bytes[2] = (context & 0xff);
1500 (*f) (3, bytes, NULL);
1501}
1502
1503static void
1504output_B1_format (f, rtype, label)
1505 vbyte_func f;
1506 unw_record_type rtype;
1507 unsigned long label;
1508{
1509 char byte;
e0c9811a 1510 int r = 0;
197865e8 1511 if (label > 0x1f)
800eeca4
JW
1512 {
1513 output_B4_format (f, rtype, label);
1514 return;
1515 }
e0c9811a
JW
1516 if (rtype == copy_state)
1517 r = 1;
1518 else if (rtype != label_state)
1519 as_bad ("Invalid record type for format B1");
800eeca4
JW
1520
1521 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1522 (*f) (1, &byte, NULL);
1523}
1524
1525static void
1526output_B2_format (f, ecount, t)
1527 vbyte_func f;
1528 unsigned long ecount;
1529 unsigned long t;
1530{
1531 char bytes[20];
1532 int count = 1;
1533 if (ecount > 0x1f)
1534 {
1535 output_B3_format (f, ecount, t);
1536 return;
1537 }
1538 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1539 count += output_leb128 (bytes + 1, t, 0);
1540 (*f) (count, bytes, NULL);
1541}
1542
1543static void
1544output_B3_format (f, ecount, t)
1545 vbyte_func f;
1546 unsigned long ecount;
1547 unsigned long t;
1548{
1549 char bytes[20];
1550 int count = 1;
1551 if (ecount <= 0x1f)
1552 {
1553 output_B2_format (f, ecount, t);
1554 return;
1555 }
1556 bytes[0] = UNW_B3;
1557 count += output_leb128 (bytes + 1, t, 0);
1558 count += output_leb128 (bytes + count, ecount, 0);
1559 (*f) (count, bytes, NULL);
1560}
1561
1562static void
1563output_B4_format (f, rtype, label)
1564 vbyte_func f;
1565 unw_record_type rtype;
1566 unsigned long label;
1567{
1568 char bytes[20];
e0c9811a 1569 int r = 0;
800eeca4 1570 int count = 1;
197865e8 1571 if (label <= 0x1f)
800eeca4
JW
1572 {
1573 output_B1_format (f, rtype, label);
1574 return;
1575 }
197865e8 1576
e0c9811a
JW
1577 if (rtype == copy_state)
1578 r = 1;
1579 else if (rtype != label_state)
1580 as_bad ("Invalid record type for format B1");
800eeca4
JW
1581
1582 bytes[0] = (UNW_B4 | (r << 3));
1583 count += output_leb128 (bytes + 1, label, 0);
1584 (*f) (count, bytes, NULL);
1585}
1586
1587static char
e0c9811a 1588format_ab_reg (ab, reg)
542d6675
KH
1589 int ab;
1590 int reg;
800eeca4
JW
1591{
1592 int ret;
e0c9811a 1593 ab = (ab & 3);
800eeca4 1594 reg = (reg & 0x1f);
e0c9811a 1595 ret = (ab << 5) | reg;
800eeca4
JW
1596 return ret;
1597}
1598
1599static void
e0c9811a 1600output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW
1601 vbyte_func f;
1602 unw_record_type rtype;
e0c9811a 1603 int ab, reg;
800eeca4
JW
1604 unsigned long t;
1605 unsigned long w1;
1606{
1607 char bytes[20];
e0c9811a 1608 int r = 0;
800eeca4
JW
1609 int count = 2;
1610 bytes[0] = UNW_X1;
197865e8 1611
e0c9811a
JW
1612 if (rtype == spill_sprel)
1613 r = 1;
1614 else if (rtype != spill_psprel)
1615 as_bad ("Invalid record type for format X1");
1616 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW
1617 count += output_leb128 (bytes + 2, t, 0);
1618 count += output_leb128 (bytes + count, w1, 0);
1619 (*f) (count, bytes, NULL);
1620}
1621
1622static void
e0c9811a 1623output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1624 vbyte_func f;
e0c9811a 1625 int ab, reg;
800eeca4
JW
1626 int x, y, treg;
1627 unsigned long t;
1628{
1629 char bytes[20];
800eeca4
JW
1630 int count = 3;
1631 bytes[0] = UNW_X2;
e0c9811a 1632 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW
1633 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1634 count += output_leb128 (bytes + 3, t, 0);
1635 (*f) (count, bytes, NULL);
1636}
1637
1638static void
e0c9811a 1639output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW
1640 vbyte_func f;
1641 unw_record_type rtype;
1642 int qp;
e0c9811a 1643 int ab, reg;
800eeca4
JW
1644 unsigned long t;
1645 unsigned long w1;
1646{
1647 char bytes[20];
e0c9811a 1648 int r = 0;
800eeca4 1649 int count = 3;
e0c9811a
JW
1650 bytes[0] = UNW_X3;
1651
1652 if (rtype == spill_sprel_p)
1653 r = 1;
1654 else if (rtype != spill_psprel_p)
1655 as_bad ("Invalid record type for format X3");
800eeca4 1656 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1657 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW
1658 count += output_leb128 (bytes + 3, t, 0);
1659 count += output_leb128 (bytes + count, w1, 0);
1660 (*f) (count, bytes, NULL);
1661}
1662
1663static void
e0c9811a 1664output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW
1665 vbyte_func f;
1666 int qp;
e0c9811a 1667 int ab, reg;
800eeca4
JW
1668 int x, y, treg;
1669 unsigned long t;
1670{
1671 char bytes[20];
800eeca4 1672 int count = 4;
e0c9811a 1673 bytes[0] = UNW_X4;
800eeca4 1674 bytes[1] = (qp & 0x3f);
e0c9811a 1675 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW
1676 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1677 count += output_leb128 (bytes + 4, t, 0);
1678 (*f) (count, bytes, NULL);
1679}
1680
1681/* This function allocates a record list structure, and initializes fields. */
542d6675 1682
800eeca4 1683static unw_rec_list *
197865e8 1684alloc_record (unw_record_type t)
800eeca4
JW
1685{
1686 unw_rec_list *ptr;
1687 ptr = xmalloc (sizeof (*ptr));
1688 ptr->next = NULL;
1689 ptr->slot_number = SLOT_NUM_NOT_SET;
1690 ptr->r.type = t;
1691 return ptr;
1692}
1693
800eeca4 1694/* This function frees an entire list of record structures. */
542d6675 1695
800eeca4
JW
1696void
1697free_list_records (unw_rec_list *first)
1698{
1699 unw_rec_list *ptr;
542d6675 1700 for (ptr = first; ptr != NULL;)
800eeca4
JW
1701 {
1702 unw_rec_list *tmp = ptr;
e0c9811a
JW
1703
1704 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1705 && tmp->r.record.r.mask.i)
1706 free (tmp->r.record.r.mask.i);
1707
800eeca4
JW
1708 ptr = ptr->next;
1709 free (tmp);
1710 }
1711}
1712
1713static unw_rec_list *
1714output_prologue ()
1715{
1716 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1717 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW
1718 return ptr;
1719}
1720
1721static unw_rec_list *
1722output_prologue_gr (saved_mask, reg)
1723 unsigned int saved_mask;
1724 unsigned int reg;
1725{
1726 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW
1727 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1728 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW
1729 ptr->r.record.r.grsave = reg;
1730 return ptr;
1731}
1732
1733static unw_rec_list *
1734output_body ()
1735{
1736 unw_rec_list *ptr = alloc_record (body);
1737 return ptr;
1738}
1739
1740static unw_rec_list *
1741output_mem_stack_f (size)
1742 unsigned int size;
1743{
1744 unw_rec_list *ptr = alloc_record (mem_stack_f);
1745 ptr->r.record.p.size = size;
1746 return ptr;
1747}
1748
1749static unw_rec_list *
1750output_mem_stack_v ()
1751{
1752 unw_rec_list *ptr = alloc_record (mem_stack_v);
1753 return ptr;
1754}
1755
1756static unw_rec_list *
1757output_psp_gr (gr)
1758 unsigned int gr;
1759{
1760 unw_rec_list *ptr = alloc_record (psp_gr);
1761 ptr->r.record.p.gr = gr;
1762 return ptr;
1763}
1764
1765static unw_rec_list *
1766output_psp_sprel (offset)
1767 unsigned int offset;
1768{
1769 unw_rec_list *ptr = alloc_record (psp_sprel);
542d6675 1770 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
1771 return ptr;
1772}
1773
1774static unw_rec_list *
1775output_rp_when ()
1776{
1777 unw_rec_list *ptr = alloc_record (rp_when);
1778 return ptr;
1779}
1780
1781static unw_rec_list *
1782output_rp_gr (gr)
1783 unsigned int gr;
1784{
1785 unw_rec_list *ptr = alloc_record (rp_gr);
1786 ptr->r.record.p.gr = gr;
1787 return ptr;
1788}
1789
1790static unw_rec_list *
1791output_rp_br (br)
1792 unsigned int br;
1793{
1794 unw_rec_list *ptr = alloc_record (rp_br);
1795 ptr->r.record.p.br = br;
1796 return ptr;
1797}
1798
1799static unw_rec_list *
1800output_rp_psprel (offset)
1801 unsigned int offset;
1802{
1803 unw_rec_list *ptr = alloc_record (rp_psprel);
542d6675 1804 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
1805 return ptr;
1806}
1807
1808static unw_rec_list *
1809output_rp_sprel (offset)
1810 unsigned int offset;
1811{
1812 unw_rec_list *ptr = alloc_record (rp_sprel);
542d6675 1813 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
1814 return ptr;
1815}
1816
1817static unw_rec_list *
1818output_pfs_when ()
1819{
1820 unw_rec_list *ptr = alloc_record (pfs_when);
1821 return ptr;
1822}
1823
1824static unw_rec_list *
1825output_pfs_gr (gr)
1826 unsigned int gr;
1827{
1828 unw_rec_list *ptr = alloc_record (pfs_gr);
1829 ptr->r.record.p.gr = gr;
1830 return ptr;
1831}
1832
1833static unw_rec_list *
1834output_pfs_psprel (offset)
1835 unsigned int offset;
1836{
1837 unw_rec_list *ptr = alloc_record (pfs_psprel);
542d6675 1838 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
1839 return ptr;
1840}
1841
1842static unw_rec_list *
1843output_pfs_sprel (offset)
1844 unsigned int offset;
1845{
1846 unw_rec_list *ptr = alloc_record (pfs_sprel);
542d6675 1847 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
1848 return ptr;
1849}
1850
1851static unw_rec_list *
1852output_preds_when ()
1853{
1854 unw_rec_list *ptr = alloc_record (preds_when);
1855 return ptr;
1856}
1857
1858static unw_rec_list *
1859output_preds_gr (gr)
1860 unsigned int gr;
1861{
1862 unw_rec_list *ptr = alloc_record (preds_gr);
1863 ptr->r.record.p.gr = gr;
1864 return ptr;
1865}
1866
1867static unw_rec_list *
1868output_preds_psprel (offset)
1869 unsigned int offset;
1870{
1871 unw_rec_list *ptr = alloc_record (preds_psprel);
542d6675 1872 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
1873 return ptr;
1874}
1875
1876static unw_rec_list *
1877output_preds_sprel (offset)
1878 unsigned int offset;
1879{
1880 unw_rec_list *ptr = alloc_record (preds_sprel);
542d6675 1881 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
1882 return ptr;
1883}
1884
1885static unw_rec_list *
1886output_fr_mem (mask)
1887 unsigned int mask;
1888{
1889 unw_rec_list *ptr = alloc_record (fr_mem);
1890 ptr->r.record.p.rmask = mask;
1891 return ptr;
1892}
1893
1894static unw_rec_list *
1895output_frgr_mem (gr_mask, fr_mask)
1896 unsigned int gr_mask;
1897 unsigned int fr_mask;
1898{
1899 unw_rec_list *ptr = alloc_record (frgr_mem);
1900 ptr->r.record.p.grmask = gr_mask;
1901 ptr->r.record.p.frmask = fr_mask;
1902 return ptr;
1903}
1904
1905static unw_rec_list *
1906output_gr_gr (mask, reg)
1907 unsigned int mask;
1908 unsigned int reg;
1909{
1910 unw_rec_list *ptr = alloc_record (gr_gr);
1911 ptr->r.record.p.grmask = mask;
1912 ptr->r.record.p.gr = reg;
1913 return ptr;
1914}
1915
1916static unw_rec_list *
1917output_gr_mem (mask)
1918 unsigned int mask;
1919{
1920 unw_rec_list *ptr = alloc_record (gr_mem);
1921 ptr->r.record.p.rmask = mask;
1922 return ptr;
1923}
1924
1925static unw_rec_list *
1926output_br_mem (unsigned int mask)
1927{
1928 unw_rec_list *ptr = alloc_record (br_mem);
1929 ptr->r.record.p.brmask = mask;
1930 return ptr;
1931}
1932
1933static unw_rec_list *
1934output_br_gr (save_mask, reg)
1935 unsigned int save_mask;
1936 unsigned int reg;
1937{
1938 unw_rec_list *ptr = alloc_record (br_gr);
1939 ptr->r.record.p.brmask = save_mask;
1940 ptr->r.record.p.gr = reg;
1941 return ptr;
1942}
1943
1944static unw_rec_list *
1945output_spill_base (offset)
1946 unsigned int offset;
1947{
1948 unw_rec_list *ptr = alloc_record (spill_base);
542d6675 1949 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
1950 return ptr;
1951}
1952
1953static unw_rec_list *
1954output_unat_when ()
1955{
1956 unw_rec_list *ptr = alloc_record (unat_when);
1957 return ptr;
1958}
1959
1960static unw_rec_list *
1961output_unat_gr (gr)
1962 unsigned int gr;
1963{
1964 unw_rec_list *ptr = alloc_record (unat_gr);
1965 ptr->r.record.p.gr = gr;
1966 return ptr;
1967}
1968
1969static unw_rec_list *
1970output_unat_psprel (offset)
1971 unsigned int offset;
1972{
1973 unw_rec_list *ptr = alloc_record (unat_psprel);
542d6675 1974 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
1975 return ptr;
1976}
1977
1978static unw_rec_list *
1979output_unat_sprel (offset)
1980 unsigned int offset;
1981{
1982 unw_rec_list *ptr = alloc_record (unat_sprel);
542d6675 1983 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
1984 return ptr;
1985}
1986
1987static unw_rec_list *
1988output_lc_when ()
1989{
1990 unw_rec_list *ptr = alloc_record (lc_when);
1991 return ptr;
1992}
1993
1994static unw_rec_list *
1995output_lc_gr (gr)
1996 unsigned int gr;
1997{
1998 unw_rec_list *ptr = alloc_record (lc_gr);
1999 ptr->r.record.p.gr = gr;
2000 return ptr;
2001}
2002
2003static unw_rec_list *
2004output_lc_psprel (offset)
2005 unsigned int offset;
2006{
2007 unw_rec_list *ptr = alloc_record (lc_psprel);
542d6675 2008 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
2009 return ptr;
2010}
2011
2012static unw_rec_list *
2013output_lc_sprel (offset)
2014 unsigned int offset;
2015{
2016 unw_rec_list *ptr = alloc_record (lc_sprel);
542d6675 2017 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
2018 return ptr;
2019}
2020
2021static unw_rec_list *
2022output_fpsr_when ()
2023{
2024 unw_rec_list *ptr = alloc_record (fpsr_when);
2025 return ptr;
2026}
2027
2028static unw_rec_list *
2029output_fpsr_gr (gr)
2030 unsigned int gr;
2031{
2032 unw_rec_list *ptr = alloc_record (fpsr_gr);
2033 ptr->r.record.p.gr = gr;
2034 return ptr;
2035}
2036
2037static unw_rec_list *
2038output_fpsr_psprel (offset)
2039 unsigned int offset;
2040{
2041 unw_rec_list *ptr = alloc_record (fpsr_psprel);
542d6675 2042 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
2043 return ptr;
2044}
2045
2046static unw_rec_list *
2047output_fpsr_sprel (offset)
2048 unsigned int offset;
2049{
2050 unw_rec_list *ptr = alloc_record (fpsr_sprel);
542d6675 2051 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
2052 return ptr;
2053}
2054
2055static unw_rec_list *
2056output_priunat_when_gr ()
2057{
2058 unw_rec_list *ptr = alloc_record (priunat_when_gr);
2059 return ptr;
2060}
2061
2062static unw_rec_list *
2063output_priunat_when_mem ()
2064{
2065 unw_rec_list *ptr = alloc_record (priunat_when_mem);
2066 return ptr;
2067}
2068
2069static unw_rec_list *
2070output_priunat_gr (gr)
2071 unsigned int gr;
2072{
2073 unw_rec_list *ptr = alloc_record (priunat_gr);
2074 ptr->r.record.p.gr = gr;
2075 return ptr;
2076}
2077
2078static unw_rec_list *
2079output_priunat_psprel (offset)
2080 unsigned int offset;
2081{
2082 unw_rec_list *ptr = alloc_record (priunat_psprel);
542d6675 2083 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
2084 return ptr;
2085}
2086
2087static unw_rec_list *
2088output_priunat_sprel (offset)
2089 unsigned int offset;
2090{
2091 unw_rec_list *ptr = alloc_record (priunat_sprel);
542d6675 2092 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
2093 return ptr;
2094}
2095
2096static unw_rec_list *
2097output_bsp_when ()
2098{
2099 unw_rec_list *ptr = alloc_record (bsp_when);
2100 return ptr;
2101}
2102
2103static unw_rec_list *
2104output_bsp_gr (gr)
2105 unsigned int gr;
2106{
2107 unw_rec_list *ptr = alloc_record (bsp_gr);
2108 ptr->r.record.p.gr = gr;
2109 return ptr;
2110}
2111
2112static unw_rec_list *
2113output_bsp_psprel (offset)
2114 unsigned int offset;
2115{
2116 unw_rec_list *ptr = alloc_record (bsp_psprel);
542d6675 2117 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
2118 return ptr;
2119}
2120
2121static unw_rec_list *
2122output_bsp_sprel (offset)
2123 unsigned int offset;
2124{
2125 unw_rec_list *ptr = alloc_record (bsp_sprel);
542d6675 2126 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
2127 return ptr;
2128}
2129
2130static unw_rec_list *
2131output_bspstore_when ()
2132{
2133 unw_rec_list *ptr = alloc_record (bspstore_when);
2134 return ptr;
2135}
2136
2137static unw_rec_list *
2138output_bspstore_gr (gr)
2139 unsigned int gr;
2140{
2141 unw_rec_list *ptr = alloc_record (bspstore_gr);
2142 ptr->r.record.p.gr = gr;
2143 return ptr;
2144}
2145
2146static unw_rec_list *
2147output_bspstore_psprel (offset)
2148 unsigned int offset;
2149{
2150 unw_rec_list *ptr = alloc_record (bspstore_psprel);
542d6675 2151 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
2152 return ptr;
2153}
2154
2155static unw_rec_list *
2156output_bspstore_sprel (offset)
2157 unsigned int offset;
2158{
2159 unw_rec_list *ptr = alloc_record (bspstore_sprel);
542d6675 2160 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
2161 return ptr;
2162}
2163
2164static unw_rec_list *
2165output_rnat_when ()
2166{
2167 unw_rec_list *ptr = alloc_record (rnat_when);
2168 return ptr;
2169}
2170
2171static unw_rec_list *
2172output_rnat_gr (gr)
2173 unsigned int gr;
2174{
2175 unw_rec_list *ptr = alloc_record (rnat_gr);
2176 ptr->r.record.p.gr = gr;
2177 return ptr;
2178}
2179
2180static unw_rec_list *
2181output_rnat_psprel (offset)
2182 unsigned int offset;
2183{
2184 unw_rec_list *ptr = alloc_record (rnat_psprel);
542d6675 2185 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW
2186 return ptr;
2187}
2188
2189static unw_rec_list *
2190output_rnat_sprel (offset)
2191 unsigned int offset;
2192{
2193 unw_rec_list *ptr = alloc_record (rnat_sprel);
542d6675 2194 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW
2195 return ptr;
2196}
2197
2198static unw_rec_list *
e0c9811a
JW
2199output_unwabi (abi, context)
2200 unsigned long abi;
2201 unsigned long context;
800eeca4 2202{
e0c9811a
JW
2203 unw_rec_list *ptr = alloc_record (unwabi);
2204 ptr->r.record.p.abi = abi;
2205 ptr->r.record.p.context = context;
800eeca4
JW
2206 return ptr;
2207}
2208
2209static unw_rec_list *
e0c9811a 2210output_epilogue (unsigned long ecount)
800eeca4 2211{
e0c9811a
JW
2212 unw_rec_list *ptr = alloc_record (epilogue);
2213 ptr->r.record.b.ecount = ecount;
800eeca4
JW
2214 return ptr;
2215}
2216
2217static unw_rec_list *
e0c9811a 2218output_label_state (unsigned long label)
800eeca4 2219{
e0c9811a
JW
2220 unw_rec_list *ptr = alloc_record (label_state);
2221 ptr->r.record.b.label = label;
800eeca4
JW
2222 return ptr;
2223}
2224
2225static unw_rec_list *
e0c9811a
JW
2226output_copy_state (unsigned long label)
2227{
2228 unw_rec_list *ptr = alloc_record (copy_state);
2229 ptr->r.record.b.label = label;
2230 return ptr;
2231}
2232
2233static unw_rec_list *
2234output_spill_psprel (ab, reg, offset)
2235 unsigned int ab;
800eeca4
JW
2236 unsigned int reg;
2237 unsigned int offset;
2238{
2239 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2240 ptr->r.record.x.ab = ab;
800eeca4 2241 ptr->r.record.x.reg = reg;
542d6675 2242 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW
2243 return ptr;
2244}
2245
2246static unw_rec_list *
e0c9811a
JW
2247output_spill_sprel (ab, reg, offset)
2248 unsigned int ab;
800eeca4
JW
2249 unsigned int reg;
2250 unsigned int offset;
2251{
2252 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2253 ptr->r.record.x.ab = ab;
800eeca4 2254 ptr->r.record.x.reg = reg;
542d6675 2255 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW
2256 return ptr;
2257}
2258
2259static unw_rec_list *
e0c9811a
JW
2260output_spill_psprel_p (ab, reg, offset, predicate)
2261 unsigned int ab;
800eeca4
JW
2262 unsigned int reg;
2263 unsigned int offset;
2264 unsigned int predicate;
2265{
2266 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2267 ptr->r.record.x.ab = ab;
800eeca4 2268 ptr->r.record.x.reg = reg;
542d6675 2269 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW
2270 ptr->r.record.x.qp = predicate;
2271 return ptr;
2272}
2273
2274static unw_rec_list *
e0c9811a
JW
2275output_spill_sprel_p (ab, reg, offset, predicate)
2276 unsigned int ab;
800eeca4
JW
2277 unsigned int reg;
2278 unsigned int offset;
2279 unsigned int predicate;
2280{
2281 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2282 ptr->r.record.x.ab = ab;
800eeca4 2283 ptr->r.record.x.reg = reg;
542d6675 2284 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW
2285 ptr->r.record.x.qp = predicate;
2286 return ptr;
2287}
2288
2289static unw_rec_list *
e0c9811a
JW
2290output_spill_reg (ab, reg, targ_reg, xy)
2291 unsigned int ab;
800eeca4
JW
2292 unsigned int reg;
2293 unsigned int targ_reg;
2294 unsigned int xy;
2295{
2296 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2297 ptr->r.record.x.ab = ab;
800eeca4
JW
2298 ptr->r.record.x.reg = reg;
2299 ptr->r.record.x.treg = targ_reg;
2300 ptr->r.record.x.xy = xy;
2301 return ptr;
2302}
2303
2304static unw_rec_list *
e0c9811a
JW
2305output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2306 unsigned int ab;
800eeca4
JW
2307 unsigned int reg;
2308 unsigned int targ_reg;
2309 unsigned int xy;
2310 unsigned int predicate;
2311{
2312 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2313 ptr->r.record.x.ab = ab;
800eeca4
JW
2314 ptr->r.record.x.reg = reg;
2315 ptr->r.record.x.treg = targ_reg;
2316 ptr->r.record.x.xy = xy;
2317 ptr->r.record.x.qp = predicate;
2318 return ptr;
2319}
2320
197865e8 2321/* Given a unw_rec_list process the correct format with the
800eeca4 2322 specified function. */
542d6675 2323
800eeca4
JW
2324static void
2325process_one_record (ptr, f)
2326 unw_rec_list *ptr;
2327 vbyte_func f;
2328{
e0c9811a
JW
2329 unsigned long fr_mask, gr_mask;
2330
197865e8 2331 switch (ptr->r.type)
800eeca4 2332 {
542d6675
KH
2333 case gr_mem:
2334 case fr_mem:
2335 case br_mem:
2336 case frgr_mem:
2337 /* These are taken care of by prologue/prologue_gr. */
2338 break;
e0c9811a 2339
542d6675
KH
2340 case prologue_gr:
2341 case prologue:
2342 if (ptr->r.type == prologue_gr)
2343 output_R2_format (f, ptr->r.record.r.grmask,
2344 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2345 else
800eeca4 2346 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
542d6675
KH
2347
2348 /* Output descriptor(s) for union of register spills (if any). */
2349 gr_mask = ptr->r.record.r.mask.gr_mem;
2350 fr_mask = ptr->r.record.r.mask.fr_mem;
2351 if (fr_mask)
2352 {
2353 if ((fr_mask & ~0xfUL) == 0)
2354 output_P6_format (f, fr_mem, fr_mask);
2355 else
2356 {
2357 output_P5_format (f, gr_mask, fr_mask);
2358 gr_mask = 0;
2359 }
2360 }
2361 if (gr_mask)
2362 output_P6_format (f, gr_mem, gr_mask);
2363 if (ptr->r.record.r.mask.br_mem)
2364 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2365
2366 /* output imask descriptor if necessary: */
2367 if (ptr->r.record.r.mask.i)
2368 output_P4_format (f, ptr->r.record.r.mask.i,
2369 ptr->r.record.r.imask_size);
2370 break;
2371
2372 case body:
2373 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2374 break;
2375 case mem_stack_f:
2376 case mem_stack_v:
2377 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2378 ptr->r.record.p.size);
2379 break;
2380 case psp_gr:
2381 case rp_gr:
2382 case pfs_gr:
2383 case preds_gr:
2384 case unat_gr:
2385 case lc_gr:
2386 case fpsr_gr:
2387 case priunat_gr:
2388 case bsp_gr:
2389 case bspstore_gr:
2390 case rnat_gr:
2391 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2392 break;
2393 case rp_br:
2394 output_P3_format (f, rp_br, ptr->r.record.p.br);
2395 break;
2396 case psp_sprel:
2397 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2398 break;
2399 case rp_when:
2400 case pfs_when:
2401 case preds_when:
2402 case unat_when:
2403 case lc_when:
2404 case fpsr_when:
2405 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2406 break;
2407 case rp_psprel:
2408 case pfs_psprel:
2409 case preds_psprel:
2410 case unat_psprel:
2411 case lc_psprel:
2412 case fpsr_psprel:
2413 case spill_base:
2414 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2415 break;
2416 case rp_sprel:
2417 case pfs_sprel:
2418 case preds_sprel:
2419 case unat_sprel:
2420 case lc_sprel:
2421 case fpsr_sprel:
2422 case priunat_sprel:
2423 case bsp_sprel:
2424 case bspstore_sprel:
2425 case rnat_sprel:
2426 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2427 break;
2428 case gr_gr:
2429 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2430 break;
2431 case br_gr:
2432 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2433 break;
2434 case spill_mask:
2435 as_bad ("spill_mask record unimplemented.");
2436 break;
2437 case priunat_when_gr:
2438 case priunat_when_mem:
2439 case bsp_when:
2440 case bspstore_when:
2441 case rnat_when:
2442 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2443 break;
2444 case priunat_psprel:
2445 case bsp_psprel:
2446 case bspstore_psprel:
2447 case rnat_psprel:
2448 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2449 break;
2450 case unwabi:
2451 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2452 break;
2453 case epilogue:
2454 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2455 break;
2456 case label_state:
2457 case copy_state:
2458 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2459 break;
2460 case spill_psprel:
2461 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2462 ptr->r.record.x.reg, ptr->r.record.x.t,
2463 ptr->r.record.x.pspoff);
2464 break;
2465 case spill_sprel:
2466 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2467 ptr->r.record.x.reg, ptr->r.record.x.t,
2468 ptr->r.record.x.spoff);
2469 break;
2470 case spill_reg:
2471 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2472 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2473 ptr->r.record.x.treg, ptr->r.record.x.t);
2474 break;
2475 case spill_psprel_p:
2476 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2477 ptr->r.record.x.ab, ptr->r.record.x.reg,
2478 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2479 break;
2480 case spill_sprel_p:
2481 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2482 ptr->r.record.x.ab, ptr->r.record.x.reg,
2483 ptr->r.record.x.t, ptr->r.record.x.spoff);
2484 break;
2485 case spill_reg_p:
2486 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2487 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2488 ptr->r.record.x.xy, ptr->r.record.x.treg,
2489 ptr->r.record.x.t);
2490 break;
2491 default:
2492 as_bad ("record_type_not_valid");
2493 break;
800eeca4
JW
2494 }
2495}
2496
197865e8 2497/* Given a unw_rec_list list, process all the records with
800eeca4
JW
2498 the specified function. */
2499static void
2500process_unw_records (list, f)
2501 unw_rec_list *list;
2502 vbyte_func f;
2503{
2504 unw_rec_list *ptr;
2505 for (ptr = list; ptr; ptr = ptr->next)
2506 process_one_record (ptr, f);
2507}
2508
2509/* Determine the size of a record list in bytes. */
2510static int
2511calc_record_size (list)
2512 unw_rec_list *list;
2513{
2514 vbyte_count = 0;
2515 process_unw_records (list, count_output);
2516 return vbyte_count;
2517}
2518
e0c9811a
JW
2519/* Update IMASK bitmask to reflect the fact that one or more registers
2520 of type TYPE are saved starting at instruction with index T. If N
2521 bits are set in REGMASK, it is assumed that instructions T through
2522 T+N-1 save these registers.
2523
2524 TYPE values:
2525 0: no save
2526 1: instruction saves next fp reg
2527 2: instruction saves next general reg
2528 3: instruction saves next branch reg */
2529static void
2530set_imask (region, regmask, t, type)
2531 unw_rec_list *region;
2532 unsigned long regmask;
2533 unsigned long t;
2534 unsigned int type;
2535{
2536 unsigned char *imask;
2537 unsigned long imask_size;
2538 unsigned int i;
2539 int pos;
2540
2541 imask = region->r.record.r.mask.i;
2542 imask_size = region->r.record.r.imask_size;
2543 if (!imask)
2544 {
542d6675 2545 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
e0c9811a
JW
2546 imask = xmalloc (imask_size);
2547 memset (imask, 0, imask_size);
2548
2549 region->r.record.r.imask_size = imask_size;
2550 region->r.record.r.mask.i = imask;
2551 }
2552
542d6675
KH
2553 i = (t / 4) + 1;
2554 pos = 2 * (3 - t % 4);
e0c9811a
JW
2555 while (regmask)
2556 {
2557 if (i >= imask_size)
2558 {
2559 as_bad ("Ignoring attempt to spill beyond end of region");
2560 return;
2561 }
2562
2563 imask[i] |= (type & 0x3) << pos;
197865e8 2564
e0c9811a
JW
2565 regmask &= (regmask - 1);
2566 pos -= 2;
2567 if (pos < 0)
2568 {
2569 pos = 0;
2570 ++i;
2571 }
2572 }
2573}
2574
2575static int
2576count_bits (unsigned long mask)
2577{
2578 int n = 0;
2579
2580 while (mask)
2581 {
2582 mask &= mask - 1;
2583 ++n;
2584 }
2585 return n;
2586}
2587
f5a30c2e
JW
2588/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2589 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2590 containing FIRST_ADDR. */
2591
e0c9811a 2592unsigned long
f5a30c2e
JW
2593slot_index (slot_addr, slot_frag, first_addr, first_frag)
2594 unsigned long slot_addr;
2595 fragS *slot_frag;
2596 unsigned long first_addr;
2597 fragS *first_frag;
e0c9811a 2598{
f5a30c2e
JW
2599 unsigned long index = 0;
2600
2601 /* First time we are called, the initial address and frag are invalid. */
2602 if (first_addr == 0)
2603 return 0;
2604
2605 /* If the two addresses are in different frags, then we need to add in
2606 the remaining size of this frag, and then the entire size of intermediate
2607 frags. */
2608 while (slot_frag != first_frag)
2609 {
2610 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2611
2612 /* Add in the full size of the frag converted to instruction slots. */
2613 index += 3 * (first_frag->fr_fix >> 4);
2614 /* Subtract away the initial part before first_addr. */
2615 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2616 + ((first_addr & 0x3) - (start_addr & 0x3)));
e0c9811a 2617
f5a30c2e
JW
2618 /* Move to the beginning of the next frag. */
2619 first_frag = first_frag->fr_next;
2620 first_addr = (unsigned long) &first_frag->fr_literal;
2621 }
2622
2623 /* Add in the used part of the last frag. */
2624 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2625 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2626 return index;
2627}
4a1805b1 2628
91a2ae2a
RH
2629/* Optimize unwind record directives. */
2630
2631static unw_rec_list *
2632optimize_unw_records (list)
2633 unw_rec_list *list;
2634{
2635 if (!list)
2636 return NULL;
2637
2638 /* If the only unwind record is ".prologue" or ".prologue" followed
2639 by ".body", then we can optimize the unwind directives away. */
2640 if (list->r.type == prologue
2641 && (list->next == NULL
2642 || (list->next->r.type == body && list->next->next == NULL)))
2643 return NULL;
2644
2645 return list;
2646}
2647
800eeca4
JW
2648/* Given a complete record list, process any records which have
2649 unresolved fields, (ie length counts for a prologue). After
197865e8 2650 this has been run, all neccessary information should be available
800eeca4 2651 within each record to generate an image. */
542d6675 2652
800eeca4
JW
2653static void
2654fixup_unw_records (list)
2655 unw_rec_list *list;
2656{
e0c9811a
JW
2657 unw_rec_list *ptr, *region = 0;
2658 unsigned long first_addr = 0, rlen = 0, t;
f5a30c2e 2659 fragS *first_frag = 0;
e0c9811a 2660
800eeca4
JW
2661 for (ptr = list; ptr; ptr = ptr->next)
2662 {
2663 if (ptr->slot_number == SLOT_NUM_NOT_SET)
542d6675 2664 as_bad (" Insn slot not set in unwind record.");
f5a30c2e
JW
2665 t = slot_index (ptr->slot_number, ptr->slot_frag,
2666 first_addr, first_frag);
800eeca4
JW
2667 switch (ptr->r.type)
2668 {
542d6675
KH
2669 case prologue:
2670 case prologue_gr:
2671 case body:
2672 {
2673 unw_rec_list *last;
2674 int size, dir_len = 0;
2675 unsigned long last_addr;
f5a30c2e 2676 fragS *last_frag;
542d6675
KH
2677
2678 first_addr = ptr->slot_number;
f5a30c2e 2679 first_frag = ptr->slot_frag;
542d6675
KH
2680 ptr->slot_number = 0;
2681 /* Find either the next body/prologue start, or the end of
2682 the list, and determine the size of the region. */
2683 last_addr = unwind.next_slot_number;
f5a30c2e 2684 last_frag = unwind.next_slot_frag;
542d6675
KH
2685 for (last = ptr->next; last != NULL; last = last->next)
2686 if (last->r.type == prologue || last->r.type == prologue_gr
2687 || last->r.type == body)
2688 {
2689 last_addr = last->slot_number;
f5a30c2e 2690 last_frag = last->slot_frag;
542d6675
KH
2691 break;
2692 }
2693 else if (!last->next)
2694 {
2695 /* In the absence of an explicit .body directive,
2696 the prologue ends after the last instruction
2697 covered by an unwind directive. */
2698 if (ptr->r.type != body)
2699 {
2700 last_addr = last->slot_number;
f5a30c2e 2701 last_frag = last->slot_frag;
542d6675
KH
2702 switch (last->r.type)
2703 {
2704 case frgr_mem:
2705 dir_len = (count_bits (last->r.record.p.frmask)
2706 + count_bits (last->r.record.p.grmask));
2707 break;
2708 case fr_mem:
2709 case gr_mem:
2710 dir_len += count_bits (last->r.record.p.rmask);
2711 break;
2712 case br_mem:
2713 case br_gr:
2714 dir_len += count_bits (last->r.record.p.brmask);
2715 break;
2716 case gr_gr:
2717 dir_len += count_bits (last->r.record.p.grmask);
2718 break;
2719 default:
2720 dir_len = 1;
2721 break;
2722 }
2723 }
2724 break;
2725 }
f5a30c2e
JW
2726 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2727 + dir_len);
542d6675 2728 rlen = ptr->r.record.r.rlen = size;
1e16b528
AS
2729 if (ptr->r.type == body)
2730 /* End of region. */
2731 region = 0;
2732 else
2733 region = ptr;
e0c9811a 2734 break;
542d6675
KH
2735 }
2736 case epilogue:
2737 ptr->r.record.b.t = rlen - 1 - t;
2738 break;
e0c9811a 2739
542d6675
KH
2740 case mem_stack_f:
2741 case mem_stack_v:
2742 case rp_when:
2743 case pfs_when:
2744 case preds_when:
2745 case unat_when:
2746 case lc_when:
2747 case fpsr_when:
2748 case priunat_when_gr:
2749 case priunat_when_mem:
2750 case bsp_when:
2751 case bspstore_when:
2752 case rnat_when:
2753 ptr->r.record.p.t = t;
2754 break;
e0c9811a 2755
542d6675
KH
2756 case spill_reg:
2757 case spill_sprel:
2758 case spill_psprel:
2759 case spill_reg_p:
2760 case spill_sprel_p:
2761 case spill_psprel_p:
2762 ptr->r.record.x.t = t;
2763 break;
e0c9811a 2764
542d6675
KH
2765 case frgr_mem:
2766 if (!region)
2767 {
2768 as_bad ("frgr_mem record before region record!\n");
2769 return;
2770 }
2771 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2772 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2773 set_imask (region, ptr->r.record.p.frmask, t, 1);
2774 set_imask (region, ptr->r.record.p.grmask, t, 2);
2775 break;
2776 case fr_mem:
2777 if (!region)
2778 {
2779 as_bad ("fr_mem record before region record!\n");
2780 return;
2781 }
2782 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2783 set_imask (region, ptr->r.record.p.rmask, t, 1);
2784 break;
2785 case gr_mem:
2786 if (!region)
2787 {
2788 as_bad ("gr_mem record before region record!\n");
2789 return;
2790 }
2791 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2792 set_imask (region, ptr->r.record.p.rmask, t, 2);
2793 break;
2794 case br_mem:
2795 if (!region)
2796 {
2797 as_bad ("br_mem record before region record!\n");
2798 return;
2799 }
2800 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2801 set_imask (region, ptr->r.record.p.brmask, t, 3);
2802 break;
e0c9811a 2803
542d6675
KH
2804 case gr_gr:
2805 if (!region)
2806 {
2807 as_bad ("gr_gr record before region record!\n");
2808 return;
2809 }
2810 set_imask (region, ptr->r.record.p.grmask, t, 2);
2811 break;
2812 case br_gr:
2813 if (!region)
2814 {
2815 as_bad ("br_gr record before region record!\n");
2816 return;
2817 }
2818 set_imask (region, ptr->r.record.p.brmask, t, 3);
2819 break;
e0c9811a 2820
542d6675
KH
2821 default:
2822 break;
800eeca4
JW
2823 }
2824 }
2825}
2826
557debba
JW
2827/* Helper routine for output_unw_records. Emits the header for the unwind
2828 info. */
2829
2830static int
07726851 2831setup_unwind_header (int size, unsigned char **mem)
557debba
JW
2832{
2833 int x, extra = 0;
1cd8ff38 2834 valueT flag_value;
557debba
JW
2835
2836 /* pad to pointer-size boundry. */
2837 x = size % md.pointer_size;
2838 if (x != 0)
2839 extra = md.pointer_size - x;
2840
40449e9f 2841 /* Add 8 for the header + a pointer for the
557debba
JW
2842 personality offset. */
2843 *mem = xmalloc (size + extra + 8 + md.pointer_size);
2844
2845 /* Clear the padding area and personality. */
40449e9f 2846 memset (*mem + 8 + size, 0, extra + md.pointer_size);
1cd8ff38 2847
557debba 2848 /* Initialize the header area. */
1cd8ff38
NC
2849 if (unwind.personality_routine)
2850 {
2851 if (md.flags & EF_IA_64_ABI64)
2852 flag_value = (bfd_vma) 3 << 32;
2853 else
2854 /* 32-bit unwind info block. */
2855 flag_value = (bfd_vma) 0x1003 << 32;
2856 }
2857 else
2858 flag_value = 0;
557debba 2859
1cd8ff38
NC
2860 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */
2861 | flag_value /* U & E handler flags. */
2862 | ((size + extra) / md.pointer_size)), /* Length. */
557debba
JW
2863 8);
2864
2865 return extra;
2866}
2867
800eeca4
JW
2868/* Generate an unwind image from a record list. Returns the number of
2869 bytes in the resulting image. The memory image itselof is returned
2870 in the 'ptr' parameter. */
2871static int
2872output_unw_records (list, ptr)
2873 unw_rec_list *list;
2874 void **ptr;
2875{
557debba 2876 int size, extra;
800eeca4
JW
2877 unsigned char *mem;
2878
91a2ae2a
RH
2879 *ptr = NULL;
2880
2881 list = optimize_unw_records (list);
800eeca4
JW
2882 fixup_unw_records (list);
2883 size = calc_record_size (list);
2884
91a2ae2a
RH
2885 if (size > 0 || unwind.force_unwind_entry)
2886 {
2887 unwind.force_unwind_entry = 0;
07726851 2888 extra = setup_unwind_header (size, &mem);
800eeca4 2889
91a2ae2a 2890 vbyte_mem_ptr = mem + 8;
91a2ae2a
RH
2891 process_unw_records (list, output_vbyte_mem);
2892
2893 *ptr = mem;
2894
557debba 2895 size += extra + 8 + md.pointer_size;
91a2ae2a
RH
2896 }
2897 return size;
800eeca4
JW
2898}
2899
e0c9811a
JW
2900static int
2901convert_expr_to_ab_reg (e, ab, regp)
2902 expressionS *e;
2903 unsigned int *ab;
2904 unsigned int *regp;
2905{
2906 unsigned int reg;
2907
2908 if (e->X_op != O_register)
2909 return 0;
2910
2911 reg = e->X_add_number;
2434f565 2912 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
e0c9811a
JW
2913 {
2914 *ab = 0;
2915 *regp = reg - REG_GR;
2916 }
2434f565
JW
2917 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2918 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
e0c9811a
JW
2919 {
2920 *ab = 1;
2921 *regp = reg - REG_FR;
2922 }
2434f565 2923 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
e0c9811a
JW
2924 {
2925 *ab = 2;
2926 *regp = reg - REG_BR;
2927 }
2928 else
2929 {
2930 *ab = 3;
2931 switch (reg)
2932 {
2933 case REG_PR: *regp = 0; break;
2934 case REG_PSP: *regp = 1; break;
2935 case REG_PRIUNAT: *regp = 2; break;
2936 case REG_BR + 0: *regp = 3; break;
2937 case REG_AR + AR_BSP: *regp = 4; break;
2938 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2939 case REG_AR + AR_RNAT: *regp = 6; break;
2940 case REG_AR + AR_UNAT: *regp = 7; break;
2941 case REG_AR + AR_FPSR: *regp = 8; break;
2942 case REG_AR + AR_PFS: *regp = 9; break;
2943 case REG_AR + AR_LC: *regp = 10; break;
2944
2945 default:
2946 return 0;
2947 }
2948 }
2949 return 1;
197865e8 2950}
e0c9811a
JW
2951
2952static int
2953convert_expr_to_xy_reg (e, xy, regp)
2954 expressionS *e;
2955 unsigned int *xy;
2956 unsigned int *regp;
2957{
2958 unsigned int reg;
2959
2960 if (e->X_op != O_register)
2961 return 0;
2962
2963 reg = e->X_add_number;
2964
2434f565 2965 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
e0c9811a
JW
2966 {
2967 *xy = 0;
2968 *regp = reg - REG_GR;
2969 }
2434f565 2970 else if (reg >= REG_FR && reg <= (REG_FR + 127))
e0c9811a
JW
2971 {
2972 *xy = 1;
2973 *regp = reg - REG_FR;
2974 }
2434f565 2975 else if (reg >= REG_BR && reg <= (REG_BR + 7))
e0c9811a
JW
2976 {
2977 *xy = 2;
2978 *regp = reg - REG_BR;
2979 }
2980 else
2981 return -1;
2982 return 1;
197865e8 2983}
e0c9811a 2984
800eeca4
JW
2985static void
2986dot_radix (dummy)
2434f565 2987 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
2988{
2989 int radix;
2990
2991 SKIP_WHITESPACE ();
2992 radix = *input_line_pointer++;
2993
2994 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2995 {
2996 as_bad ("Radix `%c' unsupported", *input_line_pointer);
542d6675 2997 ignore_rest_of_line ();
800eeca4
JW
2998 return;
2999 }
3000}
3001
3002/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
3003static void
3004dot_special_section (which)
3005 int which;
3006{
3007 set_section ((char *) special_section_name[which]);
3008}
3009
3010static void
3011add_unwind_entry (ptr)
3012 unw_rec_list *ptr;
3013{
e0c9811a
JW
3014 if (unwind.tail)
3015 unwind.tail->next = ptr;
800eeca4 3016 else
e0c9811a
JW
3017 unwind.list = ptr;
3018 unwind.tail = ptr;
800eeca4
JW
3019
3020 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW
3021 if (unwind.current_entry == NULL)
3022 unwind.current_entry = ptr;
800eeca4
JW
3023}
3024
197865e8 3025static void
800eeca4 3026dot_fframe (dummy)
2434f565 3027 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3028{
3029 expressionS e;
e0c9811a 3030
800eeca4 3031 parse_operand (&e);
197865e8 3032
800eeca4
JW
3033 if (e.X_op != O_constant)
3034 as_bad ("Operand to .fframe must be a constant");
3035 else
e0c9811a
JW
3036 add_unwind_entry (output_mem_stack_f (e.X_add_number));
3037}
3038
197865e8 3039static void
e0c9811a 3040dot_vframe (dummy)
2434f565 3041 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3042{
3043 expressionS e;
3044 unsigned reg;
3045
3046 parse_operand (&e);
3047 reg = e.X_add_number - REG_GR;
3048 if (e.X_op == O_register && reg < 128)
800eeca4 3049 {
e0c9811a 3050 add_unwind_entry (output_mem_stack_v ());
30d25259
RH
3051 if (! (unwind.prologue_mask & 2))
3052 add_unwind_entry (output_psp_gr (reg));
800eeca4 3053 }
e0c9811a
JW
3054 else
3055 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW
3056}
3057
197865e8 3058static void
e0c9811a 3059dot_vframesp (dummy)
2434f565 3060 int dummy ATTRIBUTE_UNUSED;
800eeca4 3061{
e0c9811a
JW
3062 expressionS e;
3063
3064 parse_operand (&e);
3065 if (e.X_op == O_constant)
3066 {
3067 add_unwind_entry (output_mem_stack_v ());
3068 add_unwind_entry (output_psp_sprel (e.X_add_number));
3069 }
3070 else
69906a9b 3071 as_bad ("Operand to .vframesp must be a constant (sp-relative offset)");
e0c9811a
JW
3072}
3073
197865e8 3074static void
e0c9811a 3075dot_vframepsp (dummy)
2434f565 3076 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3077{
3078 expressionS e;
3079
3080 parse_operand (&e);
3081 if (e.X_op == O_constant)
3082 {
3083 add_unwind_entry (output_mem_stack_v ());
3084 add_unwind_entry (output_psp_sprel (e.X_add_number));
3085 }
3086 else
69906a9b 3087 as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)");
800eeca4
JW
3088}
3089
197865e8 3090static void
800eeca4 3091dot_save (dummy)
2434f565 3092 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3093{
3094 expressionS e1, e2;
3095 int sep;
3096 int reg1, reg2;
3097
3098 sep = parse_operand (&e1);
3099 if (sep != ',')
3100 as_bad ("No second operand to .save");
3101 sep = parse_operand (&e2);
3102
e0c9811a 3103 reg1 = e1.X_add_number;
800eeca4 3104 reg2 = e2.X_add_number - REG_GR;
197865e8 3105
800eeca4 3106 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3107 if (e1.X_op == O_register)
800eeca4 3108 {
542d6675 3109 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
800eeca4
JW
3110 {
3111 switch (reg1)
3112 {
542d6675
KH
3113 case REG_AR + AR_BSP:
3114 add_unwind_entry (output_bsp_when ());
3115 add_unwind_entry (output_bsp_gr (reg2));
3116 break;
3117 case REG_AR + AR_BSPSTORE:
3118 add_unwind_entry (output_bspstore_when ());
3119 add_unwind_entry (output_bspstore_gr (reg2));
3120 break;
3121 case REG_AR + AR_RNAT:
3122 add_unwind_entry (output_rnat_when ());
3123 add_unwind_entry (output_rnat_gr (reg2));
3124 break;
3125 case REG_AR + AR_UNAT:
3126 add_unwind_entry (output_unat_when ());
3127 add_unwind_entry (output_unat_gr (reg2));
3128 break;
3129 case REG_AR + AR_FPSR:
3130 add_unwind_entry (output_fpsr_when ());
3131 add_unwind_entry (output_fpsr_gr (reg2));
3132 break;
3133 case REG_AR + AR_PFS:
3134 add_unwind_entry (output_pfs_when ());
3135 if (! (unwind.prologue_mask & 4))
3136 add_unwind_entry (output_pfs_gr (reg2));
3137 break;
3138 case REG_AR + AR_LC:
3139 add_unwind_entry (output_lc_when ());
3140 add_unwind_entry (output_lc_gr (reg2));
3141 break;
3142 case REG_BR:
3143 add_unwind_entry (output_rp_when ());
3144 if (! (unwind.prologue_mask & 8))
3145 add_unwind_entry (output_rp_gr (reg2));
3146 break;
3147 case REG_PR:
3148 add_unwind_entry (output_preds_when ());
3149 if (! (unwind.prologue_mask & 1))
3150 add_unwind_entry (output_preds_gr (reg2));
3151 break;
3152 case REG_PRIUNAT:
3153 add_unwind_entry (output_priunat_when_gr ());
3154 add_unwind_entry (output_priunat_gr (reg2));
3155 break;
3156 default:
3157 as_bad ("First operand not a valid register");
800eeca4
JW
3158 }
3159 }
3160 else
3161 as_bad (" Second operand not a valid register");
3162 }
3163 else
e0c9811a 3164 as_bad ("First operand not a register");
800eeca4
JW
3165}
3166
197865e8 3167static void
800eeca4 3168dot_restore (dummy)
2434f565 3169 int dummy ATTRIBUTE_UNUSED;
800eeca4 3170{
e0c9811a 3171 expressionS e1, e2;
33d01f33 3172 unsigned long ecount; /* # of _additional_ regions to pop */
e0c9811a
JW
3173 int sep;
3174
3175 sep = parse_operand (&e1);
3176 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
3177 {
3178 as_bad ("First operand to .restore must be stack pointer (sp)");
3179 return;
3180 }
3181
3182 if (sep == ',')
3183 {
3184 parse_operand (&e2);
33d01f33 3185 if (e2.X_op != O_constant || e2.X_add_number < 0)
e0c9811a 3186 {
33d01f33 3187 as_bad ("Second operand to .restore must be a constant >= 0");
e0c9811a
JW
3188 return;
3189 }
33d01f33 3190 ecount = e2.X_add_number;
e0c9811a 3191 }
33d01f33
JW
3192 else
3193 ecount = unwind.prologue_count - 1;
6290819d
NC
3194
3195 if (ecount >= unwind.prologue_count)
3196 {
3197 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
3198 ecount + 1, unwind.prologue_count);
3199 return;
3200 }
3201
e0c9811a 3202 add_unwind_entry (output_epilogue (ecount));
33d01f33
JW
3203
3204 if (ecount < unwind.prologue_count)
3205 unwind.prologue_count -= ecount + 1;
3206 else
3207 unwind.prologue_count = 0;
e0c9811a
JW
3208}
3209
197865e8 3210static void
e0c9811a 3211dot_restorereg (dummy)
2434f565 3212 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3213{
3214 unsigned int ab, reg;
3215 expressionS e;
3216
3217 parse_operand (&e);
3218
3219 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
3220 {
3221 as_bad ("First operand to .restorereg must be a preserved register");
3222 return;
3223 }
3224 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3225}
3226
197865e8 3227static void
e0c9811a 3228dot_restorereg_p (dummy)
2434f565 3229 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3230{
3231 unsigned int qp, ab, reg;
3232 expressionS e1, e2;
3233 int sep;
3234
3235 sep = parse_operand (&e1);
3236 if (sep != ',')
3237 {
3238 as_bad ("No second operand to .restorereg.p");
3239 return;
3240 }
3241
3242 parse_operand (&e2);
3243
3244 qp = e1.X_add_number - REG_P;
3245 if (e1.X_op != O_register || qp > 63)
3246 {
3247 as_bad ("First operand to .restorereg.p must be a predicate");
3248 return;
3249 }
3250
3251 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3252 {
3253 as_bad ("Second operand to .restorereg.p must be a preserved register");
3254 return;
3255 }
3256 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW
3257}
3258
3259static int
91a2ae2a
RH
3260generate_unwind_image (text_name)
3261 const char *text_name;
800eeca4
JW
3262{
3263 int size;
3264 unsigned char *unw_rec;
800eeca4 3265
10850f29
JW
3266 /* Force out pending instructions, to make sure all unwind records have
3267 a valid slot_number field. */
3268 ia64_flush_insns ();
3269
800eeca4 3270 /* Generate the unwind record. */
150f24a2 3271 size = output_unw_records (unwind.list, (void **) &unw_rec);
557debba
JW
3272 if (size % md.pointer_size != 0)
3273 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size);
6290819d 3274
800eeca4
JW
3275 /* If there are unwind records, switch sections, and output the info. */
3276 if (size != 0)
3277 {
800eeca4 3278 unsigned char *where;
91a2ae2a 3279 char *sec_name;
800eeca4 3280 expressionS exp;
1cd8ff38 3281 bfd_reloc_code_real_type reloc;
91a2ae2a
RH
3282
3283 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
3284 set_section (sec_name);
3285 bfd_set_section_flags (stdoutput, now_seg,
3286 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
800eeca4 3287
557debba
JW
3288 /* Make sure the section has 4 byte alignment for ILP32 and
3289 8 byte alignment for LP64. */
3290 frag_align (md.pointer_size_shift, 0, 0);
3291 record_alignment (now_seg, md.pointer_size_shift);
5e7474a7 3292
800eeca4 3293 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 3294 unwind.info = expr_build_dot ();
800eeca4 3295
542d6675 3296 where = (unsigned char *) frag_more (size);
800eeca4
JW
3297
3298 /* Issue a label for this address, and keep track of it to put it
3299 in the unwind section. */
3300
3301 /* Copy the information from the unwind record into this section. The
3302 data is already in the correct byte order. */
3303 memcpy (where, unw_rec, size);
91a2ae2a 3304
800eeca4 3305 /* Add the personality address to the image. */
e0c9811a 3306 if (unwind.personality_routine != 0)
542d6675 3307 {
40449e9f 3308 exp.X_op = O_symbol;
e0c9811a 3309 exp.X_add_symbol = unwind.personality_routine;
800eeca4 3310 exp.X_add_number = 0;
1cd8ff38
NC
3311
3312 if (md.flags & EF_IA_64_BE)
3313 {
3314 if (md.flags & EF_IA_64_ABI64)
3315 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB;
3316 else
3317 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB;
3318 }
40449e9f 3319 else
1cd8ff38
NC
3320 {
3321 if (md.flags & EF_IA_64_ABI64)
3322 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB;
3323 else
3324 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB;
3325 }
3326
3327 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size,
40449e9f 3328 md.pointer_size, &exp, 0, reloc);
e0c9811a 3329 unwind.personality_routine = 0;
542d6675 3330 }
800eeca4
JW
3331 }
3332
e0c9811a 3333 free_list_records (unwind.list);
6290819d 3334 free_saved_prologue_counts ();
e0c9811a 3335 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW
3336
3337 return size;
3338}
3339
197865e8 3340static void
542d6675 3341dot_handlerdata (dummy)
2434f565 3342 int dummy ATTRIBUTE_UNUSED;
800eeca4 3343{
91a2ae2a
RH
3344 const char *text_name = segment_name (now_seg);
3345
3346 /* If text section name starts with ".text" (which it should),
3347 strip this prefix off. */
3348 if (strcmp (text_name, ".text") == 0)
3349 text_name = "";
3350
3351 unwind.force_unwind_entry = 1;
3352
3353 /* Remember which segment we're in so we can switch back after .endp */
3354 unwind.saved_text_seg = now_seg;
3355 unwind.saved_text_subseg = now_subseg;
3356
3357 /* Generate unwind info into unwind-info section and then leave that
3358 section as the currently active one so dataXX directives go into
3359 the language specific data area of the unwind info block. */
3360 generate_unwind_image (text_name);
e0c9811a 3361 demand_empty_rest_of_line ();
800eeca4
JW
3362}
3363
197865e8 3364static void
800eeca4 3365dot_unwentry (dummy)
2434f565 3366 int dummy ATTRIBUTE_UNUSED;
800eeca4 3367{
91a2ae2a 3368 unwind.force_unwind_entry = 1;
e0c9811a 3369 demand_empty_rest_of_line ();
800eeca4
JW
3370}
3371
197865e8 3372static void
800eeca4 3373dot_altrp (dummy)
2434f565 3374 int dummy ATTRIBUTE_UNUSED;
800eeca4 3375{
e0c9811a
JW
3376 expressionS e;
3377 unsigned reg;
3378
3379 parse_operand (&e);
3380 reg = e.X_add_number - REG_BR;
3381 if (e.X_op == O_register && reg < 8)
3382 add_unwind_entry (output_rp_br (reg));
3383 else
3384 as_bad ("First operand not a valid branch register");
800eeca4
JW
3385}
3386
197865e8 3387static void
e0c9811a
JW
3388dot_savemem (psprel)
3389 int psprel;
800eeca4
JW
3390{
3391 expressionS e1, e2;
3392 int sep;
3393 int reg1, val;
3394
3395 sep = parse_operand (&e1);
3396 if (sep != ',')
e0c9811a 3397 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW
3398 sep = parse_operand (&e2);
3399
e0c9811a 3400 reg1 = e1.X_add_number;
800eeca4 3401 val = e2.X_add_number;
197865e8 3402
800eeca4 3403 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3404 if (e1.X_op == O_register)
800eeca4
JW
3405 {
3406 if (e2.X_op == O_constant)
3407 {
3408 switch (reg1)
3409 {
542d6675
KH
3410 case REG_AR + AR_BSP:
3411 add_unwind_entry (output_bsp_when ());
3412 add_unwind_entry ((psprel
3413 ? output_bsp_psprel
3414 : output_bsp_sprel) (val));
3415 break;
3416 case REG_AR + AR_BSPSTORE:
3417 add_unwind_entry (output_bspstore_when ());
3418 add_unwind_entry ((psprel
3419 ? output_bspstore_psprel
3420 : output_bspstore_sprel) (val));
3421 break;
3422 case REG_AR + AR_RNAT:
3423 add_unwind_entry (output_rnat_when ());
3424 add_unwind_entry ((psprel
3425 ? output_rnat_psprel
3426 : output_rnat_sprel) (val));
3427 break;
3428 case REG_AR + AR_UNAT:
3429 add_unwind_entry (output_unat_when ());
3430 add_unwind_entry ((psprel
3431 ? output_unat_psprel
3432 : output_unat_sprel) (val));
3433 break;
3434 case REG_AR + AR_FPSR:
3435 add_unwind_entry (output_fpsr_when ());
3436 add_unwind_entry ((psprel
3437 ? output_fpsr_psprel
3438 : output_fpsr_sprel) (val));
3439 break;
3440 case REG_AR + AR_PFS:
3441 add_unwind_entry (output_pfs_when ());
3442 add_unwind_entry ((psprel
3443 ? output_pfs_psprel
3444 : output_pfs_sprel) (val));
3445 break;
3446 case REG_AR + AR_LC:
3447 add_unwind_entry (output_lc_when ());
3448 add_unwind_entry ((psprel
3449 ? output_lc_psprel
3450 : output_lc_sprel) (val));
3451 break;
3452 case REG_BR:
3453 add_unwind_entry (output_rp_when ());
3454 add_unwind_entry ((psprel
3455 ? output_rp_psprel
3456 : output_rp_sprel) (val));
3457 break;
3458 case REG_PR:
3459 add_unwind_entry (output_preds_when ());
3460 add_unwind_entry ((psprel
3461 ? output_preds_psprel
3462 : output_preds_sprel) (val));
3463 break;
3464 case REG_PRIUNAT:
3465 add_unwind_entry (output_priunat_when_mem ());
3466 add_unwind_entry ((psprel
3467 ? output_priunat_psprel
3468 : output_priunat_sprel) (val));
3469 break;
3470 default:
3471 as_bad ("First operand not a valid register");
800eeca4
JW
3472 }
3473 }
3474 else
3475 as_bad (" Second operand not a valid constant");
3476 }
3477 else
e0c9811a 3478 as_bad ("First operand not a register");
800eeca4
JW
3479}
3480
197865e8 3481static void
800eeca4 3482dot_saveg (dummy)
2434f565 3483 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3484{
3485 expressionS e1, e2;
3486 int sep;
3487 sep = parse_operand (&e1);
3488 if (sep == ',')
3489 parse_operand (&e2);
197865e8 3490
800eeca4
JW
3491 if (e1.X_op != O_constant)
3492 as_bad ("First operand to .save.g must be a constant.");
3493 else
3494 {
3495 int grmask = e1.X_add_number;
3496 if (sep != ',')
3497 add_unwind_entry (output_gr_mem (grmask));
3498 else
542d6675 3499 {
800eeca4 3500 int reg = e2.X_add_number - REG_GR;
542d6675 3501 if (e2.X_op == O_register && reg >= 0 && reg < 128)
800eeca4
JW
3502 add_unwind_entry (output_gr_gr (grmask, reg));
3503 else
3504 as_bad ("Second operand is an invalid register.");
3505 }
3506 }
3507}
3508
197865e8 3509static void
800eeca4 3510dot_savef (dummy)
2434f565 3511 int dummy ATTRIBUTE_UNUSED;
800eeca4 3512{
e0c9811a 3513 expressionS e1;
800eeca4
JW
3514 int sep;
3515 sep = parse_operand (&e1);
197865e8 3516
800eeca4
JW
3517 if (e1.X_op != O_constant)
3518 as_bad ("Operand to .save.f must be a constant.");
3519 else
e0c9811a 3520 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW
3521}
3522
197865e8 3523static void
800eeca4 3524dot_saveb (dummy)
2434f565 3525 int dummy ATTRIBUTE_UNUSED;
800eeca4 3526{
e0c9811a
JW
3527 expressionS e1, e2;
3528 unsigned int reg;
3529 unsigned char sep;
3530 int brmask;
3531
800eeca4 3532 sep = parse_operand (&e1);
800eeca4 3533 if (e1.X_op != O_constant)
800eeca4 3534 {
e0c9811a
JW
3535 as_bad ("First operand to .save.b must be a constant.");
3536 return;
800eeca4 3537 }
e0c9811a
JW
3538 brmask = e1.X_add_number;
3539
3540 if (sep == ',')
3541 {
3542 sep = parse_operand (&e2);
3543 reg = e2.X_add_number - REG_GR;
3544 if (e2.X_op != O_register || reg > 127)
3545 {
3546 as_bad ("Second operand to .save.b must be a general register.");
3547 return;
3548 }
3549 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3550 }
3551 else
3552 add_unwind_entry (output_br_mem (brmask));
3553
3554 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3555 ignore_rest_of_line ();
800eeca4
JW
3556}
3557
197865e8 3558static void
800eeca4 3559dot_savegf (dummy)
2434f565 3560 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3561{
3562 expressionS e1, e2;
3563 int sep;
3564 sep = parse_operand (&e1);
3565 if (sep == ',')
3566 parse_operand (&e2);
197865e8 3567
800eeca4
JW
3568 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3569 as_bad ("Both operands of .save.gf must be constants.");
3570 else
3571 {
3572 int grmask = e1.X_add_number;
3573 int frmask = e2.X_add_number;
3574 add_unwind_entry (output_frgr_mem (grmask, frmask));
3575 }
3576}
3577
197865e8 3578static void
800eeca4 3579dot_spill (dummy)
2434f565 3580 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3581{
3582 expressionS e;
e0c9811a
JW
3583 unsigned char sep;
3584
3585 sep = parse_operand (&e);
3586 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3587 ignore_rest_of_line ();
197865e8 3588
800eeca4
JW
3589 if (e.X_op != O_constant)
3590 as_bad ("Operand to .spill must be a constant");
3591 else
e0c9811a
JW
3592 add_unwind_entry (output_spill_base (e.X_add_number));
3593}
3594
3595static void
3596dot_spillreg (dummy)
2434f565 3597 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3598{
3599 int sep, ab, xy, reg, treg;
3600 expressionS e1, e2;
3601
3602 sep = parse_operand (&e1);
3603 if (sep != ',')
3604 {
3605 as_bad ("No second operand to .spillreg");
3606 return;
3607 }
3608
3609 parse_operand (&e2);
3610
3611 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3612 {
e0c9811a
JW
3613 as_bad ("First operand to .spillreg must be a preserved register");
3614 return;
800eeca4 3615 }
e0c9811a
JW
3616
3617 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3618 {
3619 as_bad ("Second operand to .spillreg must be a register");
3620 return;
3621 }
3622
3623 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3624}
3625
3626static void
3627dot_spillmem (psprel)
3628 int psprel;
3629{
3630 expressionS e1, e2;
3631 int sep, ab, reg;
3632
3633 sep = parse_operand (&e1);
3634 if (sep != ',')
3635 {
3636 as_bad ("Second operand missing");
3637 return;
3638 }
3639
3640 parse_operand (&e2);
3641
3642 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3643 {
3644 as_bad ("First operand to .spill%s must be a preserved register",
3645 psprel ? "psp" : "sp");
3646 return;
3647 }
3648
3649 if (e2.X_op != O_constant)
3650 {
3651 as_bad ("Second operand to .spill%s must be a constant",
3652 psprel ? "psp" : "sp");
3653 return;
3654 }
3655
3656 if (psprel)
3657 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3658 else
3659 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3660}
3661
3662static void
3663dot_spillreg_p (dummy)
2434f565 3664 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3665{
3666 int sep, ab, xy, reg, treg;
3667 expressionS e1, e2, e3;
3668 unsigned int qp;
3669
3670 sep = parse_operand (&e1);
3671 if (sep != ',')
3672 {
3673 as_bad ("No second and third operand to .spillreg.p");
3674 return;
3675 }
3676
3677 sep = parse_operand (&e2);
3678 if (sep != ',')
3679 {
3680 as_bad ("No third operand to .spillreg.p");
3681 return;
3682 }
3683
3684 parse_operand (&e3);
3685
3686 qp = e1.X_add_number - REG_P;
3687
3688 if (e1.X_op != O_register || qp > 63)
3689 {
3690 as_bad ("First operand to .spillreg.p must be a predicate");
3691 return;
3692 }
3693
3694 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3695 {
3696 as_bad ("Second operand to .spillreg.p must be a preserved register");
3697 return;
3698 }
3699
3700 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3701 {
3702 as_bad ("Third operand to .spillreg.p must be a register");
3703 return;
3704 }
3705
3706 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3707}
3708
3709static void
3710dot_spillmem_p (psprel)
3711 int psprel;
3712{
3713 expressionS e1, e2, e3;
3714 int sep, ab, reg;
3715 unsigned int qp;
3716
3717 sep = parse_operand (&e1);
3718 if (sep != ',')
3719 {
3720 as_bad ("Second operand missing");
3721 return;
3722 }
3723
3724 parse_operand (&e2);
3725 if (sep != ',')
3726 {
3727 as_bad ("Second operand missing");
3728 return;
3729 }
3730
3731 parse_operand (&e3);
3732
3733 qp = e1.X_add_number - REG_P;
3734 if (e1.X_op != O_register || qp > 63)
3735 {
3736 as_bad ("First operand to .spill%s_p must be a predicate",
3737 psprel ? "psp" : "sp");
3738 return;
3739 }
3740
3741 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3742 {
3743 as_bad ("Second operand to .spill%s_p must be a preserved register",
3744 psprel ? "psp" : "sp");
3745 return;
3746 }
3747
3748 if (e3.X_op != O_constant)
3749 {
3750 as_bad ("Third operand to .spill%s_p must be a constant",
3751 psprel ? "psp" : "sp");
3752 return;
3753 }
3754
3755 if (psprel)
fa7fda74 3756 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp));
e0c9811a 3757 else
fa7fda74 3758 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp));
e0c9811a
JW
3759}
3760
6290819d
NC
3761static unsigned int
3762get_saved_prologue_count (lbl)
3763 unsigned long lbl;
3764{
3765 label_prologue_count *lpc = unwind.saved_prologue_counts;
3766
3767 while (lpc != NULL && lpc->label_number != lbl)
3768 lpc = lpc->next;
3769
3770 if (lpc != NULL)
3771 return lpc->prologue_count;
3772
3773 as_bad ("Missing .label_state %ld", lbl);
3774 return 1;
3775}
3776
3777static void
3778save_prologue_count (lbl, count)
3779 unsigned long lbl;
3780 unsigned int count;
3781{
3782 label_prologue_count *lpc = unwind.saved_prologue_counts;
3783
3784 while (lpc != NULL && lpc->label_number != lbl)
3785 lpc = lpc->next;
3786
3787 if (lpc != NULL)
3788 lpc->prologue_count = count;
3789 else
3790 {
40449e9f 3791 label_prologue_count *new_lpc = xmalloc (sizeof (* new_lpc));
6290819d
NC
3792
3793 new_lpc->next = unwind.saved_prologue_counts;
3794 new_lpc->label_number = lbl;
3795 new_lpc->prologue_count = count;
3796 unwind.saved_prologue_counts = new_lpc;
3797 }
3798}
3799
3800static void
3801free_saved_prologue_counts ()
3802{
40449e9f
KH
3803 label_prologue_count *lpc = unwind.saved_prologue_counts;
3804 label_prologue_count *next;
6290819d
NC
3805
3806 while (lpc != NULL)
3807 {
3808 next = lpc->next;
3809 free (lpc);
3810 lpc = next;
3811 }
3812
3813 unwind.saved_prologue_counts = NULL;
3814}
3815
e0c9811a
JW
3816static void
3817dot_label_state (dummy)
2434f565 3818 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3819{
3820 expressionS e;
3821
3822 parse_operand (&e);
3823 if (e.X_op != O_constant)
3824 {
3825 as_bad ("Operand to .label_state must be a constant");
3826 return;
3827 }
3828 add_unwind_entry (output_label_state (e.X_add_number));
6290819d 3829 save_prologue_count (e.X_add_number, unwind.prologue_count);
e0c9811a
JW
3830}
3831
3832static void
3833dot_copy_state (dummy)
2434f565 3834 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW
3835{
3836 expressionS e;
3837
3838 parse_operand (&e);
3839 if (e.X_op != O_constant)
3840 {
3841 as_bad ("Operand to .copy_state must be a constant");
3842 return;
3843 }
3844 add_unwind_entry (output_copy_state (e.X_add_number));
6290819d 3845 unwind.prologue_count = get_saved_prologue_count (e.X_add_number);
800eeca4
JW
3846}
3847
197865e8 3848static void
800eeca4 3849dot_unwabi (dummy)
2434f565 3850 int dummy ATTRIBUTE_UNUSED;
800eeca4 3851{
e0c9811a
JW
3852 expressionS e1, e2;
3853 unsigned char sep;
3854
3855 sep = parse_operand (&e1);
3856 if (sep != ',')
3857 {
3858 as_bad ("Second operand to .unwabi missing");
3859 return;
3860 }
3861 sep = parse_operand (&e2);
3862 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3863 ignore_rest_of_line ();
3864
3865 if (e1.X_op != O_constant)
3866 {
3867 as_bad ("First operand to .unwabi must be a constant");
3868 return;
3869 }
3870
3871 if (e2.X_op != O_constant)
3872 {
3873 as_bad ("Second operand to .unwabi must be a constant");
3874 return;
3875 }
3876
3877 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW
3878}
3879
197865e8 3880static void
800eeca4 3881dot_personality (dummy)
2434f565 3882 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3883{
3884 char *name, *p, c;
3885 SKIP_WHITESPACE ();
3886 name = input_line_pointer;
3887 c = get_symbol_end ();
3888 p = input_line_pointer;
e0c9811a 3889 unwind.personality_routine = symbol_find_or_make (name);
91a2ae2a 3890 unwind.force_unwind_entry = 1;
800eeca4
JW
3891 *p = c;
3892 SKIP_WHITESPACE ();
3893 demand_empty_rest_of_line ();
3894}
3895
3896static void
3897dot_proc (dummy)
2434f565 3898 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3899{
3900 char *name, *p, c;
3901 symbolS *sym;
3902
e0c9811a
JW
3903 unwind.proc_start = expr_build_dot ();
3904 /* Parse names of main and alternate entry points and mark them as
542d6675 3905 function symbols: */
800eeca4
JW
3906 while (1)
3907 {
3908 SKIP_WHITESPACE ();
3909 name = input_line_pointer;
3910 c = get_symbol_end ();
3911 p = input_line_pointer;
3912 sym = symbol_find_or_make (name);
e0c9811a 3913 if (unwind.proc_start == 0)
542d6675 3914 {
e0c9811a 3915 unwind.proc_start = sym;
800eeca4
JW
3916 }
3917 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3918 *p = c;
3919 SKIP_WHITESPACE ();
3920 if (*input_line_pointer != ',')
3921 break;
3922 ++input_line_pointer;
3923 }
3924 demand_empty_rest_of_line ();
3925 ia64_do_align (16);
3926
33d01f33 3927 unwind.prologue_count = 0;
e0c9811a
JW
3928 unwind.list = unwind.tail = unwind.current_entry = NULL;
3929 unwind.personality_routine = 0;
800eeca4
JW
3930}
3931
3932static void
3933dot_body (dummy)
2434f565 3934 int dummy ATTRIBUTE_UNUSED;
800eeca4 3935{
e0c9811a 3936 unwind.prologue = 0;
30d25259
RH
3937 unwind.prologue_mask = 0;
3938
800eeca4 3939 add_unwind_entry (output_body ());
e0c9811a 3940 demand_empty_rest_of_line ();
800eeca4
JW
3941}
3942
3943static void
3944dot_prologue (dummy)
2434f565 3945 int dummy ATTRIBUTE_UNUSED;
800eeca4 3946{
e0c9811a 3947 unsigned char sep;
2434f565 3948 int mask = 0, grsave = 0;
e0c9811a 3949
e0c9811a 3950 if (!is_it_end_of_statement ())
800eeca4
JW
3951 {
3952 expressionS e1, e2;
800eeca4
JW
3953 sep = parse_operand (&e1);
3954 if (sep != ',')
3955 as_bad ("No second operand to .prologue");
3956 sep = parse_operand (&e2);
e0c9811a 3957 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
542d6675 3958 ignore_rest_of_line ();
800eeca4
JW
3959
3960 if (e1.X_op == O_constant)
542d6675 3961 {
30d25259
RH
3962 mask = e1.X_add_number;
3963
800eeca4 3964 if (e2.X_op == O_constant)
30d25259
RH
3965 grsave = e2.X_add_number;
3966 else if (e2.X_op == O_register
3967 && (grsave = e2.X_add_number - REG_GR) < 128)
3968 ;
800eeca4 3969 else
30d25259
RH
3970 as_bad ("Second operand not a constant or general register");
3971
3972 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW
3973 }
3974 else
3975 as_bad ("First operand not a constant");
3976 }
3977 else
3978 add_unwind_entry (output_prologue ());
30d25259
RH
3979
3980 unwind.prologue = 1;
3981 unwind.prologue_mask = mask;
33d01f33 3982 ++unwind.prologue_count;
800eeca4
JW
3983}
3984
3985static void
3986dot_endp (dummy)
2434f565 3987 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
3988{
3989 expressionS e;
3990 unsigned char *ptr;
44f5c83a 3991 int bytes_per_address;
800eeca4
JW
3992 long where;
3993 segT saved_seg;
3994 subsegT saved_subseg;
91a2ae2a 3995 const char *sec_name, *text_name;
c538998c
JJ
3996 char *name, *p, c;
3997 symbolS *sym;
800eeca4 3998
91a2ae2a
RH
3999 if (unwind.saved_text_seg)
4000 {
4001 saved_seg = unwind.saved_text_seg;
4002 saved_subseg = unwind.saved_text_subseg;
4003 unwind.saved_text_seg = NULL;
4004 }
4005 else
4006 {
4007 saved_seg = now_seg;
4008 saved_subseg = now_subseg;
4009 }
4010
4011 /*
4012 Use a slightly ugly scheme to derive the unwind section names from
4013 the text section name:
4014
4015 text sect. unwind table sect.
4016 name: name: comments:
4017 ---------- ----------------- --------------------------------
4018 .text .IA_64.unwind
4019 .text.foo .IA_64.unwind.text.foo
4020 .foo .IA_64.unwind.foo
579f31ac
JJ
4021 .gnu.linkonce.t.foo
4022 .gnu.linkonce.ia64unw.foo
91a2ae2a
RH
4023 _info .IA_64.unwind_info gas issues error message (ditto)
4024 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
4025
4026 This mapping is done so that:
4027
4028 (a) An object file with unwind info only in .text will use
4029 unwind section names .IA_64.unwind and .IA_64.unwind_info.
4030 This follows the letter of the ABI and also ensures backwards
4031 compatibility with older toolchains.
4032
4033 (b) An object file with unwind info in multiple text sections
4034 will use separate unwind sections for each text section.
4035 This allows us to properly set the "sh_info" and "sh_link"
4036 fields in SHT_IA_64_UNWIND as required by the ABI and also
4037 lets GNU ld support programs with multiple segments
4038 containing unwind info (as might be the case for certain
4039 embedded applications).
40449e9f 4040
91a2ae2a
RH
4041 (c) An error is issued if there would be a name clash.
4042 */
4043 text_name = segment_name (saved_seg);
4044 if (strncmp (text_name, "_info", 5) == 0)
4045 {
4046 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
4047 text_name);
4048 ignore_rest_of_line ();
4049 return;
4050 }
4051 if (strcmp (text_name, ".text") == 0)
4052 text_name = "";
800eeca4 4053
800eeca4 4054 insn_group_break (1, 0, 0);
800eeca4 4055
91a2ae2a
RH
4056 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
4057 if (!unwind.info)
4058 generate_unwind_image (text_name);
800eeca4 4059
91a2ae2a
RH
4060 if (unwind.info || unwind.force_unwind_entry)
4061 {
4062 subseg_set (md.last_text_seg, 0);
4063 unwind.proc_end = expr_build_dot ();
5e7474a7 4064
91a2ae2a
RH
4065 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
4066 set_section ((char *) sec_name);
4067 bfd_set_section_flags (stdoutput, now_seg,
4068 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
5e7474a7 4069
557debba
JW
4070 /* Make sure that section has 4 byte alignment for ILP32 and
4071 8 byte alignment for LP64. */
4072 record_alignment (now_seg, md.pointer_size_shift);
800eeca4 4073
557debba
JW
4074 /* Need space for 3 pointers for procedure start, procedure end,
4075 and unwind info. */
4076 ptr = frag_more (3 * md.pointer_size);
4077 where = frag_now_fix () - (3 * md.pointer_size);
91a2ae2a 4078 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
800eeca4 4079
40449e9f 4080 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
91a2ae2a
RH
4081 e.X_op = O_pseudo_fixup;
4082 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4083 e.X_add_number = 0;
4084 e.X_add_symbol = unwind.proc_start;
4085 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
800eeca4 4086
800eeca4
JW
4087 e.X_op = O_pseudo_fixup;
4088 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4089 e.X_add_number = 0;
91a2ae2a
RH
4090 e.X_add_symbol = unwind.proc_end;
4091 ia64_cons_fix_new (frag_now, where + bytes_per_address,
4092 bytes_per_address, &e);
4093
4094 if (unwind.info)
4095 {
4096 e.X_op = O_pseudo_fixup;
4097 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4098 e.X_add_number = 0;
4099 e.X_add_symbol = unwind.info;
4100 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
4101 bytes_per_address, &e);
4102 }
4103 else
4104 md_number_to_chars (ptr + (bytes_per_address * 2), 0,
4105 bytes_per_address);
800eeca4 4106
91a2ae2a 4107 }
800eeca4 4108 subseg_set (saved_seg, saved_subseg);
c538998c
JJ
4109
4110 /* Parse names of main and alternate entry points and set symbol sizes. */
4111 while (1)
4112 {
4113 SKIP_WHITESPACE ();
4114 name = input_line_pointer;
4115 c = get_symbol_end ();
4116 p = input_line_pointer;
4117 sym = symbol_find (name);
4118 if (sym && unwind.proc_start
4119 && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION)
4120 && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL)
4121 {
4122 fragS *fr = symbol_get_frag (unwind.proc_start);
4123 fragS *frag = symbol_get_frag (sym);
4124
4125 /* Check whether the function label is at or beyond last
4126 .proc directive. */
4127 while (fr && fr != frag)
4128 fr = fr->fr_next;
4129 if (fr)
4130 {
4131 if (frag == frag_now && SEG_NORMAL (now_seg))
4132 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym));
4133 else
4134 {
4135 symbol_get_obj (sym)->size =
4136 (expressionS *) xmalloc (sizeof (expressionS));
4137 symbol_get_obj (sym)->size->X_op = O_subtract;
4138 symbol_get_obj (sym)->size->X_add_symbol
4139 = symbol_new (FAKE_LABEL_NAME, now_seg,
4140 frag_now_fix (), frag_now);
4141 symbol_get_obj (sym)->size->X_op_symbol = sym;
4142 symbol_get_obj (sym)->size->X_add_number = 0;
4143 }
4144 }
4145 }
4146 *p = c;
4147 SKIP_WHITESPACE ();
4148 if (*input_line_pointer != ',')
4149 break;
4150 ++input_line_pointer;
4151 }
4152 demand_empty_rest_of_line ();
e0c9811a 4153 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW
4154}
4155
4156static void
4157dot_template (template)
4158 int template;
4159{
4160 CURR_SLOT.user_template = template;
4161}
4162
4163static void
4164dot_regstk (dummy)
2434f565 4165 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4166{
4167 int ins, locs, outs, rots;
4168
4169 if (is_it_end_of_statement ())
4170 ins = locs = outs = rots = 0;
4171 else
4172 {
4173 ins = get_absolute_expression ();
4174 if (*input_line_pointer++ != ',')
4175 goto err;
4176 locs = get_absolute_expression ();
4177 if (*input_line_pointer++ != ',')
4178 goto err;
4179 outs = get_absolute_expression ();
4180 if (*input_line_pointer++ != ',')
4181 goto err;
4182 rots = get_absolute_expression ();
4183 }
4184 set_regstack (ins, locs, outs, rots);
4185 return;
4186
4187 err:
4188 as_bad ("Comma expected");
4189 ignore_rest_of_line ();
4190}
4191
4192static void
4193dot_rot (type)
4194 int type;
4195{
4196 unsigned num_regs, num_alloced = 0;
4197 struct dynreg **drpp, *dr;
4198 int ch, base_reg = 0;
4199 char *name, *start;
4200 size_t len;
4201
4202 switch (type)
4203 {
4204 case DYNREG_GR: base_reg = REG_GR + 32; break;
4205 case DYNREG_FR: base_reg = REG_FR + 32; break;
4206 case DYNREG_PR: base_reg = REG_P + 16; break;
4207 default: break;
4208 }
4209
542d6675 4210 /* First, remove existing names from hash table. */
800eeca4
JW
4211 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
4212 {
4213 hash_delete (md.dynreg_hash, dr->name);
4214 dr->num_regs = 0;
4215 }
4216
4217 drpp = &md.dynreg[type];
4218 while (1)
4219 {
4220 start = input_line_pointer;
4221 ch = get_symbol_end ();
4222 *input_line_pointer = ch;
4223 len = (input_line_pointer - start);
4224
4225 SKIP_WHITESPACE ();
4226 if (*input_line_pointer != '[')
4227 {
4228 as_bad ("Expected '['");
4229 goto err;
4230 }
4231 ++input_line_pointer; /* skip '[' */
4232
4233 num_regs = get_absolute_expression ();
4234
4235 if (*input_line_pointer++ != ']')
4236 {
4237 as_bad ("Expected ']'");
4238 goto err;
4239 }
4240 SKIP_WHITESPACE ();
4241
4242 num_alloced += num_regs;
4243 switch (type)
4244 {
4245 case DYNREG_GR:
4246 if (num_alloced > md.rot.num_regs)
4247 {
4248 as_bad ("Used more than the declared %d rotating registers",
4249 md.rot.num_regs);
4250 goto err;
4251 }
4252 break;
4253 case DYNREG_FR:
4254 if (num_alloced > 96)
4255 {
4256 as_bad ("Used more than the available 96 rotating registers");
4257 goto err;
4258 }
4259 break;
4260 case DYNREG_PR:
4261 if (num_alloced > 48)
4262 {
4263 as_bad ("Used more than the available 48 rotating registers");
4264 goto err;
4265 }
4266 break;
4267
4268 default:
4269 break;
4270 }
4271
4272 name = obstack_alloc (&notes, len + 1);
4273 memcpy (name, start, len);
4274 name[len] = '\0';
4275
4276 if (!*drpp)
4277 {
4278 *drpp = obstack_alloc (&notes, sizeof (*dr));
4279 memset (*drpp, 0, sizeof (*dr));
4280 }
4281
4282 dr = *drpp;
4283 dr->name = name;
4284 dr->num_regs = num_regs;
4285 dr->base = base_reg;
4286 drpp = &dr->next;
4287 base_reg += num_regs;
4288
4289 if (hash_insert (md.dynreg_hash, name, dr))
4290 {
4291 as_bad ("Attempt to redefine register set `%s'", name);
4292 goto err;
4293 }
4294
4295 if (*input_line_pointer != ',')
4296 break;
4297 ++input_line_pointer; /* skip comma */
4298 SKIP_WHITESPACE ();
4299 }
4300 demand_empty_rest_of_line ();
4301 return;
4302
4303 err:
4304 ignore_rest_of_line ();
4305}
4306
4307static void
4308dot_byteorder (byteorder)
4309 int byteorder;
4310{
4311 target_big_endian = byteorder;
4312}
4313
4314static void
4315dot_psr (dummy)
2434f565 4316 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4317{
4318 char *option;
4319 int ch;
4320
4321 while (1)
4322 {
4323 option = input_line_pointer;
4324 ch = get_symbol_end ();
4325 if (strcmp (option, "lsb") == 0)
4326 md.flags &= ~EF_IA_64_BE;
4327 else if (strcmp (option, "msb") == 0)
4328 md.flags |= EF_IA_64_BE;
4329 else if (strcmp (option, "abi32") == 0)
4330 md.flags &= ~EF_IA_64_ABI64;
4331 else if (strcmp (option, "abi64") == 0)
4332 md.flags |= EF_IA_64_ABI64;
4333 else
4334 as_bad ("Unknown psr option `%s'", option);
4335 *input_line_pointer = ch;
4336
4337 SKIP_WHITESPACE ();
4338 if (*input_line_pointer != ',')
4339 break;
4340
4341 ++input_line_pointer;
4342 SKIP_WHITESPACE ();
4343 }
4344 demand_empty_rest_of_line ();
4345}
4346
4347static void
4348dot_alias (dummy)
2434f565 4349 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4350{
4351 as_bad (".alias not implemented yet");
4352}
4353
4354static void
4355dot_ln (dummy)
2434f565 4356 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4357{
4358 new_logical_line (0, get_absolute_expression ());
4359 demand_empty_rest_of_line ();
4360}
4361
542d6675 4362static char *
800eeca4
JW
4363parse_section_name ()
4364{
4365 char *name;
4366 int len;
4367
4368 SKIP_WHITESPACE ();
4369 if (*input_line_pointer != '"')
4370 {
4371 as_bad ("Missing section name");
4372 ignore_rest_of_line ();
4373 return 0;
4374 }
4375 name = demand_copy_C_string (&len);
4376 if (!name)
4377 {
4378 ignore_rest_of_line ();
4379 return 0;
4380 }
4381 SKIP_WHITESPACE ();
4382 if (*input_line_pointer != ',')
4383 {
4384 as_bad ("Comma expected after section name");
4385 ignore_rest_of_line ();
4386 return 0;
4387 }
4388 ++input_line_pointer; /* skip comma */
4389 return name;
4390}
4391
4392static void
4393dot_xdata (size)
4394 int size;
4395{
4396 char *name = parse_section_name ();
4397 if (!name)
4398 return;
4399
4d5a53ff 4400 md.keep_pending_output = 1;
800eeca4
JW
4401 set_section (name);
4402 cons (size);
4403 obj_elf_previous (0);
4d5a53ff 4404 md.keep_pending_output = 0;
800eeca4
JW
4405}
4406
4407/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
542d6675 4408
800eeca4
JW
4409static void
4410stmt_float_cons (kind)
4411 int kind;
4412{
4413 size_t size;
4414
4415 switch (kind)
4416 {
4417 case 'd': size = 8; break;
4418 case 'x': size = 10; break;
4419
4420 case 'f':
4421 default:
4422 size = 4;
4423 break;
4424 }
4425 ia64_do_align (size);
4426 float_cons (kind);
4427}
4428
4429static void
4430stmt_cons_ua (size)
4431 int size;
4432{
4433 int saved_auto_align = md.auto_align;
4434
4435 md.auto_align = 0;
4436 cons (size);
4437 md.auto_align = saved_auto_align;
4438}
4439
4440static void
4441dot_xfloat_cons (kind)
4442 int kind;
4443{
4444 char *name = parse_section_name ();
4445 if (!name)
4446 return;
4447
4d5a53ff 4448 md.keep_pending_output = 1;
800eeca4
JW
4449 set_section (name);
4450 stmt_float_cons (kind);
4451 obj_elf_previous (0);
4d5a53ff 4452 md.keep_pending_output = 0;
800eeca4
JW
4453}
4454
4455static void
4456dot_xstringer (zero)
4457 int zero;
4458{
4459 char *name = parse_section_name ();
4460 if (!name)
4461 return;
4462
4d5a53ff 4463 md.keep_pending_output = 1;
800eeca4
JW
4464 set_section (name);
4465 stringer (zero);
4466 obj_elf_previous (0);
4d5a53ff 4467 md.keep_pending_output = 0;
800eeca4
JW
4468}
4469
4470static void
4471dot_xdata_ua (size)
4472 int size;
4473{
4474 int saved_auto_align = md.auto_align;
4475 char *name = parse_section_name ();
4476 if (!name)
4477 return;
4478
4d5a53ff 4479 md.keep_pending_output = 1;
800eeca4
JW
4480 set_section (name);
4481 md.auto_align = 0;
4482 cons (size);
4483 md.auto_align = saved_auto_align;
4484 obj_elf_previous (0);
4d5a53ff 4485 md.keep_pending_output = 0;
800eeca4
JW
4486}
4487
4488static void
4489dot_xfloat_cons_ua (kind)
4490 int kind;
4491{
4492 int saved_auto_align = md.auto_align;
4493 char *name = parse_section_name ();
4494 if (!name)
4495 return;
4496
4d5a53ff 4497 md.keep_pending_output = 1;
800eeca4
JW
4498 set_section (name);
4499 md.auto_align = 0;
4500 stmt_float_cons (kind);
4501 md.auto_align = saved_auto_align;
4502 obj_elf_previous (0);
4d5a53ff 4503 md.keep_pending_output = 0;
800eeca4
JW
4504}
4505
4506/* .reg.val <regname>,value */
542d6675 4507
800eeca4
JW
4508static void
4509dot_reg_val (dummy)
2434f565 4510 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4511{
4512 expressionS reg;
4513
4514 expression (&reg);
4515 if (reg.X_op != O_register)
4516 {
4517 as_bad (_("Register name expected"));
4518 ignore_rest_of_line ();
4519 }
4520 else if (*input_line_pointer++ != ',')
4521 {
4522 as_bad (_("Comma expected"));
4523 ignore_rest_of_line ();
4524 }
197865e8 4525 else
800eeca4
JW
4526 {
4527 valueT value = get_absolute_expression ();
4528 int regno = reg.X_add_number;
542d6675
KH
4529 if (regno < REG_GR || regno > REG_GR + 128)
4530 as_warn (_("Register value annotation ignored"));
800eeca4 4531 else
542d6675
KH
4532 {
4533 gr_values[regno - REG_GR].known = 1;
4534 gr_values[regno - REG_GR].value = value;
4535 gr_values[regno - REG_GR].path = md.path;
4536 }
800eeca4
JW
4537 }
4538 demand_empty_rest_of_line ();
4539}
4540
197865e8 4541/* select dv checking mode
800eeca4
JW
4542 .auto
4543 .explicit
4544 .default
4545
197865e8 4546 A stop is inserted when changing modes
800eeca4 4547 */
542d6675 4548
800eeca4
JW
4549static void
4550dot_dv_mode (type)
542d6675 4551 int type;
800eeca4
JW
4552{
4553 if (md.manual_bundling)
4554 as_warn (_("Directive invalid within a bundle"));
4555
4556 if (type == 'E' || type == 'A')
4557 md.mode_explicitly_set = 0;
4558 else
4559 md.mode_explicitly_set = 1;
4560
4561 md.detect_dv = 1;
4562 switch (type)
4563 {
4564 case 'A':
4565 case 'a':
4566 if (md.explicit_mode)
542d6675 4567 insn_group_break (1, 0, 0);
800eeca4
JW
4568 md.explicit_mode = 0;
4569 break;
4570 case 'E':
4571 case 'e':
4572 if (!md.explicit_mode)
542d6675 4573 insn_group_break (1, 0, 0);
800eeca4
JW
4574 md.explicit_mode = 1;
4575 break;
4576 default:
4577 case 'd':
4578 if (md.explicit_mode != md.default_explicit_mode)
542d6675 4579 insn_group_break (1, 0, 0);
800eeca4
JW
4580 md.explicit_mode = md.default_explicit_mode;
4581 md.mode_explicitly_set = 0;
4582 break;
4583 }
4584}
4585
4586static void
4587print_prmask (mask)
542d6675 4588 valueT mask;
800eeca4
JW
4589{
4590 int regno;
4591 char *comma = "";
542d6675 4592 for (regno = 0; regno < 64; regno++)
800eeca4 4593 {
542d6675
KH
4594 if (mask & ((valueT) 1 << regno))
4595 {
4596 fprintf (stderr, "%s p%d", comma, regno);
4597 comma = ",";
4598 }
800eeca4
JW
4599 }
4600}
4601
4602/*
4603 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4604 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4605 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4606 .pred.safe_across_calls p1 [, p2 [,...]]
4607 */
542d6675 4608
800eeca4
JW
4609static void
4610dot_pred_rel (type)
542d6675 4611 int type;
800eeca4
JW
4612{
4613 valueT mask = 0;
4614 int count = 0;
4615 int p1 = -1, p2 = -1;
4616
4617 if (type == 0)
4618 {
4619 if (*input_line_pointer != '"')
542d6675
KH
4620 {
4621 as_bad (_("Missing predicate relation type"));
4622 ignore_rest_of_line ();
4623 return;
4624 }
197865e8 4625 else
542d6675
KH
4626 {
4627 int len;
4628 char *form = demand_copy_C_string (&len);
4629 if (strcmp (form, "mutex") == 0)
4630 type = 'm';
4631 else if (strcmp (form, "clear") == 0)
4632 type = 'c';
4633 else if (strcmp (form, "imply") == 0)
4634 type = 'i';
4635 else
4636 {
4637 as_bad (_("Unrecognized predicate relation type"));
4638 ignore_rest_of_line ();
4639 return;
4640 }
4641 }
800eeca4 4642 if (*input_line_pointer == ',')
542d6675 4643 ++input_line_pointer;
800eeca4
JW
4644 SKIP_WHITESPACE ();
4645 }
4646
4647 SKIP_WHITESPACE ();
4648 while (1)
4649 {
4650 valueT bit = 1;
4651 int regno;
197865e8 4652
3882b010 4653 if (TOUPPER (*input_line_pointer) != 'P'
542d6675
KH
4654 || (regno = atoi (++input_line_pointer)) < 0
4655 || regno > 63)
4656 {
4657 as_bad (_("Predicate register expected"));
4658 ignore_rest_of_line ();
4659 return;
4660 }
3882b010 4661 while (ISDIGIT (*input_line_pointer))
542d6675 4662 ++input_line_pointer;
800eeca4 4663 if (p1 == -1)
542d6675 4664 p1 = regno;
800eeca4 4665 else if (p2 == -1)
542d6675 4666 p2 = regno;
800eeca4
JW
4667 bit <<= regno;
4668 if (mask & bit)
542d6675
KH
4669 as_warn (_("Duplicate predicate register ignored"));
4670 mask |= bit;
4671 count++;
4672 /* See if it's a range. */
800eeca4 4673 if (*input_line_pointer == '-')
542d6675
KH
4674 {
4675 valueT stop = 1;
4676 ++input_line_pointer;
4677
3882b010 4678 if (TOUPPER (*input_line_pointer) != 'P'
542d6675
KH
4679 || (regno = atoi (++input_line_pointer)) < 0
4680 || regno > 63)
4681 {
4682 as_bad (_("Predicate register expected"));
4683 ignore_rest_of_line ();
4684 return;
4685 }
3882b010 4686 while (ISDIGIT (*input_line_pointer))
542d6675
KH
4687 ++input_line_pointer;
4688 stop <<= regno;
4689 if (bit >= stop)
4690 {
4691 as_bad (_("Bad register range"));
4692 ignore_rest_of_line ();
4693 return;
4694 }
4695 while (bit < stop)
4696 {
4697 bit <<= 1;
4698 mask |= bit;
4699 count++;
4700 }
4701 SKIP_WHITESPACE ();
4702 }
800eeca4 4703 if (*input_line_pointer != ',')
542d6675 4704 break;
800eeca4
JW
4705 ++input_line_pointer;
4706 SKIP_WHITESPACE ();
4707 }
4708
4709 switch (type)
4710 {
4711 case 'c':
4712 if (count == 0)
542d6675 4713 mask = ~(valueT) 0;
800eeca4 4714 clear_qp_mutex (mask);
197865e8 4715 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW
4716 break;
4717 case 'i':
4718 if (count != 2 || p1 == -1 || p2 == -1)
542d6675 4719 as_bad (_("Predicate source and target required"));
800eeca4 4720 else if (p1 == 0 || p2 == 0)
542d6675 4721 as_bad (_("Use of p0 is not valid in this context"));
800eeca4 4722 else
542d6675 4723 add_qp_imply (p1, p2);
800eeca4
JW
4724 break;
4725 case 'm':
4726 if (count < 2)
542d6675
KH
4727 {
4728 as_bad (_("At least two PR arguments expected"));
4729 break;
4730 }
800eeca4 4731 else if (mask & 1)
542d6675
KH
4732 {
4733 as_bad (_("Use of p0 is not valid in this context"));
4734 break;
4735 }
800eeca4
JW
4736 add_qp_mutex (mask);
4737 break;
4738 case 's':
4739 /* note that we don't override any existing relations */
4740 if (count == 0)
542d6675
KH
4741 {
4742 as_bad (_("At least one PR argument expected"));
4743 break;
4744 }
800eeca4 4745 if (md.debug_dv)
542d6675
KH
4746 {
4747 fprintf (stderr, "Safe across calls: ");
4748 print_prmask (mask);
4749 fprintf (stderr, "\n");
4750 }
800eeca4
JW
4751 qp_safe_across_calls = mask;
4752 break;
4753 }
4754 demand_empty_rest_of_line ();
4755}
4756
4757/* .entry label [, label [, ...]]
4758 Hint to DV code that the given labels are to be considered entry points.
542d6675
KH
4759 Otherwise, only global labels are considered entry points. */
4760
800eeca4
JW
4761static void
4762dot_entry (dummy)
2434f565 4763 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4764{
4765 const char *err;
4766 char *name;
4767 int c;
4768 symbolS *symbolP;
4769
4770 do
4771 {
4772 name = input_line_pointer;
4773 c = get_symbol_end ();
4774 symbolP = symbol_find_or_make (name);
4775
4776 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4777 if (err)
542d6675
KH
4778 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4779 name, err);
800eeca4
JW
4780
4781 *input_line_pointer = c;
4782 SKIP_WHITESPACE ();
4783 c = *input_line_pointer;
4784 if (c == ',')
4785 {
4786 input_line_pointer++;
4787 SKIP_WHITESPACE ();
4788 if (*input_line_pointer == '\n')
4789 c = '\n';
4790 }
4791 }
4792 while (c == ',');
4793
4794 demand_empty_rest_of_line ();
4795}
4796
197865e8 4797/* .mem.offset offset, base
542d6675
KH
4798 "base" is used to distinguish between offsets from a different base. */
4799
800eeca4
JW
4800static void
4801dot_mem_offset (dummy)
2434f565 4802 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW
4803{
4804 md.mem_offset.hint = 1;
4805 md.mem_offset.offset = get_absolute_expression ();
4806 if (*input_line_pointer != ',')
4807 {
4808 as_bad (_("Comma expected"));
4809 ignore_rest_of_line ();
4810 return;
4811 }
4812 ++input_line_pointer;
4813 md.mem_offset.base = get_absolute_expression ();
4814 demand_empty_rest_of_line ();
4815}
4816
542d6675 4817/* ia64-specific pseudo-ops: */
800eeca4
JW
4818const pseudo_typeS md_pseudo_table[] =
4819 {
4820 { "radix", dot_radix, 0 },
4821 { "lcomm", s_lcomm_bytes, 1 },
4822 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4823 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4824 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4825 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4826 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4827 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4828 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
557debba
JW
4829 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY },
4830 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY },
800eeca4
JW
4831 { "proc", dot_proc, 0 },
4832 { "body", dot_body, 0 },
4833 { "prologue", dot_prologue, 0 },
2434f565 4834 { "endp", dot_endp, 0 },
9f1838ed 4835 { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
2434f565
JW
4836 { "loc", dwarf2_directive_loc, 0 },
4837
4838 { "fframe", dot_fframe, 0 },
4839 { "vframe", dot_vframe, 0 },
4840 { "vframesp", dot_vframesp, 0 },
4841 { "vframepsp", dot_vframepsp, 0 },
4842 { "save", dot_save, 0 },
4843 { "restore", dot_restore, 0 },
4844 { "restorereg", dot_restorereg, 0 },
4845 { "restorereg.p", dot_restorereg_p, 0 },
4846 { "handlerdata", dot_handlerdata, 0 },
4847 { "unwentry", dot_unwentry, 0 },
4848 { "altrp", dot_altrp, 0 },
e0c9811a
JW
4849 { "savesp", dot_savemem, 0 },
4850 { "savepsp", dot_savemem, 1 },
2434f565
JW
4851 { "save.g", dot_saveg, 0 },
4852 { "save.f", dot_savef, 0 },
4853 { "save.b", dot_saveb, 0 },
4854 { "save.gf", dot_savegf, 0 },
4855 { "spill", dot_spill, 0 },
4856 { "spillreg", dot_spillreg, 0 },
e0c9811a
JW
4857 { "spillsp", dot_spillmem, 0 },
4858 { "spillpsp", dot_spillmem, 1 },
2434f565 4859 { "spillreg.p", dot_spillreg_p, 0 },
e0c9811a
JW
4860 { "spillsp.p", dot_spillmem_p, 0 },
4861 { "spillpsp.p", dot_spillmem_p, 1 },
2434f565
JW
4862 { "label_state", dot_label_state, 0 },
4863 { "copy_state", dot_copy_state, 0 },
4864 { "unwabi", dot_unwabi, 0 },
4865 { "personality", dot_personality, 0 },
800eeca4 4866#if 0
2434f565 4867 { "estate", dot_estate, 0 },
800eeca4
JW
4868#endif
4869 { "mii", dot_template, 0x0 },
4870 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4871 { "mlx", dot_template, 0x2 },
4872 { "mmi", dot_template, 0x4 },
4873 { "mfi", dot_template, 0x6 },
4874 { "mmf", dot_template, 0x7 },
4875 { "mib", dot_template, 0x8 },
4876 { "mbb", dot_template, 0x9 },
4877 { "bbb", dot_template, 0xb },
4878 { "mmb", dot_template, 0xc },
4879 { "mfb", dot_template, 0xe },
4880#if 0
4881 { "lb", dot_scope, 0 },
4882 { "le", dot_scope, 1 },
4883#endif
4884 { "align", s_align_bytes, 0 },
4885 { "regstk", dot_regstk, 0 },
4886 { "rotr", dot_rot, DYNREG_GR },
4887 { "rotf", dot_rot, DYNREG_FR },
4888 { "rotp", dot_rot, DYNREG_PR },
4889 { "lsb", dot_byteorder, 0 },
4890 { "msb", dot_byteorder, 1 },
4891 { "psr", dot_psr, 0 },
4892 { "alias", dot_alias, 0 },
4893 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4894
4895 { "xdata1", dot_xdata, 1 },
4896 { "xdata2", dot_xdata, 2 },
4897 { "xdata4", dot_xdata, 4 },
4898 { "xdata8", dot_xdata, 8 },
4899 { "xreal4", dot_xfloat_cons, 'f' },
4900 { "xreal8", dot_xfloat_cons, 'd' },
4901 { "xreal10", dot_xfloat_cons, 'x' },
4902 { "xstring", dot_xstringer, 0 },
4903 { "xstringz", dot_xstringer, 1 },
4904
542d6675 4905 /* unaligned versions: */
800eeca4
JW
4906 { "xdata2.ua", dot_xdata_ua, 2 },
4907 { "xdata4.ua", dot_xdata_ua, 4 },
4908 { "xdata8.ua", dot_xdata_ua, 8 },
4909 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4910 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4911 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4912
4913 /* annotations/DV checking support */
4914 { "entry", dot_entry, 0 },
2434f565 4915 { "mem.offset", dot_mem_offset, 0 },
800eeca4
JW
4916 { "pred.rel", dot_pred_rel, 0 },
4917 { "pred.rel.clear", dot_pred_rel, 'c' },
4918 { "pred.rel.imply", dot_pred_rel, 'i' },
4919 { "pred.rel.mutex", dot_pred_rel, 'm' },
4920 { "pred.safe_across_calls", dot_pred_rel, 's' },
2434f565 4921 { "reg.val", dot_reg_val, 0 },
800eeca4
JW
4922 { "auto", dot_dv_mode, 'a' },
4923 { "explicit", dot_dv_mode, 'e' },
4924 { "default", dot_dv_mode, 'd' },
4925
87885043
JW
4926 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4927 IA-64 aligns data allocation pseudo-ops by default, so we have to
4928 tell it that these ones are supposed to be unaligned. Long term,
4929 should rewrite so that only IA-64 specific data allocation pseudo-ops
4930 are aligned by default. */
4931 {"2byte", stmt_cons_ua, 2},
4932 {"4byte", stmt_cons_ua, 4},
4933 {"8byte", stmt_cons_ua, 8},
4934
800eeca4
JW
4935 { NULL, 0, 0 }
4936 };
4937
4938static const struct pseudo_opcode
4939 {
4940 const char *name;
4941 void (*handler) (int);
4942 int arg;
4943 }
4944pseudo_opcode[] =
4945 {
4946 /* these are more like pseudo-ops, but don't start with a dot */
4947 { "data1", cons, 1 },
4948 { "data2", cons, 2 },
4949 { "data4", cons, 4 },
4950 { "data8", cons, 8 },
3969b680 4951 { "data16", cons, 16 },
800eeca4
JW
4952 { "real4", stmt_float_cons, 'f' },
4953 { "real8", stmt_float_cons, 'd' },
4954 { "real10", stmt_float_cons, 'x' },
4955 { "string", stringer, 0 },
4956 { "stringz", stringer, 1 },
4957
542d6675 4958 /* unaligned versions: */
800eeca4
JW
4959 { "data2.ua", stmt_cons_ua, 2 },
4960 { "data4.ua", stmt_cons_ua, 4 },
4961 { "data8.ua", stmt_cons_ua, 8 },
3969b680 4962 { "data16.ua", stmt_cons_ua, 16 },
800eeca4
JW
4963 { "real4.ua", float_cons, 'f' },
4964 { "real8.ua", float_cons, 'd' },
4965 { "real10.ua", float_cons, 'x' },
4966 };
4967
4968/* Declare a register by creating a symbol for it and entering it in
4969 the symbol table. */
542d6675
KH
4970
4971static symbolS *
800eeca4
JW
4972declare_register (name, regnum)
4973 const char *name;
4974 int regnum;
4975{
4976 const char *err;
4977 symbolS *sym;
4978
4979 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4980
4981 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4982 if (err)
4983 as_fatal ("Inserting \"%s\" into register table failed: %s",
4984 name, err);
4985
4986 return sym;
4987}
4988
4989static void
4990declare_register_set (prefix, num_regs, base_regnum)
4991 const char *prefix;
4992 int num_regs;
4993 int base_regnum;
4994{
4995 char name[8];
4996 int i;
4997
4998 for (i = 0; i < num_regs; ++i)
4999 {
5000 sprintf (name, "%s%u", prefix, i);
5001 declare_register (name, base_regnum + i);
5002 }
5003}
5004
5005static unsigned int
5006operand_width (opnd)
5007 enum ia64_opnd opnd;
5008{
5009 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
5010 unsigned int bits = 0;
5011 int i;
5012
5013 bits = 0;
5014 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
5015 bits += odesc->field[i].bits;
5016
5017 return bits;
5018}
5019
87f8eb97 5020static enum operand_match_result
800eeca4
JW
5021operand_match (idesc, index, e)
5022 const struct ia64_opcode *idesc;
5023 int index;
5024 expressionS *e;
5025{
5026 enum ia64_opnd opnd = idesc->operands[index];
5027 int bits, relocatable = 0;
5028 struct insn_fix *fix;
5029 bfd_signed_vma val;
5030
5031 switch (opnd)
5032 {
542d6675 5033 /* constants: */
800eeca4
JW
5034
5035 case IA64_OPND_AR_CCV:
5036 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
87f8eb97 5037 return OPERAND_MATCH;
800eeca4
JW
5038 break;
5039
c10d9d8f
JW
5040 case IA64_OPND_AR_CSD:
5041 if (e->X_op == O_register && e->X_add_number == REG_AR + 25)
5042 return OPERAND_MATCH;
5043 break;
5044
800eeca4
JW
5045 case IA64_OPND_AR_PFS:
5046 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
87f8eb97 5047 return OPERAND_MATCH;
800eeca4
JW
5048 break;
5049
5050 case IA64_OPND_GR0:
5051 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
87f8eb97 5052 return OPERAND_MATCH;
800eeca4
JW
5053 break;
5054
5055 case IA64_OPND_IP:
5056 if (e->X_op == O_register && e->X_add_number == REG_IP)
87f8eb97 5057 return OPERAND_MATCH;
800eeca4
JW
5058 break;
5059
5060 case IA64_OPND_PR:
5061 if (e->X_op == O_register && e->X_add_number == REG_PR)
87f8eb97 5062 return OPERAND_MATCH;
800eeca4
JW
5063 break;
5064
5065 case IA64_OPND_PR_ROT:
5066 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
87f8eb97 5067 return OPERAND_MATCH;
800eeca4
JW
5068 break;
5069
5070 case IA64_OPND_PSR:
5071 if (e->X_op == O_register && e->X_add_number == REG_PSR)
87f8eb97 5072 return OPERAND_MATCH;
800eeca4
JW
5073 break;
5074
5075 case IA64_OPND_PSR_L:
5076 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
87f8eb97 5077 return OPERAND_MATCH;
800eeca4
JW
5078 break;
5079
5080 case IA64_OPND_PSR_UM:
5081 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
87f8eb97 5082 return OPERAND_MATCH;
800eeca4
JW
5083 break;
5084
5085 case IA64_OPND_C1:
87f8eb97
JW
5086 if (e->X_op == O_constant)
5087 {
5088 if (e->X_add_number == 1)
5089 return OPERAND_MATCH;
5090 else
5091 return OPERAND_OUT_OF_RANGE;
5092 }
800eeca4
JW
5093 break;
5094
5095 case IA64_OPND_C8:
87f8eb97
JW
5096 if (e->X_op == O_constant)
5097 {
5098 if (e->X_add_number == 8)
5099 return OPERAND_MATCH;
5100 else
5101 return OPERAND_OUT_OF_RANGE;
5102 }
800eeca4
JW
5103 break;
5104
5105 case IA64_OPND_C16:
87f8eb97
JW
5106 if (e->X_op == O_constant)
5107 {
5108 if (e->X_add_number == 16)
5109 return OPERAND_MATCH;
5110 else
5111 return OPERAND_OUT_OF_RANGE;
5112 }
800eeca4
JW
5113 break;
5114
542d6675 5115 /* register operands: */
800eeca4
JW
5116
5117 case IA64_OPND_AR3:
5118 if (e->X_op == O_register && e->X_add_number >= REG_AR
5119 && e->X_add_number < REG_AR + 128)
87f8eb97 5120 return OPERAND_MATCH;
800eeca4
JW
5121 break;
5122
5123 case IA64_OPND_B1:
5124 case IA64_OPND_B2:
5125 if (e->X_op == O_register && e->X_add_number >= REG_BR
5126 && e->X_add_number < REG_BR + 8)
87f8eb97 5127 return OPERAND_MATCH;
800eeca4
JW
5128 break;
5129
5130 case IA64_OPND_CR3:
5131 if (e->X_op == O_register && e->X_add_number >= REG_CR
5132 && e->X_add_number < REG_CR + 128)
87f8eb97 5133 return OPERAND_MATCH;
800eeca4
JW
5134 break;
5135
5136 case IA64_OPND_F1:
5137 case IA64_OPND_F2:
5138 case IA64_OPND_F3:
5139 case IA64_OPND_F4:
5140 if (e->X_op == O_register && e->X_add_number >= REG_FR
5141 && e->X_add_number < REG_FR + 128)
87f8eb97 5142 return OPERAND_MATCH;
800eeca4
JW
5143 break;
5144
5145 case IA64_OPND_P1:
5146 case IA64_OPND_P2:
5147 if (e->X_op == O_register && e->X_add_number >= REG_P
5148 && e->X_add_number < REG_P + 64)
87f8eb97 5149 return OPERAND_MATCH;
800eeca4
JW
5150 break;
5151
5152 case IA64_OPND_R1:
5153 case IA64_OPND_R2:
5154 case IA64_OPND_R3:
5155 if (e->X_op == O_register && e->X_add_number >= REG_GR
5156 && e->X_add_number < REG_GR + 128)
87f8eb97 5157 return OPERAND_MATCH;
800eeca4
JW
5158 break;
5159
5160 case IA64_OPND_R3_2:
87f8eb97 5161 if (e->X_op == O_register && e->X_add_number >= REG_GR)
40449e9f 5162 {
87f8eb97
JW
5163 if (e->X_add_number < REG_GR + 4)
5164 return OPERAND_MATCH;
5165 else if (e->X_add_number < REG_GR + 128)
5166 return OPERAND_OUT_OF_RANGE;
5167 }
800eeca4
JW
5168 break;
5169
542d6675 5170 /* indirect operands: */
800eeca4
JW
5171 case IA64_OPND_CPUID_R3:
5172 case IA64_OPND_DBR_R3:
5173 case IA64_OPND_DTR_R3:
5174 case IA64_OPND_ITR_R3:
5175 case IA64_OPND_IBR_R3:
5176 case IA64_OPND_MSR_R3:
5177 case IA64_OPND_PKR_R3:
5178 case IA64_OPND_PMC_R3:
5179 case IA64_OPND_PMD_R3:
5180 case IA64_OPND_RR_R3:
5181 if (e->X_op == O_index && e->X_op_symbol
5182 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
5183 == opnd - IA64_OPND_CPUID_R3))
87f8eb97 5184 return OPERAND_MATCH;
800eeca4
JW
5185 break;
5186
5187 case IA64_OPND_MR3:
5188 if (e->X_op == O_index && !e->X_op_symbol)
87f8eb97 5189 return OPERAND_MATCH;
800eeca4
JW
5190 break;
5191
542d6675 5192 /* immediate operands: */
800eeca4
JW
5193 case IA64_OPND_CNT2a:
5194 case IA64_OPND_LEN4:
5195 case IA64_OPND_LEN6:
5196 bits = operand_width (idesc->operands[index]);
87f8eb97
JW
5197 if (e->X_op == O_constant)
5198 {
5199 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
5200 return OPERAND_MATCH;
5201 else
5202 return OPERAND_OUT_OF_RANGE;
5203 }
800eeca4
JW
5204 break;
5205
5206 case IA64_OPND_CNT2b:
87f8eb97
JW
5207 if (e->X_op == O_constant)
5208 {
5209 if ((bfd_vma) (e->X_add_number - 1) < 3)
5210 return OPERAND_MATCH;
5211 else
5212 return OPERAND_OUT_OF_RANGE;
5213 }
800eeca4
JW
5214 break;
5215
5216 case IA64_OPND_CNT2c:
5217 val = e->X_add_number;
87f8eb97
JW
5218 if (e->X_op == O_constant)
5219 {
5220 if ((val == 0 || val == 7 || val == 15 || val == 16))
5221 return OPERAND_MATCH;
5222 else
5223 return OPERAND_OUT_OF_RANGE;
5224 }
800eeca4
JW
5225 break;
5226
5227 case IA64_OPND_SOR:
5228 /* SOR must be an integer multiple of 8 */
87f8eb97
JW
5229 if (e->X_op == O_constant && e->X_add_number & 0x7)
5230 return OPERAND_OUT_OF_RANGE;
800eeca4
JW
5231 case IA64_OPND_SOF:
5232 case IA64_OPND_SOL:
87f8eb97
JW
5233 if (e->X_op == O_constant)
5234 {
5235 if ((bfd_vma) e->X_add_number <= 96)
5236 return OPERAND_MATCH;
5237 else
5238 return OPERAND_OUT_OF_RANGE;
5239 }
800eeca4
JW
5240 break;
5241
5242 case IA64_OPND_IMMU62:
5243 if (e->X_op == O_constant)
542d6675 5244 {
800eeca4 5245 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
87f8eb97
JW
5246 return OPERAND_MATCH;
5247 else
5248 return OPERAND_OUT_OF_RANGE;
542d6675 5249 }
197865e8 5250 else
542d6675
KH
5251 {
5252 /* FIXME -- need 62-bit relocation type */
5253 as_bad (_("62-bit relocation not yet implemented"));
5254 }
800eeca4
JW
5255 break;
5256
5257 case IA64_OPND_IMMU64:
5258 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
5259 || e->X_op == O_subtract)
5260 {
5261 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5262 fix->code = BFD_RELOC_IA64_IMM64;
5263 if (e->X_op != O_subtract)
5264 {
5265 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5266 if (e->X_op == O_pseudo_fixup)
5267 e->X_op = O_symbol;
5268 }
5269
5270 fix->opnd = idesc->operands[index];
5271 fix->expr = *e;
5272 fix->is_pcrel = 0;
5273 ++CURR_SLOT.num_fixups;
87f8eb97 5274 return OPERAND_MATCH;
800eeca4
JW
5275 }
5276 else if (e->X_op == O_constant)
87f8eb97 5277 return OPERAND_MATCH;
800eeca4
JW
5278 break;
5279
5280 case IA64_OPND_CCNT5:
5281 case IA64_OPND_CNT5:
5282 case IA64_OPND_CNT6:
5283 case IA64_OPND_CPOS6a:
5284 case IA64_OPND_CPOS6b:
5285 case IA64_OPND_CPOS6c:
5286 case IA64_OPND_IMMU2:
5287 case IA64_OPND_IMMU7a:
5288 case IA64_OPND_IMMU7b:
800eeca4
JW
5289 case IA64_OPND_IMMU21:
5290 case IA64_OPND_IMMU24:
5291 case IA64_OPND_MBTYPE4:
5292 case IA64_OPND_MHTYPE8:
5293 case IA64_OPND_POS6:
5294 bits = operand_width (idesc->operands[index]);
87f8eb97
JW
5295 if (e->X_op == O_constant)
5296 {
5297 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5298 return OPERAND_MATCH;
5299 else
5300 return OPERAND_OUT_OF_RANGE;
5301 }
800eeca4
JW
5302 break;
5303
bf3ca999
TW
5304 case IA64_OPND_IMMU9:
5305 bits = operand_width (idesc->operands[index]);
87f8eb97 5306 if (e->X_op == O_constant)
542d6675 5307 {
87f8eb97
JW
5308 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5309 {
5310 int lobits = e->X_add_number & 0x3;
5311 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
5312 e->X_add_number |= (bfd_vma) 0x3;
5313 return OPERAND_MATCH;
5314 }
5315 else
5316 return OPERAND_OUT_OF_RANGE;
542d6675 5317 }
bf3ca999
TW
5318 break;
5319
800eeca4
JW
5320 case IA64_OPND_IMM44:
5321 /* least 16 bits must be zero */
5322 if ((e->X_add_number & 0xffff) != 0)
87f8eb97
JW
5323 /* XXX technically, this is wrong: we should not be issuing warning
5324 messages until we're sure this instruction pattern is going to
5325 be used! */
542d6675 5326 as_warn (_("lower 16 bits of mask ignored"));
800eeca4 5327
87f8eb97 5328 if (e->X_op == O_constant)
542d6675 5329 {
87f8eb97
JW
5330 if (((e->X_add_number >= 0
5331 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
5332 || (e->X_add_number < 0
5333 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
542d6675 5334 {
87f8eb97
JW
5335 /* sign-extend */
5336 if (e->X_add_number >= 0
5337 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
5338 {
5339 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
5340 }
5341 return OPERAND_MATCH;
542d6675 5342 }
87f8eb97
JW
5343 else
5344 return OPERAND_OUT_OF_RANGE;
542d6675 5345 }
800eeca4
JW
5346 break;
5347
5348 case IA64_OPND_IMM17:
5349 /* bit 0 is a don't care (pr0 is hardwired to 1) */
87f8eb97 5350 if (e->X_op == O_constant)
542d6675 5351 {
87f8eb97
JW
5352 if (((e->X_add_number >= 0
5353 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
5354 || (e->X_add_number < 0
5355 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
542d6675 5356 {
87f8eb97
JW
5357 /* sign-extend */
5358 if (e->X_add_number >= 0
5359 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
5360 {
5361 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
5362 }
5363 return OPERAND_MATCH;
542d6675 5364 }
87f8eb97
JW
5365 else
5366 return OPERAND_OUT_OF_RANGE;
542d6675 5367 }
800eeca4
JW
5368 break;
5369
5370 case IA64_OPND_IMM14:
5371 case IA64_OPND_IMM22:
5372 relocatable = 1;
5373 case IA64_OPND_IMM1:
5374 case IA64_OPND_IMM8:
5375 case IA64_OPND_IMM8U4:
5376 case IA64_OPND_IMM8M1:
5377 case IA64_OPND_IMM8M1U4:
5378 case IA64_OPND_IMM8M1U8:
5379 case IA64_OPND_IMM9a:
5380 case IA64_OPND_IMM9b:
5381 bits = operand_width (idesc->operands[index]);
5382 if (relocatable && (e->X_op == O_symbol
5383 || e->X_op == O_subtract
5384 || e->X_op == O_pseudo_fixup))
5385 {
5386 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5387
5388 if (idesc->operands[index] == IA64_OPND_IMM14)
5389 fix->code = BFD_RELOC_IA64_IMM14;
5390 else
5391 fix->code = BFD_RELOC_IA64_IMM22;
5392
5393 if (e->X_op != O_subtract)
5394 {
5395 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5396 if (e->X_op == O_pseudo_fixup)
5397 e->X_op = O_symbol;
5398 }
5399
5400 fix->opnd = idesc->operands[index];
5401 fix->expr = *e;
5402 fix->is_pcrel = 0;
5403 ++CURR_SLOT.num_fixups;
87f8eb97 5404 return OPERAND_MATCH;
800eeca4
JW
5405 }
5406 else if (e->X_op != O_constant
5407 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
87f8eb97 5408 return OPERAND_MISMATCH;
800eeca4
JW
5409
5410 if (opnd == IA64_OPND_IMM8M1U4)
5411 {
5412 /* Zero is not valid for unsigned compares that take an adjusted
5413 constant immediate range. */
5414 if (e->X_add_number == 0)
87f8eb97 5415 return OPERAND_OUT_OF_RANGE;
800eeca4
JW
5416
5417 /* Sign-extend 32-bit unsigned numbers, so that the following range
5418 checks will work. */
5419 val = e->X_add_number;
197865e8
KH
5420 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5421 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW
5422 val = ((val << 32) >> 32);
5423
5424 /* Check for 0x100000000. This is valid because
5425 0x100000000-1 is the same as ((uint32_t) -1). */
5426 if (val == ((bfd_signed_vma) 1 << 32))
87f8eb97 5427 return OPERAND_MATCH;
800eeca4
JW
5428
5429 val = val - 1;
5430 }
5431 else if (opnd == IA64_OPND_IMM8M1U8)
5432 {
5433 /* Zero is not valid for unsigned compares that take an adjusted
5434 constant immediate range. */
5435 if (e->X_add_number == 0)
87f8eb97 5436 return OPERAND_OUT_OF_RANGE;
800eeca4
JW
5437
5438 /* Check for 0x10000000000000000. */
5439 if (e->X_op == O_big)
5440 {
5441 if (generic_bignum[0] == 0
5442 && generic_bignum[1] == 0
5443 && generic_bignum[2] == 0
5444 && generic_bignum[3] == 0
5445 && generic_bignum[4] == 1)
87f8eb97 5446 return OPERAND_MATCH;
800eeca4 5447 else
87f8eb97 5448 return OPERAND_OUT_OF_RANGE;
800eeca4
JW
5449 }
5450 else
5451 val = e->X_add_number - 1;
5452 }
5453 else if (opnd == IA64_OPND_IMM8M1)
5454 val = e->X_add_number - 1;
5455 else if (opnd == IA64_OPND_IMM8U4)
5456 {
5457 /* Sign-extend 32-bit unsigned numbers, so that the following range
5458 checks will work. */
5459 val = e->X_add_number;
197865e8
KH
5460 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5461 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW
5462 val = ((val << 32) >> 32);
5463 }
5464 else
5465 val = e->X_add_number;
5466
2434f565
JW
5467 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
5468 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
87f8eb97
JW
5469 return OPERAND_MATCH;
5470 else
5471 return OPERAND_OUT_OF_RANGE;
800eeca4
JW
5472
5473 case IA64_OPND_INC3:
5474 /* +/- 1, 4, 8, 16 */
5475 val = e->X_add_number;
5476 if (val < 0)
5477 val = -val;
87f8eb97
JW
5478 if (e->X_op == O_constant)
5479 {
5480 if ((val == 1 || val == 4 || val == 8 || val == 16))
5481 return OPERAND_MATCH;
5482 else
5483 return OPERAND_OUT_OF_RANGE;
5484 }
800eeca4
JW
5485 break;
5486
5487 case IA64_OPND_TGT25:
5488 case IA64_OPND_TGT25b:
5489 case IA64_OPND_TGT25c:
5490 case IA64_OPND_TGT64:
5491 if (e->X_op == O_symbol)
5492 {
5493 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5494 if (opnd == IA64_OPND_TGT25)
5495 fix->code = BFD_RELOC_IA64_PCREL21F;
5496 else if (opnd == IA64_OPND_TGT25b)
5497 fix->code = BFD_RELOC_IA64_PCREL21M;
5498 else if (opnd == IA64_OPND_TGT25c)
5499 fix->code = BFD_RELOC_IA64_PCREL21B;
542d6675 5500 else if (opnd == IA64_OPND_TGT64)
c67e42c9
RH
5501 fix->code = BFD_RELOC_IA64_PCREL60B;
5502 else
5503 abort ();
5504
800eeca4
JW
5505 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5506 fix->opnd = idesc->operands[index];
5507 fix->expr = *e;
5508 fix->is_pcrel = 1;
5509 ++CURR_SLOT.num_fixups;
87f8eb97 5510 return OPERAND_MATCH;
800eeca4
JW
5511 }
5512 case IA64_OPND_TAG13:
5513 case IA64_OPND_TAG13b:
5514 switch (e->X_op)
5515 {
5516 case O_constant:
87f8eb97 5517 return OPERAND_MATCH;
800eeca4
JW
5518
5519 case O_symbol:
5520 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
fa1cb89c
JW
5521 /* There are no external relocs for TAG13/TAG13b fields, so we
5522 create a dummy reloc. This will not live past md_apply_fix3. */
5523 fix->code = BFD_RELOC_UNUSED;
5524 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
800eeca4
JW
5525 fix->opnd = idesc->operands[index];
5526 fix->expr = *e;
5527 fix->is_pcrel = 1;
5528 ++CURR_SLOT.num_fixups;
87f8eb97 5529 return OPERAND_MATCH;
800eeca4
JW
5530
5531 default:
5532 break;
5533 }
5534 break;
5535
a823923b
RH
5536 case IA64_OPND_LDXMOV:
5537 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5538 fix->code = BFD_RELOC_IA64_LDXMOV;
5539 fix->opnd = idesc->operands[index];
5540 fix->expr = *e;
5541 fix->is_pcrel = 0;
5542 ++CURR_SLOT.num_fixups;
5543 return OPERAND_MATCH;
5544
800eeca4
JW
5545 default:
5546 break;
5547 }
87f8eb97 5548 return OPERAND_MISMATCH;
800eeca4
JW
5549}
5550
5551static int
5552parse_operand (e)
5553 expressionS *e;
5554{
5555 int sep = '\0';
5556
5557 memset (e, 0, sizeof (*e));
5558 e->X_op = O_absent;
5559 SKIP_WHITESPACE ();
5560 if (*input_line_pointer != '}')
5561 expression (e);
5562 sep = *input_line_pointer++;
5563
5564 if (sep == '}')
5565 {
5566 if (!md.manual_bundling)
5567 as_warn ("Found '}' when manual bundling is off");
5568 else
5569 CURR_SLOT.manual_bundling_off = 1;
5570 md.manual_bundling = 0;
5571 sep = '\0';
5572 }
5573 return sep;
5574}
5575
5576/* Returns the next entry in the opcode table that matches the one in
5577 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 5578 found, NULL is returned instead. */
800eeca4
JW
5579
5580static struct ia64_opcode *
5581get_next_opcode (struct ia64_opcode *idesc)
5582{
5583 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5584 ia64_free_opcode (idesc);
5585 return next;
5586}
5587
5588/* Parse the operands for the opcode and find the opcode variant that
5589 matches the specified operands, or NULL if no match is possible. */
542d6675
KH
5590
5591static struct ia64_opcode *
800eeca4
JW
5592parse_operands (idesc)
5593 struct ia64_opcode *idesc;
5594{
5595 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
87f8eb97 5596 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
800eeca4 5597 enum ia64_opnd expected_operand = IA64_OPND_NIL;
87f8eb97 5598 enum operand_match_result result;
800eeca4
JW
5599 char mnemonic[129];
5600 char *first_arg = 0, *end, *saved_input_pointer;
5601 unsigned int sof;
5602
5603 assert (strlen (idesc->name) <= 128);
5604
5605 strcpy (mnemonic, idesc->name);
5606 if (idesc->operands[2] == IA64_OPND_SOF)
5607 {
5608 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5609 can't parse the first operand until we have parsed the
5610 remaining operands of the "alloc" instruction. */
5611 SKIP_WHITESPACE ();
5612 first_arg = input_line_pointer;
5613 end = strchr (input_line_pointer, '=');
5614 if (!end)
5615 {
5616 as_bad ("Expected separator `='");
5617 return 0;
5618 }
5619 input_line_pointer = end + 1;
5620 ++i;
5621 ++num_outputs;
5622 }
5623
5624 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5625 {
5626 sep = parse_operand (CURR_SLOT.opnd + i);
5627 if (CURR_SLOT.opnd[i].X_op == O_absent)
5628 break;
5629
5630 ++num_operands;
5631
5632 if (sep != '=' && sep != ',')
5633 break;
5634
5635 if (sep == '=')
5636 {
5637 if (num_outputs > 0)
5638 as_bad ("Duplicate equal sign (=) in instruction");
5639 else
5640 num_outputs = i + 1;
5641 }
5642 }
5643 if (sep != '\0')
5644 {
5645 as_bad ("Illegal operand separator `%c'", sep);
5646 return 0;
5647 }
197865e8 5648
800eeca4
JW
5649 if (idesc->operands[2] == IA64_OPND_SOF)
5650 {
5651 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5652 know (strcmp (idesc->name, "alloc") == 0);
5653 if (num_operands == 5 /* first_arg not included in this count! */
5654 && CURR_SLOT.opnd[2].X_op == O_constant
5655 && CURR_SLOT.opnd[3].X_op == O_constant
5656 && CURR_SLOT.opnd[4].X_op == O_constant
5657 && CURR_SLOT.opnd[5].X_op == O_constant)
5658 {
5659 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5660 CURR_SLOT.opnd[3].X_add_number,
5661 CURR_SLOT.opnd[4].X_add_number,
5662 CURR_SLOT.opnd[5].X_add_number);
5663
542d6675 5664 /* now we can parse the first arg: */
800eeca4
JW
5665 saved_input_pointer = input_line_pointer;
5666 input_line_pointer = first_arg;
5667 sep = parse_operand (CURR_SLOT.opnd + 0);
5668 if (sep != '=')
5669 --num_outputs; /* force error */
5670 input_line_pointer = saved_input_pointer;
5671
5672 CURR_SLOT.opnd[2].X_add_number = sof;
5673 CURR_SLOT.opnd[3].X_add_number
5674 = sof - CURR_SLOT.opnd[4].X_add_number;
5675 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5676 }
5677 }
5678
5679 highest_unmatched_operand = 0;
87f8eb97
JW
5680 curr_out_of_range_pos = -1;
5681 error_pos = 0;
800eeca4
JW
5682 expected_operand = idesc->operands[0];
5683 for (; idesc; idesc = get_next_opcode (idesc))
5684 {
5685 if (num_outputs != idesc->num_outputs)
5686 continue; /* mismatch in # of outputs */
5687
5688 CURR_SLOT.num_fixups = 0;
87f8eb97
JW
5689
5690 /* Try to match all operands. If we see an out-of-range operand,
5691 then continue trying to match the rest of the operands, since if
5692 the rest match, then this idesc will give the best error message. */
5693
5694 out_of_range_pos = -1;
800eeca4 5695 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
87f8eb97
JW
5696 {
5697 result = operand_match (idesc, i, CURR_SLOT.opnd + i);
5698 if (result != OPERAND_MATCH)
5699 {
5700 if (result != OPERAND_OUT_OF_RANGE)
5701 break;
5702 if (out_of_range_pos < 0)
5703 /* remember position of the first out-of-range operand: */
5704 out_of_range_pos = i;
5705 }
5706 }
800eeca4 5707
87f8eb97
JW
5708 /* If we did not match all operands, or if at least one operand was
5709 out-of-range, then this idesc does not match. Keep track of which
5710 idesc matched the most operands before failing. If we have two
5711 idescs that failed at the same position, and one had an out-of-range
5712 operand, then prefer the out-of-range operand. Thus if we have
5713 "add r0=0x1000000,r1" we get an error saying the constant is out
5714 of range instead of an error saying that the constant should have been
5715 a register. */
5716
5717 if (i != num_operands || out_of_range_pos >= 0)
800eeca4 5718 {
87f8eb97
JW
5719 if (i > highest_unmatched_operand
5720 || (i == highest_unmatched_operand
5721 && out_of_range_pos > curr_out_of_range_pos))
800eeca4
JW
5722 {
5723 highest_unmatched_operand = i;
87f8eb97
JW
5724 if (out_of_range_pos >= 0)
5725 {
5726 expected_operand = idesc->operands[out_of_range_pos];
5727 error_pos = out_of_range_pos;
5728 }
5729 else
5730 {
5731 expected_operand = idesc->operands[i];
5732 error_pos = i;
5733 }
5734 curr_out_of_range_pos = out_of_range_pos;
800eeca4
JW
5735 }
5736 continue;
5737 }
5738
5739 if (num_operands < NELEMS (idesc->operands)
5740 && idesc->operands[num_operands])
5741 continue; /* mismatch in number of arguments */
5742
5743 break;
5744 }
5745 if (!idesc)
5746 {
5747 if (expected_operand)
5748 as_bad ("Operand %u of `%s' should be %s",
87f8eb97 5749 error_pos + 1, mnemonic,
800eeca4
JW
5750 elf64_ia64_operands[expected_operand].desc);
5751 else
5752 as_bad ("Operand mismatch");
5753 return 0;
5754 }
5755 return idesc;
5756}
5757
88be23ec
BS
5758/* Keep track of state necessary to determine whether a NOP is necessary
5759 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5760 detect a case where additional NOPs may be necessary. */
5761static int
5762errata_nop_necessary_p (slot, insn_unit)
5763 struct slot *slot;
5764 enum ia64_unit insn_unit;
5765{
5766 int i;
5767 struct group *this_group = md.last_groups + md.group_idx;
5768 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5769 struct ia64_opcode *idesc = slot->idesc;
5770
5771 /* Test whether this could be the first insn in a problematic sequence. */
5772 if (insn_unit == IA64_UNIT_F)
5773 {
5774 for (i = 0; i < idesc->num_outputs; i++)
5775 if (idesc->operands[i] == IA64_OPND_P1
5776 || idesc->operands[i] == IA64_OPND_P2)
5777 {
5778 int regno = slot->opnd[i].X_add_number - REG_P;
3557da92 5779 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5780 if (regno >= 64)
3557da92 5781 return 0;
88be23ec
BS
5782 this_group->p_reg_set[regno] = 1;
5783 }
5784 }
5785
5786 /* Test whether this could be the second insn in a problematic sequence. */
5787 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5788 && prev_group->p_reg_set[slot->qp_regno])
5789 {
5790 for (i = 0; i < idesc->num_outputs; i++)
5791 if (idesc->operands[i] == IA64_OPND_R1
5792 || idesc->operands[i] == IA64_OPND_R2
5793 || idesc->operands[i] == IA64_OPND_R3)
5794 {
5795 int regno = slot->opnd[i].X_add_number - REG_GR;
3557da92 5796 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5797 if (regno >= 128)
3557da92 5798 return 0;
88be23ec
BS
5799 if (strncmp (idesc->name, "add", 3) != 0
5800 && strncmp (idesc->name, "sub", 3) != 0
5801 && strncmp (idesc->name, "shladd", 6) != 0
5802 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5803 this_group->g_reg_set_conditionally[regno] = 1;
5804 }
5805 }
5806
5807 /* Test whether this could be the third insn in a problematic sequence. */
5808 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5809 {
5810 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5811 idesc->operands[i] == IA64_OPND_R3
5812 /* For mov indirect. */
5813 || idesc->operands[i] == IA64_OPND_RR_R3
5814 || idesc->operands[i] == IA64_OPND_DBR_R3
5815 || idesc->operands[i] == IA64_OPND_IBR_R3
5816 || idesc->operands[i] == IA64_OPND_PKR_R3
5817 || idesc->operands[i] == IA64_OPND_PMC_R3
5818 || idesc->operands[i] == IA64_OPND_PMD_R3
5819 || idesc->operands[i] == IA64_OPND_MSR_R3
5820 || idesc->operands[i] == IA64_OPND_CPUID_R3
5821 /* For itr. */
5822 || idesc->operands[i] == IA64_OPND_ITR_R3
5823 || idesc->operands[i] == IA64_OPND_DTR_R3
5824 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5825 || idesc->operands[i] == IA64_OPND_MR3)
5826 {
5827 int regno = slot->opnd[i].X_add_number - REG_GR;
3557da92 5828 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5829 if (regno >= 128)
3557da92 5830 return 0;
88be23ec
BS
5831 if (idesc->operands[i] == IA64_OPND_R3)
5832 {
5833 if (strcmp (idesc->name, "fc") != 0
5834 && strcmp (idesc->name, "tak") != 0
5835 && strcmp (idesc->name, "thash") != 0
5836 && strcmp (idesc->name, "tpa") != 0
5837 && strcmp (idesc->name, "ttag") != 0
5838 && strncmp (idesc->name, "ptr", 3) != 0
5839 && strncmp (idesc->name, "ptc", 3) != 0
5840 && strncmp (idesc->name, "probe", 5) != 0)
40449e9f 5841 return 0;
88be23ec 5842 }
bc805888 5843 if (prev_group->g_reg_set_conditionally[regno])
88be23ec
BS
5844 return 1;
5845 }
5846 }
5847 return 0;
5848}
5849
800eeca4
JW
5850static void
5851build_insn (slot, insnp)
5852 struct slot *slot;
5853 bfd_vma *insnp;
5854{
5855 const struct ia64_operand *odesc, *o2desc;
5856 struct ia64_opcode *idesc = slot->idesc;
5857 bfd_signed_vma insn, val;
5858 const char *err;
5859 int i;
5860
5861 insn = idesc->opcode | slot->qp_regno;
5862
5863 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5864 {
c67e42c9
RH
5865 if (slot->opnd[i].X_op == O_register
5866 || slot->opnd[i].X_op == O_constant
5867 || slot->opnd[i].X_op == O_index)
5868 val = slot->opnd[i].X_add_number;
5869 else if (slot->opnd[i].X_op == O_big)
800eeca4 5870 {
c67e42c9
RH
5871 /* This must be the value 0x10000000000000000. */
5872 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5873 val = 0;
5874 }
5875 else
5876 val = 0;
5877
5878 switch (idesc->operands[i])
5879 {
5880 case IA64_OPND_IMMU64:
800eeca4
JW
5881 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5882 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5883 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5884 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH
5885 continue;
5886
5887 case IA64_OPND_IMMU62:
542d6675
KH
5888 val &= 0x3fffffffffffffffULL;
5889 if (val != slot->opnd[i].X_add_number)
5890 as_warn (_("Value truncated to 62 bits"));
5891 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5892 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5893 continue;
800eeca4 5894
c67e42c9
RH
5895 case IA64_OPND_TGT64:
5896 val >>= 4;
5897 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5898 insn |= ((((val >> 59) & 0x1) << 36)
5899 | (((val >> 0) & 0xfffff) << 13));
5900 continue;
800eeca4 5901
c67e42c9
RH
5902 case IA64_OPND_AR3:
5903 val -= REG_AR;
5904 break;
5905
5906 case IA64_OPND_B1:
5907 case IA64_OPND_B2:
5908 val -= REG_BR;
5909 break;
5910
5911 case IA64_OPND_CR3:
5912 val -= REG_CR;
5913 break;
5914
5915 case IA64_OPND_F1:
5916 case IA64_OPND_F2:
5917 case IA64_OPND_F3:
5918 case IA64_OPND_F4:
5919 val -= REG_FR;
5920 break;
5921
5922 case IA64_OPND_P1:
5923 case IA64_OPND_P2:
5924 val -= REG_P;
5925 break;
5926
5927 case IA64_OPND_R1:
5928 case IA64_OPND_R2:
5929 case IA64_OPND_R3:
5930 case IA64_OPND_R3_2:
5931 case IA64_OPND_CPUID_R3:
5932 case IA64_OPND_DBR_R3:
5933 case IA64_OPND_DTR_R3:
5934 case IA64_OPND_ITR_R3:
5935 case IA64_OPND_IBR_R3:
5936 case IA64_OPND_MR3:
5937 case IA64_OPND_MSR_R3:
5938 case IA64_OPND_PKR_R3:
5939 case IA64_OPND_PMC_R3:
5940 case IA64_OPND_PMD_R3:
197865e8 5941 case IA64_OPND_RR_R3:
c67e42c9
RH
5942 val -= REG_GR;
5943 break;
5944
5945 default:
5946 break;
5947 }
5948
5949 odesc = elf64_ia64_operands + idesc->operands[i];
5950 err = (*odesc->insert) (odesc, val, &insn);
5951 if (err)
5952 as_bad_where (slot->src_file, slot->src_line,
5953 "Bad operand value: %s", err);
5954 if (idesc->flags & IA64_OPCODE_PSEUDO)
5955 {
5956 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5957 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5958 {
5959 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5960 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5961 }
c67e42c9
RH
5962 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5963 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5964 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5965 {
c67e42c9
RH
5966 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5967 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW
5968 }
5969 }
5970 }
5971 *insnp = insn;
5972}
5973
5974static void
5975emit_one_bundle ()
5976{
5977 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5978 unsigned int manual_bundling = 0;
5979 enum ia64_unit required_unit, insn_unit = 0;
5980 enum ia64_insn_type type[3], insn_type;
5981 unsigned int template, orig_template;
542d6675 5982 bfd_vma insn[3] = { -1, -1, -1 };
800eeca4
JW
5983 struct ia64_opcode *idesc;
5984 int end_of_insn_group = 0, user_template = -1;
5985 int n, i, j, first, curr;
2434f565 5986 unw_rec_list *ptr;
800eeca4
JW
5987 bfd_vma t0 = 0, t1 = 0;
5988 struct label_fix *lfix;
5989 struct insn_fix *ifix;
5990 char mnemonic[16];
5991 fixS *fix;
5992 char *f;
5993
5994 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5995 know (first >= 0 & first < NUM_SLOTS);
5996 n = MIN (3, md.num_slots_in_use);
5997
5998 /* Determine template: user user_template if specified, best match
542d6675 5999 otherwise: */
800eeca4
JW
6000
6001 if (md.slot[first].user_template >= 0)
6002 user_template = template = md.slot[first].user_template;
6003 else
6004 {
032efc85 6005 /* Auto select appropriate template. */
800eeca4
JW
6006 memset (type, 0, sizeof (type));
6007 curr = first;
6008 for (i = 0; i < n; ++i)
6009 {
032efc85
RH
6010 if (md.slot[curr].label_fixups && i != 0)
6011 break;
800eeca4
JW
6012 type[i] = md.slot[curr].idesc->type;
6013 curr = (curr + 1) % NUM_SLOTS;
6014 }
6015 template = best_template[type[0]][type[1]][type[2]];
6016 }
6017
542d6675 6018 /* initialize instructions with appropriate nops: */
800eeca4
JW
6019 for (i = 0; i < 3; ++i)
6020 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
6021
6022 f = frag_more (16);
6023
542d6675 6024 /* now fill in slots with as many insns as possible: */
800eeca4
JW
6025 curr = first;
6026 idesc = md.slot[curr].idesc;
6027 end_of_insn_group = 0;
6028 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
6029 {
e0c9811a
JW
6030 /* Set the slot number for prologue/body records now as those
6031 refer to the current point, not the point after the
542d6675 6032 instruction has been issued: */
10850f29
JW
6033 /* Don't try to delete prologue/body records here, as that will cause
6034 them to also be deleted from the master list of unwind records. */
e0c9811a 6035 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW
6036 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
6037 || ptr->r.type == body)
f5a30c2e
JW
6038 {
6039 ptr->slot_number = (unsigned long) f + i;
6040 ptr->slot_frag = frag_now;
6041 }
e0c9811a 6042
800eeca4
JW
6043 if (idesc->flags & IA64_OPCODE_SLOT2)
6044 {
6045 if (manual_bundling && i != 2)
6046 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6047 "`%s' must be last in bundle", idesc->name);
6048 else
6049 i = 2;
6050 }
6051 if (idesc->flags & IA64_OPCODE_LAST)
6052 {
2434f565
JW
6053 int required_slot;
6054 unsigned int required_template;
800eeca4
JW
6055
6056 /* If we need a stop bit after an M slot, our only choice is
6057 template 5 (M;;MI). If we need a stop bit after a B
6058 slot, our only choice is to place it at the end of the
6059 bundle, because the only available templates are MIB,
6060 MBB, BBB, MMB, and MFB. We don't handle anything other
6061 than M and B slots because these are the only kind of
6062 instructions that can have the IA64_OPCODE_LAST bit set. */
6063 required_template = template;
6064 switch (idesc->type)
6065 {
6066 case IA64_TYPE_M:
6067 required_slot = 0;
6068 required_template = 5;
6069 break;
6070
6071 case IA64_TYPE_B:
6072 required_slot = 2;
6073 break;
6074
6075 default:
6076 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6077 "Internal error: don't know how to force %s to end"
6078 "of instruction group", idesc->name);
6079 required_slot = i;
6080 break;
6081 }
6082 if (manual_bundling && i != required_slot)
6083 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6084 "`%s' must be last in instruction group",
6085 idesc->name);
6086 if (required_slot < i)
6087 /* Can't fit this instruction. */
6088 break;
6089
6090 i = required_slot;
6091 if (required_template != template)
6092 {
6093 /* If we switch the template, we need to reset the NOPs
6094 after slot i. The slot-types of the instructions ahead
6095 of i never change, so we don't need to worry about
6096 changing NOPs in front of this slot. */
6097 for (j = i; j < 3; ++j)
6098 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
6099 }
6100 template = required_template;
6101 }
6102 if (curr != first && md.slot[curr].label_fixups)
6103 {
6104 if (manual_bundling_on)
6105 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6106 "Label must be first in a bundle");
6107 /* This insn must go into the first slot of a bundle. */
6108 break;
6109 }
6110
6111 manual_bundling_on = md.slot[curr].manual_bundling_on;
6112 manual_bundling_off = md.slot[curr].manual_bundling_off;
6113
6114 if (manual_bundling_on)
6115 {
6116 if (curr == first)
6117 manual_bundling = 1;
6118 else
6119 break; /* need to start a new bundle */
6120 }
6121
6122 if (end_of_insn_group && md.num_slots_in_use >= 1)
6123 {
6124 /* We need an instruction group boundary in the middle of a
6125 bundle. See if we can switch to an other template with
6126 an appropriate boundary. */
6127
6128 orig_template = template;
6129 if (i == 1 && (user_template == 4
6130 || (user_template < 0
6131 && (ia64_templ_desc[template].exec_unit[0]
6132 == IA64_UNIT_M))))
6133 {
6134 template = 5;
6135 end_of_insn_group = 0;
6136 }
6137 else if (i == 2 && (user_template == 0
6138 || (user_template < 0
6139 && (ia64_templ_desc[template].exec_unit[1]
6140 == IA64_UNIT_I)))
6141 /* This test makes sure we don't switch the template if
6142 the next instruction is one that needs to be first in
6143 an instruction group. Since all those instructions are
6144 in the M group, there is no way such an instruction can
6145 fit in this bundle even if we switch the template. The
6146 reason we have to check for this is that otherwise we
6147 may end up generating "MI;;I M.." which has the deadly
6148 effect that the second M instruction is no longer the
6149 first in the bundle! --davidm 99/12/16 */
6150 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
6151 {
6152 template = 1;
6153 end_of_insn_group = 0;
6154 }
6155 else if (curr != first)
6156 /* can't fit this insn */
6157 break;
6158
6159 if (template != orig_template)
6160 /* if we switch the template, we need to reset the NOPs
6161 after slot i. The slot-types of the instructions ahead
6162 of i never change, so we don't need to worry about
6163 changing NOPs in front of this slot. */
6164 for (j = i; j < 3; ++j)
6165 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
6166 }
6167 required_unit = ia64_templ_desc[template].exec_unit[i];
6168
c10d9d8f 6169 /* resolve dynamic opcodes such as "break", "hint", and "nop": */
800eeca4
JW
6170 if (idesc->type == IA64_TYPE_DYN)
6171 {
6172 if ((strcmp (idesc->name, "nop") == 0)
c10d9d8f 6173 || (strcmp (idesc->name, "hint") == 0)
800eeca4
JW
6174 || (strcmp (idesc->name, "break") == 0))
6175 insn_unit = required_unit;
6176 else if (strcmp (idesc->name, "chk.s") == 0)
6177 {
6178 insn_unit = IA64_UNIT_M;
6179 if (required_unit == IA64_UNIT_I)
6180 insn_unit = IA64_UNIT_I;
6181 }
6182 else
6183 as_fatal ("emit_one_bundle: unexpected dynamic op");
6184
6185 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 6186 ia64_free_opcode (idesc);
800eeca4
JW
6187 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
6188#if 0
6189 know (!idesc->next); /* no resolved dynamic ops have collisions */
6190#endif
6191 }
6192 else
6193 {
6194 insn_type = idesc->type;
6195 insn_unit = IA64_UNIT_NIL;
6196 switch (insn_type)
6197 {
6198 case IA64_TYPE_A:
6199 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
6200 insn_unit = required_unit;
6201 break;
542d6675 6202 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
800eeca4
JW
6203 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
6204 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
6205 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
6206 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
6207 default: break;
6208 }
6209 }
6210
6211 if (insn_unit != required_unit)
6212 {
6213 if (required_unit == IA64_UNIT_L
542d6675 6214 && insn_unit == IA64_UNIT_I
800eeca4
JW
6215 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
6216 {
6217 /* we got ourselves an MLX template but the current
197865e8 6218 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW
6219 that can go into the X slot of an MLX template. Duh. */
6220 if (md.num_slots_in_use >= NUM_SLOTS)
6221 {
6222 as_bad_where (md.slot[curr].src_file,
6223 md.slot[curr].src_line,
6224 "`%s' can't go in X slot of "
6225 "MLX template", idesc->name);
542d6675 6226 /* drop this insn so we don't livelock: */
800eeca4
JW
6227 --md.num_slots_in_use;
6228 }
6229 break;
6230 }
6231 continue; /* try next slot */
6232 }
6233
40449e9f
KH
6234 {
6235 bfd_vma addr;
800eeca4 6236
40449e9f
KH
6237 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
6238 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
6239 }
800eeca4 6240
88be23ec
BS
6241 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
6242 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6243
800eeca4
JW
6244 build_insn (md.slot + curr, insn + i);
6245
10850f29
JW
6246 /* Set slot counts for non prologue/body unwind records. */
6247 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
6248 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
6249 && ptr->r.type != body)
f5a30c2e
JW
6250 {
6251 ptr->slot_number = (unsigned long) f + i;
6252 ptr->slot_frag = frag_now;
6253 }
10850f29 6254 md.slot[curr].unwind_record = NULL;
10850f29 6255
800eeca4
JW
6256 if (required_unit == IA64_UNIT_L)
6257 {
6258 know (i == 1);
6259 /* skip one slot for long/X-unit instructions */
6260 ++i;
6261 }
6262 --md.num_slots_in_use;
6263
542d6675 6264 /* now is a good time to fix up the labels for this insn: */
800eeca4
JW
6265 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
6266 {
6267 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
6268 symbol_set_frag (lfix->sym, frag_now);
6269 }
f1bcba5b
JW
6270 /* and fix up the tags also. */
6271 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
6272 {
6273 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
6274 symbol_set_frag (lfix->sym, frag_now);
6275 }
800eeca4
JW
6276
6277 for (j = 0; j < md.slot[curr].num_fixups; ++j)
6278 {
6279 ifix = md.slot[curr].fixup + j;
5a080f89 6280 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
800eeca4
JW
6281 &ifix->expr, ifix->is_pcrel, ifix->code);
6282 fix->tc_fix_data.opnd = ifix->opnd;
6283 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
6284 fix->fx_file = md.slot[curr].src_file;
6285 fix->fx_line = md.slot[curr].src_line;
6286 }
6287
6288 end_of_insn_group = md.slot[curr].end_of_insn_group;
6289
88be23ec
BS
6290 if (end_of_insn_group)
6291 {
6292 md.group_idx = (md.group_idx + 1) % 3;
6293 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
6294 }
6295
542d6675 6296 /* clear slot: */
800eeca4
JW
6297 ia64_free_opcode (md.slot[curr].idesc);
6298 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
6299 md.slot[curr].user_template = -1;
6300
6301 if (manual_bundling_off)
6302 {
6303 manual_bundling = 0;
6304 break;
6305 }
6306 curr = (curr + 1) % NUM_SLOTS;
6307 idesc = md.slot[curr].idesc;
6308 }
6309 if (manual_bundling)
6310 {
6311 if (md.num_slots_in_use > 0)
6312 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6313 "`%s' does not fit into %s template",
6314 idesc->name, ia64_templ_desc[template].name);
6315 else
6316 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6317 "Missing '}' at end of file");
6318 }
6319 know (md.num_slots_in_use < NUM_SLOTS);
6320
6321 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
6322 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
6323
44f5c83a
JW
6324 number_to_chars_littleendian (f + 0, t0, 8);
6325 number_to_chars_littleendian (f + 8, t1, 8);
f5a30c2e
JW
6326
6327 unwind.next_slot_number = (unsigned long) f + 16;
6328 unwind.next_slot_frag = frag_now;
800eeca4
JW
6329}
6330
6331int
6332md_parse_option (c, arg)
6333 int c;
6334 char *arg;
6335{
7463c317 6336
800eeca4
JW
6337 switch (c)
6338 {
c43c2cc5 6339 /* Switches from the Intel assembler. */
44f5c83a 6340 case 'm':
800eeca4
JW
6341 if (strcmp (arg, "ilp64") == 0
6342 || strcmp (arg, "lp64") == 0
6343 || strcmp (arg, "p64") == 0)
6344 {
6345 md.flags |= EF_IA_64_ABI64;
6346 }
6347 else if (strcmp (arg, "ilp32") == 0)
6348 {
6349 md.flags &= ~EF_IA_64_ABI64;
6350 }
6351 else if (strcmp (arg, "le") == 0)
6352 {
6353 md.flags &= ~EF_IA_64_BE;
6354 }
6355 else if (strcmp (arg, "be") == 0)
6356 {
6357 md.flags |= EF_IA_64_BE;
6358 }
6359 else
6360 return 0;
6361 break;
6362
6363 case 'N':
6364 if (strcmp (arg, "so") == 0)
6365 {
542d6675 6366 /* Suppress signon message. */
800eeca4
JW
6367 }
6368 else if (strcmp (arg, "pi") == 0)
6369 {
6370 /* Reject privileged instructions. FIXME */
6371 }
6372 else if (strcmp (arg, "us") == 0)
6373 {
6374 /* Allow union of signed and unsigned range. FIXME */
6375 }
6376 else if (strcmp (arg, "close_fcalls") == 0)
6377 {
6378 /* Do not resolve global function calls. */
6379 }
6380 else
6381 return 0;
6382 break;
6383
6384 case 'C':
6385 /* temp[="prefix"] Insert temporary labels into the object file
6386 symbol table prefixed by "prefix".
6387 Default prefix is ":temp:".
6388 */
6389 break;
6390
6391 case 'a':
800eeca4
JW
6392 /* indirect=<tgt> Assume unannotated indirect branches behavior
6393 according to <tgt> --
6394 exit: branch out from the current context (default)
6395 labels: all labels in context may be branch targets
6396 */
85b40035
L
6397 if (strncmp (arg, "indirect=", 9) != 0)
6398 return 0;
800eeca4
JW
6399 break;
6400
6401 case 'x':
6402 /* -X conflicts with an ignored option, use -x instead */
6403 md.detect_dv = 1;
6404 if (!arg || strcmp (arg, "explicit") == 0)
542d6675
KH
6405 {
6406 /* set default mode to explicit */
6407 md.default_explicit_mode = 1;
6408 break;
6409 }
800eeca4 6410 else if (strcmp (arg, "auto") == 0)
542d6675
KH
6411 {
6412 md.default_explicit_mode = 0;
6413 }
800eeca4 6414 else if (strcmp (arg, "debug") == 0)
542d6675
KH
6415 {
6416 md.debug_dv = 1;
6417 }
800eeca4 6418 else if (strcmp (arg, "debugx") == 0)
542d6675
KH
6419 {
6420 md.default_explicit_mode = 1;
6421 md.debug_dv = 1;
6422 }
800eeca4 6423 else
542d6675
KH
6424 {
6425 as_bad (_("Unrecognized option '-x%s'"), arg);
6426 }
800eeca4
JW
6427 break;
6428
6429 case 'S':
6430 /* nops Print nops statistics. */
6431 break;
6432
c43c2cc5
JW
6433 /* GNU specific switches for gcc. */
6434 case OPTION_MCONSTANT_GP:
6435 md.flags |= EF_IA_64_CONS_GP;
6436 break;
6437
6438 case OPTION_MAUTO_PIC:
6439 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
6440 break;
6441
800eeca4
JW
6442 default:
6443 return 0;
6444 }
6445
6446 return 1;
6447}
6448
6449void
6450md_show_usage (stream)
6451 FILE *stream;
6452{
542d6675 6453 fputs (_("\
800eeca4 6454IA-64 options:\n\
6290819d
NC
6455 --mconstant-gp mark output file as using the constant-GP model\n\
6456 (sets ELF header flag EF_IA_64_CONS_GP)\n\
6457 --mauto-pic mark output file as using the constant-GP model\n\
6458 without function descriptors (sets ELF header flag\n\
6459 EF_IA_64_NOFUNCDESC_CONS_GP)\n\
44f5c83a
JW
6460 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6461 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
800eeca4
JW
6462 -x | -xexplicit turn on dependency violation checking (default)\n\
6463 -xauto automagically remove dependency violations\n\
6464 -xdebug debug dependency violation checker\n"),
6465 stream);
6466}
6467
acebd4ce
AS
6468void
6469ia64_after_parse_args ()
6470{
6471 if (debug_type == DEBUG_STABS)
6472 as_fatal (_("--gstabs is not supported for ia64"));
6473}
6474
44576e1f
RH
6475/* Return true if TYPE fits in TEMPL at SLOT. */
6476
6477static int
800eeca4
JW
6478match (int templ, int type, int slot)
6479{
6480 enum ia64_unit unit;
6481 int result;
6482
6483 unit = ia64_templ_desc[templ].exec_unit[slot];
6484 switch (type)
6485 {
6486 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
6487 case IA64_TYPE_A:
6488 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
6489 break;
6490 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
6491 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
6492 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
6493 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
6494 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
6495 default: result = 0; break;
6496 }
6497 return result;
6498}
6499
44576e1f
RH
6500/* Add a bit of extra goodness if a nop of type F or B would fit
6501 in TEMPL at SLOT. */
6502
6503static inline int
6504extra_goodness (int templ, int slot)
6505{
ebeeafe6 6506 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
44576e1f 6507 return 2;
ebeeafe6 6508 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
44576e1f
RH
6509 return 1;
6510 return 0;
6511}
6512
800eeca4
JW
6513/* This function is called once, at assembler startup time. It sets
6514 up all the tables, etc. that the MD part of the assembler will need
6515 that can be determined before arguments are parsed. */
6516void
6517md_begin ()
6518{
44f5c83a 6519 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
800eeca4
JW
6520 const char *err;
6521 char name[8];
6522
6523 md.auto_align = 1;
6524 md.explicit_mode = md.default_explicit_mode;
6525
6526 bfd_set_section_alignment (stdoutput, text_section, 4);
6527
44f5c83a 6528 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
13ae64f3
JJ
6529 pseudo_func[FUNC_DTP_MODULE].u.sym =
6530 symbol_new (".<dtpmod>", undefined_section, FUNC_DTP_MODULE,
6531 &zero_address_frag);
6532
6533 pseudo_func[FUNC_DTP_RELATIVE].u.sym =
6534 symbol_new (".<dtprel>", undefined_section, FUNC_DTP_RELATIVE,
6535 &zero_address_frag);
6536
800eeca4 6537 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
542d6675
KH
6538 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
6539 &zero_address_frag);
800eeca4
JW
6540
6541 pseudo_func[FUNC_GP_RELATIVE].u.sym =
542d6675
KH
6542 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
6543 &zero_address_frag);
800eeca4
JW
6544
6545 pseudo_func[FUNC_LT_RELATIVE].u.sym =
542d6675
KH
6546 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
6547 &zero_address_frag);
800eeca4 6548
fa2c7eff
RH
6549 pseudo_func[FUNC_LT_RELATIVE_X].u.sym =
6550 symbol_new (".<ltoffx>", undefined_section, FUNC_LT_RELATIVE_X,
6551 &zero_address_frag);
6552
c67e42c9 6553 pseudo_func[FUNC_PC_RELATIVE].u.sym =
542d6675
KH
6554 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
6555 &zero_address_frag);
c67e42c9 6556
800eeca4 6557 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
542d6675
KH
6558 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
6559 &zero_address_frag);
800eeca4
JW
6560
6561 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
542d6675
KH
6562 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
6563 &zero_address_frag);
800eeca4
JW
6564
6565 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
542d6675
KH
6566 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
6567 &zero_address_frag);
800eeca4 6568
13ae64f3
JJ
6569 pseudo_func[FUNC_TP_RELATIVE].u.sym =
6570 symbol_new (".<tprel>", undefined_section, FUNC_TP_RELATIVE,
6571 &zero_address_frag);
6572
800eeca4 6573 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
542d6675
KH
6574 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
6575 &zero_address_frag);
800eeca4
JW
6576
6577 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
542d6675
KH
6578 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
6579 &zero_address_frag);
800eeca4 6580
13ae64f3
JJ
6581 pseudo_func[FUNC_LT_DTP_MODULE].u.sym =
6582 symbol_new (".<ltoff.dtpmod>", undefined_section, FUNC_LT_DTP_MODULE,
6583 &zero_address_frag);
6584
6585 pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym =
6586 symbol_new (".<ltoff.dptrel>", undefined_section, FUNC_LT_DTP_RELATIVE,
6587 &zero_address_frag);
6588
6589 pseudo_func[FUNC_LT_TP_RELATIVE].u.sym =
6590 symbol_new (".<ltoff.tprel>", undefined_section, FUNC_LT_TP_RELATIVE,
6591 &zero_address_frag);
6592
3969b680
RH
6593 pseudo_func[FUNC_IPLT_RELOC].u.sym =
6594 symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC,
6595 &zero_address_frag);
6596
197865e8 6597 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH
6598 base 4 value, in which each match counts for 3, each F counts
6599 for 2, each B counts for 1. This should maximize the number of
6600 F and B nops in the chosen bundles, which is good because these
6601 pipelines are least likely to be overcommitted. */
800eeca4
JW
6602 for (i = 0; i < IA64_NUM_TYPES; ++i)
6603 for (j = 0; j < IA64_NUM_TYPES; ++j)
6604 for (k = 0; k < IA64_NUM_TYPES; ++k)
6605 {
6606 best = 0;
6607 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6608 {
6609 goodness = 0;
6610 if (match (t, i, 0))
6611 {
6612 if (match (t, j, 1))
6613 {
6614 if (match (t, k, 2))
44576e1f 6615 goodness = 3 + 3 + 3;
800eeca4 6616 else
44576e1f 6617 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW
6618 }
6619 else if (match (t, j, 2))
44576e1f 6620 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 6621 else
44576e1f
RH
6622 {
6623 goodness = 3;
6624 goodness += extra_goodness (t, 1);
6625 goodness += extra_goodness (t, 2);
6626 }
800eeca4
JW
6627 }
6628 else if (match (t, i, 1))
6629 {
6630 if (match (t, j, 2))
44576e1f 6631 goodness = 3 + 3;
800eeca4 6632 else
44576e1f 6633 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW
6634 }
6635 else if (match (t, i, 2))
44576e1f 6636 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW
6637
6638 if (goodness > best)
6639 {
6640 best = goodness;
6641 best_template[i][j][k] = t;
6642 }
6643 }
6644 }
6645
6646 for (i = 0; i < NUM_SLOTS; ++i)
6647 md.slot[i].user_template = -1;
6648
6649 md.pseudo_hash = hash_new ();
6650 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6651 {
6652 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6653 (void *) (pseudo_opcode + i));
6654 if (err)
6655 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6656 pseudo_opcode[i].name, err);
6657 }
6658
6659 md.reg_hash = hash_new ();
6660 md.dynreg_hash = hash_new ();
6661 md.const_hash = hash_new ();
6662 md.entry_hash = hash_new ();
6663
542d6675 6664 /* general registers: */
800eeca4
JW
6665
6666 total = 128;
6667 for (i = 0; i < total; ++i)
6668 {
6669 sprintf (name, "r%d", i - REG_GR);
6670 md.regsym[i] = declare_register (name, i);
6671 }
6672
542d6675 6673 /* floating point registers: */
800eeca4
JW
6674 total += 128;
6675 for (; i < total; ++i)
6676 {
6677 sprintf (name, "f%d", i - REG_FR);
6678 md.regsym[i] = declare_register (name, i);
6679 }
6680
542d6675 6681 /* application registers: */
800eeca4
JW
6682 total += 128;
6683 ar_base = i;
6684 for (; i < total; ++i)
6685 {
6686 sprintf (name, "ar%d", i - REG_AR);
6687 md.regsym[i] = declare_register (name, i);
6688 }
6689
542d6675 6690 /* control registers: */
800eeca4
JW
6691 total += 128;
6692 cr_base = i;
6693 for (; i < total; ++i)
6694 {
6695 sprintf (name, "cr%d", i - REG_CR);
6696 md.regsym[i] = declare_register (name, i);
6697 }
6698
542d6675 6699 /* predicate registers: */
800eeca4
JW
6700 total += 64;
6701 for (; i < total; ++i)
6702 {
6703 sprintf (name, "p%d", i - REG_P);
6704 md.regsym[i] = declare_register (name, i);
6705 }
6706
542d6675 6707 /* branch registers: */
800eeca4
JW
6708 total += 8;
6709 for (; i < total; ++i)
6710 {
6711 sprintf (name, "b%d", i - REG_BR);
6712 md.regsym[i] = declare_register (name, i);
6713 }
6714
6715 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6716 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6717 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6718 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6719 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6720 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6721 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6722
6723 for (i = 0; i < NELEMS (indirect_reg); ++i)
6724 {
6725 regnum = indirect_reg[i].regnum;
6726 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6727 }
6728
542d6675 6729 /* define synonyms for application registers: */
800eeca4
JW
6730 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6731 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6732 REG_AR + ar[i - REG_AR].regnum);
6733
542d6675 6734 /* define synonyms for control registers: */
800eeca4
JW
6735 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6736 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6737 REG_CR + cr[i - REG_CR].regnum);
6738
6739 declare_register ("gp", REG_GR + 1);
6740 declare_register ("sp", REG_GR + 12);
6741 declare_register ("rp", REG_BR + 0);
6742
542d6675 6743 /* pseudo-registers used to specify unwind info: */
e0c9811a
JW
6744 declare_register ("psp", REG_PSP);
6745
800eeca4
JW
6746 declare_register_set ("ret", 4, REG_GR + 8);
6747 declare_register_set ("farg", 8, REG_FR + 8);
6748 declare_register_set ("fret", 8, REG_FR + 8);
6749
6750 for (i = 0; i < NELEMS (const_bits); ++i)
6751 {
6752 err = hash_insert (md.const_hash, const_bits[i].name,
6753 (PTR) (const_bits + i));
6754 if (err)
6755 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6756 name, err);
6757 }
6758
44f5c83a
JW
6759 /* Set the architecture and machine depending on defaults and command line
6760 options. */
6761 if (md.flags & EF_IA_64_ABI64)
6762 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6763 else
6764 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6765
6766 if (! ok)
6767 as_warn (_("Could not set architecture and machine"));
800eeca4 6768
557debba
JW
6769 /* Set the pointer size and pointer shift size depending on md.flags */
6770
6771 if (md.flags & EF_IA_64_ABI64)
6772 {
6773 md.pointer_size = 8; /* pointers are 8 bytes */
6774 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */
6775 }
6776 else
6777 {
6778 md.pointer_size = 4; /* pointers are 4 bytes */
6779 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */
6780 }
6781
800eeca4
JW
6782 md.mem_offset.hint = 0;
6783 md.path = 0;
6784 md.maxpaths = 0;
6785 md.entry_labels = NULL;
6786}
6787
44f5c83a
JW
6788/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6789 because that is called after md_parse_option which is where we do the
6790 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6791 default endianness. */
6792
6793void
6794ia64_init (argc, argv)
2434f565
JW
6795 int argc ATTRIBUTE_UNUSED;
6796 char **argv ATTRIBUTE_UNUSED;
44f5c83a 6797{
1cd8ff38 6798 md.flags = MD_FLAGS_DEFAULT;
44f5c83a
JW
6799}
6800
6801/* Return a string for the target object file format. */
6802
6803const char *
6804ia64_target_format ()
6805{
6806 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6807 {
72a76794
JW
6808 if (md.flags & EF_IA_64_BE)
6809 {
6810 if (md.flags & EF_IA_64_ABI64)
1cd8ff38 6811#if defined(TE_AIX50)
7463c317 6812 return "elf64-ia64-aix-big";
1cd8ff38
NC
6813#elif defined(TE_HPUX)
6814 return "elf64-ia64-hpux-big";
7463c317 6815#else
72a76794 6816 return "elf64-ia64-big";
7463c317 6817#endif
72a76794 6818 else
1cd8ff38 6819#if defined(TE_AIX50)
7463c317 6820 return "elf32-ia64-aix-big";
1cd8ff38
NC
6821#elif defined(TE_HPUX)
6822 return "elf32-ia64-hpux-big";
7463c317 6823#else
72a76794 6824 return "elf32-ia64-big";
7463c317 6825#endif
72a76794 6826 }
44f5c83a 6827 else
72a76794
JW
6828 {
6829 if (md.flags & EF_IA_64_ABI64)
7463c317
TW
6830#ifdef TE_AIX50
6831 return "elf64-ia64-aix-little";
6832#else
72a76794 6833 return "elf64-ia64-little";
7463c317 6834#endif
72a76794 6835 else
7463c317
TW
6836#ifdef TE_AIX50
6837 return "elf32-ia64-aix-little";
6838#else
72a76794 6839 return "elf32-ia64-little";
7463c317 6840#endif
72a76794 6841 }
44f5c83a
JW
6842 }
6843 else
6844 return "unknown-format";
6845}
6846
800eeca4
JW
6847void
6848ia64_end_of_source ()
6849{
542d6675 6850 /* terminate insn group upon reaching end of file: */
800eeca4
JW
6851 insn_group_break (1, 0, 0);
6852
542d6675 6853 /* emits slots we haven't written yet: */
800eeca4
JW
6854 ia64_flush_insns ();
6855
6856 bfd_set_private_flags (stdoutput, md.flags);
6857
800eeca4
JW
6858 md.mem_offset.hint = 0;
6859}
6860
6861void
6862ia64_start_line ()
6863{
f1bcba5b
JW
6864 if (md.qp.X_op == O_register)
6865 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW
6866 md.qp.X_op = O_absent;
6867
6868 if (ignore_input ())
6869 return;
6870
6871 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6872 {
6873 if (md.detect_dv && !md.explicit_mode)
542d6675 6874 as_warn (_("Explicit stops are ignored in auto mode"));
800eeca4 6875 else
542d6675 6876 insn_group_break (1, 0, 0);
800eeca4
JW
6877 }
6878}
6879
f1bcba5b
JW
6880/* This is a hook for ia64_frob_label, so that it can distinguish tags from
6881 labels. */
6882static int defining_tag = 0;
6883
800eeca4
JW
6884int
6885ia64_unrecognized_line (ch)
6886 int ch;
6887{
6888 switch (ch)
6889 {
6890 case '(':
6891 expression (&md.qp);
6892 if (*input_line_pointer++ != ')')
6893 {
6894 as_bad ("Expected ')'");
6895 return 0;
6896 }
6897 if (md.qp.X_op != O_register)
6898 {
6899 as_bad ("Qualifying predicate expected");
6900 return 0;
6901 }
6902 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6903 {
6904 as_bad ("Predicate register expected");
6905 return 0;
6906 }
6907 return 1;
6908
6909 case '{':
6910 if (md.manual_bundling)
6911 as_warn ("Found '{' when manual bundling is already turned on");
6912 else
6913 CURR_SLOT.manual_bundling_on = 1;
6914 md.manual_bundling = 1;
6915
542d6675
KH
6916 /* Bundling is only acceptable in explicit mode
6917 or when in default automatic mode. */
800eeca4 6918 if (md.detect_dv && !md.explicit_mode)
542d6675
KH
6919 {
6920 if (!md.mode_explicitly_set
6921 && !md.default_explicit_mode)
6922 dot_dv_mode ('E');
6923 else
6924 as_warn (_("Found '{' after explicit switch to automatic mode"));
6925 }
800eeca4
JW
6926 return 1;
6927
6928 case '}':
6929 if (!md.manual_bundling)
6930 as_warn ("Found '}' when manual bundling is off");
6931 else
6932 PREV_SLOT.manual_bundling_off = 1;
6933 md.manual_bundling = 0;
6934
6935 /* switch back to automatic mode, if applicable */
197865e8 6936 if (md.detect_dv
542d6675
KH
6937 && md.explicit_mode
6938 && !md.mode_explicitly_set
6939 && !md.default_explicit_mode)
6940 dot_dv_mode ('A');
800eeca4
JW
6941
6942 /* Allow '{' to follow on the same line. We also allow ";;", but that
6943 happens automatically because ';' is an end of line marker. */
6944 SKIP_WHITESPACE ();
6945 if (input_line_pointer[0] == '{')
6946 {
6947 input_line_pointer++;
6948 return ia64_unrecognized_line ('{');
6949 }
6950
6951 demand_empty_rest_of_line ();
6952 return 1;
6953
f1bcba5b
JW
6954 case '[':
6955 {
6956 char *s;
6957 char c;
6958 symbolS *tag;
4d5a53ff 6959 int temp;
f1bcba5b
JW
6960
6961 if (md.qp.X_op == O_register)
6962 {
6963 as_bad ("Tag must come before qualifying predicate.");
6964 return 0;
6965 }
4d5a53ff
JW
6966
6967 /* This implements just enough of read_a_source_file in read.c to
6968 recognize labels. */
6969 if (is_name_beginner (*input_line_pointer))
6970 {
6971 s = input_line_pointer;
6972 c = get_symbol_end ();
6973 }
6974 else if (LOCAL_LABELS_FB
3882b010 6975 && ISDIGIT (*input_line_pointer))
4d5a53ff
JW
6976 {
6977 temp = 0;
3882b010 6978 while (ISDIGIT (*input_line_pointer))
4d5a53ff
JW
6979 temp = (temp * 10) + *input_line_pointer++ - '0';
6980 fb_label_instance_inc (temp);
6981 s = fb_label_name (temp, 0);
6982 c = *input_line_pointer;
6983 }
6984 else
6985 {
6986 s = NULL;
6987 c = '\0';
6988 }
f1bcba5b
JW
6989 if (c != ':')
6990 {
6991 /* Put ':' back for error messages' sake. */
6992 *input_line_pointer++ = ':';
6993 as_bad ("Expected ':'");
6994 return 0;
6995 }
4d5a53ff 6996
f1bcba5b
JW
6997 defining_tag = 1;
6998 tag = colon (s);
6999 defining_tag = 0;
7000 /* Put ':' back for error messages' sake. */
7001 *input_line_pointer++ = ':';
7002 if (*input_line_pointer++ != ']')
7003 {
7004 as_bad ("Expected ']'");
7005 return 0;
7006 }
7007 if (! tag)
7008 {
7009 as_bad ("Tag name expected");
7010 return 0;
7011 }
7012 return 1;
7013 }
7014
800eeca4
JW
7015 default:
7016 break;
7017 }
542d6675
KH
7018
7019 /* Not a valid line. */
7020 return 0;
800eeca4
JW
7021}
7022
7023void
7024ia64_frob_label (sym)
7025 struct symbol *sym;
7026{
7027 struct label_fix *fix;
7028
f1bcba5b
JW
7029 /* Tags need special handling since they are not bundle breaks like
7030 labels. */
7031 if (defining_tag)
7032 {
7033 fix = obstack_alloc (&notes, sizeof (*fix));
7034 fix->sym = sym;
7035 fix->next = CURR_SLOT.tag_fixups;
7036 CURR_SLOT.tag_fixups = fix;
7037
7038 return;
7039 }
7040
800eeca4
JW
7041 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
7042 {
7043 md.last_text_seg = now_seg;
7044 fix = obstack_alloc (&notes, sizeof (*fix));
7045 fix->sym = sym;
7046 fix->next = CURR_SLOT.label_fixups;
7047 CURR_SLOT.label_fixups = fix;
7048
542d6675 7049 /* Keep track of how many code entry points we've seen. */
800eeca4 7050 if (md.path == md.maxpaths)
542d6675
KH
7051 {
7052 md.maxpaths += 20;
7053 md.entry_labels = (const char **)
7054 xrealloc ((void *) md.entry_labels,
7055 md.maxpaths * sizeof (char *));
7056 }
800eeca4
JW
7057 md.entry_labels[md.path++] = S_GET_NAME (sym);
7058 }
7059}
7060
7061void
7062ia64_flush_pending_output ()
7063{
4d5a53ff
JW
7064 if (!md.keep_pending_output
7065 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
800eeca4
JW
7066 {
7067 /* ??? This causes many unnecessary stop bits to be emitted.
7068 Unfortunately, it isn't clear if it is safe to remove this. */
7069 insn_group_break (1, 0, 0);
7070 ia64_flush_insns ();
7071 }
7072}
7073
7074/* Do ia64-specific expression optimization. All that's done here is
7075 to transform index expressions that are either due to the indexing
7076 of rotating registers or due to the indexing of indirect register
7077 sets. */
7078int
7079ia64_optimize_expr (l, op, r)
7080 expressionS *l;
7081 operatorT op;
7082 expressionS *r;
7083{
7084 unsigned num_regs;
7085
7086 if (op == O_index)
7087 {
7088 if (l->X_op == O_register && r->X_op == O_constant)
7089 {
7090 num_regs = (l->X_add_number >> 16);
7091 if ((unsigned) r->X_add_number >= num_regs)
7092 {
7093 if (!num_regs)
7094 as_bad ("No current frame");
7095 else
7096 as_bad ("Index out of range 0..%u", num_regs - 1);
7097 r->X_add_number = 0;
7098 }
7099 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
7100 return 1;
7101 }
7102 else if (l->X_op == O_register && r->X_op == O_register)
7103 {
7104 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
7105 || l->X_add_number == IND_MEM)
7106 {
7107 as_bad ("Indirect register set name expected");
7108 l->X_add_number = IND_CPUID;
7109 }
7110 l->X_op = O_index;
7111 l->X_op_symbol = md.regsym[l->X_add_number];
7112 l->X_add_number = r->X_add_number;
7113 return 1;
7114 }
7115 }
7116 return 0;
7117}
7118
7119int
7120ia64_parse_name (name, e)
7121 char *name;
7122 expressionS *e;
7123{
7124 struct const_desc *cdesc;
7125 struct dynreg *dr = 0;
7126 unsigned int regnum;
7127 struct symbol *sym;
7128 char *end;
7129
542d6675 7130 /* first see if NAME is a known register name: */
800eeca4
JW
7131 sym = hash_find (md.reg_hash, name);
7132 if (sym)
7133 {
7134 e->X_op = O_register;
7135 e->X_add_number = S_GET_VALUE (sym);
7136 return 1;
7137 }
7138
7139 cdesc = hash_find (md.const_hash, name);
7140 if (cdesc)
7141 {
7142 e->X_op = O_constant;
7143 e->X_add_number = cdesc->value;
7144 return 1;
7145 }
7146
542d6675 7147 /* check for inN, locN, or outN: */
800eeca4
JW
7148 switch (name[0])
7149 {
7150 case 'i':
3882b010 7151 if (name[1] == 'n' && ISDIGIT (name[2]))
800eeca4
JW
7152 {
7153 dr = &md.in;
7154 name += 2;
7155 }
7156 break;
7157
7158 case 'l':
3882b010 7159 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3]))
800eeca4
JW
7160 {
7161 dr = &md.loc;
7162 name += 3;
7163 }
7164 break;
7165
7166 case 'o':
3882b010 7167 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3]))
800eeca4
JW
7168 {
7169 dr = &md.out;
7170 name += 3;
7171 }
7172 break;
7173
7174 default:
7175 break;
7176 }
7177
7178 if (dr)
7179 {
542d6675 7180 /* The name is inN, locN, or outN; parse the register number. */
800eeca4
JW
7181 regnum = strtoul (name, &end, 10);
7182 if (end > name && *end == '\0')
7183 {
7184 if ((unsigned) regnum >= dr->num_regs)
7185 {
7186 if (!dr->num_regs)
7187 as_bad ("No current frame");
7188 else
542d6675
KH
7189 as_bad ("Register number out of range 0..%u",
7190 dr->num_regs - 1);
800eeca4
JW
7191 regnum = 0;
7192 }
7193 e->X_op = O_register;
7194 e->X_add_number = dr->base + regnum;
7195 return 1;
7196 }
7197 }
7198
7199 if ((dr = hash_find (md.dynreg_hash, name)))
7200 {
7201 /* We've got ourselves the name of a rotating register set.
542d6675
KH
7202 Store the base register number in the low 16 bits of
7203 X_add_number and the size of the register set in the top 16
7204 bits. */
800eeca4
JW
7205 e->X_op = O_register;
7206 e->X_add_number = dr->base | (dr->num_regs << 16);
7207 return 1;
7208 }
7209 return 0;
7210}
7211
7212/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7213
7214char *
7215ia64_canonicalize_symbol_name (name)
7216 char *name;
7217{
542d6675
KH
7218 size_t len = strlen (name);
7219 if (len > 1 && name[len - 1] == '#')
7220 name[len - 1] = '\0';
800eeca4
JW
7221 return name;
7222}
7223
3e37788f
JW
7224/* Return true if idesc is a conditional branch instruction. This excludes
7225 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7226 because they always read/write resources regardless of the value of the
7227 qualifying predicate. br.ia must always use p0, and hence is always
7228 taken. Thus this function returns true for branches which can fall
7229 through, and which use no resources if they do fall through. */
1deb8127 7230
800eeca4
JW
7231static int
7232is_conditional_branch (idesc)
542d6675 7233 struct ia64_opcode *idesc;
800eeca4 7234{
1deb8127 7235 /* br is a conditional branch. Everything that starts with br. except
3e37788f
JW
7236 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7237 Everything that starts with brl is a conditional branch. */
1deb8127
JW
7238 return (idesc->name[0] == 'b' && idesc->name[1] == 'r'
7239 && (idesc->name[2] == '\0'
3e37788f
JW
7240 || (idesc->name[2] == '.' && idesc->name[3] != 'i'
7241 && idesc->name[3] != 'c' && idesc->name[3] != 'w')
7242 || idesc->name[2] == 'l'
7243 /* br.cond, br.call, br.clr */
7244 || (idesc->name[2] == '.' && idesc->name[3] == 'c'
7245 && (idesc->name[4] == 'a' || idesc->name[4] == 'o'
7246 || (idesc->name[4] == 'l' && idesc->name[5] == 'r')))));
800eeca4
JW
7247}
7248
7249/* Return whether the given opcode is a taken branch. If there's any doubt,
542d6675
KH
7250 returns zero. */
7251
800eeca4
JW
7252static int
7253is_taken_branch (idesc)
542d6675 7254 struct ia64_opcode *idesc;
800eeca4
JW
7255{
7256 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
542d6675 7257 || strncmp (idesc->name, "br.ia", 5) == 0);
800eeca4
JW
7258}
7259
7260/* Return whether the given opcode is an interruption or rfi. If there's any
542d6675
KH
7261 doubt, returns zero. */
7262
800eeca4
JW
7263static int
7264is_interruption_or_rfi (idesc)
542d6675 7265 struct ia64_opcode *idesc;
800eeca4
JW
7266{
7267 if (strcmp (idesc->name, "rfi") == 0)
7268 return 1;
7269 return 0;
7270}
7271
7272/* Returns the index of the given dependency in the opcode's list of chks, or
7273 -1 if there is no dependency. */
542d6675 7274
800eeca4
JW
7275static int
7276depends_on (depind, idesc)
542d6675
KH
7277 int depind;
7278 struct ia64_opcode *idesc;
800eeca4
JW
7279{
7280 int i;
7281 const struct ia64_opcode_dependency *dep = idesc->dependencies;
542d6675 7282 for (i = 0; i < dep->nchks; i++)
800eeca4 7283 {
542d6675
KH
7284 if (depind == DEP (dep->chks[i]))
7285 return i;
800eeca4
JW
7286 }
7287 return -1;
7288}
7289
7290/* Determine a set of specific resources used for a particular resource
7291 class. Returns the number of specific resources identified For those
7292 cases which are not determinable statically, the resource returned is
197865e8 7293 marked nonspecific.
800eeca4
JW
7294
7295 Meanings of value in 'NOTE':
7296 1) only read/write when the register number is explicitly encoded in the
7297 insn.
7298 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 7299 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW
7300 3) general register value is used to specify an indirect register; not
7301 determinable statically.
7302 4) only read the given resource when bits 7:0 of the indirect index
7303 register value does not match the register number of the resource; not
7304 determinable statically.
7305 5) all rules are implementation specific.
7306 6) only when both the index specified by the reader and the index specified
7307 by the writer have the same value in bits 63:61; not determinable
197865e8 7308 statically.
800eeca4 7309 7) only access the specified resource when the corresponding mask bit is
197865e8 7310 set
800eeca4
JW
7311 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7312 only read when these insns reference FR2-31
7313 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7314 written when these insns write FR32-127
7315 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7316 instruction
7317 11) The target predicates are written independently of PR[qp], but source
7318 registers are only read if PR[qp] is true. Since the state of PR[qp]
7319 cannot statically be determined, all source registers are marked used.
7320 12) This insn only reads the specified predicate register when that
7321 register is the PR[qp].
7322 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 7323 with data returned from memory, not the post-incremented address register.
800eeca4
JW
7324 14) The RSE resource includes the implementation-specific RSE internal
7325 state resources. At least one (and possibly more) of these resources are
7326 read by each instruction listed in IC:rse-readers. At least one (and
7327 possibly more) of these resources are written by each insn listed in
197865e8 7328 IC:rse-writers.
800eeca4 7329 15+16) Represents reserved instructions, which the assembler does not
197865e8 7330 generate.
800eeca4
JW
7331
7332 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7333 this code; there are no dependency violations based on memory access.
800eeca4
JW
7334*/
7335
7336#define MAX_SPECS 256
7337#define DV_CHK 1
7338#define DV_REG 0
7339
7340static int
7341specify_resource (dep, idesc, type, specs, note, path)
542d6675
KH
7342 const struct ia64_dependency *dep;
7343 struct ia64_opcode *idesc;
7344 int type; /* is this a DV chk or a DV reg? */
7345 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
7346 int note; /* resource note for this insn's usage */
7347 int path; /* which execution path to examine */
800eeca4
JW
7348{
7349 int count = 0;
7350 int i;
7351 int rsrc_write = 0;
7352 struct rsrc tmpl;
197865e8 7353
800eeca4
JW
7354 if (dep->mode == IA64_DV_WAW
7355 || (dep->mode == IA64_DV_RAW && type == DV_REG)
7356 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
7357 rsrc_write = 1;
7358
7359 /* template for any resources we identify */
7360 tmpl.dependency = dep;
7361 tmpl.note = note;
7362 tmpl.insn_srlz = tmpl.data_srlz = 0;
7363 tmpl.qp_regno = CURR_SLOT.qp_regno;
7364 tmpl.link_to_qp_branch = 1;
7365 tmpl.mem_offset.hint = 0;
7366 tmpl.specific = 1;
7367 tmpl.index = 0;
7484b8e6 7368 tmpl.cmp_type = CMP_NONE;
800eeca4
JW
7369
7370#define UNHANDLED \
7371as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7372dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7373#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7374
7375 /* we don't need to track these */
7376 if (dep->semantics == IA64_DVS_NONE)
7377 return 0;
7378
7379 switch (dep->specifier)
7380 {
7381 case IA64_RS_AR_K:
7382 if (note == 1)
542d6675
KH
7383 {
7384 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7385 {
7386 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7387 if (regno >= 0 && regno <= 7)
7388 {
7389 specs[count] = tmpl;
7390 specs[count++].index = regno;
7391 }
7392 }
7393 }
800eeca4 7394 else if (note == 0)
542d6675
KH
7395 {
7396 for (i = 0; i < 8; i++)
7397 {
7398 specs[count] = tmpl;
7399 specs[count++].index = i;
7400 }
7401 }
800eeca4 7402 else
542d6675
KH
7403 {
7404 UNHANDLED;
7405 }
800eeca4
JW
7406 break;
7407
7408 case IA64_RS_AR_UNAT:
7409 /* This is a mov =AR or mov AR= instruction. */
7410 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7411 {
7412 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7413 if (regno == AR_UNAT)
7414 {
7415 specs[count++] = tmpl;
7416 }
7417 }
7418 else
7419 {
7420 /* This is a spill/fill, or other instruction that modifies the
7421 unat register. */
7422
7423 /* Unless we can determine the specific bits used, mark the whole
7424 thing; bits 8:3 of the memory address indicate the bit used in
7425 UNAT. The .mem.offset hint may be used to eliminate a small
7426 subset of conflicts. */
7427 specs[count] = tmpl;
7428 if (md.mem_offset.hint)
7429 {
542d6675
KH
7430 if (md.debug_dv)
7431 fprintf (stderr, " Using hint for spill/fill\n");
7432 /* The index isn't actually used, just set it to something
7433 approximating the bit index. */
800eeca4
JW
7434 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
7435 specs[count].mem_offset.hint = 1;
7436 specs[count].mem_offset.offset = md.mem_offset.offset;
7437 specs[count++].mem_offset.base = md.mem_offset.base;
7438 }
7439 else
7440 {
7441 specs[count++].specific = 0;
7442 }
7443 }
7444 break;
7445
7446 case IA64_RS_AR:
7447 if (note == 1)
542d6675
KH
7448 {
7449 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7450 {
7451 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7452 if ((regno >= 8 && regno <= 15)
7453 || (regno >= 20 && regno <= 23)
7454 || (regno >= 31 && regno <= 39)
7455 || (regno >= 41 && regno <= 47)
7456 || (regno >= 67 && regno <= 111))
7457 {
7458 specs[count] = tmpl;
7459 specs[count++].index = regno;
7460 }
7461 }
7462 }
800eeca4 7463 else
542d6675
KH
7464 {
7465 UNHANDLED;
7466 }
800eeca4
JW
7467 break;
7468
7469 case IA64_RS_ARb:
7470 if (note == 1)
542d6675
KH
7471 {
7472 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7473 {
7474 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7475 if ((regno >= 48 && regno <= 63)
7476 || (regno >= 112 && regno <= 127))
7477 {
7478 specs[count] = tmpl;
7479 specs[count++].index = regno;
7480 }
7481 }
7482 }
800eeca4 7483 else if (note == 0)
542d6675
KH
7484 {
7485 for (i = 48; i < 64; i++)
7486 {
7487 specs[count] = tmpl;
7488 specs[count++].index = i;
7489 }
7490 for (i = 112; i < 128; i++)
7491 {
7492 specs[count] = tmpl;
7493 specs[count++].index = i;
7494 }
7495 }
197865e8 7496 else
542d6675
KH
7497 {
7498 UNHANDLED;
7499 }
800eeca4
JW
7500 break;
7501
7502 case IA64_RS_BR:
7503 if (note != 1)
542d6675
KH
7504 {
7505 UNHANDLED;
7506 }
800eeca4 7507 else
542d6675
KH
7508 {
7509 if (rsrc_write)
7510 {
7511 for (i = 0; i < idesc->num_outputs; i++)
7512 if (idesc->operands[i] == IA64_OPND_B1
7513 || idesc->operands[i] == IA64_OPND_B2)
7514 {
7515 specs[count] = tmpl;
7516 specs[count++].index =
7517 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7518 }
7519 }
7520 else
7521 {
40449e9f 7522 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
542d6675
KH
7523 if (idesc->operands[i] == IA64_OPND_B1
7524 || idesc->operands[i] == IA64_OPND_B2)
7525 {
7526 specs[count] = tmpl;
7527 specs[count++].index =
7528 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7529 }
7530 }
7531 }
800eeca4
JW
7532 break;
7533
7534 case IA64_RS_CPUID: /* four or more registers */
7535 if (note == 3)
542d6675
KH
7536 {
7537 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
7538 {
7539 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7540 if (regno >= 0 && regno < NELEMS (gr_values)
7541 && KNOWN (regno))
7542 {
7543 specs[count] = tmpl;
7544 specs[count++].index = gr_values[regno].value & 0xFF;
7545 }
7546 else
7547 {
7548 specs[count] = tmpl;
7549 specs[count++].specific = 0;
7550 }
7551 }
7552 }
800eeca4 7553 else
542d6675
KH
7554 {
7555 UNHANDLED;
7556 }
800eeca4
JW
7557 break;
7558
7559 case IA64_RS_DBR: /* four or more registers */
7560 if (note == 3)
542d6675
KH
7561 {
7562 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
7563 {
7564 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7565 if (regno >= 0 && regno < NELEMS (gr_values)
7566 && KNOWN (regno))
7567 {
7568 specs[count] = tmpl;
7569 specs[count++].index = gr_values[regno].value & 0xFF;
7570 }
7571 else
7572 {
7573 specs[count] = tmpl;
7574 specs[count++].specific = 0;
7575 }
7576 }
7577 }
800eeca4 7578 else if (note == 0 && !rsrc_write)
542d6675
KH
7579 {
7580 specs[count] = tmpl;
7581 specs[count++].specific = 0;
7582 }
800eeca4 7583 else
542d6675
KH
7584 {
7585 UNHANDLED;
7586 }
800eeca4
JW
7587 break;
7588
7589 case IA64_RS_IBR: /* four or more registers */
7590 if (note == 3)
542d6675
KH
7591 {
7592 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
7593 {
7594 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7595 if (regno >= 0 && regno < NELEMS (gr_values)
7596 && KNOWN (regno))
7597 {
7598 specs[count] = tmpl;
7599 specs[count++].index = gr_values[regno].value & 0xFF;
7600 }
7601 else
7602 {
7603 specs[count] = tmpl;
7604 specs[count++].specific = 0;
7605 }
7606 }
7607 }
800eeca4 7608 else
542d6675
KH
7609 {
7610 UNHANDLED;
7611 }
800eeca4
JW
7612 break;
7613
7614 case IA64_RS_MSR:
7615 if (note == 5)
7616 {
7617 /* These are implementation specific. Force all references to
7618 conflict with all other references. */
7619 specs[count] = tmpl;
7620 specs[count++].specific = 0;
7621 }
7622 else
7623 {
7624 UNHANDLED;
7625 }
7626 break;
7627
7628 case IA64_RS_PKR: /* 16 or more registers */
7629 if (note == 3 || note == 4)
542d6675
KH
7630 {
7631 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
7632 {
7633 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7634 if (regno >= 0 && regno < NELEMS (gr_values)
7635 && KNOWN (regno))
7636 {
7637 if (note == 3)
7638 {
7639 specs[count] = tmpl;
7640 specs[count++].index = gr_values[regno].value & 0xFF;
7641 }
7642 else
7643 for (i = 0; i < NELEMS (gr_values); i++)
7644 {
7645 /* Uses all registers *except* the one in R3. */
2434f565 7646 if ((unsigned)i != (gr_values[regno].value & 0xFF))
542d6675
KH
7647 {
7648 specs[count] = tmpl;
7649 specs[count++].index = i;
7650 }
7651 }
7652 }
7653 else
7654 {
7655 specs[count] = tmpl;
7656 specs[count++].specific = 0;
7657 }
7658 }
7659 }
7660 else if (note == 0)
7661 {
7662 /* probe et al. */
7663 specs[count] = tmpl;
7664 specs[count++].specific = 0;
7665 }
7666 break;
7667
7668 case IA64_RS_PMC: /* four or more registers */
7669 if (note == 3)
7670 {
7671 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7672 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7673
7674 {
7675 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7676 ? 1 : !rsrc_write);
7677 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7678 if (regno >= 0 && regno < NELEMS (gr_values)
7679 && KNOWN (regno))
7680 {
7681 specs[count] = tmpl;
7682 specs[count++].index = gr_values[regno].value & 0xFF;
7683 }
7684 else
7685 {
7686 specs[count] = tmpl;
7687 specs[count++].specific = 0;
7688 }
7689 }
7690 }
7691 else
7692 {
7693 UNHANDLED;
7694 }
800eeca4
JW
7695 break;
7696
7697 case IA64_RS_PMD: /* four or more registers */
7698 if (note == 3)
542d6675
KH
7699 {
7700 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7701 {
7702 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7703 if (regno >= 0 && regno < NELEMS (gr_values)
7704 && KNOWN (regno))
7705 {
7706 specs[count] = tmpl;
7707 specs[count++].index = gr_values[regno].value & 0xFF;
7708 }
7709 else
7710 {
7711 specs[count] = tmpl;
7712 specs[count++].specific = 0;
7713 }
7714 }
7715 }
800eeca4 7716 else
542d6675
KH
7717 {
7718 UNHANDLED;
7719 }
800eeca4
JW
7720 break;
7721
7722 case IA64_RS_RR: /* eight registers */
7723 if (note == 6)
542d6675
KH
7724 {
7725 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7726 {
7727 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7728 if (regno >= 0 && regno < NELEMS (gr_values)
7729 && KNOWN (regno))
7730 {
7731 specs[count] = tmpl;
7732 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7733 }
7734 else
7735 {
7736 specs[count] = tmpl;
7737 specs[count++].specific = 0;
7738 }
7739 }
7740 }
800eeca4 7741 else if (note == 0 && !rsrc_write)
542d6675
KH
7742 {
7743 specs[count] = tmpl;
7744 specs[count++].specific = 0;
7745 }
197865e8 7746 else
542d6675
KH
7747 {
7748 UNHANDLED;
7749 }
800eeca4
JW
7750 break;
7751
7752 case IA64_RS_CR_IRR:
197865e8 7753 if (note == 0)
542d6675
KH
7754 {
7755 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7756 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7757 if (rsrc_write
7758 && idesc->operands[1] == IA64_OPND_CR3
7759 && regno == CR_IVR)
7760 {
7761 for (i = 0; i < 4; i++)
7762 {
7763 specs[count] = tmpl;
7764 specs[count++].index = CR_IRR0 + i;
7765 }
7766 }
7767 }
800eeca4 7768 else if (note == 1)
542d6675
KH
7769 {
7770 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7771 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7772 && regno >= CR_IRR0
7773 && regno <= CR_IRR3)
7774 {
7775 specs[count] = tmpl;
7776 specs[count++].index = regno;
7777 }
7778 }
800eeca4 7779 else
542d6675
KH
7780 {
7781 UNHANDLED;
7782 }
800eeca4
JW
7783 break;
7784
7785 case IA64_RS_CR_LRR:
7786 if (note != 1)
542d6675
KH
7787 {
7788 UNHANDLED;
7789 }
197865e8 7790 else
542d6675
KH
7791 {
7792 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7793 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7794 && (regno == CR_LRR0 || regno == CR_LRR1))
7795 {
7796 specs[count] = tmpl;
7797 specs[count++].index = regno;
7798 }
7799 }
800eeca4
JW
7800 break;
7801
7802 case IA64_RS_CR:
7803 if (note == 1)
542d6675
KH
7804 {
7805 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7806 {
7807 specs[count] = tmpl;
7808 specs[count++].index =
7809 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7810 }
7811 }
800eeca4 7812 else
542d6675
KH
7813 {
7814 UNHANDLED;
7815 }
800eeca4
JW
7816 break;
7817
7818 case IA64_RS_FR:
7819 case IA64_RS_FRb:
7820 if (note != 1)
542d6675
KH
7821 {
7822 UNHANDLED;
7823 }
800eeca4 7824 else if (rsrc_write)
542d6675
KH
7825 {
7826 if (dep->specifier == IA64_RS_FRb
7827 && idesc->operands[0] == IA64_OPND_F1)
7828 {
7829 specs[count] = tmpl;
7830 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7831 }
7832 }
800eeca4 7833 else
542d6675
KH
7834 {
7835 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7836 {
7837 if (idesc->operands[i] == IA64_OPND_F2
7838 || idesc->operands[i] == IA64_OPND_F3
7839 || idesc->operands[i] == IA64_OPND_F4)
7840 {
7841 specs[count] = tmpl;
7842 specs[count++].index =
7843 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7844 }
7845 }
7846 }
800eeca4
JW
7847 break;
7848
7849 case IA64_RS_GR:
7850 if (note == 13)
542d6675
KH
7851 {
7852 /* This reference applies only to the GR whose value is loaded with
7853 data returned from memory. */
7854 specs[count] = tmpl;
7855 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7856 }
800eeca4 7857 else if (note == 1)
542d6675
KH
7858 {
7859 if (rsrc_write)
7860 {
7861 for (i = 0; i < idesc->num_outputs; i++)
50b81f19
JW
7862 if (idesc->operands[i] == IA64_OPND_R1
7863 || idesc->operands[i] == IA64_OPND_R2
7864 || idesc->operands[i] == IA64_OPND_R3)
7865 {
7866 specs[count] = tmpl;
197865e8 7867 specs[count++].index =
50b81f19
JW
7868 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7869 }
7870 if (idesc->flags & IA64_OPCODE_POSTINC)
7871 for (i = 0; i < NELEMS (idesc->operands); i++)
7872 if (idesc->operands[i] == IA64_OPND_MR3)
7873 {
7874 specs[count] = tmpl;
7875 specs[count++].index =
7876 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7877 }
542d6675
KH
7878 }
7879 else
7880 {
7881 /* Look for anything that reads a GR. */
7882 for (i = 0; i < NELEMS (idesc->operands); i++)
7883 {
7884 if (idesc->operands[i] == IA64_OPND_MR3
7885 || idesc->operands[i] == IA64_OPND_CPUID_R3
7886 || idesc->operands[i] == IA64_OPND_DBR_R3
7887 || idesc->operands[i] == IA64_OPND_IBR_R3
800eeca4 7888 || idesc->operands[i] == IA64_OPND_MSR_R3
542d6675
KH
7889 || idesc->operands[i] == IA64_OPND_PKR_R3
7890 || idesc->operands[i] == IA64_OPND_PMC_R3
7891 || idesc->operands[i] == IA64_OPND_PMD_R3
7892 || idesc->operands[i] == IA64_OPND_RR_R3
7893 || ((i >= idesc->num_outputs)
7894 && (idesc->operands[i] == IA64_OPND_R1
7895 || idesc->operands[i] == IA64_OPND_R2
7896 || idesc->operands[i] == IA64_OPND_R3
50b81f19
JW
7897 /* addl source register. */
7898 || idesc->operands[i] == IA64_OPND_R3_2)))
542d6675
KH
7899 {
7900 specs[count] = tmpl;
7901 specs[count++].index =
7902 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7903 }
7904 }
7905 }
7906 }
197865e8 7907 else
542d6675
KH
7908 {
7909 UNHANDLED;
7910 }
800eeca4
JW
7911 break;
7912
139368c9
JW
7913 /* This is the same as IA64_RS_PRr, except that the register range is
7914 from 1 - 15, and there are no rotating register reads/writes here. */
800eeca4
JW
7915 case IA64_RS_PR:
7916 if (note == 0)
542d6675 7917 {
139368c9 7918 for (i = 1; i < 16; i++)
542d6675 7919 {
139368c9
JW
7920 specs[count] = tmpl;
7921 specs[count++].index = i;
7922 }
7923 }
7924 else if (note == 7)
7925 {
7926 valueT mask = 0;
7927 /* Mark only those registers indicated by the mask. */
7928 if (rsrc_write)
7929 {
7930 mask = CURR_SLOT.opnd[2].X_add_number;
7931 for (i = 1; i < 16; i++)
7932 if (mask & ((valueT) 1 << i))
7933 {
7934 specs[count] = tmpl;
7935 specs[count++].index = i;
7936 }
7937 }
7938 else
7939 {
7940 UNHANDLED;
7941 }
7942 }
7943 else if (note == 11) /* note 11 implies note 1 as well */
7944 {
7945 if (rsrc_write)
7946 {
7947 for (i = 0; i < idesc->num_outputs; i++)
7948 {
7949 if (idesc->operands[i] == IA64_OPND_P1
7950 || idesc->operands[i] == IA64_OPND_P2)
7951 {
7952 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7953 if (regno >= 1 && regno < 16)
7954 {
7955 specs[count] = tmpl;
7956 specs[count++].index = regno;
7957 }
7958 }
7959 }
7960 }
7961 else
7962 {
7963 UNHANDLED;
7964 }
7965 }
7966 else if (note == 12)
7967 {
7968 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7969 {
7970 specs[count] = tmpl;
7971 specs[count++].index = CURR_SLOT.qp_regno;
7972 }
7973 }
7974 else if (note == 1)
7975 {
7976 if (rsrc_write)
7977 {
7978 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7979 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
07726851
KH
7980 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
7981 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
139368c9
JW
7982
7983 if ((idesc->operands[0] == IA64_OPND_P1
7984 || idesc->operands[0] == IA64_OPND_P2)
7985 && p1 >= 1 && p1 < 16)
542d6675
KH
7986 {
7987 specs[count] = tmpl;
139368c9
JW
7988 specs[count].cmp_type =
7989 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7990 specs[count++].index = p1;
7991 }
7992 if ((idesc->operands[1] == IA64_OPND_P1
7993 || idesc->operands[1] == IA64_OPND_P2)
7994 && p2 >= 1 && p2 < 16)
7995 {
7996 specs[count] = tmpl;
7997 specs[count].cmp_type =
7998 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7999 specs[count++].index = p2;
542d6675
KH
8000 }
8001 }
8002 else
8003 {
139368c9 8004 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
542d6675
KH
8005 {
8006 specs[count] = tmpl;
139368c9
JW
8007 specs[count++].index = CURR_SLOT.qp_regno;
8008 }
8009 if (idesc->operands[1] == IA64_OPND_PR)
8010 {
8011 for (i = 1; i < 16; i++)
8012 {
8013 specs[count] = tmpl;
8014 specs[count++].index = i;
8015 }
542d6675
KH
8016 }
8017 }
8018 }
139368c9
JW
8019 else
8020 {
8021 UNHANDLED;
8022 }
8023 break;
8024
8025 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
8026 simplified cases of this. */
8027 case IA64_RS_PRr:
8028 if (note == 0)
8029 {
8030 for (i = 16; i < 63; i++)
8031 {
8032 specs[count] = tmpl;
8033 specs[count++].index = i;
8034 }
8035 }
800eeca4 8036 else if (note == 7)
542d6675
KH
8037 {
8038 valueT mask = 0;
8039 /* Mark only those registers indicated by the mask. */
8040 if (rsrc_write
8041 && idesc->operands[0] == IA64_OPND_PR)
8042 {
8043 mask = CURR_SLOT.opnd[2].X_add_number;
40449e9f 8044 if (mask & ((valueT) 1 << 16))
139368c9
JW
8045 for (i = 16; i < 63; i++)
8046 {
8047 specs[count] = tmpl;
8048 specs[count++].index = i;
8049 }
542d6675
KH
8050 }
8051 else if (rsrc_write
8052 && idesc->operands[0] == IA64_OPND_PR_ROT)
8053 {
8054 for (i = 16; i < 63; i++)
8055 {
8056 specs[count] = tmpl;
8057 specs[count++].index = i;
8058 }
8059 }
8060 else
8061 {
8062 UNHANDLED;
8063 }
8064 }
800eeca4 8065 else if (note == 11) /* note 11 implies note 1 as well */
542d6675
KH
8066 {
8067 if (rsrc_write)
8068 {
8069 for (i = 0; i < idesc->num_outputs; i++)
8070 {
8071 if (idesc->operands[i] == IA64_OPND_P1
8072 || idesc->operands[i] == IA64_OPND_P2)
8073 {
8074 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
139368c9 8075 if (regno >= 16 && regno < 63)
542d6675
KH
8076 {
8077 specs[count] = tmpl;
8078 specs[count++].index = regno;
8079 }
8080 }
8081 }
8082 }
8083 else
8084 {
8085 UNHANDLED;
8086 }
8087 }
800eeca4 8088 else if (note == 12)
542d6675 8089 {
139368c9 8090 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH
8091 {
8092 specs[count] = tmpl;
8093 specs[count++].index = CURR_SLOT.qp_regno;
8094 }
8095 }
800eeca4 8096 else if (note == 1)
542d6675
KH
8097 {
8098 if (rsrc_write)
8099 {
8100 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8101 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
07726851
KH
8102 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
8103 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
7484b8e6 8104
542d6675
KH
8105 if ((idesc->operands[0] == IA64_OPND_P1
8106 || idesc->operands[0] == IA64_OPND_P2)
139368c9 8107 && p1 >= 16 && p1 < 63)
542d6675
KH
8108 {
8109 specs[count] = tmpl;
4a4f25cf 8110 specs[count].cmp_type =
7484b8e6 8111 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
542d6675
KH
8112 specs[count++].index = p1;
8113 }
8114 if ((idesc->operands[1] == IA64_OPND_P1
8115 || idesc->operands[1] == IA64_OPND_P2)
139368c9 8116 && p2 >= 16 && p2 < 63)
542d6675
KH
8117 {
8118 specs[count] = tmpl;
4a4f25cf 8119 specs[count].cmp_type =
7484b8e6 8120 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
542d6675
KH
8121 specs[count++].index = p2;
8122 }
8123 }
8124 else
8125 {
139368c9 8126 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH
8127 {
8128 specs[count] = tmpl;
8129 specs[count++].index = CURR_SLOT.qp_regno;
8130 }
8131 if (idesc->operands[1] == IA64_OPND_PR)
8132 {
139368c9 8133 for (i = 16; i < 63; i++)
542d6675
KH
8134 {
8135 specs[count] = tmpl;
8136 specs[count++].index = i;
8137 }
8138 }
8139 }
8140 }
197865e8 8141 else
542d6675
KH
8142 {
8143 UNHANDLED;
8144 }
800eeca4
JW
8145 break;
8146
8147 case IA64_RS_PSR:
197865e8 8148 /* Verify that the instruction is using the PSR bit indicated in
542d6675 8149 dep->regindex. */
800eeca4 8150 if (note == 0)
542d6675
KH
8151 {
8152 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
8153 {
8154 if (dep->regindex < 6)
8155 {
8156 specs[count++] = tmpl;
8157 }
8158 }
8159 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
8160 {
8161 if (dep->regindex < 32
8162 || dep->regindex == 35
8163 || dep->regindex == 36
8164 || (!rsrc_write && dep->regindex == PSR_CPL))
8165 {
8166 specs[count++] = tmpl;
8167 }
8168 }
8169 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
8170 {
8171 if (dep->regindex < 32
8172 || dep->regindex == 35
8173 || dep->regindex == 36
8174 || (rsrc_write && dep->regindex == PSR_CPL))
8175 {
8176 specs[count++] = tmpl;
8177 }
8178 }
8179 else
8180 {
8181 /* Several PSR bits have very specific dependencies. */
8182 switch (dep->regindex)
8183 {
8184 default:
8185 specs[count++] = tmpl;
8186 break;
8187 case PSR_IC:
8188 if (rsrc_write)
8189 {
8190 specs[count++] = tmpl;
8191 }
8192 else
8193 {
8194 /* Only certain CR accesses use PSR.ic */
8195 if (idesc->operands[0] == IA64_OPND_CR3
8196 || idesc->operands[1] == IA64_OPND_CR3)
8197 {
8198 int index =
8199 ((idesc->operands[0] == IA64_OPND_CR3)
8200 ? 0 : 1);
8201 int regno =
8202 CURR_SLOT.opnd[index].X_add_number - REG_CR;
8203
8204 switch (regno)
8205 {
8206 default:
8207 break;
8208 case CR_ITIR:
8209 case CR_IFS:
8210 case CR_IIM:
8211 case CR_IIP:
8212 case CR_IPSR:
8213 case CR_ISR:
8214 case CR_IFA:
8215 case CR_IHA:
8216 case CR_IIPA:
8217 specs[count++] = tmpl;
8218 break;
8219 }
8220 }
8221 }
8222 break;
8223 case PSR_CPL:
8224 if (rsrc_write)
8225 {
8226 specs[count++] = tmpl;
8227 }
8228 else
8229 {
8230 /* Only some AR accesses use cpl */
8231 if (idesc->operands[0] == IA64_OPND_AR3
8232 || idesc->operands[1] == IA64_OPND_AR3)
8233 {
8234 int index =
8235 ((idesc->operands[0] == IA64_OPND_AR3)
8236 ? 0 : 1);
8237 int regno =
8238 CURR_SLOT.opnd[index].X_add_number - REG_AR;
8239
8240 if (regno == AR_ITC
8241 || (index == 0
8242 && (regno == AR_ITC
8243 || regno == AR_RSC
8244 || (regno >= AR_K0
8245 && regno <= AR_K7))))
8246 {
8247 specs[count++] = tmpl;
8248 }
8249 }
8250 else
8251 {
8252 specs[count++] = tmpl;
8253 }
8254 break;
8255 }
8256 }
8257 }
8258 }
800eeca4 8259 else if (note == 7)
542d6675
KH
8260 {
8261 valueT mask = 0;
8262 if (idesc->operands[0] == IA64_OPND_IMMU24)
8263 {
8264 mask = CURR_SLOT.opnd[0].X_add_number;
8265 }
8266 else
8267 {
8268 UNHANDLED;
8269 }
8270 if (mask & ((valueT) 1 << dep->regindex))
8271 {
8272 specs[count++] = tmpl;
8273 }
8274 }
800eeca4 8275 else if (note == 8)
542d6675
KH
8276 {
8277 int min = dep->regindex == PSR_DFL ? 2 : 32;
8278 int max = dep->regindex == PSR_DFL ? 31 : 127;
8279 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8280 for (i = 0; i < NELEMS (idesc->operands); i++)
8281 {
8282 if (idesc->operands[i] == IA64_OPND_F1
8283 || idesc->operands[i] == IA64_OPND_F2
8284 || idesc->operands[i] == IA64_OPND_F3
8285 || idesc->operands[i] == IA64_OPND_F4)
8286 {
8287 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8288 if (reg >= min && reg <= max)
8289 {
8290 specs[count++] = tmpl;
8291 }
8292 }
8293 }
8294 }
800eeca4 8295 else if (note == 9)
542d6675
KH
8296 {
8297 int min = dep->regindex == PSR_MFL ? 2 : 32;
8298 int max = dep->regindex == PSR_MFL ? 31 : 127;
8299 /* mfh is read on writes to FR32-127; mfl is read on writes to
8300 FR2-31 */
8301 for (i = 0; i < idesc->num_outputs; i++)
8302 {
8303 if (idesc->operands[i] == IA64_OPND_F1)
8304 {
8305 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8306 if (reg >= min && reg <= max)
8307 {
8308 specs[count++] = tmpl;
8309 }
8310 }
8311 }
8312 }
800eeca4 8313 else if (note == 10)
542d6675
KH
8314 {
8315 for (i = 0; i < NELEMS (idesc->operands); i++)
8316 {
8317 if (idesc->operands[i] == IA64_OPND_R1
8318 || idesc->operands[i] == IA64_OPND_R2
8319 || idesc->operands[i] == IA64_OPND_R3)
8320 {
8321 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8322 if (regno >= 16 && regno <= 31)
8323 {
8324 specs[count++] = tmpl;
8325 }
8326 }
8327 }
8328 }
800eeca4 8329 else
542d6675
KH
8330 {
8331 UNHANDLED;
8332 }
800eeca4
JW
8333 break;
8334
8335 case IA64_RS_AR_FPSR:
8336 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
542d6675
KH
8337 {
8338 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8339 if (regno == AR_FPSR)
8340 {
8341 specs[count++] = tmpl;
8342 }
8343 }
800eeca4 8344 else
542d6675
KH
8345 {
8346 specs[count++] = tmpl;
8347 }
800eeca4
JW
8348 break;
8349
197865e8 8350 case IA64_RS_ARX:
800eeca4
JW
8351 /* Handle all AR[REG] resources */
8352 if (note == 0 || note == 1)
542d6675
KH
8353 {
8354 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8355 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
8356 && regno == dep->regindex)
8357 {
8358 specs[count++] = tmpl;
8359 }
8360 /* other AR[REG] resources may be affected by AR accesses */
8361 else if (idesc->operands[0] == IA64_OPND_AR3)
8362 {
8363 /* AR[] writes */
8364 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
8365 switch (dep->regindex)
8366 {
8367 default:
8368 break;
8369 case AR_BSP:
8370 case AR_RNAT:
8371 if (regno == AR_BSPSTORE)
8372 {
8373 specs[count++] = tmpl;
8374 }
8375 case AR_RSC:
8376 if (!rsrc_write &&
8377 (regno == AR_BSPSTORE
8378 || regno == AR_RNAT))
8379 {
8380 specs[count++] = tmpl;
8381 }
8382 break;
8383 }
8384 }
8385 else if (idesc->operands[1] == IA64_OPND_AR3)
8386 {
8387 /* AR[] reads */
8388 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
8389 switch (dep->regindex)
8390 {
8391 default:
8392 break;
8393 case AR_RSC:
8394 if (regno == AR_BSPSTORE || regno == AR_RNAT)
8395 {
8396 specs[count++] = tmpl;
8397 }
8398 break;
8399 }
8400 }
8401 else
8402 {
8403 specs[count++] = tmpl;
8404 }
8405 }
800eeca4 8406 else
542d6675
KH
8407 {
8408 UNHANDLED;
8409 }
800eeca4
JW
8410 break;
8411
8412 case IA64_RS_CRX:
8413 /* Handle all CR[REG] resources */
8414 if (note == 0 || note == 1)
542d6675
KH
8415 {
8416 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
8417 {
8418 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
8419 if (regno == dep->regindex)
8420 {
8421 specs[count++] = tmpl;
8422 }
8423 else if (!rsrc_write)
8424 {
8425 /* Reads from CR[IVR] affect other resources. */
8426 if (regno == CR_IVR)
8427 {
8428 if ((dep->regindex >= CR_IRR0
8429 && dep->regindex <= CR_IRR3)
8430 || dep->regindex == CR_TPR)
8431 {
8432 specs[count++] = tmpl;
8433 }
8434 }
8435 }
8436 }
8437 else
8438 {
8439 specs[count++] = tmpl;
8440 }
8441 }
800eeca4 8442 else
542d6675
KH
8443 {
8444 UNHANDLED;
8445 }
800eeca4
JW
8446 break;
8447
8448 case IA64_RS_INSERVICE:
8449 /* look for write of EOI (67) or read of IVR (65) */
8450 if ((idesc->operands[0] == IA64_OPND_CR3
542d6675
KH
8451 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
8452 || (idesc->operands[1] == IA64_OPND_CR3
8453 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
8454 {
8455 specs[count++] = tmpl;
8456 }
800eeca4
JW
8457 break;
8458
8459 case IA64_RS_GR0:
8460 if (note == 1)
542d6675
KH
8461 {
8462 specs[count++] = tmpl;
8463 }
800eeca4 8464 else
542d6675
KH
8465 {
8466 UNHANDLED;
8467 }
800eeca4
JW
8468 break;
8469
8470 case IA64_RS_CFM:
8471 if (note != 2)
542d6675
KH
8472 {
8473 specs[count++] = tmpl;
8474 }
800eeca4 8475 else
542d6675
KH
8476 {
8477 /* Check if any of the registers accessed are in the rotating region.
8478 mov to/from pr accesses CFM only when qp_regno is in the rotating
8479 region */
8480 for (i = 0; i < NELEMS (idesc->operands); i++)
8481 {
8482 if (idesc->operands[i] == IA64_OPND_R1
8483 || idesc->operands[i] == IA64_OPND_R2
8484 || idesc->operands[i] == IA64_OPND_R3)
8485 {
8486 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8487 /* Assumes that md.rot.num_regs is always valid */
8488 if (md.rot.num_regs > 0
8489 && num > 31
8490 && num < 31 + md.rot.num_regs)
8491 {
8492 specs[count] = tmpl;
8493 specs[count++].specific = 0;
8494 }
8495 }
8496 else if (idesc->operands[i] == IA64_OPND_F1
8497 || idesc->operands[i] == IA64_OPND_F2
8498 || idesc->operands[i] == IA64_OPND_F3
8499 || idesc->operands[i] == IA64_OPND_F4)
8500 {
8501 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8502 if (num > 31)
8503 {
8504 specs[count] = tmpl;
8505 specs[count++].specific = 0;
8506 }
8507 }
8508 else if (idesc->operands[i] == IA64_OPND_P1
8509 || idesc->operands[i] == IA64_OPND_P2)
8510 {
8511 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
8512 if (num > 15)
8513 {
8514 specs[count] = tmpl;
8515 specs[count++].specific = 0;
8516 }
8517 }
8518 }
8519 if (CURR_SLOT.qp_regno > 15)
8520 {
8521 specs[count] = tmpl;
8522 specs[count++].specific = 0;
8523 }
8524 }
800eeca4
JW
8525 break;
8526
139368c9
JW
8527 /* This is the same as IA64_RS_PRr, except simplified to account for
8528 the fact that there is only one register. */
800eeca4
JW
8529 case IA64_RS_PR63:
8530 if (note == 0)
542d6675
KH
8531 {
8532 specs[count++] = tmpl;
8533 }
139368c9 8534 else if (note == 7)
40449e9f
KH
8535 {
8536 valueT mask = 0;
8537 if (idesc->operands[2] == IA64_OPND_IMM17)
8538 mask = CURR_SLOT.opnd[2].X_add_number;
8539 if (mask & ((valueT) 1 << 63))
139368c9 8540 specs[count++] = tmpl;
40449e9f 8541 }
800eeca4 8542 else if (note == 11)
542d6675
KH
8543 {
8544 if ((idesc->operands[0] == IA64_OPND_P1
8545 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
8546 || (idesc->operands[1] == IA64_OPND_P2
8547 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
8548 {
8549 specs[count++] = tmpl;
8550 }
8551 }
800eeca4 8552 else if (note == 12)
542d6675
KH
8553 {
8554 if (CURR_SLOT.qp_regno == 63)
8555 {
8556 specs[count++] = tmpl;
8557 }
8558 }
800eeca4 8559 else if (note == 1)
542d6675
KH
8560 {
8561 if (rsrc_write)
8562 {
40449e9f
KH
8563 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8564 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
07726851
KH
8565 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
8566 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
7484b8e6 8567
4a4f25cf 8568 if (p1 == 63
7484b8e6
TW
8569 && (idesc->operands[0] == IA64_OPND_P1
8570 || idesc->operands[0] == IA64_OPND_P2))
8571 {
40449e9f 8572 specs[count] = tmpl;
4a4f25cf 8573 specs[count++].cmp_type =
7484b8e6
TW
8574 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8575 }
8576 if (p2 == 63
8577 && (idesc->operands[1] == IA64_OPND_P1
8578 || idesc->operands[1] == IA64_OPND_P2))
8579 {
40449e9f 8580 specs[count] = tmpl;
4a4f25cf 8581 specs[count++].cmp_type =
7484b8e6
TW
8582 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8583 }
542d6675
KH
8584 }
8585 else
8586 {
8587 if (CURR_SLOT.qp_regno == 63)
8588 {
8589 specs[count++] = tmpl;
8590 }
8591 }
8592 }
800eeca4 8593 else
542d6675
KH
8594 {
8595 UNHANDLED;
8596 }
800eeca4
JW
8597 break;
8598
8599 case IA64_RS_RSE:
8600 /* FIXME we can identify some individual RSE written resources, but RSE
542d6675
KH
8601 read resources have not yet been completely identified, so for now
8602 treat RSE as a single resource */
800eeca4 8603 if (strncmp (idesc->name, "mov", 3) == 0)
542d6675
KH
8604 {
8605 if (rsrc_write)
8606 {
8607 if (idesc->operands[0] == IA64_OPND_AR3
8608 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
8609 {
8610 specs[count] = tmpl;
8611 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8612 }
8613 }
8614 else
8615 {
8616 if (idesc->operands[0] == IA64_OPND_AR3)
8617 {
8618 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
8619 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
8620 {
8621 specs[count++] = tmpl;
8622 }
8623 }
8624 else if (idesc->operands[1] == IA64_OPND_AR3)
8625 {
8626 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
8627 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
8628 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
8629 {
8630 specs[count++] = tmpl;
8631 }
8632 }
8633 }
8634 }
197865e8 8635 else
542d6675
KH
8636 {
8637 specs[count++] = tmpl;
8638 }
800eeca4
JW
8639 break;
8640
8641 case IA64_RS_ANY:
8642 /* FIXME -- do any of these need to be non-specific? */
8643 specs[count++] = tmpl;
8644 break;
8645
8646 default:
8647 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
8648 break;
8649 }
8650
8651 return count;
8652}
8653
8654/* Clear branch flags on marked resources. This breaks the link between the
542d6675
KH
8655 QP of the marking instruction and a subsequent branch on the same QP. */
8656
800eeca4
JW
8657static void
8658clear_qp_branch_flag (mask)
542d6675 8659 valueT mask;
800eeca4
JW
8660{
8661 int i;
542d6675 8662 for (i = 0; i < regdepslen; i++)
800eeca4 8663 {
197865e8 8664 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4 8665 if ((bit & mask) != 0)
542d6675
KH
8666 {
8667 regdeps[i].link_to_qp_branch = 0;
8668 }
800eeca4
JW
8669 }
8670}
8671
197865e8 8672/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4 8673
542d6675
KH
8674 Any changes to a PR clears the mutex relations which include that PR. */
8675
800eeca4
JW
8676static void
8677clear_qp_mutex (mask)
542d6675 8678 valueT mask;
800eeca4
JW
8679{
8680 int i;
8681
8682 i = 0;
8683 while (i < qp_mutexeslen)
8684 {
8685 if ((qp_mutexes[i].prmask & mask) != 0)
542d6675
KH
8686 {
8687 if (md.debug_dv)
8688 {
8689 fprintf (stderr, " Clearing mutex relation");
8690 print_prmask (qp_mutexes[i].prmask);
8691 fprintf (stderr, "\n");
8692 }
8693 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8694 }
800eeca4 8695 else
542d6675 8696 ++i;
800eeca4
JW
8697 }
8698}
8699
8700/* Clear implies relations which contain PRs in the given masks.
8701 P1_MASK indicates the source of the implies relation, while P2_MASK
542d6675
KH
8702 indicates the implied PR. */
8703
800eeca4
JW
8704static void
8705clear_qp_implies (p1_mask, p2_mask)
542d6675
KH
8706 valueT p1_mask;
8707 valueT p2_mask;
800eeca4
JW
8708{
8709 int i;
8710
8711 i = 0;
8712 while (i < qp_implieslen)
8713 {
197865e8 8714 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
542d6675
KH
8715 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8716 {
8717 if (md.debug_dv)
8718 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8719 qp_implies[i].p1, qp_implies[i].p2);
8720 qp_implies[i] = qp_implies[--qp_implieslen];
8721 }
197865e8 8722 else
542d6675 8723 ++i;
800eeca4
JW
8724 }
8725}
8726
542d6675
KH
8727/* Add the PRs specified to the list of implied relations. */
8728
800eeca4
JW
8729static void
8730add_qp_imply (p1, p2)
542d6675 8731 int p1, p2;
800eeca4
JW
8732{
8733 valueT mask;
8734 valueT bit;
8735 int i;
8736
542d6675 8737 /* p0 is not meaningful here. */
800eeca4
JW
8738 if (p1 == 0 || p2 == 0)
8739 abort ();
8740
8741 if (p1 == p2)
8742 return;
8743
542d6675
KH
8744 /* If it exists already, ignore it. */
8745 for (i = 0; i < qp_implieslen; i++)
800eeca4 8746 {
197865e8 8747 if (qp_implies[i].p1 == p1
542d6675
KH
8748 && qp_implies[i].p2 == p2
8749 && qp_implies[i].path == md.path
8750 && !qp_implies[i].p2_branched)
8751 return;
800eeca4
JW
8752 }
8753
8754 if (qp_implieslen == qp_impliestotlen)
8755 {
8756 qp_impliestotlen += 20;
8757 qp_implies = (struct qp_imply *)
542d6675
KH
8758 xrealloc ((void *) qp_implies,
8759 qp_impliestotlen * sizeof (struct qp_imply));
800eeca4
JW
8760 }
8761 if (md.debug_dv)
8762 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8763 qp_implies[qp_implieslen].p1 = p1;
8764 qp_implies[qp_implieslen].p2 = p2;
8765 qp_implies[qp_implieslen].path = md.path;
8766 qp_implies[qp_implieslen++].p2_branched = 0;
8767
8768 /* Add in the implied transitive relations; for everything that p2 implies,
8769 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 8770 as well. */
542d6675 8771 for (i = 0; i < qp_implieslen; i++)
800eeca4
JW
8772 {
8773 if (qp_implies[i].p1 == p2)
542d6675 8774 add_qp_imply (p1, qp_implies[i].p2);
800eeca4 8775 if (qp_implies[i].p2 == p1)
542d6675 8776 add_qp_imply (qp_implies[i].p1, p2);
800eeca4
JW
8777 }
8778 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH
8779 relation containing p2, duplicate it and replace p2 with p1. */
8780 bit = (valueT) 1 << p1;
8781 mask = (valueT) 1 << p2;
542d6675 8782 for (i = 0; i < qp_mutexeslen; i++)
800eeca4
JW
8783 {
8784 if (qp_mutexes[i].prmask & mask)
542d6675 8785 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
800eeca4
JW
8786 }
8787}
8788
800eeca4
JW
8789/* Add the PRs specified in the mask to the mutex list; this means that only
8790 one of the PRs can be true at any time. PR0 should never be included in
8791 the mask. */
542d6675 8792
800eeca4
JW
8793static void
8794add_qp_mutex (mask)
542d6675 8795 valueT mask;
800eeca4
JW
8796{
8797 if (mask & 0x1)
8798 abort ();
8799
8800 if (qp_mutexeslen == qp_mutexestotlen)
8801 {
8802 qp_mutexestotlen += 20;
8803 qp_mutexes = (struct qpmutex *)
542d6675
KH
8804 xrealloc ((void *) qp_mutexes,
8805 qp_mutexestotlen * sizeof (struct qpmutex));
800eeca4
JW
8806 }
8807 if (md.debug_dv)
8808 {
8809 fprintf (stderr, " Registering mutex on");
8810 print_prmask (mask);
8811 fprintf (stderr, "\n");
8812 }
8813 qp_mutexes[qp_mutexeslen].path = md.path;
8814 qp_mutexes[qp_mutexeslen++].prmask = mask;
8815}
8816
cb5301b6
RH
8817static int
8818has_suffix_p (name, suffix)
40449e9f
KH
8819 const char *name;
8820 const char *suffix;
cb5301b6
RH
8821{
8822 size_t namelen = strlen (name);
8823 size_t sufflen = strlen (suffix);
8824
8825 if (namelen <= sufflen)
8826 return 0;
8827 return strcmp (name + namelen - sufflen, suffix) == 0;
8828}
8829
800eeca4
JW
8830static void
8831clear_register_values ()
8832{
8833 int i;
8834 if (md.debug_dv)
8835 fprintf (stderr, " Clearing register values\n");
542d6675 8836 for (i = 1; i < NELEMS (gr_values); i++)
800eeca4
JW
8837 gr_values[i].known = 0;
8838}
8839
8840/* Keep track of register values/changes which affect DV tracking.
8841
8842 optimization note: should add a flag to classes of insns where otherwise we
542d6675 8843 have to examine a group of strings to identify them. */
800eeca4 8844
800eeca4
JW
8845static void
8846note_register_values (idesc)
542d6675 8847 struct ia64_opcode *idesc;
800eeca4
JW
8848{
8849 valueT qp_changemask = 0;
8850 int i;
8851
542d6675
KH
8852 /* Invalidate values for registers being written to. */
8853 for (i = 0; i < idesc->num_outputs; i++)
800eeca4 8854 {
197865e8 8855 if (idesc->operands[i] == IA64_OPND_R1
542d6675
KH
8856 || idesc->operands[i] == IA64_OPND_R2
8857 || idesc->operands[i] == IA64_OPND_R3)
8858 {
8859 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8860 if (regno > 0 && regno < NELEMS (gr_values))
8861 gr_values[regno].known = 0;
8862 }
50b81f19
JW
8863 else if (idesc->operands[i] == IA64_OPND_R3_2)
8864 {
8865 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8866 if (regno > 0 && regno < 4)
8867 gr_values[regno].known = 0;
8868 }
197865e8 8869 else if (idesc->operands[i] == IA64_OPND_P1
542d6675
KH
8870 || idesc->operands[i] == IA64_OPND_P2)
8871 {
8872 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8873 qp_changemask |= (valueT) 1 << regno;
8874 }
800eeca4 8875 else if (idesc->operands[i] == IA64_OPND_PR)
542d6675
KH
8876 {
8877 if (idesc->operands[2] & (valueT) 0x10000)
8878 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8879 else
8880 qp_changemask = idesc->operands[2];
8881 break;
8882 }
800eeca4 8883 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
542d6675
KH
8884 {
8885 if (idesc->operands[1] & ((valueT) 1 << 43))
8886 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8887 else
8888 qp_changemask = idesc->operands[1];
8889 qp_changemask &= ~(valueT) 0xFFFF;
8890 break;
8891 }
8892 }
8893
8894 /* Always clear qp branch flags on any PR change. */
8895 /* FIXME there may be exceptions for certain compares. */
800eeca4
JW
8896 clear_qp_branch_flag (qp_changemask);
8897
542d6675 8898 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
800eeca4
JW
8899 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8900 {
197865e8 8901 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4 8902 if (strcmp (idesc->name, "clrrrb.pr") != 0)
542d6675
KH
8903 {
8904 for (i = 32; i < 32 + md.rot.num_regs; i++)
8905 gr_values[i].known = 0;
8906 }
800eeca4
JW
8907 clear_qp_mutex (qp_changemask);
8908 clear_qp_implies (qp_changemask, qp_changemask);
8909 }
542d6675
KH
8910 /* After a call, all register values are undefined, except those marked
8911 as "safe". */
800eeca4 8912 else if (strncmp (idesc->name, "br.call", 6) == 0
542d6675 8913 || strncmp (idesc->name, "brl.call", 7) == 0)
800eeca4 8914 {
56d27c17 8915 /* FIXME keep GR values which are marked as "safe_across_calls" */
800eeca4
JW
8916 clear_register_values ();
8917 clear_qp_mutex (~qp_safe_across_calls);
8918 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8919 clear_qp_branch_flag (~qp_safe_across_calls);
8920 }
e9718fe1 8921 else if (is_interruption_or_rfi (idesc)
542d6675 8922 || is_taken_branch (idesc))
e9718fe1
TW
8923 {
8924 clear_register_values ();
197865e8
KH
8925 clear_qp_mutex (~(valueT) 0);
8926 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 8927 }
542d6675 8928 /* Look for mutex and implies relations. */
197865e8 8929 else if ((idesc->operands[0] == IA64_OPND_P1
542d6675
KH
8930 || idesc->operands[0] == IA64_OPND_P2)
8931 && (idesc->operands[1] == IA64_OPND_P1
8932 || idesc->operands[1] == IA64_OPND_P2))
800eeca4
JW
8933 {
8934 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH
8935 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8936 valueT p1mask = (valueT) 1 << p1;
8937 valueT p2mask = (valueT) 1 << p2;
800eeca4 8938
542d6675 8939 /* If one of the PRs is PR0, we can't really do anything. */
800eeca4 8940 if (p1 == 0 || p2 == 0)
542d6675
KH
8941 {
8942 if (md.debug_dv)
8943 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8944 }
800eeca4 8945 /* In general, clear mutexes and implies which include P1 or P2,
542d6675 8946 with the following exceptions. */
cb5301b6
RH
8947 else if (has_suffix_p (idesc->name, ".or.andcm")
8948 || has_suffix_p (idesc->name, ".and.orcm"))
542d6675
KH
8949 {
8950 add_qp_mutex (p1mask | p2mask);
8951 clear_qp_implies (p2mask, p1mask);
8952 }
cb5301b6
RH
8953 else if (has_suffix_p (idesc->name, ".andcm")
8954 || has_suffix_p (idesc->name, ".and"))
542d6675
KH
8955 {
8956 clear_qp_implies (0, p1mask | p2mask);
8957 }
cb5301b6
RH
8958 else if (has_suffix_p (idesc->name, ".orcm")
8959 || has_suffix_p (idesc->name, ".or"))
542d6675
KH
8960 {
8961 clear_qp_mutex (p1mask | p2mask);
8962 clear_qp_implies (p1mask | p2mask, 0);
8963 }
800eeca4 8964 else
542d6675
KH
8965 {
8966 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
cb5301b6 8967 if (has_suffix_p (idesc->name, ".unc"))
542d6675
KH
8968 {
8969 add_qp_mutex (p1mask | p2mask);
8970 if (CURR_SLOT.qp_regno != 0)
8971 {
8972 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8973 CURR_SLOT.qp_regno);
8974 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8975 CURR_SLOT.qp_regno);
8976 }
8977 }
8978 else if (CURR_SLOT.qp_regno == 0)
8979 {
8980 add_qp_mutex (p1mask | p2mask);
8981 }
8982 else
8983 {
8984 clear_qp_mutex (p1mask | p2mask);
8985 }
8986 }
8987 }
8988 /* Look for mov imm insns into GRs. */
800eeca4 8989 else if (idesc->operands[0] == IA64_OPND_R1
542d6675
KH
8990 && (idesc->operands[1] == IA64_OPND_IMM22
8991 || idesc->operands[1] == IA64_OPND_IMMU64)
8992 && (strcmp (idesc->name, "mov") == 0
8993 || strcmp (idesc->name, "movl") == 0))
800eeca4
JW
8994 {
8995 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
542d6675
KH
8996 if (regno > 0 && regno < NELEMS (gr_values))
8997 {
8998 gr_values[regno].known = 1;
8999 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
9000 gr_values[regno].path = md.path;
9001 if (md.debug_dv)
2434f565
JW
9002 {
9003 fprintf (stderr, " Know gr%d = ", regno);
9004 fprintf_vma (stderr, gr_values[regno].value);
9005 fputs ("\n", stderr);
9006 }
542d6675 9007 }
800eeca4 9008 }
197865e8 9009 else
800eeca4
JW
9010 {
9011 clear_qp_mutex (qp_changemask);
9012 clear_qp_implies (qp_changemask, qp_changemask);
9013 }
9014}
9015
542d6675
KH
9016/* Return whether the given predicate registers are currently mutex. */
9017
800eeca4
JW
9018static int
9019qp_mutex (p1, p2, path)
542d6675
KH
9020 int p1;
9021 int p2;
9022 int path;
800eeca4
JW
9023{
9024 int i;
9025 valueT mask;
9026
9027 if (p1 != p2)
9028 {
542d6675
KH
9029 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
9030 for (i = 0; i < qp_mutexeslen; i++)
9031 {
9032 if (qp_mutexes[i].path >= path
9033 && (qp_mutexes[i].prmask & mask) == mask)
9034 return 1;
9035 }
800eeca4
JW
9036 }
9037 return 0;
9038}
9039
9040/* Return whether the given resource is in the given insn's list of chks
9041 Return 1 if the conflict is absolutely determined, 2 if it's a potential
542d6675
KH
9042 conflict. */
9043
800eeca4
JW
9044static int
9045resources_match (rs, idesc, note, qp_regno, path)
542d6675
KH
9046 struct rsrc *rs;
9047 struct ia64_opcode *idesc;
9048 int note;
9049 int qp_regno;
9050 int path;
800eeca4
JW
9051{
9052 struct rsrc specs[MAX_SPECS];
9053 int count;
9054
9055 /* If the marked resource's qp_regno and the given qp_regno are mutex,
9056 we don't need to check. One exception is note 11, which indicates that
9057 target predicates are written regardless of PR[qp]. */
197865e8 9058 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW
9059 && note != 11)
9060 return 0;
9061
9062 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
9063 while (count-- > 0)
9064 {
9065 /* UNAT checking is a bit more specific than other resources */
9066 if (rs->dependency->specifier == IA64_RS_AR_UNAT
542d6675
KH
9067 && specs[count].mem_offset.hint
9068 && rs->mem_offset.hint)
9069 {
9070 if (rs->mem_offset.base == specs[count].mem_offset.base)
9071 {
9072 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
9073 ((specs[count].mem_offset.offset >> 3) & 0x3F))
9074 return 1;
9075 else
9076 continue;
9077 }
9078 }
800eeca4 9079
7484b8e6 9080 /* Skip apparent PR write conflicts where both writes are an AND or both
4a4f25cf 9081 writes are an OR. */
7484b8e6 9082 if (rs->dependency->specifier == IA64_RS_PR
afa680f8 9083 || rs->dependency->specifier == IA64_RS_PRr
7484b8e6
TW
9084 || rs->dependency->specifier == IA64_RS_PR63)
9085 {
9086 if (specs[count].cmp_type != CMP_NONE
9087 && specs[count].cmp_type == rs->cmp_type)
9088 {
9089 if (md.debug_dv)
9090 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
9091 dv_mode[rs->dependency->mode],
afa680f8 9092 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6
TW
9093 specs[count].index : 63);
9094 continue;
9095 }
9096 if (md.debug_dv)
4a4f25cf 9097 fprintf (stderr,
7484b8e6
TW
9098 " %s on parallel compare conflict %s vs %s on PR%d\n",
9099 dv_mode[rs->dependency->mode],
4a4f25cf 9100 dv_cmp_type[rs->cmp_type],
7484b8e6 9101 dv_cmp_type[specs[count].cmp_type],
afa680f8 9102 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6 9103 specs[count].index : 63);
4a4f25cf 9104
7484b8e6
TW
9105 }
9106
800eeca4 9107 /* If either resource is not specific, conservatively assume a conflict
197865e8 9108 */
800eeca4 9109 if (!specs[count].specific || !rs->specific)
542d6675 9110 return 2;
800eeca4 9111 else if (specs[count].index == rs->index)
542d6675 9112 return 1;
800eeca4
JW
9113 }
9114#if 0
9115 if (md.debug_dv)
9116 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
9117#endif
9118
9119 return 0;
9120}
9121
9122/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
9123 insert a stop to create the break. Update all resource dependencies
9124 appropriately. If QP_REGNO is non-zero, only apply the break to resources
9125 which use the same QP_REGNO and have the link_to_qp_branch flag set.
9126 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
542d6675 9127 instruction. */
800eeca4
JW
9128
9129static void
9130insn_group_break (insert_stop, qp_regno, save_current)
542d6675
KH
9131 int insert_stop;
9132 int qp_regno;
9133 int save_current;
800eeca4
JW
9134{
9135 int i;
9136
9137 if (insert_stop && md.num_slots_in_use > 0)
9138 PREV_SLOT.end_of_insn_group = 1;
9139
9140 if (md.debug_dv)
9141 {
197865e8 9142 fprintf (stderr, " Insn group break%s",
542d6675 9143 (insert_stop ? " (w/stop)" : ""));
800eeca4 9144 if (qp_regno != 0)
542d6675 9145 fprintf (stderr, " effective for QP=%d", qp_regno);
800eeca4
JW
9146 fprintf (stderr, "\n");
9147 }
9148
9149 i = 0;
9150 while (i < regdepslen)
9151 {
9152 const struct ia64_dependency *dep = regdeps[i].dependency;
9153
9154 if (qp_regno != 0
542d6675
KH
9155 && regdeps[i].qp_regno != qp_regno)
9156 {
9157 ++i;
9158 continue;
9159 }
800eeca4
JW
9160
9161 if (save_current
542d6675
KH
9162 && CURR_SLOT.src_file == regdeps[i].file
9163 && CURR_SLOT.src_line == regdeps[i].line)
9164 {
9165 ++i;
9166 continue;
9167 }
800eeca4
JW
9168
9169 /* clear dependencies which are automatically cleared by a stop, or
542d6675 9170 those that have reached the appropriate state of insn serialization */
800eeca4 9171 if (dep->semantics == IA64_DVS_IMPLIED
542d6675
KH
9172 || dep->semantics == IA64_DVS_IMPLIEDF
9173 || regdeps[i].insn_srlz == STATE_SRLZ)
9174 {
9175 print_dependency ("Removing", i);
9176 regdeps[i] = regdeps[--regdepslen];
9177 }
800eeca4 9178 else
542d6675
KH
9179 {
9180 if (dep->semantics == IA64_DVS_DATA
9181 || dep->semantics == IA64_DVS_INSTR
800eeca4 9182 || dep->semantics == IA64_DVS_SPECIFIC)
542d6675
KH
9183 {
9184 if (regdeps[i].insn_srlz == STATE_NONE)
9185 regdeps[i].insn_srlz = STATE_STOP;
9186 if (regdeps[i].data_srlz == STATE_NONE)
9187 regdeps[i].data_srlz = STATE_STOP;
9188 }
9189 ++i;
9190 }
800eeca4
JW
9191 }
9192}
9193
542d6675
KH
9194/* Add the given resource usage spec to the list of active dependencies. */
9195
197865e8 9196static void
800eeca4 9197mark_resource (idesc, dep, spec, depind, path)
2434f565
JW
9198 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
9199 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
542d6675
KH
9200 struct rsrc *spec;
9201 int depind;
9202 int path;
800eeca4
JW
9203{
9204 if (regdepslen == regdepstotlen)
9205 {
9206 regdepstotlen += 20;
9207 regdeps = (struct rsrc *)
542d6675 9208 xrealloc ((void *) regdeps,
bc805888 9209 regdepstotlen * sizeof (struct rsrc));
800eeca4
JW
9210 }
9211
9212 regdeps[regdepslen] = *spec;
9213 regdeps[regdepslen].depind = depind;
9214 regdeps[regdepslen].path = path;
9215 regdeps[regdepslen].file = CURR_SLOT.src_file;
9216 regdeps[regdepslen].line = CURR_SLOT.src_line;
9217
9218 print_dependency ("Adding", regdepslen);
9219
9220 ++regdepslen;
9221}
9222
9223static void
9224print_dependency (action, depind)
542d6675
KH
9225 const char *action;
9226 int depind;
800eeca4
JW
9227{
9228 if (md.debug_dv)
9229 {
197865e8 9230 fprintf (stderr, " %s %s '%s'",
542d6675
KH
9231 action, dv_mode[(regdeps[depind].dependency)->mode],
9232 (regdeps[depind].dependency)->name);
800eeca4 9233 if (regdeps[depind].specific && regdeps[depind].index != 0)
542d6675 9234 fprintf (stderr, " (%d)", regdeps[depind].index);
800eeca4 9235 if (regdeps[depind].mem_offset.hint)
2434f565
JW
9236 {
9237 fputs (" ", stderr);
9238 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
9239 fputs ("+", stderr);
9240 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
9241 }
800eeca4
JW
9242 fprintf (stderr, "\n");
9243 }
9244}
9245
9246static void
9247instruction_serialization ()
9248{
9249 int i;
9250 if (md.debug_dv)
9251 fprintf (stderr, " Instruction serialization\n");
542d6675 9252 for (i = 0; i < regdepslen; i++)
800eeca4
JW
9253 if (regdeps[i].insn_srlz == STATE_STOP)
9254 regdeps[i].insn_srlz = STATE_SRLZ;
9255}
9256
9257static void
9258data_serialization ()
9259{
9260 int i = 0;
9261 if (md.debug_dv)
9262 fprintf (stderr, " Data serialization\n");
9263 while (i < regdepslen)
9264 {
9265 if (regdeps[i].data_srlz == STATE_STOP
542d6675
KH
9266 /* Note: as of 991210, all "other" dependencies are cleared by a
9267 data serialization. This might change with new tables */
9268 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
9269 {
9270 print_dependency ("Removing", i);
9271 regdeps[i] = regdeps[--regdepslen];
9272 }
800eeca4 9273 else
542d6675 9274 ++i;
800eeca4
JW
9275 }
9276}
9277
542d6675
KH
9278/* Insert stops and serializations as needed to avoid DVs. */
9279
800eeca4
JW
9280static void
9281remove_marked_resource (rs)
542d6675 9282 struct rsrc *rs;
800eeca4
JW
9283{
9284 switch (rs->dependency->semantics)
9285 {
9286 case IA64_DVS_SPECIFIC:
9287 if (md.debug_dv)
9288 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 9289 /* ...fall through... */
800eeca4
JW
9290 case IA64_DVS_INSTR:
9291 if (md.debug_dv)
542d6675 9292 fprintf (stderr, "Inserting instr serialization\n");
800eeca4 9293 if (rs->insn_srlz < STATE_STOP)
542d6675 9294 insn_group_break (1, 0, 0);
800eeca4 9295 if (rs->insn_srlz < STATE_SRLZ)
542d6675
KH
9296 {
9297 int oldqp = CURR_SLOT.qp_regno;
9298 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9299 /* Manually jam a srlz.i insn into the stream */
9300 CURR_SLOT.qp_regno = 0;
9301 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
9302 instruction_serialization ();
9303 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9304 if (++md.num_slots_in_use >= NUM_SLOTS)
9305 emit_one_bundle ();
9306 CURR_SLOT.qp_regno = oldqp;
9307 CURR_SLOT.idesc = oldidesc;
9308 }
800eeca4
JW
9309 insn_group_break (1, 0, 0);
9310 break;
9311 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
542d6675
KH
9312 "other" types of DV are eliminated
9313 by a data serialization */
800eeca4
JW
9314 case IA64_DVS_DATA:
9315 if (md.debug_dv)
542d6675 9316 fprintf (stderr, "Inserting data serialization\n");
800eeca4 9317 if (rs->data_srlz < STATE_STOP)
542d6675 9318 insn_group_break (1, 0, 0);
800eeca4 9319 {
542d6675
KH
9320 int oldqp = CURR_SLOT.qp_regno;
9321 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9322 /* Manually jam a srlz.d insn into the stream */
9323 CURR_SLOT.qp_regno = 0;
9324 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
9325 data_serialization ();
9326 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9327 if (++md.num_slots_in_use >= NUM_SLOTS)
9328 emit_one_bundle ();
9329 CURR_SLOT.qp_regno = oldqp;
9330 CURR_SLOT.idesc = oldidesc;
800eeca4
JW
9331 }
9332 break;
9333 case IA64_DVS_IMPLIED:
9334 case IA64_DVS_IMPLIEDF:
9335 if (md.debug_dv)
542d6675 9336 fprintf (stderr, "Inserting stop\n");
800eeca4
JW
9337 insn_group_break (1, 0, 0);
9338 break;
9339 default:
9340 break;
9341 }
9342}
9343
9344/* Check the resources used by the given opcode against the current dependency
197865e8 9345 list.
800eeca4
JW
9346
9347 The check is run once for each execution path encountered. In this case,
9348 a unique execution path is the sequence of instructions following a code
9349 entry point, e.g. the following has three execution paths, one starting
9350 at L0, one at L1, and one at L2.
197865e8 9351
800eeca4
JW
9352 L0: nop
9353 L1: add
9354 L2: add
197865e8 9355 br.ret
800eeca4 9356*/
542d6675 9357
800eeca4
JW
9358static void
9359check_dependencies (idesc)
542d6675 9360 struct ia64_opcode *idesc;
800eeca4
JW
9361{
9362 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9363 int path;
9364 int i;
9365
9366 /* Note that the number of marked resources may change within the
197865e8 9367 loop if in auto mode. */
800eeca4
JW
9368 i = 0;
9369 while (i < regdepslen)
9370 {
9371 struct rsrc *rs = &regdeps[i];
9372 const struct ia64_dependency *dep = rs->dependency;
9373 int chkind;
9374 int note;
9375 int start_over = 0;
9376
9377 if (dep->semantics == IA64_DVS_NONE
542d6675
KH
9378 || (chkind = depends_on (rs->depind, idesc)) == -1)
9379 {
9380 ++i;
9381 continue;
9382 }
9383
9384 note = NOTE (opdeps->chks[chkind]);
9385
9386 /* Check this resource against each execution path seen thus far. */
9387 for (path = 0; path <= md.path; path++)
9388 {
9389 int matchtype;
9390
9391 /* If the dependency wasn't on the path being checked, ignore it. */
9392 if (rs->path < path)
9393 continue;
9394
9395 /* If the QP for this insn implies a QP which has branched, don't
9396 bother checking. Ed. NOTE: I don't think this check is terribly
9397 useful; what's the point of generating code which will only be
9398 reached if its QP is zero?
9399 This code was specifically inserted to handle the following code,
9400 based on notes from Intel's DV checking code, where p1 implies p2.
9401
9402 mov r4 = 2
9403 (p2) br.cond L
9404 (p1) mov r4 = 7
9405 */
9406 if (CURR_SLOT.qp_regno != 0)
9407 {
9408 int skip = 0;
9409 int implies;
9410 for (implies = 0; implies < qp_implieslen; implies++)
9411 {
9412 if (qp_implies[implies].path >= path
9413 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
9414 && qp_implies[implies].p2_branched)
9415 {
9416 skip = 1;
9417 break;
9418 }
9419 }
9420 if (skip)
9421 continue;
9422 }
9423
9424 if ((matchtype = resources_match (rs, idesc, note,
9425 CURR_SLOT.qp_regno, path)) != 0)
9426 {
9427 char msg[1024];
9428 char pathmsg[256] = "";
9429 char indexmsg[256] = "";
9430 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
9431
9432 if (path != 0)
9433 sprintf (pathmsg, " when entry is at label '%s'",
9434 md.entry_labels[path - 1]);
9435 if (rs->specific && rs->index != 0)
9436 sprintf (indexmsg, ", specific resource number is %d",
9437 rs->index);
9438 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9439 idesc->name,
9440 (certain ? "violates" : "may violate"),
9441 dv_mode[dep->mode], dep->name,
9442 dv_sem[dep->semantics],
9443 pathmsg, indexmsg);
9444
9445 if (md.explicit_mode)
9446 {
9447 as_warn ("%s", msg);
9448 if (path < md.path)
9449 as_warn (_("Only the first path encountering the conflict "
9450 "is reported"));
9451 as_warn_where (rs->file, rs->line,
9452 _("This is the location of the "
9453 "conflicting usage"));
9454 /* Don't bother checking other paths, to avoid duplicating
9455 the same warning */
9456 break;
9457 }
9458 else
9459 {
9460 if (md.debug_dv)
9461 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
9462
9463 remove_marked_resource (rs);
9464
9465 /* since the set of dependencies has changed, start over */
9466 /* FIXME -- since we're removing dvs as we go, we
9467 probably don't really need to start over... */
9468 start_over = 1;
9469 break;
9470 }
9471 }
9472 }
800eeca4 9473 if (start_over)
542d6675 9474 i = 0;
800eeca4 9475 else
542d6675 9476 ++i;
800eeca4
JW
9477 }
9478}
9479
542d6675
KH
9480/* Register new dependencies based on the given opcode. */
9481
800eeca4
JW
9482static void
9483mark_resources (idesc)
542d6675 9484 struct ia64_opcode *idesc;
800eeca4
JW
9485{
9486 int i;
9487 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9488 int add_only_qp_reads = 0;
9489
9490 /* A conditional branch only uses its resources if it is taken; if it is
9491 taken, we stop following that path. The other branch types effectively
9492 *always* write their resources. If it's not taken, register only QP
197865e8 9493 reads. */
800eeca4
JW
9494 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
9495 {
9496 add_only_qp_reads = 1;
9497 }
9498
9499 if (md.debug_dv)
9500 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
9501
542d6675 9502 for (i = 0; i < opdeps->nregs; i++)
800eeca4
JW
9503 {
9504 const struct ia64_dependency *dep;
9505 struct rsrc specs[MAX_SPECS];
9506 int note;
9507 int path;
9508 int count;
197865e8 9509
800eeca4 9510 dep = ia64_find_dependency (opdeps->regs[i]);
542d6675 9511 note = NOTE (opdeps->regs[i]);
800eeca4
JW
9512
9513 if (add_only_qp_reads
542d6675
KH
9514 && !(dep->mode == IA64_DV_WAR
9515 && (dep->specifier == IA64_RS_PR
139368c9 9516 || dep->specifier == IA64_RS_PRr
542d6675
KH
9517 || dep->specifier == IA64_RS_PR63)))
9518 continue;
800eeca4
JW
9519
9520 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
9521
9522#if 0
9523 if (md.debug_dv && !count)
542d6675
KH
9524 fprintf (stderr, " No %s %s usage found (path %d)\n",
9525 dv_mode[dep->mode], dep->name, md.path);
800eeca4 9526#endif
197865e8 9527
800eeca4 9528 while (count-- > 0)
542d6675
KH
9529 {
9530 mark_resource (idesc, dep, &specs[count],
9531 DEP (opdeps->regs[i]), md.path);
9532 }
800eeca4
JW
9533
9534 /* The execution path may affect register values, which may in turn
542d6675 9535 affect which indirect-access resources are accessed. */
800eeca4 9536 switch (dep->specifier)
542d6675
KH
9537 {
9538 default:
9539 break;
9540 case IA64_RS_CPUID:
9541 case IA64_RS_DBR:
9542 case IA64_RS_IBR:
800eeca4 9543 case IA64_RS_MSR:
542d6675
KH
9544 case IA64_RS_PKR:
9545 case IA64_RS_PMC:
9546 case IA64_RS_PMD:
9547 case IA64_RS_RR:
9548 for (path = 0; path < md.path; path++)
9549 {
9550 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
9551 while (count-- > 0)
9552 mark_resource (idesc, dep, &specs[count],
9553 DEP (opdeps->regs[i]), path);
9554 }
9555 break;
9556 }
9557 }
9558}
9559
9560/* Remove dependencies when they no longer apply. */
9561
800eeca4
JW
9562static void
9563update_dependencies (idesc)
542d6675 9564 struct ia64_opcode *idesc;
800eeca4
JW
9565{
9566 int i;
9567
9568 if (strcmp (idesc->name, "srlz.i") == 0)
9569 {
9570 instruction_serialization ();
9571 }
9572 else if (strcmp (idesc->name, "srlz.d") == 0)
9573 {
9574 data_serialization ();
9575 }
9576 else if (is_interruption_or_rfi (idesc)
542d6675 9577 || is_taken_branch (idesc))
800eeca4 9578 {
542d6675
KH
9579 /* Although technically the taken branch doesn't clear dependencies
9580 which require a srlz.[id], we don't follow the branch; the next
9581 instruction is assumed to start with a clean slate. */
800eeca4 9582 regdepslen = 0;
800eeca4
JW
9583 md.path = 0;
9584 }
9585 else if (is_conditional_branch (idesc)
542d6675 9586 && CURR_SLOT.qp_regno != 0)
800eeca4
JW
9587 {
9588 int is_call = strstr (idesc->name, ".call") != NULL;
9589
542d6675
KH
9590 for (i = 0; i < qp_implieslen; i++)
9591 {
9592 /* If the conditional branch's predicate is implied by the predicate
9593 in an existing dependency, remove that dependency. */
9594 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
9595 {
9596 int depind = 0;
9597 /* Note that this implied predicate takes a branch so that if
9598 a later insn generates a DV but its predicate implies this
9599 one, we can avoid the false DV warning. */
9600 qp_implies[i].p2_branched = 1;
9601 while (depind < regdepslen)
9602 {
9603 if (regdeps[depind].qp_regno == qp_implies[i].p1)
9604 {
9605 print_dependency ("Removing", depind);
9606 regdeps[depind] = regdeps[--regdepslen];
9607 }
9608 else
9609 ++depind;
9610 }
9611 }
9612 }
800eeca4 9613 /* Any marked resources which have this same predicate should be
542d6675
KH
9614 cleared, provided that the QP hasn't been modified between the
9615 marking instruction and the branch. */
800eeca4 9616 if (is_call)
542d6675
KH
9617 {
9618 insn_group_break (0, CURR_SLOT.qp_regno, 1);
9619 }
800eeca4 9620 else
542d6675
KH
9621 {
9622 i = 0;
9623 while (i < regdepslen)
9624 {
9625 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
9626 && regdeps[i].link_to_qp_branch
9627 && (regdeps[i].file != CURR_SLOT.src_file
9628 || regdeps[i].line != CURR_SLOT.src_line))
9629 {
9630 /* Treat like a taken branch */
9631 print_dependency ("Removing", i);
9632 regdeps[i] = regdeps[--regdepslen];
9633 }
9634 else
9635 ++i;
9636 }
9637 }
800eeca4
JW
9638 }
9639}
9640
9641/* Examine the current instruction for dependency violations. */
542d6675 9642
800eeca4
JW
9643static int
9644check_dv (idesc)
542d6675 9645 struct ia64_opcode *idesc;
800eeca4
JW
9646{
9647 if (md.debug_dv)
9648 {
197865e8 9649 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
542d6675
KH
9650 idesc->name, CURR_SLOT.src_line,
9651 idesc->dependencies->nchks,
9652 idesc->dependencies->nregs);
800eeca4
JW
9653 }
9654
197865e8 9655 /* Look through the list of currently marked resources; if the current
800eeca4 9656 instruction has the dependency in its chks list which uses that resource,
542d6675 9657 check against the specific resources used. */
800eeca4
JW
9658 check_dependencies (idesc);
9659
542d6675
KH
9660 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9661 then add them to the list of marked resources. */
800eeca4
JW
9662 mark_resources (idesc);
9663
9664 /* There are several types of dependency semantics, and each has its own
197865e8
KH
9665 requirements for being cleared
9666
800eeca4
JW
9667 Instruction serialization (insns separated by interruption, rfi, or
9668 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9669
9670 Data serialization (instruction serialization, or writer + srlz.d +
9671 reader, where writer and srlz.d are in separate groups) clears
9672 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9673 always be the case).
9674
9675 Instruction group break (groups separated by stop, taken branch,
9676 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9677 */
9678 update_dependencies (idesc);
9679
9680 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 9681 warning. Keep track of as many as possible that are useful. */
800eeca4
JW
9682 note_register_values (idesc);
9683
197865e8 9684 /* We don't need or want this anymore. */
800eeca4
JW
9685 md.mem_offset.hint = 0;
9686
9687 return 0;
9688}
9689
9690/* Translate one line of assembly. Pseudo ops and labels do not show
9691 here. */
9692void
9693md_assemble (str)
9694 char *str;
9695{
9696 char *saved_input_line_pointer, *mnemonic;
9697 const struct pseudo_opcode *pdesc;
9698 struct ia64_opcode *idesc;
9699 unsigned char qp_regno;
9700 unsigned int flags;
9701 int ch;
9702
9703 saved_input_line_pointer = input_line_pointer;
9704 input_line_pointer = str;
9705
542d6675 9706 /* extract the opcode (mnemonic): */
800eeca4
JW
9707
9708 mnemonic = input_line_pointer;
9709 ch = get_symbol_end ();
9710 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9711 if (pdesc)
9712 {
9713 *input_line_pointer = ch;
9714 (*pdesc->handler) (pdesc->arg);
9715 goto done;
9716 }
9717
542d6675 9718 /* Find the instruction descriptor matching the arguments. */
800eeca4
JW
9719
9720 idesc = ia64_find_opcode (mnemonic);
9721 *input_line_pointer = ch;
9722 if (!idesc)
9723 {
9724 as_bad ("Unknown opcode `%s'", mnemonic);
9725 goto done;
9726 }
9727
9728 idesc = parse_operands (idesc);
9729 if (!idesc)
9730 goto done;
9731
542d6675 9732 /* Handle the dynamic ops we can handle now: */
800eeca4
JW
9733 if (idesc->type == IA64_TYPE_DYN)
9734 {
9735 if (strcmp (idesc->name, "add") == 0)
9736 {
9737 if (CURR_SLOT.opnd[2].X_op == O_register
9738 && CURR_SLOT.opnd[2].X_add_number < 4)
9739 mnemonic = "addl";
9740 else
9741 mnemonic = "adds";
3d56ab85 9742 ia64_free_opcode (idesc);
800eeca4
JW
9743 idesc = ia64_find_opcode (mnemonic);
9744#if 0
9745 know (!idesc->next);
9746#endif
9747 }
9748 else if (strcmp (idesc->name, "mov") == 0)
9749 {
9750 enum ia64_opnd opnd1, opnd2;
9751 int rop;
9752
9753 opnd1 = idesc->operands[0];
9754 opnd2 = idesc->operands[1];
9755 if (opnd1 == IA64_OPND_AR3)
9756 rop = 0;
9757 else if (opnd2 == IA64_OPND_AR3)
9758 rop = 1;
9759 else
9760 abort ();
9761 if (CURR_SLOT.opnd[rop].X_op == O_register
9762 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9763 mnemonic = "mov.i";
9764 else
9765 mnemonic = "mov.m";
3d56ab85 9766 ia64_free_opcode (idesc);
800eeca4
JW
9767 idesc = ia64_find_opcode (mnemonic);
9768 while (idesc != NULL
9769 && (idesc->operands[0] != opnd1
9770 || idesc->operands[1] != opnd2))
9771 idesc = get_next_opcode (idesc);
9772 }
9773 }
9774
9775 qp_regno = 0;
9776 if (md.qp.X_op == O_register)
f1bcba5b
JW
9777 {
9778 qp_regno = md.qp.X_add_number - REG_P;
9779 md.qp.X_op = O_absent;
9780 }
800eeca4
JW
9781
9782 flags = idesc->flags;
9783
9784 if ((flags & IA64_OPCODE_FIRST) != 0)
9785 insn_group_break (1, 0, 0);
9786
9787 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9788 {
9789 as_bad ("`%s' cannot be predicated", idesc->name);
9790 goto done;
9791 }
9792
542d6675 9793 /* Build the instruction. */
800eeca4
JW
9794 CURR_SLOT.qp_regno = qp_regno;
9795 CURR_SLOT.idesc = idesc;
9796 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
4dc7ead9 9797 dwarf2_where (&CURR_SLOT.debug_line);
800eeca4
JW
9798
9799 /* Add unwind entry, if there is one. */
e0c9811a 9800 if (unwind.current_entry)
800eeca4 9801 {
e0c9811a
JW
9802 CURR_SLOT.unwind_record = unwind.current_entry;
9803 unwind.current_entry = NULL;
800eeca4
JW
9804 }
9805
542d6675 9806 /* Check for dependency violations. */
800eeca4 9807 if (md.detect_dv)
542d6675 9808 check_dv (idesc);
800eeca4
JW
9809
9810 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9811 if (++md.num_slots_in_use >= NUM_SLOTS)
9812 emit_one_bundle ();
9813
9814 if ((flags & IA64_OPCODE_LAST) != 0)
9815 insn_group_break (1, 0, 0);
9816
9817 md.last_text_seg = now_seg;
9818
9819 done:
9820 input_line_pointer = saved_input_line_pointer;
9821}
9822
9823/* Called when symbol NAME cannot be found in the symbol table.
9824 Should be used for dynamic valued symbols only. */
542d6675
KH
9825
9826symbolS *
800eeca4 9827md_undefined_symbol (name)
2434f565 9828 char *name ATTRIBUTE_UNUSED;
800eeca4
JW
9829{
9830 return 0;
9831}
9832
9833/* Called for any expression that can not be recognized. When the
9834 function is called, `input_line_pointer' will point to the start of
9835 the expression. */
542d6675 9836
800eeca4
JW
9837void
9838md_operand (e)
9839 expressionS *e;
9840{
9841 enum pseudo_type pseudo_type;
e0c9811a 9842 const char *name;
800eeca4
JW
9843 size_t len;
9844 int ch, i;
9845
9846 switch (*input_line_pointer)
9847 {
9848 case '@':
542d6675 9849 /* Find what relocation pseudo-function we're dealing with. */
800eeca4
JW
9850 pseudo_type = 0;
9851 ch = *++input_line_pointer;
9852 for (i = 0; i < NELEMS (pseudo_func); ++i)
9853 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9854 {
9855 len = strlen (pseudo_func[i].name);
9856 if (strncmp (pseudo_func[i].name + 1,
9857 input_line_pointer + 1, len - 1) == 0
9858 && !is_part_of_name (input_line_pointer[len]))
9859 {
9860 input_line_pointer += len;
9861 pseudo_type = pseudo_func[i].type;
9862 break;
9863 }
9864 }
9865 switch (pseudo_type)
9866 {
9867 case PSEUDO_FUNC_RELOC:
9868 SKIP_WHITESPACE ();
9869 if (*input_line_pointer != '(')
9870 {
9871 as_bad ("Expected '('");
9872 goto err;
9873 }
542d6675
KH
9874 /* Skip '('. */
9875 ++input_line_pointer;
800eeca4
JW
9876 expression (e);
9877 if (*input_line_pointer++ != ')')
9878 {
9879 as_bad ("Missing ')'");
9880 goto err;
9881 }
9882 if (e->X_op != O_symbol)
9883 {
9884 if (e->X_op != O_pseudo_fixup)
9885 {
9886 as_bad ("Not a symbolic expression");
9887 goto err;
9888 }
13ae64f3
JJ
9889 if (i != FUNC_LT_RELATIVE)
9890 {
9891 as_bad ("Illegal combination of relocation functions");
9892 goto err;
9893 }
9894 switch (S_GET_VALUE (e->X_op_symbol))
800eeca4 9895 {
13ae64f3
JJ
9896 case FUNC_FPTR_RELATIVE:
9897 i = FUNC_LT_FPTR_RELATIVE; break;
9898 case FUNC_DTP_MODULE:
9899 i = FUNC_LT_DTP_MODULE; break;
9900 case FUNC_DTP_RELATIVE:
9901 i = FUNC_LT_DTP_RELATIVE; break;
9902 case FUNC_TP_RELATIVE:
9903 i = FUNC_LT_TP_RELATIVE; break;
9904 default:
800eeca4
JW
9905 as_bad ("Illegal combination of relocation functions");
9906 goto err;
9907 }
9908 }
542d6675
KH
9909 /* Make sure gas doesn't get rid of local symbols that are used
9910 in relocs. */
800eeca4
JW
9911 e->X_op = O_pseudo_fixup;
9912 e->X_op_symbol = pseudo_func[i].u.sym;
9913 break;
9914
9915 case PSEUDO_FUNC_CONST:
9916 e->X_op = O_constant;
9917 e->X_add_number = pseudo_func[i].u.ival;
9918 break;
9919
e0c9811a
JW
9920 case PSEUDO_FUNC_REG:
9921 e->X_op = O_register;
9922 e->X_add_number = pseudo_func[i].u.ival;
9923 break;
9924
800eeca4 9925 default:
e0c9811a
JW
9926 name = input_line_pointer - 1;
9927 get_symbol_end ();
9928 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW
9929 goto err;
9930 }
9931 break;
9932
9933 case '[':
9934 ++input_line_pointer;
9935 expression (e);
9936 if (*input_line_pointer != ']')
9937 {
9938 as_bad ("Closing bracket misssing");
9939 goto err;
9940 }
9941 else
9942 {
9943 if (e->X_op != O_register)
9944 as_bad ("Register expected as index");
9945
9946 ++input_line_pointer;
9947 e->X_op = O_index;
9948 }
9949 break;
9950
9951 default:
9952 break;
9953 }
9954 return;
9955
9956 err:
9957 ignore_rest_of_line ();
9958}
9959
9960/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9961 a section symbol plus some offset. For relocs involving @fptr(),
9962 directives we don't want such adjustments since we need to have the
9963 original symbol's name in the reloc. */
9964int
9965ia64_fix_adjustable (fix)
9966 fixS *fix;
9967{
9968 /* Prevent all adjustments to global symbols */
9969 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9970 return 0;
9971
9972 switch (fix->fx_r_type)
9973 {
9974 case BFD_RELOC_IA64_FPTR64I:
9975 case BFD_RELOC_IA64_FPTR32MSB:
9976 case BFD_RELOC_IA64_FPTR32LSB:
9977 case BFD_RELOC_IA64_FPTR64MSB:
9978 case BFD_RELOC_IA64_FPTR64LSB:
9979 case BFD_RELOC_IA64_LTOFF_FPTR22:
9980 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9981 return 0;
9982 default:
9983 break;
9984 }
9985
9986 return 1;
9987}
9988
9989int
9990ia64_force_relocation (fix)
9991 fixS *fix;
9992{
9993 switch (fix->fx_r_type)
9994 {
9995 case BFD_RELOC_IA64_FPTR64I:
9996 case BFD_RELOC_IA64_FPTR32MSB:
9997 case BFD_RELOC_IA64_FPTR32LSB:
9998 case BFD_RELOC_IA64_FPTR64MSB:
9999 case BFD_RELOC_IA64_FPTR64LSB:
10000
10001 case BFD_RELOC_IA64_LTOFF22:
10002 case BFD_RELOC_IA64_LTOFF64I:
10003 case BFD_RELOC_IA64_LTOFF_FPTR22:
10004 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10005 case BFD_RELOC_IA64_PLTOFF22:
10006 case BFD_RELOC_IA64_PLTOFF64I:
10007 case BFD_RELOC_IA64_PLTOFF64MSB:
10008 case BFD_RELOC_IA64_PLTOFF64LSB:
fa2c7eff
RH
10009
10010 case BFD_RELOC_IA64_LTOFF22X:
10011 case BFD_RELOC_IA64_LDXMOV:
800eeca4
JW
10012 return 1;
10013
10014 default:
a161fe53 10015 break;
800eeca4 10016 }
a161fe53 10017
ae6063d4 10018 return generic_force_reloc (fix);
800eeca4
JW
10019}
10020
10021/* Decide from what point a pc-relative relocation is relative to,
10022 relative to the pc-relative fixup. Er, relatively speaking. */
10023long
10024ia64_pcrel_from_section (fix, sec)
10025 fixS *fix;
10026 segT sec;
10027{
10028 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 10029
800eeca4
JW
10030 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
10031 off &= ~0xfUL;
10032
10033 return off;
10034}
10035
6174d9c8
RH
10036
10037/* Used to emit section-relative relocs for the dwarf2 debug data. */
10038void
10039ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10040{
10041 expressionS expr;
10042
10043 expr.X_op = O_pseudo_fixup;
10044 expr.X_op_symbol = pseudo_func[FUNC_SEC_RELATIVE].u.sym;
10045 expr.X_add_number = 0;
10046 expr.X_add_symbol = symbol;
10047 emit_expr (&expr, size);
10048}
10049
800eeca4
JW
10050/* This is called whenever some data item (not an instruction) needs a
10051 fixup. We pick the right reloc code depending on the byteorder
10052 currently in effect. */
10053void
10054ia64_cons_fix_new (f, where, nbytes, exp)
10055 fragS *f;
10056 int where;
10057 int nbytes;
10058 expressionS *exp;
10059{
10060 bfd_reloc_code_real_type code;
10061 fixS *fix;
10062
10063 switch (nbytes)
10064 {
10065 /* There are no reloc for 8 and 16 bit quantities, but we allow
10066 them here since they will work fine as long as the expression
10067 is fully defined at the end of the pass over the source file. */
10068 case 1: code = BFD_RELOC_8; break;
10069 case 2: code = BFD_RELOC_16; break;
10070 case 4:
10071 if (target_big_endian)
10072 code = BFD_RELOC_IA64_DIR32MSB;
10073 else
10074 code = BFD_RELOC_IA64_DIR32LSB;
10075 break;
10076
10077 case 8:
40449e9f 10078 /* In 32-bit mode, data8 could mean function descriptors too. */
5f44c186 10079 if (exp->X_op == O_pseudo_fixup
40449e9f
KH
10080 && exp->X_op_symbol
10081 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC
10082 && !(md.flags & EF_IA_64_ABI64))
10083 {
10084 if (target_big_endian)
10085 code = BFD_RELOC_IA64_IPLTMSB;
10086 else
10087 code = BFD_RELOC_IA64_IPLTLSB;
10088 exp->X_op = O_symbol;
10089 break;
10090 }
10091 else
10092 {
10093 if (target_big_endian)
10094 code = BFD_RELOC_IA64_DIR64MSB;
10095 else
10096 code = BFD_RELOC_IA64_DIR64LSB;
10097 break;
10098 }
800eeca4 10099
3969b680
RH
10100 case 16:
10101 if (exp->X_op == O_pseudo_fixup
10102 && exp->X_op_symbol
10103 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC)
10104 {
10105 if (target_big_endian)
10106 code = BFD_RELOC_IA64_IPLTMSB;
10107 else
10108 code = BFD_RELOC_IA64_IPLTLSB;
3969b680
RH
10109 exp->X_op = O_symbol;
10110 break;
10111 }
10112 /* FALLTHRU */
10113
800eeca4
JW
10114 default:
10115 as_bad ("Unsupported fixup size %d", nbytes);
10116 ignore_rest_of_line ();
10117 return;
10118 }
6174d9c8 10119
800eeca4
JW
10120 if (exp->X_op == O_pseudo_fixup)
10121 {
800eeca4
JW
10122 exp->X_op = O_symbol;
10123 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
6174d9c8 10124 /* ??? If code unchanged, unsupported. */
800eeca4 10125 }
3969b680 10126
800eeca4
JW
10127 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
10128 /* We need to store the byte order in effect in case we're going
10129 to fix an 8 or 16 bit relocation (for which there no real
94f592af 10130 relocs available). See md_apply_fix3(). */
800eeca4
JW
10131 fix->tc_fix_data.bigendian = target_big_endian;
10132}
10133
10134/* Return the actual relocation we wish to associate with the pseudo
10135 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 10136 symbols in the pseudo_func array, or NULL. */
800eeca4
JW
10137
10138static bfd_reloc_code_real_type
10139ia64_gen_real_reloc_type (sym, r_type)
10140 struct symbol *sym;
10141 bfd_reloc_code_real_type r_type;
10142{
10143 bfd_reloc_code_real_type new = 0;
10144
10145 if (sym == NULL)
10146 {
10147 return r_type;
10148 }
10149
10150 switch (S_GET_VALUE (sym))
10151 {
10152 case FUNC_FPTR_RELATIVE:
10153 switch (r_type)
10154 {
10155 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
10156 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
10157 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
10158 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
10159 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
10160 default: break;
10161 }
10162 break;
10163
10164 case FUNC_GP_RELATIVE:
10165 switch (r_type)
10166 {
10167 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
10168 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
10169 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
10170 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
10171 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
10172 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
10173 default: break;
10174 }
10175 break;
10176
10177 case FUNC_LT_RELATIVE:
10178 switch (r_type)
10179 {
10180 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
10181 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
10182 default: break;
10183 }
10184 break;
10185
fa2c7eff
RH
10186 case FUNC_LT_RELATIVE_X:
10187 switch (r_type)
10188 {
10189 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22X; break;
10190 default: break;
10191 }
10192 break;
10193
c67e42c9
RH
10194 case FUNC_PC_RELATIVE:
10195 switch (r_type)
10196 {
10197 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
10198 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
10199 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
10200 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
10201 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
10202 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
10203 default: break;
10204 }
10205 break;
10206
800eeca4
JW
10207 case FUNC_PLT_RELATIVE:
10208 switch (r_type)
10209 {
10210 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
10211 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
10212 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
10213 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
10214 default: break;
10215 }
10216 break;
10217
10218 case FUNC_SEC_RELATIVE:
10219 switch (r_type)
10220 {
10221 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
10222 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
10223 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
10224 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
10225 default: break;
10226 }
10227 break;
10228
10229 case FUNC_SEG_RELATIVE:
10230 switch (r_type)
10231 {
10232 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
10233 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
10234 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
10235 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
10236 default: break;
10237 }
10238 break;
10239
10240 case FUNC_LTV_RELATIVE:
10241 switch (r_type)
10242 {
10243 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
10244 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
10245 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
10246 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
10247 default: break;
10248 }
10249 break;
10250
10251 case FUNC_LT_FPTR_RELATIVE:
10252 switch (r_type)
10253 {
10254 case BFD_RELOC_IA64_IMM22:
10255 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
10256 case BFD_RELOC_IA64_IMM64:
10257 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
10258 default:
10259 break;
10260 }
10261 break;
3969b680 10262
13ae64f3
JJ
10263 case FUNC_TP_RELATIVE:
10264 switch (r_type)
10265 {
10266 case BFD_RELOC_IA64_IMM14:
10267 new = BFD_RELOC_IA64_TPREL14; break;
10268 case BFD_RELOC_IA64_IMM22:
10269 new = BFD_RELOC_IA64_TPREL22; break;
10270 case BFD_RELOC_IA64_IMM64:
10271 new = BFD_RELOC_IA64_TPREL64I; break;
10272 default:
10273 break;
10274 }
10275 break;
10276
10277 case FUNC_LT_TP_RELATIVE:
10278 switch (r_type)
10279 {
10280 case BFD_RELOC_IA64_IMM22:
10281 new = BFD_RELOC_IA64_LTOFF_TPREL22; break;
10282 default:
10283 break;
10284 }
10285 break;
10286
10287 case FUNC_LT_DTP_MODULE:
10288 switch (r_type)
10289 {
10290 case BFD_RELOC_IA64_IMM22:
10291 new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break;
10292 default:
10293 break;
10294 }
10295 break;
10296
10297 case FUNC_DTP_RELATIVE:
10298 switch (r_type)
10299 {
6174d9c8
RH
10300 case BFD_RELOC_IA64_DIR64MSB:
10301 new = BFD_RELOC_IA64_DTPREL64MSB; break;
10302 case BFD_RELOC_IA64_DIR64LSB:
10303 new = BFD_RELOC_IA64_DTPREL64LSB; break;
13ae64f3
JJ
10304 case BFD_RELOC_IA64_IMM14:
10305 new = BFD_RELOC_IA64_DTPREL14; break;
10306 case BFD_RELOC_IA64_IMM22:
10307 new = BFD_RELOC_IA64_DTPREL22; break;
10308 case BFD_RELOC_IA64_IMM64:
10309 new = BFD_RELOC_IA64_DTPREL64I; break;
10310 default:
10311 break;
10312 }
10313 break;
10314
10315 case FUNC_LT_DTP_RELATIVE:
10316 switch (r_type)
10317 {
10318 case BFD_RELOC_IA64_IMM22:
10319 new = BFD_RELOC_IA64_LTOFF_DTPREL22; break;
10320 default:
10321 break;
10322 }
10323 break;
10324
40449e9f
KH
10325 case FUNC_IPLT_RELOC:
10326 break;
1cd8ff38 10327
800eeca4
JW
10328 default:
10329 abort ();
10330 }
6174d9c8 10331
800eeca4
JW
10332 /* Hmmmm. Should this ever occur? */
10333 if (new)
10334 return new;
10335 else
10336 return r_type;
10337}
10338
10339/* Here is where generate the appropriate reloc for pseudo relocation
10340 functions. */
10341void
10342ia64_validate_fix (fix)
10343 fixS *fix;
10344{
10345 switch (fix->fx_r_type)
10346 {
10347 case BFD_RELOC_IA64_FPTR64I:
10348 case BFD_RELOC_IA64_FPTR32MSB:
10349 case BFD_RELOC_IA64_FPTR64LSB:
10350 case BFD_RELOC_IA64_LTOFF_FPTR22:
10351 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10352 if (fix->fx_offset != 0)
10353 as_bad_where (fix->fx_file, fix->fx_line,
10354 "No addend allowed in @fptr() relocation");
10355 break;
10356 default:
10357 break;
10358 }
10359
10360 return;
10361}
10362
10363static void
10364fix_insn (fix, odesc, value)
10365 fixS *fix;
10366 const struct ia64_operand *odesc;
10367 valueT value;
10368{
10369 bfd_vma insn[3], t0, t1, control_bits;
10370 const char *err;
10371 char *fixpos;
10372 long slot;
10373
10374 slot = fix->fx_where & 0x3;
10375 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
10376
c67e42c9 10377 /* Bundles are always in little-endian byte order */
800eeca4
JW
10378 t0 = bfd_getl64 (fixpos);
10379 t1 = bfd_getl64 (fixpos + 8);
10380 control_bits = t0 & 0x1f;
10381 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
10382 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
10383 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
10384
c67e42c9
RH
10385 err = NULL;
10386 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 10387 {
c67e42c9
RH
10388 insn[1] = (value >> 22) & 0x1ffffffffffLL;
10389 insn[2] |= (((value & 0x7f) << 13)
10390 | (((value >> 7) & 0x1ff) << 27)
10391 | (((value >> 16) & 0x1f) << 22)
10392 | (((value >> 21) & 0x1) << 21)
10393 | (((value >> 63) & 0x1) << 36));
800eeca4 10394 }
c67e42c9
RH
10395 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
10396 {
10397 if (value & ~0x3fffffffffffffffULL)
10398 err = "integer operand out of range";
10399 insn[1] = (value >> 21) & 0x1ffffffffffLL;
10400 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
10401 }
10402 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
10403 {
10404 value >>= 4;
10405 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
10406 insn[2] |= ((((value >> 59) & 0x1) << 36)
10407 | (((value >> 0) & 0xfffff) << 13));
10408 }
10409 else
10410 err = (*odesc->insert) (odesc, value, insn + slot);
10411
10412 if (err)
10413 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW
10414
10415 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
10416 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
44f5c83a
JW
10417 number_to_chars_littleendian (fixpos + 0, t0, 8);
10418 number_to_chars_littleendian (fixpos + 8, t1, 8);
800eeca4
JW
10419}
10420
10421/* Attempt to simplify or even eliminate a fixup. The return value is
10422 ignored; perhaps it was once meaningful, but now it is historical.
10423 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10424
10425 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 10426 (if possible). */
94f592af
NC
10427
10428void
10429md_apply_fix3 (fix, valP, seg)
800eeca4 10430 fixS *fix;
40449e9f 10431 valueT *valP;
2434f565 10432 segT seg ATTRIBUTE_UNUSED;
800eeca4
JW
10433{
10434 char *fixpos;
40449e9f 10435 valueT value = *valP;
800eeca4
JW
10436
10437 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
10438
10439 if (fix->fx_pcrel)
10440 {
10441 switch (fix->fx_r_type)
10442 {
10443 case BFD_RELOC_IA64_DIR32MSB:
10444 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
800eeca4
JW
10445 break;
10446
10447 case BFD_RELOC_IA64_DIR32LSB:
10448 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
800eeca4
JW
10449 break;
10450
10451 case BFD_RELOC_IA64_DIR64MSB:
10452 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
800eeca4
JW
10453 break;
10454
10455 case BFD_RELOC_IA64_DIR64LSB:
10456 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
800eeca4
JW
10457 break;
10458
10459 default:
10460 break;
10461 }
10462 }
10463 if (fix->fx_addsy)
10464 {
00f7efb6 10465 switch (fix->fx_r_type)
800eeca4 10466 {
00f7efb6 10467 case BFD_RELOC_UNUSED:
fa1cb89c
JW
10468 /* This must be a TAG13 or TAG13b operand. There are no external
10469 relocs defined for them, so we must give an error. */
800eeca4
JW
10470 as_bad_where (fix->fx_file, fix->fx_line,
10471 "%s must have a constant value",
10472 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
fa1cb89c 10473 fix->fx_done = 1;
94f592af 10474 return;
00f7efb6
JJ
10475
10476 case BFD_RELOC_IA64_TPREL14:
10477 case BFD_RELOC_IA64_TPREL22:
10478 case BFD_RELOC_IA64_TPREL64I:
10479 case BFD_RELOC_IA64_LTOFF_TPREL22:
10480 case BFD_RELOC_IA64_LTOFF_DTPMOD22:
10481 case BFD_RELOC_IA64_DTPREL14:
10482 case BFD_RELOC_IA64_DTPREL22:
10483 case BFD_RELOC_IA64_DTPREL64I:
10484 case BFD_RELOC_IA64_LTOFF_DTPREL22:
10485 S_SET_THREAD_LOCAL (fix->fx_addsy);
10486 break;
7925dd68
JJ
10487
10488 default:
10489 break;
800eeca4 10490 }
800eeca4
JW
10491 }
10492 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
10493 {
10494 if (fix->tc_fix_data.bigendian)
10495 number_to_chars_bigendian (fixpos, value, fix->fx_size);
10496 else
10497 number_to_chars_littleendian (fixpos, value, fix->fx_size);
10498 fix->fx_done = 1;
800eeca4
JW
10499 }
10500 else
10501 {
10502 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
10503 fix->fx_done = 1;
800eeca4 10504 }
800eeca4
JW
10505}
10506
10507/* Generate the BFD reloc to be stuck in the object file from the
10508 fixup used internally in the assembler. */
542d6675
KH
10509
10510arelent *
800eeca4 10511tc_gen_reloc (sec, fixp)
2434f565 10512 asection *sec ATTRIBUTE_UNUSED;
800eeca4
JW
10513 fixS *fixp;
10514{
10515 arelent *reloc;
10516
10517 reloc = xmalloc (sizeof (*reloc));
10518 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10519 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10520 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
10521 reloc->addend = fixp->fx_offset;
10522 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
10523
10524 if (!reloc->howto)
10525 {
10526 as_bad_where (fixp->fx_file, fixp->fx_line,
10527 "Cannot represent %s relocation in object file",
10528 bfd_get_reloc_code_name (fixp->fx_r_type));
10529 }
10530 return reloc;
10531}
10532
10533/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC
10534 of type TYPE, and store the appropriate bytes in *LIT. The number
10535 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW
10536 returned, or NULL on OK. */
10537
10538#define MAX_LITTLENUMS 5
10539
542d6675 10540char *
800eeca4
JW
10541md_atof (type, lit, size)
10542 int type;
10543 char *lit;
10544 int *size;
10545{
10546 LITTLENUM_TYPE words[MAX_LITTLENUMS];
10547 LITTLENUM_TYPE *word;
10548 char *t;
10549 int prec;
10550
10551 switch (type)
10552 {
10553 /* IEEE floats */
10554 case 'f':
10555 case 'F':
10556 case 's':
10557 case 'S':
10558 prec = 2;
10559 break;
10560
10561 case 'd':
10562 case 'D':
10563 case 'r':
10564 case 'R':
10565 prec = 4;
10566 break;
10567
10568 case 'x':
10569 case 'X':
10570 case 'p':
10571 case 'P':
10572 prec = 5;
10573 break;
10574
10575 default:
10576 *size = 0;
10577 return "Bad call to MD_ATOF()";
10578 }
10579 t = atof_ieee (input_line_pointer, type, words);
10580 if (t)
10581 input_line_pointer = t;
10582 *size = prec * sizeof (LITTLENUM_TYPE);
10583
10584 for (word = words + prec - 1; prec--;)
10585 {
10586 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
10587 lit += sizeof (LITTLENUM_TYPE);
10588 }
10589 return 0;
10590}
10591
10592/* Round up a section's size to the appropriate boundary. */
10593valueT
10594md_section_align (seg, size)
10595 segT seg;
10596 valueT size;
10597{
10598 int align = bfd_get_section_alignment (stdoutput, seg);
197865e8 10599 valueT mask = ((valueT) 1 << align) - 1;
800eeca4
JW
10600
10601 return (size + mask) & ~mask;
10602}
10603
10604/* Handle ia64 specific semantics of the align directive. */
10605
0a9ef439 10606void
800eeca4 10607ia64_md_do_align (n, fill, len, max)
91a2ae2a
RH
10608 int n ATTRIBUTE_UNUSED;
10609 const char *fill ATTRIBUTE_UNUSED;
2434f565 10610 int len ATTRIBUTE_UNUSED;
91a2ae2a 10611 int max ATTRIBUTE_UNUSED;
800eeca4 10612{
0a9ef439 10613 if (subseg_text_p (now_seg))
800eeca4 10614 ia64_flush_insns ();
0a9ef439 10615}
800eeca4 10616
0a9ef439
RH
10617/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10618 of an rs_align_code fragment. */
800eeca4 10619
0a9ef439
RH
10620void
10621ia64_handle_align (fragp)
10622 fragS *fragp;
10623{
10624 /* Use mfi bundle of nops with no stop bits. */
10625 static const unsigned char be_nop[]
10626 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10627 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10628 static const unsigned char le_nop[]
10629 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10630 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10631
10632 int bytes;
10633 char *p;
10634
10635 if (fragp->fr_type != rs_align_code)
10636 return;
10637
10638 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
10639 p = fragp->fr_literal + fragp->fr_fix;
10640
10641 /* Make sure we are on a 16-byte boundary, in case someone has been
10642 putting data into a text section. */
10643 if (bytes & 15)
10644 {
10645 int fix = bytes & 15;
10646 memset (p, 0, fix);
10647 p += fix;
10648 bytes -= fix;
10649 fragp->fr_fix += fix;
800eeca4
JW
10650 }
10651
0a9ef439
RH
10652 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
10653 fragp->fr_var = 16;
800eeca4 10654}
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