Commit | Line | Data |
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49f58d10 | 1 | /* tc-m32c.c -- Assembler for the Renesas M32C. |
2571583a | 2 | Copyright (C) 2005-2017 Free Software Foundation, Inc. |
49f58d10 JB |
3 | Contributed by RedHat. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
49f58d10 JB |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
49f58d10 | 22 | #include "as.h" |
3739860c | 23 | #include "subsegs.h" |
49f58d10 JB |
24 | #include "symcat.h" |
25 | #include "opcodes/m32c-desc.h" | |
26 | #include "opcodes/m32c-opc.h" | |
27 | #include "cgen.h" | |
28 | #include "elf/common.h" | |
29 | #include "elf/m32c.h" | |
49f58d10 JB |
30 | #include "safe-ctype.h" |
31 | ||
32 | /* Structure to hold all of the different components | |
33 | describing an individual instruction. */ | |
34 | typedef struct | |
35 | { | |
36 | const CGEN_INSN * insn; | |
37 | const CGEN_INSN * orig_insn; | |
38 | CGEN_FIELDS fields; | |
39 | #if CGEN_INT_INSN_P | |
40 | CGEN_INSN_INT buffer [1]; | |
41 | #define INSN_VALUE(buf) (*(buf)) | |
42 | #else | |
43 | unsigned char buffer [CGEN_MAX_INSN_SIZE]; | |
44 | #define INSN_VALUE(buf) (buf) | |
45 | #endif | |
46 | char * addr; | |
47 | fragS * frag; | |
48 | int num_fixups; | |
49 | fixS * fixups [GAS_CGEN_MAX_FIXUPS]; | |
50 | int indices [MAX_OPERAND_INSTANCES]; | |
51 | } | |
52 | m32c_insn; | |
53 | ||
144f4bc6 DD |
54 | #define rl_for(_insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&((_insn).insn->base->attrs))) |
55 | #define relaxable(_insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&((_insn).insn->base->attrs))) | |
6772dd07 | 56 | |
49f58d10 JB |
57 | const char comment_chars[] = ";"; |
58 | const char line_comment_chars[] = "#"; | |
59 | const char line_separator_chars[] = "|"; | |
60 | const char EXP_CHARS[] = "eE"; | |
61 | const char FLT_CHARS[] = "dD"; | |
62 | \f | |
63 | #define M32C_SHORTOPTS "" | |
64 | const char * md_shortopts = M32C_SHORTOPTS; | |
65 | ||
66 | /* assembler options */ | |
67 | #define OPTION_CPU_M16C (OPTION_MD_BASE) | |
68 | #define OPTION_CPU_M32C (OPTION_MD_BASE + 1) | |
6772dd07 | 69 | #define OPTION_LINKRELAX (OPTION_MD_BASE + 2) |
c54b5932 | 70 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE + 3) |
49f58d10 JB |
71 | |
72 | struct option md_longopts[] = | |
73 | { | |
74 | { "m16c", no_argument, NULL, OPTION_CPU_M16C }, | |
75 | { "m32c", no_argument, NULL, OPTION_CPU_M32C }, | |
6772dd07 | 76 | { "relax", no_argument, NULL, OPTION_LINKRELAX }, |
c54b5932 | 77 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
49f58d10 JB |
78 | {NULL, no_argument, NULL, 0} |
79 | }; | |
80 | size_t md_longopts_size = sizeof (md_longopts); | |
81 | ||
82 | /* Default machine */ | |
83 | ||
84 | #define DEFAULT_MACHINE bfd_mach_m16c | |
85 | #define DEFAULT_FLAGS EF_M32C_CPU_M16C | |
86 | ||
87 | static unsigned long m32c_mach = bfd_mach_m16c; | |
88 | static int cpu_mach = (1 << MACH_M16C); | |
89 | static int insn_size; | |
6772dd07 | 90 | static int m32c_relax = 0; |
49f58d10 JB |
91 | |
92 | /* Flags to set in the elf header */ | |
93 | static flagword m32c_flags = DEFAULT_FLAGS; | |
94 | ||
4fb1e3d3 DB |
95 | static char default_isa = 1 << (7 - ISA_M16C); |
96 | static CGEN_BITSET m32c_isa = {1, & default_isa}; | |
49f58d10 JB |
97 | |
98 | static void | |
99 | set_isa (enum isa_attr isa_num) | |
100 | { | |
4fb1e3d3 | 101 | cgen_bitset_set (& m32c_isa, isa_num); |
49f58d10 JB |
102 | } |
103 | ||
104 | static void s_bss (int); | |
105 | ||
106 | int | |
17b9d67d | 107 | md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) |
49f58d10 JB |
108 | { |
109 | switch (c) | |
110 | { | |
111 | case OPTION_CPU_M16C: | |
112 | m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C; | |
113 | m32c_mach = bfd_mach_m16c; | |
114 | cpu_mach = (1 << MACH_M16C); | |
115 | set_isa (ISA_M16C); | |
116 | break; | |
117 | ||
118 | case OPTION_CPU_M32C: | |
119 | m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C; | |
120 | m32c_mach = bfd_mach_m32c; | |
121 | cpu_mach = (1 << MACH_M32C); | |
122 | set_isa (ISA_M32C); | |
123 | break; | |
124 | ||
6772dd07 DD |
125 | case OPTION_LINKRELAX: |
126 | m32c_relax = 1; | |
127 | break; | |
128 | ||
c54b5932 DD |
129 | case OPTION_H_TICK_HEX: |
130 | enable_h_tick_hex = 1; | |
131 | break; | |
132 | ||
49f58d10 JB |
133 | default: |
134 | return 0; | |
135 | } | |
136 | return 1; | |
137 | } | |
138 | ||
139 | void | |
140 | md_show_usage (FILE * stream) | |
141 | { | |
142 | fprintf (stream, _(" M32C specific command line options:\n")); | |
3739860c | 143 | } |
49f58d10 JB |
144 | |
145 | static void | |
146 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
147 | { | |
148 | int temp; | |
149 | ||
150 | temp = get_absolute_expression (); | |
151 | subseg_set (bss_section, (subsegT) temp); | |
152 | demand_empty_rest_of_line (); | |
153 | } | |
154 | ||
155 | /* The target specific pseudo-ops which we support. */ | |
156 | const pseudo_typeS md_pseudo_table[] = | |
157 | { | |
158 | { "bss", s_bss, 0}, | |
7bc4c13c | 159 | { "3byte", cons, 3 }, |
49f58d10 JB |
160 | { "word", cons, 4 }, |
161 | { NULL, NULL, 0 } | |
162 | }; | |
163 | ||
164 | \f | |
165 | void | |
166 | md_begin (void) | |
167 | { | |
168 | /* Initialize the `cgen' interface. */ | |
6772dd07 | 169 | |
49f58d10 JB |
170 | /* Set the machine number and endian. */ |
171 | gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach, | |
172 | CGEN_CPU_OPEN_ENDIAN, | |
173 | CGEN_ENDIAN_BIG, | |
4fb1e3d3 | 174 | CGEN_CPU_OPEN_ISAS, & m32c_isa, |
49f58d10 JB |
175 | CGEN_CPU_OPEN_END); |
176 | ||
177 | m32c_cgen_init_asm (gas_cgen_cpu_desc); | |
178 | ||
179 | /* This is a callback from cgen to gas to parse operands. */ | |
180 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
181 | ||
182 | /* Set the ELF flags if desired. */ | |
183 | if (m32c_flags) | |
184 | bfd_set_private_flags (stdoutput, m32c_flags); | |
185 | ||
186 | /* Set the machine type */ | |
187 | bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach); | |
188 | ||
189 | insn_size = 0; | |
190 | } | |
191 | ||
192 | void | |
193 | m32c_md_end (void) | |
194 | { | |
195 | int i, n_nops; | |
196 | ||
bbc434cb DD |
197 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
198 | { | |
199 | /* Pad with nops for objdump. */ | |
200 | n_nops = (32 - ((insn_size) % 32)) / 8; | |
201 | for (i = 1; i <= n_nops; i++) | |
f854977c | 202 | md_assemble ((char *) "nop"); |
bbc434cb | 203 | } |
49f58d10 JB |
204 | } |
205 | ||
206 | void | |
207 | m32c_start_line_hook (void) | |
208 | { | |
209 | #if 0 /* not necessary....handled in the .cpu file */ | |
210 | char *s = input_line_pointer; | |
211 | char *sg; | |
212 | ||
213 | for (s = input_line_pointer ; s && s[0] != '\n'; s++) | |
214 | { | |
215 | if (s[0] == ':') | |
216 | { | |
217 | /* Remove :g suffix. Squeeze out blanks. */ | |
218 | if (s[1] == 'g') | |
219 | { | |
220 | for (sg = s - 1; sg && sg >= input_line_pointer; sg--) | |
221 | { | |
222 | sg[2] = sg[0]; | |
223 | } | |
224 | sg[1] = ' '; | |
225 | sg[2] = ' '; | |
226 | input_line_pointer += 2; | |
227 | } | |
228 | } | |
229 | } | |
230 | #endif | |
231 | } | |
232 | ||
233 | /* Process [[indirect-operands]] in instruction str. */ | |
234 | ||
235 | static bfd_boolean | |
236 | m32c_indirect_operand (char *str) | |
237 | { | |
238 | char *new_str; | |
239 | char *s; | |
240 | char *ns; | |
241 | int ns_len; | |
242 | char *ns_end; | |
243 | enum indirect_type {none, relative, absolute} ; | |
244 | enum indirect_type indirection [3] = { none, none, none }; | |
245 | int brace_n [3] = { 0, 0, 0 }; | |
246 | int operand; | |
247 | ||
248 | s = str; | |
249 | operand = 1; | |
250 | for (s = str; *s; s++) | |
251 | { | |
252 | if (s[0] == ',') | |
253 | operand = 2; | |
254 | /* [abs] where abs is not a0 or a1 */ | |
255 | if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1')) | |
256 | && (ISBLANK (s[0]) || s[0] == ',')) | |
257 | indirection[operand] = absolute; | |
258 | if (s[0] == ']' && s[1] == ']') | |
259 | indirection[operand] = relative; | |
260 | if (s[0] == '[' && s[1] == '[') | |
261 | indirection[operand] = relative; | |
262 | } | |
3739860c | 263 | |
49f58d10 JB |
264 | if (indirection[1] == none && indirection[2] == none) |
265 | return FALSE; | |
3739860c | 266 | |
49f58d10 JB |
267 | operand = 1; |
268 | ns_len = strlen (str); | |
325801bd | 269 | new_str = XNEWVEC (char, ns_len); |
49f58d10 JB |
270 | ns = new_str; |
271 | ns_end = ns + ns_len; | |
3739860c | 272 | |
49f58d10 JB |
273 | for (s = str; *s; s++) |
274 | { | |
275 | if (s[0] == ',') | |
276 | operand = 2; | |
3739860c | 277 | |
49f58d10 JB |
278 | if (s[0] == '[' && ! brace_n[operand]) |
279 | { | |
280 | brace_n[operand] += 1; | |
281 | /* Squeeze [[ to [ if this is an indirect operand. */ | |
282 | if (indirection[operand] != none) | |
283 | continue; | |
284 | } | |
3739860c | 285 | |
49f58d10 JB |
286 | else if (s[0] == '[' && brace_n[operand]) |
287 | { | |
288 | brace_n[operand] += 1; | |
289 | } | |
290 | else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative) | |
291 | { | |
292 | s += 1; /* skip one ]. */ | |
293 | brace_n[operand] -= 2; /* allow for 2 [. */ | |
294 | } | |
295 | else if (s[0] == ']' && indirection[operand] == absolute) | |
296 | { | |
297 | brace_n[operand] -= 1; | |
298 | continue; /* skip closing ]. */ | |
299 | } | |
300 | else if (s[0] == ']') | |
301 | { | |
302 | brace_n[operand] -= 1; | |
303 | } | |
304 | *ns = s[0]; | |
305 | ns += 1; | |
306 | if (ns >= ns_end) | |
307 | return FALSE; | |
308 | if (s[0] == 0) | |
309 | break; | |
310 | } | |
311 | *ns = '\0'; | |
312 | for (operand = 1; operand <= 2; operand++) | |
313 | if (brace_n[operand]) | |
314 | { | |
315 | fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]); | |
316 | } | |
3739860c | 317 | |
49f58d10 | 318 | if (indirection[1] != none && indirection[2] != none) |
f854977c | 319 | md_assemble ((char *) "src-dest-indirect"); |
49f58d10 | 320 | else if (indirection[1] != none) |
f854977c | 321 | md_assemble ((char *) "src-indirect"); |
49f58d10 | 322 | else if (indirection[2] != none) |
f854977c | 323 | md_assemble ((char *) "dest-indirect"); |
49f58d10 JB |
324 | |
325 | md_assemble (new_str); | |
326 | free (new_str); | |
327 | return TRUE; | |
328 | } | |
329 | ||
330 | void | |
331 | md_assemble (char * str) | |
332 | { | |
333 | static int last_insn_had_delay_slot = 0; | |
334 | m32c_insn insn; | |
335 | char * errmsg; | |
6772dd07 DD |
336 | finished_insnS results; |
337 | int rl_type; | |
49f58d10 JB |
338 | |
339 | if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str)) | |
340 | return; | |
341 | ||
342 | /* Initialize GAS's cgen interface for a new instruction. */ | |
343 | gas_cgen_init_parse (); | |
344 | ||
345 | insn.insn = m32c_cgen_assemble_insn | |
346 | (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); | |
3739860c | 347 | |
49f58d10 JB |
348 | if (!insn.insn) |
349 | { | |
6b73c529 | 350 | as_bad ("%s", errmsg); |
49f58d10 JB |
351 | return; |
352 | } | |
353 | ||
6772dd07 | 354 | results.num_fixups = 0; |
49f58d10 JB |
355 | /* Doesn't really matter what we pass for RELAX_P here. */ |
356 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
6772dd07 | 357 | CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results); |
49f58d10 JB |
358 | |
359 | last_insn_had_delay_slot | |
360 | = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); | |
87975d2a | 361 | (void) last_insn_had_delay_slot; |
49f58d10 | 362 | insn_size = CGEN_INSN_BITSIZE(insn.insn); |
6772dd07 DD |
363 | |
364 | rl_type = rl_for (insn); | |
365 | ||
366 | /* We have to mark all the jumps, because we need to adjust them | |
367 | when we delete bytes, but we only need to mark the displacements | |
368 | if they're symbolic - if they're not, we've already picked the | |
369 | shortest opcode by now. The linker, however, will still have to | |
370 | check any operands to see if they're the displacement type, since | |
371 | we don't know (nor record) *which* operands are relaxable. */ | |
372 | if (m32c_relax | |
373 | && rl_type != RL_TYPE_NONE | |
374 | && (rl_type == RL_TYPE_JUMP || results.num_fixups) | |
375 | && !relaxable (insn)) | |
376 | { | |
377 | int reloc = 0; | |
378 | int addend = results.num_fixups + 16 * insn_size/8; | |
379 | ||
380 | switch (rl_for (insn)) | |
381 | { | |
382 | case RL_TYPE_JUMP: reloc = BFD_RELOC_M32C_RL_JUMP; break; | |
383 | case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break; | |
384 | case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break; | |
385 | } | |
386 | if (insn.insn->base->num == M32C_INSN_JMP16_S | |
387 | || insn.insn->base->num == M32C_INSN_JMP32_S) | |
388 | addend = 0x10; | |
389 | ||
390 | fix_new (results.frag, | |
391 | results.addr - results.frag->fr_literal, | |
392 | 0, abs_section_sym, addend, 0, | |
393 | reloc); | |
394 | } | |
49f58d10 JB |
395 | } |
396 | ||
397 | /* The syntax in the manual says constants begin with '#'. | |
398 | We just ignore it. */ | |
399 | ||
3739860c | 400 | void |
49f58d10 JB |
401 | md_operand (expressionS * exp) |
402 | { | |
403 | /* In case of a syntax error, escape back to try next syntax combo. */ | |
404 | if (exp->X_op == O_absent) | |
405 | gas_cgen_md_operand (exp); | |
406 | } | |
407 | ||
408 | valueT | |
409 | md_section_align (segT segment, valueT size) | |
410 | { | |
411 | int align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 412 | return ((size + (1 << align) - 1) & -(1 << align)); |
49f58d10 JB |
413 | } |
414 | ||
415 | symbolS * | |
416 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
417 | { | |
418 | return 0; | |
419 | } | |
420 | \f | |
421 | const relax_typeS md_relax_table[] = | |
422 | { | |
423 | /* The fields are: | |
424 | 1) most positive reach of this state, | |
425 | 2) most negative reach of this state, | |
426 | 3) how many bytes this mode will have in the variable part of the frag | |
427 | 4) which index into the table to try if we can't fit into this one. */ | |
428 | ||
429 | /* 0 */ { 0, 0, 0, 0 }, /* unused */ | |
430 | /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */ | |
431 | ||
432 | /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */ | |
433 | /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */ | |
434 | /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */ | |
435 | ||
436 | /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */ | |
437 | /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */ | |
438 | /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */ | |
439 | ||
440 | /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */ | |
441 | /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */ | |
442 | /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */ | |
443 | /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */ | |
444 | ||
445 | /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */ | |
446 | /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */ | |
447 | /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */ | |
448 | ||
449 | /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */ | |
450 | /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */ | |
451 | /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */ | |
d14c4fad DD |
452 | /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */ |
453 | ||
454 | /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */ | |
455 | /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */ | |
456 | /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */ | |
144f4bc6 DD |
457 | /* 22 */ { 0, 0, 4, 0 }, /* jsr32.a */ |
458 | ||
459 | /* 23 */ { 0, 0, 3, 0 }, /* adjnz pc8 */ | |
460 | /* 24 */ { 0, 0, 4, 0 }, /* adjnz disp8 pc8 */ | |
461 | /* 25 */ { 0, 0, 5, 0 }, /* adjnz disp16 pc8 */ | |
462 | /* 26 */ { 0, 0, 6, 0 } /* adjnz disp24 pc8 */ | |
49f58d10 JB |
463 | }; |
464 | ||
465 | enum { | |
466 | M32C_MACRO_JCND16_5_W, | |
467 | M32C_MACRO_JCND16_5_A, | |
468 | M32C_MACRO_JCND16_W, | |
469 | M32C_MACRO_JCND16_A, | |
470 | M32C_MACRO_JCND32_W, | |
471 | M32C_MACRO_JCND32_A, | |
144f4bc6 DD |
472 | /* the digit is the array index of the pcrel byte */ |
473 | M32C_MACRO_ADJNZ_2, | |
474 | M32C_MACRO_ADJNZ_3, | |
475 | M32C_MACRO_ADJNZ_4, | |
476 | M32C_MACRO_ADJNZ_5, | |
85e53f62 | 477 | }; |
49f58d10 JB |
478 | |
479 | static struct { | |
480 | int insn; | |
481 | int bytes; | |
482 | int insn_for_extern; | |
483 | int pcrel_aim_offset; | |
484 | } subtype_mappings[] = { | |
485 | /* 0 */ { 0, 0, 0, 0 }, | |
486 | /* 1 */ { 0, 0, 0, 0 }, | |
487 | ||
488 | /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 }, | |
489 | /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 }, | |
490 | /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 }, | |
491 | ||
492 | /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 }, | |
493 | /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 }, | |
494 | /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 }, | |
495 | ||
496 | /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 }, | |
497 | /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 }, | |
498 | /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 }, | |
499 | /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 }, | |
500 | ||
501 | /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 }, | |
502 | /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 }, | |
503 | /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 }, | |
504 | ||
505 | /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 }, | |
506 | /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 }, | |
507 | /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 }, | |
d14c4fad DD |
508 | /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 }, |
509 | ||
510 | /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 }, | |
511 | /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 }, | |
512 | /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 }, | |
144f4bc6 DD |
513 | /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 }, |
514 | ||
515 | /* 23 */ { -M32C_MACRO_ADJNZ_2, 3, -M32C_MACRO_ADJNZ_2, 0 }, | |
516 | /* 24 */ { -M32C_MACRO_ADJNZ_3, 4, -M32C_MACRO_ADJNZ_3, 0 }, | |
517 | /* 25 */ { -M32C_MACRO_ADJNZ_4, 5, -M32C_MACRO_ADJNZ_4, 0 }, | |
518 | /* 26 */ { -M32C_MACRO_ADJNZ_5, 6, -M32C_MACRO_ADJNZ_5, 0 } | |
49f58d10 JB |
519 | }; |
520 | #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0])) | |
521 | ||
522 | void | |
523 | m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state) | |
524 | { | |
525 | symbolS *symbolP = fragP->fr_symbol; | |
526 | if (symbolP && !S_IS_DEFINED (symbolP)) | |
527 | *aim = 0; | |
528 | /* Adjust for m32c pcrel not being relative to the next opcode. */ | |
529 | *aim += subtype_mappings[this_state].pcrel_aim_offset; | |
530 | } | |
531 | ||
532 | static int | |
144f4bc6 | 533 | insn_to_subtype (int inum, const CGEN_INSN *insn) |
49f58d10 JB |
534 | { |
535 | unsigned int i; | |
144f4bc6 DD |
536 | |
537 | if (insn | |
538 | && (strncmp (insn->base->mnemonic, "adjnz", 5) == 0 | |
539 | || strncmp (insn->base->mnemonic, "sbjnz", 5) == 0)) | |
540 | { | |
541 | i = 23 + insn->base->bitsize/8 - 3; | |
542 | /*printf("mapping %d used for %s\n", i, insn->base->mnemonic);*/ | |
543 | return i; | |
544 | } | |
545 | ||
49f58d10 | 546 | for (i=0; i<NUM_MAPPINGS; i++) |
144f4bc6 | 547 | if (inum == subtype_mappings[i].insn) |
49f58d10 JB |
548 | { |
549 | /*printf("mapping %d used\n", i);*/ | |
550 | return i; | |
551 | } | |
552 | abort (); | |
553 | } | |
554 | ||
555 | /* Return an initial guess of the length by which a fragment must grow to | |
556 | hold a branch to reach its destination. | |
557 | Also updates fr_type/fr_subtype as necessary. | |
558 | ||
559 | Called just before doing relaxation. | |
560 | Any symbol that is now undefined will not become defined. | |
561 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
562 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
563 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
564 | 0 value. */ | |
565 | ||
566 | int | |
567 | md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED) | |
568 | { | |
569 | int where = fragP->fr_opcode - fragP->fr_literal; | |
570 | ||
571 | if (fragP->fr_subtype == 1) | |
144f4bc6 | 572 | fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num, fragP->fr_cgen.insn); |
49f58d10 JB |
573 | |
574 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
575 | { | |
576 | int new_insn; | |
577 | ||
578 | new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern; | |
144f4bc6 | 579 | fragP->fr_subtype = insn_to_subtype (new_insn, 0); |
49f58d10 JB |
580 | } |
581 | ||
582 | if (fragP->fr_cgen.insn->base | |
583 | && fragP->fr_cgen.insn->base->num | |
584 | != subtype_mappings[fragP->fr_subtype].insn | |
585 | && subtype_mappings[fragP->fr_subtype].insn > 0) | |
586 | { | |
587 | int new_insn= subtype_mappings[fragP->fr_subtype].insn; | |
588 | if (new_insn >= 0) | |
589 | { | |
590 | fragP->fr_cgen.insn = (fragP->fr_cgen.insn | |
591 | - fragP->fr_cgen.insn->base->num | |
592 | + new_insn); | |
593 | } | |
594 | } | |
595 | ||
596 | return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where); | |
3739860c | 597 | } |
49f58d10 JB |
598 | |
599 | /* *fragP has been relaxed to its final size, and now needs to have | |
600 | the bytes inside it modified to conform to the new size. | |
601 | ||
602 | Called after relaxation is finished. | |
603 | fragP->fr_type == rs_machine_dependent. | |
604 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
605 | ||
606 | static int | |
607 | target_address_for (fragS *frag) | |
608 | { | |
609 | int rv = frag->fr_offset; | |
610 | symbolS *sym = frag->fr_symbol; | |
611 | ||
612 | if (sym) | |
613 | rv += S_GET_VALUE (sym); | |
614 | ||
615 | /*printf("target_address_for returns %d\n", rv);*/ | |
616 | return rv; | |
617 | } | |
618 | ||
619 | void | |
620 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, | |
621 | segT sec ATTRIBUTE_UNUSED, | |
622 | fragS * fragP ATTRIBUTE_UNUSED) | |
623 | { | |
624 | int addend; | |
625 | int operand; | |
49f58d10 | 626 | int where = fragP->fr_opcode - fragP->fr_literal; |
6772dd07 | 627 | int rl_where = fragP->fr_opcode - fragP->fr_literal; |
49f58d10 | 628 | unsigned char *op = (unsigned char *)fragP->fr_opcode; |
6772dd07 | 629 | int rl_addend = 0; |
49f58d10 JB |
630 | |
631 | addend = target_address_for (fragP) - (fragP->fr_address + where); | |
49f58d10 JB |
632 | |
633 | fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes; | |
634 | ||
635 | switch (subtype_mappings[fragP->fr_subtype].insn) | |
636 | { | |
637 | case M32C_INSN_JCND16_5: | |
638 | op[1] = addend - 1; | |
639 | operand = M32C_OPERAND_LAB_8_8; | |
6772dd07 | 640 | rl_addend = 0x21; |
49f58d10 JB |
641 | break; |
642 | ||
643 | case -M32C_MACRO_JCND16_5_W: | |
644 | op[0] ^= 0x04; | |
645 | op[1] = 4; | |
646 | op[2] = 0xf4; | |
647 | op[3] = addend - 3; | |
648 | op[4] = (addend - 3) >> 8; | |
649 | operand = M32C_OPERAND_LAB_8_16; | |
650 | where += 2; | |
6772dd07 | 651 | rl_addend = 0x51; |
49f58d10 JB |
652 | break; |
653 | ||
654 | case -M32C_MACRO_JCND16_5_A: | |
655 | op[0] ^= 0x04; | |
656 | op[1] = 5; | |
657 | op[2] = 0xfc; | |
658 | operand = M32C_OPERAND_LAB_8_24; | |
659 | where += 2; | |
6772dd07 | 660 | rl_addend = 0x61; |
49f58d10 JB |
661 | break; |
662 | ||
663 | ||
664 | case M32C_INSN_JCND16: | |
665 | op[2] = addend - 2; | |
666 | operand = M32C_OPERAND_LAB_16_8; | |
6772dd07 | 667 | rl_addend = 0x31; |
49f58d10 JB |
668 | break; |
669 | ||
670 | case -M32C_MACRO_JCND16_W: | |
671 | op[1] ^= 0x04; | |
672 | op[2] = 4; | |
673 | op[3] = 0xf4; | |
674 | op[4] = addend - 4; | |
675 | op[5] = (addend - 4) >> 8; | |
676 | operand = M32C_OPERAND_LAB_8_16; | |
677 | where += 3; | |
6772dd07 | 678 | rl_addend = 0x61; |
49f58d10 JB |
679 | break; |
680 | ||
681 | case -M32C_MACRO_JCND16_A: | |
682 | op[1] ^= 0x04; | |
683 | op[2] = 5; | |
684 | op[3] = 0xfc; | |
685 | operand = M32C_OPERAND_LAB_8_24; | |
686 | where += 3; | |
6772dd07 | 687 | rl_addend = 0x71; |
49f58d10 JB |
688 | break; |
689 | ||
690 | case M32C_INSN_JMP16_S: | |
691 | op[0] = 0x60 | ((addend-2) & 0x07); | |
692 | operand = M32C_OPERAND_LAB_5_3; | |
6772dd07 | 693 | rl_addend = 0x10; |
49f58d10 JB |
694 | break; |
695 | ||
696 | case M32C_INSN_JMP16_B: | |
697 | op[0] = 0xfe; | |
698 | op[1] = addend - 1; | |
699 | operand = M32C_OPERAND_LAB_8_8; | |
6772dd07 | 700 | rl_addend = 0x21; |
49f58d10 JB |
701 | break; |
702 | ||
703 | case M32C_INSN_JMP16_W: | |
704 | op[0] = 0xf4; | |
705 | op[1] = addend - 1; | |
706 | op[2] = (addend - 1) >> 8; | |
707 | operand = M32C_OPERAND_LAB_8_16; | |
6772dd07 | 708 | rl_addend = 0x31; |
49f58d10 JB |
709 | break; |
710 | ||
711 | case M32C_INSN_JMP16_A: | |
712 | op[0] = 0xfc; | |
713 | op[1] = 0; | |
714 | op[2] = 0; | |
715 | op[3] = 0; | |
716 | operand = M32C_OPERAND_LAB_8_24; | |
6772dd07 | 717 | rl_addend = 0x41; |
49f58d10 JB |
718 | break; |
719 | ||
720 | case M32C_INSN_JCND32: | |
721 | op[1] = addend - 1; | |
722 | operand = M32C_OPERAND_LAB_8_8; | |
6772dd07 | 723 | rl_addend = 0x21; |
49f58d10 JB |
724 | break; |
725 | ||
726 | case -M32C_MACRO_JCND32_W: | |
727 | op[0] ^= 0x40; | |
728 | op[1] = 4; | |
729 | op[2] = 0xce; | |
730 | op[3] = addend - 3; | |
731 | op[4] = (addend - 3) >> 8; | |
732 | operand = M32C_OPERAND_LAB_8_16; | |
733 | where += 2; | |
6772dd07 | 734 | rl_addend = 0x51; |
49f58d10 JB |
735 | break; |
736 | ||
737 | case -M32C_MACRO_JCND32_A: | |
738 | op[0] ^= 0x40; | |
739 | op[1] = 5; | |
740 | op[2] = 0xcc; | |
741 | operand = M32C_OPERAND_LAB_8_24; | |
742 | where += 2; | |
6772dd07 | 743 | rl_addend = 0x61; |
49f58d10 JB |
744 | break; |
745 | ||
49f58d10 JB |
746 | case M32C_INSN_JMP32_S: |
747 | addend = ((addend-2) & 0x07); | |
748 | op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30); | |
749 | operand = M32C_OPERAND_LAB32_JMP_S; | |
6772dd07 | 750 | rl_addend = 0x10; |
49f58d10 JB |
751 | break; |
752 | ||
753 | case M32C_INSN_JMP32_B: | |
754 | op[0] = 0xbb; | |
755 | op[1] = addend - 1; | |
756 | operand = M32C_OPERAND_LAB_8_8; | |
6772dd07 | 757 | rl_addend = 0x21; |
49f58d10 JB |
758 | break; |
759 | ||
760 | case M32C_INSN_JMP32_W: | |
761 | op[0] = 0xce; | |
762 | op[1] = addend - 1; | |
763 | op[2] = (addend - 1) >> 8; | |
764 | operand = M32C_OPERAND_LAB_8_16; | |
6772dd07 | 765 | rl_addend = 0x31; |
49f58d10 JB |
766 | break; |
767 | ||
768 | case M32C_INSN_JMP32_A: | |
769 | op[0] = 0xcc; | |
770 | op[1] = 0; | |
771 | op[2] = 0; | |
772 | op[3] = 0; | |
773 | operand = M32C_OPERAND_LAB_8_24; | |
6772dd07 | 774 | rl_addend = 0x41; |
49f58d10 JB |
775 | break; |
776 | ||
777 | ||
d14c4fad DD |
778 | case M32C_INSN_JSR16_W: |
779 | op[0] = 0xf5; | |
780 | op[1] = addend - 1; | |
781 | op[2] = (addend - 1) >> 8; | |
782 | operand = M32C_OPERAND_LAB_8_16; | |
6772dd07 | 783 | rl_addend = 0x31; |
d14c4fad DD |
784 | break; |
785 | ||
786 | case M32C_INSN_JSR16_A: | |
787 | op[0] = 0xfd; | |
788 | op[1] = 0; | |
789 | op[2] = 0; | |
790 | op[3] = 0; | |
791 | operand = M32C_OPERAND_LAB_8_24; | |
6772dd07 | 792 | rl_addend = 0x41; |
d14c4fad DD |
793 | break; |
794 | ||
795 | case M32C_INSN_JSR32_W: | |
796 | op[0] = 0xcf; | |
797 | op[1] = addend - 1; | |
798 | op[2] = (addend - 1) >> 8; | |
799 | operand = M32C_OPERAND_LAB_8_16; | |
6772dd07 | 800 | rl_addend = 0x31; |
d14c4fad DD |
801 | break; |
802 | ||
803 | case M32C_INSN_JSR32_A: | |
804 | op[0] = 0xcd; | |
805 | op[1] = 0; | |
806 | op[2] = 0; | |
807 | op[3] = 0; | |
808 | operand = M32C_OPERAND_LAB_8_24; | |
6772dd07 | 809 | rl_addend = 0x41; |
d14c4fad DD |
810 | break; |
811 | ||
144f4bc6 DD |
812 | case -M32C_MACRO_ADJNZ_2: |
813 | rl_addend = 0x31; | |
911c9c13 | 814 | op[2] = addend - 2; |
144f4bc6 DD |
815 | operand = M32C_OPERAND_LAB_16_8; |
816 | break; | |
817 | case -M32C_MACRO_ADJNZ_3: | |
818 | rl_addend = 0x41; | |
911c9c13 | 819 | op[3] = addend - 2; |
144f4bc6 DD |
820 | operand = M32C_OPERAND_LAB_24_8; |
821 | break; | |
822 | case -M32C_MACRO_ADJNZ_4: | |
823 | rl_addend = 0x51; | |
911c9c13 | 824 | op[4] = addend - 2; |
144f4bc6 DD |
825 | operand = M32C_OPERAND_LAB_32_8; |
826 | break; | |
827 | case -M32C_MACRO_ADJNZ_5: | |
828 | rl_addend = 0x61; | |
911c9c13 | 829 | op[5] = addend - 2; |
144f4bc6 DD |
830 | operand = M32C_OPERAND_LAB_40_8; |
831 | break; | |
d14c4fad | 832 | |
49f58d10 JB |
833 | default: |
834 | printf("\nHey! Need more opcode converters! missing: %d %s\n\n", | |
835 | fragP->fr_subtype, | |
836 | fragP->fr_cgen.insn->base->name); | |
837 | abort(); | |
838 | } | |
839 | ||
6772dd07 DD |
840 | if (m32c_relax) |
841 | { | |
842 | if (operand != M32C_OPERAND_LAB_8_24) | |
843 | fragP->fr_offset = (fragP->fr_address + where); | |
844 | ||
845 | fix_new (fragP, | |
846 | rl_where, | |
847 | 0, abs_section_sym, rl_addend, 0, | |
848 | BFD_RELOC_M32C_RL_JUMP); | |
849 | } | |
850 | ||
49f58d10 | 851 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
6772dd07 DD |
852 | || operand == M32C_OPERAND_LAB_8_24 |
853 | || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3 | |
854 | && operand != M32C_OPERAND_LAB32_JMP_S))) | |
49f58d10 | 855 | { |
9c2799c2 | 856 | gas_assert (fragP->fr_cgen.insn != 0); |
87975d2a AM |
857 | gas_cgen_record_fixup (fragP, |
858 | where, | |
859 | fragP->fr_cgen.insn, | |
860 | (fragP->fr_fix - where) * 8, | |
861 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
862 | operand), | |
863 | fragP->fr_cgen.opinfo, | |
864 | fragP->fr_symbol, | |
865 | fragP->fr_offset); | |
49f58d10 JB |
866 | } |
867 | } | |
868 | \f | |
869 | /* Functions concerning relocs. */ | |
870 | ||
871 | /* The location from which a PC relative jump should be calculated, | |
872 | given a PC relative reloc. */ | |
873 | ||
874 | long | |
875 | md_pcrel_from_section (fixS * fixP, segT sec) | |
876 | { | |
877 | if (fixP->fx_addsy != (symbolS *) NULL | |
878 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
879 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
880 | /* The symbol is undefined (or is defined but not in this section). | |
881 | Let the linker figure it out. */ | |
882 | return 0; | |
883 | ||
884 | return (fixP->fx_frag->fr_address + fixP->fx_where); | |
885 | } | |
886 | ||
887 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
888 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
889 | *FIXP may be modified if desired. */ | |
890 | ||
891 | bfd_reloc_code_real_type | |
892 | md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, | |
893 | const CGEN_OPERAND * operand, | |
894 | fixS * fixP ATTRIBUTE_UNUSED) | |
895 | { | |
896 | static const struct op_reloc { | |
897 | /* A CGEN operand type that can be a relocatable expression. */ | |
898 | CGEN_OPERAND_TYPE operand; | |
899 | ||
900 | /* The appropriate BFD reloc type to use for that. */ | |
901 | bfd_reloc_code_real_type reloc; | |
902 | ||
903 | /* The offset from the start of the instruction to the field to be | |
904 | relocated, in bytes. */ | |
905 | int offset; | |
906 | } op_reloc_table[] = { | |
907 | ||
cab0a0db | 908 | /* PC-REL relocs for 8-bit fields. */ |
6772dd07 | 909 | { M32C_OPERAND_LAB_8_8, BFD_RELOC_8_PCREL, 1 }, |
cab0a0db DD |
910 | { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 }, |
911 | { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 }, | |
912 | { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 }, | |
913 | { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 }, | |
914 | ||
6772dd07 DD |
915 | /* PC-REL relocs for 16-bit fields. */ |
916 | { M32C_OPERAND_LAB_8_16, BFD_RELOC_16_PCREL, 1 }, | |
917 | ||
fd54057a DD |
918 | /* Absolute relocs for 8-bit fields. */ |
919 | { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 }, | |
920 | { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 }, | |
921 | { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 }, | |
922 | { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 }, | |
923 | { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 }, | |
924 | { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 }, | |
925 | { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 }, | |
926 | { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 }, | |
927 | { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 }, | |
928 | { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 }, | |
929 | { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 }, | |
930 | { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 }, | |
931 | { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 }, | |
932 | { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 }, | |
933 | { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 }, | |
934 | { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 }, | |
935 | { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 }, | |
936 | { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 }, | |
937 | { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 }, | |
6b73c529 DD |
938 | { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 }, |
939 | { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 }, | |
940 | { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 }, | |
941 | { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 }, | |
fd54057a | 942 | |
49f58d10 | 943 | /* Absolute relocs for 16-bit fields. */ |
6b73c529 | 944 | { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 }, |
49f58d10 JB |
945 | { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 }, |
946 | { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 }, | |
947 | { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 }, | |
cab0a0db DD |
948 | { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 }, |
949 | { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 }, | |
950 | { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 }, | |
951 | { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 }, | |
49f58d10 JB |
952 | { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 }, |
953 | { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 }, | |
954 | { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 }, | |
955 | { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 }, | |
956 | { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 }, | |
957 | { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 }, | |
958 | { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 }, | |
959 | { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 }, | |
cab0a0db DD |
960 | { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 }, |
961 | { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 }, | |
6b73c529 DD |
962 | { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 }, |
963 | { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 }, | |
964 | { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 }, | |
965 | { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 }, | |
49f58d10 JB |
966 | |
967 | /* Absolute relocs for 24-bit fields. */ | |
968 | { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 }, | |
6b73c529 | 969 | { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 }, |
cab0a0db | 970 | { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 }, |
49f58d10 JB |
971 | { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 }, |
972 | { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 }, | |
973 | { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 }, | |
974 | { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 }, | |
cab0a0db DD |
975 | { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 }, |
976 | { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 }, | |
977 | { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 }, | |
978 | { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 }, | |
6b73c529 DD |
979 | { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 }, |
980 | { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 }, | |
49f58d10 JB |
981 | |
982 | /* Absolute relocs for 32-bit fields. */ | |
983 | { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 }, | |
984 | { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 }, | |
985 | { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 }, | |
986 | { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 }, | |
987 | ||
988 | }; | |
989 | ||
990 | int i; | |
991 | ||
992 | for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; ) | |
993 | { | |
994 | const struct op_reloc *or = &op_reloc_table[i]; | |
995 | ||
996 | if (or->operand == operand->type) | |
997 | { | |
998 | fixP->fx_where += or->offset; | |
999 | fixP->fx_size -= or->offset; | |
fd54057a DD |
1000 | |
1001 | if (fixP->fx_cgen.opinfo | |
1002 | && fixP->fx_cgen.opinfo != BFD_RELOC_NONE) | |
1003 | return fixP->fx_cgen.opinfo; | |
1004 | ||
49f58d10 JB |
1005 | return or->reloc; |
1006 | } | |
1007 | } | |
1008 | ||
1009 | fprintf | |
1010 | (stderr, | |
cab0a0db DD |
1011 | "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n", |
1012 | operand->name); | |
49f58d10 JB |
1013 | |
1014 | return BFD_RELOC_NONE; | |
1015 | } | |
1016 | ||
e110eeb7 DD |
1017 | void |
1018 | m32c_cons_fix_new (fragS * frag, | |
1019 | int where, | |
1020 | int size, | |
62ebcb5c AM |
1021 | expressionS *exp, |
1022 | bfd_reloc_code_real_type type) | |
e110eeb7 | 1023 | { |
e110eeb7 DD |
1024 | switch (size) |
1025 | { | |
1026 | case 1: | |
1027 | type = BFD_RELOC_8; | |
1028 | break; | |
1029 | case 2: | |
1030 | type = BFD_RELOC_16; | |
1031 | break; | |
1032 | case 3: | |
1033 | type = BFD_RELOC_24; | |
1034 | break; | |
1035 | case 4: | |
1036 | default: | |
1037 | type = BFD_RELOC_32; | |
1038 | break; | |
1039 | case 8: | |
1040 | type = BFD_RELOC_64; | |
1041 | break; | |
1042 | } | |
1043 | ||
1044 | fix_new_exp (frag, where, (int) size, exp, 0, type); | |
1045 | } | |
1046 | ||
6772dd07 DD |
1047 | void |
1048 | m32c_apply_fix (struct fix *f, valueT *t, segT s) | |
1049 | { | |
1050 | if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP | |
1051 | || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR | |
1052 | || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR) | |
1053 | return; | |
1054 | gas_cgen_md_apply_fix (f, t, s); | |
1055 | } | |
1056 | ||
1057 | arelent * | |
1058 | tc_gen_reloc (asection *sec, fixS *fx) | |
1059 | { | |
1060 | if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP | |
1061 | || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR | |
1062 | || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR) | |
1063 | { | |
1064 | arelent * reloc; | |
3739860c | 1065 | |
325801bd | 1066 | reloc = XNEW (arelent); |
3739860c | 1067 | |
325801bd | 1068 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
6772dd07 DD |
1069 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy); |
1070 | reloc->address = fx->fx_frag->fr_address + fx->fx_where; | |
1071 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type); | |
1072 | reloc->addend = fx->fx_offset; | |
1073 | return reloc; | |
1074 | ||
1075 | } | |
1076 | return gas_cgen_tc_gen_reloc (sec, fx); | |
1077 | } | |
1078 | ||
49f58d10 JB |
1079 | /* See whether we need to force a relocation into the output file. |
1080 | This is used to force out switch and PC relative relocations when | |
1081 | relaxing. */ | |
1082 | ||
1083 | int | |
1084 | m32c_force_relocation (fixS * fixp) | |
1085 | { | |
1086 | int reloc = fixp->fx_r_type; | |
1087 | ||
1088 | if (reloc > (int)BFD_RELOC_UNUSED) | |
1089 | { | |
1090 | reloc -= (int)BFD_RELOC_UNUSED; | |
1091 | switch (reloc) | |
1092 | { | |
1093 | case M32C_OPERAND_DSP_32_S16: | |
1094 | case M32C_OPERAND_DSP_32_U16: | |
1095 | case M32C_OPERAND_IMM_32_HI: | |
1096 | case M32C_OPERAND_DSP_16_S16: | |
1097 | case M32C_OPERAND_DSP_16_U16: | |
1098 | case M32C_OPERAND_IMM_16_HI: | |
1099 | case M32C_OPERAND_DSP_24_S16: | |
1100 | case M32C_OPERAND_DSP_24_U16: | |
1101 | case M32C_OPERAND_IMM_24_HI: | |
1102 | return 1; | |
6772dd07 DD |
1103 | |
1104 | /* If we're doing linker relaxing, we need to keep all the | |
1105 | pc-relative jumps in case we need to fix them due to | |
1106 | deleted bytes between the jump and its destination. */ | |
1107 | case M32C_OPERAND_LAB_8_8: | |
1108 | case M32C_OPERAND_LAB_8_16: | |
1109 | case M32C_OPERAND_LAB_8_24: | |
1110 | case M32C_OPERAND_LAB_16_8: | |
1111 | case M32C_OPERAND_LAB_24_8: | |
1112 | case M32C_OPERAND_LAB_32_8: | |
1113 | case M32C_OPERAND_LAB_40_8: | |
1114 | if (m32c_relax) | |
1115 | return 1; | |
1116 | default: | |
1117 | break; | |
49f58d10 JB |
1118 | } |
1119 | } | |
1120 | else | |
1121 | { | |
6772dd07 DD |
1122 | switch (fixp->fx_r_type) |
1123 | { | |
1124 | case BFD_RELOC_16: | |
1125 | return 1; | |
1126 | ||
1127 | case BFD_RELOC_M32C_RL_JUMP: | |
1128 | case BFD_RELOC_M32C_RL_1ADDR: | |
1129 | case BFD_RELOC_M32C_RL_2ADDR: | |
1130 | case BFD_RELOC_8_PCREL: | |
1131 | case BFD_RELOC_16_PCREL: | |
1132 | if (m32c_relax) | |
1133 | return 1; | |
1134 | default: | |
1135 | break; | |
1136 | } | |
49f58d10 JB |
1137 | } |
1138 | ||
1139 | return generic_force_reloc (fixp); | |
1140 | } | |
1141 | \f | |
1142 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1143 | ||
1144 | void | |
1145 | md_number_to_chars (char * buf, valueT val, int n) | |
1146 | { | |
b96282be | 1147 | number_to_chars_littleendian (buf, val, n); |
49f58d10 JB |
1148 | } |
1149 | ||
1150 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1151 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1152 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ | |
1153 | ||
1154 | /* Equal to MAX_PRECISION in atof-ieee.c. */ | |
1155 | #define MAX_LITTLENUMS 6 | |
1156 | ||
6d4af3c2 | 1157 | const char * |
49f58d10 JB |
1158 | md_atof (int type, char * litP, int * sizeP) |
1159 | { | |
499ac353 | 1160 | return ieee_md_atof (type, litP, sizeP, TRUE); |
49f58d10 JB |
1161 | } |
1162 | ||
1163 | bfd_boolean | |
1164 | m32c_fix_adjustable (fixS * fixP) | |
1165 | { | |
1166 | int reloc; | |
1167 | if (fixP->fx_addsy == NULL) | |
1168 | return 1; | |
1169 | ||
1170 | /* We need the symbol name for the VTABLE entries. */ | |
1171 | reloc = fixP->fx_r_type; | |
1172 | if (reloc > (int)BFD_RELOC_UNUSED) | |
1173 | { | |
1174 | reloc -= (int)BFD_RELOC_UNUSED; | |
1175 | switch (reloc) | |
1176 | { | |
1177 | case M32C_OPERAND_DSP_32_S16: | |
1178 | case M32C_OPERAND_DSP_32_U16: | |
1179 | case M32C_OPERAND_IMM_32_HI: | |
1180 | case M32C_OPERAND_DSP_16_S16: | |
1181 | case M32C_OPERAND_DSP_16_U16: | |
1182 | case M32C_OPERAND_IMM_16_HI: | |
1183 | case M32C_OPERAND_DSP_24_S16: | |
1184 | case M32C_OPERAND_DSP_24_U16: | |
1185 | case M32C_OPERAND_IMM_24_HI: | |
1186 | return 0; | |
1187 | } | |
1188 | } | |
1189 | else | |
1190 | { | |
1191 | if (fixP->fx_r_type == BFD_RELOC_16) | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | /* Do not adjust relocations involving symbols in merged sections. | |
1196 | ||
1197 | A reloc patching in the value of some symbol S plus some addend A | |
1198 | can be produced in different ways: | |
1199 | ||
1200 | 1) It might simply be a reference to the data at S + A. Clearly, | |
1201 | if linker merging shift that data around, the value patched in | |
1202 | by the reloc needs to be adjusted accordingly. | |
1203 | ||
1204 | 2) Or, it might be a reference to S, with A added in as a constant | |
1205 | bias. For example, given code like this: | |
1206 | ||
1207 | static int S[100]; | |
1208 | ||
1209 | ... S[i - 8] ... | |
1210 | ||
1211 | it would be reasonable for the compiler to rearrange the array | |
1212 | reference to something like: | |
1213 | ||
1214 | ... (S-8)[i] ... | |
1215 | ||
1216 | and emit assembly code that refers to S - (8 * sizeof (int)), | |
1217 | so the subtraction is done entirely at compile-time. In this | |
1218 | case, the reloc's addend A would be -(8 * sizeof (int)), and | |
1219 | shifting around code or data at S + A should not affect the | |
1220 | reloc: the reloc isn't referring to that code or data at all. | |
1221 | ||
1222 | The linker has no way of knowing which case it has in hand. So, | |
1223 | to disambiguate, we have the linker always treat reloc addends as | |
1224 | in case 2): they're constants that should be simply added to the | |
1225 | symbol value, just like the reloc says. And we express case 1) | |
1226 | in different way: we have the compiler place a label at the real | |
1227 | target, and reference that label with an addend of zero. (The | |
1228 | compiler is unlikely to reference code using a label plus an | |
1229 | offset anyway, since it doesn't know the sizes of the | |
1230 | instructions.) | |
1231 | ||
1232 | The simplification being done by gas/write.c:adjust_reloc_syms, | |
1233 | however, turns the explicit-label usage into the label-plus- | |
1234 | offset usage, re-introducing the ambiguity the compiler avoided. | |
1235 | So we need to disable that simplification for symbols referring | |
1236 | to merged data. | |
1237 | ||
1238 | This only affects object size a little bit. */ | |
1239 | if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) | |
1240 | return 0; | |
1241 | ||
6772dd07 DD |
1242 | if (m32c_relax) |
1243 | return 0; | |
1244 | ||
49f58d10 JB |
1245 | return 1; |
1246 | } | |
1247 | ||
1248 | /* Worker function for m32c_is_colon_insn(). */ | |
2e57ce7b AM |
1249 | static int |
1250 | restore_colon (char *next_i_l_p, char *nul_char) | |
49f58d10 | 1251 | { |
49f58d10 JB |
1252 | /* Restore the colon, and advance input_line_pointer to |
1253 | the end of the new symbol. */ | |
2e57ce7b AM |
1254 | *input_line_pointer = *nul_char; |
1255 | input_line_pointer = next_i_l_p; | |
1256 | *nul_char = *next_i_l_p; | |
1257 | *next_i_l_p = 0; | |
1258 | return 1; | |
49f58d10 JB |
1259 | } |
1260 | ||
1261 | /* Determines if the symbol starting at START and ending in | |
1262 | a colon that was at the location pointed to by INPUT_LINE_POINTER | |
1263 | (but which has now been replaced bu a NUL) is in fact an | |
1264 | :Z, :S, :Q, or :G suffix. | |
1265 | If it is, then it restores the colon, advances INPUT_LINE_POINTER | |
2e57ce7b AM |
1266 | to the real end of the instruction/symbol, saves the char there to |
1267 | NUL_CHAR and pokes a NUL, and returns 1. Otherwise it returns 0. */ | |
1268 | int | |
1269 | m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED, char *nul_char) | |
49f58d10 JB |
1270 | { |
1271 | char * i_l_p = input_line_pointer; | |
1272 | ||
2e57ce7b AM |
1273 | if (*nul_char == '"') |
1274 | ++i_l_p; | |
1275 | ||
49f58d10 JB |
1276 | /* Check to see if the text following the colon is 'G' */ |
1277 | if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
2e57ce7b | 1278 | return restore_colon (i_l_p + 2, nul_char); |
49f58d10 JB |
1279 | |
1280 | /* Check to see if the text following the colon is 'Q' */ | |
1281 | if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
2e57ce7b | 1282 | return restore_colon (i_l_p + 2, nul_char); |
49f58d10 JB |
1283 | |
1284 | /* Check to see if the text following the colon is 'S' */ | |
1285 | if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
2e57ce7b | 1286 | return restore_colon (i_l_p + 2, nul_char); |
49f58d10 JB |
1287 | |
1288 | /* Check to see if the text following the colon is 'Z' */ | |
1289 | if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
2e57ce7b | 1290 | return restore_colon (i_l_p + 2, nul_char); |
49f58d10 JB |
1291 | |
1292 | return 0; | |
1293 | } |