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252b5132 RH |
1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
2 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation. | |
3 | ||
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "symcat.h" | |
26 | #include "opcodes/m32r-desc.h" | |
27 | #include "opcodes/m32r-opc.h" | |
28 | #include "cgen.h" | |
29 | ||
30 | /* Linked list of symbols that are debugging symbols to be defined as the | |
31 | beginning of the current instruction. */ | |
32 | typedef struct sym_link | |
33 | { | |
34 | struct sym_link *next; | |
35 | symbolS *symbol; | |
36 | } sym_linkS; | |
37 | ||
38 | static sym_linkS *debug_sym_link = (sym_linkS *)0; | |
39 | ||
40 | /* Structure to hold all of the different components describing | |
41 | an individual instruction. */ | |
42 | typedef struct | |
43 | { | |
44 | const CGEN_INSN * insn; | |
45 | const CGEN_INSN * orig_insn; | |
46 | CGEN_FIELDS fields; | |
47 | #if CGEN_INT_INSN_P | |
48 | CGEN_INSN_INT buffer [1]; | |
49 | #define INSN_VALUE(buf) (*(buf)) | |
50 | #else | |
51 | unsigned char buffer [CGEN_MAX_INSN_SIZE]; | |
52 | #define INSN_VALUE(buf) (buf) | |
53 | #endif | |
54 | char * addr; | |
55 | fragS * frag; | |
56 | int num_fixups; | |
57 | fixS * fixups [GAS_CGEN_MAX_FIXUPS]; | |
58 | int indices [MAX_OPERAND_INSTANCES]; | |
59 | sym_linkS *debug_sym_link; | |
60 | } | |
61 | m32r_insn; | |
62 | ||
63 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
64 | boundary (i.e. was the first of two 16 bit insns). */ | |
65 | static m32r_insn prev_insn; | |
66 | ||
67 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
68 | alignment request. */ | |
69 | static int seen_relaxable_p = 0; | |
70 | ||
71 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
72 | for the linker to do relaxing. | |
73 | We do simple forms of relaxing internally, but they are always done. | |
74 | This flag does not apply to them. */ | |
75 | static int m32r_relax; | |
76 | ||
77 | #if 0 /* not supported yet */ | |
78 | /* If non-NULL, pointer to cpu description file to read. | |
79 | This allows runtime additions to the assembler. */ | |
80 | static const char * m32r_cpu_desc; | |
81 | #endif | |
82 | ||
83 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. | |
84 | Each high/shigh reloc must be paired with it's low cousin in order to | |
85 | properly calculate the addend in a relocatable link (since there is a | |
86 | potential carry from the low to the high/shigh). | |
87 | This option is off by default though for user-written assembler code it | |
88 | might make sense to make the default be on (i.e. have gcc pass a flag | |
89 | to turn it off). This warning must not be on for GCC created code as | |
90 | optimization may delete the low but not the high/shigh (at least we | |
91 | shouldn't assume or require it to). */ | |
92 | static int warn_unmatched_high = 0; | |
93 | ||
94 | ||
95 | /* stuff for .scomm symbols. */ | |
96 | static segT sbss_section; | |
97 | static asection scom_section; | |
98 | static asymbol scom_symbol; | |
99 | ||
100 | const char comment_chars[] = ";"; | |
101 | const char line_comment_chars[] = "#"; | |
102 | const char line_separator_chars[] = ""; | |
103 | const char EXP_CHARS[] = "eE"; | |
104 | const char FLT_CHARS[] = "dD"; | |
105 | ||
106 | /* Relocations against symbols are done in two | |
107 | parts, with a HI relocation and a LO relocation. Each relocation | |
108 | has only 16 bits of space to store an addend. This means that in | |
109 | order for the linker to handle carries correctly, it must be able | |
110 | to locate both the HI and the LO relocation. This means that the | |
111 | relocations must appear in order in the relocation table. | |
112 | ||
113 | In order to implement this, we keep track of each unmatched HI | |
114 | relocation. We then sort them so that they immediately precede the | |
115 | corresponding LO relocation. */ | |
116 | ||
117 | struct m32r_hi_fixup | |
118 | { | |
119 | struct m32r_hi_fixup * next; /* Next HI fixup. */ | |
120 | fixS * fixp; /* This fixup. */ | |
121 | segT seg; /* The section this fixup is in. */ | |
122 | ||
123 | }; | |
124 | ||
125 | /* The list of unmatched HI relocs. */ | |
126 | ||
127 | static struct m32r_hi_fixup * m32r_hi_fixup_list; | |
128 | ||
129 | \f | |
130 | \f | |
131 | #define M32R_SHORTOPTS "" | |
132 | const char * md_shortopts = M32R_SHORTOPTS; | |
133 | ||
134 | struct option md_longopts[] = | |
135 | { | |
136 | ||
137 | /* Sigh. I guess all warnings must now have both variants. */ | |
138 | #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4) | |
2f3519a2 NC |
139 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
140 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
252b5132 | 141 | #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5) |
2f3519a2 NC |
142 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
143 | {"Wnuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
252b5132 RH |
144 | |
145 | #if 0 /* not supported yet */ | |
146 | #define OPTION_RELAX (OPTION_MD_BASE + 6) | |
147 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
148 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 7) | |
149 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, | |
150 | #endif | |
151 | ||
152 | {NULL, no_argument, NULL, 0} | |
153 | }; | |
154 | size_t md_longopts_size = sizeof (md_longopts); | |
155 | ||
156 | int | |
157 | md_parse_option (c, arg) | |
158 | int c; | |
159 | char * arg; | |
160 | { | |
161 | switch (c) | |
162 | { | |
163 | ||
164 | case OPTION_WARN_UNMATCHED: | |
165 | warn_unmatched_high = 1; | |
166 | break; | |
167 | ||
168 | case OPTION_NO_WARN_UNMATCHED: | |
169 | warn_unmatched_high = 0; | |
170 | break; | |
171 | ||
172 | #if 0 /* not supported yet */ | |
173 | case OPTION_RELAX: | |
174 | m32r_relax = 1; | |
175 | break; | |
176 | case OPTION_CPU_DESC: | |
177 | m32r_cpu_desc = arg; | |
178 | break; | |
179 | #endif | |
180 | ||
181 | default: | |
2f3519a2 NC |
182 | if (arg) |
183 | fprintf (stderr, _("%s: unrecognised command line option: -%c\n"), myname, c); | |
184 | else | |
185 | fprintf (stderr, _("%s: unrecognised command line option: -%c%s\n"), myname, c, arg); | |
252b5132 RH |
186 | return 0; |
187 | } | |
188 | return 1; | |
189 | } | |
190 | ||
191 | void | |
192 | md_show_usage (stream) | |
193 | FILE * stream; | |
194 | { | |
195 | fprintf (stream, _(" M32R specific command line options:\n")); | |
196 | ||
197 | ||
198 | fprintf (stream, _("\ | |
199 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
200 | fprintf (stream, _("\ | |
201 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
202 | fprintf (stream, _("\ | |
203 | -Wuh synonym for -warn-unmatched-high\n")); | |
204 | fprintf (stream, _("\ | |
205 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
206 | ||
207 | #if 0 | |
208 | fprintf (stream, _("\ | |
209 | -relax create linker relaxable code\n")); | |
210 | fprintf (stream, _("\ | |
211 | -cpu-desc provide runtime cpu description file\n")); | |
212 | #endif | |
213 | } | |
214 | ||
215 | static void fill_insn PARAMS ((int)); | |
216 | static void m32r_scomm PARAMS ((int)); | |
217 | static void debug_sym PARAMS ((int)); | |
218 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
219 | ||
220 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
221 | static subsegT prev_subseg; | |
222 | static segT prev_seg; | |
223 | ||
224 | /* The target specific pseudo-ops which we support. */ | |
225 | const pseudo_typeS md_pseudo_table[] = | |
226 | { | |
227 | { "word", cons, 4 }, | |
228 | { "fillinsn", fill_insn, 0 }, | |
229 | { "scomm", m32r_scomm, 0 }, | |
230 | { "debugsym", debug_sym, 0 }, | |
231 | { NULL, NULL, 0 } | |
232 | }; | |
233 | ||
234 | /* FIXME: Should be machine generated. */ | |
235 | #define NOP_INSN 0x7000 | |
236 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
237 | ||
238 | /* When we align the .text section, insert the correct NOP pattern. | |
239 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
240 | MAX is the maximum number of characters to skip when doing the alignment, | |
241 | or 0 if there is no maximum. */ | |
242 | ||
243 | int | |
244 | m32r_do_align (n, fill, len, max) | |
245 | int n; | |
246 | const char * fill; | |
247 | int len; | |
248 | int max; | |
249 | { | |
250 | /* Only do this if the fill pattern wasn't specified. */ | |
251 | if (fill == NULL | |
b9e57a38 | 252 | && subseg_text_p (now_seg) |
252b5132 RH |
253 | /* Only do this special handling if aligning to at least a |
254 | 4 byte boundary. */ | |
255 | && n > 1 | |
256 | /* Only do this special handling if we're allowed to emit at | |
257 | least two bytes. */ | |
258 | && (max == 0 || max > 1)) | |
259 | { | |
260 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
261 | ||
262 | #if 0 | |
263 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
264 | /* FIXME: How much memory will cause gas to use when assembling a big | |
265 | program? Perhaps we can avoid the frag_align call? */ | |
266 | frag_align (1, 0, 0); | |
267 | #endif | |
268 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
269 | nop. */ | |
270 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
271 | /* If doing larger alignments use a repeating sequence of appropriate | |
272 | nops. */ | |
273 | if (n > 2) | |
274 | { | |
275 | static const unsigned char multi_nop_pattern[] = | |
276 | { 0x70, 0x00, 0xf0, 0x00 }; | |
277 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, | |
278 | max ? max - 2 : 0); | |
279 | } | |
280 | ||
281 | prev_insn.insn = NULL; | |
282 | return 1; | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | /* If the last instruction was the first of 2 16 bit insns, | |
289 | output a nop to move the PC to a 32 bit boundary. | |
290 | ||
291 | This is done via an alignment specification since branch relaxing | |
292 | may make it unnecessary. | |
293 | ||
294 | Internally, we need to output one of these each time a 32 bit insn is | |
295 | seen after an insn that is relaxable. */ | |
296 | ||
297 | static void | |
298 | fill_insn (ignore) | |
299 | int ignore; | |
300 | { | |
301 | (void) m32r_do_align (2, NULL, 0, 0); | |
302 | prev_insn.insn = NULL; | |
303 | seen_relaxable_p = 0; | |
304 | } | |
305 | ||
306 | /* Record the symbol so that when we output the insn, we can create | |
307 | a symbol that is at the start of the instruction. This is used | |
308 | to emit the label for the start of a breakpoint without causing | |
309 | the assembler to emit a NOP if the previous instruction was a | |
310 | 16 bit instruction. */ | |
311 | ||
312 | static void | |
313 | debug_sym (ignore) | |
314 | int ignore; | |
315 | { | |
316 | register char *name; | |
317 | register char delim; | |
318 | register char *end_name; | |
319 | register symbolS *symbolP; | |
320 | register sym_linkS *link; | |
321 | ||
322 | name = input_line_pointer; | |
323 | delim = get_symbol_end (); | |
324 | end_name = input_line_pointer; | |
325 | ||
326 | if ((symbolP = symbol_find (name)) == NULL | |
327 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
328 | { | |
329 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
330 | } | |
331 | ||
332 | symbol_table_insert (symbolP); | |
333 | if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) | |
334 | /* xgettext:c-format */ | |
335 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
336 | ||
337 | else | |
338 | { | |
339 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
340 | link->symbol = symbolP; | |
341 | link->next = debug_sym_link; | |
342 | debug_sym_link = link; | |
f412ead8 | 343 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
344 | } |
345 | ||
346 | *end_name = delim; | |
347 | demand_empty_rest_of_line (); | |
348 | } | |
349 | ||
350 | /* Second pass to expanding the debug symbols, go through linked | |
351 | list of symbols and reassign the address. */ | |
352 | ||
353 | static void | |
354 | expand_debug_syms (syms, align) | |
355 | sym_linkS *syms; | |
356 | int align; | |
357 | { | |
358 | char *save_input_line = input_line_pointer; | |
359 | sym_linkS *next_syms; | |
360 | ||
361 | if (!syms) | |
362 | return; | |
363 | ||
364 | (void) m32r_do_align (align, NULL, 0, 0); | |
365 | for (; syms != (sym_linkS *)0; syms = next_syms) | |
366 | { | |
367 | symbolS *symbolP = syms->symbol; | |
368 | next_syms = syms->next; | |
369 | input_line_pointer = ".\n"; | |
370 | pseudo_set (symbolP); | |
371 | free ((char *)syms); | |
372 | } | |
373 | ||
374 | input_line_pointer = save_input_line; | |
375 | } | |
376 | ||
377 | /* Cover function to fill_insn called after a label and at end of assembly. | |
378 | The result is always 1: we're called in a conditional to see if the | |
379 | current line is a label. */ | |
380 | ||
381 | int | |
382 | m32r_fill_insn (done) | |
383 | int done; | |
384 | { | |
385 | if (prev_seg != NULL) | |
386 | { | |
387 | segT seg = now_seg; | |
388 | subsegT subseg = now_subseg; | |
389 | ||
390 | subseg_set (prev_seg, prev_subseg); | |
391 | ||
392 | fill_insn (0); | |
393 | ||
394 | subseg_set (seg, subseg); | |
395 | } | |
396 | ||
397 | if (done && debug_sym_link) | |
398 | { | |
399 | expand_debug_syms (debug_sym_link, 1); | |
400 | debug_sym_link = (sym_linkS *)0; | |
401 | } | |
402 | ||
403 | return 1; | |
404 | } | |
405 | \f | |
406 | void | |
407 | md_begin () | |
408 | { | |
409 | flagword applicable; | |
410 | segT seg; | |
411 | subsegT subseg; | |
412 | ||
413 | /* Initialize the `cgen' interface. */ | |
414 | ||
415 | /* Set the machine number and endian. */ | |
416 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
417 | CGEN_CPU_OPEN_ENDIAN, | |
418 | CGEN_ENDIAN_BIG, | |
419 | CGEN_CPU_OPEN_END); | |
420 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
421 | ||
422 | /* The operand instance table is used during optimization to determine | |
423 | which insns can be executed in parallel. It is also used to give | |
424 | warnings regarding operand interference in parallel insns. */ | |
425 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
426 | ||
427 | /* This is a callback from cgen to gas to parse operands. */ | |
428 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
429 | ||
430 | #if 0 /* not supported yet */ | |
431 | /* If a runtime cpu description file was provided, parse it. */ | |
432 | if (m32r_cpu_desc != NULL) | |
433 | { | |
434 | const char * errmsg; | |
435 | ||
436 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); | |
437 | if (errmsg != NULL) | |
438 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
439 | } | |
440 | #endif | |
441 | ||
442 | /* Save the current subseg so we can restore it [it's the default one and | |
443 | we don't want the initial section to be .sbss]. */ | |
444 | seg = now_seg; | |
445 | subseg = now_subseg; | |
446 | ||
447 | /* The sbss section is for local .scomm symbols. */ | |
448 | sbss_section = subseg_new (".sbss", 0); | |
449 | ||
450 | /* This is copied from perform_an_assembly_pass. */ | |
451 | applicable = bfd_applicable_section_flags (stdoutput); | |
452 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
453 | ||
454 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ | |
455 | seg_info (bss_section)->bss = 1; | |
456 | #endif | |
457 | ||
458 | subseg_set (seg, subseg); | |
459 | ||
460 | /* We must construct a fake section similar to bfd_com_section | |
461 | but with the name .scommon. */ | |
462 | scom_section = bfd_com_section; | |
463 | scom_section.name = ".scommon"; | |
464 | scom_section.output_section = & scom_section; | |
465 | scom_section.symbol = & scom_symbol; | |
466 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
467 | scom_symbol = * bfd_com_section.symbol; | |
468 | scom_symbol.name = ".scommon"; | |
469 | scom_symbol.section = & scom_section; | |
470 | ||
471 | } | |
472 | ||
473 | ||
474 | ||
475 | void | |
476 | md_assemble (str) | |
477 | char * str; | |
478 | { | |
479 | m32r_insn insn; | |
480 | char * errmsg; | |
481 | char * str2 = NULL; | |
482 | ||
483 | /* Initialize GAS's cgen interface for a new instruction. */ | |
484 | gas_cgen_init_parse (); | |
485 | ||
486 | ||
487 | insn.debug_sym_link = debug_sym_link; | |
488 | debug_sym_link = (sym_linkS *)0; | |
489 | ||
490 | insn.insn = m32r_cgen_assemble_insn | |
491 | (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); | |
492 | ||
493 | if (!insn.insn) | |
494 | { | |
495 | as_bad (errmsg); | |
496 | return; | |
497 | } | |
498 | ||
499 | ||
500 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
501 | { | |
502 | /* 32 bit insns must live on 32 bit boundaries. */ | |
503 | if (prev_insn.insn || seen_relaxable_p) | |
504 | { | |
505 | /* ??? If calling fill_insn too many times turns us into a memory | |
506 | pig, can we call a fn to assemble a nop instead of | |
507 | !seen_relaxable_p? */ | |
508 | fill_insn (0); | |
509 | } | |
510 | ||
511 | expand_debug_syms (insn.debug_sym_link, 2); | |
512 | ||
513 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
514 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
515 | CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); | |
516 | } | |
517 | else | |
518 | { | |
519 | int on_32bit_boundary_p; | |
520 | ||
521 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
522 | abort(); | |
523 | ||
524 | insn.orig_insn = insn.insn; | |
525 | ||
526 | /* Compute whether we're on a 32 bit boundary or not. | |
527 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
528 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
529 | ||
530 | ||
531 | expand_debug_syms (insn.debug_sym_link, 1); | |
532 | ||
533 | { | |
534 | int i; | |
535 | finished_insnS fi; | |
536 | ||
537 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
538 | frag_grow (4); | |
539 | ||
540 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
541 | CGEN_FIELDS_BITSIZE (& insn.fields), | |
542 | 1 /*relax_p*/, &fi); | |
543 | insn.addr = fi.addr; | |
544 | insn.frag = fi.frag; | |
545 | insn.num_fixups = fi.num_fixups; | |
546 | for (i = 0; i < fi.num_fixups; ++i) | |
547 | insn.fixups[i] = fi.fixups[i]; | |
548 | } | |
549 | ||
550 | ||
551 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
552 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
553 | if (on_32bit_boundary_p) | |
554 | prev_insn = insn; | |
555 | else | |
556 | prev_insn.insn = NULL; | |
557 | ||
558 | /* If the insn needs the following one to be on a 32 bit boundary | |
559 | (e.g. subroutine calls), fill this insn's slot. */ | |
560 | if (on_32bit_boundary_p | |
561 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
562 | fill_insn (0); | |
563 | ||
564 | /* If this is a relaxable insn (can be replaced with a larger version) | |
565 | mark the fact so that we can emit an alignment directive for a | |
566 | following 32 bit insn if we see one. */ | |
567 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
568 | seen_relaxable_p = 1; | |
569 | } | |
570 | ||
571 | /* Set these so m32r_fill_insn can use them. */ | |
572 | prev_seg = now_seg; | |
573 | prev_subseg = now_subseg; | |
574 | } | |
575 | ||
576 | /* The syntax in the manual says constants begin with '#'. | |
577 | We just ignore it. */ | |
578 | ||
579 | void | |
580 | md_operand (expressionP) | |
581 | expressionS * expressionP; | |
582 | { | |
583 | if (* input_line_pointer == '#') | |
584 | { | |
585 | input_line_pointer ++; | |
586 | expression (expressionP); | |
587 | } | |
588 | } | |
589 | ||
590 | valueT | |
591 | md_section_align (segment, size) | |
592 | segT segment; | |
593 | valueT size; | |
594 | { | |
595 | int align = bfd_get_section_alignment (stdoutput, segment); | |
596 | return ((size + (1 << align) - 1) & (-1 << align)); | |
597 | } | |
598 | ||
599 | symbolS * | |
600 | md_undefined_symbol (name) | |
601 | char * name; | |
602 | { | |
603 | return 0; | |
604 | } | |
605 | \f | |
606 | /* .scomm pseudo-op handler. | |
607 | ||
608 | This is a new pseudo-op to handle putting objects in .scommon. | |
609 | By doing this the linker won't need to do any work and more importantly | |
610 | it removes the implicit -G arg necessary to correctly link the object file. | |
611 | */ | |
612 | ||
613 | static void | |
614 | m32r_scomm (ignore) | |
615 | int ignore; | |
616 | { | |
617 | register char * name; | |
618 | register char c; | |
619 | register char * p; | |
620 | offsetT size; | |
621 | register symbolS * symbolP; | |
622 | offsetT align; | |
623 | int align2; | |
624 | ||
625 | name = input_line_pointer; | |
626 | c = get_symbol_end (); | |
627 | ||
628 | /* just after name is now '\0' */ | |
629 | p = input_line_pointer; | |
630 | * p = c; | |
631 | SKIP_WHITESPACE (); | |
632 | if (* input_line_pointer != ',') | |
633 | { | |
634 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
635 | ignore_rest_of_line (); | |
636 | return; | |
637 | } | |
638 | ||
639 | input_line_pointer ++; /* skip ',' */ | |
640 | if ((size = get_absolute_expression ()) < 0) | |
641 | { | |
642 | /* xgettext:c-format */ | |
643 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); | |
644 | ignore_rest_of_line (); | |
645 | return; | |
646 | } | |
647 | ||
648 | /* The third argument to .scomm is the alignment. */ | |
649 | if (* input_line_pointer != ',') | |
650 | align = 8; | |
651 | else | |
652 | { | |
653 | ++ input_line_pointer; | |
654 | align = get_absolute_expression (); | |
655 | if (align <= 0) | |
656 | { | |
657 | as_warn (_("ignoring bad alignment")); | |
658 | align = 8; | |
659 | } | |
660 | } | |
661 | /* Convert to a power of 2 alignment. */ | |
662 | if (align) | |
663 | { | |
664 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) | |
665 | continue; | |
666 | if (align != 1) | |
667 | { | |
668 | as_bad (_("Common alignment not a power of 2")); | |
669 | ignore_rest_of_line (); | |
670 | return; | |
671 | } | |
672 | } | |
673 | else | |
674 | align2 = 0; | |
675 | ||
676 | * p = 0; | |
677 | symbolP = symbol_find_or_make (name); | |
678 | * p = c; | |
679 | ||
680 | if (S_IS_DEFINED (symbolP)) | |
681 | { | |
682 | /* xgettext:c-format */ | |
683 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), | |
684 | S_GET_NAME (symbolP)); | |
685 | ignore_rest_of_line (); | |
686 | return; | |
687 | } | |
688 | ||
689 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
690 | { | |
691 | /* xgettext:c-format */ | |
692 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), | |
693 | S_GET_NAME (symbolP), | |
694 | (long) S_GET_VALUE (symbolP), | |
695 | (long) size); | |
696 | ||
697 | ignore_rest_of_line (); | |
698 | return; | |
699 | } | |
700 | ||
f412ead8 | 701 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
702 | { |
703 | segT old_sec = now_seg; | |
704 | int old_subsec = now_subseg; | |
705 | char * pfrag; | |
706 | ||
707 | record_alignment (sbss_section, align2); | |
708 | subseg_set (sbss_section, 0); | |
709 | ||
710 | if (align2) | |
711 | frag_align (align2, 0, 0); | |
712 | ||
713 | if (S_GET_SEGMENT (symbolP) == sbss_section) | |
f412ead8 | 714 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 | 715 | |
f412ead8 | 716 | symbol_set_frag (symbolP, frag_now); |
252b5132 RH |
717 | |
718 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, | |
719 | (char *) 0); | |
720 | * pfrag = 0; | |
721 | S_SET_SIZE (symbolP, size); | |
722 | S_SET_SEGMENT (symbolP, sbss_section); | |
723 | S_CLEAR_EXTERNAL (symbolP); | |
724 | subseg_set (old_sec, old_subsec); | |
725 | } | |
726 | else | |
727 | { | |
728 | S_SET_VALUE (symbolP, (valueT) size); | |
729 | S_SET_ALIGN (symbolP, align2); | |
730 | S_SET_EXTERNAL (symbolP); | |
731 | S_SET_SEGMENT (symbolP, & scom_section); | |
732 | } | |
733 | ||
734 | demand_empty_rest_of_line (); | |
735 | } | |
736 | \f | |
737 | /* Interface to relax_segment. */ | |
738 | ||
739 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
740 | ||
741 | const relax_typeS md_relax_table[] = | |
742 | { | |
743 | /* The fields are: | |
744 | 1) most positive reach of this state, | |
745 | 2) most negative reach of this state, | |
746 | 3) how many bytes this mode will add to the size of the current frag | |
747 | 4) which index into the table to try if we can't fit into this one. */ | |
748 | ||
749 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
750 | each list. */ | |
751 | {1, 1, 0, 0}, | |
752 | ||
753 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
754 | so we subtract 2 from the following. */ | |
755 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
756 | This doesn't handle a branch in the right slot at the border: | |
757 | the "& -4" isn't taken into account. It's not important enough to | |
758 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
759 | case). */ | |
760 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
761 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
762 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
763 | /* Same thing, but with leading nop for alignment. */ | |
764 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
765 | }; | |
766 | ||
767 | long | |
768 | m32r_relax_frag (fragP, stretch) | |
769 | fragS * fragP; | |
770 | long stretch; | |
771 | { | |
772 | /* Address of branch insn. */ | |
773 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
774 | long growth = 0; | |
775 | ||
776 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
777 | if (fragP->fr_subtype == 2) | |
778 | { | |
779 | if ((address & 3) != 0) | |
780 | { | |
781 | fragP->fr_subtype = 3; | |
782 | growth = 2; | |
783 | } | |
784 | } | |
785 | else if (fragP->fr_subtype == 3) | |
786 | { | |
787 | if ((address & 3) == 0) | |
788 | { | |
789 | fragP->fr_subtype = 2; | |
790 | growth = -2; | |
791 | } | |
792 | } | |
793 | else | |
794 | { | |
795 | growth = relax_frag (fragP, stretch); | |
796 | ||
797 | /* Long jump on odd halfword boundary? */ | |
798 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
799 | { | |
800 | fragP->fr_subtype = 3; | |
801 | growth += 2; | |
802 | } | |
803 | } | |
804 | ||
805 | return growth; | |
806 | } | |
807 | ||
808 | /* Return an initial guess of the length by which a fragment must grow to | |
809 | hold a branch to reach its destination. | |
810 | Also updates fr_type/fr_subtype as necessary. | |
811 | ||
812 | Called just before doing relaxation. | |
813 | Any symbol that is now undefined will not become defined. | |
814 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
815 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
816 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
817 | 0 value. */ | |
818 | ||
819 | int | |
820 | md_estimate_size_before_relax (fragP, segment) | |
821 | fragS * fragP; | |
822 | segT segment; | |
823 | { | |
824 | int old_fr_fix = fragP->fr_fix; | |
825 | ||
826 | /* The only thing we have to handle here are symbols outside of the | |
827 | current segment. They may be undefined or in a different segment in | |
828 | which case linker scripts may place them anywhere. | |
829 | However, we can't finish the fragment here and emit the reloc as insn | |
830 | alignment requirements may move the insn about. */ | |
831 | ||
832 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
833 | { | |
834 | /* The symbol is undefined in this segment. | |
835 | Change the relaxation subtype to the max allowable and leave | |
836 | all further handling to md_convert_frag. */ | |
837 | fragP->fr_subtype = 2; | |
838 | ||
839 | #if 0 /* Can't use this, but leave in for illustration. */ | |
840 | /* Change 16 bit insn to 32 bit insn. */ | |
841 | fragP->fr_opcode[0] |= 0x80; | |
842 | ||
843 | /* Increase known (fixed) size of fragment. */ | |
844 | fragP->fr_fix += 2; | |
845 | ||
846 | /* Create a relocation for it. */ | |
847 | fix_new (fragP, old_fr_fix, 4, | |
848 | fragP->fr_symbol, | |
849 | fragP->fr_offset, 1 /* pcrel */, | |
850 | /* FIXME: Can't use a real BFD reloc here. | |
851 | gas_cgen_md_apply_fix3 can't handle it. */ | |
852 | BFD_RELOC_M32R_26_PCREL); | |
853 | ||
854 | /* Mark this fragment as finished. */ | |
855 | frag_wane (fragP); | |
856 | #else | |
857 | { | |
858 | const CGEN_INSN * insn; | |
859 | int i; | |
860 | ||
861 | /* Update the recorded insn. | |
862 | Fortunately we don't have to look very far. | |
863 | FIXME: Change this to record in the instruction the next higher | |
864 | relaxable insn to use. */ | |
865 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
866 | { | |
867 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
868 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
869 | == 0) | |
870 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX)) | |
871 | break; | |
872 | } | |
873 | if (i == 4) | |
874 | abort (); | |
875 | ||
876 | fragP->fr_cgen.insn = insn; | |
877 | return 2; | |
878 | } | |
879 | #endif | |
880 | } | |
881 | ||
882 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
883 | } | |
884 | ||
885 | /* *fragP has been relaxed to its final size, and now needs to have | |
886 | the bytes inside it modified to conform to the new size. | |
887 | ||
888 | Called after relaxation is finished. | |
889 | fragP->fr_type == rs_machine_dependent. | |
890 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
891 | ||
892 | void | |
893 | md_convert_frag (abfd, sec, fragP) | |
894 | bfd * abfd; | |
895 | segT sec; | |
896 | fragS * fragP; | |
897 | { | |
898 | char * opcode; | |
899 | char * displacement; | |
900 | int target_address; | |
901 | int opcode_address; | |
902 | int extension; | |
903 | int addend; | |
904 | ||
905 | opcode = fragP->fr_opcode; | |
906 | ||
907 | /* Address opcode resides at in file space. */ | |
908 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
909 | ||
910 | switch (fragP->fr_subtype) | |
911 | { | |
912 | case 1 : | |
913 | extension = 0; | |
914 | displacement = & opcode[1]; | |
915 | break; | |
916 | case 2 : | |
917 | opcode[0] |= 0x80; | |
918 | extension = 2; | |
919 | displacement = & opcode[1]; | |
920 | break; | |
921 | case 3 : | |
922 | opcode[2] = opcode[0] | 0x80; | |
923 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
924 | opcode_address += 2; | |
925 | extension = 4; | |
926 | displacement = & opcode[3]; | |
927 | break; | |
928 | default : | |
929 | abort (); | |
930 | } | |
931 | ||
932 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
933 | { | |
934 | /* symbol must be resolved by linker */ | |
935 | if (fragP->fr_offset & 3) | |
936 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
937 | addend = fragP->fr_offset >> 2; | |
938 | } | |
939 | else | |
940 | { | |
941 | /* Address we want to reach in file space. */ | |
942 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
f412ead8 | 943 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
944 | addend = (target_address - (opcode_address & -4)) >> 2; |
945 | } | |
946 | ||
947 | /* Create a relocation for symbols that must be resolved by the linker. | |
948 | Otherwise output the completed insn. */ | |
949 | ||
950 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
951 | { | |
952 | assert (fragP->fr_subtype != 1); | |
953 | assert (fragP->fr_cgen.insn != 0); | |
954 | gas_cgen_record_fixup (fragP, | |
955 | /* Offset of branch insn in frag. */ | |
956 | fragP->fr_fix + extension - 4, | |
957 | fragP->fr_cgen.insn, | |
958 | 4 /*length*/, | |
959 | /* FIXME: quick hack */ | |
960 | #if 0 | |
961 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
962 | fragP->fr_cgen.opindex), | |
963 | #else | |
964 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
965 | M32R_OPERAND_DISP24), | |
966 | #endif | |
967 | fragP->fr_cgen.opinfo, | |
968 | fragP->fr_symbol, fragP->fr_offset); | |
969 | } | |
970 | ||
971 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
972 | ||
973 | md_number_to_chars (displacement, (valueT) addend, | |
974 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
975 | ||
976 | fragP->fr_fix += extension; | |
977 | } | |
978 | \f | |
979 | /* Functions concerning relocs. */ | |
980 | ||
981 | /* The location from which a PC relative jump should be calculated, | |
982 | given a PC relative reloc. */ | |
983 | ||
984 | long | |
985 | md_pcrel_from_section (fixP, sec) | |
986 | fixS * fixP; | |
987 | segT sec; | |
988 | { | |
989 | if (fixP->fx_addsy != (symbolS *) NULL | |
990 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
991 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
992 | { | |
993 | /* The symbol is undefined (or is defined but not in this section). | |
994 | Let the linker figure it out. */ | |
995 | return 0; | |
996 | } | |
997 | ||
998 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
999 | } | |
1000 | ||
1001 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1002 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1003 | *FIXP may be modified if desired. */ | |
1004 | ||
1005 | bfd_reloc_code_real_type | |
1006 | md_cgen_lookup_reloc (insn, operand, fixP) | |
1007 | const CGEN_INSN * insn; | |
1008 | const CGEN_OPERAND * operand; | |
1009 | fixS * fixP; | |
1010 | { | |
1011 | switch (operand->type) | |
1012 | { | |
1013 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1014 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1015 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1016 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1017 | case M32R_OPERAND_HI16 : | |
1018 | case M32R_OPERAND_SLO16 : | |
1019 | case M32R_OPERAND_ULO16 : | |
1020 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1021 | if (fixP->fx_cgen.opinfo != 0) | |
1022 | return fixP->fx_cgen.opinfo; | |
1023 | break; | |
1024 | default : /* avoid -Wall warning */ | |
1025 | break; | |
1026 | } | |
1027 | return BFD_RELOC_NONE; | |
1028 | } | |
1029 | ||
1030 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
1031 | ||
1032 | static void | |
1033 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1034 | int reloc_type; | |
1035 | fixS * fixP; | |
1036 | segT seg; | |
1037 | { | |
1038 | struct m32r_hi_fixup * hi_fixup; | |
1039 | ||
1040 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1041 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1042 | ||
1043 | hi_fixup = ((struct m32r_hi_fixup *) | |
1044 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1045 | hi_fixup->fixp = fixP; | |
1046 | hi_fixup->seg = now_seg; | |
1047 | hi_fixup->next = m32r_hi_fixup_list; | |
1048 | ||
1049 | m32r_hi_fixup_list = hi_fixup; | |
1050 | } | |
1051 | ||
1052 | /* Called while parsing an instruction to create a fixup. | |
1053 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1054 | ||
1055 | fixS * | |
1056 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
1057 | fragS * frag; | |
1058 | int where; | |
1059 | const CGEN_INSN * insn; | |
1060 | int length; | |
1061 | const CGEN_OPERAND * operand; | |
1062 | int opinfo; | |
1063 | expressionS * exp; | |
1064 | { | |
1065 | fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, | |
1066 | operand, opinfo, exp); | |
1067 | ||
1068 | switch (operand->type) | |
1069 | { | |
1070 | case M32R_OPERAND_HI16 : | |
1071 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1072 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1073 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1074 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
1075 | break; | |
1076 | default : /* avoid -Wall warning */ | |
1077 | break; | |
1078 | } | |
1079 | ||
1080 | return fixP; | |
1081 | } | |
1082 | ||
1083 | /* Return BFD reloc type from opinfo field in a fixS. | |
1084 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1085 | are BFD_RELOC_UNUSED + operand number. */ | |
1086 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
1087 | ||
1088 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1089 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1090 | tc_gen_reloc. */ | |
1091 | ||
1092 | void | |
1093 | m32r_frob_file () | |
1094 | { | |
1095 | struct m32r_hi_fixup * l; | |
1096 | ||
1097 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1098 | { | |
1099 | segment_info_type * seginfo; | |
1100 | int pass; | |
1101 | ||
1102 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1103 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1104 | ||
1105 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1106 | if (l->fixp->fx_next != NULL | |
1107 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1108 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1109 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1110 | continue; | |
1111 | ||
1112 | /* Look through the fixups for this segment for a matching `low'. | |
1113 | When we find one, move the high/shigh just in front of it. We do | |
1114 | this in two passes. In the first pass, we try to find a | |
1115 | unique `low'. In the second pass, we permit multiple high's | |
1116 | relocs for a single `low'. */ | |
1117 | seginfo = seg_info (l->seg); | |
1118 | for (pass = 0; pass < 2; pass++) | |
1119 | { | |
1120 | fixS * f; | |
1121 | fixS * prev; | |
1122 | ||
1123 | prev = NULL; | |
1124 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1125 | { | |
1126 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1127 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1128 | && f->fx_addsy == l->fixp->fx_addsy | |
1129 | && f->fx_offset == l->fixp->fx_offset | |
1130 | && (pass == 1 | |
1131 | || prev == NULL | |
1132 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1133 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1134 | || prev->fx_addsy != f->fx_addsy | |
1135 | || prev->fx_offset != f->fx_offset)) | |
1136 | { | |
1137 | fixS ** pf; | |
1138 | ||
1139 | /* Move l->fixp before f. */ | |
1140 | for (pf = &seginfo->fix_root; | |
1141 | * pf != l->fixp; | |
1142 | pf = & (* pf)->fx_next) | |
1143 | assert (* pf != NULL); | |
1144 | ||
1145 | * pf = l->fixp->fx_next; | |
1146 | ||
1147 | l->fixp->fx_next = f; | |
1148 | if (prev == NULL) | |
1149 | seginfo->fix_root = l->fixp; | |
1150 | else | |
1151 | prev->fx_next = l->fixp; | |
1152 | ||
1153 | break; | |
1154 | } | |
1155 | ||
1156 | prev = f; | |
1157 | } | |
1158 | ||
1159 | if (f != NULL) | |
1160 | break; | |
1161 | ||
1162 | if (pass == 1 | |
1163 | && warn_unmatched_high) | |
1164 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1165 | _("Unmatched high/shigh reloc")); | |
1166 | } | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | /* See whether we need to force a relocation into the output file. | |
1171 | This is used to force out switch and PC relative relocations when | |
1172 | relaxing. */ | |
1173 | ||
1174 | int | |
1175 | m32r_force_relocation (fix) | |
1176 | fixS * fix; | |
1177 | { | |
1178 | if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1179 | || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1180 | return 1; | |
1181 | ||
1182 | if (! m32r_relax) | |
1183 | return 0; | |
1184 | ||
1185 | return (fix->fx_pcrel | |
1186 | || 0 /* ??? */); | |
1187 | } | |
1188 | \f | |
1189 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1190 | ||
1191 | void | |
1192 | md_number_to_chars (buf, val, n) | |
1193 | char * buf; | |
1194 | valueT val; | |
1195 | int n; | |
1196 | { | |
1197 | if (target_big_endian) | |
1198 | number_to_chars_bigendian (buf, val, n); | |
1199 | else | |
1200 | number_to_chars_littleendian (buf, val, n); | |
1201 | } | |
1202 | ||
1203 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1204 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1205 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1206 | */ | |
1207 | ||
1208 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1209 | #define MAX_LITTLENUMS 6 | |
1210 | ||
1211 | char * | |
1212 | md_atof (type, litP, sizeP) | |
1213 | char type; | |
1214 | char *litP; | |
1215 | int *sizeP; | |
1216 | { | |
1217 | int i; | |
1218 | int prec; | |
1219 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1220 | char * t; | |
1221 | char * atof_ieee (); | |
1222 | ||
1223 | switch (type) | |
1224 | { | |
1225 | case 'f': | |
1226 | case 'F': | |
1227 | case 's': | |
1228 | case 'S': | |
1229 | prec = 2; | |
1230 | break; | |
1231 | ||
1232 | case 'd': | |
1233 | case 'D': | |
1234 | case 'r': | |
1235 | case 'R': | |
1236 | prec = 4; | |
1237 | break; | |
1238 | ||
1239 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1240 | ||
1241 | default: | |
1242 | * sizeP = 0; | |
1243 | return _("Bad call to md_atof()"); | |
1244 | } | |
1245 | ||
1246 | t = atof_ieee (input_line_pointer, type, words); | |
1247 | if (t) | |
1248 | input_line_pointer = t; | |
1249 | * sizeP = prec * sizeof (LITTLENUM_TYPE); | |
1250 | ||
1251 | if (target_big_endian) | |
1252 | { | |
1253 | for (i = 0; i < prec; i++) | |
1254 | { | |
1255 | md_number_to_chars (litP, (valueT) words[i], | |
1256 | sizeof (LITTLENUM_TYPE)); | |
1257 | litP += sizeof (LITTLENUM_TYPE); | |
1258 | } | |
1259 | } | |
1260 | else | |
1261 | { | |
1262 | for (i = prec - 1; i >= 0; i--) | |
1263 | { | |
1264 | md_number_to_chars (litP, (valueT) words[i], | |
1265 | sizeof (LITTLENUM_TYPE)); | |
1266 | litP += sizeof (LITTLENUM_TYPE); | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | void | |
1274 | m32r_elf_section_change_hook () | |
1275 | { | |
1276 | /* If we have reached the end of a section and we have just emitted a | |
1277 | 16 bit insn, then emit a nop to make sure that the section ends on | |
1278 | a 32 bit boundary. */ | |
1279 | ||
1280 | if (prev_insn.insn || seen_relaxable_p) | |
1281 | (void) m32r_fill_insn (0); | |
1282 | } | |
1283 | ||
1284 | boolean | |
1285 | m32r_fix_adjustable (fixP) | |
1286 | fixS *fixP; | |
1287 | { | |
1288 | ||
1289 | if (fixP->fx_addsy == NULL) | |
1290 | return 1; | |
1291 | ||
1292 | /* Prevent all adjustments to global symbols. */ | |
1293 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
1294 | return 0; | |
1295 | if (S_IS_WEAK (fixP->fx_addsy)) | |
1296 | return 0; | |
1297 | ||
1298 | /* We need the symbol name for the VTABLE entries */ | |
1299 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1300 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1301 | return 0; | |
1302 | ||
1303 | return 1; | |
1304 | } |