Commit | Line | Data |
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4bf4a882 | 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
ebd1c875 | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, |
20203fb9 | 3 | 2006, 2007, 2009 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
ab3e48dc | 24 | #include "subsegs.h" |
252b5132 RH |
25 | #include "symcat.h" |
26 | #include "opcodes/m32r-desc.h" | |
27 | #include "opcodes/m32r-opc.h" | |
28 | #include "cgen.h" | |
88845958 | 29 | #include "elf/m32r.h" |
252b5132 RH |
30 | |
31 | /* Linked list of symbols that are debugging symbols to be defined as the | |
32 | beginning of the current instruction. */ | |
33 | typedef struct sym_link | |
34 | { | |
35 | struct sym_link *next; | |
ab3e48dc | 36 | symbolS *symbol; |
252b5132 RH |
37 | } sym_linkS; |
38 | ||
ab3e48dc KH |
39 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
40 | ||
252b5132 RH |
41 | /* Structure to hold all of the different components describing |
42 | an individual instruction. */ | |
43 | typedef struct | |
44 | { | |
ab3e48dc KH |
45 | const CGEN_INSN *insn; |
46 | const CGEN_INSN *orig_insn; | |
47 | CGEN_FIELDS fields; | |
252b5132 | 48 | #if CGEN_INT_INSN_P |
ab3e48dc | 49 | CGEN_INSN_INT buffer[1]; |
252b5132 RH |
50 | #define INSN_VALUE(buf) (*(buf)) |
51 | #else | |
ab3e48dc | 52 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
252b5132 RH |
53 | #define INSN_VALUE(buf) (buf) |
54 | #endif | |
ab3e48dc KH |
55 | char *addr; |
56 | fragS *frag; | |
57 | int num_fixups; | |
58 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; | |
59 | int indices[MAX_OPERAND_INSTANCES]; | |
60 | sym_linkS *debug_sym_link; | |
252b5132 RH |
61 | } |
62 | m32r_insn; | |
63 | ||
64 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
65 | boundary (i.e. was the first of two 16 bit insns). */ | |
ab3e48dc | 66 | static m32r_insn prev_insn; |
252b5132 RH |
67 | |
68 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
69 | alignment request. */ | |
70 | static int seen_relaxable_p = 0; | |
71 | ||
6edf0760 NC |
72 | /* Non-zero if we are generating PIC code. */ |
73 | int pic_code; | |
74 | ||
252b5132 RH |
75 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
76 | for the linker to do relaxing. | |
77 | We do simple forms of relaxing internally, but they are always done. | |
78 | This flag does not apply to them. */ | |
79 | static int m32r_relax; | |
80 | ||
252b5132 RH |
81 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. |
82 | Each high/shigh reloc must be paired with it's low cousin in order to | |
83 | properly calculate the addend in a relocatable link (since there is a | |
84 | potential carry from the low to the high/shigh). | |
85 | This option is off by default though for user-written assembler code it | |
86 | might make sense to make the default be on (i.e. have gcc pass a flag | |
87 | to turn it off). This warning must not be on for GCC created code as | |
88 | optimization may delete the low but not the high/shigh (at least we | |
89 | shouldn't assume or require it to). */ | |
90 | static int warn_unmatched_high = 0; | |
91 | ||
88845958 NC |
92 | /* 1 if -m32rx has been specified, in which case support for |
93 | the extended M32RX instruction set should be enabled. | |
94 | 2 if -m32r2 has been specified, in which case support for | |
95 | the extended M32R2 instruction set should be enabled. */ | |
96 | static int enable_m32rx = 0; /* Default to M32R. */ | |
925c058e DE |
97 | |
98 | /* Non-zero if -m32rx -hidden has been specified, in which case support for | |
99 | the special M32RX instruction set should be enabled. */ | |
100 | static int enable_special = 0; | |
101 | ||
88845958 NC |
102 | /* Non-zero if -bitinst has been specified, in which case support |
103 | for extended M32R bit-field instruction set should be enabled. */ | |
bd337dde | 104 | static int enable_special_m32r = 1; |
88845958 NC |
105 | |
106 | /* Non-zero if -float has been specified, in which case support for | |
107 | extended M32R floating point instruction set should be enabled. */ | |
108 | static int enable_special_float = 0; | |
109 | ||
925c058e DE |
110 | /* Non-zero if the programmer should be warned when an explicit parallel |
111 | instruction might have constraint violations. */ | |
112 | static int warn_explicit_parallel_conflicts = 1; | |
113 | ||
b145f546 NC |
114 | /* Non-zero if the programmer should not receive any messages about |
115 | parallel instruction with potential or real constraint violations. | |
116 | The ability to suppress these messages is intended only for hardware | |
117 | vendors testing the chip. It superceedes | |
118 | warn_explicit_parallel_conflicts. */ | |
119 | static int ignore_parallel_conflicts = 0; | |
88845958 | 120 | |
925c058e | 121 | /* Non-zero if insns can be made parallel. */ |
6858915a | 122 | static int use_parallel = 0; |
88845958 NC |
123 | |
124 | /* Non-zero if optimizations should be performed. */ | |
925c058e | 125 | static int optimize; |
252b5132 | 126 | |
88845958 NC |
127 | /* m32r er_flags. */ |
128 | static int m32r_flags = 0; | |
129 | ||
ab3e48dc | 130 | /* Stuff for .scomm symbols. */ |
252b5132 RH |
131 | static segT sbss_section; |
132 | static asection scom_section; | |
133 | static asymbol scom_symbol; | |
134 | ||
135 | const char comment_chars[] = ";"; | |
136 | const char line_comment_chars[] = "#"; | |
88845958 | 137 | const char line_separator_chars[] = "!"; |
252b5132 RH |
138 | const char EXP_CHARS[] = "eE"; |
139 | const char FLT_CHARS[] = "dD"; | |
140 | ||
141 | /* Relocations against symbols are done in two | |
142 | parts, with a HI relocation and a LO relocation. Each relocation | |
143 | has only 16 bits of space to store an addend. This means that in | |
144 | order for the linker to handle carries correctly, it must be able | |
145 | to locate both the HI and the LO relocation. This means that the | |
146 | relocations must appear in order in the relocation table. | |
147 | ||
148 | In order to implement this, we keep track of each unmatched HI | |
149 | relocation. We then sort them so that they immediately precede the | |
82efde3a | 150 | corresponding LO relocation. */ |
252b5132 RH |
151 | |
152 | struct m32r_hi_fixup | |
153 | { | |
ab3e48dc KH |
154 | /* Next HI fixup. */ |
155 | struct m32r_hi_fixup *next; | |
156 | ||
157 | /* This fixup. */ | |
158 | fixS *fixp; | |
252b5132 | 159 | |
ab3e48dc KH |
160 | /* The section this fixup is in. */ |
161 | segT seg; | |
252b5132 RH |
162 | }; |
163 | ||
164 | /* The list of unmatched HI relocs. */ | |
165 | ||
ab3e48dc | 166 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
252b5132 | 167 | \f |
ea1562b3 NC |
168 | struct |
169 | { | |
88845958 NC |
170 | enum bfd_architecture bfd_mach; |
171 | int mach_flags; | |
172 | } mach_table[] = | |
173 | { | |
174 | { bfd_mach_m32r, (1<<MACH_M32R) }, | |
175 | { bfd_mach_m32rx, (1<<MACH_M32RX) }, | |
176 | { bfd_mach_m32r2, (1<<MACH_M32R2) } | |
177 | }; | |
178 | ||
925c058e | 179 | static void |
88845958 | 180 | allow_m32rx (int on) |
925c058e DE |
181 | { |
182 | enable_m32rx = on; | |
183 | ||
184 | if (stdoutput != NULL) | |
88845958 NC |
185 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); |
186 | ||
187 | if (gas_cgen_cpu_desc != NULL) | |
188 | gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; | |
925c058e | 189 | } |
252b5132 | 190 | \f |
6edf0760 | 191 | #define M32R_SHORTOPTS "O::K:" |
ab3e48dc KH |
192 | |
193 | const char *md_shortopts = M32R_SHORTOPTS; | |
252b5132 | 194 | |
ea1562b3 NC |
195 | enum md_option_enums |
196 | { | |
197 | OPTION_M32R = OPTION_MD_BASE, | |
198 | OPTION_M32RX, | |
199 | OPTION_M32R2, | |
200 | OPTION_BIG, | |
201 | OPTION_LITTLE, | |
202 | OPTION_PARALLEL, | |
203 | OPTION_NO_PARALLEL, | |
204 | OPTION_WARN_PARALLEL, | |
205 | OPTION_NO_WARN_PARALLEL, | |
206 | OPTION_IGNORE_PARALLEL, | |
207 | OPTION_NO_IGNORE_PARALLEL, | |
208 | OPTION_SPECIAL, | |
209 | OPTION_SPECIAL_M32R, | |
210 | OPTION_NO_SPECIAL_M32R, | |
211 | OPTION_SPECIAL_FLOAT, | |
212 | OPTION_WARN_UNMATCHED, | |
213 | OPTION_NO_WARN_UNMATCHED | |
214 | }; | |
215 | ||
252b5132 RH |
216 | struct option md_longopts[] = |
217 | { | |
8ad9e709 | 218 | {"m32r", no_argument, NULL, OPTION_M32R}, |
925c058e | 219 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
88845958 NC |
220 | {"m32r2", no_argument, NULL, OPTION_M32R2}, |
221 | {"big", no_argument, NULL, OPTION_BIG}, | |
222 | {"little", no_argument, NULL, OPTION_LITTLE}, | |
223 | {"EB", no_argument, NULL, OPTION_BIG}, | |
224 | {"EL", no_argument, NULL, OPTION_LITTLE}, | |
225 | {"parallel", no_argument, NULL, OPTION_PARALLEL}, | |
226 | {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, | |
925c058e DE |
227 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
228 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
925c058e DE |
229 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
230 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
b145f546 NC |
231 | {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, |
232 | {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, | |
233 | {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
234 | {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
925c058e | 235 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
88845958 | 236 | {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, |
bd337dde | 237 | {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R}, |
88845958 | 238 | {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, |
252b5132 | 239 | /* Sigh. I guess all warnings must now have both variants. */ |
2f3519a2 NC |
240 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
241 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
d3388653 NC |
242 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
243 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, | |
252b5132 RH |
244 | {NULL, no_argument, NULL, 0} |
245 | }; | |
ab3e48dc | 246 | |
252b5132 RH |
247 | size_t md_longopts_size = sizeof (md_longopts); |
248 | ||
88845958 NC |
249 | static void |
250 | little (int on) | |
251 | { | |
252 | target_big_endian = ! on; | |
253 | } | |
254 | ||
255 | /* Use parallel execution. */ | |
256 | ||
257 | static int | |
258 | parallel (void) | |
259 | { | |
260 | if (! enable_m32rx) | |
261 | return 0; | |
262 | ||
263 | if (use_parallel == 1) | |
264 | return 1; | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
252b5132 | 269 | int |
ea1562b3 | 270 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
271 | { |
272 | switch (c) | |
273 | { | |
925c058e DE |
274 | case 'O': |
275 | optimize = 1; | |
88845958 | 276 | use_parallel = 1; |
925c058e DE |
277 | break; |
278 | ||
8ad9e709 NC |
279 | case OPTION_M32R: |
280 | allow_m32rx (0); | |
281 | break; | |
ab3e48dc | 282 | |
925c058e DE |
283 | case OPTION_M32RX: |
284 | allow_m32rx (1); | |
285 | break; | |
ab3e48dc | 286 | |
88845958 NC |
287 | case OPTION_M32R2: |
288 | allow_m32rx (2); | |
289 | enable_special = 1; | |
290 | enable_special_m32r = 1; | |
291 | break; | |
292 | ||
293 | case OPTION_BIG: | |
294 | target_big_endian = 1; | |
295 | break; | |
296 | ||
297 | case OPTION_LITTLE: | |
298 | target_big_endian = 0; | |
299 | break; | |
300 | ||
301 | case OPTION_PARALLEL: | |
302 | use_parallel = 1; | |
303 | break; | |
304 | ||
305 | case OPTION_NO_PARALLEL: | |
306 | use_parallel = 0; | |
307 | break; | |
308 | ||
925c058e DE |
309 | case OPTION_WARN_PARALLEL: |
310 | warn_explicit_parallel_conflicts = 1; | |
311 | break; | |
ab3e48dc | 312 | |
925c058e | 313 | case OPTION_NO_WARN_PARALLEL: |
88845958 | 314 | warn_explicit_parallel_conflicts = 0; |
88845958 NC |
315 | break; |
316 | ||
b145f546 NC |
317 | case OPTION_IGNORE_PARALLEL: |
318 | ignore_parallel_conflicts = 1; | |
88845958 NC |
319 | break; |
320 | ||
b145f546 NC |
321 | case OPTION_NO_IGNORE_PARALLEL: |
322 | ignore_parallel_conflicts = 0; | |
925c058e DE |
323 | break; |
324 | ||
325 | case OPTION_SPECIAL: | |
326 | if (enable_m32rx) | |
327 | enable_special = 1; | |
328 | else | |
329 | { | |
330 | /* Pretend that we do not recognise this option. */ | |
331 | as_bad (_("Unrecognised option: -hidden")); | |
332 | return 0; | |
333 | } | |
334 | break; | |
252b5132 | 335 | |
88845958 NC |
336 | case OPTION_SPECIAL_M32R: |
337 | enable_special_m32r = 1; | |
338 | break; | |
339 | ||
bd337dde NC |
340 | case OPTION_NO_SPECIAL_M32R: |
341 | enable_special_m32r = 0; | |
342 | break; | |
343 | ||
88845958 NC |
344 | case OPTION_SPECIAL_FLOAT: |
345 | enable_special_float = 1; | |
346 | break; | |
347 | ||
252b5132 RH |
348 | case OPTION_WARN_UNMATCHED: |
349 | warn_unmatched_high = 1; | |
350 | break; | |
351 | ||
352 | case OPTION_NO_WARN_UNMATCHED: | |
353 | warn_unmatched_high = 0; | |
354 | break; | |
ab3e48dc | 355 | |
6edf0760 NC |
356 | case 'K': |
357 | if (strcmp (arg, "PIC") != 0) | |
358 | as_warn (_("Unrecognized option following -K")); | |
359 | else | |
360 | pic_code = 1; | |
361 | break; | |
362 | ||
252b5132 RH |
363 | default: |
364 | return 0; | |
365 | } | |
ab3e48dc | 366 | |
252b5132 RH |
367 | return 1; |
368 | } | |
369 | ||
370 | void | |
ea1562b3 | 371 | md_show_usage (FILE *stream) |
252b5132 RH |
372 | { |
373 | fprintf (stream, _(" M32R specific command line options:\n")); | |
374 | ||
ded0aeb7 NC |
375 | fprintf (stream, _("\ |
376 | -m32r disable support for the m32rx instruction set\n")); | |
925c058e DE |
377 | fprintf (stream, _("\ |
378 | -m32rx support the extended m32rx instruction set\n")); | |
379 | fprintf (stream, _("\ | |
88845958 NC |
380 | -m32r2 support the extended m32r2 instruction set\n")); |
381 | fprintf (stream, _("\ | |
382 | -EL,-little produce little endian code and data\n")); | |
383 | fprintf (stream, _("\ | |
384 | -EB,-big produce big endian code and data\n")); | |
385 | fprintf (stream, _("\ | |
386 | -parallel try to combine instructions in parallel\n")); | |
387 | fprintf (stream, _("\ | |
388 | -no-parallel disable -parallel\n")); | |
389 | fprintf (stream, _("\ | |
bd337dde NC |
390 | -no-bitinst disallow the M32R2's extended bit-field instructions\n")); |
391 | fprintf (stream, _("\ | |
88845958 | 392 | -O try to optimize code. Implies -parallel\n")); |
925c058e DE |
393 | |
394 | fprintf (stream, _("\ | |
395 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); | |
396 | fprintf (stream, _("\ | |
b145f546 | 397 | might violate contraints\n")); |
925c058e DE |
398 | fprintf (stream, _("\ |
399 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); | |
400 | fprintf (stream, _("\ | |
b145f546 | 401 | instructions might violate contraints\n")); |
925c058e DE |
402 | fprintf (stream, _("\ |
403 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); | |
404 | fprintf (stream, _("\ | |
405 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); | |
88845958 | 406 | fprintf (stream, _("\ |
b145f546 | 407 | -ignore-parallel-conflicts do not check parallel instructions\n")); |
88845958 | 408 | fprintf (stream, _("\ |
9fd07943 | 409 | for constraint violations\n")); |
88845958 | 410 | fprintf (stream, _("\ |
b145f546 | 411 | -no-ignore-parallel-conflicts check parallel instructions for\n")); |
88845958 | 412 | fprintf (stream, _("\ |
9fd07943 | 413 | constraint violations\n")); |
88845958 | 414 | fprintf (stream, _("\ |
b145f546 | 415 | -Ip synonym for -ignore-parallel-conflicts\n")); |
88845958 | 416 | fprintf (stream, _("\ |
b145f546 | 417 | -nIp synonym for -no-ignore-parallel-conflicts\n")); |
252b5132 RH |
418 | |
419 | fprintf (stream, _("\ | |
420 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
421 | fprintf (stream, _("\ | |
422 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
423 | fprintf (stream, _("\ | |
424 | -Wuh synonym for -warn-unmatched-high\n")); | |
425 | fprintf (stream, _("\ | |
426 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
427 | ||
6edf0760 NC |
428 | fprintf (stream, _("\ |
429 | -KPIC generate PIC\n")); | |
ab3e48dc | 430 | } |
252b5132 | 431 | |
252b5132 RH |
432 | /* Set by md_assemble for use by m32r_fill_insn. */ |
433 | static subsegT prev_subseg; | |
434 | static segT prev_seg; | |
435 | ||
097f809a NC |
436 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" |
437 | symbolS * GOT_symbol; | |
438 | ||
439 | static inline int | |
440 | m32r_PIC_related_p (symbolS *sym) | |
441 | { | |
442 | expressionS *exp; | |
443 | ||
444 | if (! sym) | |
445 | return 0; | |
446 | ||
447 | if (sym == GOT_symbol) | |
448 | return 1; | |
449 | ||
450 | exp = symbol_get_value_expression (sym); | |
451 | ||
452 | return (exp->X_op == O_PIC_reloc | |
453 | || exp->X_md == BFD_RELOC_M32R_26_PLTREL | |
454 | || m32r_PIC_related_p (exp->X_add_symbol) | |
455 | || m32r_PIC_related_p (exp->X_op_symbol)); | |
456 | } | |
457 | ||
458 | static inline int | |
459 | m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p) | |
460 | { | |
461 | expressionS *exp = main_exp; | |
462 | ||
463 | if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol)) | |
464 | return 1; | |
465 | ||
466 | if (exp->X_op == O_symbol && exp->X_add_symbol) | |
467 | { | |
468 | if (exp->X_add_symbol == GOT_symbol) | |
469 | { | |
470 | *r_type_p = BFD_RELOC_M32R_GOTPC24; | |
471 | return 0; | |
472 | } | |
473 | } | |
474 | else if (exp->X_op == O_add) | |
475 | { | |
476 | exp = symbol_get_value_expression (exp->X_add_symbol); | |
477 | if (! exp) | |
478 | return 0; | |
479 | } | |
480 | ||
0a7b9ba6 | 481 | if (exp->X_op == O_PIC_reloc) |
097f809a NC |
482 | { |
483 | *r_type_p = exp->X_md; | |
484 | if (exp == main_exp) | |
485 | exp->X_op = O_symbol; | |
486 | else | |
487 | { | |
488 | main_exp->X_add_symbol = exp->X_add_symbol; | |
489 | main_exp->X_add_number += exp->X_add_number; | |
490 | } | |
491 | } | |
492 | else | |
493 | return (m32r_PIC_related_p (exp->X_add_symbol) | |
494 | || m32r_PIC_related_p (exp->X_op_symbol)); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
252b5132 | 499 | /* FIXME: Should be machine generated. */ |
88845958 | 500 | #define NOP_INSN 0x7000 |
ab3e48dc | 501 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
252b5132 | 502 | |
0a9ef439 RH |
503 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
504 | of an rs_align_code fragment. */ | |
252b5132 | 505 | |
0a9ef439 | 506 | void |
ea1562b3 | 507 | m32r_handle_align (fragS *fragp) |
252b5132 | 508 | { |
0a9ef439 RH |
509 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
510 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; | |
252b5132 | 511 | |
0a9ef439 RH |
512 | int bytes, fix; |
513 | char *p; | |
ab3e48dc | 514 | |
0a9ef439 RH |
515 | if (fragp->fr_type != rs_align_code) |
516 | return; | |
517 | ||
518 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
519 | p = fragp->fr_literal + fragp->fr_fix; | |
520 | fix = 0; | |
521 | ||
522 | if (bytes & 1) | |
523 | { | |
524 | fix = 1; | |
525 | *p++ = 0; | |
526 | bytes--; | |
252b5132 RH |
527 | } |
528 | ||
0a9ef439 RH |
529 | if (bytes & 2) |
530 | { | |
531 | memcpy (p, nop_pattern, 2); | |
532 | p += 2; | |
533 | bytes -= 2; | |
534 | fix += 2; | |
535 | } | |
536 | ||
537 | memcpy (p, multi_nop_pattern, 4); | |
538 | ||
539 | fragp->fr_fix += fix; | |
540 | fragp->fr_var = 4; | |
252b5132 RH |
541 | } |
542 | ||
543 | /* If the last instruction was the first of 2 16 bit insns, | |
544 | output a nop to move the PC to a 32 bit boundary. | |
545 | ||
546 | This is done via an alignment specification since branch relaxing | |
547 | may make it unnecessary. | |
548 | ||
549 | Internally, we need to output one of these each time a 32 bit insn is | |
550 | seen after an insn that is relaxable. */ | |
551 | ||
552 | static void | |
ea1562b3 | 553 | fill_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 554 | { |
0a9ef439 | 555 | frag_align_code (2, 0); |
252b5132 RH |
556 | prev_insn.insn = NULL; |
557 | seen_relaxable_p = 0; | |
558 | } | |
559 | ||
560 | /* Record the symbol so that when we output the insn, we can create | |
561 | a symbol that is at the start of the instruction. This is used | |
562 | to emit the label for the start of a breakpoint without causing | |
563 | the assembler to emit a NOP if the previous instruction was a | |
564 | 16 bit instruction. */ | |
565 | ||
566 | static void | |
ea1562b3 | 567 | debug_sym (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 568 | { |
ea1562b3 NC |
569 | char *name; |
570 | char delim; | |
571 | char *end_name; | |
572 | symbolS *symbolP; | |
91d6fa6a | 573 | sym_linkS *lnk; |
252b5132 RH |
574 | |
575 | name = input_line_pointer; | |
576 | delim = get_symbol_end (); | |
577 | end_name = input_line_pointer; | |
ab3e48dc | 578 | |
252b5132 RH |
579 | if ((symbolP = symbol_find (name)) == NULL |
580 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
ea1562b3 | 581 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); |
252b5132 RH |
582 | |
583 | symbol_table_insert (symbolP); | |
6edf0760 NC |
584 | if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section |
585 | || S_IS_EXTERNAL (symbolP) | |
586 | || S_IS_WEAK (symbolP))) | |
252b5132 RH |
587 | /* xgettext:c-format */ |
588 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
589 | ||
590 | else | |
591 | { | |
91d6fa6a NC |
592 | lnk = (sym_linkS *) xmalloc (sizeof (sym_linkS)); |
593 | lnk->symbol = symbolP; | |
594 | lnk->next = debug_sym_link; | |
595 | debug_sym_link = lnk; | |
f412ead8 | 596 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
597 | } |
598 | ||
599 | *end_name = delim; | |
600 | demand_empty_rest_of_line (); | |
601 | } | |
602 | ||
603 | /* Second pass to expanding the debug symbols, go through linked | |
604 | list of symbols and reassign the address. */ | |
605 | ||
606 | static void | |
ea1562b3 | 607 | expand_debug_syms (sym_linkS *syms, int align) |
252b5132 RH |
608 | { |
609 | char *save_input_line = input_line_pointer; | |
610 | sym_linkS *next_syms; | |
611 | ||
612 | if (!syms) | |
613 | return; | |
614 | ||
a8150a88 | 615 | (void) frag_align_code (align, 0); |
ab3e48dc | 616 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
252b5132 RH |
617 | { |
618 | symbolS *symbolP = syms->symbol; | |
619 | next_syms = syms->next; | |
620 | input_line_pointer = ".\n"; | |
621 | pseudo_set (symbolP); | |
ab3e48dc | 622 | free ((char *) syms); |
252b5132 RH |
623 | } |
624 | ||
625 | input_line_pointer = save_input_line; | |
626 | } | |
627 | ||
88845958 | 628 | void |
ea1562b3 | 629 | m32r_flush_pending_output (void) |
88845958 NC |
630 | { |
631 | if (debug_sym_link) | |
632 | { | |
633 | expand_debug_syms (debug_sym_link, 1); | |
634 | debug_sym_link = (sym_linkS *) 0; | |
635 | } | |
636 | } | |
637 | ||
252b5132 RH |
638 | /* Cover function to fill_insn called after a label and at end of assembly. |
639 | The result is always 1: we're called in a conditional to see if the | |
640 | current line is a label. */ | |
641 | ||
642 | int | |
ea1562b3 | 643 | m32r_fill_insn (int done) |
252b5132 RH |
644 | { |
645 | if (prev_seg != NULL) | |
646 | { | |
ab3e48dc | 647 | segT seg = now_seg; |
252b5132 RH |
648 | subsegT subseg = now_subseg; |
649 | ||
650 | subseg_set (prev_seg, prev_subseg); | |
ab3e48dc | 651 | |
252b5132 RH |
652 | fill_insn (0); |
653 | ||
654 | subseg_set (seg, subseg); | |
655 | } | |
656 | ||
657 | if (done && debug_sym_link) | |
658 | { | |
659 | expand_debug_syms (debug_sym_link, 1); | |
ab3e48dc | 660 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
661 | } |
662 | ||
663 | return 1; | |
664 | } | |
665 | \f | |
88845958 NC |
666 | /* The default target format to use. */ |
667 | ||
668 | const char * | |
ea1562b3 | 669 | m32r_target_format (void) |
88845958 NC |
670 | { |
671 | #ifdef TE_LINUX | |
672 | if (target_big_endian) | |
673 | return "elf32-m32r-linux"; | |
674 | else | |
675 | return "elf32-m32rle-linux"; | |
676 | #else | |
677 | if (target_big_endian) | |
678 | return "elf32-m32r"; | |
679 | else | |
680 | return "elf32-m32rle"; | |
681 | #endif | |
682 | } | |
683 | ||
252b5132 | 684 | void |
ea1562b3 | 685 | md_begin (void) |
252b5132 RH |
686 | { |
687 | flagword applicable; | |
ab3e48dc KH |
688 | segT seg; |
689 | subsegT subseg; | |
252b5132 RH |
690 | |
691 | /* Initialize the `cgen' interface. */ | |
ab3e48dc | 692 | |
252b5132 RH |
693 | /* Set the machine number and endian. */ |
694 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
695 | CGEN_CPU_OPEN_ENDIAN, | |
88845958 NC |
696 | (target_big_endian ? |
697 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), | |
252b5132 RH |
698 | CGEN_CPU_OPEN_END); |
699 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
700 | ||
701 | /* The operand instance table is used during optimization to determine | |
702 | which insns can be executed in parallel. It is also used to give | |
703 | warnings regarding operand interference in parallel insns. */ | |
704 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
705 | ||
706 | /* This is a callback from cgen to gas to parse operands. */ | |
707 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
708 | ||
252b5132 RH |
709 | /* Save the current subseg so we can restore it [it's the default one and |
710 | we don't want the initial section to be .sbss]. */ | |
711 | seg = now_seg; | |
712 | subseg = now_subseg; | |
713 | ||
714 | /* The sbss section is for local .scomm symbols. */ | |
715 | sbss_section = subseg_new (".sbss", 0); | |
71ac351c | 716 | seg_info (sbss_section)->bss = 1; |
ab3e48dc | 717 | |
252b5132 RH |
718 | /* This is copied from perform_an_assembly_pass. */ |
719 | applicable = bfd_applicable_section_flags (stdoutput); | |
720 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ab3e48dc | 721 | |
252b5132 RH |
722 | subseg_set (seg, subseg); |
723 | ||
724 | /* We must construct a fake section similar to bfd_com_section | |
725 | but with the name .scommon. */ | |
726 | scom_section = bfd_com_section; | |
727 | scom_section.name = ".scommon"; | |
ea1562b3 NC |
728 | scom_section.output_section = & scom_section; |
729 | scom_section.symbol = & scom_symbol; | |
730 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
731 | scom_symbol = * bfd_com_section.symbol; | |
252b5132 | 732 | scom_symbol.name = ".scommon"; |
ea1562b3 | 733 | scom_symbol.section = & scom_section; |
252b5132 | 734 | |
925c058e | 735 | allow_m32rx (enable_m32rx); |
002de68b | 736 | |
07726851 | 737 | gas_cgen_initialize_saved_fixups_array (); |
925c058e DE |
738 | } |
739 | ||
740 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ | |
741 | ((operand)->hw_type == HW_H_COND \ | |
742 | || ((operand)->hw_type == HW_H_PSW) \ | |
743 | || ((operand)->hw_type == HW_H_CR \ | |
744 | && (indices [index] == 0 || indices [index] == 1))) | |
745 | ||
746 | /* Returns true if an output of instruction 'a' is referenced by an operand | |
747 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
748 | checked, otherwise its inputs are examined. */ | |
749 | ||
750 | static int | |
ea1562b3 NC |
751 | first_writes_to_seconds_operands (m32r_insn *a, |
752 | m32r_insn *b, | |
753 | const int check_outputs) | |
925c058e | 754 | { |
ab3e48dc KH |
755 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
756 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); | |
925c058e DE |
757 | int a_index; |
758 | ||
b145f546 NC |
759 | if (ignore_parallel_conflicts) |
760 | return 0; | |
761 | ||
925c058e DE |
762 | /* If at least one of the instructions takes no operands, then there is |
763 | nothing to check. There really are instructions without operands, | |
764 | eg 'nop'. */ | |
765 | if (a_operands == NULL || b_ops == NULL) | |
766 | return 0; | |
ab3e48dc | 767 | |
925c058e DE |
768 | /* Scan the operand list of 'a' looking for an output operand. */ |
769 | for (a_index = 0; | |
770 | a_operands->type != CGEN_OPINST_END; | |
771 | a_index ++, a_operands ++) | |
772 | { | |
773 | if (a_operands->type == CGEN_OPINST_OUTPUT) | |
774 | { | |
775 | int b_index; | |
ab3e48dc | 776 | const CGEN_OPINST *b_operands = b_ops; |
925c058e DE |
777 | |
778 | /* Special Case: | |
779 | The Condition bit 'C' is a shadow of the CBR register (control | |
780 | register 1) and also a shadow of bit 31 of the program status | |
781 | word (control register 0). For now this is handled here, rather | |
ab3e48dc KH |
782 | than by cgen.... */ |
783 | ||
925c058e DE |
784 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
785 | { | |
786 | /* Scan operand list of 'b' looking for another reference to the | |
787 | condition bit, which goes in the right direction. */ | |
788 | for (b_index = 0; | |
789 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 790 | b_index++, b_operands++) |
925c058e DE |
791 | { |
792 | if ((b_operands->type | |
793 | == (check_outputs | |
794 | ? CGEN_OPINST_OUTPUT | |
795 | : CGEN_OPINST_INPUT)) | |
796 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
797 | return 1; | |
798 | } | |
799 | } | |
800 | else | |
801 | { | |
802 | /* Scan operand list of 'b' looking for an operand that | |
803 | references the same hardware element, and which goes in the | |
804 | right direction. */ | |
805 | for (b_index = 0; | |
806 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 807 | b_index++, b_operands++) |
925c058e DE |
808 | { |
809 | if ((b_operands->type | |
810 | == (check_outputs | |
811 | ? CGEN_OPINST_OUTPUT | |
812 | : CGEN_OPINST_INPUT)) | |
813 | && (b_operands->hw_type == a_operands->hw_type) | |
ab3e48dc | 814 | && (a->indices[a_index] == b->indices[b_index])) |
925c058e DE |
815 | return 1; |
816 | } | |
817 | } | |
818 | } | |
819 | } | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | /* Returns true if the insn can (potentially) alter the program counter. */ | |
825 | ||
826 | static int | |
ea1562b3 | 827 | writes_to_pc (m32r_insn *a) |
925c058e | 828 | { |
925c058e DE |
829 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) |
830 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) | |
831 | return 1; | |
925c058e DE |
832 | return 0; |
833 | } | |
834 | ||
ab3e48dc KH |
835 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
836 | Otherwise return a pointer to an error message explaining why not. */ | |
925c058e DE |
837 | |
838 | static const char * | |
ea1562b3 | 839 | can_make_parallel (m32r_insn *a, m32r_insn *b) |
925c058e DE |
840 | { |
841 | PIPE_ATTR a_pipe; | |
842 | PIPE_ATTR b_pipe; | |
ab3e48dc | 843 | |
925c058e | 844 | /* Make sure the instructions are the right length. */ |
ab3e48dc KH |
845 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
846 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) | |
847 | abort (); | |
925c058e | 848 | |
b34976b6 | 849 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
b145f546 | 850 | return _("instructions write to the same destination register."); |
ab3e48dc | 851 | |
925c058e DE |
852 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
853 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); | |
854 | ||
855 | /* Make sure that the instructions use the correct execution pipelines. */ | |
ab3e48dc | 856 | if (a_pipe == PIPE_NONE |
925c058e DE |
857 | || b_pipe == PIPE_NONE) |
858 | return _("Instructions do not use parallel execution pipelines."); | |
859 | ||
860 | /* Leave this test for last, since it is the only test that can | |
861 | go away if the instructions are swapped, and we want to make | |
862 | sure that any other errors are detected before this happens. */ | |
ab3e48dc | 863 | if (a_pipe == PIPE_S |
88845958 NC |
864 | || b_pipe == PIPE_O |
865 | || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) | |
925c058e | 866 | return _("Instructions share the same execution pipeline"); |
ab3e48dc | 867 | |
925c058e DE |
868 | return NULL; |
869 | } | |
870 | ||
871 | /* Force the top bit of the second 16-bit insn to be set. */ | |
872 | ||
873 | static void | |
ea1562b3 | 874 | make_parallel (CGEN_INSN_BYTES_PTR buffer) |
925c058e DE |
875 | { |
876 | #if CGEN_INT_INSN_P | |
877 | *buffer |= 0x8000; | |
878 | #else | |
ab3e48dc | 879 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
880 | |= 0x80; |
881 | #endif | |
252b5132 RH |
882 | } |
883 | ||
925c058e | 884 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
252b5132 | 885 | |
925c058e | 886 | static void |
ea1562b3 | 887 | target_make_parallel (char *buffer) |
925c058e | 888 | { |
ab3e48dc | 889 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
890 | |= 0x80; |
891 | } | |
892 | ||
893 | /* Assemble two instructions with an explicit parallel operation (||) or | |
894 | sequential operation (->). */ | |
895 | ||
896 | static void | |
ea1562b3 | 897 | assemble_two_insns (char *str1, char *str2, int parallel_p) |
925c058e | 898 | { |
ab3e48dc | 899 | char *str3; |
925c058e DE |
900 | m32r_insn first; |
901 | m32r_insn second; | |
ab3e48dc KH |
902 | char *errmsg; |
903 | char save_str2 = *str2; | |
925c058e | 904 | |
67c1ffbe | 905 | /* Separate the two instructions. */ |
ab3e48dc | 906 | *str2 = 0; |
925c058e DE |
907 | |
908 | /* Make sure the two insns begin on a 32 bit boundary. | |
909 | This is also done for the serial case (foo -> bar), relaxing doesn't | |
910 | affect insns written like this. | |
911 | Note that we must always do this as we can't assume anything about | |
912 | whether we're currently on a 32 bit boundary or not. Relaxing may | |
913 | change this. */ | |
914 | fill_insn (0); | |
915 | ||
916 | first.debug_sym_link = debug_sym_link; | |
ab3e48dc | 917 | debug_sym_link = (sym_linkS *) 0; |
925c058e DE |
918 | |
919 | /* Parse the first instruction. */ | |
920 | if (! (first.insn = m32r_cgen_assemble_insn | |
ea1562b3 | 921 | (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg))) |
925c058e | 922 | { |
20203fb9 | 923 | as_bad ("%s", errmsg); |
925c058e DE |
924 | return; |
925 | } | |
926 | ||
927 | /* Check it. */ | |
928 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) | |
929 | { | |
ab3e48dc | 930 | /* xgettext:c-format */ |
ea1562b3 | 931 | as_bad (_("not a 16 bit instruction '%s'"), str1); |
925c058e DE |
932 | return; |
933 | } | |
88845958 NC |
934 | #ifdef E_M32R2_ARCH |
935 | else if ((enable_m32rx == 1) | |
936 | /* FIXME: Need standard macro to perform this test. */ | |
937 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
938 | & (1 << MACH_M32R2)) | |
939 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
940 | & (1 << MACH_M32RX))))) | |
941 | { | |
942 | /* xgettext:c-format */ | |
ea1562b3 | 943 | as_bad (_("instruction '%s' is for the M32R2 only"), str1); |
88845958 NC |
944 | return; |
945 | } | |
946 | else if ((! enable_special | |
947 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
948 | || (! enable_special_m32r | |
949 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) | |
950 | #else | |
925c058e DE |
951 | else if (! enable_special |
952 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 953 | #endif |
925c058e | 954 | { |
ab3e48dc | 955 | /* xgettext:c-format */ |
ea1562b3 | 956 | as_bad (_("unknown instruction '%s'"), str1); |
925c058e DE |
957 | return; |
958 | } | |
959 | else if (! enable_m32rx | |
ab3e48dc KH |
960 | /* FIXME: Need standard macro to perform this test. */ |
961 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
962 | == (1 << MACH_M32RX))) | |
925c058e | 963 | { |
ab3e48dc | 964 | /* xgettext:c-format */ |
ea1562b3 | 965 | as_bad (_("instruction '%s' is for the M32RX only"), str1); |
925c058e DE |
966 | return; |
967 | } | |
ab3e48dc | 968 | |
925c058e | 969 | /* Check to see if this is an allowable parallel insn. */ |
ab3e48dc KH |
970 | if (parallel_p |
971 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 972 | { |
ab3e48dc | 973 | /* xgettext:c-format */ |
ea1562b3 | 974 | as_bad (_("instruction '%s' cannot be executed in parallel."), str1); |
925c058e DE |
975 | return; |
976 | } | |
ab3e48dc KH |
977 | |
978 | /* Restore the original assembly text, just in case it is needed. */ | |
979 | *str2 = save_str2; | |
980 | ||
981 | /* Save the original string pointer. */ | |
ea1562b3 | 982 | str3 = str1; |
ab3e48dc KH |
983 | |
984 | /* Advanced past the parsed string. */ | |
ea1562b3 | 985 | str1 = str2 + 2; |
ab3e48dc KH |
986 | |
987 | /* Remember the entire string in case it is needed for error | |
988 | messages. */ | |
989 | str2 = str3; | |
925c058e DE |
990 | |
991 | /* Convert the opcode to lower case. */ | |
992 | { | |
ea1562b3 | 993 | char *s2 = str1; |
ab3e48dc | 994 | |
3882b010 | 995 | while (ISSPACE (*s2++)) |
925c058e DE |
996 | continue; |
997 | ||
998 | --s2; | |
999 | ||
3882b010 | 1000 | while (ISALNUM (*s2)) |
925c058e | 1001 | { |
3882b010 | 1002 | *s2 = TOLOWER (*s2); |
ab3e48dc | 1003 | s2++; |
925c058e DE |
1004 | } |
1005 | } | |
ab3e48dc KH |
1006 | |
1007 | /* Preserve any fixups that have been generated and reset the list | |
1008 | to empty. */ | |
002de68b | 1009 | gas_cgen_save_fixups (0); |
925c058e DE |
1010 | |
1011 | /* Get the indices of the operands of the instruction. */ | |
1012 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
1013 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
1014 | /* FIXME: ALIAS insns do not have operands, so we use this function | |
1015 | to find the equivalent insn and overwrite the value stored in our | |
1016 | structure. We still need the original insn, however, since this | |
1017 | may have certain attributes that are not present in the unaliased | |
1018 | version (eg relaxability). When aliases behave differently this | |
1019 | may have to change. */ | |
1020 | first.orig_insn = first.insn; | |
1021 | { | |
1022 | CGEN_FIELDS tmp_fields; | |
1023 | first.insn = cgen_lookup_get_insn_operands | |
1024 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, | |
1025 | first.indices, &tmp_fields); | |
1026 | } | |
ab3e48dc | 1027 | |
925c058e DE |
1028 | if (first.insn == NULL) |
1029 | as_fatal (_("internal error: lookup/get operands failed")); | |
1030 | ||
1031 | second.debug_sym_link = NULL; | |
1032 | ||
1033 | /* Parse the second instruction. */ | |
1034 | if (! (second.insn = m32r_cgen_assemble_insn | |
ea1562b3 | 1035 | (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg))) |
925c058e | 1036 | { |
20203fb9 | 1037 | as_bad ("%s", errmsg); |
925c058e DE |
1038 | return; |
1039 | } | |
1040 | ||
1041 | /* Check it. */ | |
1042 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) | |
1043 | { | |
ab3e48dc | 1044 | /* xgettext:c-format */ |
ea1562b3 | 1045 | as_bad (_("not a 16 bit instruction '%s'"), str1); |
925c058e DE |
1046 | return; |
1047 | } | |
88845958 NC |
1048 | #ifdef E_M32R2_ARCH |
1049 | else if ((enable_m32rx == 1) | |
1050 | /* FIXME: Need standard macro to perform this test. */ | |
1051 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1052 | & (1 << MACH_M32R2)) | |
1053 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1054 | & (1 << MACH_M32RX))))) | |
1055 | { | |
1056 | /* xgettext:c-format */ | |
ea1562b3 | 1057 | as_bad (_("instruction '%s' is for the M32R2 only"), str1); |
88845958 NC |
1058 | return; |
1059 | } | |
1060 | else if ((! enable_special | |
1061 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1062 | || (! enable_special_m32r | |
1063 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) | |
1064 | #else | |
925c058e DE |
1065 | else if (! enable_special |
1066 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1067 | #endif |
925c058e | 1068 | { |
ab3e48dc | 1069 | /* xgettext:c-format */ |
ea1562b3 | 1070 | as_bad (_("unknown instruction '%s'"), str1); |
925c058e DE |
1071 | return; |
1072 | } | |
1073 | else if (! enable_m32rx | |
1074 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1075 | { | |
ab3e48dc | 1076 | /* xgettext:c-format */ |
ea1562b3 | 1077 | as_bad (_("instruction '%s' is for the M32RX only"), str1); |
925c058e DE |
1078 | return; |
1079 | } | |
1080 | ||
1081 | /* Check to see if this is an allowable parallel insn. */ | |
ab3e48dc KH |
1082 | if (parallel_p |
1083 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1084 | { |
ab3e48dc | 1085 | /* xgettext:c-format */ |
ea1562b3 | 1086 | as_bad (_("instruction '%s' cannot be executed in parallel."), str1); |
925c058e DE |
1087 | return; |
1088 | } | |
ab3e48dc | 1089 | |
925c058e DE |
1090 | if (parallel_p && ! enable_m32rx) |
1091 | { | |
1092 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP | |
1093 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
1094 | { | |
ab3e48dc | 1095 | /* xgettext:c-format */ |
925c058e DE |
1096 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
1097 | return; | |
1098 | } | |
1099 | } | |
1100 | ||
1101 | /* Get the indices of the operands of the instruction. */ | |
1102 | second.orig_insn = second.insn; | |
1103 | { | |
1104 | CGEN_FIELDS tmp_fields; | |
1105 | second.insn = cgen_lookup_get_insn_operands | |
1106 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, | |
1107 | second.indices, &tmp_fields); | |
1108 | } | |
ab3e48dc | 1109 | |
925c058e DE |
1110 | if (second.insn == NULL) |
1111 | as_fatal (_("internal error: lookup/get operands failed")); | |
1112 | ||
1113 | /* We assume that if the first instruction writes to a register that is | |
1114 | read by the second instruction it is because the programmer intended | |
1115 | this to happen, (after all they have explicitly requested that these | |
1116 | two instructions be executed in parallel). Although if the global | |
1117 | variable warn_explicit_parallel_conflicts is true then we do generate | |
1118 | a warning message. Similarly we assume that parallel branch and jump | |
1119 | instructions are deliberate and should not produce errors. */ | |
ab3e48dc | 1120 | |
925c058e DE |
1121 | if (parallel_p && warn_explicit_parallel_conflicts) |
1122 | { | |
b34976b6 | 1123 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
ab3e48dc | 1124 | /* xgettext:c-format */ |
b145f546 | 1125 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
ab3e48dc | 1126 | |
b34976b6 | 1127 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
ab3e48dc | 1128 | /* xgettext:c-format */ |
b145f546 | 1129 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
925c058e | 1130 | } |
ab3e48dc | 1131 | |
925c058e | 1132 | if (!parallel_p |
ab3e48dc | 1133 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
925c058e DE |
1134 | { |
1135 | /* Get the fixups for the first instruction. */ | |
002de68b | 1136 | gas_cgen_swap_fixups (0); |
925c058e DE |
1137 | |
1138 | /* Write it out. */ | |
1139 | expand_debug_syms (first.debug_sym_link, 1); | |
1140 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc KH |
1141 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
1142 | ||
925c058e DE |
1143 | /* Force the top bit of the second insn to be set. */ |
1144 | if (parallel_p) | |
1145 | make_parallel (second.buffer); | |
1146 | ||
1147 | /* Get its fixups. */ | |
002de68b | 1148 | gas_cgen_restore_fixups (0); |
925c058e DE |
1149 | |
1150 | /* Write it out. */ | |
1151 | expand_debug_syms (second.debug_sym_link, 1); | |
1152 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc | 1153 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
925c058e DE |
1154 | } |
1155 | /* Try swapping the instructions to see if they work that way. */ | |
ab3e48dc | 1156 | else if (can_make_parallel (&second, &first) == NULL) |
925c058e DE |
1157 | { |
1158 | /* Write out the second instruction first. */ | |
1159 | expand_debug_syms (second.debug_sym_link, 1); | |
1160 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc KH |
1161 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
1162 | ||
925c058e DE |
1163 | /* Force the top bit of the first instruction to be set. */ |
1164 | make_parallel (first.buffer); | |
1165 | ||
1166 | /* Get the fixups for the first instruction. */ | |
002de68b | 1167 | gas_cgen_restore_fixups (0); |
925c058e DE |
1168 | |
1169 | /* Write out the first instruction. */ | |
1170 | expand_debug_syms (first.debug_sym_link, 1); | |
1171 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc | 1172 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
925c058e DE |
1173 | } |
1174 | else | |
1175 | { | |
1176 | as_bad ("'%s': %s", str2, errmsg); | |
1177 | return; | |
1178 | } | |
ab3e48dc | 1179 | |
88845958 NC |
1180 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) |
1181 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1182 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1183 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) | |
1184 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) | |
1185 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1186 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) | |
1187 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1188 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1189 | ||
925c058e DE |
1190 | /* Set these so m32r_fill_insn can use them. */ |
1191 | prev_seg = now_seg; | |
1192 | prev_subseg = now_subseg; | |
1193 | } | |
252b5132 RH |
1194 | |
1195 | void | |
ea1562b3 | 1196 | md_assemble (char *str) |
252b5132 RH |
1197 | { |
1198 | m32r_insn insn; | |
ab3e48dc KH |
1199 | char *errmsg; |
1200 | char *str2 = NULL; | |
252b5132 RH |
1201 | |
1202 | /* Initialize GAS's cgen interface for a new instruction. */ | |
1203 | gas_cgen_init_parse (); | |
1204 | ||
67c1ffbe | 1205 | /* Look for a parallel instruction separator. */ |
925c058e DE |
1206 | if ((str2 = strstr (str, "||")) != NULL) |
1207 | { | |
1208 | assemble_two_insns (str, str2, 1); | |
88845958 | 1209 | m32r_flags |= E_M32R_HAS_PARALLEL; |
925c058e DE |
1210 | return; |
1211 | } | |
1212 | ||
67c1ffbe | 1213 | /* Also look for a sequential instruction separator. */ |
925c058e DE |
1214 | if ((str2 = strstr (str, "->")) != NULL) |
1215 | { | |
1216 | assemble_two_insns (str, str2, 0); | |
1217 | return; | |
1218 | } | |
ab3e48dc | 1219 | |
252b5132 | 1220 | insn.debug_sym_link = debug_sym_link; |
ab3e48dc | 1221 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
1222 | |
1223 | insn.insn = m32r_cgen_assemble_insn | |
ab3e48dc KH |
1224 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
1225 | ||
252b5132 RH |
1226 | if (!insn.insn) |
1227 | { | |
20203fb9 | 1228 | as_bad ("%s", errmsg); |
252b5132 RH |
1229 | return; |
1230 | } | |
1231 | ||
88845958 NC |
1232 | #ifdef E_M32R2_ARCH |
1233 | if ((enable_m32rx == 1) | |
1234 | /* FIXME: Need standard macro to perform this test. */ | |
1235 | && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1236 | & (1 << MACH_M32R2)) | |
1237 | && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1238 | & (1 << MACH_M32RX))))) | |
1239 | { | |
1240 | /* xgettext:c-format */ | |
1241 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1242 | return; | |
1243 | } | |
1244 | else if ((! enable_special | |
1245 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
1246 | || (! enable_special_m32r | |
1247 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) | |
1248 | #else | |
925c058e DE |
1249 | if (! enable_special |
1250 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1251 | #endif |
925c058e | 1252 | { |
ab3e48dc | 1253 | /* xgettext:c-format */ |
925c058e DE |
1254 | as_bad (_("unknown instruction '%s'"), str); |
1255 | return; | |
1256 | } | |
1257 | else if (! enable_m32rx | |
1258 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1259 | { | |
ab3e48dc | 1260 | /* xgettext:c-format */ |
925c058e DE |
1261 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1262 | return; | |
1263 | } | |
ab3e48dc | 1264 | |
88845958 NC |
1265 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
1266 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1267 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) | |
1268 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1269 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1270 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1271 | ||
252b5132 RH |
1272 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
1273 | { | |
1274 | /* 32 bit insns must live on 32 bit boundaries. */ | |
1275 | if (prev_insn.insn || seen_relaxable_p) | |
1276 | { | |
1277 | /* ??? If calling fill_insn too many times turns us into a memory | |
1278 | pig, can we call a fn to assemble a nop instead of | |
1279 | !seen_relaxable_p? */ | |
1280 | fill_insn (0); | |
1281 | } | |
1282 | ||
1283 | expand_debug_syms (insn.debug_sym_link, 2); | |
1284 | ||
1285 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
1286 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
ab3e48dc | 1287 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
252b5132 RH |
1288 | } |
1289 | else | |
1290 | { | |
1291 | int on_32bit_boundary_p; | |
b34976b6 | 1292 | int swap = FALSE; |
252b5132 RH |
1293 | |
1294 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
ab3e48dc | 1295 | abort (); |
252b5132 RH |
1296 | |
1297 | insn.orig_insn = insn.insn; | |
1298 | ||
925c058e DE |
1299 | /* If the previous insn was relaxable, then it may be expanded |
1300 | to fill the current 16 bit slot. Emit a NOP here to occupy | |
1301 | this slot, so that we can start at optimizing at a 32 bit | |
1302 | boundary. */ | |
1303 | if (prev_insn.insn && seen_relaxable_p && optimize) | |
1304 | fill_insn (0); | |
ab3e48dc | 1305 | |
925c058e DE |
1306 | if (enable_m32rx) |
1307 | { | |
1308 | /* Get the indices of the operands of the instruction. | |
1309 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
1310 | { | |
1311 | CGEN_FIELDS tmp_fields; | |
1312 | insn.insn = cgen_lookup_get_insn_operands | |
1313 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, | |
1314 | 16, insn.indices, &tmp_fields); | |
1315 | } | |
ab3e48dc | 1316 | |
925c058e DE |
1317 | if (insn.insn == NULL) |
1318 | as_fatal (_("internal error: lookup/get operands failed")); | |
1319 | } | |
1320 | ||
252b5132 RH |
1321 | /* Compute whether we're on a 32 bit boundary or not. |
1322 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1323 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
1324 | ||
097dba13 NC |
1325 | /* Change a frag to, if each insn to swap is in a different frag. |
1326 | It must keep only one instruction in a frag. */ | |
1327 | if (parallel() && on_32bit_boundary_p) | |
1328 | { | |
1329 | frag_wane (frag_now); | |
1330 | frag_new (0); | |
1331 | } | |
1332 | ||
925c058e DE |
1333 | /* Look to see if this instruction can be combined with the |
1334 | previous instruction to make one, parallel, 32 bit instruction. | |
1335 | If the previous instruction (potentially) changed the flow of | |
1336 | program control, then it cannot be combined with the current | |
1337 | instruction. If the current instruction is relaxable, then it | |
1338 | might be replaced with a longer version, so we cannot combine it. | |
1339 | Also if the output of the previous instruction is used as an | |
1340 | input to the current instruction then it cannot be combined. | |
1341 | Otherwise call can_make_parallel() with both orderings of the | |
1342 | instructions to see if they can be combined. */ | |
ab3e48dc | 1343 | if (! on_32bit_boundary_p |
88845958 | 1344 | && parallel () |
ab3e48dc KH |
1345 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
1346 | && ! writes_to_pc (&prev_insn) | |
b34976b6 | 1347 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
925c058e | 1348 | { |
ab3e48dc | 1349 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
925c058e | 1350 | make_parallel (insn.buffer); |
ab3e48dc | 1351 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
b34976b6 | 1352 | swap = TRUE; |
925c058e | 1353 | } |
252b5132 RH |
1354 | |
1355 | expand_debug_syms (insn.debug_sym_link, 1); | |
1356 | ||
1357 | { | |
1358 | int i; | |
1359 | finished_insnS fi; | |
1360 | ||
1361 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1362 | frag_grow (4); | |
1363 | ||
1364 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
ab3e48dc KH |
1365 | CGEN_FIELDS_BITSIZE (&insn.fields), |
1366 | 1 /* relax_p */, &fi); | |
252b5132 RH |
1367 | insn.addr = fi.addr; |
1368 | insn.frag = fi.frag; | |
1369 | insn.num_fixups = fi.num_fixups; | |
1370 | for (i = 0; i < fi.num_fixups; ++i) | |
1371 | insn.fixups[i] = fi.fixups[i]; | |
1372 | } | |
1373 | ||
925c058e DE |
1374 | if (swap) |
1375 | { | |
ab3e48dc | 1376 | int i, tmp; |
925c058e DE |
1377 | |
1378 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
1379 | ||
1380 | /* Swap the two insns */ | |
ab3e48dc KH |
1381 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
1382 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); | |
925c058e DE |
1383 | |
1384 | target_make_parallel (insn.addr); | |
1385 | ||
1386 | /* Swap any relaxable frags recorded for the two insns. */ | |
1387 | /* FIXME: Clarify. relaxation precludes parallel insns */ | |
1388 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
1389 | prev_insn.frag->fr_opcode = insn.addr; | |
1390 | else if (insn.frag->fr_opcode == insn.addr) | |
1391 | insn.frag->fr_opcode = prev_insn.addr; | |
1392 | ||
097dba13 NC |
1393 | /* Change a frag to, if each insn is in a different frag. |
1394 | It must keep only one instruction in a frag. */ | |
1395 | if (prev_insn.frag != insn.frag) | |
1396 | { | |
1397 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1398 | prev_insn.fixups[i]->fx_frag = insn.frag; | |
1399 | for (i = 0; i < insn.num_fixups; ++i) | |
1400 | insn.fixups[i]->fx_frag = prev_insn.frag; | |
1401 | } | |
1402 | else | |
1403 | { | |
1404 | /* Update the addresses in any fixups. | |
1405 | Note that we don't have to handle the case where each insn is in | |
1406 | a different frag as we ensure they're in the same frag above. */ | |
1407 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1408 | prev_insn.fixups[i]->fx_where += 2; | |
1409 | for (i = 0; i < insn.num_fixups; ++i) | |
1410 | insn.fixups[i]->fx_where -= 2; | |
1411 | } | |
925c058e | 1412 | } |
252b5132 RH |
1413 | |
1414 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1415 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1416 | if (on_32bit_boundary_p) | |
1417 | prev_insn = insn; | |
1418 | else | |
1419 | prev_insn.insn = NULL; | |
ab3e48dc | 1420 | |
252b5132 RH |
1421 | /* If the insn needs the following one to be on a 32 bit boundary |
1422 | (e.g. subroutine calls), fill this insn's slot. */ | |
1423 | if (on_32bit_boundary_p | |
1424 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
1425 | fill_insn (0); | |
1426 | ||
1427 | /* If this is a relaxable insn (can be replaced with a larger version) | |
1428 | mark the fact so that we can emit an alignment directive for a | |
1429 | following 32 bit insn if we see one. */ | |
1430 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
1431 | seen_relaxable_p = 1; | |
1432 | } | |
1433 | ||
1434 | /* Set these so m32r_fill_insn can use them. */ | |
1435 | prev_seg = now_seg; | |
1436 | prev_subseg = now_subseg; | |
1437 | } | |
1438 | ||
1439 | /* The syntax in the manual says constants begin with '#'. | |
1440 | We just ignore it. */ | |
1441 | ||
ab3e48dc | 1442 | void |
ea1562b3 | 1443 | md_operand (expressionS *expressionP) |
252b5132 | 1444 | { |
ab3e48dc | 1445 | if (*input_line_pointer == '#') |
252b5132 | 1446 | { |
ab3e48dc | 1447 | input_line_pointer++; |
252b5132 RH |
1448 | expression (expressionP); |
1449 | } | |
1450 | } | |
1451 | ||
1452 | valueT | |
ea1562b3 | 1453 | md_section_align (segT segment, valueT size) |
252b5132 RH |
1454 | { |
1455 | int align = bfd_get_section_alignment (stdoutput, segment); | |
ea1562b3 | 1456 | |
252b5132 RH |
1457 | return ((size + (1 << align) - 1) & (-1 << align)); |
1458 | } | |
1459 | ||
1460 | symbolS * | |
ea1562b3 | 1461 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
1462 | { |
1463 | return 0; | |
1464 | } | |
1465 | \f | |
1466 | /* .scomm pseudo-op handler. | |
1467 | ||
1468 | This is a new pseudo-op to handle putting objects in .scommon. | |
ab3e48dc KH |
1469 | By doing this the linker won't need to do any work, |
1470 | and more importantly it removes the implicit -G arg necessary to | |
1471 | correctly link the object file. */ | |
252b5132 RH |
1472 | |
1473 | static void | |
ea1562b3 | 1474 | m32r_scomm (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 1475 | { |
ea1562b3 NC |
1476 | char *name; |
1477 | char c; | |
1478 | char *p; | |
ab3e48dc | 1479 | offsetT size; |
ea1562b3 | 1480 | symbolS *symbolP; |
ab3e48dc KH |
1481 | offsetT align; |
1482 | int align2; | |
252b5132 RH |
1483 | |
1484 | name = input_line_pointer; | |
1485 | c = get_symbol_end (); | |
1486 | ||
ab3e48dc | 1487 | /* Just after name is now '\0'. */ |
252b5132 | 1488 | p = input_line_pointer; |
ab3e48dc | 1489 | *p = c; |
252b5132 | 1490 | SKIP_WHITESPACE (); |
ab3e48dc | 1491 | if (*input_line_pointer != ',') |
252b5132 RH |
1492 | { |
1493 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
1494 | ignore_rest_of_line (); | |
1495 | return; | |
1496 | } | |
1497 | ||
ab3e48dc KH |
1498 | /* Skip ','. */ |
1499 | input_line_pointer++; | |
252b5132 RH |
1500 | if ((size = get_absolute_expression ()) < 0) |
1501 | { | |
ab3e48dc | 1502 | /* xgettext:c-format */ |
252b5132 RH |
1503 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
1504 | ignore_rest_of_line (); | |
1505 | return; | |
1506 | } | |
1507 | ||
1508 | /* The third argument to .scomm is the alignment. */ | |
ab3e48dc | 1509 | if (*input_line_pointer != ',') |
252b5132 RH |
1510 | align = 8; |
1511 | else | |
1512 | { | |
ab3e48dc | 1513 | ++input_line_pointer; |
252b5132 RH |
1514 | align = get_absolute_expression (); |
1515 | if (align <= 0) | |
1516 | { | |
1517 | as_warn (_("ignoring bad alignment")); | |
1518 | align = 8; | |
1519 | } | |
1520 | } | |
ab3e48dc | 1521 | |
252b5132 RH |
1522 | /* Convert to a power of 2 alignment. */ |
1523 | if (align) | |
1524 | { | |
ab3e48dc | 1525 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
252b5132 RH |
1526 | continue; |
1527 | if (align != 1) | |
1528 | { | |
1529 | as_bad (_("Common alignment not a power of 2")); | |
1530 | ignore_rest_of_line (); | |
1531 | return; | |
1532 | } | |
1533 | } | |
1534 | else | |
1535 | align2 = 0; | |
1536 | ||
ab3e48dc | 1537 | *p = 0; |
252b5132 | 1538 | symbolP = symbol_find_or_make (name); |
ab3e48dc | 1539 | *p = c; |
252b5132 RH |
1540 | |
1541 | if (S_IS_DEFINED (symbolP)) | |
1542 | { | |
ab3e48dc | 1543 | /* xgettext:c-format */ |
252b5132 RH |
1544 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
1545 | S_GET_NAME (symbolP)); | |
1546 | ignore_rest_of_line (); | |
1547 | return; | |
1548 | } | |
1549 | ||
1550 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1551 | { | |
ab3e48dc | 1552 | /* xgettext:c-format */ |
252b5132 RH |
1553 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
1554 | S_GET_NAME (symbolP), | |
1555 | (long) S_GET_VALUE (symbolP), | |
1556 | (long) size); | |
1557 | ||
1558 | ignore_rest_of_line (); | |
1559 | return; | |
1560 | } | |
1561 | ||
f412ead8 | 1562 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 1563 | { |
ab3e48dc KH |
1564 | segT old_sec = now_seg; |
1565 | int old_subsec = now_subseg; | |
1566 | char *pfrag; | |
252b5132 RH |
1567 | |
1568 | record_alignment (sbss_section, align2); | |
1569 | subseg_set (sbss_section, 0); | |
ab3e48dc | 1570 | |
252b5132 RH |
1571 | if (align2) |
1572 | frag_align (align2, 0, 0); | |
ab3e48dc | 1573 | |
252b5132 | 1574 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
f412ead8 | 1575 | symbol_get_frag (symbolP)->fr_symbol = 0; |
ab3e48dc | 1576 | |
f412ead8 | 1577 | symbol_set_frag (symbolP, frag_now); |
ab3e48dc | 1578 | |
252b5132 RH |
1579 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1580 | (char *) 0); | |
ab3e48dc | 1581 | *pfrag = 0; |
252b5132 RH |
1582 | S_SET_SIZE (symbolP, size); |
1583 | S_SET_SEGMENT (symbolP, sbss_section); | |
1584 | S_CLEAR_EXTERNAL (symbolP); | |
1585 | subseg_set (old_sec, old_subsec); | |
1586 | } | |
1587 | else | |
1588 | { | |
1589 | S_SET_VALUE (symbolP, (valueT) size); | |
1590 | S_SET_ALIGN (symbolP, align2); | |
1591 | S_SET_EXTERNAL (symbolP); | |
ab3e48dc | 1592 | S_SET_SEGMENT (symbolP, &scom_section); |
252b5132 RH |
1593 | } |
1594 | ||
1595 | demand_empty_rest_of_line (); | |
1596 | } | |
ea1562b3 NC |
1597 | |
1598 | /* The target specific pseudo-ops which we support. */ | |
1599 | const pseudo_typeS md_pseudo_table[] = | |
1600 | { | |
1601 | { "word", cons, 4 }, | |
1602 | { "fillinsn", fill_insn, 0 }, | |
1603 | { "scomm", m32r_scomm, 0 }, | |
1604 | { "debugsym", debug_sym, 0 }, | |
1605 | { "m32r", allow_m32rx, 0 }, | |
1606 | { "m32rx", allow_m32rx, 1 }, | |
1607 | { "m32r2", allow_m32rx, 2 }, | |
1608 | { "little", little, 1 }, | |
1609 | { "big", little, 0 }, | |
1610 | { NULL, NULL, 0 } | |
1611 | }; | |
252b5132 RH |
1612 | \f |
1613 | /* Interface to relax_segment. */ | |
1614 | ||
1615 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1616 | ||
1617 | const relax_typeS md_relax_table[] = | |
1618 | { | |
1619 | /* The fields are: | |
1620 | 1) most positive reach of this state, | |
1621 | 2) most negative reach of this state, | |
1622 | 3) how many bytes this mode will add to the size of the current frag | |
1623 | 4) which index into the table to try if we can't fit into this one. */ | |
1624 | ||
1625 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1626 | each list. */ | |
1627 | {1, 1, 0, 0}, | |
1628 | ||
1629 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1630 | so we subtract 2 from the following. */ | |
1631 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1632 | This doesn't handle a branch in the right slot at the border: | |
1633 | the "& -4" isn't taken into account. It's not important enough to | |
1634 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1635 | case). */ | |
1636 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1637 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1638 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1639 | /* Same thing, but with leading nop for alignment. */ | |
1640 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1641 | }; | |
1642 | ||
1643 | long | |
ea1562b3 | 1644 | m32r_relax_frag (segT segment, fragS *fragP, long stretch) |
252b5132 RH |
1645 | { |
1646 | /* Address of branch insn. */ | |
1647 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1648 | long growth = 0; | |
1649 | ||
1650 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1651 | if (fragP->fr_subtype == 2) | |
1652 | { | |
1653 | if ((address & 3) != 0) | |
1654 | { | |
1655 | fragP->fr_subtype = 3; | |
1656 | growth = 2; | |
1657 | } | |
1658 | } | |
1659 | else if (fragP->fr_subtype == 3) | |
1660 | { | |
1661 | if ((address & 3) == 0) | |
1662 | { | |
1663 | fragP->fr_subtype = 2; | |
1664 | growth = -2; | |
1665 | } | |
1666 | } | |
1667 | else | |
1668 | { | |
c842b53a | 1669 | growth = relax_frag (segment, fragP, stretch); |
252b5132 RH |
1670 | |
1671 | /* Long jump on odd halfword boundary? */ | |
1672 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1673 | { | |
1674 | fragP->fr_subtype = 3; | |
1675 | growth += 2; | |
1676 | } | |
1677 | } | |
1678 | ||
1679 | return growth; | |
1680 | } | |
1681 | ||
1682 | /* Return an initial guess of the length by which a fragment must grow to | |
1683 | hold a branch to reach its destination. | |
1684 | Also updates fr_type/fr_subtype as necessary. | |
1685 | ||
1686 | Called just before doing relaxation. | |
1687 | Any symbol that is now undefined will not become defined. | |
1688 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1689 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
ab3e48dc KH |
1690 | Although it may not be explicit in the frag, pretend fr_var starts |
1691 | with a 0 value. */ | |
252b5132 RH |
1692 | |
1693 | int | |
ea1562b3 | 1694 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 1695 | { |
252b5132 RH |
1696 | /* The only thing we have to handle here are symbols outside of the |
1697 | current segment. They may be undefined or in a different segment in | |
1698 | which case linker scripts may place them anywhere. | |
1699 | However, we can't finish the fragment here and emit the reloc as insn | |
1700 | alignment requirements may move the insn about. */ | |
6edf0760 NC |
1701 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
1702 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1703 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 RH |
1704 | { |
1705 | /* The symbol is undefined in this segment. | |
1706 | Change the relaxation subtype to the max allowable and leave | |
1707 | all further handling to md_convert_frag. */ | |
1708 | fragP->fr_subtype = 2; | |
1709 | ||
252b5132 | 1710 | { |
ab3e48dc KH |
1711 | const CGEN_INSN *insn; |
1712 | int i; | |
252b5132 RH |
1713 | |
1714 | /* Update the recorded insn. | |
1715 | Fortunately we don't have to look very far. | |
1716 | FIXME: Change this to record in the instruction the next higher | |
1717 | relaxable insn to use. */ | |
1718 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1719 | { | |
1720 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
1721 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
1722 | == 0) | |
b11dcf4e | 1723 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
252b5132 RH |
1724 | break; |
1725 | } | |
1726 | if (i == 4) | |
1727 | abort (); | |
1728 | ||
1729 | fragP->fr_cgen.insn = insn; | |
1730 | return 2; | |
1731 | } | |
252b5132 RH |
1732 | } |
1733 | ||
606ab118 | 1734 | return md_relax_table[fragP->fr_subtype].rlx_length; |
ab3e48dc | 1735 | } |
252b5132 | 1736 | |
ab3e48dc | 1737 | /* *FRAGP has been relaxed to its final size, and now needs to have |
252b5132 RH |
1738 | the bytes inside it modified to conform to the new size. |
1739 | ||
1740 | Called after relaxation is finished. | |
1741 | fragP->fr_type == rs_machine_dependent. | |
1742 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1743 | ||
1744 | void | |
ea1562b3 NC |
1745 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
1746 | segT sec, | |
1747 | fragS *fragP) | |
252b5132 | 1748 | { |
ab3e48dc KH |
1749 | char *opcode; |
1750 | char *displacement; | |
1751 | int target_address; | |
1752 | int opcode_address; | |
1753 | int extension; | |
1754 | int addend; | |
252b5132 RH |
1755 | |
1756 | opcode = fragP->fr_opcode; | |
1757 | ||
1758 | /* Address opcode resides at in file space. */ | |
1759 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1760 | ||
1761 | switch (fragP->fr_subtype) | |
1762 | { | |
ab3e48dc | 1763 | case 1: |
252b5132 | 1764 | extension = 0; |
ab3e48dc | 1765 | displacement = &opcode[1]; |
252b5132 | 1766 | break; |
ab3e48dc | 1767 | case 2: |
252b5132 RH |
1768 | opcode[0] |= 0x80; |
1769 | extension = 2; | |
ab3e48dc | 1770 | displacement = &opcode[1]; |
252b5132 | 1771 | break; |
ab3e48dc | 1772 | case 3: |
252b5132 RH |
1773 | opcode[2] = opcode[0] | 0x80; |
1774 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1775 | opcode_address += 2; | |
1776 | extension = 4; | |
ab3e48dc | 1777 | displacement = &opcode[3]; |
252b5132 | 1778 | break; |
ab3e48dc | 1779 | default: |
252b5132 RH |
1780 | abort (); |
1781 | } | |
1782 | ||
6edf0760 NC |
1783 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1784 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1785 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1786 | { |
ab3e48dc | 1787 | /* Symbol must be resolved by linker. */ |
252b5132 RH |
1788 | if (fragP->fr_offset & 3) |
1789 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
6edf0760 NC |
1790 | #ifdef USE_M32R_OLD_RELOC |
1791 | addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ | |
1792 | #else | |
1793 | addend = 0; | |
1794 | #endif | |
252b5132 RH |
1795 | } |
1796 | else | |
1797 | { | |
1798 | /* Address we want to reach in file space. */ | |
1799 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
252b5132 RH |
1800 | addend = (target_address - (opcode_address & -4)) >> 2; |
1801 | } | |
1802 | ||
1803 | /* Create a relocation for symbols that must be resolved by the linker. | |
1804 | Otherwise output the completed insn. */ | |
1805 | ||
6edf0760 NC |
1806 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1807 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1808 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1809 | { |
097f809a NC |
1810 | fixS *fixP; |
1811 | ||
9c2799c2 NC |
1812 | gas_assert (fragP->fr_subtype != 1); |
1813 | gas_assert (fragP->fr_cgen.insn != 0); | |
097f809a NC |
1814 | |
1815 | fixP = gas_cgen_record_fixup (fragP, | |
1816 | /* Offset of branch insn in frag. */ | |
1817 | fragP->fr_fix + extension - 4, | |
1818 | fragP->fr_cgen.insn, | |
1819 | 4 /* Length. */, | |
1820 | /* FIXME: quick hack. */ | |
097f809a NC |
1821 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
1822 | M32R_OPERAND_DISP24), | |
097f809a NC |
1823 | fragP->fr_cgen.opinfo, |
1824 | fragP->fr_symbol, fragP->fr_offset); | |
1825 | if (fragP->fr_cgen.opinfo) | |
1826 | fixP->fx_r_type = fragP->fr_cgen.opinfo; | |
252b5132 RH |
1827 | } |
1828 | ||
1829 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1830 | ||
1831 | md_number_to_chars (displacement, (valueT) addend, | |
1832 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1833 | ||
1834 | fragP->fr_fix += extension; | |
1835 | } | |
1836 | \f | |
1837 | /* Functions concerning relocs. */ | |
1838 | ||
1839 | /* The location from which a PC relative jump should be calculated, | |
1840 | given a PC relative reloc. */ | |
1841 | ||
1842 | long | |
ea1562b3 | 1843 | md_pcrel_from_section (fixS *fixP, segT sec) |
252b5132 RH |
1844 | { |
1845 | if (fixP->fx_addsy != (symbolS *) NULL | |
1846 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
6edf0760 NC |
1847 | || S_GET_SEGMENT (fixP->fx_addsy) != sec |
1848 | || S_IS_EXTERNAL (fixP->fx_addsy) | |
1849 | || S_IS_WEAK (fixP->fx_addsy))) | |
252b5132 | 1850 | { |
a7498ae6 NC |
1851 | if (S_GET_SEGMENT (fixP->fx_addsy) != sec |
1852 | && S_IS_DEFINED (fixP->fx_addsy) | |
1853 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
1854 | && ! S_IS_WEAK (fixP->fx_addsy)) | |
1855 | return fixP->fx_offset; | |
1856 | ||
252b5132 RH |
1857 | /* The symbol is undefined (or is defined but not in this section). |
1858 | Let the linker figure it out. */ | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1863 | } | |
1864 | ||
1865 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1866 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1867 | *FIXP may be modified if desired. */ | |
1868 | ||
1869 | bfd_reloc_code_real_type | |
ea1562b3 NC |
1870 | md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, |
1871 | const CGEN_OPERAND *operand, | |
1872 | fixS *fixP) | |
252b5132 RH |
1873 | { |
1874 | switch (operand->type) | |
1875 | { | |
ab3e48dc KH |
1876 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
1877 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; | |
1878 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; | |
1879 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; | |
1880 | case M32R_OPERAND_HI16: | |
1881 | case M32R_OPERAND_SLO16: | |
1882 | case M32R_OPERAND_ULO16: | |
252b5132 RH |
1883 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1884 | if (fixP->fx_cgen.opinfo != 0) | |
1885 | return fixP->fx_cgen.opinfo; | |
1886 | break; | |
ab3e48dc KH |
1887 | default: |
1888 | /* Avoid -Wall warning. */ | |
252b5132 RH |
1889 | break; |
1890 | } | |
1891 | return BFD_RELOC_NONE; | |
1892 | } | |
1893 | ||
1894 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
1895 | ||
1896 | static void | |
ea1562b3 NC |
1897 | m32r_record_hi16 (int reloc_type, |
1898 | fixS *fixP, | |
1899 | segT seg ATTRIBUTE_UNUSED) | |
252b5132 | 1900 | { |
ab3e48dc | 1901 | struct m32r_hi_fixup *hi_fixup; |
252b5132 | 1902 | |
9c2799c2 | 1903 | gas_assert (reloc_type == BFD_RELOC_M32R_HI16_SLO |
252b5132 RH |
1904 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); |
1905 | ||
ea1562b3 | 1906 | hi_fixup = xmalloc (sizeof (* hi_fixup)); |
252b5132 RH |
1907 | hi_fixup->fixp = fixP; |
1908 | hi_fixup->seg = now_seg; | |
1909 | hi_fixup->next = m32r_hi_fixup_list; | |
ab3e48dc | 1910 | |
252b5132 RH |
1911 | m32r_hi_fixup_list = hi_fixup; |
1912 | } | |
1913 | ||
1914 | /* Called while parsing an instruction to create a fixup. | |
1915 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1916 | ||
1917 | fixS * | |
ea1562b3 NC |
1918 | m32r_cgen_record_fixup_exp (fragS *frag, |
1919 | int where, | |
1920 | const CGEN_INSN *insn, | |
1921 | int length, | |
1922 | const CGEN_OPERAND *operand, | |
1923 | int opinfo, | |
1924 | expressionS *exp) | |
252b5132 | 1925 | { |
097f809a NC |
1926 | fixS *fixP; |
1927 | bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; | |
1928 | ||
1929 | if (m32r_check_fixup (exp, &r_type)) | |
1930 | as_bad (_("Invalid PIC expression.")); | |
1931 | ||
1932 | fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, | |
1933 | operand, opinfo, exp); | |
252b5132 RH |
1934 | |
1935 | switch (operand->type) | |
1936 | { | |
ab3e48dc | 1937 | case M32R_OPERAND_HI16: |
252b5132 RH |
1938 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1939 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1940 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1941 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
1942 | break; | |
097f809a | 1943 | |
ab3e48dc | 1944 | default: |
097f809a | 1945 | /* Avoid -Wall warning. */ |
252b5132 RH |
1946 | break; |
1947 | } | |
1948 | ||
097f809a NC |
1949 | switch (r_type) |
1950 | { | |
1951 | case BFD_RELOC_UNUSED: | |
1952 | default: | |
1953 | return fixP; | |
1954 | ||
1955 | case BFD_RELOC_M32R_GOTPC24: | |
1956 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
1957 | r_type = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
1958 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1959 | r_type = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
1960 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
1961 | r_type = BFD_RELOC_M32R_GOTPC_LO; | |
1962 | break; | |
ea1562b3 | 1963 | |
097f809a NC |
1964 | case BFD_RELOC_M32R_GOT24: |
1965 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
1966 | r_type = BFD_RELOC_M32R_GOT16_HI_SLO; | |
1967 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1968 | r_type = BFD_RELOC_M32R_GOT16_HI_ULO; | |
1969 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
1970 | r_type = BFD_RELOC_M32R_GOT16_LO; | |
1971 | break; | |
ea1562b3 | 1972 | |
097f809a NC |
1973 | case BFD_RELOC_M32R_GOTOFF: |
1974 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
1975 | r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO; | |
1976 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1977 | r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO; | |
1978 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
1979 | r_type = BFD_RELOC_M32R_GOTOFF_LO; | |
1980 | break; | |
ea1562b3 | 1981 | |
097f809a NC |
1982 | case BFD_RELOC_M32R_26_PLTREL: |
1983 | as_bad (_("Invalid PIC expression.")); | |
1984 | break; | |
1985 | } | |
1986 | ||
1987 | fixP->fx_r_type = r_type; | |
1988 | ||
252b5132 RH |
1989 | return fixP; |
1990 | } | |
1991 | ||
1992 | /* Return BFD reloc type from opinfo field in a fixS. | |
1993 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1994 | are BFD_RELOC_UNUSED + operand number. */ | |
1995 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
1996 | ||
1997 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
55cf6793 | 1998 | the corresponding LO16 reloc. This is called before md_apply_fix and |
252b5132 RH |
1999 | tc_gen_reloc. */ |
2000 | ||
2001 | void | |
ea1562b3 | 2002 | m32r_frob_file (void) |
252b5132 | 2003 | { |
ab3e48dc | 2004 | struct m32r_hi_fixup *l; |
252b5132 RH |
2005 | |
2006 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
2007 | { | |
ab3e48dc KH |
2008 | segment_info_type *seginfo; |
2009 | int pass; | |
252b5132 | 2010 | |
9c2799c2 | 2011 | gas_assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO |
252b5132 RH |
2012 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); |
2013 | ||
2014 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
2015 | if (l->fixp->fx_next != NULL | |
2016 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
2017 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
2018 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
2019 | continue; | |
2020 | ||
2021 | /* Look through the fixups for this segment for a matching `low'. | |
2022 | When we find one, move the high/shigh just in front of it. We do | |
2023 | this in two passes. In the first pass, we try to find a | |
2024 | unique `low'. In the second pass, we permit multiple high's | |
2025 | relocs for a single `low'. */ | |
2026 | seginfo = seg_info (l->seg); | |
2027 | for (pass = 0; pass < 2; pass++) | |
2028 | { | |
ab3e48dc KH |
2029 | fixS *f; |
2030 | fixS *prev; | |
252b5132 RH |
2031 | |
2032 | prev = NULL; | |
2033 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
2034 | { | |
2035 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
2036 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
2037 | && f->fx_addsy == l->fixp->fx_addsy | |
2038 | && f->fx_offset == l->fixp->fx_offset | |
2039 | && (pass == 1 | |
2040 | || prev == NULL | |
2041 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
2042 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
2043 | || prev->fx_addsy != f->fx_addsy | |
ab3e48dc | 2044 | || prev->fx_offset != f->fx_offset)) |
252b5132 | 2045 | { |
ab3e48dc | 2046 | fixS **pf; |
252b5132 RH |
2047 | |
2048 | /* Move l->fixp before f. */ | |
2049 | for (pf = &seginfo->fix_root; | |
ab3e48dc KH |
2050 | *pf != l->fixp; |
2051 | pf = & (*pf)->fx_next) | |
9c2799c2 | 2052 | gas_assert (*pf != NULL); |
252b5132 | 2053 | |
ab3e48dc | 2054 | *pf = l->fixp->fx_next; |
252b5132 RH |
2055 | |
2056 | l->fixp->fx_next = f; | |
2057 | if (prev == NULL) | |
2058 | seginfo->fix_root = l->fixp; | |
2059 | else | |
2060 | prev->fx_next = l->fixp; | |
2061 | ||
2062 | break; | |
2063 | } | |
2064 | ||
2065 | prev = f; | |
2066 | } | |
2067 | ||
2068 | if (f != NULL) | |
2069 | break; | |
2070 | ||
2071 | if (pass == 1 | |
2072 | && warn_unmatched_high) | |
2073 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
2074 | _("Unmatched high/shigh reloc")); | |
2075 | } | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | /* See whether we need to force a relocation into the output file. | |
2080 | This is used to force out switch and PC relative relocations when | |
2081 | relaxing. */ | |
2082 | ||
2083 | int | |
ea1562b3 | 2084 | m32r_force_relocation (fixS *fix) |
252b5132 | 2085 | { |
ae6063d4 | 2086 | if (generic_force_reloc (fix)) |
252b5132 RH |
2087 | return 1; |
2088 | ||
2089 | if (! m32r_relax) | |
2090 | return 0; | |
2091 | ||
ab3e48dc | 2092 | return fix->fx_pcrel; |
252b5132 RH |
2093 | } |
2094 | \f | |
2095 | /* Write a value out to the object file, using the appropriate endianness. */ | |
2096 | ||
2097 | void | |
ea1562b3 | 2098 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
2099 | { |
2100 | if (target_big_endian) | |
2101 | number_to_chars_bigendian (buf, val, n); | |
2102 | else | |
2103 | number_to_chars_littleendian (buf, val, n); | |
2104 | } | |
2105 | ||
ab3e48dc KH |
2106 | /* Turn a string in input_line_pointer into a floating point constant |
2107 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2108 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
2109 | returned, or NULL on OK. */ | |
252b5132 | 2110 | |
ab3e48dc | 2111 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
2112 | #define MAX_LITTLENUMS 6 |
2113 | ||
2114 | char * | |
ea1562b3 | 2115 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2116 | { |
499ac353 | 2117 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
2118 | } |
2119 | ||
2120 | void | |
ea1562b3 | 2121 | m32r_elf_section_change_hook (void) |
252b5132 RH |
2122 | { |
2123 | /* If we have reached the end of a section and we have just emitted a | |
2124 | 16 bit insn, then emit a nop to make sure that the section ends on | |
2125 | a 32 bit boundary. */ | |
ab3e48dc | 2126 | |
252b5132 RH |
2127 | if (prev_insn.insn || seen_relaxable_p) |
2128 | (void) m32r_fill_insn (0); | |
2129 | } | |
2130 | ||
60bcf0fa | 2131 | /* Return true if can adjust the reloc to be relative to its section |
ab3e48dc | 2132 | (such as .data) instead of relative to some symbol. */ |
60bcf0fa | 2133 | |
b34976b6 | 2134 | bfd_boolean |
ea1562b3 | 2135 | m32r_fix_adjustable (fixS *fixP) |
252b5132 | 2136 | { |
5c86cbc7 | 2137 | bfd_reloc_code_real_type reloc_type; |
ab3e48dc | 2138 | |
5c86cbc7 CM |
2139 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
2140 | { | |
2141 | const CGEN_INSN *insn = NULL; | |
2142 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; | |
ab3e48dc KH |
2143 | const CGEN_OPERAND *operand = |
2144 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); | |
ea1562b3 | 2145 | |
5c86cbc7 CM |
2146 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
2147 | } | |
2148 | else | |
2149 | reloc_type = fixP->fx_r_type; | |
2150 | ||
6edf0760 NC |
2151 | if (fixP->fx_addsy == NULL) |
2152 | return 1; | |
2153 | ||
2154 | /* Prevent all adjustments to global symbols. */ | |
e97b3f28 | 2155 | if (S_IS_EXTERNAL (fixP->fx_addsy)) |
6edf0760 NC |
2156 | return 0; |
2157 | if (S_IS_WEAK (fixP->fx_addsy)) | |
2158 | return 0; | |
2159 | ||
2160 | if (pic_code | |
2161 | && (reloc_type == BFD_RELOC_M32R_24 | |
2162 | || reloc_type == BFD_RELOC_M32R_26_PCREL | |
2163 | || reloc_type == BFD_RELOC_M32R_HI16_SLO | |
2164 | || reloc_type == BFD_RELOC_M32R_HI16_ULO | |
2165 | || reloc_type == BFD_RELOC_M32R_LO16)) | |
2166 | return 0; | |
2167 | ||
097f809a NC |
2168 | if (reloc_type == BFD_RELOC_M32R_GOT24 |
2169 | || reloc_type == BFD_RELOC_M32R_26_PLTREL | |
2170 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO | |
2171 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO | |
2172 | || reloc_type == BFD_RELOC_M32R_GOTPC_LO | |
2173 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO | |
2174 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO | |
2175 | || reloc_type == BFD_RELOC_M32R_GOT16_LO) | |
2176 | return 0; | |
2177 | ||
ab3e48dc | 2178 | /* We need the symbol name for the VTABLE entries. */ |
5c86cbc7 CM |
2179 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
2180 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
2181 | return 0; |
2182 | ||
2183 | return 1; | |
2184 | } | |
88845958 NC |
2185 | |
2186 | void | |
097f809a | 2187 | m32r_elf_final_processing (void) |
88845958 NC |
2188 | { |
2189 | if (use_parallel) | |
2190 | m32r_flags |= E_M32R_HAS_PARALLEL; | |
2191 | elf_elfheader (stdoutput)->e_flags |= m32r_flags; | |
2192 | } | |
6edf0760 | 2193 | |
6edf0760 NC |
2194 | /* Translate internal representation of relocation info to BFD target |
2195 | format. */ | |
097f809a | 2196 | |
6edf0760 | 2197 | arelent * |
ea1562b3 | 2198 | tc_gen_reloc (asection * section, fixS * fixP) |
6edf0760 NC |
2199 | { |
2200 | arelent * reloc; | |
2201 | bfd_reloc_code_real_type code; | |
2202 | ||
ea1562b3 | 2203 | reloc = xmalloc (sizeof (* reloc)); |
6edf0760 | 2204 | |
ea1562b3 | 2205 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
6edf0760 NC |
2206 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); |
2207 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
157e7bd1 NC |
2208 | |
2209 | if (fixP->fx_pcrel) | |
2210 | { | |
2211 | if (fixP->fx_r_type == BFD_RELOC_32) | |
2212 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
2213 | else if (fixP->fx_r_type == BFD_RELOC_16) | |
2214 | { | |
2215 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
2216 | bfd_set_error (bfd_error_bad_value); | |
2217 | } | |
2218 | } | |
6edf0760 NC |
2219 | |
2220 | code = fixP->fx_r_type; | |
2221 | if (pic_code) | |
2222 | { | |
2223 | #ifdef DEBUG_PIC | |
2224 | printf("%s",bfd_get_reloc_code_name(code)); | |
2225 | #endif | |
2226 | switch (code) | |
2227 | { | |
2228 | case BFD_RELOC_M32R_26_PCREL: | |
2229 | code = BFD_RELOC_M32R_26_PLTREL; | |
2230 | break; | |
ea1562b3 | 2231 | |
6edf0760 NC |
2232 | case BFD_RELOC_M32R_24: |
2233 | if (fixP->fx_addsy != NULL | |
2234 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2235 | code = BFD_RELOC_M32R_GOTPC24; | |
2236 | else | |
2237 | code = BFD_RELOC_M32R_GOT24; | |
2238 | break; | |
ea1562b3 | 2239 | |
6edf0760 NC |
2240 | case BFD_RELOC_M32R_HI16_ULO: |
2241 | if (fixP->fx_addsy != NULL | |
2242 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2243 | code = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
2244 | else | |
2245 | code = BFD_RELOC_M32R_GOT16_HI_ULO; | |
2246 | break; | |
ea1562b3 | 2247 | |
6edf0760 NC |
2248 | case BFD_RELOC_M32R_HI16_SLO: |
2249 | if (fixP->fx_addsy != NULL | |
2250 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2251 | code = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
2252 | else | |
2253 | code = BFD_RELOC_M32R_GOT16_HI_SLO; | |
2254 | break; | |
ea1562b3 | 2255 | |
6edf0760 NC |
2256 | case BFD_RELOC_M32R_LO16: |
2257 | if (fixP->fx_addsy != NULL | |
2258 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2259 | code = BFD_RELOC_M32R_GOTPC_LO; | |
2260 | else | |
2261 | code = BFD_RELOC_M32R_GOT16_LO; | |
2262 | break; | |
ea1562b3 | 2263 | |
6edf0760 NC |
2264 | default: |
2265 | break; | |
2266 | } | |
2267 | #ifdef DEBUG_PIC | |
2268 | printf(" => %s",bfd_get_reloc_code_name(code)); | |
2269 | #endif | |
2270 | } | |
2271 | ||
2272 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
ea1562b3 | 2273 | |
6edf0760 NC |
2274 | #ifdef DEBUG_PIC |
2275 | printf(" => %s\n",reloc->howto->name); | |
2276 | #endif | |
ea1562b3 NC |
2277 | |
2278 | if (reloc->howto == (reloc_howto_type *) NULL) | |
6edf0760 NC |
2279 | { |
2280 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2281 | _("internal error: can't export reloc type %d (`%s')"), | |
2282 | fixP->fx_r_type, bfd_get_reloc_code_name (code)); | |
2283 | return NULL; | |
2284 | } | |
2285 | ||
097f809a | 2286 | /* Use fx_offset for these cases. */ |
6edf0760 | 2287 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
157e7bd1 NC |
2288 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2289 | || fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
6edf0760 | 2290 | reloc->addend = fixP->fx_offset; |
097f809a NC |
2291 | else if ((!pic_code |
2292 | && code != BFD_RELOC_M32R_26_PLTREL) | |
6edf0760 NC |
2293 | && fixP->fx_pcrel |
2294 | && fixP->fx_addsy != NULL | |
2295 | && (S_GET_SEGMENT(fixP->fx_addsy) != section) | |
2296 | && S_IS_DEFINED (fixP->fx_addsy) | |
2297 | && ! S_IS_EXTERNAL(fixP->fx_addsy) | |
2298 | && ! S_IS_WEAK(fixP->fx_addsy)) | |
097f809a | 2299 | /* Already used fx_offset in the opcode field itseld. */ |
a7498ae6 | 2300 | reloc->addend = fixP->fx_offset; |
6edf0760 NC |
2301 | else |
2302 | reloc->addend = fixP->fx_addnumber; | |
2303 | ||
2304 | return reloc; | |
2305 | } | |
097f809a NC |
2306 | |
2307 | inline static char * | |
2308 | m32r_end_of_match (char *cont, char *what) | |
2309 | { | |
2310 | int len = strlen (what); | |
2311 | ||
2312 | if (strncasecmp (cont, what, strlen (what)) == 0 | |
2313 | && ! is_part_of_name (cont[len])) | |
2314 | return cont + len; | |
2315 | ||
2316 | return NULL; | |
2317 | } | |
2318 | ||
2319 | int | |
9497f5ac NC |
2320 | m32r_parse_name (char const *name, |
2321 | expressionS *exprP, | |
2322 | enum expr_mode mode, | |
2323 | char *nextcharP) | |
097f809a NC |
2324 | { |
2325 | char *next = input_line_pointer; | |
2326 | char *next_end; | |
2327 | int reloc_type; | |
2328 | operatorT op_type; | |
2329 | segT segment; | |
2330 | ||
2331 | exprP->X_op_symbol = NULL; | |
2332 | exprP->X_md = BFD_RELOC_UNUSED; | |
2333 | ||
2334 | if (strcmp (name, GOT_NAME) == 0) | |
2335 | { | |
2336 | if (! GOT_symbol) | |
2337 | GOT_symbol = symbol_find_or_make (name); | |
2338 | ||
2339 | exprP->X_add_symbol = GOT_symbol; | |
2340 | no_suffix: | |
2341 | /* If we have an absolute symbol or a | |
2342 | reg, then we know its value now. */ | |
2343 | segment = S_GET_SEGMENT (exprP->X_add_symbol); | |
9497f5ac | 2344 | if (mode != expr_defer && segment == absolute_section) |
097f809a NC |
2345 | { |
2346 | exprP->X_op = O_constant; | |
2347 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); | |
2348 | exprP->X_add_symbol = NULL; | |
2349 | } | |
9497f5ac | 2350 | else if (mode != expr_defer && segment == reg_section) |
097f809a NC |
2351 | { |
2352 | exprP->X_op = O_register; | |
2353 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); | |
2354 | exprP->X_add_symbol = NULL; | |
2355 | } | |
2356 | else | |
2357 | { | |
2358 | exprP->X_op = O_symbol; | |
2359 | exprP->X_add_number = 0; | |
2360 | } | |
2361 | ||
2362 | return 1; | |
2363 | } | |
2364 | ||
2365 | exprP->X_add_symbol = symbol_find_or_make (name); | |
2366 | ||
2367 | if (*nextcharP != '@') | |
2368 | goto no_suffix; | |
2369 | else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF"))) | |
2370 | { | |
2371 | reloc_type = BFD_RELOC_M32R_GOTOFF; | |
2372 | op_type = O_PIC_reloc; | |
2373 | } | |
2374 | else if ((next_end = m32r_end_of_match (next + 1, "GOT"))) | |
2375 | { | |
2376 | reloc_type = BFD_RELOC_M32R_GOT24; | |
2377 | op_type = O_PIC_reloc; | |
2378 | } | |
2379 | else if ((next_end = m32r_end_of_match (next + 1, "PLT"))) | |
2380 | { | |
2381 | reloc_type = BFD_RELOC_M32R_26_PLTREL; | |
2382 | op_type = O_PIC_reloc; | |
2383 | } | |
2384 | else | |
2385 | goto no_suffix; | |
2386 | ||
2387 | *input_line_pointer = *nextcharP; | |
2388 | input_line_pointer = next_end; | |
2389 | *nextcharP = *input_line_pointer; | |
2390 | *input_line_pointer = '\0'; | |
2391 | ||
2392 | exprP->X_op = op_type; | |
2393 | exprP->X_add_number = 0; | |
2394 | exprP->X_md = reloc_type; | |
2395 | ||
2396 | return 1; | |
2397 | } | |
2398 | ||
2399 | int | |
2400 | m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp) | |
2401 | { | |
2402 | if (exp->X_op == O_PIC_reloc | |
2403 | && exp->X_md == BFD_RELOC_M32R_26_PLTREL) | |
2404 | { | |
2405 | exp->X_op = O_symbol; | |
2406 | opinfo = exp->X_md; | |
2407 | } | |
2408 | ||
2409 | return opinfo; | |
2410 | } |