Commit | Line | Data |
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4bf4a882 | 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
bd337dde | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 |
ab3e48dc | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
ab3e48dc | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "symcat.h" |
27 | #include "opcodes/m32r-desc.h" | |
28 | #include "opcodes/m32r-opc.h" | |
29 | #include "cgen.h" | |
88845958 | 30 | #include "elf/m32r.h" |
252b5132 RH |
31 | |
32 | /* Linked list of symbols that are debugging symbols to be defined as the | |
33 | beginning of the current instruction. */ | |
34 | typedef struct sym_link | |
35 | { | |
36 | struct sym_link *next; | |
ab3e48dc | 37 | symbolS *symbol; |
252b5132 RH |
38 | } sym_linkS; |
39 | ||
ab3e48dc KH |
40 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
41 | ||
252b5132 RH |
42 | /* Structure to hold all of the different components describing |
43 | an individual instruction. */ | |
44 | typedef struct | |
45 | { | |
ab3e48dc KH |
46 | const CGEN_INSN *insn; |
47 | const CGEN_INSN *orig_insn; | |
48 | CGEN_FIELDS fields; | |
252b5132 | 49 | #if CGEN_INT_INSN_P |
ab3e48dc | 50 | CGEN_INSN_INT buffer[1]; |
252b5132 RH |
51 | #define INSN_VALUE(buf) (*(buf)) |
52 | #else | |
ab3e48dc | 53 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
252b5132 RH |
54 | #define INSN_VALUE(buf) (buf) |
55 | #endif | |
ab3e48dc KH |
56 | char *addr; |
57 | fragS *frag; | |
58 | int num_fixups; | |
59 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; | |
60 | int indices[MAX_OPERAND_INSTANCES]; | |
61 | sym_linkS *debug_sym_link; | |
252b5132 RH |
62 | } |
63 | m32r_insn; | |
64 | ||
65 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
66 | boundary (i.e. was the first of two 16 bit insns). */ | |
ab3e48dc | 67 | static m32r_insn prev_insn; |
252b5132 RH |
68 | |
69 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
70 | alignment request. */ | |
71 | static int seen_relaxable_p = 0; | |
72 | ||
6edf0760 NC |
73 | /* Non-zero if we are generating PIC code. */ |
74 | int pic_code; | |
75 | ||
252b5132 RH |
76 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
77 | for the linker to do relaxing. | |
78 | We do simple forms of relaxing internally, but they are always done. | |
79 | This flag does not apply to them. */ | |
80 | static int m32r_relax; | |
81 | ||
ab3e48dc KH |
82 | #if 0 |
83 | /* Not supported yet. */ | |
252b5132 RH |
84 | /* If non-NULL, pointer to cpu description file to read. |
85 | This allows runtime additions to the assembler. */ | |
ab3e48dc | 86 | static const char *m32r_cpu_desc; |
252b5132 RH |
87 | #endif |
88 | ||
89 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. | |
90 | Each high/shigh reloc must be paired with it's low cousin in order to | |
91 | properly calculate the addend in a relocatable link (since there is a | |
92 | potential carry from the low to the high/shigh). | |
93 | This option is off by default though for user-written assembler code it | |
94 | might make sense to make the default be on (i.e. have gcc pass a flag | |
95 | to turn it off). This warning must not be on for GCC created code as | |
96 | optimization may delete the low but not the high/shigh (at least we | |
97 | shouldn't assume or require it to). */ | |
98 | static int warn_unmatched_high = 0; | |
99 | ||
88845958 NC |
100 | /* 1 if -m32rx has been specified, in which case support for |
101 | the extended M32RX instruction set should be enabled. | |
102 | 2 if -m32r2 has been specified, in which case support for | |
103 | the extended M32R2 instruction set should be enabled. */ | |
104 | static int enable_m32rx = 0; /* Default to M32R. */ | |
925c058e DE |
105 | |
106 | /* Non-zero if -m32rx -hidden has been specified, in which case support for | |
107 | the special M32RX instruction set should be enabled. */ | |
108 | static int enable_special = 0; | |
109 | ||
88845958 NC |
110 | /* Non-zero if -bitinst has been specified, in which case support |
111 | for extended M32R bit-field instruction set should be enabled. */ | |
bd337dde | 112 | static int enable_special_m32r = 1; |
88845958 NC |
113 | |
114 | /* Non-zero if -float has been specified, in which case support for | |
115 | extended M32R floating point instruction set should be enabled. */ | |
116 | static int enable_special_float = 0; | |
117 | ||
925c058e DE |
118 | /* Non-zero if the programmer should be warned when an explicit parallel |
119 | instruction might have constraint violations. */ | |
120 | static int warn_explicit_parallel_conflicts = 1; | |
121 | ||
b145f546 NC |
122 | /* Non-zero if the programmer should not receive any messages about |
123 | parallel instruction with potential or real constraint violations. | |
124 | The ability to suppress these messages is intended only for hardware | |
125 | vendors testing the chip. It superceedes | |
126 | warn_explicit_parallel_conflicts. */ | |
127 | static int ignore_parallel_conflicts = 0; | |
88845958 | 128 | |
925c058e | 129 | /* Non-zero if insns can be made parallel. */ |
88845958 NC |
130 | static int use_parallel = 1; |
131 | ||
132 | /* Non-zero if optimizations should be performed. */ | |
925c058e | 133 | static int optimize; |
252b5132 | 134 | |
88845958 NC |
135 | /* m32r er_flags. */ |
136 | static int m32r_flags = 0; | |
137 | ||
ab3e48dc | 138 | /* Stuff for .scomm symbols. */ |
252b5132 RH |
139 | static segT sbss_section; |
140 | static asection scom_section; | |
141 | static asymbol scom_symbol; | |
142 | ||
143 | const char comment_chars[] = ";"; | |
144 | const char line_comment_chars[] = "#"; | |
88845958 | 145 | const char line_separator_chars[] = "!"; |
252b5132 RH |
146 | const char EXP_CHARS[] = "eE"; |
147 | const char FLT_CHARS[] = "dD"; | |
148 | ||
149 | /* Relocations against symbols are done in two | |
150 | parts, with a HI relocation and a LO relocation. Each relocation | |
151 | has only 16 bits of space to store an addend. This means that in | |
152 | order for the linker to handle carries correctly, it must be able | |
153 | to locate both the HI and the LO relocation. This means that the | |
154 | relocations must appear in order in the relocation table. | |
155 | ||
156 | In order to implement this, we keep track of each unmatched HI | |
157 | relocation. We then sort them so that they immediately precede the | |
82efde3a | 158 | corresponding LO relocation. */ |
252b5132 RH |
159 | |
160 | struct m32r_hi_fixup | |
161 | { | |
ab3e48dc KH |
162 | /* Next HI fixup. */ |
163 | struct m32r_hi_fixup *next; | |
164 | ||
165 | /* This fixup. */ | |
166 | fixS *fixp; | |
252b5132 | 167 | |
ab3e48dc KH |
168 | /* The section this fixup is in. */ |
169 | segT seg; | |
252b5132 RH |
170 | }; |
171 | ||
172 | /* The list of unmatched HI relocs. */ | |
173 | ||
ab3e48dc | 174 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
252b5132 | 175 | \f |
88845958 NC |
176 | struct { |
177 | enum bfd_architecture bfd_mach; | |
178 | int mach_flags; | |
179 | } mach_table[] = | |
180 | { | |
181 | { bfd_mach_m32r, (1<<MACH_M32R) }, | |
182 | { bfd_mach_m32rx, (1<<MACH_M32RX) }, | |
183 | { bfd_mach_m32r2, (1<<MACH_M32R2) } | |
184 | }; | |
185 | ||
186 | static void allow_m32rx (int); | |
78a0c6fb | 187 | |
925c058e | 188 | static void |
88845958 | 189 | allow_m32rx (int on) |
925c058e DE |
190 | { |
191 | enable_m32rx = on; | |
192 | ||
193 | if (stdoutput != NULL) | |
88845958 NC |
194 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); |
195 | ||
196 | if (gas_cgen_cpu_desc != NULL) | |
197 | gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; | |
925c058e | 198 | } |
252b5132 | 199 | \f |
6edf0760 | 200 | #define M32R_SHORTOPTS "O::K:" |
ab3e48dc KH |
201 | |
202 | const char *md_shortopts = M32R_SHORTOPTS; | |
252b5132 RH |
203 | |
204 | struct option md_longopts[] = | |
205 | { | |
b145f546 NC |
206 | #define OPTION_M32R (OPTION_MD_BASE) |
207 | #define OPTION_M32RX (OPTION_M32R + 1) | |
208 | #define OPTION_M32R2 (OPTION_M32RX + 1) | |
209 | #define OPTION_BIG (OPTION_M32R2 + 1) | |
210 | #define OPTION_LITTLE (OPTION_BIG + 1) | |
211 | #define OPTION_PARALLEL (OPTION_LITTLE + 1) | |
212 | #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1) | |
213 | #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1) | |
214 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) | |
215 | #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1) | |
216 | #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1) | |
217 | #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1) | |
218 | #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1) | |
bd337dde NC |
219 | #define OPTION_NO_SPECIAL_M32R (OPTION_SPECIAL_M32R + 1) |
220 | #define OPTION_SPECIAL_FLOAT (OPTION_NO_SPECIAL_M32R + 1) | |
b145f546 NC |
221 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1) |
222 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) | |
8ad9e709 | 223 | {"m32r", no_argument, NULL, OPTION_M32R}, |
925c058e | 224 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
88845958 NC |
225 | {"m32r2", no_argument, NULL, OPTION_M32R2}, |
226 | {"big", no_argument, NULL, OPTION_BIG}, | |
227 | {"little", no_argument, NULL, OPTION_LITTLE}, | |
228 | {"EB", no_argument, NULL, OPTION_BIG}, | |
229 | {"EL", no_argument, NULL, OPTION_LITTLE}, | |
230 | {"parallel", no_argument, NULL, OPTION_PARALLEL}, | |
231 | {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, | |
925c058e DE |
232 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
233 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
925c058e DE |
234 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
235 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
b145f546 NC |
236 | {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, |
237 | {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, | |
238 | {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
239 | {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
925c058e | 240 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
88845958 | 241 | {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, |
bd337dde | 242 | {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R}, |
88845958 | 243 | {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, |
252b5132 | 244 | /* Sigh. I guess all warnings must now have both variants. */ |
2f3519a2 NC |
245 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
246 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
d3388653 NC |
247 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
248 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, | |
252b5132 | 249 | |
ab3e48dc KH |
250 | #if 0 |
251 | /* Not supported yet. */ | |
8ad9e709 NC |
252 | #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) |
253 | #define OPTION_CPU_DESC (OPTION_RELAX + 1) | |
252b5132 | 254 | {"relax", no_argument, NULL, OPTION_RELAX}, |
252b5132 RH |
255 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
256 | #endif | |
252b5132 RH |
257 | {NULL, no_argument, NULL, 0} |
258 | }; | |
ab3e48dc | 259 | |
252b5132 RH |
260 | size_t md_longopts_size = sizeof (md_longopts); |
261 | ||
88845958 NC |
262 | static void little (int); |
263 | static int parallel (void); | |
264 | ||
265 | static void | |
266 | little (int on) | |
267 | { | |
268 | target_big_endian = ! on; | |
269 | } | |
270 | ||
271 | /* Use parallel execution. */ | |
272 | ||
273 | static int | |
274 | parallel (void) | |
275 | { | |
276 | if (! enable_m32rx) | |
277 | return 0; | |
278 | ||
279 | if (use_parallel == 1) | |
280 | return 1; | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
252b5132 RH |
285 | int |
286 | md_parse_option (c, arg) | |
ab3e48dc | 287 | int c; |
78a0c6fb | 288 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
289 | { |
290 | switch (c) | |
291 | { | |
925c058e DE |
292 | case 'O': |
293 | optimize = 1; | |
88845958 | 294 | use_parallel = 1; |
925c058e DE |
295 | break; |
296 | ||
8ad9e709 NC |
297 | case OPTION_M32R: |
298 | allow_m32rx (0); | |
299 | break; | |
ab3e48dc | 300 | |
925c058e DE |
301 | case OPTION_M32RX: |
302 | allow_m32rx (1); | |
303 | break; | |
ab3e48dc | 304 | |
88845958 NC |
305 | case OPTION_M32R2: |
306 | allow_m32rx (2); | |
307 | enable_special = 1; | |
308 | enable_special_m32r = 1; | |
309 | break; | |
310 | ||
311 | case OPTION_BIG: | |
312 | target_big_endian = 1; | |
313 | break; | |
314 | ||
315 | case OPTION_LITTLE: | |
316 | target_big_endian = 0; | |
317 | break; | |
318 | ||
319 | case OPTION_PARALLEL: | |
320 | use_parallel = 1; | |
321 | break; | |
322 | ||
323 | case OPTION_NO_PARALLEL: | |
324 | use_parallel = 0; | |
325 | break; | |
326 | ||
925c058e DE |
327 | case OPTION_WARN_PARALLEL: |
328 | warn_explicit_parallel_conflicts = 1; | |
329 | break; | |
ab3e48dc | 330 | |
925c058e | 331 | case OPTION_NO_WARN_PARALLEL: |
88845958 | 332 | warn_explicit_parallel_conflicts = 0; |
88845958 NC |
333 | break; |
334 | ||
b145f546 NC |
335 | case OPTION_IGNORE_PARALLEL: |
336 | ignore_parallel_conflicts = 1; | |
88845958 NC |
337 | break; |
338 | ||
b145f546 NC |
339 | case OPTION_NO_IGNORE_PARALLEL: |
340 | ignore_parallel_conflicts = 0; | |
925c058e DE |
341 | break; |
342 | ||
343 | case OPTION_SPECIAL: | |
344 | if (enable_m32rx) | |
345 | enable_special = 1; | |
346 | else | |
347 | { | |
348 | /* Pretend that we do not recognise this option. */ | |
349 | as_bad (_("Unrecognised option: -hidden")); | |
350 | return 0; | |
351 | } | |
352 | break; | |
252b5132 | 353 | |
88845958 NC |
354 | case OPTION_SPECIAL_M32R: |
355 | enable_special_m32r = 1; | |
356 | break; | |
357 | ||
bd337dde NC |
358 | case OPTION_NO_SPECIAL_M32R: |
359 | enable_special_m32r = 0; | |
360 | break; | |
361 | ||
88845958 NC |
362 | case OPTION_SPECIAL_FLOAT: |
363 | enable_special_float = 1; | |
364 | break; | |
365 | ||
252b5132 RH |
366 | case OPTION_WARN_UNMATCHED: |
367 | warn_unmatched_high = 1; | |
368 | break; | |
369 | ||
370 | case OPTION_NO_WARN_UNMATCHED: | |
371 | warn_unmatched_high = 0; | |
372 | break; | |
ab3e48dc | 373 | |
6edf0760 NC |
374 | case 'K': |
375 | if (strcmp (arg, "PIC") != 0) | |
376 | as_warn (_("Unrecognized option following -K")); | |
377 | else | |
378 | pic_code = 1; | |
379 | break; | |
380 | ||
ab3e48dc KH |
381 | #if 0 |
382 | /* Not supported yet. */ | |
252b5132 RH |
383 | case OPTION_RELAX: |
384 | m32r_relax = 1; | |
385 | break; | |
386 | case OPTION_CPU_DESC: | |
387 | m32r_cpu_desc = arg; | |
388 | break; | |
389 | #endif | |
390 | ||
391 | default: | |
392 | return 0; | |
393 | } | |
ab3e48dc | 394 | |
252b5132 RH |
395 | return 1; |
396 | } | |
397 | ||
398 | void | |
399 | md_show_usage (stream) | |
ab3e48dc | 400 | FILE *stream; |
252b5132 RH |
401 | { |
402 | fprintf (stream, _(" M32R specific command line options:\n")); | |
403 | ||
ded0aeb7 NC |
404 | fprintf (stream, _("\ |
405 | -m32r disable support for the m32rx instruction set\n")); | |
925c058e DE |
406 | fprintf (stream, _("\ |
407 | -m32rx support the extended m32rx instruction set\n")); | |
408 | fprintf (stream, _("\ | |
88845958 NC |
409 | -m32r2 support the extended m32r2 instruction set\n")); |
410 | fprintf (stream, _("\ | |
411 | -EL,-little produce little endian code and data\n")); | |
412 | fprintf (stream, _("\ | |
413 | -EB,-big produce big endian code and data\n")); | |
414 | fprintf (stream, _("\ | |
415 | -parallel try to combine instructions in parallel\n")); | |
416 | fprintf (stream, _("\ | |
417 | -no-parallel disable -parallel\n")); | |
418 | fprintf (stream, _("\ | |
bd337dde NC |
419 | -no-bitinst disallow the M32R2's extended bit-field instructions\n")); |
420 | fprintf (stream, _("\ | |
88845958 | 421 | -O try to optimize code. Implies -parallel\n")); |
925c058e DE |
422 | |
423 | fprintf (stream, _("\ | |
424 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); | |
425 | fprintf (stream, _("\ | |
b145f546 | 426 | might violate contraints\n")); |
925c058e DE |
427 | fprintf (stream, _("\ |
428 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); | |
429 | fprintf (stream, _("\ | |
b145f546 | 430 | instructions might violate contraints\n")); |
925c058e DE |
431 | fprintf (stream, _("\ |
432 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); | |
433 | fprintf (stream, _("\ | |
434 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); | |
88845958 | 435 | fprintf (stream, _("\ |
b145f546 | 436 | -ignore-parallel-conflicts do not check parallel instructions\n")); |
88845958 | 437 | fprintf (stream, _("\ |
b145f546 | 438 | fo contraint violations\n")); |
88845958 | 439 | fprintf (stream, _("\ |
b145f546 | 440 | -no-ignore-parallel-conflicts check parallel instructions for\n")); |
88845958 | 441 | fprintf (stream, _("\ |
b145f546 | 442 | contraint violations\n")); |
88845958 | 443 | fprintf (stream, _("\ |
b145f546 | 444 | -Ip synonym for -ignore-parallel-conflicts\n")); |
88845958 | 445 | fprintf (stream, _("\ |
b145f546 | 446 | -nIp synonym for -no-ignore-parallel-conflicts\n")); |
252b5132 RH |
447 | |
448 | fprintf (stream, _("\ | |
449 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
450 | fprintf (stream, _("\ | |
451 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
452 | fprintf (stream, _("\ | |
453 | -Wuh synonym for -warn-unmatched-high\n")); | |
454 | fprintf (stream, _("\ | |
455 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
456 | ||
6edf0760 NC |
457 | fprintf (stream, _("\ |
458 | -KPIC generate PIC\n")); | |
459 | ||
252b5132 RH |
460 | #if 0 |
461 | fprintf (stream, _("\ | |
462 | -relax create linker relaxable code\n")); | |
463 | fprintf (stream, _("\ | |
464 | -cpu-desc provide runtime cpu description file\n")); | |
465 | #endif | |
ab3e48dc | 466 | } |
252b5132 RH |
467 | |
468 | static void fill_insn PARAMS ((int)); | |
469 | static void m32r_scomm PARAMS ((int)); | |
470 | static void debug_sym PARAMS ((int)); | |
471 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
472 | ||
473 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
474 | static subsegT prev_subseg; | |
475 | static segT prev_seg; | |
476 | ||
477 | /* The target specific pseudo-ops which we support. */ | |
478 | const pseudo_typeS md_pseudo_table[] = | |
479 | { | |
480 | { "word", cons, 4 }, | |
481 | { "fillinsn", fill_insn, 0 }, | |
482 | { "scomm", m32r_scomm, 0 }, | |
483 | { "debugsym", debug_sym, 0 }, | |
925c058e DE |
484 | { "m32r", allow_m32rx, 0 }, |
485 | { "m32rx", allow_m32rx, 1 }, | |
88845958 NC |
486 | { "m32r2", allow_m32rx, 2 }, |
487 | { "little", little, 1 }, | |
488 | { "big", little, 0 }, | |
252b5132 RH |
489 | { NULL, NULL, 0 } |
490 | }; | |
491 | ||
492 | /* FIXME: Should be machine generated. */ | |
88845958 | 493 | #define NOP_INSN 0x7000 |
ab3e48dc | 494 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
252b5132 | 495 | |
0a9ef439 RH |
496 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
497 | of an rs_align_code fragment. */ | |
252b5132 | 498 | |
0a9ef439 RH |
499 | void |
500 | m32r_handle_align (fragp) | |
015c05c1 | 501 | fragS *fragp; |
252b5132 | 502 | { |
0a9ef439 RH |
503 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
504 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; | |
252b5132 | 505 | |
0a9ef439 RH |
506 | int bytes, fix; |
507 | char *p; | |
ab3e48dc | 508 | |
0a9ef439 RH |
509 | if (fragp->fr_type != rs_align_code) |
510 | return; | |
511 | ||
512 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
513 | p = fragp->fr_literal + fragp->fr_fix; | |
514 | fix = 0; | |
515 | ||
516 | if (bytes & 1) | |
517 | { | |
518 | fix = 1; | |
519 | *p++ = 0; | |
520 | bytes--; | |
252b5132 RH |
521 | } |
522 | ||
0a9ef439 RH |
523 | if (bytes & 2) |
524 | { | |
525 | memcpy (p, nop_pattern, 2); | |
526 | p += 2; | |
527 | bytes -= 2; | |
528 | fix += 2; | |
529 | } | |
530 | ||
531 | memcpy (p, multi_nop_pattern, 4); | |
532 | ||
533 | fragp->fr_fix += fix; | |
534 | fragp->fr_var = 4; | |
252b5132 RH |
535 | } |
536 | ||
537 | /* If the last instruction was the first of 2 16 bit insns, | |
538 | output a nop to move the PC to a 32 bit boundary. | |
539 | ||
540 | This is done via an alignment specification since branch relaxing | |
541 | may make it unnecessary. | |
542 | ||
543 | Internally, we need to output one of these each time a 32 bit insn is | |
544 | seen after an insn that is relaxable. */ | |
545 | ||
546 | static void | |
547 | fill_insn (ignore) | |
78a0c6fb | 548 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 549 | { |
0a9ef439 | 550 | frag_align_code (2, 0); |
252b5132 RH |
551 | prev_insn.insn = NULL; |
552 | seen_relaxable_p = 0; | |
553 | } | |
554 | ||
555 | /* Record the symbol so that when we output the insn, we can create | |
556 | a symbol that is at the start of the instruction. This is used | |
557 | to emit the label for the start of a breakpoint without causing | |
558 | the assembler to emit a NOP if the previous instruction was a | |
559 | 16 bit instruction. */ | |
560 | ||
561 | static void | |
562 | debug_sym (ignore) | |
78a0c6fb | 563 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
564 | { |
565 | register char *name; | |
566 | register char delim; | |
567 | register char *end_name; | |
568 | register symbolS *symbolP; | |
569 | register sym_linkS *link; | |
570 | ||
571 | name = input_line_pointer; | |
572 | delim = get_symbol_end (); | |
573 | end_name = input_line_pointer; | |
ab3e48dc | 574 | |
252b5132 RH |
575 | if ((symbolP = symbol_find (name)) == NULL |
576 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
577 | { | |
578 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
579 | } | |
580 | ||
581 | symbol_table_insert (symbolP); | |
6edf0760 NC |
582 | if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section |
583 | || S_IS_EXTERNAL (symbolP) | |
584 | || S_IS_WEAK (symbolP))) | |
252b5132 RH |
585 | /* xgettext:c-format */ |
586 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
587 | ||
588 | else | |
589 | { | |
590 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
591 | link->symbol = symbolP; | |
592 | link->next = debug_sym_link; | |
593 | debug_sym_link = link; | |
f412ead8 | 594 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
595 | } |
596 | ||
597 | *end_name = delim; | |
598 | demand_empty_rest_of_line (); | |
599 | } | |
600 | ||
601 | /* Second pass to expanding the debug symbols, go through linked | |
602 | list of symbols and reassign the address. */ | |
603 | ||
604 | static void | |
605 | expand_debug_syms (syms, align) | |
606 | sym_linkS *syms; | |
607 | int align; | |
608 | { | |
609 | char *save_input_line = input_line_pointer; | |
610 | sym_linkS *next_syms; | |
611 | ||
612 | if (!syms) | |
613 | return; | |
614 | ||
a8150a88 | 615 | (void) frag_align_code (align, 0); |
ab3e48dc | 616 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
252b5132 RH |
617 | { |
618 | symbolS *symbolP = syms->symbol; | |
619 | next_syms = syms->next; | |
620 | input_line_pointer = ".\n"; | |
621 | pseudo_set (symbolP); | |
ab3e48dc | 622 | free ((char *) syms); |
252b5132 RH |
623 | } |
624 | ||
625 | input_line_pointer = save_input_line; | |
626 | } | |
627 | ||
88845958 NC |
628 | void |
629 | m32r_flush_pending_output() | |
630 | { | |
631 | if (debug_sym_link) | |
632 | { | |
633 | expand_debug_syms (debug_sym_link, 1); | |
634 | debug_sym_link = (sym_linkS *) 0; | |
635 | } | |
636 | } | |
637 | ||
252b5132 RH |
638 | /* Cover function to fill_insn called after a label and at end of assembly. |
639 | The result is always 1: we're called in a conditional to see if the | |
640 | current line is a label. */ | |
641 | ||
642 | int | |
643 | m32r_fill_insn (done) | |
644 | int done; | |
645 | { | |
646 | if (prev_seg != NULL) | |
647 | { | |
ab3e48dc | 648 | segT seg = now_seg; |
252b5132 RH |
649 | subsegT subseg = now_subseg; |
650 | ||
651 | subseg_set (prev_seg, prev_subseg); | |
ab3e48dc | 652 | |
252b5132 RH |
653 | fill_insn (0); |
654 | ||
655 | subseg_set (seg, subseg); | |
656 | } | |
657 | ||
658 | if (done && debug_sym_link) | |
659 | { | |
660 | expand_debug_syms (debug_sym_link, 1); | |
ab3e48dc | 661 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
662 | } |
663 | ||
664 | return 1; | |
665 | } | |
666 | \f | |
88845958 NC |
667 | /* The default target format to use. */ |
668 | ||
669 | const char * | |
670 | m32r_target_format () | |
671 | { | |
672 | #ifdef TE_LINUX | |
673 | if (target_big_endian) | |
674 | return "elf32-m32r-linux"; | |
675 | else | |
676 | return "elf32-m32rle-linux"; | |
677 | #else | |
678 | if (target_big_endian) | |
679 | return "elf32-m32r"; | |
680 | else | |
681 | return "elf32-m32rle"; | |
682 | #endif | |
683 | } | |
684 | ||
252b5132 RH |
685 | void |
686 | md_begin () | |
687 | { | |
688 | flagword applicable; | |
ab3e48dc KH |
689 | segT seg; |
690 | subsegT subseg; | |
252b5132 RH |
691 | |
692 | /* Initialize the `cgen' interface. */ | |
ab3e48dc | 693 | |
252b5132 RH |
694 | /* Set the machine number and endian. */ |
695 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
696 | CGEN_CPU_OPEN_ENDIAN, | |
88845958 NC |
697 | (target_big_endian ? |
698 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), | |
252b5132 RH |
699 | CGEN_CPU_OPEN_END); |
700 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
701 | ||
702 | /* The operand instance table is used during optimization to determine | |
703 | which insns can be executed in parallel. It is also used to give | |
704 | warnings regarding operand interference in parallel insns. */ | |
705 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
706 | ||
707 | /* This is a callback from cgen to gas to parse operands. */ | |
708 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
709 | ||
ab3e48dc KH |
710 | #if 0 |
711 | /* Not supported yet. */ | |
252b5132 RH |
712 | /* If a runtime cpu description file was provided, parse it. */ |
713 | if (m32r_cpu_desc != NULL) | |
714 | { | |
ab3e48dc | 715 | const char *errmsg; |
252b5132 RH |
716 | |
717 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); | |
718 | if (errmsg != NULL) | |
719 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
720 | } | |
721 | #endif | |
722 | ||
723 | /* Save the current subseg so we can restore it [it's the default one and | |
724 | we don't want the initial section to be .sbss]. */ | |
725 | seg = now_seg; | |
726 | subseg = now_subseg; | |
727 | ||
728 | /* The sbss section is for local .scomm symbols. */ | |
729 | sbss_section = subseg_new (".sbss", 0); | |
ab3e48dc | 730 | |
252b5132 RH |
731 | /* This is copied from perform_an_assembly_pass. */ |
732 | applicable = bfd_applicable_section_flags (stdoutput); | |
733 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ab3e48dc KH |
734 | |
735 | #if 0 | |
736 | /* What does this do? [see perform_an_assembly_pass] */ | |
252b5132 RH |
737 | seg_info (bss_section)->bss = 1; |
738 | #endif | |
739 | ||
740 | subseg_set (seg, subseg); | |
741 | ||
742 | /* We must construct a fake section similar to bfd_com_section | |
743 | but with the name .scommon. */ | |
744 | scom_section = bfd_com_section; | |
745 | scom_section.name = ".scommon"; | |
ab3e48dc KH |
746 | scom_section.output_section = &scom_section; |
747 | scom_section.symbol = &scom_symbol; | |
748 | scom_section.symbol_ptr_ptr = &scom_section.symbol; | |
749 | scom_symbol = *bfd_com_section.symbol; | |
252b5132 | 750 | scom_symbol.name = ".scommon"; |
ab3e48dc | 751 | scom_symbol.section = &scom_section; |
252b5132 | 752 | |
925c058e | 753 | allow_m32rx (enable_m32rx); |
002de68b | 754 | |
07726851 | 755 | gas_cgen_initialize_saved_fixups_array (); |
925c058e DE |
756 | } |
757 | ||
758 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ | |
759 | ((operand)->hw_type == HW_H_COND \ | |
760 | || ((operand)->hw_type == HW_H_PSW) \ | |
761 | || ((operand)->hw_type == HW_H_CR \ | |
762 | && (indices [index] == 0 || indices [index] == 1))) | |
763 | ||
764 | /* Returns true if an output of instruction 'a' is referenced by an operand | |
765 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
766 | checked, otherwise its inputs are examined. */ | |
767 | ||
78a0c6fb AM |
768 | static int first_writes_to_seconds_operands |
769 | PARAMS ((m32r_insn *, m32r_insn *, const int)); | |
770 | ||
925c058e DE |
771 | static int |
772 | first_writes_to_seconds_operands (a, b, check_outputs) | |
ab3e48dc KH |
773 | m32r_insn *a; |
774 | m32r_insn *b; | |
775 | const int check_outputs; | |
925c058e | 776 | { |
ab3e48dc KH |
777 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
778 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); | |
925c058e DE |
779 | int a_index; |
780 | ||
b145f546 NC |
781 | if (ignore_parallel_conflicts) |
782 | return 0; | |
783 | ||
925c058e DE |
784 | /* If at least one of the instructions takes no operands, then there is |
785 | nothing to check. There really are instructions without operands, | |
786 | eg 'nop'. */ | |
787 | if (a_operands == NULL || b_ops == NULL) | |
788 | return 0; | |
ab3e48dc | 789 | |
925c058e DE |
790 | /* Scan the operand list of 'a' looking for an output operand. */ |
791 | for (a_index = 0; | |
792 | a_operands->type != CGEN_OPINST_END; | |
793 | a_index ++, a_operands ++) | |
794 | { | |
795 | if (a_operands->type == CGEN_OPINST_OUTPUT) | |
796 | { | |
797 | int b_index; | |
ab3e48dc | 798 | const CGEN_OPINST *b_operands = b_ops; |
925c058e DE |
799 | |
800 | /* Special Case: | |
801 | The Condition bit 'C' is a shadow of the CBR register (control | |
802 | register 1) and also a shadow of bit 31 of the program status | |
803 | word (control register 0). For now this is handled here, rather | |
ab3e48dc KH |
804 | than by cgen.... */ |
805 | ||
925c058e DE |
806 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
807 | { | |
808 | /* Scan operand list of 'b' looking for another reference to the | |
809 | condition bit, which goes in the right direction. */ | |
810 | for (b_index = 0; | |
811 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 812 | b_index++, b_operands++) |
925c058e DE |
813 | { |
814 | if ((b_operands->type | |
815 | == (check_outputs | |
816 | ? CGEN_OPINST_OUTPUT | |
817 | : CGEN_OPINST_INPUT)) | |
818 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
819 | return 1; | |
820 | } | |
821 | } | |
822 | else | |
823 | { | |
824 | /* Scan operand list of 'b' looking for an operand that | |
825 | references the same hardware element, and which goes in the | |
826 | right direction. */ | |
827 | for (b_index = 0; | |
828 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 829 | b_index++, b_operands++) |
925c058e DE |
830 | { |
831 | if ((b_operands->type | |
832 | == (check_outputs | |
833 | ? CGEN_OPINST_OUTPUT | |
834 | : CGEN_OPINST_INPUT)) | |
835 | && (b_operands->hw_type == a_operands->hw_type) | |
ab3e48dc | 836 | && (a->indices[a_index] == b->indices[b_index])) |
925c058e DE |
837 | return 1; |
838 | } | |
839 | } | |
840 | } | |
841 | } | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | /* Returns true if the insn can (potentially) alter the program counter. */ | |
847 | ||
78a0c6fb AM |
848 | static int writes_to_pc PARAMS ((m32r_insn *)); |
849 | ||
925c058e DE |
850 | static int |
851 | writes_to_pc (a) | |
ab3e48dc | 852 | m32r_insn *a; |
925c058e | 853 | { |
ab3e48dc KH |
854 | #if 0 |
855 | /* Once PC operands are working.... */ | |
856 | const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, | |
857 | a->insn); | |
925c058e DE |
858 | |
859 | if (a_operands == NULL) | |
860 | return 0; | |
861 | ||
862 | while (a_operands->type != CGEN_OPINST_END) | |
863 | { | |
864 | if (a_operands->operand != NULL | |
ab3e48dc KH |
865 | && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, |
866 | a_operands->operand) == M32R_OPERAND_PC) | |
925c058e | 867 | return 1; |
ab3e48dc KH |
868 | |
869 | a_operands++; | |
925c058e DE |
870 | } |
871 | #else | |
872 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) | |
873 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) | |
874 | return 1; | |
875 | #endif | |
876 | return 0; | |
877 | } | |
878 | ||
ab3e48dc KH |
879 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
880 | Otherwise return a pointer to an error message explaining why not. */ | |
925c058e | 881 | |
78a0c6fb AM |
882 | static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *)); |
883 | ||
925c058e DE |
884 | static const char * |
885 | can_make_parallel (a, b) | |
ab3e48dc KH |
886 | m32r_insn *a; |
887 | m32r_insn *b; | |
925c058e DE |
888 | { |
889 | PIPE_ATTR a_pipe; | |
890 | PIPE_ATTR b_pipe; | |
ab3e48dc | 891 | |
925c058e | 892 | /* Make sure the instructions are the right length. */ |
ab3e48dc KH |
893 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
894 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) | |
895 | abort (); | |
925c058e | 896 | |
b34976b6 | 897 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
b145f546 | 898 | return _("instructions write to the same destination register."); |
ab3e48dc | 899 | |
925c058e DE |
900 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
901 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); | |
902 | ||
903 | /* Make sure that the instructions use the correct execution pipelines. */ | |
ab3e48dc | 904 | if (a_pipe == PIPE_NONE |
925c058e DE |
905 | || b_pipe == PIPE_NONE) |
906 | return _("Instructions do not use parallel execution pipelines."); | |
907 | ||
908 | /* Leave this test for last, since it is the only test that can | |
909 | go away if the instructions are swapped, and we want to make | |
910 | sure that any other errors are detected before this happens. */ | |
ab3e48dc | 911 | if (a_pipe == PIPE_S |
88845958 NC |
912 | || b_pipe == PIPE_O |
913 | || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) | |
925c058e | 914 | return _("Instructions share the same execution pipeline"); |
ab3e48dc | 915 | |
925c058e DE |
916 | return NULL; |
917 | } | |
918 | ||
919 | /* Force the top bit of the second 16-bit insn to be set. */ | |
920 | ||
78a0c6fb AM |
921 | static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR)); |
922 | ||
925c058e DE |
923 | static void |
924 | make_parallel (buffer) | |
925 | CGEN_INSN_BYTES_PTR buffer; | |
926 | { | |
927 | #if CGEN_INT_INSN_P | |
928 | *buffer |= 0x8000; | |
929 | #else | |
ab3e48dc | 930 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
931 | |= 0x80; |
932 | #endif | |
252b5132 RH |
933 | } |
934 | ||
925c058e | 935 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
252b5132 | 936 | |
78a0c6fb AM |
937 | static void target_make_parallel PARAMS ((char *)); |
938 | ||
925c058e DE |
939 | static void |
940 | target_make_parallel (buffer) | |
941 | char *buffer; | |
942 | { | |
ab3e48dc | 943 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
944 | |= 0x80; |
945 | } | |
946 | ||
947 | /* Assemble two instructions with an explicit parallel operation (||) or | |
948 | sequential operation (->). */ | |
949 | ||
78a0c6fb AM |
950 | static void assemble_two_insns PARAMS ((char *, char *, int)); |
951 | ||
925c058e DE |
952 | static void |
953 | assemble_two_insns (str, str2, parallel_p) | |
ab3e48dc KH |
954 | char *str; |
955 | char *str2; | |
956 | int parallel_p; | |
925c058e | 957 | { |
ab3e48dc | 958 | char *str3; |
925c058e DE |
959 | m32r_insn first; |
960 | m32r_insn second; | |
ab3e48dc KH |
961 | char *errmsg; |
962 | char save_str2 = *str2; | |
925c058e | 963 | |
67c1ffbe | 964 | /* Separate the two instructions. */ |
ab3e48dc | 965 | *str2 = 0; |
925c058e DE |
966 | |
967 | /* Make sure the two insns begin on a 32 bit boundary. | |
968 | This is also done for the serial case (foo -> bar), relaxing doesn't | |
969 | affect insns written like this. | |
970 | Note that we must always do this as we can't assume anything about | |
971 | whether we're currently on a 32 bit boundary or not. Relaxing may | |
972 | change this. */ | |
973 | fill_insn (0); | |
974 | ||
975 | first.debug_sym_link = debug_sym_link; | |
ab3e48dc | 976 | debug_sym_link = (sym_linkS *) 0; |
925c058e DE |
977 | |
978 | /* Parse the first instruction. */ | |
979 | if (! (first.insn = m32r_cgen_assemble_insn | |
980 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) | |
981 | { | |
982 | as_bad (errmsg); | |
983 | return; | |
984 | } | |
985 | ||
986 | /* Check it. */ | |
987 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) | |
988 | { | |
ab3e48dc | 989 | /* xgettext:c-format */ |
925c058e DE |
990 | as_bad (_("not a 16 bit instruction '%s'"), str); |
991 | return; | |
992 | } | |
88845958 NC |
993 | #ifdef E_M32R2_ARCH |
994 | else if ((enable_m32rx == 1) | |
995 | /* FIXME: Need standard macro to perform this test. */ | |
996 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
997 | & (1 << MACH_M32R2)) | |
998 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
999 | & (1 << MACH_M32RX))))) | |
1000 | { | |
1001 | /* xgettext:c-format */ | |
1002 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1003 | return; | |
1004 | } | |
1005 | else if ((! enable_special | |
1006 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
1007 | || (! enable_special_m32r | |
1008 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) | |
1009 | #else | |
925c058e DE |
1010 | else if (! enable_special |
1011 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1012 | #endif |
925c058e | 1013 | { |
ab3e48dc | 1014 | /* xgettext:c-format */ |
925c058e DE |
1015 | as_bad (_("unknown instruction '%s'"), str); |
1016 | return; | |
1017 | } | |
1018 | else if (! enable_m32rx | |
ab3e48dc KH |
1019 | /* FIXME: Need standard macro to perform this test. */ |
1020 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1021 | == (1 << MACH_M32RX))) | |
925c058e | 1022 | { |
ab3e48dc | 1023 | /* xgettext:c-format */ |
925c058e DE |
1024 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1025 | return; | |
1026 | } | |
ab3e48dc | 1027 | |
925c058e | 1028 | /* Check to see if this is an allowable parallel insn. */ |
ab3e48dc KH |
1029 | if (parallel_p |
1030 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1031 | { |
ab3e48dc | 1032 | /* xgettext:c-format */ |
925c058e DE |
1033 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
1034 | return; | |
1035 | } | |
ab3e48dc KH |
1036 | |
1037 | /* Restore the original assembly text, just in case it is needed. */ | |
1038 | *str2 = save_str2; | |
1039 | ||
1040 | /* Save the original string pointer. */ | |
1041 | str3 = str; | |
1042 | ||
1043 | /* Advanced past the parsed string. */ | |
1044 | str = str2 + 2; | |
1045 | ||
1046 | /* Remember the entire string in case it is needed for error | |
1047 | messages. */ | |
1048 | str2 = str3; | |
925c058e DE |
1049 | |
1050 | /* Convert the opcode to lower case. */ | |
1051 | { | |
1052 | char *s2 = str; | |
ab3e48dc | 1053 | |
3882b010 | 1054 | while (ISSPACE (*s2++)) |
925c058e DE |
1055 | continue; |
1056 | ||
1057 | --s2; | |
1058 | ||
3882b010 | 1059 | while (ISALNUM (*s2)) |
925c058e | 1060 | { |
3882b010 | 1061 | *s2 = TOLOWER (*s2); |
ab3e48dc | 1062 | s2++; |
925c058e DE |
1063 | } |
1064 | } | |
ab3e48dc KH |
1065 | |
1066 | /* Preserve any fixups that have been generated and reset the list | |
1067 | to empty. */ | |
002de68b | 1068 | gas_cgen_save_fixups (0); |
925c058e DE |
1069 | |
1070 | /* Get the indices of the operands of the instruction. */ | |
1071 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
1072 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
1073 | /* FIXME: ALIAS insns do not have operands, so we use this function | |
1074 | to find the equivalent insn and overwrite the value stored in our | |
1075 | structure. We still need the original insn, however, since this | |
1076 | may have certain attributes that are not present in the unaliased | |
1077 | version (eg relaxability). When aliases behave differently this | |
1078 | may have to change. */ | |
1079 | first.orig_insn = first.insn; | |
1080 | { | |
1081 | CGEN_FIELDS tmp_fields; | |
1082 | first.insn = cgen_lookup_get_insn_operands | |
1083 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, | |
1084 | first.indices, &tmp_fields); | |
1085 | } | |
ab3e48dc | 1086 | |
925c058e DE |
1087 | if (first.insn == NULL) |
1088 | as_fatal (_("internal error: lookup/get operands failed")); | |
1089 | ||
1090 | second.debug_sym_link = NULL; | |
1091 | ||
1092 | /* Parse the second instruction. */ | |
1093 | if (! (second.insn = m32r_cgen_assemble_insn | |
1094 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) | |
1095 | { | |
1096 | as_bad (errmsg); | |
1097 | return; | |
1098 | } | |
1099 | ||
1100 | /* Check it. */ | |
1101 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) | |
1102 | { | |
ab3e48dc | 1103 | /* xgettext:c-format */ |
925c058e DE |
1104 | as_bad (_("not a 16 bit instruction '%s'"), str); |
1105 | return; | |
1106 | } | |
88845958 NC |
1107 | #ifdef E_M32R2_ARCH |
1108 | else if ((enable_m32rx == 1) | |
1109 | /* FIXME: Need standard macro to perform this test. */ | |
1110 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1111 | & (1 << MACH_M32R2)) | |
1112 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1113 | & (1 << MACH_M32RX))))) | |
1114 | { | |
1115 | /* xgettext:c-format */ | |
1116 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1117 | return; | |
1118 | } | |
1119 | else if ((! enable_special | |
1120 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1121 | || (! enable_special_m32r | |
1122 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) | |
1123 | #else | |
925c058e DE |
1124 | else if (! enable_special |
1125 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1126 | #endif |
925c058e | 1127 | { |
ab3e48dc | 1128 | /* xgettext:c-format */ |
925c058e DE |
1129 | as_bad (_("unknown instruction '%s'"), str); |
1130 | return; | |
1131 | } | |
1132 | else if (! enable_m32rx | |
1133 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1134 | { | |
ab3e48dc | 1135 | /* xgettext:c-format */ |
925c058e DE |
1136 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1137 | return; | |
1138 | } | |
1139 | ||
1140 | /* Check to see if this is an allowable parallel insn. */ | |
ab3e48dc KH |
1141 | if (parallel_p |
1142 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1143 | { |
ab3e48dc | 1144 | /* xgettext:c-format */ |
925c058e DE |
1145 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
1146 | return; | |
1147 | } | |
ab3e48dc | 1148 | |
925c058e DE |
1149 | if (parallel_p && ! enable_m32rx) |
1150 | { | |
1151 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP | |
1152 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
1153 | { | |
ab3e48dc | 1154 | /* xgettext:c-format */ |
925c058e DE |
1155 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
1156 | return; | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | /* Get the indices of the operands of the instruction. */ | |
1161 | second.orig_insn = second.insn; | |
1162 | { | |
1163 | CGEN_FIELDS tmp_fields; | |
1164 | second.insn = cgen_lookup_get_insn_operands | |
1165 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, | |
1166 | second.indices, &tmp_fields); | |
1167 | } | |
ab3e48dc | 1168 | |
925c058e DE |
1169 | if (second.insn == NULL) |
1170 | as_fatal (_("internal error: lookup/get operands failed")); | |
1171 | ||
1172 | /* We assume that if the first instruction writes to a register that is | |
1173 | read by the second instruction it is because the programmer intended | |
1174 | this to happen, (after all they have explicitly requested that these | |
1175 | two instructions be executed in parallel). Although if the global | |
1176 | variable warn_explicit_parallel_conflicts is true then we do generate | |
1177 | a warning message. Similarly we assume that parallel branch and jump | |
1178 | instructions are deliberate and should not produce errors. */ | |
ab3e48dc | 1179 | |
925c058e DE |
1180 | if (parallel_p && warn_explicit_parallel_conflicts) |
1181 | { | |
b34976b6 | 1182 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
ab3e48dc | 1183 | /* xgettext:c-format */ |
b145f546 | 1184 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
ab3e48dc | 1185 | |
b34976b6 | 1186 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
ab3e48dc | 1187 | /* xgettext:c-format */ |
b145f546 | 1188 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
925c058e | 1189 | } |
ab3e48dc | 1190 | |
925c058e | 1191 | if (!parallel_p |
ab3e48dc | 1192 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
925c058e DE |
1193 | { |
1194 | /* Get the fixups for the first instruction. */ | |
002de68b | 1195 | gas_cgen_swap_fixups (0); |
925c058e DE |
1196 | |
1197 | /* Write it out. */ | |
1198 | expand_debug_syms (first.debug_sym_link, 1); | |
1199 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc KH |
1200 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
1201 | ||
925c058e DE |
1202 | /* Force the top bit of the second insn to be set. */ |
1203 | if (parallel_p) | |
1204 | make_parallel (second.buffer); | |
1205 | ||
1206 | /* Get its fixups. */ | |
002de68b | 1207 | gas_cgen_restore_fixups (0); |
925c058e DE |
1208 | |
1209 | /* Write it out. */ | |
1210 | expand_debug_syms (second.debug_sym_link, 1); | |
1211 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc | 1212 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
925c058e DE |
1213 | } |
1214 | /* Try swapping the instructions to see if they work that way. */ | |
ab3e48dc | 1215 | else if (can_make_parallel (&second, &first) == NULL) |
925c058e DE |
1216 | { |
1217 | /* Write out the second instruction first. */ | |
1218 | expand_debug_syms (second.debug_sym_link, 1); | |
1219 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc KH |
1220 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
1221 | ||
925c058e DE |
1222 | /* Force the top bit of the first instruction to be set. */ |
1223 | make_parallel (first.buffer); | |
1224 | ||
1225 | /* Get the fixups for the first instruction. */ | |
002de68b | 1226 | gas_cgen_restore_fixups (0); |
925c058e DE |
1227 | |
1228 | /* Write out the first instruction. */ | |
1229 | expand_debug_syms (first.debug_sym_link, 1); | |
1230 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc | 1231 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
925c058e DE |
1232 | } |
1233 | else | |
1234 | { | |
1235 | as_bad ("'%s': %s", str2, errmsg); | |
1236 | return; | |
1237 | } | |
ab3e48dc | 1238 | |
88845958 NC |
1239 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) |
1240 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1241 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1242 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) | |
1243 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) | |
1244 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1245 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) | |
1246 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1247 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1248 | ||
925c058e DE |
1249 | /* Set these so m32r_fill_insn can use them. */ |
1250 | prev_seg = now_seg; | |
1251 | prev_subseg = now_subseg; | |
1252 | } | |
252b5132 RH |
1253 | |
1254 | void | |
1255 | md_assemble (str) | |
ab3e48dc | 1256 | char *str; |
252b5132 RH |
1257 | { |
1258 | m32r_insn insn; | |
ab3e48dc KH |
1259 | char *errmsg; |
1260 | char *str2 = NULL; | |
252b5132 RH |
1261 | |
1262 | /* Initialize GAS's cgen interface for a new instruction. */ | |
1263 | gas_cgen_init_parse (); | |
1264 | ||
67c1ffbe | 1265 | /* Look for a parallel instruction separator. */ |
925c058e DE |
1266 | if ((str2 = strstr (str, "||")) != NULL) |
1267 | { | |
1268 | assemble_two_insns (str, str2, 1); | |
88845958 | 1269 | m32r_flags |= E_M32R_HAS_PARALLEL; |
925c058e DE |
1270 | return; |
1271 | } | |
1272 | ||
67c1ffbe | 1273 | /* Also look for a sequential instruction separator. */ |
925c058e DE |
1274 | if ((str2 = strstr (str, "->")) != NULL) |
1275 | { | |
1276 | assemble_two_insns (str, str2, 0); | |
1277 | return; | |
1278 | } | |
ab3e48dc | 1279 | |
252b5132 | 1280 | insn.debug_sym_link = debug_sym_link; |
ab3e48dc | 1281 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
1282 | |
1283 | insn.insn = m32r_cgen_assemble_insn | |
ab3e48dc KH |
1284 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
1285 | ||
252b5132 RH |
1286 | if (!insn.insn) |
1287 | { | |
1288 | as_bad (errmsg); | |
1289 | return; | |
1290 | } | |
1291 | ||
88845958 NC |
1292 | #ifdef E_M32R2_ARCH |
1293 | if ((enable_m32rx == 1) | |
1294 | /* FIXME: Need standard macro to perform this test. */ | |
1295 | && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1296 | & (1 << MACH_M32R2)) | |
1297 | && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1298 | & (1 << MACH_M32RX))))) | |
1299 | { | |
1300 | /* xgettext:c-format */ | |
1301 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1302 | return; | |
1303 | } | |
1304 | else if ((! enable_special | |
1305 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
1306 | || (! enable_special_m32r | |
1307 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) | |
1308 | #else | |
925c058e DE |
1309 | if (! enable_special |
1310 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1311 | #endif |
925c058e | 1312 | { |
ab3e48dc | 1313 | /* xgettext:c-format */ |
925c058e DE |
1314 | as_bad (_("unknown instruction '%s'"), str); |
1315 | return; | |
1316 | } | |
1317 | else if (! enable_m32rx | |
1318 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1319 | { | |
ab3e48dc | 1320 | /* xgettext:c-format */ |
925c058e DE |
1321 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1322 | return; | |
1323 | } | |
ab3e48dc | 1324 | |
88845958 NC |
1325 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
1326 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1327 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) | |
1328 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1329 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1330 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1331 | ||
252b5132 RH |
1332 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
1333 | { | |
1334 | /* 32 bit insns must live on 32 bit boundaries. */ | |
1335 | if (prev_insn.insn || seen_relaxable_p) | |
1336 | { | |
1337 | /* ??? If calling fill_insn too many times turns us into a memory | |
1338 | pig, can we call a fn to assemble a nop instead of | |
1339 | !seen_relaxable_p? */ | |
1340 | fill_insn (0); | |
1341 | } | |
1342 | ||
1343 | expand_debug_syms (insn.debug_sym_link, 2); | |
1344 | ||
1345 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
1346 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
ab3e48dc | 1347 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
252b5132 RH |
1348 | } |
1349 | else | |
1350 | { | |
1351 | int on_32bit_boundary_p; | |
b34976b6 | 1352 | int swap = FALSE; |
252b5132 RH |
1353 | |
1354 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
ab3e48dc | 1355 | abort (); |
252b5132 RH |
1356 | |
1357 | insn.orig_insn = insn.insn; | |
1358 | ||
925c058e DE |
1359 | /* If the previous insn was relaxable, then it may be expanded |
1360 | to fill the current 16 bit slot. Emit a NOP here to occupy | |
1361 | this slot, so that we can start at optimizing at a 32 bit | |
1362 | boundary. */ | |
1363 | if (prev_insn.insn && seen_relaxable_p && optimize) | |
1364 | fill_insn (0); | |
ab3e48dc | 1365 | |
925c058e DE |
1366 | if (enable_m32rx) |
1367 | { | |
1368 | /* Get the indices of the operands of the instruction. | |
1369 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
1370 | { | |
1371 | CGEN_FIELDS tmp_fields; | |
1372 | insn.insn = cgen_lookup_get_insn_operands | |
1373 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, | |
1374 | 16, insn.indices, &tmp_fields); | |
1375 | } | |
ab3e48dc | 1376 | |
925c058e DE |
1377 | if (insn.insn == NULL) |
1378 | as_fatal (_("internal error: lookup/get operands failed")); | |
1379 | } | |
1380 | ||
252b5132 RH |
1381 | /* Compute whether we're on a 32 bit boundary or not. |
1382 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1383 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
1384 | ||
925c058e DE |
1385 | /* Look to see if this instruction can be combined with the |
1386 | previous instruction to make one, parallel, 32 bit instruction. | |
1387 | If the previous instruction (potentially) changed the flow of | |
1388 | program control, then it cannot be combined with the current | |
1389 | instruction. If the current instruction is relaxable, then it | |
1390 | might be replaced with a longer version, so we cannot combine it. | |
1391 | Also if the output of the previous instruction is used as an | |
1392 | input to the current instruction then it cannot be combined. | |
1393 | Otherwise call can_make_parallel() with both orderings of the | |
1394 | instructions to see if they can be combined. */ | |
ab3e48dc | 1395 | if (! on_32bit_boundary_p |
88845958 | 1396 | && parallel () |
ab3e48dc KH |
1397 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
1398 | && ! writes_to_pc (&prev_insn) | |
b34976b6 | 1399 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
925c058e | 1400 | { |
ab3e48dc | 1401 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
925c058e | 1402 | make_parallel (insn.buffer); |
ab3e48dc | 1403 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
b34976b6 | 1404 | swap = TRUE; |
925c058e | 1405 | } |
252b5132 RH |
1406 | |
1407 | expand_debug_syms (insn.debug_sym_link, 1); | |
1408 | ||
1409 | { | |
1410 | int i; | |
1411 | finished_insnS fi; | |
1412 | ||
1413 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1414 | frag_grow (4); | |
1415 | ||
1416 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
ab3e48dc KH |
1417 | CGEN_FIELDS_BITSIZE (&insn.fields), |
1418 | 1 /* relax_p */, &fi); | |
252b5132 RH |
1419 | insn.addr = fi.addr; |
1420 | insn.frag = fi.frag; | |
1421 | insn.num_fixups = fi.num_fixups; | |
1422 | for (i = 0; i < fi.num_fixups; ++i) | |
1423 | insn.fixups[i] = fi.fixups[i]; | |
1424 | } | |
1425 | ||
925c058e DE |
1426 | if (swap) |
1427 | { | |
ab3e48dc | 1428 | int i, tmp; |
925c058e DE |
1429 | |
1430 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
1431 | ||
1432 | /* Swap the two insns */ | |
ab3e48dc KH |
1433 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
1434 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); | |
925c058e DE |
1435 | |
1436 | target_make_parallel (insn.addr); | |
1437 | ||
1438 | /* Swap any relaxable frags recorded for the two insns. */ | |
1439 | /* FIXME: Clarify. relaxation precludes parallel insns */ | |
1440 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
1441 | prev_insn.frag->fr_opcode = insn.addr; | |
1442 | else if (insn.frag->fr_opcode == insn.addr) | |
1443 | insn.frag->fr_opcode = prev_insn.addr; | |
1444 | ||
1445 | /* Update the addresses in any fixups. | |
1446 | Note that we don't have to handle the case where each insn is in | |
1447 | a different frag as we ensure they're in the same frag above. */ | |
1448 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1449 | prev_insn.fixups[i]->fx_where += 2; | |
1450 | for (i = 0; i < insn.num_fixups; ++i) | |
1451 | insn.fixups[i]->fx_where -= 2; | |
1452 | } | |
252b5132 RH |
1453 | |
1454 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1455 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1456 | if (on_32bit_boundary_p) | |
1457 | prev_insn = insn; | |
1458 | else | |
1459 | prev_insn.insn = NULL; | |
ab3e48dc | 1460 | |
252b5132 RH |
1461 | /* If the insn needs the following one to be on a 32 bit boundary |
1462 | (e.g. subroutine calls), fill this insn's slot. */ | |
1463 | if (on_32bit_boundary_p | |
1464 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
1465 | fill_insn (0); | |
1466 | ||
1467 | /* If this is a relaxable insn (can be replaced with a larger version) | |
1468 | mark the fact so that we can emit an alignment directive for a | |
1469 | following 32 bit insn if we see one. */ | |
1470 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
1471 | seen_relaxable_p = 1; | |
1472 | } | |
1473 | ||
1474 | /* Set these so m32r_fill_insn can use them. */ | |
1475 | prev_seg = now_seg; | |
1476 | prev_subseg = now_subseg; | |
1477 | } | |
1478 | ||
1479 | /* The syntax in the manual says constants begin with '#'. | |
1480 | We just ignore it. */ | |
1481 | ||
ab3e48dc | 1482 | void |
252b5132 | 1483 | md_operand (expressionP) |
ab3e48dc | 1484 | expressionS *expressionP; |
252b5132 | 1485 | { |
ab3e48dc | 1486 | if (*input_line_pointer == '#') |
252b5132 | 1487 | { |
ab3e48dc | 1488 | input_line_pointer++; |
252b5132 RH |
1489 | expression (expressionP); |
1490 | } | |
1491 | } | |
1492 | ||
1493 | valueT | |
1494 | md_section_align (segment, size) | |
ab3e48dc | 1495 | segT segment; |
252b5132 RH |
1496 | valueT size; |
1497 | { | |
1498 | int align = bfd_get_section_alignment (stdoutput, segment); | |
1499 | return ((size + (1 << align) - 1) & (-1 << align)); | |
1500 | } | |
1501 | ||
1502 | symbolS * | |
1503 | md_undefined_symbol (name) | |
78a0c6fb | 1504 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
1505 | { |
1506 | return 0; | |
1507 | } | |
1508 | \f | |
1509 | /* .scomm pseudo-op handler. | |
1510 | ||
1511 | This is a new pseudo-op to handle putting objects in .scommon. | |
ab3e48dc KH |
1512 | By doing this the linker won't need to do any work, |
1513 | and more importantly it removes the implicit -G arg necessary to | |
1514 | correctly link the object file. */ | |
252b5132 RH |
1515 | |
1516 | static void | |
1517 | m32r_scomm (ignore) | |
78a0c6fb | 1518 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 1519 | { |
ab3e48dc KH |
1520 | register char *name; |
1521 | register char c; | |
1522 | register char *p; | |
1523 | offsetT size; | |
1524 | register symbolS *symbolP; | |
1525 | offsetT align; | |
1526 | int align2; | |
252b5132 RH |
1527 | |
1528 | name = input_line_pointer; | |
1529 | c = get_symbol_end (); | |
1530 | ||
ab3e48dc | 1531 | /* Just after name is now '\0'. */ |
252b5132 | 1532 | p = input_line_pointer; |
ab3e48dc | 1533 | *p = c; |
252b5132 | 1534 | SKIP_WHITESPACE (); |
ab3e48dc | 1535 | if (*input_line_pointer != ',') |
252b5132 RH |
1536 | { |
1537 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
1538 | ignore_rest_of_line (); | |
1539 | return; | |
1540 | } | |
1541 | ||
ab3e48dc KH |
1542 | /* Skip ','. */ |
1543 | input_line_pointer++; | |
252b5132 RH |
1544 | if ((size = get_absolute_expression ()) < 0) |
1545 | { | |
ab3e48dc | 1546 | /* xgettext:c-format */ |
252b5132 RH |
1547 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
1548 | ignore_rest_of_line (); | |
1549 | return; | |
1550 | } | |
1551 | ||
1552 | /* The third argument to .scomm is the alignment. */ | |
ab3e48dc | 1553 | if (*input_line_pointer != ',') |
252b5132 RH |
1554 | align = 8; |
1555 | else | |
1556 | { | |
ab3e48dc | 1557 | ++input_line_pointer; |
252b5132 RH |
1558 | align = get_absolute_expression (); |
1559 | if (align <= 0) | |
1560 | { | |
1561 | as_warn (_("ignoring bad alignment")); | |
1562 | align = 8; | |
1563 | } | |
1564 | } | |
ab3e48dc | 1565 | |
252b5132 RH |
1566 | /* Convert to a power of 2 alignment. */ |
1567 | if (align) | |
1568 | { | |
ab3e48dc | 1569 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
252b5132 RH |
1570 | continue; |
1571 | if (align != 1) | |
1572 | { | |
1573 | as_bad (_("Common alignment not a power of 2")); | |
1574 | ignore_rest_of_line (); | |
1575 | return; | |
1576 | } | |
1577 | } | |
1578 | else | |
1579 | align2 = 0; | |
1580 | ||
ab3e48dc | 1581 | *p = 0; |
252b5132 | 1582 | symbolP = symbol_find_or_make (name); |
ab3e48dc | 1583 | *p = c; |
252b5132 RH |
1584 | |
1585 | if (S_IS_DEFINED (symbolP)) | |
1586 | { | |
ab3e48dc | 1587 | /* xgettext:c-format */ |
252b5132 RH |
1588 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
1589 | S_GET_NAME (symbolP)); | |
1590 | ignore_rest_of_line (); | |
1591 | return; | |
1592 | } | |
1593 | ||
1594 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1595 | { | |
ab3e48dc | 1596 | /* xgettext:c-format */ |
252b5132 RH |
1597 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
1598 | S_GET_NAME (symbolP), | |
1599 | (long) S_GET_VALUE (symbolP), | |
1600 | (long) size); | |
1601 | ||
1602 | ignore_rest_of_line (); | |
1603 | return; | |
1604 | } | |
1605 | ||
f412ead8 | 1606 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 1607 | { |
ab3e48dc KH |
1608 | segT old_sec = now_seg; |
1609 | int old_subsec = now_subseg; | |
1610 | char *pfrag; | |
252b5132 RH |
1611 | |
1612 | record_alignment (sbss_section, align2); | |
1613 | subseg_set (sbss_section, 0); | |
ab3e48dc | 1614 | |
252b5132 RH |
1615 | if (align2) |
1616 | frag_align (align2, 0, 0); | |
ab3e48dc | 1617 | |
252b5132 | 1618 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
f412ead8 | 1619 | symbol_get_frag (symbolP)->fr_symbol = 0; |
ab3e48dc | 1620 | |
f412ead8 | 1621 | symbol_set_frag (symbolP, frag_now); |
ab3e48dc | 1622 | |
252b5132 RH |
1623 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1624 | (char *) 0); | |
ab3e48dc | 1625 | *pfrag = 0; |
252b5132 RH |
1626 | S_SET_SIZE (symbolP, size); |
1627 | S_SET_SEGMENT (symbolP, sbss_section); | |
1628 | S_CLEAR_EXTERNAL (symbolP); | |
1629 | subseg_set (old_sec, old_subsec); | |
1630 | } | |
1631 | else | |
1632 | { | |
1633 | S_SET_VALUE (symbolP, (valueT) size); | |
1634 | S_SET_ALIGN (symbolP, align2); | |
1635 | S_SET_EXTERNAL (symbolP); | |
ab3e48dc | 1636 | S_SET_SEGMENT (symbolP, &scom_section); |
252b5132 RH |
1637 | } |
1638 | ||
1639 | demand_empty_rest_of_line (); | |
1640 | } | |
1641 | \f | |
1642 | /* Interface to relax_segment. */ | |
1643 | ||
1644 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1645 | ||
1646 | const relax_typeS md_relax_table[] = | |
1647 | { | |
1648 | /* The fields are: | |
1649 | 1) most positive reach of this state, | |
1650 | 2) most negative reach of this state, | |
1651 | 3) how many bytes this mode will add to the size of the current frag | |
1652 | 4) which index into the table to try if we can't fit into this one. */ | |
1653 | ||
1654 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1655 | each list. */ | |
1656 | {1, 1, 0, 0}, | |
1657 | ||
1658 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1659 | so we subtract 2 from the following. */ | |
1660 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1661 | This doesn't handle a branch in the right slot at the border: | |
1662 | the "& -4" isn't taken into account. It's not important enough to | |
1663 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1664 | case). */ | |
1665 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1666 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1667 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1668 | /* Same thing, but with leading nop for alignment. */ | |
1669 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1670 | }; | |
1671 | ||
1672 | long | |
c842b53a ILT |
1673 | m32r_relax_frag (segment, fragP, stretch) |
1674 | segT segment; | |
ab3e48dc KH |
1675 | fragS *fragP; |
1676 | long stretch; | |
252b5132 RH |
1677 | { |
1678 | /* Address of branch insn. */ | |
1679 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1680 | long growth = 0; | |
1681 | ||
1682 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1683 | if (fragP->fr_subtype == 2) | |
1684 | { | |
1685 | if ((address & 3) != 0) | |
1686 | { | |
1687 | fragP->fr_subtype = 3; | |
1688 | growth = 2; | |
1689 | } | |
1690 | } | |
1691 | else if (fragP->fr_subtype == 3) | |
1692 | { | |
1693 | if ((address & 3) == 0) | |
1694 | { | |
1695 | fragP->fr_subtype = 2; | |
1696 | growth = -2; | |
1697 | } | |
1698 | } | |
1699 | else | |
1700 | { | |
c842b53a | 1701 | growth = relax_frag (segment, fragP, stretch); |
252b5132 RH |
1702 | |
1703 | /* Long jump on odd halfword boundary? */ | |
1704 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1705 | { | |
1706 | fragP->fr_subtype = 3; | |
1707 | growth += 2; | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | return growth; | |
1712 | } | |
1713 | ||
1714 | /* Return an initial guess of the length by which a fragment must grow to | |
1715 | hold a branch to reach its destination. | |
1716 | Also updates fr_type/fr_subtype as necessary. | |
1717 | ||
1718 | Called just before doing relaxation. | |
1719 | Any symbol that is now undefined will not become defined. | |
1720 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1721 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
ab3e48dc KH |
1722 | Although it may not be explicit in the frag, pretend fr_var starts |
1723 | with a 0 value. */ | |
252b5132 RH |
1724 | |
1725 | int | |
1726 | md_estimate_size_before_relax (fragP, segment) | |
ab3e48dc KH |
1727 | fragS *fragP; |
1728 | segT segment; | |
252b5132 | 1729 | { |
252b5132 RH |
1730 | /* The only thing we have to handle here are symbols outside of the |
1731 | current segment. They may be undefined or in a different segment in | |
1732 | which case linker scripts may place them anywhere. | |
1733 | However, we can't finish the fragment here and emit the reloc as insn | |
1734 | alignment requirements may move the insn about. */ | |
1735 | ||
6edf0760 NC |
1736 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
1737 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1738 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1739 | { |
78a0c6fb | 1740 | #if 0 |
606ab118 | 1741 | int old_fr_fix = fragP->fr_fix; |
78a0c6fb | 1742 | #endif |
606ab118 | 1743 | |
252b5132 RH |
1744 | /* The symbol is undefined in this segment. |
1745 | Change the relaxation subtype to the max allowable and leave | |
1746 | all further handling to md_convert_frag. */ | |
1747 | fragP->fr_subtype = 2; | |
1748 | ||
ab3e48dc KH |
1749 | #if 0 |
1750 | /* Can't use this, but leave in for illustration. */ | |
252b5132 RH |
1751 | /* Change 16 bit insn to 32 bit insn. */ |
1752 | fragP->fr_opcode[0] |= 0x80; | |
1753 | ||
1754 | /* Increase known (fixed) size of fragment. */ | |
1755 | fragP->fr_fix += 2; | |
1756 | ||
1757 | /* Create a relocation for it. */ | |
1758 | fix_new (fragP, old_fr_fix, 4, | |
1759 | fragP->fr_symbol, | |
ab3e48dc | 1760 | fragP->fr_offset, 1 /* pcrel */, |
252b5132 RH |
1761 | /* FIXME: Can't use a real BFD reloc here. |
1762 | gas_cgen_md_apply_fix3 can't handle it. */ | |
1763 | BFD_RELOC_M32R_26_PCREL); | |
1764 | ||
1765 | /* Mark this fragment as finished. */ | |
1766 | frag_wane (fragP); | |
606ab118 | 1767 | return fragP->fr_fix - old_fr_fix; |
252b5132 RH |
1768 | #else |
1769 | { | |
ab3e48dc KH |
1770 | const CGEN_INSN *insn; |
1771 | int i; | |
252b5132 RH |
1772 | |
1773 | /* Update the recorded insn. | |
1774 | Fortunately we don't have to look very far. | |
1775 | FIXME: Change this to record in the instruction the next higher | |
1776 | relaxable insn to use. */ | |
1777 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1778 | { | |
1779 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
1780 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
1781 | == 0) | |
b11dcf4e | 1782 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
252b5132 RH |
1783 | break; |
1784 | } | |
1785 | if (i == 4) | |
1786 | abort (); | |
1787 | ||
1788 | fragP->fr_cgen.insn = insn; | |
1789 | return 2; | |
1790 | } | |
1791 | #endif | |
1792 | } | |
1793 | ||
606ab118 | 1794 | return md_relax_table[fragP->fr_subtype].rlx_length; |
ab3e48dc | 1795 | } |
252b5132 | 1796 | |
ab3e48dc | 1797 | /* *FRAGP has been relaxed to its final size, and now needs to have |
252b5132 RH |
1798 | the bytes inside it modified to conform to the new size. |
1799 | ||
1800 | Called after relaxation is finished. | |
1801 | fragP->fr_type == rs_machine_dependent. | |
1802 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1803 | ||
1804 | void | |
1805 | md_convert_frag (abfd, sec, fragP) | |
78a0c6fb | 1806 | bfd *abfd ATTRIBUTE_UNUSED; |
ab3e48dc KH |
1807 | segT sec; |
1808 | fragS *fragP; | |
252b5132 | 1809 | { |
ab3e48dc KH |
1810 | char *opcode; |
1811 | char *displacement; | |
1812 | int target_address; | |
1813 | int opcode_address; | |
1814 | int extension; | |
1815 | int addend; | |
252b5132 RH |
1816 | |
1817 | opcode = fragP->fr_opcode; | |
1818 | ||
1819 | /* Address opcode resides at in file space. */ | |
1820 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1821 | ||
1822 | switch (fragP->fr_subtype) | |
1823 | { | |
ab3e48dc | 1824 | case 1: |
252b5132 | 1825 | extension = 0; |
ab3e48dc | 1826 | displacement = &opcode[1]; |
252b5132 | 1827 | break; |
ab3e48dc | 1828 | case 2: |
252b5132 RH |
1829 | opcode[0] |= 0x80; |
1830 | extension = 2; | |
ab3e48dc | 1831 | displacement = &opcode[1]; |
252b5132 | 1832 | break; |
ab3e48dc | 1833 | case 3: |
252b5132 RH |
1834 | opcode[2] = opcode[0] | 0x80; |
1835 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1836 | opcode_address += 2; | |
1837 | extension = 4; | |
ab3e48dc | 1838 | displacement = &opcode[3]; |
252b5132 | 1839 | break; |
ab3e48dc | 1840 | default: |
252b5132 RH |
1841 | abort (); |
1842 | } | |
1843 | ||
6edf0760 NC |
1844 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1845 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1846 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1847 | { |
ab3e48dc | 1848 | /* Symbol must be resolved by linker. */ |
252b5132 RH |
1849 | if (fragP->fr_offset & 3) |
1850 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
6edf0760 NC |
1851 | #ifdef USE_M32R_OLD_RELOC |
1852 | addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ | |
1853 | #else | |
1854 | addend = 0; | |
1855 | #endif | |
252b5132 RH |
1856 | } |
1857 | else | |
1858 | { | |
1859 | /* Address we want to reach in file space. */ | |
1860 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
252b5132 RH |
1861 | addend = (target_address - (opcode_address & -4)) >> 2; |
1862 | } | |
1863 | ||
1864 | /* Create a relocation for symbols that must be resolved by the linker. | |
1865 | Otherwise output the completed insn. */ | |
1866 | ||
6edf0760 NC |
1867 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1868 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1869 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 RH |
1870 | { |
1871 | assert (fragP->fr_subtype != 1); | |
1872 | assert (fragP->fr_cgen.insn != 0); | |
1873 | gas_cgen_record_fixup (fragP, | |
1874 | /* Offset of branch insn in frag. */ | |
1875 | fragP->fr_fix + extension - 4, | |
1876 | fragP->fr_cgen.insn, | |
ab3e48dc KH |
1877 | 4 /* Length. */, |
1878 | /* FIXME: quick hack. */ | |
252b5132 RH |
1879 | #if 0 |
1880 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
1881 | fragP->fr_cgen.opindex), | |
1882 | #else | |
1883 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
1884 | M32R_OPERAND_DISP24), | |
1885 | #endif | |
1886 | fragP->fr_cgen.opinfo, | |
1887 | fragP->fr_symbol, fragP->fr_offset); | |
1888 | } | |
1889 | ||
1890 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1891 | ||
1892 | md_number_to_chars (displacement, (valueT) addend, | |
1893 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1894 | ||
1895 | fragP->fr_fix += extension; | |
1896 | } | |
1897 | \f | |
1898 | /* Functions concerning relocs. */ | |
1899 | ||
1900 | /* The location from which a PC relative jump should be calculated, | |
1901 | given a PC relative reloc. */ | |
1902 | ||
1903 | long | |
1904 | md_pcrel_from_section (fixP, sec) | |
ab3e48dc KH |
1905 | fixS *fixP; |
1906 | segT sec; | |
252b5132 RH |
1907 | { |
1908 | if (fixP->fx_addsy != (symbolS *) NULL | |
1909 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
6edf0760 NC |
1910 | || S_GET_SEGMENT (fixP->fx_addsy) != sec |
1911 | || S_IS_EXTERNAL (fixP->fx_addsy) | |
1912 | || S_IS_WEAK (fixP->fx_addsy))) | |
252b5132 RH |
1913 | { |
1914 | /* The symbol is undefined (or is defined but not in this section). | |
1915 | Let the linker figure it out. */ | |
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1920 | } | |
1921 | ||
1922 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1923 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1924 | *FIXP may be modified if desired. */ | |
1925 | ||
1926 | bfd_reloc_code_real_type | |
1927 | md_cgen_lookup_reloc (insn, operand, fixP) | |
78a0c6fb | 1928 | const CGEN_INSN *insn ATTRIBUTE_UNUSED; |
ab3e48dc KH |
1929 | const CGEN_OPERAND *operand; |
1930 | fixS *fixP; | |
252b5132 RH |
1931 | { |
1932 | switch (operand->type) | |
1933 | { | |
ab3e48dc KH |
1934 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
1935 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; | |
1936 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; | |
1937 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; | |
1938 | case M32R_OPERAND_HI16: | |
1939 | case M32R_OPERAND_SLO16: | |
1940 | case M32R_OPERAND_ULO16: | |
252b5132 RH |
1941 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1942 | if (fixP->fx_cgen.opinfo != 0) | |
1943 | return fixP->fx_cgen.opinfo; | |
1944 | break; | |
ab3e48dc KH |
1945 | default: |
1946 | /* Avoid -Wall warning. */ | |
252b5132 RH |
1947 | break; |
1948 | } | |
1949 | return BFD_RELOC_NONE; | |
1950 | } | |
1951 | ||
1952 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
1953 | ||
78a0c6fb AM |
1954 | static void m32r_record_hi16 PARAMS ((int, fixS *, segT)); |
1955 | ||
252b5132 RH |
1956 | static void |
1957 | m32r_record_hi16 (reloc_type, fixP, seg) | |
ab3e48dc KH |
1958 | int reloc_type; |
1959 | fixS *fixP; | |
78a0c6fb | 1960 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 1961 | { |
ab3e48dc | 1962 | struct m32r_hi_fixup *hi_fixup; |
252b5132 RH |
1963 | |
1964 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1965 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1966 | ||
1967 | hi_fixup = ((struct m32r_hi_fixup *) | |
1968 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1969 | hi_fixup->fixp = fixP; | |
1970 | hi_fixup->seg = now_seg; | |
1971 | hi_fixup->next = m32r_hi_fixup_list; | |
ab3e48dc | 1972 | |
252b5132 RH |
1973 | m32r_hi_fixup_list = hi_fixup; |
1974 | } | |
1975 | ||
1976 | /* Called while parsing an instruction to create a fixup. | |
1977 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1978 | ||
1979 | fixS * | |
1980 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ab3e48dc KH |
1981 | fragS *frag; |
1982 | int where; | |
1983 | const CGEN_INSN *insn; | |
1984 | int length; | |
1985 | const CGEN_OPERAND *operand; | |
1986 | int opinfo; | |
1987 | expressionS *exp; | |
252b5132 | 1988 | { |
ab3e48dc KH |
1989 | fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, |
1990 | operand, opinfo, exp); | |
252b5132 RH |
1991 | |
1992 | switch (operand->type) | |
1993 | { | |
ab3e48dc | 1994 | case M32R_OPERAND_HI16: |
252b5132 RH |
1995 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1996 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1997 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1998 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
1999 | break; | |
ab3e48dc KH |
2000 | default: |
2001 | /* Avoid -Wall warning */ | |
252b5132 RH |
2002 | break; |
2003 | } | |
2004 | ||
2005 | return fixP; | |
2006 | } | |
2007 | ||
2008 | /* Return BFD reloc type from opinfo field in a fixS. | |
2009 | It's tricky using fx_r_type in m32r_frob_file because the values | |
2010 | are BFD_RELOC_UNUSED + operand number. */ | |
2011 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
2012 | ||
2013 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
94f592af | 2014 | the corresponding LO16 reloc. This is called before md_apply_fix3 and |
252b5132 RH |
2015 | tc_gen_reloc. */ |
2016 | ||
2017 | void | |
2018 | m32r_frob_file () | |
2019 | { | |
ab3e48dc | 2020 | struct m32r_hi_fixup *l; |
252b5132 RH |
2021 | |
2022 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
2023 | { | |
ab3e48dc KH |
2024 | segment_info_type *seginfo; |
2025 | int pass; | |
252b5132 RH |
2026 | |
2027 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
2028 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
2029 | ||
2030 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
2031 | if (l->fixp->fx_next != NULL | |
2032 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
2033 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
2034 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
2035 | continue; | |
2036 | ||
2037 | /* Look through the fixups for this segment for a matching `low'. | |
2038 | When we find one, move the high/shigh just in front of it. We do | |
2039 | this in two passes. In the first pass, we try to find a | |
2040 | unique `low'. In the second pass, we permit multiple high's | |
2041 | relocs for a single `low'. */ | |
2042 | seginfo = seg_info (l->seg); | |
2043 | for (pass = 0; pass < 2; pass++) | |
2044 | { | |
ab3e48dc KH |
2045 | fixS *f; |
2046 | fixS *prev; | |
252b5132 RH |
2047 | |
2048 | prev = NULL; | |
2049 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
2050 | { | |
2051 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
2052 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
2053 | && f->fx_addsy == l->fixp->fx_addsy | |
2054 | && f->fx_offset == l->fixp->fx_offset | |
2055 | && (pass == 1 | |
2056 | || prev == NULL | |
2057 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
2058 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
2059 | || prev->fx_addsy != f->fx_addsy | |
ab3e48dc | 2060 | || prev->fx_offset != f->fx_offset)) |
252b5132 | 2061 | { |
ab3e48dc | 2062 | fixS **pf; |
252b5132 RH |
2063 | |
2064 | /* Move l->fixp before f. */ | |
2065 | for (pf = &seginfo->fix_root; | |
ab3e48dc KH |
2066 | *pf != l->fixp; |
2067 | pf = & (*pf)->fx_next) | |
2068 | assert (*pf != NULL); | |
252b5132 | 2069 | |
ab3e48dc | 2070 | *pf = l->fixp->fx_next; |
252b5132 RH |
2071 | |
2072 | l->fixp->fx_next = f; | |
2073 | if (prev == NULL) | |
2074 | seginfo->fix_root = l->fixp; | |
2075 | else | |
2076 | prev->fx_next = l->fixp; | |
2077 | ||
2078 | break; | |
2079 | } | |
2080 | ||
2081 | prev = f; | |
2082 | } | |
2083 | ||
2084 | if (f != NULL) | |
2085 | break; | |
2086 | ||
2087 | if (pass == 1 | |
2088 | && warn_unmatched_high) | |
2089 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
2090 | _("Unmatched high/shigh reloc")); | |
2091 | } | |
2092 | } | |
2093 | } | |
2094 | ||
2095 | /* See whether we need to force a relocation into the output file. | |
2096 | This is used to force out switch and PC relative relocations when | |
2097 | relaxing. */ | |
2098 | ||
2099 | int | |
2100 | m32r_force_relocation (fix) | |
ab3e48dc | 2101 | fixS *fix; |
252b5132 | 2102 | { |
ae6063d4 | 2103 | if (generic_force_reloc (fix)) |
252b5132 RH |
2104 | return 1; |
2105 | ||
2106 | if (! m32r_relax) | |
2107 | return 0; | |
2108 | ||
ab3e48dc | 2109 | return fix->fx_pcrel; |
252b5132 RH |
2110 | } |
2111 | \f | |
2112 | /* Write a value out to the object file, using the appropriate endianness. */ | |
2113 | ||
2114 | void | |
2115 | md_number_to_chars (buf, val, n) | |
ab3e48dc | 2116 | char *buf; |
252b5132 | 2117 | valueT val; |
ab3e48dc | 2118 | int n; |
252b5132 RH |
2119 | { |
2120 | if (target_big_endian) | |
2121 | number_to_chars_bigendian (buf, val, n); | |
2122 | else | |
2123 | number_to_chars_littleendian (buf, val, n); | |
2124 | } | |
2125 | ||
ab3e48dc KH |
2126 | /* Turn a string in input_line_pointer into a floating point constant |
2127 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2128 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
2129 | returned, or NULL on OK. */ | |
252b5132 | 2130 | |
ab3e48dc | 2131 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
2132 | #define MAX_LITTLENUMS 6 |
2133 | ||
2134 | char * | |
2135 | md_atof (type, litP, sizeP) | |
2136 | char type; | |
2137 | char *litP; | |
2138 | int *sizeP; | |
2139 | { | |
ab3e48dc KH |
2140 | int i; |
2141 | int prec; | |
2142 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2143 | char *t; | |
252b5132 RH |
2144 | |
2145 | switch (type) | |
2146 | { | |
2147 | case 'f': | |
2148 | case 'F': | |
2149 | case 's': | |
2150 | case 'S': | |
2151 | prec = 2; | |
2152 | break; | |
2153 | ||
2154 | case 'd': | |
2155 | case 'D': | |
2156 | case 'r': | |
2157 | case 'R': | |
2158 | prec = 4; | |
2159 | break; | |
2160 | ||
ab3e48dc KH |
2161 | /* FIXME: Some targets allow other format chars for bigger sizes |
2162 | here. */ | |
252b5132 RH |
2163 | |
2164 | default: | |
ab3e48dc | 2165 | *sizeP = 0; |
252b5132 RH |
2166 | return _("Bad call to md_atof()"); |
2167 | } | |
2168 | ||
2169 | t = atof_ieee (input_line_pointer, type, words); | |
2170 | if (t) | |
2171 | input_line_pointer = t; | |
ab3e48dc | 2172 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
252b5132 RH |
2173 | |
2174 | if (target_big_endian) | |
2175 | { | |
2176 | for (i = 0; i < prec; i++) | |
2177 | { | |
2178 | md_number_to_chars (litP, (valueT) words[i], | |
2179 | sizeof (LITTLENUM_TYPE)); | |
2180 | litP += sizeof (LITTLENUM_TYPE); | |
2181 | } | |
2182 | } | |
2183 | else | |
2184 | { | |
2185 | for (i = prec - 1; i >= 0; i--) | |
2186 | { | |
2187 | md_number_to_chars (litP, (valueT) words[i], | |
2188 | sizeof (LITTLENUM_TYPE)); | |
2189 | litP += sizeof (LITTLENUM_TYPE); | |
2190 | } | |
2191 | } | |
ab3e48dc | 2192 | |
252b5132 RH |
2193 | return 0; |
2194 | } | |
2195 | ||
2196 | void | |
2197 | m32r_elf_section_change_hook () | |
2198 | { | |
2199 | /* If we have reached the end of a section and we have just emitted a | |
2200 | 16 bit insn, then emit a nop to make sure that the section ends on | |
2201 | a 32 bit boundary. */ | |
ab3e48dc | 2202 | |
252b5132 RH |
2203 | if (prev_insn.insn || seen_relaxable_p) |
2204 | (void) m32r_fill_insn (0); | |
2205 | } | |
2206 | ||
60bcf0fa | 2207 | /* Return true if can adjust the reloc to be relative to its section |
ab3e48dc | 2208 | (such as .data) instead of relative to some symbol. */ |
60bcf0fa | 2209 | |
b34976b6 | 2210 | bfd_boolean |
252b5132 RH |
2211 | m32r_fix_adjustable (fixP) |
2212 | fixS *fixP; | |
2213 | { | |
5c86cbc7 | 2214 | bfd_reloc_code_real_type reloc_type; |
ab3e48dc | 2215 | |
5c86cbc7 CM |
2216 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
2217 | { | |
2218 | const CGEN_INSN *insn = NULL; | |
2219 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; | |
ab3e48dc KH |
2220 | const CGEN_OPERAND *operand = |
2221 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); | |
5c86cbc7 CM |
2222 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
2223 | } | |
2224 | else | |
2225 | reloc_type = fixP->fx_r_type; | |
2226 | ||
6edf0760 NC |
2227 | if (fixP->fx_addsy == NULL) |
2228 | return 1; | |
2229 | ||
2230 | /* Prevent all adjustments to global symbols. */ | |
2231 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
2232 | return 0; | |
2233 | if (S_IS_WEAK (fixP->fx_addsy)) | |
2234 | return 0; | |
2235 | ||
2236 | if (pic_code | |
2237 | && (reloc_type == BFD_RELOC_M32R_24 | |
2238 | || reloc_type == BFD_RELOC_M32R_26_PCREL | |
2239 | || reloc_type == BFD_RELOC_M32R_HI16_SLO | |
2240 | || reloc_type == BFD_RELOC_M32R_HI16_ULO | |
2241 | || reloc_type == BFD_RELOC_M32R_LO16)) | |
2242 | return 0; | |
2243 | ||
ab3e48dc | 2244 | /* We need the symbol name for the VTABLE entries. */ |
5c86cbc7 CM |
2245 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
2246 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
2247 | return 0; |
2248 | ||
2249 | return 1; | |
2250 | } | |
88845958 NC |
2251 | |
2252 | void | |
2253 | m32r_elf_final_processing () | |
2254 | { | |
2255 | if (use_parallel) | |
2256 | m32r_flags |= E_M32R_HAS_PARALLEL; | |
2257 | elf_elfheader (stdoutput)->e_flags |= m32r_flags; | |
2258 | } | |
6edf0760 NC |
2259 | |
2260 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
2261 | ||
2262 | /* Translate internal representation of relocation info to BFD target | |
2263 | format. */ | |
2264 | arelent * | |
2265 | tc_gen_reloc (section, fixP) | |
2266 | asection * section; | |
2267 | fixS * fixP; | |
2268 | { | |
2269 | arelent * reloc; | |
2270 | bfd_reloc_code_real_type code; | |
2271 | ||
2272 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
2273 | ||
2274 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2275 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2276 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
2277 | ||
2278 | code = fixP->fx_r_type; | |
2279 | if (pic_code) | |
2280 | { | |
2281 | #ifdef DEBUG_PIC | |
2282 | printf("%s",bfd_get_reloc_code_name(code)); | |
2283 | #endif | |
2284 | switch (code) | |
2285 | { | |
2286 | case BFD_RELOC_M32R_26_PCREL: | |
2287 | code = BFD_RELOC_M32R_26_PLTREL; | |
2288 | break; | |
2289 | case BFD_RELOC_M32R_24: | |
2290 | if (fixP->fx_addsy != NULL | |
2291 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2292 | code = BFD_RELOC_M32R_GOTPC24; | |
2293 | else | |
2294 | code = BFD_RELOC_M32R_GOT24; | |
2295 | break; | |
2296 | case BFD_RELOC_M32R_HI16_ULO: | |
2297 | if (fixP->fx_addsy != NULL | |
2298 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2299 | code = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
2300 | else | |
2301 | code = BFD_RELOC_M32R_GOT16_HI_ULO; | |
2302 | break; | |
2303 | case BFD_RELOC_M32R_HI16_SLO: | |
2304 | if (fixP->fx_addsy != NULL | |
2305 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2306 | code = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
2307 | else | |
2308 | code = BFD_RELOC_M32R_GOT16_HI_SLO; | |
2309 | break; | |
2310 | case BFD_RELOC_M32R_LO16: | |
2311 | if (fixP->fx_addsy != NULL | |
2312 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2313 | code = BFD_RELOC_M32R_GOTPC_LO; | |
2314 | else | |
2315 | code = BFD_RELOC_M32R_GOT16_LO; | |
2316 | break; | |
2317 | default: | |
2318 | break; | |
2319 | } | |
2320 | #ifdef DEBUG_PIC | |
2321 | printf(" => %s",bfd_get_reloc_code_name(code)); | |
2322 | #endif | |
2323 | } | |
2324 | ||
2325 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
2326 | #ifdef DEBUG_PIC | |
2327 | printf(" => %s\n",reloc->howto->name); | |
2328 | #endif | |
2329 | if (reloc->howto == (reloc_howto_type *) NULL) | |
2330 | { | |
2331 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2332 | _("internal error: can't export reloc type %d (`%s')"), | |
2333 | fixP->fx_r_type, bfd_get_reloc_code_name (code)); | |
2334 | return NULL; | |
2335 | } | |
2336 | ||
2337 | /* Use fx_offset for these cases */ | |
2338 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2339 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) | |
2340 | reloc->addend = fixP->fx_offset; | |
2341 | else if (!pic_code | |
2342 | && fixP->fx_pcrel | |
2343 | && fixP->fx_addsy != NULL | |
2344 | && (S_GET_SEGMENT(fixP->fx_addsy) != section) | |
2345 | && S_IS_DEFINED (fixP->fx_addsy) | |
2346 | && ! S_IS_EXTERNAL(fixP->fx_addsy) | |
2347 | && ! S_IS_WEAK(fixP->fx_addsy)) | |
2348 | /* already used fx_offset in the opcode field itseld. */ | |
2349 | reloc->addend = 0; | |
2350 | else | |
2351 | reloc->addend = fixP->fx_addnumber; | |
2352 | ||
2353 | return reloc; | |
2354 | } |