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252b5132 | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
ab3e48dc KH |
2 | Copyright (C) 1996, 1997, 1998, 1999, 2000 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <ctype.h> | |
24 | #include "as.h" | |
ab3e48dc | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "symcat.h" |
27 | #include "opcodes/m32r-desc.h" | |
28 | #include "opcodes/m32r-opc.h" | |
29 | #include "cgen.h" | |
30 | ||
31 | /* Linked list of symbols that are debugging symbols to be defined as the | |
32 | beginning of the current instruction. */ | |
33 | typedef struct sym_link | |
34 | { | |
35 | struct sym_link *next; | |
ab3e48dc | 36 | symbolS *symbol; |
252b5132 RH |
37 | } sym_linkS; |
38 | ||
ab3e48dc KH |
39 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
40 | ||
252b5132 RH |
41 | /* Structure to hold all of the different components describing |
42 | an individual instruction. */ | |
43 | typedef struct | |
44 | { | |
ab3e48dc KH |
45 | const CGEN_INSN *insn; |
46 | const CGEN_INSN *orig_insn; | |
47 | CGEN_FIELDS fields; | |
252b5132 | 48 | #if CGEN_INT_INSN_P |
ab3e48dc | 49 | CGEN_INSN_INT buffer[1]; |
252b5132 RH |
50 | #define INSN_VALUE(buf) (*(buf)) |
51 | #else | |
ab3e48dc | 52 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
252b5132 RH |
53 | #define INSN_VALUE(buf) (buf) |
54 | #endif | |
ab3e48dc KH |
55 | char *addr; |
56 | fragS *frag; | |
57 | int num_fixups; | |
58 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; | |
59 | int indices[MAX_OPERAND_INSTANCES]; | |
60 | sym_linkS *debug_sym_link; | |
252b5132 RH |
61 | } |
62 | m32r_insn; | |
63 | ||
64 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
65 | boundary (i.e. was the first of two 16 bit insns). */ | |
ab3e48dc | 66 | static m32r_insn prev_insn; |
252b5132 RH |
67 | |
68 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
69 | alignment request. */ | |
70 | static int seen_relaxable_p = 0; | |
71 | ||
72 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
73 | for the linker to do relaxing. | |
74 | We do simple forms of relaxing internally, but they are always done. | |
75 | This flag does not apply to them. */ | |
76 | static int m32r_relax; | |
77 | ||
ab3e48dc KH |
78 | #if 0 |
79 | /* Not supported yet. */ | |
252b5132 RH |
80 | /* If non-NULL, pointer to cpu description file to read. |
81 | This allows runtime additions to the assembler. */ | |
ab3e48dc | 82 | static const char *m32r_cpu_desc; |
252b5132 RH |
83 | #endif |
84 | ||
85 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. | |
86 | Each high/shigh reloc must be paired with it's low cousin in order to | |
87 | properly calculate the addend in a relocatable link (since there is a | |
88 | potential carry from the low to the high/shigh). | |
89 | This option is off by default though for user-written assembler code it | |
90 | might make sense to make the default be on (i.e. have gcc pass a flag | |
91 | to turn it off). This warning must not be on for GCC created code as | |
92 | optimization may delete the low but not the high/shigh (at least we | |
93 | shouldn't assume or require it to). */ | |
94 | static int warn_unmatched_high = 0; | |
95 | ||
925c058e DE |
96 | /* Non-zero if -m32rx has been specified, in which case support for the |
97 | extended M32RX instruction set should be enabled. */ | |
98 | static int enable_m32rx = 0; | |
99 | ||
100 | /* Non-zero if -m32rx -hidden has been specified, in which case support for | |
101 | the special M32RX instruction set should be enabled. */ | |
102 | static int enable_special = 0; | |
103 | ||
104 | /* Non-zero if the programmer should be warned when an explicit parallel | |
105 | instruction might have constraint violations. */ | |
106 | static int warn_explicit_parallel_conflicts = 1; | |
107 | ||
108 | /* Non-zero if insns can be made parallel. */ | |
109 | static int optimize; | |
252b5132 | 110 | |
ab3e48dc | 111 | /* Stuff for .scomm symbols. */ |
252b5132 RH |
112 | static segT sbss_section; |
113 | static asection scom_section; | |
114 | static asymbol scom_symbol; | |
115 | ||
116 | const char comment_chars[] = ";"; | |
117 | const char line_comment_chars[] = "#"; | |
118 | const char line_separator_chars[] = ""; | |
119 | const char EXP_CHARS[] = "eE"; | |
120 | const char FLT_CHARS[] = "dD"; | |
121 | ||
122 | /* Relocations against symbols are done in two | |
123 | parts, with a HI relocation and a LO relocation. Each relocation | |
124 | has only 16 bits of space to store an addend. This means that in | |
125 | order for the linker to handle carries correctly, it must be able | |
126 | to locate both the HI and the LO relocation. This means that the | |
127 | relocations must appear in order in the relocation table. | |
128 | ||
129 | In order to implement this, we keep track of each unmatched HI | |
130 | relocation. We then sort them so that they immediately precede the | |
82efde3a | 131 | corresponding LO relocation. */ |
252b5132 RH |
132 | |
133 | struct m32r_hi_fixup | |
134 | { | |
ab3e48dc KH |
135 | /* Next HI fixup. */ |
136 | struct m32r_hi_fixup *next; | |
137 | ||
138 | /* This fixup. */ | |
139 | fixS *fixp; | |
252b5132 | 140 | |
ab3e48dc KH |
141 | /* The section this fixup is in. */ |
142 | segT seg; | |
252b5132 RH |
143 | }; |
144 | ||
145 | /* The list of unmatched HI relocs. */ | |
146 | ||
ab3e48dc | 147 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
252b5132 | 148 | \f |
925c058e DE |
149 | static void |
150 | allow_m32rx (on) | |
151 | int on; | |
152 | { | |
153 | enable_m32rx = on; | |
154 | ||
155 | if (stdoutput != NULL) | |
156 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, | |
157 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
158 | } | |
252b5132 | 159 | \f |
925c058e | 160 | #define M32R_SHORTOPTS "O" |
ab3e48dc KH |
161 | |
162 | const char *md_shortopts = M32R_SHORTOPTS; | |
252b5132 RH |
163 | |
164 | struct option md_longopts[] = | |
165 | { | |
8ad9e709 NC |
166 | #define OPTION_M32R (OPTION_MD_BASE) |
167 | #define OPTION_M32RX (OPTION_M32R + 1) | |
168 | #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1) | |
169 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) | |
170 | #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1) | |
171 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1) | |
172 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) | |
173 | {"m32r", no_argument, NULL, OPTION_M32R}, | |
925c058e | 174 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
925c058e DE |
175 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
176 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
925c058e DE |
177 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
178 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
925c058e | 179 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
252b5132 | 180 | /* Sigh. I guess all warnings must now have both variants. */ |
2f3519a2 NC |
181 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
182 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
d3388653 NC |
183 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
184 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, | |
252b5132 | 185 | |
ab3e48dc KH |
186 | #if 0 |
187 | /* Not supported yet. */ | |
8ad9e709 NC |
188 | #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) |
189 | #define OPTION_CPU_DESC (OPTION_RELAX + 1) | |
252b5132 | 190 | {"relax", no_argument, NULL, OPTION_RELAX}, |
252b5132 RH |
191 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
192 | #endif | |
252b5132 RH |
193 | {NULL, no_argument, NULL, 0} |
194 | }; | |
ab3e48dc | 195 | |
252b5132 RH |
196 | size_t md_longopts_size = sizeof (md_longopts); |
197 | ||
198 | int | |
199 | md_parse_option (c, arg) | |
ab3e48dc KH |
200 | int c; |
201 | char *arg; | |
252b5132 RH |
202 | { |
203 | switch (c) | |
204 | { | |
925c058e DE |
205 | case 'O': |
206 | optimize = 1; | |
207 | break; | |
208 | ||
8ad9e709 NC |
209 | case OPTION_M32R: |
210 | allow_m32rx (0); | |
211 | break; | |
ab3e48dc | 212 | |
925c058e DE |
213 | case OPTION_M32RX: |
214 | allow_m32rx (1); | |
215 | break; | |
ab3e48dc | 216 | |
925c058e DE |
217 | case OPTION_WARN_PARALLEL: |
218 | warn_explicit_parallel_conflicts = 1; | |
219 | break; | |
ab3e48dc | 220 | |
925c058e DE |
221 | case OPTION_NO_WARN_PARALLEL: |
222 | warn_explicit_parallel_conflicts = 0; | |
223 | break; | |
224 | ||
225 | case OPTION_SPECIAL: | |
226 | if (enable_m32rx) | |
227 | enable_special = 1; | |
228 | else | |
229 | { | |
230 | /* Pretend that we do not recognise this option. */ | |
231 | as_bad (_("Unrecognised option: -hidden")); | |
232 | return 0; | |
233 | } | |
234 | break; | |
252b5132 RH |
235 | |
236 | case OPTION_WARN_UNMATCHED: | |
237 | warn_unmatched_high = 1; | |
238 | break; | |
239 | ||
240 | case OPTION_NO_WARN_UNMATCHED: | |
241 | warn_unmatched_high = 0; | |
242 | break; | |
ab3e48dc KH |
243 | |
244 | #if 0 | |
245 | /* Not supported yet. */ | |
252b5132 RH |
246 | case OPTION_RELAX: |
247 | m32r_relax = 1; | |
248 | break; | |
249 | case OPTION_CPU_DESC: | |
250 | m32r_cpu_desc = arg; | |
251 | break; | |
252 | #endif | |
253 | ||
254 | default: | |
255 | return 0; | |
256 | } | |
ab3e48dc | 257 | |
252b5132 RH |
258 | return 1; |
259 | } | |
260 | ||
261 | void | |
262 | md_show_usage (stream) | |
ab3e48dc | 263 | FILE *stream; |
252b5132 RH |
264 | { |
265 | fprintf (stream, _(" M32R specific command line options:\n")); | |
266 | ||
ded0aeb7 NC |
267 | fprintf (stream, _("\ |
268 | -m32r disable support for the m32rx instruction set\n")); | |
925c058e DE |
269 | fprintf (stream, _("\ |
270 | -m32rx support the extended m32rx instruction set\n")); | |
271 | fprintf (stream, _("\ | |
272 | -O try to combine instructions in parallel\n")); | |
273 | ||
274 | fprintf (stream, _("\ | |
275 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); | |
276 | fprintf (stream, _("\ | |
277 | violate contraints\n")); | |
278 | fprintf (stream, _("\ | |
279 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); | |
280 | fprintf (stream, _("\ | |
281 | instructions violate contraints\n")); | |
282 | fprintf (stream, _("\ | |
283 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); | |
284 | fprintf (stream, _("\ | |
285 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); | |
252b5132 RH |
286 | |
287 | fprintf (stream, _("\ | |
288 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
289 | fprintf (stream, _("\ | |
290 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
291 | fprintf (stream, _("\ | |
292 | -Wuh synonym for -warn-unmatched-high\n")); | |
293 | fprintf (stream, _("\ | |
294 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
295 | ||
296 | #if 0 | |
297 | fprintf (stream, _("\ | |
298 | -relax create linker relaxable code\n")); | |
299 | fprintf (stream, _("\ | |
300 | -cpu-desc provide runtime cpu description file\n")); | |
301 | #endif | |
ab3e48dc | 302 | } |
252b5132 RH |
303 | |
304 | static void fill_insn PARAMS ((int)); | |
305 | static void m32r_scomm PARAMS ((int)); | |
306 | static void debug_sym PARAMS ((int)); | |
307 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
308 | ||
309 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
310 | static subsegT prev_subseg; | |
311 | static segT prev_seg; | |
312 | ||
313 | /* The target specific pseudo-ops which we support. */ | |
314 | const pseudo_typeS md_pseudo_table[] = | |
315 | { | |
316 | { "word", cons, 4 }, | |
317 | { "fillinsn", fill_insn, 0 }, | |
318 | { "scomm", m32r_scomm, 0 }, | |
319 | { "debugsym", debug_sym, 0 }, | |
ab3e48dc | 320 | /* Not documented as so far there is no need for them.... */ |
925c058e DE |
321 | { "m32r", allow_m32rx, 0 }, |
322 | { "m32rx", allow_m32rx, 1 }, | |
252b5132 RH |
323 | { NULL, NULL, 0 } |
324 | }; | |
325 | ||
326 | /* FIXME: Should be machine generated. */ | |
327 | #define NOP_INSN 0x7000 | |
ab3e48dc | 328 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
252b5132 | 329 | |
0a9ef439 RH |
330 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
331 | of an rs_align_code fragment. */ | |
252b5132 | 332 | |
0a9ef439 RH |
333 | void |
334 | m32r_handle_align (fragp) | |
252b5132 | 335 | { |
0a9ef439 RH |
336 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
337 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; | |
252b5132 | 338 | |
0a9ef439 RH |
339 | int bytes, fix; |
340 | char *p; | |
ab3e48dc | 341 | |
0a9ef439 RH |
342 | if (fragp->fr_type != rs_align_code) |
343 | return; | |
344 | ||
345 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
346 | p = fragp->fr_literal + fragp->fr_fix; | |
347 | fix = 0; | |
348 | ||
349 | if (bytes & 1) | |
350 | { | |
351 | fix = 1; | |
352 | *p++ = 0; | |
353 | bytes--; | |
252b5132 RH |
354 | } |
355 | ||
0a9ef439 RH |
356 | if (bytes & 2) |
357 | { | |
358 | memcpy (p, nop_pattern, 2); | |
359 | p += 2; | |
360 | bytes -= 2; | |
361 | fix += 2; | |
362 | } | |
363 | ||
364 | memcpy (p, multi_nop_pattern, 4); | |
365 | ||
366 | fragp->fr_fix += fix; | |
367 | fragp->fr_var = 4; | |
252b5132 RH |
368 | } |
369 | ||
370 | /* If the last instruction was the first of 2 16 bit insns, | |
371 | output a nop to move the PC to a 32 bit boundary. | |
372 | ||
373 | This is done via an alignment specification since branch relaxing | |
374 | may make it unnecessary. | |
375 | ||
376 | Internally, we need to output one of these each time a 32 bit insn is | |
377 | seen after an insn that is relaxable. */ | |
378 | ||
379 | static void | |
380 | fill_insn (ignore) | |
381 | int ignore; | |
382 | { | |
0a9ef439 | 383 | frag_align_code (2, 0); |
252b5132 RH |
384 | prev_insn.insn = NULL; |
385 | seen_relaxable_p = 0; | |
386 | } | |
387 | ||
388 | /* Record the symbol so that when we output the insn, we can create | |
389 | a symbol that is at the start of the instruction. This is used | |
390 | to emit the label for the start of a breakpoint without causing | |
391 | the assembler to emit a NOP if the previous instruction was a | |
392 | 16 bit instruction. */ | |
393 | ||
394 | static void | |
395 | debug_sym (ignore) | |
396 | int ignore; | |
397 | { | |
398 | register char *name; | |
399 | register char delim; | |
400 | register char *end_name; | |
401 | register symbolS *symbolP; | |
402 | register sym_linkS *link; | |
403 | ||
404 | name = input_line_pointer; | |
405 | delim = get_symbol_end (); | |
406 | end_name = input_line_pointer; | |
ab3e48dc | 407 | |
252b5132 RH |
408 | if ((symbolP = symbol_find (name)) == NULL |
409 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
410 | { | |
411 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
412 | } | |
413 | ||
414 | symbol_table_insert (symbolP); | |
415 | if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) | |
416 | /* xgettext:c-format */ | |
417 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
418 | ||
419 | else | |
420 | { | |
421 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
422 | link->symbol = symbolP; | |
423 | link->next = debug_sym_link; | |
424 | debug_sym_link = link; | |
f412ead8 | 425 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
426 | } |
427 | ||
428 | *end_name = delim; | |
429 | demand_empty_rest_of_line (); | |
430 | } | |
431 | ||
432 | /* Second pass to expanding the debug symbols, go through linked | |
433 | list of symbols and reassign the address. */ | |
434 | ||
435 | static void | |
436 | expand_debug_syms (syms, align) | |
437 | sym_linkS *syms; | |
438 | int align; | |
439 | { | |
440 | char *save_input_line = input_line_pointer; | |
441 | sym_linkS *next_syms; | |
442 | ||
443 | if (!syms) | |
444 | return; | |
445 | ||
446 | (void) m32r_do_align (align, NULL, 0, 0); | |
ab3e48dc | 447 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
252b5132 RH |
448 | { |
449 | symbolS *symbolP = syms->symbol; | |
450 | next_syms = syms->next; | |
451 | input_line_pointer = ".\n"; | |
452 | pseudo_set (symbolP); | |
ab3e48dc | 453 | free ((char *) syms); |
252b5132 RH |
454 | } |
455 | ||
456 | input_line_pointer = save_input_line; | |
457 | } | |
458 | ||
459 | /* Cover function to fill_insn called after a label and at end of assembly. | |
460 | The result is always 1: we're called in a conditional to see if the | |
461 | current line is a label. */ | |
462 | ||
463 | int | |
464 | m32r_fill_insn (done) | |
465 | int done; | |
466 | { | |
467 | if (prev_seg != NULL) | |
468 | { | |
ab3e48dc | 469 | segT seg = now_seg; |
252b5132 RH |
470 | subsegT subseg = now_subseg; |
471 | ||
472 | subseg_set (prev_seg, prev_subseg); | |
ab3e48dc | 473 | |
252b5132 RH |
474 | fill_insn (0); |
475 | ||
476 | subseg_set (seg, subseg); | |
477 | } | |
478 | ||
479 | if (done && debug_sym_link) | |
480 | { | |
481 | expand_debug_syms (debug_sym_link, 1); | |
ab3e48dc | 482 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
483 | } |
484 | ||
485 | return 1; | |
486 | } | |
487 | \f | |
488 | void | |
489 | md_begin () | |
490 | { | |
491 | flagword applicable; | |
ab3e48dc KH |
492 | segT seg; |
493 | subsegT subseg; | |
252b5132 RH |
494 | |
495 | /* Initialize the `cgen' interface. */ | |
ab3e48dc | 496 | |
252b5132 RH |
497 | /* Set the machine number and endian. */ |
498 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
499 | CGEN_CPU_OPEN_ENDIAN, | |
500 | CGEN_ENDIAN_BIG, | |
501 | CGEN_CPU_OPEN_END); | |
502 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
503 | ||
504 | /* The operand instance table is used during optimization to determine | |
505 | which insns can be executed in parallel. It is also used to give | |
506 | warnings regarding operand interference in parallel insns. */ | |
507 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
508 | ||
509 | /* This is a callback from cgen to gas to parse operands. */ | |
510 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
511 | ||
ab3e48dc KH |
512 | #if 0 |
513 | /* Not supported yet. */ | |
252b5132 RH |
514 | /* If a runtime cpu description file was provided, parse it. */ |
515 | if (m32r_cpu_desc != NULL) | |
516 | { | |
ab3e48dc | 517 | const char *errmsg; |
252b5132 RH |
518 | |
519 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); | |
520 | if (errmsg != NULL) | |
521 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
522 | } | |
523 | #endif | |
524 | ||
525 | /* Save the current subseg so we can restore it [it's the default one and | |
526 | we don't want the initial section to be .sbss]. */ | |
527 | seg = now_seg; | |
528 | subseg = now_subseg; | |
529 | ||
530 | /* The sbss section is for local .scomm symbols. */ | |
531 | sbss_section = subseg_new (".sbss", 0); | |
ab3e48dc | 532 | |
252b5132 RH |
533 | /* This is copied from perform_an_assembly_pass. */ |
534 | applicable = bfd_applicable_section_flags (stdoutput); | |
535 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ab3e48dc KH |
536 | |
537 | #if 0 | |
538 | /* What does this do? [see perform_an_assembly_pass] */ | |
252b5132 RH |
539 | seg_info (bss_section)->bss = 1; |
540 | #endif | |
541 | ||
542 | subseg_set (seg, subseg); | |
543 | ||
544 | /* We must construct a fake section similar to bfd_com_section | |
545 | but with the name .scommon. */ | |
546 | scom_section = bfd_com_section; | |
547 | scom_section.name = ".scommon"; | |
ab3e48dc KH |
548 | scom_section.output_section = &scom_section; |
549 | scom_section.symbol = &scom_symbol; | |
550 | scom_section.symbol_ptr_ptr = &scom_section.symbol; | |
551 | scom_symbol = *bfd_com_section.symbol; | |
252b5132 | 552 | scom_symbol.name = ".scommon"; |
ab3e48dc | 553 | scom_symbol.section = &scom_section; |
252b5132 | 554 | |
925c058e DE |
555 | allow_m32rx (enable_m32rx); |
556 | } | |
557 | ||
558 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ | |
559 | ((operand)->hw_type == HW_H_COND \ | |
560 | || ((operand)->hw_type == HW_H_PSW) \ | |
561 | || ((operand)->hw_type == HW_H_CR \ | |
562 | && (indices [index] == 0 || indices [index] == 1))) | |
563 | ||
564 | /* Returns true if an output of instruction 'a' is referenced by an operand | |
565 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
566 | checked, otherwise its inputs are examined. */ | |
567 | ||
568 | static int | |
569 | first_writes_to_seconds_operands (a, b, check_outputs) | |
ab3e48dc KH |
570 | m32r_insn *a; |
571 | m32r_insn *b; | |
572 | const int check_outputs; | |
925c058e | 573 | { |
ab3e48dc KH |
574 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
575 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); | |
925c058e DE |
576 | int a_index; |
577 | ||
578 | /* If at least one of the instructions takes no operands, then there is | |
579 | nothing to check. There really are instructions without operands, | |
580 | eg 'nop'. */ | |
581 | if (a_operands == NULL || b_ops == NULL) | |
582 | return 0; | |
ab3e48dc | 583 | |
925c058e DE |
584 | /* Scan the operand list of 'a' looking for an output operand. */ |
585 | for (a_index = 0; | |
586 | a_operands->type != CGEN_OPINST_END; | |
587 | a_index ++, a_operands ++) | |
588 | { | |
589 | if (a_operands->type == CGEN_OPINST_OUTPUT) | |
590 | { | |
591 | int b_index; | |
ab3e48dc | 592 | const CGEN_OPINST *b_operands = b_ops; |
925c058e DE |
593 | |
594 | /* Special Case: | |
595 | The Condition bit 'C' is a shadow of the CBR register (control | |
596 | register 1) and also a shadow of bit 31 of the program status | |
597 | word (control register 0). For now this is handled here, rather | |
ab3e48dc KH |
598 | than by cgen.... */ |
599 | ||
925c058e DE |
600 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
601 | { | |
602 | /* Scan operand list of 'b' looking for another reference to the | |
603 | condition bit, which goes in the right direction. */ | |
604 | for (b_index = 0; | |
605 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 606 | b_index++, b_operands++) |
925c058e DE |
607 | { |
608 | if ((b_operands->type | |
609 | == (check_outputs | |
610 | ? CGEN_OPINST_OUTPUT | |
611 | : CGEN_OPINST_INPUT)) | |
612 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
613 | return 1; | |
614 | } | |
615 | } | |
616 | else | |
617 | { | |
618 | /* Scan operand list of 'b' looking for an operand that | |
619 | references the same hardware element, and which goes in the | |
620 | right direction. */ | |
621 | for (b_index = 0; | |
622 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 623 | b_index++, b_operands++) |
925c058e DE |
624 | { |
625 | if ((b_operands->type | |
626 | == (check_outputs | |
627 | ? CGEN_OPINST_OUTPUT | |
628 | : CGEN_OPINST_INPUT)) | |
629 | && (b_operands->hw_type == a_operands->hw_type) | |
ab3e48dc | 630 | && (a->indices[a_index] == b->indices[b_index])) |
925c058e DE |
631 | return 1; |
632 | } | |
633 | } | |
634 | } | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | /* Returns true if the insn can (potentially) alter the program counter. */ | |
641 | ||
642 | static int | |
643 | writes_to_pc (a) | |
ab3e48dc | 644 | m32r_insn *a; |
925c058e | 645 | { |
ab3e48dc KH |
646 | #if 0 |
647 | /* Once PC operands are working.... */ | |
648 | const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, | |
649 | a->insn); | |
925c058e DE |
650 | |
651 | if (a_operands == NULL) | |
652 | return 0; | |
653 | ||
654 | while (a_operands->type != CGEN_OPINST_END) | |
655 | { | |
656 | if (a_operands->operand != NULL | |
ab3e48dc KH |
657 | && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, |
658 | a_operands->operand) == M32R_OPERAND_PC) | |
925c058e | 659 | return 1; |
ab3e48dc KH |
660 | |
661 | a_operands++; | |
925c058e DE |
662 | } |
663 | #else | |
664 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) | |
665 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) | |
666 | return 1; | |
667 | #endif | |
668 | return 0; | |
669 | } | |
670 | ||
ab3e48dc KH |
671 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
672 | Otherwise return a pointer to an error message explaining why not. */ | |
925c058e DE |
673 | |
674 | static const char * | |
675 | can_make_parallel (a, b) | |
ab3e48dc KH |
676 | m32r_insn *a; |
677 | m32r_insn *b; | |
925c058e DE |
678 | { |
679 | PIPE_ATTR a_pipe; | |
680 | PIPE_ATTR b_pipe; | |
ab3e48dc | 681 | |
925c058e | 682 | /* Make sure the instructions are the right length. */ |
ab3e48dc KH |
683 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
684 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) | |
685 | abort (); | |
925c058e DE |
686 | |
687 | if (first_writes_to_seconds_operands (a, b, true)) | |
688 | return _("Instructions write to the same destination register."); | |
ab3e48dc | 689 | |
925c058e DE |
690 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
691 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); | |
692 | ||
693 | /* Make sure that the instructions use the correct execution pipelines. */ | |
ab3e48dc | 694 | if (a_pipe == PIPE_NONE |
925c058e DE |
695 | || b_pipe == PIPE_NONE) |
696 | return _("Instructions do not use parallel execution pipelines."); | |
697 | ||
698 | /* Leave this test for last, since it is the only test that can | |
699 | go away if the instructions are swapped, and we want to make | |
700 | sure that any other errors are detected before this happens. */ | |
ab3e48dc | 701 | if (a_pipe == PIPE_S |
925c058e DE |
702 | || b_pipe == PIPE_O) |
703 | return _("Instructions share the same execution pipeline"); | |
ab3e48dc | 704 | |
925c058e DE |
705 | return NULL; |
706 | } | |
707 | ||
708 | /* Force the top bit of the second 16-bit insn to be set. */ | |
709 | ||
710 | static void | |
711 | make_parallel (buffer) | |
712 | CGEN_INSN_BYTES_PTR buffer; | |
713 | { | |
714 | #if CGEN_INT_INSN_P | |
715 | *buffer |= 0x8000; | |
716 | #else | |
ab3e48dc | 717 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
718 | |= 0x80; |
719 | #endif | |
252b5132 RH |
720 | } |
721 | ||
925c058e | 722 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
252b5132 | 723 | |
925c058e DE |
724 | static void |
725 | target_make_parallel (buffer) | |
726 | char *buffer; | |
727 | { | |
ab3e48dc | 728 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
729 | |= 0x80; |
730 | } | |
731 | ||
732 | /* Assemble two instructions with an explicit parallel operation (||) or | |
733 | sequential operation (->). */ | |
734 | ||
735 | static void | |
736 | assemble_two_insns (str, str2, parallel_p) | |
ab3e48dc KH |
737 | char *str; |
738 | char *str2; | |
739 | int parallel_p; | |
925c058e | 740 | { |
ab3e48dc | 741 | char *str3; |
925c058e DE |
742 | m32r_insn first; |
743 | m32r_insn second; | |
ab3e48dc KH |
744 | char *errmsg; |
745 | char save_str2 = *str2; | |
925c058e | 746 | |
ab3e48dc KH |
747 | /* Seperate the two instructions. */ |
748 | *str2 = 0; | |
925c058e DE |
749 | |
750 | /* Make sure the two insns begin on a 32 bit boundary. | |
751 | This is also done for the serial case (foo -> bar), relaxing doesn't | |
752 | affect insns written like this. | |
753 | Note that we must always do this as we can't assume anything about | |
754 | whether we're currently on a 32 bit boundary or not. Relaxing may | |
755 | change this. */ | |
756 | fill_insn (0); | |
757 | ||
758 | first.debug_sym_link = debug_sym_link; | |
ab3e48dc | 759 | debug_sym_link = (sym_linkS *) 0; |
925c058e DE |
760 | |
761 | /* Parse the first instruction. */ | |
762 | if (! (first.insn = m32r_cgen_assemble_insn | |
763 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) | |
764 | { | |
765 | as_bad (errmsg); | |
766 | return; | |
767 | } | |
768 | ||
769 | /* Check it. */ | |
770 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) | |
771 | { | |
ab3e48dc | 772 | /* xgettext:c-format */ |
925c058e DE |
773 | as_bad (_("not a 16 bit instruction '%s'"), str); |
774 | return; | |
775 | } | |
776 | else if (! enable_special | |
777 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
778 | { | |
ab3e48dc | 779 | /* xgettext:c-format */ |
925c058e DE |
780 | as_bad (_("unknown instruction '%s'"), str); |
781 | return; | |
782 | } | |
783 | else if (! enable_m32rx | |
ab3e48dc KH |
784 | /* FIXME: Need standard macro to perform this test. */ |
785 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
786 | == (1 << MACH_M32RX))) | |
925c058e | 787 | { |
ab3e48dc | 788 | /* xgettext:c-format */ |
925c058e DE |
789 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
790 | return; | |
791 | } | |
ab3e48dc | 792 | |
925c058e | 793 | /* Check to see if this is an allowable parallel insn. */ |
ab3e48dc KH |
794 | if (parallel_p |
795 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 796 | { |
ab3e48dc | 797 | /* xgettext:c-format */ |
925c058e DE |
798 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
799 | return; | |
800 | } | |
ab3e48dc KH |
801 | |
802 | /* Restore the original assembly text, just in case it is needed. */ | |
803 | *str2 = save_str2; | |
804 | ||
805 | /* Save the original string pointer. */ | |
806 | str3 = str; | |
807 | ||
808 | /* Advanced past the parsed string. */ | |
809 | str = str2 + 2; | |
810 | ||
811 | /* Remember the entire string in case it is needed for error | |
812 | messages. */ | |
813 | str2 = str3; | |
925c058e DE |
814 | |
815 | /* Convert the opcode to lower case. */ | |
816 | { | |
817 | char *s2 = str; | |
ab3e48dc KH |
818 | |
819 | while (isspace (*s2++)) | |
925c058e DE |
820 | continue; |
821 | ||
822 | --s2; | |
823 | ||
824 | while (isalnum (*s2)) | |
825 | { | |
826 | if (isupper ((unsigned char) *s2)) | |
827 | *s2 = tolower (*s2); | |
ab3e48dc | 828 | s2++; |
925c058e DE |
829 | } |
830 | } | |
ab3e48dc KH |
831 | |
832 | /* Preserve any fixups that have been generated and reset the list | |
833 | to empty. */ | |
925c058e DE |
834 | gas_cgen_save_fixups (); |
835 | ||
836 | /* Get the indices of the operands of the instruction. */ | |
837 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
838 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
839 | /* FIXME: ALIAS insns do not have operands, so we use this function | |
840 | to find the equivalent insn and overwrite the value stored in our | |
841 | structure. We still need the original insn, however, since this | |
842 | may have certain attributes that are not present in the unaliased | |
843 | version (eg relaxability). When aliases behave differently this | |
844 | may have to change. */ | |
845 | first.orig_insn = first.insn; | |
846 | { | |
847 | CGEN_FIELDS tmp_fields; | |
848 | first.insn = cgen_lookup_get_insn_operands | |
849 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, | |
850 | first.indices, &tmp_fields); | |
851 | } | |
ab3e48dc | 852 | |
925c058e DE |
853 | if (first.insn == NULL) |
854 | as_fatal (_("internal error: lookup/get operands failed")); | |
855 | ||
856 | second.debug_sym_link = NULL; | |
857 | ||
858 | /* Parse the second instruction. */ | |
859 | if (! (second.insn = m32r_cgen_assemble_insn | |
860 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) | |
861 | { | |
862 | as_bad (errmsg); | |
863 | return; | |
864 | } | |
865 | ||
866 | /* Check it. */ | |
867 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) | |
868 | { | |
ab3e48dc | 869 | /* xgettext:c-format */ |
925c058e DE |
870 | as_bad (_("not a 16 bit instruction '%s'"), str); |
871 | return; | |
872 | } | |
873 | else if (! enable_special | |
874 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
875 | { | |
ab3e48dc | 876 | /* xgettext:c-format */ |
925c058e DE |
877 | as_bad (_("unknown instruction '%s'"), str); |
878 | return; | |
879 | } | |
880 | else if (! enable_m32rx | |
881 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
882 | { | |
ab3e48dc | 883 | /* xgettext:c-format */ |
925c058e DE |
884 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
885 | return; | |
886 | } | |
887 | ||
888 | /* Check to see if this is an allowable parallel insn. */ | |
ab3e48dc KH |
889 | if (parallel_p |
890 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 891 | { |
ab3e48dc | 892 | /* xgettext:c-format */ |
925c058e DE |
893 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
894 | return; | |
895 | } | |
ab3e48dc | 896 | |
925c058e DE |
897 | if (parallel_p && ! enable_m32rx) |
898 | { | |
899 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP | |
900 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
901 | { | |
ab3e48dc | 902 | /* xgettext:c-format */ |
925c058e DE |
903 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
904 | return; | |
905 | } | |
906 | } | |
907 | ||
908 | /* Get the indices of the operands of the instruction. */ | |
909 | second.orig_insn = second.insn; | |
910 | { | |
911 | CGEN_FIELDS tmp_fields; | |
912 | second.insn = cgen_lookup_get_insn_operands | |
913 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, | |
914 | second.indices, &tmp_fields); | |
915 | } | |
ab3e48dc | 916 | |
925c058e DE |
917 | if (second.insn == NULL) |
918 | as_fatal (_("internal error: lookup/get operands failed")); | |
919 | ||
920 | /* We assume that if the first instruction writes to a register that is | |
921 | read by the second instruction it is because the programmer intended | |
922 | this to happen, (after all they have explicitly requested that these | |
923 | two instructions be executed in parallel). Although if the global | |
924 | variable warn_explicit_parallel_conflicts is true then we do generate | |
925 | a warning message. Similarly we assume that parallel branch and jump | |
926 | instructions are deliberate and should not produce errors. */ | |
ab3e48dc | 927 | |
925c058e DE |
928 | if (parallel_p && warn_explicit_parallel_conflicts) |
929 | { | |
ab3e48dc KH |
930 | if (first_writes_to_seconds_operands (&first, &second, false)) |
931 | /* xgettext:c-format */ | |
925c058e | 932 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
ab3e48dc KH |
933 | |
934 | if (first_writes_to_seconds_operands (&second, &first, false)) | |
935 | /* xgettext:c-format */ | |
925c058e DE |
936 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
937 | } | |
ab3e48dc | 938 | |
925c058e | 939 | if (!parallel_p |
ab3e48dc | 940 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
925c058e DE |
941 | { |
942 | /* Get the fixups for the first instruction. */ | |
943 | gas_cgen_swap_fixups (); | |
944 | ||
945 | /* Write it out. */ | |
946 | expand_debug_syms (first.debug_sym_link, 1); | |
947 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc KH |
948 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
949 | ||
925c058e DE |
950 | /* Force the top bit of the second insn to be set. */ |
951 | if (parallel_p) | |
952 | make_parallel (second.buffer); | |
953 | ||
954 | /* Get its fixups. */ | |
955 | gas_cgen_restore_fixups (); | |
956 | ||
957 | /* Write it out. */ | |
958 | expand_debug_syms (second.debug_sym_link, 1); | |
959 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc | 960 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
925c058e DE |
961 | } |
962 | /* Try swapping the instructions to see if they work that way. */ | |
ab3e48dc | 963 | else if (can_make_parallel (&second, &first) == NULL) |
925c058e DE |
964 | { |
965 | /* Write out the second instruction first. */ | |
966 | expand_debug_syms (second.debug_sym_link, 1); | |
967 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc KH |
968 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
969 | ||
925c058e DE |
970 | /* Force the top bit of the first instruction to be set. */ |
971 | make_parallel (first.buffer); | |
972 | ||
973 | /* Get the fixups for the first instruction. */ | |
974 | gas_cgen_restore_fixups (); | |
975 | ||
976 | /* Write out the first instruction. */ | |
977 | expand_debug_syms (first.debug_sym_link, 1); | |
978 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc | 979 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
925c058e DE |
980 | } |
981 | else | |
982 | { | |
983 | as_bad ("'%s': %s", str2, errmsg); | |
984 | return; | |
985 | } | |
ab3e48dc | 986 | |
925c058e DE |
987 | /* Set these so m32r_fill_insn can use them. */ |
988 | prev_seg = now_seg; | |
989 | prev_subseg = now_subseg; | |
990 | } | |
252b5132 RH |
991 | |
992 | void | |
993 | md_assemble (str) | |
ab3e48dc | 994 | char *str; |
252b5132 RH |
995 | { |
996 | m32r_insn insn; | |
ab3e48dc KH |
997 | char *errmsg; |
998 | char *str2 = NULL; | |
252b5132 RH |
999 | |
1000 | /* Initialize GAS's cgen interface for a new instruction. */ | |
1001 | gas_cgen_init_parse (); | |
1002 | ||
925c058e DE |
1003 | /* Look for a parallel instruction seperator. */ |
1004 | if ((str2 = strstr (str, "||")) != NULL) | |
1005 | { | |
1006 | assemble_two_insns (str, str2, 1); | |
1007 | return; | |
1008 | } | |
1009 | ||
1010 | /* Also look for a sequential instruction seperator. */ | |
1011 | if ((str2 = strstr (str, "->")) != NULL) | |
1012 | { | |
1013 | assemble_two_insns (str, str2, 0); | |
1014 | return; | |
1015 | } | |
ab3e48dc | 1016 | |
252b5132 | 1017 | insn.debug_sym_link = debug_sym_link; |
ab3e48dc | 1018 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
1019 | |
1020 | insn.insn = m32r_cgen_assemble_insn | |
ab3e48dc KH |
1021 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
1022 | ||
252b5132 RH |
1023 | if (!insn.insn) |
1024 | { | |
1025 | as_bad (errmsg); | |
1026 | return; | |
1027 | } | |
1028 | ||
925c058e DE |
1029 | if (! enable_special |
1030 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
1031 | { | |
ab3e48dc | 1032 | /* xgettext:c-format */ |
925c058e DE |
1033 | as_bad (_("unknown instruction '%s'"), str); |
1034 | return; | |
1035 | } | |
1036 | else if (! enable_m32rx | |
1037 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1038 | { | |
ab3e48dc | 1039 | /* xgettext:c-format */ |
925c058e DE |
1040 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1041 | return; | |
1042 | } | |
ab3e48dc | 1043 | |
252b5132 RH |
1044 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
1045 | { | |
1046 | /* 32 bit insns must live on 32 bit boundaries. */ | |
1047 | if (prev_insn.insn || seen_relaxable_p) | |
1048 | { | |
1049 | /* ??? If calling fill_insn too many times turns us into a memory | |
1050 | pig, can we call a fn to assemble a nop instead of | |
1051 | !seen_relaxable_p? */ | |
1052 | fill_insn (0); | |
1053 | } | |
1054 | ||
1055 | expand_debug_syms (insn.debug_sym_link, 2); | |
1056 | ||
1057 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
1058 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
ab3e48dc | 1059 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
252b5132 RH |
1060 | } |
1061 | else | |
1062 | { | |
1063 | int on_32bit_boundary_p; | |
925c058e | 1064 | int swap = false; |
252b5132 RH |
1065 | |
1066 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
ab3e48dc | 1067 | abort (); |
252b5132 RH |
1068 | |
1069 | insn.orig_insn = insn.insn; | |
1070 | ||
925c058e DE |
1071 | /* If the previous insn was relaxable, then it may be expanded |
1072 | to fill the current 16 bit slot. Emit a NOP here to occupy | |
1073 | this slot, so that we can start at optimizing at a 32 bit | |
1074 | boundary. */ | |
1075 | if (prev_insn.insn && seen_relaxable_p && optimize) | |
1076 | fill_insn (0); | |
ab3e48dc | 1077 | |
925c058e DE |
1078 | if (enable_m32rx) |
1079 | { | |
1080 | /* Get the indices of the operands of the instruction. | |
1081 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
1082 | { | |
1083 | CGEN_FIELDS tmp_fields; | |
1084 | insn.insn = cgen_lookup_get_insn_operands | |
1085 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, | |
1086 | 16, insn.indices, &tmp_fields); | |
1087 | } | |
ab3e48dc | 1088 | |
925c058e DE |
1089 | if (insn.insn == NULL) |
1090 | as_fatal (_("internal error: lookup/get operands failed")); | |
1091 | } | |
1092 | ||
252b5132 RH |
1093 | /* Compute whether we're on a 32 bit boundary or not. |
1094 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1095 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
1096 | ||
925c058e DE |
1097 | /* Look to see if this instruction can be combined with the |
1098 | previous instruction to make one, parallel, 32 bit instruction. | |
1099 | If the previous instruction (potentially) changed the flow of | |
1100 | program control, then it cannot be combined with the current | |
1101 | instruction. If the current instruction is relaxable, then it | |
1102 | might be replaced with a longer version, so we cannot combine it. | |
1103 | Also if the output of the previous instruction is used as an | |
1104 | input to the current instruction then it cannot be combined. | |
1105 | Otherwise call can_make_parallel() with both orderings of the | |
1106 | instructions to see if they can be combined. */ | |
ab3e48dc KH |
1107 | if (! on_32bit_boundary_p |
1108 | && enable_m32rx | |
1109 | && optimize | |
1110 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 | |
1111 | && ! writes_to_pc (&prev_insn) | |
1112 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, false)) | |
925c058e | 1113 | { |
ab3e48dc | 1114 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
925c058e | 1115 | make_parallel (insn.buffer); |
ab3e48dc | 1116 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
925c058e DE |
1117 | swap = true; |
1118 | } | |
252b5132 RH |
1119 | |
1120 | expand_debug_syms (insn.debug_sym_link, 1); | |
1121 | ||
1122 | { | |
1123 | int i; | |
1124 | finished_insnS fi; | |
1125 | ||
1126 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1127 | frag_grow (4); | |
1128 | ||
1129 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
ab3e48dc KH |
1130 | CGEN_FIELDS_BITSIZE (&insn.fields), |
1131 | 1 /* relax_p */, &fi); | |
252b5132 RH |
1132 | insn.addr = fi.addr; |
1133 | insn.frag = fi.frag; | |
1134 | insn.num_fixups = fi.num_fixups; | |
1135 | for (i = 0; i < fi.num_fixups; ++i) | |
1136 | insn.fixups[i] = fi.fixups[i]; | |
1137 | } | |
1138 | ||
925c058e DE |
1139 | if (swap) |
1140 | { | |
ab3e48dc | 1141 | int i, tmp; |
925c058e DE |
1142 | |
1143 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
1144 | ||
1145 | /* Swap the two insns */ | |
ab3e48dc KH |
1146 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
1147 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); | |
925c058e DE |
1148 | |
1149 | target_make_parallel (insn.addr); | |
1150 | ||
1151 | /* Swap any relaxable frags recorded for the two insns. */ | |
1152 | /* FIXME: Clarify. relaxation precludes parallel insns */ | |
1153 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
1154 | prev_insn.frag->fr_opcode = insn.addr; | |
1155 | else if (insn.frag->fr_opcode == insn.addr) | |
1156 | insn.frag->fr_opcode = prev_insn.addr; | |
1157 | ||
1158 | /* Update the addresses in any fixups. | |
1159 | Note that we don't have to handle the case where each insn is in | |
1160 | a different frag as we ensure they're in the same frag above. */ | |
1161 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1162 | prev_insn.fixups[i]->fx_where += 2; | |
1163 | for (i = 0; i < insn.num_fixups; ++i) | |
1164 | insn.fixups[i]->fx_where -= 2; | |
1165 | } | |
252b5132 RH |
1166 | |
1167 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1168 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1169 | if (on_32bit_boundary_p) | |
1170 | prev_insn = insn; | |
1171 | else | |
1172 | prev_insn.insn = NULL; | |
ab3e48dc | 1173 | |
252b5132 RH |
1174 | /* If the insn needs the following one to be on a 32 bit boundary |
1175 | (e.g. subroutine calls), fill this insn's slot. */ | |
1176 | if (on_32bit_boundary_p | |
1177 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
1178 | fill_insn (0); | |
1179 | ||
1180 | /* If this is a relaxable insn (can be replaced with a larger version) | |
1181 | mark the fact so that we can emit an alignment directive for a | |
1182 | following 32 bit insn if we see one. */ | |
1183 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
1184 | seen_relaxable_p = 1; | |
1185 | } | |
1186 | ||
1187 | /* Set these so m32r_fill_insn can use them. */ | |
1188 | prev_seg = now_seg; | |
1189 | prev_subseg = now_subseg; | |
1190 | } | |
1191 | ||
1192 | /* The syntax in the manual says constants begin with '#'. | |
1193 | We just ignore it. */ | |
1194 | ||
ab3e48dc | 1195 | void |
252b5132 | 1196 | md_operand (expressionP) |
ab3e48dc | 1197 | expressionS *expressionP; |
252b5132 | 1198 | { |
ab3e48dc | 1199 | if (*input_line_pointer == '#') |
252b5132 | 1200 | { |
ab3e48dc | 1201 | input_line_pointer++; |
252b5132 RH |
1202 | expression (expressionP); |
1203 | } | |
1204 | } | |
1205 | ||
1206 | valueT | |
1207 | md_section_align (segment, size) | |
ab3e48dc | 1208 | segT segment; |
252b5132 RH |
1209 | valueT size; |
1210 | { | |
1211 | int align = bfd_get_section_alignment (stdoutput, segment); | |
1212 | return ((size + (1 << align) - 1) & (-1 << align)); | |
1213 | } | |
1214 | ||
1215 | symbolS * | |
1216 | md_undefined_symbol (name) | |
ab3e48dc | 1217 | char *name; |
252b5132 RH |
1218 | { |
1219 | return 0; | |
1220 | } | |
1221 | \f | |
1222 | /* .scomm pseudo-op handler. | |
1223 | ||
1224 | This is a new pseudo-op to handle putting objects in .scommon. | |
ab3e48dc KH |
1225 | By doing this the linker won't need to do any work, |
1226 | and more importantly it removes the implicit -G arg necessary to | |
1227 | correctly link the object file. */ | |
252b5132 RH |
1228 | |
1229 | static void | |
1230 | m32r_scomm (ignore) | |
1231 | int ignore; | |
1232 | { | |
ab3e48dc KH |
1233 | register char *name; |
1234 | register char c; | |
1235 | register char *p; | |
1236 | offsetT size; | |
1237 | register symbolS *symbolP; | |
1238 | offsetT align; | |
1239 | int align2; | |
252b5132 RH |
1240 | |
1241 | name = input_line_pointer; | |
1242 | c = get_symbol_end (); | |
1243 | ||
ab3e48dc | 1244 | /* Just after name is now '\0'. */ |
252b5132 | 1245 | p = input_line_pointer; |
ab3e48dc | 1246 | *p = c; |
252b5132 | 1247 | SKIP_WHITESPACE (); |
ab3e48dc | 1248 | if (*input_line_pointer != ',') |
252b5132 RH |
1249 | { |
1250 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
1251 | ignore_rest_of_line (); | |
1252 | return; | |
1253 | } | |
1254 | ||
ab3e48dc KH |
1255 | /* Skip ','. */ |
1256 | input_line_pointer++; | |
252b5132 RH |
1257 | if ((size = get_absolute_expression ()) < 0) |
1258 | { | |
ab3e48dc | 1259 | /* xgettext:c-format */ |
252b5132 RH |
1260 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
1261 | ignore_rest_of_line (); | |
1262 | return; | |
1263 | } | |
1264 | ||
1265 | /* The third argument to .scomm is the alignment. */ | |
ab3e48dc | 1266 | if (*input_line_pointer != ',') |
252b5132 RH |
1267 | align = 8; |
1268 | else | |
1269 | { | |
ab3e48dc | 1270 | ++input_line_pointer; |
252b5132 RH |
1271 | align = get_absolute_expression (); |
1272 | if (align <= 0) | |
1273 | { | |
1274 | as_warn (_("ignoring bad alignment")); | |
1275 | align = 8; | |
1276 | } | |
1277 | } | |
ab3e48dc | 1278 | |
252b5132 RH |
1279 | /* Convert to a power of 2 alignment. */ |
1280 | if (align) | |
1281 | { | |
ab3e48dc | 1282 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
252b5132 RH |
1283 | continue; |
1284 | if (align != 1) | |
1285 | { | |
1286 | as_bad (_("Common alignment not a power of 2")); | |
1287 | ignore_rest_of_line (); | |
1288 | return; | |
1289 | } | |
1290 | } | |
1291 | else | |
1292 | align2 = 0; | |
1293 | ||
ab3e48dc | 1294 | *p = 0; |
252b5132 | 1295 | symbolP = symbol_find_or_make (name); |
ab3e48dc | 1296 | *p = c; |
252b5132 RH |
1297 | |
1298 | if (S_IS_DEFINED (symbolP)) | |
1299 | { | |
ab3e48dc | 1300 | /* xgettext:c-format */ |
252b5132 RH |
1301 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
1302 | S_GET_NAME (symbolP)); | |
1303 | ignore_rest_of_line (); | |
1304 | return; | |
1305 | } | |
1306 | ||
1307 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1308 | { | |
ab3e48dc | 1309 | /* xgettext:c-format */ |
252b5132 RH |
1310 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
1311 | S_GET_NAME (symbolP), | |
1312 | (long) S_GET_VALUE (symbolP), | |
1313 | (long) size); | |
1314 | ||
1315 | ignore_rest_of_line (); | |
1316 | return; | |
1317 | } | |
1318 | ||
f412ead8 | 1319 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 1320 | { |
ab3e48dc KH |
1321 | segT old_sec = now_seg; |
1322 | int old_subsec = now_subseg; | |
1323 | char *pfrag; | |
252b5132 RH |
1324 | |
1325 | record_alignment (sbss_section, align2); | |
1326 | subseg_set (sbss_section, 0); | |
ab3e48dc | 1327 | |
252b5132 RH |
1328 | if (align2) |
1329 | frag_align (align2, 0, 0); | |
ab3e48dc | 1330 | |
252b5132 | 1331 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
f412ead8 | 1332 | symbol_get_frag (symbolP)->fr_symbol = 0; |
ab3e48dc | 1333 | |
f412ead8 | 1334 | symbol_set_frag (symbolP, frag_now); |
ab3e48dc | 1335 | |
252b5132 RH |
1336 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1337 | (char *) 0); | |
ab3e48dc | 1338 | *pfrag = 0; |
252b5132 RH |
1339 | S_SET_SIZE (symbolP, size); |
1340 | S_SET_SEGMENT (symbolP, sbss_section); | |
1341 | S_CLEAR_EXTERNAL (symbolP); | |
1342 | subseg_set (old_sec, old_subsec); | |
1343 | } | |
1344 | else | |
1345 | { | |
1346 | S_SET_VALUE (symbolP, (valueT) size); | |
1347 | S_SET_ALIGN (symbolP, align2); | |
1348 | S_SET_EXTERNAL (symbolP); | |
ab3e48dc | 1349 | S_SET_SEGMENT (symbolP, &scom_section); |
252b5132 RH |
1350 | } |
1351 | ||
1352 | demand_empty_rest_of_line (); | |
1353 | } | |
1354 | \f | |
1355 | /* Interface to relax_segment. */ | |
1356 | ||
1357 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1358 | ||
1359 | const relax_typeS md_relax_table[] = | |
1360 | { | |
1361 | /* The fields are: | |
1362 | 1) most positive reach of this state, | |
1363 | 2) most negative reach of this state, | |
1364 | 3) how many bytes this mode will add to the size of the current frag | |
1365 | 4) which index into the table to try if we can't fit into this one. */ | |
1366 | ||
1367 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1368 | each list. */ | |
1369 | {1, 1, 0, 0}, | |
1370 | ||
1371 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1372 | so we subtract 2 from the following. */ | |
1373 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1374 | This doesn't handle a branch in the right slot at the border: | |
1375 | the "& -4" isn't taken into account. It's not important enough to | |
1376 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1377 | case). */ | |
1378 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1379 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1380 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1381 | /* Same thing, but with leading nop for alignment. */ | |
1382 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1383 | }; | |
1384 | ||
1385 | long | |
1386 | m32r_relax_frag (fragP, stretch) | |
ab3e48dc KH |
1387 | fragS *fragP; |
1388 | long stretch; | |
252b5132 RH |
1389 | { |
1390 | /* Address of branch insn. */ | |
1391 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1392 | long growth = 0; | |
1393 | ||
1394 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1395 | if (fragP->fr_subtype == 2) | |
1396 | { | |
1397 | if ((address & 3) != 0) | |
1398 | { | |
1399 | fragP->fr_subtype = 3; | |
1400 | growth = 2; | |
1401 | } | |
1402 | } | |
1403 | else if (fragP->fr_subtype == 3) | |
1404 | { | |
1405 | if ((address & 3) == 0) | |
1406 | { | |
1407 | fragP->fr_subtype = 2; | |
1408 | growth = -2; | |
1409 | } | |
1410 | } | |
1411 | else | |
1412 | { | |
1413 | growth = relax_frag (fragP, stretch); | |
1414 | ||
1415 | /* Long jump on odd halfword boundary? */ | |
1416 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1417 | { | |
1418 | fragP->fr_subtype = 3; | |
1419 | growth += 2; | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | return growth; | |
1424 | } | |
1425 | ||
1426 | /* Return an initial guess of the length by which a fragment must grow to | |
1427 | hold a branch to reach its destination. | |
1428 | Also updates fr_type/fr_subtype as necessary. | |
1429 | ||
1430 | Called just before doing relaxation. | |
1431 | Any symbol that is now undefined will not become defined. | |
1432 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1433 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
ab3e48dc KH |
1434 | Although it may not be explicit in the frag, pretend fr_var starts |
1435 | with a 0 value. */ | |
252b5132 RH |
1436 | |
1437 | int | |
1438 | md_estimate_size_before_relax (fragP, segment) | |
ab3e48dc KH |
1439 | fragS *fragP; |
1440 | segT segment; | |
252b5132 | 1441 | { |
ab3e48dc | 1442 | int old_fr_fix = fragP->fr_fix; |
252b5132 RH |
1443 | |
1444 | /* The only thing we have to handle here are symbols outside of the | |
1445 | current segment. They may be undefined or in a different segment in | |
1446 | which case linker scripts may place them anywhere. | |
1447 | However, we can't finish the fragment here and emit the reloc as insn | |
1448 | alignment requirements may move the insn about. */ | |
1449 | ||
1450 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1451 | { | |
1452 | /* The symbol is undefined in this segment. | |
1453 | Change the relaxation subtype to the max allowable and leave | |
1454 | all further handling to md_convert_frag. */ | |
1455 | fragP->fr_subtype = 2; | |
1456 | ||
ab3e48dc KH |
1457 | #if 0 |
1458 | /* Can't use this, but leave in for illustration. */ | |
252b5132 RH |
1459 | /* Change 16 bit insn to 32 bit insn. */ |
1460 | fragP->fr_opcode[0] |= 0x80; | |
1461 | ||
1462 | /* Increase known (fixed) size of fragment. */ | |
1463 | fragP->fr_fix += 2; | |
1464 | ||
1465 | /* Create a relocation for it. */ | |
1466 | fix_new (fragP, old_fr_fix, 4, | |
1467 | fragP->fr_symbol, | |
ab3e48dc | 1468 | fragP->fr_offset, 1 /* pcrel */, |
252b5132 RH |
1469 | /* FIXME: Can't use a real BFD reloc here. |
1470 | gas_cgen_md_apply_fix3 can't handle it. */ | |
1471 | BFD_RELOC_M32R_26_PCREL); | |
1472 | ||
1473 | /* Mark this fragment as finished. */ | |
1474 | frag_wane (fragP); | |
1475 | #else | |
1476 | { | |
ab3e48dc KH |
1477 | const CGEN_INSN *insn; |
1478 | int i; | |
252b5132 RH |
1479 | |
1480 | /* Update the recorded insn. | |
1481 | Fortunately we don't have to look very far. | |
1482 | FIXME: Change this to record in the instruction the next higher | |
1483 | relaxable insn to use. */ | |
1484 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1485 | { | |
1486 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
1487 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
1488 | == 0) | |
1489 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX)) | |
1490 | break; | |
1491 | } | |
1492 | if (i == 4) | |
1493 | abort (); | |
1494 | ||
1495 | fragP->fr_cgen.insn = insn; | |
1496 | return 2; | |
1497 | } | |
1498 | #endif | |
1499 | } | |
1500 | ||
1501 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
ab3e48dc | 1502 | } |
252b5132 | 1503 | |
ab3e48dc | 1504 | /* *FRAGP has been relaxed to its final size, and now needs to have |
252b5132 RH |
1505 | the bytes inside it modified to conform to the new size. |
1506 | ||
1507 | Called after relaxation is finished. | |
1508 | fragP->fr_type == rs_machine_dependent. | |
1509 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1510 | ||
1511 | void | |
1512 | md_convert_frag (abfd, sec, fragP) | |
ab3e48dc KH |
1513 | bfd *abfd; |
1514 | segT sec; | |
1515 | fragS *fragP; | |
252b5132 | 1516 | { |
ab3e48dc KH |
1517 | char *opcode; |
1518 | char *displacement; | |
1519 | int target_address; | |
1520 | int opcode_address; | |
1521 | int extension; | |
1522 | int addend; | |
252b5132 RH |
1523 | |
1524 | opcode = fragP->fr_opcode; | |
1525 | ||
1526 | /* Address opcode resides at in file space. */ | |
1527 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1528 | ||
1529 | switch (fragP->fr_subtype) | |
1530 | { | |
ab3e48dc | 1531 | case 1: |
252b5132 | 1532 | extension = 0; |
ab3e48dc | 1533 | displacement = &opcode[1]; |
252b5132 | 1534 | break; |
ab3e48dc | 1535 | case 2: |
252b5132 RH |
1536 | opcode[0] |= 0x80; |
1537 | extension = 2; | |
ab3e48dc | 1538 | displacement = &opcode[1]; |
252b5132 | 1539 | break; |
ab3e48dc | 1540 | case 3: |
252b5132 RH |
1541 | opcode[2] = opcode[0] | 0x80; |
1542 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1543 | opcode_address += 2; | |
1544 | extension = 4; | |
ab3e48dc | 1545 | displacement = &opcode[3]; |
252b5132 | 1546 | break; |
ab3e48dc | 1547 | default: |
252b5132 RH |
1548 | abort (); |
1549 | } | |
1550 | ||
1551 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1552 | { | |
ab3e48dc | 1553 | /* Symbol must be resolved by linker. */ |
252b5132 RH |
1554 | if (fragP->fr_offset & 3) |
1555 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
1556 | addend = fragP->fr_offset >> 2; | |
1557 | } | |
1558 | else | |
1559 | { | |
1560 | /* Address we want to reach in file space. */ | |
1561 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
f412ead8 | 1562 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
1563 | addend = (target_address - (opcode_address & -4)) >> 2; |
1564 | } | |
1565 | ||
1566 | /* Create a relocation for symbols that must be resolved by the linker. | |
1567 | Otherwise output the completed insn. */ | |
1568 | ||
1569 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1570 | { | |
1571 | assert (fragP->fr_subtype != 1); | |
1572 | assert (fragP->fr_cgen.insn != 0); | |
1573 | gas_cgen_record_fixup (fragP, | |
1574 | /* Offset of branch insn in frag. */ | |
1575 | fragP->fr_fix + extension - 4, | |
1576 | fragP->fr_cgen.insn, | |
ab3e48dc KH |
1577 | 4 /* Length. */, |
1578 | /* FIXME: quick hack. */ | |
252b5132 RH |
1579 | #if 0 |
1580 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
1581 | fragP->fr_cgen.opindex), | |
1582 | #else | |
1583 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
1584 | M32R_OPERAND_DISP24), | |
1585 | #endif | |
1586 | fragP->fr_cgen.opinfo, | |
1587 | fragP->fr_symbol, fragP->fr_offset); | |
1588 | } | |
1589 | ||
1590 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1591 | ||
1592 | md_number_to_chars (displacement, (valueT) addend, | |
1593 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1594 | ||
1595 | fragP->fr_fix += extension; | |
1596 | } | |
1597 | \f | |
1598 | /* Functions concerning relocs. */ | |
1599 | ||
1600 | /* The location from which a PC relative jump should be calculated, | |
1601 | given a PC relative reloc. */ | |
1602 | ||
1603 | long | |
1604 | md_pcrel_from_section (fixP, sec) | |
ab3e48dc KH |
1605 | fixS *fixP; |
1606 | segT sec; | |
252b5132 RH |
1607 | { |
1608 | if (fixP->fx_addsy != (symbolS *) NULL | |
1609 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1610 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1611 | { | |
1612 | /* The symbol is undefined (or is defined but not in this section). | |
1613 | Let the linker figure it out. */ | |
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1618 | } | |
1619 | ||
1620 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1621 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1622 | *FIXP may be modified if desired. */ | |
1623 | ||
1624 | bfd_reloc_code_real_type | |
1625 | md_cgen_lookup_reloc (insn, operand, fixP) | |
ab3e48dc KH |
1626 | const CGEN_INSN *insn; |
1627 | const CGEN_OPERAND *operand; | |
1628 | fixS *fixP; | |
252b5132 RH |
1629 | { |
1630 | switch (operand->type) | |
1631 | { | |
ab3e48dc KH |
1632 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
1633 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; | |
1634 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; | |
1635 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; | |
1636 | case M32R_OPERAND_HI16: | |
1637 | case M32R_OPERAND_SLO16: | |
1638 | case M32R_OPERAND_ULO16: | |
252b5132 RH |
1639 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1640 | if (fixP->fx_cgen.opinfo != 0) | |
1641 | return fixP->fx_cgen.opinfo; | |
1642 | break; | |
ab3e48dc KH |
1643 | default: |
1644 | /* Avoid -Wall warning. */ | |
252b5132 RH |
1645 | break; |
1646 | } | |
1647 | return BFD_RELOC_NONE; | |
1648 | } | |
1649 | ||
1650 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
1651 | ||
1652 | static void | |
1653 | m32r_record_hi16 (reloc_type, fixP, seg) | |
ab3e48dc KH |
1654 | int reloc_type; |
1655 | fixS *fixP; | |
1656 | segT seg; | |
252b5132 | 1657 | { |
ab3e48dc | 1658 | struct m32r_hi_fixup *hi_fixup; |
252b5132 RH |
1659 | |
1660 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1661 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1662 | ||
1663 | hi_fixup = ((struct m32r_hi_fixup *) | |
1664 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1665 | hi_fixup->fixp = fixP; | |
1666 | hi_fixup->seg = now_seg; | |
1667 | hi_fixup->next = m32r_hi_fixup_list; | |
ab3e48dc | 1668 | |
252b5132 RH |
1669 | m32r_hi_fixup_list = hi_fixup; |
1670 | } | |
1671 | ||
1672 | /* Called while parsing an instruction to create a fixup. | |
1673 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1674 | ||
1675 | fixS * | |
1676 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ab3e48dc KH |
1677 | fragS *frag; |
1678 | int where; | |
1679 | const CGEN_INSN *insn; | |
1680 | int length; | |
1681 | const CGEN_OPERAND *operand; | |
1682 | int opinfo; | |
1683 | expressionS *exp; | |
252b5132 | 1684 | { |
ab3e48dc KH |
1685 | fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, |
1686 | operand, opinfo, exp); | |
252b5132 RH |
1687 | |
1688 | switch (operand->type) | |
1689 | { | |
ab3e48dc | 1690 | case M32R_OPERAND_HI16: |
252b5132 RH |
1691 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1692 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1693 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1694 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
1695 | break; | |
ab3e48dc KH |
1696 | default: |
1697 | /* Avoid -Wall warning */ | |
252b5132 RH |
1698 | break; |
1699 | } | |
1700 | ||
1701 | return fixP; | |
1702 | } | |
1703 | ||
1704 | /* Return BFD reloc type from opinfo field in a fixS. | |
1705 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1706 | are BFD_RELOC_UNUSED + operand number. */ | |
1707 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
1708 | ||
1709 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1710 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1711 | tc_gen_reloc. */ | |
1712 | ||
1713 | void | |
1714 | m32r_frob_file () | |
1715 | { | |
ab3e48dc | 1716 | struct m32r_hi_fixup *l; |
252b5132 RH |
1717 | |
1718 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1719 | { | |
ab3e48dc KH |
1720 | segment_info_type *seginfo; |
1721 | int pass; | |
252b5132 RH |
1722 | |
1723 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1724 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1725 | ||
1726 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1727 | if (l->fixp->fx_next != NULL | |
1728 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1729 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1730 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1731 | continue; | |
1732 | ||
1733 | /* Look through the fixups for this segment for a matching `low'. | |
1734 | When we find one, move the high/shigh just in front of it. We do | |
1735 | this in two passes. In the first pass, we try to find a | |
1736 | unique `low'. In the second pass, we permit multiple high's | |
1737 | relocs for a single `low'. */ | |
1738 | seginfo = seg_info (l->seg); | |
1739 | for (pass = 0; pass < 2; pass++) | |
1740 | { | |
ab3e48dc KH |
1741 | fixS *f; |
1742 | fixS *prev; | |
252b5132 RH |
1743 | |
1744 | prev = NULL; | |
1745 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1746 | { | |
1747 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1748 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1749 | && f->fx_addsy == l->fixp->fx_addsy | |
1750 | && f->fx_offset == l->fixp->fx_offset | |
1751 | && (pass == 1 | |
1752 | || prev == NULL | |
1753 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1754 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1755 | || prev->fx_addsy != f->fx_addsy | |
ab3e48dc | 1756 | || prev->fx_offset != f->fx_offset)) |
252b5132 | 1757 | { |
ab3e48dc | 1758 | fixS **pf; |
252b5132 RH |
1759 | |
1760 | /* Move l->fixp before f. */ | |
1761 | for (pf = &seginfo->fix_root; | |
ab3e48dc KH |
1762 | *pf != l->fixp; |
1763 | pf = & (*pf)->fx_next) | |
1764 | assert (*pf != NULL); | |
252b5132 | 1765 | |
ab3e48dc | 1766 | *pf = l->fixp->fx_next; |
252b5132 RH |
1767 | |
1768 | l->fixp->fx_next = f; | |
1769 | if (prev == NULL) | |
1770 | seginfo->fix_root = l->fixp; | |
1771 | else | |
1772 | prev->fx_next = l->fixp; | |
1773 | ||
1774 | break; | |
1775 | } | |
1776 | ||
1777 | prev = f; | |
1778 | } | |
1779 | ||
1780 | if (f != NULL) | |
1781 | break; | |
1782 | ||
1783 | if (pass == 1 | |
1784 | && warn_unmatched_high) | |
1785 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1786 | _("Unmatched high/shigh reloc")); | |
1787 | } | |
1788 | } | |
1789 | } | |
1790 | ||
1791 | /* See whether we need to force a relocation into the output file. | |
1792 | This is used to force out switch and PC relative relocations when | |
1793 | relaxing. */ | |
1794 | ||
1795 | int | |
1796 | m32r_force_relocation (fix) | |
ab3e48dc | 1797 | fixS *fix; |
252b5132 RH |
1798 | { |
1799 | if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1800 | || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1801 | return 1; | |
1802 | ||
1803 | if (! m32r_relax) | |
1804 | return 0; | |
1805 | ||
ab3e48dc | 1806 | return fix->fx_pcrel; |
252b5132 RH |
1807 | } |
1808 | \f | |
1809 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1810 | ||
1811 | void | |
1812 | md_number_to_chars (buf, val, n) | |
ab3e48dc | 1813 | char *buf; |
252b5132 | 1814 | valueT val; |
ab3e48dc | 1815 | int n; |
252b5132 RH |
1816 | { |
1817 | if (target_big_endian) | |
1818 | number_to_chars_bigendian (buf, val, n); | |
1819 | else | |
1820 | number_to_chars_littleendian (buf, val, n); | |
1821 | } | |
1822 | ||
ab3e48dc KH |
1823 | /* Turn a string in input_line_pointer into a floating point constant |
1824 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1825 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1826 | returned, or NULL on OK. */ | |
252b5132 | 1827 | |
ab3e48dc | 1828 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
1829 | #define MAX_LITTLENUMS 6 |
1830 | ||
1831 | char * | |
1832 | md_atof (type, litP, sizeP) | |
1833 | char type; | |
1834 | char *litP; | |
1835 | int *sizeP; | |
1836 | { | |
ab3e48dc KH |
1837 | int i; |
1838 | int prec; | |
1839 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1840 | char *t; | |
1841 | char *atof_ieee (); | |
252b5132 RH |
1842 | |
1843 | switch (type) | |
1844 | { | |
1845 | case 'f': | |
1846 | case 'F': | |
1847 | case 's': | |
1848 | case 'S': | |
1849 | prec = 2; | |
1850 | break; | |
1851 | ||
1852 | case 'd': | |
1853 | case 'D': | |
1854 | case 'r': | |
1855 | case 'R': | |
1856 | prec = 4; | |
1857 | break; | |
1858 | ||
ab3e48dc KH |
1859 | /* FIXME: Some targets allow other format chars for bigger sizes |
1860 | here. */ | |
252b5132 RH |
1861 | |
1862 | default: | |
ab3e48dc | 1863 | *sizeP = 0; |
252b5132 RH |
1864 | return _("Bad call to md_atof()"); |
1865 | } | |
1866 | ||
1867 | t = atof_ieee (input_line_pointer, type, words); | |
1868 | if (t) | |
1869 | input_line_pointer = t; | |
ab3e48dc | 1870 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
252b5132 RH |
1871 | |
1872 | if (target_big_endian) | |
1873 | { | |
1874 | for (i = 0; i < prec; i++) | |
1875 | { | |
1876 | md_number_to_chars (litP, (valueT) words[i], | |
1877 | sizeof (LITTLENUM_TYPE)); | |
1878 | litP += sizeof (LITTLENUM_TYPE); | |
1879 | } | |
1880 | } | |
1881 | else | |
1882 | { | |
1883 | for (i = prec - 1; i >= 0; i--) | |
1884 | { | |
1885 | md_number_to_chars (litP, (valueT) words[i], | |
1886 | sizeof (LITTLENUM_TYPE)); | |
1887 | litP += sizeof (LITTLENUM_TYPE); | |
1888 | } | |
1889 | } | |
ab3e48dc | 1890 | |
252b5132 RH |
1891 | return 0; |
1892 | } | |
1893 | ||
1894 | void | |
1895 | m32r_elf_section_change_hook () | |
1896 | { | |
1897 | /* If we have reached the end of a section and we have just emitted a | |
1898 | 16 bit insn, then emit a nop to make sure that the section ends on | |
1899 | a 32 bit boundary. */ | |
ab3e48dc | 1900 | |
252b5132 RH |
1901 | if (prev_insn.insn || seen_relaxable_p) |
1902 | (void) m32r_fill_insn (0); | |
1903 | } | |
1904 | ||
60bcf0fa | 1905 | /* Return true if can adjust the reloc to be relative to its section |
ab3e48dc | 1906 | (such as .data) instead of relative to some symbol. */ |
60bcf0fa | 1907 | |
252b5132 RH |
1908 | boolean |
1909 | m32r_fix_adjustable (fixP) | |
1910 | fixS *fixP; | |
1911 | { | |
1912 | ||
5c86cbc7 | 1913 | bfd_reloc_code_real_type reloc_type; |
ab3e48dc | 1914 | |
5c86cbc7 CM |
1915 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
1916 | { | |
1917 | const CGEN_INSN *insn = NULL; | |
1918 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; | |
ab3e48dc KH |
1919 | const CGEN_OPERAND *operand = |
1920 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); | |
5c86cbc7 CM |
1921 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
1922 | } | |
1923 | else | |
1924 | reloc_type = fixP->fx_r_type; | |
1925 | ||
252b5132 RH |
1926 | if (fixP->fx_addsy == NULL) |
1927 | return 1; | |
60bcf0fa | 1928 | |
ab3e48dc | 1929 | /* Prevent all adjustments to global symbols. */ |
252b5132 RH |
1930 | if (S_IS_EXTERN (fixP->fx_addsy)) |
1931 | return 0; | |
1932 | if (S_IS_WEAK (fixP->fx_addsy)) | |
1933 | return 0; | |
60bcf0fa | 1934 | |
ab3e48dc | 1935 | /* We need the symbol name for the VTABLE entries. */ |
5c86cbc7 CM |
1936 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
1937 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
1938 | return 0; |
1939 | ||
1940 | return 1; | |
1941 | } |