Commit | Line | Data |
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76090fdd | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
a15a45e5 | 25 | #include "symcat.h" |
c8cf7e17 | 26 | #include "cgen-opc.h" |
defc70bf | 27 | #include "cgen.h" |
c8cf7e17 | 28 | |
defc70bf DE |
29 | /* Linked list of symbols that are debugging symbols to be defined as the |
30 | beginning of the current instruction. */ | |
31 | typedef struct sym_link | |
32 | { | |
33 | struct sym_link *next; | |
34 | symbolS *symbol; | |
35 | } sym_linkS; | |
36 | ||
37 | static sym_linkS *debug_sym_link = (sym_linkS *)0; | |
38 | ||
ca6a899d NC |
39 | /* Structure to hold all of the different components describing |
40 | an individual instruction. */ | |
b6930bdf NC |
41 | typedef struct |
42 | { | |
43 | const CGEN_INSN * insn; | |
a15a45e5 | 44 | const CGEN_INSN * orig_insn; |
b6930bdf NC |
45 | CGEN_FIELDS fields; |
46 | #ifdef CGEN_INT_INSN | |
47 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
48 | #else | |
49 | char buffer [CGEN_MAX_INSN_SIZE]; | |
50 | #endif | |
51 | char * addr; | |
52 | fragS * frag; | |
defc70bf DE |
53 | int num_fixups; |
54 | fixS * fixups [CGEN_MAX_FIXUPS]; | |
6cf2575a | 55 | int indices [MAX_OPERAND_INSTANCES]; |
defc70bf | 56 | sym_linkS *debug_sym_link; |
b6930bdf NC |
57 | } |
58 | m32r_insn; | |
59 | ||
60 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
61 | boundary (i.e. was the first of two 16 bit insns). */ | |
62 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
63 | |
64 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
65 | alignment request. */ | |
66 | static int seen_relaxable_p = 0; | |
67 | ||
68 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
69 | for the linker to do relaxing. | |
70 | We do simple forms of relaxing internally, but they are always done. | |
71 | This flag does not apply to them. */ | |
72 | static int m32r_relax; | |
73 | ||
74 | /* If non-NULL, pointer to cpu description file to read. | |
75 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 76 | static char * m32r_cpu_desc; |
c8cf7e17 | 77 | |
7c629878 DE |
78 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. |
79 | Each high/shigh reloc must be paired with it's low cousin in order to | |
80 | properly calculate the addend in a relocatable link (since there is a | |
81 | potential carry from the low to the high/shigh). | |
82 | This option is off by default though for user-written assembler code it | |
83 | might make sense to make the default be on (i.e. have gcc pass a flag | |
84 | to turn it off). This warning must not be on for GCC created code as | |
85 | optimization may delete the low but not the high/shigh (at least we | |
86 | shouldn't assume or require it to). */ | |
87 | static int warn_unmatched_high = 0; | |
88 | ||
b5e9e562 | 89 | /* start-sanitize-m32rx */ |
32c2be76 | 90 | /* Non-zero if --m32rx has been specified, in which case support for the |
a450e9f4 | 91 | extended M32RX instruction set should be enabled. */ |
a450e9f4 | 92 | static int enable_m32rx = 0; |
b6930bdf | 93 | |
98c5cd5a | 94 | /* Non-zero if --m32rx --hidden has been specified, in which case support for |
32c2be76 NC |
95 | the special M32RX instruction set should be enabled. */ |
96 | static int enable_special = 0; | |
97 | ||
b6930bdf NC |
98 | /* Non-zero if the programmer should be warned when an explicit parallel |
99 | instruction might have constraint violations. */ | |
100 | static int warn_explicit_parallel_conflicts = 1; | |
48401fcf | 101 | |
48401fcf TT |
102 | /* Non-zero if insns can be made parallel. */ |
103 | static int optimize; | |
b5e9e562 | 104 | /* end-sanitize-m32rx */ |
a450e9f4 | 105 | |
c8cf7e17 | 106 | /* stuff for .scomm symbols. */ |
ebde3f62 | 107 | static segT sbss_section; |
c8cf7e17 | 108 | static asection scom_section; |
ebde3f62 | 109 | static asymbol scom_symbol; |
c8cf7e17 | 110 | |
ebde3f62 NC |
111 | const char comment_chars[] = ";"; |
112 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 113 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
114 | const char EXP_CHARS[] = "eE"; |
115 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
116 | |
117 | /* Relocations against symbols are done in two | |
118 | parts, with a HI relocation and a LO relocation. Each relocation | |
119 | has only 16 bits of space to store an addend. This means that in | |
120 | order for the linker to handle carries correctly, it must be able | |
121 | to locate both the HI and the LO relocation. This means that the | |
122 | relocations must appear in order in the relocation table. | |
123 | ||
124 | In order to implement this, we keep track of each unmatched HI | |
125 | relocation. We then sort them so that they immediately precede the | |
126 | corresponding LO relocation. */ | |
127 | ||
128 | struct m32r_hi_fixup | |
129 | { | |
ebde3f62 NC |
130 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
131 | fixS * fixp; /* This fixup. */ | |
132 | segT seg; /* The section this fixup is in. */ | |
133 | ||
c8cf7e17 DE |
134 | }; |
135 | ||
136 | /* The list of unmatched HI relocs. */ | |
137 | ||
ebde3f62 | 138 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 139 | |
a450e9f4 | 140 | \f |
b5e9e562 | 141 | /* start-sanitize-m32rx */ |
a450e9f4 | 142 | static void |
55a4759f DE |
143 | allow_m32rx (on) |
144 | int on; | |
a450e9f4 NC |
145 | { |
146 | enable_m32rx = on; | |
147 | ||
148 | if (stdoutput != NULL) | |
ebde3f62 NC |
149 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
150 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 151 | } |
b5e9e562 | 152 | /* end-sanitize-m32rx */ |
c8cf7e17 | 153 | \f |
48401fcf | 154 | #define M32R_SHORTOPTS "" |
defc70bf | 155 | /* start-sanitize-m32rx */ |
48401fcf TT |
156 | #undef M32R_SHORTOPTS |
157 | #define M32R_SHORTOPTS "O" | |
defc70bf | 158 | /* end-sanitize-m32rx */ |
48401fcf | 159 | const char * md_shortopts = M32R_SHORTOPTS; |
c8cf7e17 | 160 | |
a450e9f4 NC |
161 | struct option md_longopts[] = |
162 | { | |
b5e9e562 | 163 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
164 | #define OPTION_M32RX (OPTION_MD_BASE) |
165 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
7c629878 DE |
166 | #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1) |
167 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
168 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
169 | #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2) | |
170 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
171 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
32c2be76 | 172 | #define OPTION_SPECIAL (OPTION_MD_BASE + 3) |
98c5cd5a | 173 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
b5e9e562 | 174 | /* end-sanitize-m32rx */ |
a450e9f4 | 175 | |
7c629878 DE |
176 | /* Sigh. I guess all warnings must now have both variants. */ |
177 | #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4) | |
178 | {"warn-unmatched-high", OPTION_WARN_UNMATCHED}, | |
179 | {"Wuh", OPTION_WARN_UNMATCHED}, | |
180 | #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5) | |
181 | {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED}, | |
182 | {"Wnuh", OPTION_WARN_UNMATCHED}, | |
183 | ||
c8cf7e17 | 184 | #if 0 /* not supported yet */ |
7c629878 | 185 | #define OPTION_RELAX (OPTION_MD_BASE + 6) |
c8cf7e17 | 186 | {"relax", no_argument, NULL, OPTION_RELAX}, |
7c629878 | 187 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 7) |
c8cf7e17 DE |
188 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
189 | #endif | |
a450e9f4 | 190 | |
c8cf7e17 DE |
191 | {NULL, no_argument, NULL, 0} |
192 | }; | |
ebde3f62 | 193 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
194 | |
195 | int | |
196 | md_parse_option (c, arg) | |
ebde3f62 NC |
197 | int c; |
198 | char * arg; | |
c8cf7e17 DE |
199 | { |
200 | switch (c) | |
201 | { | |
b5e9e562 | 202 | /* start-sanitize-m32rx */ |
48401fcf TT |
203 | case 'O': |
204 | optimize = 1; | |
205 | break; | |
48401fcf | 206 | |
a450e9f4 NC |
207 | case OPTION_M32RX: |
208 | allow_m32rx (1); | |
209 | break; | |
b6930bdf | 210 | |
7c629878 | 211 | case OPTION_WARN_PARALLEL: |
b6930bdf NC |
212 | warn_explicit_parallel_conflicts = 1; |
213 | break; | |
214 | ||
7c629878 | 215 | case OPTION_NO_WARN_PARALLEL: |
b6930bdf NC |
216 | warn_explicit_parallel_conflicts = 0; |
217 | break; | |
7c629878 | 218 | |
32c2be76 | 219 | case OPTION_SPECIAL: |
98c5cd5a NC |
220 | if (enable_m32rx) |
221 | enable_special = 1; | |
222 | else | |
223 | { | |
224 | extern char * myname; | |
225 | ||
226 | /* Pretend that we do not recognise this option. */ | |
227 | fprintf (stderr, _("%s: unrecognised option: --hidden\n"), myname); | |
228 | return 0; | |
229 | } | |
32c2be76 | 230 | break; |
b5e9e562 | 231 | /* end-sanitize-m32rx */ |
7c629878 DE |
232 | |
233 | case OPTION_WARN_UNMATCHED: | |
234 | warn_unmatched_high = 1; | |
235 | break; | |
236 | ||
237 | case OPTION_NO_WARN_UNMATCHED: | |
238 | warn_unmatched_high = 0; | |
239 | break; | |
a450e9f4 | 240 | |
c8cf7e17 DE |
241 | #if 0 /* not supported yet */ |
242 | case OPTION_RELAX: | |
243 | m32r_relax = 1; | |
244 | break; | |
245 | case OPTION_CPU_DESC: | |
246 | m32r_cpu_desc = arg; | |
247 | break; | |
248 | #endif | |
7c629878 | 249 | |
c8cf7e17 DE |
250 | default: |
251 | return 0; | |
252 | } | |
253 | return 1; | |
254 | } | |
255 | ||
256 | void | |
257 | md_show_usage (stream) | |
ebde3f62 | 258 | FILE * stream; |
c8cf7e17 | 259 | { |
7c629878 DE |
260 | fprintf (stream, _("M32R specific command line options:\n")); |
261 | ||
b5e9e562 | 262 | /* start-sanitize-m32rx */ |
48401fcf | 263 | fprintf (stream, _("\ |
99bf7e37 | 264 | --m32rx support the extended m32rx instruction set\n")); |
32c2be76 | 265 | fprintf (stream, _("\ |
99bf7e37 | 266 | -O try to combine instructions in parallel\n")); |
48401fcf TT |
267 | |
268 | fprintf (stream, _("\ | |
99bf7e37 | 269 | --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n")); |
48401fcf | 270 | fprintf (stream, _("\ |
99bf7e37 | 271 | --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n")); |
48401fcf | 272 | fprintf (stream, _("\ |
99bf7e37 | 273 | --Wp synonym for --warn-explicit-parallel-conflicts\n")); |
48401fcf | 274 | fprintf (stream, _("\ |
99bf7e37 | 275 | --Wnp synonym for --no-warn-explicit-parallel-conflicts\n")); |
b5e9e562 | 276 | /* end-sanitize-m32rx */ |
a450e9f4 | 277 | |
7c629878 | 278 | fprintf (stream, _("\ |
99bf7e37 | 279 | --warn-unmatched-high warn when a high or shigh reloc has no matching low reloc\n")); |
7c629878 | 280 | fprintf (stream, _("\ |
99bf7e37 | 281 | --no-warn-unmatched-high do not warn when a high or shigh reloc has no matching low reloc\n")); |
7c629878 | 282 | fprintf (stream, _("\ |
99bf7e37 | 283 | --Wuh synonym for --warn-unmatched-high\n")); |
7c629878 | 284 | fprintf (stream, _("\ |
99bf7e37 | 285 | --Wnuh synonym for --no-warn-unmatched-high\n")); |
7c629878 | 286 | |
c8cf7e17 | 287 | #if 0 |
48401fcf | 288 | fprintf (stream, _("\ |
99bf7e37 | 289 | --relax create linker relaxable code\n")); |
48401fcf | 290 | fprintf (stream, _("\ |
99bf7e37 | 291 | --cpu-desc provide runtime cpu description file\n")); |
c8cf7e17 DE |
292 | #endif |
293 | } | |
294 | ||
295 | static void fill_insn PARAMS ((int)); | |
296 | static void m32r_scomm PARAMS ((int)); | |
defc70bf DE |
297 | static void debug_sym PARAMS ((int)); |
298 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
c8cf7e17 DE |
299 | |
300 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
301 | static subsegT prev_subseg; | |
302 | static segT prev_seg; | |
303 | ||
304 | /* The target specific pseudo-ops which we support. */ | |
305 | const pseudo_typeS md_pseudo_table[] = | |
306 | { | |
defc70bf DE |
307 | { "word", cons, 4 }, |
308 | { "fillinsn", fill_insn, 0 }, | |
309 | { "scomm", m32r_scomm, 0 }, | |
310 | { "debugsym", debug_sym, 0 }, | |
b5e9e562 | 311 | /* start-sanitize-m32rx */ |
defc70bf DE |
312 | { "m32r", allow_m32rx, 0 }, |
313 | { "m32rx", allow_m32rx, 1 }, | |
b5e9e562 | 314 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
315 | { NULL, NULL, 0 } |
316 | }; | |
317 | ||
318 | /* FIXME: Should be machine generated. */ | |
319 | #define NOP_INSN 0x7000 | |
320 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
321 | ||
322 | /* When we align the .text section, insert the correct NOP pattern. | |
323 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
324 | MAX is the maximum number of characters to skip when doing the alignment, | |
325 | or 0 if there is no maximum. */ | |
326 | ||
327 | int | |
328 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
329 | int n; |
330 | const char * fill; | |
331 | int len; | |
332 | int max; | |
c8cf7e17 | 333 | { |
99bf7e37 NC |
334 | /* Only do this if the fill pattern wasn't specified. */ |
335 | if (fill == NULL | |
c8cf7e17 DE |
336 | && (now_seg->flags & SEC_CODE) != 0 |
337 | /* Only do this special handling if aligning to at least a | |
338 | 4 byte boundary. */ | |
339 | && n > 1 | |
775fdd0c | 340 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
341 | least two bytes. */ |
342 | && (max == 0 || max > 1)) | |
343 | { | |
344 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
345 | ||
346 | #if 0 | |
347 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
348 | /* FIXME: How much memory will cause gas to use when assembling a big | |
349 | program? Perhaps we can avoid the frag_align call? */ | |
350 | frag_align (1, 0, 0); | |
351 | #endif | |
352 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
353 | nop. */ | |
354 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
355 | /* If doing larger alignments use a repeating sequence of appropriate | |
356 | nops. */ | |
357 | if (n > 2) | |
358 | { | |
ebde3f62 NC |
359 | static const unsigned char multi_nop_pattern[] = |
360 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
361 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
362 | max ? max - 2 : 0); | |
363 | } | |
364 | return 1; | |
365 | } | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | static void | |
371 | assemble_nop (opcode) | |
372 | int opcode; | |
373 | { | |
ebde3f62 | 374 | char * f = frag_more (2); |
c8cf7e17 DE |
375 | md_number_to_chars (f, opcode, 2); |
376 | } | |
377 | ||
378 | /* If the last instruction was the first of 2 16 bit insns, | |
379 | output a nop to move the PC to a 32 bit boundary. | |
380 | ||
381 | This is done via an alignment specification since branch relaxing | |
382 | may make it unnecessary. | |
383 | ||
384 | Internally, we need to output one of these each time a 32 bit insn is | |
385 | seen after an insn that is relaxable. */ | |
386 | ||
387 | static void | |
388 | fill_insn (ignore) | |
389 | int ignore; | |
390 | { | |
391 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 392 | prev_insn.insn = NULL; |
c8cf7e17 DE |
393 | seen_relaxable_p = 0; |
394 | } | |
395 | ||
defc70bf DE |
396 | /* Record the symbol so that when we output the insn, we can create |
397 | a symbol that is at the start of the instruction. This is used | |
398 | to emit the label for the start of a breakpoint without causing | |
399 | the assembler to emit a NOP if the previous instruction was a | |
400 | 16 bit instruction. */ | |
401 | ||
402 | static void | |
403 | debug_sym (ignore) | |
404 | int ignore; | |
405 | { | |
406 | register char *name; | |
407 | register char delim; | |
408 | register char *end_name; | |
409 | register symbolS *symbolP; | |
410 | register sym_linkS *link; | |
411 | ||
412 | name = input_line_pointer; | |
413 | delim = get_symbol_end (); | |
414 | end_name = input_line_pointer; | |
415 | ||
416 | if ((symbolP = symbol_find (name)) == NULL | |
417 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
418 | { | |
419 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
420 | } | |
421 | ||
422 | symbol_table_insert (symbolP); | |
423 | if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) | |
ca6a899d | 424 | /* xgettext:c-format */ |
defc70bf DE |
425 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); |
426 | ||
427 | else | |
428 | { | |
429 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
430 | link->symbol = symbolP; | |
431 | link->next = debug_sym_link; | |
432 | debug_sym_link = link; | |
433 | symbolP->local = 1; | |
434 | } | |
435 | ||
436 | *end_name = delim; | |
437 | demand_empty_rest_of_line (); | |
438 | } | |
439 | ||
440 | /* Second pass to expanding the debug symbols, go through linked | |
441 | list of symbols and reassign the address. */ | |
442 | ||
443 | static void | |
444 | expand_debug_syms (syms, align) | |
445 | sym_linkS *syms; | |
446 | int align; | |
447 | { | |
448 | char *save_input_line = input_line_pointer; | |
449 | sym_linkS *next_syms; | |
450 | expressionS exp; | |
451 | ||
452 | if (!syms) | |
453 | return; | |
454 | ||
455 | (void) m32r_do_align (align, NULL, 0, 0); | |
456 | for (; syms != (sym_linkS *)0; syms = next_syms) | |
457 | { | |
458 | symbolS *symbolP = syms->symbol; | |
459 | next_syms = syms->next; | |
460 | input_line_pointer = ".\n"; | |
461 | pseudo_set (symbolP); | |
462 | free ((char *)syms); | |
463 | } | |
464 | ||
465 | input_line_pointer = save_input_line; | |
466 | } | |
467 | ||
c8cf7e17 | 468 | /* Cover function to fill_insn called after a label and at end of assembly. |
c8cf7e17 DE |
469 | The result is always 1: we're called in a conditional to see if the |
470 | current line is a label. */ | |
471 | ||
472 | int | |
473 | m32r_fill_insn (done) | |
474 | int done; | |
475 | { | |
c8cf7e17 DE |
476 | if (prev_seg != NULL) |
477 | { | |
48401fcf TT |
478 | segT seg = now_seg; |
479 | subsegT subseg = now_subseg; | |
480 | ||
c8cf7e17 | 481 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 482 | |
c8cf7e17 | 483 | fill_insn (0); |
99bf7e37 | 484 | |
c8cf7e17 DE |
485 | subseg_set (seg, subseg); |
486 | } | |
99bf7e37 NC |
487 | |
488 | if (done && debug_sym_link) | |
489 | { | |
490 | expand_debug_syms (debug_sym_link, 1); | |
491 | debug_sym_link = (sym_linkS *)0; | |
492 | } | |
493 | ||
c8cf7e17 DE |
494 | return 1; |
495 | } | |
496 | \f | |
497 | void | |
498 | md_begin () | |
499 | { | |
500 | flagword applicable; | |
ebde3f62 NC |
501 | segT seg; |
502 | subsegT subseg; | |
c8cf7e17 DE |
503 | |
504 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
505 | |
506 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 507 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 508 | |
4e9d8dea | 509 | /* Set the machine number and endian. */ |
c8cf7e17 | 510 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
511 | target_big_endian ? |
512 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
513 | |
514 | #if 0 /* not supported yet */ | |
515 | /* If a runtime cpu description file was provided, parse it. */ | |
516 | if (m32r_cpu_desc != NULL) | |
517 | { | |
ebde3f62 | 518 | const char * errmsg; |
c8cf7e17 DE |
519 | |
520 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
521 | if (errmsg != NULL) | |
522 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
523 | } | |
524 | #endif | |
525 | ||
526 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
527 | we don't want the initial section to be .sbss]. */ |
528 | seg = now_seg; | |
c8cf7e17 DE |
529 | subseg = now_subseg; |
530 | ||
531 | /* The sbss section is for local .scomm symbols. */ | |
532 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 533 | |
c8cf7e17 DE |
534 | /* This is copied from perform_an_assembly_pass. */ |
535 | applicable = bfd_applicable_section_flags (stdoutput); | |
536 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 537 | |
c8cf7e17 DE |
538 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
539 | seg_info (bss_section)->bss = 1; | |
540 | #endif | |
541 | ||
542 | subseg_set (seg, subseg); | |
543 | ||
544 | /* We must construct a fake section similar to bfd_com_section | |
545 | but with the name .scommon. */ | |
ebde3f62 NC |
546 | scom_section = bfd_com_section; |
547 | scom_section.name = ".scommon"; | |
548 | scom_section.output_section = & scom_section; | |
549 | scom_section.symbol = & scom_symbol; | |
550 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
551 | scom_symbol = * bfd_com_section.symbol; | |
552 | scom_symbol.name = ".scommon"; | |
553 | scom_symbol.section = & scom_section; | |
a450e9f4 | 554 | |
b5e9e562 | 555 | /* start-sanitize-m32rx */ |
a450e9f4 | 556 | allow_m32rx (enable_m32rx); |
b5e9e562 | 557 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
558 | } |
559 | ||
89285fc9 | 560 | /* start-sanitize-m32rx */ |
55a4759f | 561 | |
a15a45e5 DE |
562 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ |
563 | (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \ | |
564 | || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \ | |
565 | && (indices [index] == 0 || indices [index] == 1))) | |
566 | ||
6cf2575a NC |
567 | /* Returns true if an output of instruction 'a' is referenced by an operand |
568 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
569 | checked, otherwise its inputs are examined. */ | |
48401fcf | 570 | |
ebde3f62 | 571 | static int |
6cf2575a | 572 | first_writes_to_seconds_operands (a, b, check_outputs) |
26192c50 NC |
573 | m32r_insn * a; |
574 | m32r_insn * b; | |
6cf2575a | 575 | const int check_outputs; |
00aa5b17 | 576 | { |
c9cec4ef | 577 | const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn); |
39149be2 | 578 | const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn); |
6cf2575a | 579 | int a_index; |
00aa5b17 | 580 | |
0c22a4c1 | 581 | /* If at least one of the instructions takes no operands, then there is |
c9cec4ef NC |
582 | nothing to check. There really are instructions without operands, |
583 | eg 'nop'. */ | |
39149be2 | 584 | if (a_operands == NULL || b_ops == NULL) |
c9cec4ef NC |
585 | return 0; |
586 | ||
6cf2575a | 587 | /* Scan the operand list of 'a' looking for an output operand. */ |
c9cec4ef | 588 | for (a_index = 0; |
6cf2575a NC |
589 | CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END; |
590 | a_index ++, a_operands ++) | |
26192c50 | 591 | { |
6cf2575a | 592 | if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT) |
26192c50 | 593 | { |
c9cec4ef | 594 | int b_index; |
39149be2 | 595 | const CGEN_OPERAND_INSTANCE * b_operands = b_ops; |
a15a45e5 DE |
596 | |
597 | /* Special Case: | |
598 | The Condition bit 'C' is a shadow of the CBR register (control | |
599 | register 1) and also a shadow of bit 31 of the program status | |
600 | word (control register 0). For now this is handled here, rather | |
601 | than by cgen.... */ | |
602 | ||
603 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) | |
604 | { | |
605 | /* Scan operand list of 'b' looking for another reference to the | |
606 | condition bit, which goes in the right direction. */ | |
607 | for (b_index = 0; | |
608 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; | |
609 | b_index ++, b_operands ++) | |
610 | { | |
611 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
612 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
613 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
614 | return 1; | |
615 | } | |
616 | } | |
617 | else | |
6cf2575a | 618 | { |
ca6a899d NC |
619 | /* Scan operand list of 'b' looking for an operand that |
620 | references the same hardware element, and which goes in the | |
621 | right direction. */ | |
a15a45e5 DE |
622 | for (b_index = 0; |
623 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; | |
624 | b_index ++, b_operands ++) | |
625 | { | |
626 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
627 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
628 | && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands)) | |
629 | && (a->indices [a_index] == b->indices [b_index])) | |
630 | return 1; | |
631 | } | |
6cf2575a | 632 | } |
26192c50 NC |
633 | } |
634 | } | |
635 | ||
6cf2575a | 636 | return 0; |
26192c50 NC |
637 | } |
638 | ||
6cf2575a | 639 | /* Returns true if the insn can (potentially) alter the program counter. */ |
48401fcf | 640 | |
89285fc9 | 641 | static int |
6cf2575a | 642 | writes_to_pc (a) |
89285fc9 | 643 | m32r_insn * a; |
89285fc9 | 644 | { |
a15a45e5 | 645 | #if 0 /* Once PC operands are working.... */ |
c9cec4ef | 646 | const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn); |
8e7a5a04 | 647 | |
c9cec4ef NC |
648 | if (a_operands == NULL) |
649 | return 0; | |
650 | ||
651 | while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END) | |
6cf2575a NC |
652 | { |
653 | if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL | |
654 | && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC) | |
655 | return 1; | |
c9cec4ef NC |
656 | |
657 | a_operands ++; | |
6cf2575a | 658 | } |
8e7a5a04 NC |
659 | #else |
660 | if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI) | |
661 | || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI)) | |
662 | return 1; | |
663 | #endif | |
6cf2575a | 664 | return 0; |
89285fc9 | 665 | } |
26192c50 | 666 | |
775fdd0c NC |
667 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
668 | otherwise it returns a pointer to an error message explaining why not. */ | |
48401fcf | 669 | |
775fdd0c | 670 | static const char * |
26192c50 | 671 | can_make_parallel (a, b) |
b6930bdf NC |
672 | m32r_insn * a; |
673 | m32r_insn * b; | |
775fdd0c NC |
674 | { |
675 | PIPE_ATTR a_pipe; | |
676 | PIPE_ATTR b_pipe; | |
89285fc9 | 677 | |
775fdd0c | 678 | /* Make sure the instructions are the right length. */ |
b6930bdf NC |
679 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
680 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c | 681 | abort(); |
89285fc9 | 682 | |
6cf2575a | 683 | if (first_writes_to_seconds_operands (a, b, true)) |
d0023d7e | 684 | return _("Instructions write to the same destination register."); |
775fdd0c | 685 | |
b6930bdf NC |
686 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
687 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 688 | |
b6930bdf | 689 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
690 | if ( a_pipe == PIPE_NONE |
691 | || b_pipe == PIPE_NONE) | |
d0023d7e | 692 | return _("Instructions do not use parallel execution pipelines."); |
89285fc9 NC |
693 | |
694 | /* Leave this test for last, since it is the only test that can | |
695 | go away if the instructions are swapped, and we want to make | |
696 | sure that any other errors are detected before this happens. */ | |
775fdd0c NC |
697 | if ( a_pipe == PIPE_S |
698 | || b_pipe == PIPE_O) | |
d0023d7e | 699 | return _("Instructions share the same execution pipeline"); |
89285fc9 | 700 | |
775fdd0c NC |
701 | return NULL; |
702 | } | |
775fdd0c NC |
703 | |
704 | #ifdef CGEN_INT_INSN | |
f2980bb4 | 705 | |
775fdd0c | 706 | static void |
b6930bdf NC |
707 | make_parallel (buffer) |
708 | cgen_insn_t * buffer; | |
775fdd0c NC |
709 | { |
710 | /* Force the top bit of the second insn to be set. */ | |
711 | ||
712 | bfd_vma value; | |
713 | ||
714 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
715 | { | |
716 | value = bfd_getb16 ((bfd_byte *) buffer); | |
717 | value |= 0x8000; | |
718 | bfd_putb16 (value, (char *) buffer); | |
719 | } | |
720 | else | |
721 | { | |
722 | value = bfd_getl16 ((bfd_byte *) buffer); | |
723 | value |= 0x8000; | |
724 | bfd_putl16 (value, (char *) buffer); | |
725 | } | |
726 | } | |
f2980bb4 | 727 | |
775fdd0c | 728 | #else |
f2980bb4 | 729 | |
775fdd0c | 730 | static void |
b6930bdf NC |
731 | make_parallel (buffer) |
732 | char * buffer; | |
775fdd0c NC |
733 | { |
734 | /* Force the top bit of the second insn to be set. */ | |
735 | ||
736 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
737 | } | |
775fdd0c | 738 | |
f2980bb4 | 739 | #endif /* ! CGEN_INT_INSN */ |
775fdd0c | 740 | |
b6930bdf NC |
741 | static void |
742 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 743 | char * str; |
b6930bdf | 744 | char * str2; |
c8cf7e17 | 745 | { |
b6930bdf NC |
746 | char * str3; |
747 | m32r_insn first; | |
748 | m32r_insn second; | |
749 | char * errmsg; | |
ebde3f62 | 750 | |
b6930bdf | 751 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 752 | |
b6930bdf NC |
753 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
754 | so that the parallel instruction will start on a 32 bit boundary. */ | |
755 | if (prev_insn.insn) | |
756 | fill_insn (0); | |
ebde3f62 | 757 | |
defc70bf DE |
758 | first.debug_sym_link = debug_sym_link; |
759 | debug_sym_link = (sym_linkS *)0; | |
760 | ||
b6930bdf NC |
761 | /* Parse the first instruction. */ |
762 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
763 | (str, & first.fields, first.buffer, & errmsg))) | |
764 | { | |
765 | as_bad (errmsg); | |
766 | return; | |
767 | } | |
f2980bb4 | 768 | |
32c2be76 NC |
769 | if (! enable_special |
770 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL)) | |
771 | { | |
772 | /* xgettext:c-format */ | |
773 | as_bad (_("unknown instruction '%s'"), str); | |
32c2be76 NC |
774 | return; |
775 | } | |
776 | else if (! enable_m32rx | |
f2980bb4 | 777 | /* FIXME: Need standard macro to perform this test. */ |
b6930bdf NC |
778 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
779 | { | |
32c2be76 | 780 | /* xgettext:c-format */ |
48401fcf | 781 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
b6930bdf | 782 | return; |
ebde3f62 | 783 | } |
32c2be76 | 784 | |
f2980bb4 DE |
785 | /* Check to see if this is an allowable parallel insn. */ |
786 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
787 | { | |
ca6a899d | 788 | /* xgettext:c-format */ |
f2980bb4 DE |
789 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
790 | return; | |
a15a45e5 DE |
791 | } |
792 | ||
b6930bdf NC |
793 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
794 | str3 = str; /* Save the original string pointer. */ | |
795 | str = str2 + 2; /* Advanced past the parsed string. */ | |
796 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
f2980bb4 | 797 | |
b6930bdf NC |
798 | /* Preserve any fixups that have been generated and reset the list to empty. */ |
799 | cgen_save_fixups(); | |
800 | ||
f2980bb4 | 801 | /* Get the indices of the operands of the instruction. */ |
6cf2575a NC |
802 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact |
803 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
c9cec4ef NC |
804 | /* FIXME: ALIAS insns do not have operands, so we use this function |
805 | to find the equivalent insn and overwrite the value stored in our | |
a15a45e5 DE |
806 | structure. We still need the original insn, however, since this |
807 | may have certain attributes that are not present in the unaliased | |
808 | version (eg relaxability). When aliases behave differently this | |
809 | may have to change. */ | |
810 | first.orig_insn = first.insn; | |
ca6a899d NC |
811 | first.insn = m32r_cgen_lookup_get_insn_operands |
812 | (NULL, bfd_getb16 ((char *) first.buffer), 16, first.indices); | |
813 | ||
c9cec4ef | 814 | if (first.insn == NULL) |
f2980bb4 | 815 | as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn")); |
6cf2575a | 816 | |
defc70bf DE |
817 | second.debug_sym_link = NULL; |
818 | ||
b6930bdf NC |
819 | /* Parse the second instruction. */ |
820 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
821 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
822 | { |
823 | as_bad (errmsg); | |
824 | return; | |
825 | } | |
c8cf7e17 | 826 | |
b6930bdf | 827 | /* Check it. */ |
32c2be76 NC |
828 | if (! enable_special |
829 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL)) | |
830 | { | |
831 | /* xgettext:c-format */ | |
832 | as_bad (_("unknown instruction '%s'"), str); | |
32c2be76 NC |
833 | return; |
834 | } | |
835 | else if (! enable_m32rx | |
b6930bdf | 836 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
ebde3f62 | 837 | { |
32c2be76 | 838 | /* xgettext:c-format */ |
48401fcf | 839 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
ebde3f62 NC |
840 | return; |
841 | } | |
f2980bb4 DE |
842 | |
843 | /* Check to see if this is an allowable parallel insn. */ | |
844 | if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
845 | { | |
ca6a899d | 846 | /* xgettext:c-format */ |
f2980bb4 DE |
847 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
848 | return; | |
849 | } | |
ebde3f62 | 850 | |
b6930bdf | 851 | if (! enable_m32rx) |
ebde3f62 | 852 | { |
f2980bb4 DE |
853 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP |
854 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
ebde3f62 | 855 | { |
32c2be76 | 856 | /* xgettext:c-format */ |
48401fcf | 857 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
b6930bdf | 858 | return; |
ebde3f62 | 859 | } |
b6930bdf | 860 | } |
9121b102 | 861 | |
f2980bb4 | 862 | /* Get the indices of the operands of the instruction. */ |
a15a45e5 | 863 | second.orig_insn = second.insn; |
ca6a899d NC |
864 | second.insn = m32r_cgen_lookup_get_insn_operands |
865 | (NULL, bfd_getb16 ((char *) second.buffer), 16, second.indices); | |
866 | ||
c9cec4ef | 867 | if (second.insn == NULL) |
f2980bb4 | 868 | as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn")); |
6cf2575a | 869 | |
b6930bdf NC |
870 | /* We assume that if the first instruction writes to a register that is |
871 | read by the second instruction it is because the programmer intended | |
872 | this to happen, (after all they have explicitly requested that these | |
26192c50 NC |
873 | two instructions be executed in parallel). Although if the global |
874 | variable warn_explicit_parallel_conflicts is true then we do generate | |
875 | a warning message. Similarly we assume that parallel branch and jump | |
00aa5b17 | 876 | instructions are deliberate and should not produce errors. */ |
b6930bdf | 877 | |
00aa5b17 | 878 | if (warn_explicit_parallel_conflicts) |
b6930bdf | 879 | { |
6cf2575a | 880 | if (first_writes_to_seconds_operands (& first, & second, false)) |
32c2be76 | 881 | /* xgettext:c-format */ |
48401fcf | 882 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
26192c50 | 883 | |
6cf2575a | 884 | if (first_writes_to_seconds_operands (& second, & first, false)) |
32c2be76 | 885 | /* xgettext:c-format */ |
48401fcf | 886 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
00aa5b17 DE |
887 | } |
888 | ||
889 | if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL) | |
890 | { | |
b6930bdf NC |
891 | /* Get the fixups for the first instruction. */ |
892 | cgen_swap_fixups (); | |
893 | ||
894 | /* Write it out. */ | |
defc70bf DE |
895 | expand_debug_syms (first.debug_sym_link, 1); |
896 | cgen_asm_finish_insn (first.orig_insn, first.buffer, | |
897 | CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL); | |
ebde3f62 | 898 | |
b6930bdf NC |
899 | /* Force the top bit of the second insn to be set. */ |
900 | make_parallel (second.buffer); | |
ebde3f62 | 901 | |
b6930bdf NC |
902 | /* Get its fixups. */ |
903 | cgen_restore_fixups (); | |
775fdd0c | 904 | |
b6930bdf | 905 | /* Write it out. */ |
defc70bf DE |
906 | expand_debug_syms (second.debug_sym_link, 1); |
907 | cgen_asm_finish_insn (second.orig_insn, second.buffer, | |
908 | CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL); | |
b6930bdf | 909 | } |
89285fc9 | 910 | /* Try swapping the instructions to see if they work that way. */ |
6cf2575a | 911 | else if (can_make_parallel (& second, & first) == NULL) |
b6930bdf NC |
912 | { |
913 | /* Write out the second instruction first. */ | |
defc70bf DE |
914 | expand_debug_syms (second.debug_sym_link, 1); |
915 | cgen_asm_finish_insn (second.orig_insn, second.buffer, | |
916 | CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL); | |
775fdd0c | 917 | |
b6930bdf NC |
918 | /* Force the top bit of the first instruction to be set. */ |
919 | make_parallel (first.buffer); | |
920 | ||
921 | /* Get the fixups for the first instruction. */ | |
922 | cgen_restore_fixups (); | |
923 | ||
924 | /* Write out the first instruction. */ | |
defc70bf DE |
925 | expand_debug_syms (first.debug_sym_link, 1); |
926 | cgen_asm_finish_insn (first.orig_insn, first.buffer, | |
927 | CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL); | |
b6930bdf NC |
928 | } |
929 | else | |
930 | { | |
931 | as_bad ("'%s': %s", str2, errmsg); | |
932 | return; | |
933 | } | |
ebde3f62 | 934 | |
b6930bdf NC |
935 | /* Set these so m32r_fill_insn can use them. */ |
936 | prev_seg = now_seg; | |
937 | prev_subseg = now_subseg; | |
b6930bdf | 938 | } |
55a4759f | 939 | |
b6930bdf NC |
940 | /* end-sanitize-m32rx */ |
941 | ||
942 | ||
943 | void | |
944 | md_assemble (str) | |
945 | char * str; | |
946 | { | |
947 | m32r_insn insn; | |
948 | char * errmsg; | |
949 | char * str2 = NULL; | |
950 | ||
951 | /* Initialize GAS's cgen interface for a new instruction. */ | |
952 | cgen_asm_init_parse (); | |
953 | ||
954 | /* start-sanitize-m32rx */ | |
955 | /* Look for a parallel instruction seperator. */ | |
956 | if ((str2 = strstr (str, "||")) != NULL) | |
957 | { | |
958 | assemble_parallel_insn (str, str2); | |
959 | return; | |
ebde3f62 | 960 | } |
b6930bdf NC |
961 | /* end-sanitize-m32rx */ |
962 | ||
defc70bf DE |
963 | insn.debug_sym_link = debug_sym_link; |
964 | debug_sym_link = (sym_linkS *)0; | |
965 | ||
ca6a899d NC |
966 | insn.insn = CGEN_SYM (assemble_insn) |
967 | (str, & insn.fields, insn.buffer, & errmsg); | |
968 | ||
b6930bdf NC |
969 | if (!insn.insn) |
970 | { | |
971 | as_bad (errmsg); | |
972 | return; | |
973 | } | |
974 | ||
975 | /* start-sanitize-m32rx */ | |
32c2be76 NC |
976 | if (! enable_special |
977 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL)) | |
978 | { | |
979 | /* xgettext:c-format */ | |
980 | as_bad (_("unknown instruction '%s'"), str); | |
32c2be76 NC |
981 | return; |
982 | } | |
983 | else if (! enable_m32rx | |
984 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
b6930bdf | 985 | { |
32c2be76 | 986 | /* xgettext:c-format */ |
48401fcf | 987 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
b6930bdf NC |
988 | return; |
989 | } | |
990 | /* end-sanitize-m32rx */ | |
991 | ||
992 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
993 | { |
994 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 995 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 | 996 | { |
0c22a4c1 | 997 | /* ??? If calling fill_insn too many times turns us into a memory |
ebde3f62 NC |
998 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ |
999 | fill_insn (0); | |
1000 | } | |
f2980bb4 | 1001 | |
defc70bf DE |
1002 | expand_debug_syms (insn.debug_sym_link, 2); |
1003 | ||
f2980bb4 | 1004 | /* Doesn't really matter what we pass for RELAX_P here. */ |
defc70bf DE |
1005 | cgen_asm_finish_insn (insn.insn, insn.buffer, |
1006 | CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); | |
c8cf7e17 DE |
1007 | } |
1008 | else | |
1009 | { | |
defc70bf | 1010 | int on_32bit_boundary_p; |
b6930bdf | 1011 | /* start-sanitize-m32rx */ |
b6930bdf | 1012 | int swap = false; |
b6930bdf | 1013 | /* end-sanitize-m32rx */ |
f2980bb4 | 1014 | |
b6930bdf NC |
1015 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) |
1016 | abort(); | |
f2980bb4 | 1017 | |
defc70bf DE |
1018 | insn.orig_insn = insn.insn; |
1019 | /* start-sanitize-m32rx */ | |
f2980bb4 DE |
1020 | if (enable_m32rx) |
1021 | { | |
1022 | /* Get the indices of the operands of the instruction. | |
1023 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
ca6a899d NC |
1024 | insn.insn = m32r_cgen_lookup_get_insn_operands |
1025 | (NULL, bfd_getb16 ((char *) insn.buffer), 16, insn.indices); | |
1026 | ||
f2980bb4 DE |
1027 | if (insn.insn == NULL) |
1028 | as_fatal (_("internal error: m32r_cgen_get_insn_operands failed")); | |
1029 | } | |
defc70bf | 1030 | /* end-sanitize-m32rx */ |
6cf2575a | 1031 | |
defc70bf | 1032 | /* Compute whether we're on a 32 bit boundary or not. |
b6930bdf | 1033 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
defc70bf | 1034 | on_32bit_boundary_p = prev_insn.insn == NULL; |
f2980bb4 | 1035 | |
defc70bf DE |
1036 | /* start-sanitize-m32rx */ |
1037 | /* Look to see if this instruction can be combined with the | |
1038 | previous instruction to make one, parallel, 32 bit instruction. | |
1039 | If the previous instruction (potentially) changed the flow of | |
1040 | program control, then it cannot be combined with the current | |
1041 | instruction. If the current instruction is relaxable, then it | |
1042 | might be replaced with a longer version, so we cannot combine it. | |
1043 | Also if the output of the previous instruction is used as an | |
1044 | input to the current instruction then it cannot be combined. | |
1045 | Otherwise call can_make_parallel() with both orderings of the | |
1046 | instructions to see if they can be combined. */ | |
1047 | if ( ! on_32bit_boundary_p | |
1048 | && enable_m32rx | |
1049 | && optimize | |
1050 | && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 | |
1051 | && ! writes_to_pc (& prev_insn) | |
1052 | && ! first_writes_to_seconds_operands (& prev_insn, &insn, false) | |
1053 | ) | |
775fdd0c | 1054 | { |
defc70bf DE |
1055 | if (can_make_parallel (& prev_insn, & insn) == NULL) |
1056 | make_parallel (insn.buffer); | |
1057 | else if (can_make_parallel (& insn, & prev_insn) == NULL) | |
1058 | swap = true; | |
775fdd0c | 1059 | } |
defc70bf DE |
1060 | /* end-sanitize-m32rx */ |
1061 | ||
1062 | expand_debug_syms (insn.debug_sym_link, 1); | |
1063 | ||
1064 | { | |
1065 | int i; | |
1066 | finished_insnS fi; | |
1067 | ||
1068 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1069 | frag_grow (4); | |
c8cf7e17 | 1070 | |
defc70bf DE |
1071 | cgen_asm_finish_insn (insn.orig_insn, insn.buffer, |
1072 | CGEN_FIELDS_BITSIZE (& insn.fields), | |
1073 | 1 /*relax_p*/, &fi); | |
1074 | insn.addr = fi.addr; | |
1075 | insn.frag = fi.frag; | |
1076 | insn.num_fixups = fi.num_fixups; | |
1077 | for (i = 0; i < fi.num_fixups; ++i) | |
1078 | insn.fixups[i] = fi.fixups[i]; | |
1079 | } | |
b6930bdf NC |
1080 | |
1081 | /* start-sanitize-m32rx */ | |
b6930bdf NC |
1082 | if (swap) |
1083 | { | |
defc70bf | 1084 | int i,tmp; |
f2980bb4 | 1085 | |
b6930bdf NC |
1086 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp |
1087 | ||
1088 | /* Swap the two insns */ | |
1089 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
1090 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
1091 | ||
1092 | make_parallel (insn.addr); | |
1093 | ||
1094 | /* Swap any relaxable frags recorded for the two insns. */ | |
defc70bf | 1095 | /* FIXME: Clarify. relaxation precludes parallel insns */ |
b6930bdf | 1096 | if (prev_insn.frag->fr_opcode == prev_insn.addr) |
b86c0dd3 | 1097 | prev_insn.frag->fr_opcode = insn.addr; |
b6930bdf | 1098 | else if (insn.frag->fr_opcode == insn.addr) |
b86c0dd3 | 1099 | insn.frag->fr_opcode = prev_insn.addr; |
b6930bdf | 1100 | |
defc70bf DE |
1101 | /* Update the addresses in any fixups. |
1102 | Note that we don't have to handle the case where each insn is in | |
1103 | a different frag as we ensure they're in the same frag above. */ | |
1104 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1105 | prev_insn.fixups[i]->fx_where += 2; | |
1106 | for (i = 0; i < insn.num_fixups; ++i) | |
1107 | insn.fixups[i]->fx_where -= 2; | |
1108 | } | |
b6930bdf | 1109 | /* end-sanitize-m32rx */ |
defc70bf DE |
1110 | |
1111 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1112 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1113 | if (on_32bit_boundary_p) | |
1114 | prev_insn = insn; | |
1115 | else | |
1116 | prev_insn.insn = NULL; | |
b6930bdf | 1117 | |
c8cf7e17 DE |
1118 | /* If the insn needs the following one to be on a 32 bit boundary |
1119 | (e.g. subroutine calls), fill this insn's slot. */ | |
defc70bf | 1120 | if (on_32bit_boundary_p |
f2980bb4 | 1121 | && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) |
c8cf7e17 | 1122 | fill_insn (0); |
c8cf7e17 | 1123 | |
775fdd0c | 1124 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
1125 | mark the fact so that we can emit an alignment directive for a |
1126 | following 32 bit insn if we see one. */ | |
f2980bb4 | 1127 | if (CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) |
775fdd0c NC |
1128 | seen_relaxable_p = 1; |
1129 | } | |
c8cf7e17 DE |
1130 | |
1131 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 1132 | prev_seg = now_seg; |
c8cf7e17 DE |
1133 | prev_subseg = now_subseg; |
1134 | } | |
1135 | ||
1136 | /* The syntax in the manual says constants begin with '#'. | |
1137 | We just ignore it. */ | |
1138 | ||
1139 | void | |
1140 | md_operand (expressionP) | |
ebde3f62 | 1141 | expressionS * expressionP; |
c8cf7e17 | 1142 | { |
ebde3f62 | 1143 | if (* input_line_pointer == '#') |
c8cf7e17 | 1144 | { |
ebde3f62 | 1145 | input_line_pointer ++; |
c8cf7e17 DE |
1146 | expression (expressionP); |
1147 | } | |
1148 | } | |
1149 | ||
1150 | valueT | |
1151 | md_section_align (segment, size) | |
ebde3f62 | 1152 | segT segment; |
c8cf7e17 DE |
1153 | valueT size; |
1154 | { | |
1155 | int align = bfd_get_section_alignment (stdoutput, segment); | |
1156 | return ((size + (1 << align) - 1) & (-1 << align)); | |
1157 | } | |
1158 | ||
1159 | symbolS * | |
1160 | md_undefined_symbol (name) | |
ebde3f62 | 1161 | char * name; |
c8cf7e17 DE |
1162 | { |
1163 | return 0; | |
1164 | } | |
1165 | \f | |
1166 | /* .scomm pseudo-op handler. | |
1167 | ||
1168 | This is a new pseudo-op to handle putting objects in .scommon. | |
1169 | By doing this the linker won't need to do any work and more importantly | |
1170 | it removes the implicit -G arg necessary to correctly link the object file. | |
1171 | */ | |
1172 | ||
1173 | static void | |
1174 | m32r_scomm (ignore) | |
1175 | int ignore; | |
1176 | { | |
ebde3f62 NC |
1177 | register char * name; |
1178 | register char c; | |
1179 | register char * p; | |
1180 | offsetT size; | |
1181 | register symbolS * symbolP; | |
1182 | offsetT align; | |
1183 | int align2; | |
c8cf7e17 DE |
1184 | |
1185 | name = input_line_pointer; | |
1186 | c = get_symbol_end (); | |
1187 | ||
1188 | /* just after name is now '\0' */ | |
1189 | p = input_line_pointer; | |
ebde3f62 | 1190 | * p = c; |
c8cf7e17 | 1191 | SKIP_WHITESPACE (); |
ebde3f62 | 1192 | if (* input_line_pointer != ',') |
c8cf7e17 | 1193 | { |
48401fcf | 1194 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); |
c8cf7e17 DE |
1195 | ignore_rest_of_line (); |
1196 | return; | |
1197 | } | |
1198 | ||
b6930bdf | 1199 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
1200 | if ((size = get_absolute_expression ()) < 0) |
1201 | { | |
ca6a899d | 1202 | /* xgettext:c-format */ |
48401fcf | 1203 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
c8cf7e17 DE |
1204 | ignore_rest_of_line (); |
1205 | return; | |
1206 | } | |
1207 | ||
1208 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 1209 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
1210 | align = 8; |
1211 | else | |
1212 | { | |
ebde3f62 | 1213 | ++ input_line_pointer; |
c8cf7e17 DE |
1214 | align = get_absolute_expression (); |
1215 | if (align <= 0) | |
1216 | { | |
48401fcf | 1217 | as_warn (_("ignoring bad alignment")); |
c8cf7e17 DE |
1218 | align = 8; |
1219 | } | |
1220 | } | |
1221 | /* Convert to a power of 2 alignment. */ | |
1222 | if (align) | |
1223 | { | |
ebde3f62 | 1224 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
1225 | continue; |
1226 | if (align != 1) | |
1227 | { | |
48401fcf | 1228 | as_bad (_("Common alignment not a power of 2")); |
c8cf7e17 DE |
1229 | ignore_rest_of_line (); |
1230 | return; | |
1231 | } | |
1232 | } | |
1233 | else | |
1234 | align2 = 0; | |
1235 | ||
ebde3f62 | 1236 | * p = 0; |
c8cf7e17 | 1237 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 1238 | * p = c; |
c8cf7e17 DE |
1239 | |
1240 | if (S_IS_DEFINED (symbolP)) | |
1241 | { | |
ca6a899d | 1242 | /* xgettext:c-format */ |
48401fcf | 1243 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
c8cf7e17 DE |
1244 | S_GET_NAME (symbolP)); |
1245 | ignore_rest_of_line (); | |
1246 | return; | |
1247 | } | |
1248 | ||
1249 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1250 | { | |
ca6a899d | 1251 | /* xgettext:c-format */ |
48401fcf | 1252 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
c8cf7e17 DE |
1253 | S_GET_NAME (symbolP), |
1254 | (long) S_GET_VALUE (symbolP), | |
1255 | (long) size); | |
1256 | ||
1257 | ignore_rest_of_line (); | |
1258 | return; | |
1259 | } | |
1260 | ||
1261 | if (symbolP->local) | |
1262 | { | |
ebde3f62 NC |
1263 | segT old_sec = now_seg; |
1264 | int old_subsec = now_subseg; | |
1265 | char * pfrag; | |
c8cf7e17 DE |
1266 | |
1267 | record_alignment (sbss_section, align2); | |
1268 | subseg_set (sbss_section, 0); | |
775fdd0c | 1269 | |
c8cf7e17 DE |
1270 | if (align2) |
1271 | frag_align (align2, 0, 0); | |
775fdd0c | 1272 | |
c8cf7e17 DE |
1273 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
1274 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 1275 | |
c8cf7e17 | 1276 | symbolP->sy_frag = frag_now; |
b6930bdf | 1277 | |
c8cf7e17 DE |
1278 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1279 | (char *) 0); | |
ebde3f62 | 1280 | * pfrag = 0; |
c8cf7e17 DE |
1281 | S_SET_SIZE (symbolP, size); |
1282 | S_SET_SEGMENT (symbolP, sbss_section); | |
1283 | S_CLEAR_EXTERNAL (symbolP); | |
1284 | subseg_set (old_sec, old_subsec); | |
1285 | } | |
1286 | else | |
1287 | { | |
1288 | S_SET_VALUE (symbolP, (valueT) size); | |
1289 | S_SET_ALIGN (symbolP, align2); | |
1290 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 1291 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
1292 | } |
1293 | ||
1294 | demand_empty_rest_of_line (); | |
1295 | } | |
1296 | \f | |
1297 | /* Interface to relax_segment. */ | |
1298 | ||
1299 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1300 | ||
1301 | const relax_typeS md_relax_table[] = | |
1302 | { | |
1303 | /* The fields are: | |
1304 | 1) most positive reach of this state, | |
1305 | 2) most negative reach of this state, | |
1306 | 3) how many bytes this mode will add to the size of the current frag | |
1307 | 4) which index into the table to try if we can't fit into this one. */ | |
1308 | ||
1309 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1310 | each list. */ | |
1311 | {1, 1, 0, 0}, | |
1312 | ||
1313 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1314 | so we subtract 2 from the following. */ | |
1315 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1316 | This doesn't handle a branch in the right slot at the border: | |
1317 | the "& -4" isn't taken into account. It's not important enough to | |
1318 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1319 | case). */ | |
1320 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1321 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1322 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1323 | /* Same thing, but with leading nop for alignment. */ | |
1324 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1325 | }; | |
1326 | ||
1327 | long | |
1328 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1329 | fragS * fragP; |
1330 | long stretch; | |
c8cf7e17 DE |
1331 | { |
1332 | /* Address of branch insn. */ | |
1333 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1334 | long growth = 0; | |
1335 | ||
1336 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1337 | if (fragP->fr_subtype == 2) | |
1338 | { | |
1339 | if ((address & 3) != 0) | |
1340 | { | |
1341 | fragP->fr_subtype = 3; | |
1342 | growth = 2; | |
1343 | } | |
1344 | } | |
1345 | else if (fragP->fr_subtype == 3) | |
1346 | { | |
1347 | if ((address & 3) == 0) | |
1348 | { | |
1349 | fragP->fr_subtype = 2; | |
1350 | growth = -2; | |
1351 | } | |
1352 | } | |
1353 | else | |
1354 | { | |
1355 | growth = relax_frag (fragP, stretch); | |
1356 | ||
1357 | /* Long jump on odd halfword boundary? */ | |
1358 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1359 | { | |
1360 | fragP->fr_subtype = 3; | |
1361 | growth += 2; | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | return growth; | |
1366 | } | |
1367 | ||
1368 | /* Return an initial guess of the length by which a fragment must grow to | |
1369 | hold a branch to reach its destination. | |
1370 | Also updates fr_type/fr_subtype as necessary. | |
1371 | ||
1372 | Called just before doing relaxation. | |
1373 | Any symbol that is now undefined will not become defined. | |
1374 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1375 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1376 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1377 | 0 value. */ | |
1378 | ||
1379 | int | |
1380 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1381 | fragS * fragP; |
1382 | segT segment; | |
c8cf7e17 | 1383 | { |
ebde3f62 NC |
1384 | int old_fr_fix = fragP->fr_fix; |
1385 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1386 | |
1387 | /* The only thing we have to handle here are symbols outside of the | |
1388 | current segment. They may be undefined or in a different segment in | |
1389 | which case linker scripts may place them anywhere. | |
1390 | However, we can't finish the fragment here and emit the reloc as insn | |
1391 | alignment requirements may move the insn about. */ | |
1392 | ||
1393 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1394 | { | |
1395 | /* The symbol is undefined in this segment. | |
1396 | Change the relaxation subtype to the max allowable and leave | |
1397 | all further handling to md_convert_frag. */ | |
1398 | fragP->fr_subtype = 2; | |
1399 | ||
1400 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1401 | /* Change 16 bit insn to 32 bit insn. */ | |
1402 | opcode[0] |= 0x80; | |
1403 | ||
1404 | /* Increase known (fixed) size of fragment. */ | |
1405 | fragP->fr_fix += 2; | |
1406 | ||
1407 | /* Create a relocation for it. */ | |
1408 | fix_new (fragP, old_fr_fix, 4, | |
1409 | fragP->fr_symbol, | |
1410 | fragP->fr_offset, 1 /* pcrel */, | |
1411 | /* FIXME: Can't use a real BFD reloc here. | |
1412 | cgen_md_apply_fix3 can't handle it. */ | |
1413 | BFD_RELOC_M32R_26_PCREL); | |
1414 | ||
1415 | /* Mark this fragment as finished. */ | |
1416 | frag_wane (fragP); | |
1417 | #else | |
a450e9f4 | 1418 | { |
ebde3f62 NC |
1419 | const CGEN_INSN * insn; |
1420 | int i; | |
a450e9f4 NC |
1421 | |
1422 | /* Update the recorded insn. | |
1423 | Fortunately we don't have to look very far. | |
1424 | FIXME: Change this to record in the instruction the next higher | |
1425 | relaxable insn to use. */ | |
1426 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1427 | { | |
b5e9e562 DE |
1428 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1429 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1430 | == 0) |
1431 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1432 | break; | |
1433 | } | |
1434 | if (i == 4) | |
1435 | abort (); | |
b6930bdf | 1436 | |
a450e9f4 NC |
1437 | fragP->fr_cgen.insn = insn; |
1438 | return 2; | |
1439 | } | |
c8cf7e17 DE |
1440 | #endif |
1441 | } | |
1442 | ||
1443 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1444 | } | |
1445 | ||
1446 | /* *fragP has been relaxed to its final size, and now needs to have | |
1447 | the bytes inside it modified to conform to the new size. | |
1448 | ||
1449 | Called after relaxation is finished. | |
1450 | fragP->fr_type == rs_machine_dependent. | |
1451 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1452 | ||
1453 | void | |
1454 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1455 | bfd * abfd; |
1456 | segT sec; | |
1457 | fragS * fragP; | |
c8cf7e17 | 1458 | { |
ebde3f62 NC |
1459 | char * opcode; |
1460 | char * displacement; | |
1461 | int target_address; | |
1462 | int opcode_address; | |
1463 | int extension; | |
1464 | int addend; | |
c8cf7e17 DE |
1465 | |
1466 | opcode = fragP->fr_opcode; | |
1467 | ||
1468 | /* Address opcode resides at in file space. */ | |
1469 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1470 | ||
1471 | switch (fragP->fr_subtype) | |
1472 | { | |
1473 | case 1 : | |
1474 | extension = 0; | |
ebde3f62 | 1475 | displacement = & opcode[1]; |
c8cf7e17 DE |
1476 | break; |
1477 | case 2 : | |
1478 | opcode[0] |= 0x80; | |
1479 | extension = 2; | |
ebde3f62 | 1480 | displacement = & opcode[1]; |
c8cf7e17 DE |
1481 | break; |
1482 | case 3 : | |
1483 | opcode[2] = opcode[0] | 0x80; | |
1484 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1485 | opcode_address += 2; | |
1486 | extension = 4; | |
ebde3f62 | 1487 | displacement = & opcode[3]; |
c8cf7e17 DE |
1488 | break; |
1489 | default : | |
1490 | abort (); | |
1491 | } | |
1492 | ||
1493 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1494 | { | |
1495 | /* symbol must be resolved by linker */ | |
1496 | if (fragP->fr_offset & 3) | |
48401fcf | 1497 | as_warn (_("Addend to unresolved symbol not on word boundary.")); |
c8cf7e17 DE |
1498 | addend = fragP->fr_offset >> 2; |
1499 | } | |
1500 | else | |
1501 | { | |
1502 | /* Address we want to reach in file space. */ | |
1503 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1504 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1505 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1506 | } | |
1507 | ||
1508 | /* Create a relocation for symbols that must be resolved by the linker. | |
1509 | Otherwise output the completed insn. */ | |
1510 | ||
1511 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1512 | { | |
1513 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1514 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1515 | cgen_record_fixup (fragP, |
1516 | /* Offset of branch insn in frag. */ | |
1517 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1518 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1519 | 4 /*length*/, |
1520 | /* FIXME: quick hack */ | |
1521 | #if 0 | |
a450e9f4 | 1522 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1523 | #else |
1524 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1525 | #endif | |
a450e9f4 | 1526 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1527 | fragP->fr_symbol, fragP->fr_offset); |
1528 | } | |
1529 | ||
1530 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1531 | ||
1532 | md_number_to_chars (displacement, (valueT) addend, | |
1533 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1534 | ||
1535 | fragP->fr_fix += extension; | |
1536 | } | |
1537 | \f | |
1538 | /* Functions concerning relocs. */ | |
1539 | ||
1540 | /* The location from which a PC relative jump should be calculated, | |
1541 | given a PC relative reloc. */ | |
1542 | ||
1543 | long | |
1544 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1545 | fixS * fixP; |
1546 | segT sec; | |
c8cf7e17 DE |
1547 | { |
1548 | if (fixP->fx_addsy != (symbolS *) NULL | |
1549 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1550 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1551 | { | |
1552 | /* The symbol is undefined (or is defined but not in this section). | |
1553 | Let the linker figure it out. */ | |
1554 | return 0; | |
1555 | } | |
1556 | ||
1557 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1558 | } | |
1559 | ||
1560 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1561 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1562 | *FIXP may be modified if desired. */ | |
1563 | ||
1564 | bfd_reloc_code_real_type | |
1565 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1566 | const CGEN_INSN * insn; |
1567 | const CGEN_OPERAND * operand; | |
1568 | fixS * fixP; | |
c8cf7e17 DE |
1569 | { |
1570 | switch (CGEN_OPERAND_TYPE (operand)) | |
1571 | { | |
1572 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1573 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1574 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1575 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1576 | case M32R_OPERAND_HI16 : | |
1577 | case M32R_OPERAND_SLO16 : | |
1578 | case M32R_OPERAND_ULO16 : | |
1579 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1580 | if (fixP->tc_fix_data.opinfo != 0) | |
1581 | return fixP->tc_fix_data.opinfo; | |
1582 | break; | |
1583 | } | |
1584 | return BFD_RELOC_NONE; | |
1585 | } | |
1586 | ||
b6930bdf NC |
1587 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1588 | ||
1589 | static void | |
1590 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1591 | int reloc_type; | |
1592 | fixS * fixP; | |
1593 | segT seg; | |
1594 | { | |
1595 | struct m32r_hi_fixup * hi_fixup; | |
1596 | ||
1597 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1598 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1599 | ||
1600 | hi_fixup = ((struct m32r_hi_fixup *) | |
1601 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1602 | hi_fixup->fixp = fixP; | |
1603 | hi_fixup->seg = now_seg; | |
1604 | hi_fixup->next = m32r_hi_fixup_list; | |
1605 | ||
1606 | m32r_hi_fixup_list = hi_fixup; | |
1607 | } | |
1608 | ||
c8cf7e17 DE |
1609 | /* Called while parsing an instruction to create a fixup. |
1610 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1611 | ||
1612 | fixS * | |
1613 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1614 | fragS * frag; |
1615 | int where; | |
1616 | const CGEN_INSN * insn; | |
1617 | int length; | |
1618 | const CGEN_OPERAND * operand; | |
1619 | int opinfo; | |
1620 | expressionS * exp; | |
c8cf7e17 | 1621 | { |
ebde3f62 NC |
1622 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1623 | operand, opinfo, exp); | |
c8cf7e17 DE |
1624 | |
1625 | switch (CGEN_OPERAND_TYPE (operand)) | |
1626 | { | |
1627 | case M32R_OPERAND_HI16 : | |
1628 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1629 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1630 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1631 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1632 | break; | |
1633 | } | |
1634 | ||
1635 | return fixP; | |
1636 | } | |
1637 | ||
c8cf7e17 DE |
1638 | /* Return BFD reloc type from opinfo field in a fixS. |
1639 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1640 | are BFD_RELOC_UNUSED + operand number. */ | |
1641 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1642 | ||
1643 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1644 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1645 | tc_gen_reloc. */ | |
1646 | ||
1647 | void | |
1648 | m32r_frob_file () | |
1649 | { | |
ebde3f62 | 1650 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1651 | |
1652 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1653 | { | |
ebde3f62 NC |
1654 | segment_info_type * seginfo; |
1655 | int pass; | |
c8cf7e17 DE |
1656 | |
1657 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1658 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1659 | ||
1660 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1661 | if (l->fixp->fx_next != NULL | |
1662 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1663 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1664 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1665 | continue; | |
1666 | ||
1667 | /* Look through the fixups for this segment for a matching `low'. | |
1668 | When we find one, move the high/shigh just in front of it. We do | |
1669 | this in two passes. In the first pass, we try to find a | |
1670 | unique `low'. In the second pass, we permit multiple high's | |
1671 | relocs for a single `low'. */ | |
1672 | seginfo = seg_info (l->seg); | |
1673 | for (pass = 0; pass < 2; pass++) | |
1674 | { | |
ebde3f62 NC |
1675 | fixS * f; |
1676 | fixS * prev; | |
c8cf7e17 DE |
1677 | |
1678 | prev = NULL; | |
1679 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1680 | { | |
1681 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1682 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1683 | && f->fx_addsy == l->fixp->fx_addsy | |
1684 | && f->fx_offset == l->fixp->fx_offset | |
1685 | && (pass == 1 | |
1686 | || prev == NULL | |
1687 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1688 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1689 | || prev->fx_addsy != f->fx_addsy | |
1690 | || prev->fx_offset != f->fx_offset)) | |
1691 | { | |
ebde3f62 | 1692 | fixS ** pf; |
c8cf7e17 DE |
1693 | |
1694 | /* Move l->fixp before f. */ | |
1695 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1696 | * pf != l->fixp; |
1697 | pf = & (* pf)->fx_next) | |
1698 | assert (* pf != NULL); | |
c8cf7e17 | 1699 | |
ebde3f62 | 1700 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1701 | |
1702 | l->fixp->fx_next = f; | |
1703 | if (prev == NULL) | |
1704 | seginfo->fix_root = l->fixp; | |
1705 | else | |
1706 | prev->fx_next = l->fixp; | |
1707 | ||
1708 | break; | |
1709 | } | |
1710 | ||
1711 | prev = f; | |
1712 | } | |
1713 | ||
1714 | if (f != NULL) | |
1715 | break; | |
1716 | ||
7c629878 DE |
1717 | if (pass == 1 |
1718 | && warn_unmatched_high) | |
c8cf7e17 | 1719 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, |
48401fcf | 1720 | _("Unmatched high/shigh reloc")); |
c8cf7e17 DE |
1721 | } |
1722 | } | |
1723 | } | |
1724 | ||
1725 | /* See whether we need to force a relocation into the output file. | |
1726 | This is used to force out switch and PC relative relocations when | |
1727 | relaxing. */ | |
1728 | ||
1729 | int | |
1730 | m32r_force_relocation (fix) | |
ebde3f62 | 1731 | fixS * fix; |
c8cf7e17 DE |
1732 | { |
1733 | if (! m32r_relax) | |
1734 | return 0; | |
1735 | ||
1736 | return (fix->fx_pcrel | |
1737 | || 0 /* ??? */); | |
1738 | } | |
1739 | \f | |
1740 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1741 | ||
1742 | void | |
1743 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1744 | char * buf; |
c8cf7e17 | 1745 | valueT val; |
ebde3f62 | 1746 | int n; |
c8cf7e17 DE |
1747 | { |
1748 | if (target_big_endian) | |
1749 | number_to_chars_bigendian (buf, val, n); | |
1750 | else | |
1751 | number_to_chars_littleendian (buf, val, n); | |
1752 | } | |
1753 | ||
1754 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1755 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1756 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1757 | */ | |
1758 | ||
1759 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1760 | #define MAX_LITTLENUMS 6 | |
1761 | ||
1762 | char * | |
1763 | md_atof (type, litP, sizeP) | |
1764 | char type; | |
1765 | char *litP; | |
1766 | int *sizeP; | |
1767 | { | |
ebde3f62 NC |
1768 | int i; |
1769 | int prec; | |
1770 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1771 | LITTLENUM_TYPE * wordP; | |
1772 | char * t; | |
1773 | char * atof_ieee (); | |
c8cf7e17 DE |
1774 | |
1775 | switch (type) | |
1776 | { | |
1777 | case 'f': | |
1778 | case 'F': | |
1779 | case 's': | |
1780 | case 'S': | |
1781 | prec = 2; | |
1782 | break; | |
1783 | ||
1784 | case 'd': | |
1785 | case 'D': | |
1786 | case 'r': | |
1787 | case 'R': | |
1788 | prec = 4; | |
1789 | break; | |
1790 | ||
1791 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1792 | ||
1793 | default: | |
ebde3f62 | 1794 | * sizeP = 0; |
48401fcf | 1795 | return _("Bad call to md_atof()"); |
c8cf7e17 DE |
1796 | } |
1797 | ||
1798 | t = atof_ieee (input_line_pointer, type, words); | |
1799 | if (t) | |
1800 | input_line_pointer = t; | |
ebde3f62 | 1801 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1802 | |
1803 | if (target_big_endian) | |
1804 | { | |
1805 | for (i = 0; i < prec; i++) | |
1806 | { | |
ebde3f62 NC |
1807 | md_number_to_chars (litP, (valueT) words[i], |
1808 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1809 | litP += sizeof (LITTLENUM_TYPE); |
1810 | } | |
1811 | } | |
1812 | else | |
1813 | { | |
1814 | for (i = prec - 1; i >= 0; i--) | |
1815 | { | |
ebde3f62 NC |
1816 | md_number_to_chars (litP, (valueT) words[i], |
1817 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1818 | litP += sizeof (LITTLENUM_TYPE); |
1819 | } | |
1820 | } | |
1821 | ||
1822 | return 0; | |
1823 | } | |
48401fcf TT |
1824 | |
1825 | void | |
1826 | m32r_elf_section_change_hook () | |
1827 | { | |
1828 | /* If we have reached the end of a section and we have just emitted a | |
1829 | 16 bit insn, then emit a nop to make sure that the section ends on | |
1830 | a 32 bit boundary. */ | |
1831 | ||
1832 | if (prev_insn.insn || seen_relaxable_p) | |
1833 | (void) m32r_fill_insn (0); | |
1834 | } |