Commit | Line | Data |
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76090fdd | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "cgen-opc.h" | |
26 | ||
b6930bdf NC |
27 | typedef struct |
28 | { | |
29 | const CGEN_INSN * insn; | |
30 | CGEN_FIELDS fields; | |
31 | #ifdef CGEN_INT_INSN | |
32 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
33 | #else | |
34 | char buffer [CGEN_MAX_INSN_SIZE]; | |
35 | #endif | |
36 | char * addr; | |
37 | fragS * frag; | |
6cf2575a | 38 | int indices [MAX_OPERAND_INSTANCES]; |
b6930bdf NC |
39 | } |
40 | m32r_insn; | |
41 | ||
42 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
43 | boundary (i.e. was the first of two 16 bit insns). */ | |
44 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
45 | |
46 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
47 | alignment request. */ | |
48 | static int seen_relaxable_p = 0; | |
49 | ||
50 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
51 | for the linker to do relaxing. | |
52 | We do simple forms of relaxing internally, but they are always done. | |
53 | This flag does not apply to them. */ | |
54 | static int m32r_relax; | |
55 | ||
56 | /* If non-NULL, pointer to cpu description file to read. | |
57 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 58 | static char * m32r_cpu_desc; |
c8cf7e17 | 59 | |
b5e9e562 | 60 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
61 | /* Non-zero if -m32rx has been specified, in which case support for the |
62 | extended M32RX instruction set should be enabled. */ | |
a450e9f4 | 63 | static int enable_m32rx = 0; |
b6930bdf NC |
64 | |
65 | /* Non-zero if the programmer should be warned when an explicit parallel | |
66 | instruction might have constraint violations. */ | |
67 | static int warn_explicit_parallel_conflicts = 1; | |
b5e9e562 | 68 | /* end-sanitize-m32rx */ |
a450e9f4 | 69 | |
c8cf7e17 | 70 | /* stuff for .scomm symbols. */ |
ebde3f62 | 71 | static segT sbss_section; |
c8cf7e17 | 72 | static asection scom_section; |
ebde3f62 | 73 | static asymbol scom_symbol; |
c8cf7e17 | 74 | |
ebde3f62 NC |
75 | const char comment_chars[] = ";"; |
76 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 77 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
78 | const char EXP_CHARS[] = "eE"; |
79 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
80 | |
81 | /* Relocations against symbols are done in two | |
82 | parts, with a HI relocation and a LO relocation. Each relocation | |
83 | has only 16 bits of space to store an addend. This means that in | |
84 | order for the linker to handle carries correctly, it must be able | |
85 | to locate both the HI and the LO relocation. This means that the | |
86 | relocations must appear in order in the relocation table. | |
87 | ||
88 | In order to implement this, we keep track of each unmatched HI | |
89 | relocation. We then sort them so that they immediately precede the | |
90 | corresponding LO relocation. */ | |
91 | ||
92 | struct m32r_hi_fixup | |
93 | { | |
ebde3f62 NC |
94 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
95 | fixS * fixp; /* This fixup. */ | |
96 | segT seg; /* The section this fixup is in. */ | |
97 | ||
c8cf7e17 DE |
98 | }; |
99 | ||
100 | /* The list of unmatched HI relocs. */ | |
101 | ||
ebde3f62 | 102 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 103 | |
a450e9f4 | 104 | \f |
b5e9e562 | 105 | /* start-sanitize-m32rx */ |
a450e9f4 | 106 | static void |
55a4759f DE |
107 | allow_m32rx (on) |
108 | int on; | |
a450e9f4 NC |
109 | { |
110 | enable_m32rx = on; | |
111 | ||
112 | if (stdoutput != NULL) | |
ebde3f62 NC |
113 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
114 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 115 | } |
b5e9e562 | 116 | /* end-sanitize-m32rx */ |
c8cf7e17 | 117 | \f |
ebde3f62 | 118 | const char * md_shortopts = ""; |
c8cf7e17 | 119 | |
a450e9f4 NC |
120 | struct option md_longopts[] = |
121 | { | |
b5e9e562 | 122 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
123 | #define OPTION_M32RX (OPTION_MD_BASE) |
124 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
b6930bdf NC |
125 | #define OPTION_WARN (OPTION_MD_BASE + 1) |
126 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN}, | |
127 | #define OPTION_NO_WARN (OPTION_MD_BASE + 2) | |
128 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, | |
b5e9e562 | 129 | /* end-sanitize-m32rx */ |
a450e9f4 | 130 | |
c8cf7e17 | 131 | #if 0 /* not supported yet */ |
b6930bdf | 132 | #define OPTION_RELAX (OPTION_MD_BASE + 3) |
c8cf7e17 | 133 | {"relax", no_argument, NULL, OPTION_RELAX}, |
b6930bdf | 134 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 4) |
c8cf7e17 DE |
135 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
136 | #endif | |
a450e9f4 | 137 | |
c8cf7e17 DE |
138 | {NULL, no_argument, NULL, 0} |
139 | }; | |
ebde3f62 | 140 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
141 | |
142 | int | |
143 | md_parse_option (c, arg) | |
ebde3f62 NC |
144 | int c; |
145 | char * arg; | |
c8cf7e17 DE |
146 | { |
147 | switch (c) | |
148 | { | |
b5e9e562 | 149 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
150 | case OPTION_M32RX: |
151 | allow_m32rx (1); | |
152 | break; | |
b6930bdf NC |
153 | |
154 | case OPTION_WARN: | |
155 | warn_explicit_parallel_conflicts = 1; | |
156 | break; | |
157 | ||
158 | case OPTION_NO_WARN: | |
159 | warn_explicit_parallel_conflicts = 0; | |
160 | break; | |
b5e9e562 | 161 | /* end-sanitize-m32rx */ |
a450e9f4 | 162 | |
c8cf7e17 DE |
163 | #if 0 /* not supported yet */ |
164 | case OPTION_RELAX: | |
165 | m32r_relax = 1; | |
166 | break; | |
167 | case OPTION_CPU_DESC: | |
168 | m32r_cpu_desc = arg; | |
169 | break; | |
170 | #endif | |
171 | default: | |
172 | return 0; | |
173 | } | |
174 | return 1; | |
175 | } | |
176 | ||
177 | void | |
178 | md_show_usage (stream) | |
ebde3f62 | 179 | FILE * stream; |
c8cf7e17 | 180 | { |
a450e9f4 | 181 | fprintf (stream, "M32R/X options:\n"); |
b5e9e562 | 182 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
183 | fprintf (stream, "\ |
184 | --m32rx support the extended m32rx instruction set\n"); | |
b6930bdf NC |
185 | |
186 | fprintf (stream, "\ | |
00aa5b17 DE |
187 | --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n"); |
188 | fprintf (stream, "\ | |
b6930bdf | 189 | --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n"); |
b5e9e562 | 190 | /* end-sanitize-m32rx */ |
a450e9f4 | 191 | |
c8cf7e17 DE |
192 | #if 0 |
193 | fprintf (stream, "\ | |
194 | --relax create linker relaxable code\n"); | |
195 | fprintf (stream, "\ | |
196 | --cpu-desc provide runtime cpu description file\n"); | |
c8cf7e17 DE |
197 | #endif |
198 | } | |
199 | ||
200 | static void fill_insn PARAMS ((int)); | |
201 | static void m32r_scomm PARAMS ((int)); | |
202 | ||
203 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
204 | static subsegT prev_subseg; | |
205 | static segT prev_seg; | |
206 | ||
207 | /* The target specific pseudo-ops which we support. */ | |
208 | const pseudo_typeS md_pseudo_table[] = | |
209 | { | |
210 | { "word", cons, 4 }, | |
211 | { "fillinsn", fill_insn, 0 }, | |
212 | { "scomm", m32r_scomm, 0 }, | |
b5e9e562 | 213 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
214 | { "m32r", allow_m32rx, 0}, |
215 | { "m32rx", allow_m32rx, 1}, | |
b5e9e562 | 216 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
217 | { NULL, NULL, 0 } |
218 | }; | |
219 | ||
220 | /* FIXME: Should be machine generated. */ | |
221 | #define NOP_INSN 0x7000 | |
222 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
223 | ||
224 | /* When we align the .text section, insert the correct NOP pattern. | |
225 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
226 | MAX is the maximum number of characters to skip when doing the alignment, | |
227 | or 0 if there is no maximum. */ | |
228 | ||
229 | int | |
230 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
231 | int n; |
232 | const char * fill; | |
233 | int len; | |
234 | int max; | |
c8cf7e17 | 235 | { |
ebde3f62 | 236 | if ((fill == NULL || (* fill == 0 && len == 1)) |
c8cf7e17 DE |
237 | && (now_seg->flags & SEC_CODE) != 0 |
238 | /* Only do this special handling if aligning to at least a | |
239 | 4 byte boundary. */ | |
240 | && n > 1 | |
775fdd0c | 241 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
242 | least two bytes. */ |
243 | && (max == 0 || max > 1)) | |
244 | { | |
245 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
246 | ||
247 | #if 0 | |
248 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
249 | /* FIXME: How much memory will cause gas to use when assembling a big | |
250 | program? Perhaps we can avoid the frag_align call? */ | |
251 | frag_align (1, 0, 0); | |
252 | #endif | |
253 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
254 | nop. */ | |
255 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
256 | /* If doing larger alignments use a repeating sequence of appropriate | |
257 | nops. */ | |
258 | if (n > 2) | |
259 | { | |
ebde3f62 NC |
260 | static const unsigned char multi_nop_pattern[] = |
261 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
262 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
263 | max ? max - 2 : 0); | |
264 | } | |
265 | return 1; | |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static void | |
272 | assemble_nop (opcode) | |
273 | int opcode; | |
274 | { | |
ebde3f62 | 275 | char * f = frag_more (2); |
c8cf7e17 DE |
276 | md_number_to_chars (f, opcode, 2); |
277 | } | |
278 | ||
279 | /* If the last instruction was the first of 2 16 bit insns, | |
280 | output a nop to move the PC to a 32 bit boundary. | |
281 | ||
282 | This is done via an alignment specification since branch relaxing | |
283 | may make it unnecessary. | |
284 | ||
285 | Internally, we need to output one of these each time a 32 bit insn is | |
286 | seen after an insn that is relaxable. */ | |
287 | ||
288 | static void | |
289 | fill_insn (ignore) | |
290 | int ignore; | |
291 | { | |
292 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 293 | prev_insn.insn = NULL; |
c8cf7e17 DE |
294 | seen_relaxable_p = 0; |
295 | } | |
296 | ||
297 | /* Cover function to fill_insn called after a label and at end of assembly. | |
298 | ||
299 | The result is always 1: we're called in a conditional to see if the | |
300 | current line is a label. */ | |
301 | ||
302 | int | |
303 | m32r_fill_insn (done) | |
304 | int done; | |
305 | { | |
ebde3f62 | 306 | segT seg; |
c8cf7e17 DE |
307 | subsegT subseg; |
308 | ||
309 | if (prev_seg != NULL) | |
310 | { | |
ebde3f62 | 311 | seg = now_seg; |
c8cf7e17 | 312 | subseg = now_subseg; |
ebde3f62 | 313 | |
c8cf7e17 | 314 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 315 | |
c8cf7e17 | 316 | fill_insn (0); |
ebde3f62 | 317 | |
c8cf7e17 DE |
318 | subseg_set (seg, subseg); |
319 | } | |
ebde3f62 | 320 | |
c8cf7e17 DE |
321 | return 1; |
322 | } | |
323 | \f | |
324 | void | |
325 | md_begin () | |
326 | { | |
327 | flagword applicable; | |
ebde3f62 NC |
328 | segT seg; |
329 | subsegT subseg; | |
c8cf7e17 DE |
330 | |
331 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
332 | |
333 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 334 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 335 | |
4e9d8dea | 336 | /* Set the machine number and endian. */ |
c8cf7e17 | 337 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
338 | target_big_endian ? |
339 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
340 | |
341 | #if 0 /* not supported yet */ | |
342 | /* If a runtime cpu description file was provided, parse it. */ | |
343 | if (m32r_cpu_desc != NULL) | |
344 | { | |
ebde3f62 | 345 | const char * errmsg; |
c8cf7e17 DE |
346 | |
347 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
348 | if (errmsg != NULL) | |
349 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
350 | } | |
351 | #endif | |
352 | ||
353 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
354 | we don't want the initial section to be .sbss]. */ |
355 | seg = now_seg; | |
c8cf7e17 DE |
356 | subseg = now_subseg; |
357 | ||
358 | /* The sbss section is for local .scomm symbols. */ | |
359 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 360 | |
c8cf7e17 DE |
361 | /* This is copied from perform_an_assembly_pass. */ |
362 | applicable = bfd_applicable_section_flags (stdoutput); | |
363 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 364 | |
c8cf7e17 DE |
365 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
366 | seg_info (bss_section)->bss = 1; | |
367 | #endif | |
368 | ||
369 | subseg_set (seg, subseg); | |
370 | ||
371 | /* We must construct a fake section similar to bfd_com_section | |
372 | but with the name .scommon. */ | |
ebde3f62 NC |
373 | scom_section = bfd_com_section; |
374 | scom_section.name = ".scommon"; | |
375 | scom_section.output_section = & scom_section; | |
376 | scom_section.symbol = & scom_symbol; | |
377 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
378 | scom_symbol = * bfd_com_section.symbol; | |
379 | scom_symbol.name = ".scommon"; | |
380 | scom_symbol.section = & scom_section; | |
a450e9f4 | 381 | |
b5e9e562 | 382 | /* start-sanitize-m32rx */ |
a450e9f4 | 383 | allow_m32rx (enable_m32rx); |
b5e9e562 | 384 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
385 | } |
386 | ||
89285fc9 | 387 | /* start-sanitize-m32rx */ |
55a4759f DE |
388 | #ifdef HAVE_CPU_M32RX |
389 | ||
6cf2575a NC |
390 | /* Returns true if an output of instruction 'a' is referenced by an operand |
391 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
392 | checked, otherwise its inputs are examined. */ | |
ebde3f62 | 393 | static int |
6cf2575a | 394 | first_writes_to_seconds_operands (a, b, check_outputs) |
26192c50 NC |
395 | m32r_insn * a; |
396 | m32r_insn * b; | |
6cf2575a | 397 | const int check_outputs; |
00aa5b17 | 398 | { |
c9cec4ef NC |
399 | const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn); |
400 | const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn); | |
6cf2575a | 401 | int a_index; |
00aa5b17 | 402 | |
c9cec4ef NC |
403 | /* If at least one of the instructions take sno opeands, then there is |
404 | nothing to check. There really are instructions without operands, | |
405 | eg 'nop'. */ | |
406 | if (a_operands == NULL || b_operands == NULL) | |
407 | return 0; | |
408 | ||
6cf2575a | 409 | /* Scan the operand list of 'a' looking for an output operand. */ |
c9cec4ef | 410 | for (a_index = 0; |
6cf2575a NC |
411 | CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END; |
412 | a_index ++, a_operands ++) | |
26192c50 | 413 | { |
6cf2575a | 414 | if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT) |
26192c50 | 415 | { |
c9cec4ef | 416 | int b_index; |
6cf2575a NC |
417 | |
418 | /* Scan operand list of 'b' looking for an operand that references | |
419 | the same hardware element, and which goes in the right direction. */ | |
c9cec4ef | 420 | for (b_index = 0; |
6cf2575a NC |
421 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; |
422 | b_index ++, b_operands ++) | |
423 | { | |
424 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
425 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
426 | && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands)) | |
427 | && (a->indices [a_index] == b->indices [b_index])) | |
428 | return 1; | |
429 | } | |
26192c50 NC |
430 | } |
431 | } | |
432 | ||
6cf2575a | 433 | return 0; |
26192c50 NC |
434 | } |
435 | ||
6cf2575a | 436 | /* Returns true if the insn can (potentially) alter the program counter. */ |
89285fc9 | 437 | static int |
6cf2575a | 438 | writes_to_pc (a) |
89285fc9 | 439 | m32r_insn * a; |
89285fc9 | 440 | { |
8e7a5a04 | 441 | #if 0 |
c9cec4ef | 442 | const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn); |
8e7a5a04 | 443 | |
c9cec4ef NC |
444 | if (a_operands == NULL) |
445 | return 0; | |
446 | ||
447 | while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END) | |
6cf2575a NC |
448 | { |
449 | if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL | |
450 | && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC) | |
451 | return 1; | |
c9cec4ef NC |
452 | |
453 | a_operands ++; | |
6cf2575a | 454 | } |
8e7a5a04 NC |
455 | #else |
456 | if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI) | |
457 | || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI)) | |
458 | return 1; | |
459 | #endif | |
6cf2575a | 460 | return 0; |
89285fc9 | 461 | } |
26192c50 | 462 | |
775fdd0c NC |
463 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
464 | otherwise it returns a pointer to an error message explaining why not. */ | |
465 | static const char * | |
26192c50 | 466 | can_make_parallel (a, b) |
b6930bdf NC |
467 | m32r_insn * a; |
468 | m32r_insn * b; | |
775fdd0c NC |
469 | { |
470 | PIPE_ATTR a_pipe; | |
471 | PIPE_ATTR b_pipe; | |
89285fc9 | 472 | |
775fdd0c | 473 | /* Make sure the instructions are the right length. */ |
b6930bdf NC |
474 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
475 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c | 476 | abort(); |
89285fc9 | 477 | |
6cf2575a | 478 | if (first_writes_to_seconds_operands (a, b, true)) |
89285fc9 | 479 | return "Instructions write to the same destination register."; |
775fdd0c | 480 | |
b6930bdf NC |
481 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
482 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 483 | |
b6930bdf | 484 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
485 | if ( a_pipe == PIPE_NONE |
486 | || b_pipe == PIPE_NONE) | |
487 | return "Instructions do not use parallel execution pipelines."; | |
89285fc9 NC |
488 | |
489 | /* Leave this test for last, since it is the only test that can | |
490 | go away if the instructions are swapped, and we want to make | |
491 | sure that any other errors are detected before this happens. */ | |
775fdd0c NC |
492 | if ( a_pipe == PIPE_S |
493 | || b_pipe == PIPE_O) | |
494 | return "Instructions share the same execution pipeline"; | |
89285fc9 | 495 | |
775fdd0c NC |
496 | return NULL; |
497 | } | |
775fdd0c NC |
498 | |
499 | #ifdef CGEN_INT_INSN | |
500 | static void | |
b6930bdf NC |
501 | make_parallel (buffer) |
502 | cgen_insn_t * buffer; | |
775fdd0c NC |
503 | { |
504 | /* Force the top bit of the second insn to be set. */ | |
505 | ||
506 | bfd_vma value; | |
507 | ||
508 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
509 | { | |
510 | value = bfd_getb16 ((bfd_byte *) buffer); | |
511 | value |= 0x8000; | |
512 | bfd_putb16 (value, (char *) buffer); | |
513 | } | |
514 | else | |
515 | { | |
516 | value = bfd_getl16 ((bfd_byte *) buffer); | |
517 | value |= 0x8000; | |
518 | bfd_putl16 (value, (char *) buffer); | |
519 | } | |
520 | } | |
521 | #else | |
522 | static void | |
b6930bdf NC |
523 | make_parallel (buffer) |
524 | char * buffer; | |
775fdd0c NC |
525 | { |
526 | /* Force the top bit of the second insn to be set. */ | |
527 | ||
528 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
529 | } | |
530 | #endif | |
531 | ||
532 | ||
b6930bdf NC |
533 | static void |
534 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 535 | char * str; |
b6930bdf | 536 | char * str2; |
c8cf7e17 | 537 | { |
b6930bdf NC |
538 | char * str3; |
539 | m32r_insn first; | |
540 | m32r_insn second; | |
541 | char * errmsg; | |
ebde3f62 | 542 | |
b6930bdf | 543 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 544 | |
b6930bdf NC |
545 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
546 | so that the parallel instruction will start on a 32 bit boundary. */ | |
547 | if (prev_insn.insn) | |
548 | fill_insn (0); | |
ebde3f62 | 549 | |
b6930bdf NC |
550 | /* Parse the first instruction. */ |
551 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
552 | (str, & first.fields, first.buffer, & errmsg))) | |
553 | { | |
554 | as_bad (errmsg); | |
555 | return; | |
556 | } | |
79420f9a | 557 | |
b6930bdf NC |
558 | /* Check to see if this is an allowable parallel insn. */ |
559 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
560 | { | |
561 | as_bad ("instruction '%s' cannot be executed in parallel.", str); | |
562 | return; | |
563 | } | |
ebde3f62 | 564 | |
b6930bdf NC |
565 | if (! enable_m32rx |
566 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
567 | { | |
568 | as_bad ("instruction '%s' is for the M32RX only", str); | |
569 | return; | |
ebde3f62 NC |
570 | } |
571 | ||
b6930bdf NC |
572 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
573 | str3 = str; /* Save the original string pointer. */ | |
574 | str = str2 + 2; /* Advanced past the parsed string. */ | |
575 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
576 | ||
577 | /* Preserve any fixups that have been generated and reset the list to empty. */ | |
578 | cgen_save_fixups(); | |
579 | ||
6cf2575a NC |
580 | /* Get the indicies of the operands of the instruction. */ |
581 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
582 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
c9cec4ef NC |
583 | /* FIXME: ALIAS insns do not have operands, so we use this function |
584 | to find the equivalent insn and overwrite the value stored in our | |
585 | structure. When aliases behave differently this may have to change. */ | |
586 | first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16, | |
587 | first.indices); | |
588 | if (first.insn == NULL) | |
6cf2575a NC |
589 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn"); |
590 | ||
b6930bdf NC |
591 | /* Parse the second instruction. */ |
592 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
593 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
594 | { |
595 | as_bad (errmsg); | |
596 | return; | |
597 | } | |
c8cf7e17 | 598 | |
b6930bdf NC |
599 | /* Check it. */ |
600 | if (! enable_m32rx | |
601 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
ebde3f62 NC |
602 | { |
603 | as_bad ("instruction '%s' is for the M32RX only", str); | |
604 | return; | |
605 | } | |
ebde3f62 | 606 | |
b6930bdf | 607 | if (! enable_m32rx) |
ebde3f62 | 608 | { |
b6930bdf NC |
609 | if ( strcmp (first.insn->name, "nop") != 0 |
610 | && strcmp (second.insn->name, "nop") != 0) | |
ebde3f62 | 611 | { |
b6930bdf NC |
612 | as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2); |
613 | return; | |
ebde3f62 | 614 | } |
b6930bdf | 615 | } |
9121b102 | 616 | |
6cf2575a | 617 | /* Get the indicies of the operands of the instruction. */ |
c9cec4ef NC |
618 | second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16, |
619 | second.indices); | |
620 | if (second.insn == NULL) | |
6cf2575a NC |
621 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn"); |
622 | ||
b6930bdf NC |
623 | /* We assume that if the first instruction writes to a register that is |
624 | read by the second instruction it is because the programmer intended | |
625 | this to happen, (after all they have explicitly requested that these | |
26192c50 NC |
626 | two instructions be executed in parallel). Although if the global |
627 | variable warn_explicit_parallel_conflicts is true then we do generate | |
628 | a warning message. Similarly we assume that parallel branch and jump | |
00aa5b17 | 629 | instructions are deliberate and should not produce errors. */ |
b6930bdf | 630 | |
00aa5b17 | 631 | if (warn_explicit_parallel_conflicts) |
b6930bdf | 632 | { |
6cf2575a NC |
633 | if (first_writes_to_seconds_operands (& first, & second, false)) |
634 | as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2); | |
26192c50 | 635 | |
6cf2575a NC |
636 | if (first_writes_to_seconds_operands (& second, & first, false)) |
637 | as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2); | |
00aa5b17 DE |
638 | } |
639 | ||
640 | if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL) | |
641 | { | |
b6930bdf NC |
642 | /* Get the fixups for the first instruction. */ |
643 | cgen_swap_fixups (); | |
644 | ||
645 | /* Write it out. */ | |
646 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
647 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
ebde3f62 | 648 | |
b6930bdf NC |
649 | /* Force the top bit of the second insn to be set. */ |
650 | make_parallel (second.buffer); | |
ebde3f62 | 651 | |
b6930bdf NC |
652 | /* Get its fixups. */ |
653 | cgen_restore_fixups (); | |
775fdd0c | 654 | |
b6930bdf NC |
655 | /* Write it out. */ |
656 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
657 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
658 | } | |
89285fc9 | 659 | /* Try swapping the instructions to see if they work that way. */ |
6cf2575a | 660 | else if (can_make_parallel (& second, & first) == NULL) |
b6930bdf NC |
661 | { |
662 | /* Write out the second instruction first. */ | |
663 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
664 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
775fdd0c | 665 | |
b6930bdf NC |
666 | /* Force the top bit of the first instruction to be set. */ |
667 | make_parallel (first.buffer); | |
668 | ||
669 | /* Get the fixups for the first instruction. */ | |
670 | cgen_restore_fixups (); | |
671 | ||
672 | /* Write out the first instruction. */ | |
673 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
674 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
675 | } | |
676 | else | |
677 | { | |
678 | as_bad ("'%s': %s", str2, errmsg); | |
679 | return; | |
680 | } | |
ebde3f62 | 681 | |
b6930bdf NC |
682 | /* Set these so m32r_fill_insn can use them. */ |
683 | prev_seg = now_seg; | |
684 | prev_subseg = now_subseg; | |
685 | ||
686 | return; | |
687 | } | |
55a4759f DE |
688 | |
689 | #endif /* HAVE_CPU_M32RX */ | |
690 | ||
b6930bdf NC |
691 | /* end-sanitize-m32rx */ |
692 | ||
693 | ||
694 | void | |
695 | md_assemble (str) | |
696 | char * str; | |
697 | { | |
698 | m32r_insn insn; | |
699 | char * errmsg; | |
700 | char * str2 = NULL; | |
701 | ||
702 | /* Initialize GAS's cgen interface for a new instruction. */ | |
703 | cgen_asm_init_parse (); | |
704 | ||
705 | /* start-sanitize-m32rx */ | |
55a4759f | 706 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
707 | /* Look for a parallel instruction seperator. */ |
708 | if ((str2 = strstr (str, "||")) != NULL) | |
709 | { | |
710 | assemble_parallel_insn (str, str2); | |
711 | return; | |
ebde3f62 | 712 | } |
55a4759f | 713 | #endif |
b6930bdf NC |
714 | /* end-sanitize-m32rx */ |
715 | ||
716 | insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); | |
717 | if (!insn.insn) | |
718 | { | |
719 | as_bad (errmsg); | |
720 | return; | |
721 | } | |
722 | ||
723 | /* start-sanitize-m32rx */ | |
55a4759f | 724 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
725 | if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
726 | { | |
727 | as_bad ("instruction '%s' is for the M32RX only", str); | |
728 | return; | |
729 | } | |
55a4759f | 730 | #endif |
b6930bdf NC |
731 | /* end-sanitize-m32rx */ |
732 | ||
733 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
734 | { |
735 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 736 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 NC |
737 | { |
738 | /* FIXME: If calling fill_insn too many times turns us into a memory | |
739 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ | |
740 | fill_insn (0); | |
741 | } | |
742 | ||
b6930bdf NC |
743 | (void) cgen_asm_finish_insn (insn.insn, insn.buffer, |
744 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
c8cf7e17 DE |
745 | } |
746 | else | |
747 | { | |
b6930bdf NC |
748 | /* start-sanitize-m32rx */ |
749 | /* start-sanitize-phase2-m32rx */ | |
750 | int swap = false; | |
751 | /* end-sanitize-phase2-m32rx */ | |
752 | /* end-sanitize-m32rx */ | |
753 | ||
754 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
755 | abort(); | |
756 | ||
6cf2575a | 757 | /* Get the indicies of the operands of the instruction. */ |
c9cec4ef NC |
758 | insn.insn = m32r_cgen_get_insn_operands (insn.insn, |
759 | bfd_getb16 ((char *) insn.buffer), | |
760 | 16, | |
761 | insn.indices); | |
762 | if (insn.insn == NULL) | |
6cf2575a NC |
763 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed"); |
764 | ||
c8cf7e17 | 765 | /* Keep track of whether we've seen a pair of 16 bit insns. |
b6930bdf NC |
766 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
767 | if (prev_insn.insn) | |
775fdd0c NC |
768 | { |
769 | /* start-sanitize-m32rx */ | |
b6930bdf | 770 | /* start-sanitize-phase2-m32rx */ |
55a4759f | 771 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
772 | /* Look to see if this instruction can be combined with the |
773 | previous instruction to make one, parallel, 32 bit instruction. | |
774 | If the previous instruction (potentially) changed the flow of | |
775 | program control, then it cannot be combined with the current | |
ed295804 NC |
776 | instruction. Also if the output of the previous instruction |
777 | is used as an input to the current instruction then it cannot | |
778 | be combined. Otherwise call can_make_parallel() with both | |
b6930bdf | 779 | orderings of the instructions to see if they can be combined. */ |
6cf2575a NC |
780 | if (! writes_to_pc (& prev_insn) |
781 | && ! first_writes_to_seconds_operands (& prev_insn, &insn, false) | |
ed295804 | 782 | ) |
775fdd0c | 783 | { |
ed295804 NC |
784 | if (can_make_parallel (& prev_insn, & insn) == NULL) |
785 | make_parallel (insn.buffer); | |
786 | else if (can_make_parallel (& insn, & prev_insn.insn) == NULL) | |
787 | swap = true; | |
775fdd0c | 788 | } |
55a4759f | 789 | #endif |
b6930bdf | 790 | /* end-sanitize-phase2-m32rx */ |
775fdd0c NC |
791 | /* end-sanitize-m32rx */ |
792 | ||
b6930bdf | 793 | prev_insn.insn = NULL; |
775fdd0c | 794 | } |
c8cf7e17 | 795 | else |
775fdd0c | 796 | { |
b6930bdf | 797 | prev_insn = insn; |
775fdd0c | 798 | } |
c8cf7e17 | 799 | |
b6930bdf NC |
800 | /* Record the frag that might be used by this insn. */ |
801 | insn.frag = frag_now; | |
802 | insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer, | |
803 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
804 | ||
805 | /* start-sanitize-m32rx */ | |
806 | /* start-sanitize-phase2-m32rx */ | |
55a4759f | 807 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
808 | if (swap) |
809 | { | |
810 | int tmp; | |
811 | ||
812 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
813 | ||
814 | /* Swap the two insns */ | |
815 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
816 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
817 | ||
818 | make_parallel (insn.addr); | |
819 | ||
820 | /* Swap any relaxable frags recorded for the two insns. */ | |
821 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
822 | { | |
823 | prev_insn.frag->fr_opcode = insn.addr; | |
824 | } | |
825 | else if (insn.frag->fr_opcode == insn.addr) | |
826 | { | |
827 | insn.frag->fr_opcode = prev_insn.addr; | |
828 | } | |
829 | } | |
830 | /* end-sanitize-phase2-m32rx */ | |
831 | ||
832 | /* Record where this instruction was assembled. */ | |
833 | prev_insn.addr = insn.addr; | |
834 | prev_insn.frag = insn.frag; | |
55a4759f | 835 | #endif |
b6930bdf NC |
836 | /* end-sanitize-m32rx */ |
837 | ||
c8cf7e17 DE |
838 | /* If the insn needs the following one to be on a 32 bit boundary |
839 | (e.g. subroutine calls), fill this insn's slot. */ | |
b6930bdf NC |
840 | if (prev_insn.insn |
841 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0) | |
c8cf7e17 | 842 | fill_insn (0); |
c8cf7e17 | 843 | |
775fdd0c | 844 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
845 | mark the fact so that we can emit an alignment directive for a |
846 | following 32 bit insn if we see one. */ | |
847 | if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0) | |
775fdd0c NC |
848 | seen_relaxable_p = 1; |
849 | } | |
c8cf7e17 DE |
850 | |
851 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 852 | prev_seg = now_seg; |
c8cf7e17 DE |
853 | prev_subseg = now_subseg; |
854 | } | |
855 | ||
856 | /* The syntax in the manual says constants begin with '#'. | |
857 | We just ignore it. */ | |
858 | ||
859 | void | |
860 | md_operand (expressionP) | |
ebde3f62 | 861 | expressionS * expressionP; |
c8cf7e17 | 862 | { |
ebde3f62 | 863 | if (* input_line_pointer == '#') |
c8cf7e17 | 864 | { |
ebde3f62 | 865 | input_line_pointer ++; |
c8cf7e17 DE |
866 | expression (expressionP); |
867 | } | |
868 | } | |
869 | ||
870 | valueT | |
871 | md_section_align (segment, size) | |
ebde3f62 | 872 | segT segment; |
c8cf7e17 DE |
873 | valueT size; |
874 | { | |
875 | int align = bfd_get_section_alignment (stdoutput, segment); | |
876 | return ((size + (1 << align) - 1) & (-1 << align)); | |
877 | } | |
878 | ||
879 | symbolS * | |
880 | md_undefined_symbol (name) | |
ebde3f62 | 881 | char * name; |
c8cf7e17 DE |
882 | { |
883 | return 0; | |
884 | } | |
885 | \f | |
886 | /* .scomm pseudo-op handler. | |
887 | ||
888 | This is a new pseudo-op to handle putting objects in .scommon. | |
889 | By doing this the linker won't need to do any work and more importantly | |
890 | it removes the implicit -G arg necessary to correctly link the object file. | |
891 | */ | |
892 | ||
893 | static void | |
894 | m32r_scomm (ignore) | |
895 | int ignore; | |
896 | { | |
ebde3f62 NC |
897 | register char * name; |
898 | register char c; | |
899 | register char * p; | |
900 | offsetT size; | |
901 | register symbolS * symbolP; | |
902 | offsetT align; | |
903 | int align2; | |
c8cf7e17 DE |
904 | |
905 | name = input_line_pointer; | |
906 | c = get_symbol_end (); | |
907 | ||
908 | /* just after name is now '\0' */ | |
909 | p = input_line_pointer; | |
ebde3f62 | 910 | * p = c; |
c8cf7e17 | 911 | SKIP_WHITESPACE (); |
ebde3f62 | 912 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
913 | { |
914 | as_bad ("Expected comma after symbol-name: rest of line ignored."); | |
915 | ignore_rest_of_line (); | |
916 | return; | |
917 | } | |
918 | ||
b6930bdf | 919 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
920 | if ((size = get_absolute_expression ()) < 0) |
921 | { | |
922 | as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size); | |
923 | ignore_rest_of_line (); | |
924 | return; | |
925 | } | |
926 | ||
927 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 928 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
929 | align = 8; |
930 | else | |
931 | { | |
ebde3f62 | 932 | ++ input_line_pointer; |
c8cf7e17 DE |
933 | align = get_absolute_expression (); |
934 | if (align <= 0) | |
935 | { | |
936 | as_warn ("ignoring bad alignment"); | |
937 | align = 8; | |
938 | } | |
939 | } | |
940 | /* Convert to a power of 2 alignment. */ | |
941 | if (align) | |
942 | { | |
ebde3f62 | 943 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
944 | continue; |
945 | if (align != 1) | |
946 | { | |
947 | as_bad ("Common alignment not a power of 2"); | |
948 | ignore_rest_of_line (); | |
949 | return; | |
950 | } | |
951 | } | |
952 | else | |
953 | align2 = 0; | |
954 | ||
ebde3f62 | 955 | * p = 0; |
c8cf7e17 | 956 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 957 | * p = c; |
c8cf7e17 DE |
958 | |
959 | if (S_IS_DEFINED (symbolP)) | |
960 | { | |
961 | as_bad ("Ignoring attempt to re-define symbol `%s'.", | |
962 | S_GET_NAME (symbolP)); | |
963 | ignore_rest_of_line (); | |
964 | return; | |
965 | } | |
966 | ||
967 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
968 | { | |
969 | as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.", | |
970 | S_GET_NAME (symbolP), | |
971 | (long) S_GET_VALUE (symbolP), | |
972 | (long) size); | |
973 | ||
974 | ignore_rest_of_line (); | |
975 | return; | |
976 | } | |
977 | ||
978 | if (symbolP->local) | |
979 | { | |
ebde3f62 NC |
980 | segT old_sec = now_seg; |
981 | int old_subsec = now_subseg; | |
982 | char * pfrag; | |
c8cf7e17 DE |
983 | |
984 | record_alignment (sbss_section, align2); | |
985 | subseg_set (sbss_section, 0); | |
775fdd0c | 986 | |
c8cf7e17 DE |
987 | if (align2) |
988 | frag_align (align2, 0, 0); | |
775fdd0c | 989 | |
c8cf7e17 DE |
990 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
991 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 992 | |
c8cf7e17 | 993 | symbolP->sy_frag = frag_now; |
b6930bdf | 994 | |
c8cf7e17 DE |
995 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
996 | (char *) 0); | |
ebde3f62 | 997 | * pfrag = 0; |
c8cf7e17 DE |
998 | S_SET_SIZE (symbolP, size); |
999 | S_SET_SEGMENT (symbolP, sbss_section); | |
1000 | S_CLEAR_EXTERNAL (symbolP); | |
1001 | subseg_set (old_sec, old_subsec); | |
1002 | } | |
1003 | else | |
1004 | { | |
1005 | S_SET_VALUE (symbolP, (valueT) size); | |
1006 | S_SET_ALIGN (symbolP, align2); | |
1007 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 1008 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
1009 | } |
1010 | ||
1011 | demand_empty_rest_of_line (); | |
1012 | } | |
1013 | \f | |
1014 | /* Interface to relax_segment. */ | |
1015 | ||
1016 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1017 | ||
1018 | const relax_typeS md_relax_table[] = | |
1019 | { | |
1020 | /* The fields are: | |
1021 | 1) most positive reach of this state, | |
1022 | 2) most negative reach of this state, | |
1023 | 3) how many bytes this mode will add to the size of the current frag | |
1024 | 4) which index into the table to try if we can't fit into this one. */ | |
1025 | ||
1026 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1027 | each list. */ | |
1028 | {1, 1, 0, 0}, | |
1029 | ||
1030 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1031 | so we subtract 2 from the following. */ | |
1032 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1033 | This doesn't handle a branch in the right slot at the border: | |
1034 | the "& -4" isn't taken into account. It's not important enough to | |
1035 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1036 | case). */ | |
1037 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1038 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1039 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1040 | /* Same thing, but with leading nop for alignment. */ | |
1041 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1042 | }; | |
1043 | ||
1044 | long | |
1045 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1046 | fragS * fragP; |
1047 | long stretch; | |
c8cf7e17 DE |
1048 | { |
1049 | /* Address of branch insn. */ | |
1050 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1051 | long growth = 0; | |
1052 | ||
1053 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1054 | if (fragP->fr_subtype == 2) | |
1055 | { | |
1056 | if ((address & 3) != 0) | |
1057 | { | |
1058 | fragP->fr_subtype = 3; | |
1059 | growth = 2; | |
1060 | } | |
1061 | } | |
1062 | else if (fragP->fr_subtype == 3) | |
1063 | { | |
1064 | if ((address & 3) == 0) | |
1065 | { | |
1066 | fragP->fr_subtype = 2; | |
1067 | growth = -2; | |
1068 | } | |
1069 | } | |
1070 | else | |
1071 | { | |
1072 | growth = relax_frag (fragP, stretch); | |
1073 | ||
1074 | /* Long jump on odd halfword boundary? */ | |
1075 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1076 | { | |
1077 | fragP->fr_subtype = 3; | |
1078 | growth += 2; | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | return growth; | |
1083 | } | |
1084 | ||
1085 | /* Return an initial guess of the length by which a fragment must grow to | |
1086 | hold a branch to reach its destination. | |
1087 | Also updates fr_type/fr_subtype as necessary. | |
1088 | ||
1089 | Called just before doing relaxation. | |
1090 | Any symbol that is now undefined will not become defined. | |
1091 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1092 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1093 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1094 | 0 value. */ | |
1095 | ||
1096 | int | |
1097 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1098 | fragS * fragP; |
1099 | segT segment; | |
c8cf7e17 | 1100 | { |
ebde3f62 NC |
1101 | int old_fr_fix = fragP->fr_fix; |
1102 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1103 | |
1104 | /* The only thing we have to handle here are symbols outside of the | |
1105 | current segment. They may be undefined or in a different segment in | |
1106 | which case linker scripts may place them anywhere. | |
1107 | However, we can't finish the fragment here and emit the reloc as insn | |
1108 | alignment requirements may move the insn about. */ | |
1109 | ||
1110 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1111 | { | |
1112 | /* The symbol is undefined in this segment. | |
1113 | Change the relaxation subtype to the max allowable and leave | |
1114 | all further handling to md_convert_frag. */ | |
1115 | fragP->fr_subtype = 2; | |
1116 | ||
1117 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1118 | /* Change 16 bit insn to 32 bit insn. */ | |
1119 | opcode[0] |= 0x80; | |
1120 | ||
1121 | /* Increase known (fixed) size of fragment. */ | |
1122 | fragP->fr_fix += 2; | |
1123 | ||
1124 | /* Create a relocation for it. */ | |
1125 | fix_new (fragP, old_fr_fix, 4, | |
1126 | fragP->fr_symbol, | |
1127 | fragP->fr_offset, 1 /* pcrel */, | |
1128 | /* FIXME: Can't use a real BFD reloc here. | |
1129 | cgen_md_apply_fix3 can't handle it. */ | |
1130 | BFD_RELOC_M32R_26_PCREL); | |
1131 | ||
1132 | /* Mark this fragment as finished. */ | |
1133 | frag_wane (fragP); | |
1134 | #else | |
a450e9f4 | 1135 | { |
ebde3f62 NC |
1136 | const CGEN_INSN * insn; |
1137 | int i; | |
a450e9f4 NC |
1138 | |
1139 | /* Update the recorded insn. | |
1140 | Fortunately we don't have to look very far. | |
1141 | FIXME: Change this to record in the instruction the next higher | |
1142 | relaxable insn to use. */ | |
1143 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1144 | { | |
b5e9e562 DE |
1145 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1146 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1147 | == 0) |
1148 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1149 | break; | |
1150 | } | |
1151 | if (i == 4) | |
1152 | abort (); | |
b6930bdf | 1153 | |
a450e9f4 NC |
1154 | fragP->fr_cgen.insn = insn; |
1155 | return 2; | |
1156 | } | |
c8cf7e17 DE |
1157 | #endif |
1158 | } | |
1159 | ||
1160 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1161 | } | |
1162 | ||
1163 | /* *fragP has been relaxed to its final size, and now needs to have | |
1164 | the bytes inside it modified to conform to the new size. | |
1165 | ||
1166 | Called after relaxation is finished. | |
1167 | fragP->fr_type == rs_machine_dependent. | |
1168 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1169 | ||
1170 | void | |
1171 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1172 | bfd * abfd; |
1173 | segT sec; | |
1174 | fragS * fragP; | |
c8cf7e17 | 1175 | { |
ebde3f62 NC |
1176 | char * opcode; |
1177 | char * displacement; | |
1178 | int target_address; | |
1179 | int opcode_address; | |
1180 | int extension; | |
1181 | int addend; | |
c8cf7e17 DE |
1182 | |
1183 | opcode = fragP->fr_opcode; | |
1184 | ||
1185 | /* Address opcode resides at in file space. */ | |
1186 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1187 | ||
1188 | switch (fragP->fr_subtype) | |
1189 | { | |
1190 | case 1 : | |
1191 | extension = 0; | |
ebde3f62 | 1192 | displacement = & opcode[1]; |
c8cf7e17 DE |
1193 | break; |
1194 | case 2 : | |
1195 | opcode[0] |= 0x80; | |
1196 | extension = 2; | |
ebde3f62 | 1197 | displacement = & opcode[1]; |
c8cf7e17 DE |
1198 | break; |
1199 | case 3 : | |
1200 | opcode[2] = opcode[0] | 0x80; | |
1201 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1202 | opcode_address += 2; | |
1203 | extension = 4; | |
ebde3f62 | 1204 | displacement = & opcode[3]; |
c8cf7e17 DE |
1205 | break; |
1206 | default : | |
1207 | abort (); | |
1208 | } | |
1209 | ||
1210 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1211 | { | |
1212 | /* symbol must be resolved by linker */ | |
1213 | if (fragP->fr_offset & 3) | |
1214 | as_warn ("Addend to unresolved symbol not on word boundary."); | |
1215 | addend = fragP->fr_offset >> 2; | |
1216 | } | |
1217 | else | |
1218 | { | |
1219 | /* Address we want to reach in file space. */ | |
1220 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1221 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1222 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1223 | } | |
1224 | ||
1225 | /* Create a relocation for symbols that must be resolved by the linker. | |
1226 | Otherwise output the completed insn. */ | |
1227 | ||
1228 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1229 | { | |
1230 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1231 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1232 | cgen_record_fixup (fragP, |
1233 | /* Offset of branch insn in frag. */ | |
1234 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1235 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1236 | 4 /*length*/, |
1237 | /* FIXME: quick hack */ | |
1238 | #if 0 | |
a450e9f4 | 1239 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1240 | #else |
1241 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1242 | #endif | |
a450e9f4 | 1243 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1244 | fragP->fr_symbol, fragP->fr_offset); |
1245 | } | |
1246 | ||
1247 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1248 | ||
1249 | md_number_to_chars (displacement, (valueT) addend, | |
1250 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1251 | ||
1252 | fragP->fr_fix += extension; | |
1253 | } | |
1254 | \f | |
1255 | /* Functions concerning relocs. */ | |
1256 | ||
1257 | /* The location from which a PC relative jump should be calculated, | |
1258 | given a PC relative reloc. */ | |
1259 | ||
1260 | long | |
1261 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1262 | fixS * fixP; |
1263 | segT sec; | |
c8cf7e17 DE |
1264 | { |
1265 | if (fixP->fx_addsy != (symbolS *) NULL | |
1266 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1267 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1268 | { | |
1269 | /* The symbol is undefined (or is defined but not in this section). | |
1270 | Let the linker figure it out. */ | |
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1275 | } | |
1276 | ||
1277 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1278 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1279 | *FIXP may be modified if desired. */ | |
1280 | ||
1281 | bfd_reloc_code_real_type | |
1282 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1283 | const CGEN_INSN * insn; |
1284 | const CGEN_OPERAND * operand; | |
1285 | fixS * fixP; | |
c8cf7e17 DE |
1286 | { |
1287 | switch (CGEN_OPERAND_TYPE (operand)) | |
1288 | { | |
1289 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1290 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1291 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1292 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1293 | case M32R_OPERAND_HI16 : | |
1294 | case M32R_OPERAND_SLO16 : | |
1295 | case M32R_OPERAND_ULO16 : | |
1296 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1297 | if (fixP->tc_fix_data.opinfo != 0) | |
1298 | return fixP->tc_fix_data.opinfo; | |
1299 | break; | |
1300 | } | |
1301 | return BFD_RELOC_NONE; | |
1302 | } | |
1303 | ||
b6930bdf NC |
1304 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1305 | ||
1306 | static void | |
1307 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1308 | int reloc_type; | |
1309 | fixS * fixP; | |
1310 | segT seg; | |
1311 | { | |
1312 | struct m32r_hi_fixup * hi_fixup; | |
1313 | ||
1314 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1315 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1316 | ||
1317 | hi_fixup = ((struct m32r_hi_fixup *) | |
1318 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1319 | hi_fixup->fixp = fixP; | |
1320 | hi_fixup->seg = now_seg; | |
1321 | hi_fixup->next = m32r_hi_fixup_list; | |
1322 | ||
1323 | m32r_hi_fixup_list = hi_fixup; | |
1324 | } | |
1325 | ||
c8cf7e17 DE |
1326 | /* Called while parsing an instruction to create a fixup. |
1327 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1328 | ||
1329 | fixS * | |
1330 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1331 | fragS * frag; |
1332 | int where; | |
1333 | const CGEN_INSN * insn; | |
1334 | int length; | |
1335 | const CGEN_OPERAND * operand; | |
1336 | int opinfo; | |
1337 | expressionS * exp; | |
c8cf7e17 | 1338 | { |
ebde3f62 NC |
1339 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1340 | operand, opinfo, exp); | |
c8cf7e17 DE |
1341 | |
1342 | switch (CGEN_OPERAND_TYPE (operand)) | |
1343 | { | |
1344 | case M32R_OPERAND_HI16 : | |
1345 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1346 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1347 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1348 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1349 | break; | |
1350 | } | |
1351 | ||
1352 | return fixP; | |
1353 | } | |
1354 | ||
c8cf7e17 DE |
1355 | /* Return BFD reloc type from opinfo field in a fixS. |
1356 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1357 | are BFD_RELOC_UNUSED + operand number. */ | |
1358 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1359 | ||
1360 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1361 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1362 | tc_gen_reloc. */ | |
1363 | ||
1364 | void | |
1365 | m32r_frob_file () | |
1366 | { | |
ebde3f62 | 1367 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1368 | |
1369 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1370 | { | |
ebde3f62 NC |
1371 | segment_info_type * seginfo; |
1372 | int pass; | |
c8cf7e17 DE |
1373 | |
1374 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1375 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1376 | ||
1377 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1378 | if (l->fixp->fx_next != NULL | |
1379 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1380 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1381 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1382 | continue; | |
1383 | ||
1384 | /* Look through the fixups for this segment for a matching `low'. | |
1385 | When we find one, move the high/shigh just in front of it. We do | |
1386 | this in two passes. In the first pass, we try to find a | |
1387 | unique `low'. In the second pass, we permit multiple high's | |
1388 | relocs for a single `low'. */ | |
1389 | seginfo = seg_info (l->seg); | |
1390 | for (pass = 0; pass < 2; pass++) | |
1391 | { | |
ebde3f62 NC |
1392 | fixS * f; |
1393 | fixS * prev; | |
c8cf7e17 DE |
1394 | |
1395 | prev = NULL; | |
1396 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1397 | { | |
1398 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1399 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1400 | && f->fx_addsy == l->fixp->fx_addsy | |
1401 | && f->fx_offset == l->fixp->fx_offset | |
1402 | && (pass == 1 | |
1403 | || prev == NULL | |
1404 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1405 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1406 | || prev->fx_addsy != f->fx_addsy | |
1407 | || prev->fx_offset != f->fx_offset)) | |
1408 | { | |
ebde3f62 | 1409 | fixS ** pf; |
c8cf7e17 DE |
1410 | |
1411 | /* Move l->fixp before f. */ | |
1412 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1413 | * pf != l->fixp; |
1414 | pf = & (* pf)->fx_next) | |
1415 | assert (* pf != NULL); | |
c8cf7e17 | 1416 | |
ebde3f62 | 1417 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1418 | |
1419 | l->fixp->fx_next = f; | |
1420 | if (prev == NULL) | |
1421 | seginfo->fix_root = l->fixp; | |
1422 | else | |
1423 | prev->fx_next = l->fixp; | |
1424 | ||
1425 | break; | |
1426 | } | |
1427 | ||
1428 | prev = f; | |
1429 | } | |
1430 | ||
1431 | if (f != NULL) | |
1432 | break; | |
1433 | ||
1434 | if (pass == 1) | |
1435 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1436 | "Unmatched high/shigh reloc"); | |
1437 | } | |
1438 | } | |
1439 | } | |
1440 | ||
1441 | /* See whether we need to force a relocation into the output file. | |
1442 | This is used to force out switch and PC relative relocations when | |
1443 | relaxing. */ | |
1444 | ||
1445 | int | |
1446 | m32r_force_relocation (fix) | |
ebde3f62 | 1447 | fixS * fix; |
c8cf7e17 DE |
1448 | { |
1449 | if (! m32r_relax) | |
1450 | return 0; | |
1451 | ||
1452 | return (fix->fx_pcrel | |
1453 | || 0 /* ??? */); | |
1454 | } | |
1455 | \f | |
1456 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1457 | ||
1458 | void | |
1459 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1460 | char * buf; |
c8cf7e17 | 1461 | valueT val; |
ebde3f62 | 1462 | int n; |
c8cf7e17 DE |
1463 | { |
1464 | if (target_big_endian) | |
1465 | number_to_chars_bigendian (buf, val, n); | |
1466 | else | |
1467 | number_to_chars_littleendian (buf, val, n); | |
1468 | } | |
1469 | ||
1470 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1471 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1472 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1473 | */ | |
1474 | ||
1475 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1476 | #define MAX_LITTLENUMS 6 | |
1477 | ||
1478 | char * | |
1479 | md_atof (type, litP, sizeP) | |
1480 | char type; | |
1481 | char *litP; | |
1482 | int *sizeP; | |
1483 | { | |
ebde3f62 NC |
1484 | int i; |
1485 | int prec; | |
1486 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1487 | LITTLENUM_TYPE * wordP; | |
1488 | char * t; | |
1489 | char * atof_ieee (); | |
c8cf7e17 DE |
1490 | |
1491 | switch (type) | |
1492 | { | |
1493 | case 'f': | |
1494 | case 'F': | |
1495 | case 's': | |
1496 | case 'S': | |
1497 | prec = 2; | |
1498 | break; | |
1499 | ||
1500 | case 'd': | |
1501 | case 'D': | |
1502 | case 'r': | |
1503 | case 'R': | |
1504 | prec = 4; | |
1505 | break; | |
1506 | ||
1507 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1508 | ||
1509 | default: | |
ebde3f62 | 1510 | * sizeP = 0; |
c8cf7e17 DE |
1511 | return "Bad call to md_atof()"; |
1512 | } | |
1513 | ||
1514 | t = atof_ieee (input_line_pointer, type, words); | |
1515 | if (t) | |
1516 | input_line_pointer = t; | |
ebde3f62 | 1517 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1518 | |
1519 | if (target_big_endian) | |
1520 | { | |
1521 | for (i = 0; i < prec; i++) | |
1522 | { | |
ebde3f62 NC |
1523 | md_number_to_chars (litP, (valueT) words[i], |
1524 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1525 | litP += sizeof (LITTLENUM_TYPE); |
1526 | } | |
1527 | } | |
1528 | else | |
1529 | { | |
1530 | for (i = prec - 1; i >= 0; i--) | |
1531 | { | |
ebde3f62 NC |
1532 | md_number_to_chars (litP, (valueT) words[i], |
1533 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1534 | litP += sizeof (LITTLENUM_TYPE); |
1535 | } | |
1536 | } | |
1537 | ||
1538 | return 0; | |
1539 | } |