Commit | Line | Data |
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76090fdd | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "cgen-opc.h" | |
26 | ||
b6930bdf NC |
27 | typedef struct |
28 | { | |
29 | const CGEN_INSN * insn; | |
30 | CGEN_FIELDS fields; | |
31 | #ifdef CGEN_INT_INSN | |
32 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
33 | #else | |
34 | char buffer [CGEN_MAX_INSN_SIZE]; | |
35 | #endif | |
36 | char * addr; | |
37 | fragS * frag; | |
38 | } | |
39 | m32r_insn; | |
40 | ||
41 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
42 | boundary (i.e. was the first of two 16 bit insns). */ | |
43 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
44 | |
45 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
46 | alignment request. */ | |
47 | static int seen_relaxable_p = 0; | |
48 | ||
49 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
50 | for the linker to do relaxing. | |
51 | We do simple forms of relaxing internally, but they are always done. | |
52 | This flag does not apply to them. */ | |
53 | static int m32r_relax; | |
54 | ||
55 | /* If non-NULL, pointer to cpu description file to read. | |
56 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 57 | static char * m32r_cpu_desc; |
c8cf7e17 | 58 | |
b5e9e562 | 59 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
60 | /* Non-zero if -m32rx has been specified, in which case support for the |
61 | extended M32RX instruction set should be enabled. */ | |
a450e9f4 | 62 | static int enable_m32rx = 0; |
b6930bdf NC |
63 | |
64 | /* Non-zero if the programmer should be warned when an explicit parallel | |
65 | instruction might have constraint violations. */ | |
66 | static int warn_explicit_parallel_conflicts = 1; | |
b5e9e562 | 67 | /* end-sanitize-m32rx */ |
a450e9f4 | 68 | |
c8cf7e17 | 69 | /* stuff for .scomm symbols. */ |
ebde3f62 | 70 | static segT sbss_section; |
c8cf7e17 | 71 | static asection scom_section; |
ebde3f62 | 72 | static asymbol scom_symbol; |
c8cf7e17 | 73 | |
ebde3f62 NC |
74 | const char comment_chars[] = ";"; |
75 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 76 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
77 | const char EXP_CHARS[] = "eE"; |
78 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
79 | |
80 | /* Relocations against symbols are done in two | |
81 | parts, with a HI relocation and a LO relocation. Each relocation | |
82 | has only 16 bits of space to store an addend. This means that in | |
83 | order for the linker to handle carries correctly, it must be able | |
84 | to locate both the HI and the LO relocation. This means that the | |
85 | relocations must appear in order in the relocation table. | |
86 | ||
87 | In order to implement this, we keep track of each unmatched HI | |
88 | relocation. We then sort them so that they immediately precede the | |
89 | corresponding LO relocation. */ | |
90 | ||
91 | struct m32r_hi_fixup | |
92 | { | |
ebde3f62 NC |
93 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
94 | fixS * fixp; /* This fixup. */ | |
95 | segT seg; /* The section this fixup is in. */ | |
96 | ||
c8cf7e17 DE |
97 | }; |
98 | ||
99 | /* The list of unmatched HI relocs. */ | |
100 | ||
ebde3f62 | 101 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 102 | |
a450e9f4 | 103 | \f |
b5e9e562 | 104 | /* start-sanitize-m32rx */ |
a450e9f4 | 105 | static void |
55a4759f DE |
106 | allow_m32rx (on) |
107 | int on; | |
a450e9f4 NC |
108 | { |
109 | enable_m32rx = on; | |
110 | ||
111 | if (stdoutput != NULL) | |
ebde3f62 NC |
112 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
113 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 114 | } |
b5e9e562 | 115 | /* end-sanitize-m32rx */ |
c8cf7e17 | 116 | \f |
ebde3f62 | 117 | const char * md_shortopts = ""; |
c8cf7e17 | 118 | |
a450e9f4 NC |
119 | struct option md_longopts[] = |
120 | { | |
b5e9e562 | 121 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
122 | #define OPTION_M32RX (OPTION_MD_BASE) |
123 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
b6930bdf NC |
124 | #define OPTION_WARN (OPTION_MD_BASE + 1) |
125 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN}, | |
126 | #define OPTION_NO_WARN (OPTION_MD_BASE + 2) | |
127 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, | |
b5e9e562 | 128 | /* end-sanitize-m32rx */ |
a450e9f4 | 129 | |
c8cf7e17 | 130 | #if 0 /* not supported yet */ |
b6930bdf | 131 | #define OPTION_RELAX (OPTION_MD_BASE + 3) |
c8cf7e17 | 132 | {"relax", no_argument, NULL, OPTION_RELAX}, |
b6930bdf | 133 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 4) |
c8cf7e17 DE |
134 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
135 | #endif | |
a450e9f4 | 136 | |
c8cf7e17 DE |
137 | {NULL, no_argument, NULL, 0} |
138 | }; | |
ebde3f62 | 139 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
140 | |
141 | int | |
142 | md_parse_option (c, arg) | |
ebde3f62 NC |
143 | int c; |
144 | char * arg; | |
c8cf7e17 DE |
145 | { |
146 | switch (c) | |
147 | { | |
b5e9e562 | 148 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
149 | case OPTION_M32RX: |
150 | allow_m32rx (1); | |
151 | break; | |
b6930bdf NC |
152 | |
153 | case OPTION_WARN: | |
154 | warn_explicit_parallel_conflicts = 1; | |
155 | break; | |
156 | ||
157 | case OPTION_NO_WARN: | |
158 | warn_explicit_parallel_conflicts = 0; | |
159 | break; | |
b5e9e562 | 160 | /* end-sanitize-m32rx */ |
a450e9f4 | 161 | |
c8cf7e17 DE |
162 | #if 0 /* not supported yet */ |
163 | case OPTION_RELAX: | |
164 | m32r_relax = 1; | |
165 | break; | |
166 | case OPTION_CPU_DESC: | |
167 | m32r_cpu_desc = arg; | |
168 | break; | |
169 | #endif | |
170 | default: | |
171 | return 0; | |
172 | } | |
173 | return 1; | |
174 | } | |
175 | ||
176 | void | |
177 | md_show_usage (stream) | |
ebde3f62 | 178 | FILE * stream; |
c8cf7e17 | 179 | { |
a450e9f4 | 180 | fprintf (stream, "M32R/X options:\n"); |
b5e9e562 | 181 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
182 | fprintf (stream, "\ |
183 | --m32rx support the extended m32rx instruction set\n"); | |
b6930bdf NC |
184 | |
185 | fprintf (stream, "\ | |
00aa5b17 DE |
186 | --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n"); |
187 | fprintf (stream, "\ | |
b6930bdf | 188 | --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n"); |
b5e9e562 | 189 | /* end-sanitize-m32rx */ |
a450e9f4 | 190 | |
c8cf7e17 DE |
191 | #if 0 |
192 | fprintf (stream, "\ | |
193 | --relax create linker relaxable code\n"); | |
194 | fprintf (stream, "\ | |
195 | --cpu-desc provide runtime cpu description file\n"); | |
c8cf7e17 DE |
196 | #endif |
197 | } | |
198 | ||
199 | static void fill_insn PARAMS ((int)); | |
200 | static void m32r_scomm PARAMS ((int)); | |
201 | ||
202 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
203 | static subsegT prev_subseg; | |
204 | static segT prev_seg; | |
205 | ||
206 | /* The target specific pseudo-ops which we support. */ | |
207 | const pseudo_typeS md_pseudo_table[] = | |
208 | { | |
209 | { "word", cons, 4 }, | |
210 | { "fillinsn", fill_insn, 0 }, | |
211 | { "scomm", m32r_scomm, 0 }, | |
b5e9e562 | 212 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
213 | { "m32r", allow_m32rx, 0}, |
214 | { "m32rx", allow_m32rx, 1}, | |
b5e9e562 | 215 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
216 | { NULL, NULL, 0 } |
217 | }; | |
218 | ||
219 | /* FIXME: Should be machine generated. */ | |
220 | #define NOP_INSN 0x7000 | |
221 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
222 | ||
223 | /* When we align the .text section, insert the correct NOP pattern. | |
224 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
225 | MAX is the maximum number of characters to skip when doing the alignment, | |
226 | or 0 if there is no maximum. */ | |
227 | ||
228 | int | |
229 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
230 | int n; |
231 | const char * fill; | |
232 | int len; | |
233 | int max; | |
c8cf7e17 | 234 | { |
ebde3f62 | 235 | if ((fill == NULL || (* fill == 0 && len == 1)) |
c8cf7e17 DE |
236 | && (now_seg->flags & SEC_CODE) != 0 |
237 | /* Only do this special handling if aligning to at least a | |
238 | 4 byte boundary. */ | |
239 | && n > 1 | |
775fdd0c | 240 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
241 | least two bytes. */ |
242 | && (max == 0 || max > 1)) | |
243 | { | |
244 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
245 | ||
246 | #if 0 | |
247 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
248 | /* FIXME: How much memory will cause gas to use when assembling a big | |
249 | program? Perhaps we can avoid the frag_align call? */ | |
250 | frag_align (1, 0, 0); | |
251 | #endif | |
252 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
253 | nop. */ | |
254 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
255 | /* If doing larger alignments use a repeating sequence of appropriate | |
256 | nops. */ | |
257 | if (n > 2) | |
258 | { | |
ebde3f62 NC |
259 | static const unsigned char multi_nop_pattern[] = |
260 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
261 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
262 | max ? max - 2 : 0); | |
263 | } | |
264 | return 1; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static void | |
271 | assemble_nop (opcode) | |
272 | int opcode; | |
273 | { | |
ebde3f62 | 274 | char * f = frag_more (2); |
c8cf7e17 DE |
275 | md_number_to_chars (f, opcode, 2); |
276 | } | |
277 | ||
278 | /* If the last instruction was the first of 2 16 bit insns, | |
279 | output a nop to move the PC to a 32 bit boundary. | |
280 | ||
281 | This is done via an alignment specification since branch relaxing | |
282 | may make it unnecessary. | |
283 | ||
284 | Internally, we need to output one of these each time a 32 bit insn is | |
285 | seen after an insn that is relaxable. */ | |
286 | ||
287 | static void | |
288 | fill_insn (ignore) | |
289 | int ignore; | |
290 | { | |
291 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 292 | prev_insn.insn = NULL; |
c8cf7e17 DE |
293 | seen_relaxable_p = 0; |
294 | } | |
295 | ||
296 | /* Cover function to fill_insn called after a label and at end of assembly. | |
297 | ||
298 | The result is always 1: we're called in a conditional to see if the | |
299 | current line is a label. */ | |
300 | ||
301 | int | |
302 | m32r_fill_insn (done) | |
303 | int done; | |
304 | { | |
ebde3f62 | 305 | segT seg; |
c8cf7e17 DE |
306 | subsegT subseg; |
307 | ||
308 | if (prev_seg != NULL) | |
309 | { | |
ebde3f62 | 310 | seg = now_seg; |
c8cf7e17 | 311 | subseg = now_subseg; |
ebde3f62 | 312 | |
c8cf7e17 | 313 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 314 | |
c8cf7e17 | 315 | fill_insn (0); |
ebde3f62 | 316 | |
c8cf7e17 DE |
317 | subseg_set (seg, subseg); |
318 | } | |
ebde3f62 | 319 | |
c8cf7e17 DE |
320 | return 1; |
321 | } | |
322 | \f | |
323 | void | |
324 | md_begin () | |
325 | { | |
326 | flagword applicable; | |
ebde3f62 NC |
327 | segT seg; |
328 | subsegT subseg; | |
c8cf7e17 DE |
329 | |
330 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
331 | |
332 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 333 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 334 | |
4e9d8dea | 335 | /* Set the machine number and endian. */ |
c8cf7e17 | 336 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
337 | target_big_endian ? |
338 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
339 | |
340 | #if 0 /* not supported yet */ | |
341 | /* If a runtime cpu description file was provided, parse it. */ | |
342 | if (m32r_cpu_desc != NULL) | |
343 | { | |
ebde3f62 | 344 | const char * errmsg; |
c8cf7e17 DE |
345 | |
346 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
347 | if (errmsg != NULL) | |
348 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
349 | } | |
350 | #endif | |
351 | ||
352 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
353 | we don't want the initial section to be .sbss]. */ |
354 | seg = now_seg; | |
c8cf7e17 DE |
355 | subseg = now_subseg; |
356 | ||
357 | /* The sbss section is for local .scomm symbols. */ | |
358 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 359 | |
c8cf7e17 DE |
360 | /* This is copied from perform_an_assembly_pass. */ |
361 | applicable = bfd_applicable_section_flags (stdoutput); | |
362 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 363 | |
c8cf7e17 DE |
364 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
365 | seg_info (bss_section)->bss = 1; | |
366 | #endif | |
367 | ||
368 | subseg_set (seg, subseg); | |
369 | ||
370 | /* We must construct a fake section similar to bfd_com_section | |
371 | but with the name .scommon. */ | |
ebde3f62 NC |
372 | scom_section = bfd_com_section; |
373 | scom_section.name = ".scommon"; | |
374 | scom_section.output_section = & scom_section; | |
375 | scom_section.symbol = & scom_symbol; | |
376 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
377 | scom_symbol = * bfd_com_section.symbol; | |
378 | scom_symbol.name = ".scommon"; | |
379 | scom_symbol.section = & scom_section; | |
a450e9f4 | 380 | |
b5e9e562 | 381 | /* start-sanitize-m32rx */ |
a450e9f4 | 382 | allow_m32rx (enable_m32rx); |
b5e9e562 | 383 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
384 | } |
385 | ||
89285fc9 | 386 | /* start-sanitize-m32rx */ |
55a4759f DE |
387 | #ifdef HAVE_CPU_M32RX |
388 | ||
ebde3f62 NC |
389 | /* Returns non zero if the given instruction writes to a destination register. */ |
390 | static int | |
391 | writes_to_dest_reg (insn) | |
392 | const CGEN_INSN * insn; | |
393 | { | |
394 | unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); | |
395 | unsigned char c; | |
396 | ||
397 | /* Scan the syntax string looking for a destination register. */ | |
398 | while ((c = (* syntax ++)) != 0) | |
399 | if (c == 128 + M32R_OPERAND_DR) | |
400 | break; | |
401 | ||
402 | return c; | |
403 | } | |
404 | ||
775fdd0c | 405 | /* Returns non zero if the given instruction reads from a source register. |
b6930bdf | 406 | Ignores the first 'num_ignore' macthes in the syntax string. */ |
ebde3f62 | 407 | static int |
b6930bdf | 408 | reads_from_src_reg (insn, num_ignore) |
ebde3f62 | 409 | const CGEN_INSN * insn; |
b6930bdf | 410 | int num_ignore; |
ebde3f62 | 411 | { |
775fdd0c NC |
412 | unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); |
413 | unsigned char c; | |
414 | ||
415 | /* Scan the syntax string looking for a source register. */ | |
416 | while ((c = (* syntax ++)) != 0) | |
417 | { | |
775fdd0c NC |
418 | if ( c == 128 + M32R_OPERAND_SR |
419 | || c == 128 + M32R_OPERAND_SRC1 | |
420 | || c == 128 + M32R_OPERAND_SRC2) | |
b6930bdf NC |
421 | { |
422 | if (num_ignore -- > 0) | |
423 | continue; | |
424 | else | |
425 | break; | |
426 | } | |
775fdd0c NC |
427 | } |
428 | ||
429 | return c; | |
ebde3f62 NC |
430 | } |
431 | ||
775fdd0c | 432 | /* Returns the integer value of the destination register held in the fields. */ |
b6930bdf | 433 | #define get_dest_reg(fields) (fields).f_r1 |
775fdd0c NC |
434 | |
435 | /* Returns an integer representing the source register of the given type. */ | |
436 | static int | |
b6930bdf NC |
437 | get_src_reg (syntax_field, fields) |
438 | unsigned char syntax_field; | |
775fdd0c NC |
439 | CGEN_FIELDS * fields; |
440 | { | |
00aa5b17 DE |
441 | /* Relies upon the fact that no instruction with a $src1 operand |
442 | also has a $dr operand. */ | |
443 | return m32r_cgen_get_operand (CGEN_SYNTAX_FIELD (syntax_field), fields); | |
775fdd0c NC |
444 | } |
445 | ||
26192c50 NC |
446 | /* Returns zero iff the output register of instruction 'a' |
447 | is an input register to instruction 'b'. */ | |
448 | static int | |
449 | check_parallel_io_clash (a, b) | |
450 | m32r_insn * a; | |
451 | m32r_insn * b; | |
00aa5b17 DE |
452 | { |
453 | #if 0 /* FIXME: to be revisited. */ | |
454 | { | |
455 | const CGEN_INSN *insn; | |
456 | int a_indices[MAX_OPERAND_INSTANCES]; | |
457 | ||
458 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
459 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
460 | insn = m32r_cgen_get_insn_operands (a->insn, | |
461 | bfd_getb16 ((char *) a->buffer), 16, | |
462 | a_indices); | |
463 | if (! insn) | |
464 | as_fatal ("internal error: m32r_cgen_get_insn_operands"); | |
465 | } | |
466 | #endif | |
467 | ||
26192c50 NC |
468 | if (writes_to_dest_reg (a->insn)) |
469 | { | |
470 | unsigned char syntax_field; | |
471 | int skip = 0; | |
472 | ||
473 | while (syntax_field = reads_from_src_reg (b->insn, skip ++)) | |
474 | { | |
475 | if (get_src_reg (syntax_field, & b->fields) == get_dest_reg (a->fields)) | |
476 | return 0; | |
477 | } | |
478 | } | |
479 | ||
480 | return 1; | |
481 | } | |
482 | ||
89285fc9 NC |
483 | /* Returns non zero iff instruction 'a' has a side effect |
484 | that affects the destination of instruction 'b'. */ | |
485 | static int | |
486 | check_for_side_effects (a, b) | |
487 | m32r_insn * a; | |
488 | m32r_insn * b; | |
489 | { | |
490 | unsigned char syntax_field; | |
491 | ||
492 | if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_WRITE_SRC) != WRITE_SRC_YES) | |
493 | return 0; | |
494 | ||
495 | if (! writes_to_dest_reg (b->insn)) | |
496 | return 0; | |
497 | ||
498 | /* Find the source register. */ | |
499 | syntax_field = reads_from_src_reg (a->insn, 0); | |
500 | ||
501 | /* The st-plus and st-minus instructions have two sources, | |
502 | only the second one has a side effect. */ | |
503 | if (syntax_field == 128 + M32R_OPERAND_SRC1) | |
504 | syntax_field = reads_from_src_reg (a->insn, 1); /* We know that this will be src2 */ | |
505 | ||
506 | return get_dest_reg (b->fields) == get_src_reg (syntax_field, & a->fields); | |
507 | } | |
26192c50 | 508 | |
775fdd0c NC |
509 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
510 | otherwise it returns a pointer to an error message explaining why not. */ | |
511 | static const char * | |
26192c50 | 512 | can_make_parallel (a, b) |
b6930bdf NC |
513 | m32r_insn * a; |
514 | m32r_insn * b; | |
775fdd0c NC |
515 | { |
516 | PIPE_ATTR a_pipe; | |
517 | PIPE_ATTR b_pipe; | |
89285fc9 | 518 | |
775fdd0c | 519 | /* Make sure the instructions are the right length. */ |
b6930bdf NC |
520 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
521 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c | 522 | abort(); |
89285fc9 NC |
523 | |
524 | /* Make sure that the destinations are different. */ | |
525 | if ( writes_to_dest_reg (a->insn) | |
526 | && writes_to_dest_reg (b->insn) | |
527 | && (get_dest_reg (a->fields) == get_dest_reg (b->fields))) | |
528 | return "Instructions write to the same destination register."; | |
529 | ||
530 | /* Special case: Some instructions also modify their source register. */ | |
531 | if (check_for_side_effects (a, b)) | |
532 | return "Destination of second instruction written to by side effect of first instruction."; | |
533 | ||
534 | if (check_for_side_effects (b, a)) | |
535 | return "Destination of first instruction written to by side effect of second instruction."; | |
775fdd0c | 536 | |
89285fc9 NC |
537 | /* Special case: The branch-and-link type instructions also write to r14. */ |
538 | if (writes_to_dest_reg (b->insn) | |
539 | && get_dest_reg (b->fields) == 14 | |
540 | && CGEN_INSN_ATTR (a->insn, CGEN_INSN_WRITE_LR) == WRITE_LR_YES) | |
541 | return "Both instructions write to the link register"; | |
542 | ||
b6930bdf NC |
543 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
544 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 545 | |
b6930bdf | 546 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
547 | if ( a_pipe == PIPE_NONE |
548 | || b_pipe == PIPE_NONE) | |
549 | return "Instructions do not use parallel execution pipelines."; | |
89285fc9 NC |
550 | |
551 | /* Leave this test for last, since it is the only test that can | |
552 | go away if the instructions are swapped, and we want to make | |
553 | sure that any other errors are detected before this happens. */ | |
775fdd0c NC |
554 | if ( a_pipe == PIPE_S |
555 | || b_pipe == PIPE_O) | |
556 | return "Instructions share the same execution pipeline"; | |
89285fc9 | 557 | |
775fdd0c NC |
558 | return NULL; |
559 | } | |
775fdd0c NC |
560 | |
561 | #ifdef CGEN_INT_INSN | |
562 | static void | |
b6930bdf NC |
563 | make_parallel (buffer) |
564 | cgen_insn_t * buffer; | |
775fdd0c NC |
565 | { |
566 | /* Force the top bit of the second insn to be set. */ | |
567 | ||
568 | bfd_vma value; | |
569 | ||
570 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
571 | { | |
572 | value = bfd_getb16 ((bfd_byte *) buffer); | |
573 | value |= 0x8000; | |
574 | bfd_putb16 (value, (char *) buffer); | |
575 | } | |
576 | else | |
577 | { | |
578 | value = bfd_getl16 ((bfd_byte *) buffer); | |
579 | value |= 0x8000; | |
580 | bfd_putl16 (value, (char *) buffer); | |
581 | } | |
582 | } | |
583 | #else | |
584 | static void | |
b6930bdf NC |
585 | make_parallel (buffer) |
586 | char * buffer; | |
775fdd0c NC |
587 | { |
588 | /* Force the top bit of the second insn to be set. */ | |
589 | ||
590 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
591 | } | |
592 | #endif | |
593 | ||
594 | ||
b6930bdf NC |
595 | static void |
596 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 597 | char * str; |
b6930bdf | 598 | char * str2; |
c8cf7e17 | 599 | { |
b6930bdf NC |
600 | char * str3; |
601 | m32r_insn first; | |
602 | m32r_insn second; | |
603 | char * errmsg; | |
ebde3f62 | 604 | |
b6930bdf | 605 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 606 | |
b6930bdf NC |
607 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
608 | so that the parallel instruction will start on a 32 bit boundary. */ | |
609 | if (prev_insn.insn) | |
610 | fill_insn (0); | |
ebde3f62 | 611 | |
b6930bdf NC |
612 | /* Parse the first instruction. */ |
613 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
614 | (str, & first.fields, first.buffer, & errmsg))) | |
615 | { | |
616 | as_bad (errmsg); | |
617 | return; | |
618 | } | |
79420f9a | 619 | |
b6930bdf NC |
620 | /* Check to see if this is an allowable parallel insn. */ |
621 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
622 | { | |
623 | as_bad ("instruction '%s' cannot be executed in parallel.", str); | |
624 | return; | |
625 | } | |
ebde3f62 | 626 | |
b6930bdf NC |
627 | if (! enable_m32rx |
628 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
629 | { | |
630 | as_bad ("instruction '%s' is for the M32RX only", str); | |
631 | return; | |
ebde3f62 NC |
632 | } |
633 | ||
b6930bdf NC |
634 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
635 | str3 = str; /* Save the original string pointer. */ | |
636 | str = str2 + 2; /* Advanced past the parsed string. */ | |
637 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
638 | ||
639 | /* Preserve any fixups that have been generated and reset the list to empty. */ | |
640 | cgen_save_fixups(); | |
641 | ||
642 | /* Parse the second instruction. */ | |
643 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
644 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
645 | { |
646 | as_bad (errmsg); | |
647 | return; | |
648 | } | |
c8cf7e17 | 649 | |
b6930bdf NC |
650 | /* Check it. */ |
651 | if (! enable_m32rx | |
652 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
ebde3f62 NC |
653 | { |
654 | as_bad ("instruction '%s' is for the M32RX only", str); | |
655 | return; | |
656 | } | |
ebde3f62 | 657 | |
b6930bdf | 658 | if (! enable_m32rx) |
ebde3f62 | 659 | { |
b6930bdf NC |
660 | if ( strcmp (first.insn->name, "nop") != 0 |
661 | && strcmp (second.insn->name, "nop") != 0) | |
ebde3f62 | 662 | { |
b6930bdf NC |
663 | as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2); |
664 | return; | |
ebde3f62 | 665 | } |
b6930bdf | 666 | } |
9121b102 | 667 | |
b6930bdf NC |
668 | /* We assume that if the first instruction writes to a register that is |
669 | read by the second instruction it is because the programmer intended | |
670 | this to happen, (after all they have explicitly requested that these | |
26192c50 NC |
671 | two instructions be executed in parallel). Although if the global |
672 | variable warn_explicit_parallel_conflicts is true then we do generate | |
673 | a warning message. Similarly we assume that parallel branch and jump | |
00aa5b17 | 674 | instructions are deliberate and should not produce errors. */ |
b6930bdf | 675 | |
00aa5b17 | 676 | if (warn_explicit_parallel_conflicts) |
b6930bdf | 677 | { |
00aa5b17 | 678 | if (! check_parallel_io_clash (& first, & second)) |
89285fc9 | 679 | as_warn ("%s: output of first instruction is the same as the input of second instruction - is this intentional ?", str2); |
26192c50 | 680 | |
00aa5b17 DE |
681 | if (! check_parallel_io_clash (& second, & first)) |
682 | as_warn ("%s: output of second instruction is the same as the input of first instruction - is this intentional ?", str2); | |
683 | } | |
684 | ||
685 | if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL) | |
686 | { | |
b6930bdf NC |
687 | /* Get the fixups for the first instruction. */ |
688 | cgen_swap_fixups (); | |
689 | ||
690 | /* Write it out. */ | |
691 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
692 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
ebde3f62 | 693 | |
b6930bdf NC |
694 | /* Force the top bit of the second insn to be set. */ |
695 | make_parallel (second.buffer); | |
ebde3f62 | 696 | |
b6930bdf NC |
697 | /* Get its fixups. */ |
698 | cgen_restore_fixups (); | |
775fdd0c | 699 | |
b6930bdf NC |
700 | /* Write it out. */ |
701 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
702 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
703 | } | |
89285fc9 NC |
704 | /* Try swapping the instructions to see if they work that way. */ |
705 | else if (can_make_parallel (& second, & first, false, false) == NULL) | |
b6930bdf NC |
706 | { |
707 | /* Write out the second instruction first. */ | |
708 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
709 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
775fdd0c | 710 | |
b6930bdf NC |
711 | /* Force the top bit of the first instruction to be set. */ |
712 | make_parallel (first.buffer); | |
713 | ||
714 | /* Get the fixups for the first instruction. */ | |
715 | cgen_restore_fixups (); | |
716 | ||
717 | /* Write out the first instruction. */ | |
718 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
719 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
720 | } | |
721 | else | |
722 | { | |
723 | as_bad ("'%s': %s", str2, errmsg); | |
724 | return; | |
725 | } | |
ebde3f62 | 726 | |
b6930bdf NC |
727 | /* Set these so m32r_fill_insn can use them. */ |
728 | prev_seg = now_seg; | |
729 | prev_subseg = now_subseg; | |
730 | ||
731 | return; | |
732 | } | |
55a4759f DE |
733 | |
734 | #endif /* HAVE_CPU_M32RX */ | |
735 | ||
b6930bdf NC |
736 | /* end-sanitize-m32rx */ |
737 | ||
738 | ||
739 | void | |
740 | md_assemble (str) | |
741 | char * str; | |
742 | { | |
743 | m32r_insn insn; | |
744 | char * errmsg; | |
745 | char * str2 = NULL; | |
746 | ||
747 | /* Initialize GAS's cgen interface for a new instruction. */ | |
748 | cgen_asm_init_parse (); | |
749 | ||
750 | /* start-sanitize-m32rx */ | |
55a4759f | 751 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
752 | /* Look for a parallel instruction seperator. */ |
753 | if ((str2 = strstr (str, "||")) != NULL) | |
754 | { | |
755 | assemble_parallel_insn (str, str2); | |
756 | return; | |
ebde3f62 | 757 | } |
55a4759f | 758 | #endif |
b6930bdf NC |
759 | /* end-sanitize-m32rx */ |
760 | ||
761 | insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); | |
762 | if (!insn.insn) | |
763 | { | |
764 | as_bad (errmsg); | |
765 | return; | |
766 | } | |
767 | ||
768 | /* start-sanitize-m32rx */ | |
55a4759f | 769 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
770 | if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
771 | { | |
772 | as_bad ("instruction '%s' is for the M32RX only", str); | |
773 | return; | |
774 | } | |
55a4759f | 775 | #endif |
b6930bdf NC |
776 | /* end-sanitize-m32rx */ |
777 | ||
778 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
779 | { |
780 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 781 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 NC |
782 | { |
783 | /* FIXME: If calling fill_insn too many times turns us into a memory | |
784 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ | |
785 | fill_insn (0); | |
786 | } | |
787 | ||
b6930bdf NC |
788 | (void) cgen_asm_finish_insn (insn.insn, insn.buffer, |
789 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
c8cf7e17 DE |
790 | } |
791 | else | |
792 | { | |
b6930bdf NC |
793 | /* start-sanitize-m32rx */ |
794 | /* start-sanitize-phase2-m32rx */ | |
795 | int swap = false; | |
796 | /* end-sanitize-phase2-m32rx */ | |
797 | /* end-sanitize-m32rx */ | |
798 | ||
799 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
800 | abort(); | |
801 | ||
c8cf7e17 | 802 | /* Keep track of whether we've seen a pair of 16 bit insns. |
b6930bdf NC |
803 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
804 | if (prev_insn.insn) | |
775fdd0c NC |
805 | { |
806 | /* start-sanitize-m32rx */ | |
b6930bdf | 807 | /* start-sanitize-phase2-m32rx */ |
55a4759f | 808 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
809 | /* Look to see if this instruction can be combined with the |
810 | previous instruction to make one, parallel, 32 bit instruction. | |
811 | If the previous instruction (potentially) changed the flow of | |
812 | program control, then it cannot be combined with the current | |
ed295804 NC |
813 | instruction. Also if the output of the previous instruction |
814 | is used as an input to the current instruction then it cannot | |
815 | be combined. Otherwise call can_make_parallel() with both | |
b6930bdf NC |
816 | orderings of the instructions to see if they can be combined. */ |
817 | if ( ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_COND_CTI) | |
ed295804 NC |
818 | && ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_UNCOND_CTI) |
819 | && check_parallel_io_clash (& prev_insn, &insn) | |
820 | ) | |
775fdd0c | 821 | { |
ed295804 NC |
822 | if (can_make_parallel (& prev_insn, & insn) == NULL) |
823 | make_parallel (insn.buffer); | |
824 | else if (can_make_parallel (& insn, & prev_insn.insn) == NULL) | |
825 | swap = true; | |
775fdd0c | 826 | } |
55a4759f | 827 | #endif |
b6930bdf | 828 | /* end-sanitize-phase2-m32rx */ |
775fdd0c NC |
829 | /* end-sanitize-m32rx */ |
830 | ||
b6930bdf | 831 | prev_insn.insn = NULL; |
775fdd0c | 832 | } |
c8cf7e17 | 833 | else |
775fdd0c | 834 | { |
b6930bdf | 835 | prev_insn = insn; |
775fdd0c | 836 | } |
c8cf7e17 | 837 | |
b6930bdf NC |
838 | /* Record the frag that might be used by this insn. */ |
839 | insn.frag = frag_now; | |
840 | insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer, | |
841 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
842 | ||
843 | /* start-sanitize-m32rx */ | |
844 | /* start-sanitize-phase2-m32rx */ | |
55a4759f | 845 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
846 | if (swap) |
847 | { | |
848 | int tmp; | |
849 | ||
850 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
851 | ||
852 | /* Swap the two insns */ | |
853 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
854 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
855 | ||
856 | make_parallel (insn.addr); | |
857 | ||
858 | /* Swap any relaxable frags recorded for the two insns. */ | |
859 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
860 | { | |
861 | prev_insn.frag->fr_opcode = insn.addr; | |
862 | } | |
863 | else if (insn.frag->fr_opcode == insn.addr) | |
864 | { | |
865 | insn.frag->fr_opcode = prev_insn.addr; | |
866 | } | |
867 | } | |
868 | /* end-sanitize-phase2-m32rx */ | |
869 | ||
870 | /* Record where this instruction was assembled. */ | |
871 | prev_insn.addr = insn.addr; | |
872 | prev_insn.frag = insn.frag; | |
55a4759f | 873 | #endif |
b6930bdf NC |
874 | /* end-sanitize-m32rx */ |
875 | ||
c8cf7e17 DE |
876 | /* If the insn needs the following one to be on a 32 bit boundary |
877 | (e.g. subroutine calls), fill this insn's slot. */ | |
b6930bdf NC |
878 | if (prev_insn.insn |
879 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0) | |
c8cf7e17 | 880 | fill_insn (0); |
c8cf7e17 | 881 | |
775fdd0c | 882 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
883 | mark the fact so that we can emit an alignment directive for a |
884 | following 32 bit insn if we see one. */ | |
885 | if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0) | |
775fdd0c NC |
886 | seen_relaxable_p = 1; |
887 | } | |
c8cf7e17 DE |
888 | |
889 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 890 | prev_seg = now_seg; |
c8cf7e17 DE |
891 | prev_subseg = now_subseg; |
892 | } | |
893 | ||
894 | /* The syntax in the manual says constants begin with '#'. | |
895 | We just ignore it. */ | |
896 | ||
897 | void | |
898 | md_operand (expressionP) | |
ebde3f62 | 899 | expressionS * expressionP; |
c8cf7e17 | 900 | { |
ebde3f62 | 901 | if (* input_line_pointer == '#') |
c8cf7e17 | 902 | { |
ebde3f62 | 903 | input_line_pointer ++; |
c8cf7e17 DE |
904 | expression (expressionP); |
905 | } | |
906 | } | |
907 | ||
908 | valueT | |
909 | md_section_align (segment, size) | |
ebde3f62 | 910 | segT segment; |
c8cf7e17 DE |
911 | valueT size; |
912 | { | |
913 | int align = bfd_get_section_alignment (stdoutput, segment); | |
914 | return ((size + (1 << align) - 1) & (-1 << align)); | |
915 | } | |
916 | ||
917 | symbolS * | |
918 | md_undefined_symbol (name) | |
ebde3f62 | 919 | char * name; |
c8cf7e17 DE |
920 | { |
921 | return 0; | |
922 | } | |
923 | \f | |
924 | /* .scomm pseudo-op handler. | |
925 | ||
926 | This is a new pseudo-op to handle putting objects in .scommon. | |
927 | By doing this the linker won't need to do any work and more importantly | |
928 | it removes the implicit -G arg necessary to correctly link the object file. | |
929 | */ | |
930 | ||
931 | static void | |
932 | m32r_scomm (ignore) | |
933 | int ignore; | |
934 | { | |
ebde3f62 NC |
935 | register char * name; |
936 | register char c; | |
937 | register char * p; | |
938 | offsetT size; | |
939 | register symbolS * symbolP; | |
940 | offsetT align; | |
941 | int align2; | |
c8cf7e17 DE |
942 | |
943 | name = input_line_pointer; | |
944 | c = get_symbol_end (); | |
945 | ||
946 | /* just after name is now '\0' */ | |
947 | p = input_line_pointer; | |
ebde3f62 | 948 | * p = c; |
c8cf7e17 | 949 | SKIP_WHITESPACE (); |
ebde3f62 | 950 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
951 | { |
952 | as_bad ("Expected comma after symbol-name: rest of line ignored."); | |
953 | ignore_rest_of_line (); | |
954 | return; | |
955 | } | |
956 | ||
b6930bdf | 957 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
958 | if ((size = get_absolute_expression ()) < 0) |
959 | { | |
960 | as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size); | |
961 | ignore_rest_of_line (); | |
962 | return; | |
963 | } | |
964 | ||
965 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 966 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
967 | align = 8; |
968 | else | |
969 | { | |
ebde3f62 | 970 | ++ input_line_pointer; |
c8cf7e17 DE |
971 | align = get_absolute_expression (); |
972 | if (align <= 0) | |
973 | { | |
974 | as_warn ("ignoring bad alignment"); | |
975 | align = 8; | |
976 | } | |
977 | } | |
978 | /* Convert to a power of 2 alignment. */ | |
979 | if (align) | |
980 | { | |
ebde3f62 | 981 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
982 | continue; |
983 | if (align != 1) | |
984 | { | |
985 | as_bad ("Common alignment not a power of 2"); | |
986 | ignore_rest_of_line (); | |
987 | return; | |
988 | } | |
989 | } | |
990 | else | |
991 | align2 = 0; | |
992 | ||
ebde3f62 | 993 | * p = 0; |
c8cf7e17 | 994 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 995 | * p = c; |
c8cf7e17 DE |
996 | |
997 | if (S_IS_DEFINED (symbolP)) | |
998 | { | |
999 | as_bad ("Ignoring attempt to re-define symbol `%s'.", | |
1000 | S_GET_NAME (symbolP)); | |
1001 | ignore_rest_of_line (); | |
1002 | return; | |
1003 | } | |
1004 | ||
1005 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1006 | { | |
1007 | as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.", | |
1008 | S_GET_NAME (symbolP), | |
1009 | (long) S_GET_VALUE (symbolP), | |
1010 | (long) size); | |
1011 | ||
1012 | ignore_rest_of_line (); | |
1013 | return; | |
1014 | } | |
1015 | ||
1016 | if (symbolP->local) | |
1017 | { | |
ebde3f62 NC |
1018 | segT old_sec = now_seg; |
1019 | int old_subsec = now_subseg; | |
1020 | char * pfrag; | |
c8cf7e17 DE |
1021 | |
1022 | record_alignment (sbss_section, align2); | |
1023 | subseg_set (sbss_section, 0); | |
775fdd0c | 1024 | |
c8cf7e17 DE |
1025 | if (align2) |
1026 | frag_align (align2, 0, 0); | |
775fdd0c | 1027 | |
c8cf7e17 DE |
1028 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
1029 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 1030 | |
c8cf7e17 | 1031 | symbolP->sy_frag = frag_now; |
b6930bdf | 1032 | |
c8cf7e17 DE |
1033 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1034 | (char *) 0); | |
ebde3f62 | 1035 | * pfrag = 0; |
c8cf7e17 DE |
1036 | S_SET_SIZE (symbolP, size); |
1037 | S_SET_SEGMENT (symbolP, sbss_section); | |
1038 | S_CLEAR_EXTERNAL (symbolP); | |
1039 | subseg_set (old_sec, old_subsec); | |
1040 | } | |
1041 | else | |
1042 | { | |
1043 | S_SET_VALUE (symbolP, (valueT) size); | |
1044 | S_SET_ALIGN (symbolP, align2); | |
1045 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 1046 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
1047 | } |
1048 | ||
1049 | demand_empty_rest_of_line (); | |
1050 | } | |
1051 | \f | |
1052 | /* Interface to relax_segment. */ | |
1053 | ||
1054 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1055 | ||
1056 | const relax_typeS md_relax_table[] = | |
1057 | { | |
1058 | /* The fields are: | |
1059 | 1) most positive reach of this state, | |
1060 | 2) most negative reach of this state, | |
1061 | 3) how many bytes this mode will add to the size of the current frag | |
1062 | 4) which index into the table to try if we can't fit into this one. */ | |
1063 | ||
1064 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1065 | each list. */ | |
1066 | {1, 1, 0, 0}, | |
1067 | ||
1068 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1069 | so we subtract 2 from the following. */ | |
1070 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1071 | This doesn't handle a branch in the right slot at the border: | |
1072 | the "& -4" isn't taken into account. It's not important enough to | |
1073 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1074 | case). */ | |
1075 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1076 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1077 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1078 | /* Same thing, but with leading nop for alignment. */ | |
1079 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1080 | }; | |
1081 | ||
1082 | long | |
1083 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1084 | fragS * fragP; |
1085 | long stretch; | |
c8cf7e17 DE |
1086 | { |
1087 | /* Address of branch insn. */ | |
1088 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1089 | long growth = 0; | |
1090 | ||
1091 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1092 | if (fragP->fr_subtype == 2) | |
1093 | { | |
1094 | if ((address & 3) != 0) | |
1095 | { | |
1096 | fragP->fr_subtype = 3; | |
1097 | growth = 2; | |
1098 | } | |
1099 | } | |
1100 | else if (fragP->fr_subtype == 3) | |
1101 | { | |
1102 | if ((address & 3) == 0) | |
1103 | { | |
1104 | fragP->fr_subtype = 2; | |
1105 | growth = -2; | |
1106 | } | |
1107 | } | |
1108 | else | |
1109 | { | |
1110 | growth = relax_frag (fragP, stretch); | |
1111 | ||
1112 | /* Long jump on odd halfword boundary? */ | |
1113 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1114 | { | |
1115 | fragP->fr_subtype = 3; | |
1116 | growth += 2; | |
1117 | } | |
1118 | } | |
1119 | ||
1120 | return growth; | |
1121 | } | |
1122 | ||
1123 | /* Return an initial guess of the length by which a fragment must grow to | |
1124 | hold a branch to reach its destination. | |
1125 | Also updates fr_type/fr_subtype as necessary. | |
1126 | ||
1127 | Called just before doing relaxation. | |
1128 | Any symbol that is now undefined will not become defined. | |
1129 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1130 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1131 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1132 | 0 value. */ | |
1133 | ||
1134 | int | |
1135 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1136 | fragS * fragP; |
1137 | segT segment; | |
c8cf7e17 | 1138 | { |
ebde3f62 NC |
1139 | int old_fr_fix = fragP->fr_fix; |
1140 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1141 | |
1142 | /* The only thing we have to handle here are symbols outside of the | |
1143 | current segment. They may be undefined or in a different segment in | |
1144 | which case linker scripts may place them anywhere. | |
1145 | However, we can't finish the fragment here and emit the reloc as insn | |
1146 | alignment requirements may move the insn about. */ | |
1147 | ||
1148 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1149 | { | |
1150 | /* The symbol is undefined in this segment. | |
1151 | Change the relaxation subtype to the max allowable and leave | |
1152 | all further handling to md_convert_frag. */ | |
1153 | fragP->fr_subtype = 2; | |
1154 | ||
1155 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1156 | /* Change 16 bit insn to 32 bit insn. */ | |
1157 | opcode[0] |= 0x80; | |
1158 | ||
1159 | /* Increase known (fixed) size of fragment. */ | |
1160 | fragP->fr_fix += 2; | |
1161 | ||
1162 | /* Create a relocation for it. */ | |
1163 | fix_new (fragP, old_fr_fix, 4, | |
1164 | fragP->fr_symbol, | |
1165 | fragP->fr_offset, 1 /* pcrel */, | |
1166 | /* FIXME: Can't use a real BFD reloc here. | |
1167 | cgen_md_apply_fix3 can't handle it. */ | |
1168 | BFD_RELOC_M32R_26_PCREL); | |
1169 | ||
1170 | /* Mark this fragment as finished. */ | |
1171 | frag_wane (fragP); | |
1172 | #else | |
a450e9f4 | 1173 | { |
ebde3f62 NC |
1174 | const CGEN_INSN * insn; |
1175 | int i; | |
a450e9f4 NC |
1176 | |
1177 | /* Update the recorded insn. | |
1178 | Fortunately we don't have to look very far. | |
1179 | FIXME: Change this to record in the instruction the next higher | |
1180 | relaxable insn to use. */ | |
1181 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1182 | { | |
b5e9e562 DE |
1183 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1184 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1185 | == 0) |
1186 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1187 | break; | |
1188 | } | |
1189 | if (i == 4) | |
1190 | abort (); | |
b6930bdf | 1191 | |
a450e9f4 NC |
1192 | fragP->fr_cgen.insn = insn; |
1193 | return 2; | |
1194 | } | |
c8cf7e17 DE |
1195 | #endif |
1196 | } | |
1197 | ||
1198 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1199 | } | |
1200 | ||
1201 | /* *fragP has been relaxed to its final size, and now needs to have | |
1202 | the bytes inside it modified to conform to the new size. | |
1203 | ||
1204 | Called after relaxation is finished. | |
1205 | fragP->fr_type == rs_machine_dependent. | |
1206 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1207 | ||
1208 | void | |
1209 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1210 | bfd * abfd; |
1211 | segT sec; | |
1212 | fragS * fragP; | |
c8cf7e17 | 1213 | { |
ebde3f62 NC |
1214 | char * opcode; |
1215 | char * displacement; | |
1216 | int target_address; | |
1217 | int opcode_address; | |
1218 | int extension; | |
1219 | int addend; | |
c8cf7e17 DE |
1220 | |
1221 | opcode = fragP->fr_opcode; | |
1222 | ||
1223 | /* Address opcode resides at in file space. */ | |
1224 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1225 | ||
1226 | switch (fragP->fr_subtype) | |
1227 | { | |
1228 | case 1 : | |
1229 | extension = 0; | |
ebde3f62 | 1230 | displacement = & opcode[1]; |
c8cf7e17 DE |
1231 | break; |
1232 | case 2 : | |
1233 | opcode[0] |= 0x80; | |
1234 | extension = 2; | |
ebde3f62 | 1235 | displacement = & opcode[1]; |
c8cf7e17 DE |
1236 | break; |
1237 | case 3 : | |
1238 | opcode[2] = opcode[0] | 0x80; | |
1239 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1240 | opcode_address += 2; | |
1241 | extension = 4; | |
ebde3f62 | 1242 | displacement = & opcode[3]; |
c8cf7e17 DE |
1243 | break; |
1244 | default : | |
1245 | abort (); | |
1246 | } | |
1247 | ||
1248 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1249 | { | |
1250 | /* symbol must be resolved by linker */ | |
1251 | if (fragP->fr_offset & 3) | |
1252 | as_warn ("Addend to unresolved symbol not on word boundary."); | |
1253 | addend = fragP->fr_offset >> 2; | |
1254 | } | |
1255 | else | |
1256 | { | |
1257 | /* Address we want to reach in file space. */ | |
1258 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1259 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1260 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1261 | } | |
1262 | ||
1263 | /* Create a relocation for symbols that must be resolved by the linker. | |
1264 | Otherwise output the completed insn. */ | |
1265 | ||
1266 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1267 | { | |
1268 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1269 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1270 | cgen_record_fixup (fragP, |
1271 | /* Offset of branch insn in frag. */ | |
1272 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1273 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1274 | 4 /*length*/, |
1275 | /* FIXME: quick hack */ | |
1276 | #if 0 | |
a450e9f4 | 1277 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1278 | #else |
1279 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1280 | #endif | |
a450e9f4 | 1281 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1282 | fragP->fr_symbol, fragP->fr_offset); |
1283 | } | |
1284 | ||
1285 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1286 | ||
1287 | md_number_to_chars (displacement, (valueT) addend, | |
1288 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1289 | ||
1290 | fragP->fr_fix += extension; | |
1291 | } | |
1292 | \f | |
1293 | /* Functions concerning relocs. */ | |
1294 | ||
1295 | /* The location from which a PC relative jump should be calculated, | |
1296 | given a PC relative reloc. */ | |
1297 | ||
1298 | long | |
1299 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1300 | fixS * fixP; |
1301 | segT sec; | |
c8cf7e17 DE |
1302 | { |
1303 | if (fixP->fx_addsy != (symbolS *) NULL | |
1304 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1305 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1306 | { | |
1307 | /* The symbol is undefined (or is defined but not in this section). | |
1308 | Let the linker figure it out. */ | |
1309 | return 0; | |
1310 | } | |
1311 | ||
1312 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1313 | } | |
1314 | ||
1315 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1316 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1317 | *FIXP may be modified if desired. */ | |
1318 | ||
1319 | bfd_reloc_code_real_type | |
1320 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1321 | const CGEN_INSN * insn; |
1322 | const CGEN_OPERAND * operand; | |
1323 | fixS * fixP; | |
c8cf7e17 DE |
1324 | { |
1325 | switch (CGEN_OPERAND_TYPE (operand)) | |
1326 | { | |
1327 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1328 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1329 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1330 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1331 | case M32R_OPERAND_HI16 : | |
1332 | case M32R_OPERAND_SLO16 : | |
1333 | case M32R_OPERAND_ULO16 : | |
1334 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1335 | if (fixP->tc_fix_data.opinfo != 0) | |
1336 | return fixP->tc_fix_data.opinfo; | |
1337 | break; | |
1338 | } | |
1339 | return BFD_RELOC_NONE; | |
1340 | } | |
1341 | ||
b6930bdf NC |
1342 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1343 | ||
1344 | static void | |
1345 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1346 | int reloc_type; | |
1347 | fixS * fixP; | |
1348 | segT seg; | |
1349 | { | |
1350 | struct m32r_hi_fixup * hi_fixup; | |
1351 | ||
1352 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1353 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1354 | ||
1355 | hi_fixup = ((struct m32r_hi_fixup *) | |
1356 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1357 | hi_fixup->fixp = fixP; | |
1358 | hi_fixup->seg = now_seg; | |
1359 | hi_fixup->next = m32r_hi_fixup_list; | |
1360 | ||
1361 | m32r_hi_fixup_list = hi_fixup; | |
1362 | } | |
1363 | ||
c8cf7e17 DE |
1364 | /* Called while parsing an instruction to create a fixup. |
1365 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1366 | ||
1367 | fixS * | |
1368 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1369 | fragS * frag; |
1370 | int where; | |
1371 | const CGEN_INSN * insn; | |
1372 | int length; | |
1373 | const CGEN_OPERAND * operand; | |
1374 | int opinfo; | |
1375 | expressionS * exp; | |
c8cf7e17 | 1376 | { |
ebde3f62 NC |
1377 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1378 | operand, opinfo, exp); | |
c8cf7e17 DE |
1379 | |
1380 | switch (CGEN_OPERAND_TYPE (operand)) | |
1381 | { | |
1382 | case M32R_OPERAND_HI16 : | |
1383 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1384 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1385 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1386 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1387 | break; | |
1388 | } | |
1389 | ||
1390 | return fixP; | |
1391 | } | |
1392 | ||
c8cf7e17 DE |
1393 | /* Return BFD reloc type from opinfo field in a fixS. |
1394 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1395 | are BFD_RELOC_UNUSED + operand number. */ | |
1396 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1397 | ||
1398 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1399 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1400 | tc_gen_reloc. */ | |
1401 | ||
1402 | void | |
1403 | m32r_frob_file () | |
1404 | { | |
ebde3f62 | 1405 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1406 | |
1407 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1408 | { | |
ebde3f62 NC |
1409 | segment_info_type * seginfo; |
1410 | int pass; | |
c8cf7e17 DE |
1411 | |
1412 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1413 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1414 | ||
1415 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1416 | if (l->fixp->fx_next != NULL | |
1417 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1418 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1419 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1420 | continue; | |
1421 | ||
1422 | /* Look through the fixups for this segment for a matching `low'. | |
1423 | When we find one, move the high/shigh just in front of it. We do | |
1424 | this in two passes. In the first pass, we try to find a | |
1425 | unique `low'. In the second pass, we permit multiple high's | |
1426 | relocs for a single `low'. */ | |
1427 | seginfo = seg_info (l->seg); | |
1428 | for (pass = 0; pass < 2; pass++) | |
1429 | { | |
ebde3f62 NC |
1430 | fixS * f; |
1431 | fixS * prev; | |
c8cf7e17 DE |
1432 | |
1433 | prev = NULL; | |
1434 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1435 | { | |
1436 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1437 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1438 | && f->fx_addsy == l->fixp->fx_addsy | |
1439 | && f->fx_offset == l->fixp->fx_offset | |
1440 | && (pass == 1 | |
1441 | || prev == NULL | |
1442 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1443 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1444 | || prev->fx_addsy != f->fx_addsy | |
1445 | || prev->fx_offset != f->fx_offset)) | |
1446 | { | |
ebde3f62 | 1447 | fixS ** pf; |
c8cf7e17 DE |
1448 | |
1449 | /* Move l->fixp before f. */ | |
1450 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1451 | * pf != l->fixp; |
1452 | pf = & (* pf)->fx_next) | |
1453 | assert (* pf != NULL); | |
c8cf7e17 | 1454 | |
ebde3f62 | 1455 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1456 | |
1457 | l->fixp->fx_next = f; | |
1458 | if (prev == NULL) | |
1459 | seginfo->fix_root = l->fixp; | |
1460 | else | |
1461 | prev->fx_next = l->fixp; | |
1462 | ||
1463 | break; | |
1464 | } | |
1465 | ||
1466 | prev = f; | |
1467 | } | |
1468 | ||
1469 | if (f != NULL) | |
1470 | break; | |
1471 | ||
1472 | if (pass == 1) | |
1473 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1474 | "Unmatched high/shigh reloc"); | |
1475 | } | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | /* See whether we need to force a relocation into the output file. | |
1480 | This is used to force out switch and PC relative relocations when | |
1481 | relaxing. */ | |
1482 | ||
1483 | int | |
1484 | m32r_force_relocation (fix) | |
ebde3f62 | 1485 | fixS * fix; |
c8cf7e17 DE |
1486 | { |
1487 | if (! m32r_relax) | |
1488 | return 0; | |
1489 | ||
1490 | return (fix->fx_pcrel | |
1491 | || 0 /* ??? */); | |
1492 | } | |
1493 | \f | |
1494 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1495 | ||
1496 | void | |
1497 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1498 | char * buf; |
c8cf7e17 | 1499 | valueT val; |
ebde3f62 | 1500 | int n; |
c8cf7e17 DE |
1501 | { |
1502 | if (target_big_endian) | |
1503 | number_to_chars_bigendian (buf, val, n); | |
1504 | else | |
1505 | number_to_chars_littleendian (buf, val, n); | |
1506 | } | |
1507 | ||
1508 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1509 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1510 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1511 | */ | |
1512 | ||
1513 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1514 | #define MAX_LITTLENUMS 6 | |
1515 | ||
1516 | char * | |
1517 | md_atof (type, litP, sizeP) | |
1518 | char type; | |
1519 | char *litP; | |
1520 | int *sizeP; | |
1521 | { | |
ebde3f62 NC |
1522 | int i; |
1523 | int prec; | |
1524 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1525 | LITTLENUM_TYPE * wordP; | |
1526 | char * t; | |
1527 | char * atof_ieee (); | |
c8cf7e17 DE |
1528 | |
1529 | switch (type) | |
1530 | { | |
1531 | case 'f': | |
1532 | case 'F': | |
1533 | case 's': | |
1534 | case 'S': | |
1535 | prec = 2; | |
1536 | break; | |
1537 | ||
1538 | case 'd': | |
1539 | case 'D': | |
1540 | case 'r': | |
1541 | case 'R': | |
1542 | prec = 4; | |
1543 | break; | |
1544 | ||
1545 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1546 | ||
1547 | default: | |
ebde3f62 | 1548 | * sizeP = 0; |
c8cf7e17 DE |
1549 | return "Bad call to md_atof()"; |
1550 | } | |
1551 | ||
1552 | t = atof_ieee (input_line_pointer, type, words); | |
1553 | if (t) | |
1554 | input_line_pointer = t; | |
ebde3f62 | 1555 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1556 | |
1557 | if (target_big_endian) | |
1558 | { | |
1559 | for (i = 0; i < prec; i++) | |
1560 | { | |
ebde3f62 NC |
1561 | md_number_to_chars (litP, (valueT) words[i], |
1562 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1563 | litP += sizeof (LITTLENUM_TYPE); |
1564 | } | |
1565 | } | |
1566 | else | |
1567 | { | |
1568 | for (i = prec - 1; i >= 0; i--) | |
1569 | { | |
ebde3f62 NC |
1570 | md_number_to_chars (litP, (valueT) words[i], |
1571 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1572 | litP += sizeof (LITTLENUM_TYPE); |
1573 | } | |
1574 | } | |
1575 | ||
1576 | return 0; | |
1577 | } |