Commit | Line | Data |
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76090fdd | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "cgen-opc.h" | |
26 | ||
b86c0dd3 | 27 | /* Structure to hold all of the different components describing an individual instruction. */ |
b6930bdf NC |
28 | typedef struct |
29 | { | |
30 | const CGEN_INSN * insn; | |
31 | CGEN_FIELDS fields; | |
32 | #ifdef CGEN_INT_INSN | |
33 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
34 | #else | |
35 | char buffer [CGEN_MAX_INSN_SIZE]; | |
36 | #endif | |
37 | char * addr; | |
38 | fragS * frag; | |
6cf2575a | 39 | int indices [MAX_OPERAND_INSTANCES]; |
b6930bdf NC |
40 | } |
41 | m32r_insn; | |
42 | ||
43 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
44 | boundary (i.e. was the first of two 16 bit insns). */ | |
45 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
46 | |
47 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
48 | alignment request. */ | |
49 | static int seen_relaxable_p = 0; | |
50 | ||
51 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
52 | for the linker to do relaxing. | |
53 | We do simple forms of relaxing internally, but they are always done. | |
54 | This flag does not apply to them. */ | |
55 | static int m32r_relax; | |
56 | ||
57 | /* If non-NULL, pointer to cpu description file to read. | |
58 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 59 | static char * m32r_cpu_desc; |
c8cf7e17 | 60 | |
b5e9e562 | 61 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
62 | /* Non-zero if -m32rx has been specified, in which case support for the |
63 | extended M32RX instruction set should be enabled. */ | |
a450e9f4 | 64 | static int enable_m32rx = 0; |
b6930bdf NC |
65 | |
66 | /* Non-zero if the programmer should be warned when an explicit parallel | |
67 | instruction might have constraint violations. */ | |
68 | static int warn_explicit_parallel_conflicts = 1; | |
b5e9e562 | 69 | /* end-sanitize-m32rx */ |
a450e9f4 | 70 | |
c8cf7e17 | 71 | /* stuff for .scomm symbols. */ |
ebde3f62 | 72 | static segT sbss_section; |
c8cf7e17 | 73 | static asection scom_section; |
ebde3f62 | 74 | static asymbol scom_symbol; |
c8cf7e17 | 75 | |
ebde3f62 NC |
76 | const char comment_chars[] = ";"; |
77 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 78 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
79 | const char EXP_CHARS[] = "eE"; |
80 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
81 | |
82 | /* Relocations against symbols are done in two | |
83 | parts, with a HI relocation and a LO relocation. Each relocation | |
84 | has only 16 bits of space to store an addend. This means that in | |
85 | order for the linker to handle carries correctly, it must be able | |
86 | to locate both the HI and the LO relocation. This means that the | |
87 | relocations must appear in order in the relocation table. | |
88 | ||
89 | In order to implement this, we keep track of each unmatched HI | |
90 | relocation. We then sort them so that they immediately precede the | |
91 | corresponding LO relocation. */ | |
92 | ||
93 | struct m32r_hi_fixup | |
94 | { | |
ebde3f62 NC |
95 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
96 | fixS * fixp; /* This fixup. */ | |
97 | segT seg; /* The section this fixup is in. */ | |
98 | ||
c8cf7e17 DE |
99 | }; |
100 | ||
101 | /* The list of unmatched HI relocs. */ | |
102 | ||
ebde3f62 | 103 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 104 | |
a450e9f4 | 105 | \f |
b5e9e562 | 106 | /* start-sanitize-m32rx */ |
a450e9f4 | 107 | static void |
55a4759f DE |
108 | allow_m32rx (on) |
109 | int on; | |
a450e9f4 NC |
110 | { |
111 | enable_m32rx = on; | |
112 | ||
113 | if (stdoutput != NULL) | |
ebde3f62 NC |
114 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
115 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 116 | } |
b5e9e562 | 117 | /* end-sanitize-m32rx */ |
c8cf7e17 | 118 | \f |
ebde3f62 | 119 | const char * md_shortopts = ""; |
c8cf7e17 | 120 | |
a450e9f4 NC |
121 | struct option md_longopts[] = |
122 | { | |
b5e9e562 | 123 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
124 | #define OPTION_M32RX (OPTION_MD_BASE) |
125 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
b6930bdf NC |
126 | #define OPTION_WARN (OPTION_MD_BASE + 1) |
127 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN}, | |
128 | #define OPTION_NO_WARN (OPTION_MD_BASE + 2) | |
129 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, | |
b5e9e562 | 130 | /* end-sanitize-m32rx */ |
a450e9f4 | 131 | |
c8cf7e17 | 132 | #if 0 /* not supported yet */ |
b6930bdf | 133 | #define OPTION_RELAX (OPTION_MD_BASE + 3) |
c8cf7e17 | 134 | {"relax", no_argument, NULL, OPTION_RELAX}, |
b6930bdf | 135 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 4) |
c8cf7e17 DE |
136 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
137 | #endif | |
a450e9f4 | 138 | |
c8cf7e17 DE |
139 | {NULL, no_argument, NULL, 0} |
140 | }; | |
ebde3f62 | 141 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
142 | |
143 | int | |
144 | md_parse_option (c, arg) | |
ebde3f62 NC |
145 | int c; |
146 | char * arg; | |
c8cf7e17 DE |
147 | { |
148 | switch (c) | |
149 | { | |
b5e9e562 | 150 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
151 | case OPTION_M32RX: |
152 | allow_m32rx (1); | |
153 | break; | |
b6930bdf NC |
154 | |
155 | case OPTION_WARN: | |
156 | warn_explicit_parallel_conflicts = 1; | |
157 | break; | |
158 | ||
159 | case OPTION_NO_WARN: | |
160 | warn_explicit_parallel_conflicts = 0; | |
161 | break; | |
b5e9e562 | 162 | /* end-sanitize-m32rx */ |
a450e9f4 | 163 | |
c8cf7e17 DE |
164 | #if 0 /* not supported yet */ |
165 | case OPTION_RELAX: | |
166 | m32r_relax = 1; | |
167 | break; | |
168 | case OPTION_CPU_DESC: | |
169 | m32r_cpu_desc = arg; | |
170 | break; | |
171 | #endif | |
172 | default: | |
173 | return 0; | |
174 | } | |
175 | return 1; | |
176 | } | |
177 | ||
178 | void | |
179 | md_show_usage (stream) | |
ebde3f62 | 180 | FILE * stream; |
c8cf7e17 | 181 | { |
a450e9f4 | 182 | fprintf (stream, "M32R/X options:\n"); |
b5e9e562 | 183 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
184 | fprintf (stream, "\ |
185 | --m32rx support the extended m32rx instruction set\n"); | |
b6930bdf NC |
186 | |
187 | fprintf (stream, "\ | |
00aa5b17 DE |
188 | --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n"); |
189 | fprintf (stream, "\ | |
b6930bdf | 190 | --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n"); |
b5e9e562 | 191 | /* end-sanitize-m32rx */ |
a450e9f4 | 192 | |
c8cf7e17 DE |
193 | #if 0 |
194 | fprintf (stream, "\ | |
195 | --relax create linker relaxable code\n"); | |
196 | fprintf (stream, "\ | |
197 | --cpu-desc provide runtime cpu description file\n"); | |
c8cf7e17 DE |
198 | #endif |
199 | } | |
200 | ||
201 | static void fill_insn PARAMS ((int)); | |
202 | static void m32r_scomm PARAMS ((int)); | |
203 | ||
204 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
205 | static subsegT prev_subseg; | |
206 | static segT prev_seg; | |
207 | ||
208 | /* The target specific pseudo-ops which we support. */ | |
209 | const pseudo_typeS md_pseudo_table[] = | |
210 | { | |
211 | { "word", cons, 4 }, | |
212 | { "fillinsn", fill_insn, 0 }, | |
213 | { "scomm", m32r_scomm, 0 }, | |
b5e9e562 | 214 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
215 | { "m32r", allow_m32rx, 0}, |
216 | { "m32rx", allow_m32rx, 1}, | |
b5e9e562 | 217 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
218 | { NULL, NULL, 0 } |
219 | }; | |
220 | ||
221 | /* FIXME: Should be machine generated. */ | |
222 | #define NOP_INSN 0x7000 | |
223 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
224 | ||
225 | /* When we align the .text section, insert the correct NOP pattern. | |
226 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
227 | MAX is the maximum number of characters to skip when doing the alignment, | |
228 | or 0 if there is no maximum. */ | |
229 | ||
230 | int | |
231 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
232 | int n; |
233 | const char * fill; | |
234 | int len; | |
235 | int max; | |
c8cf7e17 | 236 | { |
ebde3f62 | 237 | if ((fill == NULL || (* fill == 0 && len == 1)) |
c8cf7e17 DE |
238 | && (now_seg->flags & SEC_CODE) != 0 |
239 | /* Only do this special handling if aligning to at least a | |
240 | 4 byte boundary. */ | |
241 | && n > 1 | |
775fdd0c | 242 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
243 | least two bytes. */ |
244 | && (max == 0 || max > 1)) | |
245 | { | |
246 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
247 | ||
248 | #if 0 | |
249 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
250 | /* FIXME: How much memory will cause gas to use when assembling a big | |
251 | program? Perhaps we can avoid the frag_align call? */ | |
252 | frag_align (1, 0, 0); | |
253 | #endif | |
254 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
255 | nop. */ | |
256 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
257 | /* If doing larger alignments use a repeating sequence of appropriate | |
258 | nops. */ | |
259 | if (n > 2) | |
260 | { | |
ebde3f62 NC |
261 | static const unsigned char multi_nop_pattern[] = |
262 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
263 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
264 | max ? max - 2 : 0); | |
265 | } | |
266 | return 1; | |
267 | } | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | static void | |
273 | assemble_nop (opcode) | |
274 | int opcode; | |
275 | { | |
ebde3f62 | 276 | char * f = frag_more (2); |
c8cf7e17 DE |
277 | md_number_to_chars (f, opcode, 2); |
278 | } | |
279 | ||
280 | /* If the last instruction was the first of 2 16 bit insns, | |
281 | output a nop to move the PC to a 32 bit boundary. | |
282 | ||
283 | This is done via an alignment specification since branch relaxing | |
284 | may make it unnecessary. | |
285 | ||
286 | Internally, we need to output one of these each time a 32 bit insn is | |
287 | seen after an insn that is relaxable. */ | |
288 | ||
289 | static void | |
290 | fill_insn (ignore) | |
291 | int ignore; | |
292 | { | |
293 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 294 | prev_insn.insn = NULL; |
c8cf7e17 DE |
295 | seen_relaxable_p = 0; |
296 | } | |
297 | ||
298 | /* Cover function to fill_insn called after a label and at end of assembly. | |
299 | ||
300 | The result is always 1: we're called in a conditional to see if the | |
301 | current line is a label. */ | |
302 | ||
303 | int | |
304 | m32r_fill_insn (done) | |
305 | int done; | |
306 | { | |
ebde3f62 | 307 | segT seg; |
c8cf7e17 DE |
308 | subsegT subseg; |
309 | ||
310 | if (prev_seg != NULL) | |
311 | { | |
ebde3f62 | 312 | seg = now_seg; |
c8cf7e17 | 313 | subseg = now_subseg; |
ebde3f62 | 314 | |
c8cf7e17 | 315 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 316 | |
c8cf7e17 | 317 | fill_insn (0); |
ebde3f62 | 318 | |
c8cf7e17 DE |
319 | subseg_set (seg, subseg); |
320 | } | |
ebde3f62 | 321 | |
c8cf7e17 DE |
322 | return 1; |
323 | } | |
324 | \f | |
325 | void | |
326 | md_begin () | |
327 | { | |
328 | flagword applicable; | |
ebde3f62 NC |
329 | segT seg; |
330 | subsegT subseg; | |
c8cf7e17 DE |
331 | |
332 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
333 | |
334 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 335 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 336 | |
4e9d8dea | 337 | /* Set the machine number and endian. */ |
c8cf7e17 | 338 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
339 | target_big_endian ? |
340 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
341 | |
342 | #if 0 /* not supported yet */ | |
343 | /* If a runtime cpu description file was provided, parse it. */ | |
344 | if (m32r_cpu_desc != NULL) | |
345 | { | |
ebde3f62 | 346 | const char * errmsg; |
c8cf7e17 DE |
347 | |
348 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
349 | if (errmsg != NULL) | |
350 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
351 | } | |
352 | #endif | |
353 | ||
354 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
355 | we don't want the initial section to be .sbss]. */ |
356 | seg = now_seg; | |
c8cf7e17 DE |
357 | subseg = now_subseg; |
358 | ||
359 | /* The sbss section is for local .scomm symbols. */ | |
360 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 361 | |
c8cf7e17 DE |
362 | /* This is copied from perform_an_assembly_pass. */ |
363 | applicable = bfd_applicable_section_flags (stdoutput); | |
364 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 365 | |
c8cf7e17 DE |
366 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
367 | seg_info (bss_section)->bss = 1; | |
368 | #endif | |
369 | ||
370 | subseg_set (seg, subseg); | |
371 | ||
372 | /* We must construct a fake section similar to bfd_com_section | |
373 | but with the name .scommon. */ | |
ebde3f62 NC |
374 | scom_section = bfd_com_section; |
375 | scom_section.name = ".scommon"; | |
376 | scom_section.output_section = & scom_section; | |
377 | scom_section.symbol = & scom_symbol; | |
378 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
379 | scom_symbol = * bfd_com_section.symbol; | |
380 | scom_symbol.name = ".scommon"; | |
381 | scom_symbol.section = & scom_section; | |
a450e9f4 | 382 | |
b5e9e562 | 383 | /* start-sanitize-m32rx */ |
a450e9f4 | 384 | allow_m32rx (enable_m32rx); |
b5e9e562 | 385 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
386 | } |
387 | ||
89285fc9 | 388 | /* start-sanitize-m32rx */ |
55a4759f DE |
389 | #ifdef HAVE_CPU_M32RX |
390 | ||
6cf2575a NC |
391 | /* Returns true if an output of instruction 'a' is referenced by an operand |
392 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
393 | checked, otherwise its inputs are examined. */ | |
ebde3f62 | 394 | static int |
6cf2575a | 395 | first_writes_to_seconds_operands (a, b, check_outputs) |
26192c50 NC |
396 | m32r_insn * a; |
397 | m32r_insn * b; | |
6cf2575a | 398 | const int check_outputs; |
00aa5b17 | 399 | { |
c9cec4ef NC |
400 | const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn); |
401 | const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn); | |
6cf2575a | 402 | int a_index; |
00aa5b17 | 403 | |
c9cec4ef NC |
404 | /* If at least one of the instructions take sno opeands, then there is |
405 | nothing to check. There really are instructions without operands, | |
406 | eg 'nop'. */ | |
407 | if (a_operands == NULL || b_operands == NULL) | |
408 | return 0; | |
409 | ||
6cf2575a | 410 | /* Scan the operand list of 'a' looking for an output operand. */ |
c9cec4ef | 411 | for (a_index = 0; |
6cf2575a NC |
412 | CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END; |
413 | a_index ++, a_operands ++) | |
26192c50 | 414 | { |
6cf2575a | 415 | if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT) |
26192c50 | 416 | { |
c9cec4ef | 417 | int b_index; |
6cf2575a NC |
418 | |
419 | /* Scan operand list of 'b' looking for an operand that references | |
420 | the same hardware element, and which goes in the right direction. */ | |
c9cec4ef | 421 | for (b_index = 0; |
6cf2575a NC |
422 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; |
423 | b_index ++, b_operands ++) | |
424 | { | |
425 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
426 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
427 | && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands)) | |
428 | && (a->indices [a_index] == b->indices [b_index])) | |
429 | return 1; | |
430 | } | |
26192c50 NC |
431 | } |
432 | } | |
433 | ||
6cf2575a | 434 | return 0; |
26192c50 NC |
435 | } |
436 | ||
6cf2575a | 437 | /* Returns true if the insn can (potentially) alter the program counter. */ |
89285fc9 | 438 | static int |
6cf2575a | 439 | writes_to_pc (a) |
89285fc9 | 440 | m32r_insn * a; |
89285fc9 | 441 | { |
8e7a5a04 | 442 | #if 0 |
c9cec4ef | 443 | const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn); |
8e7a5a04 | 444 | |
c9cec4ef NC |
445 | if (a_operands == NULL) |
446 | return 0; | |
447 | ||
448 | while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END) | |
6cf2575a NC |
449 | { |
450 | if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL | |
451 | && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC) | |
452 | return 1; | |
c9cec4ef NC |
453 | |
454 | a_operands ++; | |
6cf2575a | 455 | } |
8e7a5a04 NC |
456 | #else |
457 | if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI) | |
458 | || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI)) | |
459 | return 1; | |
460 | #endif | |
6cf2575a | 461 | return 0; |
89285fc9 | 462 | } |
26192c50 | 463 | |
775fdd0c NC |
464 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
465 | otherwise it returns a pointer to an error message explaining why not. */ | |
466 | static const char * | |
26192c50 | 467 | can_make_parallel (a, b) |
b6930bdf NC |
468 | m32r_insn * a; |
469 | m32r_insn * b; | |
775fdd0c NC |
470 | { |
471 | PIPE_ATTR a_pipe; | |
472 | PIPE_ATTR b_pipe; | |
89285fc9 | 473 | |
775fdd0c | 474 | /* Make sure the instructions are the right length. */ |
b6930bdf NC |
475 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
476 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c | 477 | abort(); |
89285fc9 | 478 | |
6cf2575a | 479 | if (first_writes_to_seconds_operands (a, b, true)) |
89285fc9 | 480 | return "Instructions write to the same destination register."; |
775fdd0c | 481 | |
b6930bdf NC |
482 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
483 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 484 | |
b6930bdf | 485 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
486 | if ( a_pipe == PIPE_NONE |
487 | || b_pipe == PIPE_NONE) | |
488 | return "Instructions do not use parallel execution pipelines."; | |
89285fc9 NC |
489 | |
490 | /* Leave this test for last, since it is the only test that can | |
491 | go away if the instructions are swapped, and we want to make | |
492 | sure that any other errors are detected before this happens. */ | |
775fdd0c NC |
493 | if ( a_pipe == PIPE_S |
494 | || b_pipe == PIPE_O) | |
495 | return "Instructions share the same execution pipeline"; | |
89285fc9 | 496 | |
775fdd0c NC |
497 | return NULL; |
498 | } | |
775fdd0c NC |
499 | |
500 | #ifdef CGEN_INT_INSN | |
501 | static void | |
b6930bdf NC |
502 | make_parallel (buffer) |
503 | cgen_insn_t * buffer; | |
775fdd0c NC |
504 | { |
505 | /* Force the top bit of the second insn to be set. */ | |
506 | ||
507 | bfd_vma value; | |
508 | ||
509 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
510 | { | |
511 | value = bfd_getb16 ((bfd_byte *) buffer); | |
512 | value |= 0x8000; | |
513 | bfd_putb16 (value, (char *) buffer); | |
514 | } | |
515 | else | |
516 | { | |
517 | value = bfd_getl16 ((bfd_byte *) buffer); | |
518 | value |= 0x8000; | |
519 | bfd_putl16 (value, (char *) buffer); | |
520 | } | |
521 | } | |
522 | #else | |
523 | static void | |
b6930bdf NC |
524 | make_parallel (buffer) |
525 | char * buffer; | |
775fdd0c NC |
526 | { |
527 | /* Force the top bit of the second insn to be set. */ | |
528 | ||
529 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
530 | } | |
531 | #endif | |
532 | ||
533 | ||
b6930bdf NC |
534 | static void |
535 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 536 | char * str; |
b6930bdf | 537 | char * str2; |
c8cf7e17 | 538 | { |
b6930bdf NC |
539 | char * str3; |
540 | m32r_insn first; | |
541 | m32r_insn second; | |
542 | char * errmsg; | |
ebde3f62 | 543 | |
b6930bdf | 544 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 545 | |
b6930bdf NC |
546 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
547 | so that the parallel instruction will start on a 32 bit boundary. */ | |
548 | if (prev_insn.insn) | |
549 | fill_insn (0); | |
ebde3f62 | 550 | |
b6930bdf NC |
551 | /* Parse the first instruction. */ |
552 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
553 | (str, & first.fields, first.buffer, & errmsg))) | |
554 | { | |
555 | as_bad (errmsg); | |
556 | return; | |
557 | } | |
79420f9a | 558 | |
b6930bdf NC |
559 | /* Check to see if this is an allowable parallel insn. */ |
560 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
561 | { | |
562 | as_bad ("instruction '%s' cannot be executed in parallel.", str); | |
563 | return; | |
564 | } | |
ebde3f62 | 565 | |
b6930bdf NC |
566 | if (! enable_m32rx |
567 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
568 | { | |
569 | as_bad ("instruction '%s' is for the M32RX only", str); | |
570 | return; | |
ebde3f62 NC |
571 | } |
572 | ||
b6930bdf NC |
573 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
574 | str3 = str; /* Save the original string pointer. */ | |
575 | str = str2 + 2; /* Advanced past the parsed string. */ | |
576 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
577 | ||
578 | /* Preserve any fixups that have been generated and reset the list to empty. */ | |
579 | cgen_save_fixups(); | |
580 | ||
6cf2575a NC |
581 | /* Get the indicies of the operands of the instruction. */ |
582 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
583 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
c9cec4ef NC |
584 | /* FIXME: ALIAS insns do not have operands, so we use this function |
585 | to find the equivalent insn and overwrite the value stored in our | |
586 | structure. When aliases behave differently this may have to change. */ | |
587 | first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16, | |
588 | first.indices); | |
589 | if (first.insn == NULL) | |
6cf2575a NC |
590 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn"); |
591 | ||
b6930bdf NC |
592 | /* Parse the second instruction. */ |
593 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
594 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
595 | { |
596 | as_bad (errmsg); | |
597 | return; | |
598 | } | |
c8cf7e17 | 599 | |
b6930bdf NC |
600 | /* Check it. */ |
601 | if (! enable_m32rx | |
602 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
ebde3f62 NC |
603 | { |
604 | as_bad ("instruction '%s' is for the M32RX only", str); | |
605 | return; | |
606 | } | |
ebde3f62 | 607 | |
b6930bdf | 608 | if (! enable_m32rx) |
ebde3f62 | 609 | { |
b6930bdf NC |
610 | if ( strcmp (first.insn->name, "nop") != 0 |
611 | && strcmp (second.insn->name, "nop") != 0) | |
ebde3f62 | 612 | { |
b6930bdf NC |
613 | as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2); |
614 | return; | |
ebde3f62 | 615 | } |
b6930bdf | 616 | } |
9121b102 | 617 | |
6cf2575a | 618 | /* Get the indicies of the operands of the instruction. */ |
c9cec4ef NC |
619 | second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16, |
620 | second.indices); | |
621 | if (second.insn == NULL) | |
6cf2575a NC |
622 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn"); |
623 | ||
b6930bdf NC |
624 | /* We assume that if the first instruction writes to a register that is |
625 | read by the second instruction it is because the programmer intended | |
626 | this to happen, (after all they have explicitly requested that these | |
26192c50 NC |
627 | two instructions be executed in parallel). Although if the global |
628 | variable warn_explicit_parallel_conflicts is true then we do generate | |
629 | a warning message. Similarly we assume that parallel branch and jump | |
00aa5b17 | 630 | instructions are deliberate and should not produce errors. */ |
b6930bdf | 631 | |
00aa5b17 | 632 | if (warn_explicit_parallel_conflicts) |
b6930bdf | 633 | { |
6cf2575a NC |
634 | if (first_writes_to_seconds_operands (& first, & second, false)) |
635 | as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2); | |
26192c50 | 636 | |
6cf2575a NC |
637 | if (first_writes_to_seconds_operands (& second, & first, false)) |
638 | as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2); | |
00aa5b17 DE |
639 | } |
640 | ||
641 | if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL) | |
642 | { | |
b6930bdf NC |
643 | /* Get the fixups for the first instruction. */ |
644 | cgen_swap_fixups (); | |
645 | ||
646 | /* Write it out. */ | |
647 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
648 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
ebde3f62 | 649 | |
b6930bdf NC |
650 | /* Force the top bit of the second insn to be set. */ |
651 | make_parallel (second.buffer); | |
ebde3f62 | 652 | |
b6930bdf NC |
653 | /* Get its fixups. */ |
654 | cgen_restore_fixups (); | |
775fdd0c | 655 | |
b6930bdf NC |
656 | /* Write it out. */ |
657 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
658 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
659 | } | |
89285fc9 | 660 | /* Try swapping the instructions to see if they work that way. */ |
6cf2575a | 661 | else if (can_make_parallel (& second, & first) == NULL) |
b6930bdf NC |
662 | { |
663 | /* Write out the second instruction first. */ | |
664 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
665 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
775fdd0c | 666 | |
b6930bdf NC |
667 | /* Force the top bit of the first instruction to be set. */ |
668 | make_parallel (first.buffer); | |
669 | ||
670 | /* Get the fixups for the first instruction. */ | |
671 | cgen_restore_fixups (); | |
672 | ||
673 | /* Write out the first instruction. */ | |
674 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
675 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
676 | } | |
677 | else | |
678 | { | |
679 | as_bad ("'%s': %s", str2, errmsg); | |
680 | return; | |
681 | } | |
ebde3f62 | 682 | |
b6930bdf NC |
683 | /* Set these so m32r_fill_insn can use them. */ |
684 | prev_seg = now_seg; | |
685 | prev_subseg = now_subseg; | |
686 | ||
687 | return; | |
688 | } | |
55a4759f DE |
689 | |
690 | #endif /* HAVE_CPU_M32RX */ | |
691 | ||
b6930bdf NC |
692 | /* end-sanitize-m32rx */ |
693 | ||
694 | ||
695 | void | |
696 | md_assemble (str) | |
697 | char * str; | |
698 | { | |
699 | m32r_insn insn; | |
700 | char * errmsg; | |
701 | char * str2 = NULL; | |
702 | ||
703 | /* Initialize GAS's cgen interface for a new instruction. */ | |
704 | cgen_asm_init_parse (); | |
705 | ||
706 | /* start-sanitize-m32rx */ | |
55a4759f | 707 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
708 | /* Look for a parallel instruction seperator. */ |
709 | if ((str2 = strstr (str, "||")) != NULL) | |
710 | { | |
711 | assemble_parallel_insn (str, str2); | |
712 | return; | |
ebde3f62 | 713 | } |
55a4759f | 714 | #endif |
b6930bdf NC |
715 | /* end-sanitize-m32rx */ |
716 | ||
717 | insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); | |
718 | if (!insn.insn) | |
719 | { | |
720 | as_bad (errmsg); | |
721 | return; | |
722 | } | |
723 | ||
724 | /* start-sanitize-m32rx */ | |
55a4759f | 725 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
726 | if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
727 | { | |
728 | as_bad ("instruction '%s' is for the M32RX only", str); | |
729 | return; | |
730 | } | |
55a4759f | 731 | #endif |
b6930bdf NC |
732 | /* end-sanitize-m32rx */ |
733 | ||
734 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
735 | { |
736 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 737 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 NC |
738 | { |
739 | /* FIXME: If calling fill_insn too many times turns us into a memory | |
740 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ | |
741 | fill_insn (0); | |
742 | } | |
743 | ||
b6930bdf NC |
744 | (void) cgen_asm_finish_insn (insn.insn, insn.buffer, |
745 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
c8cf7e17 DE |
746 | } |
747 | else | |
748 | { | |
b6930bdf NC |
749 | /* start-sanitize-m32rx */ |
750 | /* start-sanitize-phase2-m32rx */ | |
751 | int swap = false; | |
752 | /* end-sanitize-phase2-m32rx */ | |
753 | /* end-sanitize-m32rx */ | |
754 | ||
755 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
756 | abort(); | |
757 | ||
6cf2575a | 758 | /* Get the indicies of the operands of the instruction. */ |
c9cec4ef NC |
759 | insn.insn = m32r_cgen_get_insn_operands (insn.insn, |
760 | bfd_getb16 ((char *) insn.buffer), | |
761 | 16, | |
762 | insn.indices); | |
763 | if (insn.insn == NULL) | |
6cf2575a NC |
764 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed"); |
765 | ||
c8cf7e17 | 766 | /* Keep track of whether we've seen a pair of 16 bit insns. |
b6930bdf NC |
767 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
768 | if (prev_insn.insn) | |
775fdd0c NC |
769 | { |
770 | /* start-sanitize-m32rx */ | |
b6930bdf | 771 | /* start-sanitize-phase2-m32rx */ |
55a4759f | 772 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
773 | /* Look to see if this instruction can be combined with the |
774 | previous instruction to make one, parallel, 32 bit instruction. | |
775 | If the previous instruction (potentially) changed the flow of | |
776 | program control, then it cannot be combined with the current | |
b86c0dd3 NC |
777 | instruction. If the current instruction is relaxable, then it |
778 | might be replaced with a longer version, so we cannot combine it. | |
779 | Also if the output of the previous instruction is used as an | |
780 | input to the current instruction then it cannot be combined. | |
781 | Otherwise call can_make_parallel() with both orderings of the | |
782 | instructions to see if they can be combined. */ | |
783 | if ( enable_m32rx | |
784 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) == 0 | |
785 | && ! writes_to_pc (& prev_insn) | |
6cf2575a | 786 | && ! first_writes_to_seconds_operands (& prev_insn, &insn, false) |
ed295804 | 787 | ) |
775fdd0c | 788 | { |
ed295804 NC |
789 | if (can_make_parallel (& prev_insn, & insn) == NULL) |
790 | make_parallel (insn.buffer); | |
791 | else if (can_make_parallel (& insn, & prev_insn.insn) == NULL) | |
792 | swap = true; | |
775fdd0c | 793 | } |
55a4759f | 794 | #endif |
b6930bdf | 795 | /* end-sanitize-phase2-m32rx */ |
775fdd0c NC |
796 | /* end-sanitize-m32rx */ |
797 | ||
b6930bdf | 798 | prev_insn.insn = NULL; |
775fdd0c | 799 | } |
c8cf7e17 | 800 | else |
775fdd0c | 801 | { |
b6930bdf | 802 | prev_insn = insn; |
775fdd0c | 803 | } |
c8cf7e17 | 804 | |
b6930bdf NC |
805 | /* Record the frag that might be used by this insn. */ |
806 | insn.frag = frag_now; | |
807 | insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer, | |
808 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
809 | ||
810 | /* start-sanitize-m32rx */ | |
811 | /* start-sanitize-phase2-m32rx */ | |
55a4759f | 812 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
813 | if (swap) |
814 | { | |
815 | int tmp; | |
816 | ||
817 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
818 | ||
819 | /* Swap the two insns */ | |
820 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
821 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
822 | ||
823 | make_parallel (insn.addr); | |
824 | ||
825 | /* Swap any relaxable frags recorded for the two insns. */ | |
826 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
b86c0dd3 | 827 | prev_insn.frag->fr_opcode = insn.addr; |
b6930bdf | 828 | else if (insn.frag->fr_opcode == insn.addr) |
b86c0dd3 | 829 | insn.frag->fr_opcode = prev_insn.addr; |
b6930bdf NC |
830 | } |
831 | /* end-sanitize-phase2-m32rx */ | |
832 | ||
833 | /* Record where this instruction was assembled. */ | |
834 | prev_insn.addr = insn.addr; | |
835 | prev_insn.frag = insn.frag; | |
55a4759f | 836 | #endif |
b6930bdf NC |
837 | /* end-sanitize-m32rx */ |
838 | ||
c8cf7e17 DE |
839 | /* If the insn needs the following one to be on a 32 bit boundary |
840 | (e.g. subroutine calls), fill this insn's slot. */ | |
b86c0dd3 | 841 | if (prev_insn.insn != NULL |
b6930bdf | 842 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0) |
c8cf7e17 | 843 | fill_insn (0); |
c8cf7e17 | 844 | |
775fdd0c | 845 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
846 | mark the fact so that we can emit an alignment directive for a |
847 | following 32 bit insn if we see one. */ | |
848 | if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0) | |
775fdd0c NC |
849 | seen_relaxable_p = 1; |
850 | } | |
c8cf7e17 DE |
851 | |
852 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 853 | prev_seg = now_seg; |
c8cf7e17 DE |
854 | prev_subseg = now_subseg; |
855 | } | |
856 | ||
857 | /* The syntax in the manual says constants begin with '#'. | |
858 | We just ignore it. */ | |
859 | ||
860 | void | |
861 | md_operand (expressionP) | |
ebde3f62 | 862 | expressionS * expressionP; |
c8cf7e17 | 863 | { |
ebde3f62 | 864 | if (* input_line_pointer == '#') |
c8cf7e17 | 865 | { |
ebde3f62 | 866 | input_line_pointer ++; |
c8cf7e17 DE |
867 | expression (expressionP); |
868 | } | |
869 | } | |
870 | ||
871 | valueT | |
872 | md_section_align (segment, size) | |
ebde3f62 | 873 | segT segment; |
c8cf7e17 DE |
874 | valueT size; |
875 | { | |
876 | int align = bfd_get_section_alignment (stdoutput, segment); | |
877 | return ((size + (1 << align) - 1) & (-1 << align)); | |
878 | } | |
879 | ||
880 | symbolS * | |
881 | md_undefined_symbol (name) | |
ebde3f62 | 882 | char * name; |
c8cf7e17 DE |
883 | { |
884 | return 0; | |
885 | } | |
886 | \f | |
887 | /* .scomm pseudo-op handler. | |
888 | ||
889 | This is a new pseudo-op to handle putting objects in .scommon. | |
890 | By doing this the linker won't need to do any work and more importantly | |
891 | it removes the implicit -G arg necessary to correctly link the object file. | |
892 | */ | |
893 | ||
894 | static void | |
895 | m32r_scomm (ignore) | |
896 | int ignore; | |
897 | { | |
ebde3f62 NC |
898 | register char * name; |
899 | register char c; | |
900 | register char * p; | |
901 | offsetT size; | |
902 | register symbolS * symbolP; | |
903 | offsetT align; | |
904 | int align2; | |
c8cf7e17 DE |
905 | |
906 | name = input_line_pointer; | |
907 | c = get_symbol_end (); | |
908 | ||
909 | /* just after name is now '\0' */ | |
910 | p = input_line_pointer; | |
ebde3f62 | 911 | * p = c; |
c8cf7e17 | 912 | SKIP_WHITESPACE (); |
ebde3f62 | 913 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
914 | { |
915 | as_bad ("Expected comma after symbol-name: rest of line ignored."); | |
916 | ignore_rest_of_line (); | |
917 | return; | |
918 | } | |
919 | ||
b6930bdf | 920 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
921 | if ((size = get_absolute_expression ()) < 0) |
922 | { | |
923 | as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size); | |
924 | ignore_rest_of_line (); | |
925 | return; | |
926 | } | |
927 | ||
928 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 929 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
930 | align = 8; |
931 | else | |
932 | { | |
ebde3f62 | 933 | ++ input_line_pointer; |
c8cf7e17 DE |
934 | align = get_absolute_expression (); |
935 | if (align <= 0) | |
936 | { | |
937 | as_warn ("ignoring bad alignment"); | |
938 | align = 8; | |
939 | } | |
940 | } | |
941 | /* Convert to a power of 2 alignment. */ | |
942 | if (align) | |
943 | { | |
ebde3f62 | 944 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
945 | continue; |
946 | if (align != 1) | |
947 | { | |
948 | as_bad ("Common alignment not a power of 2"); | |
949 | ignore_rest_of_line (); | |
950 | return; | |
951 | } | |
952 | } | |
953 | else | |
954 | align2 = 0; | |
955 | ||
ebde3f62 | 956 | * p = 0; |
c8cf7e17 | 957 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 958 | * p = c; |
c8cf7e17 DE |
959 | |
960 | if (S_IS_DEFINED (symbolP)) | |
961 | { | |
962 | as_bad ("Ignoring attempt to re-define symbol `%s'.", | |
963 | S_GET_NAME (symbolP)); | |
964 | ignore_rest_of_line (); | |
965 | return; | |
966 | } | |
967 | ||
968 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
969 | { | |
970 | as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.", | |
971 | S_GET_NAME (symbolP), | |
972 | (long) S_GET_VALUE (symbolP), | |
973 | (long) size); | |
974 | ||
975 | ignore_rest_of_line (); | |
976 | return; | |
977 | } | |
978 | ||
979 | if (symbolP->local) | |
980 | { | |
ebde3f62 NC |
981 | segT old_sec = now_seg; |
982 | int old_subsec = now_subseg; | |
983 | char * pfrag; | |
c8cf7e17 DE |
984 | |
985 | record_alignment (sbss_section, align2); | |
986 | subseg_set (sbss_section, 0); | |
775fdd0c | 987 | |
c8cf7e17 DE |
988 | if (align2) |
989 | frag_align (align2, 0, 0); | |
775fdd0c | 990 | |
c8cf7e17 DE |
991 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
992 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 993 | |
c8cf7e17 | 994 | symbolP->sy_frag = frag_now; |
b6930bdf | 995 | |
c8cf7e17 DE |
996 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
997 | (char *) 0); | |
ebde3f62 | 998 | * pfrag = 0; |
c8cf7e17 DE |
999 | S_SET_SIZE (symbolP, size); |
1000 | S_SET_SEGMENT (symbolP, sbss_section); | |
1001 | S_CLEAR_EXTERNAL (symbolP); | |
1002 | subseg_set (old_sec, old_subsec); | |
1003 | } | |
1004 | else | |
1005 | { | |
1006 | S_SET_VALUE (symbolP, (valueT) size); | |
1007 | S_SET_ALIGN (symbolP, align2); | |
1008 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 1009 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
1010 | } |
1011 | ||
1012 | demand_empty_rest_of_line (); | |
1013 | } | |
1014 | \f | |
1015 | /* Interface to relax_segment. */ | |
1016 | ||
1017 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1018 | ||
1019 | const relax_typeS md_relax_table[] = | |
1020 | { | |
1021 | /* The fields are: | |
1022 | 1) most positive reach of this state, | |
1023 | 2) most negative reach of this state, | |
1024 | 3) how many bytes this mode will add to the size of the current frag | |
1025 | 4) which index into the table to try if we can't fit into this one. */ | |
1026 | ||
1027 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1028 | each list. */ | |
1029 | {1, 1, 0, 0}, | |
1030 | ||
1031 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1032 | so we subtract 2 from the following. */ | |
1033 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1034 | This doesn't handle a branch in the right slot at the border: | |
1035 | the "& -4" isn't taken into account. It's not important enough to | |
1036 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1037 | case). */ | |
1038 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1039 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1040 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1041 | /* Same thing, but with leading nop for alignment. */ | |
1042 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1043 | }; | |
1044 | ||
1045 | long | |
1046 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1047 | fragS * fragP; |
1048 | long stretch; | |
c8cf7e17 DE |
1049 | { |
1050 | /* Address of branch insn. */ | |
1051 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1052 | long growth = 0; | |
1053 | ||
1054 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1055 | if (fragP->fr_subtype == 2) | |
1056 | { | |
1057 | if ((address & 3) != 0) | |
1058 | { | |
1059 | fragP->fr_subtype = 3; | |
1060 | growth = 2; | |
1061 | } | |
1062 | } | |
1063 | else if (fragP->fr_subtype == 3) | |
1064 | { | |
1065 | if ((address & 3) == 0) | |
1066 | { | |
1067 | fragP->fr_subtype = 2; | |
1068 | growth = -2; | |
1069 | } | |
1070 | } | |
1071 | else | |
1072 | { | |
1073 | growth = relax_frag (fragP, stretch); | |
1074 | ||
1075 | /* Long jump on odd halfword boundary? */ | |
1076 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1077 | { | |
1078 | fragP->fr_subtype = 3; | |
1079 | growth += 2; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | return growth; | |
1084 | } | |
1085 | ||
1086 | /* Return an initial guess of the length by which a fragment must grow to | |
1087 | hold a branch to reach its destination. | |
1088 | Also updates fr_type/fr_subtype as necessary. | |
1089 | ||
1090 | Called just before doing relaxation. | |
1091 | Any symbol that is now undefined will not become defined. | |
1092 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1093 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1094 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1095 | 0 value. */ | |
1096 | ||
1097 | int | |
1098 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1099 | fragS * fragP; |
1100 | segT segment; | |
c8cf7e17 | 1101 | { |
ebde3f62 NC |
1102 | int old_fr_fix = fragP->fr_fix; |
1103 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1104 | |
1105 | /* The only thing we have to handle here are symbols outside of the | |
1106 | current segment. They may be undefined or in a different segment in | |
1107 | which case linker scripts may place them anywhere. | |
1108 | However, we can't finish the fragment here and emit the reloc as insn | |
1109 | alignment requirements may move the insn about. */ | |
1110 | ||
1111 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1112 | { | |
1113 | /* The symbol is undefined in this segment. | |
1114 | Change the relaxation subtype to the max allowable and leave | |
1115 | all further handling to md_convert_frag. */ | |
1116 | fragP->fr_subtype = 2; | |
1117 | ||
1118 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1119 | /* Change 16 bit insn to 32 bit insn. */ | |
1120 | opcode[0] |= 0x80; | |
1121 | ||
1122 | /* Increase known (fixed) size of fragment. */ | |
1123 | fragP->fr_fix += 2; | |
1124 | ||
1125 | /* Create a relocation for it. */ | |
1126 | fix_new (fragP, old_fr_fix, 4, | |
1127 | fragP->fr_symbol, | |
1128 | fragP->fr_offset, 1 /* pcrel */, | |
1129 | /* FIXME: Can't use a real BFD reloc here. | |
1130 | cgen_md_apply_fix3 can't handle it. */ | |
1131 | BFD_RELOC_M32R_26_PCREL); | |
1132 | ||
1133 | /* Mark this fragment as finished. */ | |
1134 | frag_wane (fragP); | |
1135 | #else | |
a450e9f4 | 1136 | { |
ebde3f62 NC |
1137 | const CGEN_INSN * insn; |
1138 | int i; | |
a450e9f4 NC |
1139 | |
1140 | /* Update the recorded insn. | |
1141 | Fortunately we don't have to look very far. | |
1142 | FIXME: Change this to record in the instruction the next higher | |
1143 | relaxable insn to use. */ | |
1144 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1145 | { | |
b5e9e562 DE |
1146 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1147 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1148 | == 0) |
1149 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1150 | break; | |
1151 | } | |
1152 | if (i == 4) | |
1153 | abort (); | |
b6930bdf | 1154 | |
a450e9f4 NC |
1155 | fragP->fr_cgen.insn = insn; |
1156 | return 2; | |
1157 | } | |
c8cf7e17 DE |
1158 | #endif |
1159 | } | |
1160 | ||
1161 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1162 | } | |
1163 | ||
1164 | /* *fragP has been relaxed to its final size, and now needs to have | |
1165 | the bytes inside it modified to conform to the new size. | |
1166 | ||
1167 | Called after relaxation is finished. | |
1168 | fragP->fr_type == rs_machine_dependent. | |
1169 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1170 | ||
1171 | void | |
1172 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1173 | bfd * abfd; |
1174 | segT sec; | |
1175 | fragS * fragP; | |
c8cf7e17 | 1176 | { |
ebde3f62 NC |
1177 | char * opcode; |
1178 | char * displacement; | |
1179 | int target_address; | |
1180 | int opcode_address; | |
1181 | int extension; | |
1182 | int addend; | |
c8cf7e17 DE |
1183 | |
1184 | opcode = fragP->fr_opcode; | |
1185 | ||
1186 | /* Address opcode resides at in file space. */ | |
1187 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1188 | ||
1189 | switch (fragP->fr_subtype) | |
1190 | { | |
1191 | case 1 : | |
1192 | extension = 0; | |
ebde3f62 | 1193 | displacement = & opcode[1]; |
c8cf7e17 DE |
1194 | break; |
1195 | case 2 : | |
1196 | opcode[0] |= 0x80; | |
1197 | extension = 2; | |
ebde3f62 | 1198 | displacement = & opcode[1]; |
c8cf7e17 DE |
1199 | break; |
1200 | case 3 : | |
1201 | opcode[2] = opcode[0] | 0x80; | |
1202 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1203 | opcode_address += 2; | |
1204 | extension = 4; | |
ebde3f62 | 1205 | displacement = & opcode[3]; |
c8cf7e17 DE |
1206 | break; |
1207 | default : | |
1208 | abort (); | |
1209 | } | |
1210 | ||
1211 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1212 | { | |
1213 | /* symbol must be resolved by linker */ | |
1214 | if (fragP->fr_offset & 3) | |
1215 | as_warn ("Addend to unresolved symbol not on word boundary."); | |
1216 | addend = fragP->fr_offset >> 2; | |
1217 | } | |
1218 | else | |
1219 | { | |
1220 | /* Address we want to reach in file space. */ | |
1221 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1222 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1223 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1224 | } | |
1225 | ||
1226 | /* Create a relocation for symbols that must be resolved by the linker. | |
1227 | Otherwise output the completed insn. */ | |
1228 | ||
1229 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1230 | { | |
1231 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1232 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1233 | cgen_record_fixup (fragP, |
1234 | /* Offset of branch insn in frag. */ | |
1235 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1236 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1237 | 4 /*length*/, |
1238 | /* FIXME: quick hack */ | |
1239 | #if 0 | |
a450e9f4 | 1240 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1241 | #else |
1242 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1243 | #endif | |
a450e9f4 | 1244 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1245 | fragP->fr_symbol, fragP->fr_offset); |
1246 | } | |
1247 | ||
1248 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1249 | ||
1250 | md_number_to_chars (displacement, (valueT) addend, | |
1251 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1252 | ||
1253 | fragP->fr_fix += extension; | |
1254 | } | |
1255 | \f | |
1256 | /* Functions concerning relocs. */ | |
1257 | ||
1258 | /* The location from which a PC relative jump should be calculated, | |
1259 | given a PC relative reloc. */ | |
1260 | ||
1261 | long | |
1262 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1263 | fixS * fixP; |
1264 | segT sec; | |
c8cf7e17 DE |
1265 | { |
1266 | if (fixP->fx_addsy != (symbolS *) NULL | |
1267 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1268 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1269 | { | |
1270 | /* The symbol is undefined (or is defined but not in this section). | |
1271 | Let the linker figure it out. */ | |
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1276 | } | |
1277 | ||
1278 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1279 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1280 | *FIXP may be modified if desired. */ | |
1281 | ||
1282 | bfd_reloc_code_real_type | |
1283 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1284 | const CGEN_INSN * insn; |
1285 | const CGEN_OPERAND * operand; | |
1286 | fixS * fixP; | |
c8cf7e17 DE |
1287 | { |
1288 | switch (CGEN_OPERAND_TYPE (operand)) | |
1289 | { | |
1290 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1291 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1292 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1293 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1294 | case M32R_OPERAND_HI16 : | |
1295 | case M32R_OPERAND_SLO16 : | |
1296 | case M32R_OPERAND_ULO16 : | |
1297 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1298 | if (fixP->tc_fix_data.opinfo != 0) | |
1299 | return fixP->tc_fix_data.opinfo; | |
1300 | break; | |
1301 | } | |
1302 | return BFD_RELOC_NONE; | |
1303 | } | |
1304 | ||
b6930bdf NC |
1305 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1306 | ||
1307 | static void | |
1308 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1309 | int reloc_type; | |
1310 | fixS * fixP; | |
1311 | segT seg; | |
1312 | { | |
1313 | struct m32r_hi_fixup * hi_fixup; | |
1314 | ||
1315 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1316 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1317 | ||
1318 | hi_fixup = ((struct m32r_hi_fixup *) | |
1319 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1320 | hi_fixup->fixp = fixP; | |
1321 | hi_fixup->seg = now_seg; | |
1322 | hi_fixup->next = m32r_hi_fixup_list; | |
1323 | ||
1324 | m32r_hi_fixup_list = hi_fixup; | |
1325 | } | |
1326 | ||
c8cf7e17 DE |
1327 | /* Called while parsing an instruction to create a fixup. |
1328 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1329 | ||
1330 | fixS * | |
1331 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1332 | fragS * frag; |
1333 | int where; | |
1334 | const CGEN_INSN * insn; | |
1335 | int length; | |
1336 | const CGEN_OPERAND * operand; | |
1337 | int opinfo; | |
1338 | expressionS * exp; | |
c8cf7e17 | 1339 | { |
ebde3f62 NC |
1340 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1341 | operand, opinfo, exp); | |
c8cf7e17 DE |
1342 | |
1343 | switch (CGEN_OPERAND_TYPE (operand)) | |
1344 | { | |
1345 | case M32R_OPERAND_HI16 : | |
1346 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1347 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1348 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1349 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1350 | break; | |
1351 | } | |
1352 | ||
1353 | return fixP; | |
1354 | } | |
1355 | ||
c8cf7e17 DE |
1356 | /* Return BFD reloc type from opinfo field in a fixS. |
1357 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1358 | are BFD_RELOC_UNUSED + operand number. */ | |
1359 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1360 | ||
1361 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1362 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1363 | tc_gen_reloc. */ | |
1364 | ||
1365 | void | |
1366 | m32r_frob_file () | |
1367 | { | |
ebde3f62 | 1368 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1369 | |
1370 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1371 | { | |
ebde3f62 NC |
1372 | segment_info_type * seginfo; |
1373 | int pass; | |
c8cf7e17 DE |
1374 | |
1375 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1376 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1377 | ||
1378 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1379 | if (l->fixp->fx_next != NULL | |
1380 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1381 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1382 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1383 | continue; | |
1384 | ||
1385 | /* Look through the fixups for this segment for a matching `low'. | |
1386 | When we find one, move the high/shigh just in front of it. We do | |
1387 | this in two passes. In the first pass, we try to find a | |
1388 | unique `low'. In the second pass, we permit multiple high's | |
1389 | relocs for a single `low'. */ | |
1390 | seginfo = seg_info (l->seg); | |
1391 | for (pass = 0; pass < 2; pass++) | |
1392 | { | |
ebde3f62 NC |
1393 | fixS * f; |
1394 | fixS * prev; | |
c8cf7e17 DE |
1395 | |
1396 | prev = NULL; | |
1397 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1398 | { | |
1399 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1400 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1401 | && f->fx_addsy == l->fixp->fx_addsy | |
1402 | && f->fx_offset == l->fixp->fx_offset | |
1403 | && (pass == 1 | |
1404 | || prev == NULL | |
1405 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1406 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1407 | || prev->fx_addsy != f->fx_addsy | |
1408 | || prev->fx_offset != f->fx_offset)) | |
1409 | { | |
ebde3f62 | 1410 | fixS ** pf; |
c8cf7e17 DE |
1411 | |
1412 | /* Move l->fixp before f. */ | |
1413 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1414 | * pf != l->fixp; |
1415 | pf = & (* pf)->fx_next) | |
1416 | assert (* pf != NULL); | |
c8cf7e17 | 1417 | |
ebde3f62 | 1418 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1419 | |
1420 | l->fixp->fx_next = f; | |
1421 | if (prev == NULL) | |
1422 | seginfo->fix_root = l->fixp; | |
1423 | else | |
1424 | prev->fx_next = l->fixp; | |
1425 | ||
1426 | break; | |
1427 | } | |
1428 | ||
1429 | prev = f; | |
1430 | } | |
1431 | ||
1432 | if (f != NULL) | |
1433 | break; | |
1434 | ||
1435 | if (pass == 1) | |
1436 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1437 | "Unmatched high/shigh reloc"); | |
1438 | } | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | /* See whether we need to force a relocation into the output file. | |
1443 | This is used to force out switch and PC relative relocations when | |
1444 | relaxing. */ | |
1445 | ||
1446 | int | |
1447 | m32r_force_relocation (fix) | |
ebde3f62 | 1448 | fixS * fix; |
c8cf7e17 DE |
1449 | { |
1450 | if (! m32r_relax) | |
1451 | return 0; | |
1452 | ||
1453 | return (fix->fx_pcrel | |
1454 | || 0 /* ??? */); | |
1455 | } | |
1456 | \f | |
1457 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1458 | ||
1459 | void | |
1460 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1461 | char * buf; |
c8cf7e17 | 1462 | valueT val; |
ebde3f62 | 1463 | int n; |
c8cf7e17 DE |
1464 | { |
1465 | if (target_big_endian) | |
1466 | number_to_chars_bigendian (buf, val, n); | |
1467 | else | |
1468 | number_to_chars_littleendian (buf, val, n); | |
1469 | } | |
1470 | ||
1471 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1472 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1473 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1474 | */ | |
1475 | ||
1476 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1477 | #define MAX_LITTLENUMS 6 | |
1478 | ||
1479 | char * | |
1480 | md_atof (type, litP, sizeP) | |
1481 | char type; | |
1482 | char *litP; | |
1483 | int *sizeP; | |
1484 | { | |
ebde3f62 NC |
1485 | int i; |
1486 | int prec; | |
1487 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1488 | LITTLENUM_TYPE * wordP; | |
1489 | char * t; | |
1490 | char * atof_ieee (); | |
c8cf7e17 DE |
1491 | |
1492 | switch (type) | |
1493 | { | |
1494 | case 'f': | |
1495 | case 'F': | |
1496 | case 's': | |
1497 | case 'S': | |
1498 | prec = 2; | |
1499 | break; | |
1500 | ||
1501 | case 'd': | |
1502 | case 'D': | |
1503 | case 'r': | |
1504 | case 'R': | |
1505 | prec = 4; | |
1506 | break; | |
1507 | ||
1508 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1509 | ||
1510 | default: | |
ebde3f62 | 1511 | * sizeP = 0; |
c8cf7e17 DE |
1512 | return "Bad call to md_atof()"; |
1513 | } | |
1514 | ||
1515 | t = atof_ieee (input_line_pointer, type, words); | |
1516 | if (t) | |
1517 | input_line_pointer = t; | |
ebde3f62 | 1518 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1519 | |
1520 | if (target_big_endian) | |
1521 | { | |
1522 | for (i = 0; i < prec; i++) | |
1523 | { | |
ebde3f62 NC |
1524 | md_number_to_chars (litP, (valueT) words[i], |
1525 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1526 | litP += sizeof (LITTLENUM_TYPE); |
1527 | } | |
1528 | } | |
1529 | else | |
1530 | { | |
1531 | for (i = prec - 1; i >= 0; i--) | |
1532 | { | |
ebde3f62 NC |
1533 | md_number_to_chars (litP, (valueT) words[i], |
1534 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1535 | litP += sizeof (LITTLENUM_TYPE); |
1536 | } | |
1537 | } | |
1538 | ||
1539 | return 0; | |
1540 | } |