Commit | Line | Data |
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76090fdd | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "cgen-opc.h" | |
26 | ||
b6930bdf NC |
27 | typedef struct |
28 | { | |
29 | const CGEN_INSN * insn; | |
30 | CGEN_FIELDS fields; | |
31 | #ifdef CGEN_INT_INSN | |
32 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
33 | #else | |
34 | char buffer [CGEN_MAX_INSN_SIZE]; | |
35 | #endif | |
36 | char * addr; | |
37 | fragS * frag; | |
6cf2575a | 38 | int indices [MAX_OPERAND_INSTANCES]; |
b6930bdf NC |
39 | } |
40 | m32r_insn; | |
41 | ||
42 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
43 | boundary (i.e. was the first of two 16 bit insns). */ | |
44 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
45 | |
46 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
47 | alignment request. */ | |
48 | static int seen_relaxable_p = 0; | |
49 | ||
50 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
51 | for the linker to do relaxing. | |
52 | We do simple forms of relaxing internally, but they are always done. | |
53 | This flag does not apply to them. */ | |
54 | static int m32r_relax; | |
55 | ||
56 | /* If non-NULL, pointer to cpu description file to read. | |
57 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 58 | static char * m32r_cpu_desc; |
c8cf7e17 | 59 | |
b5e9e562 | 60 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
61 | /* Non-zero if -m32rx has been specified, in which case support for the |
62 | extended M32RX instruction set should be enabled. */ | |
a450e9f4 | 63 | static int enable_m32rx = 0; |
b6930bdf NC |
64 | |
65 | /* Non-zero if the programmer should be warned when an explicit parallel | |
66 | instruction might have constraint violations. */ | |
67 | static int warn_explicit_parallel_conflicts = 1; | |
b5e9e562 | 68 | /* end-sanitize-m32rx */ |
a450e9f4 | 69 | |
c8cf7e17 | 70 | /* stuff for .scomm symbols. */ |
ebde3f62 | 71 | static segT sbss_section; |
c8cf7e17 | 72 | static asection scom_section; |
ebde3f62 | 73 | static asymbol scom_symbol; |
c8cf7e17 | 74 | |
ebde3f62 NC |
75 | const char comment_chars[] = ";"; |
76 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 77 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
78 | const char EXP_CHARS[] = "eE"; |
79 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
80 | |
81 | /* Relocations against symbols are done in two | |
82 | parts, with a HI relocation and a LO relocation. Each relocation | |
83 | has only 16 bits of space to store an addend. This means that in | |
84 | order for the linker to handle carries correctly, it must be able | |
85 | to locate both the HI and the LO relocation. This means that the | |
86 | relocations must appear in order in the relocation table. | |
87 | ||
88 | In order to implement this, we keep track of each unmatched HI | |
89 | relocation. We then sort them so that they immediately precede the | |
90 | corresponding LO relocation. */ | |
91 | ||
92 | struct m32r_hi_fixup | |
93 | { | |
ebde3f62 NC |
94 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
95 | fixS * fixp; /* This fixup. */ | |
96 | segT seg; /* The section this fixup is in. */ | |
97 | ||
c8cf7e17 DE |
98 | }; |
99 | ||
100 | /* The list of unmatched HI relocs. */ | |
101 | ||
ebde3f62 | 102 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 103 | |
a450e9f4 | 104 | \f |
b5e9e562 | 105 | /* start-sanitize-m32rx */ |
a450e9f4 | 106 | static void |
55a4759f DE |
107 | allow_m32rx (on) |
108 | int on; | |
a450e9f4 NC |
109 | { |
110 | enable_m32rx = on; | |
111 | ||
112 | if (stdoutput != NULL) | |
ebde3f62 NC |
113 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
114 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 115 | } |
b5e9e562 | 116 | /* end-sanitize-m32rx */ |
c8cf7e17 | 117 | \f |
ebde3f62 | 118 | const char * md_shortopts = ""; |
c8cf7e17 | 119 | |
a450e9f4 NC |
120 | struct option md_longopts[] = |
121 | { | |
b5e9e562 | 122 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
123 | #define OPTION_M32RX (OPTION_MD_BASE) |
124 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
b6930bdf NC |
125 | #define OPTION_WARN (OPTION_MD_BASE + 1) |
126 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN}, | |
127 | #define OPTION_NO_WARN (OPTION_MD_BASE + 2) | |
128 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, | |
b5e9e562 | 129 | /* end-sanitize-m32rx */ |
a450e9f4 | 130 | |
c8cf7e17 | 131 | #if 0 /* not supported yet */ |
b6930bdf | 132 | #define OPTION_RELAX (OPTION_MD_BASE + 3) |
c8cf7e17 | 133 | {"relax", no_argument, NULL, OPTION_RELAX}, |
b6930bdf | 134 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 4) |
c8cf7e17 DE |
135 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
136 | #endif | |
a450e9f4 | 137 | |
c8cf7e17 DE |
138 | {NULL, no_argument, NULL, 0} |
139 | }; | |
ebde3f62 | 140 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
141 | |
142 | int | |
143 | md_parse_option (c, arg) | |
ebde3f62 NC |
144 | int c; |
145 | char * arg; | |
c8cf7e17 DE |
146 | { |
147 | switch (c) | |
148 | { | |
b5e9e562 | 149 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
150 | case OPTION_M32RX: |
151 | allow_m32rx (1); | |
152 | break; | |
b6930bdf NC |
153 | |
154 | case OPTION_WARN: | |
155 | warn_explicit_parallel_conflicts = 1; | |
156 | break; | |
157 | ||
158 | case OPTION_NO_WARN: | |
159 | warn_explicit_parallel_conflicts = 0; | |
160 | break; | |
b5e9e562 | 161 | /* end-sanitize-m32rx */ |
a450e9f4 | 162 | |
c8cf7e17 DE |
163 | #if 0 /* not supported yet */ |
164 | case OPTION_RELAX: | |
165 | m32r_relax = 1; | |
166 | break; | |
167 | case OPTION_CPU_DESC: | |
168 | m32r_cpu_desc = arg; | |
169 | break; | |
170 | #endif | |
171 | default: | |
172 | return 0; | |
173 | } | |
174 | return 1; | |
175 | } | |
176 | ||
177 | void | |
178 | md_show_usage (stream) | |
ebde3f62 | 179 | FILE * stream; |
c8cf7e17 | 180 | { |
a450e9f4 | 181 | fprintf (stream, "M32R/X options:\n"); |
b5e9e562 | 182 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
183 | fprintf (stream, "\ |
184 | --m32rx support the extended m32rx instruction set\n"); | |
b6930bdf NC |
185 | |
186 | fprintf (stream, "\ | |
00aa5b17 DE |
187 | --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n"); |
188 | fprintf (stream, "\ | |
b6930bdf | 189 | --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n"); |
b5e9e562 | 190 | /* end-sanitize-m32rx */ |
a450e9f4 | 191 | |
c8cf7e17 DE |
192 | #if 0 |
193 | fprintf (stream, "\ | |
194 | --relax create linker relaxable code\n"); | |
195 | fprintf (stream, "\ | |
196 | --cpu-desc provide runtime cpu description file\n"); | |
c8cf7e17 DE |
197 | #endif |
198 | } | |
199 | ||
200 | static void fill_insn PARAMS ((int)); | |
201 | static void m32r_scomm PARAMS ((int)); | |
202 | ||
203 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
204 | static subsegT prev_subseg; | |
205 | static segT prev_seg; | |
206 | ||
207 | /* The target specific pseudo-ops which we support. */ | |
208 | const pseudo_typeS md_pseudo_table[] = | |
209 | { | |
210 | { "word", cons, 4 }, | |
211 | { "fillinsn", fill_insn, 0 }, | |
212 | { "scomm", m32r_scomm, 0 }, | |
b5e9e562 | 213 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
214 | { "m32r", allow_m32rx, 0}, |
215 | { "m32rx", allow_m32rx, 1}, | |
b5e9e562 | 216 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
217 | { NULL, NULL, 0 } |
218 | }; | |
219 | ||
220 | /* FIXME: Should be machine generated. */ | |
221 | #define NOP_INSN 0x7000 | |
222 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
223 | ||
224 | /* When we align the .text section, insert the correct NOP pattern. | |
225 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
226 | MAX is the maximum number of characters to skip when doing the alignment, | |
227 | or 0 if there is no maximum. */ | |
228 | ||
229 | int | |
230 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
231 | int n; |
232 | const char * fill; | |
233 | int len; | |
234 | int max; | |
c8cf7e17 | 235 | { |
ebde3f62 | 236 | if ((fill == NULL || (* fill == 0 && len == 1)) |
c8cf7e17 DE |
237 | && (now_seg->flags & SEC_CODE) != 0 |
238 | /* Only do this special handling if aligning to at least a | |
239 | 4 byte boundary. */ | |
240 | && n > 1 | |
775fdd0c | 241 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
242 | least two bytes. */ |
243 | && (max == 0 || max > 1)) | |
244 | { | |
245 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
246 | ||
247 | #if 0 | |
248 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
249 | /* FIXME: How much memory will cause gas to use when assembling a big | |
250 | program? Perhaps we can avoid the frag_align call? */ | |
251 | frag_align (1, 0, 0); | |
252 | #endif | |
253 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
254 | nop. */ | |
255 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
256 | /* If doing larger alignments use a repeating sequence of appropriate | |
257 | nops. */ | |
258 | if (n > 2) | |
259 | { | |
ebde3f62 NC |
260 | static const unsigned char multi_nop_pattern[] = |
261 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
262 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
263 | max ? max - 2 : 0); | |
264 | } | |
265 | return 1; | |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static void | |
272 | assemble_nop (opcode) | |
273 | int opcode; | |
274 | { | |
ebde3f62 | 275 | char * f = frag_more (2); |
c8cf7e17 DE |
276 | md_number_to_chars (f, opcode, 2); |
277 | } | |
278 | ||
279 | /* If the last instruction was the first of 2 16 bit insns, | |
280 | output a nop to move the PC to a 32 bit boundary. | |
281 | ||
282 | This is done via an alignment specification since branch relaxing | |
283 | may make it unnecessary. | |
284 | ||
285 | Internally, we need to output one of these each time a 32 bit insn is | |
286 | seen after an insn that is relaxable. */ | |
287 | ||
288 | static void | |
289 | fill_insn (ignore) | |
290 | int ignore; | |
291 | { | |
292 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 293 | prev_insn.insn = NULL; |
c8cf7e17 DE |
294 | seen_relaxable_p = 0; |
295 | } | |
296 | ||
297 | /* Cover function to fill_insn called after a label and at end of assembly. | |
298 | ||
299 | The result is always 1: we're called in a conditional to see if the | |
300 | current line is a label. */ | |
301 | ||
302 | int | |
303 | m32r_fill_insn (done) | |
304 | int done; | |
305 | { | |
ebde3f62 | 306 | segT seg; |
c8cf7e17 DE |
307 | subsegT subseg; |
308 | ||
309 | if (prev_seg != NULL) | |
310 | { | |
ebde3f62 | 311 | seg = now_seg; |
c8cf7e17 | 312 | subseg = now_subseg; |
ebde3f62 | 313 | |
c8cf7e17 | 314 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 315 | |
c8cf7e17 | 316 | fill_insn (0); |
ebde3f62 | 317 | |
c8cf7e17 DE |
318 | subseg_set (seg, subseg); |
319 | } | |
ebde3f62 | 320 | |
c8cf7e17 DE |
321 | return 1; |
322 | } | |
323 | \f | |
324 | void | |
325 | md_begin () | |
326 | { | |
327 | flagword applicable; | |
ebde3f62 NC |
328 | segT seg; |
329 | subsegT subseg; | |
c8cf7e17 DE |
330 | |
331 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
332 | |
333 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 334 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 335 | |
4e9d8dea | 336 | /* Set the machine number and endian. */ |
c8cf7e17 | 337 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
338 | target_big_endian ? |
339 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
340 | |
341 | #if 0 /* not supported yet */ | |
342 | /* If a runtime cpu description file was provided, parse it. */ | |
343 | if (m32r_cpu_desc != NULL) | |
344 | { | |
ebde3f62 | 345 | const char * errmsg; |
c8cf7e17 DE |
346 | |
347 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
348 | if (errmsg != NULL) | |
349 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
350 | } | |
351 | #endif | |
352 | ||
353 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
354 | we don't want the initial section to be .sbss]. */ |
355 | seg = now_seg; | |
c8cf7e17 DE |
356 | subseg = now_subseg; |
357 | ||
358 | /* The sbss section is for local .scomm symbols. */ | |
359 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 360 | |
c8cf7e17 DE |
361 | /* This is copied from perform_an_assembly_pass. */ |
362 | applicable = bfd_applicable_section_flags (stdoutput); | |
363 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 364 | |
c8cf7e17 DE |
365 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
366 | seg_info (bss_section)->bss = 1; | |
367 | #endif | |
368 | ||
369 | subseg_set (seg, subseg); | |
370 | ||
371 | /* We must construct a fake section similar to bfd_com_section | |
372 | but with the name .scommon. */ | |
ebde3f62 NC |
373 | scom_section = bfd_com_section; |
374 | scom_section.name = ".scommon"; | |
375 | scom_section.output_section = & scom_section; | |
376 | scom_section.symbol = & scom_symbol; | |
377 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
378 | scom_symbol = * bfd_com_section.symbol; | |
379 | scom_symbol.name = ".scommon"; | |
380 | scom_symbol.section = & scom_section; | |
a450e9f4 | 381 | |
b5e9e562 | 382 | /* start-sanitize-m32rx */ |
a450e9f4 | 383 | allow_m32rx (enable_m32rx); |
b5e9e562 | 384 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
385 | } |
386 | ||
89285fc9 | 387 | /* start-sanitize-m32rx */ |
55a4759f DE |
388 | #ifdef HAVE_CPU_M32RX |
389 | ||
6cf2575a NC |
390 | /* Returns true if an output of instruction 'a' is referenced by an operand |
391 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
392 | checked, otherwise its inputs are examined. */ | |
ebde3f62 | 393 | static int |
6cf2575a | 394 | first_writes_to_seconds_operands (a, b, check_outputs) |
26192c50 NC |
395 | m32r_insn * a; |
396 | m32r_insn * b; | |
6cf2575a | 397 | const int check_outputs; |
00aa5b17 | 398 | { |
6cf2575a NC |
399 | const CGEN_OPERAND_INSTANCE * a_operands; |
400 | int a_index; | |
00aa5b17 | 401 | |
6cf2575a NC |
402 | /* Scan the operand list of 'a' looking for an output operand. */ |
403 | for (a_index = 0, a_operands = CGEN_INSN_OPERANDS (a->insn); | |
404 | CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END; | |
405 | a_index ++, a_operands ++) | |
26192c50 | 406 | { |
6cf2575a | 407 | if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT) |
26192c50 | 408 | { |
6cf2575a NC |
409 | const CGEN_OPERAND_INSTANCE * b_operands; |
410 | int b_index; | |
411 | ||
412 | /* Scan operand list of 'b' looking for an operand that references | |
413 | the same hardware element, and which goes in the right direction. */ | |
414 | for (b_index = 0, b_operands = CGEN_INSN_OPERANDS (b->insn); | |
415 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; | |
416 | b_index ++, b_operands ++) | |
417 | { | |
418 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
419 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
420 | && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands)) | |
421 | && (a->indices [a_index] == b->indices [b_index])) | |
422 | return 1; | |
423 | } | |
26192c50 NC |
424 | } |
425 | } | |
426 | ||
6cf2575a | 427 | return 0; |
26192c50 NC |
428 | } |
429 | ||
6cf2575a | 430 | /* Returns true if the insn can (potentially) alter the program counter. */ |
89285fc9 | 431 | static int |
6cf2575a | 432 | writes_to_pc (a) |
89285fc9 | 433 | m32r_insn * a; |
89285fc9 | 434 | { |
6cf2575a | 435 | const CGEN_OPERAND_INSTANCE * a_operands; |
89285fc9 | 436 | |
6cf2575a NC |
437 | for (a_operands = CGEN_INSN_OPERANDS (a->insn); |
438 | CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END; | |
439 | a_operands ++) | |
440 | { | |
441 | if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL | |
442 | && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC) | |
443 | return 1; | |
444 | } | |
89285fc9 | 445 | |
6cf2575a | 446 | return 0; |
89285fc9 | 447 | } |
26192c50 | 448 | |
775fdd0c NC |
449 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
450 | otherwise it returns a pointer to an error message explaining why not. */ | |
451 | static const char * | |
26192c50 | 452 | can_make_parallel (a, b) |
b6930bdf NC |
453 | m32r_insn * a; |
454 | m32r_insn * b; | |
775fdd0c NC |
455 | { |
456 | PIPE_ATTR a_pipe; | |
457 | PIPE_ATTR b_pipe; | |
89285fc9 | 458 | |
775fdd0c | 459 | /* Make sure the instructions are the right length. */ |
b6930bdf NC |
460 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
461 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c | 462 | abort(); |
89285fc9 | 463 | |
6cf2575a | 464 | if (first_writes_to_seconds_operands (a, b, true)) |
89285fc9 | 465 | return "Instructions write to the same destination register."; |
775fdd0c | 466 | |
b6930bdf NC |
467 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
468 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 469 | |
b6930bdf | 470 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
471 | if ( a_pipe == PIPE_NONE |
472 | || b_pipe == PIPE_NONE) | |
473 | return "Instructions do not use parallel execution pipelines."; | |
89285fc9 NC |
474 | |
475 | /* Leave this test for last, since it is the only test that can | |
476 | go away if the instructions are swapped, and we want to make | |
477 | sure that any other errors are detected before this happens. */ | |
775fdd0c NC |
478 | if ( a_pipe == PIPE_S |
479 | || b_pipe == PIPE_O) | |
480 | return "Instructions share the same execution pipeline"; | |
89285fc9 | 481 | |
775fdd0c NC |
482 | return NULL; |
483 | } | |
775fdd0c NC |
484 | |
485 | #ifdef CGEN_INT_INSN | |
486 | static void | |
b6930bdf NC |
487 | make_parallel (buffer) |
488 | cgen_insn_t * buffer; | |
775fdd0c NC |
489 | { |
490 | /* Force the top bit of the second insn to be set. */ | |
491 | ||
492 | bfd_vma value; | |
493 | ||
494 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
495 | { | |
496 | value = bfd_getb16 ((bfd_byte *) buffer); | |
497 | value |= 0x8000; | |
498 | bfd_putb16 (value, (char *) buffer); | |
499 | } | |
500 | else | |
501 | { | |
502 | value = bfd_getl16 ((bfd_byte *) buffer); | |
503 | value |= 0x8000; | |
504 | bfd_putl16 (value, (char *) buffer); | |
505 | } | |
506 | } | |
507 | #else | |
508 | static void | |
b6930bdf NC |
509 | make_parallel (buffer) |
510 | char * buffer; | |
775fdd0c NC |
511 | { |
512 | /* Force the top bit of the second insn to be set. */ | |
513 | ||
514 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
515 | } | |
516 | #endif | |
517 | ||
518 | ||
b6930bdf NC |
519 | static void |
520 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 521 | char * str; |
b6930bdf | 522 | char * str2; |
c8cf7e17 | 523 | { |
b6930bdf NC |
524 | char * str3; |
525 | m32r_insn first; | |
526 | m32r_insn second; | |
527 | char * errmsg; | |
ebde3f62 | 528 | |
b6930bdf | 529 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 530 | |
b6930bdf NC |
531 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
532 | so that the parallel instruction will start on a 32 bit boundary. */ | |
533 | if (prev_insn.insn) | |
534 | fill_insn (0); | |
ebde3f62 | 535 | |
b6930bdf NC |
536 | /* Parse the first instruction. */ |
537 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
538 | (str, & first.fields, first.buffer, & errmsg))) | |
539 | { | |
540 | as_bad (errmsg); | |
541 | return; | |
542 | } | |
79420f9a | 543 | |
b6930bdf NC |
544 | /* Check to see if this is an allowable parallel insn. */ |
545 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
546 | { | |
547 | as_bad ("instruction '%s' cannot be executed in parallel.", str); | |
548 | return; | |
549 | } | |
ebde3f62 | 550 | |
b6930bdf NC |
551 | if (! enable_m32rx |
552 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
553 | { | |
554 | as_bad ("instruction '%s' is for the M32RX only", str); | |
555 | return; | |
ebde3f62 NC |
556 | } |
557 | ||
b6930bdf NC |
558 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
559 | str3 = str; /* Save the original string pointer. */ | |
560 | str = str2 + 2; /* Advanced past the parsed string. */ | |
561 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
562 | ||
563 | /* Preserve any fixups that have been generated and reset the list to empty. */ | |
564 | cgen_save_fixups(); | |
565 | ||
6cf2575a NC |
566 | /* Get the indicies of the operands of the instruction. */ |
567 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
568 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
569 | if (m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16, | |
570 | first.indices) == NULL) | |
571 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn"); | |
572 | ||
b6930bdf NC |
573 | /* Parse the second instruction. */ |
574 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
575 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
576 | { |
577 | as_bad (errmsg); | |
578 | return; | |
579 | } | |
c8cf7e17 | 580 | |
b6930bdf NC |
581 | /* Check it. */ |
582 | if (! enable_m32rx | |
583 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
ebde3f62 NC |
584 | { |
585 | as_bad ("instruction '%s' is for the M32RX only", str); | |
586 | return; | |
587 | } | |
ebde3f62 | 588 | |
b6930bdf | 589 | if (! enable_m32rx) |
ebde3f62 | 590 | { |
b6930bdf NC |
591 | if ( strcmp (first.insn->name, "nop") != 0 |
592 | && strcmp (second.insn->name, "nop") != 0) | |
ebde3f62 | 593 | { |
b6930bdf NC |
594 | as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2); |
595 | return; | |
ebde3f62 | 596 | } |
b6930bdf | 597 | } |
9121b102 | 598 | |
6cf2575a NC |
599 | /* Get the indicies of the operands of the instruction. */ |
600 | if (m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16, | |
601 | second.indices) == NULL) | |
602 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn"); | |
603 | ||
b6930bdf NC |
604 | /* We assume that if the first instruction writes to a register that is |
605 | read by the second instruction it is because the programmer intended | |
606 | this to happen, (after all they have explicitly requested that these | |
26192c50 NC |
607 | two instructions be executed in parallel). Although if the global |
608 | variable warn_explicit_parallel_conflicts is true then we do generate | |
609 | a warning message. Similarly we assume that parallel branch and jump | |
00aa5b17 | 610 | instructions are deliberate and should not produce errors. */ |
b6930bdf | 611 | |
00aa5b17 | 612 | if (warn_explicit_parallel_conflicts) |
b6930bdf | 613 | { |
6cf2575a NC |
614 | if (first_writes_to_seconds_operands (& first, & second, false)) |
615 | as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2); | |
26192c50 | 616 | |
6cf2575a NC |
617 | if (first_writes_to_seconds_operands (& second, & first, false)) |
618 | as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2); | |
00aa5b17 DE |
619 | } |
620 | ||
621 | if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL) | |
622 | { | |
b6930bdf NC |
623 | /* Get the fixups for the first instruction. */ |
624 | cgen_swap_fixups (); | |
625 | ||
626 | /* Write it out. */ | |
627 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
628 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
ebde3f62 | 629 | |
b6930bdf NC |
630 | /* Force the top bit of the second insn to be set. */ |
631 | make_parallel (second.buffer); | |
ebde3f62 | 632 | |
b6930bdf NC |
633 | /* Get its fixups. */ |
634 | cgen_restore_fixups (); | |
775fdd0c | 635 | |
b6930bdf NC |
636 | /* Write it out. */ |
637 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
638 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
639 | } | |
89285fc9 | 640 | /* Try swapping the instructions to see if they work that way. */ |
6cf2575a | 641 | else if (can_make_parallel (& second, & first) == NULL) |
b6930bdf NC |
642 | { |
643 | /* Write out the second instruction first. */ | |
644 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
645 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
775fdd0c | 646 | |
b6930bdf NC |
647 | /* Force the top bit of the first instruction to be set. */ |
648 | make_parallel (first.buffer); | |
649 | ||
650 | /* Get the fixups for the first instruction. */ | |
651 | cgen_restore_fixups (); | |
652 | ||
653 | /* Write out the first instruction. */ | |
654 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
655 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
656 | } | |
657 | else | |
658 | { | |
659 | as_bad ("'%s': %s", str2, errmsg); | |
660 | return; | |
661 | } | |
ebde3f62 | 662 | |
b6930bdf NC |
663 | /* Set these so m32r_fill_insn can use them. */ |
664 | prev_seg = now_seg; | |
665 | prev_subseg = now_subseg; | |
666 | ||
667 | return; | |
668 | } | |
55a4759f DE |
669 | |
670 | #endif /* HAVE_CPU_M32RX */ | |
671 | ||
b6930bdf NC |
672 | /* end-sanitize-m32rx */ |
673 | ||
674 | ||
675 | void | |
676 | md_assemble (str) | |
677 | char * str; | |
678 | { | |
679 | m32r_insn insn; | |
680 | char * errmsg; | |
681 | char * str2 = NULL; | |
682 | ||
683 | /* Initialize GAS's cgen interface for a new instruction. */ | |
684 | cgen_asm_init_parse (); | |
685 | ||
686 | /* start-sanitize-m32rx */ | |
55a4759f | 687 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
688 | /* Look for a parallel instruction seperator. */ |
689 | if ((str2 = strstr (str, "||")) != NULL) | |
690 | { | |
691 | assemble_parallel_insn (str, str2); | |
692 | return; | |
ebde3f62 | 693 | } |
55a4759f | 694 | #endif |
b6930bdf NC |
695 | /* end-sanitize-m32rx */ |
696 | ||
697 | insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); | |
698 | if (!insn.insn) | |
699 | { | |
700 | as_bad (errmsg); | |
701 | return; | |
702 | } | |
703 | ||
704 | /* start-sanitize-m32rx */ | |
55a4759f | 705 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
706 | if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
707 | { | |
708 | as_bad ("instruction '%s' is for the M32RX only", str); | |
709 | return; | |
710 | } | |
55a4759f | 711 | #endif |
b6930bdf NC |
712 | /* end-sanitize-m32rx */ |
713 | ||
714 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
715 | { |
716 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 717 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 NC |
718 | { |
719 | /* FIXME: If calling fill_insn too many times turns us into a memory | |
720 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ | |
721 | fill_insn (0); | |
722 | } | |
723 | ||
b6930bdf NC |
724 | (void) cgen_asm_finish_insn (insn.insn, insn.buffer, |
725 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
c8cf7e17 DE |
726 | } |
727 | else | |
728 | { | |
b6930bdf NC |
729 | /* start-sanitize-m32rx */ |
730 | /* start-sanitize-phase2-m32rx */ | |
731 | int swap = false; | |
732 | /* end-sanitize-phase2-m32rx */ | |
733 | /* end-sanitize-m32rx */ | |
734 | ||
735 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
736 | abort(); | |
737 | ||
6cf2575a NC |
738 | /* Get the indicies of the operands of the instruction. */ |
739 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
740 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
741 | if (m32r_cgen_get_insn_operands (insn.insn, bfd_getb16 ((char *) insn.buffer), 16, | |
742 | insn.indices) == NULL) | |
743 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed"); | |
744 | ||
c8cf7e17 | 745 | /* Keep track of whether we've seen a pair of 16 bit insns. |
b6930bdf NC |
746 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
747 | if (prev_insn.insn) | |
775fdd0c NC |
748 | { |
749 | /* start-sanitize-m32rx */ | |
b6930bdf | 750 | /* start-sanitize-phase2-m32rx */ |
55a4759f | 751 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
752 | /* Look to see if this instruction can be combined with the |
753 | previous instruction to make one, parallel, 32 bit instruction. | |
754 | If the previous instruction (potentially) changed the flow of | |
755 | program control, then it cannot be combined with the current | |
ed295804 NC |
756 | instruction. Also if the output of the previous instruction |
757 | is used as an input to the current instruction then it cannot | |
758 | be combined. Otherwise call can_make_parallel() with both | |
b6930bdf | 759 | orderings of the instructions to see if they can be combined. */ |
6cf2575a NC |
760 | if (! writes_to_pc (& prev_insn) |
761 | && ! first_writes_to_seconds_operands (& prev_insn, &insn, false) | |
ed295804 | 762 | ) |
775fdd0c | 763 | { |
ed295804 NC |
764 | if (can_make_parallel (& prev_insn, & insn) == NULL) |
765 | make_parallel (insn.buffer); | |
766 | else if (can_make_parallel (& insn, & prev_insn.insn) == NULL) | |
767 | swap = true; | |
775fdd0c | 768 | } |
55a4759f | 769 | #endif |
b6930bdf | 770 | /* end-sanitize-phase2-m32rx */ |
775fdd0c NC |
771 | /* end-sanitize-m32rx */ |
772 | ||
b6930bdf | 773 | prev_insn.insn = NULL; |
775fdd0c | 774 | } |
c8cf7e17 | 775 | else |
775fdd0c | 776 | { |
b6930bdf | 777 | prev_insn = insn; |
775fdd0c | 778 | } |
c8cf7e17 | 779 | |
b6930bdf NC |
780 | /* Record the frag that might be used by this insn. */ |
781 | insn.frag = frag_now; | |
782 | insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer, | |
783 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
784 | ||
785 | /* start-sanitize-m32rx */ | |
786 | /* start-sanitize-phase2-m32rx */ | |
55a4759f | 787 | #ifdef HAVE_CPU_M32RX |
b6930bdf NC |
788 | if (swap) |
789 | { | |
790 | int tmp; | |
791 | ||
792 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
793 | ||
794 | /* Swap the two insns */ | |
795 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
796 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
797 | ||
798 | make_parallel (insn.addr); | |
799 | ||
800 | /* Swap any relaxable frags recorded for the two insns. */ | |
801 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
802 | { | |
803 | prev_insn.frag->fr_opcode = insn.addr; | |
804 | } | |
805 | else if (insn.frag->fr_opcode == insn.addr) | |
806 | { | |
807 | insn.frag->fr_opcode = prev_insn.addr; | |
808 | } | |
809 | } | |
810 | /* end-sanitize-phase2-m32rx */ | |
811 | ||
812 | /* Record where this instruction was assembled. */ | |
813 | prev_insn.addr = insn.addr; | |
814 | prev_insn.frag = insn.frag; | |
55a4759f | 815 | #endif |
b6930bdf NC |
816 | /* end-sanitize-m32rx */ |
817 | ||
c8cf7e17 DE |
818 | /* If the insn needs the following one to be on a 32 bit boundary |
819 | (e.g. subroutine calls), fill this insn's slot. */ | |
b6930bdf NC |
820 | if (prev_insn.insn |
821 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0) | |
c8cf7e17 | 822 | fill_insn (0); |
c8cf7e17 | 823 | |
775fdd0c | 824 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
825 | mark the fact so that we can emit an alignment directive for a |
826 | following 32 bit insn if we see one. */ | |
827 | if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0) | |
775fdd0c NC |
828 | seen_relaxable_p = 1; |
829 | } | |
c8cf7e17 DE |
830 | |
831 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 832 | prev_seg = now_seg; |
c8cf7e17 DE |
833 | prev_subseg = now_subseg; |
834 | } | |
835 | ||
836 | /* The syntax in the manual says constants begin with '#'. | |
837 | We just ignore it. */ | |
838 | ||
839 | void | |
840 | md_operand (expressionP) | |
ebde3f62 | 841 | expressionS * expressionP; |
c8cf7e17 | 842 | { |
ebde3f62 | 843 | if (* input_line_pointer == '#') |
c8cf7e17 | 844 | { |
ebde3f62 | 845 | input_line_pointer ++; |
c8cf7e17 DE |
846 | expression (expressionP); |
847 | } | |
848 | } | |
849 | ||
850 | valueT | |
851 | md_section_align (segment, size) | |
ebde3f62 | 852 | segT segment; |
c8cf7e17 DE |
853 | valueT size; |
854 | { | |
855 | int align = bfd_get_section_alignment (stdoutput, segment); | |
856 | return ((size + (1 << align) - 1) & (-1 << align)); | |
857 | } | |
858 | ||
859 | symbolS * | |
860 | md_undefined_symbol (name) | |
ebde3f62 | 861 | char * name; |
c8cf7e17 DE |
862 | { |
863 | return 0; | |
864 | } | |
865 | \f | |
866 | /* .scomm pseudo-op handler. | |
867 | ||
868 | This is a new pseudo-op to handle putting objects in .scommon. | |
869 | By doing this the linker won't need to do any work and more importantly | |
870 | it removes the implicit -G arg necessary to correctly link the object file. | |
871 | */ | |
872 | ||
873 | static void | |
874 | m32r_scomm (ignore) | |
875 | int ignore; | |
876 | { | |
ebde3f62 NC |
877 | register char * name; |
878 | register char c; | |
879 | register char * p; | |
880 | offsetT size; | |
881 | register symbolS * symbolP; | |
882 | offsetT align; | |
883 | int align2; | |
c8cf7e17 DE |
884 | |
885 | name = input_line_pointer; | |
886 | c = get_symbol_end (); | |
887 | ||
888 | /* just after name is now '\0' */ | |
889 | p = input_line_pointer; | |
ebde3f62 | 890 | * p = c; |
c8cf7e17 | 891 | SKIP_WHITESPACE (); |
ebde3f62 | 892 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
893 | { |
894 | as_bad ("Expected comma after symbol-name: rest of line ignored."); | |
895 | ignore_rest_of_line (); | |
896 | return; | |
897 | } | |
898 | ||
b6930bdf | 899 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
900 | if ((size = get_absolute_expression ()) < 0) |
901 | { | |
902 | as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size); | |
903 | ignore_rest_of_line (); | |
904 | return; | |
905 | } | |
906 | ||
907 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 908 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
909 | align = 8; |
910 | else | |
911 | { | |
ebde3f62 | 912 | ++ input_line_pointer; |
c8cf7e17 DE |
913 | align = get_absolute_expression (); |
914 | if (align <= 0) | |
915 | { | |
916 | as_warn ("ignoring bad alignment"); | |
917 | align = 8; | |
918 | } | |
919 | } | |
920 | /* Convert to a power of 2 alignment. */ | |
921 | if (align) | |
922 | { | |
ebde3f62 | 923 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
924 | continue; |
925 | if (align != 1) | |
926 | { | |
927 | as_bad ("Common alignment not a power of 2"); | |
928 | ignore_rest_of_line (); | |
929 | return; | |
930 | } | |
931 | } | |
932 | else | |
933 | align2 = 0; | |
934 | ||
ebde3f62 | 935 | * p = 0; |
c8cf7e17 | 936 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 937 | * p = c; |
c8cf7e17 DE |
938 | |
939 | if (S_IS_DEFINED (symbolP)) | |
940 | { | |
941 | as_bad ("Ignoring attempt to re-define symbol `%s'.", | |
942 | S_GET_NAME (symbolP)); | |
943 | ignore_rest_of_line (); | |
944 | return; | |
945 | } | |
946 | ||
947 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
948 | { | |
949 | as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.", | |
950 | S_GET_NAME (symbolP), | |
951 | (long) S_GET_VALUE (symbolP), | |
952 | (long) size); | |
953 | ||
954 | ignore_rest_of_line (); | |
955 | return; | |
956 | } | |
957 | ||
958 | if (symbolP->local) | |
959 | { | |
ebde3f62 NC |
960 | segT old_sec = now_seg; |
961 | int old_subsec = now_subseg; | |
962 | char * pfrag; | |
c8cf7e17 DE |
963 | |
964 | record_alignment (sbss_section, align2); | |
965 | subseg_set (sbss_section, 0); | |
775fdd0c | 966 | |
c8cf7e17 DE |
967 | if (align2) |
968 | frag_align (align2, 0, 0); | |
775fdd0c | 969 | |
c8cf7e17 DE |
970 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
971 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 972 | |
c8cf7e17 | 973 | symbolP->sy_frag = frag_now; |
b6930bdf | 974 | |
c8cf7e17 DE |
975 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
976 | (char *) 0); | |
ebde3f62 | 977 | * pfrag = 0; |
c8cf7e17 DE |
978 | S_SET_SIZE (symbolP, size); |
979 | S_SET_SEGMENT (symbolP, sbss_section); | |
980 | S_CLEAR_EXTERNAL (symbolP); | |
981 | subseg_set (old_sec, old_subsec); | |
982 | } | |
983 | else | |
984 | { | |
985 | S_SET_VALUE (symbolP, (valueT) size); | |
986 | S_SET_ALIGN (symbolP, align2); | |
987 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 988 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
989 | } |
990 | ||
991 | demand_empty_rest_of_line (); | |
992 | } | |
993 | \f | |
994 | /* Interface to relax_segment. */ | |
995 | ||
996 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
997 | ||
998 | const relax_typeS md_relax_table[] = | |
999 | { | |
1000 | /* The fields are: | |
1001 | 1) most positive reach of this state, | |
1002 | 2) most negative reach of this state, | |
1003 | 3) how many bytes this mode will add to the size of the current frag | |
1004 | 4) which index into the table to try if we can't fit into this one. */ | |
1005 | ||
1006 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1007 | each list. */ | |
1008 | {1, 1, 0, 0}, | |
1009 | ||
1010 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1011 | so we subtract 2 from the following. */ | |
1012 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1013 | This doesn't handle a branch in the right slot at the border: | |
1014 | the "& -4" isn't taken into account. It's not important enough to | |
1015 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1016 | case). */ | |
1017 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1018 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1019 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1020 | /* Same thing, but with leading nop for alignment. */ | |
1021 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1022 | }; | |
1023 | ||
1024 | long | |
1025 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1026 | fragS * fragP; |
1027 | long stretch; | |
c8cf7e17 DE |
1028 | { |
1029 | /* Address of branch insn. */ | |
1030 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1031 | long growth = 0; | |
1032 | ||
1033 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1034 | if (fragP->fr_subtype == 2) | |
1035 | { | |
1036 | if ((address & 3) != 0) | |
1037 | { | |
1038 | fragP->fr_subtype = 3; | |
1039 | growth = 2; | |
1040 | } | |
1041 | } | |
1042 | else if (fragP->fr_subtype == 3) | |
1043 | { | |
1044 | if ((address & 3) == 0) | |
1045 | { | |
1046 | fragP->fr_subtype = 2; | |
1047 | growth = -2; | |
1048 | } | |
1049 | } | |
1050 | else | |
1051 | { | |
1052 | growth = relax_frag (fragP, stretch); | |
1053 | ||
1054 | /* Long jump on odd halfword boundary? */ | |
1055 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1056 | { | |
1057 | fragP->fr_subtype = 3; | |
1058 | growth += 2; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | return growth; | |
1063 | } | |
1064 | ||
1065 | /* Return an initial guess of the length by which a fragment must grow to | |
1066 | hold a branch to reach its destination. | |
1067 | Also updates fr_type/fr_subtype as necessary. | |
1068 | ||
1069 | Called just before doing relaxation. | |
1070 | Any symbol that is now undefined will not become defined. | |
1071 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1072 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1073 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1074 | 0 value. */ | |
1075 | ||
1076 | int | |
1077 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1078 | fragS * fragP; |
1079 | segT segment; | |
c8cf7e17 | 1080 | { |
ebde3f62 NC |
1081 | int old_fr_fix = fragP->fr_fix; |
1082 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1083 | |
1084 | /* The only thing we have to handle here are symbols outside of the | |
1085 | current segment. They may be undefined or in a different segment in | |
1086 | which case linker scripts may place them anywhere. | |
1087 | However, we can't finish the fragment here and emit the reloc as insn | |
1088 | alignment requirements may move the insn about. */ | |
1089 | ||
1090 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1091 | { | |
1092 | /* The symbol is undefined in this segment. | |
1093 | Change the relaxation subtype to the max allowable and leave | |
1094 | all further handling to md_convert_frag. */ | |
1095 | fragP->fr_subtype = 2; | |
1096 | ||
1097 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1098 | /* Change 16 bit insn to 32 bit insn. */ | |
1099 | opcode[0] |= 0x80; | |
1100 | ||
1101 | /* Increase known (fixed) size of fragment. */ | |
1102 | fragP->fr_fix += 2; | |
1103 | ||
1104 | /* Create a relocation for it. */ | |
1105 | fix_new (fragP, old_fr_fix, 4, | |
1106 | fragP->fr_symbol, | |
1107 | fragP->fr_offset, 1 /* pcrel */, | |
1108 | /* FIXME: Can't use a real BFD reloc here. | |
1109 | cgen_md_apply_fix3 can't handle it. */ | |
1110 | BFD_RELOC_M32R_26_PCREL); | |
1111 | ||
1112 | /* Mark this fragment as finished. */ | |
1113 | frag_wane (fragP); | |
1114 | #else | |
a450e9f4 | 1115 | { |
ebde3f62 NC |
1116 | const CGEN_INSN * insn; |
1117 | int i; | |
a450e9f4 NC |
1118 | |
1119 | /* Update the recorded insn. | |
1120 | Fortunately we don't have to look very far. | |
1121 | FIXME: Change this to record in the instruction the next higher | |
1122 | relaxable insn to use. */ | |
1123 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1124 | { | |
b5e9e562 DE |
1125 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1126 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1127 | == 0) |
1128 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1129 | break; | |
1130 | } | |
1131 | if (i == 4) | |
1132 | abort (); | |
b6930bdf | 1133 | |
a450e9f4 NC |
1134 | fragP->fr_cgen.insn = insn; |
1135 | return 2; | |
1136 | } | |
c8cf7e17 DE |
1137 | #endif |
1138 | } | |
1139 | ||
1140 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1141 | } | |
1142 | ||
1143 | /* *fragP has been relaxed to its final size, and now needs to have | |
1144 | the bytes inside it modified to conform to the new size. | |
1145 | ||
1146 | Called after relaxation is finished. | |
1147 | fragP->fr_type == rs_machine_dependent. | |
1148 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1149 | ||
1150 | void | |
1151 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1152 | bfd * abfd; |
1153 | segT sec; | |
1154 | fragS * fragP; | |
c8cf7e17 | 1155 | { |
ebde3f62 NC |
1156 | char * opcode; |
1157 | char * displacement; | |
1158 | int target_address; | |
1159 | int opcode_address; | |
1160 | int extension; | |
1161 | int addend; | |
c8cf7e17 DE |
1162 | |
1163 | opcode = fragP->fr_opcode; | |
1164 | ||
1165 | /* Address opcode resides at in file space. */ | |
1166 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1167 | ||
1168 | switch (fragP->fr_subtype) | |
1169 | { | |
1170 | case 1 : | |
1171 | extension = 0; | |
ebde3f62 | 1172 | displacement = & opcode[1]; |
c8cf7e17 DE |
1173 | break; |
1174 | case 2 : | |
1175 | opcode[0] |= 0x80; | |
1176 | extension = 2; | |
ebde3f62 | 1177 | displacement = & opcode[1]; |
c8cf7e17 DE |
1178 | break; |
1179 | case 3 : | |
1180 | opcode[2] = opcode[0] | 0x80; | |
1181 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1182 | opcode_address += 2; | |
1183 | extension = 4; | |
ebde3f62 | 1184 | displacement = & opcode[3]; |
c8cf7e17 DE |
1185 | break; |
1186 | default : | |
1187 | abort (); | |
1188 | } | |
1189 | ||
1190 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1191 | { | |
1192 | /* symbol must be resolved by linker */ | |
1193 | if (fragP->fr_offset & 3) | |
1194 | as_warn ("Addend to unresolved symbol not on word boundary."); | |
1195 | addend = fragP->fr_offset >> 2; | |
1196 | } | |
1197 | else | |
1198 | { | |
1199 | /* Address we want to reach in file space. */ | |
1200 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1201 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1202 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1203 | } | |
1204 | ||
1205 | /* Create a relocation for symbols that must be resolved by the linker. | |
1206 | Otherwise output the completed insn. */ | |
1207 | ||
1208 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1209 | { | |
1210 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1211 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1212 | cgen_record_fixup (fragP, |
1213 | /* Offset of branch insn in frag. */ | |
1214 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1215 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1216 | 4 /*length*/, |
1217 | /* FIXME: quick hack */ | |
1218 | #if 0 | |
a450e9f4 | 1219 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1220 | #else |
1221 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1222 | #endif | |
a450e9f4 | 1223 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1224 | fragP->fr_symbol, fragP->fr_offset); |
1225 | } | |
1226 | ||
1227 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1228 | ||
1229 | md_number_to_chars (displacement, (valueT) addend, | |
1230 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1231 | ||
1232 | fragP->fr_fix += extension; | |
1233 | } | |
1234 | \f | |
1235 | /* Functions concerning relocs. */ | |
1236 | ||
1237 | /* The location from which a PC relative jump should be calculated, | |
1238 | given a PC relative reloc. */ | |
1239 | ||
1240 | long | |
1241 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1242 | fixS * fixP; |
1243 | segT sec; | |
c8cf7e17 DE |
1244 | { |
1245 | if (fixP->fx_addsy != (symbolS *) NULL | |
1246 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1247 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1248 | { | |
1249 | /* The symbol is undefined (or is defined but not in this section). | |
1250 | Let the linker figure it out. */ | |
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1255 | } | |
1256 | ||
1257 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1258 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1259 | *FIXP may be modified if desired. */ | |
1260 | ||
1261 | bfd_reloc_code_real_type | |
1262 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1263 | const CGEN_INSN * insn; |
1264 | const CGEN_OPERAND * operand; | |
1265 | fixS * fixP; | |
c8cf7e17 DE |
1266 | { |
1267 | switch (CGEN_OPERAND_TYPE (operand)) | |
1268 | { | |
1269 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1270 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1271 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1272 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1273 | case M32R_OPERAND_HI16 : | |
1274 | case M32R_OPERAND_SLO16 : | |
1275 | case M32R_OPERAND_ULO16 : | |
1276 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1277 | if (fixP->tc_fix_data.opinfo != 0) | |
1278 | return fixP->tc_fix_data.opinfo; | |
1279 | break; | |
1280 | } | |
1281 | return BFD_RELOC_NONE; | |
1282 | } | |
1283 | ||
b6930bdf NC |
1284 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1285 | ||
1286 | static void | |
1287 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1288 | int reloc_type; | |
1289 | fixS * fixP; | |
1290 | segT seg; | |
1291 | { | |
1292 | struct m32r_hi_fixup * hi_fixup; | |
1293 | ||
1294 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1295 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1296 | ||
1297 | hi_fixup = ((struct m32r_hi_fixup *) | |
1298 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1299 | hi_fixup->fixp = fixP; | |
1300 | hi_fixup->seg = now_seg; | |
1301 | hi_fixup->next = m32r_hi_fixup_list; | |
1302 | ||
1303 | m32r_hi_fixup_list = hi_fixup; | |
1304 | } | |
1305 | ||
c8cf7e17 DE |
1306 | /* Called while parsing an instruction to create a fixup. |
1307 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1308 | ||
1309 | fixS * | |
1310 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1311 | fragS * frag; |
1312 | int where; | |
1313 | const CGEN_INSN * insn; | |
1314 | int length; | |
1315 | const CGEN_OPERAND * operand; | |
1316 | int opinfo; | |
1317 | expressionS * exp; | |
c8cf7e17 | 1318 | { |
ebde3f62 NC |
1319 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1320 | operand, opinfo, exp); | |
c8cf7e17 DE |
1321 | |
1322 | switch (CGEN_OPERAND_TYPE (operand)) | |
1323 | { | |
1324 | case M32R_OPERAND_HI16 : | |
1325 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1326 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1327 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1328 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1329 | break; | |
1330 | } | |
1331 | ||
1332 | return fixP; | |
1333 | } | |
1334 | ||
c8cf7e17 DE |
1335 | /* Return BFD reloc type from opinfo field in a fixS. |
1336 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1337 | are BFD_RELOC_UNUSED + operand number. */ | |
1338 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1339 | ||
1340 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1341 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1342 | tc_gen_reloc. */ | |
1343 | ||
1344 | void | |
1345 | m32r_frob_file () | |
1346 | { | |
ebde3f62 | 1347 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1348 | |
1349 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1350 | { | |
ebde3f62 NC |
1351 | segment_info_type * seginfo; |
1352 | int pass; | |
c8cf7e17 DE |
1353 | |
1354 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1355 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1356 | ||
1357 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1358 | if (l->fixp->fx_next != NULL | |
1359 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1360 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1361 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1362 | continue; | |
1363 | ||
1364 | /* Look through the fixups for this segment for a matching `low'. | |
1365 | When we find one, move the high/shigh just in front of it. We do | |
1366 | this in two passes. In the first pass, we try to find a | |
1367 | unique `low'. In the second pass, we permit multiple high's | |
1368 | relocs for a single `low'. */ | |
1369 | seginfo = seg_info (l->seg); | |
1370 | for (pass = 0; pass < 2; pass++) | |
1371 | { | |
ebde3f62 NC |
1372 | fixS * f; |
1373 | fixS * prev; | |
c8cf7e17 DE |
1374 | |
1375 | prev = NULL; | |
1376 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1377 | { | |
1378 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1379 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1380 | && f->fx_addsy == l->fixp->fx_addsy | |
1381 | && f->fx_offset == l->fixp->fx_offset | |
1382 | && (pass == 1 | |
1383 | || prev == NULL | |
1384 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1385 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1386 | || prev->fx_addsy != f->fx_addsy | |
1387 | || prev->fx_offset != f->fx_offset)) | |
1388 | { | |
ebde3f62 | 1389 | fixS ** pf; |
c8cf7e17 DE |
1390 | |
1391 | /* Move l->fixp before f. */ | |
1392 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1393 | * pf != l->fixp; |
1394 | pf = & (* pf)->fx_next) | |
1395 | assert (* pf != NULL); | |
c8cf7e17 | 1396 | |
ebde3f62 | 1397 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1398 | |
1399 | l->fixp->fx_next = f; | |
1400 | if (prev == NULL) | |
1401 | seginfo->fix_root = l->fixp; | |
1402 | else | |
1403 | prev->fx_next = l->fixp; | |
1404 | ||
1405 | break; | |
1406 | } | |
1407 | ||
1408 | prev = f; | |
1409 | } | |
1410 | ||
1411 | if (f != NULL) | |
1412 | break; | |
1413 | ||
1414 | if (pass == 1) | |
1415 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1416 | "Unmatched high/shigh reloc"); | |
1417 | } | |
1418 | } | |
1419 | } | |
1420 | ||
1421 | /* See whether we need to force a relocation into the output file. | |
1422 | This is used to force out switch and PC relative relocations when | |
1423 | relaxing. */ | |
1424 | ||
1425 | int | |
1426 | m32r_force_relocation (fix) | |
ebde3f62 | 1427 | fixS * fix; |
c8cf7e17 DE |
1428 | { |
1429 | if (! m32r_relax) | |
1430 | return 0; | |
1431 | ||
1432 | return (fix->fx_pcrel | |
1433 | || 0 /* ??? */); | |
1434 | } | |
1435 | \f | |
1436 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1437 | ||
1438 | void | |
1439 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1440 | char * buf; |
c8cf7e17 | 1441 | valueT val; |
ebde3f62 | 1442 | int n; |
c8cf7e17 DE |
1443 | { |
1444 | if (target_big_endian) | |
1445 | number_to_chars_bigendian (buf, val, n); | |
1446 | else | |
1447 | number_to_chars_littleendian (buf, val, n); | |
1448 | } | |
1449 | ||
1450 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1451 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1452 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1453 | */ | |
1454 | ||
1455 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1456 | #define MAX_LITTLENUMS 6 | |
1457 | ||
1458 | char * | |
1459 | md_atof (type, litP, sizeP) | |
1460 | char type; | |
1461 | char *litP; | |
1462 | int *sizeP; | |
1463 | { | |
ebde3f62 NC |
1464 | int i; |
1465 | int prec; | |
1466 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1467 | LITTLENUM_TYPE * wordP; | |
1468 | char * t; | |
1469 | char * atof_ieee (); | |
c8cf7e17 DE |
1470 | |
1471 | switch (type) | |
1472 | { | |
1473 | case 'f': | |
1474 | case 'F': | |
1475 | case 's': | |
1476 | case 'S': | |
1477 | prec = 2; | |
1478 | break; | |
1479 | ||
1480 | case 'd': | |
1481 | case 'D': | |
1482 | case 'r': | |
1483 | case 'R': | |
1484 | prec = 4; | |
1485 | break; | |
1486 | ||
1487 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1488 | ||
1489 | default: | |
ebde3f62 | 1490 | * sizeP = 0; |
c8cf7e17 DE |
1491 | return "Bad call to md_atof()"; |
1492 | } | |
1493 | ||
1494 | t = atof_ieee (input_line_pointer, type, words); | |
1495 | if (t) | |
1496 | input_line_pointer = t; | |
ebde3f62 | 1497 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1498 | |
1499 | if (target_big_endian) | |
1500 | { | |
1501 | for (i = 0; i < prec; i++) | |
1502 | { | |
ebde3f62 NC |
1503 | md_number_to_chars (litP, (valueT) words[i], |
1504 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1505 | litP += sizeof (LITTLENUM_TYPE); |
1506 | } | |
1507 | } | |
1508 | else | |
1509 | { | |
1510 | for (i = prec - 1; i >= 0; i--) | |
1511 | { | |
ebde3f62 NC |
1512 | md_number_to_chars (litP, (valueT) words[i], |
1513 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1514 | litP += sizeof (LITTLENUM_TYPE); |
1515 | } | |
1516 | } | |
1517 | ||
1518 | return 0; | |
1519 | } |