Commit | Line | Data |
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a450e9f4 | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "cgen-opc.h" | |
26 | ||
b6930bdf NC |
27 | typedef struct |
28 | { | |
29 | const CGEN_INSN * insn; | |
30 | CGEN_FIELDS fields; | |
31 | #ifdef CGEN_INT_INSN | |
32 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
33 | #else | |
34 | char buffer [CGEN_MAX_INSN_SIZE]; | |
35 | #endif | |
36 | char * addr; | |
37 | fragS * frag; | |
38 | } | |
39 | m32r_insn; | |
40 | ||
41 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
42 | boundary (i.e. was the first of two 16 bit insns). */ | |
43 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
44 | |
45 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
46 | alignment request. */ | |
47 | static int seen_relaxable_p = 0; | |
48 | ||
49 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
50 | for the linker to do relaxing. | |
51 | We do simple forms of relaxing internally, but they are always done. | |
52 | This flag does not apply to them. */ | |
53 | static int m32r_relax; | |
54 | ||
55 | /* If non-NULL, pointer to cpu description file to read. | |
56 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 57 | static char * m32r_cpu_desc; |
c8cf7e17 | 58 | |
b5e9e562 | 59 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
60 | /* Non-zero if -m32rx has been specified, in which case support for the |
61 | extended M32RX instruction set should be enabled. */ | |
a450e9f4 | 62 | static int enable_m32rx = 0; |
b6930bdf NC |
63 | |
64 | /* Non-zero if the programmer should be warned when an explicit parallel | |
65 | instruction might have constraint violations. */ | |
66 | static int warn_explicit_parallel_conflicts = 1; | |
b5e9e562 | 67 | /* end-sanitize-m32rx */ |
a450e9f4 | 68 | |
c8cf7e17 | 69 | /* stuff for .scomm symbols. */ |
ebde3f62 | 70 | static segT sbss_section; |
c8cf7e17 | 71 | static asection scom_section; |
ebde3f62 | 72 | static asymbol scom_symbol; |
c8cf7e17 | 73 | |
ebde3f62 NC |
74 | const char comment_chars[] = ";"; |
75 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 76 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
77 | const char EXP_CHARS[] = "eE"; |
78 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
79 | |
80 | /* Relocations against symbols are done in two | |
81 | parts, with a HI relocation and a LO relocation. Each relocation | |
82 | has only 16 bits of space to store an addend. This means that in | |
83 | order for the linker to handle carries correctly, it must be able | |
84 | to locate both the HI and the LO relocation. This means that the | |
85 | relocations must appear in order in the relocation table. | |
86 | ||
87 | In order to implement this, we keep track of each unmatched HI | |
88 | relocation. We then sort them so that they immediately precede the | |
89 | corresponding LO relocation. */ | |
90 | ||
91 | struct m32r_hi_fixup | |
92 | { | |
ebde3f62 NC |
93 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
94 | fixS * fixp; /* This fixup. */ | |
95 | segT seg; /* The section this fixup is in. */ | |
96 | ||
c8cf7e17 DE |
97 | }; |
98 | ||
99 | /* The list of unmatched HI relocs. */ | |
100 | ||
ebde3f62 | 101 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 102 | |
a450e9f4 | 103 | \f |
b5e9e562 | 104 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
105 | static void |
106 | allow_m32rx (int on) | |
107 | { | |
108 | enable_m32rx = on; | |
109 | ||
110 | if (stdoutput != NULL) | |
ebde3f62 NC |
111 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
112 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 113 | } |
b5e9e562 | 114 | /* end-sanitize-m32rx */ |
c8cf7e17 | 115 | \f |
ebde3f62 | 116 | const char * md_shortopts = ""; |
c8cf7e17 | 117 | |
a450e9f4 NC |
118 | struct option md_longopts[] = |
119 | { | |
b5e9e562 | 120 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
121 | #define OPTION_M32RX (OPTION_MD_BASE) |
122 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
b6930bdf NC |
123 | #define OPTION_WARN (OPTION_MD_BASE + 1) |
124 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN}, | |
125 | #define OPTION_NO_WARN (OPTION_MD_BASE + 2) | |
126 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, | |
b5e9e562 | 127 | /* end-sanitize-m32rx */ |
a450e9f4 | 128 | |
c8cf7e17 | 129 | #if 0 /* not supported yet */ |
b6930bdf | 130 | #define OPTION_RELAX (OPTION_MD_BASE + 3) |
c8cf7e17 | 131 | {"relax", no_argument, NULL, OPTION_RELAX}, |
b6930bdf | 132 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 4) |
c8cf7e17 DE |
133 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
134 | #endif | |
a450e9f4 | 135 | |
c8cf7e17 DE |
136 | {NULL, no_argument, NULL, 0} |
137 | }; | |
ebde3f62 | 138 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
139 | |
140 | int | |
141 | md_parse_option (c, arg) | |
ebde3f62 NC |
142 | int c; |
143 | char * arg; | |
c8cf7e17 DE |
144 | { |
145 | switch (c) | |
146 | { | |
b5e9e562 | 147 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
148 | case OPTION_M32RX: |
149 | allow_m32rx (1); | |
150 | break; | |
b6930bdf NC |
151 | |
152 | case OPTION_WARN: | |
153 | warn_explicit_parallel_conflicts = 1; | |
154 | break; | |
155 | ||
156 | case OPTION_NO_WARN: | |
157 | warn_explicit_parallel_conflicts = 0; | |
158 | break; | |
b5e9e562 | 159 | /* end-sanitize-m32rx */ |
a450e9f4 | 160 | |
c8cf7e17 DE |
161 | #if 0 /* not supported yet */ |
162 | case OPTION_RELAX: | |
163 | m32r_relax = 1; | |
164 | break; | |
165 | case OPTION_CPU_DESC: | |
166 | m32r_cpu_desc = arg; | |
167 | break; | |
168 | #endif | |
169 | default: | |
170 | return 0; | |
171 | } | |
172 | return 1; | |
173 | } | |
174 | ||
175 | void | |
176 | md_show_usage (stream) | |
ebde3f62 | 177 | FILE * stream; |
c8cf7e17 | 178 | { |
a450e9f4 | 179 | fprintf (stream, "M32R/X options:\n"); |
b5e9e562 | 180 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
181 | fprintf (stream, "\ |
182 | --m32rx support the extended m32rx instruction set\n"); | |
b6930bdf NC |
183 | |
184 | fprintf (stream, "\ | |
185 | --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\ | |
186 | --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n"); | |
b5e9e562 | 187 | /* end-sanitize-m32rx */ |
a450e9f4 | 188 | |
c8cf7e17 DE |
189 | #if 0 |
190 | fprintf (stream, "\ | |
191 | --relax create linker relaxable code\n"); | |
192 | fprintf (stream, "\ | |
193 | --cpu-desc provide runtime cpu description file\n"); | |
c8cf7e17 DE |
194 | #endif |
195 | } | |
196 | ||
197 | static void fill_insn PARAMS ((int)); | |
198 | static void m32r_scomm PARAMS ((int)); | |
199 | ||
200 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
201 | static subsegT prev_subseg; | |
202 | static segT prev_seg; | |
203 | ||
204 | /* The target specific pseudo-ops which we support. */ | |
205 | const pseudo_typeS md_pseudo_table[] = | |
206 | { | |
207 | { "word", cons, 4 }, | |
208 | { "fillinsn", fill_insn, 0 }, | |
209 | { "scomm", m32r_scomm, 0 }, | |
b5e9e562 | 210 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
211 | { "m32r", allow_m32rx, 0}, |
212 | { "m32rx", allow_m32rx, 1}, | |
b5e9e562 | 213 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
214 | { NULL, NULL, 0 } |
215 | }; | |
216 | ||
217 | /* FIXME: Should be machine generated. */ | |
218 | #define NOP_INSN 0x7000 | |
219 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
220 | ||
221 | /* When we align the .text section, insert the correct NOP pattern. | |
222 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
223 | MAX is the maximum number of characters to skip when doing the alignment, | |
224 | or 0 if there is no maximum. */ | |
225 | ||
226 | int | |
227 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
228 | int n; |
229 | const char * fill; | |
230 | int len; | |
231 | int max; | |
c8cf7e17 | 232 | { |
ebde3f62 | 233 | if ((fill == NULL || (* fill == 0 && len == 1)) |
c8cf7e17 DE |
234 | && (now_seg->flags & SEC_CODE) != 0 |
235 | /* Only do this special handling if aligning to at least a | |
236 | 4 byte boundary. */ | |
237 | && n > 1 | |
775fdd0c | 238 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
239 | least two bytes. */ |
240 | && (max == 0 || max > 1)) | |
241 | { | |
242 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
243 | ||
244 | #if 0 | |
245 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
246 | /* FIXME: How much memory will cause gas to use when assembling a big | |
247 | program? Perhaps we can avoid the frag_align call? */ | |
248 | frag_align (1, 0, 0); | |
249 | #endif | |
250 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
251 | nop. */ | |
252 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
253 | /* If doing larger alignments use a repeating sequence of appropriate | |
254 | nops. */ | |
255 | if (n > 2) | |
256 | { | |
ebde3f62 NC |
257 | static const unsigned char multi_nop_pattern[] = |
258 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
259 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
260 | max ? max - 2 : 0); | |
261 | } | |
262 | return 1; | |
263 | } | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | static void | |
269 | assemble_nop (opcode) | |
270 | int opcode; | |
271 | { | |
ebde3f62 | 272 | char * f = frag_more (2); |
c8cf7e17 DE |
273 | md_number_to_chars (f, opcode, 2); |
274 | } | |
275 | ||
276 | /* If the last instruction was the first of 2 16 bit insns, | |
277 | output a nop to move the PC to a 32 bit boundary. | |
278 | ||
279 | This is done via an alignment specification since branch relaxing | |
280 | may make it unnecessary. | |
281 | ||
282 | Internally, we need to output one of these each time a 32 bit insn is | |
283 | seen after an insn that is relaxable. */ | |
284 | ||
285 | static void | |
286 | fill_insn (ignore) | |
287 | int ignore; | |
288 | { | |
289 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 290 | prev_insn.insn = NULL; |
c8cf7e17 DE |
291 | seen_relaxable_p = 0; |
292 | } | |
293 | ||
294 | /* Cover function to fill_insn called after a label and at end of assembly. | |
295 | ||
296 | The result is always 1: we're called in a conditional to see if the | |
297 | current line is a label. */ | |
298 | ||
299 | int | |
300 | m32r_fill_insn (done) | |
301 | int done; | |
302 | { | |
ebde3f62 | 303 | segT seg; |
c8cf7e17 DE |
304 | subsegT subseg; |
305 | ||
306 | if (prev_seg != NULL) | |
307 | { | |
ebde3f62 | 308 | seg = now_seg; |
c8cf7e17 | 309 | subseg = now_subseg; |
ebde3f62 | 310 | |
c8cf7e17 | 311 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 312 | |
c8cf7e17 | 313 | fill_insn (0); |
ebde3f62 | 314 | |
c8cf7e17 DE |
315 | subseg_set (seg, subseg); |
316 | } | |
ebde3f62 | 317 | |
c8cf7e17 DE |
318 | return 1; |
319 | } | |
320 | \f | |
321 | void | |
322 | md_begin () | |
323 | { | |
324 | flagword applicable; | |
ebde3f62 NC |
325 | segT seg; |
326 | subsegT subseg; | |
c8cf7e17 DE |
327 | |
328 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
329 | |
330 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 331 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 332 | |
4e9d8dea | 333 | /* Set the machine number and endian. */ |
c8cf7e17 | 334 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
335 | target_big_endian ? |
336 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
337 | |
338 | #if 0 /* not supported yet */ | |
339 | /* If a runtime cpu description file was provided, parse it. */ | |
340 | if (m32r_cpu_desc != NULL) | |
341 | { | |
ebde3f62 | 342 | const char * errmsg; |
c8cf7e17 DE |
343 | |
344 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
345 | if (errmsg != NULL) | |
346 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
347 | } | |
348 | #endif | |
349 | ||
350 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
351 | we don't want the initial section to be .sbss]. */ |
352 | seg = now_seg; | |
c8cf7e17 DE |
353 | subseg = now_subseg; |
354 | ||
355 | /* The sbss section is for local .scomm symbols. */ | |
356 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 357 | |
c8cf7e17 DE |
358 | /* This is copied from perform_an_assembly_pass. */ |
359 | applicable = bfd_applicable_section_flags (stdoutput); | |
360 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 361 | |
c8cf7e17 DE |
362 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
363 | seg_info (bss_section)->bss = 1; | |
364 | #endif | |
365 | ||
366 | subseg_set (seg, subseg); | |
367 | ||
368 | /* We must construct a fake section similar to bfd_com_section | |
369 | but with the name .scommon. */ | |
ebde3f62 NC |
370 | scom_section = bfd_com_section; |
371 | scom_section.name = ".scommon"; | |
372 | scom_section.output_section = & scom_section; | |
373 | scom_section.symbol = & scom_symbol; | |
374 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
375 | scom_symbol = * bfd_com_section.symbol; | |
376 | scom_symbol.name = ".scommon"; | |
377 | scom_symbol.section = & scom_section; | |
a450e9f4 | 378 | |
b5e9e562 | 379 | /* start-sanitize-m32rx */ |
a450e9f4 | 380 | allow_m32rx (enable_m32rx); |
b5e9e562 | 381 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
382 | } |
383 | ||
b6930bdf | 384 | /* start-sanitize-m32rx */ |
ebde3f62 NC |
385 | /* Returns non zero if the given instruction writes to a destination register. */ |
386 | static int | |
387 | writes_to_dest_reg (insn) | |
388 | const CGEN_INSN * insn; | |
389 | { | |
390 | unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); | |
391 | unsigned char c; | |
392 | ||
393 | /* Scan the syntax string looking for a destination register. */ | |
394 | while ((c = (* syntax ++)) != 0) | |
395 | if (c == 128 + M32R_OPERAND_DR) | |
396 | break; | |
397 | ||
398 | return c; | |
399 | } | |
400 | ||
775fdd0c | 401 | /* Returns non zero if the given instruction reads from a source register. |
b6930bdf | 402 | Ignores the first 'num_ignore' macthes in the syntax string. */ |
ebde3f62 | 403 | static int |
b6930bdf | 404 | reads_from_src_reg (insn, num_ignore) |
ebde3f62 | 405 | const CGEN_INSN * insn; |
b6930bdf | 406 | int num_ignore; |
ebde3f62 | 407 | { |
775fdd0c NC |
408 | unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); |
409 | unsigned char c; | |
410 | ||
411 | /* Scan the syntax string looking for a source register. */ | |
412 | while ((c = (* syntax ++)) != 0) | |
413 | { | |
775fdd0c NC |
414 | if ( c == 128 + M32R_OPERAND_SR |
415 | || c == 128 + M32R_OPERAND_SRC1 | |
416 | || c == 128 + M32R_OPERAND_SRC2) | |
b6930bdf NC |
417 | { |
418 | if (num_ignore -- > 0) | |
419 | continue; | |
420 | else | |
421 | break; | |
422 | } | |
775fdd0c NC |
423 | } |
424 | ||
425 | return c; | |
ebde3f62 NC |
426 | } |
427 | ||
775fdd0c | 428 | /* Returns the integer value of the destination register held in the fields. */ |
b6930bdf | 429 | #define get_dest_reg(fields) (fields).f_r1 |
775fdd0c NC |
430 | |
431 | /* Returns an integer representing the source register of the given type. */ | |
432 | static int | |
b6930bdf NC |
433 | get_src_reg (syntax_field, fields) |
434 | unsigned char syntax_field; | |
775fdd0c NC |
435 | CGEN_FIELDS * fields; |
436 | { | |
b6930bdf | 437 | switch (syntax_field) |
775fdd0c NC |
438 | { |
439 | case 128 + M32R_OPERAND_SR: return fields->f_r2; | |
440 | /* Relies upon the fact that no instruction with a $src1 operand | |
441 | also has a $dr operand. */ | |
442 | case 128 + M32R_OPERAND_SRC1: return fields->f_r1; | |
443 | case 128 + M32R_OPERAND_SRC2: return fields->f_r2; | |
444 | default: abort(); return -1; | |
445 | } | |
446 | } | |
447 | ||
775fdd0c NC |
448 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
449 | otherwise it returns a pointer to an error message explaining why not. */ | |
450 | static const char * | |
b6930bdf NC |
451 | can_make_parallel (a, b, test_a_inputs, test_b_inputs) |
452 | m32r_insn * a; | |
453 | m32r_insn * b; | |
454 | int test_a_inputs; | |
455 | int test_b_inputs; | |
775fdd0c NC |
456 | { |
457 | PIPE_ATTR a_pipe; | |
458 | PIPE_ATTR b_pipe; | |
459 | ||
460 | /* Make sure the instructions are the right length. */ | |
b6930bdf NC |
461 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
462 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c NC |
463 | abort(); |
464 | ||
b6930bdf NC |
465 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
466 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 467 | |
b6930bdf | 468 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
469 | if ( a_pipe == PIPE_NONE |
470 | || b_pipe == PIPE_NONE) | |
471 | return "Instructions do not use parallel execution pipelines."; | |
472 | ||
473 | if ( a_pipe == PIPE_S | |
474 | || b_pipe == PIPE_O) | |
475 | return "Instructions share the same execution pipeline"; | |
476 | ||
b6930bdf NC |
477 | if ( writes_to_dest_reg (a->insn) |
478 | && writes_to_dest_reg (b->insn) | |
479 | && (get_dest_reg (a->fields) == get_dest_reg (b->fields))) | |
775fdd0c NC |
480 | return "Instructions write to the same destination register."; |
481 | ||
482 | /* If requested, make sure that the first instruction does not | |
483 | overwrite the inputs of the second instruction. */ | |
b6930bdf | 484 | if (test_b_inputs && writes_to_dest_reg (a->insn)) |
775fdd0c | 485 | { |
b6930bdf NC |
486 | unsigned char syntax_field; |
487 | int skip = 0; | |
775fdd0c | 488 | |
b6930bdf | 489 | while (syntax_field = reads_from_src_reg (b->insn, skip ++)) |
775fdd0c | 490 | { |
b6930bdf | 491 | if (get_src_reg (syntax_field, & b->fields) == get_dest_reg (a->fields)) |
775fdd0c NC |
492 | return "First instruction writes to register read by the second instruction"; |
493 | } | |
494 | } | |
495 | ||
496 | /* Similarly, if requested, make sure that the second instruction | |
497 | does not overwrite the inputs of the first instruction. */ | |
b6930bdf | 498 | if (test_a_inputs && writes_to_dest_reg (b->insn)) |
775fdd0c | 499 | { |
b6930bdf NC |
500 | unsigned char syntax_field; |
501 | int skip = 0; | |
775fdd0c | 502 | |
b6930bdf | 503 | while (syntax_field = reads_from_src_reg (a->insn, skip ++)) |
775fdd0c | 504 | { |
b6930bdf | 505 | if (get_src_reg (syntax_field, & a->fields) == get_dest_reg (b->fields)) |
775fdd0c NC |
506 | return "Second instruction writes to register read by the first instruction"; |
507 | } | |
508 | } | |
509 | ||
510 | return NULL; | |
511 | } | |
775fdd0c NC |
512 | |
513 | #ifdef CGEN_INT_INSN | |
514 | static void | |
b6930bdf NC |
515 | make_parallel (buffer) |
516 | cgen_insn_t * buffer; | |
775fdd0c NC |
517 | { |
518 | /* Force the top bit of the second insn to be set. */ | |
519 | ||
520 | bfd_vma value; | |
521 | ||
522 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
523 | { | |
524 | value = bfd_getb16 ((bfd_byte *) buffer); | |
525 | value |= 0x8000; | |
526 | bfd_putb16 (value, (char *) buffer); | |
527 | } | |
528 | else | |
529 | { | |
530 | value = bfd_getl16 ((bfd_byte *) buffer); | |
531 | value |= 0x8000; | |
532 | bfd_putl16 (value, (char *) buffer); | |
533 | } | |
534 | } | |
535 | #else | |
536 | static void | |
b6930bdf NC |
537 | make_parallel (buffer) |
538 | char * buffer; | |
775fdd0c NC |
539 | { |
540 | /* Force the top bit of the second insn to be set. */ | |
541 | ||
542 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
543 | } | |
544 | #endif | |
545 | ||
546 | ||
b6930bdf NC |
547 | static void |
548 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 549 | char * str; |
b6930bdf | 550 | char * str2; |
c8cf7e17 | 551 | { |
b6930bdf NC |
552 | char * str3; |
553 | m32r_insn first; | |
554 | m32r_insn second; | |
555 | char * errmsg; | |
ebde3f62 | 556 | |
b6930bdf | 557 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 558 | |
b6930bdf NC |
559 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
560 | so that the parallel instruction will start on a 32 bit boundary. */ | |
561 | if (prev_insn.insn) | |
562 | fill_insn (0); | |
ebde3f62 | 563 | |
b6930bdf NC |
564 | /* Parse the first instruction. */ |
565 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
566 | (str, & first.fields, first.buffer, & errmsg))) | |
567 | { | |
568 | as_bad (errmsg); | |
569 | return; | |
570 | } | |
ebde3f62 | 571 | |
b6930bdf NC |
572 | /* Check to see if this is an allowable parallel insn. */ |
573 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
574 | { | |
575 | as_bad ("instruction '%s' cannot be executed in parallel.", str); | |
576 | return; | |
577 | } | |
ebde3f62 | 578 | |
b6930bdf NC |
579 | if (! enable_m32rx |
580 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
581 | { | |
582 | as_bad ("instruction '%s' is for the M32RX only", str); | |
583 | return; | |
ebde3f62 NC |
584 | } |
585 | ||
b6930bdf NC |
586 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
587 | str3 = str; /* Save the original string pointer. */ | |
588 | str = str2 + 2; /* Advanced past the parsed string. */ | |
589 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
590 | ||
591 | /* Preserve any fixups that have been generated and reset the list to empty. */ | |
592 | cgen_save_fixups(); | |
593 | ||
594 | /* Parse the second instruction. */ | |
595 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
596 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
597 | { |
598 | as_bad (errmsg); | |
599 | return; | |
600 | } | |
c8cf7e17 | 601 | |
b6930bdf NC |
602 | /* Check it. */ |
603 | if (! enable_m32rx | |
604 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
ebde3f62 NC |
605 | { |
606 | as_bad ("instruction '%s' is for the M32RX only", str); | |
607 | return; | |
608 | } | |
ebde3f62 | 609 | |
b6930bdf | 610 | if (! enable_m32rx) |
ebde3f62 | 611 | { |
b6930bdf NC |
612 | if ( strcmp (first.insn->name, "nop") != 0 |
613 | && strcmp (second.insn->name, "nop") != 0) | |
ebde3f62 | 614 | { |
b6930bdf NC |
615 | as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2); |
616 | return; | |
ebde3f62 | 617 | } |
b6930bdf | 618 | } |
9121b102 | 619 | |
b6930bdf NC |
620 | /* We assume that if the first instruction writes to a register that is |
621 | read by the second instruction it is because the programmer intended | |
622 | this to happen, (after all they have explicitly requested that these | |
623 | two instructions be executed in parallel). Similarly we assume that | |
624 | parallel branch and jump instructions are deliberate and should not | |
625 | produce errors. If warn_explicit_parallel is defined however, we do | |
626 | generate warning messages. */ | |
627 | ||
628 | if (can_make_parallel (& first, & second, false, false) == NULL) | |
629 | { | |
630 | /* Get the fixups for the first instruction. */ | |
631 | cgen_swap_fixups (); | |
632 | ||
633 | /* Write it out. */ | |
634 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
635 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
ebde3f62 | 636 | |
b6930bdf NC |
637 | /* Force the top bit of the second insn to be set. */ |
638 | make_parallel (second.buffer); | |
ebde3f62 | 639 | |
b6930bdf NC |
640 | /* Get its fixups. */ |
641 | cgen_restore_fixups (); | |
775fdd0c | 642 | |
b6930bdf NC |
643 | /* Write it out. */ |
644 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
645 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
646 | } | |
647 | else if ((errmsg = (char *) can_make_parallel (& second, & first, | |
648 | false, false)) == NULL) | |
649 | { | |
650 | /* Write out the second instruction first. */ | |
651 | (void) cgen_asm_finish_insn (second.insn, second.buffer, | |
652 | CGEN_FIELDS_BITSIZE (& second.fields)); | |
775fdd0c | 653 | |
b6930bdf NC |
654 | /* Force the top bit of the first instruction to be set. */ |
655 | make_parallel (first.buffer); | |
656 | ||
657 | /* Get the fixups for the first instruction. */ | |
658 | cgen_restore_fixups (); | |
659 | ||
660 | /* Write out the first instruction. */ | |
661 | (void) cgen_asm_finish_insn (first.insn, first.buffer, | |
662 | CGEN_FIELDS_BITSIZE (& first.fields)); | |
663 | } | |
664 | else | |
665 | { | |
666 | as_bad ("'%s': %s", str2, errmsg); | |
667 | return; | |
668 | } | |
ebde3f62 | 669 | |
b6930bdf NC |
670 | /* Set these so m32r_fill_insn can use them. */ |
671 | prev_seg = now_seg; | |
672 | prev_subseg = now_subseg; | |
673 | ||
674 | return; | |
675 | } | |
676 | /* end-sanitize-m32rx */ | |
677 | ||
678 | ||
679 | void | |
680 | md_assemble (str) | |
681 | char * str; | |
682 | { | |
683 | m32r_insn insn; | |
684 | char * errmsg; | |
685 | char * str2 = NULL; | |
686 | ||
687 | /* Initialize GAS's cgen interface for a new instruction. */ | |
688 | cgen_asm_init_parse (); | |
689 | ||
690 | /* start-sanitize-m32rx */ | |
691 | /* Look for a parallel instruction seperator. */ | |
692 | if ((str2 = strstr (str, "||")) != NULL) | |
693 | { | |
694 | assemble_parallel_insn (str, str2); | |
695 | return; | |
ebde3f62 | 696 | } |
b6930bdf NC |
697 | /* end-sanitize-m32rx */ |
698 | ||
699 | insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); | |
700 | if (!insn.insn) | |
701 | { | |
702 | as_bad (errmsg); | |
703 | return; | |
704 | } | |
705 | ||
706 | /* start-sanitize-m32rx */ | |
707 | if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
708 | { | |
709 | as_bad ("instruction '%s' is for the M32RX only", str); | |
710 | return; | |
711 | } | |
712 | /* end-sanitize-m32rx */ | |
713 | ||
714 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
715 | { |
716 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 717 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 NC |
718 | { |
719 | /* FIXME: If calling fill_insn too many times turns us into a memory | |
720 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ | |
721 | fill_insn (0); | |
722 | } | |
723 | ||
b6930bdf NC |
724 | (void) cgen_asm_finish_insn (insn.insn, insn.buffer, |
725 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
c8cf7e17 DE |
726 | } |
727 | else | |
728 | { | |
b6930bdf NC |
729 | /* start-sanitize-m32rx */ |
730 | /* start-sanitize-phase2-m32rx */ | |
731 | int swap = false; | |
732 | /* end-sanitize-phase2-m32rx */ | |
733 | /* end-sanitize-m32rx */ | |
734 | ||
735 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
736 | abort(); | |
737 | ||
c8cf7e17 | 738 | /* Keep track of whether we've seen a pair of 16 bit insns. |
b6930bdf NC |
739 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
740 | if (prev_insn.insn) | |
775fdd0c NC |
741 | { |
742 | /* start-sanitize-m32rx */ | |
b6930bdf NC |
743 | /* start-sanitize-phase2-m32rx */ |
744 | /* Look to see if this instruction can be combined with the | |
745 | previous instruction to make one, parallel, 32 bit instruction. | |
746 | If the previous instruction (potentially) changed the flow of | |
747 | program control, then it cannot be combined with the current | |
748 | instruction, otherwise call can_make_parallel() with both | |
749 | orderings of the instructions to see if they can be combined. */ | |
750 | if ( ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_COND_CTI) | |
751 | && ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_UNCOND_CTI)) | |
775fdd0c | 752 | { |
b6930bdf NC |
753 | if (can_make_parallel (& prev_insn, & insn, false, true) == NULL) |
754 | { | |
755 | make_parallel (insn.buffer); | |
756 | } | |
757 | else if (can_make_parallel (& insn, & prev_insn.insn, true, false) == NULL) | |
758 | { | |
759 | swap = true; | |
760 | } | |
775fdd0c | 761 | } |
b6930bdf | 762 | /* end-sanitize-phase2-m32rx */ |
775fdd0c NC |
763 | /* end-sanitize-m32rx */ |
764 | ||
b6930bdf | 765 | prev_insn.insn = NULL; |
775fdd0c | 766 | } |
c8cf7e17 | 767 | else |
775fdd0c | 768 | { |
b6930bdf | 769 | prev_insn = insn; |
775fdd0c | 770 | } |
c8cf7e17 | 771 | |
b6930bdf NC |
772 | /* Record the frag that might be used by this insn. */ |
773 | insn.frag = frag_now; | |
774 | insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer, | |
775 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
776 | ||
777 | /* start-sanitize-m32rx */ | |
778 | /* start-sanitize-phase2-m32rx */ | |
779 | if (swap) | |
780 | { | |
781 | int tmp; | |
782 | ||
783 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
784 | ||
785 | /* Swap the two insns */ | |
786 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
787 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
788 | ||
789 | make_parallel (insn.addr); | |
790 | ||
791 | /* Swap any relaxable frags recorded for the two insns. */ | |
792 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
793 | { | |
794 | prev_insn.frag->fr_opcode = insn.addr; | |
795 | } | |
796 | else if (insn.frag->fr_opcode == insn.addr) | |
797 | { | |
798 | insn.frag->fr_opcode = prev_insn.addr; | |
799 | } | |
800 | } | |
801 | /* end-sanitize-phase2-m32rx */ | |
802 | ||
803 | /* Record where this instruction was assembled. */ | |
804 | prev_insn.addr = insn.addr; | |
805 | prev_insn.frag = insn.frag; | |
806 | /* end-sanitize-m32rx */ | |
807 | ||
c8cf7e17 DE |
808 | /* If the insn needs the following one to be on a 32 bit boundary |
809 | (e.g. subroutine calls), fill this insn's slot. */ | |
b6930bdf NC |
810 | if (prev_insn.insn |
811 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0) | |
c8cf7e17 | 812 | fill_insn (0); |
c8cf7e17 | 813 | |
775fdd0c | 814 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
815 | mark the fact so that we can emit an alignment directive for a |
816 | following 32 bit insn if we see one. */ | |
817 | if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0) | |
775fdd0c NC |
818 | seen_relaxable_p = 1; |
819 | } | |
c8cf7e17 DE |
820 | |
821 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 822 | prev_seg = now_seg; |
c8cf7e17 DE |
823 | prev_subseg = now_subseg; |
824 | } | |
825 | ||
826 | /* The syntax in the manual says constants begin with '#'. | |
827 | We just ignore it. */ | |
828 | ||
829 | void | |
830 | md_operand (expressionP) | |
ebde3f62 | 831 | expressionS * expressionP; |
c8cf7e17 | 832 | { |
ebde3f62 | 833 | if (* input_line_pointer == '#') |
c8cf7e17 | 834 | { |
ebde3f62 | 835 | input_line_pointer ++; |
c8cf7e17 DE |
836 | expression (expressionP); |
837 | } | |
838 | } | |
839 | ||
840 | valueT | |
841 | md_section_align (segment, size) | |
ebde3f62 | 842 | segT segment; |
c8cf7e17 DE |
843 | valueT size; |
844 | { | |
845 | int align = bfd_get_section_alignment (stdoutput, segment); | |
846 | return ((size + (1 << align) - 1) & (-1 << align)); | |
847 | } | |
848 | ||
849 | symbolS * | |
850 | md_undefined_symbol (name) | |
ebde3f62 | 851 | char * name; |
c8cf7e17 DE |
852 | { |
853 | return 0; | |
854 | } | |
855 | \f | |
856 | /* .scomm pseudo-op handler. | |
857 | ||
858 | This is a new pseudo-op to handle putting objects in .scommon. | |
859 | By doing this the linker won't need to do any work and more importantly | |
860 | it removes the implicit -G arg necessary to correctly link the object file. | |
861 | */ | |
862 | ||
863 | static void | |
864 | m32r_scomm (ignore) | |
865 | int ignore; | |
866 | { | |
ebde3f62 NC |
867 | register char * name; |
868 | register char c; | |
869 | register char * p; | |
870 | offsetT size; | |
871 | register symbolS * symbolP; | |
872 | offsetT align; | |
873 | int align2; | |
c8cf7e17 DE |
874 | |
875 | name = input_line_pointer; | |
876 | c = get_symbol_end (); | |
877 | ||
878 | /* just after name is now '\0' */ | |
879 | p = input_line_pointer; | |
ebde3f62 | 880 | * p = c; |
c8cf7e17 | 881 | SKIP_WHITESPACE (); |
ebde3f62 | 882 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
883 | { |
884 | as_bad ("Expected comma after symbol-name: rest of line ignored."); | |
885 | ignore_rest_of_line (); | |
886 | return; | |
887 | } | |
888 | ||
b6930bdf | 889 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
890 | if ((size = get_absolute_expression ()) < 0) |
891 | { | |
892 | as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size); | |
893 | ignore_rest_of_line (); | |
894 | return; | |
895 | } | |
896 | ||
897 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 898 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
899 | align = 8; |
900 | else | |
901 | { | |
ebde3f62 | 902 | ++ input_line_pointer; |
c8cf7e17 DE |
903 | align = get_absolute_expression (); |
904 | if (align <= 0) | |
905 | { | |
906 | as_warn ("ignoring bad alignment"); | |
907 | align = 8; | |
908 | } | |
909 | } | |
910 | /* Convert to a power of 2 alignment. */ | |
911 | if (align) | |
912 | { | |
ebde3f62 | 913 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
914 | continue; |
915 | if (align != 1) | |
916 | { | |
917 | as_bad ("Common alignment not a power of 2"); | |
918 | ignore_rest_of_line (); | |
919 | return; | |
920 | } | |
921 | } | |
922 | else | |
923 | align2 = 0; | |
924 | ||
ebde3f62 | 925 | * p = 0; |
c8cf7e17 | 926 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 927 | * p = c; |
c8cf7e17 DE |
928 | |
929 | if (S_IS_DEFINED (symbolP)) | |
930 | { | |
931 | as_bad ("Ignoring attempt to re-define symbol `%s'.", | |
932 | S_GET_NAME (symbolP)); | |
933 | ignore_rest_of_line (); | |
934 | return; | |
935 | } | |
936 | ||
937 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
938 | { | |
939 | as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.", | |
940 | S_GET_NAME (symbolP), | |
941 | (long) S_GET_VALUE (symbolP), | |
942 | (long) size); | |
943 | ||
944 | ignore_rest_of_line (); | |
945 | return; | |
946 | } | |
947 | ||
948 | if (symbolP->local) | |
949 | { | |
ebde3f62 NC |
950 | segT old_sec = now_seg; |
951 | int old_subsec = now_subseg; | |
952 | char * pfrag; | |
c8cf7e17 DE |
953 | |
954 | record_alignment (sbss_section, align2); | |
955 | subseg_set (sbss_section, 0); | |
775fdd0c | 956 | |
c8cf7e17 DE |
957 | if (align2) |
958 | frag_align (align2, 0, 0); | |
775fdd0c | 959 | |
c8cf7e17 DE |
960 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
961 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 962 | |
c8cf7e17 | 963 | symbolP->sy_frag = frag_now; |
b6930bdf | 964 | |
c8cf7e17 DE |
965 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
966 | (char *) 0); | |
ebde3f62 | 967 | * pfrag = 0; |
c8cf7e17 DE |
968 | S_SET_SIZE (symbolP, size); |
969 | S_SET_SEGMENT (symbolP, sbss_section); | |
970 | S_CLEAR_EXTERNAL (symbolP); | |
971 | subseg_set (old_sec, old_subsec); | |
972 | } | |
973 | else | |
974 | { | |
975 | S_SET_VALUE (symbolP, (valueT) size); | |
976 | S_SET_ALIGN (symbolP, align2); | |
977 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 978 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
979 | } |
980 | ||
981 | demand_empty_rest_of_line (); | |
982 | } | |
983 | \f | |
984 | /* Interface to relax_segment. */ | |
985 | ||
986 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
987 | ||
988 | const relax_typeS md_relax_table[] = | |
989 | { | |
990 | /* The fields are: | |
991 | 1) most positive reach of this state, | |
992 | 2) most negative reach of this state, | |
993 | 3) how many bytes this mode will add to the size of the current frag | |
994 | 4) which index into the table to try if we can't fit into this one. */ | |
995 | ||
996 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
997 | each list. */ | |
998 | {1, 1, 0, 0}, | |
999 | ||
1000 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1001 | so we subtract 2 from the following. */ | |
1002 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1003 | This doesn't handle a branch in the right slot at the border: | |
1004 | the "& -4" isn't taken into account. It's not important enough to | |
1005 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1006 | case). */ | |
1007 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1008 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1009 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1010 | /* Same thing, but with leading nop for alignment. */ | |
1011 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1012 | }; | |
1013 | ||
1014 | long | |
1015 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1016 | fragS * fragP; |
1017 | long stretch; | |
c8cf7e17 DE |
1018 | { |
1019 | /* Address of branch insn. */ | |
1020 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1021 | long growth = 0; | |
1022 | ||
1023 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1024 | if (fragP->fr_subtype == 2) | |
1025 | { | |
1026 | if ((address & 3) != 0) | |
1027 | { | |
1028 | fragP->fr_subtype = 3; | |
1029 | growth = 2; | |
1030 | } | |
1031 | } | |
1032 | else if (fragP->fr_subtype == 3) | |
1033 | { | |
1034 | if ((address & 3) == 0) | |
1035 | { | |
1036 | fragP->fr_subtype = 2; | |
1037 | growth = -2; | |
1038 | } | |
1039 | } | |
1040 | else | |
1041 | { | |
1042 | growth = relax_frag (fragP, stretch); | |
1043 | ||
1044 | /* Long jump on odd halfword boundary? */ | |
1045 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1046 | { | |
1047 | fragP->fr_subtype = 3; | |
1048 | growth += 2; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | return growth; | |
1053 | } | |
1054 | ||
1055 | /* Return an initial guess of the length by which a fragment must grow to | |
1056 | hold a branch to reach its destination. | |
1057 | Also updates fr_type/fr_subtype as necessary. | |
1058 | ||
1059 | Called just before doing relaxation. | |
1060 | Any symbol that is now undefined will not become defined. | |
1061 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1062 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1063 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1064 | 0 value. */ | |
1065 | ||
1066 | int | |
1067 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1068 | fragS * fragP; |
1069 | segT segment; | |
c8cf7e17 | 1070 | { |
ebde3f62 NC |
1071 | int old_fr_fix = fragP->fr_fix; |
1072 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1073 | |
1074 | /* The only thing we have to handle here are symbols outside of the | |
1075 | current segment. They may be undefined or in a different segment in | |
1076 | which case linker scripts may place them anywhere. | |
1077 | However, we can't finish the fragment here and emit the reloc as insn | |
1078 | alignment requirements may move the insn about. */ | |
1079 | ||
1080 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1081 | { | |
1082 | /* The symbol is undefined in this segment. | |
1083 | Change the relaxation subtype to the max allowable and leave | |
1084 | all further handling to md_convert_frag. */ | |
1085 | fragP->fr_subtype = 2; | |
1086 | ||
1087 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1088 | /* Change 16 bit insn to 32 bit insn. */ | |
1089 | opcode[0] |= 0x80; | |
1090 | ||
1091 | /* Increase known (fixed) size of fragment. */ | |
1092 | fragP->fr_fix += 2; | |
1093 | ||
1094 | /* Create a relocation for it. */ | |
1095 | fix_new (fragP, old_fr_fix, 4, | |
1096 | fragP->fr_symbol, | |
1097 | fragP->fr_offset, 1 /* pcrel */, | |
1098 | /* FIXME: Can't use a real BFD reloc here. | |
1099 | cgen_md_apply_fix3 can't handle it. */ | |
1100 | BFD_RELOC_M32R_26_PCREL); | |
1101 | ||
1102 | /* Mark this fragment as finished. */ | |
1103 | frag_wane (fragP); | |
1104 | #else | |
a450e9f4 | 1105 | { |
ebde3f62 NC |
1106 | const CGEN_INSN * insn; |
1107 | int i; | |
a450e9f4 NC |
1108 | |
1109 | /* Update the recorded insn. | |
1110 | Fortunately we don't have to look very far. | |
1111 | FIXME: Change this to record in the instruction the next higher | |
1112 | relaxable insn to use. */ | |
1113 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1114 | { | |
b5e9e562 DE |
1115 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1116 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1117 | == 0) |
1118 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1119 | break; | |
1120 | } | |
1121 | if (i == 4) | |
1122 | abort (); | |
b6930bdf | 1123 | |
a450e9f4 NC |
1124 | fragP->fr_cgen.insn = insn; |
1125 | return 2; | |
1126 | } | |
c8cf7e17 DE |
1127 | #endif |
1128 | } | |
1129 | ||
1130 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1131 | } | |
1132 | ||
1133 | /* *fragP has been relaxed to its final size, and now needs to have | |
1134 | the bytes inside it modified to conform to the new size. | |
1135 | ||
1136 | Called after relaxation is finished. | |
1137 | fragP->fr_type == rs_machine_dependent. | |
1138 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1139 | ||
1140 | void | |
1141 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1142 | bfd * abfd; |
1143 | segT sec; | |
1144 | fragS * fragP; | |
c8cf7e17 | 1145 | { |
ebde3f62 NC |
1146 | char * opcode; |
1147 | char * displacement; | |
1148 | int target_address; | |
1149 | int opcode_address; | |
1150 | int extension; | |
1151 | int addend; | |
c8cf7e17 DE |
1152 | |
1153 | opcode = fragP->fr_opcode; | |
1154 | ||
1155 | /* Address opcode resides at in file space. */ | |
1156 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1157 | ||
1158 | switch (fragP->fr_subtype) | |
1159 | { | |
1160 | case 1 : | |
1161 | extension = 0; | |
ebde3f62 | 1162 | displacement = & opcode[1]; |
c8cf7e17 DE |
1163 | break; |
1164 | case 2 : | |
1165 | opcode[0] |= 0x80; | |
1166 | extension = 2; | |
ebde3f62 | 1167 | displacement = & opcode[1]; |
c8cf7e17 DE |
1168 | break; |
1169 | case 3 : | |
1170 | opcode[2] = opcode[0] | 0x80; | |
1171 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1172 | opcode_address += 2; | |
1173 | extension = 4; | |
ebde3f62 | 1174 | displacement = & opcode[3]; |
c8cf7e17 DE |
1175 | break; |
1176 | default : | |
1177 | abort (); | |
1178 | } | |
1179 | ||
1180 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1181 | { | |
1182 | /* symbol must be resolved by linker */ | |
1183 | if (fragP->fr_offset & 3) | |
1184 | as_warn ("Addend to unresolved symbol not on word boundary."); | |
1185 | addend = fragP->fr_offset >> 2; | |
1186 | } | |
1187 | else | |
1188 | { | |
1189 | /* Address we want to reach in file space. */ | |
1190 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1191 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1192 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1193 | } | |
1194 | ||
1195 | /* Create a relocation for symbols that must be resolved by the linker. | |
1196 | Otherwise output the completed insn. */ | |
1197 | ||
1198 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1199 | { | |
1200 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1201 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1202 | cgen_record_fixup (fragP, |
1203 | /* Offset of branch insn in frag. */ | |
1204 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1205 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1206 | 4 /*length*/, |
1207 | /* FIXME: quick hack */ | |
1208 | #if 0 | |
a450e9f4 | 1209 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1210 | #else |
1211 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1212 | #endif | |
a450e9f4 | 1213 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1214 | fragP->fr_symbol, fragP->fr_offset); |
1215 | } | |
1216 | ||
1217 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1218 | ||
1219 | md_number_to_chars (displacement, (valueT) addend, | |
1220 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1221 | ||
1222 | fragP->fr_fix += extension; | |
1223 | } | |
1224 | \f | |
1225 | /* Functions concerning relocs. */ | |
1226 | ||
1227 | /* The location from which a PC relative jump should be calculated, | |
1228 | given a PC relative reloc. */ | |
1229 | ||
1230 | long | |
1231 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1232 | fixS * fixP; |
1233 | segT sec; | |
c8cf7e17 DE |
1234 | { |
1235 | if (fixP->fx_addsy != (symbolS *) NULL | |
1236 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1237 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1238 | { | |
1239 | /* The symbol is undefined (or is defined but not in this section). | |
1240 | Let the linker figure it out. */ | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1245 | } | |
1246 | ||
1247 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1248 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1249 | *FIXP may be modified if desired. */ | |
1250 | ||
1251 | bfd_reloc_code_real_type | |
1252 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1253 | const CGEN_INSN * insn; |
1254 | const CGEN_OPERAND * operand; | |
1255 | fixS * fixP; | |
c8cf7e17 DE |
1256 | { |
1257 | switch (CGEN_OPERAND_TYPE (operand)) | |
1258 | { | |
1259 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1260 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1261 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1262 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1263 | case M32R_OPERAND_HI16 : | |
1264 | case M32R_OPERAND_SLO16 : | |
1265 | case M32R_OPERAND_ULO16 : | |
1266 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1267 | if (fixP->tc_fix_data.opinfo != 0) | |
1268 | return fixP->tc_fix_data.opinfo; | |
1269 | break; | |
1270 | } | |
1271 | return BFD_RELOC_NONE; | |
1272 | } | |
1273 | ||
b6930bdf NC |
1274 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1275 | ||
1276 | static void | |
1277 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1278 | int reloc_type; | |
1279 | fixS * fixP; | |
1280 | segT seg; | |
1281 | { | |
1282 | struct m32r_hi_fixup * hi_fixup; | |
1283 | ||
1284 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1285 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1286 | ||
1287 | hi_fixup = ((struct m32r_hi_fixup *) | |
1288 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1289 | hi_fixup->fixp = fixP; | |
1290 | hi_fixup->seg = now_seg; | |
1291 | hi_fixup->next = m32r_hi_fixup_list; | |
1292 | ||
1293 | m32r_hi_fixup_list = hi_fixup; | |
1294 | } | |
1295 | ||
c8cf7e17 DE |
1296 | /* Called while parsing an instruction to create a fixup. |
1297 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1298 | ||
1299 | fixS * | |
1300 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1301 | fragS * frag; |
1302 | int where; | |
1303 | const CGEN_INSN * insn; | |
1304 | int length; | |
1305 | const CGEN_OPERAND * operand; | |
1306 | int opinfo; | |
1307 | expressionS * exp; | |
c8cf7e17 | 1308 | { |
ebde3f62 NC |
1309 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1310 | operand, opinfo, exp); | |
c8cf7e17 DE |
1311 | |
1312 | switch (CGEN_OPERAND_TYPE (operand)) | |
1313 | { | |
1314 | case M32R_OPERAND_HI16 : | |
1315 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1316 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1317 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1318 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1319 | break; | |
1320 | } | |
1321 | ||
1322 | return fixP; | |
1323 | } | |
1324 | ||
c8cf7e17 DE |
1325 | /* Return BFD reloc type from opinfo field in a fixS. |
1326 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1327 | are BFD_RELOC_UNUSED + operand number. */ | |
1328 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1329 | ||
1330 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1331 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1332 | tc_gen_reloc. */ | |
1333 | ||
1334 | void | |
1335 | m32r_frob_file () | |
1336 | { | |
ebde3f62 | 1337 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1338 | |
1339 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1340 | { | |
ebde3f62 NC |
1341 | segment_info_type * seginfo; |
1342 | int pass; | |
c8cf7e17 DE |
1343 | |
1344 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1345 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1346 | ||
1347 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1348 | if (l->fixp->fx_next != NULL | |
1349 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1350 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1351 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1352 | continue; | |
1353 | ||
1354 | /* Look through the fixups for this segment for a matching `low'. | |
1355 | When we find one, move the high/shigh just in front of it. We do | |
1356 | this in two passes. In the first pass, we try to find a | |
1357 | unique `low'. In the second pass, we permit multiple high's | |
1358 | relocs for a single `low'. */ | |
1359 | seginfo = seg_info (l->seg); | |
1360 | for (pass = 0; pass < 2; pass++) | |
1361 | { | |
ebde3f62 NC |
1362 | fixS * f; |
1363 | fixS * prev; | |
c8cf7e17 DE |
1364 | |
1365 | prev = NULL; | |
1366 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1367 | { | |
1368 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1369 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1370 | && f->fx_addsy == l->fixp->fx_addsy | |
1371 | && f->fx_offset == l->fixp->fx_offset | |
1372 | && (pass == 1 | |
1373 | || prev == NULL | |
1374 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1375 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1376 | || prev->fx_addsy != f->fx_addsy | |
1377 | || prev->fx_offset != f->fx_offset)) | |
1378 | { | |
ebde3f62 | 1379 | fixS ** pf; |
c8cf7e17 DE |
1380 | |
1381 | /* Move l->fixp before f. */ | |
1382 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1383 | * pf != l->fixp; |
1384 | pf = & (* pf)->fx_next) | |
1385 | assert (* pf != NULL); | |
c8cf7e17 | 1386 | |
ebde3f62 | 1387 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1388 | |
1389 | l->fixp->fx_next = f; | |
1390 | if (prev == NULL) | |
1391 | seginfo->fix_root = l->fixp; | |
1392 | else | |
1393 | prev->fx_next = l->fixp; | |
1394 | ||
1395 | break; | |
1396 | } | |
1397 | ||
1398 | prev = f; | |
1399 | } | |
1400 | ||
1401 | if (f != NULL) | |
1402 | break; | |
1403 | ||
1404 | if (pass == 1) | |
1405 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1406 | "Unmatched high/shigh reloc"); | |
1407 | } | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | /* See whether we need to force a relocation into the output file. | |
1412 | This is used to force out switch and PC relative relocations when | |
1413 | relaxing. */ | |
1414 | ||
1415 | int | |
1416 | m32r_force_relocation (fix) | |
ebde3f62 | 1417 | fixS * fix; |
c8cf7e17 DE |
1418 | { |
1419 | if (! m32r_relax) | |
1420 | return 0; | |
1421 | ||
1422 | return (fix->fx_pcrel | |
1423 | || 0 /* ??? */); | |
1424 | } | |
1425 | \f | |
1426 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1427 | ||
1428 | void | |
1429 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1430 | char * buf; |
c8cf7e17 | 1431 | valueT val; |
ebde3f62 | 1432 | int n; |
c8cf7e17 DE |
1433 | { |
1434 | if (target_big_endian) | |
1435 | number_to_chars_bigendian (buf, val, n); | |
1436 | else | |
1437 | number_to_chars_littleendian (buf, val, n); | |
1438 | } | |
1439 | ||
1440 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1441 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1442 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1443 | */ | |
1444 | ||
1445 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1446 | #define MAX_LITTLENUMS 6 | |
1447 | ||
1448 | char * | |
1449 | md_atof (type, litP, sizeP) | |
1450 | char type; | |
1451 | char *litP; | |
1452 | int *sizeP; | |
1453 | { | |
ebde3f62 NC |
1454 | int i; |
1455 | int prec; | |
1456 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1457 | LITTLENUM_TYPE * wordP; | |
1458 | char * t; | |
1459 | char * atof_ieee (); | |
c8cf7e17 DE |
1460 | |
1461 | switch (type) | |
1462 | { | |
1463 | case 'f': | |
1464 | case 'F': | |
1465 | case 's': | |
1466 | case 'S': | |
1467 | prec = 2; | |
1468 | break; | |
1469 | ||
1470 | case 'd': | |
1471 | case 'D': | |
1472 | case 'r': | |
1473 | case 'R': | |
1474 | prec = 4; | |
1475 | break; | |
1476 | ||
1477 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1478 | ||
1479 | default: | |
ebde3f62 | 1480 | * sizeP = 0; |
c8cf7e17 DE |
1481 | return "Bad call to md_atof()"; |
1482 | } | |
1483 | ||
1484 | t = atof_ieee (input_line_pointer, type, words); | |
1485 | if (t) | |
1486 | input_line_pointer = t; | |
ebde3f62 | 1487 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1488 | |
1489 | if (target_big_endian) | |
1490 | { | |
1491 | for (i = 0; i < prec; i++) | |
1492 | { | |
ebde3f62 NC |
1493 | md_number_to_chars (litP, (valueT) words[i], |
1494 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1495 | litP += sizeof (LITTLENUM_TYPE); |
1496 | } | |
1497 | } | |
1498 | else | |
1499 | { | |
1500 | for (i = prec - 1; i >= 0; i--) | |
1501 | { | |
ebde3f62 NC |
1502 | md_number_to_chars (litP, (valueT) words[i], |
1503 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1504 | litP += sizeof (LITTLENUM_TYPE); |
1505 | } | |
1506 | } | |
1507 | ||
1508 | return 0; | |
1509 | } |