Commit | Line | Data |
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76090fdd | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
9121b102 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation. |
c8cf7e17 DE |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
a15a45e5 | 25 | #include "symcat.h" |
c8cf7e17 DE |
26 | #include "cgen-opc.h" |
27 | ||
b86c0dd3 | 28 | /* Structure to hold all of the different components describing an individual instruction. */ |
b6930bdf NC |
29 | typedef struct |
30 | { | |
31 | const CGEN_INSN * insn; | |
a15a45e5 | 32 | const CGEN_INSN * orig_insn; |
b6930bdf NC |
33 | CGEN_FIELDS fields; |
34 | #ifdef CGEN_INT_INSN | |
35 | cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)]; | |
36 | #else | |
37 | char buffer [CGEN_MAX_INSN_SIZE]; | |
38 | #endif | |
39 | char * addr; | |
40 | fragS * frag; | |
6cf2575a | 41 | int indices [MAX_OPERAND_INSTANCES]; |
b6930bdf NC |
42 | } |
43 | m32r_insn; | |
44 | ||
45 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
46 | boundary (i.e. was the first of two 16 bit insns). */ | |
47 | static m32r_insn prev_insn; | |
c8cf7e17 DE |
48 | |
49 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
50 | alignment request. */ | |
51 | static int seen_relaxable_p = 0; | |
52 | ||
53 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
54 | for the linker to do relaxing. | |
55 | We do simple forms of relaxing internally, but they are always done. | |
56 | This flag does not apply to them. */ | |
57 | static int m32r_relax; | |
58 | ||
59 | /* If non-NULL, pointer to cpu description file to read. | |
60 | This allows runtime additions to the assembler. */ | |
ebde3f62 | 61 | static char * m32r_cpu_desc; |
c8cf7e17 | 62 | |
b5e9e562 | 63 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
64 | /* Non-zero if -m32rx has been specified, in which case support for the |
65 | extended M32RX instruction set should be enabled. */ | |
a450e9f4 | 66 | static int enable_m32rx = 0; |
b6930bdf NC |
67 | |
68 | /* Non-zero if the programmer should be warned when an explicit parallel | |
69 | instruction might have constraint violations. */ | |
70 | static int warn_explicit_parallel_conflicts = 1; | |
b5e9e562 | 71 | /* end-sanitize-m32rx */ |
a450e9f4 | 72 | |
c8cf7e17 | 73 | /* stuff for .scomm symbols. */ |
ebde3f62 | 74 | static segT sbss_section; |
c8cf7e17 | 75 | static asection scom_section; |
ebde3f62 | 76 | static asymbol scom_symbol; |
c8cf7e17 | 77 | |
ebde3f62 NC |
78 | const char comment_chars[] = ";"; |
79 | const char line_comment_chars[] = "#"; | |
c8cf7e17 | 80 | const char line_separator_chars[] = ""; |
ebde3f62 NC |
81 | const char EXP_CHARS[] = "eE"; |
82 | const char FLT_CHARS[] = "dD"; | |
c8cf7e17 DE |
83 | |
84 | /* Relocations against symbols are done in two | |
85 | parts, with a HI relocation and a LO relocation. Each relocation | |
86 | has only 16 bits of space to store an addend. This means that in | |
87 | order for the linker to handle carries correctly, it must be able | |
88 | to locate both the HI and the LO relocation. This means that the | |
89 | relocations must appear in order in the relocation table. | |
90 | ||
91 | In order to implement this, we keep track of each unmatched HI | |
92 | relocation. We then sort them so that they immediately precede the | |
93 | corresponding LO relocation. */ | |
94 | ||
95 | struct m32r_hi_fixup | |
96 | { | |
ebde3f62 NC |
97 | struct m32r_hi_fixup * next; /* Next HI fixup. */ |
98 | fixS * fixp; /* This fixup. */ | |
99 | segT seg; /* The section this fixup is in. */ | |
100 | ||
c8cf7e17 DE |
101 | }; |
102 | ||
103 | /* The list of unmatched HI relocs. */ | |
104 | ||
ebde3f62 | 105 | static struct m32r_hi_fixup * m32r_hi_fixup_list; |
c8cf7e17 | 106 | |
a450e9f4 | 107 | \f |
b5e9e562 | 108 | /* start-sanitize-m32rx */ |
a450e9f4 | 109 | static void |
55a4759f DE |
110 | allow_m32rx (on) |
111 | int on; | |
a450e9f4 NC |
112 | { |
113 | enable_m32rx = on; | |
114 | ||
115 | if (stdoutput != NULL) | |
ebde3f62 NC |
116 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
117 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
a450e9f4 | 118 | } |
b5e9e562 | 119 | /* end-sanitize-m32rx */ |
c8cf7e17 | 120 | \f |
ebde3f62 | 121 | const char * md_shortopts = ""; |
c8cf7e17 | 122 | |
a450e9f4 NC |
123 | struct option md_longopts[] = |
124 | { | |
b5e9e562 | 125 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
126 | #define OPTION_M32RX (OPTION_MD_BASE) |
127 | {"m32rx", no_argument, NULL, OPTION_M32RX}, | |
b6930bdf NC |
128 | #define OPTION_WARN (OPTION_MD_BASE + 1) |
129 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN}, | |
a15a45e5 | 130 | {"Wp", no_argument, NULL, OPTION_WARN}, |
b6930bdf NC |
131 | #define OPTION_NO_WARN (OPTION_MD_BASE + 2) |
132 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, | |
a15a45e5 | 133 | {"Wnp", no_argument, NULL, OPTION_NO_WARN}, |
b5e9e562 | 134 | /* end-sanitize-m32rx */ |
a450e9f4 | 135 | |
c8cf7e17 | 136 | #if 0 /* not supported yet */ |
b6930bdf | 137 | #define OPTION_RELAX (OPTION_MD_BASE + 3) |
c8cf7e17 | 138 | {"relax", no_argument, NULL, OPTION_RELAX}, |
b6930bdf | 139 | #define OPTION_CPU_DESC (OPTION_MD_BASE + 4) |
c8cf7e17 DE |
140 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
141 | #endif | |
a450e9f4 | 142 | |
c8cf7e17 DE |
143 | {NULL, no_argument, NULL, 0} |
144 | }; | |
ebde3f62 | 145 | size_t md_longopts_size = sizeof (md_longopts); |
c8cf7e17 DE |
146 | |
147 | int | |
148 | md_parse_option (c, arg) | |
ebde3f62 NC |
149 | int c; |
150 | char * arg; | |
c8cf7e17 DE |
151 | { |
152 | switch (c) | |
153 | { | |
b5e9e562 | 154 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
155 | case OPTION_M32RX: |
156 | allow_m32rx (1); | |
157 | break; | |
b6930bdf NC |
158 | |
159 | case OPTION_WARN: | |
160 | warn_explicit_parallel_conflicts = 1; | |
161 | break; | |
162 | ||
163 | case OPTION_NO_WARN: | |
164 | warn_explicit_parallel_conflicts = 0; | |
165 | break; | |
b5e9e562 | 166 | /* end-sanitize-m32rx */ |
a450e9f4 | 167 | |
c8cf7e17 DE |
168 | #if 0 /* not supported yet */ |
169 | case OPTION_RELAX: | |
170 | m32r_relax = 1; | |
171 | break; | |
172 | case OPTION_CPU_DESC: | |
173 | m32r_cpu_desc = arg; | |
174 | break; | |
175 | #endif | |
176 | default: | |
177 | return 0; | |
178 | } | |
179 | return 1; | |
180 | } | |
181 | ||
182 | void | |
183 | md_show_usage (stream) | |
ebde3f62 | 184 | FILE * stream; |
c8cf7e17 | 185 | { |
a450e9f4 | 186 | fprintf (stream, "M32R/X options:\n"); |
b5e9e562 | 187 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
188 | fprintf (stream, "\ |
189 | --m32rx support the extended m32rx instruction set\n"); | |
b6930bdf NC |
190 | |
191 | fprintf (stream, "\ | |
00aa5b17 DE |
192 | --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n"); |
193 | fprintf (stream, "\ | |
b6930bdf | 194 | --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n"); |
a15a45e5 DE |
195 | fprintf (stream, "\ |
196 | --Wp Synonym for --warn-explicit-parallel-conflicts\n"); | |
197 | fprintf (stream, "\ | |
198 | --Wnp Synonym for --no-warn-explicit-parallel-conflicts\n"); | |
b5e9e562 | 199 | /* end-sanitize-m32rx */ |
a450e9f4 | 200 | |
c8cf7e17 DE |
201 | #if 0 |
202 | fprintf (stream, "\ | |
203 | --relax create linker relaxable code\n"); | |
204 | fprintf (stream, "\ | |
205 | --cpu-desc provide runtime cpu description file\n"); | |
c8cf7e17 DE |
206 | #endif |
207 | } | |
208 | ||
209 | static void fill_insn PARAMS ((int)); | |
210 | static void m32r_scomm PARAMS ((int)); | |
211 | ||
212 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
213 | static subsegT prev_subseg; | |
214 | static segT prev_seg; | |
215 | ||
216 | /* The target specific pseudo-ops which we support. */ | |
217 | const pseudo_typeS md_pseudo_table[] = | |
218 | { | |
219 | { "word", cons, 4 }, | |
220 | { "fillinsn", fill_insn, 0 }, | |
221 | { "scomm", m32r_scomm, 0 }, | |
b5e9e562 | 222 | /* start-sanitize-m32rx */ |
a450e9f4 NC |
223 | { "m32r", allow_m32rx, 0}, |
224 | { "m32rx", allow_m32rx, 1}, | |
b5e9e562 | 225 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
226 | { NULL, NULL, 0 } |
227 | }; | |
228 | ||
229 | /* FIXME: Should be machine generated. */ | |
230 | #define NOP_INSN 0x7000 | |
231 | #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ | |
232 | ||
233 | /* When we align the .text section, insert the correct NOP pattern. | |
234 | N is the power of 2 alignment. LEN is the length of pattern FILL. | |
235 | MAX is the maximum number of characters to skip when doing the alignment, | |
236 | or 0 if there is no maximum. */ | |
237 | ||
238 | int | |
239 | m32r_do_align (n, fill, len, max) | |
ebde3f62 NC |
240 | int n; |
241 | const char * fill; | |
242 | int len; | |
243 | int max; | |
c8cf7e17 | 244 | { |
ebde3f62 | 245 | if ((fill == NULL || (* fill == 0 && len == 1)) |
c8cf7e17 DE |
246 | && (now_seg->flags & SEC_CODE) != 0 |
247 | /* Only do this special handling if aligning to at least a | |
248 | 4 byte boundary. */ | |
249 | && n > 1 | |
775fdd0c | 250 | /* Only do this special handling if we're allowed to emit at |
c8cf7e17 DE |
251 | least two bytes. */ |
252 | && (max == 0 || max > 1)) | |
253 | { | |
254 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; | |
255 | ||
256 | #if 0 | |
257 | /* First align to a 2 byte boundary, in case there is an odd .byte. */ | |
258 | /* FIXME: How much memory will cause gas to use when assembling a big | |
259 | program? Perhaps we can avoid the frag_align call? */ | |
260 | frag_align (1, 0, 0); | |
261 | #endif | |
262 | /* Next align to a 4 byte boundary (we know n >= 2) using a parallel | |
263 | nop. */ | |
264 | frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); | |
265 | /* If doing larger alignments use a repeating sequence of appropriate | |
266 | nops. */ | |
267 | if (n > 2) | |
268 | { | |
ebde3f62 NC |
269 | static const unsigned char multi_nop_pattern[] = |
270 | { 0x70, 0x00, 0xf0, 0x00 }; | |
c8cf7e17 DE |
271 | frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, |
272 | max ? max - 2 : 0); | |
273 | } | |
274 | return 1; | |
275 | } | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static void | |
281 | assemble_nop (opcode) | |
282 | int opcode; | |
283 | { | |
ebde3f62 | 284 | char * f = frag_more (2); |
c8cf7e17 DE |
285 | md_number_to_chars (f, opcode, 2); |
286 | } | |
287 | ||
288 | /* If the last instruction was the first of 2 16 bit insns, | |
289 | output a nop to move the PC to a 32 bit boundary. | |
290 | ||
291 | This is done via an alignment specification since branch relaxing | |
292 | may make it unnecessary. | |
293 | ||
294 | Internally, we need to output one of these each time a 32 bit insn is | |
295 | seen after an insn that is relaxable. */ | |
296 | ||
297 | static void | |
298 | fill_insn (ignore) | |
299 | int ignore; | |
300 | { | |
301 | (void) m32r_do_align (2, NULL, 0, 0); | |
b6930bdf | 302 | prev_insn.insn = NULL; |
c8cf7e17 DE |
303 | seen_relaxable_p = 0; |
304 | } | |
305 | ||
306 | /* Cover function to fill_insn called after a label and at end of assembly. | |
307 | ||
308 | The result is always 1: we're called in a conditional to see if the | |
309 | current line is a label. */ | |
310 | ||
311 | int | |
312 | m32r_fill_insn (done) | |
313 | int done; | |
314 | { | |
ebde3f62 | 315 | segT seg; |
c8cf7e17 DE |
316 | subsegT subseg; |
317 | ||
318 | if (prev_seg != NULL) | |
319 | { | |
ebde3f62 | 320 | seg = now_seg; |
c8cf7e17 | 321 | subseg = now_subseg; |
ebde3f62 | 322 | |
c8cf7e17 | 323 | subseg_set (prev_seg, prev_subseg); |
ebde3f62 | 324 | |
c8cf7e17 | 325 | fill_insn (0); |
ebde3f62 | 326 | |
c8cf7e17 DE |
327 | subseg_set (seg, subseg); |
328 | } | |
ebde3f62 | 329 | |
c8cf7e17 DE |
330 | return 1; |
331 | } | |
332 | \f | |
333 | void | |
334 | md_begin () | |
335 | { | |
336 | flagword applicable; | |
ebde3f62 NC |
337 | segT seg; |
338 | subsegT subseg; | |
c8cf7e17 DE |
339 | |
340 | /* Initialize the `cgen' interface. */ | |
4e9d8dea DE |
341 | |
342 | /* This is a callback from cgen to gas to parse operands. */ | |
a450e9f4 | 343 | cgen_parse_operand_fn = cgen_parse_operand; |
ebde3f62 | 344 | |
4e9d8dea | 345 | /* Set the machine number and endian. */ |
c8cf7e17 | 346 | CGEN_SYM (init_asm) (0 /* mach number */, |
ebde3f62 NC |
347 | target_big_endian ? |
348 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
c8cf7e17 DE |
349 | |
350 | #if 0 /* not supported yet */ | |
351 | /* If a runtime cpu description file was provided, parse it. */ | |
352 | if (m32r_cpu_desc != NULL) | |
353 | { | |
ebde3f62 | 354 | const char * errmsg; |
c8cf7e17 DE |
355 | |
356 | errmsg = cgen_read_cpu_file (m32r_cpu_desc); | |
357 | if (errmsg != NULL) | |
358 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
359 | } | |
360 | #endif | |
361 | ||
362 | /* Save the current subseg so we can restore it [it's the default one and | |
ebde3f62 NC |
363 | we don't want the initial section to be .sbss]. */ |
364 | seg = now_seg; | |
c8cf7e17 DE |
365 | subseg = now_subseg; |
366 | ||
367 | /* The sbss section is for local .scomm symbols. */ | |
368 | sbss_section = subseg_new (".sbss", 0); | |
ebde3f62 | 369 | |
c8cf7e17 DE |
370 | /* This is copied from perform_an_assembly_pass. */ |
371 | applicable = bfd_applicable_section_flags (stdoutput); | |
372 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ebde3f62 | 373 | |
c8cf7e17 DE |
374 | #if 0 /* What does this do? [see perform_an_assembly_pass] */ |
375 | seg_info (bss_section)->bss = 1; | |
376 | #endif | |
377 | ||
378 | subseg_set (seg, subseg); | |
379 | ||
380 | /* We must construct a fake section similar to bfd_com_section | |
381 | but with the name .scommon. */ | |
ebde3f62 NC |
382 | scom_section = bfd_com_section; |
383 | scom_section.name = ".scommon"; | |
384 | scom_section.output_section = & scom_section; | |
385 | scom_section.symbol = & scom_symbol; | |
386 | scom_section.symbol_ptr_ptr = & scom_section.symbol; | |
387 | scom_symbol = * bfd_com_section.symbol; | |
388 | scom_symbol.name = ".scommon"; | |
389 | scom_symbol.section = & scom_section; | |
a450e9f4 | 390 | |
b5e9e562 | 391 | /* start-sanitize-m32rx */ |
a450e9f4 | 392 | allow_m32rx (enable_m32rx); |
b5e9e562 | 393 | /* end-sanitize-m32rx */ |
c8cf7e17 DE |
394 | } |
395 | ||
89285fc9 | 396 | /* start-sanitize-m32rx */ |
55a4759f | 397 | |
a15a45e5 DE |
398 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ |
399 | (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \ | |
400 | || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \ | |
401 | && (indices [index] == 0 || indices [index] == 1))) | |
402 | ||
6cf2575a NC |
403 | /* Returns true if an output of instruction 'a' is referenced by an operand |
404 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
405 | checked, otherwise its inputs are examined. */ | |
ebde3f62 | 406 | static int |
6cf2575a | 407 | first_writes_to_seconds_operands (a, b, check_outputs) |
26192c50 NC |
408 | m32r_insn * a; |
409 | m32r_insn * b; | |
6cf2575a | 410 | const int check_outputs; |
00aa5b17 | 411 | { |
c9cec4ef | 412 | const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn); |
39149be2 | 413 | const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn); |
6cf2575a | 414 | int a_index; |
00aa5b17 | 415 | |
0c22a4c1 | 416 | /* If at least one of the instructions takes no operands, then there is |
c9cec4ef NC |
417 | nothing to check. There really are instructions without operands, |
418 | eg 'nop'. */ | |
39149be2 | 419 | if (a_operands == NULL || b_ops == NULL) |
c9cec4ef NC |
420 | return 0; |
421 | ||
6cf2575a | 422 | /* Scan the operand list of 'a' looking for an output operand. */ |
c9cec4ef | 423 | for (a_index = 0; |
6cf2575a NC |
424 | CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END; |
425 | a_index ++, a_operands ++) | |
26192c50 | 426 | { |
6cf2575a | 427 | if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT) |
26192c50 | 428 | { |
c9cec4ef | 429 | int b_index; |
39149be2 | 430 | const CGEN_OPERAND_INSTANCE * b_operands = b_ops; |
a15a45e5 DE |
431 | |
432 | /* Special Case: | |
433 | The Condition bit 'C' is a shadow of the CBR register (control | |
434 | register 1) and also a shadow of bit 31 of the program status | |
435 | word (control register 0). For now this is handled here, rather | |
436 | than by cgen.... */ | |
437 | ||
438 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) | |
439 | { | |
440 | /* Scan operand list of 'b' looking for another reference to the | |
441 | condition bit, which goes in the right direction. */ | |
442 | for (b_index = 0; | |
443 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; | |
444 | b_index ++, b_operands ++) | |
445 | { | |
446 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
447 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
448 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
449 | return 1; | |
450 | } | |
451 | } | |
452 | else | |
6cf2575a | 453 | { |
a15a45e5 DE |
454 | /* Scan operand list of 'b' looking for an operand that references |
455 | the same hardware element, and which goes in the right direction. */ | |
456 | for (b_index = 0; | |
457 | CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END; | |
458 | b_index ++, b_operands ++) | |
459 | { | |
460 | if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) == | |
461 | (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT)) | |
462 | && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands)) | |
463 | && (a->indices [a_index] == b->indices [b_index])) | |
464 | return 1; | |
465 | } | |
6cf2575a | 466 | } |
26192c50 NC |
467 | } |
468 | } | |
469 | ||
6cf2575a | 470 | return 0; |
26192c50 NC |
471 | } |
472 | ||
6cf2575a | 473 | /* Returns true if the insn can (potentially) alter the program counter. */ |
89285fc9 | 474 | static int |
6cf2575a | 475 | writes_to_pc (a) |
89285fc9 | 476 | m32r_insn * a; |
89285fc9 | 477 | { |
a15a45e5 | 478 | #if 0 /* Once PC operands are working.... */ |
c9cec4ef | 479 | const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn); |
8e7a5a04 | 480 | |
c9cec4ef NC |
481 | if (a_operands == NULL) |
482 | return 0; | |
483 | ||
484 | while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END) | |
6cf2575a NC |
485 | { |
486 | if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL | |
487 | && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC) | |
488 | return 1; | |
c9cec4ef NC |
489 | |
490 | a_operands ++; | |
6cf2575a | 491 | } |
8e7a5a04 NC |
492 | #else |
493 | if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI) | |
494 | || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI)) | |
495 | return 1; | |
496 | #endif | |
6cf2575a | 497 | return 0; |
89285fc9 | 498 | } |
26192c50 | 499 | |
775fdd0c NC |
500 | /* Returns NULL if the two 16 bit insns can be executed in parallel, |
501 | otherwise it returns a pointer to an error message explaining why not. */ | |
502 | static const char * | |
26192c50 | 503 | can_make_parallel (a, b) |
b6930bdf NC |
504 | m32r_insn * a; |
505 | m32r_insn * b; | |
775fdd0c NC |
506 | { |
507 | PIPE_ATTR a_pipe; | |
508 | PIPE_ATTR b_pipe; | |
89285fc9 | 509 | |
775fdd0c | 510 | /* Make sure the instructions are the right length. */ |
b6930bdf NC |
511 | if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 |
512 | || CGEN_FIELDS_BITSIZE (& b->fields) != 16) | |
775fdd0c | 513 | abort(); |
89285fc9 | 514 | |
6cf2575a | 515 | if (first_writes_to_seconds_operands (a, b, true)) |
89285fc9 | 516 | return "Instructions write to the same destination register."; |
775fdd0c | 517 | |
b6930bdf NC |
518 | a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE); |
519 | b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE); | |
775fdd0c | 520 | |
b6930bdf | 521 | /* Make sure that the instructions use the correct execution pipelines. */ |
775fdd0c NC |
522 | if ( a_pipe == PIPE_NONE |
523 | || b_pipe == PIPE_NONE) | |
524 | return "Instructions do not use parallel execution pipelines."; | |
89285fc9 NC |
525 | |
526 | /* Leave this test for last, since it is the only test that can | |
527 | go away if the instructions are swapped, and we want to make | |
528 | sure that any other errors are detected before this happens. */ | |
775fdd0c NC |
529 | if ( a_pipe == PIPE_S |
530 | || b_pipe == PIPE_O) | |
531 | return "Instructions share the same execution pipeline"; | |
89285fc9 | 532 | |
775fdd0c NC |
533 | return NULL; |
534 | } | |
775fdd0c NC |
535 | |
536 | #ifdef CGEN_INT_INSN | |
537 | static void | |
b6930bdf NC |
538 | make_parallel (buffer) |
539 | cgen_insn_t * buffer; | |
775fdd0c NC |
540 | { |
541 | /* Force the top bit of the second insn to be set. */ | |
542 | ||
543 | bfd_vma value; | |
544 | ||
545 | if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) | |
546 | { | |
547 | value = bfd_getb16 ((bfd_byte *) buffer); | |
548 | value |= 0x8000; | |
549 | bfd_putb16 (value, (char *) buffer); | |
550 | } | |
551 | else | |
552 | { | |
553 | value = bfd_getl16 ((bfd_byte *) buffer); | |
554 | value |= 0x8000; | |
555 | bfd_putl16 (value, (char *) buffer); | |
556 | } | |
557 | } | |
558 | #else | |
559 | static void | |
b6930bdf NC |
560 | make_parallel (buffer) |
561 | char * buffer; | |
775fdd0c NC |
562 | { |
563 | /* Force the top bit of the second insn to be set. */ | |
564 | ||
565 | buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80; | |
566 | } | |
567 | #endif | |
568 | ||
569 | ||
b6930bdf NC |
570 | static void |
571 | assemble_parallel_insn (str, str2) | |
ebde3f62 | 572 | char * str; |
b6930bdf | 573 | char * str2; |
c8cf7e17 | 574 | { |
b6930bdf NC |
575 | char * str3; |
576 | m32r_insn first; | |
577 | m32r_insn second; | |
578 | char * errmsg; | |
ebde3f62 | 579 | |
b6930bdf | 580 | * str2 = 0; /* Seperate the two instructions. */ |
c8cf7e17 | 581 | |
b6930bdf NC |
582 | /* If there was a previous 16 bit insn, then fill the following 16 bit slot, |
583 | so that the parallel instruction will start on a 32 bit boundary. */ | |
584 | if (prev_insn.insn) | |
585 | fill_insn (0); | |
ebde3f62 | 586 | |
b6930bdf NC |
587 | /* Parse the first instruction. */ |
588 | if (! (first.insn = CGEN_SYM (assemble_insn) | |
589 | (str, & first.fields, first.buffer, & errmsg))) | |
590 | { | |
591 | as_bad (errmsg); | |
592 | return; | |
593 | } | |
79420f9a | 594 | |
b6930bdf NC |
595 | /* Check to see if this is an allowable parallel insn. */ |
596 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
597 | { | |
598 | as_bad ("instruction '%s' cannot be executed in parallel.", str); | |
599 | return; | |
600 | } | |
ebde3f62 | 601 | |
b6930bdf NC |
602 | if (! enable_m32rx |
603 | && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
604 | { | |
605 | as_bad ("instruction '%s' is for the M32RX only", str); | |
606 | return; | |
ebde3f62 NC |
607 | } |
608 | ||
a15a45e5 DE |
609 | /* Temporary Hack: |
610 | If the instruciton is relaxable, reparse it looking for a non-relaxable variant. | |
611 | (We do not want to relax instructions inside a parallel construction, and if it | |
612 | turns out that the branch is too far for the displacement field available to the | |
613 | non-relaxed instruction, then this is the programmer's fault. | |
614 | A better solution would be to pass attribute requirements to assemble_insn() so | |
615 | that the relaxable variant would not be accepted as a valid parse of the instruction. */ | |
616 | ||
617 | if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_RELAXABLE) != 0) | |
618 | { | |
619 | char buf[128]; | |
620 | char * p; | |
621 | /* Oh dear - the insn is relaxable, so it might be replaced with a longer, | |
622 | non-parallel version. Try appending ".s" to the instruction and reparsing it. */ | |
623 | ||
624 | p = strchr (str, ' '); | |
625 | if (p == NULL) | |
626 | abort(); | |
627 | * p = 0; | |
628 | sprintf (buf, "%s.s %s", str, p + 1); | |
629 | * p = ' '; | |
630 | ||
631 | /* Reset fixup list to empty. */ | |
632 | cgen_save_fixups(); | |
633 | ||
634 | first.insn = CGEN_SYM (assemble_insn) (buf, & first.fields, first.buffer, & errmsg); | |
635 | ||
636 | if (first.insn == NULL) | |
637 | abort(); | |
638 | } | |
639 | ||
b6930bdf NC |
640 | *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */ |
641 | str3 = str; /* Save the original string pointer. */ | |
642 | str = str2 + 2; /* Advanced past the parsed string. */ | |
643 | str2 = str3; /* Remember the entire string in case it is needed for error messages. */ | |
644 | ||
645 | /* Preserve any fixups that have been generated and reset the list to empty. */ | |
646 | cgen_save_fixups(); | |
647 | ||
6cf2575a NC |
648 | /* Get the indicies of the operands of the instruction. */ |
649 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
650 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
c9cec4ef NC |
651 | /* FIXME: ALIAS insns do not have operands, so we use this function |
652 | to find the equivalent insn and overwrite the value stored in our | |
a15a45e5 DE |
653 | structure. We still need the original insn, however, since this |
654 | may have certain attributes that are not present in the unaliased | |
655 | version (eg relaxability). When aliases behave differently this | |
656 | may have to change. */ | |
657 | first.orig_insn = first.insn; | |
c9cec4ef NC |
658 | first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16, |
659 | first.indices); | |
660 | if (first.insn == NULL) | |
6cf2575a NC |
661 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn"); |
662 | ||
b6930bdf NC |
663 | /* Parse the second instruction. */ |
664 | if (! (second.insn = CGEN_SYM (assemble_insn) | |
665 | (str, & second.fields, second.buffer, & errmsg))) | |
4e9d8dea DE |
666 | { |
667 | as_bad (errmsg); | |
668 | return; | |
669 | } | |
c8cf7e17 | 670 | |
b6930bdf NC |
671 | /* Check it. */ |
672 | if (! enable_m32rx | |
673 | && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
ebde3f62 NC |
674 | { |
675 | as_bad ("instruction '%s' is for the M32RX only", str); | |
676 | return; | |
677 | } | |
ebde3f62 | 678 | |
b6930bdf | 679 | if (! enable_m32rx) |
ebde3f62 | 680 | { |
b6930bdf NC |
681 | if ( strcmp (first.insn->name, "nop") != 0 |
682 | && strcmp (second.insn->name, "nop") != 0) | |
ebde3f62 | 683 | { |
b6930bdf NC |
684 | as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2); |
685 | return; | |
ebde3f62 | 686 | } |
b6930bdf | 687 | } |
9121b102 | 688 | |
a15a45e5 DE |
689 | /* See comment above. */ |
690 | if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_RELAXABLE) != 0) | |
691 | { | |
692 | char buf[128]; | |
693 | char * p; | |
694 | /* Oh dear - the insn is relaxable, so it might be replaced with a longer, | |
695 | non-parallel version. Try appending ".s" to the instruction and reparsing it. */ | |
696 | ||
697 | p = strchr (str, ' '); | |
698 | if (p == NULL) | |
699 | abort(); | |
700 | * p = 0; | |
701 | sprintf (buf, "%s.s %s", str, p + 1); | |
702 | * p = ' '; | |
703 | ||
704 | /* Reset fixup list to empty, preserving saved fixups. */ | |
705 | cgen_restore_fixups(); | |
706 | cgen_save_fixups(); | |
707 | ||
708 | second.insn = CGEN_SYM (assemble_insn) (buf, & second.fields, second.buffer, & errmsg); | |
709 | ||
710 | if (second.insn == NULL) | |
711 | abort(); | |
712 | } | |
713 | ||
6cf2575a | 714 | /* Get the indicies of the operands of the instruction. */ |
a15a45e5 | 715 | second.orig_insn = second.insn; |
c9cec4ef NC |
716 | second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16, |
717 | second.indices); | |
718 | if (second.insn == NULL) | |
6cf2575a NC |
719 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn"); |
720 | ||
b6930bdf NC |
721 | /* We assume that if the first instruction writes to a register that is |
722 | read by the second instruction it is because the programmer intended | |
723 | this to happen, (after all they have explicitly requested that these | |
26192c50 NC |
724 | two instructions be executed in parallel). Although if the global |
725 | variable warn_explicit_parallel_conflicts is true then we do generate | |
726 | a warning message. Similarly we assume that parallel branch and jump | |
00aa5b17 | 727 | instructions are deliberate and should not produce errors. */ |
b6930bdf | 728 | |
00aa5b17 | 729 | if (warn_explicit_parallel_conflicts) |
b6930bdf | 730 | { |
6cf2575a NC |
731 | if (first_writes_to_seconds_operands (& first, & second, false)) |
732 | as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2); | |
26192c50 | 733 | |
6cf2575a NC |
734 | if (first_writes_to_seconds_operands (& second, & first, false)) |
735 | as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2); | |
00aa5b17 DE |
736 | } |
737 | ||
738 | if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL) | |
739 | { | |
b6930bdf NC |
740 | /* Get the fixups for the first instruction. */ |
741 | cgen_swap_fixups (); | |
742 | ||
743 | /* Write it out. */ | |
a15a45e5 | 744 | (void) cgen_asm_finish_insn (first.orig_insn, first.buffer, |
b6930bdf | 745 | CGEN_FIELDS_BITSIZE (& first.fields)); |
ebde3f62 | 746 | |
b6930bdf NC |
747 | /* Force the top bit of the second insn to be set. */ |
748 | make_parallel (second.buffer); | |
ebde3f62 | 749 | |
b6930bdf NC |
750 | /* Get its fixups. */ |
751 | cgen_restore_fixups (); | |
775fdd0c | 752 | |
b6930bdf | 753 | /* Write it out. */ |
a15a45e5 | 754 | (void) cgen_asm_finish_insn (second.orig_insn, second.buffer, |
b6930bdf NC |
755 | CGEN_FIELDS_BITSIZE (& second.fields)); |
756 | } | |
89285fc9 | 757 | /* Try swapping the instructions to see if they work that way. */ |
6cf2575a | 758 | else if (can_make_parallel (& second, & first) == NULL) |
b6930bdf NC |
759 | { |
760 | /* Write out the second instruction first. */ | |
a15a45e5 | 761 | (void) cgen_asm_finish_insn (second.orig_insn, second.buffer, |
b6930bdf | 762 | CGEN_FIELDS_BITSIZE (& second.fields)); |
775fdd0c | 763 | |
b6930bdf NC |
764 | /* Force the top bit of the first instruction to be set. */ |
765 | make_parallel (first.buffer); | |
766 | ||
767 | /* Get the fixups for the first instruction. */ | |
768 | cgen_restore_fixups (); | |
769 | ||
770 | /* Write out the first instruction. */ | |
a15a45e5 | 771 | (void) cgen_asm_finish_insn (first.orig_insn, first.buffer, |
b6930bdf NC |
772 | CGEN_FIELDS_BITSIZE (& first.fields)); |
773 | } | |
774 | else | |
775 | { | |
776 | as_bad ("'%s': %s", str2, errmsg); | |
777 | return; | |
778 | } | |
ebde3f62 | 779 | |
b6930bdf NC |
780 | /* Set these so m32r_fill_insn can use them. */ |
781 | prev_seg = now_seg; | |
782 | prev_subseg = now_subseg; | |
783 | ||
784 | return; | |
785 | } | |
55a4759f | 786 | |
b6930bdf NC |
787 | /* end-sanitize-m32rx */ |
788 | ||
789 | ||
790 | void | |
791 | md_assemble (str) | |
792 | char * str; | |
793 | { | |
794 | m32r_insn insn; | |
795 | char * errmsg; | |
796 | char * str2 = NULL; | |
797 | ||
798 | /* Initialize GAS's cgen interface for a new instruction. */ | |
799 | cgen_asm_init_parse (); | |
800 | ||
801 | /* start-sanitize-m32rx */ | |
802 | /* Look for a parallel instruction seperator. */ | |
803 | if ((str2 = strstr (str, "||")) != NULL) | |
804 | { | |
805 | assemble_parallel_insn (str, str2); | |
806 | return; | |
ebde3f62 | 807 | } |
b6930bdf NC |
808 | /* end-sanitize-m32rx */ |
809 | ||
810 | insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); | |
811 | if (!insn.insn) | |
812 | { | |
813 | as_bad (errmsg); | |
814 | return; | |
815 | } | |
816 | ||
817 | /* start-sanitize-m32rx */ | |
818 | if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
819 | { | |
820 | as_bad ("instruction '%s' is for the M32RX only", str); | |
821 | return; | |
822 | } | |
823 | /* end-sanitize-m32rx */ | |
824 | ||
825 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) | |
c8cf7e17 DE |
826 | { |
827 | /* 32 bit insns must live on 32 bit boundaries. */ | |
b6930bdf | 828 | if (prev_insn.insn || seen_relaxable_p) |
ebde3f62 | 829 | { |
0c22a4c1 | 830 | /* ??? If calling fill_insn too many times turns us into a memory |
ebde3f62 NC |
831 | pig, can we call assemble_nop instead of !seen_relaxable_p? */ |
832 | fill_insn (0); | |
833 | } | |
834 | ||
b6930bdf NC |
835 | (void) cgen_asm_finish_insn (insn.insn, insn.buffer, |
836 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
c8cf7e17 DE |
837 | } |
838 | else | |
839 | { | |
b6930bdf NC |
840 | /* start-sanitize-m32rx */ |
841 | /* start-sanitize-phase2-m32rx */ | |
842 | int swap = false; | |
843 | /* end-sanitize-phase2-m32rx */ | |
844 | /* end-sanitize-m32rx */ | |
845 | ||
846 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
847 | abort(); | |
848 | ||
0c22a4c1 | 849 | /* Get the indices of the operands of the instruction. */ |
c9cec4ef NC |
850 | insn.insn = m32r_cgen_get_insn_operands (insn.insn, |
851 | bfd_getb16 ((char *) insn.buffer), | |
852 | 16, | |
853 | insn.indices); | |
854 | if (insn.insn == NULL) | |
6cf2575a NC |
855 | as_fatal ("internal error: m32r_cgen_get_insn_operands failed"); |
856 | ||
c8cf7e17 | 857 | /* Keep track of whether we've seen a pair of 16 bit insns. |
b6930bdf NC |
858 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
859 | if (prev_insn.insn) | |
775fdd0c NC |
860 | { |
861 | /* start-sanitize-m32rx */ | |
b6930bdf NC |
862 | /* start-sanitize-phase2-m32rx */ |
863 | /* Look to see if this instruction can be combined with the | |
864 | previous instruction to make one, parallel, 32 bit instruction. | |
865 | If the previous instruction (potentially) changed the flow of | |
866 | program control, then it cannot be combined with the current | |
b86c0dd3 NC |
867 | instruction. If the current instruction is relaxable, then it |
868 | might be replaced with a longer version, so we cannot combine it. | |
869 | Also if the output of the previous instruction is used as an | |
870 | input to the current instruction then it cannot be combined. | |
871 | Otherwise call can_make_parallel() with both orderings of the | |
872 | instructions to see if they can be combined. */ | |
873 | if ( enable_m32rx | |
874 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) == 0 | |
875 | && ! writes_to_pc (& prev_insn) | |
6cf2575a | 876 | && ! first_writes_to_seconds_operands (& prev_insn, &insn, false) |
ed295804 | 877 | ) |
775fdd0c | 878 | { |
ed295804 NC |
879 | if (can_make_parallel (& prev_insn, & insn) == NULL) |
880 | make_parallel (insn.buffer); | |
881 | else if (can_make_parallel (& insn, & prev_insn.insn) == NULL) | |
882 | swap = true; | |
775fdd0c | 883 | } |
b6930bdf | 884 | /* end-sanitize-phase2-m32rx */ |
775fdd0c NC |
885 | /* end-sanitize-m32rx */ |
886 | ||
b6930bdf | 887 | prev_insn.insn = NULL; |
775fdd0c | 888 | } |
c8cf7e17 | 889 | else |
775fdd0c | 890 | { |
b6930bdf | 891 | prev_insn = insn; |
775fdd0c | 892 | } |
c8cf7e17 | 893 | |
b6930bdf NC |
894 | /* Record the frag that might be used by this insn. */ |
895 | insn.frag = frag_now; | |
896 | insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer, | |
897 | CGEN_FIELDS_BITSIZE (& insn.fields)); | |
898 | ||
899 | /* start-sanitize-m32rx */ | |
900 | /* start-sanitize-phase2-m32rx */ | |
901 | if (swap) | |
902 | { | |
0c22a4c1 | 903 | int tmp; |
b6930bdf NC |
904 | |
905 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
906 | ||
907 | /* Swap the two insns */ | |
908 | SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); | |
909 | SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); | |
910 | ||
911 | make_parallel (insn.addr); | |
912 | ||
913 | /* Swap any relaxable frags recorded for the two insns. */ | |
914 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
b86c0dd3 | 915 | prev_insn.frag->fr_opcode = insn.addr; |
b6930bdf | 916 | else if (insn.frag->fr_opcode == insn.addr) |
b86c0dd3 | 917 | insn.frag->fr_opcode = prev_insn.addr; |
b6930bdf NC |
918 | } |
919 | /* end-sanitize-phase2-m32rx */ | |
920 | ||
921 | /* Record where this instruction was assembled. */ | |
922 | prev_insn.addr = insn.addr; | |
923 | prev_insn.frag = insn.frag; | |
924 | /* end-sanitize-m32rx */ | |
925 | ||
c8cf7e17 DE |
926 | /* If the insn needs the following one to be on a 32 bit boundary |
927 | (e.g. subroutine calls), fill this insn's slot. */ | |
b86c0dd3 | 928 | if (prev_insn.insn != NULL |
b6930bdf | 929 | && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0) |
c8cf7e17 | 930 | fill_insn (0); |
c8cf7e17 | 931 | |
775fdd0c | 932 | /* If this is a relaxable insn (can be replaced with a larger version) |
b6930bdf NC |
933 | mark the fact so that we can emit an alignment directive for a |
934 | following 32 bit insn if we see one. */ | |
935 | if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0) | |
775fdd0c NC |
936 | seen_relaxable_p = 1; |
937 | } | |
c8cf7e17 DE |
938 | |
939 | /* Set these so m32r_fill_insn can use them. */ | |
ebde3f62 | 940 | prev_seg = now_seg; |
c8cf7e17 DE |
941 | prev_subseg = now_subseg; |
942 | } | |
943 | ||
944 | /* The syntax in the manual says constants begin with '#'. | |
945 | We just ignore it. */ | |
946 | ||
947 | void | |
948 | md_operand (expressionP) | |
ebde3f62 | 949 | expressionS * expressionP; |
c8cf7e17 | 950 | { |
ebde3f62 | 951 | if (* input_line_pointer == '#') |
c8cf7e17 | 952 | { |
ebde3f62 | 953 | input_line_pointer ++; |
c8cf7e17 DE |
954 | expression (expressionP); |
955 | } | |
956 | } | |
957 | ||
958 | valueT | |
959 | md_section_align (segment, size) | |
ebde3f62 | 960 | segT segment; |
c8cf7e17 DE |
961 | valueT size; |
962 | { | |
963 | int align = bfd_get_section_alignment (stdoutput, segment); | |
964 | return ((size + (1 << align) - 1) & (-1 << align)); | |
965 | } | |
966 | ||
967 | symbolS * | |
968 | md_undefined_symbol (name) | |
ebde3f62 | 969 | char * name; |
c8cf7e17 DE |
970 | { |
971 | return 0; | |
972 | } | |
973 | \f | |
974 | /* .scomm pseudo-op handler. | |
975 | ||
976 | This is a new pseudo-op to handle putting objects in .scommon. | |
977 | By doing this the linker won't need to do any work and more importantly | |
978 | it removes the implicit -G arg necessary to correctly link the object file. | |
979 | */ | |
980 | ||
981 | static void | |
982 | m32r_scomm (ignore) | |
983 | int ignore; | |
984 | { | |
ebde3f62 NC |
985 | register char * name; |
986 | register char c; | |
987 | register char * p; | |
988 | offsetT size; | |
989 | register symbolS * symbolP; | |
990 | offsetT align; | |
991 | int align2; | |
c8cf7e17 DE |
992 | |
993 | name = input_line_pointer; | |
994 | c = get_symbol_end (); | |
995 | ||
996 | /* just after name is now '\0' */ | |
997 | p = input_line_pointer; | |
ebde3f62 | 998 | * p = c; |
c8cf7e17 | 999 | SKIP_WHITESPACE (); |
ebde3f62 | 1000 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
1001 | { |
1002 | as_bad ("Expected comma after symbol-name: rest of line ignored."); | |
1003 | ignore_rest_of_line (); | |
1004 | return; | |
1005 | } | |
1006 | ||
b6930bdf | 1007 | input_line_pointer ++; /* skip ',' */ |
c8cf7e17 DE |
1008 | if ((size = get_absolute_expression ()) < 0) |
1009 | { | |
1010 | as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size); | |
1011 | ignore_rest_of_line (); | |
1012 | return; | |
1013 | } | |
1014 | ||
1015 | /* The third argument to .scomm is the alignment. */ | |
ebde3f62 | 1016 | if (* input_line_pointer != ',') |
c8cf7e17 DE |
1017 | align = 8; |
1018 | else | |
1019 | { | |
ebde3f62 | 1020 | ++ input_line_pointer; |
c8cf7e17 DE |
1021 | align = get_absolute_expression (); |
1022 | if (align <= 0) | |
1023 | { | |
1024 | as_warn ("ignoring bad alignment"); | |
1025 | align = 8; | |
1026 | } | |
1027 | } | |
1028 | /* Convert to a power of 2 alignment. */ | |
1029 | if (align) | |
1030 | { | |
ebde3f62 | 1031 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) |
c8cf7e17 DE |
1032 | continue; |
1033 | if (align != 1) | |
1034 | { | |
1035 | as_bad ("Common alignment not a power of 2"); | |
1036 | ignore_rest_of_line (); | |
1037 | return; | |
1038 | } | |
1039 | } | |
1040 | else | |
1041 | align2 = 0; | |
1042 | ||
ebde3f62 | 1043 | * p = 0; |
c8cf7e17 | 1044 | symbolP = symbol_find_or_make (name); |
ebde3f62 | 1045 | * p = c; |
c8cf7e17 DE |
1046 | |
1047 | if (S_IS_DEFINED (symbolP)) | |
1048 | { | |
1049 | as_bad ("Ignoring attempt to re-define symbol `%s'.", | |
1050 | S_GET_NAME (symbolP)); | |
1051 | ignore_rest_of_line (); | |
1052 | return; | |
1053 | } | |
1054 | ||
1055 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1056 | { | |
1057 | as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.", | |
1058 | S_GET_NAME (symbolP), | |
1059 | (long) S_GET_VALUE (symbolP), | |
1060 | (long) size); | |
1061 | ||
1062 | ignore_rest_of_line (); | |
1063 | return; | |
1064 | } | |
1065 | ||
1066 | if (symbolP->local) | |
1067 | { | |
ebde3f62 NC |
1068 | segT old_sec = now_seg; |
1069 | int old_subsec = now_subseg; | |
1070 | char * pfrag; | |
c8cf7e17 DE |
1071 | |
1072 | record_alignment (sbss_section, align2); | |
1073 | subseg_set (sbss_section, 0); | |
775fdd0c | 1074 | |
c8cf7e17 DE |
1075 | if (align2) |
1076 | frag_align (align2, 0, 0); | |
775fdd0c | 1077 | |
c8cf7e17 DE |
1078 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
1079 | symbolP->sy_frag->fr_symbol = 0; | |
775fdd0c | 1080 | |
c8cf7e17 | 1081 | symbolP->sy_frag = frag_now; |
b6930bdf | 1082 | |
c8cf7e17 DE |
1083 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1084 | (char *) 0); | |
ebde3f62 | 1085 | * pfrag = 0; |
c8cf7e17 DE |
1086 | S_SET_SIZE (symbolP, size); |
1087 | S_SET_SEGMENT (symbolP, sbss_section); | |
1088 | S_CLEAR_EXTERNAL (symbolP); | |
1089 | subseg_set (old_sec, old_subsec); | |
1090 | } | |
1091 | else | |
1092 | { | |
1093 | S_SET_VALUE (symbolP, (valueT) size); | |
1094 | S_SET_ALIGN (symbolP, align2); | |
1095 | S_SET_EXTERNAL (symbolP); | |
b6930bdf | 1096 | S_SET_SEGMENT (symbolP, & scom_section); |
c8cf7e17 DE |
1097 | } |
1098 | ||
1099 | demand_empty_rest_of_line (); | |
1100 | } | |
1101 | \f | |
1102 | /* Interface to relax_segment. */ | |
1103 | ||
1104 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1105 | ||
1106 | const relax_typeS md_relax_table[] = | |
1107 | { | |
1108 | /* The fields are: | |
1109 | 1) most positive reach of this state, | |
1110 | 2) most negative reach of this state, | |
1111 | 3) how many bytes this mode will add to the size of the current frag | |
1112 | 4) which index into the table to try if we can't fit into this one. */ | |
1113 | ||
1114 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1115 | each list. */ | |
1116 | {1, 1, 0, 0}, | |
1117 | ||
1118 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1119 | so we subtract 2 from the following. */ | |
1120 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1121 | This doesn't handle a branch in the right slot at the border: | |
1122 | the "& -4" isn't taken into account. It's not important enough to | |
1123 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1124 | case). */ | |
1125 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1126 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1127 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1128 | /* Same thing, but with leading nop for alignment. */ | |
1129 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1130 | }; | |
1131 | ||
1132 | long | |
1133 | m32r_relax_frag (fragP, stretch) | |
ebde3f62 NC |
1134 | fragS * fragP; |
1135 | long stretch; | |
c8cf7e17 DE |
1136 | { |
1137 | /* Address of branch insn. */ | |
1138 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1139 | long growth = 0; | |
1140 | ||
1141 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1142 | if (fragP->fr_subtype == 2) | |
1143 | { | |
1144 | if ((address & 3) != 0) | |
1145 | { | |
1146 | fragP->fr_subtype = 3; | |
1147 | growth = 2; | |
1148 | } | |
1149 | } | |
1150 | else if (fragP->fr_subtype == 3) | |
1151 | { | |
1152 | if ((address & 3) == 0) | |
1153 | { | |
1154 | fragP->fr_subtype = 2; | |
1155 | growth = -2; | |
1156 | } | |
1157 | } | |
1158 | else | |
1159 | { | |
1160 | growth = relax_frag (fragP, stretch); | |
1161 | ||
1162 | /* Long jump on odd halfword boundary? */ | |
1163 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1164 | { | |
1165 | fragP->fr_subtype = 3; | |
1166 | growth += 2; | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | return growth; | |
1171 | } | |
1172 | ||
1173 | /* Return an initial guess of the length by which a fragment must grow to | |
1174 | hold a branch to reach its destination. | |
1175 | Also updates fr_type/fr_subtype as necessary. | |
1176 | ||
1177 | Called just before doing relaxation. | |
1178 | Any symbol that is now undefined will not become defined. | |
1179 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1180 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
1181 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
1182 | 0 value. */ | |
1183 | ||
1184 | int | |
1185 | md_estimate_size_before_relax (fragP, segment) | |
ebde3f62 NC |
1186 | fragS * fragP; |
1187 | segT segment; | |
c8cf7e17 | 1188 | { |
ebde3f62 NC |
1189 | int old_fr_fix = fragP->fr_fix; |
1190 | char * opcode = fragP->fr_opcode; | |
c8cf7e17 DE |
1191 | |
1192 | /* The only thing we have to handle here are symbols outside of the | |
1193 | current segment. They may be undefined or in a different segment in | |
1194 | which case linker scripts may place them anywhere. | |
1195 | However, we can't finish the fragment here and emit the reloc as insn | |
1196 | alignment requirements may move the insn about. */ | |
1197 | ||
1198 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1199 | { | |
1200 | /* The symbol is undefined in this segment. | |
1201 | Change the relaxation subtype to the max allowable and leave | |
1202 | all further handling to md_convert_frag. */ | |
1203 | fragP->fr_subtype = 2; | |
1204 | ||
1205 | #if 0 /* Can't use this, but leave in for illustration. */ | |
1206 | /* Change 16 bit insn to 32 bit insn. */ | |
1207 | opcode[0] |= 0x80; | |
1208 | ||
1209 | /* Increase known (fixed) size of fragment. */ | |
1210 | fragP->fr_fix += 2; | |
1211 | ||
1212 | /* Create a relocation for it. */ | |
1213 | fix_new (fragP, old_fr_fix, 4, | |
1214 | fragP->fr_symbol, | |
1215 | fragP->fr_offset, 1 /* pcrel */, | |
1216 | /* FIXME: Can't use a real BFD reloc here. | |
1217 | cgen_md_apply_fix3 can't handle it. */ | |
1218 | BFD_RELOC_M32R_26_PCREL); | |
1219 | ||
1220 | /* Mark this fragment as finished. */ | |
1221 | frag_wane (fragP); | |
1222 | #else | |
a450e9f4 | 1223 | { |
ebde3f62 NC |
1224 | const CGEN_INSN * insn; |
1225 | int i; | |
a450e9f4 NC |
1226 | |
1227 | /* Update the recorded insn. | |
1228 | Fortunately we don't have to look very far. | |
1229 | FIXME: Change this to record in the instruction the next higher | |
1230 | relaxable insn to use. */ | |
1231 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1232 | { | |
b5e9e562 DE |
1233 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
1234 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
a450e9f4 NC |
1235 | == 0) |
1236 | && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX)) | |
1237 | break; | |
1238 | } | |
1239 | if (i == 4) | |
1240 | abort (); | |
b6930bdf | 1241 | |
a450e9f4 NC |
1242 | fragP->fr_cgen.insn = insn; |
1243 | return 2; | |
1244 | } | |
c8cf7e17 DE |
1245 | #endif |
1246 | } | |
1247 | ||
1248 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
1249 | } | |
1250 | ||
1251 | /* *fragP has been relaxed to its final size, and now needs to have | |
1252 | the bytes inside it modified to conform to the new size. | |
1253 | ||
1254 | Called after relaxation is finished. | |
1255 | fragP->fr_type == rs_machine_dependent. | |
1256 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1257 | ||
1258 | void | |
1259 | md_convert_frag (abfd, sec, fragP) | |
775fdd0c NC |
1260 | bfd * abfd; |
1261 | segT sec; | |
1262 | fragS * fragP; | |
c8cf7e17 | 1263 | { |
ebde3f62 NC |
1264 | char * opcode; |
1265 | char * displacement; | |
1266 | int target_address; | |
1267 | int opcode_address; | |
1268 | int extension; | |
1269 | int addend; | |
c8cf7e17 DE |
1270 | |
1271 | opcode = fragP->fr_opcode; | |
1272 | ||
1273 | /* Address opcode resides at in file space. */ | |
1274 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1275 | ||
1276 | switch (fragP->fr_subtype) | |
1277 | { | |
1278 | case 1 : | |
1279 | extension = 0; | |
ebde3f62 | 1280 | displacement = & opcode[1]; |
c8cf7e17 DE |
1281 | break; |
1282 | case 2 : | |
1283 | opcode[0] |= 0x80; | |
1284 | extension = 2; | |
ebde3f62 | 1285 | displacement = & opcode[1]; |
c8cf7e17 DE |
1286 | break; |
1287 | case 3 : | |
1288 | opcode[2] = opcode[0] | 0x80; | |
1289 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1290 | opcode_address += 2; | |
1291 | extension = 4; | |
ebde3f62 | 1292 | displacement = & opcode[3]; |
c8cf7e17 DE |
1293 | break; |
1294 | default : | |
1295 | abort (); | |
1296 | } | |
1297 | ||
1298 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1299 | { | |
1300 | /* symbol must be resolved by linker */ | |
1301 | if (fragP->fr_offset & 3) | |
1302 | as_warn ("Addend to unresolved symbol not on word boundary."); | |
1303 | addend = fragP->fr_offset >> 2; | |
1304 | } | |
1305 | else | |
1306 | { | |
1307 | /* Address we want to reach in file space. */ | |
1308 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
1309 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
1310 | addend = (target_address - (opcode_address & -4)) >> 2; | |
1311 | } | |
1312 | ||
1313 | /* Create a relocation for symbols that must be resolved by the linker. | |
1314 | Otherwise output the completed insn. */ | |
1315 | ||
1316 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1317 | { | |
1318 | assert (fragP->fr_subtype != 1); | |
a450e9f4 | 1319 | assert (fragP->fr_cgen.insn != 0); |
c8cf7e17 DE |
1320 | cgen_record_fixup (fragP, |
1321 | /* Offset of branch insn in frag. */ | |
1322 | fragP->fr_fix + extension - 4, | |
a450e9f4 | 1323 | fragP->fr_cgen.insn, |
c8cf7e17 DE |
1324 | 4 /*length*/, |
1325 | /* FIXME: quick hack */ | |
1326 | #if 0 | |
a450e9f4 | 1327 | CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex), |
c8cf7e17 DE |
1328 | #else |
1329 | CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24), | |
1330 | #endif | |
a450e9f4 | 1331 | fragP->fr_cgen.opinfo, |
c8cf7e17 DE |
1332 | fragP->fr_symbol, fragP->fr_offset); |
1333 | } | |
1334 | ||
1335 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1336 | ||
1337 | md_number_to_chars (displacement, (valueT) addend, | |
1338 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1339 | ||
1340 | fragP->fr_fix += extension; | |
1341 | } | |
1342 | \f | |
1343 | /* Functions concerning relocs. */ | |
1344 | ||
1345 | /* The location from which a PC relative jump should be calculated, | |
1346 | given a PC relative reloc. */ | |
1347 | ||
1348 | long | |
1349 | md_pcrel_from_section (fixP, sec) | |
ebde3f62 NC |
1350 | fixS * fixP; |
1351 | segT sec; | |
c8cf7e17 DE |
1352 | { |
1353 | if (fixP->fx_addsy != (symbolS *) NULL | |
1354 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1355 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1356 | { | |
1357 | /* The symbol is undefined (or is defined but not in this section). | |
1358 | Let the linker figure it out. */ | |
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1363 | } | |
1364 | ||
1365 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1366 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1367 | *FIXP may be modified if desired. */ | |
1368 | ||
1369 | bfd_reloc_code_real_type | |
1370 | CGEN_SYM (lookup_reloc) (insn, operand, fixP) | |
ebde3f62 NC |
1371 | const CGEN_INSN * insn; |
1372 | const CGEN_OPERAND * operand; | |
1373 | fixS * fixP; | |
c8cf7e17 DE |
1374 | { |
1375 | switch (CGEN_OPERAND_TYPE (operand)) | |
1376 | { | |
1377 | case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; | |
1378 | case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; | |
1379 | case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; | |
1380 | case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; | |
1381 | case M32R_OPERAND_HI16 : | |
1382 | case M32R_OPERAND_SLO16 : | |
1383 | case M32R_OPERAND_ULO16 : | |
1384 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1385 | if (fixP->tc_fix_data.opinfo != 0) | |
1386 | return fixP->tc_fix_data.opinfo; | |
1387 | break; | |
1388 | } | |
1389 | return BFD_RELOC_NONE; | |
1390 | } | |
1391 | ||
b6930bdf NC |
1392 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
1393 | ||
1394 | static void | |
1395 | m32r_record_hi16 (reloc_type, fixP, seg) | |
1396 | int reloc_type; | |
1397 | fixS * fixP; | |
1398 | segT seg; | |
1399 | { | |
1400 | struct m32r_hi_fixup * hi_fixup; | |
1401 | ||
1402 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1403 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1404 | ||
1405 | hi_fixup = ((struct m32r_hi_fixup *) | |
1406 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1407 | hi_fixup->fixp = fixP; | |
1408 | hi_fixup->seg = now_seg; | |
1409 | hi_fixup->next = m32r_hi_fixup_list; | |
1410 | ||
1411 | m32r_hi_fixup_list = hi_fixup; | |
1412 | } | |
1413 | ||
c8cf7e17 DE |
1414 | /* Called while parsing an instruction to create a fixup. |
1415 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1416 | ||
1417 | fixS * | |
1418 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ebde3f62 NC |
1419 | fragS * frag; |
1420 | int where; | |
1421 | const CGEN_INSN * insn; | |
1422 | int length; | |
1423 | const CGEN_OPERAND * operand; | |
1424 | int opinfo; | |
1425 | expressionS * exp; | |
c8cf7e17 | 1426 | { |
ebde3f62 NC |
1427 | fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length, |
1428 | operand, opinfo, exp); | |
c8cf7e17 DE |
1429 | |
1430 | switch (CGEN_OPERAND_TYPE (operand)) | |
1431 | { | |
1432 | case M32R_OPERAND_HI16 : | |
1433 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ | |
1434 | if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1435 | || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1436 | m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg); | |
1437 | break; | |
1438 | } | |
1439 | ||
1440 | return fixP; | |
1441 | } | |
1442 | ||
c8cf7e17 DE |
1443 | /* Return BFD reloc type from opinfo field in a fixS. |
1444 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1445 | are BFD_RELOC_UNUSED + operand number. */ | |
1446 | #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo) | |
1447 | ||
1448 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
1449 | the corresponding LO16 reloc. This is called before md_apply_fix and | |
1450 | tc_gen_reloc. */ | |
1451 | ||
1452 | void | |
1453 | m32r_frob_file () | |
1454 | { | |
ebde3f62 | 1455 | struct m32r_hi_fixup * l; |
c8cf7e17 DE |
1456 | |
1457 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1458 | { | |
ebde3f62 NC |
1459 | segment_info_type * seginfo; |
1460 | int pass; | |
c8cf7e17 DE |
1461 | |
1462 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1463 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1464 | ||
1465 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1466 | if (l->fixp->fx_next != NULL | |
1467 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1468 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1469 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1470 | continue; | |
1471 | ||
1472 | /* Look through the fixups for this segment for a matching `low'. | |
1473 | When we find one, move the high/shigh just in front of it. We do | |
1474 | this in two passes. In the first pass, we try to find a | |
1475 | unique `low'. In the second pass, we permit multiple high's | |
1476 | relocs for a single `low'. */ | |
1477 | seginfo = seg_info (l->seg); | |
1478 | for (pass = 0; pass < 2; pass++) | |
1479 | { | |
ebde3f62 NC |
1480 | fixS * f; |
1481 | fixS * prev; | |
c8cf7e17 DE |
1482 | |
1483 | prev = NULL; | |
1484 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1485 | { | |
1486 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1487 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1488 | && f->fx_addsy == l->fixp->fx_addsy | |
1489 | && f->fx_offset == l->fixp->fx_offset | |
1490 | && (pass == 1 | |
1491 | || prev == NULL | |
1492 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1493 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1494 | || prev->fx_addsy != f->fx_addsy | |
1495 | || prev->fx_offset != f->fx_offset)) | |
1496 | { | |
ebde3f62 | 1497 | fixS ** pf; |
c8cf7e17 DE |
1498 | |
1499 | /* Move l->fixp before f. */ | |
1500 | for (pf = &seginfo->fix_root; | |
ebde3f62 NC |
1501 | * pf != l->fixp; |
1502 | pf = & (* pf)->fx_next) | |
1503 | assert (* pf != NULL); | |
c8cf7e17 | 1504 | |
ebde3f62 | 1505 | * pf = l->fixp->fx_next; |
c8cf7e17 DE |
1506 | |
1507 | l->fixp->fx_next = f; | |
1508 | if (prev == NULL) | |
1509 | seginfo->fix_root = l->fixp; | |
1510 | else | |
1511 | prev->fx_next = l->fixp; | |
1512 | ||
1513 | break; | |
1514 | } | |
1515 | ||
1516 | prev = f; | |
1517 | } | |
1518 | ||
1519 | if (f != NULL) | |
1520 | break; | |
1521 | ||
1522 | if (pass == 1) | |
1523 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1524 | "Unmatched high/shigh reloc"); | |
1525 | } | |
1526 | } | |
1527 | } | |
1528 | ||
1529 | /* See whether we need to force a relocation into the output file. | |
1530 | This is used to force out switch and PC relative relocations when | |
1531 | relaxing. */ | |
1532 | ||
1533 | int | |
1534 | m32r_force_relocation (fix) | |
ebde3f62 | 1535 | fixS * fix; |
c8cf7e17 DE |
1536 | { |
1537 | if (! m32r_relax) | |
1538 | return 0; | |
1539 | ||
1540 | return (fix->fx_pcrel | |
1541 | || 0 /* ??? */); | |
1542 | } | |
1543 | \f | |
1544 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1545 | ||
1546 | void | |
1547 | md_number_to_chars (buf, val, n) | |
ebde3f62 | 1548 | char * buf; |
c8cf7e17 | 1549 | valueT val; |
ebde3f62 | 1550 | int n; |
c8cf7e17 DE |
1551 | { |
1552 | if (target_big_endian) | |
1553 | number_to_chars_bigendian (buf, val, n); | |
1554 | else | |
1555 | number_to_chars_littleendian (buf, val, n); | |
1556 | } | |
1557 | ||
1558 | /* Turn a string in input_line_pointer into a floating point constant of type | |
1559 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
1560 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
1561 | */ | |
1562 | ||
1563 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
1564 | #define MAX_LITTLENUMS 6 | |
1565 | ||
1566 | char * | |
1567 | md_atof (type, litP, sizeP) | |
1568 | char type; | |
1569 | char *litP; | |
1570 | int *sizeP; | |
1571 | { | |
ebde3f62 NC |
1572 | int i; |
1573 | int prec; | |
1574 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
1575 | LITTLENUM_TYPE * wordP; | |
1576 | char * t; | |
1577 | char * atof_ieee (); | |
c8cf7e17 DE |
1578 | |
1579 | switch (type) | |
1580 | { | |
1581 | case 'f': | |
1582 | case 'F': | |
1583 | case 's': | |
1584 | case 'S': | |
1585 | prec = 2; | |
1586 | break; | |
1587 | ||
1588 | case 'd': | |
1589 | case 'D': | |
1590 | case 'r': | |
1591 | case 'R': | |
1592 | prec = 4; | |
1593 | break; | |
1594 | ||
1595 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
1596 | ||
1597 | default: | |
ebde3f62 | 1598 | * sizeP = 0; |
c8cf7e17 DE |
1599 | return "Bad call to md_atof()"; |
1600 | } | |
1601 | ||
1602 | t = atof_ieee (input_line_pointer, type, words); | |
1603 | if (t) | |
1604 | input_line_pointer = t; | |
ebde3f62 | 1605 | * sizeP = prec * sizeof (LITTLENUM_TYPE); |
c8cf7e17 DE |
1606 | |
1607 | if (target_big_endian) | |
1608 | { | |
1609 | for (i = 0; i < prec; i++) | |
1610 | { | |
ebde3f62 NC |
1611 | md_number_to_chars (litP, (valueT) words[i], |
1612 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1613 | litP += sizeof (LITTLENUM_TYPE); |
1614 | } | |
1615 | } | |
1616 | else | |
1617 | { | |
1618 | for (i = prec - 1; i >= 0; i--) | |
1619 | { | |
ebde3f62 NC |
1620 | md_number_to_chars (litP, (valueT) words[i], |
1621 | sizeof (LITTLENUM_TYPE)); | |
c8cf7e17 DE |
1622 | litP += sizeof (LITTLENUM_TYPE); |
1623 | } | |
1624 | } | |
1625 | ||
1626 | return 0; | |
1627 | } |