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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
4b95cf5c 2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
252b5132 21#include "as.h"
3882b010 22#include "safe-ctype.h"
252b5132
RH		 23#include "obstack.h"
24#include "subsegs.h"
f27a3839 25#include "dwarf2dbg.h"
c04898f8 26#include "dw2gencfi.h"
252b5132
RH		 27
28#include "opcode/m68k.h"
29#include "m68k-parse.h"
30
0d96863f
CM		 31#if defined (OBJ_ELF)
32#include "elf/m68k.h"
33#endif
34
31302357
AS		 35#ifdef M68KCOFF
36#include "obj-coff.h"
37#endif
38
cf869cce
NC		 39#ifdef OBJ_ELF
40static void m68k_elf_cons (int);
41#endif
42
252b5132
RH		 43/* This string holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful. The macro
45 tc_comment_chars points to this. We use this, rather than the
46 usual comment_chars, so that the --bitwise-or option will work. */
47#if defined (TE_SVR4) || defined (TE_DELTA)
48const char *m68k_comment_chars = "|#";
49#else
50const char *m68k_comment_chars = "|";
51#endif
52
53/* This array holds the chars that only start a comment at the beginning of
54 a line. If the line seems to have the form '# 123 filename'
55 .line and .file directives will appear in the pre-processed output */
56/* Note that input_file.c hand checks for '#' at the beginning of the
57 first line of the input file. This is because the compiler outputs
92774660
KH		 58 #NO_APP at the beginning of its output. */
59/* Also note that comments like this one will always work. */
252b5132
RH		 60const char line_comment_chars[] = "#*";
61
63a0b638 62const char line_separator_chars[] = ";";
252b5132 63
36759679 64/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 65const char EXP_CHARS[] = "eE";
252b5132
RH		 66
67/* Chars that mean this number is a floating point constant, as
68 in "0f12.456" or "0d1.2345e12". */
69
5a38dc70 70const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 71
72/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
73 changed in read.c . Ideally it shouldn't have to know about it at all,
74 but nothing is ideal around here. */
75
252b5132
RH		 76/* Are we trying to generate PIC code? If so, absolute references
77 ought to be made into linkage table references or pc-relative
92774660 78 references. Not implemented. For ELF there are other means
252b5132
RH		 79 to denote pic relocations. */
80int flag_want_pic;
81
36759679
NC		 82static int flag_short_refs; /* -l option. */
83static int flag_long_jumps; /* -S option. */
28e7409f 84static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 85
86#ifdef REGISTER_PREFIX_OPTIONAL
87int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
88#else
89int flag_reg_prefix_optional;
90#endif
91
92/* Whether --register-prefix-optional was used on the command line. */
93static int reg_prefix_optional_seen;
94
95/* The floating point coprocessor to use by default. */
96static enum m68k_register m68k_float_copnum = COP1;
97
98/* If this is non-zero, then references to number(%pc) will be taken
99 to refer to number, rather than to %pc + number. */
100static int m68k_abspcadd;
101
102/* If this is non-zero, then the quick forms of the move, add, and sub
103 instructions are used when possible. */
104static int m68k_quick = 1;
105
106/* If this is non-zero, then if the size is not specified for a base
107 or outer displacement, the assembler assumes that the size should
108 be 32 bits. */
109static int m68k_rel32 = 1;
110
111/* This is non-zero if m68k_rel32 was set from the command line. */
112static int m68k_rel32_from_cmdline;
113
114/* The default width to use for an index register when using a base
115 displacement. */
116static enum m68k_size m68k_index_width_default = SIZE_LONG;
117
118/* We want to warn if any text labels are misaligned. In order to get
119 the right line number, we need to record the line number for each
120 label. */
252b5132
RH		 121struct label_line
122{
123 struct label_line *next;
124 symbolS *label;
125 char *file;
126 unsigned int line;
127 int text;
128};
129
130/* The list of labels. */
131
132static struct label_line *labels;
133
134/* The current label. */
135
136static struct label_line *current_label;
137
60fed2d3
NC		 138/* Pointer to list holding the opcodes sorted by name. */
139static struct m68k_opcode const ** m68k_sorted_opcodes;
140
36759679
NC		 141/* Its an arbitrary name: This means I don't approve of it.
142 See flames below. */
252b5132
RH		 143static struct obstack robyn;
144
252b5132
RH		 145struct m68k_incant
146 {
147 const char *m_operands;
148 unsigned long m_opcode;
149 short m_opnum;
150 short m_codenum;
151 int m_arch;
152 struct m68k_incant *m_next;
153 };
154
155#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
156#define gettwo(x) (((x)->m_opcode)&0xffff)
157
2da12c60
NS		 158static const enum m68k_register m68000_ctrl[] = { 0 };
159static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 160 SFC, DFC, USP, VBR,
161 0
162};
2da12c60 163static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 164 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
165 0
166};
2da12c60 167static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 168 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
169 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
170 0
171};
2da12c60 172static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 173 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
174 USP, VBR, URP, SRP, PCR,
175 0
176};
2da12c60 177static const enum m68k_register mcf_ctrl[] = {
3e602632 178 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 179 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
180 0
181};
87298967
NS		 182static const enum m68k_register mcf51_ctrl[] = {
183 VBR, CPUCR,
f75192f2
KH		 184 0
185};
78336706 186static const enum m68k_register mcf5206_ctrl[] = {
0d999f33 187 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 188 0
189};
2da12c60 190static const enum m68k_register mcf5208_ctrl[] = {
78336706 191 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 192 0
193};
96e0bbcc 194static const enum m68k_register mcf5210a_ctrl[] = {
78336706 195 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 196 0
197};
2da12c60 198static const enum m68k_register mcf5213_ctrl[] = {
78336706 199 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 200 0
201};
2da12c60 202static const enum m68k_register mcf5216_ctrl[] = {
78336706 203 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 204 0
205};
46203761
MK		 206static const enum m68k_register mcf5221x_ctrl[] = {
207 VBR, FLASHBAR, RAMBAR, RAMBAR1,
208 0
209};
d5be9593 210static const enum m68k_register mcf52223_ctrl[] = {
0d999f33 211 VBR, FLASHBAR, RAMBAR, RAMBAR1,
d5be9593
NS		 212 0
213};
96e0bbcc 214static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 215 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 216 0
217};
218static const enum m68k_register mcf5225_ctrl[] = {
78336706 219 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 220 0
221};
87298967
NS		 222static const enum m68k_register mcf52259_ctrl[] = {
223 VBR, FLASHBAR, RAMBAR, RAMBAR1,
224 0
225};
226static const enum m68k_register mcf52277_ctrl[] = {
227 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
228 0
229};
2da12c60 230static const enum m68k_register mcf5235_ctrl[] = {
78336706 231 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 232 0
233};
2da12c60 234static const enum m68k_register mcf5249_ctrl[] = {
78336706 235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 236 0
237};
2da12c60
NS		 238static const enum m68k_register mcf5250_ctrl[] = {
239 VBR,
240 0
241};
d5be9593 242static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 243 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 244 0
245};
2da12c60 246static const enum m68k_register mcf5271_ctrl[] = {
78336706 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 248 0
249};
250static const enum m68k_register mcf5272_ctrl[] = {
78336706 251 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 252 0
253};
254static const enum m68k_register mcf5275_ctrl[] = {
78336706 255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 256 0
257};
258static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 259 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
260 0
261};
87298967 262static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 264 0
265};
78336706 266static const enum m68k_register mcf5307_ctrl[] = {
87298967 267 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 268 0
269};
270static const enum m68k_register mcf5329_ctrl[] = {
78336706 271 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 272 0
273};
274static const enum m68k_register mcf5373_ctrl[] = {
78336706 275 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 276 0
277};
278static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 279 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
280 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
281 MBAR, SECMBAR,
282 MPCR /* Multiprocessor Control register */,
283 EDRAMBAR /* Embedded DRAM Base Address Register */,
284 /* Permutation control registers. */
3e602632
NC		 285 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
286 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 291 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 292 0
293};
def8fc92
KH		 294static const enum m68k_register mcf5407_ctrl[] = {
295 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
296 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
297 /* Legacy names */
298 TC /* ASID */,
299 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
300 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
301 0
302};
0d999f33
MK		 303static const enum m68k_register mcf54418_ctrl[] = {
304 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
305 VBR, PC, RAMBAR1,
306 /* Legacy names */
307 TC /* ASID */, BUSCR /* MMUBAR */,
308 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
309 RAMBAR /* RAMBAR1 */,
310 0
311};
9a2e615a
NS		 312static const enum m68k_register mcf54455_ctrl[] = {
313 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
0d999f33 314 VBR, PC, RAMBAR1,
9a2e615a
NS		 315 /* Legacy names */
316 TC /* ASID */, BUSCR /* MMUBAR */,
317 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
0d999f33 318 RAMBAR /* RAMBAR1 */,
9a2e615a
NS		 319 0
320};
a8e24a56
NS		 321static const enum m68k_register mcf5475_ctrl[] = {
322 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
323 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
324 /* Legacy names */
325 TC /* ASID */, BUSCR /* MMUBAR */,
326 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 327 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 328 0
329};
330static const enum m68k_register mcf5485_ctrl[] = {
331 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
332 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
333 /* Legacy names */
334 TC /* ASID */, BUSCR /* MMUBAR */,
335 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 336 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 337 0
338};
f7ec513b 339static const enum m68k_register fido_ctrl[] = {
d0fa1372 340 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 341 0
342};
2da12c60 343#define cpu32_ctrl m68010_ctrl
252b5132
RH		 344
345static const enum m68k_register *control_regs;
346
36759679 347/* Internal form of a 68020 instruction. */
252b5132
RH		 348struct m68k_it
349{
350 const char *error;
36759679 351 const char *args; /* List of opcode info. */
252b5132
RH		 352 int numargs;
353
36759679 354 int numo; /* Number of shorts in opcode. */
252b5132
RH		 355 short opcode[11];
356
357 struct m68k_op operands[6];
358
36759679 359 int nexp; /* Number of exprs in use. */
252b5132
RH		 360 struct m68k_exp exprs[4];
361
36759679 362 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 363 struct
364 {
36759679 365 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 366 symbolS *fadd;
367 offsetT foff;
368 int fragty;
369 }
370 fragb[4];
371
36759679 372 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 373 struct
374 {
375 int n;
376 expressionS exp;
377 char wid;
378 char pcrel;
379 /* In a pc relative address the difference between the address
380 of the offset and the address that the offset is relative
381 to. This depends on the addressing mode. Basically this
382 is the value to put in the offset field to address the
383 first byte of the offset, without regarding the special
384 significance of some values (in the branch instruction, for
385 example). */
386 int pcrel_fix;
387#ifdef OBJ_ELF
388 /* Whether this expression needs special pic relocation, and if
389 so, which. */
390 enum pic_relocation pic_reloc;
391#endif
392 }
36759679 393 reloc[5]; /* Five is enough??? */
252b5132
RH		 394};
395
9840d27e 396#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 397#define float_of_arch(x) ((x) & mfloat)
398#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 399#define arch_coldfire_p(x) ((x) & mcfisa_a)
400#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 401
36759679 402/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 403#define HAVE_LONG_DISP(x) \
404 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
405#define HAVE_LONG_CALL(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407#define HAVE_LONG_COND(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409#define HAVE_LONG_BRANCH(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 411#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 412
36759679 413static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 414
415#define op(ex) ((ex)->exp.X_op)
416#define adds(ex) ((ex)->exp.X_add_symbol)
417#define subs(ex) ((ex)->exp.X_op_symbol)
418#define offs(ex) ((ex)->exp.X_add_number)
419
36759679 420/* Macros for adding things to the m68k_it struct. */
31302357 421#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 422
36759679
NC		 423/* Like addword, but goes BEFORE general operands. */
424
252b5132 425static void
31302357 426insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 427{
428 int z;
07726851 429 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 430 the_ins.opcode[z] = the_ins.opcode[z - 1];
431 for (z = 0; z < the_ins.nrel; z++)
432 the_ins.reloc[z].n += 2;
252b5132
RH		 433 for (z = 0; z < the_ins.nfrag; z++)
434 the_ins.fragb[z].fragoff++;
8a104df9 435 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 436 the_ins.numo++;
437}
438
439/* The numo+1 kludge is so we can hit the low order byte of the prev word.
440 Blecch. */
441static void
31302357 442add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 443{
31302357
AS		 444 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
445 ? the_ins.numo * 2 - 1
446 : (width == 'b'
447 ? the_ins.numo * 2 + 1
448 : the_ins.numo * 2));
252b5132
RH		 449 the_ins.reloc[the_ins.nrel].exp = exp->exp;
450 the_ins.reloc[the_ins.nrel].wid = width;
451 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
452#ifdef OBJ_ELF
453 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
454#endif
455 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
456}
457
458/* Cause an extra frag to be generated here, inserting up to 10 bytes
459 (that value is chosen in the frag_var call in md_assemble). TYPE
460 is the subtype of the frag to be generated; its primary type is
461 rs_machine_dependent.
462
463 The TYPE parameter is also used by md_convert_frag_1 and
464 md_estimate_size_before_relax. The appropriate type of fixup will
465 be emitted by md_convert_frag_1.
466
467 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
468static void
31302357 469add_frag (symbolS *add, offsetT off, int type)
252b5132 470{
8a104df9
KH		 471 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
472 the_ins.fragb[the_ins.nfrag].fadd = add;
473 the_ins.fragb[the_ins.nfrag].foff = off;
474 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 475}
476
477#define isvar(ex) \
478 (op (ex) != O_constant && op (ex) != O_big)
479
31302357
AS		 480static char *crack_operand (char *str, struct m68k_op *opP);
481static int get_num (struct m68k_exp *exp, int ok);
482static int reverse_16_bits (int in);
483static int reverse_8_bits (int in);
484static void install_gen_operand (int mode, int val);
485static void install_operand (int mode, int val);
486static void s_bss (int);
487static void s_data1 (int);
488static void s_data2 (int);
489static void s_even (int);
490static void s_proc (int);
491static void s_chip (int);
492static void s_fopt (int);
493static void s_opt (int);
494static void s_reg (int);
495static void s_restore (int);
496static void s_save (int);
497static void s_mri_if (int);
498static void s_mri_else (int);
499static void s_mri_endi (int);
500static void s_mri_break (int);
501static void s_mri_next (int);
502static void s_mri_for (int);
503static void s_mri_endf (int);
504static void s_mri_repeat (int);
505static void s_mri_until (int);
506static void s_mri_while (int);
507static void s_mri_endw (int);
266abb8f
NS		 508static void s_m68k_cpu (int);
509static void s_m68k_arch (int);
510
511struct m68k_cpu
512{
513 unsigned long arch; /* Architecture features. */
2da12c60 514 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 515 const char *name; /* Name */
0b2e31dc
NS		 516 int alias; /* Alias for a cannonical name. If 1, then
517 succeeds canonical name, if -1 then
518 succeeds canonical name, if <-1 ||>1 this is a
519 deprecated name, and the next/previous name
520 should be used. */
266abb8f 521};
252b5132 522
266abb8f
NS		 523/* We hold flags for features explicitly enabled and explicitly
524 disabled. */
252b5132 525static int current_architecture;
266abb8f 526static int not_current_architecture;
266abb8f
NS		 527static const struct m68k_cpu *selected_arch;
528static const struct m68k_cpu *selected_cpu;
529static int initialized;
252b5132 530
266abb8f
NS		 531/* Architecture models. */
532static const struct m68k_cpu m68k_archs[] =
533{
2da12c60
NS		 534 {m68000, m68000_ctrl, "68000", 0},
535 {m68010, m68010_ctrl, "68010", 0},
536 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
537 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
538 {m68040, m68040_ctrl, "68040", 0},
539 {m68060, m68060_ctrl, "68060", 0},
540 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 541 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 542 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
543 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
544 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 545 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
547 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 548 {0,0,NULL, 0}
549};
252b5132 550
87298967
NS		 551/* For -mno-mac we want to turn off all types of mac. */
552static const unsigned no_mac = mcfmac | mcfemac;
553
0b2e31dc
NS		 554/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
555 for either. */
266abb8f
NS		 556static const struct m68k_cpu m68k_extensions[] =
557{
2da12c60
NS		 558 {m68851, NULL, "68851", -1},
559 {m68881, NULL, "68881", -1},
560 {m68881, NULL, "68882", -1},
cf869cce 561
2da12c60 562 {cfloat|m68881, NULL, "float", 0},
cf869cce 563
2da12c60
NS		 564 {mcfhwdiv, NULL, "div", 1},
565 {mcfusp, NULL, "usp", 1},
87298967 566 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 567 {mcfemac, NULL, "emac", 1},
cf869cce 568
2da12c60 569 {0,NULL,NULL, 0}
266abb8f
NS		 570};
571
572/* Processor list */
573static const struct m68k_cpu m68k_cpus[] =
574{
2da12c60
NS		 575 {m68000, m68000_ctrl, "68000", 0},
576 {m68000, m68000_ctrl, "68ec000", 1},
577 {m68000, m68000_ctrl, "68hc000", 1},
578 {m68000, m68000_ctrl, "68hc001", 1},
579 {m68000, m68000_ctrl, "68008", 1},
580 {m68000, m68000_ctrl, "68302", 1},
581 {m68000, m68000_ctrl, "68306", 1},
582 {m68000, m68000_ctrl, "68307", 1},
583 {m68000, m68000_ctrl, "68322", 1},
584 {m68000, m68000_ctrl, "68356", 1},
585 {m68010, m68010_ctrl, "68010", 0},
586 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
587 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
588 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
589 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
590 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
591 {m68040, m68040_ctrl, "68040", 0},
592 {m68040, m68040_ctrl, "68ec040", 1},
593 {m68060, m68060_ctrl, "68060", 0},
594 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 595
2da12c60
NS		 596 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
597 {cpu32|m68881, cpu32_ctrl, "68330", 1},
598 {cpu32|m68881, cpu32_ctrl, "68331", 1},
599 {cpu32|m68881, cpu32_ctrl, "68332", 1},
600 {cpu32|m68881, cpu32_ctrl, "68333", 1},
601 {cpu32|m68881, cpu32_ctrl, "68334", 1},
602 {cpu32|m68881, cpu32_ctrl, "68336", 1},
603 {cpu32|m68881, cpu32_ctrl, "68340", 1},
604 {cpu32|m68881, cpu32_ctrl, "68341", 1},
605 {cpu32|m68881, cpu32_ctrl, "68349", 1},
606 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 607
87298967
NS		 608 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
609 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
c1c30076 610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
87298967
NS		 611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
612 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
c1c30076
NS		 613 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
614 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
615 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
87298967 616 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
c1c30076 617 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
87298967 618 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
c1c30076 619 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
cf869cce 620
2da12c60
NS		 621 {mcfisa_a, mcf_ctrl, "5200", 0},
622 {mcfisa_a, mcf_ctrl, "5202", 1},
623 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 624 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 625
78336706 626 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 627
2da12c60
NS		 628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 630
96e0bbcc
NS		 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 633
2da12c60
NS		 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 637
2da12c60
NS		 638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
641
46203761
MK		 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
643
d5be9593
NS		 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
646
96e0bbcc
NS		 647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 651
96e0bbcc
NS		 652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
653 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 654
87298967
NS		 655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
657
2da12c60
NS		 658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
663
664 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
665 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 666 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 667
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
674
2da12c60
NS		 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
677
678 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
679
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
682
683 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
684 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
687
87298967
NS		 688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
695
78336706 696 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 697
698 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
699 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
702
703 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
704 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
705 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
706
def8fc92 707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a 708
0d999f33
MK		 709 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
710 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
714
9a2e615a
NS		 715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
716 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
717 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
718 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
719 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
720 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 721
a8e24a56
NS		 722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
725 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 729
a8e24a56
NS		 730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
731 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
733 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
734 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
735 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
736 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 737
b3768379 738 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 739 {fido_a, fido_ctrl, "fido", 1},
9840d27e 740
2da12c60 741 {0,NULL,NULL, 0}
dc84e067 742 };
252b5132 743
266abb8f
NS		 744static const struct m68k_cpu *m68k_lookup_cpu
745(const char *, const struct m68k_cpu *, int, int *);
746static int m68k_set_arch (const char *, int, int);
747static int m68k_set_cpu (const char *, int, int);
748static int m68k_set_extension (const char *, int, int);
749static void m68k_init_arch (void);
252b5132 750
151337e8
NC		 751/* This is the assembler relaxation table for m68k. m68k is a rich CISC
752 architecture and we have a lot of relaxation modes. */
252b5132 753
151337e8
NC		 754/* Macros used in the relaxation code. */
755#define TAB(x,y) (((x) << 2) + (y))
756#define TABTYPE(x) ((x) >> 2)
757
758/* Relaxation states. */
759#define BYTE 0
760#define SHORT 1
761#define LONG 2
762#define SZ_UNDEF 3
763
764/* Here are all the relaxation modes we support. First we can relax ordinary
765 branches. On 68020 and higher and on CPU32 all branch instructions take
766 three forms, so on these CPUs all branches always remain as such. When we
767 have to expand to the LONG form on a 68000, though, we substitute an
768 absolute jump instead. This is a direct replacement for unconditional
769 branches and a branch over a jump for conditional branches. However, if the
770 user requires PIC and disables this with --pcrel, we can only relax between
771 BYTE and SHORT forms, punting if that isn't enough. This gives us four
772 different relaxation modes for branches: */
773
36759679
NC		 774#define BRANCHBWL 0 /* Branch byte, word, or long. */
775#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
776#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
777#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 778
779/* We also relax coprocessor branches and DBcc's. All CPUs that support
780 coprocessor branches support them in word and long forms, so we have only
781 one relaxation mode for them. DBcc's are word only on all CPUs. We can
782 relax them to the LONG form with a branch-around sequence. This sequence
783 can use a long branch (if available) or an absolute jump (if acceptable).
784 This gives us two relaxation modes. If long branches are not available and
785 absolute jumps are not acceptable, we don't relax DBcc's. */
786
36759679
NC		 787#define FBRANCH 4 /* Coprocessor branch. */
788#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
789#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 790
791/* That's all for instruction relaxation. However, we also relax PC-relative
792 operands. Specifically, we have three operand relaxation modes. On the
793 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
794 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
795 two. Also PC+displacement+index operands in their simple form (with a non-
796 suppressed index without memory indirection) are supported on all CPUs, but
797 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
798 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
799 form of the PC+displacement+index operand. Finally, some absolute operands
800 can be relaxed down to 16-bit PC-relative. */
801
36759679
NC		 802#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
803#define PCINDEX 8 /* PC + displacement + index. */
804#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 805
cac27205
NC		 806/* This relaxation is required for branches where there is no long
807 branch and we are in pcrel mode. We generate a bne/beq pair. */
808#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
809 */
810
252b5132 811/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 812 needed; this is currently 12 bytes for bne/beq pair. */
813#define FRAG_VAR_SIZE 12
252b5132
RH		 814
815/* The fields are:
816 How far Forward this mode will reach:
817 How far Backward this mode will reach:
818 How many bytes this mode will add to the size of the frag
819 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 820
821 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 822relax_typeS md_relax_table[] =
823{
ac62c346
AM		 824 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
825 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
826 { 0, 0, 4, 0 },
827 { 1, 1, 0, 0 },
828
829 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
830 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
831 { 0, 0, 4, 0 },
832 { 1, 1, 0, 0 },
833
834 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
835 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
836 { 0, 0, 6, 0 },
837 { 1, 1, 0, 0 },
838
839 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
840 { 0, 0, 2, 0 },
841 { 1, 1, 0, 0 },
842 { 1, 1, 0, 0 },
843
36759679 844 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 845 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
846 { 0, 0, 4, 0 },
847 { 1, 1, 0, 0 },
848
36759679 849 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 850 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
851 { 0, 0, 10, 0 },
852 { 1, 1, 0, 0 },
853
36759679 854 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 855 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
856 { 0, 0, 10, 0 },
857 { 1, 1, 0, 0 },
858
36759679 859 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 860 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
861 { 0, 0, 6, 0 },
862 { 1, 1, 0, 0 },
863
864 { 125, -130, 0, TAB (PCINDEX, SHORT) },
865 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
866 { 0, 0, 4, 0 },
867 { 1, 1, 0, 0 },
868
36759679 869 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 870 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
871 { 0, 0, 4, 0 },
872 { 1, 1, 0, 0 },
cac27205
NC		 873
874 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
875 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
876 { 0, 0, 10, 0 },
877 { 1, 1, 0, 0 },
252b5132
RH		 878};
879
880/* These are the machine dependent pseudo-ops. These are included so
881 the assembler can work on the output from the SUN C compiler, which
36759679 882 generates these. */
252b5132
RH		 883
884/* This table describes all the machine specific pseudo-ops the assembler
885 has to support. The fields are:
886 pseudo-op name without dot
887 function to call to execute this pseudo-op
36759679 888 Integer arg to pass to the function. */
252b5132
RH		 889const pseudo_typeS md_pseudo_table[] =
890{
891 {"data1", s_data1, 0},
892 {"data2", s_data2, 0},
893 {"bss", s_bss, 0},
894 {"even", s_even, 0},
895 {"skip", s_space, 0},
896 {"proc", s_proc, 0},
897#if defined (TE_SUN3) || defined (OBJ_ELF)
898 {"align", s_align_bytes, 0},
899#endif
900#ifdef OBJ_ELF
901 {"swbeg", s_ignore, 0},
cf869cce 902 {"long", m68k_elf_cons, 4},
252b5132
RH		 903#endif
904 {"extend", float_cons, 'x'},
905 {"ldouble", float_cons, 'x'},
906
266abb8f
NS		 907 {"arch", s_m68k_arch, 0},
908 {"cpu", s_m68k_cpu, 0},
909
252b5132
RH		 910 /* The following pseudo-ops are supported for MRI compatibility. */
911 {"chip", s_chip, 0},
912 {"comline", s_space, 1},
913 {"fopt", s_fopt, 0},
914 {"mask2", s_ignore, 0},
915 {"opt", s_opt, 0},
916 {"reg", s_reg, 0},
917 {"restore", s_restore, 0},
918 {"save", s_save, 0},
919
920 {"if", s_mri_if, 0},
921 {"if.b", s_mri_if, 'b'},
922 {"if.w", s_mri_if, 'w'},
923 {"if.l", s_mri_if, 'l'},
924 {"else", s_mri_else, 0},
925 {"else.s", s_mri_else, 's'},
926 {"else.l", s_mri_else, 'l'},
927 {"endi", s_mri_endi, 0},
928 {"break", s_mri_break, 0},
929 {"break.s", s_mri_break, 's'},
930 {"break.l", s_mri_break, 'l'},
931 {"next", s_mri_next, 0},
932 {"next.s", s_mri_next, 's'},
933 {"next.l", s_mri_next, 'l'},
934 {"for", s_mri_for, 0},
935 {"for.b", s_mri_for, 'b'},
936 {"for.w", s_mri_for, 'w'},
937 {"for.l", s_mri_for, 'l'},
938 {"endf", s_mri_endf, 0},
939 {"repeat", s_mri_repeat, 0},
940 {"until", s_mri_until, 0},
941 {"until.b", s_mri_until, 'b'},
942 {"until.w", s_mri_until, 'w'},
943 {"until.l", s_mri_until, 'l'},
944 {"while", s_mri_while, 0},
945 {"while.b", s_mri_while, 'b'},
946 {"while.w", s_mri_while, 'w'},
947 {"while.l", s_mri_while, 'l'},
948 {"endw", s_mri_endw, 0},
949
950 {0, 0, 0}
951};
952
252b5132 953/* The mote pseudo ops are put into the opcode table, since they
31302357 954 don't start with a . they look like opcodes to gas. */
252b5132 955
5a38dc70 956const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 957{
958
959 {"dcl", cons, 4},
960 {"dc", cons, 2},
961 {"dcw", cons, 2},
962 {"dcb", cons, 1},
963
964 {"dsl", s_space, 4},
965 {"ds", s_space, 2},
966 {"dsw", s_space, 2},
967 {"dsb", s_space, 1},
968
969 {"xdef", s_globl, 0},
970#ifdef OBJ_ELF
971 {"align", s_align_bytes, 0},
972#else
973 {"align", s_align_ptwo, 0},
974#endif
975#ifdef M68KCOFF
976 {"sect", obj_coff_section, 0},
977 {"section", obj_coff_section, 0},
978#endif
979 {0, 0, 0}
980};
981
bd17c2c3
AM		 982/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
983 gives identical results to a 32-bit host. */
984#define TRUNC(X) ((valueT) (X) & 0xffffffff)
985#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
986
987#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
988#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
989#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
990#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
991
992#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
993#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 994#define islong(x) (1)
995
252b5132
RH		 996static char notend_table[256];
997static char alt_notend_table[256];
998#define notend(s) \
999 (! (notend_table[(unsigned char) *s] \
1000 || (*s == ':' \
1001 && alt_notend_table[(unsigned char) s[1]])))
1002
252b5132
RH		 1003#ifdef OBJ_ELF
1004
c801568a
AM		 1005/* Return zero if the reference to SYMBOL from within the same segment may
1006 be relaxed. */
1007
1008/* On an ELF system, we can't relax an externally visible symbol,
1009 because it may be overridden by a shared library. However, if
1010 TARGET_OS is "elf", then we presume that we are assembling for an
1011 embedded system, in which case we don't have to worry about shared
1012 libraries, and we can relax any external sym. */
1013
1014#define relaxable_symbol(symbol) \
6358301e 1015 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 1016 || S_IS_WEAK (symbol)))
1017
252b5132
RH		 1018/* Compute the relocation code for a fixup of SIZE bytes, using pc
1019 relative relocation if PCREL is non-zero. PIC says whether a special
1020 pic relocation was requested. */
1021
252b5132 1022static bfd_reloc_code_real_type
31302357 1023get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 1024{
1025 switch (pic)
1026 {
1027 case pic_got_pcrel:
1028 switch (size)
1029 {
1030 case 1:
1031 return BFD_RELOC_8_GOT_PCREL;
1032 case 2:
1033 return BFD_RELOC_16_GOT_PCREL;
1034 case 4:
1035 return BFD_RELOC_32_GOT_PCREL;
1036 }
1037 break;
1038
1039 case pic_got_off:
1040 switch (size)
1041 {
1042 case 1:
1043 return BFD_RELOC_8_GOTOFF;
1044 case 2:
1045 return BFD_RELOC_16_GOTOFF;
1046 case 4:
1047 return BFD_RELOC_32_GOTOFF;
1048 }
1049 break;
1050
1051 case pic_plt_pcrel:
1052 switch (size)
1053 {
1054 case 1:
1055 return BFD_RELOC_8_PLT_PCREL;
1056 case 2:
1057 return BFD_RELOC_16_PLT_PCREL;
1058 case 4:
1059 return BFD_RELOC_32_PLT_PCREL;
1060 }
1061 break;
1062
1063 case pic_plt_off:
1064 switch (size)
1065 {
1066 case 1:
1067 return BFD_RELOC_8_PLTOFF;
1068 case 2:
1069 return BFD_RELOC_16_PLTOFF;
1070 case 4:
1071 return BFD_RELOC_32_PLTOFF;
1072 }
1073 break;
1074
cf869cce
NC		 1075 case pic_tls_gd:
1076 switch (size)
1077 {
1078 case 1:
1079 return BFD_RELOC_68K_TLS_GD8;
1080 case 2:
1081 return BFD_RELOC_68K_TLS_GD16;
1082 case 4:
1083 return BFD_RELOC_68K_TLS_GD32;
1084 }
1085 break;
1086
1087 case pic_tls_ldm:
1088 switch (size)
1089 {
1090 case 1:
1091 return BFD_RELOC_68K_TLS_LDM8;
1092 case 2:
1093 return BFD_RELOC_68K_TLS_LDM16;
1094 case 4:
1095 return BFD_RELOC_68K_TLS_LDM32;
1096 }
1097 break;
1098
1099 case pic_tls_ldo:
1100 switch (size)
1101 {
1102 case 1:
1103 return BFD_RELOC_68K_TLS_LDO8;
1104 case 2:
1105 return BFD_RELOC_68K_TLS_LDO16;
1106 case 4:
1107 return BFD_RELOC_68K_TLS_LDO32;
1108 }
1109 break;
1110
1111 case pic_tls_ie:
1112 switch (size)
1113 {
1114 case 1:
1115 return BFD_RELOC_68K_TLS_IE8;
1116 case 2:
1117 return BFD_RELOC_68K_TLS_IE16;
1118 case 4:
1119 return BFD_RELOC_68K_TLS_IE32;
1120 }
1121 break;
1122
1123 case pic_tls_le:
1124 switch (size)
1125 {
1126 case 1:
1127 return BFD_RELOC_68K_TLS_LE8;
1128 case 2:
1129 return BFD_RELOC_68K_TLS_LE16;
1130 case 4:
1131 return BFD_RELOC_68K_TLS_LE32;
1132 }
1133 break;
1134
252b5132
RH		 1135 case pic_none:
1136 if (pcrel)
1137 {
1138 switch (size)
1139 {
1140 case 1:
1141 return BFD_RELOC_8_PCREL;
1142 case 2:
1143 return BFD_RELOC_16_PCREL;
1144 case 4:
1145 return BFD_RELOC_32_PCREL;
1146 }
1147 }
1148 else
1149 {
1150 switch (size)
1151 {
1152 case 1:
1153 return BFD_RELOC_8;
1154 case 2:
1155 return BFD_RELOC_16;
1156 case 4:
1157 return BFD_RELOC_32;
1158 }
1159 }
1160 }
1161
1162 if (pcrel)
1163 {
1164 if (pic == pic_none)
1165 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1166 else
1167 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1168 }
1169 else
1170 {
1171 if (pic == pic_none)
1172 as_bad (_("Can not do %d byte relocation"), size);
1173 else
1174 as_bad (_("Can not do %d byte pic relocation"), size);
1175 }
1176
1177 return BFD_RELOC_NONE;
1178}
1179
1180/* Here we decide which fixups can be adjusted to make them relative
1181 to the beginning of the section instead of the symbol. Basically
1182 we need to make sure that the dynamic relocations are done
1183 correctly, so in some cases we force the original symbol to be
1184 used. */
1185int
31302357 1186tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1187{
36759679 1188 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1189 switch (fixP->fx_r_type)
1190 {
1191 case BFD_RELOC_8_GOT_PCREL:
1192 case BFD_RELOC_16_GOT_PCREL:
1193 case BFD_RELOC_32_GOT_PCREL:
1194 case BFD_RELOC_8_GOTOFF:
1195 case BFD_RELOC_16_GOTOFF:
1196 case BFD_RELOC_32_GOTOFF:
1197 case BFD_RELOC_8_PLT_PCREL:
1198 case BFD_RELOC_16_PLT_PCREL:
1199 case BFD_RELOC_32_PLT_PCREL:
1200 case BFD_RELOC_8_PLTOFF:
1201 case BFD_RELOC_16_PLTOFF:
1202 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1203 case BFD_RELOC_68K_TLS_GD32:
1204 case BFD_RELOC_68K_TLS_GD16:
1205 case BFD_RELOC_68K_TLS_GD8:
1206 case BFD_RELOC_68K_TLS_LDM32:
1207 case BFD_RELOC_68K_TLS_LDM16:
1208 case BFD_RELOC_68K_TLS_LDM8:
1209 case BFD_RELOC_68K_TLS_LDO32:
1210 case BFD_RELOC_68K_TLS_LDO16:
1211 case BFD_RELOC_68K_TLS_LDO8:
1212 case BFD_RELOC_68K_TLS_IE32:
1213 case BFD_RELOC_68K_TLS_IE16:
1214 case BFD_RELOC_68K_TLS_IE8:
1215 case BFD_RELOC_68K_TLS_LE32:
1216 case BFD_RELOC_68K_TLS_LE16:
1217 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1218 return 0;
1219
1220 case BFD_RELOC_VTABLE_INHERIT:
1221 case BFD_RELOC_VTABLE_ENTRY:
1222 return 0;
1223
1224 default:
1225 return 1;
1226 }
1227}
1228
1229#else /* !OBJ_ELF */
1230
1231#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1232
22184a77
NC		 1233/* PR gas/3041 Weak symbols are not relaxable
1234 because they must be treated as extern. */
1235#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1236
252b5132
RH		 1237#endif /* OBJ_ELF */
1238
252b5132 1239arelent *
31302357 1240tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1241{
1242 arelent *reloc;
1243 bfd_reloc_code_real_type code;
1244
8ec6253e
NC		 1245 /* If the tcbit is set, then this was a fixup of a negative value
1246 that was never resolved. We do not have a reloc to handle this,
1247 so just return. We assume that other code will have detected this
1248 situation and produced a helpful error message, so we just tell the
1249 user that the reloc cannot be produced. */
252b5132 1250 if (fixp->fx_tcbit)
8ec6253e
NC		 1251 {
1252 if (fixp->fx_addsy)
b091f402
AM		 1253 as_bad_where (fixp->fx_file, fixp->fx_line,
1254 _("Unable to produce reloc against symbol '%s'"),
1255 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1256 return NULL;
1257 }
252b5132
RH		 1258
1259 if (fixp->fx_r_type != BFD_RELOC_NONE)
1260 {
1261 code = fixp->fx_r_type;
1262
1263 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1264 that fixup_segment converted a non-PC relative reloc into a
1265 PC relative reloc. In such a case, we need to convert the
1266 reloc code. */
1267 if (fixp->fx_pcrel)
1268 {
1269 switch (code)
1270 {
1271 case BFD_RELOC_8:
1272 code = BFD_RELOC_8_PCREL;
1273 break;
1274 case BFD_RELOC_16:
1275 code = BFD_RELOC_16_PCREL;
1276 break;
1277 case BFD_RELOC_32:
1278 code = BFD_RELOC_32_PCREL;
1279 break;
1280 case BFD_RELOC_8_PCREL:
1281 case BFD_RELOC_16_PCREL:
1282 case BFD_RELOC_32_PCREL:
1283 case BFD_RELOC_8_GOT_PCREL:
1284 case BFD_RELOC_16_GOT_PCREL:
1285 case BFD_RELOC_32_GOT_PCREL:
1286 case BFD_RELOC_8_GOTOFF:
1287 case BFD_RELOC_16_GOTOFF:
1288 case BFD_RELOC_32_GOTOFF:
1289 case BFD_RELOC_8_PLT_PCREL:
1290 case BFD_RELOC_16_PLT_PCREL:
1291 case BFD_RELOC_32_PLT_PCREL:
1292 case BFD_RELOC_8_PLTOFF:
1293 case BFD_RELOC_16_PLTOFF:
1294 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1295 case BFD_RELOC_68K_TLS_GD32:
1296 case BFD_RELOC_68K_TLS_GD16:
1297 case BFD_RELOC_68K_TLS_GD8:
1298 case BFD_RELOC_68K_TLS_LDM32:
1299 case BFD_RELOC_68K_TLS_LDM16:
1300 case BFD_RELOC_68K_TLS_LDM8:
1301 case BFD_RELOC_68K_TLS_LDO32:
1302 case BFD_RELOC_68K_TLS_LDO16:
1303 case BFD_RELOC_68K_TLS_LDO8:
1304 case BFD_RELOC_68K_TLS_IE32:
1305 case BFD_RELOC_68K_TLS_IE16:
1306 case BFD_RELOC_68K_TLS_IE8:
1307 case BFD_RELOC_68K_TLS_LE32:
1308 case BFD_RELOC_68K_TLS_LE16:
1309 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1310 break;
1311 default:
1312 as_bad_where (fixp->fx_file, fixp->fx_line,
1313 _("Cannot make %s relocation PC relative"),
1314 bfd_get_reloc_code_name (code));
1315 }
1316 }
1317 }
1318 else
1319 {
1320#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1321 switch (F (fixp->fx_size, fixp->fx_pcrel))
1322 {
1323#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1324 MAP (1, 0, BFD_RELOC_8);
1325 MAP (2, 0, BFD_RELOC_16);
1326 MAP (4, 0, BFD_RELOC_32);
1327 MAP (1, 1, BFD_RELOC_8_PCREL);
1328 MAP (2, 1, BFD_RELOC_16_PCREL);
1329 MAP (4, 1, BFD_RELOC_32_PCREL);
1330 default:
1331 abort ();
1332 }
1333 }
1334#undef F
1335#undef MAP
1336
1337 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1338 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1339 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1340 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1341#ifndef OBJ_ELF
33f0727f
NC		 1342 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1343 && fixp->fx_addsy
1344 && S_IS_WEAK (fixp->fx_addsy)
1345 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
b2b74248
NC		 1346 {
1347 /* PR gas/3041 References to weak symbols must be treated as extern
1348 in order to be overridable by the linker, even if they are defined
1349 in the same object file. So the original addend must be written
1350 "as is" into the output section without further processing.
1351 The addend value must be hacked here in order to force
1352 bfd_install_relocation() to write the original value into the
1353 output section.
1354 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1355 value has already been added to the addend in fixup_segment(). We
1356 have to remove it.
1357 2) bfd_install_relocation() will incorrectly treat this symbol as
1358 resolved, so it will write the symbol value plus its addend and
1359 section VMA. As a workaround we can tweak the addend value here in
1360 order to get the original value in the section after the call to
1361 bfd_install_relocation(). */
1362 reloc->addend = fixp->fx_addnumber
1363 /* Fix because of MD_APPLY_SYM_VALUE() */
1364 - S_GET_VALUE (fixp->fx_addsy)
1365 /* Fix for bfd_install_relocation() */
1366 - (S_GET_VALUE (fixp->fx_addsy)
1367 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1368 }
33f0727f
NC		 1369 else if (fixp->fx_pcrel)
1370 reloc->addend = fixp->fx_addnumber;
252b5132
RH		 1371 else
1372 reloc->addend = 0;
1373#else
1374 if (!fixp->fx_pcrel)
1375 reloc->addend = fixp->fx_addnumber;
1376 else
1377 reloc->addend = (section->vma
552c607f 1378 + fixp->fx_pcrel_adjust
252b5132
RH		 1379 + fixp->fx_addnumber
1380 + md_pcrel_from (fixp));
1381#endif
1382
1383 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1384 gas_assert (reloc->howto != 0);
252b5132
RH		 1385
1386 return reloc;
1387}
1388
252b5132
RH		 1389/* Handle of the OPCODE hash table. NULL means any use before
1390 m68k_ip_begin() will crash. */
1391static struct hash_control *op_hash;
1392\f
1393/* Assemble an m68k instruction. */
1394
1395static void
31302357 1396m68k_ip (char *instring)
252b5132
RH		 1397{
1398 register char *p;
1399 register struct m68k_op *opP;
1400 register const struct m68k_incant *opcode;
1401 register const char *s;
1402 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1403 char *pdot, *pdotmove;
1404 enum m68k_size siz1, siz2;
1405 char c;
1406 int losing;
1407 int opsfound;
03b13e59 1408 struct m68k_op operands_backup[6];
252b5132
RH		 1409 LITTLENUM_TYPE words[6];
1410 LITTLENUM_TYPE *wordp;
1411 unsigned long ok_arch = 0;
1412
1413 if (*instring == ' ')
36759679 1414 instring++; /* Skip leading whitespace. */
252b5132
RH		 1415
1416 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1417 or exactly 1 space. */
252b5132
RH		 1418 pdot = 0;
1419 for (p = instring; *p != '\0'; p++)
1420 {
1421 if (*p == ' ')
1422 break;
1423 if (*p == '.')
1424 pdot = p;
1425 }
1426
1427 if (p == instring)
1428 {
1429 the_ins.error = _("No operator");
1430 return;
1431 }
1432
1433 /* p now points to the end of the opcode name, probably whitespace.
1434 Make sure the name is null terminated by clobbering the
1435 whitespace, look it up in the hash table, then fix it back.
1436 Remove a dot, first, since the opcode tables have none. */
1437 if (pdot != NULL)
1438 {
1439 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1440 *pdotmove = pdotmove[1];
1441 p--;
1442 }
1443
1444 c = *p;
1445 *p = '\0';
1446 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1447 *p = c;
1448
1449 if (pdot != NULL)
1450 {
1451 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1452 *pdotmove = pdotmove[-1];
1453 *pdot = '.';
1454 ++p;
1455 }
1456
1457 if (opcode == NULL)
1458 {
1459 the_ins.error = _("Unknown operator");
1460 return;
1461 }
1462
36759679 1463 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1464 while (*p == ' ')
1465 ++p;
1466
1467 if (opcode->m_operands == 0)
1468 {
1469 char *old = input_line_pointer;
1470 *old = '\n';
1471 input_line_pointer = p;
36759679 1472 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1473 mote_pseudo_table[opcode->m_opnum].poc_handler
1474 (mote_pseudo_table[opcode->m_opnum].poc_val);
1475 input_line_pointer = old;
1476 *old = 0;
1477
1478 return;
1479 }
1480
1481 if (flag_mri && opcode->m_opnum == 0)
1482 {
1483 /* In MRI mode, random garbage is allowed after an instruction
1484 which accepts no operands. */
1485 the_ins.args = opcode->m_operands;
1486 the_ins.numargs = opcode->m_opnum;
1487 the_ins.numo = opcode->m_codenum;
1488 the_ins.opcode[0] = getone (opcode);
1489 the_ins.opcode[1] = gettwo (opcode);
1490 return;
1491 }
1492
1493 for (opP = &the_ins.operands[0]; *p; opP++)
1494 {
1495 p = crack_operand (p, opP);
1496
1497 if (opP->error)
1498 {
1499 the_ins.error = opP->error;
1500 return;
1501 }
1502 }
1503
1504 opsfound = opP - &the_ins.operands[0];
1505
1506 /* This ugly hack is to support the floating pt opcodes in their
1507 standard form. Essentially, we fake a first enty of type COP#1 */
1508 if (opcode->m_operands[0] == 'I')
1509 {
1510 int n;
1511
1512 for (n = opsfound; n > 0; --n)
1513 the_ins.operands[n] = the_ins.operands[n - 1];
1514
31302357 1515 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1516 the_ins.operands[0].mode = CONTROL;
1517 the_ins.operands[0].reg = m68k_float_copnum;
1518 opsfound++;
1519 }
1520
36759679 1521 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1522 for (losing = 0;;)
1523 {
1524 /* If we didn't get the right number of ops, or we have no
92774660 1525 common model with this pattern then reject this pattern. */
252b5132
RH		 1526
1527 ok_arch |= opcode->m_arch;
1528 if (opsfound != opcode->m_opnum
1529 || ((opcode->m_arch & current_architecture) == 0))
1530 ++losing;
1531 else
1532 {
03b13e59
NC		 1533 int i;
1534
1535 /* Make a copy of the operands of this insn so that
1536 we can modify them safely, should we want to. */
9c2799c2 1537 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1538 for (i = 0; i < opsfound; i++)
1539 operands_backup[i] = the_ins.operands[i];
1540
1541 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1542 *s && !losing;
1543 s += 2, opP++)
1544 {
1545 /* Warning: this switch is huge! */
1546 /* I've tried to organize the cases into this order:
1547 non-alpha first, then alpha by letter. Lower-case
1548 goes directly before uppercase counterpart. */
1549 /* Code with multiple case ...: gets sorted by the lowest
1550 case ... it belongs to. I hope this makes sense. */
1551 switch (*s)
1552 {
1553 case '!':
1554 switch (opP->mode)
1555 {
1556 case IMMED:
1557 case DREG:
1558 case AREG:
1559 case FPREG:
1560 case CONTROL:
1561 case AINC:
1562 case ADEC:
1563 case REGLST:
1564 losing++;
1565 break;
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 case '<':
1572 switch (opP->mode)
1573 {
1574 case DREG:
1575 case AREG:
1576 case FPREG:
1577 case CONTROL:
1578 case IMMED:
1579 case ADEC:
1580 case REGLST:
1581 losing++;
1582 break;
1583 default:
1584 break;
1585 }
1586 break;
1587
1588 case '>':
1589 switch (opP->mode)
1590 {
1591 case DREG:
1592 case AREG:
1593 case FPREG:
1594 case CONTROL:
1595 case IMMED:
1596 case AINC:
1597 case REGLST:
1598 losing++;
1599 break;
1600 case ABSL:
1601 break;
1602 default:
1603 if (opP->reg == PC
1604 || opP->reg == ZPC)
1605 losing++;
1606 break;
1607 }
1608 break;
1609
1610 case 'm':
1611 switch (opP->mode)
1612 {
1613 case DREG:
1614 case AREG:
1615 case AINDR:
1616 case AINC:
1617 case ADEC:
1618 break;
1619 default:
1620 losing++;
1621 }
8a104df9 1622 break;
252b5132
RH		 1623
1624 case 'n':
1625 switch (opP->mode)
1626 {
1627 case DISP:
1628 break;
1629 default:
1630 losing++;
1631 }
8a104df9 1632 break;
252b5132
RH		 1633
1634 case 'o':
1635 switch (opP->mode)
1636 {
1637 case BASE:
1638 case ABSL:
1639 case IMMED:
1640 break;
1641 default:
1642 losing++;
1643 }
8a104df9 1644 break;
252b5132
RH		 1645
1646 case 'p':
1647 switch (opP->mode)
1648 {
1649 case DREG:
1650 case AREG:
1651 case AINDR:
1652 case AINC:
1653 case ADEC:
1654 break;
1655 case DISP:
1656 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1657 losing++;
252b5132
RH		 1658 break;
1659 default:
1660 losing++;
1661 }
8a104df9 1662 break;
252b5132
RH		 1663
1664 case 'q':
1665 switch (opP->mode)
1666 {
1667 case DREG:
1668 case AINDR:
1669 case AINC:
1670 case ADEC:
1671 break;
1672 case DISP:
1673 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1674 losing++;
252b5132
RH		 1675 break;
1676 default:
1677 losing++;
1678 break;
1679 }
8a104df9 1680 break;
252b5132
RH		 1681
1682 case 'v':
1683 switch (opP->mode)
1684 {
1685 case DREG:
1686 case AINDR:
1687 case AINC:
1688 case ADEC:
1689 case ABSL:
1690 break;
1691 case DISP:
1692 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1693 losing++;
252b5132
RH		 1694 break;
1695 default:
1696 losing++;
1697 break;
1698 }
1699 break;
1700
1701 case '#':
1702 if (opP->mode != IMMED)
1703 losing++;
1704 else if (s[1] == 'b'
1705 && ! isvar (&opP->disp)
1706 && (opP->disp.exp.X_op != O_constant
1707 || ! isbyte (opP->disp.exp.X_add_number)))
1708 losing++;
1709 else if (s[1] == 'B'
1710 && ! isvar (&opP->disp)
1711 && (opP->disp.exp.X_op != O_constant
1712 || ! issbyte (opP->disp.exp.X_add_number)))
1713 losing++;
1714 else if (s[1] == 'w'
1715 && ! isvar (&opP->disp)
1716 && (opP->disp.exp.X_op != O_constant
1717 || ! isword (opP->disp.exp.X_add_number)))
1718 losing++;
1719 else if (s[1] == 'W'
1720 && ! isvar (&opP->disp)
1721 && (opP->disp.exp.X_op != O_constant
1722 || ! issword (opP->disp.exp.X_add_number)))
1723 losing++;
1724 break;
1725
1726 case '^':
1727 case 'T':
1728 if (opP->mode != IMMED)
1729 losing++;
1730 break;
1731
1732 case '$':
1733 if (opP->mode == AREG
1734 || opP->mode == CONTROL
1735 || opP->mode == FPREG
1736 || opP->mode == IMMED
1737 || opP->mode == REGLST
1738 || (opP->mode != ABSL
1739 && (opP->reg == PC
1740 || opP->reg == ZPC)))
1741 losing++;
1742 break;
1743
1744 case '%':
1745 if (opP->mode == CONTROL
1746 || opP->mode == FPREG
1747 || opP->mode == REGLST
1748 || opP->mode == IMMED
1749 || (opP->mode != ABSL
1750 && (opP->reg == PC
1751 || opP->reg == ZPC)))
1752 losing++;
1753 break;
1754
1755 case '&':
1756 switch (opP->mode)
1757 {
1758 case DREG:
1759 case AREG:
1760 case FPREG:
1761 case CONTROL:
1762 case IMMED:
1763 case AINC:
1764 case ADEC:
1765 case REGLST:
1766 losing++;
1767 break;
1768 case ABSL:
1769 break;
1770 default:
1771 if (opP->reg == PC
1772 || opP->reg == ZPC)
1773 losing++;
1774 break;
1775 }
1776 break;
1777
1778 case '*':
1779 if (opP->mode == CONTROL
1780 || opP->mode == FPREG
1781 || opP->mode == REGLST)
1782 losing++;
1783 break;
1784
1785 case '+':
1786 if (opP->mode != AINC)
1787 losing++;
1788 break;
1789
1790 case '-':
1791 if (opP->mode != ADEC)
1792 losing++;
1793 break;
1794
1795 case '/':
1796 switch (opP->mode)
1797 {
1798 case AREG:
1799 case CONTROL:
1800 case FPREG:
1801 case AINC:
1802 case ADEC:
1803 case IMMED:
1804 case REGLST:
1805 losing++;
1806 break;
1807 default:
1808 break;
1809 }
1810 break;
1811
1812 case ';':
1813 switch (opP->mode)
1814 {
1815 case AREG:
1816 case CONTROL:
1817 case FPREG:
1818 case REGLST:
1819 losing++;
1820 break;
1821 default:
1822 break;
1823 }
1824 break;
1825
1826 case '?':
1827 switch (opP->mode)
1828 {
1829 case AREG:
1830 case CONTROL:
1831 case FPREG:
1832 case AINC:
1833 case ADEC:
1834 case IMMED:
1835 case REGLST:
1836 losing++;
1837 break;
1838 case ABSL:
1839 break;
1840 default:
1841 if (opP->reg == PC || opP->reg == ZPC)
1842 losing++;
1843 break;
1844 }
1845 break;
1846
1847 case '@':
1848 switch (opP->mode)
1849 {
1850 case AREG:
1851 case CONTROL:
1852 case FPREG:
1853 case IMMED:
1854 case REGLST:
1855 losing++;
1856 break;
1857 default:
1858 break;
1859 }
1860 break;
1861
1862 case '~': /* For now! (JF FOO is this right?) */
1863 switch (opP->mode)
1864 {
1865 case DREG:
1866 case AREG:
1867 case CONTROL:
1868 case FPREG:
1869 case IMMED:
1870 case REGLST:
1871 losing++;
1872 break;
1873 case ABSL:
1874 break;
1875 default:
1876 if (opP->reg == PC
1877 || opP->reg == ZPC)
1878 losing++;
1879 break;
1880 }
1881 break;
1882
1883 case '3':
1884 if (opP->mode != CONTROL
1885 || (opP->reg != TT0 && opP->reg != TT1))
1886 losing++;
1887 break;
1888
1889 case 'A':
1890 if (opP->mode != AREG)
1891 losing++;
1892 break;
1893
1894 case 'a':
1895 if (opP->mode != AINDR)
1896 ++losing;
1897 break;
1898
fd99574b
NC		 1899 case '4':
1900 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1901 && (opP->mode != DISP
1902 || opP->reg < ADDR0
1903 || opP->reg > ADDR7))
1904 ++losing;
1905 break;
1906
252b5132
RH		 1907 case 'B': /* FOO */
1908 if (opP->mode != ABSL
1909 || (flag_long_jumps
1910 && strncmp (instring, "jbsr", 4) == 0))
1911 losing++;
1912 break;
1913
3e602632
NC		 1914 case 'b':
1915 switch (opP->mode)
1916 {
1917 case IMMED:
1918 case ABSL:
1919 case AREG:
1920 case FPREG:
1921 case CONTROL:
1922 case POST:
1923 case PRE:
1924 case REGLST:
1925 losing++;
1926 break;
1927 default:
1928 break;
1929 }
1930 break;
1931
252b5132
RH		 1932 case 'C':
1933 if (opP->mode != CONTROL || opP->reg != CCR)
1934 losing++;
1935 break;
1936
1937 case 'd':
1938 if (opP->mode != DISP
1939 || opP->reg < ADDR0
1940 || opP->reg > ADDR7)
1941 losing++;
1942 break;
1943
1944 case 'D':
1945 if (opP->mode != DREG)
1946 losing++;
1947 break;
1948
6da466c7
ILT		 1949 case 'E':
1950 if (opP->reg != ACC)
1951 losing++;
1952 break;
1953
fd99574b
NC		 1954 case 'e':
1955 if (opP->reg != ACC && opP->reg != ACC1
1956 && opP->reg != ACC2 && opP->reg != ACC3)
1957 losing++;
1958 break;
1959
252b5132
RH		 1960 case 'F':
1961 if (opP->mode != FPREG)
1962 losing++;
1963 break;
1964
6da466c7
ILT		 1965 case 'G':
1966 if (opP->reg != MACSR)
1967 losing++;
1968 break;
1969
fd99574b
NC		 1970 case 'g':
1971 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1972 losing++;
1973 break;
1974
6da466c7
ILT		 1975 case 'H':
1976 if (opP->reg != MASK)
1977 losing++;
1978 break;
1979
252b5132
RH		 1980 case 'I':
1981 if (opP->mode != CONTROL
1982 || opP->reg < COP0
1983 || opP->reg > COP7)
1984 losing++;
1985 break;
1986
fd99574b
NC		 1987 case 'i':
1988 if (opP->mode != LSH && opP->mode != RSH)
1989 losing++;
1990 break;
1991
252b5132
RH		 1992 case 'J':
1993 if (opP->mode != CONTROL
1994 || opP->reg < USP
0b2e31dc
NS		 1995 || opP->reg > last_movec_reg
1996 || !control_regs)
252b5132
RH		 1997 losing++;
1998 else
1999 {
2000 const enum m68k_register *rp;
0b2e31dc 2001
252b5132 2002 for (rp = control_regs; *rp; rp++)
78336706
NS		 2003 {
2004 if (*rp == opP->reg)
2005 break;
2006 /* In most CPUs RAMBAR refers to control reg
2007 c05 (RAMBAR1), but a few CPUs have it
2008 refer to c04 (RAMBAR0). */
2009 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
2010 {
2011 opP->reg = RAMBAR_ALT;
2012 break;
2013 }
2014 }
252b5132
RH		 2015 if (*rp == 0)
2016 losing++;
2017 }
2018 break;
2019
2020 case 'k':
2021 if (opP->mode != IMMED)
2022 losing++;
2023 break;
2024
2025 case 'l':
2026 case 'L':
2027 if (opP->mode == DREG
2028 || opP->mode == AREG
2029 || opP->mode == FPREG)
2030 {
2031 if (s[1] == '8')
2032 losing++;
2033 else
2034 {
2035 switch (opP->mode)
2036 {
2037 case DREG:
2038 opP->mask = 1 << (opP->reg - DATA0);
2039 break;
2040 case AREG:
2041 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2042 break;
2043 case FPREG:
2044 opP->mask = 1 << (opP->reg - FP0 + 16);
2045 break;
2046 default:
2047 abort ();
2048 }
2049 opP->mode = REGLST;
2050 }
2051 }
2052 else if (opP->mode == CONTROL)
2053 {
2054 if (s[1] != '8')
2055 losing++;
2056 else
2057 {
2058 switch (opP->reg)
2059 {
2060 case FPI:
2061 opP->mask = 1 << 24;
2062 break;
2063 case FPS:
2064 opP->mask = 1 << 25;
2065 break;
2066 case FPC:
2067 opP->mask = 1 << 26;
2068 break;
2069 default:
2070 losing++;
2071 break;
2072 }
2073 opP->mode = REGLST;
2074 }
2075 }
2076 else if (opP->mode != REGLST)
2077 losing++;
2078 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2079 losing++;
2080 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2081 losing++;
2082 break;
2083
2084 case 'M':
2085 if (opP->mode != IMMED)
2086 losing++;
2087 else if (opP->disp.exp.X_op != O_constant
2088 || ! issbyte (opP->disp.exp.X_add_number))
2089 losing++;
2090 else if (! m68k_quick
2091 && instring[3] != 'q'
2092 && instring[4] != 'q')
2093 losing++;
2094 break;
2095
2096 case 'O':
2097 if (opP->mode != DREG
2098 && opP->mode != IMMED
2099 && opP->mode != ABSL)
2100 losing++;
2101 break;
2102
2103 case 'Q':
2104 if (opP->mode != IMMED)
2105 losing++;
2106 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2107 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2108 losing++;
2109 else if (! m68k_quick
2110 && (strncmp (instring, "add", 3) == 0
2111 || strncmp (instring, "sub", 3) == 0)
2112 && instring[3] != 'q')
2113 losing++;
2114 break;
2115
2116 case 'R':
2117 if (opP->mode != DREG && opP->mode != AREG)
2118 losing++;
2119 break;
2120
2121 case 'r':
2122 if (opP->mode != AINDR
2123 && (opP->mode != BASE
2124 || (opP->reg != 0
2125 && opP->reg != ZADDR0)
2126 || opP->disp.exp.X_op != O_absent
2127 || ((opP->index.reg < DATA0
2128 || opP->index.reg > DATA7)
2129 && (opP->index.reg < ADDR0
2130 || opP->index.reg > ADDR7))
2131 || opP->index.size != SIZE_UNSPEC
2132 || opP->index.scale != 1))
2133 losing++;
2134 break;
2135
2136 case 's':
2137 if (opP->mode != CONTROL
2138 || ! (opP->reg == FPI
2139 || opP->reg == FPS
2140 || opP->reg == FPC))
2141 losing++;
2142 break;
2143
2144 case 'S':
2145 if (opP->mode != CONTROL || opP->reg != SR)
2146 losing++;
2147 break;
2148
2149 case 't':
2150 if (opP->mode != IMMED)
2151 losing++;
2152 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2153 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2154 losing++;
2155 break;
2156
2157 case 'U':
2158 if (opP->mode != CONTROL || opP->reg != USP)
2159 losing++;
2160 break;
2161
3e602632
NC		 2162 case 'x':
2163 if (opP->mode != IMMED)
2164 losing++;
2165 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2166 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2167 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2168 losing++;
2169 break;
2170
afa2158f
NS		 2171 case 'j':
2172 if (opP->mode != IMMED)
2173 losing++;
2174 else if (opP->disp.exp.X_op != O_constant
2175 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2176 losing++;
2177 break;
2178
2179 case 'K':
2180 if (opP->mode != IMMED)
2181 losing++;
2182 else if (opP->disp.exp.X_op != O_constant
2183 || TRUNC (opP->disp.exp.X_add_number) > 511)
2184 losing++;
2185 break;
2186
252b5132
RH		 2187 /* JF these are out of order. We could put them
2188 in order if we were willing to put up with
2189 bunches of #ifdef m68851s in the code.
2190
2191 Don't forget that you need these operands
2192 to use 68030 MMU instructions. */
2193#ifndef NO_68851
36759679 2194 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2195 case '|':
2196 if (opP->mode == CONTROL
2197 || opP->mode == FPREG
2198 || opP->mode == DREG
2199 || opP->mode == AREG
2200 || opP->mode == REGLST)
2201 losing++;
2202 /* We should accept immediate operands, but they
2203 supposedly have to be quad word, and we don't
2204 handle that. I would like to see what a Motorola
2205 assembler does before doing something here. */
2206 if (opP->mode == IMMED)
2207 losing++;
2208 break;
2209
2210 case 'f':
2211 if (opP->mode != CONTROL
2212 || (opP->reg != SFC && opP->reg != DFC))
2213 losing++;
2214 break;
2215
2216 case '0':
2217 if (opP->mode != CONTROL || opP->reg != TC)
2218 losing++;
2219 break;
2220
2221 case '1':
2222 if (opP->mode != CONTROL || opP->reg != AC)
2223 losing++;
2224 break;
2225
2226 case '2':
2227 if (opP->mode != CONTROL
2228 || (opP->reg != CAL
2229 && opP->reg != VAL
2230 && opP->reg != SCC))
2231 losing++;
2232 break;
2233
2234 case 'V':
2235 if (opP->mode != CONTROL
2236 || opP->reg != VAL)
2237 losing++;
2238 break;
2239
2240 case 'W':
2241 if (opP->mode != CONTROL
2242 || (opP->reg != DRP
2243 && opP->reg != SRP
2244 && opP->reg != CRP))
2245 losing++;
2246 break;
2247
3e602632
NC		 2248 case 'w':
2249 switch (opP->mode)
2250 {
2251 case IMMED:
2252 case ABSL:
2253 case AREG:
2254 case DREG:
2255 case FPREG:
2256 case CONTROL:
2257 case POST:
2258 case PRE:
2259 case REGLST:
2260 losing++;
2261 break;
2262 default:
2263 break;
2264 }
2265 break;
2266
252b5132
RH		 2267 case 'X':
2268 if (opP->mode != CONTROL
2269 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2270 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2271 losing++;
2272 break;
2273
2274 case 'Y':
2275 if (opP->mode != CONTROL || opP->reg != PSR)
2276 losing++;
2277 break;
2278
2279 case 'Z':
2280 if (opP->mode != CONTROL || opP->reg != PCSR)
2281 losing++;
2282 break;
2283#endif
2284 case 'c':
2285 if (opP->mode != CONTROL
2286 || (opP->reg != NC
2287 && opP->reg != IC
2288 && opP->reg != DC
2289 && opP->reg != BC))
36759679 2290 losing++;
252b5132
RH		 2291 break;
2292
2293 case '_':
2294 if (opP->mode != ABSL)
2295 ++losing;
2296 break;
2297
6da466c7
ILT		 2298 case 'u':
2299 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2300 losing++;
2301 /* FIXME: kludge instead of fixing parser:
2302 upper/lower registers are *not* CONTROL
92774660 2303 registers, but ordinary ones. */
6da466c7
ILT		 2304 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2305 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2306 opP->mode = DREG;
2307 else
2308 opP->mode = AREG;
2309 break;
2310
3e602632
NC		 2311 case 'y':
2312 if (!(opP->mode == AINDR
31302357
AS		 2313 || (opP->mode == DISP
2314 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2315 losing++;
2316 break;
2317
2318 case 'z':
2319 if (!(opP->mode == AINDR || opP->mode == DISP))
2320 losing++;
2321 break;
2322
252b5132
RH		 2323 default:
2324 abort ();
36759679 2325 }
252b5132
RH		 2326
2327 if (losing)
2328 break;
36759679 2329 }
03b13e59
NC		 2330
2331 /* Since we have found the correct instruction, copy
2332 in the modifications that we may have made. */
2333 if (!losing)
2334 for (i = 0; i < opsfound; i++)
2335 the_ins.operands[i] = operands_backup[i];
36759679 2336 }
252b5132
RH		 2337
2338 if (!losing)
36759679 2339 break;
252b5132
RH		 2340
2341 opcode = opcode->m_next;
2342
2343 if (!opcode)
2344 {
2345 if (ok_arch
2346 && !(ok_arch & current_architecture))
2347 {
6d89cc8f
NS		 2348 const struct m68k_cpu *cpu;
2349 int any = 0;
2350 size_t space = 400;
2351 char *buf = xmalloc (space + 1);
2352 size_t len;
2353 int paren = 1;
2354
2355 the_ins.error = buf;
2356 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2357 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2358 buf[space] = 0;
2359#define APPEND(STRING) \
2360 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2361
2362 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2363 switch (ok_arch)
2364 {
6b6e92f4 2365 case mcfisa_a:
b2f58c0c 2366 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2367 break;
2368 case mcfhwdiv:
b2f58c0c
NC		 2369 APPEND ("ColdFire ");
2370 APPEND (_("hardware divide"));
6b6e92f4
NC		 2371 break;
2372 case mcfisa_aa:
b2f58c0c 2373 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2374 break;
2375 case mcfisa_b:
b2f58c0c 2376 APPEND ("ColdFire ISA_B");
6b6e92f4 2377 break;
8d100c32 2378 case mcfisa_c:
b2f58c0c 2379 APPEND ("ColdFire ISA_C");
8d100c32 2380 break;
3e602632 2381 case cfloat:
b2f58c0c 2382 APPEND ("ColdFire fpu");
3e602632 2383 break;
252b5132 2384 case mfloat:
b2f58c0c 2385 APPEND ("M68K fpu");
252b5132
RH		 2386 break;
2387 case mmmu:
b2f58c0c 2388 APPEND ("M68K mmu");
252b5132
RH		 2389 break;
2390 case m68020up:
b2f58c0c
NC		 2391 APPEND ("68020 ");
2392 APPEND (_("or higher"));
252b5132
RH		 2393 break;
2394 case m68000up:
b2f58c0c
NC		 2395 APPEND ("68000 ");
2396 APPEND (_("or higher"));
252b5132
RH		 2397 break;
2398 case m68010up:
b2f58c0c
NC		 2399 APPEND ("68010 ");
2400 APPEND (_("or higher"));
252b5132
RH		 2401 break;
2402 default:
6d89cc8f
NS		 2403 paren = 0;
2404 }
2405 if (paren)
2406 APPEND (" (");
6b6e92f4 2407
6d89cc8f
NS		 2408 for (cpu = m68k_cpus; cpu->name; cpu++)
2409 if (!cpu->alias && (cpu->arch & ok_arch))
2410 {
2411 const struct m68k_cpu *alias;
869ddf2a
NS		 2412 int seen_master = 0;
2413
6d89cc8f
NS		 2414 if (any)
2415 APPEND (", ");
2416 any = 0;
2417 APPEND (cpu->name);
869ddf2a
NS		 2418 for (alias = cpu; alias != m68k_cpus; alias--)
2419 if (alias[-1].alias >= 0)
2420 break;
2421 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2422 {
869ddf2a
NS		 2423 if (!alias->alias)
2424 seen_master = 1;
2425 else
2426 {
2427 if (any)
2428 APPEND (", ");
2429 else
2430 APPEND (" [");
2431 APPEND (alias->name);
2432 any = 1;
2433 }
6d89cc8f 2434 }
869ddf2a
NS		 2435 if (any)
2436 APPEND ("]");
6d89cc8f 2437 any = 1;
252b5132 2438 }
6d89cc8f
NS		 2439 if (paren)
2440 APPEND (")");
2441#undef APPEND
2442 if (!space)
2443 {
b2f58c0c 2444 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2445 with ellipsis. */
2446 buf -= 4;
2447 while (*buf != ' ')
2448 buf--;
2449 strcpy (buf, " ...");
252b5132 2450 }
252b5132
RH		 2451 }
2452 else
2453 the_ins.error = _("operands mismatch");
2454 return;
36759679 2455 }
252b5132
RH		 2456
2457 losing = 0;
2458 }
2459
36759679 2460 /* Now assemble it. */
252b5132
RH		 2461 the_ins.args = opcode->m_operands;
2462 the_ins.numargs = opcode->m_opnum;
2463 the_ins.numo = opcode->m_codenum;
2464 the_ins.opcode[0] = getone (opcode);
2465 the_ins.opcode[1] = gettwo (opcode);
2466
2467 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2468 {
9a2e615a 2469 int have_disp = 0;
cac27205 2470 int use_pl = 0;
9a2e615a 2471
252b5132 2472 /* This switch is a doozy.
31302357 2473 Watch the first step; its a big one! */
252b5132
RH		 2474 switch (s[0])
2475 {
2476
2477 case '*':
2478 case '~':
2479 case '%':
2480 case ';':
2481 case '@':
2482 case '!':
2483 case '&':
2484 case '$':
2485 case '?':
2486 case '/':
2487 case '<':
2488 case '>':
3e602632 2489 case 'b':
252b5132
RH		 2490 case 'm':
2491 case 'n':
2492 case 'o':
2493 case 'p':
2494 case 'q':
2495 case 'v':
3e602632
NC		 2496 case 'w':
2497 case 'y':
2498 case 'z':
fd99574b 2499 case '4':
252b5132
RH		 2500#ifndef NO_68851
2501 case '|':
2502#endif
2503 switch (opP->mode)
2504 {
2505 case IMMED:
2506 tmpreg = 0x3c; /* 7.4 */
2507 if (strchr ("bwl", s[1]))
3e602632 2508 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2509 else
2510 nextword = get_num (&opP->disp, 0);
2511 if (isvar (&opP->disp))
2512 add_fix (s[1], &opP->disp, 0, 0);
2513 switch (s[1])
2514 {
2515 case 'b':
2516 if (!isbyte (nextword))
2517 opP->error = _("operand out of range");
2518 addword (nextword);
2519 baseo = 0;
2520 break;
2521 case 'w':
2522 if (!isword (nextword))
2523 opP->error = _("operand out of range");
2524 addword (nextword);
2525 baseo = 0;
2526 break;
2527 case 'W':
2528 if (!issword (nextword))
2529 opP->error = _("operand out of range");
2530 addword (nextword);
2531 baseo = 0;
2532 break;
2533 case 'l':
2534 addword (nextword >> 16);
2535 addword (nextword);
2536 baseo = 0;
2537 break;
2538
2539 case 'f':
2540 baseo = 2;
2541 outro = 8;
2542 break;
2543 case 'F':
2544 baseo = 4;
2545 outro = 11;
2546 break;
2547 case 'x':
2548 baseo = 6;
2549 outro = 15;
2550 break;
2551 case 'p':
2552 baseo = 6;
2553 outro = -1;
2554 break;
2555 default:
2556 abort ();
2557 }
2558 if (!baseo)
2559 break;
2560
36759679 2561 /* We gotta put out some float. */
252b5132
RH		 2562 if (op (&opP->disp) != O_big)
2563 {
2564 valueT val;
2565 int gencnt;
2566
2567 /* Can other cases happen here? */
2568 if (op (&opP->disp) != O_constant)
2569 abort ();
2570
2571 val = (valueT) offs (&opP->disp);
2572 gencnt = 0;
2573 do
2574 {
2575 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2576 val >>= LITTLENUM_NUMBER_OF_BITS;
2577 ++gencnt;
2578 }
2579 while (val != 0);
2580 offs (&opP->disp) = gencnt;
2581 }
2582 if (offs (&opP->disp) > 0)
2583 {
2584 if (offs (&opP->disp) > baseo)
2585 {
2586 as_warn (_("Bignum too big for %c format; truncated"),
2587 s[1]);
2588 offs (&opP->disp) = baseo;
2589 }
2590 baseo -= offs (&opP->disp);
2591 while (baseo--)
2592 addword (0);
2593 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2594 offs (&opP->disp)--;
2595 --wordp)
2596 addword (*wordp);
2597 break;
2598 }
2599 gen_to_words (words, baseo, (long) outro);
2600 for (wordp = words; baseo--; wordp++)
2601 addword (*wordp);
2602 break;
2603 case DREG:
2604 tmpreg = opP->reg - DATA; /* 0.dreg */
2605 break;
2606 case AREG:
2607 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2608 break;
2609 case AINDR:
2610 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2611 break;
2612 case ADEC:
2613 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2614 break;
2615 case AINC:
2616 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2617 break;
2618 case DISP:
2619
3e602632 2620 nextword = get_num (&opP->disp, 90);
252b5132 2621
580b9172
NC		 2622 /* Convert mode 5 addressing with a zero offset into
2623 mode 2 addressing to reduce the instruction size by a
2624 word. */
2625 if (! isvar (&opP->disp)
2626 && (nextword == 0)
2627 && (opP->disp.size == SIZE_UNSPEC)
2628 && (opP->reg >= ADDR0)
2629 && (opP->reg <= ADDR7))
2630 {
2631 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2632 break;
2633 }
2634
252b5132
RH		 2635 if (opP->reg == PC
2636 && ! isvar (&opP->disp)
2637 && m68k_abspcadd)
2638 {
2639 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2640 opP->disp.exp.X_add_symbol =
2641 section_symbol (absolute_section);
252b5132
RH		 2642 }
2643
36759679 2644 /* Force into index mode. Hope this works. */
252b5132
RH		 2645
2646 /* We do the first bit for 32-bit displacements, and the
2647 second bit for 16 bit ones. It is possible that we
2648 should make the default be WORD instead of LONG, but
2649 I think that'd break GCC, so we put up with a little
2650 inefficiency for the sake of working output. */
2651
2652 if (!issword (nextword)
2653 || (isvar (&opP->disp)
2654 && ((opP->disp.size == SIZE_UNSPEC
2655 && flag_short_refs == 0
2656 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2657 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2658 || opP->disp.size == SIZE_LONG)))
2659 {
2660 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2661 || arch_coldfire_p (current_architecture))
252b5132
RH		 2662 opP->error =
2663 _("displacement too large for this architecture; needs 68020 or higher");
2664 if (opP->reg == PC)
2665 tmpreg = 0x3B; /* 7.3 */
2666 else
2667 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2668 if (isvar (&opP->disp))
2669 {
2670 if (opP->reg == PC)
2671 {
2672 if (opP->disp.size == SIZE_LONG
2673#ifdef OBJ_ELF
2674 /* If the displacement needs pic
2675 relocation it cannot be relaxed. */
2676 || opP->disp.pic_reloc != pic_none
2677#endif
2678 )
2679 {
2680 addword (0x0170);
2681 add_fix ('l', &opP->disp, 1, 2);
2682 }
2683 else
2684 {
2685 add_frag (adds (&opP->disp),
bd17c2c3 2686 SEXT (offs (&opP->disp)),
151337e8 2687 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2688 break;
2689 }
2690 }
2691 else
2692 {
2693 addword (0x0170);
2694 add_fix ('l', &opP->disp, 0, 0);
2695 }
2696 }
2697 else
2698 addword (0x0170);
2699 addword (nextword >> 16);
2700 }
2701 else
2702 {
2703 if (opP->reg == PC)
2704 tmpreg = 0x3A; /* 7.2 */
2705 else
2706 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2707
2708 if (isvar (&opP->disp))
2709 {
2710 if (opP->reg == PC)
2711 {
2712 add_fix ('w', &opP->disp, 1, 0);
2713 }
2714 else
2715 add_fix ('w', &opP->disp, 0, 0);
2716 }
2717 }
2718 addword (nextword);
2719 break;
2720
2721 case POST:
2722 case PRE:
2723 case BASE:
2724 nextword = 0;
3e602632 2725 baseo = get_num (&opP->disp, 90);
252b5132 2726 if (opP->mode == POST || opP->mode == PRE)
3e602632 2727 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2728 /* Figure out the `addressing mode'.
2729 Also turn on the BASE_DISABLE bit, if needed. */
2730 if (opP->reg == PC || opP->reg == ZPC)
2731 {
2732 tmpreg = 0x3b; /* 7.3 */
2733 if (opP->reg == ZPC)
2734 nextword |= 0x80;
2735 }
2736 else if (opP->reg == 0)
2737 {
2738 nextword |= 0x80;
2739 tmpreg = 0x30; /* 6.garbage */
2740 }
2741 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2742 {
2743 nextword |= 0x80;
2744 tmpreg = 0x30 + opP->reg - ZADDR0;
2745 }
2746 else
2747 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2748
2749 siz1 = opP->disp.size;
2750 if (opP->mode == POST || opP->mode == PRE)
2751 siz2 = opP->odisp.size;
2752 else
2753 siz2 = SIZE_UNSPEC;
2754
36759679 2755 /* Index register stuff. */
252b5132
RH		 2756 if (opP->index.reg != 0
2757 && opP->index.reg >= DATA
2758 && opP->index.reg <= ADDR7)
2759 {
2760 nextword |= (opP->index.reg - DATA) << 12;
2761
2762 if (opP->index.size == SIZE_LONG
2763 || (opP->index.size == SIZE_UNSPEC
2764 && m68k_index_width_default == SIZE_LONG))
2765 nextword |= 0x800;
2766
92774660 2767 if ((opP->index.scale != 1
252b5132 2768 && cpu_of_arch (current_architecture) < m68020)
92774660 2769 || (opP->index.scale == 8
3e602632 2770 && (arch_coldfire_p (current_architecture)
6b6e92f4 2771 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2772 {
2773 opP->error =
2774 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2775 }
2776
6da466c7
ILT		 2777 if (arch_coldfire_p (current_architecture)
2778 && opP->index.size == SIZE_WORD)
2779 opP->error = _("invalid index size for coldfire");
2780
252b5132
RH		 2781 switch (opP->index.scale)
2782 {
2783 case 1:
2784 break;
2785 case 2:
2786 nextword |= 0x200;
2787 break;
2788 case 4:
2789 nextword |= 0x400;
2790 break;
2791 case 8:
2792 nextword |= 0x600;
2793 break;
2794 default:
2795 abort ();
2796 }
2797 /* IF its simple,
2798 GET US OUT OF HERE! */
2799
2800 /* Must be INDEX, with an index register. Address
2801 register cannot be ZERO-PC, and either :b was
2802 forced, or we know it will fit. For a 68000 or
2803 68010, force this mode anyways, because the
2804 larger modes aren't supported. */
2805 if (opP->mode == BASE
2806 && ((opP->reg >= ADDR0
2807 && opP->reg <= ADDR7)
2808 || opP->reg == PC))
2809 {
2810 if (siz1 == SIZE_BYTE
2811 || cpu_of_arch (current_architecture) < m68020
6da466c7 2812 || arch_coldfire_p (current_architecture)
252b5132
RH		 2813 || (siz1 == SIZE_UNSPEC
2814 && ! isvar (&opP->disp)
2815 && issbyte (baseo)))
2816 {
2817 nextword += baseo & 0xff;
2818 addword (nextword);
2819 if (isvar (&opP->disp))
2820 {
2821 /* Do a byte relocation. If it doesn't
2822 fit (possible on m68000) let the
2823 fixup processing complain later. */
2824 if (opP->reg == PC)
2825 add_fix ('B', &opP->disp, 1, 1);
2826 else
2827 add_fix ('B', &opP->disp, 0, 0);
2828 }
2829 else if (siz1 != SIZE_BYTE)
2830 {
2831 if (siz1 != SIZE_UNSPEC)
2832 as_warn (_("Forcing byte displacement"));
2833 if (! issbyte (baseo))
2834 opP->error = _("byte displacement out of range");
2835 }
2836
2837 break;
2838 }
2839 else if (siz1 == SIZE_UNSPEC
2840 && opP->reg == PC
2841 && isvar (&opP->disp)
2842 && subs (&opP->disp) == NULL
2843#ifdef OBJ_ELF
2844 /* If the displacement needs pic
2845 relocation it cannot be relaxed. */
2846 && opP->disp.pic_reloc == pic_none
2847#endif
2848 )
2849 {
2850 /* The code in md_convert_frag_1 needs to be
2851 able to adjust nextword. Call frag_grow
2852 to ensure that we have enough space in
2853 the frag obstack to make all the bytes
2854 contiguous. */
2855 frag_grow (14);
8a104df9
KH		 2856 nextword += baseo & 0xff;
2857 addword (nextword);
bd17c2c3
AM		 2858 add_frag (adds (&opP->disp),
2859 SEXT (offs (&opP->disp)),
8a104df9 2860 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2861
2862 break;
8a104df9 2863 }
252b5132
RH		 2864 }
2865 }
2866 else
2867 {
36759679 2868 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2869 if (opP->index.reg >= ZDATA0
2870 && opP->index.reg <= ZDATA7)
2871 nextword |= (opP->index.reg - ZDATA0) << 12;
2872 else if (opP->index.reg >= ZADDR0
2873 || opP->index.reg <= ZADDR7)
2874 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2875 }
2876
2877 /* It isn't simple. */
2878
2879 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2880 || arch_coldfire_p (current_architecture))
252b5132
RH		 2881 opP->error =
2882 _("invalid operand mode for this architecture; needs 68020 or higher");
2883
2884 nextword |= 0x100;
2885 /* If the guy specified a width, we assume that it is
2886 wide enough. Maybe it isn't. If so, we lose. */
2887 switch (siz1)
2888 {
2889 case SIZE_UNSPEC:
2890 if (isvar (&opP->disp)
2891 ? m68k_rel32
2892 : ! issword (baseo))
2893 {
2894 siz1 = SIZE_LONG;
2895 nextword |= 0x30;
2896 }
2897 else if (! isvar (&opP->disp) && baseo == 0)
2898 nextword |= 0x10;
2899 else
2900 {
2901 nextword |= 0x20;
2902 siz1 = SIZE_WORD;
2903 }
2904 break;
2905 case SIZE_BYTE:
2906 as_warn (_(":b not permitted; defaulting to :w"));
2907 /* Fall through. */
2908 case SIZE_WORD:
2909 nextword |= 0x20;
2910 break;
2911 case SIZE_LONG:
2912 nextword |= 0x30;
2913 break;
2914 }
2915
67c1ffbe 2916 /* Figure out inner displacement stuff. */
252b5132
RH		 2917 if (opP->mode == POST || opP->mode == PRE)
2918 {
2919 if (cpu_of_arch (current_architecture) & cpu32)
2920 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2921 switch (siz2)
2922 {
2923 case SIZE_UNSPEC:
2924 if (isvar (&opP->odisp)
2925 ? m68k_rel32
2926 : ! issword (outro))
2927 {
2928 siz2 = SIZE_LONG;
2929 nextword |= 0x3;
2930 }
2931 else if (! isvar (&opP->odisp) && outro == 0)
2932 nextword |= 0x1;
2933 else
2934 {
2935 nextword |= 0x2;
2936 siz2 = SIZE_WORD;
2937 }
2938 break;
2939 case 1:
2940 as_warn (_(":b not permitted; defaulting to :w"));
2941 /* Fall through. */
2942 case 2:
2943 nextword |= 0x2;
2944 break;
2945 case 3:
2946 nextword |= 0x3;
2947 break;
2948 }
2949 if (opP->mode == POST
2950 && (nextword & 0x40) == 0)
2951 nextword |= 0x04;
2952 }
2953 addword (nextword);
2954
2955 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2956 {
2957 if (opP->reg == PC || opP->reg == ZPC)
2958 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2959 else
2960 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2961 }
2962 if (siz1 == SIZE_LONG)
2963 addword (baseo >> 16);
2964 if (siz1 != SIZE_UNSPEC)
2965 addword (baseo);
2966
2967 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2968 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2969 if (siz2 == SIZE_LONG)
2970 addword (outro >> 16);
2971 if (siz2 != SIZE_UNSPEC)
2972 addword (outro);
2973
2974 break;
2975
2976 case ABSL:
3e602632 2977 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2978 switch (opP->disp.size)
2979 {
2980 default:
2981 abort ();
2982 case SIZE_UNSPEC:
2983 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2984 {
2985 tmpreg = 0x38; /* 7.0 */
2986 addword (nextword);
2987 break;
2988 }
252b5132
RH		 2989 if (isvar (&opP->disp)
2990 && !subs (&opP->disp)
2991 && adds (&opP->disp)
2992#ifdef OBJ_ELF
2993 /* If the displacement needs pic relocation it
2994 cannot be relaxed. */
2995 && opP->disp.pic_reloc == pic_none
2996#endif
252b5132
RH		 2997 && !flag_long_jumps
2998 && !strchr ("~%&$?", s[0]))
2999 {
3000 tmpreg = 0x3A; /* 7.2 */
3001 add_frag (adds (&opP->disp),
bd17c2c3 3002 SEXT (offs (&opP->disp)),
151337e8 3003 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 3004 break;
3005 }
36759679 3006 /* Fall through into long. */
252b5132
RH		 3007 case SIZE_LONG:
3008 if (isvar (&opP->disp))
3009 add_fix ('l', &opP->disp, 0, 0);
3010
3011 tmpreg = 0x39;/* 7.1 mode */
3012 addword (nextword >> 16);
3013 addword (nextword);
3014 break;
3015
3016 case SIZE_BYTE:
3017 as_bad (_("unsupported byte value; use a different suffix"));
3018 /* Fall through. */
36759679
NC		 3019
3020 case SIZE_WORD:
252b5132
RH		 3021 if (isvar (&opP->disp))
3022 add_fix ('w', &opP->disp, 0, 0);
3023
3024 tmpreg = 0x38;/* 7.0 mode */
3025 addword (nextword);
3026 break;
3027 }
3028 break;
3029 case CONTROL:
3030 case FPREG:
3031 default:
3032 as_bad (_("unknown/incorrect operand"));
bc805888 3033 /* abort (); */
252b5132 3034 }
fd99574b
NC		 3035
3036 /* If s[0] is '4', then this is for the mac instructions
3037 that can have a trailing_ampersand set. If so, set 0x100
3038 bit on tmpreg so install_gen_operand can check for it and
3039 set the appropriate bit (word2, bit 5). */
3040 if (s[0] == '4')
3041 {
3042 if (opP->trailing_ampersand)
3043 tmpreg |= 0x100;
3044 }
252b5132
RH		 3045 install_gen_operand (s[1], tmpreg);
3046 break;
3047
3048 case '#':
3049 case '^':
3050 switch (s[1])
3051 { /* JF: I hate floating point! */
3052 case 'j':
3053 tmpreg = 70;
3054 break;
3055 case '8':
3056 tmpreg = 20;
3057 break;
3058 case 'C':
3059 tmpreg = 50;
3060 break;
3061 case '3':
3062 default:
3e602632 3063 tmpreg = 90;
252b5132
RH		 3064 break;
3065 }
3066 tmpreg = get_num (&opP->disp, tmpreg);
3067 if (isvar (&opP->disp))
3068 add_fix (s[1], &opP->disp, 0, 0);
3069 switch (s[1])
3070 {
3071 case 'b': /* Danger: These do no check for
3072 certain types of overflow.
3073 user beware! */
3074 if (!isbyte (tmpreg))
3075 opP->error = _("out of range");
3076 insop (tmpreg, opcode);
3077 if (isvar (&opP->disp))
3078 the_ins.reloc[the_ins.nrel - 1].n =
3079 (opcode->m_codenum) * 2 + 1;
3080 break;
3081 case 'B':
3082 if (!issbyte (tmpreg))
3083 opP->error = _("out of range");
3084 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3085 if (isvar (&opP->disp))
3086 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3087 break;
3088 case 'w':
3089 if (!isword (tmpreg))
3090 opP->error = _("out of range");
3091 insop (tmpreg, opcode);
3092 if (isvar (&opP->disp))
3093 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3094 break;
3095 case 'W':
3096 if (!issword (tmpreg))
3097 opP->error = _("out of range");
3098 insop (tmpreg, opcode);
3099 if (isvar (&opP->disp))
3100 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3101 break;
3102 case 'l':
3103 /* Because of the way insop works, we put these two out
3104 backwards. */
3105 insop (tmpreg, opcode);
3106 insop (tmpreg >> 16, opcode);
3107 if (isvar (&opP->disp))
3108 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3109 break;
3110 case '3':
3111 tmpreg &= 0xFF;
3112 case '8':
3113 case 'C':
3114 case 'j':
3115 install_operand (s[1], tmpreg);
3116 break;
3117 default:
3118 abort ();
3119 }
3120 break;
3121
3122 case '+':
3123 case '-':
3124 case 'A':
3125 case 'a':
3126 install_operand (s[1], opP->reg - ADDR);
3127 break;
3128
3129 case 'B':
3e602632 3130 tmpreg = get_num (&opP->disp, 90);
9a2e615a 3131
252b5132
RH		 3132 switch (s[1])
3133 {
3134 case 'B':
8390138c 3135 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3136 break;
3137 case 'W':
3138 add_fix ('w', &opP->disp, 1, 0);
3139 addword (0);
3140 break;
3141 case 'L':
3142 long_branch:
151337e8 3143 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3144 add_fix ('l', &opP->disp, 1, 0);
3145 addword (0);
3146 addword (0);
3147 break;
9a2e615a
NS		 3148 case 'g': /* Conditional branch */
3149 have_disp = HAVE_LONG_CALL (current_architecture);
3150 goto var_branch;
3151
3152 case 'b': /* Unconditional branch */
3153 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3154 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a
NS		 3155 goto var_branch;
3156
3157 case 's': /* Unconditional subroutine */
3158 have_disp = HAVE_LONG_CALL (current_architecture);
3159
3160 var_branch:
3161 if (subs (&opP->disp) /* We can't relax it. */
252b5132 3162#ifdef OBJ_ELF
9a2e615a
NS		 3163 /* If the displacement needs pic relocation it cannot be
3164 relaxed. */
3165 || opP->disp.pic_reloc != pic_none
252b5132 3166#endif
9a2e615a
NS		 3167 || 0)
3168 {
3169 if (!have_disp)
3170 as_warn (_("Can't use long branches on this architecture"));
3171 goto long_branch;
3172 }
3173
252b5132 3174 /* This could either be a symbol, or an absolute
151337e8
NC		 3175 address. If it's an absolute address, turn it into
3176 an absolute jump right here and keep it out of the
3177 relaxer. */
3178 if (adds (&opP->disp) == 0)
3179 {
3180 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3181 the_ins.opcode[0] = 0x4EF9;
151337e8 3182 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3183 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3184 else /* jCC */
3185 {
3186 the_ins.opcode[0] ^= 0x0100;
3187 the_ins.opcode[0] |= 0x0006;
18566f55 3188 addword (0x4EF9);
151337e8
NC		 3189 }
3190 add_fix ('l', &opP->disp, 0, 0);
3191 addword (0);
3192 addword (0);
3193 break;
3194 }
3195
3196 /* Now we know it's going into the relaxer. Now figure
3197 out which mode. We try in this order of preference:
3198 long branch, absolute jump, byte/word branches only. */
9a2e615a 3199 if (have_disp)
bd17c2c3
AM		 3200 add_frag (adds (&opP->disp),
3201 SEXT (offs (&opP->disp)),
151337e8
NC		 3202 TAB (BRANCHBWL, SZ_UNDEF));
3203 else if (! flag_keep_pcrel)
3204 {
3205 if ((the_ins.opcode[0] == 0x6000)
3206 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3207 add_frag (adds (&opP->disp),
3208 SEXT (offs (&opP->disp)),
151337e8
NC		 3209 TAB (BRABSJUNC, SZ_UNDEF));
3210 else
bd17c2c3
AM		 3211 add_frag (adds (&opP->disp),
3212 SEXT (offs (&opP->disp)),
151337e8
NC		 3213 TAB (BRABSJCOND, SZ_UNDEF));
3214 }
252b5132 3215 else
bd17c2c3
AM		 3216 add_frag (adds (&opP->disp),
3217 SEXT (offs (&opP->disp)),
cac27205
NC		 3218 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3219 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3220 break;
3221 case 'w':
3222 if (isvar (&opP->disp))
3223 {
151337e8
NC		 3224 /* Check for DBcc instructions. We can relax them,
3225 but only if we have long branches and/or absolute
3226 jumps. */
3227 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3228 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3229 || ! flag_keep_pcrel))
252b5132 3230 {
151337e8 3231 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3232 add_frag (adds (&opP->disp),
3233 SEXT (offs (&opP->disp)),
151337e8
NC		 3234 TAB (DBCCLBR, SZ_UNDEF));
3235 else
bd17c2c3
AM		 3236 add_frag (adds (&opP->disp),
3237 SEXT (offs (&opP->disp)),
151337e8 3238 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3239 break;
3240 }
252b5132
RH		 3241 add_fix ('w', &opP->disp, 1, 0);
3242 }
3243 addword (0);
3244 break;
36759679 3245 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3246 add_fix ('l', &opP->disp, 1, 0);
3247 addword (0);
3248 addword (0);
3249 break;
36759679 3250 case 'c': /* Var size Coprocesssor branches. */
151337e8 3251 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3252 {
252b5132
RH		 3253 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3254 add_fix ('l', &opP->disp, 1, 0);
3255 addword (0);
3256 addword (0);
3257 }
151337e8 3258 else
bd17c2c3
AM		 3259 add_frag (adds (&opP->disp),
3260 SEXT (offs (&opP->disp)),
151337e8 3261 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3262 break;
3263 default:
3264 abort ();
3265 }
3266 break;
3267
36759679 3268 case 'C': /* Ignore it. */
252b5132
RH		 3269 break;
3270
36759679 3271 case 'd': /* JF this is a kludge. */
252b5132 3272 install_operand ('s', opP->reg - ADDR);
3e602632 3273 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3274 if (!issword (tmpreg))
3275 {
3276 as_warn (_("Expression out of range, using 0"));
3277 tmpreg = 0;
3278 }
3279 addword (tmpreg);
3280 break;
3281
3282 case 'D':
3283 install_operand (s[1], opP->reg - DATA);
3284 break;
3285
fd99574b
NC		 3286 case 'e': /* EMAC ACCx, reg/reg. */
3287 install_operand (s[1], opP->reg - ACC);
3288 break;
3289
36759679 3290 case 'E': /* Ignore it. */
6da466c7
ILT		 3291 break;
3292
252b5132
RH		 3293 case 'F':
3294 install_operand (s[1], opP->reg - FP0);
3295 break;
3296
fd99574b
NC		 3297 case 'g': /* EMAC ACCEXTx. */
3298 install_operand (s[1], opP->reg - ACCEXT01);
3299 break;
3300
36759679 3301 case 'G': /* Ignore it. */
6da466c7
ILT		 3302 case 'H':
3303 break;
3304
252b5132
RH		 3305 case 'I':
3306 tmpreg = opP->reg - COP0;
3307 install_operand (s[1], tmpreg);
3308 break;
3309
fd99574b
NC		 3310 case 'i': /* MAC/EMAC scale factor. */
3311 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3312 break;
3313
36759679 3314 case 'J': /* JF foo. */
252b5132
RH		 3315 switch (opP->reg)
3316 {
3317 case SFC:
3318 tmpreg = 0x000;
3319 break;
3320 case DFC:
3321 tmpreg = 0x001;
3322 break;
3323 case CACR:
3324 tmpreg = 0x002;
3325 break;
3326 case TC:
a8e24a56 3327 case ASID:
252b5132
RH		 3328 tmpreg = 0x003;
3329 break;
3e602632 3330 case ACR0:
252b5132
RH		 3331 case ITT0:
3332 tmpreg = 0x004;
3333 break;
3e602632 3334 case ACR1:
252b5132
RH		 3335 case ITT1:
3336 tmpreg = 0x005;
3337 break;
3e602632 3338 case ACR2:
252b5132
RH		 3339 case DTT0:
3340 tmpreg = 0x006;
3341 break;
3e602632 3342 case ACR3:
252b5132
RH		 3343 case DTT1:
3344 tmpreg = 0x007;
3345 break;
3346 case BUSCR:
a8e24a56 3347 case MMUBAR:
252b5132
RH		 3348 tmpreg = 0x008;
3349 break;
0d999f33
MK		 3350 case RGPIOBAR:
3351 tmpreg = 0x009;
3352 break;
3353 case ACR4:
3354 case ACR5:
3355 case ACR6:
3356 case ACR7:
3357 tmpreg = 0x00c + (opP->reg - ACR4);
3358 break;
252b5132
RH		 3359
3360 case USP:
3361 tmpreg = 0x800;
3362 break;
3363 case VBR:
3364 tmpreg = 0x801;
3365 break;
3366 case CAAR:
87298967 3367 case CPUCR:
252b5132
RH		 3368 tmpreg = 0x802;
3369 break;
3370 case MSP:
3371 tmpreg = 0x803;
3372 break;
3373 case ISP:
3374 tmpreg = 0x804;
3375 break;
3376 case MMUSR:
3377 tmpreg = 0x805;
3378 break;
3379 case URP:
3380 tmpreg = 0x806;
3381 break;
3382 case SRP:
3383 tmpreg = 0x807;
3384 break;
3385 case PCR:
3386 tmpreg = 0x808;
3387 break;
3388 case ROMBAR:
a8e24a56 3389 case ROMBAR0:
252b5132
RH		 3390 tmpreg = 0xC00;
3391 break;
3e602632
NC		 3392 case ROMBAR1:
3393 tmpreg = 0xC01;
3394 break;
3395 case FLASHBAR:
252b5132 3396 case RAMBAR0:
78336706 3397 case RAMBAR_ALT:
252b5132
RH		 3398 tmpreg = 0xC04;
3399 break;
3e602632 3400 case RAMBAR:
252b5132
RH		 3401 case RAMBAR1:
3402 tmpreg = 0xC05;
3403 break;
3e602632
NC		 3404 case MPCR:
3405 tmpreg = 0xC0C;
3406 break;
3407 case EDRAMBAR:
3408 tmpreg = 0xC0D;
3409 break;
3410 case MBAR0:
e80e0390 3411 case MBAR2:
3e602632
NC		 3412 case SECMBAR:
3413 tmpreg = 0xC0E;
3414 break;
3415 case MBAR1:
252b5132
RH		 3416 case MBAR:
3417 tmpreg = 0xC0F;
3418 break;
3e602632
NC		 3419 case PCR1U0:
3420 tmpreg = 0xD02;
3421 break;
3422 case PCR1L0:
3423 tmpreg = 0xD03;
3424 break;
3425 case PCR2U0:
3426 tmpreg = 0xD04;
3427 break;
3428 case PCR2L0:
3429 tmpreg = 0xD05;
3430 break;
3431 case PCR3U0:
3432 tmpreg = 0xD06;
3433 break;
3434 case PCR3L0:
3435 tmpreg = 0xD07;
3436 break;
3437 case PCR1L1:
3438 tmpreg = 0xD0A;
3439 break;
3440 case PCR1U1:
3441 tmpreg = 0xD0B;
3442 break;
3443 case PCR2L1:
3444 tmpreg = 0xD0C;
3445 break;
3446 case PCR2U1:
3447 tmpreg = 0xD0D;
3448 break;
3449 case PCR3L1:
3450 tmpreg = 0xD0E;
3451 break;
3452 case PCR3U1:
3453 tmpreg = 0xD0F;
3454 break;
f7ec513b
KH		 3455 case CAC:
3456 tmpreg = 0xFFE;
3457 break;
d0fa1372 3458 case MBO:
f7ec513b
KH		 3459 tmpreg = 0xFFF;
3460 break;
252b5132
RH		 3461 default:
3462 abort ();
3463 }
3464 install_operand (s[1], tmpreg);
3465 break;
3466
3467 case 'k':
3468 tmpreg = get_num (&opP->disp, 55);
3469 install_operand (s[1], tmpreg & 0x7f);
3470 break;
3471
3472 case 'l':
3473 tmpreg = opP->mask;
3474 if (s[1] == 'w')
3475 {
3476 if (tmpreg & 0x7FF0000)
3477 as_bad (_("Floating point register in register list"));
3478 insop (reverse_16_bits (tmpreg), opcode);
3479 }
3480 else
3481 {
3482 if (tmpreg & 0x700FFFF)
3483 as_bad (_("Wrong register in floating-point reglist"));
3484 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3485 }
3486 break;
3487
3488 case 'L':
3489 tmpreg = opP->mask;
3490 if (s[1] == 'w')
3491 {
3492 if (tmpreg & 0x7FF0000)
3493 as_bad (_("Floating point register in register list"));
3494 insop (tmpreg, opcode);
3495 }
3496 else if (s[1] == '8')
3497 {
3498 if (tmpreg & 0x0FFFFFF)
3499 as_bad (_("incorrect register in reglist"));
3500 install_operand (s[1], tmpreg >> 24);
3501 }
3502 else
3503 {
3504 if (tmpreg & 0x700FFFF)
3505 as_bad (_("wrong register in floating-point reglist"));
3506 else
3507 install_operand (s[1], tmpreg >> 16);
3508 }
3509 break;
3510
3511 case 'M':
3512 install_operand (s[1], get_num (&opP->disp, 60));
3513 break;
3514
3515 case 'O':
3516 tmpreg = ((opP->mode == DREG)
8fce3f5e 3517 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3518 : (get_num (&opP->disp, 40) & 0x1F));
3519 install_operand (s[1], tmpreg);
3520 break;
3521
3522 case 'Q':
3523 tmpreg = get_num (&opP->disp, 10);
3524 if (tmpreg == 8)
3525 tmpreg = 0;
3526 install_operand (s[1], tmpreg);
3527 break;
3528
3529 case 'R':
3530 /* This depends on the fact that ADDR registers are eight
3531 more than their corresponding DATA regs, so the result
36759679 3532 will have the ADDR_REG bit set. */
252b5132
RH		 3533 install_operand (s[1], opP->reg - DATA);
3534 break;
3535
3536 case 'r':
3537 if (opP->mode == AINDR)
3538 install_operand (s[1], opP->reg - DATA);
3539 else
3540 install_operand (s[1], opP->index.reg - DATA);
3541 break;
3542
3543 case 's':
3544 if (opP->reg == FPI)
3545 tmpreg = 0x1;
3546 else if (opP->reg == FPS)
3547 tmpreg = 0x2;
3548 else if (opP->reg == FPC)
3549 tmpreg = 0x4;
3550 else
3551 abort ();
3552 install_operand (s[1], tmpreg);
3553 break;
3554
36759679 3555 case 'S': /* Ignore it. */
252b5132
RH		 3556 break;
3557
3558 case 'T':
3559 install_operand (s[1], get_num (&opP->disp, 30));
3560 break;
3561
36759679 3562 case 'U': /* Ignore it. */
252b5132
RH		 3563 break;
3564
3565 case 'c':
3566 switch (opP->reg)
3567 {
3568 case NC:
3569 tmpreg = 0;
3570 break;
3571 case DC:
3572 tmpreg = 1;
3573 break;
3574 case IC:
3575 tmpreg = 2;
3576 break;
3577 case BC:
3578 tmpreg = 3;
3579 break;
3580 default:
3581 as_fatal (_("failed sanity check"));
36759679 3582 } /* switch on cache token. */
252b5132
RH		 3583 install_operand (s[1], tmpreg);
3584 break;
3585#ifndef NO_68851
92774660 3586 /* JF: These are out of order, I fear. */
252b5132
RH		 3587 case 'f':
3588 switch (opP->reg)
3589 {
3590 case SFC:
3591 tmpreg = 0;
3592 break;
3593 case DFC:
3594 tmpreg = 1;
3595 break;
3596 default:
3597 abort ();
3598 }
3599 install_operand (s[1], tmpreg);
3600 break;
3601
3602 case '0':
3603 case '1':
3604 case '2':
3605 switch (opP->reg)
3606 {
3607 case TC:
3608 tmpreg = 0;
3609 break;
3610 case CAL:
3611 tmpreg = 4;
3612 break;
3613 case VAL:
3614 tmpreg = 5;
3615 break;
3616 case SCC:
3617 tmpreg = 6;
3618 break;
3619 case AC:
3620 tmpreg = 7;
3621 break;
3622 default:
3623 abort ();
3624 }
3625 install_operand (s[1], tmpreg);
3626 break;
3627
3628 case 'V':
3629 if (opP->reg == VAL)
3630 break;
3631 abort ();
3632
3633 case 'W':
3634 switch (opP->reg)
3635 {
3636 case DRP:
3637 tmpreg = 1;
3638 break;
3639 case SRP:
3640 tmpreg = 2;
3641 break;
3642 case CRP:
3643 tmpreg = 3;
3644 break;
3645 default:
3646 abort ();
3647 }
3648 install_operand (s[1], tmpreg);
3649 break;
3650
3651 case 'X':
3652 switch (opP->reg)
3653 {
3654 case BAD:
3655 case BAD + 1:
3656 case BAD + 2:
3657 case BAD + 3:
3658 case BAD + 4:
3659 case BAD + 5:
3660 case BAD + 6:
3661 case BAD + 7:
3662 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3663 break;
3664
3665 case BAC:
3666 case BAC + 1:
3667 case BAC + 2:
3668 case BAC + 3:
3669 case BAC + 4:
3670 case BAC + 5:
3671 case BAC + 6:
3672 case BAC + 7:
3673 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3674 break;
3675
3676 default:
3677 abort ();
3678 }
3679 install_operand (s[1], tmpreg);
3680 break;
3681 case 'Y':
3682 know (opP->reg == PSR);
3683 break;
3684 case 'Z':
3685 know (opP->reg == PCSR);
3686 break;
3687#endif /* m68851 */
3688 case '3':
3689 switch (opP->reg)
3690 {
3691 case TT0:
3692 tmpreg = 2;
3693 break;
3694 case TT1:
3695 tmpreg = 3;
3696 break;
3697 default:
3698 abort ();
3699 }
3700 install_operand (s[1], tmpreg);
3701 break;
3702 case 't':
3703 tmpreg = get_num (&opP->disp, 20);
3704 install_operand (s[1], tmpreg);
3705 break;
36759679 3706 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3707 if (isvar (&opP->disp))
3708 add_fix ('l', &opP->disp, 0, 0);
3e602632 3709 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3710 addword (tmpreg >> 16);
3711 addword (tmpreg & 0xFFFF);
3712 break;
6da466c7
ILT		 3713 case 'u':
3714 install_operand (s[1], opP->reg - DATA0L);
3715 opP->reg -= (DATA0L);
36759679 3716 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3717 break;
3e602632
NC		 3718 case 'x':
3719 tmpreg = get_num (&opP->disp, 80);
3720 if (tmpreg == -1)
3721 tmpreg = 0;
3722 install_operand (s[1], tmpreg);
3723 break;
afa2158f
NS		 3724 case 'j':
3725 tmpreg = get_num (&opP->disp, 10);
3726 install_operand (s[1], tmpreg - 1);
3727 break;
3728 case 'K':
3729 tmpreg = get_num (&opP->disp, 65);
3730 install_operand (s[1], tmpreg);
3731 break;
252b5132
RH		 3732 default:
3733 abort ();
3734 }
3735 }
3736
3737 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3738 instruction, ready to be emitted. . . */
252b5132
RH		 3739}
3740
3741static int
31302357 3742reverse_16_bits (int in)
252b5132
RH		 3743{
3744 int out = 0;
3745 int n;
3746
3747 static int mask[16] =
3748 {
3749 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3750 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3751 };
3752 for (n = 0; n < 16; n++)
3753 {
3754 if (in & mask[n])
3755 out |= mask[15 - n];
3756 }
3757 return out;
3758} /* reverse_16_bits() */
3759
3760static int
31302357 3761reverse_8_bits (int in)
252b5132
RH		 3762{
3763 int out = 0;
3764 int n;
3765
3766 static int mask[8] =
3767 {
3768 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3769 };
3770
3771 for (n = 0; n < 8; n++)
3772 {
3773 if (in & mask[n])
3774 out |= mask[7 - n];
3775 }
3776 return out;
3777} /* reverse_8_bits() */
3778
cac27205
NC		 3779/* Cause an extra frag to be generated here, inserting up to
3780 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3781 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3782
3783 The TYPE parameter is also used by md_convert_frag_1 and
3784 md_estimate_size_before_relax. The appropriate type of fixup will
3785 be emitted by md_convert_frag_1.
3786
3787 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3788static void
31302357 3789install_operand (int mode, int val)
252b5132
RH		 3790{
3791 switch (mode)
3792 {
3793 case 's':
36759679 3794 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3795 break;
3796 case 'd':
3797 the_ins.opcode[0] |= val << 9;
3798 break;
afa2158f
NS		 3799 case 'E':
3800 the_ins.opcode[1] |= val << 9;
3801 break;
252b5132
RH		 3802 case '1':
3803 the_ins.opcode[1] |= val << 12;
3804 break;
3805 case '2':
3806 the_ins.opcode[1] |= val << 6;
3807 break;
3808 case '3':
3809 the_ins.opcode[1] |= val;
3810 break;
3811 case '4':
3812 the_ins.opcode[2] |= val << 12;
3813 break;
3814 case '5':
3815 the_ins.opcode[2] |= val << 6;
3816 break;
3817 case '6':
3818 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3819 three words long! */
3820 the_ins.numo++;
3821 the_ins.opcode[2] |= val;
3822 break;
3823 case '7':
3824 the_ins.opcode[1] |= val << 7;
3825 break;
3826 case '8':
3827 the_ins.opcode[1] |= val << 10;
3828 break;
3829#ifndef NO_68851
3830 case '9':
3831 the_ins.opcode[1] |= val << 5;
3832 break;
3833#endif
3834
3835 case 't':
3836 the_ins.opcode[1] |= (val << 10) | (val << 7);
3837 break;
3838 case 'D':
3839 the_ins.opcode[1] |= (val << 12) | val;
3840 break;
3841 case 'g':
3842 the_ins.opcode[0] |= val = 0xff;
3843 break;
3844 case 'i':
3845 the_ins.opcode[0] |= val << 9;
3846 break;
3847 case 'C':
3848 the_ins.opcode[1] |= val;
3849 break;
3850 case 'j':
3851 the_ins.opcode[1] |= val;
36759679 3852 the_ins.numo++; /* What a hack. */
252b5132
RH		 3853 break;
3854 case 'k':
3855 the_ins.opcode[1] |= val << 4;
3856 break;
3857 case 'b':
3858 case 'w':
3859 case 'W':
3860 case 'l':
3861 break;
3862 case 'e':
3863 the_ins.opcode[0] |= (val << 6);
3864 break;
3865 case 'L':
3866 the_ins.opcode[1] = (val >> 16);
3867 the_ins.opcode[2] = val & 0xffff;
3868 break;
6da466c7
ILT		 3869 case 'm':
3870 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3871 the_ins.opcode[0] |= ((val & 0x7) << 9);
3872 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3873 break;
fd99574b 3874 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3875 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3876 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3877 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3878 break;
fd99574b 3879 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3880 the_ins.opcode[1] |= val << 12;
3881 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3882 break;
fd99574b 3883 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3884 the_ins.opcode[0] |= (val & 0xF);
3885 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3886 break;
fd99574b 3887 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3888 the_ins.opcode[1] |= (val & 0xF);
3889 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3890 break;
3891 case 'h':
3892 the_ins.opcode[1] |= ((val != 1) << 10);
3893 break;
fd99574b
NC		 3894 case 'F':
3895 the_ins.opcode[0] |= ((val & 0x3) << 9);
3896 break;
3897 case 'f':
3898 the_ins.opcode[0] |= ((val & 0x3) << 0);
3899 break;
be8c092b 3900 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3901 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3902 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3903 break;
be8c092b 3904 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3905 the_ins.opcode[0] |= ((val & 0x1) << 7);
3906 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3907 break;
3908 case 'I':
3909 the_ins.opcode[1] |= ((val & 0x3) << 9);
3910 break;
3911 case ']':
3912 the_ins.opcode[0] |= (val & 0x1) <<10;
3913 break;
252b5132
RH		 3914 case 'c':
3915 default:
3916 as_fatal (_("failed sanity check."));
3917 }
6b6e92f4 3918}
252b5132
RH		 3919
3920static void
31302357 3921install_gen_operand (int mode, int val)
252b5132
RH		 3922{
3923 switch (mode)
3924 {
fd99574b
NC		 3925 case '/': /* Special for mask loads for mac/msac insns with
3926 possible mask; trailing_ampersend set in bit 8. */
3927 the_ins.opcode[0] |= (val & 0x3f);
3928 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3929 break;
252b5132
RH		 3930 case 's':
3931 the_ins.opcode[0] |= val;
3932 break;
3933 case 'd':
3934 /* This is a kludge!!! */
3935 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3936 break;
3937 case 'b':
3938 case 'w':
3939 case 'l':
3940 case 'f':
3941 case 'F':
3942 case 'x':
3943 case 'p':
3944 the_ins.opcode[0] |= val;
3945 break;
36759679 3946 /* more stuff goes here. */
252b5132
RH		 3947 default:
3948 as_fatal (_("failed sanity check."));
3949 }
6b6e92f4 3950}
252b5132 3951
6b6e92f4
NC		 3952/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3953 then deal with the bitfield hack. */
252b5132
RH		 3954
3955static char *
31302357 3956crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3957{
3958 register int parens;
3959 register int c;
3960 register char *beg_str;
3961 int inquote = 0;
3962
3963 if (!str)
3964 {
3965 return str;
3966 }
3967 beg_str = str;
3968 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3969 {
3970 if (! inquote)
3971 {
3972 if (*str == '(')
3973 parens++;
3974 else if (*str == ')')
3975 {
3976 if (!parens)
36759679 3977 { /* ERROR. */
252b5132
RH		 3978 opP->error = _("Extra )");
3979 return str;
3980 }
3981 --parens;
3982 }
3983 }
3984 if (flag_mri && *str == '\'')
3985 inquote = ! inquote;
3986 }
3987 if (!*str && parens)
36759679 3988 { /* ERROR. */
252b5132
RH		 3989 opP->error = _("Missing )");
3990 return str;
3991 }
3992 c = *str;
3993 *str = '\0';
3994 if (m68k_ip_op (beg_str, opP) != 0)
3995 {
3996 *str = c;
3997 return str;
3998 }
3999 *str = c;
4000 if (c == '}')
36759679 4001 c = *++str; /* JF bitfield hack. */
252b5132
RH		 4002 if (c)
4003 {
4004 c = *++str;
4005 if (!c)
4006 as_bad (_("Missing operand"));
4007 }
4008
4009 /* Detect MRI REG symbols and convert them to REGLSTs. */
4010 if (opP->mode == CONTROL && (int)opP->reg < 0)
4011 {
4012 opP->mode = REGLST;
4013 opP->mask = ~(int)opP->reg;
4014 opP->reg = 0;
4015 }
4016
4017 return str;
4018}
4019
4020/* This is the guts of the machine-dependent assembler. STR points to a
4021 machine dependent instruction. This function is supposed to emit
4022 the frags/bytes it assembles to.
4023 */
4024
4025static void
31302357 4026insert_reg (const char *regname, int regnum)
252b5132
RH		 4027{
4028 char buf[100];
4029 int i;
4030
4031#ifdef REGISTER_PREFIX
4032 if (!flag_reg_prefix_optional)
4033 {
4034 buf[0] = REGISTER_PREFIX;
4035 strcpy (buf + 1, regname);
4036 regname = buf;
4037 }
4038#endif
4039
4040 symbol_table_insert (symbol_new (regname, reg_section, regnum,
4041 &zero_address_frag));
4042
4043 for (i = 0; regname[i]; i++)
3882b010 4044 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 4045 buf[i] = '\0';
4046
4047 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4048 &zero_address_frag));
4049}
4050
4051struct init_entry
4052 {
4053 const char *name;
4054 int number;
4055 };
4056
4057static const struct init_entry init_table[] =
4058{
4059 { "d0", DATA0 },
4060 { "d1", DATA1 },
4061 { "d2", DATA2 },
4062 { "d3", DATA3 },
4063 { "d4", DATA4 },
4064 { "d5", DATA5 },
4065 { "d6", DATA6 },
4066 { "d7", DATA7 },
4067 { "a0", ADDR0 },
4068 { "a1", ADDR1 },
4069 { "a2", ADDR2 },
4070 { "a3", ADDR3 },
4071 { "a4", ADDR4 },
4072 { "a5", ADDR5 },
4073 { "a6", ADDR6 },
4074 { "fp", ADDR6 },
4075 { "a7", ADDR7 },
4076 { "sp", ADDR7 },
4077 { "ssp", ADDR7 },
4078 { "fp0", FP0 },
4079 { "fp1", FP1 },
4080 { "fp2", FP2 },
4081 { "fp3", FP3 },
4082 { "fp4", FP4 },
4083 { "fp5", FP5 },
4084 { "fp6", FP6 },
4085 { "fp7", FP7 },
4086 { "fpi", FPI },
4087 { "fpiar", FPI },
4088 { "fpc", FPI },
4089 { "fps", FPS },
4090 { "fpsr", FPS },
4091 { "fpc", FPC },
4092 { "fpcr", FPC },
4093 { "control", FPC },
4094 { "status", FPS },
4095 { "iaddr", FPI },
4096
4097 { "cop0", COP0 },
4098 { "cop1", COP1 },
4099 { "cop2", COP2 },
4100 { "cop3", COP3 },
4101 { "cop4", COP4 },
4102 { "cop5", COP5 },
4103 { "cop6", COP6 },
4104 { "cop7", COP7 },
4105 { "pc", PC },
4106 { "zpc", ZPC },
4107 { "sr", SR },
4108
4109 { "ccr", CCR },
4110 { "cc", CCR },
4111
6da466c7 4112 { "acc", ACC },
fd99574b
NC		 4113 { "acc0", ACC },
4114 { "acc1", ACC1 },
4115 { "acc2", ACC2 },
4116 { "acc3", ACC3 },
4117 { "accext01", ACCEXT01 },
4118 { "accext23", ACCEXT23 },
6da466c7
ILT		 4119 { "macsr", MACSR },
4120 { "mask", MASK },
4121
36759679
NC		 4122 /* Control registers. */
4123 { "sfc", SFC }, /* Source Function Code. */
252b5132 4124 { "sfcr", SFC },
36759679 4125 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4126 { "dfcr", DFC },
36759679
NC		 4127 { "cacr", CACR }, /* Cache Control Register. */
4128 { "caar", CAAR }, /* Cache Address Register. */
87298967 4129 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4130
36759679
NC		 4131 { "usp", USP }, /* User Stack Pointer. */
4132 { "vbr", VBR }, /* Vector Base Register. */
4133 { "msp", MSP }, /* Master Stack Pointer. */
4134 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4135
36759679
NC		 4136 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4137 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4138 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4139 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4140
4141 /* 68ec040 versions of same */
36759679
NC		 4142 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4143 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4144 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4145 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4146
a8e24a56 4147 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4148 manual indicated that the order is 2,3,0,1, but Ken Rose
4149 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4150 { "acr0", ACR0 }, /* Access Control Unit 0. */
4151 { "acr1", ACR1 }, /* Access Control Unit 1. */
4152 { "acr2", ACR2 }, /* Access Control Unit 2. */
4153 { "acr3", ACR3 }, /* Access Control Unit 3. */
0d999f33
MK		 4154 { "acr4", ACR4 }, /* Access Control Unit 4. */
4155 { "acr5", ACR5 }, /* Access Control Unit 5. */
4156 { "acr6", ACR6 }, /* Access Control Unit 6. */
4157 { "acr7", ACR7 }, /* Access Control Unit 7. */
252b5132 4158
36759679 4159 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4160 { "tcr", TC },
a8e24a56 4161 { "asid", ASID },
252b5132 4162
36759679
NC		 4163 { "mmusr", MMUSR }, /* MMU Status Register. */
4164 { "srp", SRP }, /* User Root Pointer. */
4165 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4166
4167 { "buscr", BUSCR },
a8e24a56 4168 { "mmubar", MMUBAR },
252b5132
RH		 4169 { "pcr", PCR },
4170
36759679
NC		 4171 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4172 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4173 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4174 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4175
4176 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4177 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4178 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4179 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4180 { "mpcr", MPCR }, /* mcfv4e registers. */
4181 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4182 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4183 { "asid", TC }, /* mcfv4e registers. */
4184 { "mmubar", BUSCR }, /* mcfv4e registers. */
4185 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4186 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4187 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4188 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4189 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4190 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4191 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4192 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4193 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4194 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4195 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4196 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4197
4198 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4199 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4200
4201 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b 4202
0d999f33
MK		 4203 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4204
f7ec513b 4205 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4206 { "mbb", MBO }, /* fido registers (obsolete). */
4207 { "mbo", MBO }, /* fido registers. */
36759679 4208 /* End of control registers. */
252b5132
RH		 4209
4210 { "ac", AC },
4211 { "bc", BC },
4212 { "cal", CAL },
4213 { "crp", CRP },
4214 { "drp", DRP },
4215 { "pcsr", PCSR },
4216 { "psr", PSR },
4217 { "scc", SCC },
4218 { "val", VAL },
4219 { "bad0", BAD0 },
4220 { "bad1", BAD1 },
4221 { "bad2", BAD2 },
4222 { "bad3", BAD3 },
4223 { "bad4", BAD4 },
4224 { "bad5", BAD5 },
4225 { "bad6", BAD6 },
4226 { "bad7", BAD7 },
4227 { "bac0", BAC0 },
4228 { "bac1", BAC1 },
4229 { "bac2", BAC2 },
4230 { "bac3", BAC3 },
4231 { "bac4", BAC4 },
4232 { "bac5", BAC5 },
4233 { "bac6", BAC6 },
4234 { "bac7", BAC7 },
4235
4236 { "ic", IC },
4237 { "dc", DC },
4238 { "nc", NC },
4239
4240 { "tt0", TT0 },
4241 { "tt1", TT1 },
36759679 4242 /* 68ec030 versions of same. */
252b5132
RH		 4243 { "ac0", TT0 },
4244 { "ac1", TT1 },
36759679 4245 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4246 { "acusr", PSR },
4247
4248 /* Suppressed data and address registers. */
4249 { "zd0", ZDATA0 },
4250 { "zd1", ZDATA1 },
4251 { "zd2", ZDATA2 },
4252 { "zd3", ZDATA3 },
4253 { "zd4", ZDATA4 },
4254 { "zd5", ZDATA5 },
4255 { "zd6", ZDATA6 },
4256 { "zd7", ZDATA7 },
4257 { "za0", ZADDR0 },
4258 { "za1", ZADDR1 },
4259 { "za2", ZADDR2 },
4260 { "za3", ZADDR3 },
4261 { "za4", ZADDR4 },
4262 { "za5", ZADDR5 },
4263 { "za6", ZADDR6 },
4264 { "za7", ZADDR7 },
4265
92774660 4266 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4267 { "d0l", DATA0L },
4268 { "d1l", DATA1L },
4269 { "d2l", DATA2L },
4270 { "d3l", DATA3L },
4271 { "d4l", DATA4L },
4272 { "d5l", DATA5L },
4273 { "d6l", DATA6L },
4274 { "d7l", DATA7L },
4275
4276 { "a0l", ADDR0L },
4277 { "a1l", ADDR1L },
4278 { "a2l", ADDR2L },
4279 { "a3l", ADDR3L },
4280 { "a4l", ADDR4L },
4281 { "a5l", ADDR5L },
4282 { "a6l", ADDR6L },
4283 { "a7l", ADDR7L },
4284
4285 { "d0u", DATA0U },
4286 { "d1u", DATA1U },
4287 { "d2u", DATA2U },
4288 { "d3u", DATA3U },
4289 { "d4u", DATA4U },
4290 { "d5u", DATA5U },
4291 { "d6u", DATA6U },
4292 { "d7u", DATA7U },
4293
4294 { "a0u", ADDR0U },
4295 { "a1u", ADDR1U },
4296 { "a2u", ADDR2U },
4297 { "a3u", ADDR3U },
4298 { "a4u", ADDR4U },
4299 { "a5u", ADDR5U },
4300 { "a6u", ADDR6U },
4301 { "a7u", ADDR7U },
4302
252b5132
RH		 4303 { 0, 0 }
4304};
4305
4306static void
31302357 4307init_regtable (void)
252b5132
RH		 4308{
4309 int i;
4310 for (i = 0; init_table[i].name; i++)
4311 insert_reg (init_table[i].name, init_table[i].number);
4312}
4313
252b5132 4314void
31302357 4315md_assemble (char *str)
252b5132
RH		 4316{
4317 const char *er;
4318 short *fromP;
4319 char *toP = NULL;
4320 int m, n = 0;
4321 char *to_beg_P;
4322 int shorts_this_frag;
4323 fixS *fixP;
4324
266abb8f
NS		 4325 if (!selected_cpu && !selected_arch)
4326 {
4327 /* We've not selected an architecture yet. Set the default
4328 now. We do this lazily so that an initial .cpu or .arch directive
4329 can specify. */
4330 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4331 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4332 }
4333 if (!initialized)
4334 m68k_init_arch ();
4335
252b5132
RH		 4336 /* In MRI mode, the instruction and operands are separated by a
4337 space. Anything following the operands is a comment. The label
4338 has already been removed. */
4339 if (flag_mri)
4340 {
4341 char *s;
4342 int fields = 0;
4343 int infield = 0;
4344 int inquote = 0;
4345
4346 for (s = str; *s != '\0'; s++)
4347 {
4348 if ((*s == ' ' || *s == '\t') && ! inquote)
4349 {
4350 if (infield)
4351 {
4352 ++fields;
4353 if (fields >= 2)
4354 {
4355 *s = '\0';
4356 break;
4357 }
4358 infield = 0;
4359 }
4360 }
4361 else
4362 {
4363 if (! infield)
4364 infield = 1;
4365 if (*s == '\'')
4366 inquote = ! inquote;
4367 }
4368 }
4369 }
4370
31302357 4371 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4372 m68k_ip (str);
4373 er = the_ins.error;
4374 if (!er)
4375 {
4376 for (n = 0; n < the_ins.numargs; n++)
4377 if (the_ins.operands[n].error)
4378 {
4379 er = the_ins.operands[n].error;
4380 break;
4381 }
4382 }
4383 if (er)
4384 {
4385 as_bad (_("%s -- statement `%s' ignored"), er, str);
4386 return;
4387 }
4388
4389 /* If there is a current label, record that it marks an instruction. */
4390 if (current_label != NULL)
4391 {
4392 current_label->text = 1;
4393 current_label = NULL;
4394 }
4395
f27a3839
AS		 4396#ifdef OBJ_ELF
4397 /* Tie dwarf2 debug info to the address at the start of the insn. */
4398 dwarf2_emit_insn (0);
4399#endif
4400
252b5132
RH		 4401 if (the_ins.nfrag == 0)
4402 {
36759679 4403 /* No frag hacking involved; just put it out. */
252b5132
RH		 4404 toP = frag_more (2 * the_ins.numo);
4405 fromP = &the_ins.opcode[0];
4406 for (m = the_ins.numo; m; --m)
4407 {
4408 md_number_to_chars (toP, (long) (*fromP), 2);
4409 toP += 2;
4410 fromP++;
4411 }
36759679 4412 /* Put out symbol-dependent info. */
252b5132
RH		 4413 for (m = 0; m < the_ins.nrel; m++)
4414 {
4415 switch (the_ins.reloc[m].wid)
4416 {
4417 case 'B':
4418 n = 1;
4419 break;
4420 case 'b':
4421 n = 1;
4422 break;
4423 case '3':
4424 n = 1;
4425 break;
4426 case 'w':
4427 case 'W':
4428 n = 2;
4429 break;
4430 case 'l':
4431 n = 4;
4432 break;
4433 default:
4434 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4435 the_ins.reloc[m].wid);
4436 }
4437
4438 fixP = fix_new_exp (frag_now,
4439 ((toP - frag_now->fr_literal)
4440 - the_ins.numo * 2 + the_ins.reloc[m].n),
4441 n,
4442 &the_ins.reloc[m].exp,
4443 the_ins.reloc[m].pcrel,
4444 get_reloc_code (n, the_ins.reloc[m].pcrel,
4445 the_ins.reloc[m].pic_reloc));
4446 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4447 if (the_ins.reloc[m].wid == 'B')
4448 fixP->fx_signed = 1;
4449 }
4450 return;
4451 }
4452
36759679 4453 /* There's some frag hacking. */
fbe572f9
AM		 4454 {
4455 /* Calculate the max frag size. */
4456 int wid;
4457
4458 wid = 2 * the_ins.fragb[0].fragoff;
4459 for (n = 1; n < the_ins.nfrag; n++)
4460 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4461 /* frag_var part. */
cac27205 4462 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4463 /* Make sure the whole insn fits in one chunk, in particular that
4464 the var part is attached, as we access one byte before the
4465 variable frag for byte branches. */
4466 frag_grow (wid);
4467 }
4468
252b5132
RH		 4469 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4470 {
4471 int wid;
4472
4473 if (n == 0)
4474 wid = 2 * the_ins.fragb[n].fragoff;
4475 else
4476 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4477 toP = frag_more (wid);
4478 to_beg_P = toP;
4479 shorts_this_frag = 0;
4480 for (m = wid / 2; m; --m)
4481 {
4482 md_number_to_chars (toP, (long) (*fromP), 2);
4483 toP += 2;
4484 fromP++;
4485 shorts_this_frag++;
4486 }
4487 for (m = 0; m < the_ins.nrel; m++)
4488 {
4489 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4490 {
4491 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4492 break;
4493 }
4494 wid = the_ins.reloc[m].wid;
4495 if (wid == 0)
4496 continue;
4497 the_ins.reloc[m].wid = 0;
4498 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4499
4500 fixP = fix_new_exp (frag_now,
4501 ((toP - frag_now->fr_literal)
4502 - the_ins.numo * 2 + the_ins.reloc[m].n),
4503 wid,
4504 &the_ins.reloc[m].exp,
4505 the_ins.reloc[m].pcrel,
4506 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4507 the_ins.reloc[m].pic_reloc));
4508 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4509 }
cac27205 4510 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4511 (relax_substateT) (the_ins.fragb[n].fragty),
4512 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4513 }
4514 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4515 shorts_this_frag = 0;
4516 if (n)
4517 {
055d1eb0 4518 toP = frag_more (n * 2);
252b5132
RH		 4519 while (n--)
4520 {
4521 md_number_to_chars (toP, (long) (*fromP), 2);
4522 toP += 2;
4523 fromP++;
4524 shorts_this_frag++;
4525 }
4526 }
4527 for (m = 0; m < the_ins.nrel; m++)
4528 {
4529 int wid;
4530
4531 wid = the_ins.reloc[m].wid;
4532 if (wid == 0)
4533 continue;
4534 the_ins.reloc[m].wid = 0;
4535 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4536
4537 fixP = fix_new_exp (frag_now,
4538 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4539 - shorts_this_frag * 2),
4540 wid,
4541 &the_ins.reloc[m].exp,
4542 the_ins.reloc[m].pcrel,
4543 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4544 the_ins.reloc[m].pic_reloc));
4545 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4546 }
4547}
4548
60fed2d3
NC		 4549/* Comparison function used by qsort to rank the opcode entries by name. */
4550
4551static int
4552m68k_compare_opcode (const void * v1, const void * v2)
4553{
4554 struct m68k_opcode * op1, * op2;
4555 int ret;
4556
03b13e59
NC		 4557 if (v1 == v2)
4558 return 0;
4559
60fed2d3
NC		 4560 op1 = *(struct m68k_opcode **) v1;
4561 op2 = *(struct m68k_opcode **) v2;
4562
4563 /* Compare the two names. If different, return the comparison.
4564 If the same, return the order they are in the opcode table. */
4565 ret = strcmp (op1->name, op2->name);
4566 if (ret)
4567 return ret;
4568 if (op1 < op2)
4569 return -1;
03b13e59 4570 return 1;
60fed2d3
NC		 4571}
4572
252b5132 4573void
60fed2d3 4574md_begin (void)
252b5132 4575{
60fed2d3
NC		 4576 const struct m68k_opcode *ins;
4577 struct m68k_incant *hack, *slak;
4578 const char *retval = 0; /* Empty string, or error msg text. */
4579 int i;
4580
4581 /* Set up hash tables with 68000 instructions.
4582 similar to what the vax assembler does. */
252b5132
RH		 4583 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4584 a copy of it at runtime, adding in the information we want but isn't
4585 there. I think it'd be better to have an awk script hack the table
4586 at compile time. Or even just xstr the table and use it as-is. But
4587 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4588 names. */
4589
252b5132
RH		 4590 if (flag_mri)
4591 {
4592 flag_reg_prefix_optional = 1;
4593 m68k_abspcadd = 1;
4594 if (! m68k_rel32_from_cmdline)
4595 m68k_rel32 = 0;
4596 }
4597
60fed2d3
NC		 4598 /* First sort the opcode table into alphabetical order to seperate
4599 the order that the assembler wants to see the opcodes from the
4600 order that the disassembler wants to see them. */
4601 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4602 if (!m68k_sorted_opcodes)
4603 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4604 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4605
4606 for (i = m68k_numopcodes; i--;)
4607 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4608
4609 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4610 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4611
252b5132
RH		 4612 op_hash = hash_new ();
4613
4614 obstack_begin (&robyn, 4000);
4615 for (i = 0; i < m68k_numopcodes; i++)
4616 {
78aff5a5 4617 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4618 do
4619 {
60fed2d3
NC		 4620 ins = m68k_sorted_opcodes[i];
4621
afa2158f
NS		 4622 /* We must enter all insns into the table, because .arch and
4623 .cpu directives can change things. */
252b5132 4624 slak->m_operands = ins->args;
252b5132
RH		 4625 slak->m_arch = ins->arch;
4626 slak->m_opcode = ins->opcode;
afa2158f
NS		 4627
4628 /* In most cases we can determine the number of opcode words
4629 by checking the second word of the mask. Unfortunately
4630 some instructions have 2 opcode words, but no fixed bits
4631 in the second word. A leading dot in the operands
4632 string also indicates 2 opcodes. */
4633 if (*slak->m_operands == '.')
4634 {
4635 slak->m_operands++;
4636 slak->m_codenum = 2;
4637 }
4638 else if (ins->match & 0xffffL)
4639 slak->m_codenum = 2;
4640 else
4641 slak->m_codenum = 1;
4642 slak->m_opnum = strlen (slak->m_operands) / 2;
4643
252b5132 4644 if (i + 1 != m68k_numopcodes
60fed2d3 4645 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4646 {
60fed2d3 4647 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4648 i++;
4649 }
4650 else
4651 slak->m_next = 0;
4652 slak = slak->m_next;
4653 }
4654 while (slak);
4655
4656 retval = hash_insert (op_hash, ins->name, (char *) hack);
4657 if (retval)
4658 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4659 }
4660
4661 for (i = 0; i < m68k_numaliases; i++)
4662 {
4663 const char *name = m68k_opcode_aliases[i].primary;
4664 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4665 void *val = hash_find (op_hash, name);
60fed2d3 4666
252b5132
RH		 4667 if (!val)
4668 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4669 retval = hash_insert (op_hash, alias, val);
4670 if (retval)
4671 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4672 }
4673
4674 /* In MRI mode, all unsized branches are variable sized. Normally,
4675 they are word sized. */
4676 if (flag_mri)
4677 {
4678 static struct m68k_opcode_alias mri_aliases[] =
4679 {
4680 { "bhi", "jhi", },
4681 { "bls", "jls", },
4682 { "bcc", "jcc", },
4683 { "bcs", "jcs", },
4684 { "bne", "jne", },
4685 { "beq", "jeq", },
4686 { "bvc", "jvc", },
4687 { "bvs", "jvs", },
4688 { "bpl", "jpl", },
4689 { "bmi", "jmi", },
4690 { "bge", "jge", },
4691 { "blt", "jlt", },
4692 { "bgt", "jgt", },
4693 { "ble", "jle", },
4694 { "bra", "jra", },
4695 { "bsr", "jbsr", },
4696 };
4697
8fce3f5e
AM		 4698 for (i = 0;
4699 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4700 i++)
252b5132
RH		 4701 {
4702 const char *name = mri_aliases[i].primary;
4703 const char *alias = mri_aliases[i].alias;
5a49b8ac 4704 void *val = hash_find (op_hash, name);
60fed2d3 4705
252b5132
RH		 4706 if (!val)
4707 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4708 retval = hash_jam (op_hash, alias, val);
4709 if (retval)
4710 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4711 }
4712 }
4713
8fce3f5e 4714 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4715 {
4716 notend_table[i] = 0;
4717 alt_notend_table[i] = 0;
4718 }
60fed2d3 4719
252b5132
RH		 4720 notend_table[','] = 1;
4721 notend_table['{'] = 1;
4722 notend_table['}'] = 1;
4723 alt_notend_table['a'] = 1;
4724 alt_notend_table['A'] = 1;
4725 alt_notend_table['d'] = 1;
4726 alt_notend_table['D'] = 1;
4727 alt_notend_table['#'] = 1;
4728 alt_notend_table['&'] = 1;
4729 alt_notend_table['f'] = 1;
4730 alt_notend_table['F'] = 1;
4731#ifdef REGISTER_PREFIX
4732 alt_notend_table[REGISTER_PREFIX] = 1;
4733#endif
4734
4735 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4736 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4737 alt_notend_table['('] = 1;
4738
4739 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4740 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4741 alt_notend_table['@'] = 1;
4742
4743 /* We need to put digits in alt_notend_table to handle
60fed2d3 4744 bfextu %d0{24:1},%d0 */
252b5132
RH		 4745 alt_notend_table['0'] = 1;
4746 alt_notend_table['1'] = 1;
4747 alt_notend_table['2'] = 1;
4748 alt_notend_table['3'] = 1;
4749 alt_notend_table['4'] = 1;
4750 alt_notend_table['5'] = 1;
4751 alt_notend_table['6'] = 1;
4752 alt_notend_table['7'] = 1;
4753 alt_notend_table['8'] = 1;
4754 alt_notend_table['9'] = 1;
4755
4756#ifndef MIT_SYNTAX_ONLY
4757 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4758 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4759 {
4760 int n = 0;
60fed2d3 4761
252b5132
RH		 4762 while (mote_pseudo_table[n].poc_name)
4763 {
60fed2d3 4764 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4765 hash_insert (op_hash,
4766 mote_pseudo_table[n].poc_name, (char *) hack);
4767 hack->m_operands = 0;
4768 hack->m_opnum = n;
4769 n++;
4770 }
4771 }
4772#endif
4773
4774 init_regtable ();
4775
4776#ifdef OBJ_ELF
4777 record_alignment (text_section, 2);
4778 record_alignment (data_section, 2);
4779 record_alignment (bss_section, 2);
4780#endif
4781}
4782
252b5132
RH		 4783\f
4784/* This is called when a label is defined. */
4785
4786void
31302357 4787m68k_frob_label (symbolS *sym)
252b5132
RH		 4788{
4789 struct label_line *n;
4790
4791 n = (struct label_line *) xmalloc (sizeof *n);
4792 n->next = labels;
4793 n->label = sym;
4794 as_where (&n->file, &n->line);
4795 n->text = 0;
4796 labels = n;
4797 current_label = n;
07a53e5c
RH		 4798
4799#ifdef OBJ_ELF
4800 dwarf2_emit_label (sym);
4801#endif
252b5132
RH		 4802}
4803
4804/* This is called when a value that is not an instruction is emitted. */
4805
4806void
31302357 4807m68k_flush_pending_output (void)
252b5132
RH		 4808{
4809 current_label = NULL;
4810}
4811
4812/* This is called at the end of the assembly, when the final value of
4813 the label is known. We warn if this is a text symbol aligned at an
4814 odd location. */
4815
4816void
31302357 4817m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4818{
4819 if (S_GET_SEGMENT (sym) == reg_section
4820 && (int) S_GET_VALUE (sym) < 0)
4821 {
4822 S_SET_SEGMENT (sym, absolute_section);
4823 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4824 }
4825 else if ((S_GET_VALUE (sym) & 1) != 0)
4826 {
4827 struct label_line *l;
4828
4829 for (l = labels; l != NULL; l = l->next)
4830 {
4831 if (l->label == sym)
4832 {
4833 if (l->text)
4834 as_warn_where (l->file, l->line,
4835 _("text label `%s' aligned to odd boundary"),
4836 S_GET_NAME (sym));
4837 break;
4838 }
4839 }
4840 }
4841}
4842\f
4843/* This is called if we go in or out of MRI mode because of the .mri
4844 pseudo-op. */
4845
4846void
31302357 4847m68k_mri_mode_change (int on)
252b5132
RH		 4848{
4849 if (on)
4850 {
4851 if (! flag_reg_prefix_optional)
4852 {
4853 flag_reg_prefix_optional = 1;
4854#ifdef REGISTER_PREFIX
4855 init_regtable ();
4856#endif
4857 }
4858 m68k_abspcadd = 1;
4859 if (! m68k_rel32_from_cmdline)
4860 m68k_rel32 = 0;
4861 }
4862 else
4863 {
4864 if (! reg_prefix_optional_seen)
4865 {
4866#ifdef REGISTER_PREFIX_OPTIONAL
4867 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4868#else
4869 flag_reg_prefix_optional = 0;
4870#endif
4871#ifdef REGISTER_PREFIX
4872 init_regtable ();
4873#endif
4874 }
4875 m68k_abspcadd = 0;
4876 if (! m68k_rel32_from_cmdline)
4877 m68k_rel32 = 1;
4878 }
4879}
4880
252b5132 4881char *
31302357 4882md_atof (int type, char *litP, int *sizeP)
252b5132 4883{
499ac353 4884 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4885}
4886
4887void
31302357 4888md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4889{
4890 number_to_chars_bigendian (buf, val, n);
4891}
4892
94f592af 4893void
55cf6793 4894md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4895{
bbe8ef22 4896 offsetT val = *valP;
252b5132
RH		 4897 addressT upper_limit;
4898 offsetT lower_limit;
4899
4900 /* This is unnecessary but it convinces the native rs6000 compiler
4901 to generate the code we want. */
4902 char *buf = fixP->fx_frag->fr_literal;
4903 buf += fixP->fx_where;
36759679 4904 /* End ibm compiler workaround. */
252b5132 4905
bd17c2c3 4906 val = SEXT (val);
252b5132 4907
94f592af
NC		 4908 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4909 fixP->fx_done = 1;
4910
252b5132
RH		 4911#ifdef OBJ_ELF
4912 if (fixP->fx_addsy)
4913 {
4914 memset (buf, 0, fixP->fx_size);
36759679 4915 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4916
4917 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4918 && !S_IS_DEFINED (fixP->fx_addsy)
4919 && !S_IS_WEAK (fixP->fx_addsy))
4920 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4921
4922 switch (fixP->fx_r_type)
4923 {
4924 case BFD_RELOC_68K_TLS_GD32:
4925 case BFD_RELOC_68K_TLS_GD16:
4926 case BFD_RELOC_68K_TLS_GD8:
4927 case BFD_RELOC_68K_TLS_LDM32:
4928 case BFD_RELOC_68K_TLS_LDM16:
4929 case BFD_RELOC_68K_TLS_LDM8:
4930 case BFD_RELOC_68K_TLS_LDO32:
4931 case BFD_RELOC_68K_TLS_LDO16:
4932 case BFD_RELOC_68K_TLS_LDO8:
4933 case BFD_RELOC_68K_TLS_IE32:
4934 case BFD_RELOC_68K_TLS_IE16:
4935 case BFD_RELOC_68K_TLS_IE8:
4936 case BFD_RELOC_68K_TLS_LE32:
4937 case BFD_RELOC_68K_TLS_LE16:
4938 case BFD_RELOC_68K_TLS_LE8:
4939 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4940 break;
4941
4942 default:
4943 break;
4944 }
4945
252b5132
RH		 4946 return;
4947 }
22184a77 4948#elif defined(OBJ_AOUT)
1c3f20b4 4949 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4950 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4951 {
4952 memset (buf, 0, fixP->fx_size);
1c3f20b4 4953 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4954 return;
4955 }
252b5132
RH		 4956#endif
4957
252b5132
RH		 4958 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4959 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4960 return;
252b5132
RH		 4961
4962 switch (fixP->fx_size)
4963 {
94f592af
NC		 4964 /* The cast to offsetT below are necessary to make code
4965 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4966 case 1:
4967 *buf++ = val;
4968 upper_limit = 0x7f;
4969 lower_limit = - (offsetT) 0x80;
4970 break;
4971 case 2:
4972 *buf++ = (val >> 8);
4973 *buf++ = val;
4974 upper_limit = 0x7fff;
4975 lower_limit = - (offsetT) 0x8000;
4976 break;
4977 case 4:
4978 *buf++ = (val >> 24);
4979 *buf++ = (val >> 16);
4980 *buf++ = (val >> 8);
4981 *buf++ = val;
4982 upper_limit = 0x7fffffff;
36759679 4983 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4984 break;
4985 default:
4986 BAD_CASE (fixP->fx_size);
4987 }
4988
4989 /* Fix up a negative reloc. */
4990 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4991 {
4992 fixP->fx_addsy = fixP->fx_subsy;
4993 fixP->fx_subsy = NULL;
4994 fixP->fx_tcbit = 1;
4995 }
4996
4997 /* For non-pc-relative values, it's conceivable we might get something
4998 like "0xff" for a byte field. So extend the upper part of the range
4999 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
5000 so that we can do any range checking at all. */
5001 if (! fixP->fx_pcrel && ! fixP->fx_signed)
5002 upper_limit = upper_limit * 2 + 1;
5003
5004 if ((addressT) val > upper_limit
5005 && (val > 0 || val < lower_limit))
2b878742
NS		 5006 as_bad_where (fixP->fx_file, fixP->fx_line,
5007 _("value %ld out of range"), (long)val);
252b5132
RH		 5008
5009 /* A one byte PC-relative reloc means a short branch. We can't use
5010 a short branch with a value of 0 or -1, because those indicate
5011 different opcodes (branches with longer offsets). fixup_segment
5012 in write.c may have clobbered fx_pcrel, so we need to examine the
5013 reloc type. */
5014 if ((fixP->fx_pcrel
7be1c489 5015 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 5016 && fixP->fx_size == 1
5017 && (fixP->fx_addsy == NULL
5018 || S_IS_DEFINED (fixP->fx_addsy))
5019 && (val == 0 || val == -1))
2b878742
NS		 5020 as_bad_where (fixP->fx_file, fixP->fx_line,
5021 _("invalid byte branch offset"));
252b5132
RH		 5022}
5023
252b5132
RH		 5024/* *fragP has been relaxed to its final size, and now needs to have
5025 the bytes inside it modified to conform to the new size There is UGLY
5026 MAGIC here. ..
5027 */
5028static void
31302357 5029md_convert_frag_1 (fragS *fragP)
252b5132
RH		 5030{
5031 long disp;
2b878742 5032 fixS *fixP = NULL;
252b5132
RH		 5033
5034 /* Address in object code of the displacement. */
5035 register int object_address = fragP->fr_fix + fragP->fr_address;
5036
5037 /* Address in gas core of the place to store the displacement. */
5038 /* This convinces the native rs6000 compiler to generate the code we
92774660 5039 want. */
252b5132
RH		 5040 register char *buffer_address = fragP->fr_literal;
5041 buffer_address += fragP->fr_fix;
36759679 5042 /* End ibm compiler workaround. */
252b5132
RH		 5043
5044 /* The displacement of the address, from current location. */
5045 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5046 disp = (disp + fragP->fr_offset) - object_address;
5047
252b5132
RH		 5048 switch (fragP->fr_subtype)
5049 {
151337e8
NC		 5050 case TAB (BRANCHBWL, BYTE):
5051 case TAB (BRABSJUNC, BYTE):
5052 case TAB (BRABSJCOND, BYTE):
5053 case TAB (BRANCHBW, BYTE):
cac27205 5054 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 5055 know (issbyte (disp));
5056 if (disp == 0)
b091f402
AM		 5057 as_bad_where (fragP->fr_file, fragP->fr_line,
5058 _("short branch with zero offset: use :w"));
151337e8 5059 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5060 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5061 fixP->fx_pcrel_adjust = -1;
252b5132 5062 break;
151337e8
NC		 5063 case TAB (BRANCHBWL, SHORT):
5064 case TAB (BRABSJUNC, SHORT):
5065 case TAB (BRABSJCOND, SHORT):
5066 case TAB (BRANCHBW, SHORT):
cac27205 5067 case TAB (BRANCHBWPL, SHORT):
252b5132 5068 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 5069 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5070 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5071 fragP->fr_fix += 2;
5072 break;
5073 case TAB (BRANCHBWL, LONG):
5074 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 5075 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5076 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 5077 fragP->fr_fix += 4;
252b5132 5078 break;
cac27205
NC		 5079 case TAB (BRANCHBWPL, LONG):
5080 /* Here we are converting an unconditional branch into a pair of
5081 conditional branches, in order to get the range. */
5082 fragP->fr_opcode[0] = 0x66; /* bne */
5083 fragP->fr_opcode[1] = 0xFF;
5084 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5085 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5086 fixP->fx_file = fragP->fr_file;
5087 fixP->fx_line = fragP->fr_line;
5088 fragP->fr_fix += 4; /* Skip first offset */
5089 buffer_address += 4;
5090 *buffer_address++ = 0x67; /* beq */
5091 *buffer_address++ = 0xff;
5092 fragP->fr_fix += 2; /* Skip second branch opcode */
5093 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5094 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5095 fragP->fr_fix += 4;
5096 break;
151337e8
NC		 5097 case TAB (BRABSJUNC, LONG):
5098 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5099 {
36759679 5100 if (flag_keep_pcrel)
2b878742
NS		 5101 as_bad_where (fragP->fr_file, fragP->fr_line,
5102 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5103 fragP->fr_opcode[0] = 0x4E;
36759679 5104 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5105 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5106 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5107 fragP->fr_fix += 4;
5108 }
5109 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5110 {
36759679 5111 if (flag_keep_pcrel)
2b878742
NS		 5112 as_bad_where (fragP->fr_file, fragP->fr_line,
5113 _("Conversion of PC relative branch to absolute jump"));
151337e8 5114 fragP->fr_opcode[0] = 0x4E;
36759679 5115 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5116 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5117 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5118 fragP->fr_fix += 4;
252b5132
RH		 5119 }
5120 else
5121 {
151337e8
NC		 5122 /* This cannot happen, because jbsr and jbra are the only two
5123 unconditional branches. */
5124 abort ();
252b5132
RH		 5125 }
5126 break;
151337e8 5127 case TAB (BRABSJCOND, LONG):
36759679 5128 if (flag_keep_pcrel)
2b878742
NS		 5129 as_bad_where (fragP->fr_file, fragP->fr_line,
5130 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5131
36759679
NC		 5132 /* Only Bcc 68000 instructions can come here
5133 Change bcc into b!cc/jmp absl long. */
5134 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5135 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5136
5137 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5138 different frag, in which case referring to them is a no-no.
92774660 5139 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5140 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5141 *buffer_address++ = (char) 0xf9;
36759679 5142 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5143 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5144 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5145 fragP->fr_fix += 4;
5146 break;
5147 case TAB (FBRANCH, SHORT):
5148 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5149 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5150 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5151 fragP->fr_fix += 2;
5152 break;
5153 case TAB (FBRANCH, LONG):
36759679 5154 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5155 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5156 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5157 fragP->fr_fix += 4;
252b5132 5158 break;
151337e8
NC		 5159 case TAB (DBCCLBR, SHORT):
5160 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5161 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5162 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5163 fragP->fr_fix += 2;
5164 break;
5165 case TAB (DBCCLBR, LONG):
36759679
NC		 5166 /* Only DBcc instructions can come here.
5167 Change dbcc into dbcc/bral.
5168 JF: these used to be fr_opcode[2-7], but that's wrong. */
5169 if (flag_keep_pcrel)
2b878742
NS		 5170 as_bad_where (fragP->fr_file, fragP->fr_line,
5171 _("Conversion of DBcc to absolute jump"));
28e7409f 5172
36759679 5173 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5174 *buffer_address++ = 0x04;
36759679 5175 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5176 *buffer_address++ = 0x06;
151337e8
NC		 5177 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5178 *buffer_address++ = (char) 0xff;
252b5132 5179
36759679 5180 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5181 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5182 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5183 fragP->fr_fix += 4;
252b5132 5184 break;
151337e8 5185 case TAB (DBCCABSJ, LONG):
36759679
NC		 5186 /* Only DBcc instructions can come here.
5187 Change dbcc into dbcc/jmp.
5188 JF: these used to be fr_opcode[2-7], but that's wrong. */
5189 if (flag_keep_pcrel)
2b878742
NS		 5190 as_bad_where (fragP->fr_file, fragP->fr_line,
5191 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5192
36759679 5193 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5194 *buffer_address++ = 0x04;
36759679 5195 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5196 *buffer_address++ = 0x06;
36759679 5197 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5198 *buffer_address++ = (char) 0xf9;
5199
36759679 5200 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5201 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5202 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5203 fragP->fr_fix += 4;
252b5132 5204 break;
151337e8 5205 case TAB (PCREL1632, SHORT):
252b5132
RH		 5206 fragP->fr_opcode[1] &= ~0x3F;
5207 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5208 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5209 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5210 fragP->fr_fix += 2;
252b5132 5211 break;
151337e8 5212 case TAB (PCREL1632, LONG):
252b5132
RH		 5213 /* Already set to mode 7.3; this indicates: PC indirect with
5214 suppressed index, 32-bit displacement. */
5215 *buffer_address++ = 0x01;
5216 *buffer_address++ = 0x70;
5217 fragP->fr_fix += 2;
151337e8 5218 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5219 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5220 fixP->fx_pcrel_adjust = 2;
5221 fragP->fr_fix += 4;
252b5132 5222 break;
252b5132 5223 case TAB (PCINDEX, BYTE):
9c2799c2 5224 gas_assert (fragP->fr_fix >= 2);
252b5132 5225 buffer_address[-2] &= ~1;
151337e8 5226 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5227 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5228 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5229 break;
5230 case TAB (PCINDEX, SHORT):
9c2799c2 5231 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5232 buffer_address[-2] |= 0x1;
5233 buffer_address[-1] = 0x20;
5234 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5235 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5236 fixP->fx_pcrel_adjust = 2;
151337e8 5237 fragP->fr_fix += 2;
252b5132
RH		 5238 break;
5239 case TAB (PCINDEX, LONG):
9c2799c2 5240 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5241 buffer_address[-2] |= 0x1;
5242 buffer_address[-1] = 0x30;
151337e8 5243 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5244 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5245 fixP->fx_pcrel_adjust = 2;
5246 fragP->fr_fix += 4;
5247 break;
5248 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5249 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5250 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5251 fragP->fr_fix += 2;
5252 break;
5253 case TAB (ABSTOPCREL, LONG):
36759679 5254 if (flag_keep_pcrel)
025987ea
NS		 5255 as_bad_where (fragP->fr_file, fragP->fr_line,
5256 _("Conversion of PC relative displacement to absolute"));
151337e8 5257 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5258 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5259 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5260 abort ();
5261 fragP->fr_opcode[1] &= ~0x3F;
5262 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5263 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5264 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5265 fragP->fr_fix += 4;
252b5132 5266 break;
252b5132 5267 }
2b878742
NS		 5268 if (fixP)
5269 {
5270 fixP->fx_file = fragP->fr_file;
5271 fixP->fx_line = fragP->fr_line;
5272 }
252b5132
RH		 5273}
5274
252b5132 5275void
31302357
AS		 5276md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5277 segT sec ATTRIBUTE_UNUSED,
5278 fragS *fragP)
252b5132
RH		 5279{
5280 md_convert_frag_1 (fragP);
5281}
252b5132
RH		 5282
5283/* Force truly undefined symbols to their maximum size, and generally set up
5284 the frag list to be relaxed
5285 */
5286int
31302357 5287md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5288{
151337e8 5289 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5290 switch (fragP->fr_subtype)
5291 {
151337e8 5292 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5293 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5294 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5295 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5296 {
151337e8
NC		 5297 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5298 && relaxable_symbol (fragP->fr_symbol))
252b5132 5299 {
151337e8
NC		 5300 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5301 }
5302 else if (flag_short_refs)
5303 {
5304 /* Symbol is undefined and we want short ref. */
5305 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5306 }
5307 else
5308 {
151337e8
NC		 5309 /* Symbol is still undefined. Make it LONG. */
5310 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5311 }
5312 break;
151337e8 5313 }
252b5132 5314
151337e8 5315 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5316 {
151337e8
NC		 5317 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5318 && relaxable_symbol (fragP->fr_symbol))
252b5132 5319 {
151337e8 5320 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5321 }
5322 else
5323 {
151337e8
NC		 5324 /* Symbol is undefined and we don't have long branches. */
5325 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5326 }
5327 break;
151337e8 5328 }
252b5132 5329
151337e8 5330 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5331 case TAB (DBCCLBR, SZ_UNDEF):
5332 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5333 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5334 {
8ec6253e
NC		 5335 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5336 && relaxable_symbol (fragP->fr_symbol))
151337e8 5337 || flag_short_refs)
252b5132 5338 {
151337e8 5339 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5340 }
5341 else
5342 {
151337e8 5343 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5344 }
5345 break;
151337e8 5346 }
81d4177b 5347
252b5132
RH		 5348 case TAB (PCINDEX, SZ_UNDEF):
5349 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5350 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5351 {
5352 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5353 }
5354 else
5355 {
5356 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5357 }
5358 break;
5359
151337e8
NC		 5360 case TAB (ABSTOPCREL, SZ_UNDEF):
5361 {
5362 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5363 && relaxable_symbol (fragP->fr_symbol)))
5364 {
5365 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5366 }
5367 else
5368 {
5369 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5370 }
5371 break;
5372 }
5373
252b5132
RH		 5374 default:
5375 break;
5376 }
5377
151337e8 5378 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5379 switch (fragP->fr_subtype)
5380 {
151337e8
NC		 5381 case TAB (BRANCHBWL, BYTE):
5382 case TAB (BRABSJUNC, BYTE):
5383 case TAB (BRABSJCOND, BYTE):
5384 case TAB (BRANCHBW, BYTE):
252b5132 5385 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5386 case we force word mode. If the symbol is at the start of a
5387 frag, and it is the next frag with any data in it (usually
5388 this is just the next frag, but assembler listings may
5389 introduce empty frags), we must use word mode. */
5390 if (fragP->fr_symbol)
252b5132 5391 {
ac62c346 5392 fragS *sym_frag;
252b5132 5393
ac62c346
AM		 5394 sym_frag = symbol_get_frag (fragP->fr_symbol);
5395 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5396 {
ac62c346
AM		 5397 fragS *l;
5398
23b7f870 5399 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5400 if (l->fr_fix != 0)
5401 break;
5402 if (l == sym_frag)
5403 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5404 }
5405 }
5406 break;
5407 default:
5408 break;
5409 }
ac62c346 5410 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5411}
5412
5413#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5414/* the bit-field entries in the relocation_info struct plays hell
5415 with the byte-order problems of cross-assembly. So as a hack,
5416 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5417 you there. -KWK */
252b5132
RH		 5418/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5419 are symbolnum, most sig. byte first. Last byte is broken up with
5420 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5421 nibble as nuthin. (on Sun 3 at least) */
5422/* Translate the internal relocation information into target-specific
92774660 5423 format. */
252b5132
RH		 5424#ifdef comment
5425void
31302357 5426md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5427{
36759679 5428 /* This is easy. */
252b5132 5429 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5430 /* Now the fun stuff. */
252b5132 5431 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5432 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5433 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5434 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5435 | ((ri->r_length << 5) & 0x60)
5436 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5437}
5438
36759679 5439#endif
252b5132 5440
252b5132
RH		 5441#endif /* OBJ_AOUT or OBJ_BOUT */
5442
5443#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5444int md_short_jump_size = 4;
5445int md_long_jump_size = 6;
252b5132
RH		 5446
5447void
31302357
AS		 5448md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5449 fragS *frag ATTRIBUTE_UNUSED,
5450 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5451{
5452 valueT offset;
5453
5454 offset = to_addr - (from_addr + 2);
5455
5456 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5457 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5458}
5459
5460void
31302357
AS		 5461md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5462 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5463{
5464 valueT offset;
5465
6b6e92f4 5466 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5467 {
36759679 5468 if (flag_keep_pcrel)
6b6e92f4 5469 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5470 offset = to_addr - S_GET_VALUE (to_symbol);
5471 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5472 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5473 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5474 0, NO_RELOC);
5475 }
5476 else
5477 {
5478 offset = to_addr - (from_addr + 2);
5479 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5480 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5481 }
5482}
5483
5484#endif
5485
5486/* Different values of OK tell what its OK to return. Things that
5487 aren't OK are an error (what a shock, no?)
5488
5489 0: Everything is OK
3e602632
NC		 5490 10: Absolute 1:8 only
5491 20: Absolute 0:7 only
5492 30: absolute 0:15 only
5493 40: Absolute 0:31 only
5494 50: absolute 0:127 only
252b5132 5495 55: absolute -64:63 only
3e602632 5496 60: absolute -128:127 only
afa2158f 5497 65: absolute 0:511 only
3e602632
NC		 5498 70: absolute 0:4095 only
5499 80: absolute -1, 1:7 only
5500 90: No bignums. */
252b5132
RH		 5501
5502static int
31302357 5503get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5504{
5505 if (exp->exp.X_op == O_absent)
5506 {
36759679 5507 /* Do the same thing the VAX asm does. */
252b5132
RH		 5508 op (exp) = O_constant;
5509 adds (exp) = 0;
5510 subs (exp) = 0;
5511 offs (exp) = 0;
5512 if (ok == 10)
5513 {
5514 as_warn (_("expression out of range: defaulting to 1"));
5515 offs (exp) = 1;
5516 }
5517 }
5518 else if (exp->exp.X_op == O_constant)
5519 {
5520 switch (ok)
5521 {
5522 case 10:
bd17c2c3 5523 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5524 {
5525 as_warn (_("expression out of range: defaulting to 1"));
5526 offs (exp) = 1;
5527 }
5528 break;
5529 case 20:
bd17c2c3 5530 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5531 goto outrange;
5532 break;
5533 case 30:
bd17c2c3 5534 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5535 goto outrange;
5536 break;
5537 case 40:
bd17c2c3 5538 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5539 goto outrange;
5540 break;
5541 case 50:
bd17c2c3 5542 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5543 goto outrange;
5544 break;
5545 case 55:
bd17c2c3 5546 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5547 goto outrange;
5548 break;
5549 case 60:
bd17c2c3 5550 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5551 goto outrange;
afa2158f
NS		 5552 break;
5553 case 65:
5554 if ((valueT) TRUNC (offs (exp)) > 511)
5555 goto outrange;
252b5132
RH		 5556 break;
5557 case 70:
bd17c2c3 5558 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5559 {
5560 outrange:
5561 as_warn (_("expression out of range: defaulting to 0"));
5562 offs (exp) = 0;
5563 }
5564 break;
3e602632 5565 case 80:
bd17c2c3
AM		 5566 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5567 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5568 {
5569 as_warn (_("expression out of range: defaulting to 1"));
5570 offs (exp) = 1;
5571 }
5572 break;
252b5132
RH		 5573 default:
5574 break;
5575 }
5576 }
5577 else if (exp->exp.X_op == O_big)
5578 {
36759679 5579 if (offs (exp) <= 0 /* flonum. */
3e602632 5580 && (ok == 90 /* no bignums */
36759679 5581 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5582 /* If we have a flonum zero, a zero integer should
5583 do as well (e.g., in moveq). */
5584 && generic_floating_point_number.exponent == 0
5585 && generic_floating_point_number.low[0] == 0)))
5586 {
36759679 5587 /* HACK! Turn it into a long. */
252b5132
RH		 5588 LITTLENUM_TYPE words[6];
5589
36759679 5590 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5591 op (exp) = O_constant;
5592 adds (exp) = 0;
5593 subs (exp) = 0;
5594 offs (exp) = words[1] | (words[0] << 16);
5595 }
5596 else if (ok != 0)
5597 {
5598 op (exp) = O_constant;
5599 adds (exp) = 0;
5600 subs (exp) = 0;
5601 offs (exp) = (ok == 10) ? 1 : 0;
5602 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5603 (long) offs (exp));
252b5132
RH		 5604 }
5605 }
5606 else
5607 {
3e602632 5608 if (ok >= 10 && ok <= 80)
252b5132
RH		 5609 {
5610 op (exp) = O_constant;
5611 adds (exp) = 0;
5612 subs (exp) = 0;
5613 offs (exp) = (ok == 10) ? 1 : 0;
5614 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5615 (long) offs (exp));
252b5132
RH		 5616 }
5617 }
5618
5619 if (exp->size != SIZE_UNSPEC)
5620 {
5621 switch (exp->size)
5622 {
5623 case SIZE_UNSPEC:
5624 case SIZE_LONG:
5625 break;
5626 case SIZE_BYTE:
5627 if (!isbyte (offs (exp)))
5628 as_warn (_("expression doesn't fit in BYTE"));
5629 break;
5630 case SIZE_WORD:
5631 if (!isword (offs (exp)))
5632 as_warn (_("expression doesn't fit in WORD"));
5633 break;
5634 }
5635 }
5636
5637 return offs (exp);
5638}
5639
5640/* These are the back-ends for the various machine dependent pseudo-ops. */
5641
5642static void
31302357 5643s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5644{
5645 subseg_set (data_section, 1);
5646 demand_empty_rest_of_line ();
5647}
5648
5649static void
31302357 5650s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5651{
5652 subseg_set (data_section, 2);
5653 demand_empty_rest_of_line ();
5654}
5655
5656static void
31302357 5657s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5658{
5659 /* We don't support putting frags in the BSS segment, we fake it
5660 by marking in_bss, then looking at s_skip for clues. */
5661
5662 subseg_set (bss_section, 0);
5663 demand_empty_rest_of_line ();
5664}
5665
5666static void
31302357 5667s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5668{
5669 register int temp;
5670 register long temp_fill;
5671
5672 temp = 1; /* JF should be 2? */
5673 temp_fill = get_absolute_expression ();
92774660 5674 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5675 frag_align (temp, (int) temp_fill, 0);
5676 demand_empty_rest_of_line ();
5677 record_alignment (now_seg, temp);
5678}
5679
5680static void
31302357 5681s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5682{
5683 demand_empty_rest_of_line ();
5684}
5685\f
5686/* Pseudo-ops handled for MRI compatibility. */
5687
5688/* This function returns non-zero if the argument is a conditional
5689 pseudo-op. This is called when checking whether a pending
5690 alignment is needed. */
5691
5692int
31302357 5693m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5694{
5695 return (pop->poc_handler == s_mri_if
5696 || pop->poc_handler == s_mri_else);
5697}
5698
5699/* Handle an MRI style chip specification. */
5700
5701static void
31302357 5702mri_chip (void)
252b5132
RH		 5703{
5704 char *s;
5705 char c;
5706 int i;
5707
5708 s = input_line_pointer;
5709 /* We can't use get_symbol_end since the processor names are not proper
5710 symbols. */
5711 while (is_part_of_name (c = *input_line_pointer++))
5712 ;
5713 *--input_line_pointer = 0;
266abb8f
NS		 5714 for (i = 0; m68k_cpus[i].name; i++)
5715 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5716 break;
266abb8f 5717 if (!m68k_cpus[i].name)
252b5132
RH		 5718 {
5719 as_bad (_("%s: unrecognized processor name"), s);
5720 *input_line_pointer = c;
5721 ignore_rest_of_line ();
5722 return;
5723 }
5724 *input_line_pointer = c;
5725
5726 if (*input_line_pointer == '/')
5727 current_architecture = 0;
5728 else
5729 current_architecture &= m68881 | m68851;
266abb8f 5730 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5731 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5732
5733 while (*input_line_pointer == '/')
5734 {
5735 ++input_line_pointer;
5736 s = input_line_pointer;
5737 /* We can't use get_symbol_end since the processor names are not
5738 proper symbols. */
5739 while (is_part_of_name (c = *input_line_pointer++))
5740 ;
5741 *--input_line_pointer = 0;
5742 if (strcmp (s, "68881") == 0)
5743 current_architecture |= m68881;
5744 else if (strcmp (s, "68851") == 0)
5745 current_architecture |= m68851;
5746 *input_line_pointer = c;
5747 }
252b5132
RH		 5748}
5749
5750/* The MRI CHIP pseudo-op. */
5751
5752static void
31302357 5753s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5754{
5755 char *stop = NULL;
5756 char stopc;
5757
5758 if (flag_mri)
5759 stop = mri_comment_field (&stopc);
5760 mri_chip ();
5761 if (flag_mri)
5762 mri_comment_end (stop, stopc);
5763 demand_empty_rest_of_line ();
5764}
5765
5766/* The MRI FOPT pseudo-op. */
5767
5768static void
31302357 5769s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5770{
5771 SKIP_WHITESPACE ();
5772
5773 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5774 {
5775 int temp;
5776
5777 input_line_pointer += 3;
5778 temp = get_absolute_expression ();
5779 if (temp < 0 || temp > 7)
5780 as_bad (_("bad coprocessor id"));
5781 else
5782 m68k_float_copnum = COP0 + temp;
5783 }
5784 else
5785 {
5786 as_bad (_("unrecognized fopt option"));
5787 ignore_rest_of_line ();
5788 return;
5789 }
5790
5791 demand_empty_rest_of_line ();
5792}
5793
5794/* The structure used to handle the MRI OPT pseudo-op. */
5795
5796struct opt_action
5797{
5798 /* The name of the option. */
5799 const char *name;
5800
5801 /* If this is not NULL, just call this function. The first argument
5802 is the ARG field of this structure, the second argument is
5803 whether the option was negated. */
31302357 5804 void (*pfn) (int arg, int on);
252b5132
RH		 5805
5806 /* If this is not NULL, and the PFN field is NULL, set the variable
5807 this points to. Set it to the ARG field if the option was not
5808 negated, and the NOTARG field otherwise. */
5809 int *pvar;
5810
5811 /* The value to pass to PFN or to assign to *PVAR. */
5812 int arg;
5813
5814 /* The value to assign to *PVAR if the option is negated. If PFN is
5815 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5816 the option may not be negated. */
5817 int notarg;
5818};
5819
5820/* The table used to handle the MRI OPT pseudo-op. */
5821
31302357
AS		 5822static void skip_to_comma (int, int);
5823static void opt_nest (int, int);
5824static void opt_chip (int, int);
5825static void opt_list (int, int);
5826static void opt_list_symbols (int, int);
252b5132
RH		 5827
5828static const struct opt_action opt_table[] =
5829{
5830 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5831
5832 /* We do relaxing, so there is little use for these options. */
5833 { "b", 0, 0, 0, 0 },
5834 { "brs", 0, 0, 0, 0 },
5835 { "brb", 0, 0, 0, 0 },
5836 { "brl", 0, 0, 0, 0 },
5837 { "brw", 0, 0, 0, 0 },
5838
5839 { "c", 0, 0, 0, 0 },
5840 { "cex", 0, 0, 0, 0 },
5841 { "case", 0, &symbols_case_sensitive, 1, 0 },
5842 { "cl", 0, 0, 0, 0 },
5843 { "cre", 0, 0, 0, 0 },
5844 { "d", 0, &flag_keep_locals, 1, 0 },
5845 { "e", 0, 0, 0, 0 },
5846 { "f", 0, &flag_short_refs, 1, 0 },
5847 { "frs", 0, &flag_short_refs, 1, 0 },
5848 { "frl", 0, &flag_short_refs, 0, 1 },
5849 { "g", 0, 0, 0, 0 },
5850 { "i", 0, 0, 0, 0 },
5851 { "m", 0, 0, 0, 0 },
5852 { "mex", 0, 0, 0, 0 },
5853 { "mc", 0, 0, 0, 0 },
5854 { "md", 0, 0, 0, 0 },
5855 { "nest", opt_nest, 0, 0, 0 },
5856 { "next", skip_to_comma, 0, 0, 0 },
5857 { "o", 0, 0, 0, 0 },
5858 { "old", 0, 0, 0, 0 },
5859 { "op", skip_to_comma, 0, 0, 0 },
5860 { "pco", 0, 0, 0, 0 },
5861 { "p", opt_chip, 0, 0, 0 },
5862 { "pcr", 0, 0, 0, 0 },
5863 { "pcs", 0, 0, 0, 0 },
5864 { "r", 0, 0, 0, 0 },
5865 { "quick", 0, &m68k_quick, 1, 0 },
5866 { "rel32", 0, &m68k_rel32, 1, 0 },
5867 { "s", opt_list, 0, 0, 0 },
5868 { "t", opt_list_symbols, 0, 0, 0 },
5869 { "w", 0, &flag_no_warnings, 0, 1 },
5870 { "x", 0, 0, 0, 0 }
5871};
5872
8fce3f5e 5873#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5874
5875/* The MRI OPT pseudo-op. */
5876
5877static void
31302357 5878s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5879{
5880 do
5881 {
5882 int t;
5883 char *s;
5884 char c;
5885 int i;
5886 const struct opt_action *o;
5887
5888 SKIP_WHITESPACE ();
5889
5890 t = 1;
5891 if (*input_line_pointer == '-')
5892 {
5893 ++input_line_pointer;
5894 t = 0;
5895 }
5896 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5897 {
5898 input_line_pointer += 2;
5899 t = 0;
5900 }
5901
5902 s = input_line_pointer;
5903 c = get_symbol_end ();
5904
5905 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5906 {
5907 if (strcasecmp (s, o->name) == 0)
5908 {
5909 if (o->pfn)
5910 {
5911 /* Restore input_line_pointer now in case the option
5912 takes arguments. */
5913 *input_line_pointer = c;
5914 (*o->pfn) (o->arg, t);
5915 }
5916 else if (o->pvar != NULL)
5917 {
5918 if (! t && o->arg == o->notarg)
5919 as_bad (_("option `%s' may not be negated"), s);
5920 *input_line_pointer = c;
5921 *o->pvar = t ? o->arg : o->notarg;
5922 }
5923 else
5924 *input_line_pointer = c;
5925 break;
5926 }
5927 }
5928 if (i >= OPTCOUNT)
5929 {
5930 as_bad (_("option `%s' not recognized"), s);
5931 *input_line_pointer = c;
5932 }
5933 }
5934 while (*input_line_pointer++ == ',');
5935
5936 /* Move back to terminating character. */
5937 --input_line_pointer;
5938 demand_empty_rest_of_line ();
5939}
5940
5941/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5942 not support and which take arguments. */
252b5132
RH		 5943
5944static void
31302357 5945skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5946{
5947 while (*input_line_pointer != ','
5948 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5949 ++input_line_pointer;
5950}
5951
5952/* Handle the OPT NEST=depth option. */
5953
5954static void
31302357 5955opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5956{
5957 if (*input_line_pointer != '=')
5958 {
5959 as_bad (_("bad format of OPT NEST=depth"));
5960 return;
5961 }
5962
5963 ++input_line_pointer;
5964 max_macro_nest = get_absolute_expression ();
5965}
5966
5967/* Handle the OPT P=chip option. */
5968
5969static void
31302357 5970opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5971{
5972 if (*input_line_pointer != '=')
5973 {
5974 /* This is just OPT P, which we do not support. */
5975 return;
5976 }
5977
5978 ++input_line_pointer;
5979 mri_chip ();
5980}
5981
5982/* Handle the OPT S option. */
5983
5984static void
31302357 5985opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5986{
5987 listing_list (on);
5988}
5989
5990/* Handle the OPT T option. */
5991
5992static void
31302357 5993opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5994{
5995 if (on)
5996 listing |= LISTING_SYMBOLS;
5997 else
8a104df9 5998 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5999}
6000
6001/* Handle the MRI REG pseudo-op. */
6002
6003static void
31302357 6004s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6005{
6006 char *s;
6007 int c;
6008 struct m68k_op rop;
6009 int mask;
6010 char *stop = NULL;
6011 char stopc;
6012
6013 if (line_label == NULL)
6014 {
6015 as_bad (_("missing label"));
6016 ignore_rest_of_line ();
6017 return;
6018 }
6019
6020 if (flag_mri)
6021 stop = mri_comment_field (&stopc);
6022
6023 SKIP_WHITESPACE ();
6024
6025 s = input_line_pointer;
3882b010 6026 while (ISALNUM (*input_line_pointer)
252b5132
RH		 6027#ifdef REGISTER_PREFIX
6028 || *input_line_pointer == REGISTER_PREFIX
6029#endif
6030 || *input_line_pointer == '/'
6031 || *input_line_pointer == '-')
6032 ++input_line_pointer;
6033 c = *input_line_pointer;
6034 *input_line_pointer = '\0';
6035
6036 if (m68k_ip_op (s, &rop) != 0)
6037 {
6038 if (rop.error == NULL)
6039 as_bad (_("bad register list"));
6040 else
6041 as_bad (_("bad register list: %s"), rop.error);
6042 *input_line_pointer = c;
6043 ignore_rest_of_line ();
6044 return;
6045 }
6046
6047 *input_line_pointer = c;
6048
6049 if (rop.mode == REGLST)
6050 mask = rop.mask;
6051 else if (rop.mode == DREG)
6052 mask = 1 << (rop.reg - DATA0);
6053 else if (rop.mode == AREG)
6054 mask = 1 << (rop.reg - ADDR0 + 8);
6055 else if (rop.mode == FPREG)
6056 mask = 1 << (rop.reg - FP0 + 16);
6057 else if (rop.mode == CONTROL
6058 && rop.reg == FPI)
6059 mask = 1 << 24;
6060 else if (rop.mode == CONTROL
6061 && rop.reg == FPS)
6062 mask = 1 << 25;
6063 else if (rop.mode == CONTROL
6064 && rop.reg == FPC)
6065 mask = 1 << 26;
6066 else
6067 {
6068 as_bad (_("bad register list"));
6069 ignore_rest_of_line ();
6070 return;
6071 }
6072
6073 S_SET_SEGMENT (line_label, reg_section);
6074 S_SET_VALUE (line_label, ~mask);
49309057 6075 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 6076
6077 if (flag_mri)
6078 mri_comment_end (stop, stopc);
6079
6080 demand_empty_rest_of_line ();
6081}
6082
6083/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6084
6085struct save_opts
6086{
6087 struct save_opts *next;
6088 int abspcadd;
6089 int symbols_case_sensitive;
6090 int keep_locals;
6091 int short_refs;
6092 int architecture;
2da12c60 6093 const enum m68k_register *control_regs;
252b5132
RH		 6094 int quick;
6095 int rel32;
6096 int listing;
6097 int no_warnings;
6098 /* FIXME: We don't save OPT S. */
6099};
6100
6101/* This variable holds the stack of saved options. */
6102
6103static struct save_opts *save_stack;
6104
6105/* The MRI SAVE pseudo-op. */
6106
6107static void
31302357 6108s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6109{
6110 struct save_opts *s;
6111
6112 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6113 s->abspcadd = m68k_abspcadd;
6114 s->symbols_case_sensitive = symbols_case_sensitive;
6115 s->keep_locals = flag_keep_locals;
6116 s->short_refs = flag_short_refs;
6117 s->architecture = current_architecture;
2da12c60 6118 s->control_regs = control_regs;
252b5132
RH		 6119 s->quick = m68k_quick;
6120 s->rel32 = m68k_rel32;
6121 s->listing = listing;
6122 s->no_warnings = flag_no_warnings;
6123
6124 s->next = save_stack;
6125 save_stack = s;
6126
6127 demand_empty_rest_of_line ();
6128}
6129
6130/* The MRI RESTORE pseudo-op. */
6131
6132static void
31302357 6133s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6134{
6135 struct save_opts *s;
6136
6137 if (save_stack == NULL)
6138 {
6139 as_bad (_("restore without save"));
6140 ignore_rest_of_line ();
6141 return;
6142 }
6143
6144 s = save_stack;
6145 save_stack = s->next;
6146
6147 m68k_abspcadd = s->abspcadd;
6148 symbols_case_sensitive = s->symbols_case_sensitive;
6149 flag_keep_locals = s->keep_locals;
6150 flag_short_refs = s->short_refs;
6151 current_architecture = s->architecture;
2da12c60 6152 control_regs = s->control_regs;
252b5132
RH		 6153 m68k_quick = s->quick;
6154 m68k_rel32 = s->rel32;
6155 listing = s->listing;
6156 flag_no_warnings = s->no_warnings;
6157
6158 free (s);
6159
6160 demand_empty_rest_of_line ();
6161}
6162
6163/* Types of MRI structured control directives. */
6164
6165enum mri_control_type
6166{
6167 mri_for,
6168 mri_if,
6169 mri_repeat,
6170 mri_while
6171};
6172
6173/* This structure is used to stack the MRI structured control
6174 directives. */
6175
6176struct mri_control_info
6177{
6178 /* The directive within which this one is enclosed. */
6179 struct mri_control_info *outer;
6180
6181 /* The type of directive. */
6182 enum mri_control_type type;
6183
6184 /* Whether an ELSE has been in an IF. */
6185 int else_seen;
6186
6187 /* The add or sub statement at the end of a FOR. */
6188 char *incr;
6189
6190 /* The label of the top of a FOR or REPEAT loop. */
6191 char *top;
6192
6193 /* The label to jump to for the next iteration, or the else
6194 expression of a conditional. */
6195 char *next;
6196
6197 /* The label to jump to to break out of the loop, or the label past
6198 the end of a conditional. */
6199 char *bottom;
6200};
6201
6202/* The stack of MRI structured control directives. */
6203
6204static struct mri_control_info *mri_control_stack;
6205
6206/* The current MRI structured control directive index number, used to
6207 generate label names. */
6208
6209static int mri_control_index;
6210
252b5132
RH		 6211/* Assemble an instruction for an MRI structured control directive. */
6212
6213static void
31302357 6214mri_assemble (char *str)
252b5132
RH		 6215{
6216 char *s;
6217
6218 /* md_assemble expects the opcode to be in lower case. */
6219 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6220 *s = TOLOWER (*s);
252b5132
RH		 6221
6222 md_assemble (str);
6223}
6224
6225/* Generate a new MRI label structured control directive label name. */
6226
6227static char *
31302357 6228mri_control_label (void)
252b5132
RH		 6229{
6230 char *n;
6231
6232 n = (char *) xmalloc (20);
6233 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6234 ++mri_control_index;
6235 return n;
6236}
6237
6238/* Create a new MRI structured control directive. */
6239
6240static struct mri_control_info *
31302357 6241push_mri_control (enum mri_control_type type)
252b5132
RH		 6242{
6243 struct mri_control_info *n;
6244
6245 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6246
6247 n->type = type;
6248 n->else_seen = 0;
6249 if (type == mri_if || type == mri_while)
6250 n->top = NULL;
6251 else
6252 n->top = mri_control_label ();
6253 n->next = mri_control_label ();
6254 n->bottom = mri_control_label ();
6255
6256 n->outer = mri_control_stack;
6257 mri_control_stack = n;
6258
6259 return n;
6260}
6261
6262/* Pop off the stack of MRI structured control directives. */
6263
6264static void
31302357 6265pop_mri_control (void)
252b5132
RH		 6266{
6267 struct mri_control_info *n;
6268
6269 n = mri_control_stack;
6270 mri_control_stack = n->outer;
6271 if (n->top != NULL)
6272 free (n->top);
6273 free (n->next);
6274 free (n->bottom);
6275 free (n);
6276}
6277
6278/* Recognize a condition code in an MRI structured control expression. */
6279
6280static int
31302357 6281parse_mri_condition (int *pcc)
252b5132
RH		 6282{
6283 char c1, c2;
6284
6285 know (*input_line_pointer == '<');
6286
6287 ++input_line_pointer;
6288 c1 = *input_line_pointer++;
6289 c2 = *input_line_pointer++;
6290
6291 if (*input_line_pointer != '>')
6292 {
6293 as_bad (_("syntax error in structured control directive"));
6294 return 0;
6295 }
6296
6297 ++input_line_pointer;
6298 SKIP_WHITESPACE ();
6299
3882b010
L		 6300 c1 = TOLOWER (c1);
6301 c2 = TOLOWER (c2);
252b5132
RH		 6302
6303 *pcc = (c1 << 8) | c2;
6304
6305 return 1;
6306}
6307
6308/* Parse a single operand in an MRI structured control expression. */
6309
6310static int
31302357
AS		 6311parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6312 char **rightstart, char **rightstop)
252b5132
RH		 6313{
6314 char *s;
6315
6316 SKIP_WHITESPACE ();
6317
6318 *pcc = -1;
6319 *leftstart = NULL;
6320 *leftstop = NULL;
6321 *rightstart = NULL;
6322 *rightstop = NULL;
6323
6324 if (*input_line_pointer == '<')
6325 {
6326 /* It's just a condition code. */
6327 return parse_mri_condition (pcc);
6328 }
6329
6330 /* Look ahead for the condition code. */
6331 for (s = input_line_pointer; *s != '\0'; ++s)
6332 {
6333 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6334 break;
6335 }
6336 if (*s == '\0')
6337 {
6338 as_bad (_("missing condition code in structured control directive"));
6339 return 0;
6340 }
6341
6342 *leftstart = input_line_pointer;
6343 *leftstop = s;
6344 if (*leftstop > *leftstart
6345 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6346 --*leftstop;
6347
6348 input_line_pointer = s;
6349 if (! parse_mri_condition (pcc))
6350 return 0;
6351
6352 /* Look ahead for AND or OR or end of line. */
6353 for (s = input_line_pointer; *s != '\0'; ++s)
6354 {
e1f44d10
NC		 6355 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6356 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6357 ^^^ ^^ */
8a104df9
KH		 6358 if ((s == input_line_pointer
6359 || *(s-1) == ' '
6360 || *(s-1) == '\t')
6361 && ((strncasecmp (s, "AND", 3) == 0
6362 && (s[3] == '.' || ! is_part_of_name (s[3])))
6363 || (strncasecmp (s, "OR", 2) == 0
6364 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6365 break;
252b5132
RH		 6366 }
6367
6368 *rightstart = input_line_pointer;
6369 *rightstop = s;
6370 if (*rightstop > *rightstart
6371 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6372 --*rightstop;
6373
6374 input_line_pointer = s;
6375
6376 return 1;
6377}
6378
6379#define MCC(b1, b2) (((b1) << 8) | (b2))
6380
6381/* Swap the sense of a condition. This changes the condition so that
6382 it generates the same result when the operands are swapped. */
6383
6384static int
31302357 6385swap_mri_condition (int cc)
252b5132
RH		 6386{
6387 switch (cc)
6388 {
6389 case MCC ('h', 'i'): return MCC ('c', 's');
6390 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6391 /* <HS> is an alias for <CC>. */
e1f44d10 6392 case MCC ('h', 's'):
252b5132 6393 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6394 /* <LO> is an alias for <CS>. */
e1f44d10 6395 case MCC ('l', 'o'):
252b5132
RH		 6396 case MCC ('c', 's'): return MCC ('h', 'i');
6397 case MCC ('p', 'l'): return MCC ('m', 'i');
6398 case MCC ('m', 'i'): return MCC ('p', 'l');
6399 case MCC ('g', 'e'): return MCC ('l', 'e');
6400 case MCC ('l', 't'): return MCC ('g', 't');
6401 case MCC ('g', 't'): return MCC ('l', 't');
6402 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6403 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6404 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6405 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6406 case MCC ('v', 'c'):
6407 case MCC ('v', 's'):
6408 default :
6409 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6410 (char) (cc >> 8), (char) (cc));
6411 break;
252b5132
RH		 6412 }
6413 return cc;
6414}
6415
6416/* Reverse the sense of a condition. */
6417
6418static int
31302357 6419reverse_mri_condition (int cc)
252b5132
RH		 6420{
6421 switch (cc)
6422 {
6423 case MCC ('h', 'i'): return MCC ('l', 's');
6424 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6425 /* <HS> is an alias for <CC> */
6426 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6427 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6428 /* <LO> is an alias for <CS> */
6429 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6430 case MCC ('c', 's'): return MCC ('c', 'c');
6431 case MCC ('n', 'e'): return MCC ('e', 'q');
6432 case MCC ('e', 'q'): return MCC ('n', 'e');
6433 case MCC ('v', 'c'): return MCC ('v', 's');
6434 case MCC ('v', 's'): return MCC ('v', 'c');
6435 case MCC ('p', 'l'): return MCC ('m', 'i');
6436 case MCC ('m', 'i'): return MCC ('p', 'l');
6437 case MCC ('g', 'e'): return MCC ('l', 't');
6438 case MCC ('l', 't'): return MCC ('g', 'e');
6439 case MCC ('g', 't'): return MCC ('l', 'e');
6440 case MCC ('l', 'e'): return MCC ('g', 't');
6441 }
6442 return cc;
6443}
6444
6445/* Build an MRI structured control expression. This generates test
6446 and branch instructions. It goes to TRUELAB if the condition is
6447 true, and to FALSELAB if the condition is false. Exactly one of
6448 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6449 is the size qualifier for the expression. EXTENT is the size to
6450 use for the branch. */
6451
6452static void
31302357
AS		 6453build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6454 char *rightstart, char *rightstop,
6455 const char *truelab, const char *falselab,
6456 int extent)
252b5132
RH		 6457{
6458 char *buf;
6459 char *s;
6460
6461 if (leftstart != NULL)
6462 {
6463 struct m68k_op leftop, rightop;
6464 char c;
6465
6466 /* Swap the compare operands, if necessary, to produce a legal
6467 m68k compare instruction. Comparing a register operand with
6468 a non-register operand requires the register to be on the
6469 right (cmp, cmpa). Comparing an immediate value with
6470 anything requires the immediate value to be on the left
6471 (cmpi). */
6472
6473 c = *leftstop;
6474 *leftstop = '\0';
6475 (void) m68k_ip_op (leftstart, &leftop);
6476 *leftstop = c;
6477
6478 c = *rightstop;
6479 *rightstop = '\0';
6480 (void) m68k_ip_op (rightstart, &rightop);
6481 *rightstop = c;
6482
6483 if (rightop.mode == IMMED
6484 || ((leftop.mode == DREG || leftop.mode == AREG)
6485 && (rightop.mode != DREG && rightop.mode != AREG)))
6486 {
6487 char *temp;
6488
31302357
AS		 6489 /* Correct conditional handling:
6490 if #1 <lt> d0 then ;means if (1 < d0)
6491 ...
6492 endi
e1f44d10 6493
31302357 6494 should assemble to:
e1f44d10 6495
31302357
AS		 6496 cmp #1,d0 if we do *not* swap the operands
6497 bgt true we need the swapped condition!
6498 ble false
6499 true:
6500 ...
6501 false:
6502 */
252b5132
RH		 6503 temp = leftstart;
6504 leftstart = rightstart;
6505 rightstart = temp;
6506 temp = leftstop;
6507 leftstop = rightstop;
6508 rightstop = temp;
8a104df9
KH		 6509 }
6510 else
6511 {
e1f44d10 6512 cc = swap_mri_condition (cc);
252b5132
RH		 6513 }
6514 }
6515
6516 if (truelab == NULL)
6517 {
6518 cc = reverse_mri_condition (cc);
6519 truelab = falselab;
6520 }
92774660 6521
252b5132
RH		 6522 if (leftstart != NULL)
6523 {
6524 buf = (char *) xmalloc (20
6525 + (leftstop - leftstart)
6526 + (rightstop - rightstart));
6527 s = buf;
6528 *s++ = 'c';
6529 *s++ = 'm';
6530 *s++ = 'p';
6531 if (qual != '\0')
3882b010 6532 *s++ = TOLOWER (qual);
252b5132
RH		 6533 *s++ = ' ';
6534 memcpy (s, leftstart, leftstop - leftstart);
6535 s += leftstop - leftstart;
6536 *s++ = ',';
6537 memcpy (s, rightstart, rightstop - rightstart);
6538 s += rightstop - rightstart;
6539 *s = '\0';
6540 mri_assemble (buf);
6541 free (buf);
6542 }
92774660 6543
252b5132
RH		 6544 buf = (char *) xmalloc (20 + strlen (truelab));
6545 s = buf;
6546 *s++ = 'b';
6547 *s++ = cc >> 8;
6548 *s++ = cc & 0xff;
6549 if (extent != '\0')
3882b010 6550 *s++ = TOLOWER (extent);
252b5132
RH		 6551 *s++ = ' ';
6552 strcpy (s, truelab);
6553 mri_assemble (buf);
6554 free (buf);
6555}
6556
6557/* Parse an MRI structured control expression. This generates test
6558 and branch instructions. STOP is where the expression ends. It
6559 goes to TRUELAB if the condition is true, and to FALSELAB if the
6560 condition is false. Exactly one of TRUELAB and FALSELAB will be
6561 NULL, meaning to fall through. QUAL is the size qualifier for the
6562 expression. EXTENT is the size to use for the branch. */
6563
6564static void
31302357
AS		 6565parse_mri_control_expression (char *stop, int qual, const char *truelab,
6566 const char *falselab, int extent)
252b5132
RH		 6567{
6568 int c;
6569 int cc;
6570 char *leftstart;
6571 char *leftstop;
6572 char *rightstart;
6573 char *rightstop;
6574
6575 c = *stop;
6576 *stop = '\0';
6577
6578 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6579 &rightstart, &rightstop))
6580 {
6581 *stop = c;
6582 return;
6583 }
6584
6585 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6586 {
6587 const char *flab;
6588
6589 if (falselab != NULL)
6590 flab = falselab;
6591 else
6592 flab = mri_control_label ();
6593
6594 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6595 rightstop, (const char *) NULL, flab, extent);
6596
6597 input_line_pointer += 3;
6598 if (*input_line_pointer != '.'
6599 || input_line_pointer[1] == '\0')
6600 qual = '\0';
6601 else
6602 {
6603 qual = input_line_pointer[1];
6604 input_line_pointer += 2;
6605 }
6606
6607 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6608 &rightstart, &rightstop))
6609 {
6610 *stop = c;
6611 return;
6612 }
6613
6614 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6615 rightstop, truelab, falselab, extent);
6616
6617 if (falselab == NULL)
6618 colon (flab);
6619 }
6620 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6621 {
6622 const char *tlab;
6623
6624 if (truelab != NULL)
6625 tlab = truelab;
6626 else
6627 tlab = mri_control_label ();
6628
6629 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6630 rightstop, tlab, (const char *) NULL, extent);
6631
6632 input_line_pointer += 2;
6633 if (*input_line_pointer != '.'
6634 || input_line_pointer[1] == '\0')
6635 qual = '\0';
6636 else
6637 {
6638 qual = input_line_pointer[1];
6639 input_line_pointer += 2;
6640 }
6641
6642 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6643 &rightstart, &rightstop))
6644 {
6645 *stop = c;
6646 return;
6647 }
6648
6649 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6650 rightstop, truelab, falselab, extent);
6651
6652 if (truelab == NULL)
6653 colon (tlab);
6654 }
6655 else
6656 {
6657 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6658 rightstop, truelab, falselab, extent);
6659 }
6660
6661 *stop = c;
6662 if (input_line_pointer != stop)
6663 as_bad (_("syntax error in structured control directive"));
6664}
6665
6666/* Handle the MRI IF pseudo-op. This may be a structured control
6667 directive, or it may be a regular assembler conditional, depending
6668 on its operands. */
6669
6670static void
31302357 6671s_mri_if (int qual)
252b5132
RH		 6672{
6673 char *s;
6674 int c;
6675 struct mri_control_info *n;
6676
6677 /* A structured control directive must end with THEN with an
6678 optional qualifier. */
6679 s = input_line_pointer;
e1f44d10
NC		 6680 /* We only accept '*' as introduction of comments if preceded by white space
6681 or at first column of a line (I think this can't actually happen here?)
6682 This is important when assembling:
6683 if d0 <ne> 12(a0,d0*2) then
36759679 6684 if d0 <ne> #CONST*20 then. */
31302357
AS		 6685 while (! (is_end_of_line[(unsigned char) *s]
6686 || (flag_mri
6687 && *s == '*'
6688 && (s == input_line_pointer
6689 || *(s-1) == ' '
6690 || *(s-1) == '\t'))))
252b5132
RH		 6691 ++s;
6692 --s;
6693 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6694 --s;
6695
6696 if (s - input_line_pointer > 1
6697 && s[-1] == '.')
6698 s -= 2;
6699
6700 if (s - input_line_pointer < 3
6701 || strncasecmp (s - 3, "THEN", 4) != 0)
6702 {
6703 if (qual != '\0')
6704 {
6705 as_bad (_("missing then"));
6706 ignore_rest_of_line ();
6707 return;
6708 }
6709
6710 /* It's a conditional. */
6711 s_if (O_ne);
6712 return;
6713 }
6714
6715 /* Since this might be a conditional if, this pseudo-op will be
6716 called even if we are supported to be ignoring input. Double
6717 check now. Clobber *input_line_pointer so that ignore_input
6718 thinks that this is not a special pseudo-op. */
6719 c = *input_line_pointer;
6720 *input_line_pointer = 0;
6721 if (ignore_input ())
6722 {
6723 *input_line_pointer = c;
6724 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6725 ++input_line_pointer;
6726 demand_empty_rest_of_line ();
6727 return;
6728 }
6729 *input_line_pointer = c;
6730
6731 n = push_mri_control (mri_if);
6732
6733 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6734 n->next, s[1] == '.' ? s[2] : '\0');
6735
6736 if (s[1] == '.')
6737 input_line_pointer = s + 3;
6738 else
6739 input_line_pointer = s + 1;
6740
6741 if (flag_mri)
6742 {
6743 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6744 ++input_line_pointer;
6745 }
6746
6747 demand_empty_rest_of_line ();
6748}
6749
6750/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6751 structured IF, associate the ELSE with the IF. Otherwise, assume
6752 it is a conditional else. */
6753
6754static void
31302357 6755s_mri_else (int qual)
252b5132
RH		 6756{
6757 int c;
6758 char *buf;
6759 char q[2];
6760
6761 if (qual == '\0'
6762 && (mri_control_stack == NULL
6763 || mri_control_stack->type != mri_if
6764 || mri_control_stack->else_seen))
6765 {
6766 s_else (0);
6767 return;
6768 }
6769
6770 c = *input_line_pointer;
6771 *input_line_pointer = 0;
6772 if (ignore_input ())
6773 {
6774 *input_line_pointer = c;
6775 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6776 ++input_line_pointer;
6777 demand_empty_rest_of_line ();
6778 return;
6779 }
6780 *input_line_pointer = c;
6781
6782 if (mri_control_stack == NULL
6783 || mri_control_stack->type != mri_if
6784 || mri_control_stack->else_seen)
6785 {
6786 as_bad (_("else without matching if"));
6787 ignore_rest_of_line ();
6788 return;
6789 }
6790
6791 mri_control_stack->else_seen = 1;
6792
6793 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6794 q[0] = TOLOWER (qual);
252b5132
RH		 6795 q[1] = '\0';
6796 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6797 mri_assemble (buf);
6798 free (buf);
6799
6800 colon (mri_control_stack->next);
6801
6802 if (flag_mri)
6803 {
6804 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6805 ++input_line_pointer;
6806 }
6807
6808 demand_empty_rest_of_line ();
6809}
6810
6811/* Handle the MRI ENDI pseudo-op. */
6812
6813static void
31302357 6814s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6815{
6816 if (mri_control_stack == NULL
6817 || mri_control_stack->type != mri_if)
6818 {
6819 as_bad (_("endi without matching if"));
6820 ignore_rest_of_line ();
6821 return;
6822 }
6823
6824 /* ignore_input will not return true for ENDI, so we don't need to
6825 worry about checking it again here. */
6826
6827 if (! mri_control_stack->else_seen)
6828 colon (mri_control_stack->next);
6829 colon (mri_control_stack->bottom);
6830
6831 pop_mri_control ();
6832
6833 if (flag_mri)
6834 {
6835 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6836 ++input_line_pointer;
6837 }
6838
6839 demand_empty_rest_of_line ();
6840}
6841
6842/* Handle the MRI BREAK pseudo-op. */
6843
6844static void
31302357 6845s_mri_break (int extent)
252b5132
RH		 6846{
6847 struct mri_control_info *n;
6848 char *buf;
6849 char ex[2];
6850
6851 n = mri_control_stack;
6852 while (n != NULL
6853 && n->type != mri_for
6854 && n->type != mri_repeat
6855 && n->type != mri_while)
6856 n = n->outer;
6857 if (n == NULL)
6858 {
6859 as_bad (_("break outside of structured loop"));
6860 ignore_rest_of_line ();
6861 return;
6862 }
6863
6864 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6865 ex[0] = TOLOWER (extent);
252b5132
RH		 6866 ex[1] = '\0';
6867 sprintf (buf, "bra%s %s", ex, n->bottom);
6868 mri_assemble (buf);
6869 free (buf);
6870
6871 if (flag_mri)
6872 {
6873 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6874 ++input_line_pointer;
6875 }
6876
6877 demand_empty_rest_of_line ();
6878}
6879
6880/* Handle the MRI NEXT pseudo-op. */
6881
6882static void
31302357 6883s_mri_next (int extent)
252b5132
RH		 6884{
6885 struct mri_control_info *n;
6886 char *buf;
6887 char ex[2];
6888
6889 n = mri_control_stack;
6890 while (n != NULL
6891 && n->type != mri_for
6892 && n->type != mri_repeat
6893 && n->type != mri_while)
6894 n = n->outer;
6895 if (n == NULL)
6896 {
6897 as_bad (_("next outside of structured loop"));
6898 ignore_rest_of_line ();
6899 return;
6900 }
6901
6902 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6903 ex[0] = TOLOWER (extent);
252b5132
RH		 6904 ex[1] = '\0';
6905 sprintf (buf, "bra%s %s", ex, n->next);
6906 mri_assemble (buf);
6907 free (buf);
6908
6909 if (flag_mri)
6910 {
6911 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6912 ++input_line_pointer;
6913 }
6914
6915 demand_empty_rest_of_line ();
6916}
6917
6918/* Handle the MRI FOR pseudo-op. */
6919
6920static void
31302357 6921s_mri_for (int qual)
252b5132
RH		 6922{
6923 const char *varstart, *varstop;
6924 const char *initstart, *initstop;
6925 const char *endstart, *endstop;
6926 const char *bystart, *bystop;
6927 int up;
6928 int by;
6929 int extent;
6930 struct mri_control_info *n;
6931 char *buf;
6932 char *s;
6933 char ex[2];
6934
6935 /* The syntax is
6936 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6937 */
6938
6939 SKIP_WHITESPACE ();
6940 varstart = input_line_pointer;
6941
6942 /* Look for the '='. */
6943 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6944 && *input_line_pointer != '=')
6945 ++input_line_pointer;
6946 if (*input_line_pointer != '=')
6947 {
6948 as_bad (_("missing ="));
6949 ignore_rest_of_line ();
6950 return;
6951 }
6952
6953 varstop = input_line_pointer;
6954 if (varstop > varstart
6955 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6956 --varstop;
6957
6958 ++input_line_pointer;
6959
6960 initstart = input_line_pointer;
6961
6962 /* Look for TO or DOWNTO. */
6963 up = 1;
6964 initstop = NULL;
6965 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6966 {
6967 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6968 && ! is_part_of_name (input_line_pointer[2]))
6969 {
6970 initstop = input_line_pointer;
6971 input_line_pointer += 2;
6972 break;
6973 }
6974 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6975 && ! is_part_of_name (input_line_pointer[6]))
6976 {
6977 initstop = input_line_pointer;
6978 up = 0;
6979 input_line_pointer += 6;
6980 break;
6981 }
6982 ++input_line_pointer;
6983 }
6984 if (initstop == NULL)
6985 {
6986 as_bad (_("missing to or downto"));
6987 ignore_rest_of_line ();
6988 return;
6989 }
6990 if (initstop > initstart
6991 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6992 --initstop;
6993
6994 SKIP_WHITESPACE ();
6995 endstart = input_line_pointer;
6996
6997 /* Look for BY or DO. */
6998 by = 0;
6999 endstop = NULL;
7000 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7001 {
7002 if (strncasecmp (input_line_pointer, "BY", 2) == 0
7003 && ! is_part_of_name (input_line_pointer[2]))
7004 {
7005 endstop = input_line_pointer;
7006 by = 1;
7007 input_line_pointer += 2;
7008 break;
7009 }
7010 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7011 && (input_line_pointer[2] == '.'
7012 || ! is_part_of_name (input_line_pointer[2])))
7013 {
7014 endstop = input_line_pointer;
7015 input_line_pointer += 2;
7016 break;
7017 }
7018 ++input_line_pointer;
7019 }
7020 if (endstop == NULL)
7021 {
7022 as_bad (_("missing do"));
7023 ignore_rest_of_line ();
7024 return;
7025 }
7026 if (endstop > endstart
7027 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
7028 --endstop;
7029
7030 if (! by)
7031 {
7032 bystart = "#1";
7033 bystop = bystart + 2;
7034 }
7035 else
7036 {
7037 SKIP_WHITESPACE ();
7038 bystart = input_line_pointer;
7039
7040 /* Look for DO. */
7041 bystop = NULL;
7042 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7043 {
7044 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7045 && (input_line_pointer[2] == '.'
7046 || ! is_part_of_name (input_line_pointer[2])))
7047 {
7048 bystop = input_line_pointer;
7049 input_line_pointer += 2;
7050 break;
7051 }
7052 ++input_line_pointer;
7053 }
7054 if (bystop == NULL)
7055 {
7056 as_bad (_("missing do"));
7057 ignore_rest_of_line ();
7058 return;
7059 }
7060 if (bystop > bystart
7061 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7062 --bystop;
7063 }
7064
7065 if (*input_line_pointer != '.')
7066 extent = '\0';
7067 else
7068 {
7069 extent = input_line_pointer[1];
7070 input_line_pointer += 2;
7071 }
7072
7073 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 7074 n = push_mri_control (mri_for);
7075
7076 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7077
36759679 7078 /* Move init,var. */
252b5132
RH		 7079 s = buf;
7080 *s++ = 'm';
7081 *s++ = 'o';
7082 *s++ = 'v';
7083 *s++ = 'e';
7084 if (qual != '\0')
3882b010 7085 *s++ = TOLOWER (qual);
252b5132
RH		 7086 *s++ = ' ';
7087 memcpy (s, initstart, initstop - initstart);
7088 s += initstop - initstart;
7089 *s++ = ',';
7090 memcpy (s, varstart, varstop - varstart);
7091 s += varstop - varstart;
7092 *s = '\0';
7093 mri_assemble (buf);
7094
7095 colon (n->top);
7096
36759679 7097 /* cmp end,var. */
252b5132
RH		 7098 s = buf;
7099 *s++ = 'c';
7100 *s++ = 'm';
7101 *s++ = 'p';
7102 if (qual != '\0')
3882b010 7103 *s++ = TOLOWER (qual);
252b5132
RH		 7104 *s++ = ' ';
7105 memcpy (s, endstart, endstop - endstart);
7106 s += endstop - endstart;
7107 *s++ = ',';
7108 memcpy (s, varstart, varstop - varstart);
7109 s += varstop - varstart;
7110 *s = '\0';
7111 mri_assemble (buf);
7112
36759679 7113 /* bcc bottom. */
3882b010 7114 ex[0] = TOLOWER (extent);
252b5132
RH		 7115 ex[1] = '\0';
7116 if (up)
7117 sprintf (buf, "blt%s %s", ex, n->bottom);
7118 else
7119 sprintf (buf, "bgt%s %s", ex, n->bottom);
7120 mri_assemble (buf);
7121
7122 /* Put together the add or sub instruction used by ENDF. */
7123 s = buf;
7124 if (up)
7125 strcpy (s, "add");
7126 else
7127 strcpy (s, "sub");
7128 s += 3;
7129 if (qual != '\0')
3882b010 7130 *s++ = TOLOWER (qual);
252b5132
RH		 7131 *s++ = ' ';
7132 memcpy (s, bystart, bystop - bystart);
7133 s += bystop - bystart;
7134 *s++ = ',';
7135 memcpy (s, varstart, varstop - varstart);
7136 s += varstop - varstart;
7137 *s = '\0';
7138 n->incr = buf;
7139
7140 if (flag_mri)
7141 {
7142 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7143 ++input_line_pointer;
7144 }
7145
7146 demand_empty_rest_of_line ();
7147}
7148
7149/* Handle the MRI ENDF pseudo-op. */
7150
7151static void
31302357 7152s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7153{
7154 if (mri_control_stack == NULL
7155 || mri_control_stack->type != mri_for)
7156 {
7157 as_bad (_("endf without for"));
7158 ignore_rest_of_line ();
7159 return;
7160 }
7161
7162 colon (mri_control_stack->next);
7163
7164 mri_assemble (mri_control_stack->incr);
7165
7166 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7167 mri_assemble (mri_control_stack->incr);
7168
7169 free (mri_control_stack->incr);
7170
7171 colon (mri_control_stack->bottom);
7172
7173 pop_mri_control ();
7174
7175 if (flag_mri)
7176 {
7177 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7178 ++input_line_pointer;
7179 }
7180
7181 demand_empty_rest_of_line ();
7182}
7183
7184/* Handle the MRI REPEAT pseudo-op. */
7185
7186static void
31302357 7187s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7188{
7189 struct mri_control_info *n;
7190
7191 n = push_mri_control (mri_repeat);
7192 colon (n->top);
7193 if (flag_mri)
7194 {
7195 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7196 ++input_line_pointer;
7197 }
7198 demand_empty_rest_of_line ();
7199}
7200
7201/* Handle the MRI UNTIL pseudo-op. */
7202
7203static void
31302357 7204s_mri_until (int qual)
252b5132
RH		 7205{
7206 char *s;
7207
7208 if (mri_control_stack == NULL
7209 || mri_control_stack->type != mri_repeat)
7210 {
7211 as_bad (_("until without repeat"));
7212 ignore_rest_of_line ();
7213 return;
7214 }
7215
7216 colon (mri_control_stack->next);
7217
7218 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7219 ;
7220
7221 parse_mri_control_expression (s, qual, (const char *) NULL,
7222 mri_control_stack->top, '\0');
7223
7224 colon (mri_control_stack->bottom);
7225
7226 input_line_pointer = s;
7227
7228 pop_mri_control ();
7229
7230 if (flag_mri)
7231 {
7232 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7233 ++input_line_pointer;
7234 }
7235
7236 demand_empty_rest_of_line ();
7237}
7238
7239/* Handle the MRI WHILE pseudo-op. */
7240
7241static void
31302357 7242s_mri_while (int qual)
252b5132
RH		 7243{
7244 char *s;
7245
7246 struct mri_control_info *n;
7247
7248 s = input_line_pointer;
e1f44d10
NC		 7249 /* We only accept '*' as introduction of comments if preceded by white space
7250 or at first column of a line (I think this can't actually happen here?)
7251 This is important when assembling:
7252 while d0 <ne> 12(a0,d0*2) do
36759679 7253 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7254 while (! (is_end_of_line[(unsigned char) *s]
7255 || (flag_mri
7256 && *s == '*'
7257 && (s == input_line_pointer
7258 || *(s-1) == ' '
7259 || *(s-1) == '\t'))))
252b5132
RH		 7260 s++;
7261 --s;
7262 while (*s == ' ' || *s == '\t')
7263 --s;
7264 if (s - input_line_pointer > 1
7265 && s[-1] == '.')
7266 s -= 2;
7267 if (s - input_line_pointer < 2
7268 || strncasecmp (s - 1, "DO", 2) != 0)
7269 {
7270 as_bad (_("missing do"));
7271 ignore_rest_of_line ();
7272 return;
7273 }
7274
7275 n = push_mri_control (mri_while);
7276
7277 colon (n->next);
7278
7279 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7280 s[1] == '.' ? s[2] : '\0');
7281
7282 input_line_pointer = s + 1;
7283 if (*input_line_pointer == '.')
7284 input_line_pointer += 2;
7285
7286 if (flag_mri)
7287 {
7288 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7289 ++input_line_pointer;
7290 }
7291
7292 demand_empty_rest_of_line ();
7293}
7294
7295/* Handle the MRI ENDW pseudo-op. */
7296
7297static void
31302357 7298s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7299{
7300 char *buf;
7301
7302 if (mri_control_stack == NULL
7303 || mri_control_stack->type != mri_while)
7304 {
7305 as_bad (_("endw without while"));
7306 ignore_rest_of_line ();
7307 return;
7308 }
7309
7310 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7311 sprintf (buf, "bra %s", mri_control_stack->next);
7312 mri_assemble (buf);
7313 free (buf);
7314
7315 colon (mri_control_stack->bottom);
7316
7317 pop_mri_control ();
7318
7319 if (flag_mri)
7320 {
7321 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7322 ++input_line_pointer;
7323 }
7324
7325 demand_empty_rest_of_line ();
7326}
7327\f
266abb8f
NS		 7328/* Parse a .cpu directive. */
7329
7330static void
7331s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7332{
7333 char saved_char;
7334 char *name;
7335
7336 if (initialized)
7337 {
7338 as_bad (_("already assembled instructions"));
7339 ignore_rest_of_line ();
7340 return;
7341 }
7342
7343 name = input_line_pointer;
7344 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7345 input_line_pointer++;
7346 saved_char = *input_line_pointer;
7347 *input_line_pointer = 0;
7348
7349 m68k_set_cpu (name, 1, 0);
7350
7351 *input_line_pointer = saved_char;
7352 demand_empty_rest_of_line ();
7353 return;
7354}
7355
7356/* Parse a .arch directive. */
7357
7358static void
7359s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7360{
7361 char saved_char;
7362 char *name;
7363
7364 if (initialized)
7365 {
7366 as_bad (_("already assembled instructions"));
7367 ignore_rest_of_line ();
7368 return;
7369 }
7370
7371 name = input_line_pointer;
7372 while (*input_line_pointer && *input_line_pointer != ','
7373 && !ISSPACE (*input_line_pointer))
7374 input_line_pointer++;
7375 saved_char = *input_line_pointer;
7376 *input_line_pointer = 0;
7377
7378 if (m68k_set_arch (name, 1, 0))
7379 {
7380 /* Scan extensions. */
7381 do
7382 {
7383 *input_line_pointer++ = saved_char;
7384 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7385 break;
7386 name = input_line_pointer;
7387 while (*input_line_pointer && *input_line_pointer != ','
7388 && !ISSPACE (*input_line_pointer))
7389 input_line_pointer++;
7390 saved_char = *input_line_pointer;
7391 *input_line_pointer = 0;
7392 }
7393 while (m68k_set_extension (name, 1, 0));
7394 }
7395
7396 *input_line_pointer = saved_char;
7397 demand_empty_rest_of_line ();
7398 return;
7399}
7400\f
7401/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7402 if none is found, the caller is responsible for emitting an error
7403 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7404 cpu name, if it begins with a '6' (possibly skipping an intervening
7405 'c'. We also allow a 'c' in the same place. if NEGATED is
7406 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7407 the option is indeed negated. */
7408
7409static const struct m68k_cpu *
7410m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7411 int allow_m, int *negated)
7412{
7413 /* allow negated value? */
7414 if (negated)
7415 {
7416 *negated = 0;
7417
7418 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7419 {
7420 arg += 3;
7421 *negated = 1;
7422 }
7423 }
7424
7425 /* Remove 'm' or 'mc' prefix from 68k variants. */
7426 if (allow_m)
7427 {
7428 if (arg[0] == 'm')
7429 {
7430 if (arg[1] == '6')
7431 arg += 1;
7432 else if (arg[1] == 'c' && arg[2] == '6')
7433 arg += 2;
7434 }
7435 }
7436 else if (arg[0] == 'c' && arg[1] == '6')
7437 arg += 1;
7438
7439 for (; table->name; table++)
7440 if (!strcmp (arg, table->name))
2da12c60
NS		 7441 {
7442 if (table->alias < -1 || table->alias > 1)
7443 as_bad (_("`%s' is deprecated, use `%s'"),
7444 table->name, table[table->alias < 0 ? 1 : -1].name);
7445 return table;
7446 }
266abb8f
NS		 7447 return 0;
7448}
7449
bfbba8e4 7450/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7451
7452static int
7453m68k_set_cpu (char const *name, int allow_m, int silent)
7454{
7455 const struct m68k_cpu *cpu;
7456
7457 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7458
7459 if (!cpu)
7460 {
7461 if (!silent)
7462 as_bad (_("cpu `%s' unrecognized"), name);
7463 return 0;
7464 }
266abb8f
NS		 7465 selected_cpu = cpu;
7466 return 1;
7467}
7468
bfbba8e4 7469/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7470
7471static int
7472m68k_set_arch (char const *name, int allow_m, int silent)
7473{
7474 const struct m68k_cpu *arch;
7475
7476 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7477
7478 if (!arch)
7479 {
7480 if (!silent)
7481 as_bad (_("architecture `%s' unrecognized"), name);
7482 return 0;
7483 }
266abb8f
NS		 7484 selected_arch = arch;
7485 return 1;
7486}
7487
7488/* Set the architecture extension, issuing errors if it is
7489 unrecognized, or invalid */
7490
7491static int
7492m68k_set_extension (char const *name, int allow_m, int silent)
7493{
7494 int negated;
7495 const struct m68k_cpu *ext;
7496
7497 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7498
7499 if (!ext)
7500 {
7501 if (!silent)
7502 as_bad (_("extension `%s' unrecognized"), name);
7503 return 0;
7504 }
7505
7506 if (negated)
87298967
NS		 7507 not_current_architecture |= (ext->control_regs
7508 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7509 else
7510 current_architecture |= ext->arch;
7511 return 1;
7512}
7513
31302357
AS		 7514/* md_parse_option
7515 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7516 */
252b5132
RH		 7517
7518#ifdef OBJ_ELF
5a38dc70 7519const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7520#else
5a38dc70 7521const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7522#endif
7523
7524struct option md_longopts[] = {
7525#define OPTION_PIC (OPTION_MD_BASE)
7526 {"pic", no_argument, NULL, OPTION_PIC},
7527#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7528 {"register-prefix-optional", no_argument, NULL,
7529 OPTION_REGISTER_PREFIX_OPTIONAL},
7530#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7531 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7532#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7533 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7534#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7535 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7536#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7537 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7538#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7539 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7540#define OPTION_PCREL (OPTION_MD_BASE + 7)
7541 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7542 {NULL, no_argument, NULL, 0}
7543};
bc805888 7544size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7545
7546int
31302357 7547md_parse_option (int c, char *arg)
252b5132
RH		 7548{
7549 switch (c)
7550 {
7551 case 'l': /* -l means keep external to 2 bit offset
36759679 7552 rather than 16 bit one. */
252b5132
RH		 7553 flag_short_refs = 1;
7554 break;
7555
7556 case 'S': /* -S means that jbsr's always turn into
7557 jsr's. */
7558 flag_long_jumps = 1;
7559 break;
7560
28e7409f
NC		 7561 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7562 branches into absolute jumps. */
7563 flag_keep_pcrel = 1;
7564 break;
7565
252b5132
RH		 7566 case OPTION_PIC:
7567 case 'k':
7568 flag_want_pic = 1;
36759679 7569 break; /* -pic, Position Independent Code. */
252b5132
RH		 7570
7571 case OPTION_REGISTER_PREFIX_OPTIONAL:
7572 flag_reg_prefix_optional = 1;
7573 reg_prefix_optional_seen = 1;
7574 break;
7575
7576 /* -V: SVR4 argument to print version ID. */
7577 case 'V':
7578 print_version_id ();
7579 break;
7580
7581 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7582 should be emitted or not. FIXME: Not implemented. */
7583 case 'Q':
7584 break;
7585
7586 case OPTION_BITWISE_OR:
7587 {
7588 char *n, *t;
7589 const char *s;
7590
7591 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7592 t = n;
7593 for (s = m68k_comment_chars; *s != '\0'; s++)
7594 if (*s != '|')
7595 *t++ = *s;
7596 *t = '\0';
7597 m68k_comment_chars = n;
7598 }
7599 break;
7600
7601 case OPTION_BASE_SIZE_DEFAULT_16:
7602 m68k_index_width_default = SIZE_WORD;
7603 break;
7604
7605 case OPTION_BASE_SIZE_DEFAULT_32:
7606 m68k_index_width_default = SIZE_LONG;
7607 break;
7608
7609 case OPTION_DISP_SIZE_DEFAULT_16:
7610 m68k_rel32 = 0;
7611 m68k_rel32_from_cmdline = 1;
7612 break;
7613
7614 case OPTION_DISP_SIZE_DEFAULT_32:
7615 m68k_rel32 = 1;
7616 m68k_rel32_from_cmdline = 1;
7617 break;
7618
266abb8f
NS		 7619 case 'A':
7620#if WARN_DEPRECATED
7621 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7622 arg, arg));
7623#endif
7624 /* Intentional fall-through. */
7625 case 'm':
7626 if (!strncmp (arg, "arch=", 5))
7627 m68k_set_arch (arg + 5, 1, 0);
7628 else if (!strncmp (arg, "cpu=", 4))
7629 m68k_set_cpu (arg + 4, 1, 0);
7630 else if (m68k_set_extension (arg, 0, 1))
7631 ;
0b2e31dc
NS		 7632 else if (m68k_set_arch (arg, 0, 1))
7633 ;
266abb8f
NS		 7634 else if (m68k_set_cpu (arg, 0, 1))
7635 ;
7636 else
7637 return 0;
7638 break;
7639
252b5132
RH		 7640 default:
7641 return 0;
7642 }
7643
7644 return 1;
7645}
7646
266abb8f
NS		 7647/* Setup tables from the selected arch and/or cpu */
7648
7649static void
7650m68k_init_arch (void)
7651{
266abb8f
NS		 7652 if (not_current_architecture & current_architecture)
7653 {
7654 as_bad (_("architecture features both enabled and disabled"));
7655 not_current_architecture &= ~current_architecture;
7656 }
7657 if (selected_arch)
2da12c60
NS		 7658 {
7659 current_architecture |= selected_arch->arch;
7660 control_regs = selected_arch->control_regs;
7661 }
0b2e31dc
NS		 7662 else
7663 current_architecture |= selected_cpu->arch;
0b2e31dc 7664
2da12c60
NS		 7665 current_architecture &= ~not_current_architecture;
7666
377260ba
NS		 7667 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7668 {
7669 /* Determine which float is really meant. */
7670 if (current_architecture & (m68k_mask & ~m68881))
7671 current_architecture ^= cfloat;
7672 else
7673 current_architecture ^= m68881;
7674 }
7675
0b2e31dc 7676 if (selected_cpu)
266abb8f 7677 {
2da12c60 7678 control_regs = selected_cpu->control_regs;
0b2e31dc 7679 if (current_architecture & ~selected_cpu->arch)
266abb8f 7680 {
0b2e31dc
NS		 7681 as_bad (_("selected processor does not have all features of selected architecture"));
7682 current_architecture
7683 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7684 }
7685 }
266abb8f 7686
266abb8f
NS		 7687 if ((current_architecture & m68k_mask)
7688 && (current_architecture & ~m68k_mask))
7689 {
7690 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7691 if (current_architecture & m68k_mask)
266abb8f
NS		 7692 current_architecture &= m68k_mask;
7693 else
7694 current_architecture &= ~m68k_mask;
7695 }
7696
7697 /* Permit m68881 specification with all cpus; those that can't work
7698 with a coprocessor could be doing emulation. */
7699 if (current_architecture & m68851)
7700 {
7701 if (current_architecture & m68040)
7702 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7703 }
7704 /* What other incompatibilities could we check for? */
7705
266abb8f
NS		 7706 if (cpu_of_arch (current_architecture) < m68020
7707 || arch_coldfire_p (current_architecture))
7708 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7709
7710 initialized = 1;
7711}
7712
252b5132 7713void
31302357 7714md_show_usage (FILE *stream)
252b5132 7715{
76f57f3a 7716 const char *default_cpu = TARGET_CPU;
f1f5ef86 7717 int i;
76f57f3a 7718
8a104df9 7719 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7720 if (*default_cpu == 'm')
7721 default_cpu++;
266abb8f 7722 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7723 {
266abb8f 7724 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7725 {
2da12c60
NS		 7726 while (m68k_cpus[i].alias > 0)
7727 i--;
7728 while (m68k_cpus[i].alias < 0)
7729 i++;
7730 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7731 }
7732 }
7733
bc805888 7734 fprintf (stream, _("\
266abb8f
NS		 7735-march=<arch> set architecture\n\
7736-mcpu=<cpu> set cpu [default %s]\n\
7737"), default_cpu);
7738 for (i = 0; m68k_extensions[i].name; i++)
7739 fprintf (stream, _("\
0b2e31dc
NS		 7740-m[no-]%-16s enable/disable%s architecture extension\n\
7741"), m68k_extensions[i].name,
7742 m68k_extensions[i].alias > 0 ? " ColdFire"
7743 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7744
bc805888 7745 fprintf (stream, _("\
266abb8f 7746-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7747-pic, -k generate position independent code\n\
7748-S turn jbsr into jsr\n\
28e7409f 7749--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7750--register-prefix-optional\n\
7751 recognize register names without prefix character\n\
266abb8f 7752--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7753--base-size-default-16 base reg without size is 16 bits\n\
7754--base-size-default-32 base reg without size is 32 bits (default)\n\
7755--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7756--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7757"));
7758
7759 fprintf (stream, _("Architecture variants are: "));
7760 for (i = 0; m68k_archs[i].name; i++)
7761 {
7762 if (i)
7763 fprintf (stream, " | ");
87298967 7764 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7765 }
7766 fprintf (stream, "\n");
7767
7768 fprintf (stream, _("Processor variants are: "));
7769 for (i = 0; m68k_cpus[i].name; i++)
7770 {
7771 if (i)
7772 fprintf (stream, " | ");
87298967 7773 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7774 }
7775 fprintf (stream, _("\n"));
252b5132
RH		 7776}
7777\f
7778#ifdef TEST2
7779
7780/* TEST2: Test md_assemble() */
36759679
NC		 7781/* Warning, this routine probably doesn't work anymore. */
7782int
31302357 7783main (void)
252b5132
RH		 7784{
7785 struct m68k_it the_ins;
7786 char buf[120];
7787 char *cp;
7788 int n;
7789
7790 m68k_ip_begin ();
7791 for (;;)
7792 {
7793 if (!gets (buf) || !*buf)
7794 break;
7795 if (buf[0] == '|' || buf[1] == '.')
7796 continue;
7797 for (cp = buf; *cp; cp++)
7798 if (*cp == '\t')
7799 *cp = ' ';
7800 if (is_label (buf))
7801 continue;
7802 memset (&the_ins, '\0', sizeof (the_ins));
7803 m68k_ip (&the_ins, buf);
7804 if (the_ins.error)
7805 {
7806 printf (_("Error %s in %s\n"), the_ins.error, buf);
7807 }
7808 else
7809 {
7810 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7811 for (n = 0; n < the_ins.numo; n++)
7812 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7813 printf (" ");
7814 print_the_insn (&the_ins.opcode[0], stdout);
7815 (void) putchar ('\n');
7816 }
7817 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7818 {
7819 if (the_ins.operands[n].error)
7820 {
7821 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7822 continue;
7823 }
31302357
AS		 7824 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7825 the_ins.operands[n].reg);
252b5132 7826 if (the_ins.operands[n].b_const)
31302357
AS		 7827 printf ("Constant: '%.*s', ",
7828 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7829 the_ins.operands[n].b_const);
7830 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7831 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7832 if (the_ins.operands[n].b_iadd)
31302357
AS		 7833 printf ("Iadd: '%.*s',",
7834 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7835 the_ins.operands[n].b_iadd);
7836 putchar ('\n');
252b5132
RH		 7837 }
7838 }
7839 m68k_ip_end ();
7840 return 0;
7841}
7842
31302357
AS		 7843int
7844is_label (char *str)
252b5132
RH		 7845{
7846 while (*str == ' ')
7847 str++;
7848 while (*str && *str != ' ')
7849 str++;
7850 if (str[-1] == ':' || str[1] == '=')
7851 return 1;
7852 return 0;
7853}
7854
7855#endif
7856
7857/* Possible states for relaxation:
7858
7859 0 0 branch offset byte (bra, etc)
7860 0 1 word
7861 0 2 long
7862
7863 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7864 1 1 word
7865 1 2 long
7866
7867 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7868 2 1 word-long
7869 2 2 long-word
7870 2 3 long-long
7871
7872 */
7873
7874/* We have no need to default values of symbols. */
7875
252b5132 7876symbolS *
31302357 7877md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7878{
7879 return 0;
7880}
7881
7882/* Round up a section size to the appropriate boundary. */
7883valueT
31302357 7884md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7885{
7886#ifdef OBJ_AOUT
252b5132
RH		 7887 /* For a.out, force the section size to be aligned. If we don't do
7888 this, BFD will align it for us, but it will not write out the
7889 final bytes of the section. This may be a bug in BFD, but it is
7890 easier to fix it here since that is how the other a.out targets
7891 work. */
7892 int align;
7893
7894 align = bfd_get_section_alignment (stdoutput, segment);
7895 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7896#endif
7897
7898 return size;
7899}
7900
7901/* Exactly what point is a PC-relative offset relative TO?
7902 On the 68k, it is relative to the address of the first extension
7903 word. The difference between the addresses of the offset and the
92774660 7904 first extension word is stored in fx_pcrel_adjust. */
252b5132 7905long
31302357 7906md_pcrel_from (fixS *fixP)
252b5132
RH		 7907{
7908 int adjust;
7909
552c607f 7910 adjust = fixP->fx_pcrel_adjust;
252b5132
RH		 7911 if (adjust == 64)
7912 adjust = -1;
7913 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7914}
7915
0d96863f 7916#ifdef OBJ_ELF
8a104df9 7917void
31302357 7918m68k_elf_final_processing (void)
0d96863f 7919{
266abb8f
NS		 7920 unsigned flags = 0;
7921
238d258f 7922 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7923 flags |= EF_M68K_CFV4E;
7924 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7925 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7926 flags |= EF_M68K_CPU32;
7927 else if (cpu_of_arch (current_architecture) & fido_a)
7928 flags |= EF_M68K_FIDO;
8a104df9
KH		 7929 else if ((cpu_of_arch (current_architecture) & m68000up)
7930 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7931 flags |= EF_M68K_M68000;
7932
7933 if (current_architecture & mcfisa_a)
7934 {
0b2e31dc
NS		 7935 static const unsigned isa_features[][2] =
7936 {
9a2e615a 7937 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7938 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7939 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7940 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7941 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7942 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7943 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7944 {0,0},
7945 };
7946 static const unsigned mac_features[][2] =
7947 {
c694fd50
KH		 7948 {EF_M68K_CF_MAC, mcfmac},
7949 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7950 {0,0},
7951 };
7952 unsigned ix;
7953 unsigned pattern;
266abb8f 7954
0b2e31dc 7955 pattern = (current_architecture
9a2e615a 7956 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7957 for (ix = 0; isa_features[ix][1]; ix++)
7958 {
7959 if (pattern == isa_features[ix][1])
7960 {
7961 flags |= isa_features[ix][0];
7962 break;
7963 }
7964 }
7965 if (!isa_features[ix][1])
7966 {
7967 cf_bad:
7968 as_warn (_("Not a defined coldfire architecture"));
7969 }
7970 else
7971 {
7972 if (current_architecture & cfloat)
c694fd50 7973 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7974
0b2e31dc
NS		 7975 pattern = current_architecture & (mcfmac|mcfemac);
7976 if (pattern)
7977 {
7978 for (ix = 0; mac_features[ix][1]; ix++)
7979 {
7980 if (pattern == mac_features[ix][1])
7981 {
7982 flags |= mac_features[ix][0];
7983 break;
7984 }
7985 }
7986 if (!mac_features[ix][1])
7987 goto cf_bad;
7988 }
7989 }
266abb8f
NS		 7990 }
7991 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7992}
cf869cce
NC		 7993
7994/* Parse @TLSLDO and return the desired relocation. */
7995static bfd_reloc_code_real_type
7996m68k_elf_suffix (char **str_p, expressionS *exp_p)
7997{
7998 char ident[20];
7999 char *str = *str_p;
8000 char *str2;
8001 int ch;
8002 int len;
8003
8004 if (*str++ != '@')
8005 return BFD_RELOC_UNUSED;
8006
8007 for (ch = *str, str2 = ident;
8008 (str2 < ident + sizeof (ident) - 1
8009 && (ISALNUM (ch) || ch == '@'));
8010 ch = *++str)
8011 {
8012 *str2++ = ch;
8013 }
8014
8015 *str2 = '\0';
8016 len = str2 - ident;
8017
8018 if (strncmp (ident, "TLSLDO", 6) == 0
8019 && len == 6)
8020 {
8021 /* Now check for identifier@suffix+constant. */
8022 if (*str == '-' || *str == '+')
8023 {
8024 char *orig_line = input_line_pointer;
8025 expressionS new_exp;
8026
8027 input_line_pointer = str;
8028 expression (&new_exp);
8029 if (new_exp.X_op == O_constant)
8030 {
8031 exp_p->X_add_number += new_exp.X_add_number;
8032 str = input_line_pointer;
8033 }
8034
8035 if (&input_line_pointer != str_p)
8036 input_line_pointer = orig_line;
8037 }
8038 *str_p = str;
8039
8040 return BFD_RELOC_68K_TLS_LDO32;
8041 }
8042
8043 return BFD_RELOC_UNUSED;
8044}
8045
8046/* Handles .long <tls_symbol>+0x8000 debug info.
8047 Clobbers input_line_pointer, checks end-of-line.
8048 Adapted from tc-ppc.c:ppc_elf_cons. */
8049static void
8050m68k_elf_cons (int nbytes /* 4=.long */)
8051{
8052 if (is_it_end_of_statement ())
8053 {
8054 demand_empty_rest_of_line ();
8055 return;
8056 }
8057
8058 do
8059 {
8060 expressionS exp;
8061 bfd_reloc_code_real_type reloc;
8062
8063 expression (&exp);
8064 if (exp.X_op == O_symbol
8065 && *input_line_pointer == '@'
8066 && (reloc = m68k_elf_suffix (&input_line_pointer,
8067 &exp)) != BFD_RELOC_UNUSED)
8068 {
8069 reloc_howto_type *reloc_howto;
8070 int size;
8071
8072 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8073 size = bfd_get_reloc_size (reloc_howto);
8074
8075 if (size > nbytes)
8076 {
8077 as_bad (_("%s relocations do not fit in %d bytes\n"),
8078 reloc_howto->name, nbytes);
8079 }
8080 else
8081 {
8082 char *p;
8083 int offset;
8084
8085 p = frag_more (nbytes);
8086 offset = 0;
8087 if (target_big_endian)
8088 offset = nbytes - size;
8089 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8090 &exp, 0, reloc);
8091 }
8092 }
8093 else
8094 emit_expr (&exp, (unsigned int) nbytes);
8095 }
8096 while (*input_line_pointer++ == ',');
8097
8098 /* Put terminator back into stream. */
8099 input_line_pointer--;
8100 demand_empty_rest_of_line ();
8101}
0d96863f 8102#endif
c04898f8
AS		 8103
8104int
1df69f4f 8105tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 8106{
8107 unsigned int regnum;
8108 static const char *const regnames[] =
8109 {
8110 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8111 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8112 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8113 "pc"
8114 };
8115
8116 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8117 if (strcmp (regname, regnames[regnum]) == 0)
8118 return regnum;
8119
8120 return -1;
8121}
8122
8123void
8124tc_m68k_frame_initial_instructions (void)
8125{
8126 static int sp_regno = -1;
8127
8128 if (sp_regno < 0)
8129 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8130
8131 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8132 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8133}
909c7f9c
NC		 8134
8135/* Check and emit error if broken-word handling has failed to fix up a
8136 case-table. This is called from write.c, after doing everything it
8137 knows about how to handle broken words. */
8138
8139void
8140tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
8141{
8142 if (new_offset > 32767 || new_offset < -32768)
8143 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
8144 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
8145 (long) new_offset);
8146}
8147
GDB Binutils - Deliverables
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