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* v850-opc.c: Close unterminated comment.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a1c7c0f3 1/* tc-m68k.c -- Assemble for the m68k family
9e64486e 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
6d27d3a2 3
a39116f1 4 This file is part of GAS, the GNU Assembler.
6d27d3a2 5
a39116f1
RP		 6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
6d27d3a2 10
a39116f1
RP		 11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
6d27d3a2 15
a39116f1 16 You should have received a copy of the GNU General Public License
a1c7c0f3
ILT		 17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
fecd2382
RP		 20
21#include <ctype.h>
fecd2382 22#include "as.h"
fecd2382 23#include "obstack.h"
b4ec75e0 24#include "subsegs.h"
fecd2382 25
e0982afe 26#include "opcode/m68k.h"
a1c7c0f3 27#include "m68k-parse.h"
3ad9ec6a 28
8d20a0a8
C		 29/* This string holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful. The macro
31 tc_comment_chars points to this. We use this, rather than the
32 usual comment_chars, so that the --bitwise-or option will work. */
65feb78d 33#if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
8d20a0a8 34const char *m68k_comment_chars = "|#";
5f8cb05e 35#else
8d20a0a8 36const char *m68k_comment_chars = "|";
5f8cb05e 37#endif
fecd2382
RP		 38
39/* This array holds the chars that only start a comment at the beginning of
40 a line. If the line seems to have the form '# 123 filename'
41 .line and .file directives will appear in the pre-processed output */
42/* Note that input_file.c hand checks for '#' at the beginning of the
43 first line of the input file. This is because the compiler outputs
44 #NO_APP at the beginning of its output. */
45/* Also note that comments like this one will always work. */
326b087c 46const char line_comment_chars[] = "#";
fecd2382 47
326b087c 48const char line_separator_chars[] = "";
587c4264 49
fecd2382 50/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 51CONST char EXP_CHARS[] = "eE";
fecd2382 52
49864cfa
KR		 53/* Chars that mean this number is a floating point constant, as
54 in "0f12.456" or "0d1.2345e12". */
fecd2382 55
49864cfa 56CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 57
58/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
59 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 60 but nothing is ideal around here. */
fecd2382 61
49864cfa 62const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 63
b80d39a0 64/* Are we trying to generate PIC code? If so, absolute references
dff60b7d 65 ought to be made into linkage table references or pc-relative
a043f579
ILT		 66 references. Not implemented. For ELF there are other means
67 to denote pic relocations. */
b80d39a0
KR		 68int flag_want_pic;
69
9ad5755f
KR		 70static int flag_short_refs; /* -l option */
71static int flag_long_jumps; /* -S option */
72
82489ea0
KR		 73#ifdef REGISTER_PREFIX_OPTIONAL
74int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
75#else
76int flag_reg_prefix_optional;
77#endif
78
20710f1c
ILT		 79/* Whether --register-prefix-optional was used on the command line. */
80static int reg_prefix_optional_seen;
81
27a53b88
ILT		 82/* The floating point coprocessor to use by default. */
83static enum m68k_register m68k_float_copnum = COP1;
84
6700d36e
ILT		 85/* If this is non-zero, then references to number(%pc) will be taken
86 to refer to number, rather than to %pc + number. */
87static int m68k_abspcadd;
88
89/* If this is non-zero, then the quick forms of the move, add, and sub
90 instructions are used when possible. */
91static int m68k_quick = 1;
92
93/* If this is non-zero, then if the size is not specified for a base
94 or outer displacement, the assembler assumes that the size should
95 be 32 bits. */
96static int m68k_rel32 = 1;
97
fecd2382
RP		 98/* Its an arbitrary name: This means I don't approve of it */
99/* See flames below */
100static struct obstack robyn;
101
102#define TAB(x,y) (((x)<<2)+(y))
103#define TABTYPE(xy) ((xy) >> 2)
104#define BYTE 0
105#define SHORT 1
106#define LONG 2
107#define SZ_UNDEF 3
3ad9ec6a 108#undef BRANCH
04ef74bb 109/* Case `g' except when BCC68000 is applicable. */
3ad9ec6a 110#define ABRANCH 1
04ef74bb 111/* Coprocessor branches. */
fecd2382 112#define FBRANCH 2
04ef74bb
KR		 113/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
114 supported on all cpus. Widens to 32-bit absolute. */
fecd2382 115#define PCREL 3
04ef74bb
KR		 116/* For inserting an extra jmp instruction with long offset on 68000,
117 for expanding conditional branches. (Not bsr or bra.) Since the
118 68000 doesn't support 32-bit displacements for conditional
119 branches, we fake it by reversing the condition and branching
120 around a jmp with an absolute long operand. */
fecd2382 121#define BCC68000 4
04ef74bb
KR		 122/* For the DBcc "instructions". If the displacement requires 32 bits,
123 the branch-around-a-jump game is played here too. */
fecd2382 124#define DBCC 5
04ef74bb 125/* Not currently used? */
fecd2382 126#define PCLEA 6
04ef74bb
KR		 127/* Mode AINDX (apc-relative) using PC, with variable target, might fit
128 in 16 or 8 bits. */
129#define PCINDEX 7
fecd2382 130
bcb8dff8
KR		 131struct m68k_incant
132 {
a1c7c0f3 133 const char *m_operands;
bcb8dff8
KR		 134 unsigned long m_opcode;
135 short m_opnum;
136 short m_codenum;
137 int m_arch;
138 struct m68k_incant *m_next;
139 };
140
141#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
142#define gettwo(x) (((x)->m_opcode)&0xffff)
143
a1c7c0f3
ILT		 144static const enum m68k_register m68000_control_regs[] = { 0 };
145static const enum m68k_register m68010_control_regs[] = {
82489ea0
KR		 146 SFC, DFC, USP, VBR,
147 0
148};
a1c7c0f3 149static const enum m68k_register m68020_control_regs[] = {
82489ea0
KR		 150 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
151 0
152};
a1c7c0f3 153static const enum m68k_register m68040_control_regs[] = {
82489ea0
KR		 154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
155 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
156 0
157};
a1c7c0f3 158static const enum m68k_register m68060_control_regs[] = {
82489ea0
KR		 159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
160 USP, VBR, URP, SRP, PCR,
161 0
162};
8d20a0a8
C		 163static const enum m68k_register mcf5200_control_regs[] = {
164 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
165 RAMBAR0, RAMBAR1, MBAR,
166 0
167};
b79de3a1 168#define cpu32_control_regs m68010_control_regs
82489ea0 169
a1c7c0f3 170static const enum m68k_register *control_regs;
fecd2382
RP		 171
172/* internal form of a 68020 instruction */
355afbcd 173struct m68k_it
a1c7c0f3
ILT		 174{
175 const char *error;
176 const char *args; /* list of opcode info */
177 int numargs;
355afbcd 178
a1c7c0f3
ILT		 179 int numo; /* Number of shorts in opcode */
180 short opcode[11];
355afbcd 181
a1c7c0f3 182 struct m68k_op operands[6];
355afbcd 183
a1c7c0f3
ILT		 184 int nexp; /* number of exprs in use */
185 struct m68k_exp exprs[4];
355afbcd 186
a1c7c0f3
ILT		 187 int nfrag; /* Number of frags we have to produce */
188 struct
189 {
190 int fragoff; /* Where in the current opcode the frag ends */
191 symbolS *fadd;
192 long foff;
193 int fragty;
194 }
195 fragb[4];
355afbcd 196
a1c7c0f3
ILT		 197 int nrel; /* Num of reloc strucs in use */
198 struct
199 {
200 int n;
201 expressionS exp;
202 char wid;
203 char pcrel;
204 /* In a pc relative address the difference between the address
205 of the offset and the address that the offset is relative
206 to. This depends on the addressing mode. Basically this
207 is the value to put in the offset field to address the
208 first byte of the offset, without regarding the special
209 significance of some values (in the branch instruction, for
210 example). */
211 int pcrel_fix;
a043f579
ILT		 212#ifdef OBJ_ELF
213 /* Whether this expression needs special pic relocation, and if
214 so, which. */
215 enum pic_relocation pic_reloc;
216#endif
a1c7c0f3
ILT		 217 }
218 reloc[5]; /* Five is enough??? */
219};
fecd2382 220
8d20a0a8 221#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
865a2edf
MT		 222#define float_of_arch(x) ((x) & mfloat)
223#define mmu_of_arch(x) ((x) & mmmu)
224
355afbcd 225static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 226
a1c7c0f3
ILT		 227#define op(ex) ((ex)->exp.X_op)
228#define adds(ex) ((ex)->exp.X_add_symbol)
229#define subs(ex) ((ex)->exp.X_op_symbol)
230#define offs(ex) ((ex)->exp.X_add_number)
49864cfa 231
7c15cbe8 232/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 233
234#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
235
236/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 237static void
238insop (w, opcode)
239 int w;
240 struct m68k_incant *opcode;
241{
242 int z;
243 for(z=the_ins.numo;z>opcode->m_codenum;--z)
244 the_ins.opcode[z]=the_ins.opcode[z-1];
245 for(z=0;z<the_ins.nrel;z++)
246 the_ins.reloc[z].n+=2;
5f8cb05e
ILT		 247 for (z = 0; z < the_ins.nfrag; z++)
248 the_ins.fragb[z].fragoff++;
bcb8dff8
KR		 249 the_ins.opcode[opcode->m_codenum]=w;
250 the_ins.numo++;
251}
fecd2382 252
1404ef23
KR		 253/* The numo+1 kludge is so we can hit the low order byte of the prev word.
254 Blecch. */
49864cfa 255static void
5f8cb05e 256add_fix (width, exp, pc_rel, pc_fix)
49864cfa
KR		 257 char width;
258 struct m68k_exp *exp;
259 int pc_rel;
5f8cb05e 260 int pc_fix;
49864cfa
KR		 261{
262 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
263 ? (the_ins.numo*2-1)
264 : (((width)=='b')
5f8cb05e 265 ? (the_ins.numo*2+1)
49864cfa 266 : (the_ins.numo*2)));
a1c7c0f3 267 the_ins.reloc[the_ins.nrel].exp = exp->exp;
49864cfa 268 the_ins.reloc[the_ins.nrel].wid = width;
5f8cb05e 269 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
a043f579
ILT		 270#ifdef OBJ_ELF
271 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
272#endif
49864cfa 273 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 274}
275
5f8cb05e
ILT		 276/* Cause an extra frag to be generated here, inserting up to 10 bytes
277 (that value is chosen in the frag_var call in md_assemble). TYPE
278 is the subtype of the frag to be generated; its primary type is
279 rs_machine_dependent.
280
281 The TYPE parameter is also used by md_convert_frag_1 and
282 md_estimate_size_before_relax. The appropriate type of fixup will
283 be emitted by md_convert_frag_1.
284
285 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
49864cfa
KR		 286static void
287add_frag(add,off,type)
288 symbolS *add;
289 long off;
290 int type;
291{
292 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
293 the_ins.fragb[the_ins.nfrag].fadd=add;
294 the_ins.fragb[the_ins.nfrag].foff=off;
295 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 296}
fecd2382 297
a1c7c0f3
ILT		 298#define isvar(ex) \
299 (op (ex) != O_constant && op (ex) != O_big)
fecd2382 300
49864cfa
KR		 301static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
302static int get_num PARAMS ((struct m68k_exp *exp, int ok));
49864cfa
KR		 303static int reverse_16_bits PARAMS ((int in));
304static int reverse_8_bits PARAMS ((int in));
49864cfa
KR		 305static void install_gen_operand PARAMS ((int mode, int val));
306static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 307static void s_bss PARAMS ((int));
308static void s_data1 PARAMS ((int));
309static void s_data2 PARAMS ((int));
310static void s_even PARAMS ((int));
311static void s_proc PARAMS ((int));
e9bb39b4
ILT		 312static void mri_chip PARAMS ((void));
313static void s_chip PARAMS ((int));
27a53b88 314static void s_fopt PARAMS ((int));
6700d36e
ILT		 315static void s_opt PARAMS ((int));
316static void s_reg PARAMS ((int));
e14994d9
ILT		 317static void s_restore PARAMS ((int));
318static void s_save PARAMS ((int));
b4ec75e0
ILT		 319static void s_mri_if PARAMS ((int));
320static void s_mri_else PARAMS ((int));
321static void s_mri_endi PARAMS ((int));
322static void s_mri_break PARAMS ((int));
323static void s_mri_next PARAMS ((int));
324static void s_mri_for PARAMS ((int));
325static void s_mri_endf PARAMS ((int));
326static void s_mri_repeat PARAMS ((int));
327static void s_mri_until PARAMS ((int));
328static void s_mri_while PARAMS ((int));
329static void s_mri_endw PARAMS ((int));
49864cfa
KR		 330
331static int current_architecture;
7c15cbe8 332
b79de3a1
KR		 333struct m68k_cpu {
334 unsigned long arch;
335 const char *name;
9e64486e 336 int alias;
b79de3a1
KR		 337};
338
339static const struct m68k_cpu archs[] = {
9e64486e
ILT		 340 { m68000, "68000", 0 },
341 { m68010, "68010", 0 },
342 { m68020, "68020", 0 },
343 { m68030, "68030", 0 },
344 { m68040, "68040", 0 },
345 { m68060, "68060", 0 },
346 { cpu32, "cpu32", 0 },
347 { m68881, "68881", 0 },
348 { m68851, "68851", 0 },
8d20a0a8 349 { mcf5200, "5200", 0 },
b79de3a1
KR		 350 /* Aliases (effectively, so far as gas is concerned) for the above
351 cpus. */
9e64486e
ILT		 352 { m68020, "68k", 1 },
353 { m68000, "68302", 1 },
354 { m68000, "68008", 1 },
355 { m68000, "68ec000", 1 },
356 { m68000, "68hc000", 1 },
357 { m68000, "68hc001", 1 },
358 { m68020, "68ec020", 1 },
359 { m68030, "68ec030", 1 },
360 { m68040, "68ec040", 1 },
8d20a0a8 361 { m68060, "68ec060", 1 },
9e64486e
ILT		 362 { cpu32, "68330", 1 },
363 { cpu32, "68331", 1 },
364 { cpu32, "68332", 1 },
365 { cpu32, "68333", 1 },
366 { cpu32, "68340", 1 },
367 { cpu32, "68360", 1 },
368 { m68881, "68882", 1 },
b79de3a1
KR		 369};
370
371static const int n_archs = sizeof (archs) / sizeof (archs[0]);
372
fecd2382
RP		 373/* BCC68000 is for patching in an extra jmp instruction for long offsets
374 on the 68000. The 68000 doesn't support long branches with branchs */
375
376/* This table desribes how you change sizes for the various types of variable
377 size expressions. This version only supports two kinds. */
378
49864cfa
KR		 379/* Note that calls to frag_var need to specify the maximum expansion
380 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 381
382/* The fields are:
a39116f1
RP		 383 How far Forward this mode will reach:
384 How far Backward this mode will reach:
385 How many bytes this mode will add to the size of the frag
386 Which mode to go to if the offset won't fit in this one
387 */
04ef74bb 388relax_typeS md_relax_table[] =
355afbcd
KR		 389{
390 {1, 1, 0, 0}, /* First entries aren't used */
391 {1, 1, 0, 0}, /* For no good reason except */
392 {1, 1, 0, 0}, /* that the VAX doesn't either */
393 {1, 1, 0, 0},
394
395 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
396 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
397 {0, 0, 4, 0},
398 {1, 1, 0, 0},
399
400 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
401 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
402 {0, 0, 4, 0},
403 {1, 1, 0, 0},
404
405 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
406 {(32767), (-32768), 2, TAB (PCREL, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409
410 {(127), (-128), 0, TAB (BCC68000, SHORT)},
411 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
412 {0, 0, 6, 0}, /* jmp long space */
413 {1, 1, 0, 0},
414
415 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
416 {(32767), (-32768), 2, TAB (DBCC, LONG)},
417 {0, 0, 10, 0}, /* bra/jmp long space */
418 {1, 1, 0, 0},
419
420 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
421 {32767, -32768, 2, TAB (PCLEA, LONG)},
422 {0, 0, 6, 0},
423 {1, 1, 0, 0},
424
04ef74bb
KR		 425 /* For, e.g., jmp pcrel indexed. */
426 {125, -130, 0, TAB (PCINDEX, SHORT)},
427 {32765, -32770, 2, TAB (PCINDEX, LONG)},
428 {0, 0, 4, 0},
429 {1, 1, 0, 0},
355afbcd 430};
fecd2382
RP		 431
432/* These are the machine dependent pseudo-ops. These are included so
433 the assembler can work on the output from the SUN C compiler, which
434 generates these.
a39116f1 435 */
fecd2382
RP		 436
437/* This table describes all the machine specific pseudo-ops the assembler
438 has to support. The fields are:
a39116f1
RP		 439 pseudo-op name without dot
440 function to call to execute this pseudo-op
441 Integer arg to pass to the function
442 */
326b087c 443const pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 444{
445 {"data1", s_data1, 0},
446 {"data2", s_data2, 0},
447 {"bss", s_bss, 0},
448 {"even", s_even, 0},
449 {"skip", s_space, 0},
450 {"proc", s_proc, 0},
a043f579 451#if defined (TE_SUN3) || defined (OBJ_ELF)
355afbcd 452 {"align", s_align_bytes, 0},
5f8cb05e
ILT		 453#endif
454#ifdef OBJ_ELF
455 {"swbeg", s_ignore, 0},
bec66218 456#endif
9e64486e
ILT		 457 {"extend", float_cons, 'x'},
458 {"ldouble", float_cons, 'x'},
e9bb39b4
ILT		 459
460 /* The following pseudo-ops are supported for MRI compatibility. */
461 {"chip", s_chip, 0},
462 {"comline", s_space, 1},
27a53b88
ILT		 463 {"fopt", s_fopt, 0},
464 {"mask2", s_ignore, 0},
6700d36e
ILT		 465 {"opt", s_opt, 0},
466 {"reg", s_reg, 0},
e14994d9
ILT		 467 {"restore", s_restore, 0},
468 {"save", s_save, 0},
e9bb39b4 469
b4ec75e0
ILT		 470 {"if", s_mri_if, 0},
471 {"if.b", s_mri_if, 'b'},
472 {"if.w", s_mri_if, 'w'},
473 {"if.l", s_mri_if, 'l'},
474 {"else", s_mri_else, 0},
475 {"else.s", s_mri_else, 's'},
476 {"else.l", s_mri_else, 'l'},
477 {"endi", s_mri_endi, 0},
478 {"break", s_mri_break, 0},
479 {"break.s", s_mri_break, 's'},
480 {"break.l", s_mri_break, 'l'},
481 {"next", s_mri_next, 0},
482 {"next.s", s_mri_next, 's'},
483 {"next.l", s_mri_next, 'l'},
484 {"for", s_mri_for, 0},
485 {"for.b", s_mri_for, 'b'},
486 {"for.w", s_mri_for, 'w'},
487 {"for.l", s_mri_for, 'l'},
488 {"endf", s_mri_endf, 0},
489 {"repeat", s_mri_repeat, 0},
490 {"until", s_mri_until, 0},
491 {"until.b", s_mri_until, 'b'},
492 {"until.w", s_mri_until, 'w'},
493 {"until.l", s_mri_until, 'l'},
494 {"while", s_mri_while, 0},
495 {"while.b", s_mri_while, 'b'},
496 {"while.w", s_mri_while, 'w'},
497 {"while.l", s_mri_while, 'l'},
498 {"endw", s_mri_endw, 0},
499
355afbcd 500 {0, 0, 0}
fecd2382
RP		 501};
502
503
3ad9ec6a 504/* The mote pseudo ops are put into the opcode table, since they
355afbcd 505 don't start with a . they look like opcodes to gas.
3ad9ec6a 506 */
355afbcd 507extern void obj_coff_section ();
3ad9ec6a 508
49864cfa 509CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 510{
511
b79de3a1 512 {"dcl", cons, 4},
355afbcd 513 {"dc", cons, 2},
b79de3a1
KR		 514 {"dcw", cons, 2},
515 {"dcb", cons, 1},
3ad9ec6a 516
b79de3a1 517 {"dsl", s_space, 4},
355afbcd 518 {"ds", s_space, 2},
b79de3a1
KR		 519 {"dsw", s_space, 2},
520 {"dsb", s_space, 1},
3ad9ec6a 521
355afbcd 522 {"xdef", s_globl, 0},
a043f579
ILT		 523#ifdef OBJ_ELF
524 {"align", s_align_bytes, 0},
525#else
355afbcd 526 {"align", s_align_ptwo, 0},
a043f579 527#endif
3ad9ec6a 528#ifdef M68KCOFF
355afbcd
KR		 529 {"sect", obj_coff_section, 0},
530 {"section", obj_coff_section, 0},
3ad9ec6a 531#endif
bcb8dff8 532 {0, 0, 0}
3ad9ec6a
ILT		 533};
534
fecd2382
RP		 535#define issbyte(x) ((x)>=-128 && (x)<=127)
536#define isubyte(x) ((x)>=0 && (x)<=255)
537#define issword(x) ((x)>=-32768 && (x)<=32767)
538#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 539
e284846a 540#define isbyte(x) ((x)>= -255 && (x)<=255)
a7512014 541#define isword(x) ((x)>=-65536 && (x)<=65535)
fecd2382 542#define islong(x) (1)
f8701a3f
SC		 543
544extern char *input_line_pointer;
fecd2382 545
fecd2382
RP		 546static char mklower_table[256];
547#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 548static char notend_table[256];
fecd2382 549static char alt_notend_table[256];
a1c7c0f3
ILT		 550#define notend(s) \
551 (! (notend_table[(unsigned char) *s] \
552 || (*s == ':' \
553 && alt_notend_table[(unsigned char) s[1]])))
7c15cbe8 554
49864cfa 555#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 556
82489ea0
KR		 557#ifdef NO_PCREL_RELOCS
558
559int
560make_pcrel_absolute(fixP, add_number)
561 fixS *fixP;
562 long *add_number;
563{
564 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
565
566 /* rewrite the PC relative instructions to absolute address ones.
567 * these are rumoured to be faster, and the apollo linker refuses
568 * to deal with the PC relative relocations.
569 */
570 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
571 {
572 opcode[0] = 0x4e;
573 opcode[1] = 0xf9;
574 }
575 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
576 {
577 opcode[0] = 0x4e;
578 opcode[1] = 0xb9;
579 }
580 else
581 as_fatal ("Unknown PC relative instruction");
582 *add_number -= 4;
583 return 0;
584}
585
586#endif /* NO_PCREL_RELOCS */
587
355afbcd
KR		 588short
589tc_coff_fix2rtype (fixP)
590 fixS *fixP;
fecd2382 591{
3b06beb7
ILT		 592 if (fixP->fx_tcbit && fixP->fx_size == 4)
593 return R_RELLONG_NEG;
82489ea0
KR		 594#ifdef NO_PCREL_RELOCS
595 know (fixP->fx_pcrel == 0);
596 return (fixP->fx_size == 1 ? R_RELBYTE
597 : fixP->fx_size == 2 ? R_DIR16
598 : R_DIR32);
599#else
355afbcd
KR		 600 return (fixP->fx_pcrel ?
601 (fixP->fx_size == 1 ? R_PCRBYTE :
602 fixP->fx_size == 2 ? R_PCRWORD :
603 R_PCRLONG) :
604 (fixP->fx_size == 1 ? R_RELBYTE :
605 fixP->fx_size == 2 ? R_RELWORD :
606 R_RELLONG));
82489ea0 607#endif
3ad9ec6a
ILT		 608}
609
610#endif
fecd2382 611
a043f579
ILT		 612#ifdef OBJ_ELF
613
614/* Compute the relocation code for a fixup of SIZE bytes, using pc
615 relative relocation if PCREL is non-zero. PIC says whether a special
616 pic relocation was requested. */
617
618static bfd_reloc_code_real_type get_reloc_code
619 PARAMS ((int, int, enum pic_relocation));
620
621static bfd_reloc_code_real_type
622get_reloc_code (size, pcrel, pic)
623 int size;
624 int pcrel;
625 enum pic_relocation pic;
626{
627 switch (pic)
628 {
629 case pic_got_pcrel:
630 switch (size)
631 {
632 case 1:
633 return BFD_RELOC_8_GOT_PCREL;
634 case 2:
635 return BFD_RELOC_16_GOT_PCREL;
636 case 4:
637 return BFD_RELOC_32_GOT_PCREL;
638 }
639 break;
640
641 case pic_got_off:
642 switch (size)
643 {
644 case 1:
645 return BFD_RELOC_8_GOTOFF;
646 case 2:
647 return BFD_RELOC_16_GOTOFF;
648 case 4:
649 return BFD_RELOC_32_GOTOFF;
650 }
651 break;
652
653 case pic_plt_pcrel:
654 switch (size)
655 {
656 case 1:
657 return BFD_RELOC_8_PLT_PCREL;
658 case 2:
659 return BFD_RELOC_16_PLT_PCREL;
660 case 4:
661 return BFD_RELOC_32_PLT_PCREL;
662 }
663 break;
664
665 case pic_plt_off:
666 switch (size)
667 {
668 case 1:
669 return BFD_RELOC_8_PLTOFF;
670 case 2:
671 return BFD_RELOC_16_PLTOFF;
672 case 4:
673 return BFD_RELOC_32_PLTOFF;
674 }
675 break;
676
677 case pic_none:
678 if (pcrel)
679 {
680 switch (size)
681 {
682 case 1:
683 return BFD_RELOC_8_PCREL;
684 case 2:
685 return BFD_RELOC_16_PCREL;
686 case 4:
687 return BFD_RELOC_32_PCREL;
688 }
689 }
690 else
691 {
692 switch (size)
693 {
694 case 1:
695 return BFD_RELOC_8;
696 case 2:
697 return BFD_RELOC_16;
698 case 4:
699 return BFD_RELOC_32;
700 }
701 }
702 }
703
704 as_bad ("Can not do %d byte %s%srelocation", size,
705 pcrel ? "pc-relative " : "",
706 pic == pic_none ? "" : "pic ");
707 return BFD_RELOC_NONE;
708}
709
710/* Here we decide which fixups can be adjusted to make them relative
711 to the beginning of the section instead of the symbol. Basically
712 we need to make sure that the dynamic relocations are done
713 correctly, so in some cases we force the original symbol to be
714 used. */
715int
716tc_m68k_fix_adjustable (fixP)
717 fixS *fixP;
718{
719 /* Prevent all adjustments to global symbols. */
720 if (S_IS_EXTERNAL (fixP->fx_addsy))
721 return 0;
722
723 /* adjust_reloc_syms doesn't know about the GOT */
724 switch (fixP->fx_r_type)
725 {
726 case BFD_RELOC_8_GOT_PCREL:
727 case BFD_RELOC_16_GOT_PCREL:
728 case BFD_RELOC_32_GOT_PCREL:
729 case BFD_RELOC_8_GOTOFF:
730 case BFD_RELOC_16_GOTOFF:
731 case BFD_RELOC_32_GOTOFF:
732 case BFD_RELOC_8_PLT_PCREL:
733 case BFD_RELOC_16_PLT_PCREL:
734 case BFD_RELOC_32_PLT_PCREL:
735 case BFD_RELOC_8_PLTOFF:
736 case BFD_RELOC_16_PLTOFF:
737 case BFD_RELOC_32_PLTOFF:
738 return 0;
739
740 default:
741 return 1;
742 }
743}
744
745#else /* !OBJ_ELF */
746
747#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
748
749#endif /* OBJ_ELF */
750
49864cfa
KR		 751#ifdef BFD_ASSEMBLER
752
753arelent *
754tc_gen_reloc (section, fixp)
755 asection *section;
756 fixS *fixp;
757{
758 arelent *reloc;
759 bfd_reloc_code_real_type code;
760
9e64486e 761 if (fixp->fx_tcbit)
3b06beb7
ILT		 762 abort ();
763
a043f579 764 if (fixp->fx_r_type != BFD_RELOC_NONE)
7f003b7f
ILT		 765 {
766 code = fixp->fx_r_type;
767
768 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
769 that fixup_segment converted a non-PC relative reloc into a
770 PC relative reloc. In such a case, we need to convert the
771 reloc code. */
772 if (fixp->fx_pcrel)
773 {
774 switch (code)
775 {
776 case BFD_RELOC_8:
777 code = BFD_RELOC_8_PCREL;
778 break;
779 case BFD_RELOC_16:
780 code = BFD_RELOC_16_PCREL;
781 break;
782 case BFD_RELOC_32:
783 code = BFD_RELOC_32_PCREL;
784 break;
785 case BFD_RELOC_8_PCREL:
786 case BFD_RELOC_16_PCREL:
787 case BFD_RELOC_32_PCREL:
788 case BFD_RELOC_8_GOT_PCREL:
789 case BFD_RELOC_16_GOT_PCREL:
790 case BFD_RELOC_32_GOT_PCREL:
791 case BFD_RELOC_8_GOTOFF:
792 case BFD_RELOC_16_GOTOFF:
793 case BFD_RELOC_32_GOTOFF:
794 case BFD_RELOC_8_PLT_PCREL:
795 case BFD_RELOC_16_PLT_PCREL:
796 case BFD_RELOC_32_PLT_PCREL:
797 case BFD_RELOC_8_PLTOFF:
798 case BFD_RELOC_16_PLTOFF:
799 case BFD_RELOC_32_PLTOFF:
800 break;
801 default:
802 as_bad_where (fixp->fx_file, fixp->fx_line,
803 "Cannot make %s relocation PC relative",
804 bfd_get_reloc_code_name (code));
805 }
806 }
807 }
a043f579 808 else
49864cfa 809 {
a043f579
ILT		 810#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
811 switch (F (fixp->fx_size, fixp->fx_pcrel))
812 {
49864cfa 813#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
a043f579
ILT		 814 MAP (1, 0, BFD_RELOC_8);
815 MAP (2, 0, BFD_RELOC_16);
816 MAP (4, 0, BFD_RELOC_32);
817 MAP (1, 1, BFD_RELOC_8_PCREL);
818 MAP (2, 1, BFD_RELOC_16_PCREL);
819 MAP (4, 1, BFD_RELOC_32_PCREL);
820 default:
821 abort ();
822 }
49864cfa 823 }
a043f579
ILT		 824#undef F
825#undef MAP
49864cfa
KR		 826
827 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
828 assert (reloc != 0);
829 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
830 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a043f579 831#ifndef OBJ_ELF
49864cfa
KR		 832 if (fixp->fx_pcrel)
833 reloc->addend = fixp->fx_addnumber;
834 else
835 reloc->addend = 0;
a043f579
ILT		 836#else
837 if (!fixp->fx_pcrel)
838 reloc->addend = fixp->fx_addnumber;
7f003b7f 839 else
a043f579
ILT		 840 reloc->addend = (section->vma
841 + (fixp->fx_pcrel_adjust == 64
842 ? -1 : fixp->fx_pcrel_adjust)
843 + fixp->fx_addnumber
844 + md_pcrel_from (fixp));
a043f579 845#endif
49864cfa
KR		 846
847 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
848 assert (reloc->howto != 0);
849
850 return reloc;
851}
852
853#endif /* BFD_ASSEMBLER */
854
49864cfa
KR		 855/* Handle of the OPCODE hash table. NULL means any use before
856 m68k_ip_begin() will crash. */
857static struct hash_control *op_hash;
fecd2382 858\f
a1c7c0f3 859/* Assemble an m68k instruction. */
355afbcd 860
355afbcd
KR		 861void
862m68k_ip (instring)
6d27d3a2 863 char *instring;
fecd2382 864{
6d27d3a2
KR		 865 register char *p;
866 register struct m68k_op *opP;
867 register struct m68k_incant *opcode;
a1c7c0f3 868 register const char *s;
6d27d3a2 869 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 870 char *pdot, *pdotmove;
a1c7c0f3 871 enum m68k_size siz1, siz2;
355afbcd
KR		 872 char c;
873 int losing;
874 int opsfound;
875 char *crack_operand ();
6d27d3a2
KR		 876 LITTLENUM_TYPE words[6];
877 LITTLENUM_TYPE *wordp;
8be74775 878 unsigned long ok_arch = 0;
6d27d3a2
KR		 879
880 if (*instring == ' ')
881 instring++; /* skip leading whitespace */
882
883 /* Scan up to end of operation-code, which MUST end in end-of-string
884 or exactly 1 space. */
3ad9ec6a 885 pdot = 0;
355afbcd
KR		 886 for (p = instring; *p != '\0'; p++)
887 {
888 if (*p == ' ')
889 break;
890 if (*p == '.')
891 pdot = p;
892 }
6d27d3a2 893
355afbcd
KR		 894 if (p == instring)
895 {
896 the_ins.error = "No operator";
355afbcd
KR		 897 return;
898 }
6d27d3a2
KR		 899
900 /* p now points to the end of the opcode name, probably whitespace.
a1c7c0f3
ILT		 901 Make sure the name is null terminated by clobbering the
902 whitespace, look it up in the hash table, then fix it back.
3ad9ec6a 903 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 904 if (pdot != NULL)
905 {
906 for (pdotmove = pdot; pdotmove < p; pdotmove++)
907 *pdotmove = pdotmove[1];
908 p--;
909 }
3ad9ec6a 910
6d27d3a2
KR		 911 c = *p;
912 *p = '\0';
355afbcd 913 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 914 *p = c;
915
355afbcd
KR		 916 if (pdot != NULL)
917 {
918 for (pdotmove = p; pdotmove > pdot; pdotmove--)
919 *pdotmove = pdotmove[-1];
920 *pdot = '.';
921 ++p;
922 }
3ad9ec6a 923
355afbcd
KR		 924 if (opcode == NULL)
925 {
926 the_ins.error = "Unknown operator";
355afbcd
KR		 927 return;
928 }
6d27d3a2
KR		 929
930 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 931 while (*p == ' ')
932 ++p;
6d27d3a2 933
355afbcd
KR		 934 if (opcode->m_operands == 0)
935 {
936 char *old = input_line_pointer;
937 *old = '\n';
938 input_line_pointer = p;
939 /* Ahh - it's a motorola style psuedo op */
940 mote_pseudo_table[opcode->m_opnum].poc_handler
941 (mote_pseudo_table[opcode->m_opnum].poc_val);
942 input_line_pointer = old;
943 *old = 0;
3ad9ec6a 944
355afbcd
KR		 945 return;
946 }
3ad9ec6a 947
92a25e12
ILT		 948 if (flag_mri && opcode->m_opnum == 0)
949 {
950 /* In MRI mode, random garbage is allowed after an instruction
951 which accepts no operands. */
952 the_ins.args = opcode->m_operands;
953 the_ins.numargs = opcode->m_opnum;
954 the_ins.numo = opcode->m_codenum;
955 the_ins.opcode[0] = getone (opcode);
956 the_ins.opcode[1] = gettwo (opcode);
957 return;
958 }
959
355afbcd
KR		 960 for (opP = &the_ins.operands[0]; *p; opP++)
961 {
355afbcd 962 p = crack_operand (p, opP);
6d27d3a2 963
355afbcd
KR		 964 if (opP->error)
965 {
966 the_ins.error = opP->error;
967 return;
968 }
6d27d3a2 969 }
6d27d3a2
KR		 970
971 opsfound = opP - &the_ins.operands[0];
972
a1c7c0f3
ILT		 973 /* This ugly hack is to support the floating pt opcodes in their
974 standard form. Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 975 if (opcode->m_operands[0] == 'I')
976 {
977 int n;
6d27d3a2 978
355afbcd
KR		 979 for (n = opsfound; n > 0; --n)
980 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 981
a1c7c0f3
ILT		 982 memset ((char *) (&the_ins.operands[0]), '\0',
983 sizeof (the_ins.operands[0]));
984 the_ins.operands[0].mode = CONTROL;
27a53b88 985 the_ins.operands[0].reg = m68k_float_copnum;
355afbcd
KR		 986 opsfound++;
987 }
6d27d3a2
KR		 988
989 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 990 for (losing = 0;;)
991 {
49864cfa
KR		 992 /* If we didn't get the right number of ops, or we have no
993 common model with this pattern then reject this pattern. */
6d27d3a2 994
355afbcd
KR		 995 if (opsfound != opcode->m_opnum
996 || ((opcode->m_arch & current_architecture) == 0))
997 {
998 ++losing;
999 ok_arch |= opcode->m_arch;
1000 }
1001 else
1002 {
a1c7c0f3
ILT		 1003 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1004 *s && !losing;
1005 s += 2, opP++)
355afbcd
KR		 1006 {
1007 /* Warning: this switch is huge! */
49864cfa
KR		 1008 /* I've tried to organize the cases into this order:
1009 non-alpha first, then alpha by letter. Lower-case
1010 goes directly before uppercase counterpart. */
1011 /* Code with multiple case ...: gets sorted by the lowest
1012 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 1013 switch (*s)
1014 {
a1c7c0f3
ILT		 1015 case '!':
1016 switch (opP->mode)
1017 {
1018 case IMMED:
1019 case DREG:
1020 case AREG:
1021 case FPREG:
1022 case CONTROL:
1023 case AINC:
1024 case ADEC:
1025 case REGLST:
1026 losing++;
1027 break;
1028 default:
1029 break;
1030 }
355afbcd
KR		 1031 break;
1032
1033 case '`':
1034 switch (opP->mode)
1035 {
355afbcd
KR		 1036 case IMMED:
1037 case DREG:
1038 case AREG:
a1c7c0f3
ILT		 1039 case FPREG:
1040 case CONTROL:
355afbcd
KR		 1041 case AINC:
1042 case REGLST:
1043 case AINDR:
1044 losing++;
bcb8dff8
KR		 1045 break;
1046 default:
1047 break;
355afbcd
KR		 1048 }
1049 break;
8be74775 1050
355afbcd
KR		 1051 case '#':
1052 if (opP->mode != IMMED)
1053 losing++;
a1c7c0f3
ILT		 1054 else if (s[1] == 'b'
1055 && ! isvar (&opP->disp)
336435bc
ILT		 1056 && (opP->disp.exp.X_op != O_constant
1057 || ! isbyte (opP->disp.exp.X_add_number)))
a1c7c0f3
ILT		 1058 losing++;
1059 else if (s[1] == 'w'
1060 && ! isvar (&opP->disp)
336435bc
ILT		 1061 && (opP->disp.exp.X_op != O_constant
1062 || ! isword (opP->disp.exp.X_add_number)))
a1c7c0f3 1063 losing++;
9e64486e
ILT		 1064 else if (s[1] == 'W'
1065 && ! isvar (&opP->disp)
1066 && (opP->disp.exp.X_op != O_constant
1067 || ! issword (opP->disp.exp.X_add_number)))
1068 losing++;
355afbcd
KR		 1069 break;
1070
1071 case '^':
1072 case 'T':
1073 if (opP->mode != IMMED)
1074 losing++;
1075 break;
1076
1077 case '$':
a1c7c0f3
ILT		 1078 if (opP->mode == AREG
1079 || opP->mode == CONTROL
1080 || opP->mode == FPREG
1081 || opP->mode == IMMED
1082 || opP->mode == REGLST
1083 || (opP->mode != ABSL
1084 && (opP->reg == PC
1085 || opP->reg == ZPC)))
355afbcd
KR		 1086 losing++;
1087 break;
1088
1089 case '%':
a1c7c0f3
ILT		 1090 if (opP->mode == CONTROL
1091 || opP->mode == FPREG
1092 || opP->mode == REGLST
a7512014 1093 || opP->mode == IMMED
a1c7c0f3 1094 || (opP->mode != ABSL
a1c7c0f3
ILT		 1095 && (opP->reg == PC
1096 || opP->reg == ZPC)))
355afbcd
KR		 1097 losing++;
1098 break;
1099
355afbcd 1100 case '&':
a1c7c0f3
ILT		 1101 switch (opP->mode)
1102 {
1103 case DREG:
1104 case AREG:
1105 case FPREG:
1106 case CONTROL:
1107 case IMMED:
1108 case AINC:
1109 case ADEC:
1110 case REGLST:
1111 losing++;
1112 break;
1113 case ABSL:
1114 break;
1115 default:
1116 if (opP->reg == PC
1117 || opP->reg == ZPC)
1118 losing++;
1119 break;
1120 }
355afbcd
KR		 1121 break;
1122
1123 case '*':
a1c7c0f3
ILT		 1124 if (opP->mode == CONTROL
1125 || opP->mode == FPREG
1126 || opP->mode == REGLST)
355afbcd
KR		 1127 losing++;
1128 break;
1129
1130 case '+':
1131 if (opP->mode != AINC)
1132 losing++;
1133 break;
1134
1135 case '-':
1136 if (opP->mode != ADEC)
1137 losing++;
1138 break;
1139
1140 case '/':
a1c7c0f3
ILT		 1141 switch (opP->mode)
1142 {
1143 case AREG:
1144 case CONTROL:
1145 case FPREG:
1146 case AINC:
1147 case ADEC:
1148 case IMMED:
1149 case REGLST:
1150 losing++;
1151 break;
1152 default:
1153 break;
1154 }
355afbcd
KR		 1155 break;
1156
1157 case ';':
a1c7c0f3
ILT		 1158 switch (opP->mode)
1159 {
1160 case AREG:
1161 case CONTROL:
1162 case FPREG:
1163 case REGLST:
1164 losing++;
1165 break;
1166 default:
1167 break;
1168 }
355afbcd
KR		 1169 break;
1170
1171 case '?':
a1c7c0f3
ILT		 1172 switch (opP->mode)
1173 {
1174 case AREG:
1175 case CONTROL:
1176 case FPREG:
1177 case AINC:
1178 case ADEC:
1179 case IMMED:
1180 case REGLST:
1181 losing++;
1182 break;
1183 case ABSL:
1184 break;
1185 default:
1186 if (opP->reg == PC || opP->reg == ZPC)
1187 losing++;
1188 break;
1189 }
355afbcd
KR		 1190 break;
1191
1192 case '@':
a1c7c0f3
ILT		 1193 switch (opP->mode)
1194 {
1195 case AREG:
1196 case CONTROL:
1197 case FPREG:
1198 case IMMED:
1199 case REGLST:
1200 losing++;
1201 break;
1202 default:
1203 break;
1204 }
355afbcd
KR		 1205 break;
1206
1207 case '~': /* For now! (JF FOO is this right?) */
a1c7c0f3
ILT		 1208 switch (opP->mode)
1209 {
1210 case DREG:
1211 case AREG:
1212 case CONTROL:
1213 case FPREG:
1214 case IMMED:
1215 case REGLST:
1216 losing++;
1217 break;
1218 case ABSL:
1219 break;
1220 default:
1221 if (opP->reg == PC
1222 || opP->reg == ZPC)
1223 losing++;
1224 break;
1225 }
355afbcd
KR		 1226 break;
1227
1228 case '3':
a1c7c0f3
ILT		 1229 if (opP->mode != CONTROL
1230 || (opP->reg != TT0 && opP->reg != TT1))
355afbcd
KR		 1231 losing++;
1232 break;
1233
1234 case 'A':
1235 if (opP->mode != AREG)
1236 losing++;
1237 break;
a1c7c0f3 1238
355afbcd
KR		 1239 case 'a':
1240 if (opP->mode != AINDR)
a1c7c0f3 1241 ++losing;
355afbcd 1242 break;
a1c7c0f3 1243
355afbcd 1244 case 'B': /* FOO */
a1c7c0f3
ILT		 1245 if (opP->mode != ABSL
1246 || (flag_long_jumps
1247 && strncmp (instring, "jbsr", 4) == 0))
355afbcd
KR		 1248 losing++;
1249 break;
1250
1251 case 'C':
a1c7c0f3 1252 if (opP->mode != CONTROL || opP->reg != CCR)
355afbcd
KR		 1253 losing++;
1254 break;
1255
a1c7c0f3
ILT		 1256 case 'd':
1257 if (opP->mode != DISP
1258 || opP->reg < ADDR0
1259 || opP->reg > ADDR7)
355afbcd
KR		 1260 losing++;
1261 break;
1262
1263 case 'D':
1264 if (opP->mode != DREG)
1265 losing++;
1266 break;
1267
1268 case 'F':
a1c7c0f3 1269 if (opP->mode != FPREG)
355afbcd
KR		 1270 losing++;
1271 break;
1272
1273 case 'I':
a1c7c0f3 1274 if (opP->mode != CONTROL
27a53b88
ILT		 1275 || opP->reg < COP0
1276 || opP->reg > COP7)
355afbcd
KR		 1277 losing++;
1278 break;
1279
1280 case 'J':
a1c7c0f3 1281 if (opP->mode != CONTROL
355afbcd 1282 || opP->reg < USP
82489ea0
KR		 1283 || opP->reg > last_movec_reg)
1284 losing++;
1285 else
355afbcd 1286 {
a1c7c0f3 1287 const enum m68k_register *rp;
82489ea0
KR		 1288 for (rp = control_regs; *rp; rp++)
1289 if (*rp == opP->reg)
1290 break;
1291 if (*rp == 0)
1292 losing++;
1293 }
355afbcd
KR		 1294 break;
1295
1296 case 'k':
1297 if (opP->mode != IMMED)
1298 losing++;
1299 break;
8be74775 1300
355afbcd
KR		 1301 case 'l':
1302 case 'L':
a1c7c0f3
ILT		 1303 if (opP->mode == DREG
1304 || opP->mode == AREG
1305 || opP->mode == FPREG)
355afbcd
KR		 1306 {
1307 if (s[1] == '8')
1308 losing++;
1309 else
1310 {
a1c7c0f3
ILT		 1311 switch (opP->mode)
1312 {
1313 case DREG:
1314 opP->mask = 1 << (opP->reg - DATA0);
1315 break;
1316 case AREG:
1317 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1318 break;
1319 case FPREG:
1320 opP->mask = 1 << (opP->reg - FP0 + 16);
1321 break;
1322 default:
1323 abort ();
1324 }
355afbcd 1325 opP->mode = REGLST;
355afbcd
KR		 1326 }
1327 }
a1c7c0f3 1328 else if (opP->mode == CONTROL)
355afbcd 1329 {
a1c7c0f3
ILT		 1330 if (s[1] != '8')
1331 losing++;
1332 else
1333 {
1334 switch (opP->reg)
1335 {
1336 case FPI:
1337 opP->mask = 1 << 24;
1338 break;
1339 case FPS:
1340 opP->mask = 1 << 25;
1341 break;
1342 case FPC:
1343 opP->mask = 1 << 26;
1344 break;
1345 default:
1346 losing++;
1347 break;
1348 }
1349 opP->mode = REGLST;
1350 }
355afbcd 1351 }
6700d36e
ILT		 1352 else if (opP->mode == ABSL
1353 && opP->disp.size == SIZE_UNSPEC
1354 && opP->disp.exp.X_op == O_constant)
1355 {
1356 /* This is what the MRI REG pseudo-op generates. */
1357 opP->mode = REGLST;
1358 opP->mask = opP->disp.exp.X_add_number;
1359 }
a1c7c0f3 1360 else if (opP->mode != REGLST)
355afbcd 1361 losing++;
a1c7c0f3
ILT		 1362 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1363 losing++;
1364 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
355afbcd
KR		 1365 losing++;
1366 break;
1367
1368 case 'M':
1369 if (opP->mode != IMMED)
1370 losing++;
336435bc
ILT		 1371 else if (opP->disp.exp.X_op != O_constant
1372 || ! issbyte (opP->disp.exp.X_add_number))
a1c7c0f3 1373 losing++;
6700d36e
ILT		 1374 else if (! m68k_quick
1375 && instring[3] != 'q'
1376 && instring[4] != 'q')
1377 losing++;
355afbcd 1378 break;
8be74775 1379
355afbcd 1380 case 'O':
8d20a0a8
C		 1381 if (opP->mode != DREG
1382 && opP->mode != IMMED
1383 && opP->mode != ABSL)
355afbcd
KR		 1384 losing++;
1385 break;
6d27d3a2 1386
355afbcd
KR		 1387 case 'Q':
1388 if (opP->mode != IMMED)
1389 losing++;
336435bc 1390 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1391 || opP->disp.exp.X_add_number < 1
1392 || opP->disp.exp.X_add_number > 8)
1393 losing++;
6700d36e
ILT		 1394 else if (! m68k_quick
1395 && (strncmp (instring, "add", 3) == 0
1396 || strncmp (instring, "sub", 3) == 0)
1397 && instring[3] != 'q')
1398 losing++;
355afbcd 1399 break;
8be74775 1400
355afbcd
KR		 1401 case 'R':
1402 if (opP->mode != DREG && opP->mode != AREG)
1403 losing++;
1404 break;
8be74775 1405
355afbcd 1406 case 'r':
a1c7c0f3
ILT		 1407 if (opP->mode != AINDR
1408 && (opP->mode != BASE
1409 || (opP->reg != 0
1410 && opP->reg != ZADDR0)
1411 || opP->disp.exp.X_op != O_absent
1412 || ((opP->index.reg < DATA0
1413 || opP->index.reg > DATA7)
1414 && (opP->index.reg < ADDR0
1415 || opP->index.reg > ADDR7))
1416 || opP->index.size != SIZE_UNSPEC
1417 || opP->index.scale != 1))
355afbcd
KR		 1418 losing++;
1419 break;
c50140c8 1420
355afbcd 1421 case 's':
a1c7c0f3
ILT		 1422 if (opP->mode != CONTROL
1423 || ! (opP->reg == FPI
1424 || opP->reg == FPS
1425 || opP->reg == FPC))
355afbcd
KR		 1426 losing++;
1427 break;
8be74775 1428
355afbcd 1429 case 'S':
a1c7c0f3 1430 if (opP->mode != CONTROL || opP->reg != SR)
355afbcd
KR		 1431 losing++;
1432 break;
8be74775 1433
355afbcd
KR		 1434 case 't':
1435 if (opP->mode != IMMED)
1436 losing++;
336435bc 1437 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1438 || opP->disp.exp.X_add_number < 0
1439 || opP->disp.exp.X_add_number > 7)
1440 losing++;
355afbcd 1441 break;
4134a793 1442
355afbcd 1443 case 'U':
a1c7c0f3 1444 if (opP->mode != CONTROL || opP->reg != USP)
355afbcd
KR		 1445 losing++;
1446 break;
8be74775 1447
355afbcd 1448 /* JF these are out of order. We could put them
1404ef23
KR		 1449 in order if we were willing to put up with
1450 bunches of #ifdef m68851s in the code.
4134a793 1451
1404ef23
KR		 1452 Don't forget that you need these operands
1453 to use 68030 MMU instructions. */
f8701a3f 1454#ifndef NO_68851
355afbcd
KR		 1455 /* Memory addressing mode used by pflushr */
1456 case '|':
a1c7c0f3
ILT		 1457 if (opP->mode == CONTROL
1458 || opP->mode == FPREG
1459 || opP->mode == DREG
1460 || opP->mode == AREG
1461 || opP->mode == REGLST)
355afbcd 1462 losing++;
9adcd781
ILT		 1463 /* We should accept immediate operands, but they
1464 supposedly have to be quad word, and we don't
1465 handle that. I would like to see what a Motorola
1466 assembler does before doing something here. */
1467 if (opP->mode == IMMED)
1468 losing++;
355afbcd
KR		 1469 break;
1470
1471 case 'f':
a1c7c0f3
ILT		 1472 if (opP->mode != CONTROL
1473 || (opP->reg != SFC && opP->reg != DFC))
355afbcd
KR		 1474 losing++;
1475 break;
1476
9adcd781
ILT		 1477 case '0':
1478 if (opP->mode != CONTROL || opP->reg != TC)
1479 losing++;
1480 break;
1481
1482 case '1':
1483 if (opP->mode != CONTROL || opP->reg != AC)
1484 losing++;
1485 break;
1486
1487 case '2':
a1c7c0f3 1488 if (opP->mode != CONTROL
9adcd781 1489 || (opP->reg != CAL
a1c7c0f3 1490 && opP->reg != VAL
9adcd781 1491 && opP->reg != SCC))
355afbcd
KR		 1492 losing++;
1493 break;
1494
1495 case 'V':
a1c7c0f3
ILT		 1496 if (opP->mode != CONTROL
1497 || opP->reg != VAL)
355afbcd
KR		 1498 losing++;
1499 break;
8be74775 1500
355afbcd 1501 case 'W':
a1c7c0f3
ILT		 1502 if (opP->mode != CONTROL
1503 || (opP->reg != DRP
1504 && opP->reg != SRP
355afbcd
KR		 1505 && opP->reg != CRP))
1506 losing++;
1507 break;
1508
1509 case 'X':
a1c7c0f3
ILT		 1510 if (opP->mode != CONTROL
1511 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1512 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
355afbcd
KR		 1513 losing++;
1514 break;
1515
1516 case 'Y':
a1c7c0f3 1517 if (opP->mode != CONTROL || opP->reg != PSR)
355afbcd
KR		 1518 losing++;
1519 break;
1520
1521 case 'Z':
a1c7c0f3 1522 if (opP->mode != CONTROL || opP->reg != PCSR)
355afbcd
KR		 1523 losing++;
1524 break;
f8701a3f 1525#endif
355afbcd 1526 case 'c':
a1c7c0f3
ILT		 1527 if (opP->mode != CONTROL
1528 || (opP->reg != NC
1529 && opP->reg != IC
1530 && opP->reg != DC
1531 && opP->reg != BC))
355afbcd
KR		 1532 {
1533 losing++;
1534 } /* not a cache specifier. */
1535 break;
1536
1537 case '_':
1538 if (opP->mode != ABSL)
a1c7c0f3 1539 ++losing;
355afbcd 1540 break;
8be74775 1541
355afbcd 1542 default:
a1c7c0f3 1543 abort ();
355afbcd 1544 } /* switch on type of operand */
6d27d3a2 1545
355afbcd
KR		 1546 if (losing)
1547 break;
1548 } /* for each operand */
1549 } /* if immediately wrong */
6d27d3a2 1550
355afbcd
KR		 1551 if (!losing)
1552 {
8be74775 1553 break;
355afbcd 1554 } /* got it. */
6d27d3a2 1555
355afbcd 1556 opcode = opcode->m_next;
6d27d3a2 1557
355afbcd 1558 if (!opcode)
8be74775 1559 {
355afbcd
KR		 1560 if (ok_arch
1561 && !(ok_arch & current_architecture))
8be74775 1562 {
355afbcd 1563 char buf[200], *cp;
091221ce 1564
a1c7c0f3
ILT		 1565 strcpy (buf,
1566 "invalid instruction for this architecture; needs ");
355afbcd
KR		 1567 cp = buf + strlen (buf);
1568 switch (ok_arch)
1569 {
1570 case mfloat:
82489ea0 1571 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
355afbcd
KR		 1572 break;
1573 case mmmu:
1574 strcpy (cp, "mmu (68030 or 68851)");
1575 break;
1576 case m68020up:
1577 strcpy (cp, "68020 or higher");
1578 break;
1579 case m68000up:
1580 strcpy (cp, "68000 or higher");
1581 break;
1582 case m68010up:
1583 strcpy (cp, "68010 or higher");
1584 break;
1585 default:
8be74775 1586 {
355afbcd 1587 int got_one = 0, idx;
a1c7c0f3
ILT		 1588 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1589 idx++)
8be74775 1590 {
9e64486e
ILT		 1591 if ((archs[idx].arch & ok_arch)
1592 && ! archs[idx].alias)
8be74775 1593 {
355afbcd
KR		 1594 if (got_one)
1595 {
1596 strcpy (cp, " or ");
1597 cp += strlen (cp);
1598 }
1599 got_one = 1;
1600 strcpy (cp, archs[idx].name);
8be74775
KR		 1601 cp += strlen (cp);
1602 }
8be74775
KR		 1603 }
1604 }
355afbcd 1605 }
091221ce 1606 cp = xmalloc (strlen (buf) + 1);
355afbcd
KR		 1607 strcpy (cp, buf);
1608 the_ins.error = cp;
8be74775 1609 }
355afbcd
KR		 1610 else
1611 the_ins.error = "operands mismatch";
1612 return;
1613 } /* Fell off the end */
6d27d3a2 1614
355afbcd
KR		 1615 losing = 0;
1616 }
6d27d3a2
KR		 1617
1618 /* now assemble it */
1619
355afbcd
KR		 1620 the_ins.args = opcode->m_operands;
1621 the_ins.numargs = opcode->m_opnum;
1622 the_ins.numo = opcode->m_codenum;
1623 the_ins.opcode[0] = getone (opcode);
1624 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 1625
355afbcd
KR		 1626 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1627 {
1628 /* This switch is a doozy.
6d27d3a2 1629 Watch the first step; its a big one! */
355afbcd
KR		 1630 switch (s[0])
1631 {
6d27d3a2 1632
355afbcd
KR		 1633 case '*':
1634 case '~':
1635 case '%':
1636 case ';':
1637 case '@':
1638 case '!':
1639 case '&':
1640 case '$':
1641 case '?':
1642 case '/':
1643 case '`':
1644#ifndef NO_68851
1645 case '|':
1646#endif
1647 switch (opP->mode)
1648 {
1649 case IMMED:
1650 tmpreg = 0x3c; /* 7.4 */
1651 if (strchr ("bwl", s[1]))
a1c7c0f3 1652 nextword = get_num (&opP->disp, 80);
355afbcd 1653 else
a1c7c0f3
ILT		 1654 nextword = get_num (&opP->disp, 0);
1655 if (isvar (&opP->disp))
1656 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1657 switch (s[1])
1658 {
1659 case 'b':
1660 if (!isbyte (nextword))
1661 opP->error = "operand out of range";
1662 addword (nextword);
1663 baseo = 0;
1664 break;
1665 case 'w':
1666 if (!isword (nextword))
1667 opP->error = "operand out of range";
1668 addword (nextword);
1669 baseo = 0;
1670 break;
9e64486e
ILT		 1671 case 'W':
1672 if (!issword (nextword))
1673 opP->error = "operand out of range";
1674 addword (nextword);
1675 baseo = 0;
1676 break;
355afbcd
KR		 1677 case 'l':
1678 addword (nextword >> 16);
1679 addword (nextword);
1680 baseo = 0;
1681 break;
1682
1683 case 'f':
1684 baseo = 2;
1685 outro = 8;
1686 break;
1687 case 'F':
1688 baseo = 4;
1689 outro = 11;
1690 break;
1691 case 'x':
1692 baseo = 6;
1693 outro = 15;
1694 break;
1695 case 'p':
1696 baseo = 6;
1697 outro = -1;
1698 break;
1699 default:
a1c7c0f3 1700 abort ();
355afbcd
KR		 1701 }
1702 if (!baseo)
1703 break;
6d27d3a2 1704
355afbcd 1705 /* We gotta put out some float */
a1c7c0f3 1706 if (op (&opP->disp) != O_big)
355afbcd 1707 {
bcb8dff8
KR		 1708 valueT val;
1709 int gencnt;
1710
1711 /* Can other cases happen here? */
a1c7c0f3 1712 if (op (&opP->disp) != O_constant)
bcb8dff8 1713 abort ();
82489ea0 1714
a1c7c0f3 1715 val = (valueT) offs (&opP->disp);
bcb8dff8
KR		 1716 gencnt = 0;
1717 do
1718 {
1719 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1720 val >>= LITTLENUM_NUMBER_OF_BITS;
1721 ++gencnt;
1722 }
1723 while (val != 0);
a1c7c0f3 1724 offs (&opP->disp) = gencnt;
355afbcd 1725 }
a1c7c0f3 1726 if (offs (&opP->disp) > 0)
355afbcd 1727 {
a1c7c0f3 1728 if (offs (&opP->disp) > baseo)
355afbcd 1729 {
a1c7c0f3
ILT		 1730 as_warn ("Bignum too big for %c format; truncated",
1731 s[1]);
1732 offs (&opP->disp) = baseo;
355afbcd 1733 }
a1c7c0f3 1734 baseo -= offs (&opP->disp);
355afbcd
KR		 1735 while (baseo--)
1736 addword (0);
a1c7c0f3
ILT		 1737 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1738 offs (&opP->disp)--;
1739 --wordp)
bcb8dff8 1740 addword (*wordp);
355afbcd
KR		 1741 break;
1742 }
1743 gen_to_words (words, baseo, (long) outro);
1744 for (wordp = words; baseo--; wordp++)
1745 addword (*wordp);
1746 break;
1747 case DREG:
1748 tmpreg = opP->reg - DATA; /* 0.dreg */
1749 break;
1750 case AREG:
1751 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1752 break;
1753 case AINDR:
1754 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1755 break;
1756 case ADEC:
1757 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1758 break;
1759 case AINC:
1760 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1761 break;
a1c7c0f3 1762 case DISP:
6d27d3a2 1763
a1c7c0f3 1764 nextword = get_num (&opP->disp, 80);
6700d36e
ILT		 1765
1766 if (opP->reg == PC
1767 && ! isvar (&opP->disp)
1768 && m68k_abspcadd)
1769 {
1770 opP->disp.exp.X_op = O_symbol;
1771#ifndef BFD_ASSEMBLER
1772 opP->disp.exp.X_add_symbol = &abs_symbol;
1773#else
1774 opP->disp.exp.X_add_symbol =
1775 section_symbol (absolute_section);
1776#endif
1777 }
1778
355afbcd 1779 /* Force into index mode. Hope this works */
6d27d3a2 1780
1404ef23
KR		 1781 /* We do the first bit for 32-bit displacements, and the
1782 second bit for 16 bit ones. It is possible that we
1783 should make the default be WORD instead of LONG, but
1784 I think that'd break GCC, so we put up with a little
1785 inefficiency for the sake of working output. */
6d27d3a2 1786
355afbcd 1787 if (!issword (nextword)
a1c7c0f3
ILT		 1788 || (isvar (&opP->disp)
1789 && ((opP->disp.size == SIZE_UNSPEC
b79de3a1
KR		 1790 && flag_short_refs == 0
1791 && cpu_of_arch (current_architecture) >= m68020)
a1c7c0f3 1792 || opP->disp.size == SIZE_LONG)))
355afbcd 1793 {
912e4245
ILT		 1794 if (cpu_of_arch (current_architecture) < m68020)
1795 opP->error =
1796 "displacement too large for this architecture; needs 68020 or higher";
355afbcd
KR		 1797 if (opP->reg == PC)
1798 tmpreg = 0x3B; /* 7.3 */
1799 else
1800 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
a1c7c0f3 1801 if (isvar (&opP->disp))
355afbcd
KR		 1802 {
1803 if (opP->reg == PC)
1804 {
a043f579
ILT		 1805 if (opP->disp.size == SIZE_LONG
1806#ifdef OBJ_ELF
1807 /* If the displacement needs pic
1808 relocation it cannot be relaxed. */
1809 || opP->disp.pic_reloc != pic_none
04ef74bb 1810#endif
a043f579
ILT		 1811 )
1812 {
1813 addword (0x0170);
1814 add_fix ('l', &opP->disp, 1, 2);
1815 }
1816 else
1817 {
1818 add_frag (adds (&opP->disp),
1819 offs (&opP->disp),
1820 TAB (PCLEA, SZ_UNDEF));
1821 break;
1822 }
355afbcd
KR		 1823 }
1824 else
1825 {
1826 addword (0x0170);
a1c7c0f3 1827 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1828 }
1829 }
1830 else
1831 addword (0x0170);
1832 addword (nextword >> 16);
1833 }
1834 else
1835 {
1836 if (opP->reg == PC)
1837 tmpreg = 0x3A; /* 7.2 */
1838 else
1839 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1840
a1c7c0f3 1841 if (isvar (&opP->disp))
355afbcd
KR		 1842 {
1843 if (opP->reg == PC)
1844 {
a1c7c0f3 1845 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1846 }
1847 else
a1c7c0f3 1848 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1849 }
1850 }
1851 addword (nextword);
6d27d3a2 1852 break;
6d27d3a2 1853
a1c7c0f3
ILT		 1854 case POST:
1855 case PRE:
1856 case BASE:
355afbcd 1857 nextword = 0;
a1c7c0f3
ILT		 1858 baseo = get_num (&opP->disp, 80);
1859 if (opP->mode == POST || opP->mode == PRE)
1860 outro = get_num (&opP->odisp, 80);
49864cfa
KR		 1861 /* Figure out the `addressing mode'.
1862 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 1863 if (opP->reg == PC || opP->reg == ZPC)
1864 {
a1c7c0f3 1865 tmpreg = 0x3b; /* 7.3 */
355afbcd
KR		 1866 if (opP->reg == ZPC)
1867 nextword |= 0x80;
1868 }
a1c7c0f3
ILT		 1869 else if (opP->reg == 0)
1870 {
1871 nextword |= 0x80;
1872 tmpreg = 0x30; /* 6.garbage */
1873 }
1874 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
355afbcd
KR		 1875 {
1876 nextword |= 0x80;
a1c7c0f3 1877 tmpreg = 0x30 + opP->reg - ZADDR0;
355afbcd
KR		 1878 }
1879 else
1880 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1881
a1c7c0f3
ILT		 1882 siz1 = opP->disp.size;
1883 if (opP->mode == POST || opP->mode == PRE)
1884 siz2 = opP->odisp.size;
1885 else
1886 siz2 = SIZE_UNSPEC;
355afbcd
KR		 1887
1888 /* Index register stuff */
a1c7c0f3
ILT		 1889 if (opP->index.reg != 0
1890 && opP->index.reg >= DATA
1891 && opP->index.reg <= ADDR7)
355afbcd 1892 {
a1c7c0f3 1893 nextword |= (opP->index.reg - DATA) << 12;
355afbcd 1894
a1c7c0f3
ILT		 1895 if (opP->index.size == SIZE_UNSPEC
1896 || opP->index.size == SIZE_LONG)
355afbcd 1897 nextword |= 0x800;
a1c7c0f3 1898
8d20a0a8
C		 1899 if ((opP->index.scale != 1
1900 && cpu_of_arch (current_architecture) < m68020)
1901 || (opP->index.scale == 8
1902 && current_architecture == mcf5200))
a1c7c0f3 1903 {
8d20a0a8
C		 1904 opP->error =
1905 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
a1c7c0f3
ILT		 1906 }
1907
1908 switch (opP->index.scale)
355afbcd
KR		 1909 {
1910 case 1:
1911 break;
1912 case 2:
1913 nextword |= 0x200;
1914 break;
1915 case 4:
1916 nextword |= 0x400;
1917 break;
1918 case 8:
1919 nextword |= 0x600;
1920 break;
1921 default:
a1c7c0f3 1922 abort ();
355afbcd
KR		 1923 }
1924 /* IF its simple,
49864cfa 1925 GET US OUT OF HERE! */
6d27d3a2 1926
04ef74bb
KR		 1927 /* Must be INDEX, with an index register. Address
1928 register cannot be ZERO-PC, and either :b was
1929 forced, or we know it will fit. For a 68000 or
1930 68010, force this mode anyways, because the
1931 larger modes aren't supported. */
a1c7c0f3
ILT		 1932 if (opP->mode == BASE
1933 && ((opP->reg >= ADDR0
1934 && opP->reg <= ADDR7)
1935 || opP->reg == PC))
355afbcd 1936 {
a1c7c0f3
ILT		 1937 if (siz1 == SIZE_BYTE
1938 || cpu_of_arch (current_architecture) < m68020
1939 || (siz1 == SIZE_UNSPEC
1940 && ! isvar (&opP->disp)
1941 && issbyte (baseo)))
1942 {
5f8cb05e
ILT		 1943 nextword += baseo & 0xff;
1944 addword (nextword);
a1c7c0f3 1945 if (isvar (&opP->disp))
04ef74bb 1946 {
a1c7c0f3
ILT		 1947 /* Do a byte relocation. If it doesn't
1948 fit (possible on m68000) let the
1949 fixup processing complain later. */
5f8cb05e 1950 if (opP->reg == PC)
a1c7c0f3 1951 add_fix ('B', &opP->disp, 1, 1);
5f8cb05e 1952 else
a1c7c0f3 1953 add_fix ('B', &opP->disp, 0, 0);
04ef74bb 1954 }
a1c7c0f3
ILT		 1955 else if (siz1 != SIZE_BYTE)
1956 {
1957 if (siz1 != SIZE_UNSPEC)
1958 as_warn ("Forcing byte displacement");
1959 if (! issbyte (baseo))
1960 opP->error = "byte displacement out of range";
1961 }
1962
1963 break;
1964 }
1965 else if (siz1 == SIZE_UNSPEC
1966 && opP->reg == PC
1967 && isvar (&opP->disp)
a043f579
ILT		 1968 && subs (&opP->disp) == NULL
1969#ifdef OBJ_ELF
1970 /* If the displacement needs pic
1971 relocation it cannot be relaxed. */
1972 && opP->disp.pic_reloc == pic_none
1973#endif
1974 )
a1c7c0f3 1975 {
5f8cb05e
ILT		 1976 nextword += baseo & 0xff;
1977 addword (nextword);
a1c7c0f3 1978 add_frag (adds (&opP->disp), offs (&opP->disp),
5f8cb05e 1979 TAB (PCINDEX, SZ_UNDEF));
a1c7c0f3
ILT		 1980
1981 break;
5f8cb05e 1982 }
355afbcd
KR		 1983 }
1984 }
1985 else
a1c7c0f3
ILT		 1986 {
1987 nextword |= 0x40; /* No index reg */
1988 if (opP->index.reg >= ZDATA0
1989 && opP->index.reg <= ZDATA7)
1990 nextword |= (opP->index.reg - ZDATA0) << 12;
1991 else if (opP->index.reg >= ZADDR0
1992 || opP->index.reg <= ZADDR7)
1993 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1994 }
6d27d3a2 1995
49864cfa 1996 /* It isn't simple. */
a1c7c0f3
ILT		 1997
1998 if (cpu_of_arch (current_architecture) < m68020)
1999 opP->error =
2000 "invalid operand mode for this architecture; needs 68020 or higher";
2001
355afbcd 2002 nextword |= 0x100;
49864cfa
KR		 2003 /* If the guy specified a width, we assume that it is
2004 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 2005 switch (siz1)
2006 {
a1c7c0f3 2007 case SIZE_UNSPEC:
6700d36e
ILT		 2008 if (isvar (&opP->disp)
2009 ? m68k_rel32
2010 : ! issword (baseo))
355afbcd 2011 {
a1c7c0f3 2012 siz1 = SIZE_LONG;
355afbcd
KR		 2013 nextword |= 0x30;
2014 }
6700d36e 2015 else if (! isvar (&opP->disp) && baseo == 0)
355afbcd
KR		 2016 nextword |= 0x10;
2017 else
2018 {
2019 nextword |= 0x20;
a1c7c0f3 2020 siz1 = SIZE_WORD;
355afbcd
KR		 2021 }
2022 break;
a1c7c0f3
ILT		 2023 case SIZE_BYTE:
2024 as_warn (":b not permitted; defaulting to :w");
2025 /* Fall through. */
2026 case SIZE_WORD:
355afbcd
KR		 2027 nextword |= 0x20;
2028 break;
a1c7c0f3 2029 case SIZE_LONG:
355afbcd
KR		 2030 nextword |= 0x30;
2031 break;
2032 }
6d27d3a2 2033
355afbcd 2034 /* Figure out innner displacement stuff */
a1c7c0f3 2035 if (opP->mode == POST || opP->mode == PRE)
355afbcd 2036 {
8d20a0a8
C		 2037 if (cpu_of_arch (current_architecture) & cpu32)
2038 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
355afbcd
KR		 2039 switch (siz2)
2040 {
a1c7c0f3 2041 case SIZE_UNSPEC:
6700d36e
ILT		 2042 if (isvar (&opP->odisp)
2043 ? m68k_rel32
2044 : ! issword (outro))
355afbcd 2045 {
a1c7c0f3 2046 siz2 = SIZE_LONG;
355afbcd
KR		 2047 nextword |= 0x3;
2048 }
92a25e12 2049 else if (! isvar (&opP->odisp) && outro == 0)
355afbcd
KR		 2050 nextword |= 0x1;
2051 else
2052 {
2053 nextword |= 0x2;
a1c7c0f3 2054 siz2 = SIZE_WORD;
355afbcd
KR		 2055 }
2056 break;
2057 case 1:
a1c7c0f3
ILT		 2058 as_warn (":b not permitted; defaulting to :w");
2059 /* Fall through. */
355afbcd
KR		 2060 case 2:
2061 nextword |= 0x2;
2062 break;
2063 case 3:
2064 nextword |= 0x3;
2065 break;
2066 }
92a25e12
ILT		 2067 if (opP->mode == POST
2068 && (nextword & 0x40) == 0)
355afbcd 2069 nextword |= 0x04;
355afbcd
KR		 2070 }
2071 addword (nextword);
2072
a1c7c0f3 2073 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
355afbcd
KR		 2074 {
2075 if (opP->reg == PC || opP->reg == ZPC)
a1c7c0f3 2076 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
355afbcd 2077 else
a1c7c0f3 2078 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
355afbcd 2079 }
a1c7c0f3 2080 if (siz1 == SIZE_LONG)
355afbcd 2081 addword (baseo >> 16);
a1c7c0f3 2082 if (siz1 != SIZE_UNSPEC)
355afbcd
KR		 2083 addword (baseo);
2084
a1c7c0f3
ILT		 2085 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2086 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2087 if (siz2 == SIZE_LONG)
355afbcd 2088 addword (outro >> 16);
a1c7c0f3 2089 if (siz2 != SIZE_UNSPEC)
355afbcd 2090 addword (outro);
6d27d3a2 2091
355afbcd 2092 break;
6d27d3a2 2093
355afbcd 2094 case ABSL:
a1c7c0f3
ILT		 2095 nextword = get_num (&opP->disp, 80);
2096 switch (opP->disp.size)
355afbcd
KR		 2097 {
2098 default:
a1c7c0f3
ILT		 2099 abort ();
2100 case SIZE_UNSPEC:
2101 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
355afbcd
KR		 2102 {
2103 tmpreg = 0x38; /* 7.0 */
2104 addword (nextword);
2105 break;
2106 }
bcb8dff8
KR		 2107 /* Don't generate pc relative code on 68010 and
2108 68000. */
a1c7c0f3
ILT		 2109 if (isvar (&opP->disp)
2110 && !subs (&opP->disp)
2111 && adds (&opP->disp)
a043f579
ILT		 2112#ifdef OBJ_ELF
2113 /* If the displacement needs pic relocation it
2114 cannot be relaxed. */
2115 && opP->disp.pic_reloc == pic_none
2116#endif
f00f5ecd 2117 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
355afbcd 2118 && cpu_of_arch (current_architecture) >= m68020
9ad5755f 2119 && !flag_long_jumps
355afbcd
KR		 2120 && !strchr ("~%&$?", s[0]))
2121 {
2122 tmpreg = 0x3A; /* 7.2 */
a1c7c0f3
ILT		 2123 add_frag (adds (&opP->disp),
2124 offs (&opP->disp),
355afbcd
KR		 2125 TAB (PCREL, SZ_UNDEF));
2126 break;
2127 }
04ef74bb 2128 /* Fall through into long */
a1c7c0f3
ILT		 2129 case SIZE_LONG:
2130 if (isvar (&opP->disp))
2131 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 2132
2133 tmpreg = 0x39;/* 7.1 mode */
2134 addword (nextword >> 16);
2135 addword (nextword);
2136 break;
2137
a1c7c0f3
ILT		 2138 case SIZE_WORD: /* Word */
2139 if (isvar (&opP->disp))
2140 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 2141
2142 tmpreg = 0x38;/* 7.0 mode */
2143 addword (nextword);
2144 break;
2145 }
2146 break;
a1c7c0f3
ILT		 2147 case CONTROL:
2148 case FPREG:
355afbcd
KR		 2149 default:
2150 as_bad ("unknown/incorrect operand");
2151 /* abort(); */
2152 }
2153 install_gen_operand (s[1], tmpreg);
6d27d3a2 2154 break;
6d27d3a2 2155
355afbcd
KR		 2156 case '#':
2157 case '^':
2158 switch (s[1])
2159 { /* JF: I hate floating point! */
2160 case 'j':
2161 tmpreg = 70;
2162 break;
2163 case '8':
2164 tmpreg = 20;
2165 break;
2166 case 'C':
2167 tmpreg = 50;
2168 break;
2169 case '3':
2170 default:
2171 tmpreg = 80;
2172 break;
2173 }
a1c7c0f3
ILT		 2174 tmpreg = get_num (&opP->disp, tmpreg);
2175 if (isvar (&opP->disp))
2176 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 2177 switch (s[1])
2178 {
2179 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 2180 certain types of overflow.
2181 user beware! */
355afbcd
KR		 2182 if (!isbyte (tmpreg))
2183 opP->error = "out of range";
bcb8dff8 2184 insop (tmpreg, opcode);
a1c7c0f3 2185 if (isvar (&opP->disp))
d9396c16
ILT		 2186 the_ins.reloc[the_ins.nrel - 1].n =
2187 (opcode->m_codenum) * 2 + 1;
355afbcd
KR		 2188 break;
2189 case 'w':
2190 if (!isword (tmpreg))
2191 opP->error = "out of range";
bcb8dff8 2192 insop (tmpreg, opcode);
a1c7c0f3 2193 if (isvar (&opP->disp))
355afbcd
KR		 2194 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2195 break;
9e64486e
ILT		 2196 case 'W':
2197 if (!issword (tmpreg))
2198 opP->error = "out of range";
2199 insop (tmpreg, opcode);
2200 if (isvar (&opP->disp))
2201 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2202 break;
355afbcd 2203 case 'l':
bcb8dff8
KR		 2204 /* Because of the way insop works, we put these two out
2205 backwards. */
2206 insop (tmpreg, opcode);
2207 insop (tmpreg >> 16, opcode);
a1c7c0f3 2208 if (isvar (&opP->disp))
355afbcd
KR		 2209 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2210 break;
2211 case '3':
2212 tmpreg &= 0xFF;
2213 case '8':
2214 case 'C':
2215 install_operand (s[1], tmpreg);
2216 break;
2217 default:
a1c7c0f3 2218 abort ();
355afbcd
KR		 2219 }
2220 break;
6d27d3a2 2221
355afbcd
KR		 2222 case '+':
2223 case '-':
2224 case 'A':
2225 case 'a':
2226 install_operand (s[1], opP->reg - ADDR);
2227 break;
6d27d3a2 2228
355afbcd 2229 case 'B':
a1c7c0f3 2230 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2231 switch (s[1])
2232 {
2233 case 'B':
b4ec75e0
ILT		 2234 /* The pc_fix argument winds up in fx_pcrel_adjust,
2235 which is a char, and may therefore be unsigned. We
2236 want to pass -1, but we pass 64 instead, and convert
2237 back in md_pcrel_from. */
2238 add_fix ('B', &opP->disp, 1, 64);
355afbcd
KR		 2239 break;
2240 case 'W':
a1c7c0f3 2241 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2242 addword (0);
2243 break;
2244 case 'L':
2245 long_branch:
a1c7c0f3 2246 if (cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 2247 as_warn ("Can't use long branches on 68000/68010");
2248 the_ins.opcode[the_ins.numo - 1] |= 0xff;
a1c7c0f3 2249 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2250 addword (0);
2251 addword (0);
2252 break;
2253 case 'g':
a1c7c0f3 2254 if (subs (&opP->disp)) /* We can't relax it */
355afbcd 2255 goto long_branch;
6d27d3a2 2256
a043f579
ILT		 2257#ifdef OBJ_ELF
2258 /* If the displacement needs pic relocation it cannot be
2259 relaxed. */
2260 if (opP->disp.pic_reloc != pic_none)
2261 goto long_branch;
2262#endif
2263
a1c7c0f3
ILT		 2264 /* This could either be a symbol, or an absolute
2265 address. No matter, the frag hacking will finger it
2266 out. Not quite: it can't switch from BRANCH to
2267 BCC68000 for the case where opnd is absolute (it
2268 needs to use the 68000 hack since no conditional abs
2269 jumps). */
b79de3a1 2270 if (((cpu_of_arch (current_architecture) < m68020)
a1c7c0f3 2271 || (0 == adds (&opP->disp)))
355afbcd
KR		 2272 && (the_ins.opcode[0] >= 0x6200)
2273 && (the_ins.opcode[0] <= 0x6f00))
a1c7c0f3
ILT		 2274 add_frag (adds (&opP->disp), offs (&opP->disp),
2275 TAB (BCC68000, SZ_UNDEF));
355afbcd 2276 else
a1c7c0f3
ILT		 2277 add_frag (adds (&opP->disp), offs (&opP->disp),
2278 TAB (ABRANCH, SZ_UNDEF));
355afbcd
KR		 2279 break;
2280 case 'w':
a1c7c0f3 2281 if (isvar (&opP->disp))
355afbcd 2282 {
49864cfa 2283#if 1
355afbcd
KR		 2284 /* check for DBcc instruction */
2285 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2286 {
2287 /* size varies if patch */
2288 /* needed for long form */
a1c7c0f3 2289 add_frag (adds (&opP->disp), offs (&opP->disp),
b79de3a1 2290 TAB (DBCC, SZ_UNDEF));
355afbcd
KR		 2291 break;
2292 }
49864cfa 2293#endif
a1c7c0f3 2294 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2295 }
2296 addword (0);
2297 break;
2298 case 'C': /* Fixed size LONG coproc branches */
a1c7c0f3 2299 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2300 addword (0);
2301 addword (0);
2302 break;
2303 case 'c': /* Var size Coprocesssor branches */
a1c7c0f3 2304 if (subs (&opP->disp))
355afbcd 2305 {
a1c7c0f3 2306 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2307 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2308 }
a1c7c0f3
ILT		 2309 else if (adds (&opP->disp))
2310 add_frag (adds (&opP->disp), offs (&opP->disp),
2311 TAB (FBRANCH, SZ_UNDEF));
355afbcd
KR		 2312 else
2313 {
a1c7c0f3
ILT		 2314 /* add_frag((symbolS *) 0, offs(&opP->disp),
2315 TAB(FBRANCH,SHORT)); */
355afbcd 2316 the_ins.opcode[the_ins.numo - 1] |= 0x40;
a1c7c0f3 2317 add_fix ('l', &opP->disp, 1, 0);
5f8cb05e 2318 addword (0);
355afbcd 2319 addword (0);
355afbcd
KR		 2320 }
2321 break;
2322 default:
a1c7c0f3 2323 abort ();
355afbcd
KR		 2324 }
2325 break;
6d27d3a2 2326
355afbcd
KR		 2327 case 'C': /* Ignore it */
2328 break;
6d27d3a2 2329
355afbcd 2330 case 'd': /* JF this is a kludge */
a1c7c0f3
ILT		 2331 install_operand ('s', opP->reg - ADDR);
2332 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2333 if (!issword (tmpreg))
2334 {
2335 as_warn ("Expression out of range, using 0");
2336 tmpreg = 0;
2337 }
2338 addword (tmpreg);
2339 break;
6d27d3a2 2340
355afbcd
KR		 2341 case 'D':
2342 install_operand (s[1], opP->reg - DATA);
2343 break;
6d27d3a2 2344
355afbcd 2345 case 'F':
a1c7c0f3 2346 install_operand (s[1], opP->reg - FP0);
355afbcd 2347 break;
6d27d3a2 2348
355afbcd 2349 case 'I':
27a53b88 2350 tmpreg = opP->reg - COP0;
355afbcd
KR		 2351 install_operand (s[1], tmpreg);
2352 break;
6d27d3a2 2353
355afbcd
KR		 2354 case 'J': /* JF foo */
2355 switch (opP->reg)
2356 {
2357 case SFC:
2358 tmpreg = 0x000;
2359 break;
2360 case DFC:
2361 tmpreg = 0x001;
2362 break;
2363 case CACR:
2364 tmpreg = 0x002;
2365 break;
2366 case TC:
2367 tmpreg = 0x003;
2368 break;
2369 case ITT0:
2370 tmpreg = 0x004;
2371 break;
2372 case ITT1:
2373 tmpreg = 0x005;
2374 break;
2375 case DTT0:
2376 tmpreg = 0x006;
2377 break;
2378 case DTT1:
2379 tmpreg = 0x007;
2380 break;
9ad5755f
KR		 2381 case BUSCR:
2382 tmpreg = 0x008;
2383 break;
6d27d3a2 2384
355afbcd
KR		 2385 case USP:
2386 tmpreg = 0x800;
2387 break;
2388 case VBR:
2389 tmpreg = 0x801;
2390 break;
2391 case CAAR:
2392 tmpreg = 0x802;
2393 break;
2394 case MSP:
2395 tmpreg = 0x803;
2396 break;
2397 case ISP:
2398 tmpreg = 0x804;
2399 break;
2400 case MMUSR:
2401 tmpreg = 0x805;
2402 break;
2403 case URP:
2404 tmpreg = 0x806;
2405 break;
2406 case SRP:
2407 tmpreg = 0x807;
2408 break;
9ad5755f
KR		 2409 case PCR:
2410 tmpreg = 0x808;
2411 break;
8d20a0a8
C		 2412 case ROMBAR:
2413 tmpreg = 0xC00;
2414 break;
2415 case RAMBAR0:
2416 tmpreg = 0xC04;
2417 break;
2418 case RAMBAR1:
2419 tmpreg = 0xC05;
2420 break;
2421 case MBAR:
2422 tmpreg = 0xC0F;
2423 break;
355afbcd 2424 default:
a1c7c0f3 2425 abort ();
355afbcd
KR		 2426 }
2427 install_operand (s[1], tmpreg);
2428 break;
6d27d3a2 2429
355afbcd 2430 case 'k':
a1c7c0f3 2431 tmpreg = get_num (&opP->disp, 55);
355afbcd
KR		 2432 install_operand (s[1], tmpreg & 0x7f);
2433 break;
6d27d3a2 2434
355afbcd 2435 case 'l':
a1c7c0f3 2436 tmpreg = opP->mask;
355afbcd
KR		 2437 if (s[1] == 'w')
2438 {
2439 if (tmpreg & 0x7FF0000)
2440 as_bad ("Floating point register in register list");
bcb8dff8 2441 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 2442 }
2443 else
2444 {
2445 if (tmpreg & 0x700FFFF)
2446 as_bad ("Wrong register in floating-point reglist");
2447 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2448 }
2449 break;
6d27d3a2 2450
355afbcd 2451 case 'L':
a1c7c0f3 2452 tmpreg = opP->mask;
355afbcd
KR		 2453 if (s[1] == 'w')
2454 {
2455 if (tmpreg & 0x7FF0000)
2456 as_bad ("Floating point register in register list");
bcb8dff8 2457 insop (tmpreg, opcode);
355afbcd
KR		 2458 }
2459 else if (s[1] == '8')
2460 {
2461 if (tmpreg & 0x0FFFFFF)
2462 as_bad ("incorrect register in reglist");
2463 install_operand (s[1], tmpreg >> 24);
2464 }
2465 else
2466 {
2467 if (tmpreg & 0x700FFFF)
2468 as_bad ("wrong register in floating-point reglist");
2469 else
2470 install_operand (s[1], tmpreg >> 16);
2471 }
2472 break;
6d27d3a2 2473
355afbcd 2474 case 'M':
a1c7c0f3 2475 install_operand (s[1], get_num (&opP->disp, 60));
355afbcd 2476 break;
6d27d3a2 2477
355afbcd 2478 case 'O':
a1c7c0f3
ILT		 2479 tmpreg = ((opP->mode == DREG)
2480 ? 0x20 + opP->reg - DATA
2481 : (get_num (&opP->disp, 40) & 0x1F));
355afbcd
KR		 2482 install_operand (s[1], tmpreg);
2483 break;
6d27d3a2 2484
355afbcd 2485 case 'Q':
a1c7c0f3 2486 tmpreg = get_num (&opP->disp, 10);
355afbcd
KR		 2487 if (tmpreg == 8)
2488 tmpreg = 0;
2489 install_operand (s[1], tmpreg);
2490 break;
2491
2492 case 'R':
a1c7c0f3
ILT		 2493 /* This depends on the fact that ADDR registers are eight
2494 more than their corresponding DATA regs, so the result
2495 will have the ADDR_REG bit set */
355afbcd
KR		 2496 install_operand (s[1], opP->reg - DATA);
2497 break;
6d27d3a2 2498
a1c7c0f3
ILT		 2499 case 'r':
2500 if (opP->mode == AINDR)
2501 install_operand (s[1], opP->reg - DATA);
2502 else
2503 install_operand (s[1], opP->index.reg - DATA);
2504 break;
2505
355afbcd
KR		 2506 case 's':
2507 if (opP->reg == FPI)
2508 tmpreg = 0x1;
2509 else if (opP->reg == FPS)
2510 tmpreg = 0x2;
2511 else if (opP->reg == FPC)
2512 tmpreg = 0x4;
2513 else
a1c7c0f3 2514 abort ();
355afbcd
KR		 2515 install_operand (s[1], tmpreg);
2516 break;
6d27d3a2 2517
355afbcd
KR		 2518 case 'S': /* Ignore it */
2519 break;
6d27d3a2 2520
355afbcd 2521 case 'T':
a1c7c0f3 2522 install_operand (s[1], get_num (&opP->disp, 30));
355afbcd 2523 break;
6d27d3a2 2524
355afbcd
KR		 2525 case 'U': /* Ignore it */
2526 break;
6d27d3a2 2527
355afbcd
KR		 2528 case 'c':
2529 switch (opP->reg)
2530 {
2531 case NC:
2532 tmpreg = 0;
2533 break;
2534 case DC:
2535 tmpreg = 1;
2536 break;
2537 case IC:
2538 tmpreg = 2;
2539 break;
2540 case BC:
2541 tmpreg = 3;
2542 break;
2543 default:
2544 as_fatal ("failed sanity check");
2545 } /* switch on cache token */
2546 install_operand (s[1], tmpreg);
2547 break;
a39116f1 2548#ifndef NO_68851
355afbcd
KR		 2549 /* JF: These are out of order, I fear. */
2550 case 'f':
2551 switch (opP->reg)
2552 {
2553 case SFC:
2554 tmpreg = 0;
2555 break;
2556 case DFC:
2557 tmpreg = 1;
2558 break;
2559 default:
a1c7c0f3 2560 abort ();
355afbcd
KR		 2561 }
2562 install_operand (s[1], tmpreg);
2563 break;
6d27d3a2 2564
9adcd781
ILT		 2565 case '0':
2566 case '1':
2567 case '2':
355afbcd
KR		 2568 switch (opP->reg)
2569 {
2570 case TC:
2571 tmpreg = 0;
2572 break;
2573 case CAL:
2574 tmpreg = 4;
2575 break;
2576 case VAL:
2577 tmpreg = 5;
2578 break;
2579 case SCC:
2580 tmpreg = 6;
2581 break;
2582 case AC:
2583 tmpreg = 7;
2584 break;
2585 default:
a1c7c0f3 2586 abort ();
355afbcd
KR		 2587 }
2588 install_operand (s[1], tmpreg);
2589 break;
6d27d3a2 2590
355afbcd
KR		 2591 case 'V':
2592 if (opP->reg == VAL)
2593 break;
a1c7c0f3 2594 abort ();
6d27d3a2 2595
355afbcd
KR		 2596 case 'W':
2597 switch (opP->reg)
2598 {
355afbcd
KR		 2599 case DRP:
2600 tmpreg = 1;
2601 break;
2602 case SRP:
2603 tmpreg = 2;
2604 break;
2605 case CRP:
2606 tmpreg = 3;
2607 break;
2608 default:
a1c7c0f3 2609 abort ();
355afbcd
KR		 2610 }
2611 install_operand (s[1], tmpreg);
2612 break;
6d27d3a2 2613
355afbcd
KR		 2614 case 'X':
2615 switch (opP->reg)
2616 {
2617 case BAD:
2618 case BAD + 1:
2619 case BAD + 2:
2620 case BAD + 3:
2621 case BAD + 4:
2622 case BAD + 5:
2623 case BAD + 6:
2624 case BAD + 7:
2625 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2626 break;
6d27d3a2 2627
355afbcd
KR		 2628 case BAC:
2629 case BAC + 1:
2630 case BAC + 2:
2631 case BAC + 3:
2632 case BAC + 4:
2633 case BAC + 5:
2634 case BAC + 6:
2635 case BAC + 7:
2636 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2637 break;
6d27d3a2 2638
355afbcd 2639 default:
a1c7c0f3 2640 abort ();
355afbcd
KR		 2641 }
2642 install_operand (s[1], tmpreg);
2643 break;
2644 case 'Y':
2645 know (opP->reg == PSR);
2646 break;
2647 case 'Z':
2648 know (opP->reg == PCSR);
2649 break;
f8701a3f 2650#endif /* m68851 */
355afbcd
KR		 2651 case '3':
2652 switch (opP->reg)
2653 {
2654 case TT0:
2655 tmpreg = 2;
2656 break;
2657 case TT1:
2658 tmpreg = 3;
2659 break;
2660 default:
a1c7c0f3 2661 abort ();
355afbcd
KR		 2662 }
2663 install_operand (s[1], tmpreg);
2664 break;
2665 case 't':
a1c7c0f3 2666 tmpreg = get_num (&opP->disp, 20);
355afbcd 2667 install_operand (s[1], tmpreg);
4134a793 2668 break;
a1c7c0f3
ILT		 2669 case '_': /* used only for move16 absolute 32-bit address */
2670 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2671 addword (tmpreg >> 16);
2672 addword (tmpreg & 0xFFFF);
4134a793
KR		 2673 break;
2674 default:
a1c7c0f3 2675 abort ();
4134a793 2676 }
6d27d3a2 2677 }
3ad9ec6a 2678
6d27d3a2
KR		 2679 /* By the time whe get here (FINALLY) the_ins contains the complete
2680 instruction, ready to be emitted. . . */
a1c7c0f3 2681}
fecd2382 2682
355afbcd
KR		 2683static int
2684reverse_16_bits (in)
2685 int in;
fecd2382 2686{
355afbcd
KR		 2687 int out = 0;
2688 int n;
6d27d3a2 2689
355afbcd
KR		 2690 static int mask[16] =
2691 {
2692 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2693 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2694 };
2695 for (n = 0; n < 16; n++)
2696 {
2697 if (in & mask[n])
2698 out |= mask[15 - n];
2699 }
2700 return out;
2701} /* reverse_16_bits() */
fecd2382 2702
355afbcd
KR		 2703static int
2704reverse_8_bits (in)
2705 int in;
fecd2382 2706{
355afbcd
KR		 2707 int out = 0;
2708 int n;
6d27d3a2 2709
355afbcd
KR		 2710 static int mask[8] =
2711 {
2712 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2713 };
6d27d3a2 2714
355afbcd
KR		 2715 for (n = 0; n < 8; n++)
2716 {
2717 if (in & mask[n])
2718 out |= mask[7 - n];
2719 }
2720 return out;
2721} /* reverse_8_bits() */
fecd2382 2722
04ef74bb
KR		 2723/* Cause an extra frag to be generated here, inserting up to 10 bytes
2724 (that value is chosen in the frag_var call in md_assemble). TYPE
2725 is the subtype of the frag to be generated; its primary type is
2726 rs_machine_dependent.
2727
2728 The TYPE parameter is also used by md_convert_frag_1 and
2729 md_estimate_size_before_relax. The appropriate type of fixup will
2730 be emitted by md_convert_frag_1.
2731
2732 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355afbcd
KR		 2733static void
2734install_operand (mode, val)
2735 int mode;
2736 int val;
fecd2382 2737{
355afbcd
KR		 2738 switch (mode)
2739 {
2740 case 's':
2741 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2742 break;
2743 case 'd':
2744 the_ins.opcode[0] |= val << 9;
2745 break;
2746 case '1':
2747 the_ins.opcode[1] |= val << 12;
2748 break;
2749 case '2':
2750 the_ins.opcode[1] |= val << 6;
2751 break;
2752 case '3':
2753 the_ins.opcode[1] |= val;
2754 break;
2755 case '4':
2756 the_ins.opcode[2] |= val << 12;
2757 break;
2758 case '5':
2759 the_ins.opcode[2] |= val << 6;
2760 break;
2761 case '6':
bcb8dff8
KR		 2762 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2763 three words long! */
355afbcd
KR		 2764 the_ins.numo++;
2765 the_ins.opcode[2] |= val;
2766 break;
2767 case '7':
2768 the_ins.opcode[1] |= val << 7;
2769 break;
2770 case '8':
2771 the_ins.opcode[1] |= val << 10;
2772 break;
f8701a3f 2773#ifndef NO_68851
355afbcd
KR		 2774 case '9':
2775 the_ins.opcode[1] |= val << 5;
2776 break;
f8701a3f 2777#endif
6d27d3a2 2778
355afbcd
KR		 2779 case 't':
2780 the_ins.opcode[1] |= (val << 10) | (val << 7);
2781 break;
2782 case 'D':
2783 the_ins.opcode[1] |= (val << 12) | val;
2784 break;
2785 case 'g':
2786 the_ins.opcode[0] |= val = 0xff;
2787 break;
2788 case 'i':
2789 the_ins.opcode[0] |= val << 9;
2790 break;
2791 case 'C':
2792 the_ins.opcode[1] |= val;
2793 break;
2794 case 'j':
2795 the_ins.opcode[1] |= val;
2796 the_ins.numo++; /* What a hack */
2797 break;
2798 case 'k':
2799 the_ins.opcode[1] |= val << 4;
2800 break;
2801 case 'b':
2802 case 'w':
9e64486e 2803 case 'W':
355afbcd
KR		 2804 case 'l':
2805 break;
2806 case 'e':
2807 the_ins.opcode[0] |= (val << 6);
2808 break;
2809 case 'L':
2810 the_ins.opcode[1] = (val >> 16);
2811 the_ins.opcode[2] = val & 0xffff;
2812 break;
2813 case 'c':
2814 default:
2815 as_fatal ("failed sanity check.");
2816 }
2817} /* install_operand() */
fecd2382 2818
355afbcd
KR		 2819static void
2820install_gen_operand (mode, val)
2821 int mode;
2822 int val;
fecd2382 2823{
355afbcd
KR		 2824 switch (mode)
2825 {
2826 case 's':
2827 the_ins.opcode[0] |= val;
2828 break;
2829 case 'd':
2830 /* This is a kludge!!! */
2831 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2832 break;
2833 case 'b':
2834 case 'w':
2835 case 'l':
2836 case 'f':
2837 case 'F':
2838 case 'x':
2839 case 'p':
2840 the_ins.opcode[0] |= val;
2841 break;
2842 /* more stuff goes here */
2843 default:
2844 as_fatal ("failed sanity check.");
2845 }
2846} /* install_gen_operand() */
fecd2382 2847
7c15cbe8
RP		 2848/*
2849 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2850 * then deal with the bitfield hack.
2851 */
2852
355afbcd
KR		 2853static char *
2854crack_operand (str, opP)
2855 register char *str;
2856 register struct m68k_op *opP;
fecd2382 2857{
355afbcd
KR		 2858 register int parens;
2859 register int c;
2860 register char *beg_str;
4026c122 2861 int inquote = 0;
6d27d3a2 2862
355afbcd
KR		 2863 if (!str)
2864 {
2865 return str;
2866 }
2867 beg_str = str;
4026c122 2868 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
355afbcd 2869 {
4026c122 2870 if (! inquote)
355afbcd 2871 {
4026c122
ILT		 2872 if (*str == '(')
2873 parens++;
2874 else if (*str == ')')
2875 {
2876 if (!parens)
2877 { /* ERROR */
2878 opP->error = "Extra )";
2879 return str;
2880 }
2881 --parens;
355afbcd 2882 }
f8701a3f 2883 }
4026c122
ILT		 2884 if (flag_mri && *str == '\'')
2885 inquote = ! inquote;
355afbcd
KR		 2886 }
2887 if (!*str && parens)
2888 { /* ERROR */
2889 opP->error = "Missing )";
2890 return str;
2891 }
2892 c = *str;
2893 *str = '\0';
a1c7c0f3 2894 if (m68k_ip_op (beg_str, opP) != 0)
355afbcd
KR		 2895 {
2896 *str = c;
2897 return str;
2898 }
2899 *str = c;
2900 if (c == '}')
2901 c = *++str; /* JF bitfield hack */
2902 if (c)
2903 {
2904 c = *++str;
2905 if (!c)
2906 as_bad ("Missing operand");
2907 }
2908 return str;
fecd2382
RP		 2909}
2910
fecd2382 2911/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 2912 machine dependent instruction. This function is supposed to emit
fecd2382 2913 the frags/bytes it assembles to.
a39116f1 2914 */
a933d598
SC		 2915
2916void
355afbcd
KR		 2917insert_reg (regname, regnum)
2918 char *regname;
2919 int regnum;
a933d598
SC		 2920{
2921 char buf[100];
2922 int i;
355afbcd
KR		 2923
2924#ifdef REGISTER_PREFIX
82489ea0
KR		 2925 if (!flag_reg_prefix_optional)
2926 {
2927 buf[0] = REGISTER_PREFIX;
2928 strcpy (buf + 1, regname);
2929 regname = buf;
2930 }
355afbcd
KR		 2931#endif
2932
82489ea0
KR		 2933 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2934 &zero_address_frag));
a933d598
SC		 2935
2936 for (i = 0; regname[i]; i++)
355afbcd 2937 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 2938 buf[i] = '\0';
6d27d3a2 2939
82489ea0
KR		 2940 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2941 &zero_address_frag));
a933d598
SC		 2942}
2943
49864cfa 2944struct init_entry
355afbcd 2945 {
bcb8dff8 2946 const char *name;
355afbcd 2947 int number;
49864cfa 2948 };
355afbcd 2949
bcb8dff8 2950static const struct init_entry init_table[] =
355afbcd 2951{
bcb8dff8
KR		 2952 { "d0", DATA0 },
2953 { "d1", DATA1 },
2954 { "d2", DATA2 },
2955 { "d3", DATA3 },
2956 { "d4", DATA4 },
2957 { "d5", DATA5 },
2958 { "d6", DATA6 },
2959 { "d7", DATA7 },
2960 { "a0", ADDR0 },
2961 { "a1", ADDR1 },
2962 { "a2", ADDR2 },
2963 { "a3", ADDR3 },
2964 { "a4", ADDR4 },
2965 { "a5", ADDR5 },
2966 { "a6", ADDR6 },
2967 { "fp", ADDR6 },
2968 { "a7", ADDR7 },
2969 { "sp", ADDR7 },
a1c7c0f3 2970 { "ssp", ADDR7 },
bcb8dff8
KR		 2971 { "fp0", FP0 },
2972 { "fp1", FP1 },
2973 { "fp2", FP2 },
2974 { "fp3", FP3 },
2975 { "fp4", FP4 },
2976 { "fp5", FP5 },
2977 { "fp6", FP6 },
2978 { "fp7", FP7 },
2979 { "fpi", FPI },
2980 { "fpiar", FPI },
2981 { "fpc", FPI },
2982 { "fps", FPS },
2983 { "fpsr", FPS },
2984 { "fpc", FPC },
2985 { "fpcr", FPC },
064ba683
ILT		 2986 { "control", FPC },
2987 { "status", FPS },
2988 { "iaddr", FPI },
bcb8dff8
KR		 2989
2990 { "cop0", COP0 },
2991 { "cop1", COP1 },
2992 { "cop2", COP2 },
2993 { "cop3", COP3 },
2994 { "cop4", COP4 },
2995 { "cop5", COP5 },
2996 { "cop6", COP6 },
2997 { "cop7", COP7 },
2998 { "pc", PC },
2999 { "zpc", ZPC },
3000 { "sr", SR },
3001
3002 { "ccr", CCR },
3003 { "cc", CCR },
3004
8d20a0a8
C		 3005 /* control registers */
3006 { "sfc", SFC }, /* Source Function Code */
064ba683 3007 { "sfcr", SFC },
8d20a0a8 3008 { "dfc", DFC }, /* Destination Function Code */
064ba683 3009 { "dfcr", DFC },
8d20a0a8
C		 3010 { "cacr", CACR }, /* Cache Control Register */
3011 { "caar", CAAR }, /* Cache Address Register */
3012
3013 { "usp", USP }, /* User Stack Pointer */
3014 { "vbr", VBR }, /* Vector Base Register */
3015 { "msp", MSP }, /* Master Stack Pointer */
3016 { "isp", ISP }, /* Interrupt Stack Pointer */
3017
3018 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3019 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3020 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3021 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3022
3023 /* 68ec040 versions of same */
3024 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3025 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3026 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3027 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3028
3029 /* mcf5200 versions of same */
3030 { "acr2", ITT0 }, /* Access Control Unit 2 */
3031 { "acr3", ITT1 }, /* Access Control Unit 3 */
3032 { "acr0", DTT0 }, /* Access Control Unit 0 */
3033 { "acr1", DTT1 }, /* Access Control Unit 1 */
3034
3035 { "tc", TC }, /* MMU Translation Control Register */
3036 { "tcr", TC },
3037
3038 { "mmusr", MMUSR }, /* MMU Status Register */
3039 { "srp", SRP }, /* User Root Pointer */
3040 { "urp", URP }, /* Supervisor Root Pointer */
3041
9ad5755f
KR		 3042 { "buscr", BUSCR },
3043 { "pcr", PCR },
bcb8dff8 3044
8d20a0a8
C		 3045 { "rombar", ROMBAR }, /* ROM Base Address Register */
3046 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3047 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3048 { "mbar", MBAR }, /* Module Base Address Register */
3049 /* end of control registers */
3050
bcb8dff8
KR		 3051 { "ac", AC },
3052 { "bc", BC },
3053 { "cal", CAL },
3054 { "crp", CRP },
3055 { "drp", DRP },
3056 { "pcsr", PCSR },
3057 { "psr", PSR },
3058 { "scc", SCC },
3059 { "val", VAL },
3060 { "bad0", BAD0 },
3061 { "bad1", BAD1 },
3062 { "bad2", BAD2 },
3063 { "bad3", BAD3 },
3064 { "bad4", BAD4 },
3065 { "bad5", BAD5 },
3066 { "bad6", BAD6 },
3067 { "bad7", BAD7 },
3068 { "bac0", BAC0 },
3069 { "bac1", BAC1 },
3070 { "bac2", BAC2 },
3071 { "bac3", BAC3 },
3072 { "bac4", BAC4 },
3073 { "bac5", BAC5 },
3074 { "bac6", BAC6 },
3075 { "bac7", BAC7 },
3076
3077 { "ic", IC },
3078 { "dc", DC },
3079 { "nc", NC },
3080
3081 { "tt0", TT0 },
3082 { "tt1", TT1 },
4134a793 3083 /* 68ec030 versions of same */
bcb8dff8
KR		 3084 { "ac0", TT0 },
3085 { "ac1", TT1 },
4134a793 3086 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 3087 { "acusr", PSR },
a933d598 3088
a1c7c0f3
ILT		 3089 /* Suppressed data and address registers. */
3090 { "zd0", ZDATA0 },
3091 { "zd1", ZDATA1 },
3092 { "zd2", ZDATA2 },
3093 { "zd3", ZDATA3 },
3094 { "zd4", ZDATA4 },
3095 { "zd5", ZDATA5 },
3096 { "zd6", ZDATA6 },
3097 { "zd7", ZDATA7 },
3098 { "za0", ZADDR0 },
3099 { "za1", ZADDR1 },
3100 { "za2", ZADDR2 },
3101 { "za3", ZADDR3 },
3102 { "za4", ZADDR4 },
3103 { "za5", ZADDR5 },
3104 { "za6", ZADDR6 },
3105 { "za7", ZADDR7 },
3106
bcb8dff8 3107 { 0, 0 }
a933d598
SC		 3108};
3109
a933d598 3110void
355afbcd 3111init_regtable ()
a933d598
SC		 3112{
3113 int i;
6d27d3a2 3114 for (i = 0; init_table[i].name; i++)
355afbcd 3115 insert_reg (init_table[i].name, init_table[i].number);
a933d598 3116}
6d27d3a2 3117
df3768fb 3118static int no_68851, no_68881;
a933d598 3119
dff60b7d
ILT		 3120#ifdef OBJ_AOUT
3121/* a.out machine type. Default to 68020. */
3122int m68k_aout_machtype = 2;
3123#endif
3124
fecd2382 3125void
355afbcd 3126md_assemble (str)
6d27d3a2 3127 char *str;
fecd2382 3128{
a1c7c0f3 3129 const char *er;
355afbcd
KR		 3130 short *fromP;
3131 char *toP = NULL;
3132 int m, n = 0;
3133 char *to_beg_P;
3134 int shorts_this_frag;
5f8cb05e 3135 fixS *fixP;
6d27d3a2 3136
4026c122
ILT		 3137 /* In MRI mode, the instruction and operands are separated by a
3138 space. Anything following the operands is a comment. The label
3139 has already been removed. */
3140 if (flag_mri)
3141 {
3142 char *s;
3143 int fields = 0;
3144 int infield = 0;
3145 int inquote = 0;
3146
3147 for (s = str; *s != '\0'; s++)
3148 {
3149 if ((*s == ' ' || *s == '\t') && ! inquote)
3150 {
3151 if (infield)
3152 {
3153 ++fields;
3154 if (fields >= 2)
3155 {
3156 *s = '\0';
3157 break;
3158 }
3159 infield = 0;
3160 }
3161 }
3162 else
3163 {
3164 if (! infield)
3165 infield = 1;
3166 if (*s == '\'')
3167 inquote = ! inquote;
3168 }
3169 }
3170 }
3171
e284846a 3172 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 3173 m68k_ip (str);
3174 er = the_ins.error;
3175 if (!er)
3176 {
a1c7c0f3 3177 for (n = 0; n < the_ins.numargs; n++)
355afbcd
KR		 3178 if (the_ins.operands[n].error)
3179 {
3180 er = the_ins.operands[n].error;
3181 break;
3182 }
3183 }
3184 if (er)
3185 {
3186 as_bad ("%s -- statement `%s' ignored", er, str);
3187 return;
3188 }
6d27d3a2 3189
355afbcd 3190 if (the_ins.nfrag == 0)
49864cfa
KR		 3191 {
3192 /* No frag hacking involved; just put it out */
355afbcd
KR		 3193 toP = frag_more (2 * the_ins.numo);
3194 fromP = &the_ins.opcode[0];
3195 for (m = the_ins.numo; m; --m)
3196 {
3197 md_number_to_chars (toP, (long) (*fromP), 2);
3198 toP += 2;
3199 fromP++;
f8701a3f 3200 }
355afbcd
KR		 3201 /* put out symbol-dependent info */
3202 for (m = 0; m < the_ins.nrel; m++)
3203 {
3204 switch (the_ins.reloc[m].wid)
3205 {
3206 case 'B':
3207 n = 1;
3208 break;
3209 case 'b':
3210 n = 1;
3211 break;
3212 case '3':
3213 n = 2;
3214 break;
3215 case 'w':
3216 n = 2;
3217 break;
3218 case 'l':
3219 n = 4;
3220 break;
3221 default:
49864cfa
KR		 3222 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3223 the_ins.reloc[m].wid);
355afbcd 3224 }
6d27d3a2 3225
5f8cb05e
ILT		 3226 fixP = fix_new_exp (frag_now,
3227 ((toP - frag_now->fr_literal)
3228 - the_ins.numo * 2 + the_ins.reloc[m].n),
3229 n,
3230 &the_ins.reloc[m].exp,
3231 the_ins.reloc[m].pcrel,
a043f579
ILT		 3232 get_reloc_code (n, the_ins.reloc[m].pcrel,
3233 the_ins.reloc[m].pic_reloc));
5f8cb05e 3234 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
f8701a3f 3235 }
355afbcd
KR		 3236 return;
3237 }
3238
3239 /* There's some frag hacking */
3240 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3241 {
3242 int wid;
3243
3244 if (n == 0)
3245 wid = 2 * the_ins.fragb[n].fragoff;
3246 else
3247 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3248 toP = frag_more (wid);
3249 to_beg_P = toP;
3250 shorts_this_frag = 0;
3251 for (m = wid / 2; m; --m)
3252 {
3253 md_number_to_chars (toP, (long) (*fromP), 2);
3254 toP += 2;
3255 fromP++;
3256 shorts_this_frag++;
3257 }
3258 for (m = 0; m < the_ins.nrel; m++)
3259 {
49864cfa 3260 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 3261 {
49864cfa 3262 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 3263 break;
3264 }
3265 wid = the_ins.reloc[m].wid;
3266 if (wid == 0)
3267 continue;
3268 the_ins.reloc[m].wid = 0;
3269 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3270
5f8cb05e
ILT		 3271 fixP = fix_new_exp (frag_now,
3272 ((toP - frag_now->fr_literal)
3273 - the_ins.numo * 2 + the_ins.reloc[m].n),
3274 wid,
3275 &the_ins.reloc[m].exp,
3276 the_ins.reloc[m].pcrel,
a043f579
ILT		 3277 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3278 the_ins.reloc[m].pic_reloc));
5f8cb05e 3279 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
fecd2382 3280 }
49864cfa
KR		 3281 (void) frag_var (rs_machine_dependent, 10, 0,
3282 (relax_substateT) (the_ins.fragb[n].fragty),
3283 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 3284 }
3285 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3286 shorts_this_frag = 0;
3287 if (n)
3288 {
3289 toP = frag_more (n * sizeof (short));
3290 while (n--)
3291 {
3292 md_number_to_chars (toP, (long) (*fromP), 2);
3293 toP += 2;
3294 fromP++;
3295 shorts_this_frag++;
fecd2382 3296 }
355afbcd
KR		 3297 }
3298 for (m = 0; m < the_ins.nrel; m++)
3299 {
3300 int wid;
3301
3302 wid = the_ins.reloc[m].wid;
3303 if (wid == 0)
3304 continue;
3305 the_ins.reloc[m].wid = 0;
3306 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3307
5f8cb05e
ILT		 3308 fixP = fix_new_exp (frag_now,
3309 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3310 - shorts_this_frag * 2),
3311 wid,
3312 &the_ins.reloc[m].exp,
3313 the_ins.reloc[m].pcrel,
a043f579
ILT		 3314 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3315 the_ins.reloc[m].pic_reloc));
5f8cb05e 3316 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
355afbcd 3317 }
fecd2382
RP		 3318}
3319
fecd2382 3320void
355afbcd 3321md_begin ()
fecd2382 3322{
355afbcd 3323 /*
e284846a
KR		 3324 * md_begin -- set up hash tables with 68000 instructions.
3325 * similar to what the vax assembler does. ---phr
3326 */
355afbcd 3327 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 3328 a copy of it at runtime, adding in the information we want but isn't
3329 there. I think it'd be better to have an awk script hack the table
3330 at compile time. Or even just xstr the table and use it as-is. But
3331 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3332 names. */
6d27d3a2 3333
b79de3a1 3334 register const struct m68k_opcode *ins;
355afbcd 3335 register struct m68k_incant *hack, *slak;
bcb8dff8 3336 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 3337 register unsigned int i;
3338 register char c;
3339
064ba683 3340 if (flag_mri)
6700d36e
ILT		 3341 {
3342 flag_reg_prefix_optional = 1;
3343 m68k_abspcadd = 1;
3344 m68k_rel32 = 0;
3345 }
064ba683 3346
82489ea0 3347 op_hash = hash_new ();
355afbcd
KR		 3348
3349 obstack_begin (&robyn, 4000);
a1c7c0f3 3350 for (i = 0; i < m68k_numopcodes; i++)
355afbcd
KR		 3351 {
3352 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3353 do
3354 {
a1c7c0f3 3355 ins = &m68k_opcodes[i];
e284846a
KR		 3356 /* We *could* ignore insns that don't match our arch here
3357 but just leaving them out of the hash. */
355afbcd
KR		 3358 slak->m_operands = ins->args;
3359 slak->m_opnum = strlen (slak->m_operands) / 2;
3360 slak->m_arch = ins->arch;
3361 slak->m_opcode = ins->opcode;
3362 /* This is kludgey */
3363 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
a1c7c0f3
ILT		 3364 if (i + 1 != m68k_numopcodes
3365 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
355afbcd
KR		 3366 {
3367 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 3368 i++;
355afbcd
KR		 3369 }
3370 else
3371 slak->m_next = 0;
3372 slak = slak->m_next;
f8701a3f 3373 }
355afbcd
KR		 3374 while (slak);
3375
3376 retval = hash_insert (op_hash, ins->name, (char *) hack);
dff60b7d 3377 if (retval)
b79de3a1
KR		 3378 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3379 }
3380
a1c7c0f3 3381 for (i = 0; i < m68k_numaliases; i++)
b79de3a1
KR		 3382 {
3383 const char *name = m68k_opcode_aliases[i].primary;
3384 const char *alias = m68k_opcode_aliases[i].alias;
3385 PTR val = hash_find (op_hash, name);
3386 if (!val)
3387 as_fatal ("Internal Error: Can't find %s in hash table", name);
3388 retval = hash_insert (op_hash, alias, val);
3389 if (retval)
3390 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
355afbcd 3391 }
6d27d3a2 3392
6700d36e
ILT		 3393 /* In MRI mode, all unsized branches are variable sized. Normally,
3394 they are word sized. */
3395 if (flag_mri)
3396 {
3397 static struct m68k_opcode_alias mri_aliases[] =
3398 {
3399 { "bhi", "jhi", },
3400 { "bls", "jls", },
3401 { "bcc", "jcc", },
3402 { "bcs", "jcs", },
3403 { "bne", "jne", },
3404 { "beq", "jeq", },
3405 { "bvc", "jvc", },
3406 { "bvs", "jvs", },
3407 { "bpl", "jpl", },
3408 { "bmi", "jmi", },
3409 { "bge", "jge", },
3410 { "blt", "jlt", },
3411 { "bgt", "jgt", },
3412 { "ble", "jle", },
3413 { "bra", "jra", },
3414 { "bsr", "jbsr", },
3415 };
3416
3417 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3418 {
3419 const char *name = mri_aliases[i].primary;
3420 const char *alias = mri_aliases[i].alias;
3421 PTR val = hash_find (op_hash, name);
3422 if (!val)
3423 as_fatal ("Internal Error: Can't find %s in hash table", name);
3424 retval = hash_jam (op_hash, alias, val);
3425 if (retval)
3426 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3427 }
3428 }
3429
355afbcd
KR		 3430 for (i = 0; i < sizeof (mklower_table); i++)
3431 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3432
355afbcd
KR		 3433 for (i = 0; i < sizeof (notend_table); i++)
3434 {
3435 notend_table[i] = 0;
3436 alt_notend_table[i] = 0;
3437 }
3438 notend_table[','] = 1;
3439 notend_table['{'] = 1;
3440 notend_table['}'] = 1;
3441 alt_notend_table['a'] = 1;
3442 alt_notend_table['A'] = 1;
3443 alt_notend_table['d'] = 1;
3444 alt_notend_table['D'] = 1;
3445 alt_notend_table['#'] = 1;
5f8cb05e 3446 alt_notend_table['&'] = 1;
355afbcd
KR		 3447 alt_notend_table['f'] = 1;
3448 alt_notend_table['F'] = 1;
fecd2382 3449#ifdef REGISTER_PREFIX
355afbcd 3450 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3451#endif
f8701a3f 3452
a1c7c0f3
ILT		 3453 /* We need to put '(' in alt_notend_table to handle
3454 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3455 */
3456 alt_notend_table['('] = 1;
3457
3458 /* We need to put '@' in alt_notend_table to handle
3459 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3460 */
3461 alt_notend_table['@'] = 1;
3462
8d20a0a8
C		 3463 /* We need to put digits in alt_notend_table to handle
3464 bfextu %d0{24:1},%d0
3465 */
3466 alt_notend_table['0'] = 1;
3467 alt_notend_table['1'] = 1;
3468 alt_notend_table['2'] = 1;
3469 alt_notend_table['3'] = 1;
3470 alt_notend_table['4'] = 1;
3471 alt_notend_table['5'] = 1;
3472 alt_notend_table['6'] = 1;
3473 alt_notend_table['7'] = 1;
3474 alt_notend_table['8'] = 1;
3475 alt_notend_table['9'] = 1;
3476
3ad9ec6a 3477#ifndef MIT_SYNTAX_ONLY
355afbcd 3478 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 3479 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3480 {
3481 int n = 0;
3482 while (mote_pseudo_table[n].poc_name)
3483 {
3484 hack = (struct m68k_incant *)
3485 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3486 hash_insert (op_hash,
3487 mote_pseudo_table[n].poc_name, (char *) hack);
3488 hack->m_operands = 0;
3489 hack->m_opnum = n;
3490 n++;
3491 }
3492 }
3ad9ec6a
ILT		 3493#endif
3494
355afbcd 3495 init_regtable ();
a043f579
ILT		 3496
3497#ifdef OBJ_ELF
3498 record_alignment (text_section, 2);
3499 record_alignment (data_section, 2);
3500 record_alignment (bss_section, 2);
3501#endif
fecd2382
RP		 3502}
3503
82489ea0
KR		 3504void
3505m68k_init_after_args ()
3506{
3507 if (cpu_of_arch (current_architecture) == 0)
3508 {
064ba683 3509 int i;
b79de3a1 3510 const char *default_cpu = TARGET_CPU;
82489ea0 3511
b79de3a1
KR		 3512 if (*default_cpu == 'm')
3513 default_cpu++;
3514 for (i = 0; i < n_archs; i++)
e9bb39b4 3515 if (strcasecmp (default_cpu, archs[i].name) == 0)
b79de3a1
KR		 3516 break;
3517 if (i == n_archs)
3518 {
3519 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3520 current_architecture |= m68020;
3521 }
3522 else
3523 current_architecture |= archs[i].arch;
82489ea0 3524 }
b79de3a1
KR		 3525 /* Permit m68881 specification with all cpus; those that can't work
3526 with a coprocessor could be doing emulation. */
82489ea0
KR		 3527 if (current_architecture & m68851)
3528 {
3529 if (current_architecture & m68040)
3530 {
3531 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3532 }
3533 }
3534 /* What other incompatibilities could we check for? */
3535
3536 /* Toss in some default assumptions about coprocessors. */
3537 if (!no_68881
3538 && (cpu_of_arch (current_architecture)
3539 /* Can CPU32 have a 68881 coprocessor?? */
3540 & (m68020 | m68030 | cpu32)))
3541 {
3542 current_architecture |= m68881;
3543 }
3544 if (!no_68851
3545 && (cpu_of_arch (current_architecture) & m68020up) != 0
3546 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3547 {
3548 current_architecture |= m68851;
3549 }
3550 if (no_68881 && (current_architecture & m68881))
3551 as_bad ("options for 68881 and no-68881 both given");
3552 if (no_68851 && (current_architecture & m68851))
3553 as_bad ("options for 68851 and no-68851 both given");
3554
3555#ifdef OBJ_AOUT
3556 /* Work out the magic number. This isn't very general. */
3557 if (current_architecture & m68000)
3558 m68k_aout_machtype = 0;
3559 else if (current_architecture & m68010)
3560 m68k_aout_machtype = 1;
3561 else if (current_architecture & m68020)
3562 m68k_aout_machtype = 2;
3563 else
3564 m68k_aout_machtype = 2;
3565#endif
3566
3567 /* Note which set of "movec" control registers is available. */
3568 switch (cpu_of_arch (current_architecture))
3569 {
3570 case m68000:
3571 control_regs = m68000_control_regs;
3572 break;
3573 case m68010:
3574 control_regs = m68010_control_regs;
3575 break;
3576 case m68020:
3577 case m68030:
3578 control_regs = m68020_control_regs;
3579 break;
3580 case m68040:
3581 control_regs = m68040_control_regs;
3582 break;
3583 case m68060:
3584 control_regs = m68060_control_regs;
3585 break;
b79de3a1
KR		 3586 case cpu32:
3587 control_regs = cpu32_control_regs;
3588 break;
8d20a0a8
C		 3589 case mcf5200:
3590 control_regs = mcf5200_control_regs;
3591 break;
82489ea0
KR		 3592 default:
3593 abort ();
3594 }
04ef74bb
KR		 3595
3596 if (cpu_of_arch (current_architecture) < m68020)
3597 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
82489ea0
KR		 3598}
3599
20710f1c
ILT		 3600/* This is called if we go in or out of MRI mode because of the .mri
3601 pseudo-op. */
3602
3603void
3604m68k_mri_mode_change (on)
3605 int on;
3606{
3607 if (on)
3608 {
3609 if (! flag_reg_prefix_optional)
3610 {
3611 flag_reg_prefix_optional = 1;
3612#ifdef REGISTER_PREFIX
3613 init_regtable ();
3614#endif
3615 }
3616 m68k_abspcadd = 1;
3617 m68k_rel32 = 0;
3618 }
3619 else
3620 {
3621 if (! reg_prefix_optional_seen)
3622 {
3623#ifdef REGISTER_PREFIX_OPTIONAL
3624 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3625#else
3626 flag_reg_prefix_optional = 0;
3627#endif
3628#ifdef REGISTER_PREFIX
3629 init_regtable ();
3630#endif
3631 }
3632 m68k_abspcadd = 0;
3633 m68k_rel32 = 1;
3634 }
3635}
3636
fecd2382
RP		 3637/* Equal to MAX_PRECISION in atof-ieee.c */
3638#define MAX_LITTLENUMS 6
3639
a1c7c0f3
ILT		 3640/* Turn a string in input_line_pointer into a floating point constant
3641 of type type, and store the appropriate bytes in *litP. The number
3642 of LITTLENUMS emitted is stored in *sizeP . An error message is
3643 returned, or NULL on OK. */
3644
fecd2382 3645char *
355afbcd
KR		 3646md_atof (type, litP, sizeP)
3647 char type;
3648 char *litP;
3649 int *sizeP;
fecd2382 3650{
355afbcd
KR		 3651 int prec;
3652 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3653 LITTLENUM_TYPE *wordP;
3654 char *t;
3655 char *atof_ieee ();
6d27d3a2 3656
355afbcd
KR		 3657 switch (type)
3658 {
3659 case 'f':
3660 case 'F':
3661 case 's':
3662 case 'S':
3663 prec = 2;
3664 break;
6d27d3a2 3665
355afbcd
KR		 3666 case 'd':
3667 case 'D':
3668 case 'r':
3669 case 'R':
3670 prec = 4;
3671 break;
6d27d3a2 3672
355afbcd
KR		 3673 case 'x':
3674 case 'X':
3675 prec = 6;
3676 break;
6d27d3a2 3677
355afbcd
KR		 3678 case 'p':
3679 case 'P':
3680 prec = 6;
3681 break;
6d27d3a2 3682
355afbcd
KR		 3683 default:
3684 *sizeP = 0;
3685 return "Bad call to MD_ATOF()";
3686 }
3687 t = atof_ieee (input_line_pointer, type, words);
3688 if (t)
3689 input_line_pointer = t;
3690
3691 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3692 for (wordP = words; prec--;)
3693 {
3694 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3695 litP += sizeof (LITTLENUM_TYPE);
3696 }
49864cfa 3697 return 0;
fecd2382
RP		 3698}
3699
fecd2382 3700void
355afbcd
KR		 3701md_number_to_chars (buf, val, n)
3702 char *buf;
025b0302 3703 valueT val;
355afbcd 3704 int n;
fecd2382 3705{
82489ea0 3706 number_to_chars_bigendian (buf, val, n);
fecd2382
RP		 3707}
3708
49864cfa
KR		 3709static void
3710md_apply_fix_2 (fixP, val)
355afbcd 3711 fixS *fixP;
9ad5755f 3712 offsetT val;
fecd2382 3713{
9ad5755f
KR		 3714 addressT upper_limit;
3715 offsetT lower_limit;
49864cfa 3716
9ad5755f
KR		 3717 /* This is unnecessary but it convinces the native rs6000 compiler
3718 to generate the code we want. */
355afbcd
KR		 3719 char *buf = fixP->fx_frag->fr_literal;
3720 buf += fixP->fx_where;
9ad5755f
KR		 3721 /* end ibm compiler workaround */
3722
3723 if (val & 0x80000000)
3724 val |= ~(addressT)0x7fffffff;
3725 else
3726 val &= 0x7fffffff;
6d27d3a2 3727
a043f579
ILT		 3728#ifdef OBJ_ELF
3729 if (fixP->fx_addsy)
3730 {
3731 memset (buf, 0, fixP->fx_size);
3732 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3733 return;
3734 }
3735#endif
3736
355afbcd
KR		 3737 switch (fixP->fx_size)
3738 {
b79de3a1
KR		 3739 /* The cast to offsetT below are necessary to make code correct for
3740 machines where ints are smaller than offsetT */
355afbcd
KR		 3741 case 1:
3742 *buf++ = val;
49864cfa 3743 upper_limit = 0x7f;
b79de3a1 3744 lower_limit = - (offsetT) 0x80;
355afbcd
KR		 3745 break;
3746 case 2:
3747 *buf++ = (val >> 8);
3748 *buf++ = val;
49864cfa 3749 upper_limit = 0x7fff;
b79de3a1 3750 lower_limit = - (offsetT) 0x8000;
355afbcd
KR		 3751 break;
3752 case 4:
3753 *buf++ = (val >> 24);
3754 *buf++ = (val >> 16);
3755 *buf++ = (val >> 8);
3756 *buf++ = val;
49864cfa 3757 upper_limit = 0x7fffffff;
b79de3a1 3758 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
355afbcd
KR		 3759 break;
3760 default:
3761 BAD_CASE (fixP->fx_size);
3762 }
49864cfa 3763
3b06beb7
ILT		 3764 /* Fix up a negative reloc. */
3765 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3766 {
3767 fixP->fx_addsy = fixP->fx_subsy;
3768 fixP->fx_subsy = NULL;
3769 fixP->fx_tcbit = 1;
3770 }
3771
49864cfa
KR		 3772 /* For non-pc-relative values, it's conceivable we might get something
3773 like "0xff" for a byte field. So extend the upper part of the range
3774 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3775 so that we can do any range checking at all. */
3776 if (!fixP->fx_pcrel)
3777 upper_limit = upper_limit * 2 + 1;
3778
9ad5755f
KR		 3779 if ((addressT) val > upper_limit
3780 && (val > 0 || val < lower_limit))
f3751617
ILT		 3781 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3782
3783 /* A one byte PC-relative reloc means a short branch. We can't use
3784 a short branch with a value of 0 or -1, because those indicate
3785 different opcodes (branches with longer offsets). */
3786 if (fixP->fx_pcrel
3787 && fixP->fx_size == 1
3788 && (fixP->fx_addsy == NULL
3789 || S_IS_DEFINED (fixP->fx_addsy))
3790 && (val == 0 || val == -1))
3791 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
fecd2382
RP		 3792}
3793
49864cfa
KR		 3794#ifdef BFD_ASSEMBLER
3795int
3796md_apply_fix (fixP, valp)
3797 fixS *fixP;
5f8cb05e 3798 valueT *valp;
49864cfa 3799{
9ad5755f 3800 md_apply_fix_2 (fixP, (addressT) *valp);
49864cfa
KR		 3801 return 1;
3802}
3803#else
3804void md_apply_fix (fixP, val)
3805 fixS *fixP;
3806 long val;
3807{
9ad5755f 3808 md_apply_fix_2 (fixP, (addressT) val);
49864cfa
KR		 3809}
3810#endif
fecd2382
RP		 3811
3812/* *fragP has been relaxed to its final size, and now needs to have
3813 the bytes inside it modified to conform to the new size There is UGLY
3814 MAGIC here. ..
a39116f1 3815 */
fecd2382 3816void
49864cfa 3817md_convert_frag_1 (fragP)
355afbcd 3818 register fragS *fragP;
fecd2382 3819{
355afbcd
KR		 3820 long disp;
3821 long ext = 0;
5f8cb05e 3822 fixS *fixP;
6d27d3a2 3823
355afbcd
KR		 3824 /* Address in object code of the displacement. */
3825 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 3826
9ad5755f
KR		 3827 /* Address in gas core of the place to store the displacement. */
3828 /* This convinces the native rs6000 compiler to generate the code we
3829 want. */
355afbcd
KR		 3830 register char *buffer_address = fragP->fr_literal;
3831 buffer_address += fragP->fr_fix;
9ad5755f 3832 /* end ibm compiler workaround */
6d27d3a2 3833
355afbcd
KR		 3834 /* The displacement of the address, from current location. */
3835 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3836 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 3837
5f8cb05e
ILT		 3838#ifdef BFD_ASSEMBLER
3839 disp += fragP->fr_symbol->sy_frag->fr_address;
3840#endif
3841
355afbcd
KR		 3842 switch (fragP->fr_subtype)
3843 {
3844 case TAB (BCC68000, BYTE):
3845 case TAB (ABRANCH, BYTE):
3846 know (issbyte (disp));
3847 if (disp == 0)
3848 as_bad ("short branch with zero offset: use :w");
3849 fragP->fr_opcode[1] = disp;
3850 ext = 0;
3851 break;
3852 case TAB (DBCC, SHORT):
3853 know (issword (disp));
3854 ext = 2;
3855 break;
3856 case TAB (BCC68000, SHORT):
3857 case TAB (ABRANCH, SHORT):
3858 know (issword (disp));
3859 fragP->fr_opcode[1] = 0x00;
3860 ext = 2;
3861 break;
3862 case TAB (ABRANCH, LONG):
3863 if (cpu_of_arch (current_architecture) < m68020)
3864 {
3865 if (fragP->fr_opcode[0] == 0x61)
04ef74bb 3866 /* BSR */
355afbcd
KR		 3867 {
3868 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3869 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd
KR		 3870
3871 fix_new (fragP,
3872 fragP->fr_fix,
3873 4,
3874 fragP->fr_symbol,
355afbcd
KR		 3875 fragP->fr_offset,
3876 0,
3877 NO_RELOC);
3878
3879 fragP->fr_fix += 4;
3880 ext = 0;
3881 }
04ef74bb 3882 /* BRA */
355afbcd
KR		 3883 else if (fragP->fr_opcode[0] == 0x60)
3884 {
3885 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 3886 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
bcb8dff8
KR		 3887 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3888 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3889 fragP->fr_fix += 4;
3890 ext = 0;
3891 }
3892 else
3893 {
3894 as_bad ("Long branch offset not supported.");
3895 }
3896 }
3897 else
3898 {
bcb8dff8 3899 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 3900 ext = 4;
3901 }
3902 break;
3903 case TAB (BCC68000, LONG):
3904 /* only Bcc 68000 instructions can come here */
3905 /* change bcc into b!cc/jmp absl long */
3906 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3907 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 3908
355afbcd 3909 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 3910 different frag, in which case refering to them is a no-no.
3911 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 3912 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3913 *buffer_address++ = (char) 0xf9;
355afbcd 3914 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8
KR		 3915 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3916 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3917 fragP->fr_fix += 4;
3918 ext = 0;
3919 break;
3920 case TAB (DBCC, LONG):
3921 /* only DBcc 68000 instructions can come here */
3922 /* change dbcc into dbcc/jmp absl long */
3923 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3924 *buffer_address++ = 0x00; /* branch offset = 4 */
3925 *buffer_address++ = 0x04;
3926 *buffer_address++ = 0x60; /* put in bra pc+6 */
3927 *buffer_address++ = 0x06;
3928 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 3929 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 3930
3931 fragP->fr_fix += 6; /* account for bra/jmp instructions */
bcb8dff8 3932 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 3933 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 3934 fragP->fr_fix += 4;
3935 ext = 0;
3936 break;
3937 case TAB (FBRANCH, SHORT):
3938 know ((fragP->fr_opcode[1] & 0x40) == 0);
3939 ext = 2;
3940 break;
3941 case TAB (FBRANCH, LONG):
3942 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3943 ext = 4;
3944 break;
3945 case TAB (PCREL, SHORT):
3946 ext = 2;
3947 break;
3948 case TAB (PCREL, LONG):
3949 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 3950 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 3951 /* JF FOO This code has not been tested */
bcb8dff8 3952 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 3953 0, NO_RELOC);
355afbcd 3954 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
bcb8dff8
KR		 3955 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3956 (unsigned) fragP->fr_opcode[0],
3957 (unsigned long) fragP->fr_address);
355afbcd
KR		 3958 fragP->fr_opcode[1] &= ~0x3F;
3959 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3960 fragP->fr_fix += 4;
355afbcd
KR		 3961 ext = 0;
3962 break;
3963 case TAB (PCLEA, SHORT):
49864cfa 3964 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 3965 fragP->fr_offset, 1, NO_RELOC);
355afbcd 3966 fragP->fr_opcode[1] &= ~0x3F;
04ef74bb 3967 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
355afbcd
KR		 3968 ext = 2;
3969 break;
3970 case TAB (PCLEA, LONG):
5f8cb05e
ILT		 3971 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3972 fragP->fr_offset, 1, NO_RELOC);
3973 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 3974 /* Already set to mode 7.3; this indicates: PC indirect with
3975 suppressed index, 32-bit displacement. */
355afbcd
KR		 3976 *buffer_address++ = 0x01;
3977 *buffer_address++ = 0x70;
3978 fragP->fr_fix += 2;
355afbcd
KR		 3979 ext = 4;
3980 break;
04ef74bb
KR		 3981
3982 case TAB (PCINDEX, BYTE):
3983 disp += 2;
3984 if (!issbyte (disp))
3985 {
3986 as_bad ("displacement doesn't fit in one byte");
3987 disp = 0;
3988 }
5f8cb05e
ILT		 3989 assert (fragP->fr_fix >= 2);
3990 buffer_address[-2] &= ~1;
3991 buffer_address[-1] = disp;
04ef74bb
KR		 3992 ext = 0;
3993 break;
3994 case TAB (PCINDEX, SHORT):
04ef74bb
KR		 3995 disp += 2;
3996 assert (issword (disp));
5f8cb05e
ILT		 3997 assert (fragP->fr_fix >= 2);
3998 buffer_address[-2] |= 0x1;
3999 buffer_address[-1] = 0x20;
4000 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4001 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4002 NO_RELOC);
4003 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4004 ext = 2;
4005 break;
4006 case TAB (PCINDEX, LONG):
04ef74bb 4007 disp += 2;
5f8cb05e
ILT		 4008 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4009 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4010 NO_RELOC);
4011 fixP->fx_pcrel_adjust = 2;
4012 assert (fragP->fr_fix >= 2);
4013 buffer_address[-2] |= 0x1;
4014 buffer_address[-1] = 0x30;
04ef74bb
KR		 4015 ext = 4;
4016 break;
49864cfa 4017 }
355afbcd
KR		 4018
4019 if (ext)
4020 {
4021 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4022 fragP->fr_fix += ext;
49864cfa
KR		 4023 }
4024}
355afbcd 4025
49864cfa
KR		 4026#ifndef BFD_ASSEMBLER
4027
4028void
064ba683 4029md_convert_frag (headers, sec, fragP)
49864cfa 4030 object_headers *headers;
064ba683 4031 segT sec;
49864cfa
KR		 4032 fragS *fragP;
4033{
4034 md_convert_frag_1 (fragP);
4035}
4036
4037#else
4038
4039void
4040md_convert_frag (abfd, sec, fragP)
4041 bfd *abfd;
5f8cb05e 4042 segT sec;
49864cfa
KR		 4043 fragS *fragP;
4044{
4045 md_convert_frag_1 (fragP);
4046}
4047#endif
355afbcd
KR		 4048
4049/* Force truly undefined symbols to their maximum size, and generally set up
4050 the frag list to be relaxed
4051 */
4052int
4053md_estimate_size_before_relax (fragP, segment)
4054 register fragS *fragP;
4055 segT segment;
4056{
4057 int old_fix;
4058 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4059
4060 old_fix = fragP->fr_fix;
4061
4062 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4063 switch (fragP->fr_subtype)
4064 {
4065
4066 case TAB (ABRANCH, SZ_UNDEF):
4067 {
4068 if ((fragP->fr_symbol != NULL) /* Not absolute */
4069 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4070 {
4071 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4072 break;
4073 }
4074 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4075 {
4076 /* On 68000, or for absolute value, switch to abs long */
4077 /* FIXME, we should check abs val, pick short or long */
4078 if (fragP->fr_opcode[0] == 0x61)
4079 {
4080 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4081 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd 4082 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4083 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4084 fragP->fr_fix += 4;
4085 frag_wane (fragP);
4086 }
4087 else if (fragP->fr_opcode[0] == 0x60)
4088 {
4089 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4090 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
355afbcd 4091 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4092 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4093 fragP->fr_fix += 4;
4094 frag_wane (fragP);
4095 }
4096 else
4097 {
4098 as_warn ("Long branch offset to extern symbol not supported.");
4099 }
4100 }
4101 else
4102 { /* Symbol is still undefined. Make it simple */
4103 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5f8cb05e 4104 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4105 fragP->fr_fix += 4;
bcb8dff8 4106 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4107 frag_wane (fragP);
4108 break;
4109 }
4110
a39116f1 4111 break;
355afbcd 4112 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 4113
355afbcd
KR		 4114 case TAB (FBRANCH, SZ_UNDEF):
4115 {
9ad5755f 4116 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
355afbcd
KR		 4117 {
4118 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4119 fragP->fr_var += 2;
4120 }
4121 else
4122 {
5f8cb05e
ILT		 4123 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4124 fragP->fr_offset, 1, NO_RELOC);
4125 fragP->fr_fix += 4;
4126 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4127 frag_wane (fragP);
355afbcd
KR		 4128 }
4129 break;
4130 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 4131
355afbcd
KR		 4132 case TAB (PCREL, SZ_UNDEF):
4133 {
b79de3a1
KR		 4134 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4135 || flag_short_refs
4136 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 4137 {
4138 fragP->fr_subtype = TAB (PCREL, SHORT);
4139 fragP->fr_var += 2;
4140 }
4141 else
4142 {
4143 fragP->fr_subtype = TAB (PCREL, LONG);
4144 fragP->fr_var += 4;
4145 }
4146 break;
4147 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 4148
355afbcd
KR		 4149 case TAB (BCC68000, SZ_UNDEF):
4150 {
4151 if ((fragP->fr_symbol != NULL)
4152 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4153 {
4154 fragP->fr_subtype = TAB (BCC68000, BYTE);
4155 break;
4156 }
4157 /* only Bcc 68000 instructions can come here */
4158 /* change bcc into b!cc/jmp absl long */
4159 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
9ad5755f 4160 if (flag_short_refs)
355afbcd
KR		 4161 {
4162 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4163 /* JF: these were fr_opcode[2,3] */
4164 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4165 buffer_address[1] = (char) 0xf8;
355afbcd 4166 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4167 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4168 fragP->fr_offset, 0, NO_RELOC);
4169 fragP->fr_fix += 2;
4170 }
4171 else
4172 {
4173 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4174 /* JF: these were fr_opcode[2,3] */
4175 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4176 buffer_address[1] = (char) 0xf9;
355afbcd 4177 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4178 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4179 fragP->fr_offset, 0, NO_RELOC);
4180 fragP->fr_fix += 4;
4181 }
4182 frag_wane (fragP);
4183 break;
4184 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 4185
355afbcd
KR		 4186 case TAB (DBCC, SZ_UNDEF):
4187 {
4188 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4189 {
4190 fragP->fr_subtype = TAB (DBCC, SHORT);
4191 fragP->fr_var += 2;
4192 break;
4193 }
4194 /* only DBcc 68000 instructions can come here */
4195 /* change dbcc into dbcc/jmp absl long */
4196 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4197 buffer_address[0] = 0x00; /* branch offset = 4 */
4198 buffer_address[1] = 0x04;
4199 buffer_address[2] = 0x60; /* put in bra pc + ... */
4200
9ad5755f 4201 if (flag_short_refs)
355afbcd
KR		 4202 {
4203 /* JF: these were fr_opcode[5-7] */
4204 buffer_address[3] = 0x04; /* plus 4 */
4205 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 4206 buffer_address[5] = (char) 0xf8;
355afbcd 4207 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4208 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4209 fragP->fr_offset, 0, NO_RELOC);
4210 fragP->fr_fix += 2;
4211 }
4212 else
4213 {
4214 /* JF: these were fr_opcode[5-7] */
4215 buffer_address[3] = 0x06; /* Plus 6 */
4216 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4217 buffer_address[5] = (char) 0xf9;
355afbcd 4218 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4219 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4220 fragP->fr_offset, 0, NO_RELOC);
4221 fragP->fr_fix += 4;
4222 }
6d27d3a2 4223
355afbcd
KR		 4224 frag_wane (fragP);
4225 break;
4226 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 4227
355afbcd
KR		 4228 case TAB (PCLEA, SZ_UNDEF):
4229 {
b79de3a1
KR		 4230 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4231 || flag_short_refs
4232 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 4233 {
4234 fragP->fr_subtype = TAB (PCLEA, SHORT);
4235 fragP->fr_var += 2;
4236 }
4237 else
4238 {
4239 fragP->fr_subtype = TAB (PCLEA, LONG);
4240 fragP->fr_var += 6;
4241 }
4242 break;
4243 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 4244
04ef74bb
KR		 4245 case TAB (PCINDEX, SZ_UNDEF):
4246 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4247 || cpu_of_arch (current_architecture) < m68020)
4248 {
4249 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4250 }
4251 else
4252 {
4253 fragP->fr_subtype = TAB (PCINDEX, LONG);
5f8cb05e 4254 fragP->fr_var += 4;
04ef74bb 4255 }
355afbcd 4256 break;
6d27d3a2 4257
04ef74bb
KR		 4258 default:
4259 break;
4260 }
6d27d3a2 4261
355afbcd
KR		 4262 /* now that SZ_UNDEF are taken care of, check others */
4263 switch (fragP->fr_subtype)
4264 {
4265 case TAB (BCC68000, BYTE):
4266 case TAB (ABRANCH, BYTE):
024e1779
ILT		 4267 /* We can't do a short jump to the next instruction, so in that
4268 case we force word mode. At this point S_GET_VALUE should
4269 return the offset of the symbol within its frag. If the
4270 symbol is at the start of a frag, and it is the next frag
4271 with any data in it (usually this is just the next frag, but
4272 assembler listings may introduce empty frags), we must use
4273 word mode. */
65feb78d 4274 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
355afbcd 4275 {
65feb78d
ILT		 4276 fragS *l;
4277
4278 for (l = fragP->fr_next;
4279 l != fragP->fr_symbol->sy_frag;
4280 l = l->fr_next)
4281 if (l->fr_fix + l->fr_var != 0)
4282 break;
4283 if (l == fragP->fr_symbol->sy_frag)
4284 {
4285 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4286 fragP->fr_var += 2;
4287 }
fecd2382 4288 }
355afbcd
KR		 4289 break;
4290 default:
4291 break;
4292 }
4293 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 4294}
4295
4296#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 4297/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 4298 with the byte-order problems of cross-assembly. So as a hack,
4299 I added this mach. dependent ri twiddler. Ugly, but it gets
4300 you there. -KWK */
4301/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 4302 are symbolnum, most sig. byte first. Last byte is broken up with
4303 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4304 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 4305/* Translate the internal relocation information into target-specific
4306 format. */
a79c6033 4307#ifdef comment
fecd2382 4308void
355afbcd
KR		 4309md_ri_to_chars (the_bytes, ri)
4310 char *the_bytes;
4311 struct reloc_info_generic *ri;
fecd2382 4312{
355afbcd
KR		 4313 /* this is easy */
4314 md_number_to_chars (the_bytes, ri->r_address, 4);
4315 /* now the fun stuff */
4316 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4317 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4318 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4319 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4320 ((ri->r_extern << 4) & 0x10));
fecd2382 4321}
355afbcd 4322
a79c6033
RP		 4323#endif /* comment */
4324
49864cfa 4325#ifndef BFD_ASSEMBLER
355afbcd
KR		 4326void
4327tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4328 char *where;
4329 fixS *fixP;
4330 relax_addressT segment_address_in_file;
a79c6033 4331{
355afbcd 4332 /*
1404ef23
KR		 4333 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4334 * Out: GNU LD relocation length code: 0, 1, or 2.
4335 */
6d27d3a2 4336
82489ea0 4337 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
355afbcd 4338 long r_symbolnum;
6d27d3a2 4339
355afbcd 4340 know (fixP->fx_addsy != NULL);
6d27d3a2 4341
355afbcd
KR		 4342 md_number_to_chars (where,
4343 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4344 4);
6d27d3a2 4345
355afbcd
KR		 4346 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4347 ? S_GET_TYPE (fixP->fx_addsy)
4348 : fixP->fx_addsy->sy_number);
6d27d3a2 4349
355afbcd
KR		 4350 where[4] = (r_symbolnum >> 16) & 0x0ff;
4351 where[5] = (r_symbolnum >> 8) & 0x0ff;
4352 where[6] = r_symbolnum & 0x0ff;
4353 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4354 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
49864cfa
KR		 4355}
4356#endif
a79c6033 4357
fecd2382
RP		 4358#endif /* OBJ_AOUT or OBJ_BOUT */
4359
4360#ifndef WORKING_DOT_WORD
49864cfa
KR		 4361CONST int md_short_jump_size = 4;
4362CONST int md_long_jump_size = 6;
fecd2382
RP		 4363
4364void
355afbcd
KR		 4365md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4366 char *ptr;
025b0302 4367 addressT from_addr, to_addr;
355afbcd
KR		 4368 fragS *frag;
4369 symbolS *to_symbol;
fecd2382 4370{
025b0302 4371 valueT offset;
6d27d3a2 4372
355afbcd 4373 offset = to_addr - (from_addr + 2);
6d27d3a2 4374
025b0302
ME		 4375 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4376 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 4377}
4378
4379void
355afbcd
KR		 4380md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4381 char *ptr;
025b0302 4382 addressT from_addr, to_addr;
355afbcd
KR		 4383 fragS *frag;
4384 symbolS *to_symbol;
fecd2382 4385{
025b0302 4386 valueT offset;
355afbcd
KR		 4387
4388 if (cpu_of_arch (current_architecture) < m68020)
4389 {
4390 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 4391 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4392 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 4393 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4394 0, NO_RELOC);
355afbcd
KR		 4395 }
4396 else
4397 {
4398 offset = to_addr - (from_addr + 2);
025b0302
ME		 4399 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4400 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 4401 }
fecd2382
RP		 4402}
4403
4404#endif
a1c7c0f3
ILT		 4405
4406/* Different values of OK tell what its OK to return. Things that
4407 aren't OK are an error (what a shock, no?)
6d27d3a2 4408
a39116f1
RP		 4409 0: Everything is OK
4410 10: Absolute 1:8 only
4411 20: Absolute 0:7 only
4412 30: absolute 0:15 only
4413 40: Absolute 0:31 only
4414 50: absolute 0:127 only
4415 55: absolute -64:63 only
4416 60: absolute -128:127 only
4417 70: absolute 0:4095 only
4418 80: No bignums
6d27d3a2 4419
a39116f1 4420 */
fecd2382 4421
355afbcd
KR		 4422static int
4423get_num (exp, ok)
4424 struct m68k_exp *exp;
4425 int ok;
fecd2382 4426{
a1c7c0f3 4427 if (exp->exp.X_op == O_absent)
49864cfa 4428 {
355afbcd 4429 /* Do the same thing the VAX asm does */
bcb8dff8 4430 op (exp) = O_constant;
355afbcd
KR		 4431 adds (exp) = 0;
4432 subs (exp) = 0;
4433 offs (exp) = 0;
4434 if (ok == 10)
4435 {
4436 as_warn ("expression out of range: defaulting to 1");
4437 offs (exp) = 1;
4438 }
49864cfa 4439 }
a1c7c0f3 4440 else if (exp->exp.X_op == O_constant)
49864cfa 4441 {
355afbcd
KR		 4442 switch (ok)
4443 {
4444 case 10:
4445 if (offs (exp) < 1 || offs (exp) > 8)
4446 {
4447 as_warn ("expression out of range: defaulting to 1");
4448 offs (exp) = 1;
4449 }
4450 break;
4451 case 20:
4452 if (offs (exp) < 0 || offs (exp) > 7)
4453 goto outrange;
4454 break;
4455 case 30:
4456 if (offs (exp) < 0 || offs (exp) > 15)
4457 goto outrange;
4458 break;
4459 case 40:
4460 if (offs (exp) < 0 || offs (exp) > 32)
4461 goto outrange;
4462 break;
4463 case 50:
4464 if (offs (exp) < 0 || offs (exp) > 127)
4465 goto outrange;
4466 break;
4467 case 55:
4468 if (offs (exp) < -64 || offs (exp) > 63)
4469 goto outrange;
4470 break;
4471 case 60:
4472 if (offs (exp) < -128 || offs (exp) > 127)
4473 goto outrange;
4474 break;
4475 case 70:
4476 if (offs (exp) < 0 || offs (exp) > 4095)
4477 {
4478 outrange:
4479 as_warn ("expression out of range: defaulting to 0");
4480 offs (exp) = 0;
4481 }
4482 break;
fecd2382 4483 default:
355afbcd
KR		 4484 break;
4485 }
49864cfa 4486 }
a1c7c0f3 4487 else if (exp->exp.X_op == O_big)
49864cfa 4488 {
bcb8dff8 4489 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 4490 && (ok == 80 /* no bignums */
4491 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 4492 /* If we have a flonum zero, a zero integer should
4493 do as well (e.g., in moveq). */
355afbcd
KR		 4494 && generic_floating_point_number.exponent == 0
4495 && generic_floating_point_number.low[0] == 0)))
4496 {
4497 /* HACK! Turn it into a long */
4498 LITTLENUM_TYPE words[6];
4499
4500 gen_to_words (words, 2, 8L); /* These numbers are magic! */
bcb8dff8 4501 op (exp) = O_constant;
355afbcd
KR		 4502 adds (exp) = 0;
4503 subs (exp) = 0;
4504 offs (exp) = words[1] | (words[0] << 16);
4505 }
4506 else if (ok != 0)
4507 {
bcb8dff8 4508 op (exp) = O_constant;
355afbcd
KR		 4509 adds (exp) = 0;
4510 subs (exp) = 0;
4511 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4512 as_warn ("Can't deal with expression; defaulting to %ld",
4513 offs (exp));
355afbcd 4514 }
49864cfa
KR		 4515 }
4516 else
4517 {
355afbcd
KR		 4518 if (ok >= 10 && ok <= 70)
4519 {
bcb8dff8 4520 op (exp) = O_constant;
355afbcd
KR		 4521 adds (exp) = 0;
4522 subs (exp) = 0;
4523 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4524 as_warn ("Can't deal with expression; defaulting to %ld",
4525 offs (exp));
355afbcd 4526 }
355afbcd 4527 }
49864cfa 4528
a1c7c0f3 4529 if (exp->size != SIZE_UNSPEC)
355afbcd 4530 {
a1c7c0f3 4531 switch (exp->size)
355afbcd 4532 {
a1c7c0f3
ILT		 4533 case SIZE_UNSPEC:
4534 case SIZE_LONG:
4535 break;
4536 case SIZE_BYTE:
355afbcd
KR		 4537 if (!isbyte (offs (exp)))
4538 as_warn ("expression doesn't fit in BYTE");
4539 break;
a1c7c0f3 4540 case SIZE_WORD:
355afbcd
KR		 4541 if (!isword (offs (exp)))
4542 as_warn ("expression doesn't fit in WORD");
4543 break;
a39116f1 4544 }
355afbcd 4545 }
a1c7c0f3 4546
355afbcd 4547 return offs (exp);
49864cfa 4548}
fecd2382
RP		 4549
4550/* These are the back-ends for the various machine dependent pseudo-ops. */
355afbcd 4551void demand_empty_rest_of_line (); /* Hate those extra verbose names */
fecd2382 4552
355afbcd 4553static void
bcb8dff8
KR		 4554s_data1 (ignore)
4555 int ignore;
355afbcd 4556{
bcb8dff8 4557 subseg_set (data_section, 1);
355afbcd 4558 demand_empty_rest_of_line ();
49864cfa 4559}
fecd2382 4560
355afbcd 4561static void
bcb8dff8
KR		 4562s_data2 (ignore)
4563 int ignore;
355afbcd 4564{
bcb8dff8 4565 subseg_set (data_section, 2);
355afbcd 4566 demand_empty_rest_of_line ();
49864cfa 4567}
fecd2382 4568
355afbcd 4569static void
bcb8dff8
KR		 4570s_bss (ignore)
4571 int ignore;
a1765cf0 4572{
355afbcd 4573 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 4574 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 4575
bcb8dff8 4576 subseg_set (bss_section, 0);
355afbcd 4577 demand_empty_rest_of_line ();
49864cfa 4578}
6d27d3a2 4579
355afbcd 4580static void
bcb8dff8
KR		 4581s_even (ignore)
4582 int ignore;
355afbcd
KR		 4583{
4584 register int temp;
4585 register long temp_fill;
4586
4587 temp = 1; /* JF should be 2? */
4588 temp_fill = get_absolute_expression ();
4589 if (!need_pass_2) /* Never make frag if expect extra pass. */
4590 frag_align (temp, (int) temp_fill);
4591 demand_empty_rest_of_line ();
49864cfa 4592}
355afbcd
KR		 4593
4594static void
bcb8dff8
KR		 4595s_proc (ignore)
4596 int ignore;
355afbcd
KR		 4597{
4598 demand_empty_rest_of_line ();
49864cfa 4599}
e9bb39b4
ILT		 4600\f
4601/* Pseudo-ops handled for MRI compatibility. */
4602
4603/* Handle an MRI style chip specification. */
fecd2382 4604
e9bb39b4
ILT		 4605static void
4606mri_chip ()
4607{
4608 char *s;
4609 char c;
4610 int i;
4611
4612 s = input_line_pointer;
4613 c = get_symbol_end ();
4614 for (i = 0; i < n_archs; i++)
4615 if (strcasecmp (s, archs[i].name) == 0)
4616 break;
4617 if (i >= n_archs)
4618 {
4619 as_bad ("%s: unrecognized processor name", s);
4620 *input_line_pointer = c;
4621 ignore_rest_of_line ();
4622 return;
4623 }
4624 *input_line_pointer = c;
fecd2382 4625
e9bb39b4
ILT		 4626 if (*input_line_pointer == '/')
4627 current_architecture = 0;
4628 else
4629 current_architecture &= m68881 | m68851;
4630 current_architecture |= archs[i].arch;
4631
4632 while (*input_line_pointer == '/')
4633 {
4634 ++input_line_pointer;
4635 s = input_line_pointer;
4636 c = get_symbol_end ();
4637 if (strcmp (s, "68881") == 0)
4638 current_architecture |= m68881;
4639 else if (strcmp (s, "68851") == 0)
4640 current_architecture |= m68851;
4641 *input_line_pointer = c;
4642 }
4643}
4644
4645/* The MRI CHIP pseudo-op. */
4646
4647static void
4648s_chip (ignore)
4649 int ignore;
4650{
f9680a05
ILT		 4651 char *stop = NULL;
4652 char stopc;
4653
4654 if (flag_mri)
4655 stop = mri_comment_field (&stopc);
e9bb39b4 4656 mri_chip ();
f9680a05
ILT		 4657 if (flag_mri)
4658 mri_comment_end (stop, stopc);
e9bb39b4
ILT		 4659 demand_empty_rest_of_line ();
4660}
27a53b88
ILT		 4661
4662/* The MRI FOPT pseudo-op. */
4663
4664static void
4665s_fopt (ignore)
4666 int ignore;
4667{
4668 SKIP_WHITESPACE ();
4669
4670 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4671 {
4672 int temp;
4673
4674 input_line_pointer += 3;
4675 temp = get_absolute_expression ();
4676 if (temp < 0 || temp > 7)
4677 as_bad ("bad coprocessor id");
4678 else
4679 m68k_float_copnum = COP0 + temp;
4680 }
4681 else
4682 {
4683 as_bad ("unrecognized fopt option");
4684 ignore_rest_of_line ();
4685 return;
4686 }
4687
4688 demand_empty_rest_of_line ();
4689}
6700d36e
ILT		 4690
4691/* The structure used to handle the MRI OPT pseudo-op. */
4692
4693struct opt_action
4694{
4695 /* The name of the option. */
4696 const char *name;
4697
4698 /* If this is not NULL, just call this function. The first argument
4699 is the ARG field of this structure, the second argument is
4700 whether the option was negated. */
4701 void (*pfn) PARAMS ((int arg, int on));
4702
4703 /* If this is not NULL, and the PFN field is NULL, set the variable
4704 this points to. Set it to the ARG field if the option was not
4705 negated, and the NOTARG field otherwise. */
4706 int *pvar;
4707
4708 /* The value to pass to PFN or to assign to *PVAR. */
4709 int arg;
4710
4711 /* The value to assign to *PVAR if the option is negated. If PFN is
4712 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4713 the option may not be negated. */
4714 int notarg;
4715};
4716
4717/* The table used to handle the MRI OPT pseudo-op. */
4718
4719static void skip_to_comma PARAMS ((int, int));
7e047ac2 4720static void opt_nest PARAMS ((int, int));
6700d36e
ILT		 4721static void opt_chip PARAMS ((int, int));
4722static void opt_list PARAMS ((int, int));
4723static void opt_list_symbols PARAMS ((int, int));
4724
4725static const struct opt_action opt_table[] =
4726{
4727 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4728
4729 /* We do relaxing, so there is little use for these options. */
4730 { "b", 0, 0, 0, 0 },
4731 { "brs", 0, 0, 0, 0 },
4732 { "brb", 0, 0, 0, 0 },
4733 { "brl", 0, 0, 0, 0 },
4734 { "brw", 0, 0, 0, 0 },
4735
4736 { "c", 0, 0, 0, 0 },
4737 { "cex", 0, 0, 0, 0 },
4738 { "case", 0, &symbols_case_sensitive, 1, 0 },
4739 { "cl", 0, 0, 0, 0 },
4740 { "cre", 0, 0, 0, 0 },
4741 { "d", 0, &flag_keep_locals, 1, 0 },
4742 { "e", 0, 0, 0, 0 },
4743 { "f", 0, &flag_short_refs, 1, 0 },
4744 { "frs", 0, &flag_short_refs, 1, 0 },
4745 { "frl", 0, &flag_short_refs, 0, 1 },
4746 { "g", 0, 0, 0, 0 },
4747 { "i", 0, 0, 0, 0 },
4748 { "m", 0, 0, 0, 0 },
4749 { "mex", 0, 0, 0, 0 },
4750 { "mc", 0, 0, 0, 0 },
4751 { "md", 0, 0, 0, 0 },
7e047ac2 4752 { "nest", opt_nest, 0, 0, 0 },
6700d36e
ILT		 4753 { "next", skip_to_comma, 0, 0, 0 },
4754 { "o", 0, 0, 0, 0 },
4755 { "old", 0, 0, 0, 0 },
4756 { "op", skip_to_comma, 0, 0, 0 },
4757 { "pco", 0, 0, 0, 0 },
4758 { "p", opt_chip, 0, 0, 0 },
4759 { "pcr", 0, 0, 0, 0 },
4760 { "pcs", 0, 0, 0, 0 },
4761 { "r", 0, 0, 0, 0 },
4762 { "quick", 0, &m68k_quick, 1, 0 },
4763 { "rel32", 0, &m68k_rel32, 1, 0 },
4764 { "s", opt_list, 0, 0, 0 },
4765 { "t", opt_list_symbols, 0, 0, 0 },
4766 { "w", 0, &flag_no_warnings, 0, 1 },
4767 { "x", 0, 0, 0, 0 }
4768};
4769
4770#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4771
4772/* The MRI OPT pseudo-op. */
4773
4774static void
4775s_opt (ignore)
4776 int ignore;
4777{
4778 do
4779 {
4780 int t;
4781 char *s;
4782 char c;
4783 int i;
4784 const struct opt_action *o;
4785
4786 SKIP_WHITESPACE ();
4787
4788 t = 1;
4789 if (*input_line_pointer == '-')
4790 {
4791 ++input_line_pointer;
4792 t = 0;
4793 }
4794 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4795 {
4796 input_line_pointer += 2;
4797 t = 0;
4798 }
4799
4800 s = input_line_pointer;
4801 c = get_symbol_end ();
4802
4803 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4804 {
4805 if (strcasecmp (s, o->name) == 0)
4806 {
4807 if (o->pfn)
4808 {
4809 /* Restore input_line_pointer now in case the option
4810 takes arguments. */
4811 *input_line_pointer = c;
4812 (*o->pfn) (o->arg, t);
4813 }
4814 else if (o->pvar != NULL)
4815 {
4816 if (! t && o->arg == o->notarg)
4817 as_bad ("option `%s' may not be negated", s);
4818 *input_line_pointer = c;
4819 *o->pvar = t ? o->arg : o->notarg;
4820 }
9bef2324
ILT		 4821 else
4822 *input_line_pointer = c;
6700d36e
ILT		 4823 break;
4824 }
4825 }
4826 if (i >= OPTCOUNT)
4827 {
4828 as_bad ("option `%s' not recognized", s);
4829 *input_line_pointer = c;
4830 }
4831 }
4832 while (*input_line_pointer++ == ',');
4833
4834 /* Move back to terminating character. */
4835 --input_line_pointer;
4836 demand_empty_rest_of_line ();
4837}
4838
4839/* Skip ahead to a comma. This is used for OPT options which we do
4840 not suppor tand which take arguments. */
4841
4842static void
4843skip_to_comma (arg, on)
4844 int arg;
4845 int on;
4846{
4847 while (*input_line_pointer != ','
4848 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4849 ++input_line_pointer;
4850}
4851
7e047ac2
ILT		 4852/* Handle the OPT NEST=depth option. */
4853
4854static void
4855opt_nest (arg, on)
4856 int arg;
4857 int on;
4858{
4859 if (*input_line_pointer != '=')
4860 {
4861 as_bad ("bad format of OPT NEST=depth");
4862 return;
4863 }
4864
4865 ++input_line_pointer;
4866 max_macro_nest = get_absolute_expression ();
4867}
4868
6700d36e
ILT		 4869/* Handle the OPT P=chip option. */
4870
4871static void
4872opt_chip (arg, on)
4873 int arg;
4874 int on;
4875{
4876 if (*input_line_pointer != '=')
4877 {
4878 /* This is just OPT P, which we do not support. */
4879 return;
4880 }
4881
4882 ++input_line_pointer;
4883 mri_chip ();
4884}
4885
4886/* Handle the OPT S option. */
4887
4888static void
4889opt_list (arg, on)
4890 int arg;
4891 int on;
4892{
4893 listing_list (on);
4894}
4895
4896/* Handle the OPT T option. */
4897
4898static void
4899opt_list_symbols (arg, on)
4900 int arg;
4901 int on;
4902{
4903 if (on)
4904 listing |= LISTING_SYMBOLS;
4905 else
4906 listing &=~ LISTING_SYMBOLS;
4907}
4908
4909/* Handle the MRI REG pseudo-op. */
4910
4911static void
4912s_reg (ignore)
4913 int ignore;
4914{
4915 char *s;
4916 int c;
8e11ad0a 4917 struct m68k_op rop;
6700d36e 4918 unsigned long mask;
f9680a05
ILT		 4919 char *stop = NULL;
4920 char stopc;
6700d36e 4921
7e047ac2 4922 if (line_label == NULL)
6700d36e
ILT		 4923 {
4924 as_bad ("missing label");
4925 ignore_rest_of_line ();
4926 return;
4927 }
4928
f9680a05
ILT		 4929 if (flag_mri)
4930 stop = mri_comment_field (&stopc);
4931
6700d36e
ILT		 4932 SKIP_WHITESPACE ();
4933
4934 s = input_line_pointer;
4935 while (isalnum ((unsigned char) *input_line_pointer)
4936#ifdef REGISTER_PREFIX
4937 || *input_line_pointer == REGISTER_PREFIX
4938#endif
4939 || *input_line_pointer == '/'
4940 || *input_line_pointer == '-')
4941 ++input_line_pointer;
4942 c = *input_line_pointer;
4943 *input_line_pointer = '\0';
4944
8e11ad0a 4945 if (m68k_ip_op (s, &rop) != 0)
6700d36e 4946 {
8e11ad0a 4947 if (rop.error == NULL)
6700d36e
ILT		 4948 as_bad ("bad register list");
4949 else
8e11ad0a 4950 as_bad ("bad register list: %s", rop.error);
6700d36e
ILT		 4951 *input_line_pointer = c;
4952 ignore_rest_of_line ();
4953 return;
4954 }
4955
4956 *input_line_pointer = c;
4957
8e11ad0a
ILT		 4958 if (rop.mode == REGLST)
4959 mask = rop.mask;
4960 else if (rop.mode == DREG)
4961 mask = 1 << (rop.reg - DATA0);
4962 else if (rop.mode == AREG)
4963 mask = 1 << (rop.reg - ADDR0 + 8);
4964 else if (rop.mode == FPREG)
4965 mask = 1 << (rop.reg - FP0 + 16);
4966 else if (rop.mode == CONTROL
4967 && rop.reg == FPI)
6700d36e 4968 mask = 1 << 24;
8e11ad0a
ILT		 4969 else if (rop.mode == CONTROL
4970 && rop.reg == FPS)
6700d36e 4971 mask = 1 << 25;
8e11ad0a
ILT		 4972 else if (rop.mode == CONTROL
4973 && rop.reg == FPC)
6700d36e
ILT		 4974 mask = 1 << 26;
4975 else
4976 {
4977 as_bad ("bad register list");
4978 ignore_rest_of_line ();
4979 return;
4980 }
4981
7e047ac2
ILT		 4982 S_SET_SEGMENT (line_label, absolute_section);
4983 S_SET_VALUE (line_label, mask);
4984 line_label->sy_frag = &zero_address_frag;
6700d36e 4985
85f34122 4986 if (flag_mri)
f9680a05 4987 mri_comment_end (stop, stopc);
85f34122 4988
6700d36e
ILT		 4989 demand_empty_rest_of_line ();
4990}
e14994d9
ILT		 4991
4992/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4993
4994struct save_opts
4995{
4996 struct save_opts *next;
4997 int abspcadd;
4998 int symbols_case_sensitive;
4999 int keep_locals;
5000 int short_refs;
5001 int architecture;
5002 int quick;
5003 int rel32;
5004 int listing;
5005 int no_warnings;
5006 /* FIXME: We don't save OPT S. */
5007};
5008
5009/* This variable holds the stack of saved options. */
5010
5011static struct save_opts *save_stack;
5012
5013/* The MRI SAVE pseudo-op. */
5014
5015static void
5016s_save (ignore)
5017 int ignore;
5018{
5019 struct save_opts *s;
5020
5021 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5022 s->abspcadd = m68k_abspcadd;
5023 s->symbols_case_sensitive = symbols_case_sensitive;
5024 s->keep_locals = flag_keep_locals;
5025 s->short_refs = flag_short_refs;
5026 s->architecture = current_architecture;
5027 s->quick = m68k_quick;
5028 s->rel32 = m68k_rel32;
5029 s->listing = listing;
5030 s->no_warnings = flag_no_warnings;
5031
5032 s->next = save_stack;
5033 save_stack = s;
5034
5035 demand_empty_rest_of_line ();
5036}
5037
5038/* The MRI RESTORE pseudo-op. */
5039
5040static void
5041s_restore (ignore)
5042 int ignore;
5043{
5044 struct save_opts *s;
5045
5046 if (save_stack == NULL)
5047 {
5048 as_bad ("restore without save");
5049 ignore_rest_of_line ();
5050 return;
5051 }
5052
5053 s = save_stack;
5054 save_stack = s->next;
5055
5056 m68k_abspcadd = s->abspcadd;
5057 symbols_case_sensitive = s->symbols_case_sensitive;
5058 flag_keep_locals = s->keep_locals;
5059 flag_short_refs = s->short_refs;
5060 current_architecture = s->architecture;
5061 m68k_quick = s->quick;
5062 m68k_rel32 = s->rel32;
5063 listing = s->listing;
5064 flag_no_warnings = s->no_warnings;
5065
5066 free (s);
5067
5068 demand_empty_rest_of_line ();
5069}
b4ec75e0
ILT		 5070
5071/* Types of MRI structured control directives. */
5072
5073enum mri_control_type
5074{
5075 mri_for,
5076 mri_if,
5077 mri_repeat,
5078 mri_while
5079};
5080
5081/* This structure is used to stack the MRI structured control
5082 directives. */
5083
5084struct mri_control_info
5085{
5086 /* The directive within which this one is enclosed. */
5087 struct mri_control_info *outer;
5088
5089 /* The type of directive. */
5090 enum mri_control_type type;
5091
5092 /* Whether an ELSE has been in an IF. */
5093 int else_seen;
5094
5095 /* The add or sub statement at the end of a FOR. */
5096 char *incr;
5097
5098 /* The label of the top of a FOR or REPEAT loop. */
5099 char *top;
5100
5101 /* The label to jump to for the next iteration, or the else
5102 expression of a conditional. */
5103 char *next;
5104
5105 /* The label to jump to to break out of the loop, or the label past
5106 the end of a conditional. */
5107 char *bottom;
5108};
5109
5110/* The stack of MRI structured control directives. */
5111
5112static struct mri_control_info *mri_control_stack;
5113
5114/* The current MRI structured control directive index number, used to
5115 generate label names. */
5116
5117static int mri_control_index;
5118
5119/* Some function prototypes. */
5120
5121static char *mri_control_label PARAMS ((void));
5122static struct mri_control_info *push_mri_control
5123 PARAMS ((enum mri_control_type));
5124static void pop_mri_control PARAMS ((void));
5125static int parse_mri_condition PARAMS ((int *));
5126static int parse_mri_control_operand
e1c0287d 5127 PARAMS ((int *, char **, char **, char **, char **));
b4ec75e0
ILT		 5128static int swap_mri_condition PARAMS ((int));
5129static int reverse_mri_condition PARAMS ((int));
5130static void build_mri_control_operand
e1c0287d
ILT		 5131 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5132 const char *, int));
b4ec75e0
ILT		 5133static void parse_mri_control_expression
5134 PARAMS ((char *, int, const char *, const char *, int));
5135
5136/* Generate a new MRI label structured control directive label name. */
5137
5138static char *
5139mri_control_label ()
5140{
5141 char *n;
5142
5143 n = (char *) xmalloc (20);
5144 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5145 ++mri_control_index;
5146 return n;
5147}
5148
5149/* Create a new MRI structured control directive. */
5150
5151static struct mri_control_info *
5152push_mri_control (type)
5153 enum mri_control_type type;
5154{
5155 struct mri_control_info *n;
5156
5157 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5158
5159 n->type = type;
5160 n->else_seen = 0;
5161 if (type == mri_if || type == mri_while)
5162 n->top = NULL;
5163 else
5164 n->top = mri_control_label ();
5165 n->next = mri_control_label ();
5166 n->bottom = mri_control_label ();
5167
5168 n->outer = mri_control_stack;
5169 mri_control_stack = n;
5170
5171 return n;
5172}
5173
5174/* Pop off the stack of MRI structured control directives. */
5175
5176static void
5177pop_mri_control ()
5178{
5179 struct mri_control_info *n;
5180
5181 n = mri_control_stack;
5182 mri_control_stack = n->outer;
5183 if (n->top != NULL)
5184 free (n->top);
5185 free (n->next);
5186 free (n->bottom);
5187 free (n);
5188}
5189
5190/* Recognize a condition code in an MRI structured control expression. */
5191
5192static int
5193parse_mri_condition (pcc)
5194 int *pcc;
5195{
5196 char c1, c2;
5197
5198 know (*input_line_pointer == '<');
5199
5200 ++input_line_pointer;
5201 c1 = *input_line_pointer++;
5202 c2 = *input_line_pointer++;
5203
5204 if (*input_line_pointer != '>')
5205 {
5206 as_bad ("syntax error in structured control directive");
5207 return 0;
5208 }
5209
5210 ++input_line_pointer;
5211 SKIP_WHITESPACE ();
5212
5213 if (isupper (c1))
5214 c1 = tolower (c1);
5215 if (isupper (c2))
5216 c2 = tolower (c2);
5217
5218 *pcc = (c1 << 8) | c2;
5219
5220 return 1;
5221}
5222
5223/* Parse a single operand in an MRI structured control expression. */
5224
5225static int
5226parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5227 int *pcc;
b3625fe6 5228 char **leftstart;
e1c0287d 5229 char **leftstop;
b3625fe6 5230 char **rightstart;
e1c0287d 5231 char **rightstop;
b4ec75e0
ILT		 5232{
5233 char *s;
5234
5235 SKIP_WHITESPACE ();
5236
5237 *pcc = -1;
5238 *leftstart = NULL;
5239 *leftstop = NULL;
5240 *rightstart = NULL;
5241 *rightstop = NULL;
5242
5243 if (*input_line_pointer == '<')
5244 {
5245 /* It's just a condition code. */
5246 return parse_mri_condition (pcc);
5247 }
5248
5249 /* Look ahead for the condition code. */
5250 for (s = input_line_pointer; *s != '\0'; ++s)
5251 {
5252 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5253 break;
5254 }
5255 if (*s == '\0')
5256 {
5257 as_bad ("missing condition code in structured control directive");
5258 return 0;
5259 }
5260
5261 *leftstart = input_line_pointer;
5262 *leftstop = s;
4026c122
ILT		 5263 if (*leftstop > *leftstart
5264 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5265 --*leftstop;
b4ec75e0
ILT		 5266
5267 input_line_pointer = s;
5268 if (! parse_mri_condition (pcc))
5269 return 0;
5270
5271 /* Look ahead for AND or OR or end of line. */
5272 for (s = input_line_pointer; *s != '\0'; ++s)
5273 {
5274 if ((strncasecmp (s, "AND", 3) == 0
5275 && (s[3] == '.' || ! is_part_of_name (s[3])))
5276 || (strncasecmp (s, "OR", 2) == 0
5277 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5278 break;
5279 }
5280
5281 *rightstart = input_line_pointer;
5282 *rightstop = s;
4026c122
ILT		 5283 if (*rightstop > *rightstart
5284 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5285 --*rightstop;
b4ec75e0
ILT		 5286
5287 input_line_pointer = s;
5288
5289 return 1;
5290}
5291
5292#define MCC(b1, b2) (((b1) << 8) | (b2))
5293
5294/* Swap the sense of a condition. This changes the condition so that
5295 it generates the same result when the operands are swapped. */
5296
5297static int
5298swap_mri_condition (cc)
5299 int cc;
5300{
5301 switch (cc)
5302 {
5303 case MCC ('h', 'i'): return MCC ('c', 's');
5304 case MCC ('l', 's'): return MCC ('c', 'c');
5305 case MCC ('c', 'c'): return MCC ('l', 's');
5306 case MCC ('c', 's'): return MCC ('h', 'i');
5307 case MCC ('p', 'l'): return MCC ('m', 'i');
5308 case MCC ('m', 'i'): return MCC ('p', 'l');
5309 case MCC ('g', 'e'): return MCC ('l', 'e');
5310 case MCC ('l', 't'): return MCC ('g', 't');
5311 case MCC ('g', 't'): return MCC ('l', 't');
5312 case MCC ('l', 'e'): return MCC ('g', 'e');
5313 }
5314 return cc;
5315}
5316
5317/* Reverse the sense of a condition. */
5318
5319static int
5320reverse_mri_condition (cc)
5321 int cc;
5322{
5323 switch (cc)
5324 {
5325 case MCC ('h', 'i'): return MCC ('l', 's');
5326 case MCC ('l', 's'): return MCC ('h', 'i');
5327 case MCC ('c', 'c'): return MCC ('c', 's');
5328 case MCC ('c', 's'): return MCC ('c', 'c');
5329 case MCC ('n', 'e'): return MCC ('e', 'q');
5330 case MCC ('e', 'q'): return MCC ('n', 'e');
5331 case MCC ('v', 'c'): return MCC ('v', 's');
5332 case MCC ('v', 's'): return MCC ('v', 'c');
5333 case MCC ('p', 'l'): return MCC ('m', 'i');
5334 case MCC ('m', 'i'): return MCC ('p', 'l');
5335 case MCC ('g', 'e'): return MCC ('l', 't');
5336 case MCC ('l', 't'): return MCC ('g', 'e');
5337 case MCC ('g', 't'): return MCC ('l', 'e');
5338 case MCC ('l', 'e'): return MCC ('g', 't');
5339 }
5340 return cc;
5341}
5342
5343/* Build an MRI structured control expression. This generates test
5344 and branch instructions. It goes to TRUELAB if the condition is
5345 true, and to FALSELAB if the condition is false. Exactly one of
5346 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5347 is the size qualifier for the expression. EXTENT is the size to
5348 use for the branch. */
5349
5350static void
5351build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5352 rightstop, truelab, falselab, extent)
5353 int qual;
5354 int cc;
b3625fe6 5355 char *leftstart;
e1c0287d 5356 char *leftstop;
b3625fe6 5357 char *rightstart;
e1c0287d 5358 char *rightstop;
b4ec75e0
ILT		 5359 const char *truelab;
5360 const char *falselab;
5361 int extent;
5362{
5363 char *buf;
5364 char *s;
5365
e1c0287d 5366 if (leftstart != NULL)
b3625fe6 5367 {
e1c0287d
ILT		 5368 struct m68k_op leftop, rightop;
5369 char c;
b3625fe6 5370
e1c0287d
ILT		 5371 /* Swap the compare operands, if necessary, to produce a legal
5372 m68k compare instruction. Comparing a register operand with
5373 a non-register operand requires the register to be on the
5374 right (cmp, cmpa). Comparing an immediate value with
5375 anything requires the immediate value to be on the left
5376 (cmpi). */
5377
5378 c = *leftstop;
5379 *leftstop = '\0';
5380 (void) m68k_ip_op (leftstart, &leftop);
5381 *leftstop = c;
5382
5383 c = *rightstop;
5384 *rightstop = '\0';
5385 (void) m68k_ip_op (rightstart, &rightop);
5386 *rightstop = c;
5387
5388 if (rightop.mode == IMMED
5389 || ((leftop.mode == DREG || leftop.mode == AREG)
5390 && (rightop.mode != DREG && rightop.mode != AREG)))
5391 {
5392 char *temp;
5393
5394 cc = swap_mri_condition (cc);
5395 temp = leftstart;
5396 leftstart = rightstart;
5397 rightstart = temp;
5398 temp = leftstop;
5399 leftstop = rightstop;
5400 rightstop = temp;
5401 }
b4ec75e0
ILT		 5402 }
5403
5404 if (truelab == NULL)
5405 {
5406 cc = reverse_mri_condition (cc);
5407 truelab = falselab;
5408 }
5409
5410 if (leftstart != NULL)
5411 {
5412 buf = (char *) xmalloc (20
5413 + (leftstop - leftstart)
5414 + (rightstop - rightstart));
5415 s = buf;
5416 *s++ = 'c';
5417 *s++ = 'm';
5418 *s++ = 'p';
5419 if (qual != '\0')
5420 *s++ = qual;
5421 *s++ = ' ';
5422 memcpy (s, leftstart, leftstop - leftstart);
5423 s += leftstop - leftstart;
5424 *s++ = ',';
5425 memcpy (s, rightstart, rightstop - rightstart);
5426 s += rightstop - rightstart;
5427 *s = '\0';
5428 md_assemble (buf);
5429 free (buf);
5430 }
5431
5432 buf = (char *) xmalloc (20 + strlen (truelab));
5433 s = buf;
5434 *s++ = 'b';
5435 *s++ = cc >> 8;
5436 *s++ = cc & 0xff;
5437 if (extent != '\0')
5438 *s++ = extent;
5439 *s++ = ' ';
5440 strcpy (s, truelab);
5441 md_assemble (buf);
5442 free (buf);
5443}
5444
5445/* Parse an MRI structured control expression. This generates test
5446 and branch instructions. STOP is where the expression ends. It
5447 goes to TRUELAB if the condition is true, and to FALSELAB if the
5448 condition is false. Exactly one of TRUELAB and FALSELAB will be
5449 NULL, meaning to fall through. QUAL is the size qualifier for the
5450 expression. EXTENT is the size to use for the branch. */
5451
5452static void
5453parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5454 char *stop;
5455 int qual;
5456 const char *truelab;
5457 const char *falselab;
5458 int extent;
5459{
5460 int c;
5461 int cc;
b3625fe6 5462 char *leftstart;
e1c0287d 5463 char *leftstop;
b3625fe6 5464 char *rightstart;
e1c0287d 5465 char *rightstop;
b4ec75e0
ILT		 5466
5467 c = *stop;
5468 *stop = '\0';
5469
5470 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5471 &rightstart, &rightstop))
5472 {
5473 *stop = c;
5474 return;
5475 }
5476
5477 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5478 {
5479 const char *flab;
5480
5481 if (falselab != NULL)
5482 flab = falselab;
5483 else
5484 flab = mri_control_label ();
5485
5486 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5487 rightstop, (const char *) NULL, flab, extent);
5488
5489 input_line_pointer += 3;
5490 if (*input_line_pointer != '.'
5491 || input_line_pointer[1] == '\0')
5492 qual = '\0';
5493 else
5494 {
5495 qual = input_line_pointer[1];
5496 input_line_pointer += 2;
5497 }
5498
5499 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5500 &rightstart, &rightstop))
5501 {
5502 *stop = c;
5503 return;
5504 }
5505
5506 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5507 rightstop, truelab, falselab, extent);
5508
5509 if (falselab == NULL)
5510 colon (flab);
5511 }
5512 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5513 {
5514 const char *tlab;
5515
5516 if (truelab != NULL)
5517 tlab = truelab;
5518 else
5519 tlab = mri_control_label ();
5520
5521 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5522 rightstop, tlab, (const char *) NULL, extent);
5523
5524 input_line_pointer += 2;
5525 if (*input_line_pointer != '.'
5526 || input_line_pointer[1] == '\0')
5527 qual = '\0';
5528 else
5529 {
5530 qual = input_line_pointer[1];
5531 input_line_pointer += 2;
5532 }
5533
5534 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5535 &rightstart, &rightstop))
5536 {
5537 *stop = c;
5538 return;
5539 }
5540
5541 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5542 rightstop, truelab, falselab, extent);
5543
5544 if (truelab == NULL)
5545 colon (tlab);
5546 }
5547 else
5548 {
5549 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5550 rightstop, truelab, falselab, extent);
5551 }
5552
5553 *stop = c;
5554 if (input_line_pointer != stop)
5555 as_bad ("syntax error in structured control directive");
5556}
5557
5558/* Handle the MRI IF pseudo-op. This may be a structured control
5559 directive, or it may be a regular assembler conditional, depending
5560 on its operands. */
5561
5562static void
5563s_mri_if (qual)
5564 int qual;
5565{
5566 char *s;
5567 int c;
5568 struct mri_control_info *n;
5569
5570 /* A structured control directive must end with THEN with an
5571 optional qualifier. */
5572 s = input_line_pointer;
e1c0287d
ILT		 5573 while (! is_end_of_line[(unsigned char) *s]
5574 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 5575 ++s;
5576 --s;
5577 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5578 --s;
5579
5580 if (s - input_line_pointer > 1
5581 && s[-1] == '.')
5582 s -= 2;
5583
5584 if (s - input_line_pointer < 3
5585 || strncasecmp (s - 3, "THEN", 4) != 0)
5586 {
5587 if (qual != '\0')
5588 {
5589 as_bad ("missing then");
5590 ignore_rest_of_line ();
5591 return;
5592 }
5593
5594 /* It's a conditional. */
5595 s_if (O_ne);
5596 return;
5597 }
5598
5599 /* Since this might be a conditional if, this pseudo-op will be
5600 called even if we are supported to be ignoring input. Double
5601 check now. Clobber *input_line_pointer so that ignore_input
5602 thinks that this is not a special pseudo-op. */
5603 c = *input_line_pointer;
5604 *input_line_pointer = 0;
5605 if (ignore_input ())
5606 {
5607 *input_line_pointer = c;
5608 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5609 ++input_line_pointer;
5610 demand_empty_rest_of_line ();
5611 return;
5612 }
5613 *input_line_pointer = c;
5614
5615 n = push_mri_control (mri_if);
5616
5617 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5618 n->next, s[1] == '.' ? s[2] : '\0');
5619
5620 if (s[1] == '.')
5621 input_line_pointer = s + 3;
5622 else
5623 input_line_pointer = s + 1;
5624
e1c0287d
ILT		 5625 if (flag_mri)
5626 {
5627 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5628 ++input_line_pointer;
5629 }
5630
b4ec75e0
ILT		 5631 demand_empty_rest_of_line ();
5632}
5633
5634/* Handle the MRI else pseudo-op. If we are currently doing an MRI
5635 structured IF, associate the ELSE with the IF. Otherwise, assume
5636 it is a conditional else. */
5637
5638static void
5639s_mri_else (qual)
5640 int qual;
5641{
5642 int c;
5643 char *buf;
5644 char q[2];
5645
5646 if (qual == '\0'
5647 && (mri_control_stack == NULL
5648 || mri_control_stack->type != mri_if
5649 || mri_control_stack->else_seen))
5650 {
5651 s_else (0);
5652 return;
5653 }
5654
5655 c = *input_line_pointer;
5656 *input_line_pointer = 0;
5657 if (ignore_input ())
5658 {
5659 *input_line_pointer = c;
5660 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5661 ++input_line_pointer;
5662 demand_empty_rest_of_line ();
5663 return;
5664 }
5665 *input_line_pointer = c;
5666
5667 if (mri_control_stack == NULL
5668 || mri_control_stack->type != mri_if
5669 || mri_control_stack->else_seen)
5670 {
5671 as_bad ("else without matching if");
5672 ignore_rest_of_line ();
5673 return;
5674 }
5675
5676 mri_control_stack->else_seen = 1;
5677
5678 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5679 q[0] = qual;
5680 q[1] = '\0';
5681 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5682 md_assemble (buf);
5683 free (buf);
5684
5685 colon (mri_control_stack->next);
5686
e1c0287d
ILT		 5687 if (flag_mri)
5688 {
5689 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5690 ++input_line_pointer;
5691 }
5692
b4ec75e0
ILT		 5693 demand_empty_rest_of_line ();
5694}
5695
5696/* Handle the MRI ENDI pseudo-op. */
5697
5698static void
5699s_mri_endi (ignore)
5700 int ignore;
5701{
5702 if (mri_control_stack == NULL
5703 || mri_control_stack->type != mri_if)
5704 {
5705 as_bad ("endi without matching if");
5706 ignore_rest_of_line ();
5707 return;
5708 }
5709
5710 /* ignore_input will not return true for ENDI, so we don't need to
5711 worry about checking it again here. */
5712
5713 if (! mri_control_stack->else_seen)
5714 colon (mri_control_stack->next);
5715 colon (mri_control_stack->bottom);
5716
5717 pop_mri_control ();
5718
e1c0287d
ILT		 5719 if (flag_mri)
5720 {
5721 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5722 ++input_line_pointer;
5723 }
5724
b4ec75e0
ILT		 5725 demand_empty_rest_of_line ();
5726}
5727
5728/* Handle the MRI BREAK pseudo-op. */
5729
5730static void
5731s_mri_break (extent)
5732 int extent;
5733{
5734 struct mri_control_info *n;
5735 char *buf;
5736 char ex[2];
5737
5738 n = mri_control_stack;
5739 while (n != NULL
5740 && n->type != mri_for
5741 && n->type != mri_repeat
5742 && n->type != mri_while)
5743 n = n->outer;
5744 if (n == NULL)
5745 {
5746 as_bad ("break outside of structured loop");
5747 ignore_rest_of_line ();
5748 return;
5749 }
5750
5751 buf = (char *) xmalloc (20 + strlen (n->bottom));
5752 ex[0] = extent;
5753 ex[1] = '\0';
5754 sprintf (buf, "bra%s %s", ex, n->bottom);
5755 md_assemble (buf);
5756 free (buf);
5757
e1c0287d
ILT		 5758 if (flag_mri)
5759 {
5760 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5761 ++input_line_pointer;
5762 }
5763
b4ec75e0
ILT		 5764 demand_empty_rest_of_line ();
5765}
5766
5767/* Handle the MRI NEXT pseudo-op. */
5768
5769static void
5770s_mri_next (extent)
5771 int extent;
5772{
5773 struct mri_control_info *n;
5774 char *buf;
5775 char ex[2];
5776
5777 n = mri_control_stack;
5778 while (n != NULL
5779 && n->type != mri_for
5780 && n->type != mri_repeat
5781 && n->type != mri_while)
5782 n = n->outer;
5783 if (n == NULL)
5784 {
5785 as_bad ("next outside of structured loop");
5786 ignore_rest_of_line ();
5787 return;
5788 }
5789
5790 buf = (char *) xmalloc (20 + strlen (n->next));
5791 ex[0] = extent;
5792 ex[1] = '\0';
5793 sprintf (buf, "bra%s %s", ex, n->next);
5794 md_assemble (buf);
5795 free (buf);
5796
e1c0287d
ILT		 5797 if (flag_mri)
5798 {
5799 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5800 ++input_line_pointer;
5801 }
5802
b4ec75e0
ILT		 5803 demand_empty_rest_of_line ();
5804}
5805
5806/* Handle the MRI FOR pseudo-op. */
5807
5808static void
5809s_mri_for (qual)
5810 int qual;
5811{
5812 const char *varstart, *varstop;
5813 const char *initstart, *initstop;
5814 const char *endstart, *endstop;
5815 const char *bystart, *bystop;
5816 int up;
5817 int by;
5818 int extent;
5819 struct mri_control_info *n;
5820 char *buf;
5821 char *s;
5822 char ex[2];
5823
5824 /* The syntax is
5825 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5826 */
5827
4026c122 5828 SKIP_WHITESPACE ();
b4ec75e0
ILT		 5829 varstart = input_line_pointer;
5830
5831 /* Look for the '='. */
5832 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5833 && *input_line_pointer != '=')
5834 ++input_line_pointer;
5835 if (*input_line_pointer != '=')
5836 {
5837 as_bad ("missing =");
5838 ignore_rest_of_line ();
5839 return;
5840 }
5841
5842 varstop = input_line_pointer;
4026c122
ILT		 5843 if (varstop > varstart
5844 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5845 --varstop;
b4ec75e0
ILT		 5846
5847 ++input_line_pointer;
5848
5849 initstart = input_line_pointer;
5850
5851 /* Look for TO or DOWNTO. */
5852 up = 1;
5853 initstop = NULL;
5854 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5855 {
5856 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5857 && ! is_part_of_name (input_line_pointer[2]))
5858 {
5859 initstop = input_line_pointer;
5860 input_line_pointer += 2;
5861 break;
5862 }
5863 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5864 && ! is_part_of_name (input_line_pointer[6]))
5865 {
5866 initstop = input_line_pointer;
5867 up = 0;
5868 input_line_pointer += 6;
5869 break;
5870 }
5871 ++input_line_pointer;
5872 }
5873 if (initstop == NULL)
5874 {
5875 as_bad ("missing to or downto");
5876 ignore_rest_of_line ();
5877 return;
5878 }
4026c122
ILT		 5879 if (initstop > initstart
5880 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5881 --initstop;
b4ec75e0 5882
4026c122 5883 SKIP_WHITESPACE ();
b4ec75e0
ILT		 5884 endstart = input_line_pointer;
5885
5886 /* Look for BY or DO. */
5887 by = 0;
5888 endstop = NULL;
5889 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5890 {
5891 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5892 && ! is_part_of_name (input_line_pointer[2]))
5893 {
5894 endstop = input_line_pointer;
5895 by = 1;
5896 input_line_pointer += 2;
5897 break;
5898 }
5899 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5900 && (input_line_pointer[2] == '.'
5901 || ! is_part_of_name (input_line_pointer[2])))
5902 {
5903 endstop = input_line_pointer;
5904 input_line_pointer += 2;
5905 break;
5906 }
5907 ++input_line_pointer;
5908 }
5909 if (endstop == NULL)
5910 {
5911 as_bad ("missing do");
5912 ignore_rest_of_line ();
5913 return;
5914 }
4026c122
ILT		 5915 if (endstop > endstart
5916 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5917 --endstop;
b4ec75e0
ILT		 5918
5919 if (! by)
5920 {
5921 bystart = "#1";
5922 bystop = bystart + 2;
5923 }
5924 else
5925 {
4026c122 5926 SKIP_WHITESPACE ();
b4ec75e0
ILT		 5927 bystart = input_line_pointer;
5928
5929 /* Look for DO. */
5930 bystop = NULL;
5931 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5932 {
5933 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5934 && (input_line_pointer[2] == '.'
5935 || ! is_part_of_name (input_line_pointer[2])))
5936 {
5937 bystop = input_line_pointer;
5938 input_line_pointer += 2;
5939 break;
5940 }
5941 ++input_line_pointer;
5942 }
5943 if (bystop == NULL)
5944 {
5945 as_bad ("missing do");
5946 ignore_rest_of_line ();
5947 return;
5948 }
4026c122
ILT		 5949 if (bystop > bystart
5950 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5951 --bystop;
b4ec75e0
ILT		 5952 }
5953
5954 if (*input_line_pointer != '.')
5955 extent = '\0';
5956 else
5957 {
5958 extent = input_line_pointer[1];
5959 input_line_pointer += 2;
5960 }
5961
5962 /* We have fully parsed the FOR operands. Now build the loop. */
5963
5964 n = push_mri_control (mri_for);
5965
5966 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5967
5968 /* move init,var */
5969 s = buf;
5970 *s++ = 'm';
5971 *s++ = 'o';
5972 *s++ = 'v';
5973 *s++ = 'e';
5974 if (qual != '\0')
5975 *s++ = qual;
5976 *s++ = ' ';
5977 memcpy (s, initstart, initstop - initstart);
5978 s += initstop - initstart;
5979 *s++ = ',';
5980 memcpy (s, varstart, varstop - varstart);
5981 s += varstop - varstart;
5982 *s = '\0';
5983 md_assemble (buf);
5984
5985 colon (n->top);
5986
5987 /* cmp end,var */
5988 s = buf;
5989 *s++ = 'c';
5990 *s++ = 'm';
5991 *s++ = 'p';
5992 if (qual != '\0')
5993 *s++ = qual;
5994 *s++ = ' ';
5995 memcpy (s, endstart, endstop - endstart);
5996 s += endstop - endstart;
5997 *s++ = ',';
5998 memcpy (s, varstart, varstop - varstart);
5999 s += varstop - varstart;
6000 *s = '\0';
6001 md_assemble (buf);
6002
6003 /* bcc bottom */
6004 ex[0] = extent;
6005 ex[1] = '\0';
6006 if (up)
6007 sprintf (buf, "blt%s %s", ex, n->bottom);
6008 else
6009 sprintf (buf, "bgt%s %s", ex, n->bottom);
6010 md_assemble (buf);
6011
6012 /* Put together the add or sub instruction used by ENDF. */
6013 s = buf;
6014 if (up)
6015 strcpy (s, "add");
6016 else
6017 strcpy (s, "sub");
6018 s += 3;
6019 if (qual != '\0')
6020 *s++ = qual;
6021 *s++ = ' ';
6022 memcpy (s, bystart, bystop - bystart);
6023 s += bystop - bystart;
6024 *s++ = ',';
6025 memcpy (s, varstart, varstop - varstart);
6026 s += varstop - varstart;
6027 *s = '\0';
6028 n->incr = buf;
6029
e1c0287d
ILT		 6030 if (flag_mri)
6031 {
6032 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6033 ++input_line_pointer;
6034 }
6035
b4ec75e0
ILT		 6036 demand_empty_rest_of_line ();
6037}
6038
6039/* Handle the MRI ENDF pseudo-op. */
6040
6041static void
6042s_mri_endf (ignore)
6043 int ignore;
6044{
6045 if (mri_control_stack == NULL
6046 || mri_control_stack->type != mri_for)
6047 {
6048 as_bad ("endf without for");
6049 ignore_rest_of_line ();
6050 return;
6051 }
6052
6053 colon (mri_control_stack->next);
6054
6055 md_assemble (mri_control_stack->incr);
6056
6057 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6058 md_assemble (mri_control_stack->incr);
6059
6060 free (mri_control_stack->incr);
6061
6062 colon (mri_control_stack->bottom);
6063
6064 pop_mri_control ();
6065
e1c0287d
ILT		 6066 if (flag_mri)
6067 {
6068 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6069 ++input_line_pointer;
6070 }
6071
b4ec75e0
ILT		 6072 demand_empty_rest_of_line ();
6073}
6074
6075/* Handle the MRI REPEAT pseudo-op. */
6076
6077static void
6078s_mri_repeat (ignore)
6079 int ignore;
6080{
6081 struct mri_control_info *n;
6082
6083 n = push_mri_control (mri_repeat);
6084 colon (n->top);
e1c0287d
ILT		 6085 if (flag_mri)
6086 {
6087 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6088 ++input_line_pointer;
6089 }
b4ec75e0
ILT		 6090 demand_empty_rest_of_line ();
6091}
6092
6093/* Handle the MRI UNTIL pseudo-op. */
6094
6095static void
6096s_mri_until (qual)
6097 int qual;
6098{
6099 char *s;
6100
6101 if (mri_control_stack == NULL
6102 || mri_control_stack->type != mri_repeat)
6103 {
6104 as_bad ("until without repeat");
6105 ignore_rest_of_line ();
6106 return;
6107 }
6108
6109 colon (mri_control_stack->next);
6110
6111 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6112 ;
6113
6114 parse_mri_control_expression (s, qual, (const char *) NULL,
6115 mri_control_stack->top, '\0');
6116
6117 colon (mri_control_stack->bottom);
6118
6119 input_line_pointer = s;
6120
9e64486e
ILT		 6121 pop_mri_control ();
6122
e1c0287d
ILT		 6123 if (flag_mri)
6124 {
6125 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6126 ++input_line_pointer;
6127 }
6128
b4ec75e0
ILT		 6129 demand_empty_rest_of_line ();
6130}
6131
6132/* Handle the MRI WHILE pseudo-op. */
6133
6134static void
6135s_mri_while (qual)
6136 int qual;
6137{
6138 char *s;
6139
6140 struct mri_control_info *n;
6141
6142 s = input_line_pointer;
e1c0287d
ILT		 6143 while (! is_end_of_line[(unsigned char) *s]
6144 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 6145 s++;
6146 --s;
6147 while (*s == ' ' || *s == '\t')
6148 --s;
6149 if (s - input_line_pointer > 1
6150 && s[-1] == '.')
6151 s -= 2;
6152 if (s - input_line_pointer < 2
6153 || strncasecmp (s - 1, "DO", 2) != 0)
6154 {
6155 as_bad ("missing do");
6156 ignore_rest_of_line ();
6157 return;
6158 }
6159
6160 n = push_mri_control (mri_while);
6161
6162 colon (n->next);
6163
6164 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6165 s[1] == '.' ? s[2] : '\0');
6166
6167 input_line_pointer = s + 1;
6168 if (*input_line_pointer == '.')
6169 input_line_pointer += 2;
6170
e1c0287d
ILT		 6171 if (flag_mri)
6172 {
6173 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6174 ++input_line_pointer;
6175 }
6176
b4ec75e0
ILT		 6177 demand_empty_rest_of_line ();
6178}
6179
6180/* Handle the MRI ENDW pseudo-op. */
6181
6182static void
6183s_mri_endw (ignore)
6184 int ignore;
6185{
6186 char *buf;
6187
6188 if (mri_control_stack == NULL
6189 || mri_control_stack->type != mri_while)
6190 {
6191 as_bad ("endw without while");
6192 ignore_rest_of_line ();
6193 return;
6194 }
6195
6196 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6197 sprintf (buf, "bra %s", mri_control_stack->next);
6198 md_assemble (buf);
6199 free (buf);
6200
6201 colon (mri_control_stack->bottom);
6202
6203 pop_mri_control ();
6204
e1c0287d
ILT		 6205 if (flag_mri)
6206 {
6207 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6208 ++input_line_pointer;
6209 }
6210
b4ec75e0
ILT		 6211 demand_empty_rest_of_line ();
6212}
f3d817d8 6213\f
7c15cbe8
RP		 6214/*
6215 * md_parse_option
6216 * Invocation line includes a switch not recognized by the base assembler.
6217 * See if it's a processor-specific option. These are:
6218 *
6219 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6220 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6221 * Select the architecture. Instructions or features not
6222 * supported by the selected architecture cause fatal
6223 * errors. More than one may be specified. The default is
6224 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6225 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 6226 * -[A]m[c]no-68851, -[A]m[c]no-68881
6227 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6228 * so don't use or document it, but that's the way the parsing
6229 * works).
7c15cbe8 6230 *
dff60b7d
ILT		 6231 * -pic Indicates PIC.
6232 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 6233 *
8d20a0a8
C		 6234 * --bitwise-or
6235 * Permit `|' to be used in expressions.
6236 *
7c15cbe8
RP		 6237 */
6238
5f8cb05e
ILT		 6239#ifdef OBJ_ELF
6240CONST char *md_shortopts = "lSA:m:kQ:V";
6241#else
f3d817d8 6242CONST char *md_shortopts = "lSA:m:k";
5f8cb05e
ILT		 6243#endif
6244
f3d817d8
DM		 6245struct option md_longopts[] = {
6246#define OPTION_PIC (OPTION_MD_BASE)
6247 {"pic", no_argument, NULL, OPTION_PIC},
6248#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6249 {"register-prefix-optional", no_argument, NULL,
6250 OPTION_REGISTER_PREFIX_OPTIONAL},
8d20a0a8
C		 6251#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6252 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
f3d817d8
DM		 6253 {NULL, no_argument, NULL, 0}
6254};
6255size_t md_longopts_size = sizeof(md_longopts);
82489ea0 6256
355afbcd 6257int
f3d817d8
DM		 6258md_parse_option (c, arg)
6259 int c;
6260 char *arg;
fecd2382 6261{
f3d817d8 6262 switch (c)
355afbcd
KR		 6263 {
6264 case 'l': /* -l means keep external to 2 bit offset
e284846a 6265 rather than 16 bit one */
9ad5755f 6266 flag_short_refs = 1;
355afbcd 6267 break;
6d27d3a2 6268
e284846a
KR		 6269 case 'S': /* -S means that jbsr's always turn into
6270 jsr's. */
9ad5755f 6271 flag_long_jumps = 1;
355afbcd 6272 break;
6d27d3a2 6273
355afbcd 6274 case 'A':
f3d817d8
DM		 6275 if (*arg == 'm')
6276 arg++;
355afbcd
KR		 6277 /* intentional fall-through */
6278 case 'm':
355afbcd 6279
b79de3a1 6280 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
e284846a 6281 {
064ba683
ILT		 6282 int i;
6283 unsigned long arch;
b79de3a1
KR		 6284 const char *oarg = arg;
6285
6286 arg += 3;
6287 if (*arg == 'm')
6288 {
6289 arg++;
6290 if (arg[0] == 'c' && arg[1] == '6')
6291 arg++;
6292 }
6293 for (i = 0; i < n_archs; i++)
6294 if (!strcmp (arg, archs[i].name))
6295 break;
6296 if (i == n_archs)
6297 {
6298 unknown:
6299 as_bad ("unrecognized option `%s'", oarg);
6300 return 0;
6301 }
6302 arch = archs[i].arch;
6303 if (arch == m68881)
6304 no_68881 = 1;
6305 else if (arch == m68851)
6306 no_68851 = 1;
6307 else
6308 goto unknown;
355afbcd
KR		 6309 }
6310 else
6311 {
b79de3a1
KR		 6312 int i;
6313
6314 if (arg[0] == 'c' && arg[1] == '6')
6315 arg++;
6316
6317 for (i = 0; i < n_archs; i++)
6318 if (!strcmp (arg, archs[i].name))
6319 {
6320 unsigned long arch = archs[i].arch;
6321 if (cpu_of_arch (arch))
6322 /* It's a cpu spec. */
6323 {
6324 current_architecture &= ~m68000up;
6325 current_architecture |= arch;
6326 }
6327 else if (arch == m68881)
6328 {
6329 current_architecture |= m68881;
6330 no_68881 = 0;
6331 }
6332 else if (arch == m68851)
6333 {
6334 current_architecture |= m68851;
6335 no_68851 = 0;
6336 }
6337 else
6338 /* ??? */
6339 abort ();
6340 break;
6341 }
6342 if (i == n_archs)
6343 {
6344 as_bad ("unrecognized architecture specification `%s'", arg);
6345 return 0;
6346 }
f8701a3f 6347 }
f3d817d8 6348 break;
dff60b7d 6349
f3d817d8 6350 case OPTION_PIC:
dff60b7d
ILT		 6351 case 'k':
6352 flag_want_pic = 1;
f3d817d8
DM		 6353 break; /* -pic, Position Independent Code */
6354
6355 case OPTION_REGISTER_PREFIX_OPTIONAL:
6356 flag_reg_prefix_optional = 1;
20710f1c 6357 reg_prefix_optional_seen = 1;
dff60b7d 6358 break;
355afbcd 6359
a043f579 6360 /* -V: SVR4 argument to print version ID. */
5f8cb05e 6361 case 'V':
a043f579
ILT		 6362 print_version_id ();
6363 break;
6364
6365 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6366 should be emitted or not. FIXME: Not implemented. */
6367 case 'Q':
5f8cb05e
ILT		 6368 break;
6369
8d20a0a8
C		 6370 case OPTION_BITWISE_OR:
6371 {
6372 char *n, *t;
6373 const char *s;
6374
6375 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6376 t = n;
6377 for (s = m68k_comment_chars; *s != '\0'; s++)
6378 if (*s != '|')
6379 *t++ = *s;
6380 *t = '\0';
6381 m68k_comment_chars = n;
6382 }
6383 break;
6384
355afbcd
KR		 6385 default:
6386 return 0;
6387 }
f3d817d8 6388
355afbcd 6389 return 1;
fecd2382
RP		 6390}
6391
f3d817d8
DM		 6392void
6393md_show_usage (stream)
6394 FILE *stream;
6395{
6396 fprintf(stream, "\
6397680X0 options:\n\
6398-l use 1 word for refs to undefined symbols [default 2]\n\
5f8cb05e
ILT		 6399-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6400 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
7f003b7f 6401 | -mcpu32 | -m5200\n\
f3d817d8
DM		 6402 specify variant of 680X0 architecture [default 68020]\n\
6403-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6404 target has/lacks floating-point coprocessor\n\
92a25e12
ILT		 6405 [default yes for 68020, 68030, and cpu32]\n");
6406 fprintf(stream, "\
f3d817d8
DM		 6407-m68851 | -mno-68851\n\
6408 target has/lacks memory-management unit coprocessor\n\
6409 [default yes for 68020 and up]\n\
6410-pic, -k generate position independent code\n\
6411-S turn jbsr into jsr\n\
6412--register-prefix-optional\n\
8d20a0a8
C		 6413 recognize register names without prefix character\n\
6414--bitwise-or do not treat `|' as a comment character\n");
f3d817d8
DM		 6415}
6416\f
fecd2382
RP		 6417#ifdef TEST2
6418
6419/* TEST2: Test md_assemble() */
6420/* Warning, this routine probably doesn't work anymore */
6421
355afbcd 6422main ()
fecd2382 6423{
355afbcd
KR		 6424 struct m68k_it the_ins;
6425 char buf[120];
6426 char *cp;
6427 int n;
6428
6429 m68k_ip_begin ();
6430 for (;;)
6431 {
6432 if (!gets (buf) || !*buf)
6433 break;
6434 if (buf[0] == '|' || buf[1] == '.')
6435 continue;
6436 for (cp = buf; *cp; cp++)
6437 if (*cp == '\t')
6438 *cp = ' ';
6439 if (is_label (buf))
6440 continue;
6441 memset (&the_ins, '\0', sizeof (the_ins));
6442 m68k_ip (&the_ins, buf);
6443 if (the_ins.error)
6444 {
6445 printf ("Error %s in %s\n", the_ins.error, buf);
6446 }
6447 else
6448 {
6449 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6450 for (n = 0; n < the_ins.numo; n++)
6451 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6452 printf (" ");
6453 print_the_insn (&the_ins.opcode[0], stdout);
6454 (void) putchar ('\n');
6455 }
6456 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6457 {
6458 if (the_ins.operands[n].error)
6459 {
6460 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6461 continue;
6462 }
6463 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6464 if (the_ins.operands[n].b_const)
6465 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6466 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6467 if (the_ins.operands[n].b_iadd)
6468 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6469 (void) putchar ('\n');
a39116f1 6470 }
355afbcd
KR		 6471 }
6472 m68k_ip_end ();
6473 return 0;
fecd2382
RP		 6474}
6475
355afbcd
KR		 6476is_label (str)
6477 char *str;
fecd2382 6478{
355afbcd
KR		 6479 while (*str == ' ')
6480 str++;
6481 while (*str && *str != ' ')
6482 str++;
6483 if (str[-1] == ':' || str[1] == '=')
6484 return 1;
6485 return 0;
fecd2382
RP		 6486}
6487
6488#endif
6489
6490/* Possible states for relaxation:
6d27d3a2 6491
a39116f1
RP		 6492 0 0 branch offset byte (bra, etc)
6493 0 1 word
6494 0 2 long
6d27d3a2 6495
a39116f1
RP		 6496 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6497 1 1 word
6498 1 2 long
6d27d3a2 6499
a39116f1
RP		 6500 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6501 2 1 word-long
6502 2 2 long-word
6503 2 3 long-long
6d27d3a2 6504
a39116f1 6505 */
fecd2382 6506
fecd2382
RP		 6507/* We have no need to default values of symbols. */
6508
6509/* ARGSUSED */
6510symbolS *
355afbcd
KR		 6511md_undefined_symbol (name)
6512 char *name;
fecd2382 6513{
355afbcd 6514 return 0;
fecd2382
RP		 6515}
6516
fecd2382 6517/* Round up a section size to the appropriate boundary. */
025b0302 6518valueT
355afbcd
KR		 6519md_section_align (segment, size)
6520 segT segment;
025b0302 6521 valueT size;
fecd2382 6522{
355afbcd 6523 return size; /* Byte alignment is fine */
fecd2382
RP		 6524}
6525
6526/* Exactly what point is a PC-relative offset relative TO?
5f8cb05e
ILT		 6527 On the 68k, it is relative to the address of the first extension
6528 word. The difference between the addresses of the offset and the
6529 first extension word is stored in fx_pcrel_adjust. */
fecd2382 6530long
355afbcd
KR		 6531md_pcrel_from (fixP)
6532 fixS *fixP;
fecd2382 6533{
b4ec75e0
ILT		 6534 int adjust;
6535
6536 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6537 -1 as 64. */
6538 adjust = fixP->fx_pcrel_adjust;
6539 if (adjust == 64)
6540 adjust = -1;
6541 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
fecd2382
RP		 6542}
6543
49864cfa 6544#ifndef BFD_ASSEMBLER
9ad5755f 6545/*ARGSUSED*/
355afbcd 6546void
9ad5755f
KR		 6547tc_coff_symbol_emit_hook (ignore)
6548 symbolS *ignore;
3ad9ec6a
ILT		 6549{
6550}
6551
355afbcd
KR		 6552int
6553tc_coff_sizemachdep (frag)
6554 fragS *frag;
3ad9ec6a 6555{
355afbcd
KR		 6556 switch (frag->fr_subtype & 0x3)
6557 {
6558 case BYTE:
6559 return 1;
6560 case SHORT:
6561 return 2;
6562 case LONG:
6563 return 4;
6564 default:
6565 abort ();
064ba683 6566 return 0;
355afbcd 6567 }
3ad9ec6a 6568}
49864cfa 6569#endif
355afbcd 6570
fecd2382 6571/* end of tc-m68k.c */
GDB Binutils - Deliverables
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