projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* Makefile.in (@COMMON_MAKEFILE_FRAG@): Use
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a1c7c0f3 1/* tc-m68k.c -- Assemble for the m68k family
b4d51f3d
ILT		 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
6d27d3a2 4
a39116f1 5 This file is part of GAS, the GNU Assembler.
6d27d3a2 6
a39116f1
RP		 7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
6d27d3a2 11
a39116f1
RP		 12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
6d27d3a2 16
a39116f1 17 You should have received a copy of the GNU General Public License
a1c7c0f3
ILT		 18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
fecd2382
RP		 21
22#include <ctype.h>
fecd2382 23#include "as.h"
fecd2382 24#include "obstack.h"
b4ec75e0 25#include "subsegs.h"
fecd2382 26
e0982afe 27#include "opcode/m68k.h"
a1c7c0f3 28#include "m68k-parse.h"
3ad9ec6a 29
8d20a0a8
C		 30/* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
65feb78d 34#if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
8d20a0a8 35const char *m68k_comment_chars = "|#";
5f8cb05e 36#else
8d20a0a8 37const char *m68k_comment_chars = "|";
5f8cb05e 38#endif
fecd2382
RP		 39
40/* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43/* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46/* Also note that comments like this one will always work. */
326b087c 47const char line_comment_chars[] = "#";
fecd2382 48
326b087c 49const char line_separator_chars[] = "";
587c4264 50
fecd2382 51/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 52CONST char EXP_CHARS[] = "eE";
fecd2382 53
49864cfa
KR		 54/* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
fecd2382 56
49864cfa 57CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 58
59/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 61 but nothing is ideal around here. */
fecd2382 62
49864cfa 63const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 64
b80d39a0 65/* Are we trying to generate PIC code? If so, absolute references
dff60b7d 66 ought to be made into linkage table references or pc-relative
a043f579
ILT		 67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
b80d39a0
KR		 69int flag_want_pic;
70
9ad5755f
KR		 71static int flag_short_refs; /* -l option */
72static int flag_long_jumps; /* -S option */
73
82489ea0
KR		 74#ifdef REGISTER_PREFIX_OPTIONAL
75int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76#else
77int flag_reg_prefix_optional;
78#endif
79
20710f1c
ILT		 80/* Whether --register-prefix-optional was used on the command line. */
81static int reg_prefix_optional_seen;
82
27a53b88
ILT		 83/* The floating point coprocessor to use by default. */
84static enum m68k_register m68k_float_copnum = COP1;
85
6700d36e
ILT		 86/* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88static int m68k_abspcadd;
89
90/* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92static int m68k_quick = 1;
93
94/* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97static int m68k_rel32 = 1;
98
924160b0
ILT		 99/* This is non-zero if m68k_rel32 was set from the command line. */
100static int m68k_rel32_from_cmdline;
101
b4d51f3d
ILT		 102/* The default width to use for an index register when using a base
103 displacement. */
104static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
d703b5a7
ILT		 106/* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110struct label_line
111{
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117};
118
119/* The list of labels. */
120
121static struct label_line *labels;
122
123/* The current label. */
124
125static struct label_line *current_label;
126
fecd2382
RP		 127/* Its an arbitrary name: This means I don't approve of it */
128/* See flames below */
129static struct obstack robyn;
130
131#define TAB(x,y) (((x)<<2)+(y))
132#define TABTYPE(xy) ((xy) >> 2)
133#define BYTE 0
134#define SHORT 1
135#define LONG 2
136#define SZ_UNDEF 3
3ad9ec6a 137#undef BRANCH
04ef74bb 138/* Case `g' except when BCC68000 is applicable. */
3ad9ec6a 139#define ABRANCH 1
04ef74bb 140/* Coprocessor branches. */
fecd2382 141#define FBRANCH 2
04ef74bb
KR		 142/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
fecd2382 144#define PCREL 3
04ef74bb
KR		 145/* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
fecd2382 150#define BCC68000 4
04ef74bb
KR		 151/* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
fecd2382 153#define DBCC 5
04ef74bb 154/* Not currently used? */
fecd2382 155#define PCLEA 6
04ef74bb
KR		 156/* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158#define PCINDEX 7
fecd2382 159
bcb8dff8
KR		 160struct m68k_incant
161 {
a1c7c0f3 162 const char *m_operands;
bcb8dff8
KR		 163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171#define gettwo(x) (((x)->m_opcode)&0xffff)
172
a1c7c0f3
ILT		 173static const enum m68k_register m68000_control_regs[] = { 0 };
174static const enum m68k_register m68010_control_regs[] = {
82489ea0
KR		 175 SFC, DFC, USP, VBR,
176 0
177};
a1c7c0f3 178static const enum m68k_register m68020_control_regs[] = {
82489ea0
KR		 179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181};
a1c7c0f3 182static const enum m68k_register m68040_control_regs[] = {
82489ea0
KR		 183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186};
a1c7c0f3 187static const enum m68k_register m68060_control_regs[] = {
82489ea0
KR		 188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191};
8d20a0a8
C		 192static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196};
b79de3a1 197#define cpu32_control_regs m68010_control_regs
82489ea0 198
a1c7c0f3 199static const enum m68k_register *control_regs;
fecd2382
RP		 200
201/* internal form of a 68020 instruction */
355afbcd 202struct m68k_it
a1c7c0f3
ILT		 203{
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
355afbcd 207
a1c7c0f3
ILT		 208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
355afbcd 210
a1c7c0f3 211 struct m68k_op operands[6];
355afbcd 212
a1c7c0f3
ILT		 213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
355afbcd 215
a1c7c0f3
ILT		 216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 long foff;
222 int fragty;
223 }
224 fragb[4];
355afbcd 225
a1c7c0f3
ILT		 226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
a043f579
ILT		 241#ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245#endif
a1c7c0f3
ILT		 246 }
247 reloc[5]; /* Five is enough??? */
248};
fecd2382 249
8d20a0a8 250#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
865a2edf
MT		 251#define float_of_arch(x) ((x) & mfloat)
252#define mmu_of_arch(x) ((x) & mmmu)
253
ffecfc8b
C		 254/* Macros for determining if cpu supports a specific addressing mode */
255#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
355afbcd 257static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 258
a1c7c0f3
ILT		 259#define op(ex) ((ex)->exp.X_op)
260#define adds(ex) ((ex)->exp.X_add_symbol)
261#define subs(ex) ((ex)->exp.X_op_symbol)
262#define offs(ex) ((ex)->exp.X_add_number)
49864cfa 263
7c15cbe8 264/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 265
266#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 269static void
270insop (w, opcode)
271 int w;
272 struct m68k_incant *opcode;
273{
274 int z;
275 for(z=the_ins.numo;z>opcode->m_codenum;--z)
276 the_ins.opcode[z]=the_ins.opcode[z-1];
277 for(z=0;z<the_ins.nrel;z++)
278 the_ins.reloc[z].n+=2;
5f8cb05e
ILT		 279 for (z = 0; z < the_ins.nfrag; z++)
280 the_ins.fragb[z].fragoff++;
bcb8dff8
KR		 281 the_ins.opcode[opcode->m_codenum]=w;
282 the_ins.numo++;
283}
fecd2382 284
1404ef23
KR		 285/* The numo+1 kludge is so we can hit the low order byte of the prev word.
286 Blecch. */
49864cfa 287static void
5f8cb05e 288add_fix (width, exp, pc_rel, pc_fix)
49864cfa
KR		 289 char width;
290 struct m68k_exp *exp;
291 int pc_rel;
5f8cb05e 292 int pc_fix;
49864cfa 293{
0b810a6e 294 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
49864cfa
KR		 295 ? (the_ins.numo*2-1)
296 : (((width)=='b')
5f8cb05e 297 ? (the_ins.numo*2+1)
49864cfa 298 : (the_ins.numo*2)));
a1c7c0f3 299 the_ins.reloc[the_ins.nrel].exp = exp->exp;
49864cfa 300 the_ins.reloc[the_ins.nrel].wid = width;
5f8cb05e 301 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
a043f579
ILT		 302#ifdef OBJ_ELF
303 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
304#endif
49864cfa 305 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 306}
307
5f8cb05e
ILT		 308/* Cause an extra frag to be generated here, inserting up to 10 bytes
309 (that value is chosen in the frag_var call in md_assemble). TYPE
310 is the subtype of the frag to be generated; its primary type is
311 rs_machine_dependent.
312
313 The TYPE parameter is also used by md_convert_frag_1 and
314 md_estimate_size_before_relax. The appropriate type of fixup will
315 be emitted by md_convert_frag_1.
316
317 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
49864cfa
KR		 318static void
319add_frag(add,off,type)
320 symbolS *add;
321 long off;
322 int type;
323{
324 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
325 the_ins.fragb[the_ins.nfrag].fadd=add;
326 the_ins.fragb[the_ins.nfrag].foff=off;
327 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 328}
fecd2382 329
a1c7c0f3
ILT		 330#define isvar(ex) \
331 (op (ex) != O_constant && op (ex) != O_big)
fecd2382 332
49864cfa
KR		 333static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
334static int get_num PARAMS ((struct m68k_exp *exp, int ok));
49864cfa
KR		 335static int reverse_16_bits PARAMS ((int in));
336static int reverse_8_bits PARAMS ((int in));
49864cfa
KR		 337static void install_gen_operand PARAMS ((int mode, int val));
338static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 339static void s_bss PARAMS ((int));
340static void s_data1 PARAMS ((int));
341static void s_data2 PARAMS ((int));
342static void s_even PARAMS ((int));
343static void s_proc PARAMS ((int));
e9bb39b4
ILT		 344static void mri_chip PARAMS ((void));
345static void s_chip PARAMS ((int));
27a53b88 346static void s_fopt PARAMS ((int));
6700d36e
ILT		 347static void s_opt PARAMS ((int));
348static void s_reg PARAMS ((int));
e14994d9
ILT		 349static void s_restore PARAMS ((int));
350static void s_save PARAMS ((int));
b4ec75e0
ILT		 351static void s_mri_if PARAMS ((int));
352static void s_mri_else PARAMS ((int));
353static void s_mri_endi PARAMS ((int));
354static void s_mri_break PARAMS ((int));
355static void s_mri_next PARAMS ((int));
356static void s_mri_for PARAMS ((int));
357static void s_mri_endf PARAMS ((int));
358static void s_mri_repeat PARAMS ((int));
359static void s_mri_until PARAMS ((int));
360static void s_mri_while PARAMS ((int));
361static void s_mri_endw PARAMS ((int));
49864cfa
KR		 362
363static int current_architecture;
7c15cbe8 364
b79de3a1
KR		 365struct m68k_cpu {
366 unsigned long arch;
367 const char *name;
9e64486e 368 int alias;
b79de3a1
KR		 369};
370
371static const struct m68k_cpu archs[] = {
9e64486e
ILT		 372 { m68000, "68000", 0 },
373 { m68010, "68010", 0 },
374 { m68020, "68020", 0 },
375 { m68030, "68030", 0 },
376 { m68040, "68040", 0 },
377 { m68060, "68060", 0 },
378 { cpu32, "cpu32", 0 },
379 { m68881, "68881", 0 },
380 { m68851, "68851", 0 },
8d20a0a8 381 { mcf5200, "5200", 0 },
b79de3a1
KR		 382 /* Aliases (effectively, so far as gas is concerned) for the above
383 cpus. */
9e64486e
ILT		 384 { m68020, "68k", 1 },
385 { m68000, "68302", 1 },
386 { m68000, "68008", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
8d20a0a8 393 { m68060, "68ec060", 1 },
9e64486e
ILT		 394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68340", 1 },
399 { cpu32, "68360", 1 },
400 { m68881, "68882", 1 },
b79de3a1
KR		 401};
402
403static const int n_archs = sizeof (archs) / sizeof (archs[0]);
404
fecd2382
RP		 405/* BCC68000 is for patching in an extra jmp instruction for long offsets
406 on the 68000. The 68000 doesn't support long branches with branchs */
407
408/* This table desribes how you change sizes for the various types of variable
409 size expressions. This version only supports two kinds. */
410
49864cfa
KR		 411/* Note that calls to frag_var need to specify the maximum expansion
412 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 413
414/* The fields are:
a39116f1
RP		 415 How far Forward this mode will reach:
416 How far Backward this mode will reach:
417 How many bytes this mode will add to the size of the frag
418 Which mode to go to if the offset won't fit in this one
419 */
04ef74bb 420relax_typeS md_relax_table[] =
355afbcd
KR		 421{
422 {1, 1, 0, 0}, /* First entries aren't used */
423 {1, 1, 0, 0}, /* For no good reason except */
424 {1, 1, 0, 0}, /* that the VAX doesn't either */
425 {1, 1, 0, 0},
426
427 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
428 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
429 {0, 0, 4, 0},
430 {1, 1, 0, 0},
431
432 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
433 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
434 {0, 0, 4, 0},
435 {1, 1, 0, 0},
436
437 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
438 {(32767), (-32768), 2, TAB (PCREL, LONG)},
439 {0, 0, 4, 0},
440 {1, 1, 0, 0},
441
442 {(127), (-128), 0, TAB (BCC68000, SHORT)},
443 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
444 {0, 0, 6, 0}, /* jmp long space */
445 {1, 1, 0, 0},
446
447 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
448 {(32767), (-32768), 2, TAB (DBCC, LONG)},
449 {0, 0, 10, 0}, /* bra/jmp long space */
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
453 {32767, -32768, 2, TAB (PCLEA, LONG)},
454 {0, 0, 6, 0},
455 {1, 1, 0, 0},
456
04ef74bb
KR		 457 /* For, e.g., jmp pcrel indexed. */
458 {125, -130, 0, TAB (PCINDEX, SHORT)},
459 {32765, -32770, 2, TAB (PCINDEX, LONG)},
460 {0, 0, 4, 0},
461 {1, 1, 0, 0},
355afbcd 462};
fecd2382
RP		 463
464/* These are the machine dependent pseudo-ops. These are included so
465 the assembler can work on the output from the SUN C compiler, which
466 generates these.
a39116f1 467 */
fecd2382
RP		 468
469/* This table describes all the machine specific pseudo-ops the assembler
470 has to support. The fields are:
a39116f1
RP		 471 pseudo-op name without dot
472 function to call to execute this pseudo-op
473 Integer arg to pass to the function
474 */
326b087c 475const pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 476{
477 {"data1", s_data1, 0},
478 {"data2", s_data2, 0},
479 {"bss", s_bss, 0},
480 {"even", s_even, 0},
481 {"skip", s_space, 0},
482 {"proc", s_proc, 0},
a043f579 483#if defined (TE_SUN3) || defined (OBJ_ELF)
355afbcd 484 {"align", s_align_bytes, 0},
5f8cb05e
ILT		 485#endif
486#ifdef OBJ_ELF
487 {"swbeg", s_ignore, 0},
bec66218 488#endif
9e64486e
ILT		 489 {"extend", float_cons, 'x'},
490 {"ldouble", float_cons, 'x'},
e9bb39b4
ILT		 491
492 /* The following pseudo-ops are supported for MRI compatibility. */
493 {"chip", s_chip, 0},
494 {"comline", s_space, 1},
27a53b88
ILT		 495 {"fopt", s_fopt, 0},
496 {"mask2", s_ignore, 0},
6700d36e
ILT		 497 {"opt", s_opt, 0},
498 {"reg", s_reg, 0},
e14994d9
ILT		 499 {"restore", s_restore, 0},
500 {"save", s_save, 0},
e9bb39b4 501
b4ec75e0
ILT		 502 {"if", s_mri_if, 0},
503 {"if.b", s_mri_if, 'b'},
504 {"if.w", s_mri_if, 'w'},
505 {"if.l", s_mri_if, 'l'},
506 {"else", s_mri_else, 0},
507 {"else.s", s_mri_else, 's'},
508 {"else.l", s_mri_else, 'l'},
509 {"endi", s_mri_endi, 0},
510 {"break", s_mri_break, 0},
511 {"break.s", s_mri_break, 's'},
512 {"break.l", s_mri_break, 'l'},
513 {"next", s_mri_next, 0},
514 {"next.s", s_mri_next, 's'},
515 {"next.l", s_mri_next, 'l'},
516 {"for", s_mri_for, 0},
517 {"for.b", s_mri_for, 'b'},
518 {"for.w", s_mri_for, 'w'},
519 {"for.l", s_mri_for, 'l'},
520 {"endf", s_mri_endf, 0},
521 {"repeat", s_mri_repeat, 0},
522 {"until", s_mri_until, 0},
523 {"until.b", s_mri_until, 'b'},
524 {"until.w", s_mri_until, 'w'},
525 {"until.l", s_mri_until, 'l'},
526 {"while", s_mri_while, 0},
527 {"while.b", s_mri_while, 'b'},
528 {"while.w", s_mri_while, 'w'},
529 {"while.l", s_mri_while, 'l'},
530 {"endw", s_mri_endw, 0},
531
355afbcd 532 {0, 0, 0}
fecd2382
RP		 533};
534
535
3ad9ec6a 536/* The mote pseudo ops are put into the opcode table, since they
355afbcd 537 don't start with a . they look like opcodes to gas.
3ad9ec6a 538 */
355afbcd 539extern void obj_coff_section ();
3ad9ec6a 540
49864cfa 541CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 542{
543
b79de3a1 544 {"dcl", cons, 4},
355afbcd 545 {"dc", cons, 2},
b79de3a1
KR		 546 {"dcw", cons, 2},
547 {"dcb", cons, 1},
3ad9ec6a 548
b79de3a1 549 {"dsl", s_space, 4},
355afbcd 550 {"ds", s_space, 2},
b79de3a1
KR		 551 {"dsw", s_space, 2},
552 {"dsb", s_space, 1},
3ad9ec6a 553
355afbcd 554 {"xdef", s_globl, 0},
a043f579
ILT		 555#ifdef OBJ_ELF
556 {"align", s_align_bytes, 0},
557#else
355afbcd 558 {"align", s_align_ptwo, 0},
a043f579 559#endif
3ad9ec6a 560#ifdef M68KCOFF
355afbcd
KR		 561 {"sect", obj_coff_section, 0},
562 {"section", obj_coff_section, 0},
3ad9ec6a 563#endif
bcb8dff8 564 {0, 0, 0}
3ad9ec6a
ILT		 565};
566
fecd2382
RP		 567#define issbyte(x) ((x)>=-128 && (x)<=127)
568#define isubyte(x) ((x)>=0 && (x)<=255)
569#define issword(x) ((x)>=-32768 && (x)<=32767)
570#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 571
e284846a 572#define isbyte(x) ((x)>= -255 && (x)<=255)
a7512014 573#define isword(x) ((x)>=-65536 && (x)<=65535)
fecd2382 574#define islong(x) (1)
f8701a3f
SC		 575
576extern char *input_line_pointer;
fecd2382 577
fecd2382
RP		 578static char mklower_table[256];
579#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 580static char notend_table[256];
fecd2382 581static char alt_notend_table[256];
a1c7c0f3
ILT		 582#define notend(s) \
583 (! (notend_table[(unsigned char) *s] \
584 || (*s == ':' \
585 && alt_notend_table[(unsigned char) s[1]])))
7c15cbe8 586
49864cfa 587#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 588
82489ea0
KR		 589#ifdef NO_PCREL_RELOCS
590
591int
592make_pcrel_absolute(fixP, add_number)
593 fixS *fixP;
594 long *add_number;
595{
596 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
597
598 /* rewrite the PC relative instructions to absolute address ones.
599 * these are rumoured to be faster, and the apollo linker refuses
600 * to deal with the PC relative relocations.
601 */
602 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
603 {
604 opcode[0] = 0x4e;
605 opcode[1] = 0xf9;
606 }
607 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
608 {
609 opcode[0] = 0x4e;
610 opcode[1] = 0xb9;
611 }
612 else
613 as_fatal ("Unknown PC relative instruction");
614 *add_number -= 4;
615 return 0;
616}
617
618#endif /* NO_PCREL_RELOCS */
619
355afbcd
KR		 620short
621tc_coff_fix2rtype (fixP)
622 fixS *fixP;
fecd2382 623{
3b06beb7
ILT		 624 if (fixP->fx_tcbit && fixP->fx_size == 4)
625 return R_RELLONG_NEG;
82489ea0
KR		 626#ifdef NO_PCREL_RELOCS
627 know (fixP->fx_pcrel == 0);
628 return (fixP->fx_size == 1 ? R_RELBYTE
629 : fixP->fx_size == 2 ? R_DIR16
630 : R_DIR32);
631#else
355afbcd
KR		 632 return (fixP->fx_pcrel ?
633 (fixP->fx_size == 1 ? R_PCRBYTE :
634 fixP->fx_size == 2 ? R_PCRWORD :
635 R_PCRLONG) :
636 (fixP->fx_size == 1 ? R_RELBYTE :
637 fixP->fx_size == 2 ? R_RELWORD :
638 R_RELLONG));
82489ea0 639#endif
3ad9ec6a
ILT		 640}
641
642#endif
fecd2382 643
a043f579
ILT		 644#ifdef OBJ_ELF
645
646/* Compute the relocation code for a fixup of SIZE bytes, using pc
647 relative relocation if PCREL is non-zero. PIC says whether a special
648 pic relocation was requested. */
649
650static bfd_reloc_code_real_type get_reloc_code
651 PARAMS ((int, int, enum pic_relocation));
652
653static bfd_reloc_code_real_type
654get_reloc_code (size, pcrel, pic)
655 int size;
656 int pcrel;
657 enum pic_relocation pic;
658{
659 switch (pic)
660 {
661 case pic_got_pcrel:
662 switch (size)
663 {
664 case 1:
665 return BFD_RELOC_8_GOT_PCREL;
666 case 2:
667 return BFD_RELOC_16_GOT_PCREL;
668 case 4:
669 return BFD_RELOC_32_GOT_PCREL;
670 }
671 break;
672
673 case pic_got_off:
674 switch (size)
675 {
676 case 1:
677 return BFD_RELOC_8_GOTOFF;
678 case 2:
679 return BFD_RELOC_16_GOTOFF;
680 case 4:
681 return BFD_RELOC_32_GOTOFF;
682 }
683 break;
684
685 case pic_plt_pcrel:
686 switch (size)
687 {
688 case 1:
689 return BFD_RELOC_8_PLT_PCREL;
690 case 2:
691 return BFD_RELOC_16_PLT_PCREL;
692 case 4:
693 return BFD_RELOC_32_PLT_PCREL;
694 }
695 break;
696
697 case pic_plt_off:
698 switch (size)
699 {
700 case 1:
701 return BFD_RELOC_8_PLTOFF;
702 case 2:
703 return BFD_RELOC_16_PLTOFF;
704 case 4:
705 return BFD_RELOC_32_PLTOFF;
706 }
707 break;
708
709 case pic_none:
710 if (pcrel)
711 {
712 switch (size)
713 {
714 case 1:
715 return BFD_RELOC_8_PCREL;
716 case 2:
717 return BFD_RELOC_16_PCREL;
718 case 4:
719 return BFD_RELOC_32_PCREL;
720 }
721 }
722 else
723 {
724 switch (size)
725 {
726 case 1:
727 return BFD_RELOC_8;
728 case 2:
729 return BFD_RELOC_16;
730 case 4:
731 return BFD_RELOC_32;
732 }
733 }
734 }
735
736 as_bad ("Can not do %d byte %s%srelocation", size,
737 pcrel ? "pc-relative " : "",
738 pic == pic_none ? "" : "pic ");
739 return BFD_RELOC_NONE;
740}
741
742/* Here we decide which fixups can be adjusted to make them relative
743 to the beginning of the section instead of the symbol. Basically
744 we need to make sure that the dynamic relocations are done
745 correctly, so in some cases we force the original symbol to be
746 used. */
747int
748tc_m68k_fix_adjustable (fixP)
749 fixS *fixP;
750{
751 /* Prevent all adjustments to global symbols. */
752 if (S_IS_EXTERNAL (fixP->fx_addsy))
753 return 0;
754
755 /* adjust_reloc_syms doesn't know about the GOT */
756 switch (fixP->fx_r_type)
757 {
758 case BFD_RELOC_8_GOT_PCREL:
759 case BFD_RELOC_16_GOT_PCREL:
760 case BFD_RELOC_32_GOT_PCREL:
761 case BFD_RELOC_8_GOTOFF:
762 case BFD_RELOC_16_GOTOFF:
763 case BFD_RELOC_32_GOTOFF:
764 case BFD_RELOC_8_PLT_PCREL:
765 case BFD_RELOC_16_PLT_PCREL:
766 case BFD_RELOC_32_PLT_PCREL:
767 case BFD_RELOC_8_PLTOFF:
768 case BFD_RELOC_16_PLTOFF:
769 case BFD_RELOC_32_PLTOFF:
770 return 0;
771
772 default:
773 return 1;
774 }
775}
776
777#else /* !OBJ_ELF */
778
779#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
780
781#endif /* OBJ_ELF */
782
49864cfa
KR		 783#ifdef BFD_ASSEMBLER
784
785arelent *
786tc_gen_reloc (section, fixp)
787 asection *section;
788 fixS *fixp;
789{
790 arelent *reloc;
791 bfd_reloc_code_real_type code;
792
9e64486e 793 if (fixp->fx_tcbit)
3b06beb7
ILT		 794 abort ();
795
a043f579 796 if (fixp->fx_r_type != BFD_RELOC_NONE)
7f003b7f
ILT		 797 {
798 code = fixp->fx_r_type;
799
800 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
801 that fixup_segment converted a non-PC relative reloc into a
802 PC relative reloc. In such a case, we need to convert the
803 reloc code. */
804 if (fixp->fx_pcrel)
805 {
806 switch (code)
807 {
808 case BFD_RELOC_8:
809 code = BFD_RELOC_8_PCREL;
810 break;
811 case BFD_RELOC_16:
812 code = BFD_RELOC_16_PCREL;
813 break;
814 case BFD_RELOC_32:
815 code = BFD_RELOC_32_PCREL;
816 break;
817 case BFD_RELOC_8_PCREL:
818 case BFD_RELOC_16_PCREL:
819 case BFD_RELOC_32_PCREL:
820 case BFD_RELOC_8_GOT_PCREL:
821 case BFD_RELOC_16_GOT_PCREL:
822 case BFD_RELOC_32_GOT_PCREL:
823 case BFD_RELOC_8_GOTOFF:
824 case BFD_RELOC_16_GOTOFF:
825 case BFD_RELOC_32_GOTOFF:
826 case BFD_RELOC_8_PLT_PCREL:
827 case BFD_RELOC_16_PLT_PCREL:
828 case BFD_RELOC_32_PLT_PCREL:
829 case BFD_RELOC_8_PLTOFF:
830 case BFD_RELOC_16_PLTOFF:
831 case BFD_RELOC_32_PLTOFF:
832 break;
833 default:
834 as_bad_where (fixp->fx_file, fixp->fx_line,
835 "Cannot make %s relocation PC relative",
836 bfd_get_reloc_code_name (code));
837 }
838 }
839 }
a043f579 840 else
49864cfa 841 {
a043f579
ILT		 842#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
843 switch (F (fixp->fx_size, fixp->fx_pcrel))
844 {
49864cfa 845#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
a043f579
ILT		 846 MAP (1, 0, BFD_RELOC_8);
847 MAP (2, 0, BFD_RELOC_16);
848 MAP (4, 0, BFD_RELOC_32);
849 MAP (1, 1, BFD_RELOC_8_PCREL);
850 MAP (2, 1, BFD_RELOC_16_PCREL);
851 MAP (4, 1, BFD_RELOC_32_PCREL);
852 default:
853 abort ();
854 }
49864cfa 855 }
a043f579
ILT		 856#undef F
857#undef MAP
49864cfa
KR		 858
859 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
860 assert (reloc != 0);
861 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
862 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a043f579 863#ifndef OBJ_ELF
49864cfa
KR		 864 if (fixp->fx_pcrel)
865 reloc->addend = fixp->fx_addnumber;
866 else
867 reloc->addend = 0;
a043f579
ILT		 868#else
869 if (!fixp->fx_pcrel)
870 reloc->addend = fixp->fx_addnumber;
7f003b7f 871 else
a043f579
ILT		 872 reloc->addend = (section->vma
873 + (fixp->fx_pcrel_adjust == 64
874 ? -1 : fixp->fx_pcrel_adjust)
875 + fixp->fx_addnumber
876 + md_pcrel_from (fixp));
a043f579 877#endif
49864cfa
KR		 878
879 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
880 assert (reloc->howto != 0);
881
882 return reloc;
883}
884
885#endif /* BFD_ASSEMBLER */
886
49864cfa
KR		 887/* Handle of the OPCODE hash table. NULL means any use before
888 m68k_ip_begin() will crash. */
889static struct hash_control *op_hash;
fecd2382 890\f
a1c7c0f3 891/* Assemble an m68k instruction. */
355afbcd 892
355afbcd
KR		 893void
894m68k_ip (instring)
6d27d3a2 895 char *instring;
fecd2382 896{
6d27d3a2
KR		 897 register char *p;
898 register struct m68k_op *opP;
899 register struct m68k_incant *opcode;
a1c7c0f3 900 register const char *s;
6d27d3a2 901 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 902 char *pdot, *pdotmove;
a1c7c0f3 903 enum m68k_size siz1, siz2;
355afbcd
KR		 904 char c;
905 int losing;
906 int opsfound;
907 char *crack_operand ();
6d27d3a2
KR		 908 LITTLENUM_TYPE words[6];
909 LITTLENUM_TYPE *wordp;
8be74775 910 unsigned long ok_arch = 0;
6d27d3a2
KR		 911
912 if (*instring == ' ')
913 instring++; /* skip leading whitespace */
914
915 /* Scan up to end of operation-code, which MUST end in end-of-string
916 or exactly 1 space. */
3ad9ec6a 917 pdot = 0;
355afbcd
KR		 918 for (p = instring; *p != '\0'; p++)
919 {
920 if (*p == ' ')
921 break;
922 if (*p == '.')
923 pdot = p;
924 }
6d27d3a2 925
355afbcd
KR		 926 if (p == instring)
927 {
928 the_ins.error = "No operator";
355afbcd
KR		 929 return;
930 }
6d27d3a2
KR		 931
932 /* p now points to the end of the opcode name, probably whitespace.
a1c7c0f3
ILT		 933 Make sure the name is null terminated by clobbering the
934 whitespace, look it up in the hash table, then fix it back.
3ad9ec6a 935 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 936 if (pdot != NULL)
937 {
938 for (pdotmove = pdot; pdotmove < p; pdotmove++)
939 *pdotmove = pdotmove[1];
940 p--;
941 }
3ad9ec6a 942
6d27d3a2
KR		 943 c = *p;
944 *p = '\0';
355afbcd 945 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 946 *p = c;
947
355afbcd
KR		 948 if (pdot != NULL)
949 {
950 for (pdotmove = p; pdotmove > pdot; pdotmove--)
951 *pdotmove = pdotmove[-1];
952 *pdot = '.';
953 ++p;
954 }
3ad9ec6a 955
355afbcd
KR		 956 if (opcode == NULL)
957 {
958 the_ins.error = "Unknown operator";
355afbcd
KR		 959 return;
960 }
6d27d3a2
KR		 961
962 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 963 while (*p == ' ')
964 ++p;
6d27d3a2 965
355afbcd
KR		 966 if (opcode->m_operands == 0)
967 {
968 char *old = input_line_pointer;
969 *old = '\n';
970 input_line_pointer = p;
971 /* Ahh - it's a motorola style psuedo op */
972 mote_pseudo_table[opcode->m_opnum].poc_handler
973 (mote_pseudo_table[opcode->m_opnum].poc_val);
974 input_line_pointer = old;
975 *old = 0;
3ad9ec6a 976
355afbcd
KR		 977 return;
978 }
3ad9ec6a 979
92a25e12
ILT		 980 if (flag_mri && opcode->m_opnum == 0)
981 {
982 /* In MRI mode, random garbage is allowed after an instruction
983 which accepts no operands. */
984 the_ins.args = opcode->m_operands;
985 the_ins.numargs = opcode->m_opnum;
986 the_ins.numo = opcode->m_codenum;
987 the_ins.opcode[0] = getone (opcode);
988 the_ins.opcode[1] = gettwo (opcode);
989 return;
990 }
991
355afbcd
KR		 992 for (opP = &the_ins.operands[0]; *p; opP++)
993 {
355afbcd 994 p = crack_operand (p, opP);
6d27d3a2 995
355afbcd
KR		 996 if (opP->error)
997 {
998 the_ins.error = opP->error;
999 return;
1000 }
6d27d3a2 1001 }
6d27d3a2
KR		 1002
1003 opsfound = opP - &the_ins.operands[0];
1004
a1c7c0f3
ILT		 1005 /* This ugly hack is to support the floating pt opcodes in their
1006 standard form. Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 1007 if (opcode->m_operands[0] == 'I')
1008 {
1009 int n;
6d27d3a2 1010
355afbcd
KR		 1011 for (n = opsfound; n > 0; --n)
1012 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 1013
a1c7c0f3
ILT		 1014 memset ((char *) (&the_ins.operands[0]), '\0',
1015 sizeof (the_ins.operands[0]));
1016 the_ins.operands[0].mode = CONTROL;
27a53b88 1017 the_ins.operands[0].reg = m68k_float_copnum;
355afbcd
KR		 1018 opsfound++;
1019 }
6d27d3a2
KR		 1020
1021 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 1022 for (losing = 0;;)
1023 {
49864cfa
KR		 1024 /* If we didn't get the right number of ops, or we have no
1025 common model with this pattern then reject this pattern. */
6d27d3a2 1026
0b810a6e 1027 ok_arch |= opcode->m_arch;
355afbcd
KR		 1028 if (opsfound != opcode->m_opnum
1029 || ((opcode->m_arch & current_architecture) == 0))
0b810a6e 1030 ++losing;
355afbcd
KR		 1031 else
1032 {
a1c7c0f3
ILT		 1033 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1034 *s && !losing;
1035 s += 2, opP++)
355afbcd
KR		 1036 {
1037 /* Warning: this switch is huge! */
49864cfa
KR		 1038 /* I've tried to organize the cases into this order:
1039 non-alpha first, then alpha by letter. Lower-case
1040 goes directly before uppercase counterpart. */
1041 /* Code with multiple case ...: gets sorted by the lowest
1042 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 1043 switch (*s)
1044 {
a1c7c0f3
ILT		 1045 case '!':
1046 switch (opP->mode)
1047 {
1048 case IMMED:
1049 case DREG:
1050 case AREG:
1051 case FPREG:
1052 case CONTROL:
1053 case AINC:
1054 case ADEC:
1055 case REGLST:
1056 losing++;
1057 break;
1058 default:
1059 break;
1060 }
355afbcd
KR		 1061 break;
1062
1063 case '`':
1064 switch (opP->mode)
1065 {
355afbcd
KR		 1066 case IMMED:
1067 case DREG:
1068 case AREG:
a1c7c0f3
ILT		 1069 case FPREG:
1070 case CONTROL:
355afbcd
KR		 1071 case AINC:
1072 case REGLST:
1073 case AINDR:
1074 losing++;
bcb8dff8
KR		 1075 break;
1076 default:
1077 break;
355afbcd
KR		 1078 }
1079 break;
8be74775 1080
b4d51f3d
ILT		 1081 case '<':
1082 switch (opP->mode)
1083 {
1084 case DREG:
1085 case AREG:
1086 case FPREG:
1087 case CONTROL:
1088 case IMMED:
1089 case ADEC:
1090 case REGLST:
1091 losing++;
1092 break;
1093 default:
1094 break;
1095 }
1096 break;
1097
1098 case '>':
1099 switch (opP->mode)
1100 {
1101 case DREG:
1102 case AREG:
1103 case FPREG:
1104 case CONTROL:
1105 case IMMED:
1106 case AINC:
1107 case REGLST:
1108 losing++;
1109 break;
1110 case ABSL:
1111 break;
1112 default:
1113 if (opP->reg == PC
1114 || opP->reg == ZPC)
1115 losing++;
1116 break;
1117 }
1118 break;
1119
1120 case 'm':
1121 switch (opP->mode)
1122 {
1123 case DREG:
1124 case AREG:
1125 case AINDR:
1126 case AINC:
1127 case ADEC:
1128 break;
1129 default:
1130 losing++;
1131 }
1132 break;
1133
1134 case 'n':
1135 switch (opP->mode)
1136 {
1137 case DISP:
1138 break;
1139 default:
1140 losing++;
1141 }
1142 break;
1143
1144 case 'o':
1145 switch (opP->mode)
1146 {
1147 case BASE:
1148 case ABSL:
1149 case IMMED:
1150 break;
1151 default:
1152 losing++;
1153 }
1154 break;
1155
1156 case 'p':
1157 switch (opP->mode)
1158 {
1159 case DREG:
1160 case AREG:
1161 case AINDR:
1162 case AINC:
1163 case ADEC:
1164 case DISP:
1165 break;
1166 default:
1167 losing++;
1168 }
1169 break;
1170
355afbcd
KR		 1171 case '#':
1172 if (opP->mode != IMMED)
1173 losing++;
a1c7c0f3
ILT		 1174 else if (s[1] == 'b'
1175 && ! isvar (&opP->disp)
336435bc
ILT		 1176 && (opP->disp.exp.X_op != O_constant
1177 || ! isbyte (opP->disp.exp.X_add_number)))
a1c7c0f3 1178 losing++;
a78bc551
ILT		 1179 else if (s[1] == 'B'
1180 && ! isvar (&opP->disp)
1181 && (opP->disp.exp.X_op != O_constant
1182 || ! issbyte (opP->disp.exp.X_add_number)))
1183 losing++;
a1c7c0f3
ILT		 1184 else if (s[1] == 'w'
1185 && ! isvar (&opP->disp)
336435bc
ILT		 1186 && (opP->disp.exp.X_op != O_constant
1187 || ! isword (opP->disp.exp.X_add_number)))
a1c7c0f3 1188 losing++;
9e64486e
ILT		 1189 else if (s[1] == 'W'
1190 && ! isvar (&opP->disp)
1191 && (opP->disp.exp.X_op != O_constant
1192 || ! issword (opP->disp.exp.X_add_number)))
1193 losing++;
355afbcd
KR		 1194 break;
1195
1196 case '^':
1197 case 'T':
1198 if (opP->mode != IMMED)
1199 losing++;
1200 break;
1201
1202 case '$':
a1c7c0f3
ILT		 1203 if (opP->mode == AREG
1204 || opP->mode == CONTROL
1205 || opP->mode == FPREG
1206 || opP->mode == IMMED
1207 || opP->mode == REGLST
1208 || (opP->mode != ABSL
1209 && (opP->reg == PC
1210 || opP->reg == ZPC)))
355afbcd
KR		 1211 losing++;
1212 break;
1213
1214 case '%':
a1c7c0f3
ILT		 1215 if (opP->mode == CONTROL
1216 || opP->mode == FPREG
1217 || opP->mode == REGLST
a7512014 1218 || opP->mode == IMMED
a1c7c0f3 1219 || (opP->mode != ABSL
a1c7c0f3
ILT		 1220 && (opP->reg == PC
1221 || opP->reg == ZPC)))
355afbcd
KR		 1222 losing++;
1223 break;
1224
355afbcd 1225 case '&':
a1c7c0f3
ILT		 1226 switch (opP->mode)
1227 {
1228 case DREG:
1229 case AREG:
1230 case FPREG:
1231 case CONTROL:
1232 case IMMED:
1233 case AINC:
1234 case ADEC:
1235 case REGLST:
1236 losing++;
1237 break;
1238 case ABSL:
1239 break;
1240 default:
1241 if (opP->reg == PC
1242 || opP->reg == ZPC)
1243 losing++;
1244 break;
1245 }
355afbcd
KR		 1246 break;
1247
1248 case '*':
a1c7c0f3
ILT		 1249 if (opP->mode == CONTROL
1250 || opP->mode == FPREG
1251 || opP->mode == REGLST)
355afbcd
KR		 1252 losing++;
1253 break;
1254
1255 case '+':
1256 if (opP->mode != AINC)
1257 losing++;
1258 break;
1259
1260 case '-':
1261 if (opP->mode != ADEC)
1262 losing++;
1263 break;
1264
1265 case '/':
a1c7c0f3
ILT		 1266 switch (opP->mode)
1267 {
1268 case AREG:
1269 case CONTROL:
1270 case FPREG:
1271 case AINC:
1272 case ADEC:
1273 case IMMED:
1274 case REGLST:
1275 losing++;
1276 break;
1277 default:
1278 break;
1279 }
355afbcd
KR		 1280 break;
1281
1282 case ';':
a1c7c0f3
ILT		 1283 switch (opP->mode)
1284 {
1285 case AREG:
1286 case CONTROL:
1287 case FPREG:
1288 case REGLST:
1289 losing++;
1290 break;
1291 default:
1292 break;
1293 }
355afbcd
KR		 1294 break;
1295
1296 case '?':
a1c7c0f3
ILT		 1297 switch (opP->mode)
1298 {
1299 case AREG:
1300 case CONTROL:
1301 case FPREG:
1302 case AINC:
1303 case ADEC:
1304 case IMMED:
1305 case REGLST:
1306 losing++;
1307 break;
1308 case ABSL:
1309 break;
1310 default:
1311 if (opP->reg == PC || opP->reg == ZPC)
1312 losing++;
1313 break;
1314 }
355afbcd
KR		 1315 break;
1316
1317 case '@':
a1c7c0f3
ILT		 1318 switch (opP->mode)
1319 {
1320 case AREG:
1321 case CONTROL:
1322 case FPREG:
1323 case IMMED:
1324 case REGLST:
1325 losing++;
1326 break;
1327 default:
1328 break;
1329 }
355afbcd
KR		 1330 break;
1331
1332 case '~': /* For now! (JF FOO is this right?) */
a1c7c0f3
ILT		 1333 switch (opP->mode)
1334 {
1335 case DREG:
1336 case AREG:
1337 case CONTROL:
1338 case FPREG:
1339 case IMMED:
1340 case REGLST:
1341 losing++;
1342 break;
1343 case ABSL:
1344 break;
1345 default:
1346 if (opP->reg == PC
1347 || opP->reg == ZPC)
1348 losing++;
1349 break;
1350 }
355afbcd
KR		 1351 break;
1352
1353 case '3':
a1c7c0f3
ILT		 1354 if (opP->mode != CONTROL
1355 || (opP->reg != TT0 && opP->reg != TT1))
355afbcd
KR		 1356 losing++;
1357 break;
1358
1359 case 'A':
1360 if (opP->mode != AREG)
1361 losing++;
1362 break;
a1c7c0f3 1363
355afbcd
KR		 1364 case 'a':
1365 if (opP->mode != AINDR)
a1c7c0f3 1366 ++losing;
355afbcd 1367 break;
a1c7c0f3 1368
355afbcd 1369 case 'B': /* FOO */
a1c7c0f3
ILT		 1370 if (opP->mode != ABSL
1371 || (flag_long_jumps
1372 && strncmp (instring, "jbsr", 4) == 0))
355afbcd
KR		 1373 losing++;
1374 break;
1375
1376 case 'C':
a1c7c0f3 1377 if (opP->mode != CONTROL || opP->reg != CCR)
355afbcd
KR		 1378 losing++;
1379 break;
1380
a1c7c0f3
ILT		 1381 case 'd':
1382 if (opP->mode != DISP
1383 || opP->reg < ADDR0
1384 || opP->reg > ADDR7)
355afbcd
KR		 1385 losing++;
1386 break;
1387
1388 case 'D':
1389 if (opP->mode != DREG)
1390 losing++;
1391 break;
1392
1393 case 'F':
a1c7c0f3 1394 if (opP->mode != FPREG)
355afbcd
KR		 1395 losing++;
1396 break;
1397
1398 case 'I':
a1c7c0f3 1399 if (opP->mode != CONTROL
27a53b88
ILT		 1400 || opP->reg < COP0
1401 || opP->reg > COP7)
355afbcd
KR		 1402 losing++;
1403 break;
1404
1405 case 'J':
a1c7c0f3 1406 if (opP->mode != CONTROL
355afbcd 1407 || opP->reg < USP
82489ea0
KR		 1408 || opP->reg > last_movec_reg)
1409 losing++;
1410 else
355afbcd 1411 {
a1c7c0f3 1412 const enum m68k_register *rp;
82489ea0
KR		 1413 for (rp = control_regs; *rp; rp++)
1414 if (*rp == opP->reg)
1415 break;
1416 if (*rp == 0)
1417 losing++;
1418 }
355afbcd
KR		 1419 break;
1420
1421 case 'k':
1422 if (opP->mode != IMMED)
1423 losing++;
1424 break;
8be74775 1425
355afbcd
KR		 1426 case 'l':
1427 case 'L':
a1c7c0f3
ILT		 1428 if (opP->mode == DREG
1429 || opP->mode == AREG
1430 || opP->mode == FPREG)
355afbcd
KR		 1431 {
1432 if (s[1] == '8')
1433 losing++;
1434 else
1435 {
a1c7c0f3
ILT		 1436 switch (opP->mode)
1437 {
1438 case DREG:
1439 opP->mask = 1 << (opP->reg - DATA0);
1440 break;
1441 case AREG:
1442 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1443 break;
1444 case FPREG:
1445 opP->mask = 1 << (opP->reg - FP0 + 16);
1446 break;
1447 default:
1448 abort ();
1449 }
355afbcd 1450 opP->mode = REGLST;
355afbcd
KR		 1451 }
1452 }
a1c7c0f3 1453 else if (opP->mode == CONTROL)
355afbcd 1454 {
a1c7c0f3
ILT		 1455 if (s[1] != '8')
1456 losing++;
1457 else
1458 {
1459 switch (opP->reg)
1460 {
1461 case FPI:
1462 opP->mask = 1 << 24;
1463 break;
1464 case FPS:
1465 opP->mask = 1 << 25;
1466 break;
1467 case FPC:
1468 opP->mask = 1 << 26;
1469 break;
1470 default:
1471 losing++;
1472 break;
1473 }
1474 opP->mode = REGLST;
1475 }
355afbcd 1476 }
6700d36e
ILT		 1477 else if (opP->mode == ABSL
1478 && opP->disp.size == SIZE_UNSPEC
1479 && opP->disp.exp.X_op == O_constant)
1480 {
1481 /* This is what the MRI REG pseudo-op generates. */
1482 opP->mode = REGLST;
1483 opP->mask = opP->disp.exp.X_add_number;
1484 }
a1c7c0f3 1485 else if (opP->mode != REGLST)
355afbcd 1486 losing++;
a1c7c0f3
ILT		 1487 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1488 losing++;
1489 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
355afbcd
KR		 1490 losing++;
1491 break;
1492
1493 case 'M':
1494 if (opP->mode != IMMED)
1495 losing++;
336435bc
ILT		 1496 else if (opP->disp.exp.X_op != O_constant
1497 || ! issbyte (opP->disp.exp.X_add_number))
a1c7c0f3 1498 losing++;
6700d36e
ILT		 1499 else if (! m68k_quick
1500 && instring[3] != 'q'
1501 && instring[4] != 'q')
1502 losing++;
355afbcd 1503 break;
8be74775 1504
355afbcd 1505 case 'O':
8d20a0a8
C		 1506 if (opP->mode != DREG
1507 && opP->mode != IMMED
1508 && opP->mode != ABSL)
355afbcd
KR		 1509 losing++;
1510 break;
6d27d3a2 1511
355afbcd
KR		 1512 case 'Q':
1513 if (opP->mode != IMMED)
1514 losing++;
336435bc 1515 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1516 || opP->disp.exp.X_add_number < 1
1517 || opP->disp.exp.X_add_number > 8)
1518 losing++;
6700d36e
ILT		 1519 else if (! m68k_quick
1520 && (strncmp (instring, "add", 3) == 0
1521 || strncmp (instring, "sub", 3) == 0)
1522 && instring[3] != 'q')
1523 losing++;
355afbcd 1524 break;
8be74775 1525
355afbcd
KR		 1526 case 'R':
1527 if (opP->mode != DREG && opP->mode != AREG)
1528 losing++;
1529 break;
8be74775 1530
355afbcd 1531 case 'r':
a1c7c0f3
ILT		 1532 if (opP->mode != AINDR
1533 && (opP->mode != BASE
1534 || (opP->reg != 0
1535 && opP->reg != ZADDR0)
1536 || opP->disp.exp.X_op != O_absent
1537 || ((opP->index.reg < DATA0
1538 || opP->index.reg > DATA7)
1539 && (opP->index.reg < ADDR0
1540 || opP->index.reg > ADDR7))
1541 || opP->index.size != SIZE_UNSPEC
1542 || opP->index.scale != 1))
355afbcd
KR		 1543 losing++;
1544 break;
c50140c8 1545
355afbcd 1546 case 's':
a1c7c0f3
ILT		 1547 if (opP->mode != CONTROL
1548 || ! (opP->reg == FPI
1549 || opP->reg == FPS
1550 || opP->reg == FPC))
355afbcd
KR		 1551 losing++;
1552 break;
8be74775 1553
355afbcd 1554 case 'S':
a1c7c0f3 1555 if (opP->mode != CONTROL || opP->reg != SR)
355afbcd
KR		 1556 losing++;
1557 break;
8be74775 1558
355afbcd
KR		 1559 case 't':
1560 if (opP->mode != IMMED)
1561 losing++;
336435bc 1562 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1563 || opP->disp.exp.X_add_number < 0
1564 || opP->disp.exp.X_add_number > 7)
1565 losing++;
355afbcd 1566 break;
4134a793 1567
355afbcd 1568 case 'U':
a1c7c0f3 1569 if (opP->mode != CONTROL || opP->reg != USP)
355afbcd
KR		 1570 losing++;
1571 break;
8be74775 1572
355afbcd 1573 /* JF these are out of order. We could put them
1404ef23
KR		 1574 in order if we were willing to put up with
1575 bunches of #ifdef m68851s in the code.
4134a793 1576
1404ef23
KR		 1577 Don't forget that you need these operands
1578 to use 68030 MMU instructions. */
f8701a3f 1579#ifndef NO_68851
355afbcd
KR		 1580 /* Memory addressing mode used by pflushr */
1581 case '|':
a1c7c0f3
ILT		 1582 if (opP->mode == CONTROL
1583 || opP->mode == FPREG
1584 || opP->mode == DREG
1585 || opP->mode == AREG
1586 || opP->mode == REGLST)
355afbcd 1587 losing++;
9adcd781
ILT		 1588 /* We should accept immediate operands, but they
1589 supposedly have to be quad word, and we don't
1590 handle that. I would like to see what a Motorola
1591 assembler does before doing something here. */
1592 if (opP->mode == IMMED)
1593 losing++;
355afbcd
KR		 1594 break;
1595
1596 case 'f':
a1c7c0f3
ILT		 1597 if (opP->mode != CONTROL
1598 || (opP->reg != SFC && opP->reg != DFC))
355afbcd
KR		 1599 losing++;
1600 break;
1601
9adcd781
ILT		 1602 case '0':
1603 if (opP->mode != CONTROL || opP->reg != TC)
1604 losing++;
1605 break;
1606
1607 case '1':
1608 if (opP->mode != CONTROL || opP->reg != AC)
1609 losing++;
1610 break;
1611
1612 case '2':
a1c7c0f3 1613 if (opP->mode != CONTROL
9adcd781 1614 || (opP->reg != CAL
a1c7c0f3 1615 && opP->reg != VAL
9adcd781 1616 && opP->reg != SCC))
355afbcd
KR		 1617 losing++;
1618 break;
1619
1620 case 'V':
a1c7c0f3
ILT		 1621 if (opP->mode != CONTROL
1622 || opP->reg != VAL)
355afbcd
KR		 1623 losing++;
1624 break;
8be74775 1625
355afbcd 1626 case 'W':
a1c7c0f3
ILT		 1627 if (opP->mode != CONTROL
1628 || (opP->reg != DRP
1629 && opP->reg != SRP
355afbcd
KR		 1630 && opP->reg != CRP))
1631 losing++;
1632 break;
1633
1634 case 'X':
a1c7c0f3
ILT		 1635 if (opP->mode != CONTROL
1636 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1637 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
355afbcd
KR		 1638 losing++;
1639 break;
1640
1641 case 'Y':
a1c7c0f3 1642 if (opP->mode != CONTROL || opP->reg != PSR)
355afbcd
KR		 1643 losing++;
1644 break;
1645
1646 case 'Z':
a1c7c0f3 1647 if (opP->mode != CONTROL || opP->reg != PCSR)
355afbcd
KR		 1648 losing++;
1649 break;
f8701a3f 1650#endif
355afbcd 1651 case 'c':
a1c7c0f3
ILT		 1652 if (opP->mode != CONTROL
1653 || (opP->reg != NC
1654 && opP->reg != IC
1655 && opP->reg != DC
1656 && opP->reg != BC))
355afbcd
KR		 1657 {
1658 losing++;
1659 } /* not a cache specifier. */
1660 break;
1661
1662 case '_':
1663 if (opP->mode != ABSL)
a1c7c0f3 1664 ++losing;
355afbcd 1665 break;
8be74775 1666
355afbcd 1667 default:
a1c7c0f3 1668 abort ();
355afbcd 1669 } /* switch on type of operand */
6d27d3a2 1670
355afbcd
KR		 1671 if (losing)
1672 break;
1673 } /* for each operand */
1674 } /* if immediately wrong */
6d27d3a2 1675
355afbcd
KR		 1676 if (!losing)
1677 {
8be74775 1678 break;
355afbcd 1679 } /* got it. */
6d27d3a2 1680
355afbcd 1681 opcode = opcode->m_next;
6d27d3a2 1682
355afbcd 1683 if (!opcode)
8be74775 1684 {
355afbcd
KR		 1685 if (ok_arch
1686 && !(ok_arch & current_architecture))
8be74775 1687 {
355afbcd 1688 char buf[200], *cp;
091221ce 1689
a1c7c0f3
ILT		 1690 strcpy (buf,
1691 "invalid instruction for this architecture; needs ");
355afbcd
KR		 1692 cp = buf + strlen (buf);
1693 switch (ok_arch)
1694 {
1695 case mfloat:
82489ea0 1696 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
355afbcd
KR		 1697 break;
1698 case mmmu:
1699 strcpy (cp, "mmu (68030 or 68851)");
1700 break;
1701 case m68020up:
1702 strcpy (cp, "68020 or higher");
1703 break;
1704 case m68000up:
1705 strcpy (cp, "68000 or higher");
1706 break;
1707 case m68010up:
1708 strcpy (cp, "68010 or higher");
1709 break;
1710 default:
8be74775 1711 {
355afbcd 1712 int got_one = 0, idx;
a1c7c0f3
ILT		 1713 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1714 idx++)
8be74775 1715 {
9e64486e
ILT		 1716 if ((archs[idx].arch & ok_arch)
1717 && ! archs[idx].alias)
8be74775 1718 {
355afbcd
KR		 1719 if (got_one)
1720 {
1721 strcpy (cp, " or ");
1722 cp += strlen (cp);
1723 }
1724 got_one = 1;
1725 strcpy (cp, archs[idx].name);
8be74775
KR		 1726 cp += strlen (cp);
1727 }
8be74775
KR		 1728 }
1729 }
355afbcd 1730 }
091221ce 1731 cp = xmalloc (strlen (buf) + 1);
355afbcd
KR		 1732 strcpy (cp, buf);
1733 the_ins.error = cp;
8be74775 1734 }
355afbcd
KR		 1735 else
1736 the_ins.error = "operands mismatch";
1737 return;
1738 } /* Fell off the end */
6d27d3a2 1739
355afbcd
KR		 1740 losing = 0;
1741 }
6d27d3a2
KR		 1742
1743 /* now assemble it */
1744
355afbcd
KR		 1745 the_ins.args = opcode->m_operands;
1746 the_ins.numargs = opcode->m_opnum;
1747 the_ins.numo = opcode->m_codenum;
1748 the_ins.opcode[0] = getone (opcode);
1749 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 1750
355afbcd
KR		 1751 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1752 {
1753 /* This switch is a doozy.
6d27d3a2 1754 Watch the first step; its a big one! */
355afbcd
KR		 1755 switch (s[0])
1756 {
6d27d3a2 1757
355afbcd
KR		 1758 case '*':
1759 case '~':
1760 case '%':
1761 case ';':
1762 case '@':
1763 case '!':
1764 case '&':
1765 case '$':
1766 case '?':
1767 case '/':
1768 case '`':
b4d51f3d
ILT		 1769 case '<':
1770 case '>':
1771 case 'm':
1772 case 'n':
1773 case 'o':
1774 case 'p':
355afbcd
KR		 1775#ifndef NO_68851
1776 case '|':
1777#endif
1778 switch (opP->mode)
1779 {
1780 case IMMED:
1781 tmpreg = 0x3c; /* 7.4 */
1782 if (strchr ("bwl", s[1]))
a1c7c0f3 1783 nextword = get_num (&opP->disp, 80);
355afbcd 1784 else
a1c7c0f3
ILT		 1785 nextword = get_num (&opP->disp, 0);
1786 if (isvar (&opP->disp))
1787 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1788 switch (s[1])
1789 {
1790 case 'b':
1791 if (!isbyte (nextword))
1792 opP->error = "operand out of range";
1793 addword (nextword);
1794 baseo = 0;
1795 break;
1796 case 'w':
1797 if (!isword (nextword))
1798 opP->error = "operand out of range";
1799 addword (nextword);
1800 baseo = 0;
1801 break;
9e64486e
ILT		 1802 case 'W':
1803 if (!issword (nextword))
1804 opP->error = "operand out of range";
1805 addword (nextword);
1806 baseo = 0;
1807 break;
355afbcd
KR		 1808 case 'l':
1809 addword (nextword >> 16);
1810 addword (nextword);
1811 baseo = 0;
1812 break;
1813
1814 case 'f':
1815 baseo = 2;
1816 outro = 8;
1817 break;
1818 case 'F':
1819 baseo = 4;
1820 outro = 11;
1821 break;
1822 case 'x':
1823 baseo = 6;
1824 outro = 15;
1825 break;
1826 case 'p':
1827 baseo = 6;
1828 outro = -1;
1829 break;
1830 default:
a1c7c0f3 1831 abort ();
355afbcd
KR		 1832 }
1833 if (!baseo)
1834 break;
6d27d3a2 1835
355afbcd 1836 /* We gotta put out some float */
a1c7c0f3 1837 if (op (&opP->disp) != O_big)
355afbcd 1838 {
bcb8dff8
KR		 1839 valueT val;
1840 int gencnt;
1841
1842 /* Can other cases happen here? */
a1c7c0f3 1843 if (op (&opP->disp) != O_constant)
bcb8dff8 1844 abort ();
82489ea0 1845
a1c7c0f3 1846 val = (valueT) offs (&opP->disp);
bcb8dff8
KR		 1847 gencnt = 0;
1848 do
1849 {
1850 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1851 val >>= LITTLENUM_NUMBER_OF_BITS;
1852 ++gencnt;
1853 }
1854 while (val != 0);
a1c7c0f3 1855 offs (&opP->disp) = gencnt;
355afbcd 1856 }
a1c7c0f3 1857 if (offs (&opP->disp) > 0)
355afbcd 1858 {
a1c7c0f3 1859 if (offs (&opP->disp) > baseo)
355afbcd 1860 {
a1c7c0f3
ILT		 1861 as_warn ("Bignum too big for %c format; truncated",
1862 s[1]);
1863 offs (&opP->disp) = baseo;
355afbcd 1864 }
a1c7c0f3 1865 baseo -= offs (&opP->disp);
355afbcd
KR		 1866 while (baseo--)
1867 addword (0);
a1c7c0f3
ILT		 1868 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1869 offs (&opP->disp)--;
1870 --wordp)
bcb8dff8 1871 addword (*wordp);
355afbcd
KR		 1872 break;
1873 }
1874 gen_to_words (words, baseo, (long) outro);
1875 for (wordp = words; baseo--; wordp++)
1876 addword (*wordp);
1877 break;
1878 case DREG:
1879 tmpreg = opP->reg - DATA; /* 0.dreg */
1880 break;
1881 case AREG:
1882 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1883 break;
1884 case AINDR:
1885 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1886 break;
1887 case ADEC:
1888 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1889 break;
1890 case AINC:
1891 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1892 break;
a1c7c0f3 1893 case DISP:
6d27d3a2 1894
a1c7c0f3 1895 nextword = get_num (&opP->disp, 80);
6700d36e
ILT		 1896
1897 if (opP->reg == PC
1898 && ! isvar (&opP->disp)
1899 && m68k_abspcadd)
1900 {
1901 opP->disp.exp.X_op = O_symbol;
1902#ifndef BFD_ASSEMBLER
1903 opP->disp.exp.X_add_symbol = &abs_symbol;
1904#else
1905 opP->disp.exp.X_add_symbol =
1906 section_symbol (absolute_section);
1907#endif
1908 }
1909
355afbcd 1910 /* Force into index mode. Hope this works */
6d27d3a2 1911
1404ef23
KR		 1912 /* We do the first bit for 32-bit displacements, and the
1913 second bit for 16 bit ones. It is possible that we
1914 should make the default be WORD instead of LONG, but
1915 I think that'd break GCC, so we put up with a little
1916 inefficiency for the sake of working output. */
6d27d3a2 1917
355afbcd 1918 if (!issword (nextword)
a1c7c0f3
ILT		 1919 || (isvar (&opP->disp)
1920 && ((opP->disp.size == SIZE_UNSPEC
b79de3a1
KR		 1921 && flag_short_refs == 0
1922 && cpu_of_arch (current_architecture) >= m68020)
a1c7c0f3 1923 || opP->disp.size == SIZE_LONG)))
355afbcd 1924 {
912e4245
ILT		 1925 if (cpu_of_arch (current_architecture) < m68020)
1926 opP->error =
1927 "displacement too large for this architecture; needs 68020 or higher";
355afbcd
KR		 1928 if (opP->reg == PC)
1929 tmpreg = 0x3B; /* 7.3 */
1930 else
1931 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
a1c7c0f3 1932 if (isvar (&opP->disp))
355afbcd
KR		 1933 {
1934 if (opP->reg == PC)
1935 {
a043f579
ILT		 1936 if (opP->disp.size == SIZE_LONG
1937#ifdef OBJ_ELF
1938 /* If the displacement needs pic
1939 relocation it cannot be relaxed. */
1940 || opP->disp.pic_reloc != pic_none
04ef74bb 1941#endif
a043f579
ILT		 1942 )
1943 {
1944 addword (0x0170);
1945 add_fix ('l', &opP->disp, 1, 2);
1946 }
1947 else
1948 {
1949 add_frag (adds (&opP->disp),
1950 offs (&opP->disp),
1951 TAB (PCLEA, SZ_UNDEF));
1952 break;
1953 }
355afbcd
KR		 1954 }
1955 else
1956 {
1957 addword (0x0170);
a1c7c0f3 1958 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1959 }
1960 }
1961 else
1962 addword (0x0170);
1963 addword (nextword >> 16);
1964 }
1965 else
1966 {
1967 if (opP->reg == PC)
1968 tmpreg = 0x3A; /* 7.2 */
1969 else
1970 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1971
a1c7c0f3 1972 if (isvar (&opP->disp))
355afbcd
KR		 1973 {
1974 if (opP->reg == PC)
1975 {
a1c7c0f3 1976 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1977 }
1978 else
a1c7c0f3 1979 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1980 }
1981 }
1982 addword (nextword);
6d27d3a2 1983 break;
6d27d3a2 1984
a1c7c0f3
ILT		 1985 case POST:
1986 case PRE:
1987 case BASE:
355afbcd 1988 nextword = 0;
a1c7c0f3
ILT		 1989 baseo = get_num (&opP->disp, 80);
1990 if (opP->mode == POST || opP->mode == PRE)
1991 outro = get_num (&opP->odisp, 80);
49864cfa
KR		 1992 /* Figure out the `addressing mode'.
1993 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 1994 if (opP->reg == PC || opP->reg == ZPC)
1995 {
a1c7c0f3 1996 tmpreg = 0x3b; /* 7.3 */
355afbcd
KR		 1997 if (opP->reg == ZPC)
1998 nextword |= 0x80;
1999 }
a1c7c0f3
ILT		 2000 else if (opP->reg == 0)
2001 {
2002 nextword |= 0x80;
2003 tmpreg = 0x30; /* 6.garbage */
2004 }
2005 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
355afbcd
KR		 2006 {
2007 nextword |= 0x80;
a1c7c0f3 2008 tmpreg = 0x30 + opP->reg - ZADDR0;
355afbcd
KR		 2009 }
2010 else
2011 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2012
a1c7c0f3
ILT		 2013 siz1 = opP->disp.size;
2014 if (opP->mode == POST || opP->mode == PRE)
2015 siz2 = opP->odisp.size;
2016 else
2017 siz2 = SIZE_UNSPEC;
355afbcd
KR		 2018
2019 /* Index register stuff */
a1c7c0f3
ILT		 2020 if (opP->index.reg != 0
2021 && opP->index.reg >= DATA
2022 && opP->index.reg <= ADDR7)
355afbcd 2023 {
a1c7c0f3 2024 nextword |= (opP->index.reg - DATA) << 12;
355afbcd 2025
b4d51f3d
ILT		 2026 if (opP->index.size == SIZE_LONG
2027 || (opP->index.size == SIZE_UNSPEC
2028 && m68k_index_width_default == SIZE_LONG))
355afbcd 2029 nextword |= 0x800;
a1c7c0f3 2030
8d20a0a8
C		 2031 if ((opP->index.scale != 1
2032 && cpu_of_arch (current_architecture) < m68020)
2033 || (opP->index.scale == 8
2034 && current_architecture == mcf5200))
a1c7c0f3 2035 {
8d20a0a8
C		 2036 opP->error =
2037 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
a1c7c0f3
ILT		 2038 }
2039
2040 switch (opP->index.scale)
355afbcd
KR		 2041 {
2042 case 1:
2043 break;
2044 case 2:
2045 nextword |= 0x200;
2046 break;
2047 case 4:
2048 nextword |= 0x400;
2049 break;
2050 case 8:
2051 nextword |= 0x600;
2052 break;
2053 default:
a1c7c0f3 2054 abort ();
355afbcd
KR		 2055 }
2056 /* IF its simple,
49864cfa 2057 GET US OUT OF HERE! */
6d27d3a2 2058
04ef74bb
KR		 2059 /* Must be INDEX, with an index register. Address
2060 register cannot be ZERO-PC, and either :b was
2061 forced, or we know it will fit. For a 68000 or
2062 68010, force this mode anyways, because the
2063 larger modes aren't supported. */
a1c7c0f3
ILT		 2064 if (opP->mode == BASE
2065 && ((opP->reg >= ADDR0
2066 && opP->reg <= ADDR7)
2067 || opP->reg == PC))
355afbcd 2068 {
a1c7c0f3
ILT		 2069 if (siz1 == SIZE_BYTE
2070 || cpu_of_arch (current_architecture) < m68020
2071 || (siz1 == SIZE_UNSPEC
2072 && ! isvar (&opP->disp)
2073 && issbyte (baseo)))
2074 {
5f8cb05e
ILT		 2075 nextword += baseo & 0xff;
2076 addword (nextword);
a1c7c0f3 2077 if (isvar (&opP->disp))
04ef74bb 2078 {
a1c7c0f3
ILT		 2079 /* Do a byte relocation. If it doesn't
2080 fit (possible on m68000) let the
2081 fixup processing complain later. */
5f8cb05e 2082 if (opP->reg == PC)
a1c7c0f3 2083 add_fix ('B', &opP->disp, 1, 1);
5f8cb05e 2084 else
a1c7c0f3 2085 add_fix ('B', &opP->disp, 0, 0);
04ef74bb 2086 }
a1c7c0f3
ILT		 2087 else if (siz1 != SIZE_BYTE)
2088 {
2089 if (siz1 != SIZE_UNSPEC)
2090 as_warn ("Forcing byte displacement");
2091 if (! issbyte (baseo))
2092 opP->error = "byte displacement out of range";
2093 }
2094
2095 break;
2096 }
2097 else if (siz1 == SIZE_UNSPEC
2098 && opP->reg == PC
2099 && isvar (&opP->disp)
a043f579
ILT		 2100 && subs (&opP->disp) == NULL
2101#ifdef OBJ_ELF
2102 /* If the displacement needs pic
2103 relocation it cannot be relaxed. */
2104 && opP->disp.pic_reloc == pic_none
2105#endif
2106 )
a1c7c0f3 2107 {
2156d0d7
ILT		 2108 /* The code in md_convert_frag_1 needs to be
2109 able to adjust nextword. Call frag_grow
2110 to ensure that we have enough space in
2111 the frag obstack to make all the bytes
2112 contiguous. */
2113 frag_grow (14);
5f8cb05e
ILT		 2114 nextword += baseo & 0xff;
2115 addword (nextword);
a1c7c0f3 2116 add_frag (adds (&opP->disp), offs (&opP->disp),
5f8cb05e 2117 TAB (PCINDEX, SZ_UNDEF));
a1c7c0f3
ILT		 2118
2119 break;
5f8cb05e 2120 }
355afbcd
KR		 2121 }
2122 }
2123 else
a1c7c0f3
ILT		 2124 {
2125 nextword |= 0x40; /* No index reg */
2126 if (opP->index.reg >= ZDATA0
2127 && opP->index.reg <= ZDATA7)
2128 nextword |= (opP->index.reg - ZDATA0) << 12;
2129 else if (opP->index.reg >= ZADDR0
2130 || opP->index.reg <= ZADDR7)
2131 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2132 }
6d27d3a2 2133
49864cfa 2134 /* It isn't simple. */
a1c7c0f3
ILT		 2135
2136 if (cpu_of_arch (current_architecture) < m68020)
2137 opP->error =
2138 "invalid operand mode for this architecture; needs 68020 or higher";
2139
355afbcd 2140 nextword |= 0x100;
49864cfa
KR		 2141 /* If the guy specified a width, we assume that it is
2142 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 2143 switch (siz1)
2144 {
a1c7c0f3 2145 case SIZE_UNSPEC:
6700d36e
ILT		 2146 if (isvar (&opP->disp)
2147 ? m68k_rel32
2148 : ! issword (baseo))
355afbcd 2149 {
a1c7c0f3 2150 siz1 = SIZE_LONG;
355afbcd
KR		 2151 nextword |= 0x30;
2152 }
6700d36e 2153 else if (! isvar (&opP->disp) && baseo == 0)
355afbcd
KR		 2154 nextword |= 0x10;
2155 else
2156 {
2157 nextword |= 0x20;
a1c7c0f3 2158 siz1 = SIZE_WORD;
355afbcd
KR		 2159 }
2160 break;
a1c7c0f3
ILT		 2161 case SIZE_BYTE:
2162 as_warn (":b not permitted; defaulting to :w");
2163 /* Fall through. */
2164 case SIZE_WORD:
355afbcd
KR		 2165 nextword |= 0x20;
2166 break;
a1c7c0f3 2167 case SIZE_LONG:
355afbcd
KR		 2168 nextword |= 0x30;
2169 break;
2170 }
6d27d3a2 2171
355afbcd 2172 /* Figure out innner displacement stuff */
a1c7c0f3 2173 if (opP->mode == POST || opP->mode == PRE)
355afbcd 2174 {
8d20a0a8
C		 2175 if (cpu_of_arch (current_architecture) & cpu32)
2176 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
355afbcd
KR		 2177 switch (siz2)
2178 {
a1c7c0f3 2179 case SIZE_UNSPEC:
6700d36e
ILT		 2180 if (isvar (&opP->odisp)
2181 ? m68k_rel32
2182 : ! issword (outro))
355afbcd 2183 {
a1c7c0f3 2184 siz2 = SIZE_LONG;
355afbcd
KR		 2185 nextword |= 0x3;
2186 }
92a25e12 2187 else if (! isvar (&opP->odisp) && outro == 0)
355afbcd
KR		 2188 nextword |= 0x1;
2189 else
2190 {
2191 nextword |= 0x2;
a1c7c0f3 2192 siz2 = SIZE_WORD;
355afbcd
KR		 2193 }
2194 break;
2195 case 1:
a1c7c0f3
ILT		 2196 as_warn (":b not permitted; defaulting to :w");
2197 /* Fall through. */
355afbcd
KR		 2198 case 2:
2199 nextword |= 0x2;
2200 break;
2201 case 3:
2202 nextword |= 0x3;
2203 break;
2204 }
92a25e12
ILT		 2205 if (opP->mode == POST
2206 && (nextword & 0x40) == 0)
355afbcd 2207 nextword |= 0x04;
355afbcd
KR		 2208 }
2209 addword (nextword);
2210
a1c7c0f3 2211 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
355afbcd
KR		 2212 {
2213 if (opP->reg == PC || opP->reg == ZPC)
a1c7c0f3 2214 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
355afbcd 2215 else
a1c7c0f3 2216 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
355afbcd 2217 }
a1c7c0f3 2218 if (siz1 == SIZE_LONG)
355afbcd 2219 addword (baseo >> 16);
a1c7c0f3 2220 if (siz1 != SIZE_UNSPEC)
355afbcd
KR		 2221 addword (baseo);
2222
a1c7c0f3
ILT		 2223 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2224 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2225 if (siz2 == SIZE_LONG)
355afbcd 2226 addword (outro >> 16);
a1c7c0f3 2227 if (siz2 != SIZE_UNSPEC)
355afbcd 2228 addword (outro);
6d27d3a2 2229
355afbcd 2230 break;
6d27d3a2 2231
355afbcd 2232 case ABSL:
a1c7c0f3
ILT		 2233 nextword = get_num (&opP->disp, 80);
2234 switch (opP->disp.size)
355afbcd
KR		 2235 {
2236 default:
a1c7c0f3
ILT		 2237 abort ();
2238 case SIZE_UNSPEC:
2239 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
355afbcd
KR		 2240 {
2241 tmpreg = 0x38; /* 7.0 */
2242 addword (nextword);
2243 break;
2244 }
bcb8dff8
KR		 2245 /* Don't generate pc relative code on 68010 and
2246 68000. */
a1c7c0f3
ILT		 2247 if (isvar (&opP->disp)
2248 && !subs (&opP->disp)
2249 && adds (&opP->disp)
a043f579
ILT		 2250#ifdef OBJ_ELF
2251 /* If the displacement needs pic relocation it
2252 cannot be relaxed. */
2253 && opP->disp.pic_reloc == pic_none
2254#endif
f00f5ecd 2255 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
ffecfc8b 2256 && HAVE_LONG_BRANCH(current_architecture)
9ad5755f 2257 && !flag_long_jumps
355afbcd
KR		 2258 && !strchr ("~%&$?", s[0]))
2259 {
2260 tmpreg = 0x3A; /* 7.2 */
a1c7c0f3
ILT		 2261 add_frag (adds (&opP->disp),
2262 offs (&opP->disp),
355afbcd
KR		 2263 TAB (PCREL, SZ_UNDEF));
2264 break;
2265 }
04ef74bb 2266 /* Fall through into long */
a1c7c0f3
ILT		 2267 case SIZE_LONG:
2268 if (isvar (&opP->disp))
2269 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 2270
2271 tmpreg = 0x39;/* 7.1 mode */
2272 addword (nextword >> 16);
2273 addword (nextword);
2274 break;
2275
a1c7c0f3
ILT		 2276 case SIZE_WORD: /* Word */
2277 if (isvar (&opP->disp))
2278 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 2279
2280 tmpreg = 0x38;/* 7.0 mode */
2281 addword (nextword);
2282 break;
2283 }
2284 break;
a1c7c0f3
ILT		 2285 case CONTROL:
2286 case FPREG:
355afbcd
KR		 2287 default:
2288 as_bad ("unknown/incorrect operand");
2289 /* abort(); */
2290 }
2291 install_gen_operand (s[1], tmpreg);
6d27d3a2 2292 break;
6d27d3a2 2293
355afbcd
KR		 2294 case '#':
2295 case '^':
2296 switch (s[1])
2297 { /* JF: I hate floating point! */
2298 case 'j':
2299 tmpreg = 70;
2300 break;
2301 case '8':
2302 tmpreg = 20;
2303 break;
2304 case 'C':
2305 tmpreg = 50;
2306 break;
2307 case '3':
2308 default:
2309 tmpreg = 80;
2310 break;
2311 }
a1c7c0f3
ILT		 2312 tmpreg = get_num (&opP->disp, tmpreg);
2313 if (isvar (&opP->disp))
2314 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 2315 switch (s[1])
2316 {
2317 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 2318 certain types of overflow.
2319 user beware! */
355afbcd
KR		 2320 if (!isbyte (tmpreg))
2321 opP->error = "out of range";
bcb8dff8 2322 insop (tmpreg, opcode);
a1c7c0f3 2323 if (isvar (&opP->disp))
d9396c16
ILT		 2324 the_ins.reloc[the_ins.nrel - 1].n =
2325 (opcode->m_codenum) * 2 + 1;
355afbcd 2326 break;
a78bc551
ILT		 2327 case 'B':
2328 if (!issbyte (tmpreg))
2329 opP->error = "out of range";
2330 opcode->m_opcode |= tmpreg;
2331 if (isvar (&opP->disp))
2332 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2333 break;
355afbcd
KR		 2334 case 'w':
2335 if (!isword (tmpreg))
2336 opP->error = "out of range";
bcb8dff8 2337 insop (tmpreg, opcode);
a1c7c0f3 2338 if (isvar (&opP->disp))
355afbcd
KR		 2339 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2340 break;
9e64486e
ILT		 2341 case 'W':
2342 if (!issword (tmpreg))
2343 opP->error = "out of range";
2344 insop (tmpreg, opcode);
2345 if (isvar (&opP->disp))
2346 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2347 break;
355afbcd 2348 case 'l':
bcb8dff8
KR		 2349 /* Because of the way insop works, we put these two out
2350 backwards. */
2351 insop (tmpreg, opcode);
2352 insop (tmpreg >> 16, opcode);
a1c7c0f3 2353 if (isvar (&opP->disp))
355afbcd
KR		 2354 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2355 break;
2356 case '3':
2357 tmpreg &= 0xFF;
2358 case '8':
2359 case 'C':
2360 install_operand (s[1], tmpreg);
2361 break;
2362 default:
a1c7c0f3 2363 abort ();
355afbcd
KR		 2364 }
2365 break;
6d27d3a2 2366
355afbcd
KR		 2367 case '+':
2368 case '-':
2369 case 'A':
2370 case 'a':
2371 install_operand (s[1], opP->reg - ADDR);
2372 break;
6d27d3a2 2373
355afbcd 2374 case 'B':
a1c7c0f3 2375 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2376 switch (s[1])
2377 {
2378 case 'B':
b4ec75e0
ILT		 2379 /* The pc_fix argument winds up in fx_pcrel_adjust,
2380 which is a char, and may therefore be unsigned. We
2381 want to pass -1, but we pass 64 instead, and convert
2382 back in md_pcrel_from. */
2383 add_fix ('B', &opP->disp, 1, 64);
355afbcd
KR		 2384 break;
2385 case 'W':
a1c7c0f3 2386 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2387 addword (0);
2388 break;
2389 case 'L':
2390 long_branch:
ffecfc8b
C		 2391 if (!HAVE_LONG_BRANCH(current_architecture))
2392 as_warn ("Can't use long branches on 68000/68010/5200");
355afbcd 2393 the_ins.opcode[the_ins.numo - 1] |= 0xff;
a1c7c0f3 2394 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2395 addword (0);
2396 addword (0);
2397 break;
2398 case 'g':
a1c7c0f3 2399 if (subs (&opP->disp)) /* We can't relax it */
355afbcd 2400 goto long_branch;
6d27d3a2 2401
a043f579
ILT		 2402#ifdef OBJ_ELF
2403 /* If the displacement needs pic relocation it cannot be
2404 relaxed. */
2405 if (opP->disp.pic_reloc != pic_none)
2406 goto long_branch;
2407#endif
2408
a1c7c0f3
ILT		 2409 /* This could either be a symbol, or an absolute
2410 address. No matter, the frag hacking will finger it
2411 out. Not quite: it can't switch from BRANCH to
2412 BCC68000 for the case where opnd is absolute (it
2413 needs to use the 68000 hack since no conditional abs
2414 jumps). */
ffecfc8b 2415 if (( !HAVE_LONG_BRANCH(current_architecture)
a1c7c0f3 2416 || (0 == adds (&opP->disp)))
355afbcd
KR		 2417 && (the_ins.opcode[0] >= 0x6200)
2418 && (the_ins.opcode[0] <= 0x6f00))
a1c7c0f3
ILT		 2419 add_frag (adds (&opP->disp), offs (&opP->disp),
2420 TAB (BCC68000, SZ_UNDEF));
355afbcd 2421 else
a1c7c0f3
ILT		 2422 add_frag (adds (&opP->disp), offs (&opP->disp),
2423 TAB (ABRANCH, SZ_UNDEF));
355afbcd
KR		 2424 break;
2425 case 'w':
a1c7c0f3 2426 if (isvar (&opP->disp))
355afbcd 2427 {
49864cfa 2428#if 1
355afbcd
KR		 2429 /* check for DBcc instruction */
2430 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2431 {
2432 /* size varies if patch */
2433 /* needed for long form */
a1c7c0f3 2434 add_frag (adds (&opP->disp), offs (&opP->disp),
b79de3a1 2435 TAB (DBCC, SZ_UNDEF));
355afbcd
KR		 2436 break;
2437 }
49864cfa 2438#endif
a1c7c0f3 2439 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2440 }
2441 addword (0);
2442 break;
2443 case 'C': /* Fixed size LONG coproc branches */
a1c7c0f3 2444 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2445 addword (0);
2446 addword (0);
2447 break;
2448 case 'c': /* Var size Coprocesssor branches */
a1c7c0f3 2449 if (subs (&opP->disp))
355afbcd 2450 {
a1c7c0f3 2451 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2452 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2453 }
a1c7c0f3
ILT		 2454 else if (adds (&opP->disp))
2455 add_frag (adds (&opP->disp), offs (&opP->disp),
2456 TAB (FBRANCH, SZ_UNDEF));
355afbcd
KR		 2457 else
2458 {
a1c7c0f3
ILT		 2459 /* add_frag((symbolS *) 0, offs(&opP->disp),
2460 TAB(FBRANCH,SHORT)); */
355afbcd 2461 the_ins.opcode[the_ins.numo - 1] |= 0x40;
a1c7c0f3 2462 add_fix ('l', &opP->disp, 1, 0);
5f8cb05e 2463 addword (0);
355afbcd 2464 addword (0);
355afbcd
KR		 2465 }
2466 break;
2467 default:
a1c7c0f3 2468 abort ();
355afbcd
KR		 2469 }
2470 break;
6d27d3a2 2471
355afbcd
KR		 2472 case 'C': /* Ignore it */
2473 break;
6d27d3a2 2474
355afbcd 2475 case 'd': /* JF this is a kludge */
a1c7c0f3
ILT		 2476 install_operand ('s', opP->reg - ADDR);
2477 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2478 if (!issword (tmpreg))
2479 {
2480 as_warn ("Expression out of range, using 0");
2481 tmpreg = 0;
2482 }
2483 addword (tmpreg);
2484 break;
6d27d3a2 2485
355afbcd
KR		 2486 case 'D':
2487 install_operand (s[1], opP->reg - DATA);
2488 break;
6d27d3a2 2489
355afbcd 2490 case 'F':
a1c7c0f3 2491 install_operand (s[1], opP->reg - FP0);
355afbcd 2492 break;
6d27d3a2 2493
355afbcd 2494 case 'I':
27a53b88 2495 tmpreg = opP->reg - COP0;
355afbcd
KR		 2496 install_operand (s[1], tmpreg);
2497 break;
6d27d3a2 2498
355afbcd
KR		 2499 case 'J': /* JF foo */
2500 switch (opP->reg)
2501 {
2502 case SFC:
2503 tmpreg = 0x000;
2504 break;
2505 case DFC:
2506 tmpreg = 0x001;
2507 break;
2508 case CACR:
2509 tmpreg = 0x002;
2510 break;
2511 case TC:
2512 tmpreg = 0x003;
2513 break;
2514 case ITT0:
2515 tmpreg = 0x004;
2516 break;
2517 case ITT1:
2518 tmpreg = 0x005;
2519 break;
2520 case DTT0:
2521 tmpreg = 0x006;
2522 break;
2523 case DTT1:
2524 tmpreg = 0x007;
2525 break;
9ad5755f
KR		 2526 case BUSCR:
2527 tmpreg = 0x008;
2528 break;
6d27d3a2 2529
355afbcd
KR		 2530 case USP:
2531 tmpreg = 0x800;
2532 break;
2533 case VBR:
2534 tmpreg = 0x801;
2535 break;
2536 case CAAR:
2537 tmpreg = 0x802;
2538 break;
2539 case MSP:
2540 tmpreg = 0x803;
2541 break;
2542 case ISP:
2543 tmpreg = 0x804;
2544 break;
2545 case MMUSR:
2546 tmpreg = 0x805;
2547 break;
2548 case URP:
2549 tmpreg = 0x806;
2550 break;
2551 case SRP:
2552 tmpreg = 0x807;
2553 break;
9ad5755f
KR		 2554 case PCR:
2555 tmpreg = 0x808;
2556 break;
8d20a0a8
C		 2557 case ROMBAR:
2558 tmpreg = 0xC00;
2559 break;
2560 case RAMBAR0:
2561 tmpreg = 0xC04;
2562 break;
2563 case RAMBAR1:
2564 tmpreg = 0xC05;
2565 break;
2566 case MBAR:
2567 tmpreg = 0xC0F;
2568 break;
355afbcd 2569 default:
a1c7c0f3 2570 abort ();
355afbcd
KR		 2571 }
2572 install_operand (s[1], tmpreg);
2573 break;
6d27d3a2 2574
355afbcd 2575 case 'k':
a1c7c0f3 2576 tmpreg = get_num (&opP->disp, 55);
355afbcd
KR		 2577 install_operand (s[1], tmpreg & 0x7f);
2578 break;
6d27d3a2 2579
355afbcd 2580 case 'l':
a1c7c0f3 2581 tmpreg = opP->mask;
355afbcd
KR		 2582 if (s[1] == 'w')
2583 {
2584 if (tmpreg & 0x7FF0000)
2585 as_bad ("Floating point register in register list");
bcb8dff8 2586 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 2587 }
2588 else
2589 {
2590 if (tmpreg & 0x700FFFF)
2591 as_bad ("Wrong register in floating-point reglist");
2592 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2593 }
2594 break;
6d27d3a2 2595
355afbcd 2596 case 'L':
a1c7c0f3 2597 tmpreg = opP->mask;
355afbcd
KR		 2598 if (s[1] == 'w')
2599 {
2600 if (tmpreg & 0x7FF0000)
2601 as_bad ("Floating point register in register list");
bcb8dff8 2602 insop (tmpreg, opcode);
355afbcd
KR		 2603 }
2604 else if (s[1] == '8')
2605 {
2606 if (tmpreg & 0x0FFFFFF)
2607 as_bad ("incorrect register in reglist");
2608 install_operand (s[1], tmpreg >> 24);
2609 }
2610 else
2611 {
2612 if (tmpreg & 0x700FFFF)
2613 as_bad ("wrong register in floating-point reglist");
2614 else
2615 install_operand (s[1], tmpreg >> 16);
2616 }
2617 break;
6d27d3a2 2618
355afbcd 2619 case 'M':
a1c7c0f3 2620 install_operand (s[1], get_num (&opP->disp, 60));
355afbcd 2621 break;
6d27d3a2 2622
355afbcd 2623 case 'O':
a1c7c0f3
ILT		 2624 tmpreg = ((opP->mode == DREG)
2625 ? 0x20 + opP->reg - DATA
2626 : (get_num (&opP->disp, 40) & 0x1F));
355afbcd
KR		 2627 install_operand (s[1], tmpreg);
2628 break;
6d27d3a2 2629
355afbcd 2630 case 'Q':
a1c7c0f3 2631 tmpreg = get_num (&opP->disp, 10);
355afbcd
KR		 2632 if (tmpreg == 8)
2633 tmpreg = 0;
2634 install_operand (s[1], tmpreg);
2635 break;
2636
2637 case 'R':
a1c7c0f3
ILT		 2638 /* This depends on the fact that ADDR registers are eight
2639 more than their corresponding DATA regs, so the result
2640 will have the ADDR_REG bit set */
355afbcd
KR		 2641 install_operand (s[1], opP->reg - DATA);
2642 break;
6d27d3a2 2643
a1c7c0f3
ILT		 2644 case 'r':
2645 if (opP->mode == AINDR)
2646 install_operand (s[1], opP->reg - DATA);
2647 else
2648 install_operand (s[1], opP->index.reg - DATA);
2649 break;
2650
355afbcd
KR		 2651 case 's':
2652 if (opP->reg == FPI)
2653 tmpreg = 0x1;
2654 else if (opP->reg == FPS)
2655 tmpreg = 0x2;
2656 else if (opP->reg == FPC)
2657 tmpreg = 0x4;
2658 else
a1c7c0f3 2659 abort ();
355afbcd
KR		 2660 install_operand (s[1], tmpreg);
2661 break;
6d27d3a2 2662
355afbcd
KR		 2663 case 'S': /* Ignore it */
2664 break;
6d27d3a2 2665
355afbcd 2666 case 'T':
a1c7c0f3 2667 install_operand (s[1], get_num (&opP->disp, 30));
355afbcd 2668 break;
6d27d3a2 2669
355afbcd
KR		 2670 case 'U': /* Ignore it */
2671 break;
6d27d3a2 2672
355afbcd
KR		 2673 case 'c':
2674 switch (opP->reg)
2675 {
2676 case NC:
2677 tmpreg = 0;
2678 break;
2679 case DC:
2680 tmpreg = 1;
2681 break;
2682 case IC:
2683 tmpreg = 2;
2684 break;
2685 case BC:
2686 tmpreg = 3;
2687 break;
2688 default:
2689 as_fatal ("failed sanity check");
2690 } /* switch on cache token */
2691 install_operand (s[1], tmpreg);
2692 break;
a39116f1 2693#ifndef NO_68851
355afbcd
KR		 2694 /* JF: These are out of order, I fear. */
2695 case 'f':
2696 switch (opP->reg)
2697 {
2698 case SFC:
2699 tmpreg = 0;
2700 break;
2701 case DFC:
2702 tmpreg = 1;
2703 break;
2704 default:
a1c7c0f3 2705 abort ();
355afbcd
KR		 2706 }
2707 install_operand (s[1], tmpreg);
2708 break;
6d27d3a2 2709
9adcd781
ILT		 2710 case '0':
2711 case '1':
2712 case '2':
355afbcd
KR		 2713 switch (opP->reg)
2714 {
2715 case TC:
2716 tmpreg = 0;
2717 break;
2718 case CAL:
2719 tmpreg = 4;
2720 break;
2721 case VAL:
2722 tmpreg = 5;
2723 break;
2724 case SCC:
2725 tmpreg = 6;
2726 break;
2727 case AC:
2728 tmpreg = 7;
2729 break;
2730 default:
a1c7c0f3 2731 abort ();
355afbcd
KR		 2732 }
2733 install_operand (s[1], tmpreg);
2734 break;
6d27d3a2 2735
355afbcd
KR		 2736 case 'V':
2737 if (opP->reg == VAL)
2738 break;
a1c7c0f3 2739 abort ();
6d27d3a2 2740
355afbcd
KR		 2741 case 'W':
2742 switch (opP->reg)
2743 {
355afbcd
KR		 2744 case DRP:
2745 tmpreg = 1;
2746 break;
2747 case SRP:
2748 tmpreg = 2;
2749 break;
2750 case CRP:
2751 tmpreg = 3;
2752 break;
2753 default:
a1c7c0f3 2754 abort ();
355afbcd
KR		 2755 }
2756 install_operand (s[1], tmpreg);
2757 break;
6d27d3a2 2758
355afbcd
KR		 2759 case 'X':
2760 switch (opP->reg)
2761 {
2762 case BAD:
2763 case BAD + 1:
2764 case BAD + 2:
2765 case BAD + 3:
2766 case BAD + 4:
2767 case BAD + 5:
2768 case BAD + 6:
2769 case BAD + 7:
2770 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2771 break;
6d27d3a2 2772
355afbcd
KR		 2773 case BAC:
2774 case BAC + 1:
2775 case BAC + 2:
2776 case BAC + 3:
2777 case BAC + 4:
2778 case BAC + 5:
2779 case BAC + 6:
2780 case BAC + 7:
2781 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2782 break;
6d27d3a2 2783
355afbcd 2784 default:
a1c7c0f3 2785 abort ();
355afbcd
KR		 2786 }
2787 install_operand (s[1], tmpreg);
2788 break;
2789 case 'Y':
2790 know (opP->reg == PSR);
2791 break;
2792 case 'Z':
2793 know (opP->reg == PCSR);
2794 break;
f8701a3f 2795#endif /* m68851 */
355afbcd
KR		 2796 case '3':
2797 switch (opP->reg)
2798 {
2799 case TT0:
2800 tmpreg = 2;
2801 break;
2802 case TT1:
2803 tmpreg = 3;
2804 break;
2805 default:
a1c7c0f3 2806 abort ();
355afbcd
KR		 2807 }
2808 install_operand (s[1], tmpreg);
2809 break;
2810 case 't':
a1c7c0f3 2811 tmpreg = get_num (&opP->disp, 20);
355afbcd 2812 install_operand (s[1], tmpreg);
4134a793 2813 break;
a1c7c0f3
ILT		 2814 case '_': /* used only for move16 absolute 32-bit address */
2815 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2816 addword (tmpreg >> 16);
2817 addword (tmpreg & 0xFFFF);
4134a793
KR		 2818 break;
2819 default:
a1c7c0f3 2820 abort ();
4134a793 2821 }
6d27d3a2 2822 }
3ad9ec6a 2823
6d27d3a2
KR		 2824 /* By the time whe get here (FINALLY) the_ins contains the complete
2825 instruction, ready to be emitted. . . */
a1c7c0f3 2826}
fecd2382 2827
355afbcd
KR		 2828static int
2829reverse_16_bits (in)
2830 int in;
fecd2382 2831{
355afbcd
KR		 2832 int out = 0;
2833 int n;
6d27d3a2 2834
355afbcd
KR		 2835 static int mask[16] =
2836 {
2837 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2838 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2839 };
2840 for (n = 0; n < 16; n++)
2841 {
2842 if (in & mask[n])
2843 out |= mask[15 - n];
2844 }
2845 return out;
2846} /* reverse_16_bits() */
fecd2382 2847
355afbcd
KR		 2848static int
2849reverse_8_bits (in)
2850 int in;
fecd2382 2851{
355afbcd
KR		 2852 int out = 0;
2853 int n;
6d27d3a2 2854
355afbcd
KR		 2855 static int mask[8] =
2856 {
2857 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2858 };
6d27d3a2 2859
355afbcd
KR		 2860 for (n = 0; n < 8; n++)
2861 {
2862 if (in & mask[n])
2863 out |= mask[7 - n];
2864 }
2865 return out;
2866} /* reverse_8_bits() */
fecd2382 2867
04ef74bb
KR		 2868/* Cause an extra frag to be generated here, inserting up to 10 bytes
2869 (that value is chosen in the frag_var call in md_assemble). TYPE
2870 is the subtype of the frag to be generated; its primary type is
2871 rs_machine_dependent.
2872
2873 The TYPE parameter is also used by md_convert_frag_1 and
2874 md_estimate_size_before_relax. The appropriate type of fixup will
2875 be emitted by md_convert_frag_1.
2876
2877 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355afbcd
KR		 2878static void
2879install_operand (mode, val)
2880 int mode;
2881 int val;
fecd2382 2882{
355afbcd
KR		 2883 switch (mode)
2884 {
2885 case 's':
2886 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2887 break;
2888 case 'd':
2889 the_ins.opcode[0] |= val << 9;
2890 break;
2891 case '1':
2892 the_ins.opcode[1] |= val << 12;
2893 break;
2894 case '2':
2895 the_ins.opcode[1] |= val << 6;
2896 break;
2897 case '3':
2898 the_ins.opcode[1] |= val;
2899 break;
2900 case '4':
2901 the_ins.opcode[2] |= val << 12;
2902 break;
2903 case '5':
2904 the_ins.opcode[2] |= val << 6;
2905 break;
2906 case '6':
bcb8dff8
KR		 2907 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2908 three words long! */
355afbcd
KR		 2909 the_ins.numo++;
2910 the_ins.opcode[2] |= val;
2911 break;
2912 case '7':
2913 the_ins.opcode[1] |= val << 7;
2914 break;
2915 case '8':
2916 the_ins.opcode[1] |= val << 10;
2917 break;
f8701a3f 2918#ifndef NO_68851
355afbcd
KR		 2919 case '9':
2920 the_ins.opcode[1] |= val << 5;
2921 break;
f8701a3f 2922#endif
6d27d3a2 2923
355afbcd
KR		 2924 case 't':
2925 the_ins.opcode[1] |= (val << 10) | (val << 7);
2926 break;
2927 case 'D':
2928 the_ins.opcode[1] |= (val << 12) | val;
2929 break;
2930 case 'g':
2931 the_ins.opcode[0] |= val = 0xff;
2932 break;
2933 case 'i':
2934 the_ins.opcode[0] |= val << 9;
2935 break;
2936 case 'C':
2937 the_ins.opcode[1] |= val;
2938 break;
2939 case 'j':
2940 the_ins.opcode[1] |= val;
2941 the_ins.numo++; /* What a hack */
2942 break;
2943 case 'k':
2944 the_ins.opcode[1] |= val << 4;
2945 break;
2946 case 'b':
2947 case 'w':
9e64486e 2948 case 'W':
355afbcd
KR		 2949 case 'l':
2950 break;
2951 case 'e':
2952 the_ins.opcode[0] |= (val << 6);
2953 break;
2954 case 'L':
2955 the_ins.opcode[1] = (val >> 16);
2956 the_ins.opcode[2] = val & 0xffff;
2957 break;
2958 case 'c':
2959 default:
2960 as_fatal ("failed sanity check.");
2961 }
2962} /* install_operand() */
fecd2382 2963
355afbcd
KR		 2964static void
2965install_gen_operand (mode, val)
2966 int mode;
2967 int val;
fecd2382 2968{
355afbcd
KR		 2969 switch (mode)
2970 {
2971 case 's':
2972 the_ins.opcode[0] |= val;
2973 break;
2974 case 'd':
2975 /* This is a kludge!!! */
2976 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2977 break;
2978 case 'b':
2979 case 'w':
2980 case 'l':
2981 case 'f':
2982 case 'F':
2983 case 'x':
2984 case 'p':
2985 the_ins.opcode[0] |= val;
2986 break;
2987 /* more stuff goes here */
2988 default:
2989 as_fatal ("failed sanity check.");
2990 }
2991} /* install_gen_operand() */
fecd2382 2992
7c15cbe8
RP		 2993/*
2994 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2995 * then deal with the bitfield hack.
2996 */
2997
355afbcd
KR		 2998static char *
2999crack_operand (str, opP)
3000 register char *str;
3001 register struct m68k_op *opP;
fecd2382 3002{
355afbcd
KR		 3003 register int parens;
3004 register int c;
3005 register char *beg_str;
4026c122 3006 int inquote = 0;
6d27d3a2 3007
355afbcd
KR		 3008 if (!str)
3009 {
3010 return str;
3011 }
3012 beg_str = str;
4026c122 3013 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
355afbcd 3014 {
4026c122 3015 if (! inquote)
355afbcd 3016 {
4026c122
ILT		 3017 if (*str == '(')
3018 parens++;
3019 else if (*str == ')')
3020 {
3021 if (!parens)
3022 { /* ERROR */
3023 opP->error = "Extra )";
3024 return str;
3025 }
3026 --parens;
355afbcd 3027 }
f8701a3f 3028 }
4026c122
ILT		 3029 if (flag_mri && *str == '\'')
3030 inquote = ! inquote;
355afbcd
KR		 3031 }
3032 if (!*str && parens)
3033 { /* ERROR */
3034 opP->error = "Missing )";
3035 return str;
3036 }
3037 c = *str;
3038 *str = '\0';
a1c7c0f3 3039 if (m68k_ip_op (beg_str, opP) != 0)
355afbcd
KR		 3040 {
3041 *str = c;
3042 return str;
3043 }
3044 *str = c;
3045 if (c == '}')
3046 c = *++str; /* JF bitfield hack */
3047 if (c)
3048 {
3049 c = *++str;
3050 if (!c)
3051 as_bad ("Missing operand");
3052 }
3053 return str;
fecd2382
RP		 3054}
3055
fecd2382 3056/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 3057 machine dependent instruction. This function is supposed to emit
fecd2382 3058 the frags/bytes it assembles to.
a39116f1 3059 */
a933d598
SC		 3060
3061void
355afbcd
KR		 3062insert_reg (regname, regnum)
3063 char *regname;
3064 int regnum;
a933d598
SC		 3065{
3066 char buf[100];
3067 int i;
355afbcd
KR		 3068
3069#ifdef REGISTER_PREFIX
82489ea0
KR		 3070 if (!flag_reg_prefix_optional)
3071 {
3072 buf[0] = REGISTER_PREFIX;
3073 strcpy (buf + 1, regname);
3074 regname = buf;
3075 }
355afbcd
KR		 3076#endif
3077
82489ea0
KR		 3078 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3079 &zero_address_frag));
a933d598
SC		 3080
3081 for (i = 0; regname[i]; i++)
355afbcd 3082 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 3083 buf[i] = '\0';
6d27d3a2 3084
82489ea0
KR		 3085 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3086 &zero_address_frag));
a933d598
SC		 3087}
3088
49864cfa 3089struct init_entry
355afbcd 3090 {
bcb8dff8 3091 const char *name;
355afbcd 3092 int number;
49864cfa 3093 };
355afbcd 3094
bcb8dff8 3095static const struct init_entry init_table[] =
355afbcd 3096{
bcb8dff8
KR		 3097 { "d0", DATA0 },
3098 { "d1", DATA1 },
3099 { "d2", DATA2 },
3100 { "d3", DATA3 },
3101 { "d4", DATA4 },
3102 { "d5", DATA5 },
3103 { "d6", DATA6 },
3104 { "d7", DATA7 },
3105 { "a0", ADDR0 },
3106 { "a1", ADDR1 },
3107 { "a2", ADDR2 },
3108 { "a3", ADDR3 },
3109 { "a4", ADDR4 },
3110 { "a5", ADDR5 },
3111 { "a6", ADDR6 },
3112 { "fp", ADDR6 },
3113 { "a7", ADDR7 },
3114 { "sp", ADDR7 },
a1c7c0f3 3115 { "ssp", ADDR7 },
bcb8dff8
KR		 3116 { "fp0", FP0 },
3117 { "fp1", FP1 },
3118 { "fp2", FP2 },
3119 { "fp3", FP3 },
3120 { "fp4", FP4 },
3121 { "fp5", FP5 },
3122 { "fp6", FP6 },
3123 { "fp7", FP7 },
3124 { "fpi", FPI },
3125 { "fpiar", FPI },
3126 { "fpc", FPI },
3127 { "fps", FPS },
3128 { "fpsr", FPS },
3129 { "fpc", FPC },
3130 { "fpcr", FPC },
064ba683
ILT		 3131 { "control", FPC },
3132 { "status", FPS },
3133 { "iaddr", FPI },
bcb8dff8
KR		 3134
3135 { "cop0", COP0 },
3136 { "cop1", COP1 },
3137 { "cop2", COP2 },
3138 { "cop3", COP3 },
3139 { "cop4", COP4 },
3140 { "cop5", COP5 },
3141 { "cop6", COP6 },
3142 { "cop7", COP7 },
3143 { "pc", PC },
3144 { "zpc", ZPC },
3145 { "sr", SR },
3146
3147 { "ccr", CCR },
3148 { "cc", CCR },
3149
8d20a0a8
C		 3150 /* control registers */
3151 { "sfc", SFC }, /* Source Function Code */
064ba683 3152 { "sfcr", SFC },
8d20a0a8 3153 { "dfc", DFC }, /* Destination Function Code */
064ba683 3154 { "dfcr", DFC },
8d20a0a8
C		 3155 { "cacr", CACR }, /* Cache Control Register */
3156 { "caar", CAAR }, /* Cache Address Register */
3157
3158 { "usp", USP }, /* User Stack Pointer */
3159 { "vbr", VBR }, /* Vector Base Register */
3160 { "msp", MSP }, /* Master Stack Pointer */
3161 { "isp", ISP }, /* Interrupt Stack Pointer */
3162
3163 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3164 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3165 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3166 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3167
3168 /* 68ec040 versions of same */
3169 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3170 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3171 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3172 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3173
0b810a6e
ILT		 3174 /* mcf5200 versions of same. The ColdFire programmer's reference
3175 manual indicated that the order is 2,3,0,1, but Ken Rose
3176 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3177 { "acr0", ITT0 }, /* Access Control Unit 0 */
3178 { "acr1", ITT1 }, /* Access Control Unit 1 */
3179 { "acr2", DTT0 }, /* Access Control Unit 2 */
3180 { "acr3", DTT1 }, /* Access Control Unit 3 */
8d20a0a8
C		 3181
3182 { "tc", TC }, /* MMU Translation Control Register */
3183 { "tcr", TC },
3184
3185 { "mmusr", MMUSR }, /* MMU Status Register */
3186 { "srp", SRP }, /* User Root Pointer */
3187 { "urp", URP }, /* Supervisor Root Pointer */
3188
9ad5755f
KR		 3189 { "buscr", BUSCR },
3190 { "pcr", PCR },
bcb8dff8 3191
8d20a0a8
C		 3192 { "rombar", ROMBAR }, /* ROM Base Address Register */
3193 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3194 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3195 { "mbar", MBAR }, /* Module Base Address Register */
3196 /* end of control registers */
3197
bcb8dff8
KR		 3198 { "ac", AC },
3199 { "bc", BC },
3200 { "cal", CAL },
3201 { "crp", CRP },
3202 { "drp", DRP },
3203 { "pcsr", PCSR },
3204 { "psr", PSR },
3205 { "scc", SCC },
3206 { "val", VAL },
3207 { "bad0", BAD0 },
3208 { "bad1", BAD1 },
3209 { "bad2", BAD2 },
3210 { "bad3", BAD3 },
3211 { "bad4", BAD4 },
3212 { "bad5", BAD5 },
3213 { "bad6", BAD6 },
3214 { "bad7", BAD7 },
3215 { "bac0", BAC0 },
3216 { "bac1", BAC1 },
3217 { "bac2", BAC2 },
3218 { "bac3", BAC3 },
3219 { "bac4", BAC4 },
3220 { "bac5", BAC5 },
3221 { "bac6", BAC6 },
3222 { "bac7", BAC7 },
3223
3224 { "ic", IC },
3225 { "dc", DC },
3226 { "nc", NC },
3227
3228 { "tt0", TT0 },
3229 { "tt1", TT1 },
4134a793 3230 /* 68ec030 versions of same */
bcb8dff8
KR		 3231 { "ac0", TT0 },
3232 { "ac1", TT1 },
4134a793 3233 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 3234 { "acusr", PSR },
a933d598 3235
a1c7c0f3
ILT		 3236 /* Suppressed data and address registers. */
3237 { "zd0", ZDATA0 },
3238 { "zd1", ZDATA1 },
3239 { "zd2", ZDATA2 },
3240 { "zd3", ZDATA3 },
3241 { "zd4", ZDATA4 },
3242 { "zd5", ZDATA5 },
3243 { "zd6", ZDATA6 },
3244 { "zd7", ZDATA7 },
3245 { "za0", ZADDR0 },
3246 { "za1", ZADDR1 },
3247 { "za2", ZADDR2 },
3248 { "za3", ZADDR3 },
3249 { "za4", ZADDR4 },
3250 { "za5", ZADDR5 },
3251 { "za6", ZADDR6 },
3252 { "za7", ZADDR7 },
3253
bcb8dff8 3254 { 0, 0 }
a933d598
SC		 3255};
3256
a933d598 3257void
355afbcd 3258init_regtable ()
a933d598
SC		 3259{
3260 int i;
6d27d3a2 3261 for (i = 0; init_table[i].name; i++)
355afbcd 3262 insert_reg (init_table[i].name, init_table[i].number);
a933d598 3263}
6d27d3a2 3264
df3768fb 3265static int no_68851, no_68881;
a933d598 3266
dff60b7d
ILT		 3267#ifdef OBJ_AOUT
3268/* a.out machine type. Default to 68020. */
3269int m68k_aout_machtype = 2;
3270#endif
3271
fecd2382 3272void
355afbcd 3273md_assemble (str)
6d27d3a2 3274 char *str;
fecd2382 3275{
a1c7c0f3 3276 const char *er;
355afbcd
KR		 3277 short *fromP;
3278 char *toP = NULL;
3279 int m, n = 0;
3280 char *to_beg_P;
3281 int shorts_this_frag;
5f8cb05e 3282 fixS *fixP;
6d27d3a2 3283
4026c122
ILT		 3284 /* In MRI mode, the instruction and operands are separated by a
3285 space. Anything following the operands is a comment. The label
3286 has already been removed. */
3287 if (flag_mri)
3288 {
3289 char *s;
3290 int fields = 0;
3291 int infield = 0;
3292 int inquote = 0;
3293
3294 for (s = str; *s != '\0'; s++)
3295 {
3296 if ((*s == ' ' || *s == '\t') && ! inquote)
3297 {
3298 if (infield)
3299 {
3300 ++fields;
3301 if (fields >= 2)
3302 {
3303 *s = '\0';
3304 break;
3305 }
3306 infield = 0;
3307 }
3308 }
3309 else
3310 {
3311 if (! infield)
3312 infield = 1;
3313 if (*s == '\'')
3314 inquote = ! inquote;
3315 }
3316 }
3317 }
3318
e284846a 3319 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 3320 m68k_ip (str);
3321 er = the_ins.error;
3322 if (!er)
3323 {
a1c7c0f3 3324 for (n = 0; n < the_ins.numargs; n++)
355afbcd
KR		 3325 if (the_ins.operands[n].error)
3326 {
3327 er = the_ins.operands[n].error;
3328 break;
3329 }
3330 }
3331 if (er)
3332 {
3333 as_bad ("%s -- statement `%s' ignored", er, str);
3334 return;
3335 }
6d27d3a2 3336
d703b5a7
ILT		 3337 /* If there is a current label, record that it marks an instruction. */
3338 if (current_label != NULL)
3339 {
3340 current_label->text = 1;
3341 current_label = NULL;
3342 }
3343
355afbcd 3344 if (the_ins.nfrag == 0)
49864cfa
KR		 3345 {
3346 /* No frag hacking involved; just put it out */
355afbcd
KR		 3347 toP = frag_more (2 * the_ins.numo);
3348 fromP = &the_ins.opcode[0];
3349 for (m = the_ins.numo; m; --m)
3350 {
3351 md_number_to_chars (toP, (long) (*fromP), 2);
3352 toP += 2;
3353 fromP++;
f8701a3f 3354 }
355afbcd
KR		 3355 /* put out symbol-dependent info */
3356 for (m = 0; m < the_ins.nrel; m++)
3357 {
3358 switch (the_ins.reloc[m].wid)
3359 {
3360 case 'B':
3361 n = 1;
3362 break;
3363 case 'b':
3364 n = 1;
3365 break;
3366 case '3':
0b810a6e 3367 n = 1;
355afbcd
KR		 3368 break;
3369 case 'w':
3370 n = 2;
3371 break;
3372 case 'l':
3373 n = 4;
3374 break;
3375 default:
49864cfa
KR		 3376 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3377 the_ins.reloc[m].wid);
355afbcd 3378 }
6d27d3a2 3379
5f8cb05e
ILT		 3380 fixP = fix_new_exp (frag_now,
3381 ((toP - frag_now->fr_literal)
3382 - the_ins.numo * 2 + the_ins.reloc[m].n),
3383 n,
3384 &the_ins.reloc[m].exp,
3385 the_ins.reloc[m].pcrel,
a043f579
ILT		 3386 get_reloc_code (n, the_ins.reloc[m].pcrel,
3387 the_ins.reloc[m].pic_reloc));
5f8cb05e 3388 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
a78bc551
ILT		 3389 if (the_ins.reloc[m].wid == 'B')
3390 fixP->fx_signed = 1;
f8701a3f 3391 }
355afbcd
KR		 3392 return;
3393 }
3394
3395 /* There's some frag hacking */
3396 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3397 {
3398 int wid;
3399
3400 if (n == 0)
3401 wid = 2 * the_ins.fragb[n].fragoff;
3402 else
3403 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3404 toP = frag_more (wid);
3405 to_beg_P = toP;
3406 shorts_this_frag = 0;
3407 for (m = wid / 2; m; --m)
3408 {
3409 md_number_to_chars (toP, (long) (*fromP), 2);
3410 toP += 2;
3411 fromP++;
3412 shorts_this_frag++;
3413 }
3414 for (m = 0; m < the_ins.nrel; m++)
3415 {
49864cfa 3416 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 3417 {
49864cfa 3418 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 3419 break;
3420 }
3421 wid = the_ins.reloc[m].wid;
3422 if (wid == 0)
3423 continue;
3424 the_ins.reloc[m].wid = 0;
3425 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3426
5f8cb05e
ILT		 3427 fixP = fix_new_exp (frag_now,
3428 ((toP - frag_now->fr_literal)
3429 - the_ins.numo * 2 + the_ins.reloc[m].n),
3430 wid,
3431 &the_ins.reloc[m].exp,
3432 the_ins.reloc[m].pcrel,
a043f579
ILT		 3433 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3434 the_ins.reloc[m].pic_reloc));
5f8cb05e 3435 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
fecd2382 3436 }
49864cfa
KR		 3437 (void) frag_var (rs_machine_dependent, 10, 0,
3438 (relax_substateT) (the_ins.fragb[n].fragty),
3439 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 3440 }
3441 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3442 shorts_this_frag = 0;
3443 if (n)
3444 {
3445 toP = frag_more (n * sizeof (short));
3446 while (n--)
3447 {
3448 md_number_to_chars (toP, (long) (*fromP), 2);
3449 toP += 2;
3450 fromP++;
3451 shorts_this_frag++;
fecd2382 3452 }
355afbcd
KR		 3453 }
3454 for (m = 0; m < the_ins.nrel; m++)
3455 {
3456 int wid;
3457
3458 wid = the_ins.reloc[m].wid;
3459 if (wid == 0)
3460 continue;
3461 the_ins.reloc[m].wid = 0;
3462 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3463
5f8cb05e
ILT		 3464 fixP = fix_new_exp (frag_now,
3465 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3466 - shorts_this_frag * 2),
3467 wid,
3468 &the_ins.reloc[m].exp,
3469 the_ins.reloc[m].pcrel,
a043f579
ILT		 3470 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3471 the_ins.reloc[m].pic_reloc));
5f8cb05e 3472 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
355afbcd 3473 }
fecd2382
RP		 3474}
3475
fecd2382 3476void
355afbcd 3477md_begin ()
fecd2382 3478{
355afbcd 3479 /*
e284846a
KR		 3480 * md_begin -- set up hash tables with 68000 instructions.
3481 * similar to what the vax assembler does. ---phr
3482 */
355afbcd 3483 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 3484 a copy of it at runtime, adding in the information we want but isn't
3485 there. I think it'd be better to have an awk script hack the table
3486 at compile time. Or even just xstr the table and use it as-is. But
3487 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3488 names. */
6d27d3a2 3489
b79de3a1 3490 register const struct m68k_opcode *ins;
355afbcd 3491 register struct m68k_incant *hack, *slak;
bcb8dff8 3492 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 3493 register unsigned int i;
3494 register char c;
3495
064ba683 3496 if (flag_mri)
6700d36e
ILT		 3497 {
3498 flag_reg_prefix_optional = 1;
3499 m68k_abspcadd = 1;
924160b0
ILT		 3500 if (! m68k_rel32_from_cmdline)
3501 m68k_rel32 = 0;
6700d36e 3502 }
064ba683 3503
82489ea0 3504 op_hash = hash_new ();
355afbcd
KR		 3505
3506 obstack_begin (&robyn, 4000);
a1c7c0f3 3507 for (i = 0; i < m68k_numopcodes; i++)
355afbcd
KR		 3508 {
3509 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3510 do
3511 {
a1c7c0f3 3512 ins = &m68k_opcodes[i];
e284846a
KR		 3513 /* We *could* ignore insns that don't match our arch here
3514 but just leaving them out of the hash. */
355afbcd
KR		 3515 slak->m_operands = ins->args;
3516 slak->m_opnum = strlen (slak->m_operands) / 2;
3517 slak->m_arch = ins->arch;
3518 slak->m_opcode = ins->opcode;
3519 /* This is kludgey */
3520 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
a1c7c0f3
ILT		 3521 if (i + 1 != m68k_numopcodes
3522 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
355afbcd
KR		 3523 {
3524 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 3525 i++;
355afbcd
KR		 3526 }
3527 else
3528 slak->m_next = 0;
3529 slak = slak->m_next;
f8701a3f 3530 }
355afbcd
KR		 3531 while (slak);
3532
3533 retval = hash_insert (op_hash, ins->name, (char *) hack);
dff60b7d 3534 if (retval)
b79de3a1
KR		 3535 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3536 }
3537
a1c7c0f3 3538 for (i = 0; i < m68k_numaliases; i++)
b79de3a1
KR		 3539 {
3540 const char *name = m68k_opcode_aliases[i].primary;
3541 const char *alias = m68k_opcode_aliases[i].alias;
3542 PTR val = hash_find (op_hash, name);
3543 if (!val)
3544 as_fatal ("Internal Error: Can't find %s in hash table", name);
3545 retval = hash_insert (op_hash, alias, val);
3546 if (retval)
3547 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
355afbcd 3548 }
6d27d3a2 3549
6700d36e
ILT		 3550 /* In MRI mode, all unsized branches are variable sized. Normally,
3551 they are word sized. */
3552 if (flag_mri)
3553 {
3554 static struct m68k_opcode_alias mri_aliases[] =
3555 {
3556 { "bhi", "jhi", },
3557 { "bls", "jls", },
3558 { "bcc", "jcc", },
3559 { "bcs", "jcs", },
3560 { "bne", "jne", },
3561 { "beq", "jeq", },
3562 { "bvc", "jvc", },
3563 { "bvs", "jvs", },
3564 { "bpl", "jpl", },
3565 { "bmi", "jmi", },
3566 { "bge", "jge", },
3567 { "blt", "jlt", },
3568 { "bgt", "jgt", },
3569 { "ble", "jle", },
3570 { "bra", "jra", },
3571 { "bsr", "jbsr", },
3572 };
3573
3574 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3575 {
3576 const char *name = mri_aliases[i].primary;
3577 const char *alias = mri_aliases[i].alias;
3578 PTR val = hash_find (op_hash, name);
3579 if (!val)
3580 as_fatal ("Internal Error: Can't find %s in hash table", name);
3581 retval = hash_jam (op_hash, alias, val);
3582 if (retval)
3583 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3584 }
3585 }
3586
355afbcd
KR		 3587 for (i = 0; i < sizeof (mklower_table); i++)
3588 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3589
355afbcd
KR		 3590 for (i = 0; i < sizeof (notend_table); i++)
3591 {
3592 notend_table[i] = 0;
3593 alt_notend_table[i] = 0;
3594 }
3595 notend_table[','] = 1;
3596 notend_table['{'] = 1;
3597 notend_table['}'] = 1;
3598 alt_notend_table['a'] = 1;
3599 alt_notend_table['A'] = 1;
3600 alt_notend_table['d'] = 1;
3601 alt_notend_table['D'] = 1;
3602 alt_notend_table['#'] = 1;
5f8cb05e 3603 alt_notend_table['&'] = 1;
355afbcd
KR		 3604 alt_notend_table['f'] = 1;
3605 alt_notend_table['F'] = 1;
fecd2382 3606#ifdef REGISTER_PREFIX
355afbcd 3607 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3608#endif
f8701a3f 3609
a1c7c0f3
ILT		 3610 /* We need to put '(' in alt_notend_table to handle
3611 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3612 */
3613 alt_notend_table['('] = 1;
3614
3615 /* We need to put '@' in alt_notend_table to handle
3616 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3617 */
3618 alt_notend_table['@'] = 1;
3619
8d20a0a8
C		 3620 /* We need to put digits in alt_notend_table to handle
3621 bfextu %d0{24:1},%d0
3622 */
3623 alt_notend_table['0'] = 1;
3624 alt_notend_table['1'] = 1;
3625 alt_notend_table['2'] = 1;
3626 alt_notend_table['3'] = 1;
3627 alt_notend_table['4'] = 1;
3628 alt_notend_table['5'] = 1;
3629 alt_notend_table['6'] = 1;
3630 alt_notend_table['7'] = 1;
3631 alt_notend_table['8'] = 1;
3632 alt_notend_table['9'] = 1;
3633
3ad9ec6a 3634#ifndef MIT_SYNTAX_ONLY
355afbcd 3635 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 3636 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3637 {
3638 int n = 0;
3639 while (mote_pseudo_table[n].poc_name)
3640 {
3641 hack = (struct m68k_incant *)
3642 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3643 hash_insert (op_hash,
3644 mote_pseudo_table[n].poc_name, (char *) hack);
3645 hack->m_operands = 0;
3646 hack->m_opnum = n;
3647 n++;
3648 }
3649 }
3ad9ec6a
ILT		 3650#endif
3651
355afbcd 3652 init_regtable ();
a043f579
ILT		 3653
3654#ifdef OBJ_ELF
3655 record_alignment (text_section, 2);
3656 record_alignment (data_section, 2);
3657 record_alignment (bss_section, 2);
3658#endif
fecd2382
RP		 3659}
3660
b4d51f3d
ILT		 3661static void
3662select_control_regs ()
3663{
3664 /* Note which set of "movec" control registers is available. */
3665 switch (cpu_of_arch (current_architecture))
3666 {
3667 case m68000:
3668 control_regs = m68000_control_regs;
3669 break;
3670 case m68010:
3671 control_regs = m68010_control_regs;
3672 break;
3673 case m68020:
3674 case m68030:
3675 control_regs = m68020_control_regs;
3676 break;
3677 case m68040:
3678 control_regs = m68040_control_regs;
3679 break;
3680 case m68060:
3681 control_regs = m68060_control_regs;
3682 break;
3683 case cpu32:
3684 control_regs = cpu32_control_regs;
3685 break;
3686 case mcf5200:
3687 control_regs = mcf5200_control_regs;
3688 break;
3689 default:
3690 abort ();
3691 }
3692}
3693
82489ea0
KR		 3694void
3695m68k_init_after_args ()
3696{
3697 if (cpu_of_arch (current_architecture) == 0)
3698 {
064ba683 3699 int i;
b79de3a1 3700 const char *default_cpu = TARGET_CPU;
82489ea0 3701
b79de3a1
KR		 3702 if (*default_cpu == 'm')
3703 default_cpu++;
3704 for (i = 0; i < n_archs; i++)
e9bb39b4 3705 if (strcasecmp (default_cpu, archs[i].name) == 0)
b79de3a1
KR		 3706 break;
3707 if (i == n_archs)
3708 {
3709 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3710 current_architecture |= m68020;
3711 }
3712 else
3713 current_architecture |= archs[i].arch;
82489ea0 3714 }
b79de3a1
KR		 3715 /* Permit m68881 specification with all cpus; those that can't work
3716 with a coprocessor could be doing emulation. */
82489ea0
KR		 3717 if (current_architecture & m68851)
3718 {
3719 if (current_architecture & m68040)
3720 {
3721 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3722 }
3723 }
3724 /* What other incompatibilities could we check for? */
3725
3726 /* Toss in some default assumptions about coprocessors. */
3727 if (!no_68881
3728 && (cpu_of_arch (current_architecture)
3729 /* Can CPU32 have a 68881 coprocessor?? */
3730 & (m68020 | m68030 | cpu32)))
3731 {
3732 current_architecture |= m68881;
3733 }
3734 if (!no_68851
3735 && (cpu_of_arch (current_architecture) & m68020up) != 0
3736 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3737 {
3738 current_architecture |= m68851;
3739 }
3740 if (no_68881 && (current_architecture & m68881))
3741 as_bad ("options for 68881 and no-68881 both given");
3742 if (no_68851 && (current_architecture & m68851))
3743 as_bad ("options for 68851 and no-68851 both given");
3744
3745#ifdef OBJ_AOUT
3746 /* Work out the magic number. This isn't very general. */
3747 if (current_architecture & m68000)
3748 m68k_aout_machtype = 0;
3749 else if (current_architecture & m68010)
3750 m68k_aout_machtype = 1;
3751 else if (current_architecture & m68020)
3752 m68k_aout_machtype = 2;
3753 else
3754 m68k_aout_machtype = 2;
3755#endif
3756
3757 /* Note which set of "movec" control registers is available. */
b4d51f3d 3758 select_control_regs ();
04ef74bb
KR		 3759
3760 if (cpu_of_arch (current_architecture) < m68020)
3761 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
82489ea0 3762}
d703b5a7
ILT		 3763\f
3764/* This is called when a label is defined. */
3765
3766void
3767m68k_frob_label (sym)
3768 symbolS *sym;
3769{
3770 struct label_line *n;
3771
3772 n = (struct label_line *) xmalloc (sizeof *n);
3773 n->next = labels;
3774 n->label = sym;
3775 as_where (&n->file, &n->line);
ffecfc8b 3776 n->text = 0;
d703b5a7
ILT		 3777 labels = n;
3778 current_label = n;
3779}
3780
3781/* This is called when a value that is not an instruction is emitted. */
3782
3783void
3784m68k_flush_pending_output ()
3785{
3786 current_label = NULL;
3787}
3788
3789/* This is called at the end of the assembly, when the final value of
3790 the label is known. We warn if this is a text symbol aligned at an
3791 odd location. */
3792
3793void
3794m68k_frob_symbol (sym)
3795 symbolS *sym;
3796{
3797 if ((S_GET_VALUE (sym) & 1) != 0)
3798 {
3799 struct label_line *l;
82489ea0 3800
d703b5a7
ILT		 3801 for (l = labels; l != NULL; l = l->next)
3802 {
3803 if (l->label == sym)
3804 {
3805 if (l->text)
3806 as_warn_where (l->file, l->line,
3807 "text label `%s' aligned to odd boundary",
3808 S_GET_NAME (sym));
3809 break;
3810 }
3811 }
3812 }
3813}
3814\f
20710f1c
ILT		 3815/* This is called if we go in or out of MRI mode because of the .mri
3816 pseudo-op. */
3817
3818void
3819m68k_mri_mode_change (on)
3820 int on;
3821{
3822 if (on)
3823 {
3824 if (! flag_reg_prefix_optional)
3825 {
3826 flag_reg_prefix_optional = 1;
3827#ifdef REGISTER_PREFIX
3828 init_regtable ();
3829#endif
3830 }
3831 m68k_abspcadd = 1;
924160b0
ILT		 3832 if (! m68k_rel32_from_cmdline)
3833 m68k_rel32 = 0;
20710f1c
ILT		 3834 }
3835 else
3836 {
3837 if (! reg_prefix_optional_seen)
3838 {
3839#ifdef REGISTER_PREFIX_OPTIONAL
3840 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3841#else
3842 flag_reg_prefix_optional = 0;
3843#endif
3844#ifdef REGISTER_PREFIX
3845 init_regtable ();
3846#endif
3847 }
3848 m68k_abspcadd = 0;
924160b0
ILT		 3849 if (! m68k_rel32_from_cmdline)
3850 m68k_rel32 = 1;
20710f1c
ILT		 3851 }
3852}
3853
fecd2382
RP		 3854/* Equal to MAX_PRECISION in atof-ieee.c */
3855#define MAX_LITTLENUMS 6
3856
a1c7c0f3
ILT		 3857/* Turn a string in input_line_pointer into a floating point constant
3858 of type type, and store the appropriate bytes in *litP. The number
3859 of LITTLENUMS emitted is stored in *sizeP . An error message is
3860 returned, or NULL on OK. */
3861
fecd2382 3862char *
355afbcd
KR		 3863md_atof (type, litP, sizeP)
3864 char type;
3865 char *litP;
3866 int *sizeP;
fecd2382 3867{
355afbcd
KR		 3868 int prec;
3869 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3870 LITTLENUM_TYPE *wordP;
3871 char *t;
3872 char *atof_ieee ();
6d27d3a2 3873
355afbcd
KR		 3874 switch (type)
3875 {
3876 case 'f':
3877 case 'F':
3878 case 's':
3879 case 'S':
3880 prec = 2;
3881 break;
6d27d3a2 3882
355afbcd
KR		 3883 case 'd':
3884 case 'D':
3885 case 'r':
3886 case 'R':
3887 prec = 4;
3888 break;
6d27d3a2 3889
355afbcd
KR		 3890 case 'x':
3891 case 'X':
3892 prec = 6;
3893 break;
6d27d3a2 3894
355afbcd
KR		 3895 case 'p':
3896 case 'P':
3897 prec = 6;
3898 break;
6d27d3a2 3899
355afbcd
KR		 3900 default:
3901 *sizeP = 0;
3902 return "Bad call to MD_ATOF()";
3903 }
3904 t = atof_ieee (input_line_pointer, type, words);
3905 if (t)
3906 input_line_pointer = t;
3907
3908 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3909 for (wordP = words; prec--;)
3910 {
3911 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3912 litP += sizeof (LITTLENUM_TYPE);
3913 }
49864cfa 3914 return 0;
fecd2382
RP		 3915}
3916
fecd2382 3917void
355afbcd
KR		 3918md_number_to_chars (buf, val, n)
3919 char *buf;
025b0302 3920 valueT val;
355afbcd 3921 int n;
fecd2382 3922{
82489ea0 3923 number_to_chars_bigendian (buf, val, n);
fecd2382
RP		 3924}
3925
49864cfa
KR		 3926static void
3927md_apply_fix_2 (fixP, val)
355afbcd 3928 fixS *fixP;
9ad5755f 3929 offsetT val;
fecd2382 3930{
9ad5755f
KR		 3931 addressT upper_limit;
3932 offsetT lower_limit;
49864cfa 3933
9ad5755f
KR		 3934 /* This is unnecessary but it convinces the native rs6000 compiler
3935 to generate the code we want. */
355afbcd
KR		 3936 char *buf = fixP->fx_frag->fr_literal;
3937 buf += fixP->fx_where;
9ad5755f
KR		 3938 /* end ibm compiler workaround */
3939
3940 if (val & 0x80000000)
3941 val |= ~(addressT)0x7fffffff;
3942 else
3943 val &= 0x7fffffff;
6d27d3a2 3944
a043f579
ILT		 3945#ifdef OBJ_ELF
3946 if (fixP->fx_addsy)
3947 {
3948 memset (buf, 0, fixP->fx_size);
3949 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3950 return;
3951 }
3952#endif
3953
355afbcd
KR		 3954 switch (fixP->fx_size)
3955 {
b79de3a1
KR		 3956 /* The cast to offsetT below are necessary to make code correct for
3957 machines where ints are smaller than offsetT */
355afbcd
KR		 3958 case 1:
3959 *buf++ = val;
49864cfa 3960 upper_limit = 0x7f;
b79de3a1 3961 lower_limit = - (offsetT) 0x80;
355afbcd
KR		 3962 break;
3963 case 2:
3964 *buf++ = (val >> 8);
3965 *buf++ = val;
49864cfa 3966 upper_limit = 0x7fff;
b79de3a1 3967 lower_limit = - (offsetT) 0x8000;
355afbcd
KR		 3968 break;
3969 case 4:
3970 *buf++ = (val >> 24);
3971 *buf++ = (val >> 16);
3972 *buf++ = (val >> 8);
3973 *buf++ = val;
49864cfa 3974 upper_limit = 0x7fffffff;
b79de3a1 3975 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
355afbcd
KR		 3976 break;
3977 default:
3978 BAD_CASE (fixP->fx_size);
3979 }
49864cfa 3980
3b06beb7
ILT		 3981 /* Fix up a negative reloc. */
3982 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3983 {
3984 fixP->fx_addsy = fixP->fx_subsy;
3985 fixP->fx_subsy = NULL;
3986 fixP->fx_tcbit = 1;
3987 }
3988
49864cfa
KR		 3989 /* For non-pc-relative values, it's conceivable we might get something
3990 like "0xff" for a byte field. So extend the upper part of the range
3991 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3992 so that we can do any range checking at all. */
a78bc551 3993 if (! fixP->fx_pcrel && ! fixP->fx_signed)
49864cfa
KR		 3994 upper_limit = upper_limit * 2 + 1;
3995
9ad5755f
KR		 3996 if ((addressT) val > upper_limit
3997 && (val > 0 || val < lower_limit))
f3751617
ILT		 3998 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3999
4000 /* A one byte PC-relative reloc means a short branch. We can't use
4001 a short branch with a value of 0 or -1, because those indicate
4002 different opcodes (branches with longer offsets). */
4003 if (fixP->fx_pcrel
4004 && fixP->fx_size == 1
4005 && (fixP->fx_addsy == NULL
4006 || S_IS_DEFINED (fixP->fx_addsy))
4007 && (val == 0 || val == -1))
4008 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
fecd2382
RP		 4009}
4010
49864cfa
KR		 4011#ifdef BFD_ASSEMBLER
4012int
4013md_apply_fix (fixP, valp)
4014 fixS *fixP;
5f8cb05e 4015 valueT *valp;
49864cfa 4016{
9ad5755f 4017 md_apply_fix_2 (fixP, (addressT) *valp);
49864cfa
KR		 4018 return 1;
4019}
4020#else
4021void md_apply_fix (fixP, val)
4022 fixS *fixP;
4023 long val;
4024{
9ad5755f 4025 md_apply_fix_2 (fixP, (addressT) val);
49864cfa
KR		 4026}
4027#endif
fecd2382
RP		 4028
4029/* *fragP has been relaxed to its final size, and now needs to have
4030 the bytes inside it modified to conform to the new size There is UGLY
4031 MAGIC here. ..
a39116f1 4032 */
fecd2382 4033void
49864cfa 4034md_convert_frag_1 (fragP)
355afbcd 4035 register fragS *fragP;
fecd2382 4036{
355afbcd
KR		 4037 long disp;
4038 long ext = 0;
5f8cb05e 4039 fixS *fixP;
6d27d3a2 4040
355afbcd
KR		 4041 /* Address in object code of the displacement. */
4042 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 4043
9ad5755f
KR		 4044 /* Address in gas core of the place to store the displacement. */
4045 /* This convinces the native rs6000 compiler to generate the code we
4046 want. */
355afbcd
KR		 4047 register char *buffer_address = fragP->fr_literal;
4048 buffer_address += fragP->fr_fix;
9ad5755f 4049 /* end ibm compiler workaround */
6d27d3a2 4050
355afbcd
KR		 4051 /* The displacement of the address, from current location. */
4052 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4053 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 4054
5f8cb05e
ILT		 4055#ifdef BFD_ASSEMBLER
4056 disp += fragP->fr_symbol->sy_frag->fr_address;
4057#endif
4058
355afbcd
KR		 4059 switch (fragP->fr_subtype)
4060 {
4061 case TAB (BCC68000, BYTE):
4062 case TAB (ABRANCH, BYTE):
4063 know (issbyte (disp));
4064 if (disp == 0)
4065 as_bad ("short branch with zero offset: use :w");
4066 fragP->fr_opcode[1] = disp;
4067 ext = 0;
4068 break;
4069 case TAB (DBCC, SHORT):
4070 know (issword (disp));
4071 ext = 2;
4072 break;
4073 case TAB (BCC68000, SHORT):
4074 case TAB (ABRANCH, SHORT):
4075 know (issword (disp));
4076 fragP->fr_opcode[1] = 0x00;
4077 ext = 2;
4078 break;
4079 case TAB (ABRANCH, LONG):
ffecfc8b 4080 if (!HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4081 {
4082 if (fragP->fr_opcode[0] == 0x61)
04ef74bb 4083 /* BSR */
355afbcd
KR		 4084 {
4085 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4086 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd
KR		 4087
4088 fix_new (fragP,
4089 fragP->fr_fix,
4090 4,
4091 fragP->fr_symbol,
355afbcd
KR		 4092 fragP->fr_offset,
4093 0,
4094 NO_RELOC);
4095
4096 fragP->fr_fix += 4;
4097 ext = 0;
4098 }
04ef74bb 4099 /* BRA */
355afbcd
KR		 4100 else if (fragP->fr_opcode[0] == 0x60)
4101 {
4102 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4103 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
bcb8dff8
KR		 4104 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4105 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4106 fragP->fr_fix += 4;
4107 ext = 0;
4108 }
4109 else
4110 {
4111 as_bad ("Long branch offset not supported.");
4112 }
4113 }
4114 else
4115 {
bcb8dff8 4116 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4117 ext = 4;
4118 }
4119 break;
4120 case TAB (BCC68000, LONG):
4121 /* only Bcc 68000 instructions can come here */
4122 /* change bcc into b!cc/jmp absl long */
4123 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4124 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 4125
355afbcd 4126 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 4127 different frag, in which case refering to them is a no-no.
4128 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 4129 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4130 *buffer_address++ = (char) 0xf9;
355afbcd 4131 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8
KR		 4132 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4133 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4134 fragP->fr_fix += 4;
4135 ext = 0;
4136 break;
4137 case TAB (DBCC, LONG):
4138 /* only DBcc 68000 instructions can come here */
4139 /* change dbcc into dbcc/jmp absl long */
4140 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4141 *buffer_address++ = 0x00; /* branch offset = 4 */
4142 *buffer_address++ = 0x04;
4143 *buffer_address++ = 0x60; /* put in bra pc+6 */
4144 *buffer_address++ = 0x06;
4145 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4146 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 4147
4148 fragP->fr_fix += 6; /* account for bra/jmp instructions */
bcb8dff8 4149 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 4150 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4151 fragP->fr_fix += 4;
4152 ext = 0;
4153 break;
4154 case TAB (FBRANCH, SHORT):
4155 know ((fragP->fr_opcode[1] & 0x40) == 0);
4156 ext = 2;
4157 break;
4158 case TAB (FBRANCH, LONG):
4159 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4160 ext = 4;
4161 break;
4162 case TAB (PCREL, SHORT):
4163 ext = 2;
4164 break;
4165 case TAB (PCREL, LONG):
4166 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 4167 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 4168 /* JF FOO This code has not been tested */
bcb8dff8 4169 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 4170 0, NO_RELOC);
355afbcd 4171 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
bcb8dff8
KR		 4172 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4173 (unsigned) fragP->fr_opcode[0],
4174 (unsigned long) fragP->fr_address);
355afbcd
KR		 4175 fragP->fr_opcode[1] &= ~0x3F;
4176 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4177 fragP->fr_fix += 4;
355afbcd
KR		 4178 ext = 0;
4179 break;
4180 case TAB (PCLEA, SHORT):
49864cfa 4181 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 4182 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4183 fragP->fr_opcode[1] &= ~0x3F;
04ef74bb 4184 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
355afbcd
KR		 4185 ext = 2;
4186 break;
4187 case TAB (PCLEA, LONG):
5f8cb05e
ILT		 4188 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4189 fragP->fr_offset, 1, NO_RELOC);
4190 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4191 /* Already set to mode 7.3; this indicates: PC indirect with
4192 suppressed index, 32-bit displacement. */
355afbcd
KR		 4193 *buffer_address++ = 0x01;
4194 *buffer_address++ = 0x70;
4195 fragP->fr_fix += 2;
355afbcd
KR		 4196 ext = 4;
4197 break;
04ef74bb
KR		 4198
4199 case TAB (PCINDEX, BYTE):
4200 disp += 2;
4201 if (!issbyte (disp))
4202 {
4203 as_bad ("displacement doesn't fit in one byte");
4204 disp = 0;
4205 }
5f8cb05e
ILT		 4206 assert (fragP->fr_fix >= 2);
4207 buffer_address[-2] &= ~1;
4208 buffer_address[-1] = disp;
04ef74bb
KR		 4209 ext = 0;
4210 break;
4211 case TAB (PCINDEX, SHORT):
04ef74bb
KR		 4212 disp += 2;
4213 assert (issword (disp));
5f8cb05e
ILT		 4214 assert (fragP->fr_fix >= 2);
4215 buffer_address[-2] |= 0x1;
4216 buffer_address[-1] = 0x20;
4217 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4218 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4219 NO_RELOC);
4220 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4221 ext = 2;
4222 break;
4223 case TAB (PCINDEX, LONG):
04ef74bb 4224 disp += 2;
5f8cb05e
ILT		 4225 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4226 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4227 NO_RELOC);
4228 fixP->fx_pcrel_adjust = 2;
4229 assert (fragP->fr_fix >= 2);
4230 buffer_address[-2] |= 0x1;
4231 buffer_address[-1] = 0x30;
04ef74bb
KR		 4232 ext = 4;
4233 break;
49864cfa 4234 }
355afbcd
KR		 4235
4236 if (ext)
4237 {
4238 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4239 fragP->fr_fix += ext;
49864cfa
KR		 4240 }
4241}
355afbcd 4242
49864cfa
KR		 4243#ifndef BFD_ASSEMBLER
4244
4245void
064ba683 4246md_convert_frag (headers, sec, fragP)
49864cfa 4247 object_headers *headers;
064ba683 4248 segT sec;
49864cfa
KR		 4249 fragS *fragP;
4250{
4251 md_convert_frag_1 (fragP);
4252}
4253
4254#else
4255
4256void
4257md_convert_frag (abfd, sec, fragP)
4258 bfd *abfd;
5f8cb05e 4259 segT sec;
49864cfa
KR		 4260 fragS *fragP;
4261{
4262 md_convert_frag_1 (fragP);
4263}
4264#endif
355afbcd
KR		 4265
4266/* Force truly undefined symbols to their maximum size, and generally set up
4267 the frag list to be relaxed
4268 */
4269int
4270md_estimate_size_before_relax (fragP, segment)
4271 register fragS *fragP;
4272 segT segment;
4273{
4274 int old_fix;
4275 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4276
4277 old_fix = fragP->fr_fix;
4278
4279 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4280 switch (fragP->fr_subtype)
4281 {
4282
4283 case TAB (ABRANCH, SZ_UNDEF):
4284 {
4285 if ((fragP->fr_symbol != NULL) /* Not absolute */
4286 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4287 {
4288 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4289 break;
4290 }
ffecfc8b 4291 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4292 {
4293 /* On 68000, or for absolute value, switch to abs long */
4294 /* FIXME, we should check abs val, pick short or long */
4295 if (fragP->fr_opcode[0] == 0x61)
4296 {
4297 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4298 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd 4299 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4300 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4301 fragP->fr_fix += 4;
4302 frag_wane (fragP);
4303 }
4304 else if (fragP->fr_opcode[0] == 0x60)
4305 {
4306 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4307 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
355afbcd 4308 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4309 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4310 fragP->fr_fix += 4;
4311 frag_wane (fragP);
4312 }
4313 else
4314 {
4315 as_warn ("Long branch offset to extern symbol not supported.");
4316 }
4317 }
4318 else
4319 { /* Symbol is still undefined. Make it simple */
4320 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5f8cb05e 4321 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4322 fragP->fr_fix += 4;
bcb8dff8 4323 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4324 frag_wane (fragP);
4325 break;
4326 }
4327
a39116f1 4328 break;
355afbcd 4329 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 4330
355afbcd
KR		 4331 case TAB (FBRANCH, SZ_UNDEF):
4332 {
9ad5755f 4333 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
355afbcd
KR		 4334 {
4335 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4336 fragP->fr_var += 2;
4337 }
4338 else
4339 {
5f8cb05e
ILT		 4340 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4341 fragP->fr_offset, 1, NO_RELOC);
4342 fragP->fr_fix += 4;
4343 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4344 frag_wane (fragP);
355afbcd
KR		 4345 }
4346 break;
4347 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 4348
355afbcd
KR		 4349 case TAB (PCREL, SZ_UNDEF):
4350 {
b79de3a1
KR		 4351 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4352 || flag_short_refs
4353 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 4354 {
4355 fragP->fr_subtype = TAB (PCREL, SHORT);
4356 fragP->fr_var += 2;
4357 }
4358 else
4359 {
4360 fragP->fr_subtype = TAB (PCREL, LONG);
4361 fragP->fr_var += 4;
4362 }
4363 break;
4364 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 4365
355afbcd
KR		 4366 case TAB (BCC68000, SZ_UNDEF):
4367 {
4368 if ((fragP->fr_symbol != NULL)
4369 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4370 {
4371 fragP->fr_subtype = TAB (BCC68000, BYTE);
4372 break;
4373 }
4374 /* only Bcc 68000 instructions can come here */
4375 /* change bcc into b!cc/jmp absl long */
4376 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
9ad5755f 4377 if (flag_short_refs)
355afbcd
KR		 4378 {
4379 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4380 /* JF: these were fr_opcode[2,3] */
4381 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4382 buffer_address[1] = (char) 0xf8;
355afbcd 4383 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4384 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4385 fragP->fr_offset, 0, NO_RELOC);
4386 fragP->fr_fix += 2;
4387 }
4388 else
4389 {
4390 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4391 /* JF: these were fr_opcode[2,3] */
4392 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4393 buffer_address[1] = (char) 0xf9;
355afbcd 4394 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4395 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4396 fragP->fr_offset, 0, NO_RELOC);
4397 fragP->fr_fix += 4;
4398 }
4399 frag_wane (fragP);
4400 break;
4401 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 4402
355afbcd
KR		 4403 case TAB (DBCC, SZ_UNDEF):
4404 {
4405 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4406 {
4407 fragP->fr_subtype = TAB (DBCC, SHORT);
4408 fragP->fr_var += 2;
4409 break;
4410 }
4411 /* only DBcc 68000 instructions can come here */
4412 /* change dbcc into dbcc/jmp absl long */
4413 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4414 buffer_address[0] = 0x00; /* branch offset = 4 */
4415 buffer_address[1] = 0x04;
4416 buffer_address[2] = 0x60; /* put in bra pc + ... */
4417
9ad5755f 4418 if (flag_short_refs)
355afbcd
KR		 4419 {
4420 /* JF: these were fr_opcode[5-7] */
4421 buffer_address[3] = 0x04; /* plus 4 */
4422 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 4423 buffer_address[5] = (char) 0xf8;
355afbcd 4424 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4425 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4426 fragP->fr_offset, 0, NO_RELOC);
4427 fragP->fr_fix += 2;
4428 }
4429 else
4430 {
4431 /* JF: these were fr_opcode[5-7] */
4432 buffer_address[3] = 0x06; /* Plus 6 */
4433 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4434 buffer_address[5] = (char) 0xf9;
355afbcd 4435 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4436 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4437 fragP->fr_offset, 0, NO_RELOC);
4438 fragP->fr_fix += 4;
4439 }
6d27d3a2 4440
355afbcd
KR		 4441 frag_wane (fragP);
4442 break;
4443 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 4444
355afbcd
KR		 4445 case TAB (PCLEA, SZ_UNDEF):
4446 {
b79de3a1
KR		 4447 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4448 || flag_short_refs
4449 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 4450 {
4451 fragP->fr_subtype = TAB (PCLEA, SHORT);
4452 fragP->fr_var += 2;
4453 }
4454 else
4455 {
4456 fragP->fr_subtype = TAB (PCLEA, LONG);
4457 fragP->fr_var += 6;
4458 }
4459 break;
4460 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 4461
04ef74bb
KR		 4462 case TAB (PCINDEX, SZ_UNDEF):
4463 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4464 || cpu_of_arch (current_architecture) < m68020)
4465 {
4466 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4467 }
4468 else
4469 {
4470 fragP->fr_subtype = TAB (PCINDEX, LONG);
5f8cb05e 4471 fragP->fr_var += 4;
04ef74bb 4472 }
355afbcd 4473 break;
6d27d3a2 4474
04ef74bb
KR		 4475 default:
4476 break;
4477 }
6d27d3a2 4478
355afbcd
KR		 4479 /* now that SZ_UNDEF are taken care of, check others */
4480 switch (fragP->fr_subtype)
4481 {
4482 case TAB (BCC68000, BYTE):
4483 case TAB (ABRANCH, BYTE):
024e1779
ILT		 4484 /* We can't do a short jump to the next instruction, so in that
4485 case we force word mode. At this point S_GET_VALUE should
4486 return the offset of the symbol within its frag. If the
4487 symbol is at the start of a frag, and it is the next frag
4488 with any data in it (usually this is just the next frag, but
4489 assembler listings may introduce empty frags), we must use
4490 word mode. */
65feb78d 4491 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
355afbcd 4492 {
65feb78d
ILT		 4493 fragS *l;
4494
4495 for (l = fragP->fr_next;
4496 l != fragP->fr_symbol->sy_frag;
4497 l = l->fr_next)
4498 if (l->fr_fix + l->fr_var != 0)
4499 break;
4500 if (l == fragP->fr_symbol->sy_frag)
4501 {
4502 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4503 fragP->fr_var += 2;
4504 }
fecd2382 4505 }
355afbcd
KR		 4506 break;
4507 default:
4508 break;
4509 }
4510 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 4511}
4512
4513#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 4514/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 4515 with the byte-order problems of cross-assembly. So as a hack,
4516 I added this mach. dependent ri twiddler. Ugly, but it gets
4517 you there. -KWK */
4518/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 4519 are symbolnum, most sig. byte first. Last byte is broken up with
4520 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4521 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 4522/* Translate the internal relocation information into target-specific
4523 format. */
a79c6033 4524#ifdef comment
fecd2382 4525void
355afbcd
KR		 4526md_ri_to_chars (the_bytes, ri)
4527 char *the_bytes;
4528 struct reloc_info_generic *ri;
fecd2382 4529{
355afbcd
KR		 4530 /* this is easy */
4531 md_number_to_chars (the_bytes, ri->r_address, 4);
4532 /* now the fun stuff */
4533 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4534 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4535 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4536 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4537 ((ri->r_extern << 4) & 0x10));
fecd2382 4538}
355afbcd 4539
a79c6033
RP		 4540#endif /* comment */
4541
49864cfa 4542#ifndef BFD_ASSEMBLER
355afbcd
KR		 4543void
4544tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4545 char *where;
4546 fixS *fixP;
4547 relax_addressT segment_address_in_file;
a79c6033 4548{
355afbcd 4549 /*
1404ef23
KR		 4550 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4551 * Out: GNU LD relocation length code: 0, 1, or 2.
4552 */
6d27d3a2 4553
82489ea0 4554 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
355afbcd 4555 long r_symbolnum;
6d27d3a2 4556
355afbcd 4557 know (fixP->fx_addsy != NULL);
6d27d3a2 4558
355afbcd
KR		 4559 md_number_to_chars (where,
4560 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4561 4);
6d27d3a2 4562
355afbcd
KR		 4563 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4564 ? S_GET_TYPE (fixP->fx_addsy)
4565 : fixP->fx_addsy->sy_number);
6d27d3a2 4566
355afbcd
KR		 4567 where[4] = (r_symbolnum >> 16) & 0x0ff;
4568 where[5] = (r_symbolnum >> 8) & 0x0ff;
4569 where[6] = r_symbolnum & 0x0ff;
4570 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4571 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
49864cfa
KR		 4572}
4573#endif
a79c6033 4574
fecd2382
RP		 4575#endif /* OBJ_AOUT or OBJ_BOUT */
4576
4577#ifndef WORKING_DOT_WORD
49864cfa
KR		 4578CONST int md_short_jump_size = 4;
4579CONST int md_long_jump_size = 6;
fecd2382
RP		 4580
4581void
355afbcd
KR		 4582md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4583 char *ptr;
025b0302 4584 addressT from_addr, to_addr;
355afbcd
KR		 4585 fragS *frag;
4586 symbolS *to_symbol;
fecd2382 4587{
025b0302 4588 valueT offset;
6d27d3a2 4589
355afbcd 4590 offset = to_addr - (from_addr + 2);
6d27d3a2 4591
025b0302
ME		 4592 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4593 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 4594}
4595
4596void
355afbcd
KR		 4597md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4598 char *ptr;
025b0302 4599 addressT from_addr, to_addr;
355afbcd
KR		 4600 fragS *frag;
4601 symbolS *to_symbol;
fecd2382 4602{
025b0302 4603 valueT offset;
355afbcd 4604
ffecfc8b 4605 if (!HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4606 {
4607 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 4608 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4609 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 4610 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4611 0, NO_RELOC);
355afbcd
KR		 4612 }
4613 else
4614 {
4615 offset = to_addr - (from_addr + 2);
025b0302
ME		 4616 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4617 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 4618 }
fecd2382
RP		 4619}
4620
4621#endif
a1c7c0f3
ILT		 4622
4623/* Different values of OK tell what its OK to return. Things that
4624 aren't OK are an error (what a shock, no?)
6d27d3a2 4625
a39116f1
RP		 4626 0: Everything is OK
4627 10: Absolute 1:8 only
4628 20: Absolute 0:7 only
4629 30: absolute 0:15 only
4630 40: Absolute 0:31 only
4631 50: absolute 0:127 only
4632 55: absolute -64:63 only
4633 60: absolute -128:127 only
4634 70: absolute 0:4095 only
4635 80: No bignums
6d27d3a2 4636
a39116f1 4637 */
fecd2382 4638
355afbcd
KR		 4639static int
4640get_num (exp, ok)
4641 struct m68k_exp *exp;
4642 int ok;
fecd2382 4643{
a1c7c0f3 4644 if (exp->exp.X_op == O_absent)
49864cfa 4645 {
355afbcd 4646 /* Do the same thing the VAX asm does */
bcb8dff8 4647 op (exp) = O_constant;
355afbcd
KR		 4648 adds (exp) = 0;
4649 subs (exp) = 0;
4650 offs (exp) = 0;
4651 if (ok == 10)
4652 {
4653 as_warn ("expression out of range: defaulting to 1");
4654 offs (exp) = 1;
4655 }
49864cfa 4656 }
a1c7c0f3 4657 else if (exp->exp.X_op == O_constant)
49864cfa 4658 {
355afbcd
KR		 4659 switch (ok)
4660 {
4661 case 10:
4662 if (offs (exp) < 1 || offs (exp) > 8)
4663 {
4664 as_warn ("expression out of range: defaulting to 1");
4665 offs (exp) = 1;
4666 }
4667 break;
4668 case 20:
4669 if (offs (exp) < 0 || offs (exp) > 7)
4670 goto outrange;
4671 break;
4672 case 30:
4673 if (offs (exp) < 0 || offs (exp) > 15)
4674 goto outrange;
4675 break;
4676 case 40:
4677 if (offs (exp) < 0 || offs (exp) > 32)
4678 goto outrange;
4679 break;
4680 case 50:
4681 if (offs (exp) < 0 || offs (exp) > 127)
4682 goto outrange;
4683 break;
4684 case 55:
4685 if (offs (exp) < -64 || offs (exp) > 63)
4686 goto outrange;
4687 break;
4688 case 60:
4689 if (offs (exp) < -128 || offs (exp) > 127)
4690 goto outrange;
4691 break;
4692 case 70:
4693 if (offs (exp) < 0 || offs (exp) > 4095)
4694 {
4695 outrange:
4696 as_warn ("expression out of range: defaulting to 0");
4697 offs (exp) = 0;
4698 }
4699 break;
fecd2382 4700 default:
355afbcd
KR		 4701 break;
4702 }
49864cfa 4703 }
a1c7c0f3 4704 else if (exp->exp.X_op == O_big)
49864cfa 4705 {
bcb8dff8 4706 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 4707 && (ok == 80 /* no bignums */
4708 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 4709 /* If we have a flonum zero, a zero integer should
4710 do as well (e.g., in moveq). */
355afbcd
KR		 4711 && generic_floating_point_number.exponent == 0
4712 && generic_floating_point_number.low[0] == 0)))
4713 {
4714 /* HACK! Turn it into a long */
4715 LITTLENUM_TYPE words[6];
4716
4717 gen_to_words (words, 2, 8L); /* These numbers are magic! */
bcb8dff8 4718 op (exp) = O_constant;
355afbcd
KR		 4719 adds (exp) = 0;
4720 subs (exp) = 0;
4721 offs (exp) = words[1] | (words[0] << 16);
4722 }
4723 else if (ok != 0)
4724 {
bcb8dff8 4725 op (exp) = O_constant;
355afbcd
KR		 4726 adds (exp) = 0;
4727 subs (exp) = 0;
4728 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4729 as_warn ("Can't deal with expression; defaulting to %ld",
4730 offs (exp));
355afbcd 4731 }
49864cfa
KR		 4732 }
4733 else
4734 {
355afbcd
KR		 4735 if (ok >= 10 && ok <= 70)
4736 {
bcb8dff8 4737 op (exp) = O_constant;
355afbcd
KR		 4738 adds (exp) = 0;
4739 subs (exp) = 0;
4740 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4741 as_warn ("Can't deal with expression; defaulting to %ld",
4742 offs (exp));
355afbcd 4743 }
355afbcd 4744 }
49864cfa 4745
a1c7c0f3 4746 if (exp->size != SIZE_UNSPEC)
355afbcd 4747 {
a1c7c0f3 4748 switch (exp->size)
355afbcd 4749 {
a1c7c0f3
ILT		 4750 case SIZE_UNSPEC:
4751 case SIZE_LONG:
4752 break;
4753 case SIZE_BYTE:
355afbcd
KR		 4754 if (!isbyte (offs (exp)))
4755 as_warn ("expression doesn't fit in BYTE");
4756 break;
a1c7c0f3 4757 case SIZE_WORD:
355afbcd
KR		 4758 if (!isword (offs (exp)))
4759 as_warn ("expression doesn't fit in WORD");
4760 break;
a39116f1 4761 }
355afbcd 4762 }
a1c7c0f3 4763
355afbcd 4764 return offs (exp);
49864cfa 4765}
fecd2382
RP		 4766
4767/* These are the back-ends for the various machine dependent pseudo-ops. */
355afbcd 4768void demand_empty_rest_of_line (); /* Hate those extra verbose names */
fecd2382 4769
355afbcd 4770static void
bcb8dff8
KR		 4771s_data1 (ignore)
4772 int ignore;
355afbcd 4773{
bcb8dff8 4774 subseg_set (data_section, 1);
355afbcd 4775 demand_empty_rest_of_line ();
49864cfa 4776}
fecd2382 4777
355afbcd 4778static void
bcb8dff8
KR		 4779s_data2 (ignore)
4780 int ignore;
355afbcd 4781{
bcb8dff8 4782 subseg_set (data_section, 2);
355afbcd 4783 demand_empty_rest_of_line ();
49864cfa 4784}
fecd2382 4785
355afbcd 4786static void
bcb8dff8
KR		 4787s_bss (ignore)
4788 int ignore;
a1765cf0 4789{
355afbcd 4790 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 4791 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 4792
bcb8dff8 4793 subseg_set (bss_section, 0);
355afbcd 4794 demand_empty_rest_of_line ();
49864cfa 4795}
6d27d3a2 4796
355afbcd 4797static void
bcb8dff8
KR		 4798s_even (ignore)
4799 int ignore;
355afbcd
KR		 4800{
4801 register int temp;
4802 register long temp_fill;
4803
4804 temp = 1; /* JF should be 2? */
4805 temp_fill = get_absolute_expression ();
4806 if (!need_pass_2) /* Never make frag if expect extra pass. */
4807 frag_align (temp, (int) temp_fill);
4808 demand_empty_rest_of_line ();
79811f6f 4809 record_alignment (now_seg, temp);
49864cfa 4810}
355afbcd
KR		 4811
4812static void
bcb8dff8
KR		 4813s_proc (ignore)
4814 int ignore;
355afbcd
KR		 4815{
4816 demand_empty_rest_of_line ();
49864cfa 4817}
e9bb39b4
ILT		 4818\f
4819/* Pseudo-ops handled for MRI compatibility. */
4820
a986926b
ILT		 4821/* This function returns non-zero if the argument is a conditional
4822 pseudo-op. This is called when checking whether a pending
4823 alignment is needed. */
4824
4825int
4826m68k_conditional_pseudoop (pop)
4827 pseudo_typeS *pop;
4828{
4829 return (pop->poc_handler == s_mri_if
4830 || pop->poc_handler == s_mri_else);
4831}
4832
e9bb39b4 4833/* Handle an MRI style chip specification. */
fecd2382 4834
e9bb39b4
ILT		 4835static void
4836mri_chip ()
4837{
4838 char *s;
4839 char c;
4840 int i;
4841
4842 s = input_line_pointer;
4843 c = get_symbol_end ();
4844 for (i = 0; i < n_archs; i++)
4845 if (strcasecmp (s, archs[i].name) == 0)
4846 break;
4847 if (i >= n_archs)
4848 {
4849 as_bad ("%s: unrecognized processor name", s);
4850 *input_line_pointer = c;
4851 ignore_rest_of_line ();
4852 return;
4853 }
4854 *input_line_pointer = c;
fecd2382 4855
e9bb39b4
ILT		 4856 if (*input_line_pointer == '/')
4857 current_architecture = 0;
4858 else
4859 current_architecture &= m68881 | m68851;
4860 current_architecture |= archs[i].arch;
4861
4862 while (*input_line_pointer == '/')
4863 {
4864 ++input_line_pointer;
4865 s = input_line_pointer;
4866 c = get_symbol_end ();
4867 if (strcmp (s, "68881") == 0)
4868 current_architecture |= m68881;
4869 else if (strcmp (s, "68851") == 0)
4870 current_architecture |= m68851;
4871 *input_line_pointer = c;
4872 }
b4d51f3d
ILT		 4873
4874 /* Update info about available control registers. */
4875 select_control_regs ();
e9bb39b4
ILT		 4876}
4877
4878/* The MRI CHIP pseudo-op. */
4879
4880static void
4881s_chip (ignore)
4882 int ignore;
4883{
f9680a05
ILT		 4884 char *stop = NULL;
4885 char stopc;
4886
4887 if (flag_mri)
4888 stop = mri_comment_field (&stopc);
e9bb39b4 4889 mri_chip ();
f9680a05
ILT		 4890 if (flag_mri)
4891 mri_comment_end (stop, stopc);
e9bb39b4
ILT		 4892 demand_empty_rest_of_line ();
4893}
27a53b88
ILT		 4894
4895/* The MRI FOPT pseudo-op. */
4896
4897static void
4898s_fopt (ignore)
4899 int ignore;
4900{
4901 SKIP_WHITESPACE ();
4902
4903 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4904 {
4905 int temp;
4906
4907 input_line_pointer += 3;
4908 temp = get_absolute_expression ();
4909 if (temp < 0 || temp > 7)
4910 as_bad ("bad coprocessor id");
4911 else
4912 m68k_float_copnum = COP0 + temp;
4913 }
4914 else
4915 {
4916 as_bad ("unrecognized fopt option");
4917 ignore_rest_of_line ();
4918 return;
4919 }
4920
4921 demand_empty_rest_of_line ();
4922}
6700d36e
ILT		 4923
4924/* The structure used to handle the MRI OPT pseudo-op. */
4925
4926struct opt_action
4927{
4928 /* The name of the option. */
4929 const char *name;
4930
4931 /* If this is not NULL, just call this function. The first argument
4932 is the ARG field of this structure, the second argument is
4933 whether the option was negated. */
4934 void (*pfn) PARAMS ((int arg, int on));
4935
4936 /* If this is not NULL, and the PFN field is NULL, set the variable
4937 this points to. Set it to the ARG field if the option was not
4938 negated, and the NOTARG field otherwise. */
4939 int *pvar;
4940
4941 /* The value to pass to PFN or to assign to *PVAR. */
4942 int arg;
4943
4944 /* The value to assign to *PVAR if the option is negated. If PFN is
4945 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4946 the option may not be negated. */
4947 int notarg;
4948};
4949
4950/* The table used to handle the MRI OPT pseudo-op. */
4951
4952static void skip_to_comma PARAMS ((int, int));
7e047ac2 4953static void opt_nest PARAMS ((int, int));
6700d36e
ILT		 4954static void opt_chip PARAMS ((int, int));
4955static void opt_list PARAMS ((int, int));
4956static void opt_list_symbols PARAMS ((int, int));
4957
4958static const struct opt_action opt_table[] =
4959{
4960 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4961
4962 /* We do relaxing, so there is little use for these options. */
4963 { "b", 0, 0, 0, 0 },
4964 { "brs", 0, 0, 0, 0 },
4965 { "brb", 0, 0, 0, 0 },
4966 { "brl", 0, 0, 0, 0 },
4967 { "brw", 0, 0, 0, 0 },
4968
4969 { "c", 0, 0, 0, 0 },
4970 { "cex", 0, 0, 0, 0 },
4971 { "case", 0, &symbols_case_sensitive, 1, 0 },
4972 { "cl", 0, 0, 0, 0 },
4973 { "cre", 0, 0, 0, 0 },
4974 { "d", 0, &flag_keep_locals, 1, 0 },
4975 { "e", 0, 0, 0, 0 },
4976 { "f", 0, &flag_short_refs, 1, 0 },
4977 { "frs", 0, &flag_short_refs, 1, 0 },
4978 { "frl", 0, &flag_short_refs, 0, 1 },
4979 { "g", 0, 0, 0, 0 },
4980 { "i", 0, 0, 0, 0 },
4981 { "m", 0, 0, 0, 0 },
4982 { "mex", 0, 0, 0, 0 },
4983 { "mc", 0, 0, 0, 0 },
4984 { "md", 0, 0, 0, 0 },
7e047ac2 4985 { "nest", opt_nest, 0, 0, 0 },
6700d36e
ILT		 4986 { "next", skip_to_comma, 0, 0, 0 },
4987 { "o", 0, 0, 0, 0 },
4988 { "old", 0, 0, 0, 0 },
4989 { "op", skip_to_comma, 0, 0, 0 },
4990 { "pco", 0, 0, 0, 0 },
4991 { "p", opt_chip, 0, 0, 0 },
4992 { "pcr", 0, 0, 0, 0 },
4993 { "pcs", 0, 0, 0, 0 },
4994 { "r", 0, 0, 0, 0 },
4995 { "quick", 0, &m68k_quick, 1, 0 },
4996 { "rel32", 0, &m68k_rel32, 1, 0 },
4997 { "s", opt_list, 0, 0, 0 },
4998 { "t", opt_list_symbols, 0, 0, 0 },
4999 { "w", 0, &flag_no_warnings, 0, 1 },
5000 { "x", 0, 0, 0, 0 }
5001};
5002
5003#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5004
5005/* The MRI OPT pseudo-op. */
5006
5007static void
5008s_opt (ignore)
5009 int ignore;
5010{
5011 do
5012 {
5013 int t;
5014 char *s;
5015 char c;
5016 int i;
5017 const struct opt_action *o;
5018
5019 SKIP_WHITESPACE ();
5020
5021 t = 1;
5022 if (*input_line_pointer == '-')
5023 {
5024 ++input_line_pointer;
5025 t = 0;
5026 }
5027 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5028 {
5029 input_line_pointer += 2;
5030 t = 0;
5031 }
5032
5033 s = input_line_pointer;
5034 c = get_symbol_end ();
5035
5036 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5037 {
5038 if (strcasecmp (s, o->name) == 0)
5039 {
5040 if (o->pfn)
5041 {
5042 /* Restore input_line_pointer now in case the option
5043 takes arguments. */
5044 *input_line_pointer = c;
5045 (*o->pfn) (o->arg, t);
5046 }
5047 else if (o->pvar != NULL)
5048 {
5049 if (! t && o->arg == o->notarg)
5050 as_bad ("option `%s' may not be negated", s);
5051 *input_line_pointer = c;
5052 *o->pvar = t ? o->arg : o->notarg;
5053 }
9bef2324
ILT		 5054 else
5055 *input_line_pointer = c;
6700d36e
ILT		 5056 break;
5057 }
5058 }
5059 if (i >= OPTCOUNT)
5060 {
5061 as_bad ("option `%s' not recognized", s);
5062 *input_line_pointer = c;
5063 }
5064 }
5065 while (*input_line_pointer++ == ',');
5066
5067 /* Move back to terminating character. */
5068 --input_line_pointer;
5069 demand_empty_rest_of_line ();
5070}
5071
5072/* Skip ahead to a comma. This is used for OPT options which we do
5073 not suppor tand which take arguments. */
5074
5075static void
5076skip_to_comma (arg, on)
5077 int arg;
5078 int on;
5079{
5080 while (*input_line_pointer != ','
5081 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5082 ++input_line_pointer;
5083}
5084
7e047ac2
ILT		 5085/* Handle the OPT NEST=depth option. */
5086
5087static void
5088opt_nest (arg, on)
5089 int arg;
5090 int on;
5091{
5092 if (*input_line_pointer != '=')
5093 {
5094 as_bad ("bad format of OPT NEST=depth");
5095 return;
5096 }
5097
5098 ++input_line_pointer;
5099 max_macro_nest = get_absolute_expression ();
5100}
5101
6700d36e
ILT		 5102/* Handle the OPT P=chip option. */
5103
5104static void
5105opt_chip (arg, on)
5106 int arg;
5107 int on;
5108{
5109 if (*input_line_pointer != '=')
5110 {
5111 /* This is just OPT P, which we do not support. */
5112 return;
5113 }
5114
5115 ++input_line_pointer;
5116 mri_chip ();
5117}
5118
5119/* Handle the OPT S option. */
5120
5121static void
5122opt_list (arg, on)
5123 int arg;
5124 int on;
5125{
5126 listing_list (on);
5127}
5128
5129/* Handle the OPT T option. */
5130
5131static void
5132opt_list_symbols (arg, on)
5133 int arg;
5134 int on;
5135{
5136 if (on)
5137 listing |= LISTING_SYMBOLS;
5138 else
5139 listing &=~ LISTING_SYMBOLS;
5140}
5141
5142/* Handle the MRI REG pseudo-op. */
5143
5144static void
5145s_reg (ignore)
5146 int ignore;
5147{
5148 char *s;
5149 int c;
8e11ad0a 5150 struct m68k_op rop;
6700d36e 5151 unsigned long mask;
f9680a05
ILT		 5152 char *stop = NULL;
5153 char stopc;
6700d36e 5154
7e047ac2 5155 if (line_label == NULL)
6700d36e
ILT		 5156 {
5157 as_bad ("missing label");
5158 ignore_rest_of_line ();
5159 return;
5160 }
5161
f9680a05
ILT		 5162 if (flag_mri)
5163 stop = mri_comment_field (&stopc);
5164
6700d36e
ILT		 5165 SKIP_WHITESPACE ();
5166
5167 s = input_line_pointer;
5168 while (isalnum ((unsigned char) *input_line_pointer)
5169#ifdef REGISTER_PREFIX
5170 || *input_line_pointer == REGISTER_PREFIX
5171#endif
5172 || *input_line_pointer == '/'
5173 || *input_line_pointer == '-')
5174 ++input_line_pointer;
5175 c = *input_line_pointer;
5176 *input_line_pointer = '\0';
5177
8e11ad0a 5178 if (m68k_ip_op (s, &rop) != 0)
6700d36e 5179 {
8e11ad0a 5180 if (rop.error == NULL)
6700d36e
ILT		 5181 as_bad ("bad register list");
5182 else
8e11ad0a 5183 as_bad ("bad register list: %s", rop.error);
6700d36e
ILT		 5184 *input_line_pointer = c;
5185 ignore_rest_of_line ();
5186 return;
5187 }
5188
5189 *input_line_pointer = c;
5190
8e11ad0a
ILT		 5191 if (rop.mode == REGLST)
5192 mask = rop.mask;
5193 else if (rop.mode == DREG)
5194 mask = 1 << (rop.reg - DATA0);
5195 else if (rop.mode == AREG)
5196 mask = 1 << (rop.reg - ADDR0 + 8);
5197 else if (rop.mode == FPREG)
5198 mask = 1 << (rop.reg - FP0 + 16);
5199 else if (rop.mode == CONTROL
5200 && rop.reg == FPI)
6700d36e 5201 mask = 1 << 24;
8e11ad0a
ILT		 5202 else if (rop.mode == CONTROL
5203 && rop.reg == FPS)
6700d36e 5204 mask = 1 << 25;
8e11ad0a
ILT		 5205 else if (rop.mode == CONTROL
5206 && rop.reg == FPC)
6700d36e
ILT		 5207 mask = 1 << 26;
5208 else
5209 {
5210 as_bad ("bad register list");
5211 ignore_rest_of_line ();
5212 return;
5213 }
5214
7e047ac2
ILT		 5215 S_SET_SEGMENT (line_label, absolute_section);
5216 S_SET_VALUE (line_label, mask);
5217 line_label->sy_frag = &zero_address_frag;
6700d36e 5218
85f34122 5219 if (flag_mri)
f9680a05 5220 mri_comment_end (stop, stopc);
85f34122 5221
6700d36e
ILT		 5222 demand_empty_rest_of_line ();
5223}
e14994d9
ILT		 5224
5225/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5226
5227struct save_opts
5228{
5229 struct save_opts *next;
5230 int abspcadd;
5231 int symbols_case_sensitive;
5232 int keep_locals;
5233 int short_refs;
5234 int architecture;
5235 int quick;
5236 int rel32;
5237 int listing;
5238 int no_warnings;
5239 /* FIXME: We don't save OPT S. */
5240};
5241
5242/* This variable holds the stack of saved options. */
5243
5244static struct save_opts *save_stack;
5245
5246/* The MRI SAVE pseudo-op. */
5247
5248static void
5249s_save (ignore)
5250 int ignore;
5251{
5252 struct save_opts *s;
5253
5254 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5255 s->abspcadd = m68k_abspcadd;
5256 s->symbols_case_sensitive = symbols_case_sensitive;
5257 s->keep_locals = flag_keep_locals;
5258 s->short_refs = flag_short_refs;
5259 s->architecture = current_architecture;
5260 s->quick = m68k_quick;
5261 s->rel32 = m68k_rel32;
5262 s->listing = listing;
5263 s->no_warnings = flag_no_warnings;
5264
5265 s->next = save_stack;
5266 save_stack = s;
5267
5268 demand_empty_rest_of_line ();
5269}
5270
5271/* The MRI RESTORE pseudo-op. */
5272
5273static void
5274s_restore (ignore)
5275 int ignore;
5276{
5277 struct save_opts *s;
5278
5279 if (save_stack == NULL)
5280 {
5281 as_bad ("restore without save");
5282 ignore_rest_of_line ();
5283 return;
5284 }
5285
5286 s = save_stack;
5287 save_stack = s->next;
5288
5289 m68k_abspcadd = s->abspcadd;
5290 symbols_case_sensitive = s->symbols_case_sensitive;
5291 flag_keep_locals = s->keep_locals;
5292 flag_short_refs = s->short_refs;
5293 current_architecture = s->architecture;
5294 m68k_quick = s->quick;
5295 m68k_rel32 = s->rel32;
5296 listing = s->listing;
5297 flag_no_warnings = s->no_warnings;
5298
5299 free (s);
5300
5301 demand_empty_rest_of_line ();
5302}
b4ec75e0
ILT		 5303
5304/* Types of MRI structured control directives. */
5305
5306enum mri_control_type
5307{
5308 mri_for,
5309 mri_if,
5310 mri_repeat,
5311 mri_while
5312};
5313
5314/* This structure is used to stack the MRI structured control
5315 directives. */
5316
5317struct mri_control_info
5318{
5319 /* The directive within which this one is enclosed. */
5320 struct mri_control_info *outer;
5321
5322 /* The type of directive. */
5323 enum mri_control_type type;
5324
5325 /* Whether an ELSE has been in an IF. */
5326 int else_seen;
5327
5328 /* The add or sub statement at the end of a FOR. */
5329 char *incr;
5330
5331 /* The label of the top of a FOR or REPEAT loop. */
5332 char *top;
5333
5334 /* The label to jump to for the next iteration, or the else
5335 expression of a conditional. */
5336 char *next;
5337
5338 /* The label to jump to to break out of the loop, or the label past
5339 the end of a conditional. */
5340 char *bottom;
5341};
5342
5343/* The stack of MRI structured control directives. */
5344
5345static struct mri_control_info *mri_control_stack;
5346
5347/* The current MRI structured control directive index number, used to
5348 generate label names. */
5349
5350static int mri_control_index;
5351
5352/* Some function prototypes. */
5353
5354static char *mri_control_label PARAMS ((void));
5355static struct mri_control_info *push_mri_control
5356 PARAMS ((enum mri_control_type));
5357static void pop_mri_control PARAMS ((void));
5358static int parse_mri_condition PARAMS ((int *));
5359static int parse_mri_control_operand
e1c0287d 5360 PARAMS ((int *, char **, char **, char **, char **));
b4ec75e0
ILT		 5361static int swap_mri_condition PARAMS ((int));
5362static int reverse_mri_condition PARAMS ((int));
5363static void build_mri_control_operand
e1c0287d
ILT		 5364 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5365 const char *, int));
b4ec75e0
ILT		 5366static void parse_mri_control_expression
5367 PARAMS ((char *, int, const char *, const char *, int));
5368
5369/* Generate a new MRI label structured control directive label name. */
5370
5371static char *
5372mri_control_label ()
5373{
5374 char *n;
5375
5376 n = (char *) xmalloc (20);
5377 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5378 ++mri_control_index;
5379 return n;
5380}
5381
5382/* Create a new MRI structured control directive. */
5383
5384static struct mri_control_info *
5385push_mri_control (type)
5386 enum mri_control_type type;
5387{
5388 struct mri_control_info *n;
5389
5390 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5391
5392 n->type = type;
5393 n->else_seen = 0;
5394 if (type == mri_if || type == mri_while)
5395 n->top = NULL;
5396 else
5397 n->top = mri_control_label ();
5398 n->next = mri_control_label ();
5399 n->bottom = mri_control_label ();
5400
5401 n->outer = mri_control_stack;
5402 mri_control_stack = n;
5403
5404 return n;
5405}
5406
5407/* Pop off the stack of MRI structured control directives. */
5408
5409static void
5410pop_mri_control ()
5411{
5412 struct mri_control_info *n;
5413
5414 n = mri_control_stack;
5415 mri_control_stack = n->outer;
5416 if (n->top != NULL)
5417 free (n->top);
5418 free (n->next);
5419 free (n->bottom);
5420 free (n);
5421}
5422
5423/* Recognize a condition code in an MRI structured control expression. */
5424
5425static int
5426parse_mri_condition (pcc)
5427 int *pcc;
5428{
5429 char c1, c2;
5430
5431 know (*input_line_pointer == '<');
5432
5433 ++input_line_pointer;
5434 c1 = *input_line_pointer++;
5435 c2 = *input_line_pointer++;
5436
5437 if (*input_line_pointer != '>')
5438 {
5439 as_bad ("syntax error in structured control directive");
5440 return 0;
5441 }
5442
5443 ++input_line_pointer;
5444 SKIP_WHITESPACE ();
5445
5446 if (isupper (c1))
5447 c1 = tolower (c1);
5448 if (isupper (c2))
5449 c2 = tolower (c2);
5450
5451 *pcc = (c1 << 8) | c2;
5452
5453 return 1;
5454}
5455
5456/* Parse a single operand in an MRI structured control expression. */
5457
5458static int
5459parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5460 int *pcc;
b3625fe6 5461 char **leftstart;
e1c0287d 5462 char **leftstop;
b3625fe6 5463 char **rightstart;
e1c0287d 5464 char **rightstop;
b4ec75e0
ILT		 5465{
5466 char *s;
5467
5468 SKIP_WHITESPACE ();
5469
5470 *pcc = -1;
5471 *leftstart = NULL;
5472 *leftstop = NULL;
5473 *rightstart = NULL;
5474 *rightstop = NULL;
5475
5476 if (*input_line_pointer == '<')
5477 {
5478 /* It's just a condition code. */
5479 return parse_mri_condition (pcc);
5480 }
5481
5482 /* Look ahead for the condition code. */
5483 for (s = input_line_pointer; *s != '\0'; ++s)
5484 {
5485 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5486 break;
5487 }
5488 if (*s == '\0')
5489 {
5490 as_bad ("missing condition code in structured control directive");
5491 return 0;
5492 }
5493
5494 *leftstart = input_line_pointer;
5495 *leftstop = s;
4026c122
ILT		 5496 if (*leftstop > *leftstart
5497 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5498 --*leftstop;
b4ec75e0
ILT		 5499
5500 input_line_pointer = s;
5501 if (! parse_mri_condition (pcc))
5502 return 0;
5503
5504 /* Look ahead for AND or OR or end of line. */
5505 for (s = input_line_pointer; *s != '\0'; ++s)
5506 {
5507 if ((strncasecmp (s, "AND", 3) == 0
5508 && (s[3] == '.' || ! is_part_of_name (s[3])))
5509 || (strncasecmp (s, "OR", 2) == 0
5510 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5511 break;
5512 }
5513
5514 *rightstart = input_line_pointer;
5515 *rightstop = s;
4026c122
ILT		 5516 if (*rightstop > *rightstart
5517 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5518 --*rightstop;
b4ec75e0
ILT		 5519
5520 input_line_pointer = s;
5521
5522 return 1;
5523}
5524
5525#define MCC(b1, b2) (((b1) << 8) | (b2))
5526
5527/* Swap the sense of a condition. This changes the condition so that
5528 it generates the same result when the operands are swapped. */
5529
5530static int
5531swap_mri_condition (cc)
5532 int cc;
5533{
5534 switch (cc)
5535 {
5536 case MCC ('h', 'i'): return MCC ('c', 's');
5537 case MCC ('l', 's'): return MCC ('c', 'c');
5538 case MCC ('c', 'c'): return MCC ('l', 's');
5539 case MCC ('c', 's'): return MCC ('h', 'i');
5540 case MCC ('p', 'l'): return MCC ('m', 'i');
5541 case MCC ('m', 'i'): return MCC ('p', 'l');
5542 case MCC ('g', 'e'): return MCC ('l', 'e');
5543 case MCC ('l', 't'): return MCC ('g', 't');
5544 case MCC ('g', 't'): return MCC ('l', 't');
5545 case MCC ('l', 'e'): return MCC ('g', 'e');
5546 }
5547 return cc;
5548}
5549
5550/* Reverse the sense of a condition. */
5551
5552static int
5553reverse_mri_condition (cc)
5554 int cc;
5555{
5556 switch (cc)
5557 {
5558 case MCC ('h', 'i'): return MCC ('l', 's');
5559 case MCC ('l', 's'): return MCC ('h', 'i');
5560 case MCC ('c', 'c'): return MCC ('c', 's');
5561 case MCC ('c', 's'): return MCC ('c', 'c');
5562 case MCC ('n', 'e'): return MCC ('e', 'q');
5563 case MCC ('e', 'q'): return MCC ('n', 'e');
5564 case MCC ('v', 'c'): return MCC ('v', 's');
5565 case MCC ('v', 's'): return MCC ('v', 'c');
5566 case MCC ('p', 'l'): return MCC ('m', 'i');
5567 case MCC ('m', 'i'): return MCC ('p', 'l');
5568 case MCC ('g', 'e'): return MCC ('l', 't');
5569 case MCC ('l', 't'): return MCC ('g', 'e');
5570 case MCC ('g', 't'): return MCC ('l', 'e');
5571 case MCC ('l', 'e'): return MCC ('g', 't');
5572 }
5573 return cc;
5574}
5575
5576/* Build an MRI structured control expression. This generates test
5577 and branch instructions. It goes to TRUELAB if the condition is
5578 true, and to FALSELAB if the condition is false. Exactly one of
5579 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5580 is the size qualifier for the expression. EXTENT is the size to
5581 use for the branch. */
5582
5583static void
5584build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5585 rightstop, truelab, falselab, extent)
5586 int qual;
5587 int cc;
b3625fe6 5588 char *leftstart;
e1c0287d 5589 char *leftstop;
b3625fe6 5590 char *rightstart;
e1c0287d 5591 char *rightstop;
b4ec75e0
ILT		 5592 const char *truelab;
5593 const char *falselab;
5594 int extent;
5595{
5596 char *buf;
5597 char *s;
5598
e1c0287d 5599 if (leftstart != NULL)
b3625fe6 5600 {
e1c0287d
ILT		 5601 struct m68k_op leftop, rightop;
5602 char c;
b3625fe6 5603
e1c0287d
ILT		 5604 /* Swap the compare operands, if necessary, to produce a legal
5605 m68k compare instruction. Comparing a register operand with
5606 a non-register operand requires the register to be on the
5607 right (cmp, cmpa). Comparing an immediate value with
5608 anything requires the immediate value to be on the left
5609 (cmpi). */
5610
5611 c = *leftstop;
5612 *leftstop = '\0';
5613 (void) m68k_ip_op (leftstart, &leftop);
5614 *leftstop = c;
5615
5616 c = *rightstop;
5617 *rightstop = '\0';
5618 (void) m68k_ip_op (rightstart, &rightop);
5619 *rightstop = c;
5620
5621 if (rightop.mode == IMMED
5622 || ((leftop.mode == DREG || leftop.mode == AREG)
5623 && (rightop.mode != DREG && rightop.mode != AREG)))
5624 {
5625 char *temp;
5626
5627 cc = swap_mri_condition (cc);
5628 temp = leftstart;
5629 leftstart = rightstart;
5630 rightstart = temp;
5631 temp = leftstop;
5632 leftstop = rightstop;
5633 rightstop = temp;
5634 }
b4ec75e0
ILT		 5635 }
5636
5637 if (truelab == NULL)
5638 {
5639 cc = reverse_mri_condition (cc);
5640 truelab = falselab;
5641 }
5642
5643 if (leftstart != NULL)
5644 {
5645 buf = (char *) xmalloc (20
5646 + (leftstop - leftstart)
5647 + (rightstop - rightstart));
5648 s = buf;
5649 *s++ = 'c';
5650 *s++ = 'm';
5651 *s++ = 'p';
5652 if (qual != '\0')
5653 *s++ = qual;
5654 *s++ = ' ';
5655 memcpy (s, leftstart, leftstop - leftstart);
5656 s += leftstop - leftstart;
5657 *s++ = ',';
5658 memcpy (s, rightstart, rightstop - rightstart);
5659 s += rightstop - rightstart;
5660 *s = '\0';
5661 md_assemble (buf);
5662 free (buf);
5663 }
5664
5665 buf = (char *) xmalloc (20 + strlen (truelab));
5666 s = buf;
5667 *s++ = 'b';
5668 *s++ = cc >> 8;
5669 *s++ = cc & 0xff;
5670 if (extent != '\0')
5671 *s++ = extent;
5672 *s++ = ' ';
5673 strcpy (s, truelab);
5674 md_assemble (buf);
5675 free (buf);
5676}
5677
5678/* Parse an MRI structured control expression. This generates test
5679 and branch instructions. STOP is where the expression ends. It
5680 goes to TRUELAB if the condition is true, and to FALSELAB if the
5681 condition is false. Exactly one of TRUELAB and FALSELAB will be
5682 NULL, meaning to fall through. QUAL is the size qualifier for the
5683 expression. EXTENT is the size to use for the branch. */
5684
5685static void
5686parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5687 char *stop;
5688 int qual;
5689 const char *truelab;
5690 const char *falselab;
5691 int extent;
5692{
5693 int c;
5694 int cc;
b3625fe6 5695 char *leftstart;
e1c0287d 5696 char *leftstop;
b3625fe6 5697 char *rightstart;
e1c0287d 5698 char *rightstop;
b4ec75e0
ILT		 5699
5700 c = *stop;
5701 *stop = '\0';
5702
5703 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5704 &rightstart, &rightstop))
5705 {
5706 *stop = c;
5707 return;
5708 }
5709
5710 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5711 {
5712 const char *flab;
5713
5714 if (falselab != NULL)
5715 flab = falselab;
5716 else
5717 flab = mri_control_label ();
5718
5719 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5720 rightstop, (const char *) NULL, flab, extent);
5721
5722 input_line_pointer += 3;
5723 if (*input_line_pointer != '.'
5724 || input_line_pointer[1] == '\0')
5725 qual = '\0';
5726 else
5727 {
5728 qual = input_line_pointer[1];
5729 input_line_pointer += 2;
5730 }
5731
5732 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5733 &rightstart, &rightstop))
5734 {
5735 *stop = c;
5736 return;
5737 }
5738
5739 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5740 rightstop, truelab, falselab, extent);
5741
5742 if (falselab == NULL)
5743 colon (flab);
5744 }
5745 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5746 {
5747 const char *tlab;
5748
5749 if (truelab != NULL)
5750 tlab = truelab;
5751 else
5752 tlab = mri_control_label ();
5753
5754 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5755 rightstop, tlab, (const char *) NULL, extent);
5756
5757 input_line_pointer += 2;
5758 if (*input_line_pointer != '.'
5759 || input_line_pointer[1] == '\0')
5760 qual = '\0';
5761 else
5762 {
5763 qual = input_line_pointer[1];
5764 input_line_pointer += 2;
5765 }
5766
5767 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5768 &rightstart, &rightstop))
5769 {
5770 *stop = c;
5771 return;
5772 }
5773
5774 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5775 rightstop, truelab, falselab, extent);
5776
5777 if (truelab == NULL)
5778 colon (tlab);
5779 }
5780 else
5781 {
5782 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5783 rightstop, truelab, falselab, extent);
5784 }
5785
5786 *stop = c;
5787 if (input_line_pointer != stop)
5788 as_bad ("syntax error in structured control directive");
5789}
5790
5791/* Handle the MRI IF pseudo-op. This may be a structured control
5792 directive, or it may be a regular assembler conditional, depending
5793 on its operands. */
5794
5795static void
5796s_mri_if (qual)
5797 int qual;
5798{
5799 char *s;
5800 int c;
5801 struct mri_control_info *n;
5802
5803 /* A structured control directive must end with THEN with an
5804 optional qualifier. */
5805 s = input_line_pointer;
e1c0287d
ILT		 5806 while (! is_end_of_line[(unsigned char) *s]
5807 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 5808 ++s;
5809 --s;
5810 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5811 --s;
5812
5813 if (s - input_line_pointer > 1
5814 && s[-1] == '.')
5815 s -= 2;
5816
5817 if (s - input_line_pointer < 3
5818 || strncasecmp (s - 3, "THEN", 4) != 0)
5819 {
5820 if (qual != '\0')
5821 {
5822 as_bad ("missing then");
5823 ignore_rest_of_line ();
5824 return;
5825 }
5826
5827 /* It's a conditional. */
5828 s_if (O_ne);
5829 return;
5830 }
5831
5832 /* Since this might be a conditional if, this pseudo-op will be
5833 called even if we are supported to be ignoring input. Double
5834 check now. Clobber *input_line_pointer so that ignore_input
5835 thinks that this is not a special pseudo-op. */
5836 c = *input_line_pointer;
5837 *input_line_pointer = 0;
5838 if (ignore_input ())
5839 {
5840 *input_line_pointer = c;
5841 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5842 ++input_line_pointer;
5843 demand_empty_rest_of_line ();
5844 return;
5845 }
5846 *input_line_pointer = c;
5847
5848 n = push_mri_control (mri_if);
5849
5850 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5851 n->next, s[1] == '.' ? s[2] : '\0');
5852
5853 if (s[1] == '.')
5854 input_line_pointer = s + 3;
5855 else
5856 input_line_pointer = s + 1;
5857
e1c0287d
ILT		 5858 if (flag_mri)
5859 {
5860 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5861 ++input_line_pointer;
5862 }
5863
b4ec75e0
ILT		 5864 demand_empty_rest_of_line ();
5865}
5866
5867/* Handle the MRI else pseudo-op. If we are currently doing an MRI
5868 structured IF, associate the ELSE with the IF. Otherwise, assume
5869 it is a conditional else. */
5870
5871static void
5872s_mri_else (qual)
5873 int qual;
5874{
5875 int c;
5876 char *buf;
5877 char q[2];
5878
5879 if (qual == '\0'
5880 && (mri_control_stack == NULL
5881 || mri_control_stack->type != mri_if
5882 || mri_control_stack->else_seen))
5883 {
5884 s_else (0);
5885 return;
5886 }
5887
5888 c = *input_line_pointer;
5889 *input_line_pointer = 0;
5890 if (ignore_input ())
5891 {
5892 *input_line_pointer = c;
5893 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5894 ++input_line_pointer;
5895 demand_empty_rest_of_line ();
5896 return;
5897 }
5898 *input_line_pointer = c;
5899
5900 if (mri_control_stack == NULL
5901 || mri_control_stack->type != mri_if
5902 || mri_control_stack->else_seen)
5903 {
5904 as_bad ("else without matching if");
5905 ignore_rest_of_line ();
5906 return;
5907 }
5908
5909 mri_control_stack->else_seen = 1;
5910
5911 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5912 q[0] = qual;
5913 q[1] = '\0';
5914 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5915 md_assemble (buf);
5916 free (buf);
5917
5918 colon (mri_control_stack->next);
5919
e1c0287d
ILT		 5920 if (flag_mri)
5921 {
5922 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5923 ++input_line_pointer;
5924 }
5925
b4ec75e0
ILT		 5926 demand_empty_rest_of_line ();
5927}
5928
5929/* Handle the MRI ENDI pseudo-op. */
5930
5931static void
5932s_mri_endi (ignore)
5933 int ignore;
5934{
5935 if (mri_control_stack == NULL
5936 || mri_control_stack->type != mri_if)
5937 {
5938 as_bad ("endi without matching if");
5939 ignore_rest_of_line ();
5940 return;
5941 }
5942
5943 /* ignore_input will not return true for ENDI, so we don't need to
5944 worry about checking it again here. */
5945
5946 if (! mri_control_stack->else_seen)
5947 colon (mri_control_stack->next);
5948 colon (mri_control_stack->bottom);
5949
5950 pop_mri_control ();
5951
e1c0287d
ILT		 5952 if (flag_mri)
5953 {
5954 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5955 ++input_line_pointer;
5956 }
5957
b4ec75e0
ILT		 5958 demand_empty_rest_of_line ();
5959}
5960
5961/* Handle the MRI BREAK pseudo-op. */
5962
5963static void
5964s_mri_break (extent)
5965 int extent;
5966{
5967 struct mri_control_info *n;
5968 char *buf;
5969 char ex[2];
5970
5971 n = mri_control_stack;
5972 while (n != NULL
5973 && n->type != mri_for
5974 && n->type != mri_repeat
5975 && n->type != mri_while)
5976 n = n->outer;
5977 if (n == NULL)
5978 {
5979 as_bad ("break outside of structured loop");
5980 ignore_rest_of_line ();
5981 return;
5982 }
5983
5984 buf = (char *) xmalloc (20 + strlen (n->bottom));
5985 ex[0] = extent;
5986 ex[1] = '\0';
5987 sprintf (buf, "bra%s %s", ex, n->bottom);
5988 md_assemble (buf);
5989 free (buf);
5990
e1c0287d
ILT		 5991 if (flag_mri)
5992 {
5993 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5994 ++input_line_pointer;
5995 }
5996
b4ec75e0
ILT		 5997 demand_empty_rest_of_line ();
5998}
5999
6000/* Handle the MRI NEXT pseudo-op. */
6001
6002static void
6003s_mri_next (extent)
6004 int extent;
6005{
6006 struct mri_control_info *n;
6007 char *buf;
6008 char ex[2];
6009
6010 n = mri_control_stack;
6011 while (n != NULL
6012 && n->type != mri_for
6013 && n->type != mri_repeat
6014 && n->type != mri_while)
6015 n = n->outer;
6016 if (n == NULL)
6017 {
6018 as_bad ("next outside of structured loop");
6019 ignore_rest_of_line ();
6020 return;
6021 }
6022
6023 buf = (char *) xmalloc (20 + strlen (n->next));
6024 ex[0] = extent;
6025 ex[1] = '\0';
6026 sprintf (buf, "bra%s %s", ex, n->next);
6027 md_assemble (buf);
6028 free (buf);
6029
e1c0287d
ILT		 6030 if (flag_mri)
6031 {
6032 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6033 ++input_line_pointer;
6034 }
6035
b4ec75e0
ILT		 6036 demand_empty_rest_of_line ();
6037}
6038
6039/* Handle the MRI FOR pseudo-op. */
6040
6041static void
6042s_mri_for (qual)
6043 int qual;
6044{
6045 const char *varstart, *varstop;
6046 const char *initstart, *initstop;
6047 const char *endstart, *endstop;
6048 const char *bystart, *bystop;
6049 int up;
6050 int by;
6051 int extent;
6052 struct mri_control_info *n;
6053 char *buf;
6054 char *s;
6055 char ex[2];
6056
6057 /* The syntax is
6058 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6059 */
6060
4026c122 6061 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6062 varstart = input_line_pointer;
6063
6064 /* Look for the '='. */
6065 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6066 && *input_line_pointer != '=')
6067 ++input_line_pointer;
6068 if (*input_line_pointer != '=')
6069 {
6070 as_bad ("missing =");
6071 ignore_rest_of_line ();
6072 return;
6073 }
6074
6075 varstop = input_line_pointer;
4026c122
ILT		 6076 if (varstop > varstart
6077 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6078 --varstop;
b4ec75e0
ILT		 6079
6080 ++input_line_pointer;
6081
6082 initstart = input_line_pointer;
6083
6084 /* Look for TO or DOWNTO. */
6085 up = 1;
6086 initstop = NULL;
6087 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6088 {
6089 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6090 && ! is_part_of_name (input_line_pointer[2]))
6091 {
6092 initstop = input_line_pointer;
6093 input_line_pointer += 2;
6094 break;
6095 }
6096 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6097 && ! is_part_of_name (input_line_pointer[6]))
6098 {
6099 initstop = input_line_pointer;
6100 up = 0;
6101 input_line_pointer += 6;
6102 break;
6103 }
6104 ++input_line_pointer;
6105 }
6106 if (initstop == NULL)
6107 {
6108 as_bad ("missing to or downto");
6109 ignore_rest_of_line ();
6110 return;
6111 }
4026c122
ILT		 6112 if (initstop > initstart
6113 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6114 --initstop;
b4ec75e0 6115
4026c122 6116 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6117 endstart = input_line_pointer;
6118
6119 /* Look for BY or DO. */
6120 by = 0;
6121 endstop = NULL;
6122 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6123 {
6124 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6125 && ! is_part_of_name (input_line_pointer[2]))
6126 {
6127 endstop = input_line_pointer;
6128 by = 1;
6129 input_line_pointer += 2;
6130 break;
6131 }
6132 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6133 && (input_line_pointer[2] == '.'
6134 || ! is_part_of_name (input_line_pointer[2])))
6135 {
6136 endstop = input_line_pointer;
6137 input_line_pointer += 2;
6138 break;
6139 }
6140 ++input_line_pointer;
6141 }
6142 if (endstop == NULL)
6143 {
6144 as_bad ("missing do");
6145 ignore_rest_of_line ();
6146 return;
6147 }
4026c122
ILT		 6148 if (endstop > endstart
6149 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6150 --endstop;
b4ec75e0
ILT		 6151
6152 if (! by)
6153 {
6154 bystart = "#1";
6155 bystop = bystart + 2;
6156 }
6157 else
6158 {
4026c122 6159 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6160 bystart = input_line_pointer;
6161
6162 /* Look for DO. */
6163 bystop = NULL;
6164 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6165 {
6166 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6167 && (input_line_pointer[2] == '.'
6168 || ! is_part_of_name (input_line_pointer[2])))
6169 {
6170 bystop = input_line_pointer;
6171 input_line_pointer += 2;
6172 break;
6173 }
6174 ++input_line_pointer;
6175 }
6176 if (bystop == NULL)
6177 {
6178 as_bad ("missing do");
6179 ignore_rest_of_line ();
6180 return;
6181 }
4026c122
ILT		 6182 if (bystop > bystart
6183 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6184 --bystop;
b4ec75e0
ILT		 6185 }
6186
6187 if (*input_line_pointer != '.')
6188 extent = '\0';
6189 else
6190 {
6191 extent = input_line_pointer[1];
6192 input_line_pointer += 2;
6193 }
6194
6195 /* We have fully parsed the FOR operands. Now build the loop. */
6196
6197 n = push_mri_control (mri_for);
6198
6199 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6200
6201 /* move init,var */
6202 s = buf;
6203 *s++ = 'm';
6204 *s++ = 'o';
6205 *s++ = 'v';
6206 *s++ = 'e';
6207 if (qual != '\0')
6208 *s++ = qual;
6209 *s++ = ' ';
6210 memcpy (s, initstart, initstop - initstart);
6211 s += initstop - initstart;
6212 *s++ = ',';
6213 memcpy (s, varstart, varstop - varstart);
6214 s += varstop - varstart;
6215 *s = '\0';
6216 md_assemble (buf);
6217
6218 colon (n->top);
6219
6220 /* cmp end,var */
6221 s = buf;
6222 *s++ = 'c';
6223 *s++ = 'm';
6224 *s++ = 'p';
6225 if (qual != '\0')
6226 *s++ = qual;
6227 *s++ = ' ';
6228 memcpy (s, endstart, endstop - endstart);
6229 s += endstop - endstart;
6230 *s++ = ',';
6231 memcpy (s, varstart, varstop - varstart);
6232 s += varstop - varstart;
6233 *s = '\0';
6234 md_assemble (buf);
6235
6236 /* bcc bottom */
6237 ex[0] = extent;
6238 ex[1] = '\0';
6239 if (up)
6240 sprintf (buf, "blt%s %s", ex, n->bottom);
6241 else
6242 sprintf (buf, "bgt%s %s", ex, n->bottom);
6243 md_assemble (buf);
6244
6245 /* Put together the add or sub instruction used by ENDF. */
6246 s = buf;
6247 if (up)
6248 strcpy (s, "add");
6249 else
6250 strcpy (s, "sub");
6251 s += 3;
6252 if (qual != '\0')
6253 *s++ = qual;
6254 *s++ = ' ';
6255 memcpy (s, bystart, bystop - bystart);
6256 s += bystop - bystart;
6257 *s++ = ',';
6258 memcpy (s, varstart, varstop - varstart);
6259 s += varstop - varstart;
6260 *s = '\0';
6261 n->incr = buf;
6262
e1c0287d
ILT		 6263 if (flag_mri)
6264 {
6265 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6266 ++input_line_pointer;
6267 }
6268
b4ec75e0
ILT		 6269 demand_empty_rest_of_line ();
6270}
6271
6272/* Handle the MRI ENDF pseudo-op. */
6273
6274static void
6275s_mri_endf (ignore)
6276 int ignore;
6277{
6278 if (mri_control_stack == NULL
6279 || mri_control_stack->type != mri_for)
6280 {
6281 as_bad ("endf without for");
6282 ignore_rest_of_line ();
6283 return;
6284 }
6285
6286 colon (mri_control_stack->next);
6287
6288 md_assemble (mri_control_stack->incr);
6289
6290 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6291 md_assemble (mri_control_stack->incr);
6292
6293 free (mri_control_stack->incr);
6294
6295 colon (mri_control_stack->bottom);
6296
6297 pop_mri_control ();
6298
e1c0287d
ILT		 6299 if (flag_mri)
6300 {
6301 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6302 ++input_line_pointer;
6303 }
6304
b4ec75e0
ILT		 6305 demand_empty_rest_of_line ();
6306}
6307
6308/* Handle the MRI REPEAT pseudo-op. */
6309
6310static void
6311s_mri_repeat (ignore)
6312 int ignore;
6313{
6314 struct mri_control_info *n;
6315
6316 n = push_mri_control (mri_repeat);
6317 colon (n->top);
e1c0287d
ILT		 6318 if (flag_mri)
6319 {
6320 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6321 ++input_line_pointer;
6322 }
b4ec75e0
ILT		 6323 demand_empty_rest_of_line ();
6324}
6325
6326/* Handle the MRI UNTIL pseudo-op. */
6327
6328static void
6329s_mri_until (qual)
6330 int qual;
6331{
6332 char *s;
6333
6334 if (mri_control_stack == NULL
6335 || mri_control_stack->type != mri_repeat)
6336 {
6337 as_bad ("until without repeat");
6338 ignore_rest_of_line ();
6339 return;
6340 }
6341
6342 colon (mri_control_stack->next);
6343
6344 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6345 ;
6346
6347 parse_mri_control_expression (s, qual, (const char *) NULL,
6348 mri_control_stack->top, '\0');
6349
6350 colon (mri_control_stack->bottom);
6351
6352 input_line_pointer = s;
6353
9e64486e
ILT		 6354 pop_mri_control ();
6355
e1c0287d
ILT		 6356 if (flag_mri)
6357 {
6358 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6359 ++input_line_pointer;
6360 }
6361
b4ec75e0
ILT		 6362 demand_empty_rest_of_line ();
6363}
6364
6365/* Handle the MRI WHILE pseudo-op. */
6366
6367static void
6368s_mri_while (qual)
6369 int qual;
6370{
6371 char *s;
6372
6373 struct mri_control_info *n;
6374
6375 s = input_line_pointer;
e1c0287d
ILT		 6376 while (! is_end_of_line[(unsigned char) *s]
6377 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 6378 s++;
6379 --s;
6380 while (*s == ' ' || *s == '\t')
6381 --s;
6382 if (s - input_line_pointer > 1
6383 && s[-1] == '.')
6384 s -= 2;
6385 if (s - input_line_pointer < 2
6386 || strncasecmp (s - 1, "DO", 2) != 0)
6387 {
6388 as_bad ("missing do");
6389 ignore_rest_of_line ();
6390 return;
6391 }
6392
6393 n = push_mri_control (mri_while);
6394
6395 colon (n->next);
6396
6397 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6398 s[1] == '.' ? s[2] : '\0');
6399
6400 input_line_pointer = s + 1;
6401 if (*input_line_pointer == '.')
6402 input_line_pointer += 2;
6403
e1c0287d
ILT		 6404 if (flag_mri)
6405 {
6406 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6407 ++input_line_pointer;
6408 }
6409
b4ec75e0
ILT		 6410 demand_empty_rest_of_line ();
6411}
6412
6413/* Handle the MRI ENDW pseudo-op. */
6414
6415static void
6416s_mri_endw (ignore)
6417 int ignore;
6418{
6419 char *buf;
6420
6421 if (mri_control_stack == NULL
6422 || mri_control_stack->type != mri_while)
6423 {
6424 as_bad ("endw without while");
6425 ignore_rest_of_line ();
6426 return;
6427 }
6428
6429 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6430 sprintf (buf, "bra %s", mri_control_stack->next);
6431 md_assemble (buf);
6432 free (buf);
6433
6434 colon (mri_control_stack->bottom);
6435
6436 pop_mri_control ();
6437
e1c0287d
ILT		 6438 if (flag_mri)
6439 {
6440 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6441 ++input_line_pointer;
6442 }
6443
b4ec75e0
ILT		 6444 demand_empty_rest_of_line ();
6445}
f3d817d8 6446\f
7c15cbe8
RP		 6447/*
6448 * md_parse_option
6449 * Invocation line includes a switch not recognized by the base assembler.
6450 * See if it's a processor-specific option. These are:
6451 *
6452 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6453 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6454 * Select the architecture. Instructions or features not
6455 * supported by the selected architecture cause fatal
6456 * errors. More than one may be specified. The default is
6457 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6458 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 6459 * -[A]m[c]no-68851, -[A]m[c]no-68881
6460 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6461 * so don't use or document it, but that's the way the parsing
6462 * works).
7c15cbe8 6463 *
dff60b7d
ILT		 6464 * -pic Indicates PIC.
6465 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 6466 *
8d20a0a8
C		 6467 * --bitwise-or
6468 * Permit `|' to be used in expressions.
6469 *
7c15cbe8
RP		 6470 */
6471
5f8cb05e
ILT		 6472#ifdef OBJ_ELF
6473CONST char *md_shortopts = "lSA:m:kQ:V";
6474#else
f3d817d8 6475CONST char *md_shortopts = "lSA:m:k";
5f8cb05e
ILT		 6476#endif
6477
f3d817d8
DM		 6478struct option md_longopts[] = {
6479#define OPTION_PIC (OPTION_MD_BASE)
6480 {"pic", no_argument, NULL, OPTION_PIC},
6481#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6482 {"register-prefix-optional", no_argument, NULL,
6483 OPTION_REGISTER_PREFIX_OPTIONAL},
8d20a0a8
C		 6484#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6485 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
b4d51f3d
ILT		 6486#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6487 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6488#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6489 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
924160b0
ILT		 6490#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6491 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6492#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6493 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
f3d817d8
DM		 6494 {NULL, no_argument, NULL, 0}
6495};
6496size_t md_longopts_size = sizeof(md_longopts);
82489ea0 6497
355afbcd 6498int
f3d817d8
DM		 6499md_parse_option (c, arg)
6500 int c;
6501 char *arg;
fecd2382 6502{
f3d817d8 6503 switch (c)
355afbcd
KR		 6504 {
6505 case 'l': /* -l means keep external to 2 bit offset
e284846a 6506 rather than 16 bit one */
9ad5755f 6507 flag_short_refs = 1;
355afbcd 6508 break;
6d27d3a2 6509
e284846a
KR		 6510 case 'S': /* -S means that jbsr's always turn into
6511 jsr's. */
9ad5755f 6512 flag_long_jumps = 1;
355afbcd 6513 break;
6d27d3a2 6514
355afbcd 6515 case 'A':
f3d817d8
DM		 6516 if (*arg == 'm')
6517 arg++;
355afbcd
KR		 6518 /* intentional fall-through */
6519 case 'm':
355afbcd 6520
b79de3a1 6521 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
e284846a 6522 {
064ba683
ILT		 6523 int i;
6524 unsigned long arch;
b79de3a1
KR		 6525 const char *oarg = arg;
6526
6527 arg += 3;
6528 if (*arg == 'm')
6529 {
6530 arg++;
6531 if (arg[0] == 'c' && arg[1] == '6')
6532 arg++;
6533 }
6534 for (i = 0; i < n_archs; i++)
6535 if (!strcmp (arg, archs[i].name))
6536 break;
6537 if (i == n_archs)
6538 {
6539 unknown:
6540 as_bad ("unrecognized option `%s'", oarg);
6541 return 0;
6542 }
6543 arch = archs[i].arch;
6544 if (arch == m68881)
6545 no_68881 = 1;
6546 else if (arch == m68851)
6547 no_68851 = 1;
6548 else
6549 goto unknown;
355afbcd
KR		 6550 }
6551 else
6552 {
b79de3a1
KR		 6553 int i;
6554
6555 if (arg[0] == 'c' && arg[1] == '6')
6556 arg++;
6557
6558 for (i = 0; i < n_archs; i++)
6559 if (!strcmp (arg, archs[i].name))
6560 {
6561 unsigned long arch = archs[i].arch;
6562 if (cpu_of_arch (arch))
6563 /* It's a cpu spec. */
6564 {
6565 current_architecture &= ~m68000up;
6566 current_architecture |= arch;
6567 }
6568 else if (arch == m68881)
6569 {
6570 current_architecture |= m68881;
6571 no_68881 = 0;
6572 }
6573 else if (arch == m68851)
6574 {
6575 current_architecture |= m68851;
6576 no_68851 = 0;
6577 }
6578 else
6579 /* ??? */
6580 abort ();
6581 break;
6582 }
6583 if (i == n_archs)
6584 {
6585 as_bad ("unrecognized architecture specification `%s'", arg);
6586 return 0;
6587 }
f8701a3f 6588 }
f3d817d8 6589 break;
dff60b7d 6590
f3d817d8 6591 case OPTION_PIC:
dff60b7d
ILT		 6592 case 'k':
6593 flag_want_pic = 1;
f3d817d8
DM		 6594 break; /* -pic, Position Independent Code */
6595
6596 case OPTION_REGISTER_PREFIX_OPTIONAL:
6597 flag_reg_prefix_optional = 1;
20710f1c 6598 reg_prefix_optional_seen = 1;
dff60b7d 6599 break;
355afbcd 6600
a043f579 6601 /* -V: SVR4 argument to print version ID. */
5f8cb05e 6602 case 'V':
a043f579
ILT		 6603 print_version_id ();
6604 break;
6605
6606 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6607 should be emitted or not. FIXME: Not implemented. */
6608 case 'Q':
5f8cb05e
ILT		 6609 break;
6610
8d20a0a8
C		 6611 case OPTION_BITWISE_OR:
6612 {
6613 char *n, *t;
6614 const char *s;
6615
6616 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6617 t = n;
6618 for (s = m68k_comment_chars; *s != '\0'; s++)
6619 if (*s != '|')
6620 *t++ = *s;
6621 *t = '\0';
6622 m68k_comment_chars = n;
6623 }
6624 break;
6625
b4d51f3d
ILT		 6626 case OPTION_BASE_SIZE_DEFAULT_16:
6627 m68k_index_width_default = SIZE_WORD;
6628 break;
6629
6630 case OPTION_BASE_SIZE_DEFAULT_32:
6631 m68k_index_width_default = SIZE_LONG;
6632 break;
6633
924160b0
ILT		 6634 case OPTION_DISP_SIZE_DEFAULT_16:
6635 m68k_rel32 = 0;
6636 m68k_rel32_from_cmdline = 1;
6637 break;
6638
6639 case OPTION_DISP_SIZE_DEFAULT_32:
6640 m68k_rel32 = 1;
6641 m68k_rel32_from_cmdline = 1;
6642 break;
6643
355afbcd
KR		 6644 default:
6645 return 0;
6646 }
f3d817d8 6647
355afbcd 6648 return 1;
fecd2382
RP		 6649}
6650
f3d817d8
DM		 6651void
6652md_show_usage (stream)
6653 FILE *stream;
6654{
6655 fprintf(stream, "\
6656680X0 options:\n\
6657-l use 1 word for refs to undefined symbols [default 2]\n\
5f8cb05e
ILT		 6658-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6659 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
7f003b7f 6660 | -mcpu32 | -m5200\n\
f3d817d8
DM		 6661 specify variant of 680X0 architecture [default 68020]\n\
6662-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6663 target has/lacks floating-point coprocessor\n\
92a25e12
ILT		 6664 [default yes for 68020, 68030, and cpu32]\n");
6665 fprintf(stream, "\
f3d817d8
DM		 6666-m68851 | -mno-68851\n\
6667 target has/lacks memory-management unit coprocessor\n\
6668 [default yes for 68020 and up]\n\
6669-pic, -k generate position independent code\n\
6670-S turn jbsr into jsr\n\
6671--register-prefix-optional\n\
8d20a0a8
C		 6672 recognize register names without prefix character\n\
6673--bitwise-or do not treat `|' as a comment character\n");
b4d51f3d
ILT		 6674 fprintf (stream, "\
6675--base-size-default-16 base reg without size is 16 bits\n\
924160b0
ILT		 6676--base-size-default-32 base reg without size is 32 bits (default)\n\
6677--disp-size-default-16 displacement with unknown size is 16 bits\n\
6678--disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
f3d817d8
DM		 6679}
6680\f
fecd2382
RP		 6681#ifdef TEST2
6682
6683/* TEST2: Test md_assemble() */
6684/* Warning, this routine probably doesn't work anymore */
6685
355afbcd 6686main ()
fecd2382 6687{
355afbcd
KR		 6688 struct m68k_it the_ins;
6689 char buf[120];
6690 char *cp;
6691 int n;
6692
6693 m68k_ip_begin ();
6694 for (;;)
6695 {
6696 if (!gets (buf) || !*buf)
6697 break;
6698 if (buf[0] == '|' || buf[1] == '.')
6699 continue;
6700 for (cp = buf; *cp; cp++)
6701 if (*cp == '\t')
6702 *cp = ' ';
6703 if (is_label (buf))
6704 continue;
6705 memset (&the_ins, '\0', sizeof (the_ins));
6706 m68k_ip (&the_ins, buf);
6707 if (the_ins.error)
6708 {
6709 printf ("Error %s in %s\n", the_ins.error, buf);
6710 }
6711 else
6712 {
6713 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6714 for (n = 0; n < the_ins.numo; n++)
6715 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6716 printf (" ");
6717 print_the_insn (&the_ins.opcode[0], stdout);
6718 (void) putchar ('\n');
6719 }
6720 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6721 {
6722 if (the_ins.operands[n].error)
6723 {
6724 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6725 continue;
6726 }
6727 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6728 if (the_ins.operands[n].b_const)
6729 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6730 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6731 if (the_ins.operands[n].b_iadd)
6732 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6733 (void) putchar ('\n');
a39116f1 6734 }
355afbcd
KR		 6735 }
6736 m68k_ip_end ();
6737 return 0;
fecd2382
RP		 6738}
6739
355afbcd
KR		 6740is_label (str)
6741 char *str;
fecd2382 6742{
355afbcd
KR		 6743 while (*str == ' ')
6744 str++;
6745 while (*str && *str != ' ')
6746 str++;
6747 if (str[-1] == ':' || str[1] == '=')
6748 return 1;
6749 return 0;
fecd2382
RP		 6750}
6751
6752#endif
6753
6754/* Possible states for relaxation:
6d27d3a2 6755
a39116f1
RP		 6756 0 0 branch offset byte (bra, etc)
6757 0 1 word
6758 0 2 long
6d27d3a2 6759
a39116f1
RP		 6760 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6761 1 1 word
6762 1 2 long
6d27d3a2 6763
a39116f1
RP		 6764 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6765 2 1 word-long
6766 2 2 long-word
6767 2 3 long-long
6d27d3a2 6768
a39116f1 6769 */
fecd2382 6770
fecd2382
RP		 6771/* We have no need to default values of symbols. */
6772
6773/* ARGSUSED */
6774symbolS *
355afbcd
KR		 6775md_undefined_symbol (name)
6776 char *name;
fecd2382 6777{
355afbcd 6778 return 0;
fecd2382
RP		 6779}
6780
fecd2382 6781/* Round up a section size to the appropriate boundary. */
025b0302 6782valueT
355afbcd
KR		 6783md_section_align (segment, size)
6784 segT segment;
025b0302 6785 valueT size;
fecd2382 6786{
355afbcd 6787 return size; /* Byte alignment is fine */
fecd2382
RP		 6788}
6789
6790/* Exactly what point is a PC-relative offset relative TO?
5f8cb05e
ILT		 6791 On the 68k, it is relative to the address of the first extension
6792 word. The difference between the addresses of the offset and the
6793 first extension word is stored in fx_pcrel_adjust. */
fecd2382 6794long
355afbcd
KR		 6795md_pcrel_from (fixP)
6796 fixS *fixP;
fecd2382 6797{
b4ec75e0
ILT		 6798 int adjust;
6799
6800 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6801 -1 as 64. */
6802 adjust = fixP->fx_pcrel_adjust;
6803 if (adjust == 64)
6804 adjust = -1;
6805 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
fecd2382
RP		 6806}
6807
49864cfa 6808#ifndef BFD_ASSEMBLER
9ad5755f 6809/*ARGSUSED*/
355afbcd 6810void
9ad5755f
KR		 6811tc_coff_symbol_emit_hook (ignore)
6812 symbolS *ignore;
3ad9ec6a
ILT		 6813{
6814}
6815
355afbcd
KR		 6816int
6817tc_coff_sizemachdep (frag)
6818 fragS *frag;
3ad9ec6a 6819{
355afbcd
KR		 6820 switch (frag->fr_subtype & 0x3)
6821 {
6822 case BYTE:
6823 return 1;
6824 case SHORT:
6825 return 2;
6826 case LONG:
6827 return 4;
6828 default:
6829 abort ();
064ba683 6830 return 0;
355afbcd 6831 }
3ad9ec6a 6832}
49864cfa 6833#endif
355afbcd 6834
fecd2382 6835/* end of tc-m68k.c */
GDB Binutils - Deliverables
This page took 0.643856 seconds and 4 git commands to generate.