Commit | Line | Data |
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252b5132 | 1 | /* tc-m68k.c -- Assemble for the m68k family |
6f2750fe | 2 | Copyright (C) 1987-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
252b5132 | 21 | #include "as.h" |
3882b010 | 22 | #include "safe-ctype.h" |
252b5132 RH |
23 | #include "obstack.h" |
24 | #include "subsegs.h" | |
f27a3839 | 25 | #include "dwarf2dbg.h" |
c04898f8 | 26 | #include "dw2gencfi.h" |
252b5132 RH |
27 | |
28 | #include "opcode/m68k.h" | |
29 | #include "m68k-parse.h" | |
30 | ||
0d96863f CM |
31 | #if defined (OBJ_ELF) |
32 | #include "elf/m68k.h" | |
33 | #endif | |
34 | ||
31302357 AS |
35 | #ifdef M68KCOFF |
36 | #include "obj-coff.h" | |
37 | #endif | |
38 | ||
cf869cce NC |
39 | #ifdef OBJ_ELF |
40 | static void m68k_elf_cons (int); | |
41 | #endif | |
42 | ||
252b5132 RH |
43 | /* This string holds the chars that always start a comment. If the |
44 | pre-processor is disabled, these aren't very useful. The macro | |
45 | tc_comment_chars points to this. We use this, rather than the | |
46 | usual comment_chars, so that the --bitwise-or option will work. */ | |
47 | #if defined (TE_SVR4) || defined (TE_DELTA) | |
48 | const char *m68k_comment_chars = "|#"; | |
49 | #else | |
50 | const char *m68k_comment_chars = "|"; | |
51 | #endif | |
52 | ||
53 | /* This array holds the chars that only start a comment at the beginning of | |
54 | a line. If the line seems to have the form '# 123 filename' | |
55 | .line and .file directives will appear in the pre-processed output */ | |
56 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
57 | first line of the input file. This is because the compiler outputs | |
92774660 KH |
58 | #NO_APP at the beginning of its output. */ |
59 | /* Also note that comments like this one will always work. */ | |
252b5132 RH |
60 | const char line_comment_chars[] = "#*"; |
61 | ||
63a0b638 | 62 | const char line_separator_chars[] = ";"; |
252b5132 | 63 | |
36759679 | 64 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
5a38dc70 | 65 | const char EXP_CHARS[] = "eE"; |
252b5132 RH |
66 | |
67 | /* Chars that mean this number is a floating point constant, as | |
68 | in "0f12.456" or "0d1.2345e12". */ | |
69 | ||
5a38dc70 | 70 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
252b5132 RH |
71 | |
72 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
73 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
74 | but nothing is ideal around here. */ | |
75 | ||
252b5132 RH |
76 | /* Are we trying to generate PIC code? If so, absolute references |
77 | ought to be made into linkage table references or pc-relative | |
92774660 | 78 | references. Not implemented. For ELF there are other means |
252b5132 RH |
79 | to denote pic relocations. */ |
80 | int flag_want_pic; | |
81 | ||
36759679 NC |
82 | static int flag_short_refs; /* -l option. */ |
83 | static int flag_long_jumps; /* -S option. */ | |
28e7409f | 84 | static int flag_keep_pcrel; /* --pcrel option. */ |
252b5132 RH |
85 | |
86 | #ifdef REGISTER_PREFIX_OPTIONAL | |
87 | int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
88 | #else | |
89 | int flag_reg_prefix_optional; | |
90 | #endif | |
91 | ||
92 | /* Whether --register-prefix-optional was used on the command line. */ | |
93 | static int reg_prefix_optional_seen; | |
94 | ||
95 | /* The floating point coprocessor to use by default. */ | |
96 | static enum m68k_register m68k_float_copnum = COP1; | |
97 | ||
98 | /* If this is non-zero, then references to number(%pc) will be taken | |
99 | to refer to number, rather than to %pc + number. */ | |
100 | static int m68k_abspcadd; | |
101 | ||
102 | /* If this is non-zero, then the quick forms of the move, add, and sub | |
103 | instructions are used when possible. */ | |
104 | static int m68k_quick = 1; | |
105 | ||
106 | /* If this is non-zero, then if the size is not specified for a base | |
107 | or outer displacement, the assembler assumes that the size should | |
108 | be 32 bits. */ | |
109 | static int m68k_rel32 = 1; | |
110 | ||
111 | /* This is non-zero if m68k_rel32 was set from the command line. */ | |
112 | static int m68k_rel32_from_cmdline; | |
113 | ||
114 | /* The default width to use for an index register when using a base | |
115 | displacement. */ | |
116 | static enum m68k_size m68k_index_width_default = SIZE_LONG; | |
117 | ||
118 | /* We want to warn if any text labels are misaligned. In order to get | |
119 | the right line number, we need to record the line number for each | |
120 | label. */ | |
252b5132 RH |
121 | struct label_line |
122 | { | |
123 | struct label_line *next; | |
124 | symbolS *label; | |
125 | char *file; | |
126 | unsigned int line; | |
127 | int text; | |
128 | }; | |
129 | ||
130 | /* The list of labels. */ | |
131 | ||
132 | static struct label_line *labels; | |
133 | ||
134 | /* The current label. */ | |
135 | ||
136 | static struct label_line *current_label; | |
137 | ||
60fed2d3 NC |
138 | /* Pointer to list holding the opcodes sorted by name. */ |
139 | static struct m68k_opcode const ** m68k_sorted_opcodes; | |
140 | ||
36759679 NC |
141 | /* Its an arbitrary name: This means I don't approve of it. |
142 | See flames below. */ | |
252b5132 RH |
143 | static struct obstack robyn; |
144 | ||
252b5132 RH |
145 | struct m68k_incant |
146 | { | |
147 | const char *m_operands; | |
148 | unsigned long m_opcode; | |
149 | short m_opnum; | |
150 | short m_codenum; | |
151 | int m_arch; | |
152 | struct m68k_incant *m_next; | |
153 | }; | |
154 | ||
155 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
156 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
157 | ||
2da12c60 NS |
158 | static const enum m68k_register m68000_ctrl[] = { 0 }; |
159 | static const enum m68k_register m68010_ctrl[] = { | |
252b5132 RH |
160 | SFC, DFC, USP, VBR, |
161 | 0 | |
162 | }; | |
2da12c60 | 163 | static const enum m68k_register m68020_ctrl[] = { |
252b5132 RH |
164 | SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, |
165 | 0 | |
166 | }; | |
2da12c60 | 167 | static const enum m68k_register m68040_ctrl[] = { |
252b5132 RH |
168 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, |
169 | USP, VBR, MSP, ISP, MMUSR, URP, SRP, | |
170 | 0 | |
171 | }; | |
2da12c60 | 172 | static const enum m68k_register m68060_ctrl[] = { |
252b5132 RH |
173 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, |
174 | USP, VBR, URP, SRP, PCR, | |
175 | 0 | |
176 | }; | |
2da12c60 | 177 | static const enum m68k_register mcf_ctrl[] = { |
3e602632 | 178 | CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, |
78336706 NS |
179 | RAMBAR0, RAMBAR1, RAMBAR, MBAR, |
180 | 0 | |
181 | }; | |
87298967 NS |
182 | static const enum m68k_register mcf51_ctrl[] = { |
183 | VBR, CPUCR, | |
f75192f2 KH |
184 | 0 |
185 | }; | |
78336706 | 186 | static const enum m68k_register mcf5206_ctrl[] = { |
0d999f33 | 187 | CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, |
252b5132 RH |
188 | 0 |
189 | }; | |
2da12c60 | 190 | static const enum m68k_register mcf5208_ctrl[] = { |
78336706 | 191 | CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, |
266abb8f NS |
192 | 0 |
193 | }; | |
96e0bbcc | 194 | static const enum m68k_register mcf5210a_ctrl[] = { |
78336706 | 195 | VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, |
96e0bbcc NS |
196 | 0 |
197 | }; | |
2da12c60 | 198 | static const enum m68k_register mcf5213_ctrl[] = { |
78336706 | 199 | VBR, RAMBAR, RAMBAR1, FLASHBAR, |
266abb8f NS |
200 | 0 |
201 | }; | |
2da12c60 | 202 | static const enum m68k_register mcf5216_ctrl[] = { |
78336706 | 203 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
266abb8f NS |
204 | 0 |
205 | }; | |
46203761 MK |
206 | static const enum m68k_register mcf5221x_ctrl[] = { |
207 | VBR, FLASHBAR, RAMBAR, RAMBAR1, | |
208 | 0 | |
209 | }; | |
d5be9593 | 210 | static const enum m68k_register mcf52223_ctrl[] = { |
0d999f33 | 211 | VBR, FLASHBAR, RAMBAR, RAMBAR1, |
d5be9593 NS |
212 | 0 |
213 | }; | |
96e0bbcc | 214 | static const enum m68k_register mcf52235_ctrl[] = { |
b345c8c2 | 215 | VBR, FLASHBAR, RAMBAR, RAMBAR1, |
96e0bbcc NS |
216 | 0 |
217 | }; | |
218 | static const enum m68k_register mcf5225_ctrl[] = { | |
78336706 | 219 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, |
96e0bbcc NS |
220 | 0 |
221 | }; | |
87298967 NS |
222 | static const enum m68k_register mcf52259_ctrl[] = { |
223 | VBR, FLASHBAR, RAMBAR, RAMBAR1, | |
224 | 0 | |
225 | }; | |
226 | static const enum m68k_register mcf52277_ctrl[] = { | |
227 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, | |
228 | 0 | |
229 | }; | |
2da12c60 | 230 | static const enum m68k_register mcf5235_ctrl[] = { |
78336706 | 231 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
e80e0390 NC |
232 | 0 |
233 | }; | |
2da12c60 | 234 | static const enum m68k_register mcf5249_ctrl[] = { |
78336706 | 235 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, |
3e602632 NC |
236 | 0 |
237 | }; | |
2da12c60 NS |
238 | static const enum m68k_register mcf5250_ctrl[] = { |
239 | VBR, | |
240 | 0 | |
241 | }; | |
d5be9593 | 242 | static const enum m68k_register mcf5253_ctrl[] = { |
def8fc92 | 243 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, |
d5be9593 NS |
244 | 0 |
245 | }; | |
2da12c60 | 246 | static const enum m68k_register mcf5271_ctrl[] = { |
78336706 | 247 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
248 | 0 |
249 | }; | |
250 | static const enum m68k_register mcf5272_ctrl[] = { | |
78336706 | 251 | VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, |
2da12c60 NS |
252 | 0 |
253 | }; | |
254 | static const enum m68k_register mcf5275_ctrl[] = { | |
78336706 | 255 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
256 | 0 |
257 | }; | |
258 | static const enum m68k_register mcf5282_ctrl[] = { | |
78336706 NS |
259 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
260 | 0 | |
261 | }; | |
87298967 | 262 | static const enum m68k_register mcf53017_ctrl[] = { |
b345c8c2 | 263 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
87298967 NS |
264 | 0 |
265 | }; | |
78336706 | 266 | static const enum m68k_register mcf5307_ctrl[] = { |
87298967 | 267 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, |
2da12c60 NS |
268 | 0 |
269 | }; | |
270 | static const enum m68k_register mcf5329_ctrl[] = { | |
78336706 | 271 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
272 | 0 |
273 | }; | |
274 | static const enum m68k_register mcf5373_ctrl[] = { | |
78336706 | 275 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
276 | 0 |
277 | }; | |
278 | static const enum m68k_register mcfv4e_ctrl[] = { | |
a8e24a56 NS |
279 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, |
280 | VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, | |
281 | MBAR, SECMBAR, | |
282 | MPCR /* Multiprocessor Control register */, | |
283 | EDRAMBAR /* Embedded DRAM Base Address Register */, | |
284 | /* Permutation control registers. */ | |
3e602632 NC |
285 | PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, |
286 | PCR3U0, PCR3L0, PCR3U1, PCR3L1, | |
a8e24a56 NS |
287 | /* Legacy names */ |
288 | TC /* ASID */, BUSCR /* MMUBAR */, | |
289 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
290 | MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, | |
78336706 | 291 | ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, |
a8e24a56 NS |
292 | 0 |
293 | }; | |
def8fc92 KH |
294 | static const enum m68k_register mcf5407_ctrl[] = { |
295 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, | |
296 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
297 | /* Legacy names */ | |
298 | TC /* ASID */, | |
299 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
300 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, | |
301 | 0 | |
302 | }; | |
0d999f33 MK |
303 | static const enum m68k_register mcf54418_ctrl[] = { |
304 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR, | |
305 | VBR, PC, RAMBAR1, | |
306 | /* Legacy names */ | |
307 | TC /* ASID */, BUSCR /* MMUBAR */, | |
308 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
309 | RAMBAR /* RAMBAR1 */, | |
310 | 0 | |
311 | }; | |
9a2e615a NS |
312 | static const enum m68k_register mcf54455_ctrl[] = { |
313 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
0d999f33 | 314 | VBR, PC, RAMBAR1, |
9a2e615a NS |
315 | /* Legacy names */ |
316 | TC /* ASID */, BUSCR /* MMUBAR */, | |
317 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
0d999f33 | 318 | RAMBAR /* RAMBAR1 */, |
9a2e615a NS |
319 | 0 |
320 | }; | |
a8e24a56 NS |
321 | static const enum m68k_register mcf5475_ctrl[] = { |
322 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
323 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
324 | /* Legacy names */ | |
325 | TC /* ASID */, BUSCR /* MMUBAR */, | |
326 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
78336706 | 327 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, |
a8e24a56 NS |
328 | 0 |
329 | }; | |
330 | static const enum m68k_register mcf5485_ctrl[] = { | |
331 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
332 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
333 | /* Legacy names */ | |
334 | TC /* ASID */, BUSCR /* MMUBAR */, | |
335 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
78336706 | 336 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, |
3e602632 NC |
337 | 0 |
338 | }; | |
f7ec513b | 339 | static const enum m68k_register fido_ctrl[] = { |
d0fa1372 | 340 | SFC, DFC, USP, VBR, CAC, MBO, |
f7ec513b KH |
341 | 0 |
342 | }; | |
2da12c60 | 343 | #define cpu32_ctrl m68010_ctrl |
252b5132 RH |
344 | |
345 | static const enum m68k_register *control_regs; | |
346 | ||
36759679 | 347 | /* Internal form of a 68020 instruction. */ |
252b5132 RH |
348 | struct m68k_it |
349 | { | |
350 | const char *error; | |
36759679 | 351 | const char *args; /* List of opcode info. */ |
252b5132 RH |
352 | int numargs; |
353 | ||
36759679 | 354 | int numo; /* Number of shorts in opcode. */ |
252b5132 RH |
355 | short opcode[11]; |
356 | ||
357 | struct m68k_op operands[6]; | |
358 | ||
36759679 | 359 | int nexp; /* Number of exprs in use. */ |
252b5132 RH |
360 | struct m68k_exp exprs[4]; |
361 | ||
36759679 | 362 | int nfrag; /* Number of frags we have to produce. */ |
252b5132 RH |
363 | struct |
364 | { | |
36759679 | 365 | int fragoff; /* Where in the current opcode the frag ends. */ |
252b5132 RH |
366 | symbolS *fadd; |
367 | offsetT foff; | |
368 | int fragty; | |
369 | } | |
370 | fragb[4]; | |
371 | ||
36759679 | 372 | int nrel; /* Num of reloc strucs in use. */ |
252b5132 RH |
373 | struct |
374 | { | |
375 | int n; | |
376 | expressionS exp; | |
377 | char wid; | |
378 | char pcrel; | |
379 | /* In a pc relative address the difference between the address | |
380 | of the offset and the address that the offset is relative | |
381 | to. This depends on the addressing mode. Basically this | |
382 | is the value to put in the offset field to address the | |
383 | first byte of the offset, without regarding the special | |
384 | significance of some values (in the branch instruction, for | |
385 | example). */ | |
386 | int pcrel_fix; | |
387 | #ifdef OBJ_ELF | |
388 | /* Whether this expression needs special pic relocation, and if | |
389 | so, which. */ | |
390 | enum pic_relocation pic_reloc; | |
391 | #endif | |
392 | } | |
36759679 | 393 | reloc[5]; /* Five is enough??? */ |
252b5132 RH |
394 | }; |
395 | ||
9840d27e | 396 | #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) |
252b5132 RH |
397 | #define float_of_arch(x) ((x) & mfloat) |
398 | #define mmu_of_arch(x) ((x) & mmmu) | |
6b6e92f4 NC |
399 | #define arch_coldfire_p(x) ((x) & mcfisa_a) |
400 | #define arch_coldfire_fpu(x) ((x) & cfloat) | |
252b5132 | 401 | |
36759679 | 402 | /* Macros for determining if cpu supports a specific addressing mode. */ |
9a2e615a NS |
403 | #define HAVE_LONG_DISP(x) \ |
404 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
405 | #define HAVE_LONG_CALL(x) \ | |
406 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
407 | #define HAVE_LONG_COND(x) \ | |
408 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
409 | #define HAVE_LONG_BRANCH(x) \ | |
410 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) | |
cac27205 | 411 | #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) |
252b5132 | 412 | |
36759679 | 413 | static struct m68k_it the_ins; /* The instruction being assembled. */ |
252b5132 RH |
414 | |
415 | #define op(ex) ((ex)->exp.X_op) | |
416 | #define adds(ex) ((ex)->exp.X_add_symbol) | |
417 | #define subs(ex) ((ex)->exp.X_op_symbol) | |
418 | #define offs(ex) ((ex)->exp.X_add_number) | |
419 | ||
36759679 | 420 | /* Macros for adding things to the m68k_it struct. */ |
31302357 | 421 | #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) |
252b5132 | 422 | |
36759679 NC |
423 | /* Like addword, but goes BEFORE general operands. */ |
424 | ||
252b5132 | 425 | static void |
31302357 | 426 | insop (int w, const struct m68k_incant *opcode) |
252b5132 RH |
427 | { |
428 | int z; | |
07726851 | 429 | for (z = the_ins.numo; z > opcode->m_codenum; --z) |
8a104df9 KH |
430 | the_ins.opcode[z] = the_ins.opcode[z - 1]; |
431 | for (z = 0; z < the_ins.nrel; z++) | |
432 | the_ins.reloc[z].n += 2; | |
252b5132 RH |
433 | for (z = 0; z < the_ins.nfrag; z++) |
434 | the_ins.fragb[z].fragoff++; | |
8a104df9 | 435 | the_ins.opcode[opcode->m_codenum] = w; |
252b5132 RH |
436 | the_ins.numo++; |
437 | } | |
438 | ||
439 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. | |
440 | Blecch. */ | |
441 | static void | |
31302357 | 442 | add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) |
252b5132 | 443 | { |
31302357 AS |
444 | the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' |
445 | ? the_ins.numo * 2 - 1 | |
446 | : (width == 'b' | |
447 | ? the_ins.numo * 2 + 1 | |
448 | : the_ins.numo * 2)); | |
252b5132 RH |
449 | the_ins.reloc[the_ins.nrel].exp = exp->exp; |
450 | the_ins.reloc[the_ins.nrel].wid = width; | |
451 | the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; | |
452 | #ifdef OBJ_ELF | |
453 | the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; | |
454 | #endif | |
455 | the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; | |
456 | } | |
457 | ||
458 | /* Cause an extra frag to be generated here, inserting up to 10 bytes | |
459 | (that value is chosen in the frag_var call in md_assemble). TYPE | |
460 | is the subtype of the frag to be generated; its primary type is | |
461 | rs_machine_dependent. | |
462 | ||
463 | The TYPE parameter is also used by md_convert_frag_1 and | |
464 | md_estimate_size_before_relax. The appropriate type of fixup will | |
465 | be emitted by md_convert_frag_1. | |
466 | ||
467 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
468 | static void | |
31302357 | 469 | add_frag (symbolS *add, offsetT off, int type) |
252b5132 | 470 | { |
8a104df9 KH |
471 | the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; |
472 | the_ins.fragb[the_ins.nfrag].fadd = add; | |
473 | the_ins.fragb[the_ins.nfrag].foff = off; | |
474 | the_ins.fragb[the_ins.nfrag++].fragty = type; | |
252b5132 RH |
475 | } |
476 | ||
477 | #define isvar(ex) \ | |
478 | (op (ex) != O_constant && op (ex) != O_big) | |
479 | ||
31302357 AS |
480 | static char *crack_operand (char *str, struct m68k_op *opP); |
481 | static int get_num (struct m68k_exp *exp, int ok); | |
482 | static int reverse_16_bits (int in); | |
483 | static int reverse_8_bits (int in); | |
484 | static void install_gen_operand (int mode, int val); | |
485 | static void install_operand (int mode, int val); | |
486 | static void s_bss (int); | |
487 | static void s_data1 (int); | |
488 | static void s_data2 (int); | |
489 | static void s_even (int); | |
490 | static void s_proc (int); | |
491 | static void s_chip (int); | |
492 | static void s_fopt (int); | |
493 | static void s_opt (int); | |
494 | static void s_reg (int); | |
495 | static void s_restore (int); | |
496 | static void s_save (int); | |
497 | static void s_mri_if (int); | |
498 | static void s_mri_else (int); | |
499 | static void s_mri_endi (int); | |
500 | static void s_mri_break (int); | |
501 | static void s_mri_next (int); | |
502 | static void s_mri_for (int); | |
503 | static void s_mri_endf (int); | |
504 | static void s_mri_repeat (int); | |
505 | static void s_mri_until (int); | |
506 | static void s_mri_while (int); | |
507 | static void s_mri_endw (int); | |
266abb8f NS |
508 | static void s_m68k_cpu (int); |
509 | static void s_m68k_arch (int); | |
510 | ||
511 | struct m68k_cpu | |
512 | { | |
513 | unsigned long arch; /* Architecture features. */ | |
2da12c60 | 514 | const enum m68k_register *control_regs; /* Control regs on chip */ |
266abb8f | 515 | const char *name; /* Name */ |
0b2e31dc NS |
516 | int alias; /* Alias for a cannonical name. If 1, then |
517 | succeeds canonical name, if -1 then | |
518 | succeeds canonical name, if <-1 ||>1 this is a | |
519 | deprecated name, and the next/previous name | |
520 | should be used. */ | |
266abb8f | 521 | }; |
252b5132 | 522 | |
266abb8f NS |
523 | /* We hold flags for features explicitly enabled and explicitly |
524 | disabled. */ | |
252b5132 | 525 | static int current_architecture; |
266abb8f | 526 | static int not_current_architecture; |
266abb8f NS |
527 | static const struct m68k_cpu *selected_arch; |
528 | static const struct m68k_cpu *selected_cpu; | |
529 | static int initialized; | |
252b5132 | 530 | |
266abb8f NS |
531 | /* Architecture models. */ |
532 | static const struct m68k_cpu m68k_archs[] = | |
533 | { | |
2da12c60 NS |
534 | {m68000, m68000_ctrl, "68000", 0}, |
535 | {m68010, m68010_ctrl, "68010", 0}, | |
536 | {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, | |
537 | {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, | |
538 | {m68040, m68040_ctrl, "68040", 0}, | |
539 | {m68060, m68060_ctrl, "68060", 0}, | |
540 | {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, | |
3bdcfdf4 | 541 | {fido_a, fido_ctrl, "fidoa", 0}, |
2da12c60 NS |
542 | {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, |
543 | {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, | |
544 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, | |
9a2e615a | 545 | {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, |
2da12c60 NS |
546 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, |
547 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, | |
266abb8f NS |
548 | {0,0,NULL, 0} |
549 | }; | |
252b5132 | 550 | |
87298967 NS |
551 | /* For -mno-mac we want to turn off all types of mac. */ |
552 | static const unsigned no_mac = mcfmac | mcfemac; | |
553 | ||
0b2e31dc NS |
554 | /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 |
555 | for either. */ | |
266abb8f NS |
556 | static const struct m68k_cpu m68k_extensions[] = |
557 | { | |
2da12c60 NS |
558 | {m68851, NULL, "68851", -1}, |
559 | {m68881, NULL, "68881", -1}, | |
560 | {m68881, NULL, "68882", -1}, | |
cf869cce | 561 | |
2da12c60 | 562 | {cfloat|m68881, NULL, "float", 0}, |
cf869cce | 563 | |
2da12c60 NS |
564 | {mcfhwdiv, NULL, "div", 1}, |
565 | {mcfusp, NULL, "usp", 1}, | |
87298967 | 566 | {mcfmac, (void *)&no_mac, "mac", 1}, |
2da12c60 | 567 | {mcfemac, NULL, "emac", 1}, |
cf869cce | 568 | |
2da12c60 | 569 | {0,NULL,NULL, 0} |
266abb8f NS |
570 | }; |
571 | ||
572 | /* Processor list */ | |
573 | static const struct m68k_cpu m68k_cpus[] = | |
574 | { | |
2da12c60 NS |
575 | {m68000, m68000_ctrl, "68000", 0}, |
576 | {m68000, m68000_ctrl, "68ec000", 1}, | |
577 | {m68000, m68000_ctrl, "68hc000", 1}, | |
578 | {m68000, m68000_ctrl, "68hc001", 1}, | |
579 | {m68000, m68000_ctrl, "68008", 1}, | |
580 | {m68000, m68000_ctrl, "68302", 1}, | |
581 | {m68000, m68000_ctrl, "68306", 1}, | |
582 | {m68000, m68000_ctrl, "68307", 1}, | |
583 | {m68000, m68000_ctrl, "68322", 1}, | |
584 | {m68000, m68000_ctrl, "68356", 1}, | |
585 | {m68010, m68010_ctrl, "68010", 0}, | |
586 | {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, | |
587 | {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, | |
588 | {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, | |
589 | {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, | |
590 | {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, | |
591 | {m68040, m68040_ctrl, "68040", 0}, | |
592 | {m68040, m68040_ctrl, "68ec040", 1}, | |
593 | {m68060, m68060_ctrl, "68060", 0}, | |
594 | {m68060, m68060_ctrl, "68ec060", 1}, | |
cf869cce | 595 | |
2da12c60 NS |
596 | {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, |
597 | {cpu32|m68881, cpu32_ctrl, "68330", 1}, | |
598 | {cpu32|m68881, cpu32_ctrl, "68331", 1}, | |
599 | {cpu32|m68881, cpu32_ctrl, "68332", 1}, | |
600 | {cpu32|m68881, cpu32_ctrl, "68333", 1}, | |
601 | {cpu32|m68881, cpu32_ctrl, "68334", 1}, | |
602 | {cpu32|m68881, cpu32_ctrl, "68336", 1}, | |
603 | {cpu32|m68881, cpu32_ctrl, "68340", 1}, | |
604 | {cpu32|m68881, cpu32_ctrl, "68341", 1}, | |
605 | {cpu32|m68881, cpu32_ctrl, "68349", 1}, | |
606 | {cpu32|m68881, cpu32_ctrl, "68360", 1}, | |
f75192f2 | 607 | |
87298967 NS |
608 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, |
609 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, | |
c1c30076 | 610 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1}, |
87298967 NS |
611 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, |
612 | {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, | |
c1c30076 NS |
613 | {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1}, |
614 | {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1}, | |
615 | {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1}, | |
87298967 | 616 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, |
c1c30076 | 617 | {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1}, |
87298967 | 618 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, |
c1c30076 | 619 | {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1}, |
cf869cce | 620 | |
2da12c60 NS |
621 | {mcfisa_a, mcf_ctrl, "5200", 0}, |
622 | {mcfisa_a, mcf_ctrl, "5202", 1}, | |
623 | {mcfisa_a, mcf_ctrl, "5204", 1}, | |
78336706 | 624 | {mcfisa_a, mcf5206_ctrl, "5206", 1}, |
cf869cce | 625 | |
78336706 | 626 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, |
cf869cce | 627 | |
2da12c60 NS |
628 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, |
629 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, | |
cf869cce | 630 | |
96e0bbcc NS |
631 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, |
632 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, | |
cf869cce | 633 | |
2da12c60 NS |
634 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, |
635 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, | |
636 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, | |
cf869cce | 637 | |
2da12c60 NS |
638 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, |
639 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, | |
640 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, | |
641 | ||
46203761 MK |
642 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0}, |
643 | ||
d5be9593 NS |
644 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, |
645 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, | |
646 | ||
96e0bbcc NS |
647 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, |
648 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, | |
649 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, | |
650 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, | |
cf869cce | 651 | |
96e0bbcc NS |
652 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, |
653 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, | |
cf869cce | 654 | |
87298967 NS |
655 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, |
656 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, | |
3739860c | 657 | |
2da12c60 NS |
658 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, |
659 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, | |
660 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, | |
661 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, | |
662 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, | |
3739860c | 663 | |
2da12c60 NS |
664 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, |
665 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, | |
d5be9593 | 666 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, |
87298967 NS |
667 | |
668 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, | |
669 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, | |
670 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, | |
671 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, | |
672 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, | |
673 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, | |
3739860c | 674 | |
2da12c60 NS |
675 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, |
676 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, | |
3739860c | 677 | |
2da12c60 | 678 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, |
3739860c | 679 | |
2da12c60 NS |
680 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, |
681 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, | |
3739860c | 682 | |
2da12c60 NS |
683 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, |
684 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, | |
685 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, | |
686 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, | |
3739860c | 687 | |
87298967 NS |
688 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, |
689 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, | |
690 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, | |
691 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, | |
692 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, | |
693 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, | |
694 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, | |
3739860c | 695 | |
78336706 | 696 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, |
3739860c | 697 | |
2da12c60 NS |
698 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, |
699 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, | |
700 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, | |
701 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, | |
3739860c | 702 | |
2da12c60 NS |
703 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, |
704 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, | |
705 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, | |
3739860c | 706 | |
def8fc92 | 707 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, |
9a2e615a | 708 | |
0d999f33 MK |
709 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1}, |
710 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1}, | |
711 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1}, | |
712 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1}, | |
713 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0}, | |
714 | ||
9a2e615a NS |
715 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, |
716 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, | |
717 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, | |
718 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, | |
719 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, | |
720 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, | |
3739860c | 721 | |
a8e24a56 NS |
722 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, |
723 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, | |
724 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, | |
725 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, | |
726 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, | |
727 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, | |
728 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, | |
3739860c | 729 | |
a8e24a56 NS |
730 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, |
731 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, | |
732 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, | |
733 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, | |
734 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, | |
735 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, | |
736 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, | |
3739860c | 737 | |
b3768379 | 738 | {fido_a, fido_ctrl, "fidoa", 0}, |
3bdcfdf4 | 739 | {fido_a, fido_ctrl, "fido", 1}, |
9840d27e | 740 | |
2da12c60 | 741 | {0,NULL,NULL, 0} |
dc84e067 | 742 | }; |
252b5132 | 743 | |
266abb8f NS |
744 | static const struct m68k_cpu *m68k_lookup_cpu |
745 | (const char *, const struct m68k_cpu *, int, int *); | |
746 | static int m68k_set_arch (const char *, int, int); | |
747 | static int m68k_set_cpu (const char *, int, int); | |
748 | static int m68k_set_extension (const char *, int, int); | |
749 | static void m68k_init_arch (void); | |
252b5132 | 750 | |
151337e8 NC |
751 | /* This is the assembler relaxation table for m68k. m68k is a rich CISC |
752 | architecture and we have a lot of relaxation modes. */ | |
252b5132 | 753 | |
151337e8 NC |
754 | /* Macros used in the relaxation code. */ |
755 | #define TAB(x,y) (((x) << 2) + (y)) | |
756 | #define TABTYPE(x) ((x) >> 2) | |
757 | ||
758 | /* Relaxation states. */ | |
759 | #define BYTE 0 | |
760 | #define SHORT 1 | |
761 | #define LONG 2 | |
762 | #define SZ_UNDEF 3 | |
763 | ||
764 | /* Here are all the relaxation modes we support. First we can relax ordinary | |
765 | branches. On 68020 and higher and on CPU32 all branch instructions take | |
766 | three forms, so on these CPUs all branches always remain as such. When we | |
767 | have to expand to the LONG form on a 68000, though, we substitute an | |
768 | absolute jump instead. This is a direct replacement for unconditional | |
769 | branches and a branch over a jump for conditional branches. However, if the | |
770 | user requires PIC and disables this with --pcrel, we can only relax between | |
771 | BYTE and SHORT forms, punting if that isn't enough. This gives us four | |
772 | different relaxation modes for branches: */ | |
773 | ||
36759679 NC |
774 | #define BRANCHBWL 0 /* Branch byte, word, or long. */ |
775 | #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ | |
776 | #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ | |
777 | #define BRANCHBW 3 /* Branch byte or word. */ | |
151337e8 NC |
778 | |
779 | /* We also relax coprocessor branches and DBcc's. All CPUs that support | |
780 | coprocessor branches support them in word and long forms, so we have only | |
781 | one relaxation mode for them. DBcc's are word only on all CPUs. We can | |
782 | relax them to the LONG form with a branch-around sequence. This sequence | |
783 | can use a long branch (if available) or an absolute jump (if acceptable). | |
784 | This gives us two relaxation modes. If long branches are not available and | |
785 | absolute jumps are not acceptable, we don't relax DBcc's. */ | |
786 | ||
36759679 NC |
787 | #define FBRANCH 4 /* Coprocessor branch. */ |
788 | #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ | |
789 | #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ | |
151337e8 NC |
790 | |
791 | /* That's all for instruction relaxation. However, we also relax PC-relative | |
792 | operands. Specifically, we have three operand relaxation modes. On the | |
793 | 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and | |
794 | on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the | |
795 | two. Also PC+displacement+index operands in their simple form (with a non- | |
796 | suppressed index without memory indirection) are supported on all CPUs, but | |
797 | on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher | |
798 | and on CPU32 we relax it to SHORT and LONG forms as well using the extended | |
799 | form of the PC+displacement+index operand. Finally, some absolute operands | |
800 | can be relaxed down to 16-bit PC-relative. */ | |
801 | ||
36759679 NC |
802 | #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ |
803 | #define PCINDEX 8 /* PC + displacement + index. */ | |
804 | #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ | |
252b5132 | 805 | |
cac27205 NC |
806 | /* This relaxation is required for branches where there is no long |
807 | branch and we are in pcrel mode. We generate a bne/beq pair. */ | |
808 | #define BRANCHBWPL 10 /* Branch byte, word or pair of longs | |
809 | */ | |
810 | ||
252b5132 | 811 | /* Note that calls to frag_var need to specify the maximum expansion |
cac27205 NC |
812 | needed; this is currently 12 bytes for bne/beq pair. */ |
813 | #define FRAG_VAR_SIZE 12 | |
252b5132 RH |
814 | |
815 | /* The fields are: | |
816 | How far Forward this mode will reach: | |
817 | How far Backward this mode will reach: | |
818 | How many bytes this mode will add to the size of the frag | |
819 | Which mode to go to if the offset won't fit in this one | |
d7861ad2 AM |
820 | |
821 | Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ | |
252b5132 RH |
822 | relax_typeS md_relax_table[] = |
823 | { | |
ac62c346 AM |
824 | { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, |
825 | { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, | |
826 | { 0, 0, 4, 0 }, | |
827 | { 1, 1, 0, 0 }, | |
828 | ||
829 | { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, | |
830 | { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, | |
831 | { 0, 0, 4, 0 }, | |
832 | { 1, 1, 0, 0 }, | |
833 | ||
834 | { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, | |
835 | { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, | |
836 | { 0, 0, 6, 0 }, | |
837 | { 1, 1, 0, 0 }, | |
838 | ||
839 | { 127, -128, 0, TAB (BRANCHBW, SHORT) }, | |
840 | { 0, 0, 2, 0 }, | |
841 | { 1, 1, 0, 0 }, | |
842 | { 1, 1, 0, 0 }, | |
843 | ||
36759679 | 844 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ |
ac62c346 AM |
845 | { 32767, -32768, 2, TAB (FBRANCH, LONG) }, |
846 | { 0, 0, 4, 0 }, | |
847 | { 1, 1, 0, 0 }, | |
848 | ||
36759679 | 849 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
850 | { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, |
851 | { 0, 0, 10, 0 }, | |
852 | { 1, 1, 0, 0 }, | |
853 | ||
36759679 | 854 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
855 | { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, |
856 | { 0, 0, 10, 0 }, | |
857 | { 1, 1, 0, 0 }, | |
858 | ||
36759679 | 859 | { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ |
ac62c346 AM |
860 | { 32767, -32768, 2, TAB (PCREL1632, LONG) }, |
861 | { 0, 0, 6, 0 }, | |
862 | { 1, 1, 0, 0 }, | |
863 | ||
864 | { 125, -130, 0, TAB (PCINDEX, SHORT) }, | |
865 | { 32765, -32770, 2, TAB (PCINDEX, LONG) }, | |
866 | { 0, 0, 4, 0 }, | |
867 | { 1, 1, 0, 0 }, | |
868 | ||
36759679 | 869 | { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ |
ac62c346 AM |
870 | { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, |
871 | { 0, 0, 4, 0 }, | |
872 | { 1, 1, 0, 0 }, | |
3739860c | 873 | |
cac27205 NC |
874 | { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, |
875 | { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, | |
876 | { 0, 0, 10, 0 }, | |
877 | { 1, 1, 0, 0 }, | |
252b5132 RH |
878 | }; |
879 | ||
880 | /* These are the machine dependent pseudo-ops. These are included so | |
881 | the assembler can work on the output from the SUN C compiler, which | |
36759679 | 882 | generates these. */ |
252b5132 RH |
883 | |
884 | /* This table describes all the machine specific pseudo-ops the assembler | |
885 | has to support. The fields are: | |
886 | pseudo-op name without dot | |
887 | function to call to execute this pseudo-op | |
36759679 | 888 | Integer arg to pass to the function. */ |
252b5132 RH |
889 | const pseudo_typeS md_pseudo_table[] = |
890 | { | |
891 | {"data1", s_data1, 0}, | |
892 | {"data2", s_data2, 0}, | |
893 | {"bss", s_bss, 0}, | |
894 | {"even", s_even, 0}, | |
895 | {"skip", s_space, 0}, | |
896 | {"proc", s_proc, 0}, | |
897 | #if defined (TE_SUN3) || defined (OBJ_ELF) | |
898 | {"align", s_align_bytes, 0}, | |
899 | #endif | |
900 | #ifdef OBJ_ELF | |
901 | {"swbeg", s_ignore, 0}, | |
cf869cce | 902 | {"long", m68k_elf_cons, 4}, |
252b5132 RH |
903 | #endif |
904 | {"extend", float_cons, 'x'}, | |
905 | {"ldouble", float_cons, 'x'}, | |
906 | ||
266abb8f NS |
907 | {"arch", s_m68k_arch, 0}, |
908 | {"cpu", s_m68k_cpu, 0}, | |
909 | ||
252b5132 RH |
910 | /* The following pseudo-ops are supported for MRI compatibility. */ |
911 | {"chip", s_chip, 0}, | |
912 | {"comline", s_space, 1}, | |
913 | {"fopt", s_fopt, 0}, | |
914 | {"mask2", s_ignore, 0}, | |
915 | {"opt", s_opt, 0}, | |
916 | {"reg", s_reg, 0}, | |
917 | {"restore", s_restore, 0}, | |
918 | {"save", s_save, 0}, | |
919 | ||
920 | {"if", s_mri_if, 0}, | |
921 | {"if.b", s_mri_if, 'b'}, | |
922 | {"if.w", s_mri_if, 'w'}, | |
923 | {"if.l", s_mri_if, 'l'}, | |
924 | {"else", s_mri_else, 0}, | |
925 | {"else.s", s_mri_else, 's'}, | |
926 | {"else.l", s_mri_else, 'l'}, | |
927 | {"endi", s_mri_endi, 0}, | |
928 | {"break", s_mri_break, 0}, | |
929 | {"break.s", s_mri_break, 's'}, | |
930 | {"break.l", s_mri_break, 'l'}, | |
931 | {"next", s_mri_next, 0}, | |
932 | {"next.s", s_mri_next, 's'}, | |
933 | {"next.l", s_mri_next, 'l'}, | |
934 | {"for", s_mri_for, 0}, | |
935 | {"for.b", s_mri_for, 'b'}, | |
936 | {"for.w", s_mri_for, 'w'}, | |
937 | {"for.l", s_mri_for, 'l'}, | |
938 | {"endf", s_mri_endf, 0}, | |
939 | {"repeat", s_mri_repeat, 0}, | |
940 | {"until", s_mri_until, 0}, | |
941 | {"until.b", s_mri_until, 'b'}, | |
942 | {"until.w", s_mri_until, 'w'}, | |
943 | {"until.l", s_mri_until, 'l'}, | |
944 | {"while", s_mri_while, 0}, | |
945 | {"while.b", s_mri_while, 'b'}, | |
946 | {"while.w", s_mri_while, 'w'}, | |
947 | {"while.l", s_mri_while, 'l'}, | |
948 | {"endw", s_mri_endw, 0}, | |
949 | ||
950 | {0, 0, 0} | |
951 | }; | |
952 | ||
252b5132 | 953 | /* The mote pseudo ops are put into the opcode table, since they |
31302357 | 954 | don't start with a . they look like opcodes to gas. */ |
252b5132 | 955 | |
5a38dc70 | 956 | const pseudo_typeS mote_pseudo_table[] = |
252b5132 RH |
957 | { |
958 | ||
959 | {"dcl", cons, 4}, | |
960 | {"dc", cons, 2}, | |
961 | {"dcw", cons, 2}, | |
962 | {"dcb", cons, 1}, | |
963 | ||
964 | {"dsl", s_space, 4}, | |
965 | {"ds", s_space, 2}, | |
966 | {"dsw", s_space, 2}, | |
967 | {"dsb", s_space, 1}, | |
968 | ||
969 | {"xdef", s_globl, 0}, | |
970 | #ifdef OBJ_ELF | |
971 | {"align", s_align_bytes, 0}, | |
972 | #else | |
973 | {"align", s_align_ptwo, 0}, | |
974 | #endif | |
975 | #ifdef M68KCOFF | |
976 | {"sect", obj_coff_section, 0}, | |
977 | {"section", obj_coff_section, 0}, | |
978 | #endif | |
979 | {0, 0, 0} | |
980 | }; | |
981 | ||
bd17c2c3 AM |
982 | /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host |
983 | gives identical results to a 32-bit host. */ | |
984 | #define TRUNC(X) ((valueT) (X) & 0xffffffff) | |
985 | #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) | |
986 | ||
987 | #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) | |
988 | #define isubyte(x) ((valueT) TRUNC (x) < 0x100) | |
989 | #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) | |
990 | #define isuword(x) ((valueT) TRUNC (x) < 0x10000) | |
991 | ||
992 | #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) | |
993 | #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) | |
252b5132 RH |
994 | #define islong(x) (1) |
995 | ||
252b5132 RH |
996 | static char notend_table[256]; |
997 | static char alt_notend_table[256]; | |
998 | #define notend(s) \ | |
999 | (! (notend_table[(unsigned char) *s] \ | |
1000 | || (*s == ':' \ | |
1001 | && alt_notend_table[(unsigned char) s[1]]))) | |
1002 | ||
252b5132 RH |
1003 | #ifdef OBJ_ELF |
1004 | ||
c801568a AM |
1005 | /* Return zero if the reference to SYMBOL from within the same segment may |
1006 | be relaxed. */ | |
1007 | ||
1008 | /* On an ELF system, we can't relax an externally visible symbol, | |
1009 | because it may be overridden by a shared library. However, if | |
1010 | TARGET_OS is "elf", then we presume that we are assembling for an | |
1011 | embedded system, in which case we don't have to worry about shared | |
1012 | libraries, and we can relax any external sym. */ | |
1013 | ||
1014 | #define relaxable_symbol(symbol) \ | |
6358301e | 1015 | (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ |
c801568a AM |
1016 | || S_IS_WEAK (symbol))) |
1017 | ||
252b5132 RH |
1018 | /* Compute the relocation code for a fixup of SIZE bytes, using pc |
1019 | relative relocation if PCREL is non-zero. PIC says whether a special | |
1020 | pic relocation was requested. */ | |
1021 | ||
252b5132 | 1022 | static bfd_reloc_code_real_type |
31302357 | 1023 | get_reloc_code (int size, int pcrel, enum pic_relocation pic) |
252b5132 RH |
1024 | { |
1025 | switch (pic) | |
1026 | { | |
1027 | case pic_got_pcrel: | |
1028 | switch (size) | |
1029 | { | |
1030 | case 1: | |
1031 | return BFD_RELOC_8_GOT_PCREL; | |
1032 | case 2: | |
1033 | return BFD_RELOC_16_GOT_PCREL; | |
1034 | case 4: | |
1035 | return BFD_RELOC_32_GOT_PCREL; | |
1036 | } | |
1037 | break; | |
1038 | ||
1039 | case pic_got_off: | |
1040 | switch (size) | |
1041 | { | |
1042 | case 1: | |
1043 | return BFD_RELOC_8_GOTOFF; | |
1044 | case 2: | |
1045 | return BFD_RELOC_16_GOTOFF; | |
1046 | case 4: | |
1047 | return BFD_RELOC_32_GOTOFF; | |
1048 | } | |
1049 | break; | |
1050 | ||
1051 | case pic_plt_pcrel: | |
1052 | switch (size) | |
1053 | { | |
1054 | case 1: | |
1055 | return BFD_RELOC_8_PLT_PCREL; | |
1056 | case 2: | |
1057 | return BFD_RELOC_16_PLT_PCREL; | |
1058 | case 4: | |
1059 | return BFD_RELOC_32_PLT_PCREL; | |
1060 | } | |
1061 | break; | |
1062 | ||
1063 | case pic_plt_off: | |
1064 | switch (size) | |
1065 | { | |
1066 | case 1: | |
1067 | return BFD_RELOC_8_PLTOFF; | |
1068 | case 2: | |
1069 | return BFD_RELOC_16_PLTOFF; | |
1070 | case 4: | |
1071 | return BFD_RELOC_32_PLTOFF; | |
1072 | } | |
1073 | break; | |
1074 | ||
cf869cce NC |
1075 | case pic_tls_gd: |
1076 | switch (size) | |
1077 | { | |
1078 | case 1: | |
1079 | return BFD_RELOC_68K_TLS_GD8; | |
1080 | case 2: | |
1081 | return BFD_RELOC_68K_TLS_GD16; | |
1082 | case 4: | |
1083 | return BFD_RELOC_68K_TLS_GD32; | |
1084 | } | |
1085 | break; | |
1086 | ||
1087 | case pic_tls_ldm: | |
1088 | switch (size) | |
1089 | { | |
1090 | case 1: | |
1091 | return BFD_RELOC_68K_TLS_LDM8; | |
1092 | case 2: | |
1093 | return BFD_RELOC_68K_TLS_LDM16; | |
1094 | case 4: | |
1095 | return BFD_RELOC_68K_TLS_LDM32; | |
1096 | } | |
1097 | break; | |
1098 | ||
1099 | case pic_tls_ldo: | |
1100 | switch (size) | |
1101 | { | |
1102 | case 1: | |
1103 | return BFD_RELOC_68K_TLS_LDO8; | |
1104 | case 2: | |
1105 | return BFD_RELOC_68K_TLS_LDO16; | |
1106 | case 4: | |
1107 | return BFD_RELOC_68K_TLS_LDO32; | |
1108 | } | |
1109 | break; | |
1110 | ||
1111 | case pic_tls_ie: | |
1112 | switch (size) | |
1113 | { | |
1114 | case 1: | |
1115 | return BFD_RELOC_68K_TLS_IE8; | |
1116 | case 2: | |
1117 | return BFD_RELOC_68K_TLS_IE16; | |
1118 | case 4: | |
1119 | return BFD_RELOC_68K_TLS_IE32; | |
1120 | } | |
1121 | break; | |
1122 | ||
1123 | case pic_tls_le: | |
1124 | switch (size) | |
1125 | { | |
1126 | case 1: | |
1127 | return BFD_RELOC_68K_TLS_LE8; | |
1128 | case 2: | |
1129 | return BFD_RELOC_68K_TLS_LE16; | |
1130 | case 4: | |
1131 | return BFD_RELOC_68K_TLS_LE32; | |
1132 | } | |
1133 | break; | |
1134 | ||
252b5132 RH |
1135 | case pic_none: |
1136 | if (pcrel) | |
1137 | { | |
1138 | switch (size) | |
1139 | { | |
1140 | case 1: | |
1141 | return BFD_RELOC_8_PCREL; | |
1142 | case 2: | |
1143 | return BFD_RELOC_16_PCREL; | |
1144 | case 4: | |
1145 | return BFD_RELOC_32_PCREL; | |
1146 | } | |
1147 | } | |
1148 | else | |
1149 | { | |
1150 | switch (size) | |
1151 | { | |
1152 | case 1: | |
1153 | return BFD_RELOC_8; | |
1154 | case 2: | |
1155 | return BFD_RELOC_16; | |
1156 | case 4: | |
1157 | return BFD_RELOC_32; | |
1158 | } | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | if (pcrel) | |
1163 | { | |
1164 | if (pic == pic_none) | |
1165 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
1166 | else | |
1167 | as_bad (_("Can not do %d byte pc-relative pic relocation"), size); | |
1168 | } | |
1169 | else | |
1170 | { | |
1171 | if (pic == pic_none) | |
1172 | as_bad (_("Can not do %d byte relocation"), size); | |
1173 | else | |
1174 | as_bad (_("Can not do %d byte pic relocation"), size); | |
1175 | } | |
1176 | ||
1177 | return BFD_RELOC_NONE; | |
1178 | } | |
1179 | ||
1180 | /* Here we decide which fixups can be adjusted to make them relative | |
1181 | to the beginning of the section instead of the symbol. Basically | |
1182 | we need to make sure that the dynamic relocations are done | |
1183 | correctly, so in some cases we force the original symbol to be | |
1184 | used. */ | |
1185 | int | |
31302357 | 1186 | tc_m68k_fix_adjustable (fixS *fixP) |
252b5132 | 1187 | { |
36759679 | 1188 | /* Adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1189 | switch (fixP->fx_r_type) |
1190 | { | |
1191 | case BFD_RELOC_8_GOT_PCREL: | |
1192 | case BFD_RELOC_16_GOT_PCREL: | |
1193 | case BFD_RELOC_32_GOT_PCREL: | |
1194 | case BFD_RELOC_8_GOTOFF: | |
1195 | case BFD_RELOC_16_GOTOFF: | |
1196 | case BFD_RELOC_32_GOTOFF: | |
1197 | case BFD_RELOC_8_PLT_PCREL: | |
1198 | case BFD_RELOC_16_PLT_PCREL: | |
1199 | case BFD_RELOC_32_PLT_PCREL: | |
1200 | case BFD_RELOC_8_PLTOFF: | |
1201 | case BFD_RELOC_16_PLTOFF: | |
1202 | case BFD_RELOC_32_PLTOFF: | |
cf869cce NC |
1203 | case BFD_RELOC_68K_TLS_GD32: |
1204 | case BFD_RELOC_68K_TLS_GD16: | |
1205 | case BFD_RELOC_68K_TLS_GD8: | |
1206 | case BFD_RELOC_68K_TLS_LDM32: | |
1207 | case BFD_RELOC_68K_TLS_LDM16: | |
1208 | case BFD_RELOC_68K_TLS_LDM8: | |
1209 | case BFD_RELOC_68K_TLS_LDO32: | |
1210 | case BFD_RELOC_68K_TLS_LDO16: | |
1211 | case BFD_RELOC_68K_TLS_LDO8: | |
1212 | case BFD_RELOC_68K_TLS_IE32: | |
1213 | case BFD_RELOC_68K_TLS_IE16: | |
1214 | case BFD_RELOC_68K_TLS_IE8: | |
1215 | case BFD_RELOC_68K_TLS_LE32: | |
1216 | case BFD_RELOC_68K_TLS_LE16: | |
1217 | case BFD_RELOC_68K_TLS_LE8: | |
252b5132 RH |
1218 | return 0; |
1219 | ||
1220 | case BFD_RELOC_VTABLE_INHERIT: | |
1221 | case BFD_RELOC_VTABLE_ENTRY: | |
1222 | return 0; | |
1223 | ||
1224 | default: | |
1225 | return 1; | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | #else /* !OBJ_ELF */ | |
1230 | ||
1231 | #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC | |
1232 | ||
22184a77 NC |
1233 | /* PR gas/3041 Weak symbols are not relaxable |
1234 | because they must be treated as extern. */ | |
1235 | #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol))) | |
c801568a | 1236 | |
252b5132 RH |
1237 | #endif /* OBJ_ELF */ |
1238 | ||
252b5132 | 1239 | arelent * |
31302357 | 1240 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
1241 | { |
1242 | arelent *reloc; | |
1243 | bfd_reloc_code_real_type code; | |
1244 | ||
8ec6253e NC |
1245 | /* If the tcbit is set, then this was a fixup of a negative value |
1246 | that was never resolved. We do not have a reloc to handle this, | |
1247 | so just return. We assume that other code will have detected this | |
1248 | situation and produced a helpful error message, so we just tell the | |
1249 | user that the reloc cannot be produced. */ | |
252b5132 | 1250 | if (fixp->fx_tcbit) |
8ec6253e NC |
1251 | { |
1252 | if (fixp->fx_addsy) | |
b091f402 AM |
1253 | as_bad_where (fixp->fx_file, fixp->fx_line, |
1254 | _("Unable to produce reloc against symbol '%s'"), | |
1255 | S_GET_NAME (fixp->fx_addsy)); | |
8ec6253e NC |
1256 | return NULL; |
1257 | } | |
252b5132 RH |
1258 | |
1259 | if (fixp->fx_r_type != BFD_RELOC_NONE) | |
1260 | { | |
1261 | code = fixp->fx_r_type; | |
1262 | ||
1263 | /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible | |
1264 | that fixup_segment converted a non-PC relative reloc into a | |
1265 | PC relative reloc. In such a case, we need to convert the | |
1266 | reloc code. */ | |
1267 | if (fixp->fx_pcrel) | |
1268 | { | |
1269 | switch (code) | |
1270 | { | |
1271 | case BFD_RELOC_8: | |
1272 | code = BFD_RELOC_8_PCREL; | |
1273 | break; | |
1274 | case BFD_RELOC_16: | |
1275 | code = BFD_RELOC_16_PCREL; | |
1276 | break; | |
1277 | case BFD_RELOC_32: | |
1278 | code = BFD_RELOC_32_PCREL; | |
1279 | break; | |
1280 | case BFD_RELOC_8_PCREL: | |
1281 | case BFD_RELOC_16_PCREL: | |
1282 | case BFD_RELOC_32_PCREL: | |
1283 | case BFD_RELOC_8_GOT_PCREL: | |
1284 | case BFD_RELOC_16_GOT_PCREL: | |
1285 | case BFD_RELOC_32_GOT_PCREL: | |
1286 | case BFD_RELOC_8_GOTOFF: | |
1287 | case BFD_RELOC_16_GOTOFF: | |
1288 | case BFD_RELOC_32_GOTOFF: | |
1289 | case BFD_RELOC_8_PLT_PCREL: | |
1290 | case BFD_RELOC_16_PLT_PCREL: | |
1291 | case BFD_RELOC_32_PLT_PCREL: | |
1292 | case BFD_RELOC_8_PLTOFF: | |
1293 | case BFD_RELOC_16_PLTOFF: | |
1294 | case BFD_RELOC_32_PLTOFF: | |
cf869cce NC |
1295 | case BFD_RELOC_68K_TLS_GD32: |
1296 | case BFD_RELOC_68K_TLS_GD16: | |
1297 | case BFD_RELOC_68K_TLS_GD8: | |
1298 | case BFD_RELOC_68K_TLS_LDM32: | |
1299 | case BFD_RELOC_68K_TLS_LDM16: | |
1300 | case BFD_RELOC_68K_TLS_LDM8: | |
1301 | case BFD_RELOC_68K_TLS_LDO32: | |
1302 | case BFD_RELOC_68K_TLS_LDO16: | |
1303 | case BFD_RELOC_68K_TLS_LDO8: | |
1304 | case BFD_RELOC_68K_TLS_IE32: | |
1305 | case BFD_RELOC_68K_TLS_IE16: | |
1306 | case BFD_RELOC_68K_TLS_IE8: | |
1307 | case BFD_RELOC_68K_TLS_LE32: | |
1308 | case BFD_RELOC_68K_TLS_LE16: | |
1309 | case BFD_RELOC_68K_TLS_LE8: | |
252b5132 RH |
1310 | break; |
1311 | default: | |
1312 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1313 | _("Cannot make %s relocation PC relative"), | |
1314 | bfd_get_reloc_code_name (code)); | |
1315 | } | |
1316 | } | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) | |
1321 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
1322 | { | |
1323 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
1324 | MAP (1, 0, BFD_RELOC_8); | |
1325 | MAP (2, 0, BFD_RELOC_16); | |
1326 | MAP (4, 0, BFD_RELOC_32); | |
1327 | MAP (1, 1, BFD_RELOC_8_PCREL); | |
1328 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
1329 | MAP (4, 1, BFD_RELOC_32_PCREL); | |
1330 | default: | |
1331 | abort (); | |
1332 | } | |
1333 | } | |
1334 | #undef F | |
1335 | #undef MAP | |
1336 | ||
1337 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
1338 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1339 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1340 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1341 | #ifndef OBJ_ELF | |
33f0727f NC |
1342 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
1343 | && fixp->fx_addsy | |
1344 | && S_IS_WEAK (fixp->fx_addsy) | |
1345 | && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy))) | |
b2b74248 NC |
1346 | { |
1347 | /* PR gas/3041 References to weak symbols must be treated as extern | |
1348 | in order to be overridable by the linker, even if they are defined | |
1349 | in the same object file. So the original addend must be written | |
1350 | "as is" into the output section without further processing. | |
1351 | The addend value must be hacked here in order to force | |
1352 | bfd_install_relocation() to write the original value into the | |
1353 | output section. | |
1354 | 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol | |
1355 | value has already been added to the addend in fixup_segment(). We | |
1356 | have to remove it. | |
1357 | 2) bfd_install_relocation() will incorrectly treat this symbol as | |
1358 | resolved, so it will write the symbol value plus its addend and | |
1359 | section VMA. As a workaround we can tweak the addend value here in | |
1360 | order to get the original value in the section after the call to | |
1361 | bfd_install_relocation(). */ | |
1362 | reloc->addend = fixp->fx_addnumber | |
1363 | /* Fix because of MD_APPLY_SYM_VALUE() */ | |
1364 | - S_GET_VALUE (fixp->fx_addsy) | |
1365 | /* Fix for bfd_install_relocation() */ | |
1366 | - (S_GET_VALUE (fixp->fx_addsy) | |
1367 | + S_GET_SEGMENT (fixp->fx_addsy)->vma); | |
1368 | } | |
33f0727f NC |
1369 | else if (fixp->fx_pcrel) |
1370 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
1371 | else |
1372 | reloc->addend = 0; | |
1373 | #else | |
1374 | if (!fixp->fx_pcrel) | |
1375 | reloc->addend = fixp->fx_addnumber; | |
1376 | else | |
1377 | reloc->addend = (section->vma | |
552c607f | 1378 | + fixp->fx_pcrel_adjust |
252b5132 RH |
1379 | + fixp->fx_addnumber |
1380 | + md_pcrel_from (fixp)); | |
1381 | #endif | |
1382 | ||
1383 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
9c2799c2 | 1384 | gas_assert (reloc->howto != 0); |
252b5132 RH |
1385 | |
1386 | return reloc; | |
1387 | } | |
1388 | ||
252b5132 RH |
1389 | /* Handle of the OPCODE hash table. NULL means any use before |
1390 | m68k_ip_begin() will crash. */ | |
1391 | static struct hash_control *op_hash; | |
1392 | \f | |
1393 | /* Assemble an m68k instruction. */ | |
1394 | ||
1395 | static void | |
31302357 | 1396 | m68k_ip (char *instring) |
252b5132 | 1397 | { |
ed9e98c2 AM |
1398 | char *p; |
1399 | struct m68k_op *opP; | |
1400 | const struct m68k_incant *opcode; | |
1401 | const char *s; | |
1402 | int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
252b5132 RH |
1403 | char *pdot, *pdotmove; |
1404 | enum m68k_size siz1, siz2; | |
1405 | char c; | |
1406 | int losing; | |
1407 | int opsfound; | |
03b13e59 | 1408 | struct m68k_op operands_backup[6]; |
252b5132 RH |
1409 | LITTLENUM_TYPE words[6]; |
1410 | LITTLENUM_TYPE *wordp; | |
1411 | unsigned long ok_arch = 0; | |
1412 | ||
1413 | if (*instring == ' ') | |
36759679 | 1414 | instring++; /* Skip leading whitespace. */ |
252b5132 RH |
1415 | |
1416 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
92774660 | 1417 | or exactly 1 space. */ |
252b5132 RH |
1418 | pdot = 0; |
1419 | for (p = instring; *p != '\0'; p++) | |
1420 | { | |
1421 | if (*p == ' ') | |
1422 | break; | |
1423 | if (*p == '.') | |
1424 | pdot = p; | |
1425 | } | |
1426 | ||
1427 | if (p == instring) | |
1428 | { | |
1429 | the_ins.error = _("No operator"); | |
1430 | return; | |
1431 | } | |
1432 | ||
1433 | /* p now points to the end of the opcode name, probably whitespace. | |
1434 | Make sure the name is null terminated by clobbering the | |
1435 | whitespace, look it up in the hash table, then fix it back. | |
1436 | Remove a dot, first, since the opcode tables have none. */ | |
1437 | if (pdot != NULL) | |
1438 | { | |
1439 | for (pdotmove = pdot; pdotmove < p; pdotmove++) | |
1440 | *pdotmove = pdotmove[1]; | |
1441 | p--; | |
1442 | } | |
1443 | ||
1444 | c = *p; | |
1445 | *p = '\0'; | |
1446 | opcode = (const struct m68k_incant *) hash_find (op_hash, instring); | |
1447 | *p = c; | |
1448 | ||
1449 | if (pdot != NULL) | |
1450 | { | |
1451 | for (pdotmove = p; pdotmove > pdot; pdotmove--) | |
1452 | *pdotmove = pdotmove[-1]; | |
1453 | *pdot = '.'; | |
1454 | ++p; | |
1455 | } | |
1456 | ||
1457 | if (opcode == NULL) | |
1458 | { | |
1459 | the_ins.error = _("Unknown operator"); | |
1460 | return; | |
1461 | } | |
1462 | ||
36759679 | 1463 | /* Found a legitimate opcode, start matching operands. */ |
252b5132 RH |
1464 | while (*p == ' ') |
1465 | ++p; | |
1466 | ||
1467 | if (opcode->m_operands == 0) | |
1468 | { | |
1469 | char *old = input_line_pointer; | |
1470 | *old = '\n'; | |
1471 | input_line_pointer = p; | |
36759679 | 1472 | /* Ahh - it's a motorola style psuedo op. */ |
252b5132 RH |
1473 | mote_pseudo_table[opcode->m_opnum].poc_handler |
1474 | (mote_pseudo_table[opcode->m_opnum].poc_val); | |
1475 | input_line_pointer = old; | |
1476 | *old = 0; | |
1477 | ||
1478 | return; | |
1479 | } | |
1480 | ||
1481 | if (flag_mri && opcode->m_opnum == 0) | |
1482 | { | |
1483 | /* In MRI mode, random garbage is allowed after an instruction | |
1484 | which accepts no operands. */ | |
1485 | the_ins.args = opcode->m_operands; | |
1486 | the_ins.numargs = opcode->m_opnum; | |
1487 | the_ins.numo = opcode->m_codenum; | |
1488 | the_ins.opcode[0] = getone (opcode); | |
1489 | the_ins.opcode[1] = gettwo (opcode); | |
1490 | return; | |
1491 | } | |
1492 | ||
1493 | for (opP = &the_ins.operands[0]; *p; opP++) | |
1494 | { | |
1495 | p = crack_operand (p, opP); | |
1496 | ||
1497 | if (opP->error) | |
1498 | { | |
1499 | the_ins.error = opP->error; | |
1500 | return; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | opsfound = opP - &the_ins.operands[0]; | |
1505 | ||
1506 | /* This ugly hack is to support the floating pt opcodes in their | |
1507 | standard form. Essentially, we fake a first enty of type COP#1 */ | |
1508 | if (opcode->m_operands[0] == 'I') | |
1509 | { | |
1510 | int n; | |
1511 | ||
1512 | for (n = opsfound; n > 0; --n) | |
1513 | the_ins.operands[n] = the_ins.operands[n - 1]; | |
1514 | ||
31302357 | 1515 | memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); |
252b5132 RH |
1516 | the_ins.operands[0].mode = CONTROL; |
1517 | the_ins.operands[0].reg = m68k_float_copnum; | |
1518 | opsfound++; | |
1519 | } | |
1520 | ||
36759679 | 1521 | /* We've got the operands. Find an opcode that'll accept them. */ |
252b5132 RH |
1522 | for (losing = 0;;) |
1523 | { | |
1524 | /* If we didn't get the right number of ops, or we have no | |
92774660 | 1525 | common model with this pattern then reject this pattern. */ |
252b5132 RH |
1526 | |
1527 | ok_arch |= opcode->m_arch; | |
1528 | if (opsfound != opcode->m_opnum | |
1529 | || ((opcode->m_arch & current_architecture) == 0)) | |
1530 | ++losing; | |
1531 | else | |
1532 | { | |
03b13e59 NC |
1533 | int i; |
1534 | ||
1535 | /* Make a copy of the operands of this insn so that | |
1536 | we can modify them safely, should we want to. */ | |
9c2799c2 | 1537 | gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); |
03b13e59 NC |
1538 | for (i = 0; i < opsfound; i++) |
1539 | operands_backup[i] = the_ins.operands[i]; | |
1540 | ||
1541 | for (s = opcode->m_operands, opP = &operands_backup[0]; | |
252b5132 RH |
1542 | *s && !losing; |
1543 | s += 2, opP++) | |
1544 | { | |
1545 | /* Warning: this switch is huge! */ | |
1546 | /* I've tried to organize the cases into this order: | |
1547 | non-alpha first, then alpha by letter. Lower-case | |
1548 | goes directly before uppercase counterpart. */ | |
1549 | /* Code with multiple case ...: gets sorted by the lowest | |
1550 | case ... it belongs to. I hope this makes sense. */ | |
1551 | switch (*s) | |
1552 | { | |
1553 | case '!': | |
1554 | switch (opP->mode) | |
1555 | { | |
1556 | case IMMED: | |
1557 | case DREG: | |
1558 | case AREG: | |
1559 | case FPREG: | |
1560 | case CONTROL: | |
1561 | case AINC: | |
1562 | case ADEC: | |
1563 | case REGLST: | |
1564 | losing++; | |
1565 | break; | |
1566 | default: | |
1567 | break; | |
1568 | } | |
1569 | break; | |
1570 | ||
1571 | case '<': | |
1572 | switch (opP->mode) | |
1573 | { | |
1574 | case DREG: | |
1575 | case AREG: | |
1576 | case FPREG: | |
1577 | case CONTROL: | |
1578 | case IMMED: | |
1579 | case ADEC: | |
1580 | case REGLST: | |
1581 | losing++; | |
1582 | break; | |
1583 | default: | |
1584 | break; | |
1585 | } | |
1586 | break; | |
1587 | ||
1588 | case '>': | |
1589 | switch (opP->mode) | |
1590 | { | |
1591 | case DREG: | |
1592 | case AREG: | |
1593 | case FPREG: | |
1594 | case CONTROL: | |
1595 | case IMMED: | |
1596 | case AINC: | |
1597 | case REGLST: | |
1598 | losing++; | |
1599 | break; | |
1600 | case ABSL: | |
1601 | break; | |
1602 | default: | |
1603 | if (opP->reg == PC | |
1604 | || opP->reg == ZPC) | |
1605 | losing++; | |
1606 | break; | |
1607 | } | |
1608 | break; | |
1609 | ||
1610 | case 'm': | |
1611 | switch (opP->mode) | |
1612 | { | |
1613 | case DREG: | |
1614 | case AREG: | |
1615 | case AINDR: | |
1616 | case AINC: | |
1617 | case ADEC: | |
1618 | break; | |
1619 | default: | |
1620 | losing++; | |
1621 | } | |
8a104df9 | 1622 | break; |
252b5132 RH |
1623 | |
1624 | case 'n': | |
1625 | switch (opP->mode) | |
1626 | { | |
1627 | case DISP: | |
1628 | break; | |
1629 | default: | |
1630 | losing++; | |
1631 | } | |
8a104df9 | 1632 | break; |
252b5132 RH |
1633 | |
1634 | case 'o': | |
1635 | switch (opP->mode) | |
1636 | { | |
1637 | case BASE: | |
1638 | case ABSL: | |
1639 | case IMMED: | |
1640 | break; | |
1641 | default: | |
1642 | losing++; | |
1643 | } | |
8a104df9 | 1644 | break; |
252b5132 RH |
1645 | |
1646 | case 'p': | |
1647 | switch (opP->mode) | |
1648 | { | |
1649 | case DREG: | |
1650 | case AREG: | |
1651 | case AINDR: | |
1652 | case AINC: | |
1653 | case ADEC: | |
1654 | break; | |
1655 | case DISP: | |
1656 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1657 | losing++; |
252b5132 RH |
1658 | break; |
1659 | default: | |
1660 | losing++; | |
1661 | } | |
8a104df9 | 1662 | break; |
252b5132 RH |
1663 | |
1664 | case 'q': | |
1665 | switch (opP->mode) | |
1666 | { | |
1667 | case DREG: | |
1668 | case AINDR: | |
1669 | case AINC: | |
1670 | case ADEC: | |
1671 | break; | |
1672 | case DISP: | |
1673 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1674 | losing++; |
252b5132 RH |
1675 | break; |
1676 | default: | |
1677 | losing++; | |
1678 | break; | |
1679 | } | |
8a104df9 | 1680 | break; |
252b5132 RH |
1681 | |
1682 | case 'v': | |
1683 | switch (opP->mode) | |
1684 | { | |
1685 | case DREG: | |
1686 | case AINDR: | |
1687 | case AINC: | |
1688 | case ADEC: | |
1689 | case ABSL: | |
1690 | break; | |
1691 | case DISP: | |
1692 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1693 | losing++; |
252b5132 RH |
1694 | break; |
1695 | default: | |
1696 | losing++; | |
1697 | break; | |
1698 | } | |
1699 | break; | |
1700 | ||
1701 | case '#': | |
1702 | if (opP->mode != IMMED) | |
1703 | losing++; | |
1704 | else if (s[1] == 'b' | |
1705 | && ! isvar (&opP->disp) | |
1706 | && (opP->disp.exp.X_op != O_constant | |
1707 | || ! isbyte (opP->disp.exp.X_add_number))) | |
1708 | losing++; | |
1709 | else if (s[1] == 'B' | |
1710 | && ! isvar (&opP->disp) | |
1711 | && (opP->disp.exp.X_op != O_constant | |
1712 | || ! issbyte (opP->disp.exp.X_add_number))) | |
1713 | losing++; | |
1714 | else if (s[1] == 'w' | |
1715 | && ! isvar (&opP->disp) | |
1716 | && (opP->disp.exp.X_op != O_constant | |
1717 | || ! isword (opP->disp.exp.X_add_number))) | |
1718 | losing++; | |
1719 | else if (s[1] == 'W' | |
1720 | && ! isvar (&opP->disp) | |
1721 | && (opP->disp.exp.X_op != O_constant | |
1722 | || ! issword (opP->disp.exp.X_add_number))) | |
1723 | losing++; | |
1724 | break; | |
1725 | ||
1726 | case '^': | |
1727 | case 'T': | |
1728 | if (opP->mode != IMMED) | |
1729 | losing++; | |
1730 | break; | |
1731 | ||
1732 | case '$': | |
1733 | if (opP->mode == AREG | |
1734 | || opP->mode == CONTROL | |
1735 | || opP->mode == FPREG | |
1736 | || opP->mode == IMMED | |
1737 | || opP->mode == REGLST | |
1738 | || (opP->mode != ABSL | |
1739 | && (opP->reg == PC | |
1740 | || opP->reg == ZPC))) | |
1741 | losing++; | |
1742 | break; | |
1743 | ||
1744 | case '%': | |
1745 | if (opP->mode == CONTROL | |
1746 | || opP->mode == FPREG | |
1747 | || opP->mode == REGLST | |
1748 | || opP->mode == IMMED | |
1749 | || (opP->mode != ABSL | |
1750 | && (opP->reg == PC | |
1751 | || opP->reg == ZPC))) | |
1752 | losing++; | |
1753 | break; | |
1754 | ||
1755 | case '&': | |
1756 | switch (opP->mode) | |
1757 | { | |
1758 | case DREG: | |
1759 | case AREG: | |
1760 | case FPREG: | |
1761 | case CONTROL: | |
1762 | case IMMED: | |
1763 | case AINC: | |
1764 | case ADEC: | |
1765 | case REGLST: | |
1766 | losing++; | |
1767 | break; | |
1768 | case ABSL: | |
1769 | break; | |
1770 | default: | |
1771 | if (opP->reg == PC | |
1772 | || opP->reg == ZPC) | |
1773 | losing++; | |
1774 | break; | |
1775 | } | |
1776 | break; | |
1777 | ||
1778 | case '*': | |
1779 | if (opP->mode == CONTROL | |
1780 | || opP->mode == FPREG | |
1781 | || opP->mode == REGLST) | |
1782 | losing++; | |
1783 | break; | |
1784 | ||
1785 | case '+': | |
1786 | if (opP->mode != AINC) | |
1787 | losing++; | |
1788 | break; | |
1789 | ||
1790 | case '-': | |
1791 | if (opP->mode != ADEC) | |
1792 | losing++; | |
1793 | break; | |
1794 | ||
1795 | case '/': | |
1796 | switch (opP->mode) | |
1797 | { | |
1798 | case AREG: | |
1799 | case CONTROL: | |
1800 | case FPREG: | |
1801 | case AINC: | |
1802 | case ADEC: | |
1803 | case IMMED: | |
1804 | case REGLST: | |
1805 | losing++; | |
1806 | break; | |
1807 | default: | |
1808 | break; | |
1809 | } | |
1810 | break; | |
1811 | ||
1812 | case ';': | |
1813 | switch (opP->mode) | |
1814 | { | |
1815 | case AREG: | |
1816 | case CONTROL: | |
1817 | case FPREG: | |
1818 | case REGLST: | |
1819 | losing++; | |
1820 | break; | |
1821 | default: | |
1822 | break; | |
1823 | } | |
1824 | break; | |
1825 | ||
1826 | case '?': | |
1827 | switch (opP->mode) | |
1828 | { | |
1829 | case AREG: | |
1830 | case CONTROL: | |
1831 | case FPREG: | |
1832 | case AINC: | |
1833 | case ADEC: | |
1834 | case IMMED: | |
1835 | case REGLST: | |
1836 | losing++; | |
1837 | break; | |
1838 | case ABSL: | |
1839 | break; | |
1840 | default: | |
1841 | if (opP->reg == PC || opP->reg == ZPC) | |
1842 | losing++; | |
1843 | break; | |
1844 | } | |
1845 | break; | |
1846 | ||
1847 | case '@': | |
1848 | switch (opP->mode) | |
1849 | { | |
1850 | case AREG: | |
1851 | case CONTROL: | |
1852 | case FPREG: | |
1853 | case IMMED: | |
1854 | case REGLST: | |
1855 | losing++; | |
1856 | break; | |
1857 | default: | |
1858 | break; | |
1859 | } | |
1860 | break; | |
1861 | ||
1862 | case '~': /* For now! (JF FOO is this right?) */ | |
1863 | switch (opP->mode) | |
1864 | { | |
1865 | case DREG: | |
1866 | case AREG: | |
1867 | case CONTROL: | |
1868 | case FPREG: | |
1869 | case IMMED: | |
1870 | case REGLST: | |
1871 | losing++; | |
1872 | break; | |
1873 | case ABSL: | |
1874 | break; | |
1875 | default: | |
1876 | if (opP->reg == PC | |
1877 | || opP->reg == ZPC) | |
1878 | losing++; | |
1879 | break; | |
1880 | } | |
1881 | break; | |
1882 | ||
1883 | case '3': | |
1884 | if (opP->mode != CONTROL | |
1885 | || (opP->reg != TT0 && opP->reg != TT1)) | |
1886 | losing++; | |
1887 | break; | |
1888 | ||
1889 | case 'A': | |
1890 | if (opP->mode != AREG) | |
1891 | losing++; | |
1892 | break; | |
1893 | ||
1894 | case 'a': | |
1895 | if (opP->mode != AINDR) | |
1896 | ++losing; | |
1897 | break; | |
1898 | ||
fd99574b NC |
1899 | case '4': |
1900 | if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC | |
1901 | && (opP->mode != DISP | |
1902 | || opP->reg < ADDR0 | |
1903 | || opP->reg > ADDR7)) | |
1904 | ++losing; | |
1905 | break; | |
1906 | ||
252b5132 RH |
1907 | case 'B': /* FOO */ |
1908 | if (opP->mode != ABSL | |
1909 | || (flag_long_jumps | |
1910 | && strncmp (instring, "jbsr", 4) == 0)) | |
1911 | losing++; | |
1912 | break; | |
1913 | ||
3e602632 NC |
1914 | case 'b': |
1915 | switch (opP->mode) | |
1916 | { | |
1917 | case IMMED: | |
1918 | case ABSL: | |
1919 | case AREG: | |
1920 | case FPREG: | |
1921 | case CONTROL: | |
1922 | case POST: | |
1923 | case PRE: | |
1924 | case REGLST: | |
1925 | losing++; | |
1926 | break; | |
1927 | default: | |
1928 | break; | |
1929 | } | |
1930 | break; | |
1931 | ||
252b5132 RH |
1932 | case 'C': |
1933 | if (opP->mode != CONTROL || opP->reg != CCR) | |
1934 | losing++; | |
1935 | break; | |
1936 | ||
1937 | case 'd': | |
1938 | if (opP->mode != DISP | |
1939 | || opP->reg < ADDR0 | |
1940 | || opP->reg > ADDR7) | |
1941 | losing++; | |
1942 | break; | |
1943 | ||
1944 | case 'D': | |
1945 | if (opP->mode != DREG) | |
1946 | losing++; | |
1947 | break; | |
1948 | ||
6da466c7 ILT |
1949 | case 'E': |
1950 | if (opP->reg != ACC) | |
1951 | losing++; | |
1952 | break; | |
1953 | ||
fd99574b NC |
1954 | case 'e': |
1955 | if (opP->reg != ACC && opP->reg != ACC1 | |
1956 | && opP->reg != ACC2 && opP->reg != ACC3) | |
1957 | losing++; | |
1958 | break; | |
1959 | ||
252b5132 RH |
1960 | case 'F': |
1961 | if (opP->mode != FPREG) | |
1962 | losing++; | |
1963 | break; | |
1964 | ||
6da466c7 ILT |
1965 | case 'G': |
1966 | if (opP->reg != MACSR) | |
1967 | losing++; | |
1968 | break; | |
1969 | ||
fd99574b NC |
1970 | case 'g': |
1971 | if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) | |
1972 | losing++; | |
1973 | break; | |
1974 | ||
6da466c7 ILT |
1975 | case 'H': |
1976 | if (opP->reg != MASK) | |
1977 | losing++; | |
1978 | break; | |
1979 | ||
252b5132 RH |
1980 | case 'I': |
1981 | if (opP->mode != CONTROL | |
1982 | || opP->reg < COP0 | |
1983 | || opP->reg > COP7) | |
1984 | losing++; | |
1985 | break; | |
1986 | ||
fd99574b NC |
1987 | case 'i': |
1988 | if (opP->mode != LSH && opP->mode != RSH) | |
1989 | losing++; | |
1990 | break; | |
1991 | ||
252b5132 RH |
1992 | case 'J': |
1993 | if (opP->mode != CONTROL | |
1994 | || opP->reg < USP | |
0b2e31dc NS |
1995 | || opP->reg > last_movec_reg |
1996 | || !control_regs) | |
252b5132 RH |
1997 | losing++; |
1998 | else | |
1999 | { | |
2000 | const enum m68k_register *rp; | |
3739860c | 2001 | |
252b5132 | 2002 | for (rp = control_regs; *rp; rp++) |
78336706 NS |
2003 | { |
2004 | if (*rp == opP->reg) | |
2005 | break; | |
2006 | /* In most CPUs RAMBAR refers to control reg | |
2007 | c05 (RAMBAR1), but a few CPUs have it | |
2008 | refer to c04 (RAMBAR0). */ | |
2009 | else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) | |
2010 | { | |
2011 | opP->reg = RAMBAR_ALT; | |
2012 | break; | |
2013 | } | |
2014 | } | |
252b5132 RH |
2015 | if (*rp == 0) |
2016 | losing++; | |
2017 | } | |
2018 | break; | |
2019 | ||
2020 | case 'k': | |
2021 | if (opP->mode != IMMED) | |
2022 | losing++; | |
2023 | break; | |
2024 | ||
2025 | case 'l': | |
2026 | case 'L': | |
2027 | if (opP->mode == DREG | |
2028 | || opP->mode == AREG | |
2029 | || opP->mode == FPREG) | |
2030 | { | |
2031 | if (s[1] == '8') | |
2032 | losing++; | |
2033 | else | |
2034 | { | |
2035 | switch (opP->mode) | |
2036 | { | |
2037 | case DREG: | |
2038 | opP->mask = 1 << (opP->reg - DATA0); | |
2039 | break; | |
2040 | case AREG: | |
2041 | opP->mask = 1 << (opP->reg - ADDR0 + 8); | |
2042 | break; | |
2043 | case FPREG: | |
2044 | opP->mask = 1 << (opP->reg - FP0 + 16); | |
2045 | break; | |
2046 | default: | |
2047 | abort (); | |
2048 | } | |
2049 | opP->mode = REGLST; | |
2050 | } | |
2051 | } | |
2052 | else if (opP->mode == CONTROL) | |
2053 | { | |
2054 | if (s[1] != '8') | |
2055 | losing++; | |
2056 | else | |
2057 | { | |
2058 | switch (opP->reg) | |
2059 | { | |
2060 | case FPI: | |
2061 | opP->mask = 1 << 24; | |
2062 | break; | |
2063 | case FPS: | |
2064 | opP->mask = 1 << 25; | |
2065 | break; | |
2066 | case FPC: | |
2067 | opP->mask = 1 << 26; | |
2068 | break; | |
2069 | default: | |
2070 | losing++; | |
2071 | break; | |
2072 | } | |
2073 | opP->mode = REGLST; | |
2074 | } | |
2075 | } | |
2076 | else if (opP->mode != REGLST) | |
2077 | losing++; | |
2078 | else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) | |
2079 | losing++; | |
2080 | else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) | |
2081 | losing++; | |
2082 | break; | |
2083 | ||
2084 | case 'M': | |
2085 | if (opP->mode != IMMED) | |
2086 | losing++; | |
2087 | else if (opP->disp.exp.X_op != O_constant | |
2088 | || ! issbyte (opP->disp.exp.X_add_number)) | |
2089 | losing++; | |
2090 | else if (! m68k_quick | |
2091 | && instring[3] != 'q' | |
2092 | && instring[4] != 'q') | |
2093 | losing++; | |
2094 | break; | |
2095 | ||
2096 | case 'O': | |
2097 | if (opP->mode != DREG | |
2098 | && opP->mode != IMMED | |
2099 | && opP->mode != ABSL) | |
2100 | losing++; | |
2101 | break; | |
2102 | ||
2103 | case 'Q': | |
2104 | if (opP->mode != IMMED) | |
2105 | losing++; | |
2106 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 | 2107 | || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) |
252b5132 RH |
2108 | losing++; |
2109 | else if (! m68k_quick | |
2110 | && (strncmp (instring, "add", 3) == 0 | |
2111 | || strncmp (instring, "sub", 3) == 0) | |
2112 | && instring[3] != 'q') | |
2113 | losing++; | |
2114 | break; | |
2115 | ||
2116 | case 'R': | |
2117 | if (opP->mode != DREG && opP->mode != AREG) | |
2118 | losing++; | |
2119 | break; | |
2120 | ||
2121 | case 'r': | |
2122 | if (opP->mode != AINDR | |
2123 | && (opP->mode != BASE | |
2124 | || (opP->reg != 0 | |
2125 | && opP->reg != ZADDR0) | |
2126 | || opP->disp.exp.X_op != O_absent | |
2127 | || ((opP->index.reg < DATA0 | |
2128 | || opP->index.reg > DATA7) | |
2129 | && (opP->index.reg < ADDR0 | |
2130 | || opP->index.reg > ADDR7)) | |
2131 | || opP->index.size != SIZE_UNSPEC | |
2132 | || opP->index.scale != 1)) | |
2133 | losing++; | |
2134 | break; | |
2135 | ||
2136 | case 's': | |
2137 | if (opP->mode != CONTROL | |
2138 | || ! (opP->reg == FPI | |
2139 | || opP->reg == FPS | |
2140 | || opP->reg == FPC)) | |
2141 | losing++; | |
2142 | break; | |
2143 | ||
2144 | case 'S': | |
2145 | if (opP->mode != CONTROL || opP->reg != SR) | |
2146 | losing++; | |
2147 | break; | |
2148 | ||
2149 | case 't': | |
2150 | if (opP->mode != IMMED) | |
2151 | losing++; | |
2152 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 | 2153 | || TRUNC (opP->disp.exp.X_add_number) > 7) |
252b5132 RH |
2154 | losing++; |
2155 | break; | |
2156 | ||
2157 | case 'U': | |
2158 | if (opP->mode != CONTROL || opP->reg != USP) | |
2159 | losing++; | |
2160 | break; | |
2161 | ||
3e602632 NC |
2162 | case 'x': |
2163 | if (opP->mode != IMMED) | |
2164 | losing++; | |
2165 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 AM |
2166 | || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff |
2167 | && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) | |
3e602632 NC |
2168 | losing++; |
2169 | break; | |
2170 | ||
afa2158f NS |
2171 | case 'j': |
2172 | if (opP->mode != IMMED) | |
2173 | losing++; | |
2174 | else if (opP->disp.exp.X_op != O_constant | |
2175 | || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) | |
2176 | losing++; | |
2177 | break; | |
2178 | ||
2179 | case 'K': | |
2180 | if (opP->mode != IMMED) | |
2181 | losing++; | |
2182 | else if (opP->disp.exp.X_op != O_constant | |
2183 | || TRUNC (opP->disp.exp.X_add_number) > 511) | |
2184 | losing++; | |
2185 | break; | |
2186 | ||
252b5132 RH |
2187 | /* JF these are out of order. We could put them |
2188 | in order if we were willing to put up with | |
2189 | bunches of #ifdef m68851s in the code. | |
2190 | ||
2191 | Don't forget that you need these operands | |
2192 | to use 68030 MMU instructions. */ | |
2193 | #ifndef NO_68851 | |
36759679 | 2194 | /* Memory addressing mode used by pflushr. */ |
252b5132 RH |
2195 | case '|': |
2196 | if (opP->mode == CONTROL | |
2197 | || opP->mode == FPREG | |
2198 | || opP->mode == DREG | |
2199 | || opP->mode == AREG | |
2200 | || opP->mode == REGLST) | |
2201 | losing++; | |
2202 | /* We should accept immediate operands, but they | |
2203 | supposedly have to be quad word, and we don't | |
2204 | handle that. I would like to see what a Motorola | |
2205 | assembler does before doing something here. */ | |
2206 | if (opP->mode == IMMED) | |
2207 | losing++; | |
2208 | break; | |
2209 | ||
2210 | case 'f': | |
2211 | if (opP->mode != CONTROL | |
2212 | || (opP->reg != SFC && opP->reg != DFC)) | |
2213 | losing++; | |
2214 | break; | |
2215 | ||
2216 | case '0': | |
2217 | if (opP->mode != CONTROL || opP->reg != TC) | |
2218 | losing++; | |
2219 | break; | |
2220 | ||
2221 | case '1': | |
2222 | if (opP->mode != CONTROL || opP->reg != AC) | |
2223 | losing++; | |
2224 | break; | |
2225 | ||
2226 | case '2': | |
2227 | if (opP->mode != CONTROL | |
2228 | || (opP->reg != CAL | |
2229 | && opP->reg != VAL | |
2230 | && opP->reg != SCC)) | |
2231 | losing++; | |
2232 | break; | |
2233 | ||
2234 | case 'V': | |
2235 | if (opP->mode != CONTROL | |
2236 | || opP->reg != VAL) | |
2237 | losing++; | |
2238 | break; | |
2239 | ||
2240 | case 'W': | |
2241 | if (opP->mode != CONTROL | |
2242 | || (opP->reg != DRP | |
2243 | && opP->reg != SRP | |
2244 | && opP->reg != CRP)) | |
2245 | losing++; | |
2246 | break; | |
2247 | ||
3e602632 NC |
2248 | case 'w': |
2249 | switch (opP->mode) | |
2250 | { | |
2251 | case IMMED: | |
2252 | case ABSL: | |
2253 | case AREG: | |
2254 | case DREG: | |
2255 | case FPREG: | |
2256 | case CONTROL: | |
2257 | case POST: | |
2258 | case PRE: | |
2259 | case REGLST: | |
2260 | losing++; | |
2261 | break; | |
2262 | default: | |
2263 | break; | |
2264 | } | |
2265 | break; | |
2266 | ||
252b5132 RH |
2267 | case 'X': |
2268 | if (opP->mode != CONTROL | |
2269 | || (!(opP->reg >= BAD && opP->reg <= BAD + 7) | |
2270 | && !(opP->reg >= BAC && opP->reg <= BAC + 7))) | |
2271 | losing++; | |
2272 | break; | |
2273 | ||
2274 | case 'Y': | |
2275 | if (opP->mode != CONTROL || opP->reg != PSR) | |
2276 | losing++; | |
2277 | break; | |
2278 | ||
2279 | case 'Z': | |
2280 | if (opP->mode != CONTROL || opP->reg != PCSR) | |
2281 | losing++; | |
2282 | break; | |
2283 | #endif | |
2284 | case 'c': | |
2285 | if (opP->mode != CONTROL | |
2286 | || (opP->reg != NC | |
2287 | && opP->reg != IC | |
2288 | && opP->reg != DC | |
2289 | && opP->reg != BC)) | |
36759679 | 2290 | losing++; |
252b5132 RH |
2291 | break; |
2292 | ||
2293 | case '_': | |
2294 | if (opP->mode != ABSL) | |
2295 | ++losing; | |
2296 | break; | |
2297 | ||
6da466c7 ILT |
2298 | case 'u': |
2299 | if (opP->reg < DATA0L || opP->reg > ADDR7U) | |
2300 | losing++; | |
2301 | /* FIXME: kludge instead of fixing parser: | |
2302 | upper/lower registers are *not* CONTROL | |
92774660 | 2303 | registers, but ordinary ones. */ |
6da466c7 ILT |
2304 | if ((opP->reg >= DATA0L && opP->reg <= DATA7L) |
2305 | || (opP->reg >= DATA0U && opP->reg <= DATA7U)) | |
2306 | opP->mode = DREG; | |
2307 | else | |
2308 | opP->mode = AREG; | |
2309 | break; | |
2310 | ||
3e602632 NC |
2311 | case 'y': |
2312 | if (!(opP->mode == AINDR | |
31302357 AS |
2313 | || (opP->mode == DISP |
2314 | && !(opP->reg == PC || opP->reg == ZPC)))) | |
3e602632 NC |
2315 | losing++; |
2316 | break; | |
2317 | ||
2318 | case 'z': | |
2319 | if (!(opP->mode == AINDR || opP->mode == DISP)) | |
2320 | losing++; | |
2321 | break; | |
2322 | ||
252b5132 RH |
2323 | default: |
2324 | abort (); | |
36759679 | 2325 | } |
252b5132 RH |
2326 | |
2327 | if (losing) | |
2328 | break; | |
36759679 | 2329 | } |
03b13e59 NC |
2330 | |
2331 | /* Since we have found the correct instruction, copy | |
2332 | in the modifications that we may have made. */ | |
2333 | if (!losing) | |
2334 | for (i = 0; i < opsfound; i++) | |
2335 | the_ins.operands[i] = operands_backup[i]; | |
36759679 | 2336 | } |
252b5132 RH |
2337 | |
2338 | if (!losing) | |
36759679 | 2339 | break; |
252b5132 RH |
2340 | |
2341 | opcode = opcode->m_next; | |
2342 | ||
2343 | if (!opcode) | |
2344 | { | |
2345 | if (ok_arch | |
2346 | && !(ok_arch & current_architecture)) | |
2347 | { | |
6d89cc8f NS |
2348 | const struct m68k_cpu *cpu; |
2349 | int any = 0; | |
2350 | size_t space = 400; | |
2351 | char *buf = xmalloc (space + 1); | |
2352 | size_t len; | |
2353 | int paren = 1; | |
2354 | ||
2355 | the_ins.error = buf; | |
2356 | /* Make sure there's a NUL at the end of the buffer -- strncpy | |
b2f58c0c | 2357 | won't write one when it runs out of buffer. */ |
6d89cc8f NS |
2358 | buf[space] = 0; |
2359 | #define APPEND(STRING) \ | |
2360 | (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) | |
2361 | ||
2362 | APPEND (_("invalid instruction for this architecture; needs ")); | |
252b5132 RH |
2363 | switch (ok_arch) |
2364 | { | |
6b6e92f4 | 2365 | case mcfisa_a: |
b2f58c0c | 2366 | APPEND ("ColdFire ISA_A"); |
6b6e92f4 NC |
2367 | break; |
2368 | case mcfhwdiv: | |
b2f58c0c NC |
2369 | APPEND ("ColdFire "); |
2370 | APPEND (_("hardware divide")); | |
6b6e92f4 NC |
2371 | break; |
2372 | case mcfisa_aa: | |
b2f58c0c | 2373 | APPEND ("ColdFire ISA_A+"); |
6b6e92f4 NC |
2374 | break; |
2375 | case mcfisa_b: | |
b2f58c0c | 2376 | APPEND ("ColdFire ISA_B"); |
6b6e92f4 | 2377 | break; |
8d100c32 | 2378 | case mcfisa_c: |
b2f58c0c | 2379 | APPEND ("ColdFire ISA_C"); |
8d100c32 | 2380 | break; |
3e602632 | 2381 | case cfloat: |
b2f58c0c | 2382 | APPEND ("ColdFire fpu"); |
3e602632 | 2383 | break; |
252b5132 | 2384 | case mfloat: |
b2f58c0c | 2385 | APPEND ("M68K fpu"); |
252b5132 RH |
2386 | break; |
2387 | case mmmu: | |
b2f58c0c | 2388 | APPEND ("M68K mmu"); |
252b5132 RH |
2389 | break; |
2390 | case m68020up: | |
b2f58c0c NC |
2391 | APPEND ("68020 "); |
2392 | APPEND (_("or higher")); | |
252b5132 RH |
2393 | break; |
2394 | case m68000up: | |
b2f58c0c NC |
2395 | APPEND ("68000 "); |
2396 | APPEND (_("or higher")); | |
252b5132 RH |
2397 | break; |
2398 | case m68010up: | |
b2f58c0c NC |
2399 | APPEND ("68010 "); |
2400 | APPEND (_("or higher")); | |
252b5132 RH |
2401 | break; |
2402 | default: | |
6d89cc8f NS |
2403 | paren = 0; |
2404 | } | |
2405 | if (paren) | |
2406 | APPEND (" ("); | |
6b6e92f4 | 2407 | |
6d89cc8f NS |
2408 | for (cpu = m68k_cpus; cpu->name; cpu++) |
2409 | if (!cpu->alias && (cpu->arch & ok_arch)) | |
2410 | { | |
2411 | const struct m68k_cpu *alias; | |
869ddf2a | 2412 | int seen_master = 0; |
3739860c | 2413 | |
6d89cc8f NS |
2414 | if (any) |
2415 | APPEND (", "); | |
2416 | any = 0; | |
2417 | APPEND (cpu->name); | |
869ddf2a NS |
2418 | for (alias = cpu; alias != m68k_cpus; alias--) |
2419 | if (alias[-1].alias >= 0) | |
2420 | break; | |
2421 | for (; !seen_master || alias->alias > 0; alias++) | |
6d89cc8f | 2422 | { |
869ddf2a NS |
2423 | if (!alias->alias) |
2424 | seen_master = 1; | |
2425 | else | |
2426 | { | |
2427 | if (any) | |
2428 | APPEND (", "); | |
2429 | else | |
2430 | APPEND (" ["); | |
2431 | APPEND (alias->name); | |
2432 | any = 1; | |
2433 | } | |
6d89cc8f | 2434 | } |
869ddf2a NS |
2435 | if (any) |
2436 | APPEND ("]"); | |
6d89cc8f | 2437 | any = 1; |
252b5132 | 2438 | } |
6d89cc8f NS |
2439 | if (paren) |
2440 | APPEND (")"); | |
2441 | #undef APPEND | |
2442 | if (!space) | |
2443 | { | |
b2f58c0c | 2444 | /* We ran out of space, so replace the end of the list |
6d89cc8f NS |
2445 | with ellipsis. */ |
2446 | buf -= 4; | |
2447 | while (*buf != ' ') | |
2448 | buf--; | |
2449 | strcpy (buf, " ..."); | |
252b5132 | 2450 | } |
252b5132 RH |
2451 | } |
2452 | else | |
2453 | the_ins.error = _("operands mismatch"); | |
2454 | return; | |
36759679 | 2455 | } |
252b5132 RH |
2456 | |
2457 | losing = 0; | |
2458 | } | |
2459 | ||
36759679 | 2460 | /* Now assemble it. */ |
252b5132 RH |
2461 | the_ins.args = opcode->m_operands; |
2462 | the_ins.numargs = opcode->m_opnum; | |
2463 | the_ins.numo = opcode->m_codenum; | |
2464 | the_ins.opcode[0] = getone (opcode); | |
2465 | the_ins.opcode[1] = gettwo (opcode); | |
2466 | ||
2467 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) | |
2468 | { | |
9a2e615a | 2469 | int have_disp = 0; |
cac27205 | 2470 | int use_pl = 0; |
3739860c | 2471 | |
252b5132 | 2472 | /* This switch is a doozy. |
31302357 | 2473 | Watch the first step; its a big one! */ |
252b5132 RH |
2474 | switch (s[0]) |
2475 | { | |
2476 | ||
2477 | case '*': | |
2478 | case '~': | |
2479 | case '%': | |
2480 | case ';': | |
2481 | case '@': | |
2482 | case '!': | |
2483 | case '&': | |
2484 | case '$': | |
2485 | case '?': | |
2486 | case '/': | |
2487 | case '<': | |
2488 | case '>': | |
3e602632 | 2489 | case 'b': |
252b5132 RH |
2490 | case 'm': |
2491 | case 'n': | |
2492 | case 'o': | |
2493 | case 'p': | |
2494 | case 'q': | |
2495 | case 'v': | |
3e602632 NC |
2496 | case 'w': |
2497 | case 'y': | |
2498 | case 'z': | |
fd99574b | 2499 | case '4': |
252b5132 RH |
2500 | #ifndef NO_68851 |
2501 | case '|': | |
2502 | #endif | |
2503 | switch (opP->mode) | |
2504 | { | |
2505 | case IMMED: | |
2506 | tmpreg = 0x3c; /* 7.4 */ | |
2507 | if (strchr ("bwl", s[1])) | |
3e602632 | 2508 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2509 | else |
2510 | nextword = get_num (&opP->disp, 0); | |
2511 | if (isvar (&opP->disp)) | |
2512 | add_fix (s[1], &opP->disp, 0, 0); | |
2513 | switch (s[1]) | |
2514 | { | |
2515 | case 'b': | |
2516 | if (!isbyte (nextword)) | |
2517 | opP->error = _("operand out of range"); | |
2518 | addword (nextword); | |
2519 | baseo = 0; | |
2520 | break; | |
2521 | case 'w': | |
2522 | if (!isword (nextword)) | |
2523 | opP->error = _("operand out of range"); | |
2524 | addword (nextword); | |
2525 | baseo = 0; | |
2526 | break; | |
2527 | case 'W': | |
2528 | if (!issword (nextword)) | |
2529 | opP->error = _("operand out of range"); | |
2530 | addword (nextword); | |
2531 | baseo = 0; | |
2532 | break; | |
2533 | case 'l': | |
2534 | addword (nextword >> 16); | |
2535 | addword (nextword); | |
2536 | baseo = 0; | |
2537 | break; | |
2538 | ||
2539 | case 'f': | |
2540 | baseo = 2; | |
2541 | outro = 8; | |
2542 | break; | |
2543 | case 'F': | |
2544 | baseo = 4; | |
2545 | outro = 11; | |
2546 | break; | |
2547 | case 'x': | |
2548 | baseo = 6; | |
2549 | outro = 15; | |
2550 | break; | |
2551 | case 'p': | |
2552 | baseo = 6; | |
2553 | outro = -1; | |
2554 | break; | |
2555 | default: | |
2556 | abort (); | |
2557 | } | |
2558 | if (!baseo) | |
2559 | break; | |
2560 | ||
36759679 | 2561 | /* We gotta put out some float. */ |
252b5132 RH |
2562 | if (op (&opP->disp) != O_big) |
2563 | { | |
2564 | valueT val; | |
2565 | int gencnt; | |
2566 | ||
2567 | /* Can other cases happen here? */ | |
2568 | if (op (&opP->disp) != O_constant) | |
2569 | abort (); | |
2570 | ||
2571 | val = (valueT) offs (&opP->disp); | |
2572 | gencnt = 0; | |
2573 | do | |
2574 | { | |
2575 | generic_bignum[gencnt] = (LITTLENUM_TYPE) val; | |
2576 | val >>= LITTLENUM_NUMBER_OF_BITS; | |
2577 | ++gencnt; | |
2578 | } | |
2579 | while (val != 0); | |
2580 | offs (&opP->disp) = gencnt; | |
2581 | } | |
2582 | if (offs (&opP->disp) > 0) | |
2583 | { | |
2584 | if (offs (&opP->disp) > baseo) | |
2585 | { | |
2586 | as_warn (_("Bignum too big for %c format; truncated"), | |
2587 | s[1]); | |
2588 | offs (&opP->disp) = baseo; | |
2589 | } | |
2590 | baseo -= offs (&opP->disp); | |
2591 | while (baseo--) | |
2592 | addword (0); | |
2593 | for (wordp = generic_bignum + offs (&opP->disp) - 1; | |
2594 | offs (&opP->disp)--; | |
2595 | --wordp) | |
2596 | addword (*wordp); | |
2597 | break; | |
2598 | } | |
2599 | gen_to_words (words, baseo, (long) outro); | |
2600 | for (wordp = words; baseo--; wordp++) | |
2601 | addword (*wordp); | |
2602 | break; | |
2603 | case DREG: | |
2604 | tmpreg = opP->reg - DATA; /* 0.dreg */ | |
2605 | break; | |
2606 | case AREG: | |
2607 | tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ | |
2608 | break; | |
2609 | case AINDR: | |
2610 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2611 | break; | |
2612 | case ADEC: | |
2613 | tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ | |
2614 | break; | |
2615 | case AINC: | |
2616 | tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ | |
2617 | break; | |
2618 | case DISP: | |
2619 | ||
3e602632 | 2620 | nextword = get_num (&opP->disp, 90); |
252b5132 | 2621 | |
580b9172 NC |
2622 | /* Convert mode 5 addressing with a zero offset into |
2623 | mode 2 addressing to reduce the instruction size by a | |
2624 | word. */ | |
2625 | if (! isvar (&opP->disp) | |
2626 | && (nextword == 0) | |
2627 | && (opP->disp.size == SIZE_UNSPEC) | |
2628 | && (opP->reg >= ADDR0) | |
2629 | && (opP->reg <= ADDR7)) | |
2630 | { | |
2631 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2632 | break; | |
2633 | } | |
2634 | ||
252b5132 RH |
2635 | if (opP->reg == PC |
2636 | && ! isvar (&opP->disp) | |
2637 | && m68k_abspcadd) | |
2638 | { | |
2639 | opP->disp.exp.X_op = O_symbol; | |
252b5132 RH |
2640 | opP->disp.exp.X_add_symbol = |
2641 | section_symbol (absolute_section); | |
252b5132 RH |
2642 | } |
2643 | ||
36759679 | 2644 | /* Force into index mode. Hope this works. */ |
252b5132 RH |
2645 | |
2646 | /* We do the first bit for 32-bit displacements, and the | |
2647 | second bit for 16 bit ones. It is possible that we | |
2648 | should make the default be WORD instead of LONG, but | |
2649 | I think that'd break GCC, so we put up with a little | |
2650 | inefficiency for the sake of working output. */ | |
2651 | ||
2652 | if (!issword (nextword) | |
2653 | || (isvar (&opP->disp) | |
2654 | && ((opP->disp.size == SIZE_UNSPEC | |
2655 | && flag_short_refs == 0 | |
2656 | && cpu_of_arch (current_architecture) >= m68020 | |
6da466c7 | 2657 | && ! arch_coldfire_p (current_architecture)) |
252b5132 RH |
2658 | || opP->disp.size == SIZE_LONG))) |
2659 | { | |
2660 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2661 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2662 | opP->error = |
2663 | _("displacement too large for this architecture; needs 68020 or higher"); | |
2664 | if (opP->reg == PC) | |
2665 | tmpreg = 0x3B; /* 7.3 */ | |
2666 | else | |
2667 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2668 | if (isvar (&opP->disp)) | |
2669 | { | |
2670 | if (opP->reg == PC) | |
2671 | { | |
2672 | if (opP->disp.size == SIZE_LONG | |
2673 | #ifdef OBJ_ELF | |
2674 | /* If the displacement needs pic | |
2675 | relocation it cannot be relaxed. */ | |
2676 | || opP->disp.pic_reloc != pic_none | |
2677 | #endif | |
2678 | ) | |
2679 | { | |
2680 | addword (0x0170); | |
2681 | add_fix ('l', &opP->disp, 1, 2); | |
2682 | } | |
2683 | else | |
2684 | { | |
2685 | add_frag (adds (&opP->disp), | |
bd17c2c3 | 2686 | SEXT (offs (&opP->disp)), |
151337e8 | 2687 | TAB (PCREL1632, SZ_UNDEF)); |
252b5132 RH |
2688 | break; |
2689 | } | |
2690 | } | |
2691 | else | |
2692 | { | |
2693 | addword (0x0170); | |
2694 | add_fix ('l', &opP->disp, 0, 0); | |
2695 | } | |
2696 | } | |
2697 | else | |
2698 | addword (0x0170); | |
2699 | addword (nextword >> 16); | |
2700 | } | |
2701 | else | |
2702 | { | |
2703 | if (opP->reg == PC) | |
2704 | tmpreg = 0x3A; /* 7.2 */ | |
2705 | else | |
2706 | tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ | |
2707 | ||
2708 | if (isvar (&opP->disp)) | |
2709 | { | |
2710 | if (opP->reg == PC) | |
2711 | { | |
2712 | add_fix ('w', &opP->disp, 1, 0); | |
2713 | } | |
2714 | else | |
2715 | add_fix ('w', &opP->disp, 0, 0); | |
2716 | } | |
2717 | } | |
2718 | addword (nextword); | |
2719 | break; | |
2720 | ||
2721 | case POST: | |
2722 | case PRE: | |
2723 | case BASE: | |
2724 | nextword = 0; | |
3e602632 | 2725 | baseo = get_num (&opP->disp, 90); |
252b5132 | 2726 | if (opP->mode == POST || opP->mode == PRE) |
3e602632 | 2727 | outro = get_num (&opP->odisp, 90); |
252b5132 RH |
2728 | /* Figure out the `addressing mode'. |
2729 | Also turn on the BASE_DISABLE bit, if needed. */ | |
2730 | if (opP->reg == PC || opP->reg == ZPC) | |
2731 | { | |
2732 | tmpreg = 0x3b; /* 7.3 */ | |
2733 | if (opP->reg == ZPC) | |
2734 | nextword |= 0x80; | |
2735 | } | |
2736 | else if (opP->reg == 0) | |
2737 | { | |
2738 | nextword |= 0x80; | |
2739 | tmpreg = 0x30; /* 6.garbage */ | |
2740 | } | |
2741 | else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) | |
2742 | { | |
2743 | nextword |= 0x80; | |
2744 | tmpreg = 0x30 + opP->reg - ZADDR0; | |
2745 | } | |
2746 | else | |
2747 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2748 | ||
2749 | siz1 = opP->disp.size; | |
2750 | if (opP->mode == POST || opP->mode == PRE) | |
2751 | siz2 = opP->odisp.size; | |
2752 | else | |
2753 | siz2 = SIZE_UNSPEC; | |
2754 | ||
36759679 | 2755 | /* Index register stuff. */ |
252b5132 RH |
2756 | if (opP->index.reg != 0 |
2757 | && opP->index.reg >= DATA | |
2758 | && opP->index.reg <= ADDR7) | |
2759 | { | |
2760 | nextword |= (opP->index.reg - DATA) << 12; | |
2761 | ||
2762 | if (opP->index.size == SIZE_LONG | |
2763 | || (opP->index.size == SIZE_UNSPEC | |
2764 | && m68k_index_width_default == SIZE_LONG)) | |
2765 | nextword |= 0x800; | |
2766 | ||
92774660 | 2767 | if ((opP->index.scale != 1 |
252b5132 | 2768 | && cpu_of_arch (current_architecture) < m68020) |
92774660 | 2769 | || (opP->index.scale == 8 |
3e602632 | 2770 | && (arch_coldfire_p (current_architecture) |
6b6e92f4 | 2771 | && !arch_coldfire_fpu (current_architecture)))) |
252b5132 RH |
2772 | { |
2773 | opP->error = | |
2774 | _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); | |
2775 | } | |
2776 | ||
6da466c7 ILT |
2777 | if (arch_coldfire_p (current_architecture) |
2778 | && opP->index.size == SIZE_WORD) | |
2779 | opP->error = _("invalid index size for coldfire"); | |
2780 | ||
252b5132 RH |
2781 | switch (opP->index.scale) |
2782 | { | |
2783 | case 1: | |
2784 | break; | |
2785 | case 2: | |
2786 | nextword |= 0x200; | |
2787 | break; | |
2788 | case 4: | |
2789 | nextword |= 0x400; | |
2790 | break; | |
2791 | case 8: | |
2792 | nextword |= 0x600; | |
2793 | break; | |
2794 | default: | |
2795 | abort (); | |
2796 | } | |
2797 | /* IF its simple, | |
2798 | GET US OUT OF HERE! */ | |
2799 | ||
2800 | /* Must be INDEX, with an index register. Address | |
2801 | register cannot be ZERO-PC, and either :b was | |
2802 | forced, or we know it will fit. For a 68000 or | |
2803 | 68010, force this mode anyways, because the | |
2804 | larger modes aren't supported. */ | |
2805 | if (opP->mode == BASE | |
2806 | && ((opP->reg >= ADDR0 | |
2807 | && opP->reg <= ADDR7) | |
2808 | || opP->reg == PC)) | |
2809 | { | |
2810 | if (siz1 == SIZE_BYTE | |
2811 | || cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2812 | || arch_coldfire_p (current_architecture) |
252b5132 RH |
2813 | || (siz1 == SIZE_UNSPEC |
2814 | && ! isvar (&opP->disp) | |
2815 | && issbyte (baseo))) | |
2816 | { | |
2817 | nextword += baseo & 0xff; | |
2818 | addword (nextword); | |
2819 | if (isvar (&opP->disp)) | |
2820 | { | |
2821 | /* Do a byte relocation. If it doesn't | |
2822 | fit (possible on m68000) let the | |
2823 | fixup processing complain later. */ | |
2824 | if (opP->reg == PC) | |
2825 | add_fix ('B', &opP->disp, 1, 1); | |
2826 | else | |
2827 | add_fix ('B', &opP->disp, 0, 0); | |
2828 | } | |
2829 | else if (siz1 != SIZE_BYTE) | |
2830 | { | |
2831 | if (siz1 != SIZE_UNSPEC) | |
2832 | as_warn (_("Forcing byte displacement")); | |
2833 | if (! issbyte (baseo)) | |
2834 | opP->error = _("byte displacement out of range"); | |
2835 | } | |
2836 | ||
2837 | break; | |
2838 | } | |
2839 | else if (siz1 == SIZE_UNSPEC | |
2840 | && opP->reg == PC | |
2841 | && isvar (&opP->disp) | |
2842 | && subs (&opP->disp) == NULL | |
2843 | #ifdef OBJ_ELF | |
2844 | /* If the displacement needs pic | |
2845 | relocation it cannot be relaxed. */ | |
2846 | && opP->disp.pic_reloc == pic_none | |
2847 | #endif | |
2848 | ) | |
2849 | { | |
2850 | /* The code in md_convert_frag_1 needs to be | |
2851 | able to adjust nextword. Call frag_grow | |
2852 | to ensure that we have enough space in | |
2853 | the frag obstack to make all the bytes | |
2854 | contiguous. */ | |
2855 | frag_grow (14); | |
8a104df9 KH |
2856 | nextword += baseo & 0xff; |
2857 | addword (nextword); | |
bd17c2c3 AM |
2858 | add_frag (adds (&opP->disp), |
2859 | SEXT (offs (&opP->disp)), | |
8a104df9 | 2860 | TAB (PCINDEX, SZ_UNDEF)); |
252b5132 RH |
2861 | |
2862 | break; | |
8a104df9 | 2863 | } |
252b5132 RH |
2864 | } |
2865 | } | |
2866 | else | |
2867 | { | |
36759679 | 2868 | nextword |= 0x40; /* No index reg. */ |
252b5132 RH |
2869 | if (opP->index.reg >= ZDATA0 |
2870 | && opP->index.reg <= ZDATA7) | |
2871 | nextword |= (opP->index.reg - ZDATA0) << 12; | |
2872 | else if (opP->index.reg >= ZADDR0 | |
2873 | || opP->index.reg <= ZADDR7) | |
2874 | nextword |= (opP->index.reg - ZADDR0 + 8) << 12; | |
2875 | } | |
2876 | ||
2877 | /* It isn't simple. */ | |
2878 | ||
2879 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2880 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2881 | opP->error = |
2882 | _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2883 | ||
2884 | nextword |= 0x100; | |
2885 | /* If the guy specified a width, we assume that it is | |
2886 | wide enough. Maybe it isn't. If so, we lose. */ | |
2887 | switch (siz1) | |
2888 | { | |
2889 | case SIZE_UNSPEC: | |
2890 | if (isvar (&opP->disp) | |
2891 | ? m68k_rel32 | |
2892 | : ! issword (baseo)) | |
2893 | { | |
2894 | siz1 = SIZE_LONG; | |
2895 | nextword |= 0x30; | |
2896 | } | |
2897 | else if (! isvar (&opP->disp) && baseo == 0) | |
2898 | nextword |= 0x10; | |
2899 | else | |
2900 | { | |
2901 | nextword |= 0x20; | |
2902 | siz1 = SIZE_WORD; | |
2903 | } | |
2904 | break; | |
2905 | case SIZE_BYTE: | |
2906 | as_warn (_(":b not permitted; defaulting to :w")); | |
2907 | /* Fall through. */ | |
2908 | case SIZE_WORD: | |
2909 | nextword |= 0x20; | |
2910 | break; | |
2911 | case SIZE_LONG: | |
2912 | nextword |= 0x30; | |
2913 | break; | |
2914 | } | |
2915 | ||
67c1ffbe | 2916 | /* Figure out inner displacement stuff. */ |
252b5132 RH |
2917 | if (opP->mode == POST || opP->mode == PRE) |
2918 | { | |
2919 | if (cpu_of_arch (current_architecture) & cpu32) | |
2920 | opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2921 | switch (siz2) | |
2922 | { | |
2923 | case SIZE_UNSPEC: | |
2924 | if (isvar (&opP->odisp) | |
2925 | ? m68k_rel32 | |
2926 | : ! issword (outro)) | |
2927 | { | |
2928 | siz2 = SIZE_LONG; | |
2929 | nextword |= 0x3; | |
2930 | } | |
2931 | else if (! isvar (&opP->odisp) && outro == 0) | |
2932 | nextword |= 0x1; | |
2933 | else | |
2934 | { | |
2935 | nextword |= 0x2; | |
2936 | siz2 = SIZE_WORD; | |
2937 | } | |
2938 | break; | |
2939 | case 1: | |
2940 | as_warn (_(":b not permitted; defaulting to :w")); | |
2941 | /* Fall through. */ | |
2942 | case 2: | |
2943 | nextword |= 0x2; | |
2944 | break; | |
2945 | case 3: | |
2946 | nextword |= 0x3; | |
2947 | break; | |
2948 | } | |
2949 | if (opP->mode == POST | |
2950 | && (nextword & 0x40) == 0) | |
2951 | nextword |= 0x04; | |
2952 | } | |
2953 | addword (nextword); | |
2954 | ||
2955 | if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) | |
2956 | { | |
2957 | if (opP->reg == PC || opP->reg == ZPC) | |
2958 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); | |
2959 | else | |
2960 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); | |
2961 | } | |
2962 | if (siz1 == SIZE_LONG) | |
2963 | addword (baseo >> 16); | |
2964 | if (siz1 != SIZE_UNSPEC) | |
2965 | addword (baseo); | |
2966 | ||
2967 | if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) | |
2968 | add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); | |
2969 | if (siz2 == SIZE_LONG) | |
2970 | addword (outro >> 16); | |
2971 | if (siz2 != SIZE_UNSPEC) | |
2972 | addword (outro); | |
2973 | ||
2974 | break; | |
2975 | ||
2976 | case ABSL: | |
3e602632 | 2977 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2978 | switch (opP->disp.size) |
2979 | { | |
2980 | default: | |
2981 | abort (); | |
2982 | case SIZE_UNSPEC: | |
2983 | if (!isvar (&opP->disp) && issword (offs (&opP->disp))) | |
2984 | { | |
2985 | tmpreg = 0x38; /* 7.0 */ | |
2986 | addword (nextword); | |
2987 | break; | |
2988 | } | |
252b5132 RH |
2989 | if (isvar (&opP->disp) |
2990 | && !subs (&opP->disp) | |
2991 | && adds (&opP->disp) | |
2992 | #ifdef OBJ_ELF | |
2993 | /* If the displacement needs pic relocation it | |
2994 | cannot be relaxed. */ | |
2995 | && opP->disp.pic_reloc == pic_none | |
2996 | #endif | |
252b5132 RH |
2997 | && !flag_long_jumps |
2998 | && !strchr ("~%&$?", s[0])) | |
2999 | { | |
3000 | tmpreg = 0x3A; /* 7.2 */ | |
3001 | add_frag (adds (&opP->disp), | |
bd17c2c3 | 3002 | SEXT (offs (&opP->disp)), |
151337e8 | 3003 | TAB (ABSTOPCREL, SZ_UNDEF)); |
252b5132 RH |
3004 | break; |
3005 | } | |
36759679 | 3006 | /* Fall through into long. */ |
252b5132 RH |
3007 | case SIZE_LONG: |
3008 | if (isvar (&opP->disp)) | |
3009 | add_fix ('l', &opP->disp, 0, 0); | |
3010 | ||
3011 | tmpreg = 0x39;/* 7.1 mode */ | |
3012 | addword (nextword >> 16); | |
3013 | addword (nextword); | |
3014 | break; | |
3015 | ||
3016 | case SIZE_BYTE: | |
3017 | as_bad (_("unsupported byte value; use a different suffix")); | |
3018 | /* Fall through. */ | |
36759679 NC |
3019 | |
3020 | case SIZE_WORD: | |
252b5132 RH |
3021 | if (isvar (&opP->disp)) |
3022 | add_fix ('w', &opP->disp, 0, 0); | |
3023 | ||
3024 | tmpreg = 0x38;/* 7.0 mode */ | |
3025 | addword (nextword); | |
3026 | break; | |
3027 | } | |
3028 | break; | |
3029 | case CONTROL: | |
3030 | case FPREG: | |
3031 | default: | |
3032 | as_bad (_("unknown/incorrect operand")); | |
bc805888 | 3033 | /* abort (); */ |
252b5132 | 3034 | } |
fd99574b NC |
3035 | |
3036 | /* If s[0] is '4', then this is for the mac instructions | |
3037 | that can have a trailing_ampersand set. If so, set 0x100 | |
3038 | bit on tmpreg so install_gen_operand can check for it and | |
3039 | set the appropriate bit (word2, bit 5). */ | |
3040 | if (s[0] == '4') | |
3041 | { | |
3042 | if (opP->trailing_ampersand) | |
3043 | tmpreg |= 0x100; | |
3044 | } | |
252b5132 RH |
3045 | install_gen_operand (s[1], tmpreg); |
3046 | break; | |
3047 | ||
3048 | case '#': | |
3049 | case '^': | |
3050 | switch (s[1]) | |
3051 | { /* JF: I hate floating point! */ | |
3052 | case 'j': | |
3053 | tmpreg = 70; | |
3054 | break; | |
3055 | case '8': | |
3056 | tmpreg = 20; | |
3057 | break; | |
3058 | case 'C': | |
3059 | tmpreg = 50; | |
3060 | break; | |
3061 | case '3': | |
3062 | default: | |
3e602632 | 3063 | tmpreg = 90; |
252b5132 RH |
3064 | break; |
3065 | } | |
3066 | tmpreg = get_num (&opP->disp, tmpreg); | |
3067 | if (isvar (&opP->disp)) | |
3068 | add_fix (s[1], &opP->disp, 0, 0); | |
3069 | switch (s[1]) | |
3070 | { | |
3071 | case 'b': /* Danger: These do no check for | |
3072 | certain types of overflow. | |
3073 | user beware! */ | |
3074 | if (!isbyte (tmpreg)) | |
3075 | opP->error = _("out of range"); | |
3076 | insop (tmpreg, opcode); | |
3077 | if (isvar (&opP->disp)) | |
3078 | the_ins.reloc[the_ins.nrel - 1].n = | |
3079 | (opcode->m_codenum) * 2 + 1; | |
3080 | break; | |
3081 | case 'B': | |
3082 | if (!issbyte (tmpreg)) | |
3083 | opP->error = _("out of range"); | |
3084 | the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; | |
3085 | if (isvar (&opP->disp)) | |
3086 | the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; | |
3087 | break; | |
3088 | case 'w': | |
3089 | if (!isword (tmpreg)) | |
3090 | opP->error = _("out of range"); | |
3091 | insop (tmpreg, opcode); | |
3092 | if (isvar (&opP->disp)) | |
3093 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
3094 | break; | |
3095 | case 'W': | |
3096 | if (!issword (tmpreg)) | |
3097 | opP->error = _("out of range"); | |
3098 | insop (tmpreg, opcode); | |
3099 | if (isvar (&opP->disp)) | |
3100 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
3101 | break; | |
3102 | case 'l': | |
3103 | /* Because of the way insop works, we put these two out | |
3104 | backwards. */ | |
3105 | insop (tmpreg, opcode); | |
3106 | insop (tmpreg >> 16, opcode); | |
3107 | if (isvar (&opP->disp)) | |
3108 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
3109 | break; | |
3110 | case '3': | |
3111 | tmpreg &= 0xFF; | |
3112 | case '8': | |
3113 | case 'C': | |
3114 | case 'j': | |
3115 | install_operand (s[1], tmpreg); | |
3116 | break; | |
3117 | default: | |
3118 | abort (); | |
3119 | } | |
3120 | break; | |
3121 | ||
3122 | case '+': | |
3123 | case '-': | |
3124 | case 'A': | |
3125 | case 'a': | |
3126 | install_operand (s[1], opP->reg - ADDR); | |
3127 | break; | |
3128 | ||
3129 | case 'B': | |
3e602632 | 3130 | tmpreg = get_num (&opP->disp, 90); |
3739860c | 3131 | |
252b5132 RH |
3132 | switch (s[1]) |
3133 | { | |
3134 | case 'B': | |
8390138c | 3135 | add_fix ('B', &opP->disp, 1, -1); |
252b5132 RH |
3136 | break; |
3137 | case 'W': | |
3138 | add_fix ('w', &opP->disp, 1, 0); | |
3139 | addword (0); | |
3140 | break; | |
3141 | case 'L': | |
3142 | long_branch: | |
151337e8 | 3143 | the_ins.opcode[0] |= 0xff; |
252b5132 RH |
3144 | add_fix ('l', &opP->disp, 1, 0); |
3145 | addword (0); | |
3146 | addword (0); | |
3147 | break; | |
9a2e615a NS |
3148 | case 'g': /* Conditional branch */ |
3149 | have_disp = HAVE_LONG_CALL (current_architecture); | |
3150 | goto var_branch; | |
3739860c | 3151 | |
9a2e615a NS |
3152 | case 'b': /* Unconditional branch */ |
3153 | have_disp = HAVE_LONG_BRANCH (current_architecture); | |
cac27205 | 3154 | use_pl = LONG_BRANCH_VIA_COND (current_architecture); |
9a2e615a | 3155 | goto var_branch; |
3739860c | 3156 | |
9a2e615a NS |
3157 | case 's': /* Unconditional subroutine */ |
3158 | have_disp = HAVE_LONG_CALL (current_architecture); | |
3739860c | 3159 | |
9a2e615a NS |
3160 | var_branch: |
3161 | if (subs (&opP->disp) /* We can't relax it. */ | |
252b5132 | 3162 | #ifdef OBJ_ELF |
9a2e615a NS |
3163 | /* If the displacement needs pic relocation it cannot be |
3164 | relaxed. */ | |
3165 | || opP->disp.pic_reloc != pic_none | |
252b5132 | 3166 | #endif |
9a2e615a NS |
3167 | || 0) |
3168 | { | |
3169 | if (!have_disp) | |
3170 | as_warn (_("Can't use long branches on this architecture")); | |
3171 | goto long_branch; | |
3172 | } | |
3739860c | 3173 | |
252b5132 | 3174 | /* This could either be a symbol, or an absolute |
151337e8 NC |
3175 | address. If it's an absolute address, turn it into |
3176 | an absolute jump right here and keep it out of the | |
3177 | relaxer. */ | |
3178 | if (adds (&opP->disp) == 0) | |
3179 | { | |
3180 | if (the_ins.opcode[0] == 0x6000) /* jbra */ | |
18566f55 | 3181 | the_ins.opcode[0] = 0x4EF9; |
151337e8 | 3182 | else if (the_ins.opcode[0] == 0x6100) /* jbsr */ |
18566f55 | 3183 | the_ins.opcode[0] = 0x4EB9; |
151337e8 NC |
3184 | else /* jCC */ |
3185 | { | |
3186 | the_ins.opcode[0] ^= 0x0100; | |
3187 | the_ins.opcode[0] |= 0x0006; | |
18566f55 | 3188 | addword (0x4EF9); |
151337e8 NC |
3189 | } |
3190 | add_fix ('l', &opP->disp, 0, 0); | |
3191 | addword (0); | |
3192 | addword (0); | |
3193 | break; | |
3194 | } | |
3195 | ||
3196 | /* Now we know it's going into the relaxer. Now figure | |
3197 | out which mode. We try in this order of preference: | |
3198 | long branch, absolute jump, byte/word branches only. */ | |
9a2e615a | 3199 | if (have_disp) |
bd17c2c3 AM |
3200 | add_frag (adds (&opP->disp), |
3201 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3202 | TAB (BRANCHBWL, SZ_UNDEF)); |
3203 | else if (! flag_keep_pcrel) | |
3204 | { | |
3205 | if ((the_ins.opcode[0] == 0x6000) | |
3206 | || (the_ins.opcode[0] == 0x6100)) | |
bd17c2c3 AM |
3207 | add_frag (adds (&opP->disp), |
3208 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3209 | TAB (BRABSJUNC, SZ_UNDEF)); |
3210 | else | |
bd17c2c3 AM |
3211 | add_frag (adds (&opP->disp), |
3212 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3213 | TAB (BRABSJCOND, SZ_UNDEF)); |
3214 | } | |
252b5132 | 3215 | else |
bd17c2c3 AM |
3216 | add_frag (adds (&opP->disp), |
3217 | SEXT (offs (&opP->disp)), | |
cac27205 NC |
3218 | (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) |
3219 | : TAB (BRANCHBW, SZ_UNDEF))); | |
252b5132 RH |
3220 | break; |
3221 | case 'w': | |
3222 | if (isvar (&opP->disp)) | |
3223 | { | |
151337e8 NC |
3224 | /* Check for DBcc instructions. We can relax them, |
3225 | but only if we have long branches and/or absolute | |
3226 | jumps. */ | |
3227 | if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) | |
3228 | && (HAVE_LONG_BRANCH (current_architecture) | |
9a2e615a | 3229 | || ! flag_keep_pcrel)) |
252b5132 | 3230 | { |
151337e8 | 3231 | if (HAVE_LONG_BRANCH (current_architecture)) |
bd17c2c3 AM |
3232 | add_frag (adds (&opP->disp), |
3233 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3234 | TAB (DBCCLBR, SZ_UNDEF)); |
3235 | else | |
bd17c2c3 AM |
3236 | add_frag (adds (&opP->disp), |
3237 | SEXT (offs (&opP->disp)), | |
151337e8 | 3238 | TAB (DBCCABSJ, SZ_UNDEF)); |
252b5132 RH |
3239 | break; |
3240 | } | |
252b5132 RH |
3241 | add_fix ('w', &opP->disp, 1, 0); |
3242 | } | |
3243 | addword (0); | |
3244 | break; | |
36759679 | 3245 | case 'C': /* Fixed size LONG coproc branches. */ |
252b5132 RH |
3246 | add_fix ('l', &opP->disp, 1, 0); |
3247 | addword (0); | |
3248 | addword (0); | |
3249 | break; | |
36759679 | 3250 | case 'c': /* Var size Coprocesssor branches. */ |
151337e8 | 3251 | if (subs (&opP->disp) || (adds (&opP->disp) == 0)) |
252b5132 | 3252 | { |
252b5132 RH |
3253 | the_ins.opcode[the_ins.numo - 1] |= 0x40; |
3254 | add_fix ('l', &opP->disp, 1, 0); | |
3255 | addword (0); | |
3256 | addword (0); | |
3257 | } | |
151337e8 | 3258 | else |
bd17c2c3 AM |
3259 | add_frag (adds (&opP->disp), |
3260 | SEXT (offs (&opP->disp)), | |
151337e8 | 3261 | TAB (FBRANCH, SZ_UNDEF)); |
252b5132 RH |
3262 | break; |
3263 | default: | |
3264 | abort (); | |
3265 | } | |
3266 | break; | |
3267 | ||
36759679 | 3268 | case 'C': /* Ignore it. */ |
252b5132 RH |
3269 | break; |
3270 | ||
36759679 | 3271 | case 'd': /* JF this is a kludge. */ |
252b5132 | 3272 | install_operand ('s', opP->reg - ADDR); |
3e602632 | 3273 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3274 | if (!issword (tmpreg)) |
3275 | { | |
3276 | as_warn (_("Expression out of range, using 0")); | |
3277 | tmpreg = 0; | |
3278 | } | |
3279 | addword (tmpreg); | |
3280 | break; | |
3281 | ||
3282 | case 'D': | |
3283 | install_operand (s[1], opP->reg - DATA); | |
3284 | break; | |
3285 | ||
fd99574b NC |
3286 | case 'e': /* EMAC ACCx, reg/reg. */ |
3287 | install_operand (s[1], opP->reg - ACC); | |
3288 | break; | |
3739860c | 3289 | |
36759679 | 3290 | case 'E': /* Ignore it. */ |
6da466c7 ILT |
3291 | break; |
3292 | ||
252b5132 RH |
3293 | case 'F': |
3294 | install_operand (s[1], opP->reg - FP0); | |
3295 | break; | |
3296 | ||
fd99574b NC |
3297 | case 'g': /* EMAC ACCEXTx. */ |
3298 | install_operand (s[1], opP->reg - ACCEXT01); | |
3299 | break; | |
3300 | ||
36759679 | 3301 | case 'G': /* Ignore it. */ |
6da466c7 ILT |
3302 | case 'H': |
3303 | break; | |
3304 | ||
252b5132 RH |
3305 | case 'I': |
3306 | tmpreg = opP->reg - COP0; | |
3307 | install_operand (s[1], tmpreg); | |
3308 | break; | |
3309 | ||
fd99574b NC |
3310 | case 'i': /* MAC/EMAC scale factor. */ |
3311 | install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); | |
3312 | break; | |
3313 | ||
36759679 | 3314 | case 'J': /* JF foo. */ |
252b5132 RH |
3315 | switch (opP->reg) |
3316 | { | |
3317 | case SFC: | |
3318 | tmpreg = 0x000; | |
3319 | break; | |
3320 | case DFC: | |
3321 | tmpreg = 0x001; | |
3322 | break; | |
3323 | case CACR: | |
3324 | tmpreg = 0x002; | |
3325 | break; | |
3326 | case TC: | |
a8e24a56 | 3327 | case ASID: |
252b5132 RH |
3328 | tmpreg = 0x003; |
3329 | break; | |
3e602632 | 3330 | case ACR0: |
252b5132 RH |
3331 | case ITT0: |
3332 | tmpreg = 0x004; | |
3333 | break; | |
3e602632 | 3334 | case ACR1: |
252b5132 RH |
3335 | case ITT1: |
3336 | tmpreg = 0x005; | |
3337 | break; | |
3e602632 | 3338 | case ACR2: |
252b5132 RH |
3339 | case DTT0: |
3340 | tmpreg = 0x006; | |
3341 | break; | |
3e602632 | 3342 | case ACR3: |
252b5132 RH |
3343 | case DTT1: |
3344 | tmpreg = 0x007; | |
3345 | break; | |
3346 | case BUSCR: | |
a8e24a56 | 3347 | case MMUBAR: |
252b5132 RH |
3348 | tmpreg = 0x008; |
3349 | break; | |
0d999f33 MK |
3350 | case RGPIOBAR: |
3351 | tmpreg = 0x009; | |
3352 | break; | |
3353 | case ACR4: | |
3354 | case ACR5: | |
3355 | case ACR6: | |
3356 | case ACR7: | |
3357 | tmpreg = 0x00c + (opP->reg - ACR4); | |
3358 | break; | |
252b5132 RH |
3359 | |
3360 | case USP: | |
3361 | tmpreg = 0x800; | |
3362 | break; | |
3363 | case VBR: | |
3364 | tmpreg = 0x801; | |
3365 | break; | |
3366 | case CAAR: | |
87298967 | 3367 | case CPUCR: |
252b5132 RH |
3368 | tmpreg = 0x802; |
3369 | break; | |
3370 | case MSP: | |
3371 | tmpreg = 0x803; | |
3372 | break; | |
3373 | case ISP: | |
3374 | tmpreg = 0x804; | |
3375 | break; | |
3376 | case MMUSR: | |
3377 | tmpreg = 0x805; | |
3378 | break; | |
3379 | case URP: | |
3380 | tmpreg = 0x806; | |
3381 | break; | |
3382 | case SRP: | |
3383 | tmpreg = 0x807; | |
3384 | break; | |
3385 | case PCR: | |
3386 | tmpreg = 0x808; | |
3387 | break; | |
3388 | case ROMBAR: | |
a8e24a56 | 3389 | case ROMBAR0: |
252b5132 RH |
3390 | tmpreg = 0xC00; |
3391 | break; | |
3e602632 NC |
3392 | case ROMBAR1: |
3393 | tmpreg = 0xC01; | |
3394 | break; | |
3395 | case FLASHBAR: | |
252b5132 | 3396 | case RAMBAR0: |
78336706 | 3397 | case RAMBAR_ALT: |
252b5132 RH |
3398 | tmpreg = 0xC04; |
3399 | break; | |
3e602632 | 3400 | case RAMBAR: |
252b5132 RH |
3401 | case RAMBAR1: |
3402 | tmpreg = 0xC05; | |
3403 | break; | |
3e602632 NC |
3404 | case MPCR: |
3405 | tmpreg = 0xC0C; | |
3406 | break; | |
3407 | case EDRAMBAR: | |
3408 | tmpreg = 0xC0D; | |
3409 | break; | |
3410 | case MBAR0: | |
e80e0390 | 3411 | case MBAR2: |
3e602632 NC |
3412 | case SECMBAR: |
3413 | tmpreg = 0xC0E; | |
3414 | break; | |
3415 | case MBAR1: | |
252b5132 RH |
3416 | case MBAR: |
3417 | tmpreg = 0xC0F; | |
3418 | break; | |
3e602632 NC |
3419 | case PCR1U0: |
3420 | tmpreg = 0xD02; | |
3421 | break; | |
3422 | case PCR1L0: | |
3423 | tmpreg = 0xD03; | |
3424 | break; | |
3425 | case PCR2U0: | |
3426 | tmpreg = 0xD04; | |
3427 | break; | |
3428 | case PCR2L0: | |
3429 | tmpreg = 0xD05; | |
3430 | break; | |
3431 | case PCR3U0: | |
3432 | tmpreg = 0xD06; | |
3433 | break; | |
3434 | case PCR3L0: | |
3435 | tmpreg = 0xD07; | |
3436 | break; | |
3437 | case PCR1L1: | |
3438 | tmpreg = 0xD0A; | |
3439 | break; | |
3440 | case PCR1U1: | |
3441 | tmpreg = 0xD0B; | |
3442 | break; | |
3443 | case PCR2L1: | |
3444 | tmpreg = 0xD0C; | |
3445 | break; | |
3446 | case PCR2U1: | |
3447 | tmpreg = 0xD0D; | |
3448 | break; | |
3449 | case PCR3L1: | |
3450 | tmpreg = 0xD0E; | |
3451 | break; | |
3452 | case PCR3U1: | |
3453 | tmpreg = 0xD0F; | |
3454 | break; | |
f7ec513b KH |
3455 | case CAC: |
3456 | tmpreg = 0xFFE; | |
3457 | break; | |
d0fa1372 | 3458 | case MBO: |
f7ec513b KH |
3459 | tmpreg = 0xFFF; |
3460 | break; | |
252b5132 RH |
3461 | default: |
3462 | abort (); | |
3463 | } | |
3464 | install_operand (s[1], tmpreg); | |
3465 | break; | |
3466 | ||
3467 | case 'k': | |
3468 | tmpreg = get_num (&opP->disp, 55); | |
3469 | install_operand (s[1], tmpreg & 0x7f); | |
3470 | break; | |
3471 | ||
3472 | case 'l': | |
3473 | tmpreg = opP->mask; | |
3474 | if (s[1] == 'w') | |
3475 | { | |
3476 | if (tmpreg & 0x7FF0000) | |
3477 | as_bad (_("Floating point register in register list")); | |
3478 | insop (reverse_16_bits (tmpreg), opcode); | |
3479 | } | |
3480 | else | |
3481 | { | |
3482 | if (tmpreg & 0x700FFFF) | |
3483 | as_bad (_("Wrong register in floating-point reglist")); | |
3484 | install_operand (s[1], reverse_8_bits (tmpreg >> 16)); | |
3485 | } | |
3486 | break; | |
3487 | ||
3488 | case 'L': | |
3489 | tmpreg = opP->mask; | |
3490 | if (s[1] == 'w') | |
3491 | { | |
3492 | if (tmpreg & 0x7FF0000) | |
3493 | as_bad (_("Floating point register in register list")); | |
3494 | insop (tmpreg, opcode); | |
3495 | } | |
3496 | else if (s[1] == '8') | |
3497 | { | |
3498 | if (tmpreg & 0x0FFFFFF) | |
3499 | as_bad (_("incorrect register in reglist")); | |
3500 | install_operand (s[1], tmpreg >> 24); | |
3501 | } | |
3502 | else | |
3503 | { | |
3504 | if (tmpreg & 0x700FFFF) | |
3505 | as_bad (_("wrong register in floating-point reglist")); | |
3506 | else | |
3507 | install_operand (s[1], tmpreg >> 16); | |
3508 | } | |
3509 | break; | |
3510 | ||
3511 | case 'M': | |
3512 | install_operand (s[1], get_num (&opP->disp, 60)); | |
3513 | break; | |
3514 | ||
3515 | case 'O': | |
3516 | tmpreg = ((opP->mode == DREG) | |
8fce3f5e | 3517 | ? 0x20 + (int) (opP->reg - DATA) |
252b5132 RH |
3518 | : (get_num (&opP->disp, 40) & 0x1F)); |
3519 | install_operand (s[1], tmpreg); | |
3520 | break; | |
3521 | ||
3522 | case 'Q': | |
3523 | tmpreg = get_num (&opP->disp, 10); | |
3524 | if (tmpreg == 8) | |
3525 | tmpreg = 0; | |
3526 | install_operand (s[1], tmpreg); | |
3527 | break; | |
3528 | ||
3529 | case 'R': | |
3530 | /* This depends on the fact that ADDR registers are eight | |
3531 | more than their corresponding DATA regs, so the result | |
36759679 | 3532 | will have the ADDR_REG bit set. */ |
252b5132 RH |
3533 | install_operand (s[1], opP->reg - DATA); |
3534 | break; | |
3535 | ||
3536 | case 'r': | |
3537 | if (opP->mode == AINDR) | |
3538 | install_operand (s[1], opP->reg - DATA); | |
3539 | else | |
3540 | install_operand (s[1], opP->index.reg - DATA); | |
3541 | break; | |
3542 | ||
3543 | case 's': | |
3544 | if (opP->reg == FPI) | |
3545 | tmpreg = 0x1; | |
3546 | else if (opP->reg == FPS) | |
3547 | tmpreg = 0x2; | |
3548 | else if (opP->reg == FPC) | |
3549 | tmpreg = 0x4; | |
3550 | else | |
3551 | abort (); | |
3552 | install_operand (s[1], tmpreg); | |
3553 | break; | |
3554 | ||
36759679 | 3555 | case 'S': /* Ignore it. */ |
252b5132 RH |
3556 | break; |
3557 | ||
3558 | case 'T': | |
3559 | install_operand (s[1], get_num (&opP->disp, 30)); | |
3560 | break; | |
3561 | ||
36759679 | 3562 | case 'U': /* Ignore it. */ |
252b5132 RH |
3563 | break; |
3564 | ||
3565 | case 'c': | |
3566 | switch (opP->reg) | |
3567 | { | |
3568 | case NC: | |
3569 | tmpreg = 0; | |
3570 | break; | |
3571 | case DC: | |
3572 | tmpreg = 1; | |
3573 | break; | |
3574 | case IC: | |
3575 | tmpreg = 2; | |
3576 | break; | |
3577 | case BC: | |
3578 | tmpreg = 3; | |
3579 | break; | |
3580 | default: | |
3581 | as_fatal (_("failed sanity check")); | |
36759679 | 3582 | } /* switch on cache token. */ |
252b5132 RH |
3583 | install_operand (s[1], tmpreg); |
3584 | break; | |
3585 | #ifndef NO_68851 | |
92774660 | 3586 | /* JF: These are out of order, I fear. */ |
252b5132 RH |
3587 | case 'f': |
3588 | switch (opP->reg) | |
3589 | { | |
3590 | case SFC: | |
3591 | tmpreg = 0; | |
3592 | break; | |
3593 | case DFC: | |
3594 | tmpreg = 1; | |
3595 | break; | |
3596 | default: | |
3597 | abort (); | |
3598 | } | |
3599 | install_operand (s[1], tmpreg); | |
3600 | break; | |
3601 | ||
3602 | case '0': | |
3603 | case '1': | |
3604 | case '2': | |
3605 | switch (opP->reg) | |
3606 | { | |
3607 | case TC: | |
3608 | tmpreg = 0; | |
3609 | break; | |
3610 | case CAL: | |
3611 | tmpreg = 4; | |
3612 | break; | |
3613 | case VAL: | |
3614 | tmpreg = 5; | |
3615 | break; | |
3616 | case SCC: | |
3617 | tmpreg = 6; | |
3618 | break; | |
3619 | case AC: | |
3620 | tmpreg = 7; | |
3621 | break; | |
3622 | default: | |
3623 | abort (); | |
3624 | } | |
3625 | install_operand (s[1], tmpreg); | |
3626 | break; | |
3627 | ||
3628 | case 'V': | |
3629 | if (opP->reg == VAL) | |
3630 | break; | |
3631 | abort (); | |
3632 | ||
3633 | case 'W': | |
3634 | switch (opP->reg) | |
3635 | { | |
3636 | case DRP: | |
3637 | tmpreg = 1; | |
3638 | break; | |
3639 | case SRP: | |
3640 | tmpreg = 2; | |
3641 | break; | |
3642 | case CRP: | |
3643 | tmpreg = 3; | |
3644 | break; | |
3645 | default: | |
3646 | abort (); | |
3647 | } | |
3648 | install_operand (s[1], tmpreg); | |
3649 | break; | |
3650 | ||
3651 | case 'X': | |
3652 | switch (opP->reg) | |
3653 | { | |
3654 | case BAD: | |
3655 | case BAD + 1: | |
3656 | case BAD + 2: | |
3657 | case BAD + 3: | |
3658 | case BAD + 4: | |
3659 | case BAD + 5: | |
3660 | case BAD + 6: | |
3661 | case BAD + 7: | |
3662 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
3663 | break; | |
3664 | ||
3665 | case BAC: | |
3666 | case BAC + 1: | |
3667 | case BAC + 2: | |
3668 | case BAC + 3: | |
3669 | case BAC + 4: | |
3670 | case BAC + 5: | |
3671 | case BAC + 6: | |
3672 | case BAC + 7: | |
3673 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
3674 | break; | |
3675 | ||
3676 | default: | |
3677 | abort (); | |
3678 | } | |
3679 | install_operand (s[1], tmpreg); | |
3680 | break; | |
3681 | case 'Y': | |
3682 | know (opP->reg == PSR); | |
3683 | break; | |
3684 | case 'Z': | |
3685 | know (opP->reg == PCSR); | |
3686 | break; | |
3687 | #endif /* m68851 */ | |
3688 | case '3': | |
3689 | switch (opP->reg) | |
3690 | { | |
3691 | case TT0: | |
3692 | tmpreg = 2; | |
3693 | break; | |
3694 | case TT1: | |
3695 | tmpreg = 3; | |
3696 | break; | |
3697 | default: | |
3698 | abort (); | |
3699 | } | |
3700 | install_operand (s[1], tmpreg); | |
3701 | break; | |
3702 | case 't': | |
3703 | tmpreg = get_num (&opP->disp, 20); | |
3704 | install_operand (s[1], tmpreg); | |
3705 | break; | |
36759679 | 3706 | case '_': /* used only for move16 absolute 32-bit address. */ |
252b5132 RH |
3707 | if (isvar (&opP->disp)) |
3708 | add_fix ('l', &opP->disp, 0, 0); | |
3e602632 | 3709 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3710 | addword (tmpreg >> 16); |
3711 | addword (tmpreg & 0xFFFF); | |
3712 | break; | |
6da466c7 ILT |
3713 | case 'u': |
3714 | install_operand (s[1], opP->reg - DATA0L); | |
3715 | opP->reg -= (DATA0L); | |
36759679 | 3716 | opP->reg &= 0x0F; /* remove upper/lower bit. */ |
6da466c7 | 3717 | break; |
3e602632 NC |
3718 | case 'x': |
3719 | tmpreg = get_num (&opP->disp, 80); | |
3720 | if (tmpreg == -1) | |
3721 | tmpreg = 0; | |
3722 | install_operand (s[1], tmpreg); | |
3723 | break; | |
afa2158f NS |
3724 | case 'j': |
3725 | tmpreg = get_num (&opP->disp, 10); | |
3726 | install_operand (s[1], tmpreg - 1); | |
3727 | break; | |
3728 | case 'K': | |
3729 | tmpreg = get_num (&opP->disp, 65); | |
3730 | install_operand (s[1], tmpreg); | |
3731 | break; | |
252b5132 RH |
3732 | default: |
3733 | abort (); | |
3734 | } | |
3735 | } | |
3736 | ||
3737 | /* By the time whe get here (FINALLY) the_ins contains the complete | |
92774660 | 3738 | instruction, ready to be emitted. . . */ |
252b5132 RH |
3739 | } |
3740 | ||
3741 | static int | |
31302357 | 3742 | reverse_16_bits (int in) |
252b5132 RH |
3743 | { |
3744 | int out = 0; | |
3745 | int n; | |
3746 | ||
3747 | static int mask[16] = | |
3748 | { | |
3749 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3750 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 | |
3751 | }; | |
3752 | for (n = 0; n < 16; n++) | |
3753 | { | |
3754 | if (in & mask[n]) | |
3755 | out |= mask[15 - n]; | |
3756 | } | |
3757 | return out; | |
3758 | } /* reverse_16_bits() */ | |
3759 | ||
3760 | static int | |
31302357 | 3761 | reverse_8_bits (int in) |
252b5132 RH |
3762 | { |
3763 | int out = 0; | |
3764 | int n; | |
3765 | ||
3766 | static int mask[8] = | |
3767 | { | |
3768 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3769 | }; | |
3770 | ||
3771 | for (n = 0; n < 8; n++) | |
3772 | { | |
3773 | if (in & mask[n]) | |
3774 | out |= mask[7 - n]; | |
3775 | } | |
3776 | return out; | |
3777 | } /* reverse_8_bits() */ | |
3778 | ||
cac27205 NC |
3779 | /* Cause an extra frag to be generated here, inserting up to |
3780 | FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be | |
3781 | generated; its primary type is rs_machine_dependent. | |
252b5132 RH |
3782 | |
3783 | The TYPE parameter is also used by md_convert_frag_1 and | |
3784 | md_estimate_size_before_relax. The appropriate type of fixup will | |
3785 | be emitted by md_convert_frag_1. | |
3786 | ||
3787 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
3788 | static void | |
31302357 | 3789 | install_operand (int mode, int val) |
252b5132 RH |
3790 | { |
3791 | switch (mode) | |
3792 | { | |
3793 | case 's': | |
36759679 | 3794 | the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ |
252b5132 RH |
3795 | break; |
3796 | case 'd': | |
3797 | the_ins.opcode[0] |= val << 9; | |
3798 | break; | |
afa2158f NS |
3799 | case 'E': |
3800 | the_ins.opcode[1] |= val << 9; | |
3801 | break; | |
252b5132 RH |
3802 | case '1': |
3803 | the_ins.opcode[1] |= val << 12; | |
3804 | break; | |
3805 | case '2': | |
3806 | the_ins.opcode[1] |= val << 6; | |
3807 | break; | |
3808 | case '3': | |
3809 | the_ins.opcode[1] |= val; | |
3810 | break; | |
3811 | case '4': | |
3812 | the_ins.opcode[2] |= val << 12; | |
3813 | break; | |
3814 | case '5': | |
3815 | the_ins.opcode[2] |= val << 6; | |
3816 | break; | |
3817 | case '6': | |
3818 | /* DANGER! This is a hack to force cas2l and cas2w cmds to be | |
3819 | three words long! */ | |
3820 | the_ins.numo++; | |
3821 | the_ins.opcode[2] |= val; | |
3822 | break; | |
3823 | case '7': | |
3824 | the_ins.opcode[1] |= val << 7; | |
3825 | break; | |
3826 | case '8': | |
3827 | the_ins.opcode[1] |= val << 10; | |
3828 | break; | |
3829 | #ifndef NO_68851 | |
3830 | case '9': | |
3831 | the_ins.opcode[1] |= val << 5; | |
3832 | break; | |
3833 | #endif | |
3834 | ||
3835 | case 't': | |
3836 | the_ins.opcode[1] |= (val << 10) | (val << 7); | |
3837 | break; | |
3838 | case 'D': | |
3839 | the_ins.opcode[1] |= (val << 12) | val; | |
3840 | break; | |
3841 | case 'g': | |
3842 | the_ins.opcode[0] |= val = 0xff; | |
3843 | break; | |
3844 | case 'i': | |
3845 | the_ins.opcode[0] |= val << 9; | |
3846 | break; | |
3847 | case 'C': | |
3848 | the_ins.opcode[1] |= val; | |
3849 | break; | |
3850 | case 'j': | |
3851 | the_ins.opcode[1] |= val; | |
36759679 | 3852 | the_ins.numo++; /* What a hack. */ |
252b5132 RH |
3853 | break; |
3854 | case 'k': | |
3855 | the_ins.opcode[1] |= val << 4; | |
3856 | break; | |
3857 | case 'b': | |
3858 | case 'w': | |
3859 | case 'W': | |
3860 | case 'l': | |
3861 | break; | |
3862 | case 'e': | |
3863 | the_ins.opcode[0] |= (val << 6); | |
3864 | break; | |
3865 | case 'L': | |
3866 | the_ins.opcode[1] = (val >> 16); | |
3867 | the_ins.opcode[2] = val & 0xffff; | |
3868 | break; | |
6da466c7 ILT |
3869 | case 'm': |
3870 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); | |
3871 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
3872 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3873 | break; | |
fd99574b | 3874 | case 'n': /* MAC/EMAC Rx on !load. */ |
6da466c7 ILT |
3875 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); |
3876 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
fd99574b | 3877 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); |
6da466c7 | 3878 | break; |
fd99574b | 3879 | case 'o': /* MAC/EMAC Rx on load. */ |
6da466c7 ILT |
3880 | the_ins.opcode[1] |= val << 12; |
3881 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3882 | break; | |
fd99574b | 3883 | case 'M': /* MAC/EMAC Ry on !load. */ |
6da466c7 ILT |
3884 | the_ins.opcode[0] |= (val & 0xF); |
3885 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3886 | break; | |
fd99574b | 3887 | case 'N': /* MAC/EMAC Ry on load. */ |
6da466c7 ILT |
3888 | the_ins.opcode[1] |= (val & 0xF); |
3889 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3890 | break; | |
3891 | case 'h': | |
3892 | the_ins.opcode[1] |= ((val != 1) << 10); | |
3893 | break; | |
fd99574b NC |
3894 | case 'F': |
3895 | the_ins.opcode[0] |= ((val & 0x3) << 9); | |
3896 | break; | |
3897 | case 'f': | |
3898 | the_ins.opcode[0] |= ((val & 0x3) << 0); | |
3899 | break; | |
be8c092b | 3900 | case 'G': /* EMAC accumulator in a EMAC load instruction. */ |
fd99574b NC |
3901 | the_ins.opcode[0] |= ((~val & 0x1) << 7); |
3902 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3903 | break; | |
be8c092b | 3904 | case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ |
fd99574b NC |
3905 | the_ins.opcode[0] |= ((val & 0x1) << 7); |
3906 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3907 | break; | |
3908 | case 'I': | |
3909 | the_ins.opcode[1] |= ((val & 0x3) << 9); | |
3910 | break; | |
3911 | case ']': | |
3912 | the_ins.opcode[0] |= (val & 0x1) <<10; | |
3913 | break; | |
252b5132 RH |
3914 | case 'c': |
3915 | default: | |
3916 | as_fatal (_("failed sanity check.")); | |
3917 | } | |
6b6e92f4 | 3918 | } |
252b5132 RH |
3919 | |
3920 | static void | |
31302357 | 3921 | install_gen_operand (int mode, int val) |
252b5132 RH |
3922 | { |
3923 | switch (mode) | |
3924 | { | |
fd99574b NC |
3925 | case '/': /* Special for mask loads for mac/msac insns with |
3926 | possible mask; trailing_ampersend set in bit 8. */ | |
3927 | the_ins.opcode[0] |= (val & 0x3f); | |
3928 | the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); | |
3929 | break; | |
252b5132 RH |
3930 | case 's': |
3931 | the_ins.opcode[0] |= val; | |
3932 | break; | |
3933 | case 'd': | |
3934 | /* This is a kludge!!! */ | |
3935 | the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; | |
3936 | break; | |
3937 | case 'b': | |
3938 | case 'w': | |
3939 | case 'l': | |
3940 | case 'f': | |
3941 | case 'F': | |
3942 | case 'x': | |
3943 | case 'p': | |
3944 | the_ins.opcode[0] |= val; | |
3945 | break; | |
36759679 | 3946 | /* more stuff goes here. */ |
252b5132 RH |
3947 | default: |
3948 | as_fatal (_("failed sanity check.")); | |
3949 | } | |
6b6e92f4 | 3950 | } |
252b5132 | 3951 | |
6b6e92f4 NC |
3952 | /* Verify that we have some number of paren pairs, do m68k_ip_op(), and |
3953 | then deal with the bitfield hack. */ | |
252b5132 RH |
3954 | |
3955 | static char * | |
31302357 | 3956 | crack_operand (char *str, struct m68k_op *opP) |
252b5132 | 3957 | { |
ed9e98c2 AM |
3958 | int parens; |
3959 | int c; | |
3960 | char *beg_str; | |
252b5132 RH |
3961 | int inquote = 0; |
3962 | ||
3963 | if (!str) | |
3964 | { | |
3965 | return str; | |
3966 | } | |
3967 | beg_str = str; | |
3968 | for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) | |
3969 | { | |
3970 | if (! inquote) | |
3971 | { | |
3972 | if (*str == '(') | |
3973 | parens++; | |
3974 | else if (*str == ')') | |
3975 | { | |
3976 | if (!parens) | |
36759679 | 3977 | { /* ERROR. */ |
252b5132 RH |
3978 | opP->error = _("Extra )"); |
3979 | return str; | |
3980 | } | |
3981 | --parens; | |
3982 | } | |
3983 | } | |
3984 | if (flag_mri && *str == '\'') | |
3985 | inquote = ! inquote; | |
3986 | } | |
3987 | if (!*str && parens) | |
36759679 | 3988 | { /* ERROR. */ |
252b5132 RH |
3989 | opP->error = _("Missing )"); |
3990 | return str; | |
3991 | } | |
3992 | c = *str; | |
3993 | *str = '\0'; | |
3994 | if (m68k_ip_op (beg_str, opP) != 0) | |
3995 | { | |
3996 | *str = c; | |
3997 | return str; | |
3998 | } | |
3999 | *str = c; | |
4000 | if (c == '}') | |
36759679 | 4001 | c = *++str; /* JF bitfield hack. */ |
252b5132 RH |
4002 | if (c) |
4003 | { | |
4004 | c = *++str; | |
4005 | if (!c) | |
4006 | as_bad (_("Missing operand")); | |
4007 | } | |
4008 | ||
4009 | /* Detect MRI REG symbols and convert them to REGLSTs. */ | |
4010 | if (opP->mode == CONTROL && (int)opP->reg < 0) | |
4011 | { | |
4012 | opP->mode = REGLST; | |
4013 | opP->mask = ~(int)opP->reg; | |
4014 | opP->reg = 0; | |
4015 | } | |
4016 | ||
4017 | return str; | |
4018 | } | |
4019 | ||
4020 | /* This is the guts of the machine-dependent assembler. STR points to a | |
4021 | machine dependent instruction. This function is supposed to emit | |
4022 | the frags/bytes it assembles to. | |
4023 | */ | |
4024 | ||
4025 | static void | |
31302357 | 4026 | insert_reg (const char *regname, int regnum) |
252b5132 RH |
4027 | { |
4028 | char buf[100]; | |
4029 | int i; | |
4030 | ||
4031 | #ifdef REGISTER_PREFIX | |
4032 | if (!flag_reg_prefix_optional) | |
4033 | { | |
4034 | buf[0] = REGISTER_PREFIX; | |
4035 | strcpy (buf + 1, regname); | |
4036 | regname = buf; | |
4037 | } | |
4038 | #endif | |
4039 | ||
4040 | symbol_table_insert (symbol_new (regname, reg_section, regnum, | |
4041 | &zero_address_frag)); | |
4042 | ||
4043 | for (i = 0; regname[i]; i++) | |
3882b010 | 4044 | buf[i] = TOUPPER (regname[i]); |
252b5132 RH |
4045 | buf[i] = '\0'; |
4046 | ||
4047 | symbol_table_insert (symbol_new (buf, reg_section, regnum, | |
4048 | &zero_address_frag)); | |
4049 | } | |
4050 | ||
4051 | struct init_entry | |
4052 | { | |
4053 | const char *name; | |
4054 | int number; | |
4055 | }; | |
4056 | ||
4057 | static const struct init_entry init_table[] = | |
4058 | { | |
4059 | { "d0", DATA0 }, | |
4060 | { "d1", DATA1 }, | |
4061 | { "d2", DATA2 }, | |
4062 | { "d3", DATA3 }, | |
4063 | { "d4", DATA4 }, | |
4064 | { "d5", DATA5 }, | |
4065 | { "d6", DATA6 }, | |
4066 | { "d7", DATA7 }, | |
4067 | { "a0", ADDR0 }, | |
4068 | { "a1", ADDR1 }, | |
4069 | { "a2", ADDR2 }, | |
4070 | { "a3", ADDR3 }, | |
4071 | { "a4", ADDR4 }, | |
4072 | { "a5", ADDR5 }, | |
4073 | { "a6", ADDR6 }, | |
4074 | { "fp", ADDR6 }, | |
4075 | { "a7", ADDR7 }, | |
4076 | { "sp", ADDR7 }, | |
4077 | { "ssp", ADDR7 }, | |
4078 | { "fp0", FP0 }, | |
4079 | { "fp1", FP1 }, | |
4080 | { "fp2", FP2 }, | |
4081 | { "fp3", FP3 }, | |
4082 | { "fp4", FP4 }, | |
4083 | { "fp5", FP5 }, | |
4084 | { "fp6", FP6 }, | |
4085 | { "fp7", FP7 }, | |
4086 | { "fpi", FPI }, | |
4087 | { "fpiar", FPI }, | |
4088 | { "fpc", FPI }, | |
4089 | { "fps", FPS }, | |
4090 | { "fpsr", FPS }, | |
4091 | { "fpc", FPC }, | |
4092 | { "fpcr", FPC }, | |
4093 | { "control", FPC }, | |
4094 | { "status", FPS }, | |
4095 | { "iaddr", FPI }, | |
4096 | ||
4097 | { "cop0", COP0 }, | |
4098 | { "cop1", COP1 }, | |
4099 | { "cop2", COP2 }, | |
4100 | { "cop3", COP3 }, | |
4101 | { "cop4", COP4 }, | |
4102 | { "cop5", COP5 }, | |
4103 | { "cop6", COP6 }, | |
4104 | { "cop7", COP7 }, | |
4105 | { "pc", PC }, | |
4106 | { "zpc", ZPC }, | |
4107 | { "sr", SR }, | |
4108 | ||
4109 | { "ccr", CCR }, | |
4110 | { "cc", CCR }, | |
4111 | ||
6da466c7 | 4112 | { "acc", ACC }, |
fd99574b NC |
4113 | { "acc0", ACC }, |
4114 | { "acc1", ACC1 }, | |
4115 | { "acc2", ACC2 }, | |
4116 | { "acc3", ACC3 }, | |
4117 | { "accext01", ACCEXT01 }, | |
4118 | { "accext23", ACCEXT23 }, | |
6da466c7 ILT |
4119 | { "macsr", MACSR }, |
4120 | { "mask", MASK }, | |
4121 | ||
36759679 NC |
4122 | /* Control registers. */ |
4123 | { "sfc", SFC }, /* Source Function Code. */ | |
252b5132 | 4124 | { "sfcr", SFC }, |
36759679 | 4125 | { "dfc", DFC }, /* Destination Function Code. */ |
252b5132 | 4126 | { "dfcr", DFC }, |
36759679 NC |
4127 | { "cacr", CACR }, /* Cache Control Register. */ |
4128 | { "caar", CAAR }, /* Cache Address Register. */ | |
87298967 | 4129 | { "cpucr", CPUCR }, /* CPU Control Register. */ |
252b5132 | 4130 | |
36759679 NC |
4131 | { "usp", USP }, /* User Stack Pointer. */ |
4132 | { "vbr", VBR }, /* Vector Base Register. */ | |
4133 | { "msp", MSP }, /* Master Stack Pointer. */ | |
4134 | { "isp", ISP }, /* Interrupt Stack Pointer. */ | |
252b5132 | 4135 | |
36759679 NC |
4136 | { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ |
4137 | { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ | |
4138 | { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ | |
4139 | { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ | |
252b5132 RH |
4140 | |
4141 | /* 68ec040 versions of same */ | |
36759679 NC |
4142 | { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ |
4143 | { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ | |
4144 | { "dacr0", DTT0 }, /* Data Access Control Register 0. */ | |
4145 | { "dacr1", DTT1 }, /* Data Access Control Register 0. */ | |
252b5132 | 4146 | |
a8e24a56 | 4147 | /* Coldfire versions of same. The ColdFire programmer's reference |
252b5132 RH |
4148 | manual indicated that the order is 2,3,0,1, but Ken Rose |
4149 | <rose@netcom.com> says that 0,1,2,3 is the correct order. */ | |
3e602632 NC |
4150 | { "acr0", ACR0 }, /* Access Control Unit 0. */ |
4151 | { "acr1", ACR1 }, /* Access Control Unit 1. */ | |
4152 | { "acr2", ACR2 }, /* Access Control Unit 2. */ | |
4153 | { "acr3", ACR3 }, /* Access Control Unit 3. */ | |
0d999f33 MK |
4154 | { "acr4", ACR4 }, /* Access Control Unit 4. */ |
4155 | { "acr5", ACR5 }, /* Access Control Unit 5. */ | |
4156 | { "acr6", ACR6 }, /* Access Control Unit 6. */ | |
4157 | { "acr7", ACR7 }, /* Access Control Unit 7. */ | |
252b5132 | 4158 | |
36759679 | 4159 | { "tc", TC }, /* MMU Translation Control Register. */ |
252b5132 | 4160 | { "tcr", TC }, |
a8e24a56 | 4161 | { "asid", ASID }, |
252b5132 | 4162 | |
36759679 NC |
4163 | { "mmusr", MMUSR }, /* MMU Status Register. */ |
4164 | { "srp", SRP }, /* User Root Pointer. */ | |
4165 | { "urp", URP }, /* Supervisor Root Pointer. */ | |
252b5132 RH |
4166 | |
4167 | { "buscr", BUSCR }, | |
a8e24a56 | 4168 | { "mmubar", MMUBAR }, |
252b5132 RH |
4169 | { "pcr", PCR }, |
4170 | ||
36759679 NC |
4171 | { "rombar", ROMBAR }, /* ROM Base Address Register. */ |
4172 | { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ | |
4173 | { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ | |
4174 | { "mbar", MBAR }, /* Module Base Address Register. */ | |
3e602632 NC |
4175 | |
4176 | { "mbar0", MBAR0 }, /* mcfv4e registers. */ | |
4177 | { "mbar1", MBAR1 }, /* mcfv4e registers. */ | |
a8e24a56 | 4178 | { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ |
3e602632 NC |
4179 | { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ |
4180 | { "mpcr", MPCR }, /* mcfv4e registers. */ | |
4181 | { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ | |
4182 | { "secmbar", SECMBAR }, /* mcfv4e registers. */ | |
4183 | { "asid", TC }, /* mcfv4e registers. */ | |
4184 | { "mmubar", BUSCR }, /* mcfv4e registers. */ | |
4185 | { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ | |
4186 | { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ | |
4187 | { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ | |
4188 | { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ | |
4189 | { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ | |
4190 | { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ | |
4191 | { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ | |
4192 | { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ | |
4193 | { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ | |
4194 | { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ | |
4195 | { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ | |
4196 | { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ | |
4197 | ||
4198 | { "flashbar", FLASHBAR }, /* mcf528x registers. */ | |
4199 | { "rambar", RAMBAR }, /* mcf528x registers. */ | |
e80e0390 NC |
4200 | |
4201 | { "mbar2", MBAR2 }, /* mcf5249 registers. */ | |
f7ec513b | 4202 | |
0d999f33 MK |
4203 | { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */ |
4204 | ||
f7ec513b | 4205 | { "cac", CAC }, /* fido registers. */ |
d0fa1372 KH |
4206 | { "mbb", MBO }, /* fido registers (obsolete). */ |
4207 | { "mbo", MBO }, /* fido registers. */ | |
36759679 | 4208 | /* End of control registers. */ |
252b5132 RH |
4209 | |
4210 | { "ac", AC }, | |
4211 | { "bc", BC }, | |
4212 | { "cal", CAL }, | |
4213 | { "crp", CRP }, | |
4214 | { "drp", DRP }, | |
4215 | { "pcsr", PCSR }, | |
4216 | { "psr", PSR }, | |
4217 | { "scc", SCC }, | |
4218 | { "val", VAL }, | |
4219 | { "bad0", BAD0 }, | |
4220 | { "bad1", BAD1 }, | |
4221 | { "bad2", BAD2 }, | |
4222 | { "bad3", BAD3 }, | |
4223 | { "bad4", BAD4 }, | |
4224 | { "bad5", BAD5 }, | |
4225 | { "bad6", BAD6 }, | |
4226 | { "bad7", BAD7 }, | |
4227 | { "bac0", BAC0 }, | |
4228 | { "bac1", BAC1 }, | |
4229 | { "bac2", BAC2 }, | |
4230 | { "bac3", BAC3 }, | |
4231 | { "bac4", BAC4 }, | |
4232 | { "bac5", BAC5 }, | |
4233 | { "bac6", BAC6 }, | |
4234 | { "bac7", BAC7 }, | |
4235 | ||
4236 | { "ic", IC }, | |
4237 | { "dc", DC }, | |
4238 | { "nc", NC }, | |
4239 | ||
4240 | { "tt0", TT0 }, | |
4241 | { "tt1", TT1 }, | |
36759679 | 4242 | /* 68ec030 versions of same. */ |
252b5132 RH |
4243 | { "ac0", TT0 }, |
4244 | { "ac1", TT1 }, | |
36759679 | 4245 | /* 68ec030 access control unit, identical to 030 MMU status reg. */ |
252b5132 RH |
4246 | { "acusr", PSR }, |
4247 | ||
4248 | /* Suppressed data and address registers. */ | |
4249 | { "zd0", ZDATA0 }, | |
4250 | { "zd1", ZDATA1 }, | |
4251 | { "zd2", ZDATA2 }, | |
4252 | { "zd3", ZDATA3 }, | |
4253 | { "zd4", ZDATA4 }, | |
4254 | { "zd5", ZDATA5 }, | |
4255 | { "zd6", ZDATA6 }, | |
4256 | { "zd7", ZDATA7 }, | |
4257 | { "za0", ZADDR0 }, | |
4258 | { "za1", ZADDR1 }, | |
4259 | { "za2", ZADDR2 }, | |
4260 | { "za3", ZADDR3 }, | |
4261 | { "za4", ZADDR4 }, | |
4262 | { "za5", ZADDR5 }, | |
4263 | { "za6", ZADDR6 }, | |
4264 | { "za7", ZADDR7 }, | |
4265 | ||
92774660 | 4266 | /* Upper and lower data and address registers, used by macw and msacw. */ |
6da466c7 ILT |
4267 | { "d0l", DATA0L }, |
4268 | { "d1l", DATA1L }, | |
4269 | { "d2l", DATA2L }, | |
4270 | { "d3l", DATA3L }, | |
4271 | { "d4l", DATA4L }, | |
4272 | { "d5l", DATA5L }, | |
4273 | { "d6l", DATA6L }, | |
4274 | { "d7l", DATA7L }, | |
4275 | ||
4276 | { "a0l", ADDR0L }, | |
4277 | { "a1l", ADDR1L }, | |
4278 | { "a2l", ADDR2L }, | |
4279 | { "a3l", ADDR3L }, | |
4280 | { "a4l", ADDR4L }, | |
4281 | { "a5l", ADDR5L }, | |
4282 | { "a6l", ADDR6L }, | |
4283 | { "a7l", ADDR7L }, | |
4284 | ||
4285 | { "d0u", DATA0U }, | |
4286 | { "d1u", DATA1U }, | |
4287 | { "d2u", DATA2U }, | |
4288 | { "d3u", DATA3U }, | |
4289 | { "d4u", DATA4U }, | |
4290 | { "d5u", DATA5U }, | |
4291 | { "d6u", DATA6U }, | |
4292 | { "d7u", DATA7U }, | |
4293 | ||
4294 | { "a0u", ADDR0U }, | |
4295 | { "a1u", ADDR1U }, | |
4296 | { "a2u", ADDR2U }, | |
4297 | { "a3u", ADDR3U }, | |
4298 | { "a4u", ADDR4U }, | |
4299 | { "a5u", ADDR5U }, | |
4300 | { "a6u", ADDR6U }, | |
4301 | { "a7u", ADDR7U }, | |
4302 | ||
252b5132 RH |
4303 | { 0, 0 } |
4304 | }; | |
4305 | ||
4306 | static void | |
31302357 | 4307 | init_regtable (void) |
252b5132 RH |
4308 | { |
4309 | int i; | |
4310 | for (i = 0; init_table[i].name; i++) | |
4311 | insert_reg (init_table[i].name, init_table[i].number); | |
4312 | } | |
4313 | ||
252b5132 | 4314 | void |
31302357 | 4315 | md_assemble (char *str) |
252b5132 RH |
4316 | { |
4317 | const char *er; | |
4318 | short *fromP; | |
4319 | char *toP = NULL; | |
4320 | int m, n = 0; | |
4321 | char *to_beg_P; | |
4322 | int shorts_this_frag; | |
4323 | fixS *fixP; | |
4324 | ||
266abb8f NS |
4325 | if (!selected_cpu && !selected_arch) |
4326 | { | |
4327 | /* We've not selected an architecture yet. Set the default | |
4328 | now. We do this lazily so that an initial .cpu or .arch directive | |
4329 | can specify. */ | |
4330 | if (!m68k_set_cpu (TARGET_CPU, 1, 1)) | |
4331 | as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); | |
4332 | } | |
4333 | if (!initialized) | |
4334 | m68k_init_arch (); | |
3739860c | 4335 | |
252b5132 RH |
4336 | /* In MRI mode, the instruction and operands are separated by a |
4337 | space. Anything following the operands is a comment. The label | |
4338 | has already been removed. */ | |
4339 | if (flag_mri) | |
4340 | { | |
4341 | char *s; | |
4342 | int fields = 0; | |
4343 | int infield = 0; | |
4344 | int inquote = 0; | |
4345 | ||
4346 | for (s = str; *s != '\0'; s++) | |
4347 | { | |
4348 | if ((*s == ' ' || *s == '\t') && ! inquote) | |
4349 | { | |
4350 | if (infield) | |
4351 | { | |
4352 | ++fields; | |
4353 | if (fields >= 2) | |
4354 | { | |
4355 | *s = '\0'; | |
4356 | break; | |
4357 | } | |
4358 | infield = 0; | |
4359 | } | |
4360 | } | |
4361 | else | |
4362 | { | |
4363 | if (! infield) | |
4364 | infield = 1; | |
4365 | if (*s == '\'') | |
4366 | inquote = ! inquote; | |
4367 | } | |
4368 | } | |
4369 | } | |
4370 | ||
31302357 | 4371 | memset (&the_ins, '\0', sizeof (the_ins)); |
252b5132 RH |
4372 | m68k_ip (str); |
4373 | er = the_ins.error; | |
4374 | if (!er) | |
4375 | { | |
4376 | for (n = 0; n < the_ins.numargs; n++) | |
4377 | if (the_ins.operands[n].error) | |
4378 | { | |
4379 | er = the_ins.operands[n].error; | |
4380 | break; | |
4381 | } | |
4382 | } | |
4383 | if (er) | |
4384 | { | |
4385 | as_bad (_("%s -- statement `%s' ignored"), er, str); | |
4386 | return; | |
4387 | } | |
4388 | ||
4389 | /* If there is a current label, record that it marks an instruction. */ | |
4390 | if (current_label != NULL) | |
4391 | { | |
4392 | current_label->text = 1; | |
4393 | current_label = NULL; | |
4394 | } | |
4395 | ||
f27a3839 AS |
4396 | #ifdef OBJ_ELF |
4397 | /* Tie dwarf2 debug info to the address at the start of the insn. */ | |
4398 | dwarf2_emit_insn (0); | |
4399 | #endif | |
4400 | ||
252b5132 RH |
4401 | if (the_ins.nfrag == 0) |
4402 | { | |
36759679 | 4403 | /* No frag hacking involved; just put it out. */ |
252b5132 RH |
4404 | toP = frag_more (2 * the_ins.numo); |
4405 | fromP = &the_ins.opcode[0]; | |
4406 | for (m = the_ins.numo; m; --m) | |
4407 | { | |
4408 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4409 | toP += 2; | |
4410 | fromP++; | |
4411 | } | |
36759679 | 4412 | /* Put out symbol-dependent info. */ |
252b5132 RH |
4413 | for (m = 0; m < the_ins.nrel; m++) |
4414 | { | |
4415 | switch (the_ins.reloc[m].wid) | |
4416 | { | |
4417 | case 'B': | |
4418 | n = 1; | |
4419 | break; | |
4420 | case 'b': | |
4421 | n = 1; | |
4422 | break; | |
4423 | case '3': | |
4424 | n = 1; | |
4425 | break; | |
4426 | case 'w': | |
4427 | case 'W': | |
4428 | n = 2; | |
4429 | break; | |
4430 | case 'l': | |
4431 | n = 4; | |
4432 | break; | |
4433 | default: | |
4434 | as_fatal (_("Don't know how to figure width of %c in md_assemble()"), | |
4435 | the_ins.reloc[m].wid); | |
4436 | } | |
4437 | ||
4438 | fixP = fix_new_exp (frag_now, | |
4439 | ((toP - frag_now->fr_literal) | |
4440 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4441 | n, | |
4442 | &the_ins.reloc[m].exp, | |
4443 | the_ins.reloc[m].pcrel, | |
4444 | get_reloc_code (n, the_ins.reloc[m].pcrel, | |
4445 | the_ins.reloc[m].pic_reloc)); | |
4446 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4447 | if (the_ins.reloc[m].wid == 'B') | |
4448 | fixP->fx_signed = 1; | |
4449 | } | |
4450 | return; | |
4451 | } | |
4452 | ||
36759679 | 4453 | /* There's some frag hacking. */ |
fbe572f9 AM |
4454 | { |
4455 | /* Calculate the max frag size. */ | |
4456 | int wid; | |
4457 | ||
4458 | wid = 2 * the_ins.fragb[0].fragoff; | |
4459 | for (n = 1; n < the_ins.nfrag; n++) | |
4460 | wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4461 | /* frag_var part. */ | |
cac27205 | 4462 | wid += FRAG_VAR_SIZE; |
fbe572f9 AM |
4463 | /* Make sure the whole insn fits in one chunk, in particular that |
4464 | the var part is attached, as we access one byte before the | |
4465 | variable frag for byte branches. */ | |
4466 | frag_grow (wid); | |
4467 | } | |
4468 | ||
252b5132 RH |
4469 | for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) |
4470 | { | |
4471 | int wid; | |
4472 | ||
4473 | if (n == 0) | |
4474 | wid = 2 * the_ins.fragb[n].fragoff; | |
4475 | else | |
4476 | wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4477 | toP = frag_more (wid); | |
4478 | to_beg_P = toP; | |
4479 | shorts_this_frag = 0; | |
4480 | for (m = wid / 2; m; --m) | |
4481 | { | |
4482 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4483 | toP += 2; | |
4484 | fromP++; | |
4485 | shorts_this_frag++; | |
4486 | } | |
4487 | for (m = 0; m < the_ins.nrel; m++) | |
4488 | { | |
4489 | if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) | |
4490 | { | |
4491 | the_ins.reloc[m].n -= 2 * shorts_this_frag; | |
4492 | break; | |
4493 | } | |
4494 | wid = the_ins.reloc[m].wid; | |
4495 | if (wid == 0) | |
4496 | continue; | |
4497 | the_ins.reloc[m].wid = 0; | |
4498 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4499 | ||
4500 | fixP = fix_new_exp (frag_now, | |
4501 | ((toP - frag_now->fr_literal) | |
4502 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4503 | wid, | |
4504 | &the_ins.reloc[m].exp, | |
4505 | the_ins.reloc[m].pcrel, | |
4506 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4507 | the_ins.reloc[m].pic_reloc)); | |
4508 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4509 | } | |
cac27205 | 4510 | (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, |
252b5132 RH |
4511 | (relax_substateT) (the_ins.fragb[n].fragty), |
4512 | the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); | |
4513 | } | |
28a0da39 AM |
4514 | gas_assert (the_ins.nfrag >= 1); |
4515 | n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff; | |
252b5132 RH |
4516 | shorts_this_frag = 0; |
4517 | if (n) | |
4518 | { | |
055d1eb0 | 4519 | toP = frag_more (n * 2); |
252b5132 RH |
4520 | while (n--) |
4521 | { | |
4522 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4523 | toP += 2; | |
4524 | fromP++; | |
4525 | shorts_this_frag++; | |
4526 | } | |
4527 | } | |
4528 | for (m = 0; m < the_ins.nrel; m++) | |
4529 | { | |
4530 | int wid; | |
4531 | ||
4532 | wid = the_ins.reloc[m].wid; | |
4533 | if (wid == 0) | |
4534 | continue; | |
4535 | the_ins.reloc[m].wid = 0; | |
4536 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4537 | ||
4538 | fixP = fix_new_exp (frag_now, | |
4539 | ((the_ins.reloc[m].n + toP - frag_now->fr_literal) | |
4540 | - shorts_this_frag * 2), | |
4541 | wid, | |
4542 | &the_ins.reloc[m].exp, | |
4543 | the_ins.reloc[m].pcrel, | |
4544 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4545 | the_ins.reloc[m].pic_reloc)); | |
4546 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4547 | } | |
4548 | } | |
4549 | ||
60fed2d3 NC |
4550 | /* Comparison function used by qsort to rank the opcode entries by name. */ |
4551 | ||
4552 | static int | |
4553 | m68k_compare_opcode (const void * v1, const void * v2) | |
4554 | { | |
4555 | struct m68k_opcode * op1, * op2; | |
4556 | int ret; | |
4557 | ||
03b13e59 NC |
4558 | if (v1 == v2) |
4559 | return 0; | |
4560 | ||
60fed2d3 NC |
4561 | op1 = *(struct m68k_opcode **) v1; |
4562 | op2 = *(struct m68k_opcode **) v2; | |
4563 | ||
4564 | /* Compare the two names. If different, return the comparison. | |
4565 | If the same, return the order they are in the opcode table. */ | |
4566 | ret = strcmp (op1->name, op2->name); | |
4567 | if (ret) | |
4568 | return ret; | |
4569 | if (op1 < op2) | |
4570 | return -1; | |
03b13e59 | 4571 | return 1; |
60fed2d3 NC |
4572 | } |
4573 | ||
252b5132 | 4574 | void |
60fed2d3 | 4575 | md_begin (void) |
252b5132 | 4576 | { |
60fed2d3 NC |
4577 | const struct m68k_opcode *ins; |
4578 | struct m68k_incant *hack, *slak; | |
4579 | const char *retval = 0; /* Empty string, or error msg text. */ | |
4580 | int i; | |
4581 | ||
4582 | /* Set up hash tables with 68000 instructions. | |
4583 | similar to what the vax assembler does. */ | |
252b5132 RH |
4584 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make |
4585 | a copy of it at runtime, adding in the information we want but isn't | |
4586 | there. I think it'd be better to have an awk script hack the table | |
4587 | at compile time. Or even just xstr the table and use it as-is. But | |
4588 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
4589 | names. */ | |
4590 | ||
252b5132 RH |
4591 | if (flag_mri) |
4592 | { | |
4593 | flag_reg_prefix_optional = 1; | |
4594 | m68k_abspcadd = 1; | |
4595 | if (! m68k_rel32_from_cmdline) | |
4596 | m68k_rel32 = 0; | |
4597 | } | |
4598 | ||
60fed2d3 NC |
4599 | /* First sort the opcode table into alphabetical order to seperate |
4600 | the order that the assembler wants to see the opcodes from the | |
4601 | order that the disassembler wants to see them. */ | |
4602 | m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); | |
4603 | if (!m68k_sorted_opcodes) | |
4604 | as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"), | |
045b540e | 4605 | m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes))); |
60fed2d3 NC |
4606 | |
4607 | for (i = m68k_numopcodes; i--;) | |
4608 | m68k_sorted_opcodes[i] = m68k_opcodes + i; | |
4609 | ||
4610 | qsort (m68k_sorted_opcodes, m68k_numopcodes, | |
4611 | sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); | |
4612 | ||
252b5132 RH |
4613 | op_hash = hash_new (); |
4614 | ||
4615 | obstack_begin (&robyn, 4000); | |
4616 | for (i = 0; i < m68k_numopcodes; i++) | |
4617 | { | |
78aff5a5 | 4618 | hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4619 | do |
4620 | { | |
60fed2d3 NC |
4621 | ins = m68k_sorted_opcodes[i]; |
4622 | ||
afa2158f NS |
4623 | /* We must enter all insns into the table, because .arch and |
4624 | .cpu directives can change things. */ | |
252b5132 | 4625 | slak->m_operands = ins->args; |
252b5132 RH |
4626 | slak->m_arch = ins->arch; |
4627 | slak->m_opcode = ins->opcode; | |
3739860c | 4628 | |
afa2158f NS |
4629 | /* In most cases we can determine the number of opcode words |
4630 | by checking the second word of the mask. Unfortunately | |
4631 | some instructions have 2 opcode words, but no fixed bits | |
4632 | in the second word. A leading dot in the operands | |
4633 | string also indicates 2 opcodes. */ | |
4634 | if (*slak->m_operands == '.') | |
4635 | { | |
4636 | slak->m_operands++; | |
4637 | slak->m_codenum = 2; | |
4638 | } | |
4639 | else if (ins->match & 0xffffL) | |
4640 | slak->m_codenum = 2; | |
4641 | else | |
4642 | slak->m_codenum = 1; | |
4643 | slak->m_opnum = strlen (slak->m_operands) / 2; | |
3739860c | 4644 | |
252b5132 | 4645 | if (i + 1 != m68k_numopcodes |
60fed2d3 | 4646 | && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) |
252b5132 | 4647 | { |
60fed2d3 | 4648 | slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4649 | i++; |
4650 | } | |
4651 | else | |
4652 | slak->m_next = 0; | |
4653 | slak = slak->m_next; | |
4654 | } | |
4655 | while (slak); | |
4656 | ||
4657 | retval = hash_insert (op_hash, ins->name, (char *) hack); | |
4658 | if (retval) | |
4659 | as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); | |
4660 | } | |
4661 | ||
4662 | for (i = 0; i < m68k_numaliases; i++) | |
4663 | { | |
4664 | const char *name = m68k_opcode_aliases[i].primary; | |
4665 | const char *alias = m68k_opcode_aliases[i].alias; | |
5a49b8ac | 4666 | void *val = hash_find (op_hash, name); |
60fed2d3 | 4667 | |
252b5132 RH |
4668 | if (!val) |
4669 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4670 | retval = hash_insert (op_hash, alias, val); | |
4671 | if (retval) | |
4672 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4673 | } | |
4674 | ||
4675 | /* In MRI mode, all unsized branches are variable sized. Normally, | |
4676 | they are word sized. */ | |
4677 | if (flag_mri) | |
4678 | { | |
4679 | static struct m68k_opcode_alias mri_aliases[] = | |
4680 | { | |
4681 | { "bhi", "jhi", }, | |
4682 | { "bls", "jls", }, | |
4683 | { "bcc", "jcc", }, | |
4684 | { "bcs", "jcs", }, | |
4685 | { "bne", "jne", }, | |
4686 | { "beq", "jeq", }, | |
4687 | { "bvc", "jvc", }, | |
4688 | { "bvs", "jvs", }, | |
4689 | { "bpl", "jpl", }, | |
4690 | { "bmi", "jmi", }, | |
4691 | { "bge", "jge", }, | |
4692 | { "blt", "jlt", }, | |
4693 | { "bgt", "jgt", }, | |
4694 | { "ble", "jle", }, | |
4695 | { "bra", "jra", }, | |
4696 | { "bsr", "jbsr", }, | |
4697 | }; | |
4698 | ||
8fce3f5e AM |
4699 | for (i = 0; |
4700 | i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); | |
4701 | i++) | |
252b5132 RH |
4702 | { |
4703 | const char *name = mri_aliases[i].primary; | |
4704 | const char *alias = mri_aliases[i].alias; | |
5a49b8ac | 4705 | void *val = hash_find (op_hash, name); |
60fed2d3 | 4706 | |
252b5132 RH |
4707 | if (!val) |
4708 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4709 | retval = hash_jam (op_hash, alias, val); | |
4710 | if (retval) | |
4711 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4712 | } | |
4713 | } | |
4714 | ||
8fce3f5e | 4715 | for (i = 0; i < (int) sizeof (notend_table); i++) |
252b5132 RH |
4716 | { |
4717 | notend_table[i] = 0; | |
4718 | alt_notend_table[i] = 0; | |
4719 | } | |
60fed2d3 | 4720 | |
252b5132 RH |
4721 | notend_table[','] = 1; |
4722 | notend_table['{'] = 1; | |
4723 | notend_table['}'] = 1; | |
4724 | alt_notend_table['a'] = 1; | |
4725 | alt_notend_table['A'] = 1; | |
4726 | alt_notend_table['d'] = 1; | |
4727 | alt_notend_table['D'] = 1; | |
4728 | alt_notend_table['#'] = 1; | |
4729 | alt_notend_table['&'] = 1; | |
4730 | alt_notend_table['f'] = 1; | |
4731 | alt_notend_table['F'] = 1; | |
4732 | #ifdef REGISTER_PREFIX | |
4733 | alt_notend_table[REGISTER_PREFIX] = 1; | |
4734 | #endif | |
4735 | ||
4736 | /* We need to put '(' in alt_notend_table to handle | |
60fed2d3 | 4737 | cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ |
252b5132 RH |
4738 | alt_notend_table['('] = 1; |
4739 | ||
4740 | /* We need to put '@' in alt_notend_table to handle | |
60fed2d3 | 4741 | cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ |
252b5132 RH |
4742 | alt_notend_table['@'] = 1; |
4743 | ||
4744 | /* We need to put digits in alt_notend_table to handle | |
60fed2d3 | 4745 | bfextu %d0{24:1},%d0 */ |
252b5132 RH |
4746 | alt_notend_table['0'] = 1; |
4747 | alt_notend_table['1'] = 1; | |
4748 | alt_notend_table['2'] = 1; | |
4749 | alt_notend_table['3'] = 1; | |
4750 | alt_notend_table['4'] = 1; | |
4751 | alt_notend_table['5'] = 1; | |
4752 | alt_notend_table['6'] = 1; | |
4753 | alt_notend_table['7'] = 1; | |
4754 | alt_notend_table['8'] = 1; | |
4755 | alt_notend_table['9'] = 1; | |
4756 | ||
4757 | #ifndef MIT_SYNTAX_ONLY | |
4758 | /* Insert pseudo ops, these have to go into the opcode table since | |
36759679 | 4759 | gas expects pseudo ops to start with a dot. */ |
252b5132 RH |
4760 | { |
4761 | int n = 0; | |
60fed2d3 | 4762 | |
252b5132 RH |
4763 | while (mote_pseudo_table[n].poc_name) |
4764 | { | |
60fed2d3 | 4765 | hack = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4766 | hash_insert (op_hash, |
4767 | mote_pseudo_table[n].poc_name, (char *) hack); | |
4768 | hack->m_operands = 0; | |
4769 | hack->m_opnum = n; | |
4770 | n++; | |
4771 | } | |
4772 | } | |
4773 | #endif | |
4774 | ||
4775 | init_regtable (); | |
4776 | ||
4777 | #ifdef OBJ_ELF | |
4778 | record_alignment (text_section, 2); | |
4779 | record_alignment (data_section, 2); | |
4780 | record_alignment (bss_section, 2); | |
4781 | #endif | |
4782 | } | |
4783 | ||
252b5132 RH |
4784 | \f |
4785 | /* This is called when a label is defined. */ | |
4786 | ||
4787 | void | |
31302357 | 4788 | m68k_frob_label (symbolS *sym) |
252b5132 RH |
4789 | { |
4790 | struct label_line *n; | |
4791 | ||
4792 | n = (struct label_line *) xmalloc (sizeof *n); | |
4793 | n->next = labels; | |
4794 | n->label = sym; | |
4795 | as_where (&n->file, &n->line); | |
4796 | n->text = 0; | |
4797 | labels = n; | |
4798 | current_label = n; | |
07a53e5c RH |
4799 | |
4800 | #ifdef OBJ_ELF | |
4801 | dwarf2_emit_label (sym); | |
4802 | #endif | |
252b5132 RH |
4803 | } |
4804 | ||
4805 | /* This is called when a value that is not an instruction is emitted. */ | |
4806 | ||
4807 | void | |
31302357 | 4808 | m68k_flush_pending_output (void) |
252b5132 RH |
4809 | { |
4810 | current_label = NULL; | |
4811 | } | |
4812 | ||
4813 | /* This is called at the end of the assembly, when the final value of | |
4814 | the label is known. We warn if this is a text symbol aligned at an | |
4815 | odd location. */ | |
4816 | ||
4817 | void | |
31302357 | 4818 | m68k_frob_symbol (symbolS *sym) |
252b5132 RH |
4819 | { |
4820 | if (S_GET_SEGMENT (sym) == reg_section | |
4821 | && (int) S_GET_VALUE (sym) < 0) | |
4822 | { | |
4823 | S_SET_SEGMENT (sym, absolute_section); | |
4824 | S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); | |
4825 | } | |
4826 | else if ((S_GET_VALUE (sym) & 1) != 0) | |
4827 | { | |
4828 | struct label_line *l; | |
4829 | ||
4830 | for (l = labels; l != NULL; l = l->next) | |
4831 | { | |
4832 | if (l->label == sym) | |
4833 | { | |
4834 | if (l->text) | |
4835 | as_warn_where (l->file, l->line, | |
4836 | _("text label `%s' aligned to odd boundary"), | |
4837 | S_GET_NAME (sym)); | |
4838 | break; | |
4839 | } | |
4840 | } | |
4841 | } | |
4842 | } | |
4843 | \f | |
4844 | /* This is called if we go in or out of MRI mode because of the .mri | |
4845 | pseudo-op. */ | |
4846 | ||
4847 | void | |
31302357 | 4848 | m68k_mri_mode_change (int on) |
252b5132 RH |
4849 | { |
4850 | if (on) | |
4851 | { | |
4852 | if (! flag_reg_prefix_optional) | |
4853 | { | |
4854 | flag_reg_prefix_optional = 1; | |
4855 | #ifdef REGISTER_PREFIX | |
4856 | init_regtable (); | |
4857 | #endif | |
4858 | } | |
4859 | m68k_abspcadd = 1; | |
4860 | if (! m68k_rel32_from_cmdline) | |
4861 | m68k_rel32 = 0; | |
4862 | } | |
4863 | else | |
4864 | { | |
4865 | if (! reg_prefix_optional_seen) | |
4866 | { | |
4867 | #ifdef REGISTER_PREFIX_OPTIONAL | |
4868 | flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
4869 | #else | |
4870 | flag_reg_prefix_optional = 0; | |
4871 | #endif | |
4872 | #ifdef REGISTER_PREFIX | |
4873 | init_regtable (); | |
4874 | #endif | |
4875 | } | |
4876 | m68k_abspcadd = 0; | |
4877 | if (! m68k_rel32_from_cmdline) | |
4878 | m68k_rel32 = 1; | |
4879 | } | |
4880 | } | |
4881 | ||
252b5132 | 4882 | char * |
31302357 | 4883 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 4884 | { |
499ac353 | 4885 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
4886 | } |
4887 | ||
4888 | void | |
31302357 | 4889 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
4890 | { |
4891 | number_to_chars_bigendian (buf, val, n); | |
4892 | } | |
4893 | ||
94f592af | 4894 | void |
55cf6793 | 4895 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 4896 | { |
bbe8ef22 | 4897 | offsetT val = *valP; |
252b5132 RH |
4898 | addressT upper_limit; |
4899 | offsetT lower_limit; | |
4900 | ||
4901 | /* This is unnecessary but it convinces the native rs6000 compiler | |
4902 | to generate the code we want. */ | |
4903 | char *buf = fixP->fx_frag->fr_literal; | |
4904 | buf += fixP->fx_where; | |
36759679 | 4905 | /* End ibm compiler workaround. */ |
252b5132 | 4906 | |
bd17c2c3 | 4907 | val = SEXT (val); |
252b5132 | 4908 | |
94f592af NC |
4909 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
4910 | fixP->fx_done = 1; | |
4911 | ||
252b5132 RH |
4912 | #ifdef OBJ_ELF |
4913 | if (fixP->fx_addsy) | |
4914 | { | |
4915 | memset (buf, 0, fixP->fx_size); | |
36759679 | 4916 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
4917 | |
4918 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4919 | && !S_IS_DEFINED (fixP->fx_addsy) | |
4920 | && !S_IS_WEAK (fixP->fx_addsy)) | |
4921 | S_SET_WEAK (fixP->fx_addsy); | |
cf869cce NC |
4922 | |
4923 | switch (fixP->fx_r_type) | |
4924 | { | |
4925 | case BFD_RELOC_68K_TLS_GD32: | |
4926 | case BFD_RELOC_68K_TLS_GD16: | |
4927 | case BFD_RELOC_68K_TLS_GD8: | |
4928 | case BFD_RELOC_68K_TLS_LDM32: | |
4929 | case BFD_RELOC_68K_TLS_LDM16: | |
4930 | case BFD_RELOC_68K_TLS_LDM8: | |
4931 | case BFD_RELOC_68K_TLS_LDO32: | |
4932 | case BFD_RELOC_68K_TLS_LDO16: | |
4933 | case BFD_RELOC_68K_TLS_LDO8: | |
4934 | case BFD_RELOC_68K_TLS_IE32: | |
4935 | case BFD_RELOC_68K_TLS_IE16: | |
4936 | case BFD_RELOC_68K_TLS_IE8: | |
4937 | case BFD_RELOC_68K_TLS_LE32: | |
4938 | case BFD_RELOC_68K_TLS_LE16: | |
4939 | case BFD_RELOC_68K_TLS_LE8: | |
4940 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4941 | break; | |
4942 | ||
4943 | default: | |
4944 | break; | |
4945 | } | |
4946 | ||
252b5132 RH |
4947 | return; |
4948 | } | |
22184a77 | 4949 | #elif defined(OBJ_AOUT) |
1c3f20b4 | 4950 | /* PR gas/3041 Do not fix frags referencing a weak symbol. */ |
22184a77 NC |
4951 | if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)) |
4952 | { | |
4953 | memset (buf, 0, fixP->fx_size); | |
1c3f20b4 | 4954 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
22184a77 NC |
4955 | return; |
4956 | } | |
252b5132 RH |
4957 | #endif |
4958 | ||
252b5132 RH |
4959 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
4960 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4961 | return; | |
252b5132 RH |
4962 | |
4963 | switch (fixP->fx_size) | |
4964 | { | |
94f592af NC |
4965 | /* The cast to offsetT below are necessary to make code |
4966 | correct for machines where ints are smaller than offsetT. */ | |
252b5132 RH |
4967 | case 1: |
4968 | *buf++ = val; | |
4969 | upper_limit = 0x7f; | |
4970 | lower_limit = - (offsetT) 0x80; | |
4971 | break; | |
4972 | case 2: | |
4973 | *buf++ = (val >> 8); | |
4974 | *buf++ = val; | |
4975 | upper_limit = 0x7fff; | |
4976 | lower_limit = - (offsetT) 0x8000; | |
4977 | break; | |
4978 | case 4: | |
4979 | *buf++ = (val >> 24); | |
4980 | *buf++ = (val >> 16); | |
4981 | *buf++ = (val >> 8); | |
4982 | *buf++ = val; | |
4983 | upper_limit = 0x7fffffff; | |
36759679 | 4984 | lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ |
252b5132 RH |
4985 | break; |
4986 | default: | |
4987 | BAD_CASE (fixP->fx_size); | |
4988 | } | |
4989 | ||
4990 | /* Fix up a negative reloc. */ | |
4991 | if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) | |
4992 | { | |
4993 | fixP->fx_addsy = fixP->fx_subsy; | |
4994 | fixP->fx_subsy = NULL; | |
4995 | fixP->fx_tcbit = 1; | |
4996 | } | |
4997 | ||
4998 | /* For non-pc-relative values, it's conceivable we might get something | |
4999 | like "0xff" for a byte field. So extend the upper part of the range | |
5000 | to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", | |
5001 | so that we can do any range checking at all. */ | |
5002 | if (! fixP->fx_pcrel && ! fixP->fx_signed) | |
5003 | upper_limit = upper_limit * 2 + 1; | |
5004 | ||
5005 | if ((addressT) val > upper_limit | |
5006 | && (val > 0 || val < lower_limit)) | |
2b878742 NS |
5007 | as_bad_where (fixP->fx_file, fixP->fx_line, |
5008 | _("value %ld out of range"), (long)val); | |
252b5132 RH |
5009 | |
5010 | /* A one byte PC-relative reloc means a short branch. We can't use | |
5011 | a short branch with a value of 0 or -1, because those indicate | |
5012 | different opcodes (branches with longer offsets). fixup_segment | |
5013 | in write.c may have clobbered fx_pcrel, so we need to examine the | |
5014 | reloc type. */ | |
5015 | if ((fixP->fx_pcrel | |
7be1c489 | 5016 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
252b5132 RH |
5017 | && fixP->fx_size == 1 |
5018 | && (fixP->fx_addsy == NULL | |
5019 | || S_IS_DEFINED (fixP->fx_addsy)) | |
5020 | && (val == 0 || val == -1)) | |
2b878742 NS |
5021 | as_bad_where (fixP->fx_file, fixP->fx_line, |
5022 | _("invalid byte branch offset")); | |
252b5132 RH |
5023 | } |
5024 | ||
252b5132 RH |
5025 | /* *fragP has been relaxed to its final size, and now needs to have |
5026 | the bytes inside it modified to conform to the new size There is UGLY | |
5027 | MAGIC here. .. | |
5028 | */ | |
5029 | static void | |
31302357 | 5030 | md_convert_frag_1 (fragS *fragP) |
252b5132 RH |
5031 | { |
5032 | long disp; | |
2b878742 | 5033 | fixS *fixP = NULL; |
252b5132 RH |
5034 | |
5035 | /* Address in object code of the displacement. */ | |
ed9e98c2 | 5036 | int object_address = fragP->fr_fix + fragP->fr_address; |
252b5132 RH |
5037 | |
5038 | /* Address in gas core of the place to store the displacement. */ | |
5039 | /* This convinces the native rs6000 compiler to generate the code we | |
92774660 | 5040 | want. */ |
ed9e98c2 | 5041 | char *buffer_address = fragP->fr_literal; |
252b5132 | 5042 | buffer_address += fragP->fr_fix; |
36759679 | 5043 | /* End ibm compiler workaround. */ |
252b5132 RH |
5044 | |
5045 | /* The displacement of the address, from current location. */ | |
5046 | disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; | |
5047 | disp = (disp + fragP->fr_offset) - object_address; | |
5048 | ||
252b5132 RH |
5049 | switch (fragP->fr_subtype) |
5050 | { | |
151337e8 NC |
5051 | case TAB (BRANCHBWL, BYTE): |
5052 | case TAB (BRABSJUNC, BYTE): | |
5053 | case TAB (BRABSJCOND, BYTE): | |
5054 | case TAB (BRANCHBW, BYTE): | |
cac27205 | 5055 | case TAB (BRANCHBWPL, BYTE): |
252b5132 RH |
5056 | know (issbyte (disp)); |
5057 | if (disp == 0) | |
b091f402 AM |
5058 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5059 | _("short branch with zero offset: use :w")); | |
151337e8 | 5060 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 5061 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 5062 | fixP->fx_pcrel_adjust = -1; |
252b5132 | 5063 | break; |
151337e8 NC |
5064 | case TAB (BRANCHBWL, SHORT): |
5065 | case TAB (BRABSJUNC, SHORT): | |
5066 | case TAB (BRABSJCOND, SHORT): | |
5067 | case TAB (BRANCHBW, SHORT): | |
cac27205 | 5068 | case TAB (BRANCHBWPL, SHORT): |
252b5132 | 5069 | fragP->fr_opcode[1] = 0x00; |
2b878742 NS |
5070 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5071 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5072 | fragP->fr_fix += 2; |
5073 | break; | |
5074 | case TAB (BRANCHBWL, LONG): | |
5075 | fragP->fr_opcode[1] = (char) 0xFF; | |
2b878742 NS |
5076 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5077 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
151337e8 | 5078 | fragP->fr_fix += 4; |
252b5132 | 5079 | break; |
cac27205 NC |
5080 | case TAB (BRANCHBWPL, LONG): |
5081 | /* Here we are converting an unconditional branch into a pair of | |
5082 | conditional branches, in order to get the range. */ | |
5083 | fragP->fr_opcode[0] = 0x66; /* bne */ | |
5084 | fragP->fr_opcode[1] = 0xFF; | |
5085 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
5086 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
5087 | fixP->fx_file = fragP->fr_file; | |
5088 | fixP->fx_line = fragP->fr_line; | |
5089 | fragP->fr_fix += 4; /* Skip first offset */ | |
5090 | buffer_address += 4; | |
5091 | *buffer_address++ = 0x67; /* beq */ | |
5092 | *buffer_address++ = 0xff; | |
5093 | fragP->fr_fix += 2; /* Skip second branch opcode */ | |
5094 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
5095 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
5096 | fragP->fr_fix += 4; | |
5097 | break; | |
151337e8 NC |
5098 | case TAB (BRABSJUNC, LONG): |
5099 | if (fragP->fr_opcode[0] == 0x61) /* jbsr */ | |
252b5132 | 5100 | { |
36759679 | 5101 | if (flag_keep_pcrel) |
2b878742 NS |
5102 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5103 | _("Conversion of PC relative BSR to absolute JSR")); | |
151337e8 | 5104 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 5105 | fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ |
2b878742 NS |
5106 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5107 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 NC |
5108 | fragP->fr_fix += 4; |
5109 | } | |
5110 | else if (fragP->fr_opcode[0] == 0x60) /* jbra */ | |
5111 | { | |
36759679 | 5112 | if (flag_keep_pcrel) |
2b878742 NS |
5113 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5114 | _("Conversion of PC relative branch to absolute jump")); | |
151337e8 | 5115 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 5116 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ |
2b878742 NS |
5117 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5118 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 | 5119 | fragP->fr_fix += 4; |
252b5132 RH |
5120 | } |
5121 | else | |
5122 | { | |
151337e8 NC |
5123 | /* This cannot happen, because jbsr and jbra are the only two |
5124 | unconditional branches. */ | |
5125 | abort (); | |
252b5132 RH |
5126 | } |
5127 | break; | |
151337e8 | 5128 | case TAB (BRABSJCOND, LONG): |
36759679 | 5129 | if (flag_keep_pcrel) |
2b878742 NS |
5130 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5131 | _("Conversion of PC relative conditional branch to absolute jump")); | |
92774660 | 5132 | |
36759679 NC |
5133 | /* Only Bcc 68000 instructions can come here |
5134 | Change bcc into b!cc/jmp absl long. */ | |
5135 | fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ | |
5136 | fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ | |
252b5132 RH |
5137 | |
5138 | /* JF: these used to be fr_opcode[2,3], but they may be in a | |
67c1ffbe | 5139 | different frag, in which case referring to them is a no-no. |
92774660 | 5140 | Only fr_opcode[0,1] are guaranteed to work. */ |
252b5132 RH |
5141 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
5142 | *buffer_address++ = (char) 0xf9; | |
36759679 | 5143 | fragP->fr_fix += 2; /* Account for jmp instruction. */ |
2b878742 NS |
5144 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5145 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 NC |
5146 | fragP->fr_fix += 4; |
5147 | break; | |
5148 | case TAB (FBRANCH, SHORT): | |
5149 | know ((fragP->fr_opcode[1] & 0x40) == 0); | |
2b878742 NS |
5150 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5151 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5152 | fragP->fr_fix += 2; |
5153 | break; | |
5154 | case TAB (FBRANCH, LONG): | |
36759679 | 5155 | fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ |
2b878742 NS |
5156 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5157 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
252b5132 | 5158 | fragP->fr_fix += 4; |
252b5132 | 5159 | break; |
151337e8 NC |
5160 | case TAB (DBCCLBR, SHORT): |
5161 | case TAB (DBCCABSJ, SHORT): | |
2b878742 NS |
5162 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5163 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5164 | fragP->fr_fix += 2; |
5165 | break; | |
5166 | case TAB (DBCCLBR, LONG): | |
36759679 NC |
5167 | /* Only DBcc instructions can come here. |
5168 | Change dbcc into dbcc/bral. | |
5169 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
36759679 | 5170 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
252b5132 | 5171 | *buffer_address++ = 0x04; |
36759679 | 5172 | *buffer_address++ = 0x60; /* Put in bra pc+6. */ |
252b5132 | 5173 | *buffer_address++ = 0x06; |
151337e8 NC |
5174 | *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ |
5175 | *buffer_address++ = (char) 0xff; | |
252b5132 | 5176 | |
36759679 | 5177 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
2b878742 NS |
5178 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5179 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
252b5132 | 5180 | fragP->fr_fix += 4; |
252b5132 | 5181 | break; |
151337e8 | 5182 | case TAB (DBCCABSJ, LONG): |
36759679 NC |
5183 | /* Only DBcc instructions can come here. |
5184 | Change dbcc into dbcc/jmp. | |
5185 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
5186 | if (flag_keep_pcrel) | |
2b878742 NS |
5187 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5188 | _("Conversion of PC relative conditional branch to absolute jump")); | |
151337e8 | 5189 | |
36759679 | 5190 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
151337e8 | 5191 | *buffer_address++ = 0x04; |
36759679 | 5192 | *buffer_address++ = 0x60; /* Put in bra pc + 6. */ |
151337e8 | 5193 | *buffer_address++ = 0x06; |
36759679 | 5194 | *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ |
151337e8 NC |
5195 | *buffer_address++ = (char) 0xf9; |
5196 | ||
36759679 | 5197 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
2b878742 NS |
5198 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5199 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
252b5132 | 5200 | fragP->fr_fix += 4; |
252b5132 | 5201 | break; |
151337e8 | 5202 | case TAB (PCREL1632, SHORT): |
252b5132 RH |
5203 | fragP->fr_opcode[1] &= ~0x3F; |
5204 | fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ | |
2b878742 NS |
5205 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, |
5206 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 | 5207 | fragP->fr_fix += 2; |
252b5132 | 5208 | break; |
151337e8 | 5209 | case TAB (PCREL1632, LONG): |
252b5132 RH |
5210 | /* Already set to mode 7.3; this indicates: PC indirect with |
5211 | suppressed index, 32-bit displacement. */ | |
5212 | *buffer_address++ = 0x01; | |
5213 | *buffer_address++ = 0x70; | |
5214 | fragP->fr_fix += 2; | |
151337e8 | 5215 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 5216 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
5217 | fixP->fx_pcrel_adjust = 2; |
5218 | fragP->fr_fix += 4; | |
252b5132 | 5219 | break; |
252b5132 | 5220 | case TAB (PCINDEX, BYTE): |
9c2799c2 | 5221 | gas_assert (fragP->fr_fix >= 2); |
252b5132 | 5222 | buffer_address[-2] &= ~1; |
151337e8 | 5223 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 5224 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 5225 | fixP->fx_pcrel_adjust = 1; |
252b5132 RH |
5226 | break; |
5227 | case TAB (PCINDEX, SHORT): | |
9c2799c2 | 5228 | gas_assert (fragP->fr_fix >= 2); |
252b5132 RH |
5229 | buffer_address[-2] |= 0x1; |
5230 | buffer_address[-1] = 0x20; | |
5231 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, | |
5cbdaa77 | 5232 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
252b5132 | 5233 | fixP->fx_pcrel_adjust = 2; |
151337e8 | 5234 | fragP->fr_fix += 2; |
252b5132 RH |
5235 | break; |
5236 | case TAB (PCINDEX, LONG): | |
9c2799c2 | 5237 | gas_assert (fragP->fr_fix >= 2); |
252b5132 RH |
5238 | buffer_address[-2] |= 0x1; |
5239 | buffer_address[-1] = 0x30; | |
151337e8 | 5240 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 5241 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
5242 | fixP->fx_pcrel_adjust = 2; |
5243 | fragP->fr_fix += 4; | |
5244 | break; | |
5245 | case TAB (ABSTOPCREL, SHORT): | |
2b878742 NS |
5246 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5247 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5248 | fragP->fr_fix += 2; |
5249 | break; | |
5250 | case TAB (ABSTOPCREL, LONG): | |
36759679 | 5251 | if (flag_keep_pcrel) |
025987ea NS |
5252 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5253 | _("Conversion of PC relative displacement to absolute")); | |
151337e8 | 5254 | /* The thing to do here is force it to ABSOLUTE LONG, since |
36759679 | 5255 | ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ |
151337e8 NC |
5256 | if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) |
5257 | abort (); | |
5258 | fragP->fr_opcode[1] &= ~0x3F; | |
5259 | fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ | |
2b878742 NS |
5260 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5261 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 | 5262 | fragP->fr_fix += 4; |
252b5132 | 5263 | break; |
252b5132 | 5264 | } |
2b878742 NS |
5265 | if (fixP) |
5266 | { | |
5267 | fixP->fx_file = fragP->fr_file; | |
5268 | fixP->fx_line = fragP->fr_line; | |
5269 | } | |
252b5132 RH |
5270 | } |
5271 | ||
252b5132 | 5272 | void |
31302357 AS |
5273 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
5274 | segT sec ATTRIBUTE_UNUSED, | |
5275 | fragS *fragP) | |
252b5132 RH |
5276 | { |
5277 | md_convert_frag_1 (fragP); | |
5278 | } | |
252b5132 RH |
5279 | |
5280 | /* Force truly undefined symbols to their maximum size, and generally set up | |
5281 | the frag list to be relaxed | |
5282 | */ | |
5283 | int | |
31302357 | 5284 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 5285 | { |
151337e8 | 5286 | /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ |
252b5132 RH |
5287 | switch (fragP->fr_subtype) |
5288 | { | |
151337e8 | 5289 | case TAB (BRANCHBWL, SZ_UNDEF): |
cac27205 | 5290 | case TAB (BRANCHBWPL, SZ_UNDEF): |
151337e8 | 5291 | case TAB (BRABSJUNC, SZ_UNDEF): |
151337e8 | 5292 | case TAB (BRABSJCOND, SZ_UNDEF): |
252b5132 | 5293 | { |
151337e8 NC |
5294 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
5295 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 5296 | { |
151337e8 NC |
5297 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
5298 | } | |
5299 | else if (flag_short_refs) | |
5300 | { | |
5301 | /* Symbol is undefined and we want short ref. */ | |
5302 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5303 | } |
5304 | else | |
5305 | { | |
151337e8 NC |
5306 | /* Symbol is still undefined. Make it LONG. */ |
5307 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); | |
252b5132 RH |
5308 | } |
5309 | break; | |
151337e8 | 5310 | } |
252b5132 | 5311 | |
151337e8 | 5312 | case TAB (BRANCHBW, SZ_UNDEF): |
252b5132 | 5313 | { |
151337e8 NC |
5314 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
5315 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 5316 | { |
151337e8 | 5317 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
252b5132 RH |
5318 | } |
5319 | else | |
5320 | { | |
151337e8 NC |
5321 | /* Symbol is undefined and we don't have long branches. */ |
5322 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5323 | } |
5324 | break; | |
151337e8 | 5325 | } |
252b5132 | 5326 | |
151337e8 | 5327 | case TAB (FBRANCH, SZ_UNDEF): |
151337e8 NC |
5328 | case TAB (DBCCLBR, SZ_UNDEF): |
5329 | case TAB (DBCCABSJ, SZ_UNDEF): | |
5c65dbc1 | 5330 | case TAB (PCREL1632, SZ_UNDEF): |
252b5132 | 5331 | { |
8ec6253e NC |
5332 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
5333 | && relaxable_symbol (fragP->fr_symbol)) | |
151337e8 | 5334 | || flag_short_refs) |
252b5132 | 5335 | { |
151337e8 | 5336 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
252b5132 RH |
5337 | } |
5338 | else | |
5339 | { | |
151337e8 | 5340 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); |
252b5132 RH |
5341 | } |
5342 | break; | |
151337e8 | 5343 | } |
81d4177b | 5344 | |
252b5132 RH |
5345 | case TAB (PCINDEX, SZ_UNDEF): |
5346 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
151337e8 | 5347 | && relaxable_symbol (fragP->fr_symbol))) |
252b5132 RH |
5348 | { |
5349 | fragP->fr_subtype = TAB (PCINDEX, BYTE); | |
5350 | } | |
5351 | else | |
5352 | { | |
5353 | fragP->fr_subtype = TAB (PCINDEX, LONG); | |
252b5132 RH |
5354 | } |
5355 | break; | |
5356 | ||
151337e8 NC |
5357 | case TAB (ABSTOPCREL, SZ_UNDEF): |
5358 | { | |
5359 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
5360 | && relaxable_symbol (fragP->fr_symbol))) | |
5361 | { | |
5362 | fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); | |
151337e8 NC |
5363 | } |
5364 | else | |
5365 | { | |
5366 | fragP->fr_subtype = TAB (ABSTOPCREL, LONG); | |
151337e8 NC |
5367 | } |
5368 | break; | |
5369 | } | |
5370 | ||
252b5132 RH |
5371 | default: |
5372 | break; | |
5373 | } | |
5374 | ||
151337e8 | 5375 | /* Now that SZ_UNDEF are taken care of, check others. */ |
252b5132 RH |
5376 | switch (fragP->fr_subtype) |
5377 | { | |
151337e8 NC |
5378 | case TAB (BRANCHBWL, BYTE): |
5379 | case TAB (BRABSJUNC, BYTE): | |
5380 | case TAB (BRABSJCOND, BYTE): | |
5381 | case TAB (BRANCHBW, BYTE): | |
252b5132 | 5382 | /* We can't do a short jump to the next instruction, so in that |
ac62c346 AM |
5383 | case we force word mode. If the symbol is at the start of a |
5384 | frag, and it is the next frag with any data in it (usually | |
5385 | this is just the next frag, but assembler listings may | |
5386 | introduce empty frags), we must use word mode. */ | |
5387 | if (fragP->fr_symbol) | |
252b5132 | 5388 | { |
ac62c346 | 5389 | fragS *sym_frag; |
252b5132 | 5390 | |
ac62c346 AM |
5391 | sym_frag = symbol_get_frag (fragP->fr_symbol); |
5392 | if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) | |
252b5132 | 5393 | { |
ac62c346 AM |
5394 | fragS *l; |
5395 | ||
23b7f870 | 5396 | for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) |
ac62c346 AM |
5397 | if (l->fr_fix != 0) |
5398 | break; | |
5399 | if (l == sym_frag) | |
5400 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5401 | } |
5402 | } | |
5403 | break; | |
5404 | default: | |
5405 | break; | |
5406 | } | |
ac62c346 | 5407 | return md_relax_table[fragP->fr_subtype].rlx_length; |
252b5132 RH |
5408 | } |
5409 | ||
5410 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
5411 | /* the bit-field entries in the relocation_info struct plays hell | |
5412 | with the byte-order problems of cross-assembly. So as a hack, | |
5413 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
36759679 | 5414 | you there. -KWK */ |
252b5132 RH |
5415 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes |
5416 | are symbolnum, most sig. byte first. Last byte is broken up with | |
5417 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
5418 | nibble as nuthin. (on Sun 3 at least) */ | |
5419 | /* Translate the internal relocation information into target-specific | |
92774660 | 5420 | format. */ |
252b5132 RH |
5421 | #ifdef comment |
5422 | void | |
31302357 | 5423 | md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) |
252b5132 | 5424 | { |
36759679 | 5425 | /* This is easy. */ |
252b5132 | 5426 | md_number_to_chars (the_bytes, ri->r_address, 4); |
36759679 | 5427 | /* Now the fun stuff. */ |
252b5132 | 5428 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; |
36759679 NC |
5429 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; |
5430 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
31302357 AS |
5431 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) |
5432 | | ((ri->r_length << 5) & 0x60) | |
5433 | | ((ri->r_extern << 4) & 0x10)); | |
252b5132 RH |
5434 | } |
5435 | ||
36759679 | 5436 | #endif |
252b5132 | 5437 | |
252b5132 RH |
5438 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
5439 | ||
5440 | #ifndef WORKING_DOT_WORD | |
2b4f075a HPN |
5441 | int md_short_jump_size = 4; |
5442 | int md_long_jump_size = 6; | |
252b5132 RH |
5443 | |
5444 | void | |
31302357 AS |
5445 | md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, |
5446 | fragS *frag ATTRIBUTE_UNUSED, | |
5447 | symbolS *to_symbol ATTRIBUTE_UNUSED) | |
252b5132 RH |
5448 | { |
5449 | valueT offset; | |
5450 | ||
5451 | offset = to_addr - (from_addr + 2); | |
5452 | ||
5453 | md_number_to_chars (ptr, (valueT) 0x6000, 2); | |
5454 | md_number_to_chars (ptr + 2, (valueT) offset, 2); | |
5455 | } | |
5456 | ||
5457 | void | |
31302357 AS |
5458 | md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, |
5459 | fragS *frag, symbolS *to_symbol) | |
252b5132 RH |
5460 | { |
5461 | valueT offset; | |
5462 | ||
6b6e92f4 | 5463 | if (!HAVE_LONG_BRANCH (current_architecture)) |
252b5132 | 5464 | { |
36759679 | 5465 | if (flag_keep_pcrel) |
6b6e92f4 | 5466 | as_fatal (_("Tried to convert PC relative branch to absolute jump")); |
252b5132 RH |
5467 | offset = to_addr - S_GET_VALUE (to_symbol); |
5468 | md_number_to_chars (ptr, (valueT) 0x4EF9, 2); | |
5469 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5470 | fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, | |
5471 | 0, NO_RELOC); | |
5472 | } | |
5473 | else | |
5474 | { | |
5475 | offset = to_addr - (from_addr + 2); | |
5476 | md_number_to_chars (ptr, (valueT) 0x60ff, 2); | |
5477 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5478 | } | |
5479 | } | |
5480 | ||
5481 | #endif | |
5482 | ||
5483 | /* Different values of OK tell what its OK to return. Things that | |
5484 | aren't OK are an error (what a shock, no?) | |
5485 | ||
5486 | 0: Everything is OK | |
3e602632 NC |
5487 | 10: Absolute 1:8 only |
5488 | 20: Absolute 0:7 only | |
5489 | 30: absolute 0:15 only | |
5490 | 40: Absolute 0:31 only | |
5491 | 50: absolute 0:127 only | |
252b5132 | 5492 | 55: absolute -64:63 only |
3e602632 | 5493 | 60: absolute -128:127 only |
afa2158f | 5494 | 65: absolute 0:511 only |
3e602632 NC |
5495 | 70: absolute 0:4095 only |
5496 | 80: absolute -1, 1:7 only | |
5497 | 90: No bignums. */ | |
252b5132 RH |
5498 | |
5499 | static int | |
31302357 | 5500 | get_num (struct m68k_exp *exp, int ok) |
252b5132 RH |
5501 | { |
5502 | if (exp->exp.X_op == O_absent) | |
5503 | { | |
36759679 | 5504 | /* Do the same thing the VAX asm does. */ |
252b5132 RH |
5505 | op (exp) = O_constant; |
5506 | adds (exp) = 0; | |
5507 | subs (exp) = 0; | |
5508 | offs (exp) = 0; | |
5509 | if (ok == 10) | |
5510 | { | |
5511 | as_warn (_("expression out of range: defaulting to 1")); | |
5512 | offs (exp) = 1; | |
5513 | } | |
5514 | } | |
5515 | else if (exp->exp.X_op == O_constant) | |
5516 | { | |
5517 | switch (ok) | |
5518 | { | |
5519 | case 10: | |
bd17c2c3 | 5520 | if ((valueT) TRUNC (offs (exp)) - 1 > 7) |
252b5132 RH |
5521 | { |
5522 | as_warn (_("expression out of range: defaulting to 1")); | |
5523 | offs (exp) = 1; | |
5524 | } | |
5525 | break; | |
5526 | case 20: | |
bd17c2c3 | 5527 | if ((valueT) TRUNC (offs (exp)) > 7) |
252b5132 RH |
5528 | goto outrange; |
5529 | break; | |
5530 | case 30: | |
bd17c2c3 | 5531 | if ((valueT) TRUNC (offs (exp)) > 15) |
252b5132 RH |
5532 | goto outrange; |
5533 | break; | |
5534 | case 40: | |
bd17c2c3 | 5535 | if ((valueT) TRUNC (offs (exp)) > 32) |
252b5132 RH |
5536 | goto outrange; |
5537 | break; | |
5538 | case 50: | |
bd17c2c3 | 5539 | if ((valueT) TRUNC (offs (exp)) > 127) |
252b5132 RH |
5540 | goto outrange; |
5541 | break; | |
5542 | case 55: | |
bd17c2c3 | 5543 | if ((valueT) SEXT (offs (exp)) + 64 > 127) |
252b5132 RH |
5544 | goto outrange; |
5545 | break; | |
5546 | case 60: | |
bd17c2c3 | 5547 | if ((valueT) SEXT (offs (exp)) + 128 > 255) |
252b5132 | 5548 | goto outrange; |
afa2158f NS |
5549 | break; |
5550 | case 65: | |
5551 | if ((valueT) TRUNC (offs (exp)) > 511) | |
5552 | goto outrange; | |
252b5132 RH |
5553 | break; |
5554 | case 70: | |
bd17c2c3 | 5555 | if ((valueT) TRUNC (offs (exp)) > 4095) |
252b5132 RH |
5556 | { |
5557 | outrange: | |
5558 | as_warn (_("expression out of range: defaulting to 0")); | |
5559 | offs (exp) = 0; | |
5560 | } | |
5561 | break; | |
3e602632 | 5562 | case 80: |
bd17c2c3 AM |
5563 | if ((valueT) TRUNC (offs (exp)) != 0xffffffff |
5564 | && (valueT) TRUNC (offs (exp)) - 1 > 6) | |
3e602632 NC |
5565 | { |
5566 | as_warn (_("expression out of range: defaulting to 1")); | |
5567 | offs (exp) = 1; | |
5568 | } | |
5569 | break; | |
252b5132 RH |
5570 | default: |
5571 | break; | |
5572 | } | |
5573 | } | |
5574 | else if (exp->exp.X_op == O_big) | |
5575 | { | |
36759679 | 5576 | if (offs (exp) <= 0 /* flonum. */ |
3e602632 | 5577 | && (ok == 90 /* no bignums */ |
36759679 | 5578 | || (ok > 10 /* Small-int ranges including 0 ok. */ |
252b5132 RH |
5579 | /* If we have a flonum zero, a zero integer should |
5580 | do as well (e.g., in moveq). */ | |
5581 | && generic_floating_point_number.exponent == 0 | |
5582 | && generic_floating_point_number.low[0] == 0))) | |
5583 | { | |
36759679 | 5584 | /* HACK! Turn it into a long. */ |
252b5132 RH |
5585 | LITTLENUM_TYPE words[6]; |
5586 | ||
36759679 | 5587 | gen_to_words (words, 2, 8L); /* These numbers are magic! */ |
252b5132 RH |
5588 | op (exp) = O_constant; |
5589 | adds (exp) = 0; | |
5590 | subs (exp) = 0; | |
5591 | offs (exp) = words[1] | (words[0] << 16); | |
5592 | } | |
5593 | else if (ok != 0) | |
5594 | { | |
5595 | op (exp) = O_constant; | |
5596 | adds (exp) = 0; | |
5597 | subs (exp) = 0; | |
5598 | offs (exp) = (ok == 10) ? 1 : 0; | |
5599 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
045b540e | 5600 | (long) offs (exp)); |
252b5132 RH |
5601 | } |
5602 | } | |
5603 | else | |
5604 | { | |
3e602632 | 5605 | if (ok >= 10 && ok <= 80) |
252b5132 RH |
5606 | { |
5607 | op (exp) = O_constant; | |
5608 | adds (exp) = 0; | |
5609 | subs (exp) = 0; | |
5610 | offs (exp) = (ok == 10) ? 1 : 0; | |
5611 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
045b540e | 5612 | (long) offs (exp)); |
252b5132 RH |
5613 | } |
5614 | } | |
5615 | ||
5616 | if (exp->size != SIZE_UNSPEC) | |
5617 | { | |
5618 | switch (exp->size) | |
5619 | { | |
5620 | case SIZE_UNSPEC: | |
5621 | case SIZE_LONG: | |
5622 | break; | |
5623 | case SIZE_BYTE: | |
5624 | if (!isbyte (offs (exp))) | |
5625 | as_warn (_("expression doesn't fit in BYTE")); | |
5626 | break; | |
5627 | case SIZE_WORD: | |
5628 | if (!isword (offs (exp))) | |
5629 | as_warn (_("expression doesn't fit in WORD")); | |
5630 | break; | |
5631 | } | |
5632 | } | |
5633 | ||
5634 | return offs (exp); | |
5635 | } | |
5636 | ||
5637 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
5638 | ||
5639 | static void | |
31302357 | 5640 | s_data1 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5641 | { |
5642 | subseg_set (data_section, 1); | |
5643 | demand_empty_rest_of_line (); | |
5644 | } | |
5645 | ||
5646 | static void | |
31302357 | 5647 | s_data2 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5648 | { |
5649 | subseg_set (data_section, 2); | |
5650 | demand_empty_rest_of_line (); | |
5651 | } | |
5652 | ||
5653 | static void | |
31302357 | 5654 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5655 | { |
5656 | /* We don't support putting frags in the BSS segment, we fake it | |
5657 | by marking in_bss, then looking at s_skip for clues. */ | |
5658 | ||
5659 | subseg_set (bss_section, 0); | |
5660 | demand_empty_rest_of_line (); | |
5661 | } | |
5662 | ||
5663 | static void | |
31302357 | 5664 | s_even (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5665 | { |
ed9e98c2 AM |
5666 | int temp; |
5667 | long temp_fill; | |
252b5132 RH |
5668 | |
5669 | temp = 1; /* JF should be 2? */ | |
5670 | temp_fill = get_absolute_expression (); | |
92774660 | 5671 | if (!need_pass_2) /* Never make frag if expect extra pass. */ |
252b5132 RH |
5672 | frag_align (temp, (int) temp_fill, 0); |
5673 | demand_empty_rest_of_line (); | |
5674 | record_alignment (now_seg, temp); | |
5675 | } | |
5676 | ||
5677 | static void | |
31302357 | 5678 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5679 | { |
5680 | demand_empty_rest_of_line (); | |
5681 | } | |
5682 | \f | |
5683 | /* Pseudo-ops handled for MRI compatibility. */ | |
5684 | ||
5685 | /* This function returns non-zero if the argument is a conditional | |
5686 | pseudo-op. This is called when checking whether a pending | |
5687 | alignment is needed. */ | |
5688 | ||
5689 | int | |
31302357 | 5690 | m68k_conditional_pseudoop (pseudo_typeS *pop) |
252b5132 RH |
5691 | { |
5692 | return (pop->poc_handler == s_mri_if | |
5693 | || pop->poc_handler == s_mri_else); | |
5694 | } | |
5695 | ||
5696 | /* Handle an MRI style chip specification. */ | |
5697 | ||
5698 | static void | |
31302357 | 5699 | mri_chip (void) |
252b5132 RH |
5700 | { |
5701 | char *s; | |
5702 | char c; | |
5703 | int i; | |
5704 | ||
5705 | s = input_line_pointer; | |
d02603dc | 5706 | /* We can't use get_symbol_name since the processor names are not proper |
252b5132 RH |
5707 | symbols. */ |
5708 | while (is_part_of_name (c = *input_line_pointer++)) | |
5709 | ; | |
5710 | *--input_line_pointer = 0; | |
266abb8f NS |
5711 | for (i = 0; m68k_cpus[i].name; i++) |
5712 | if (strcasecmp (s, m68k_cpus[i].name) == 0) | |
252b5132 | 5713 | break; |
266abb8f | 5714 | if (!m68k_cpus[i].name) |
252b5132 RH |
5715 | { |
5716 | as_bad (_("%s: unrecognized processor name"), s); | |
5717 | *input_line_pointer = c; | |
5718 | ignore_rest_of_line (); | |
5719 | return; | |
5720 | } | |
5721 | *input_line_pointer = c; | |
5722 | ||
5723 | if (*input_line_pointer == '/') | |
5724 | current_architecture = 0; | |
5725 | else | |
5726 | current_architecture &= m68881 | m68851; | |
266abb8f | 5727 | current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); |
2da12c60 | 5728 | control_regs = m68k_cpus[i].control_regs; |
252b5132 RH |
5729 | |
5730 | while (*input_line_pointer == '/') | |
5731 | { | |
5732 | ++input_line_pointer; | |
5733 | s = input_line_pointer; | |
d02603dc | 5734 | /* We can't use get_symbol_name since the processor names are not |
252b5132 RH |
5735 | proper symbols. */ |
5736 | while (is_part_of_name (c = *input_line_pointer++)) | |
5737 | ; | |
5738 | *--input_line_pointer = 0; | |
5739 | if (strcmp (s, "68881") == 0) | |
5740 | current_architecture |= m68881; | |
5741 | else if (strcmp (s, "68851") == 0) | |
5742 | current_architecture |= m68851; | |
5743 | *input_line_pointer = c; | |
5744 | } | |
252b5132 RH |
5745 | } |
5746 | ||
5747 | /* The MRI CHIP pseudo-op. */ | |
5748 | ||
5749 | static void | |
31302357 | 5750 | s_chip (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5751 | { |
5752 | char *stop = NULL; | |
5753 | char stopc; | |
5754 | ||
5755 | if (flag_mri) | |
5756 | stop = mri_comment_field (&stopc); | |
5757 | mri_chip (); | |
5758 | if (flag_mri) | |
5759 | mri_comment_end (stop, stopc); | |
5760 | demand_empty_rest_of_line (); | |
5761 | } | |
5762 | ||
5763 | /* The MRI FOPT pseudo-op. */ | |
5764 | ||
5765 | static void | |
31302357 | 5766 | s_fopt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5767 | { |
5768 | SKIP_WHITESPACE (); | |
5769 | ||
5770 | if (strncasecmp (input_line_pointer, "ID=", 3) == 0) | |
5771 | { | |
5772 | int temp; | |
5773 | ||
5774 | input_line_pointer += 3; | |
5775 | temp = get_absolute_expression (); | |
5776 | if (temp < 0 || temp > 7) | |
5777 | as_bad (_("bad coprocessor id")); | |
5778 | else | |
5779 | m68k_float_copnum = COP0 + temp; | |
5780 | } | |
5781 | else | |
5782 | { | |
5783 | as_bad (_("unrecognized fopt option")); | |
5784 | ignore_rest_of_line (); | |
5785 | return; | |
5786 | } | |
5787 | ||
5788 | demand_empty_rest_of_line (); | |
5789 | } | |
5790 | ||
5791 | /* The structure used to handle the MRI OPT pseudo-op. */ | |
5792 | ||
5793 | struct opt_action | |
5794 | { | |
5795 | /* The name of the option. */ | |
5796 | const char *name; | |
5797 | ||
5798 | /* If this is not NULL, just call this function. The first argument | |
5799 | is the ARG field of this structure, the second argument is | |
5800 | whether the option was negated. */ | |
31302357 | 5801 | void (*pfn) (int arg, int on); |
252b5132 RH |
5802 | |
5803 | /* If this is not NULL, and the PFN field is NULL, set the variable | |
5804 | this points to. Set it to the ARG field if the option was not | |
5805 | negated, and the NOTARG field otherwise. */ | |
5806 | int *pvar; | |
5807 | ||
5808 | /* The value to pass to PFN or to assign to *PVAR. */ | |
5809 | int arg; | |
5810 | ||
5811 | /* The value to assign to *PVAR if the option is negated. If PFN is | |
5812 | NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then | |
5813 | the option may not be negated. */ | |
5814 | int notarg; | |
5815 | }; | |
5816 | ||
5817 | /* The table used to handle the MRI OPT pseudo-op. */ | |
5818 | ||
31302357 AS |
5819 | static void skip_to_comma (int, int); |
5820 | static void opt_nest (int, int); | |
5821 | static void opt_chip (int, int); | |
5822 | static void opt_list (int, int); | |
5823 | static void opt_list_symbols (int, int); | |
252b5132 RH |
5824 | |
5825 | static const struct opt_action opt_table[] = | |
5826 | { | |
5827 | { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, | |
5828 | ||
5829 | /* We do relaxing, so there is little use for these options. */ | |
5830 | { "b", 0, 0, 0, 0 }, | |
5831 | { "brs", 0, 0, 0, 0 }, | |
5832 | { "brb", 0, 0, 0, 0 }, | |
5833 | { "brl", 0, 0, 0, 0 }, | |
5834 | { "brw", 0, 0, 0, 0 }, | |
5835 | ||
5836 | { "c", 0, 0, 0, 0 }, | |
5837 | { "cex", 0, 0, 0, 0 }, | |
5838 | { "case", 0, &symbols_case_sensitive, 1, 0 }, | |
5839 | { "cl", 0, 0, 0, 0 }, | |
5840 | { "cre", 0, 0, 0, 0 }, | |
5841 | { "d", 0, &flag_keep_locals, 1, 0 }, | |
5842 | { "e", 0, 0, 0, 0 }, | |
5843 | { "f", 0, &flag_short_refs, 1, 0 }, | |
5844 | { "frs", 0, &flag_short_refs, 1, 0 }, | |
5845 | { "frl", 0, &flag_short_refs, 0, 1 }, | |
5846 | { "g", 0, 0, 0, 0 }, | |
5847 | { "i", 0, 0, 0, 0 }, | |
5848 | { "m", 0, 0, 0, 0 }, | |
5849 | { "mex", 0, 0, 0, 0 }, | |
5850 | { "mc", 0, 0, 0, 0 }, | |
5851 | { "md", 0, 0, 0, 0 }, | |
5852 | { "nest", opt_nest, 0, 0, 0 }, | |
5853 | { "next", skip_to_comma, 0, 0, 0 }, | |
5854 | { "o", 0, 0, 0, 0 }, | |
5855 | { "old", 0, 0, 0, 0 }, | |
5856 | { "op", skip_to_comma, 0, 0, 0 }, | |
5857 | { "pco", 0, 0, 0, 0 }, | |
5858 | { "p", opt_chip, 0, 0, 0 }, | |
5859 | { "pcr", 0, 0, 0, 0 }, | |
5860 | { "pcs", 0, 0, 0, 0 }, | |
5861 | { "r", 0, 0, 0, 0 }, | |
5862 | { "quick", 0, &m68k_quick, 1, 0 }, | |
5863 | { "rel32", 0, &m68k_rel32, 1, 0 }, | |
5864 | { "s", opt_list, 0, 0, 0 }, | |
5865 | { "t", opt_list_symbols, 0, 0, 0 }, | |
5866 | { "w", 0, &flag_no_warnings, 0, 1 }, | |
5867 | { "x", 0, 0, 0, 0 } | |
5868 | }; | |
5869 | ||
8fce3f5e | 5870 | #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) |
252b5132 RH |
5871 | |
5872 | /* The MRI OPT pseudo-op. */ | |
5873 | ||
5874 | static void | |
31302357 | 5875 | s_opt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5876 | { |
5877 | do | |
5878 | { | |
5879 | int t; | |
5880 | char *s; | |
5881 | char c; | |
5882 | int i; | |
5883 | const struct opt_action *o; | |
5884 | ||
5885 | SKIP_WHITESPACE (); | |
5886 | ||
5887 | t = 1; | |
5888 | if (*input_line_pointer == '-') | |
5889 | { | |
5890 | ++input_line_pointer; | |
5891 | t = 0; | |
5892 | } | |
5893 | else if (strncasecmp (input_line_pointer, "NO", 2) == 0) | |
5894 | { | |
5895 | input_line_pointer += 2; | |
5896 | t = 0; | |
5897 | } | |
5898 | ||
d02603dc | 5899 | c = get_symbol_name (&s); |
252b5132 RH |
5900 | |
5901 | for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) | |
5902 | { | |
5903 | if (strcasecmp (s, o->name) == 0) | |
5904 | { | |
5905 | if (o->pfn) | |
5906 | { | |
5907 | /* Restore input_line_pointer now in case the option | |
5908 | takes arguments. */ | |
d02603dc | 5909 | (void) restore_line_pointer (c); |
252b5132 RH |
5910 | (*o->pfn) (o->arg, t); |
5911 | } | |
5912 | else if (o->pvar != NULL) | |
5913 | { | |
5914 | if (! t && o->arg == o->notarg) | |
5915 | as_bad (_("option `%s' may not be negated"), s); | |
d02603dc | 5916 | restore_line_pointer (c); |
252b5132 RH |
5917 | *o->pvar = t ? o->arg : o->notarg; |
5918 | } | |
5919 | else | |
5920 | *input_line_pointer = c; | |
5921 | break; | |
5922 | } | |
5923 | } | |
5924 | if (i >= OPTCOUNT) | |
5925 | { | |
5926 | as_bad (_("option `%s' not recognized"), s); | |
d02603dc | 5927 | restore_line_pointer (c); |
252b5132 RH |
5928 | } |
5929 | } | |
5930 | while (*input_line_pointer++ == ','); | |
5931 | ||
5932 | /* Move back to terminating character. */ | |
5933 | --input_line_pointer; | |
5934 | demand_empty_rest_of_line (); | |
5935 | } | |
5936 | ||
5937 | /* Skip ahead to a comma. This is used for OPT options which we do | |
67c1ffbe | 5938 | not support and which take arguments. */ |
252b5132 RH |
5939 | |
5940 | static void | |
31302357 | 5941 | skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5942 | { |
5943 | while (*input_line_pointer != ',' | |
5944 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5945 | ++input_line_pointer; | |
5946 | } | |
5947 | ||
5948 | /* Handle the OPT NEST=depth option. */ | |
5949 | ||
5950 | static void | |
31302357 | 5951 | opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5952 | { |
5953 | if (*input_line_pointer != '=') | |
5954 | { | |
5955 | as_bad (_("bad format of OPT NEST=depth")); | |
5956 | return; | |
5957 | } | |
5958 | ||
5959 | ++input_line_pointer; | |
5960 | max_macro_nest = get_absolute_expression (); | |
5961 | } | |
5962 | ||
5963 | /* Handle the OPT P=chip option. */ | |
5964 | ||
5965 | static void | |
31302357 | 5966 | opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5967 | { |
5968 | if (*input_line_pointer != '=') | |
5969 | { | |
5970 | /* This is just OPT P, which we do not support. */ | |
5971 | return; | |
5972 | } | |
5973 | ||
5974 | ++input_line_pointer; | |
5975 | mri_chip (); | |
5976 | } | |
5977 | ||
5978 | /* Handle the OPT S option. */ | |
5979 | ||
5980 | static void | |
31302357 | 5981 | opt_list (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5982 | { |
5983 | listing_list (on); | |
5984 | } | |
5985 | ||
5986 | /* Handle the OPT T option. */ | |
5987 | ||
5988 | static void | |
31302357 | 5989 | opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5990 | { |
5991 | if (on) | |
5992 | listing |= LISTING_SYMBOLS; | |
5993 | else | |
8a104df9 | 5994 | listing &= ~LISTING_SYMBOLS; |
252b5132 RH |
5995 | } |
5996 | ||
5997 | /* Handle the MRI REG pseudo-op. */ | |
5998 | ||
5999 | static void | |
31302357 | 6000 | s_reg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6001 | { |
6002 | char *s; | |
6003 | int c; | |
6004 | struct m68k_op rop; | |
6005 | int mask; | |
6006 | char *stop = NULL; | |
6007 | char stopc; | |
6008 | ||
6009 | if (line_label == NULL) | |
6010 | { | |
6011 | as_bad (_("missing label")); | |
6012 | ignore_rest_of_line (); | |
6013 | return; | |
6014 | } | |
6015 | ||
6016 | if (flag_mri) | |
6017 | stop = mri_comment_field (&stopc); | |
6018 | ||
6019 | SKIP_WHITESPACE (); | |
6020 | ||
6021 | s = input_line_pointer; | |
3882b010 | 6022 | while (ISALNUM (*input_line_pointer) |
252b5132 RH |
6023 | #ifdef REGISTER_PREFIX |
6024 | || *input_line_pointer == REGISTER_PREFIX | |
6025 | #endif | |
6026 | || *input_line_pointer == '/' | |
6027 | || *input_line_pointer == '-') | |
6028 | ++input_line_pointer; | |
6029 | c = *input_line_pointer; | |
6030 | *input_line_pointer = '\0'; | |
6031 | ||
6032 | if (m68k_ip_op (s, &rop) != 0) | |
6033 | { | |
6034 | if (rop.error == NULL) | |
6035 | as_bad (_("bad register list")); | |
6036 | else | |
6037 | as_bad (_("bad register list: %s"), rop.error); | |
6038 | *input_line_pointer = c; | |
6039 | ignore_rest_of_line (); | |
6040 | return; | |
6041 | } | |
6042 | ||
6043 | *input_line_pointer = c; | |
6044 | ||
6045 | if (rop.mode == REGLST) | |
6046 | mask = rop.mask; | |
6047 | else if (rop.mode == DREG) | |
6048 | mask = 1 << (rop.reg - DATA0); | |
6049 | else if (rop.mode == AREG) | |
6050 | mask = 1 << (rop.reg - ADDR0 + 8); | |
6051 | else if (rop.mode == FPREG) | |
6052 | mask = 1 << (rop.reg - FP0 + 16); | |
6053 | else if (rop.mode == CONTROL | |
6054 | && rop.reg == FPI) | |
6055 | mask = 1 << 24; | |
6056 | else if (rop.mode == CONTROL | |
6057 | && rop.reg == FPS) | |
6058 | mask = 1 << 25; | |
6059 | else if (rop.mode == CONTROL | |
6060 | && rop.reg == FPC) | |
6061 | mask = 1 << 26; | |
6062 | else | |
6063 | { | |
6064 | as_bad (_("bad register list")); | |
6065 | ignore_rest_of_line (); | |
6066 | return; | |
6067 | } | |
6068 | ||
6069 | S_SET_SEGMENT (line_label, reg_section); | |
6070 | S_SET_VALUE (line_label, ~mask); | |
49309057 | 6071 | symbol_set_frag (line_label, &zero_address_frag); |
252b5132 RH |
6072 | |
6073 | if (flag_mri) | |
6074 | mri_comment_end (stop, stopc); | |
6075 | ||
6076 | demand_empty_rest_of_line (); | |
6077 | } | |
6078 | ||
6079 | /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ | |
6080 | ||
6081 | struct save_opts | |
6082 | { | |
6083 | struct save_opts *next; | |
6084 | int abspcadd; | |
6085 | int symbols_case_sensitive; | |
6086 | int keep_locals; | |
6087 | int short_refs; | |
6088 | int architecture; | |
2da12c60 | 6089 | const enum m68k_register *control_regs; |
252b5132 RH |
6090 | int quick; |
6091 | int rel32; | |
6092 | int listing; | |
6093 | int no_warnings; | |
6094 | /* FIXME: We don't save OPT S. */ | |
6095 | }; | |
6096 | ||
6097 | /* This variable holds the stack of saved options. */ | |
6098 | ||
6099 | static struct save_opts *save_stack; | |
6100 | ||
6101 | /* The MRI SAVE pseudo-op. */ | |
6102 | ||
6103 | static void | |
31302357 | 6104 | s_save (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6105 | { |
6106 | struct save_opts *s; | |
6107 | ||
6108 | s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); | |
6109 | s->abspcadd = m68k_abspcadd; | |
6110 | s->symbols_case_sensitive = symbols_case_sensitive; | |
6111 | s->keep_locals = flag_keep_locals; | |
6112 | s->short_refs = flag_short_refs; | |
6113 | s->architecture = current_architecture; | |
2da12c60 | 6114 | s->control_regs = control_regs; |
252b5132 RH |
6115 | s->quick = m68k_quick; |
6116 | s->rel32 = m68k_rel32; | |
6117 | s->listing = listing; | |
6118 | s->no_warnings = flag_no_warnings; | |
6119 | ||
6120 | s->next = save_stack; | |
6121 | save_stack = s; | |
6122 | ||
6123 | demand_empty_rest_of_line (); | |
6124 | } | |
6125 | ||
6126 | /* The MRI RESTORE pseudo-op. */ | |
6127 | ||
6128 | static void | |
31302357 | 6129 | s_restore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6130 | { |
6131 | struct save_opts *s; | |
6132 | ||
6133 | if (save_stack == NULL) | |
6134 | { | |
6135 | as_bad (_("restore without save")); | |
6136 | ignore_rest_of_line (); | |
6137 | return; | |
6138 | } | |
6139 | ||
6140 | s = save_stack; | |
6141 | save_stack = s->next; | |
6142 | ||
6143 | m68k_abspcadd = s->abspcadd; | |
6144 | symbols_case_sensitive = s->symbols_case_sensitive; | |
6145 | flag_keep_locals = s->keep_locals; | |
6146 | flag_short_refs = s->short_refs; | |
6147 | current_architecture = s->architecture; | |
2da12c60 | 6148 | control_regs = s->control_regs; |
252b5132 RH |
6149 | m68k_quick = s->quick; |
6150 | m68k_rel32 = s->rel32; | |
6151 | listing = s->listing; | |
6152 | flag_no_warnings = s->no_warnings; | |
6153 | ||
6154 | free (s); | |
6155 | ||
6156 | demand_empty_rest_of_line (); | |
6157 | } | |
6158 | ||
6159 | /* Types of MRI structured control directives. */ | |
6160 | ||
6161 | enum mri_control_type | |
6162 | { | |
6163 | mri_for, | |
6164 | mri_if, | |
6165 | mri_repeat, | |
6166 | mri_while | |
6167 | }; | |
6168 | ||
6169 | /* This structure is used to stack the MRI structured control | |
6170 | directives. */ | |
6171 | ||
6172 | struct mri_control_info | |
6173 | { | |
6174 | /* The directive within which this one is enclosed. */ | |
6175 | struct mri_control_info *outer; | |
6176 | ||
6177 | /* The type of directive. */ | |
6178 | enum mri_control_type type; | |
6179 | ||
6180 | /* Whether an ELSE has been in an IF. */ | |
6181 | int else_seen; | |
6182 | ||
6183 | /* The add or sub statement at the end of a FOR. */ | |
6184 | char *incr; | |
6185 | ||
6186 | /* The label of the top of a FOR or REPEAT loop. */ | |
6187 | char *top; | |
6188 | ||
6189 | /* The label to jump to for the next iteration, or the else | |
6190 | expression of a conditional. */ | |
6191 | char *next; | |
6192 | ||
6193 | /* The label to jump to to break out of the loop, or the label past | |
6194 | the end of a conditional. */ | |
6195 | char *bottom; | |
6196 | }; | |
6197 | ||
6198 | /* The stack of MRI structured control directives. */ | |
6199 | ||
6200 | static struct mri_control_info *mri_control_stack; | |
6201 | ||
6202 | /* The current MRI structured control directive index number, used to | |
6203 | generate label names. */ | |
6204 | ||
6205 | static int mri_control_index; | |
6206 | ||
252b5132 RH |
6207 | /* Assemble an instruction for an MRI structured control directive. */ |
6208 | ||
6209 | static void | |
31302357 | 6210 | mri_assemble (char *str) |
252b5132 RH |
6211 | { |
6212 | char *s; | |
6213 | ||
6214 | /* md_assemble expects the opcode to be in lower case. */ | |
6215 | for (s = str; *s != ' ' && *s != '\0'; s++) | |
3882b010 | 6216 | *s = TOLOWER (*s); |
252b5132 RH |
6217 | |
6218 | md_assemble (str); | |
6219 | } | |
6220 | ||
6221 | /* Generate a new MRI label structured control directive label name. */ | |
6222 | ||
6223 | static char * | |
31302357 | 6224 | mri_control_label (void) |
252b5132 RH |
6225 | { |
6226 | char *n; | |
6227 | ||
6228 | n = (char *) xmalloc (20); | |
6229 | sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); | |
6230 | ++mri_control_index; | |
6231 | return n; | |
6232 | } | |
6233 | ||
6234 | /* Create a new MRI structured control directive. */ | |
6235 | ||
6236 | static struct mri_control_info * | |
31302357 | 6237 | push_mri_control (enum mri_control_type type) |
252b5132 RH |
6238 | { |
6239 | struct mri_control_info *n; | |
6240 | ||
6241 | n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); | |
6242 | ||
6243 | n->type = type; | |
6244 | n->else_seen = 0; | |
6245 | if (type == mri_if || type == mri_while) | |
6246 | n->top = NULL; | |
6247 | else | |
6248 | n->top = mri_control_label (); | |
6249 | n->next = mri_control_label (); | |
6250 | n->bottom = mri_control_label (); | |
6251 | ||
6252 | n->outer = mri_control_stack; | |
6253 | mri_control_stack = n; | |
6254 | ||
6255 | return n; | |
6256 | } | |
6257 | ||
6258 | /* Pop off the stack of MRI structured control directives. */ | |
6259 | ||
6260 | static void | |
31302357 | 6261 | pop_mri_control (void) |
252b5132 RH |
6262 | { |
6263 | struct mri_control_info *n; | |
6264 | ||
6265 | n = mri_control_stack; | |
6266 | mri_control_stack = n->outer; | |
6267 | if (n->top != NULL) | |
6268 | free (n->top); | |
6269 | free (n->next); | |
6270 | free (n->bottom); | |
6271 | free (n); | |
6272 | } | |
6273 | ||
6274 | /* Recognize a condition code in an MRI structured control expression. */ | |
6275 | ||
6276 | static int | |
31302357 | 6277 | parse_mri_condition (int *pcc) |
252b5132 RH |
6278 | { |
6279 | char c1, c2; | |
6280 | ||
6281 | know (*input_line_pointer == '<'); | |
6282 | ||
6283 | ++input_line_pointer; | |
6284 | c1 = *input_line_pointer++; | |
6285 | c2 = *input_line_pointer++; | |
6286 | ||
6287 | if (*input_line_pointer != '>') | |
6288 | { | |
6289 | as_bad (_("syntax error in structured control directive")); | |
6290 | return 0; | |
6291 | } | |
6292 | ||
6293 | ++input_line_pointer; | |
6294 | SKIP_WHITESPACE (); | |
6295 | ||
3882b010 L |
6296 | c1 = TOLOWER (c1); |
6297 | c2 = TOLOWER (c2); | |
252b5132 RH |
6298 | |
6299 | *pcc = (c1 << 8) | c2; | |
6300 | ||
6301 | return 1; | |
6302 | } | |
6303 | ||
6304 | /* Parse a single operand in an MRI structured control expression. */ | |
6305 | ||
6306 | static int | |
31302357 AS |
6307 | parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, |
6308 | char **rightstart, char **rightstop) | |
252b5132 RH |
6309 | { |
6310 | char *s; | |
6311 | ||
6312 | SKIP_WHITESPACE (); | |
6313 | ||
6314 | *pcc = -1; | |
6315 | *leftstart = NULL; | |
6316 | *leftstop = NULL; | |
6317 | *rightstart = NULL; | |
6318 | *rightstop = NULL; | |
6319 | ||
6320 | if (*input_line_pointer == '<') | |
6321 | { | |
6322 | /* It's just a condition code. */ | |
6323 | return parse_mri_condition (pcc); | |
6324 | } | |
6325 | ||
6326 | /* Look ahead for the condition code. */ | |
6327 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6328 | { | |
6329 | if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') | |
6330 | break; | |
6331 | } | |
6332 | if (*s == '\0') | |
6333 | { | |
6334 | as_bad (_("missing condition code in structured control directive")); | |
6335 | return 0; | |
6336 | } | |
6337 | ||
6338 | *leftstart = input_line_pointer; | |
6339 | *leftstop = s; | |
6340 | if (*leftstop > *leftstart | |
6341 | && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) | |
6342 | --*leftstop; | |
6343 | ||
6344 | input_line_pointer = s; | |
6345 | if (! parse_mri_condition (pcc)) | |
6346 | return 0; | |
6347 | ||
6348 | /* Look ahead for AND or OR or end of line. */ | |
6349 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6350 | { | |
e1f44d10 NC |
6351 | /* We must make sure we don't misinterpret AND/OR at the end of labels! |
6352 | if d0 <eq> #FOOAND and d1 <ne> #BAROR then | |
6353 | ^^^ ^^ */ | |
8a104df9 KH |
6354 | if ((s == input_line_pointer |
6355 | || *(s-1) == ' ' | |
6356 | || *(s-1) == '\t') | |
6357 | && ((strncasecmp (s, "AND", 3) == 0 | |
6358 | && (s[3] == '.' || ! is_part_of_name (s[3]))) | |
6359 | || (strncasecmp (s, "OR", 2) == 0 | |
6360 | && (s[2] == '.' || ! is_part_of_name (s[2]))))) | |
6361 | break; | |
252b5132 RH |
6362 | } |
6363 | ||
6364 | *rightstart = input_line_pointer; | |
6365 | *rightstop = s; | |
6366 | if (*rightstop > *rightstart | |
6367 | && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) | |
6368 | --*rightstop; | |
6369 | ||
6370 | input_line_pointer = s; | |
6371 | ||
6372 | return 1; | |
6373 | } | |
6374 | ||
6375 | #define MCC(b1, b2) (((b1) << 8) | (b2)) | |
6376 | ||
6377 | /* Swap the sense of a condition. This changes the condition so that | |
6378 | it generates the same result when the operands are swapped. */ | |
6379 | ||
6380 | static int | |
31302357 | 6381 | swap_mri_condition (int cc) |
252b5132 RH |
6382 | { |
6383 | switch (cc) | |
6384 | { | |
6385 | case MCC ('h', 'i'): return MCC ('c', 's'); | |
6386 | case MCC ('l', 's'): return MCC ('c', 'c'); | |
36759679 | 6387 | /* <HS> is an alias for <CC>. */ |
e1f44d10 | 6388 | case MCC ('h', 's'): |
252b5132 | 6389 | case MCC ('c', 'c'): return MCC ('l', 's'); |
36759679 | 6390 | /* <LO> is an alias for <CS>. */ |
e1f44d10 | 6391 | case MCC ('l', 'o'): |
252b5132 RH |
6392 | case MCC ('c', 's'): return MCC ('h', 'i'); |
6393 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6394 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6395 | case MCC ('g', 'e'): return MCC ('l', 'e'); | |
6396 | case MCC ('l', 't'): return MCC ('g', 't'); | |
6397 | case MCC ('g', 't'): return MCC ('l', 't'); | |
6398 | case MCC ('l', 'e'): return MCC ('g', 'e'); | |
36759679 | 6399 | /* Issue a warning for conditions we can not swap. */ |
8fc4ee9b AM |
6400 | case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ |
6401 | case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ | |
e1f44d10 NC |
6402 | case MCC ('v', 'c'): |
6403 | case MCC ('v', 's'): | |
6404 | default : | |
6405 | as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), | |
6406 | (char) (cc >> 8), (char) (cc)); | |
6407 | break; | |
252b5132 RH |
6408 | } |
6409 | return cc; | |
6410 | } | |
6411 | ||
6412 | /* Reverse the sense of a condition. */ | |
6413 | ||
6414 | static int | |
31302357 | 6415 | reverse_mri_condition (int cc) |
252b5132 RH |
6416 | { |
6417 | switch (cc) | |
6418 | { | |
6419 | case MCC ('h', 'i'): return MCC ('l', 's'); | |
6420 | case MCC ('l', 's'): return MCC ('h', 'i'); | |
e1f44d10 NC |
6421 | /* <HS> is an alias for <CC> */ |
6422 | case MCC ('h', 's'): return MCC ('l', 'o'); | |
252b5132 | 6423 | case MCC ('c', 'c'): return MCC ('c', 's'); |
e1f44d10 NC |
6424 | /* <LO> is an alias for <CS> */ |
6425 | case MCC ('l', 'o'): return MCC ('h', 's'); | |
252b5132 RH |
6426 | case MCC ('c', 's'): return MCC ('c', 'c'); |
6427 | case MCC ('n', 'e'): return MCC ('e', 'q'); | |
6428 | case MCC ('e', 'q'): return MCC ('n', 'e'); | |
6429 | case MCC ('v', 'c'): return MCC ('v', 's'); | |
6430 | case MCC ('v', 's'): return MCC ('v', 'c'); | |
6431 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6432 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6433 | case MCC ('g', 'e'): return MCC ('l', 't'); | |
6434 | case MCC ('l', 't'): return MCC ('g', 'e'); | |
6435 | case MCC ('g', 't'): return MCC ('l', 'e'); | |
6436 | case MCC ('l', 'e'): return MCC ('g', 't'); | |
6437 | } | |
6438 | return cc; | |
6439 | } | |
6440 | ||
6441 | /* Build an MRI structured control expression. This generates test | |
6442 | and branch instructions. It goes to TRUELAB if the condition is | |
6443 | true, and to FALSELAB if the condition is false. Exactly one of | |
6444 | TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL | |
6445 | is the size qualifier for the expression. EXTENT is the size to | |
6446 | use for the branch. */ | |
6447 | ||
6448 | static void | |
31302357 AS |
6449 | build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, |
6450 | char *rightstart, char *rightstop, | |
6451 | const char *truelab, const char *falselab, | |
6452 | int extent) | |
252b5132 RH |
6453 | { |
6454 | char *buf; | |
6455 | char *s; | |
6456 | ||
6457 | if (leftstart != NULL) | |
6458 | { | |
6459 | struct m68k_op leftop, rightop; | |
6460 | char c; | |
6461 | ||
6462 | /* Swap the compare operands, if necessary, to produce a legal | |
6463 | m68k compare instruction. Comparing a register operand with | |
6464 | a non-register operand requires the register to be on the | |
6465 | right (cmp, cmpa). Comparing an immediate value with | |
6466 | anything requires the immediate value to be on the left | |
6467 | (cmpi). */ | |
6468 | ||
6469 | c = *leftstop; | |
6470 | *leftstop = '\0'; | |
6471 | (void) m68k_ip_op (leftstart, &leftop); | |
6472 | *leftstop = c; | |
6473 | ||
6474 | c = *rightstop; | |
6475 | *rightstop = '\0'; | |
6476 | (void) m68k_ip_op (rightstart, &rightop); | |
6477 | *rightstop = c; | |
6478 | ||
6479 | if (rightop.mode == IMMED | |
6480 | || ((leftop.mode == DREG || leftop.mode == AREG) | |
6481 | && (rightop.mode != DREG && rightop.mode != AREG))) | |
6482 | { | |
6483 | char *temp; | |
6484 | ||
31302357 AS |
6485 | /* Correct conditional handling: |
6486 | if #1 <lt> d0 then ;means if (1 < d0) | |
6487 | ... | |
6488 | endi | |
e1f44d10 | 6489 | |
31302357 | 6490 | should assemble to: |
e1f44d10 | 6491 | |
31302357 AS |
6492 | cmp #1,d0 if we do *not* swap the operands |
6493 | bgt true we need the swapped condition! | |
6494 | ble false | |
6495 | true: | |
6496 | ... | |
6497 | false: | |
6498 | */ | |
252b5132 RH |
6499 | temp = leftstart; |
6500 | leftstart = rightstart; | |
6501 | rightstart = temp; | |
6502 | temp = leftstop; | |
6503 | leftstop = rightstop; | |
6504 | rightstop = temp; | |
8a104df9 KH |
6505 | } |
6506 | else | |
6507 | { | |
e1f44d10 | 6508 | cc = swap_mri_condition (cc); |
252b5132 RH |
6509 | } |
6510 | } | |
6511 | ||
6512 | if (truelab == NULL) | |
6513 | { | |
6514 | cc = reverse_mri_condition (cc); | |
6515 | truelab = falselab; | |
6516 | } | |
92774660 | 6517 | |
252b5132 RH |
6518 | if (leftstart != NULL) |
6519 | { | |
6520 | buf = (char *) xmalloc (20 | |
6521 | + (leftstop - leftstart) | |
6522 | + (rightstop - rightstart)); | |
6523 | s = buf; | |
6524 | *s++ = 'c'; | |
6525 | *s++ = 'm'; | |
6526 | *s++ = 'p'; | |
6527 | if (qual != '\0') | |
3882b010 | 6528 | *s++ = TOLOWER (qual); |
252b5132 RH |
6529 | *s++ = ' '; |
6530 | memcpy (s, leftstart, leftstop - leftstart); | |
6531 | s += leftstop - leftstart; | |
6532 | *s++ = ','; | |
6533 | memcpy (s, rightstart, rightstop - rightstart); | |
6534 | s += rightstop - rightstart; | |
6535 | *s = '\0'; | |
6536 | mri_assemble (buf); | |
6537 | free (buf); | |
6538 | } | |
92774660 | 6539 | |
252b5132 RH |
6540 | buf = (char *) xmalloc (20 + strlen (truelab)); |
6541 | s = buf; | |
6542 | *s++ = 'b'; | |
6543 | *s++ = cc >> 8; | |
6544 | *s++ = cc & 0xff; | |
6545 | if (extent != '\0') | |
3882b010 | 6546 | *s++ = TOLOWER (extent); |
252b5132 RH |
6547 | *s++ = ' '; |
6548 | strcpy (s, truelab); | |
6549 | mri_assemble (buf); | |
6550 | free (buf); | |
6551 | } | |
6552 | ||
6553 | /* Parse an MRI structured control expression. This generates test | |
6554 | and branch instructions. STOP is where the expression ends. It | |
6555 | goes to TRUELAB if the condition is true, and to FALSELAB if the | |
6556 | condition is false. Exactly one of TRUELAB and FALSELAB will be | |
6557 | NULL, meaning to fall through. QUAL is the size qualifier for the | |
6558 | expression. EXTENT is the size to use for the branch. */ | |
6559 | ||
6560 | static void | |
31302357 AS |
6561 | parse_mri_control_expression (char *stop, int qual, const char *truelab, |
6562 | const char *falselab, int extent) | |
252b5132 RH |
6563 | { |
6564 | int c; | |
6565 | int cc; | |
6566 | char *leftstart; | |
6567 | char *leftstop; | |
6568 | char *rightstart; | |
6569 | char *rightstop; | |
6570 | ||
6571 | c = *stop; | |
6572 | *stop = '\0'; | |
6573 | ||
6574 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6575 | &rightstart, &rightstop)) | |
6576 | { | |
6577 | *stop = c; | |
6578 | return; | |
6579 | } | |
6580 | ||
6581 | if (strncasecmp (input_line_pointer, "AND", 3) == 0) | |
6582 | { | |
6583 | const char *flab; | |
6584 | ||
6585 | if (falselab != NULL) | |
6586 | flab = falselab; | |
6587 | else | |
6588 | flab = mri_control_label (); | |
6589 | ||
6590 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6591 | rightstop, (const char *) NULL, flab, extent); | |
6592 | ||
6593 | input_line_pointer += 3; | |
6594 | if (*input_line_pointer != '.' | |
6595 | || input_line_pointer[1] == '\0') | |
6596 | qual = '\0'; | |
6597 | else | |
6598 | { | |
6599 | qual = input_line_pointer[1]; | |
6600 | input_line_pointer += 2; | |
6601 | } | |
6602 | ||
6603 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6604 | &rightstart, &rightstop)) | |
6605 | { | |
6606 | *stop = c; | |
6607 | return; | |
6608 | } | |
6609 | ||
6610 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6611 | rightstop, truelab, falselab, extent); | |
6612 | ||
6613 | if (falselab == NULL) | |
6614 | colon (flab); | |
6615 | } | |
6616 | else if (strncasecmp (input_line_pointer, "OR", 2) == 0) | |
6617 | { | |
6618 | const char *tlab; | |
6619 | ||
6620 | if (truelab != NULL) | |
6621 | tlab = truelab; | |
6622 | else | |
6623 | tlab = mri_control_label (); | |
6624 | ||
6625 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6626 | rightstop, tlab, (const char *) NULL, extent); | |
6627 | ||
6628 | input_line_pointer += 2; | |
6629 | if (*input_line_pointer != '.' | |
6630 | || input_line_pointer[1] == '\0') | |
6631 | qual = '\0'; | |
6632 | else | |
6633 | { | |
6634 | qual = input_line_pointer[1]; | |
6635 | input_line_pointer += 2; | |
6636 | } | |
6637 | ||
6638 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6639 | &rightstart, &rightstop)) | |
6640 | { | |
6641 | *stop = c; | |
6642 | return; | |
6643 | } | |
6644 | ||
6645 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6646 | rightstop, truelab, falselab, extent); | |
6647 | ||
6648 | if (truelab == NULL) | |
6649 | colon (tlab); | |
6650 | } | |
6651 | else | |
6652 | { | |
6653 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6654 | rightstop, truelab, falselab, extent); | |
6655 | } | |
6656 | ||
6657 | *stop = c; | |
6658 | if (input_line_pointer != stop) | |
6659 | as_bad (_("syntax error in structured control directive")); | |
6660 | } | |
6661 | ||
6662 | /* Handle the MRI IF pseudo-op. This may be a structured control | |
6663 | directive, or it may be a regular assembler conditional, depending | |
6664 | on its operands. */ | |
6665 | ||
6666 | static void | |
31302357 | 6667 | s_mri_if (int qual) |
252b5132 RH |
6668 | { |
6669 | char *s; | |
6670 | int c; | |
6671 | struct mri_control_info *n; | |
6672 | ||
6673 | /* A structured control directive must end with THEN with an | |
6674 | optional qualifier. */ | |
6675 | s = input_line_pointer; | |
e1f44d10 NC |
6676 | /* We only accept '*' as introduction of comments if preceded by white space |
6677 | or at first column of a line (I think this can't actually happen here?) | |
6678 | This is important when assembling: | |
6679 | if d0 <ne> 12(a0,d0*2) then | |
36759679 | 6680 | if d0 <ne> #CONST*20 then. */ |
31302357 AS |
6681 | while (! (is_end_of_line[(unsigned char) *s] |
6682 | || (flag_mri | |
6683 | && *s == '*' | |
6684 | && (s == input_line_pointer | |
6685 | || *(s-1) == ' ' | |
6686 | || *(s-1) == '\t')))) | |
252b5132 RH |
6687 | ++s; |
6688 | --s; | |
6689 | while (s > input_line_pointer && (*s == ' ' || *s == '\t')) | |
6690 | --s; | |
6691 | ||
6692 | if (s - input_line_pointer > 1 | |
6693 | && s[-1] == '.') | |
6694 | s -= 2; | |
6695 | ||
6696 | if (s - input_line_pointer < 3 | |
6697 | || strncasecmp (s - 3, "THEN", 4) != 0) | |
6698 | { | |
6699 | if (qual != '\0') | |
6700 | { | |
6701 | as_bad (_("missing then")); | |
6702 | ignore_rest_of_line (); | |
6703 | return; | |
6704 | } | |
6705 | ||
6706 | /* It's a conditional. */ | |
6707 | s_if (O_ne); | |
6708 | return; | |
6709 | } | |
6710 | ||
6711 | /* Since this might be a conditional if, this pseudo-op will be | |
6712 | called even if we are supported to be ignoring input. Double | |
6713 | check now. Clobber *input_line_pointer so that ignore_input | |
6714 | thinks that this is not a special pseudo-op. */ | |
6715 | c = *input_line_pointer; | |
6716 | *input_line_pointer = 0; | |
6717 | if (ignore_input ()) | |
6718 | { | |
6719 | *input_line_pointer = c; | |
6720 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6721 | ++input_line_pointer; | |
6722 | demand_empty_rest_of_line (); | |
6723 | return; | |
6724 | } | |
6725 | *input_line_pointer = c; | |
6726 | ||
6727 | n = push_mri_control (mri_if); | |
6728 | ||
6729 | parse_mri_control_expression (s - 3, qual, (const char *) NULL, | |
6730 | n->next, s[1] == '.' ? s[2] : '\0'); | |
6731 | ||
6732 | if (s[1] == '.') | |
6733 | input_line_pointer = s + 3; | |
6734 | else | |
6735 | input_line_pointer = s + 1; | |
6736 | ||
6737 | if (flag_mri) | |
6738 | { | |
6739 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6740 | ++input_line_pointer; | |
6741 | } | |
6742 | ||
6743 | demand_empty_rest_of_line (); | |
6744 | } | |
6745 | ||
6746 | /* Handle the MRI else pseudo-op. If we are currently doing an MRI | |
6747 | structured IF, associate the ELSE with the IF. Otherwise, assume | |
6748 | it is a conditional else. */ | |
6749 | ||
6750 | static void | |
31302357 | 6751 | s_mri_else (int qual) |
252b5132 RH |
6752 | { |
6753 | int c; | |
6754 | char *buf; | |
6755 | char q[2]; | |
6756 | ||
6757 | if (qual == '\0' | |
6758 | && (mri_control_stack == NULL | |
6759 | || mri_control_stack->type != mri_if | |
6760 | || mri_control_stack->else_seen)) | |
6761 | { | |
6762 | s_else (0); | |
6763 | return; | |
6764 | } | |
6765 | ||
6766 | c = *input_line_pointer; | |
6767 | *input_line_pointer = 0; | |
6768 | if (ignore_input ()) | |
6769 | { | |
6770 | *input_line_pointer = c; | |
6771 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6772 | ++input_line_pointer; | |
6773 | demand_empty_rest_of_line (); | |
6774 | return; | |
6775 | } | |
6776 | *input_line_pointer = c; | |
6777 | ||
6778 | if (mri_control_stack == NULL | |
6779 | || mri_control_stack->type != mri_if | |
6780 | || mri_control_stack->else_seen) | |
6781 | { | |
6782 | as_bad (_("else without matching if")); | |
6783 | ignore_rest_of_line (); | |
6784 | return; | |
6785 | } | |
6786 | ||
6787 | mri_control_stack->else_seen = 1; | |
6788 | ||
6789 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); | |
3882b010 | 6790 | q[0] = TOLOWER (qual); |
252b5132 RH |
6791 | q[1] = '\0'; |
6792 | sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); | |
6793 | mri_assemble (buf); | |
6794 | free (buf); | |
6795 | ||
6796 | colon (mri_control_stack->next); | |
6797 | ||
6798 | if (flag_mri) | |
6799 | { | |
6800 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6801 | ++input_line_pointer; | |
6802 | } | |
6803 | ||
6804 | demand_empty_rest_of_line (); | |
6805 | } | |
6806 | ||
6807 | /* Handle the MRI ENDI pseudo-op. */ | |
6808 | ||
6809 | static void | |
31302357 | 6810 | s_mri_endi (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6811 | { |
6812 | if (mri_control_stack == NULL | |
6813 | || mri_control_stack->type != mri_if) | |
6814 | { | |
6815 | as_bad (_("endi without matching if")); | |
6816 | ignore_rest_of_line (); | |
6817 | return; | |
6818 | } | |
6819 | ||
6820 | /* ignore_input will not return true for ENDI, so we don't need to | |
6821 | worry about checking it again here. */ | |
6822 | ||
6823 | if (! mri_control_stack->else_seen) | |
6824 | colon (mri_control_stack->next); | |
6825 | colon (mri_control_stack->bottom); | |
6826 | ||
6827 | pop_mri_control (); | |
6828 | ||
6829 | if (flag_mri) | |
6830 | { | |
6831 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6832 | ++input_line_pointer; | |
6833 | } | |
6834 | ||
6835 | demand_empty_rest_of_line (); | |
6836 | } | |
6837 | ||
6838 | /* Handle the MRI BREAK pseudo-op. */ | |
6839 | ||
6840 | static void | |
31302357 | 6841 | s_mri_break (int extent) |
252b5132 RH |
6842 | { |
6843 | struct mri_control_info *n; | |
6844 | char *buf; | |
6845 | char ex[2]; | |
6846 | ||
6847 | n = mri_control_stack; | |
6848 | while (n != NULL | |
6849 | && n->type != mri_for | |
6850 | && n->type != mri_repeat | |
6851 | && n->type != mri_while) | |
6852 | n = n->outer; | |
6853 | if (n == NULL) | |
6854 | { | |
6855 | as_bad (_("break outside of structured loop")); | |
6856 | ignore_rest_of_line (); | |
6857 | return; | |
6858 | } | |
6859 | ||
6860 | buf = (char *) xmalloc (20 + strlen (n->bottom)); | |
3882b010 | 6861 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6862 | ex[1] = '\0'; |
6863 | sprintf (buf, "bra%s %s", ex, n->bottom); | |
6864 | mri_assemble (buf); | |
6865 | free (buf); | |
6866 | ||
6867 | if (flag_mri) | |
6868 | { | |
6869 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6870 | ++input_line_pointer; | |
6871 | } | |
6872 | ||
6873 | demand_empty_rest_of_line (); | |
6874 | } | |
6875 | ||
6876 | /* Handle the MRI NEXT pseudo-op. */ | |
6877 | ||
6878 | static void | |
31302357 | 6879 | s_mri_next (int extent) |
252b5132 RH |
6880 | { |
6881 | struct mri_control_info *n; | |
6882 | char *buf; | |
6883 | char ex[2]; | |
6884 | ||
6885 | n = mri_control_stack; | |
6886 | while (n != NULL | |
6887 | && n->type != mri_for | |
6888 | && n->type != mri_repeat | |
6889 | && n->type != mri_while) | |
6890 | n = n->outer; | |
6891 | if (n == NULL) | |
6892 | { | |
6893 | as_bad (_("next outside of structured loop")); | |
6894 | ignore_rest_of_line (); | |
6895 | return; | |
6896 | } | |
6897 | ||
6898 | buf = (char *) xmalloc (20 + strlen (n->next)); | |
3882b010 | 6899 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6900 | ex[1] = '\0'; |
6901 | sprintf (buf, "bra%s %s", ex, n->next); | |
6902 | mri_assemble (buf); | |
6903 | free (buf); | |
6904 | ||
6905 | if (flag_mri) | |
6906 | { | |
6907 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6908 | ++input_line_pointer; | |
6909 | } | |
6910 | ||
6911 | demand_empty_rest_of_line (); | |
6912 | } | |
6913 | ||
6914 | /* Handle the MRI FOR pseudo-op. */ | |
6915 | ||
6916 | static void | |
31302357 | 6917 | s_mri_for (int qual) |
252b5132 RH |
6918 | { |
6919 | const char *varstart, *varstop; | |
6920 | const char *initstart, *initstop; | |
6921 | const char *endstart, *endstop; | |
6922 | const char *bystart, *bystop; | |
6923 | int up; | |
6924 | int by; | |
6925 | int extent; | |
6926 | struct mri_control_info *n; | |
6927 | char *buf; | |
6928 | char *s; | |
6929 | char ex[2]; | |
6930 | ||
6931 | /* The syntax is | |
6932 | FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e | |
6933 | */ | |
6934 | ||
6935 | SKIP_WHITESPACE (); | |
6936 | varstart = input_line_pointer; | |
6937 | ||
6938 | /* Look for the '='. */ | |
6939 | while (! is_end_of_line[(unsigned char) *input_line_pointer] | |
6940 | && *input_line_pointer != '=') | |
6941 | ++input_line_pointer; | |
6942 | if (*input_line_pointer != '=') | |
6943 | { | |
6944 | as_bad (_("missing =")); | |
6945 | ignore_rest_of_line (); | |
6946 | return; | |
6947 | } | |
6948 | ||
6949 | varstop = input_line_pointer; | |
6950 | if (varstop > varstart | |
6951 | && (varstop[-1] == ' ' || varstop[-1] == '\t')) | |
6952 | --varstop; | |
6953 | ||
6954 | ++input_line_pointer; | |
6955 | ||
6956 | initstart = input_line_pointer; | |
6957 | ||
6958 | /* Look for TO or DOWNTO. */ | |
6959 | up = 1; | |
6960 | initstop = NULL; | |
6961 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6962 | { | |
6963 | if (strncasecmp (input_line_pointer, "TO", 2) == 0 | |
6964 | && ! is_part_of_name (input_line_pointer[2])) | |
6965 | { | |
6966 | initstop = input_line_pointer; | |
6967 | input_line_pointer += 2; | |
6968 | break; | |
6969 | } | |
6970 | if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 | |
6971 | && ! is_part_of_name (input_line_pointer[6])) | |
6972 | { | |
6973 | initstop = input_line_pointer; | |
6974 | up = 0; | |
6975 | input_line_pointer += 6; | |
6976 | break; | |
6977 | } | |
6978 | ++input_line_pointer; | |
6979 | } | |
6980 | if (initstop == NULL) | |
6981 | { | |
6982 | as_bad (_("missing to or downto")); | |
6983 | ignore_rest_of_line (); | |
6984 | return; | |
6985 | } | |
6986 | if (initstop > initstart | |
6987 | && (initstop[-1] == ' ' || initstop[-1] == '\t')) | |
6988 | --initstop; | |
6989 | ||
6990 | SKIP_WHITESPACE (); | |
6991 | endstart = input_line_pointer; | |
6992 | ||
6993 | /* Look for BY or DO. */ | |
6994 | by = 0; | |
6995 | endstop = NULL; | |
6996 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6997 | { | |
6998 | if (strncasecmp (input_line_pointer, "BY", 2) == 0 | |
6999 | && ! is_part_of_name (input_line_pointer[2])) | |
7000 | { | |
7001 | endstop = input_line_pointer; | |
7002 | by = 1; | |
7003 | input_line_pointer += 2; | |
7004 | break; | |
7005 | } | |
7006 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
7007 | && (input_line_pointer[2] == '.' | |
7008 | || ! is_part_of_name (input_line_pointer[2]))) | |
7009 | { | |
7010 | endstop = input_line_pointer; | |
7011 | input_line_pointer += 2; | |
7012 | break; | |
7013 | } | |
7014 | ++input_line_pointer; | |
7015 | } | |
7016 | if (endstop == NULL) | |
7017 | { | |
7018 | as_bad (_("missing do")); | |
7019 | ignore_rest_of_line (); | |
7020 | return; | |
7021 | } | |
7022 | if (endstop > endstart | |
7023 | && (endstop[-1] == ' ' || endstop[-1] == '\t')) | |
7024 | --endstop; | |
7025 | ||
7026 | if (! by) | |
7027 | { | |
7028 | bystart = "#1"; | |
7029 | bystop = bystart + 2; | |
7030 | } | |
7031 | else | |
7032 | { | |
7033 | SKIP_WHITESPACE (); | |
7034 | bystart = input_line_pointer; | |
7035 | ||
7036 | /* Look for DO. */ | |
7037 | bystop = NULL; | |
7038 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7039 | { | |
7040 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
7041 | && (input_line_pointer[2] == '.' | |
7042 | || ! is_part_of_name (input_line_pointer[2]))) | |
7043 | { | |
7044 | bystop = input_line_pointer; | |
7045 | input_line_pointer += 2; | |
7046 | break; | |
7047 | } | |
7048 | ++input_line_pointer; | |
7049 | } | |
7050 | if (bystop == NULL) | |
7051 | { | |
7052 | as_bad (_("missing do")); | |
7053 | ignore_rest_of_line (); | |
7054 | return; | |
7055 | } | |
7056 | if (bystop > bystart | |
7057 | && (bystop[-1] == ' ' || bystop[-1] == '\t')) | |
7058 | --bystop; | |
7059 | } | |
7060 | ||
7061 | if (*input_line_pointer != '.') | |
7062 | extent = '\0'; | |
7063 | else | |
7064 | { | |
7065 | extent = input_line_pointer[1]; | |
7066 | input_line_pointer += 2; | |
7067 | } | |
7068 | ||
7069 | /* We have fully parsed the FOR operands. Now build the loop. */ | |
252b5132 RH |
7070 | n = push_mri_control (mri_for); |
7071 | ||
7072 | buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); | |
7073 | ||
36759679 | 7074 | /* Move init,var. */ |
252b5132 RH |
7075 | s = buf; |
7076 | *s++ = 'm'; | |
7077 | *s++ = 'o'; | |
7078 | *s++ = 'v'; | |
7079 | *s++ = 'e'; | |
7080 | if (qual != '\0') | |
3882b010 | 7081 | *s++ = TOLOWER (qual); |
252b5132 RH |
7082 | *s++ = ' '; |
7083 | memcpy (s, initstart, initstop - initstart); | |
7084 | s += initstop - initstart; | |
7085 | *s++ = ','; | |
7086 | memcpy (s, varstart, varstop - varstart); | |
7087 | s += varstop - varstart; | |
7088 | *s = '\0'; | |
7089 | mri_assemble (buf); | |
7090 | ||
7091 | colon (n->top); | |
7092 | ||
36759679 | 7093 | /* cmp end,var. */ |
252b5132 RH |
7094 | s = buf; |
7095 | *s++ = 'c'; | |
7096 | *s++ = 'm'; | |
7097 | *s++ = 'p'; | |
7098 | if (qual != '\0') | |
3882b010 | 7099 | *s++ = TOLOWER (qual); |
252b5132 RH |
7100 | *s++ = ' '; |
7101 | memcpy (s, endstart, endstop - endstart); | |
7102 | s += endstop - endstart; | |
7103 | *s++ = ','; | |
7104 | memcpy (s, varstart, varstop - varstart); | |
7105 | s += varstop - varstart; | |
7106 | *s = '\0'; | |
7107 | mri_assemble (buf); | |
7108 | ||
36759679 | 7109 | /* bcc bottom. */ |
3882b010 | 7110 | ex[0] = TOLOWER (extent); |
252b5132 RH |
7111 | ex[1] = '\0'; |
7112 | if (up) | |
7113 | sprintf (buf, "blt%s %s", ex, n->bottom); | |
7114 | else | |
7115 | sprintf (buf, "bgt%s %s", ex, n->bottom); | |
7116 | mri_assemble (buf); | |
7117 | ||
7118 | /* Put together the add or sub instruction used by ENDF. */ | |
7119 | s = buf; | |
7120 | if (up) | |
7121 | strcpy (s, "add"); | |
7122 | else | |
7123 | strcpy (s, "sub"); | |
7124 | s += 3; | |
7125 | if (qual != '\0') | |
3882b010 | 7126 | *s++ = TOLOWER (qual); |
252b5132 RH |
7127 | *s++ = ' '; |
7128 | memcpy (s, bystart, bystop - bystart); | |
7129 | s += bystop - bystart; | |
7130 | *s++ = ','; | |
7131 | memcpy (s, varstart, varstop - varstart); | |
7132 | s += varstop - varstart; | |
7133 | *s = '\0'; | |
7134 | n->incr = buf; | |
7135 | ||
7136 | if (flag_mri) | |
7137 | { | |
7138 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7139 | ++input_line_pointer; | |
7140 | } | |
7141 | ||
7142 | demand_empty_rest_of_line (); | |
7143 | } | |
7144 | ||
7145 | /* Handle the MRI ENDF pseudo-op. */ | |
7146 | ||
7147 | static void | |
31302357 | 7148 | s_mri_endf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7149 | { |
7150 | if (mri_control_stack == NULL | |
7151 | || mri_control_stack->type != mri_for) | |
7152 | { | |
7153 | as_bad (_("endf without for")); | |
7154 | ignore_rest_of_line (); | |
7155 | return; | |
7156 | } | |
7157 | ||
7158 | colon (mri_control_stack->next); | |
7159 | ||
7160 | mri_assemble (mri_control_stack->incr); | |
7161 | ||
7162 | sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); | |
7163 | mri_assemble (mri_control_stack->incr); | |
7164 | ||
7165 | free (mri_control_stack->incr); | |
7166 | ||
7167 | colon (mri_control_stack->bottom); | |
7168 | ||
7169 | pop_mri_control (); | |
7170 | ||
7171 | if (flag_mri) | |
7172 | { | |
7173 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7174 | ++input_line_pointer; | |
7175 | } | |
7176 | ||
7177 | demand_empty_rest_of_line (); | |
7178 | } | |
7179 | ||
7180 | /* Handle the MRI REPEAT pseudo-op. */ | |
7181 | ||
7182 | static void | |
31302357 | 7183 | s_mri_repeat (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7184 | { |
7185 | struct mri_control_info *n; | |
7186 | ||
7187 | n = push_mri_control (mri_repeat); | |
7188 | colon (n->top); | |
7189 | if (flag_mri) | |
7190 | { | |
7191 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7192 | ++input_line_pointer; | |
7193 | } | |
7194 | demand_empty_rest_of_line (); | |
7195 | } | |
7196 | ||
7197 | /* Handle the MRI UNTIL pseudo-op. */ | |
7198 | ||
7199 | static void | |
31302357 | 7200 | s_mri_until (int qual) |
252b5132 RH |
7201 | { |
7202 | char *s; | |
7203 | ||
7204 | if (mri_control_stack == NULL | |
7205 | || mri_control_stack->type != mri_repeat) | |
7206 | { | |
7207 | as_bad (_("until without repeat")); | |
7208 | ignore_rest_of_line (); | |
7209 | return; | |
7210 | } | |
7211 | ||
7212 | colon (mri_control_stack->next); | |
7213 | ||
7214 | for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) | |
7215 | ; | |
7216 | ||
7217 | parse_mri_control_expression (s, qual, (const char *) NULL, | |
7218 | mri_control_stack->top, '\0'); | |
7219 | ||
7220 | colon (mri_control_stack->bottom); | |
7221 | ||
7222 | input_line_pointer = s; | |
7223 | ||
7224 | pop_mri_control (); | |
7225 | ||
7226 | if (flag_mri) | |
7227 | { | |
7228 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7229 | ++input_line_pointer; | |
7230 | } | |
7231 | ||
7232 | demand_empty_rest_of_line (); | |
7233 | } | |
7234 | ||
7235 | /* Handle the MRI WHILE pseudo-op. */ | |
7236 | ||
7237 | static void | |
31302357 | 7238 | s_mri_while (int qual) |
252b5132 RH |
7239 | { |
7240 | char *s; | |
7241 | ||
7242 | struct mri_control_info *n; | |
7243 | ||
7244 | s = input_line_pointer; | |
e1f44d10 NC |
7245 | /* We only accept '*' as introduction of comments if preceded by white space |
7246 | or at first column of a line (I think this can't actually happen here?) | |
7247 | This is important when assembling: | |
7248 | while d0 <ne> 12(a0,d0*2) do | |
36759679 | 7249 | while d0 <ne> #CONST*20 do. */ |
8a104df9 KH |
7250 | while (! (is_end_of_line[(unsigned char) *s] |
7251 | || (flag_mri | |
7252 | && *s == '*' | |
7253 | && (s == input_line_pointer | |
7254 | || *(s-1) == ' ' | |
7255 | || *(s-1) == '\t')))) | |
252b5132 RH |
7256 | s++; |
7257 | --s; | |
7258 | while (*s == ' ' || *s == '\t') | |
7259 | --s; | |
7260 | if (s - input_line_pointer > 1 | |
7261 | && s[-1] == '.') | |
7262 | s -= 2; | |
7263 | if (s - input_line_pointer < 2 | |
7264 | || strncasecmp (s - 1, "DO", 2) != 0) | |
7265 | { | |
7266 | as_bad (_("missing do")); | |
7267 | ignore_rest_of_line (); | |
7268 | return; | |
7269 | } | |
7270 | ||
7271 | n = push_mri_control (mri_while); | |
7272 | ||
7273 | colon (n->next); | |
7274 | ||
7275 | parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, | |
7276 | s[1] == '.' ? s[2] : '\0'); | |
7277 | ||
7278 | input_line_pointer = s + 1; | |
7279 | if (*input_line_pointer == '.') | |
7280 | input_line_pointer += 2; | |
7281 | ||
7282 | if (flag_mri) | |
7283 | { | |
7284 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7285 | ++input_line_pointer; | |
7286 | } | |
7287 | ||
7288 | demand_empty_rest_of_line (); | |
7289 | } | |
7290 | ||
7291 | /* Handle the MRI ENDW pseudo-op. */ | |
7292 | ||
7293 | static void | |
31302357 | 7294 | s_mri_endw (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7295 | { |
7296 | char *buf; | |
7297 | ||
7298 | if (mri_control_stack == NULL | |
7299 | || mri_control_stack->type != mri_while) | |
7300 | { | |
7301 | as_bad (_("endw without while")); | |
7302 | ignore_rest_of_line (); | |
7303 | return; | |
7304 | } | |
7305 | ||
7306 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); | |
7307 | sprintf (buf, "bra %s", mri_control_stack->next); | |
7308 | mri_assemble (buf); | |
7309 | free (buf); | |
7310 | ||
7311 | colon (mri_control_stack->bottom); | |
7312 | ||
7313 | pop_mri_control (); | |
7314 | ||
7315 | if (flag_mri) | |
7316 | { | |
7317 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7318 | ++input_line_pointer; | |
7319 | } | |
7320 | ||
7321 | demand_empty_rest_of_line (); | |
7322 | } | |
7323 | \f | |
266abb8f NS |
7324 | /* Parse a .cpu directive. */ |
7325 | ||
7326 | static void | |
7327 | s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) | |
7328 | { | |
7329 | char saved_char; | |
7330 | char *name; | |
7331 | ||
7332 | if (initialized) | |
7333 | { | |
7334 | as_bad (_("already assembled instructions")); | |
7335 | ignore_rest_of_line (); | |
7336 | return; | |
7337 | } | |
3739860c | 7338 | |
266abb8f NS |
7339 | name = input_line_pointer; |
7340 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
7341 | input_line_pointer++; | |
7342 | saved_char = *input_line_pointer; | |
7343 | *input_line_pointer = 0; | |
7344 | ||
7345 | m68k_set_cpu (name, 1, 0); | |
3739860c | 7346 | |
266abb8f NS |
7347 | *input_line_pointer = saved_char; |
7348 | demand_empty_rest_of_line (); | |
7349 | return; | |
7350 | } | |
7351 | ||
7352 | /* Parse a .arch directive. */ | |
7353 | ||
7354 | static void | |
7355 | s_m68k_arch (int ignored ATTRIBUTE_UNUSED) | |
7356 | { | |
7357 | char saved_char; | |
7358 | char *name; | |
7359 | ||
7360 | if (initialized) | |
7361 | { | |
7362 | as_bad (_("already assembled instructions")); | |
7363 | ignore_rest_of_line (); | |
7364 | return; | |
7365 | } | |
3739860c | 7366 | |
266abb8f NS |
7367 | name = input_line_pointer; |
7368 | while (*input_line_pointer && *input_line_pointer != ',' | |
7369 | && !ISSPACE (*input_line_pointer)) | |
7370 | input_line_pointer++; | |
7371 | saved_char = *input_line_pointer; | |
7372 | *input_line_pointer = 0; | |
7373 | ||
7374 | if (m68k_set_arch (name, 1, 0)) | |
7375 | { | |
7376 | /* Scan extensions. */ | |
7377 | do | |
7378 | { | |
7379 | *input_line_pointer++ = saved_char; | |
7380 | if (!*input_line_pointer || ISSPACE (*input_line_pointer)) | |
7381 | break; | |
7382 | name = input_line_pointer; | |
7383 | while (*input_line_pointer && *input_line_pointer != ',' | |
7384 | && !ISSPACE (*input_line_pointer)) | |
7385 | input_line_pointer++; | |
7386 | saved_char = *input_line_pointer; | |
7387 | *input_line_pointer = 0; | |
7388 | } | |
7389 | while (m68k_set_extension (name, 1, 0)); | |
7390 | } | |
3739860c | 7391 | |
266abb8f NS |
7392 | *input_line_pointer = saved_char; |
7393 | demand_empty_rest_of_line (); | |
7394 | return; | |
7395 | } | |
7396 | \f | |
7397 | /* Lookup a cpu name in TABLE and return the slot found. Return NULL | |
7398 | if none is found, the caller is responsible for emitting an error | |
7399 | message. If ALLOW_M is non-zero, we allow an initial 'm' on the | |
7400 | cpu name, if it begins with a '6' (possibly skipping an intervening | |
7401 | 'c'. We also allow a 'c' in the same place. if NEGATED is | |
7402 | non-zero, we accept a leading 'no-' and *NEGATED is set to true, if | |
7403 | the option is indeed negated. */ | |
7404 | ||
7405 | static const struct m68k_cpu * | |
7406 | m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, | |
7407 | int allow_m, int *negated) | |
7408 | { | |
7409 | /* allow negated value? */ | |
7410 | if (negated) | |
7411 | { | |
7412 | *negated = 0; | |
7413 | ||
7414 | if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') | |
7415 | { | |
7416 | arg += 3; | |
7417 | *negated = 1; | |
7418 | } | |
7419 | } | |
3739860c | 7420 | |
266abb8f NS |
7421 | /* Remove 'm' or 'mc' prefix from 68k variants. */ |
7422 | if (allow_m) | |
7423 | { | |
7424 | if (arg[0] == 'm') | |
7425 | { | |
7426 | if (arg[1] == '6') | |
7427 | arg += 1; | |
7428 | else if (arg[1] == 'c' && arg[2] == '6') | |
7429 | arg += 2; | |
7430 | } | |
7431 | } | |
7432 | else if (arg[0] == 'c' && arg[1] == '6') | |
7433 | arg += 1; | |
7434 | ||
7435 | for (; table->name; table++) | |
7436 | if (!strcmp (arg, table->name)) | |
2da12c60 NS |
7437 | { |
7438 | if (table->alias < -1 || table->alias > 1) | |
7439 | as_bad (_("`%s' is deprecated, use `%s'"), | |
7440 | table->name, table[table->alias < 0 ? 1 : -1].name); | |
7441 | return table; | |
7442 | } | |
266abb8f NS |
7443 | return 0; |
7444 | } | |
7445 | ||
bfbba8e4 | 7446 | /* Set the cpu, issuing errors if it is unrecognized. */ |
266abb8f NS |
7447 | |
7448 | static int | |
7449 | m68k_set_cpu (char const *name, int allow_m, int silent) | |
7450 | { | |
7451 | const struct m68k_cpu *cpu; | |
7452 | ||
7453 | cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); | |
7454 | ||
7455 | if (!cpu) | |
7456 | { | |
7457 | if (!silent) | |
7458 | as_bad (_("cpu `%s' unrecognized"), name); | |
7459 | return 0; | |
7460 | } | |
266abb8f NS |
7461 | selected_cpu = cpu; |
7462 | return 1; | |
7463 | } | |
7464 | ||
bfbba8e4 | 7465 | /* Set the architecture, issuing errors if it is unrecognized. */ |
266abb8f NS |
7466 | |
7467 | static int | |
7468 | m68k_set_arch (char const *name, int allow_m, int silent) | |
7469 | { | |
7470 | const struct m68k_cpu *arch; | |
7471 | ||
7472 | arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); | |
7473 | ||
7474 | if (!arch) | |
7475 | { | |
7476 | if (!silent) | |
7477 | as_bad (_("architecture `%s' unrecognized"), name); | |
7478 | return 0; | |
7479 | } | |
266abb8f NS |
7480 | selected_arch = arch; |
7481 | return 1; | |
7482 | } | |
7483 | ||
7484 | /* Set the architecture extension, issuing errors if it is | |
7485 | unrecognized, or invalid */ | |
7486 | ||
7487 | static int | |
7488 | m68k_set_extension (char const *name, int allow_m, int silent) | |
7489 | { | |
7490 | int negated; | |
7491 | const struct m68k_cpu *ext; | |
7492 | ||
7493 | ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); | |
7494 | ||
7495 | if (!ext) | |
7496 | { | |
7497 | if (!silent) | |
7498 | as_bad (_("extension `%s' unrecognized"), name); | |
7499 | return 0; | |
7500 | } | |
7501 | ||
7502 | if (negated) | |
87298967 NS |
7503 | not_current_architecture |= (ext->control_regs |
7504 | ? *(unsigned *)ext->control_regs: ext->arch); | |
266abb8f NS |
7505 | else |
7506 | current_architecture |= ext->arch; | |
7507 | return 1; | |
7508 | } | |
7509 | ||
31302357 AS |
7510 | /* md_parse_option |
7511 | Invocation line includes a switch not recognized by the base assembler. | |
266abb8f | 7512 | */ |
252b5132 RH |
7513 | |
7514 | #ifdef OBJ_ELF | |
5a38dc70 | 7515 | const char *md_shortopts = "lSA:m:kQ:V"; |
252b5132 | 7516 | #else |
5a38dc70 | 7517 | const char *md_shortopts = "lSA:m:k"; |
252b5132 RH |
7518 | #endif |
7519 | ||
7520 | struct option md_longopts[] = { | |
7521 | #define OPTION_PIC (OPTION_MD_BASE) | |
7522 | {"pic", no_argument, NULL, OPTION_PIC}, | |
7523 | #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) | |
7524 | {"register-prefix-optional", no_argument, NULL, | |
7525 | OPTION_REGISTER_PREFIX_OPTIONAL}, | |
7526 | #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) | |
7527 | {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, | |
7528 | #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) | |
7529 | {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, | |
7530 | #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) | |
7531 | {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, | |
7532 | #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) | |
7533 | {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, | |
7534 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) | |
7535 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, | |
28e7409f NC |
7536 | #define OPTION_PCREL (OPTION_MD_BASE + 7) |
7537 | {"pcrel", no_argument, NULL, OPTION_PCREL}, | |
252b5132 RH |
7538 | {NULL, no_argument, NULL, 0} |
7539 | }; | |
bc805888 | 7540 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
7541 | |
7542 | int | |
31302357 | 7543 | md_parse_option (int c, char *arg) |
252b5132 RH |
7544 | { |
7545 | switch (c) | |
7546 | { | |
7547 | case 'l': /* -l means keep external to 2 bit offset | |
36759679 | 7548 | rather than 16 bit one. */ |
252b5132 RH |
7549 | flag_short_refs = 1; |
7550 | break; | |
7551 | ||
7552 | case 'S': /* -S means that jbsr's always turn into | |
7553 | jsr's. */ | |
7554 | flag_long_jumps = 1; | |
7555 | break; | |
7556 | ||
28e7409f NC |
7557 | case OPTION_PCREL: /* --pcrel means never turn PC-relative |
7558 | branches into absolute jumps. */ | |
7559 | flag_keep_pcrel = 1; | |
7560 | break; | |
7561 | ||
252b5132 RH |
7562 | case OPTION_PIC: |
7563 | case 'k': | |
7564 | flag_want_pic = 1; | |
36759679 | 7565 | break; /* -pic, Position Independent Code. */ |
252b5132 RH |
7566 | |
7567 | case OPTION_REGISTER_PREFIX_OPTIONAL: | |
7568 | flag_reg_prefix_optional = 1; | |
7569 | reg_prefix_optional_seen = 1; | |
7570 | break; | |
7571 | ||
7572 | /* -V: SVR4 argument to print version ID. */ | |
7573 | case 'V': | |
7574 | print_version_id (); | |
7575 | break; | |
7576 | ||
7577 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
7578 | should be emitted or not. FIXME: Not implemented. */ | |
7579 | case 'Q': | |
7580 | break; | |
7581 | ||
7582 | case OPTION_BITWISE_OR: | |
7583 | { | |
7584 | char *n, *t; | |
7585 | const char *s; | |
7586 | ||
7587 | n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); | |
7588 | t = n; | |
7589 | for (s = m68k_comment_chars; *s != '\0'; s++) | |
7590 | if (*s != '|') | |
7591 | *t++ = *s; | |
7592 | *t = '\0'; | |
7593 | m68k_comment_chars = n; | |
7594 | } | |
7595 | break; | |
7596 | ||
7597 | case OPTION_BASE_SIZE_DEFAULT_16: | |
7598 | m68k_index_width_default = SIZE_WORD; | |
7599 | break; | |
7600 | ||
7601 | case OPTION_BASE_SIZE_DEFAULT_32: | |
7602 | m68k_index_width_default = SIZE_LONG; | |
7603 | break; | |
7604 | ||
7605 | case OPTION_DISP_SIZE_DEFAULT_16: | |
7606 | m68k_rel32 = 0; | |
7607 | m68k_rel32_from_cmdline = 1; | |
7608 | break; | |
7609 | ||
7610 | case OPTION_DISP_SIZE_DEFAULT_32: | |
7611 | m68k_rel32 = 1; | |
7612 | m68k_rel32_from_cmdline = 1; | |
7613 | break; | |
7614 | ||
266abb8f NS |
7615 | case 'A': |
7616 | #if WARN_DEPRECATED | |
7617 | as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", | |
7618 | arg, arg)); | |
7619 | #endif | |
7620 | /* Intentional fall-through. */ | |
7621 | case 'm': | |
7622 | if (!strncmp (arg, "arch=", 5)) | |
7623 | m68k_set_arch (arg + 5, 1, 0); | |
7624 | else if (!strncmp (arg, "cpu=", 4)) | |
7625 | m68k_set_cpu (arg + 4, 1, 0); | |
7626 | else if (m68k_set_extension (arg, 0, 1)) | |
7627 | ; | |
0b2e31dc NS |
7628 | else if (m68k_set_arch (arg, 0, 1)) |
7629 | ; | |
266abb8f NS |
7630 | else if (m68k_set_cpu (arg, 0, 1)) |
7631 | ; | |
7632 | else | |
7633 | return 0; | |
7634 | break; | |
7635 | ||
252b5132 RH |
7636 | default: |
7637 | return 0; | |
7638 | } | |
7639 | ||
7640 | return 1; | |
7641 | } | |
7642 | ||
266abb8f NS |
7643 | /* Setup tables from the selected arch and/or cpu */ |
7644 | ||
7645 | static void | |
7646 | m68k_init_arch (void) | |
7647 | { | |
266abb8f NS |
7648 | if (not_current_architecture & current_architecture) |
7649 | { | |
7650 | as_bad (_("architecture features both enabled and disabled")); | |
7651 | not_current_architecture &= ~current_architecture; | |
7652 | } | |
7653 | if (selected_arch) | |
2da12c60 NS |
7654 | { |
7655 | current_architecture |= selected_arch->arch; | |
7656 | control_regs = selected_arch->control_regs; | |
7657 | } | |
0b2e31dc NS |
7658 | else |
7659 | current_architecture |= selected_cpu->arch; | |
3739860c | 7660 | |
2da12c60 NS |
7661 | current_architecture &= ~not_current_architecture; |
7662 | ||
377260ba NS |
7663 | if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) |
7664 | { | |
7665 | /* Determine which float is really meant. */ | |
7666 | if (current_architecture & (m68k_mask & ~m68881)) | |
7667 | current_architecture ^= cfloat; | |
7668 | else | |
7669 | current_architecture ^= m68881; | |
7670 | } | |
7671 | ||
0b2e31dc | 7672 | if (selected_cpu) |
266abb8f | 7673 | { |
2da12c60 | 7674 | control_regs = selected_cpu->control_regs; |
0b2e31dc | 7675 | if (current_architecture & ~selected_cpu->arch) |
266abb8f | 7676 | { |
0b2e31dc NS |
7677 | as_bad (_("selected processor does not have all features of selected architecture")); |
7678 | current_architecture | |
7679 | = selected_cpu->arch & ~not_current_architecture; | |
266abb8f NS |
7680 | } |
7681 | } | |
266abb8f | 7682 | |
266abb8f NS |
7683 | if ((current_architecture & m68k_mask) |
7684 | && (current_architecture & ~m68k_mask)) | |
7685 | { | |
7686 | as_bad (_ ("m68k and cf features both selected")); | |
0b2e31dc | 7687 | if (current_architecture & m68k_mask) |
266abb8f NS |
7688 | current_architecture &= m68k_mask; |
7689 | else | |
7690 | current_architecture &= ~m68k_mask; | |
7691 | } | |
3739860c | 7692 | |
266abb8f NS |
7693 | /* Permit m68881 specification with all cpus; those that can't work |
7694 | with a coprocessor could be doing emulation. */ | |
7695 | if (current_architecture & m68851) | |
7696 | { | |
7697 | if (current_architecture & m68040) | |
7698 | as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); | |
7699 | } | |
7700 | /* What other incompatibilities could we check for? */ | |
7701 | ||
266abb8f NS |
7702 | if (cpu_of_arch (current_architecture) < m68020 |
7703 | || arch_coldfire_p (current_architecture)) | |
7704 | md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; | |
3739860c | 7705 | |
266abb8f NS |
7706 | initialized = 1; |
7707 | } | |
7708 | ||
252b5132 | 7709 | void |
31302357 | 7710 | md_show_usage (FILE *stream) |
252b5132 | 7711 | { |
76f57f3a | 7712 | const char *default_cpu = TARGET_CPU; |
f1f5ef86 | 7713 | int i; |
76f57f3a | 7714 | |
8a104df9 | 7715 | /* Get the canonical name for the default target CPU. */ |
76f57f3a JT |
7716 | if (*default_cpu == 'm') |
7717 | default_cpu++; | |
266abb8f | 7718 | for (i = 0; m68k_cpus[i].name; i++) |
76f57f3a | 7719 | { |
266abb8f | 7720 | if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) |
76f57f3a | 7721 | { |
2da12c60 NS |
7722 | while (m68k_cpus[i].alias > 0) |
7723 | i--; | |
7724 | while (m68k_cpus[i].alias < 0) | |
7725 | i++; | |
7726 | default_cpu = m68k_cpus[i].name; | |
76f57f3a JT |
7727 | } |
7728 | } | |
7729 | ||
bc805888 | 7730 | fprintf (stream, _("\ |
266abb8f NS |
7731 | -march=<arch> set architecture\n\ |
7732 | -mcpu=<cpu> set cpu [default %s]\n\ | |
7733 | "), default_cpu); | |
7734 | for (i = 0; m68k_extensions[i].name; i++) | |
7735 | fprintf (stream, _("\ | |
0b2e31dc NS |
7736 | -m[no-]%-16s enable/disable%s architecture extension\n\ |
7737 | "), m68k_extensions[i].name, | |
7738 | m68k_extensions[i].alias > 0 ? " ColdFire" | |
7739 | : m68k_extensions[i].alias < 0 ? " m68k" : ""); | |
3739860c | 7740 | |
bc805888 | 7741 | fprintf (stream, _("\ |
266abb8f | 7742 | -l use 1 word for refs to undefined symbols [default 2]\n\ |
252b5132 RH |
7743 | -pic, -k generate position independent code\n\ |
7744 | -S turn jbsr into jsr\n\ | |
28e7409f | 7745 | --pcrel never turn PC-relative branches into absolute jumps\n\ |
252b5132 RH |
7746 | --register-prefix-optional\n\ |
7747 | recognize register names without prefix character\n\ | |
266abb8f | 7748 | --bitwise-or do not treat `|' as a comment character\n\ |
252b5132 RH |
7749 | --base-size-default-16 base reg without size is 16 bits\n\ |
7750 | --base-size-default-32 base reg without size is 32 bits (default)\n\ | |
7751 | --disp-size-default-16 displacement with unknown size is 16 bits\n\ | |
266abb8f NS |
7752 | --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ |
7753 | ")); | |
3739860c | 7754 | |
266abb8f NS |
7755 | fprintf (stream, _("Architecture variants are: ")); |
7756 | for (i = 0; m68k_archs[i].name; i++) | |
7757 | { | |
7758 | if (i) | |
7759 | fprintf (stream, " | "); | |
87298967 | 7760 | fprintf (stream, "%s", m68k_archs[i].name); |
266abb8f NS |
7761 | } |
7762 | fprintf (stream, "\n"); | |
7763 | ||
7764 | fprintf (stream, _("Processor variants are: ")); | |
7765 | for (i = 0; m68k_cpus[i].name; i++) | |
7766 | { | |
7767 | if (i) | |
7768 | fprintf (stream, " | "); | |
87298967 | 7769 | fprintf (stream, "%s", m68k_cpus[i].name); |
266abb8f NS |
7770 | } |
7771 | fprintf (stream, _("\n")); | |
252b5132 RH |
7772 | } |
7773 | \f | |
7774 | #ifdef TEST2 | |
7775 | ||
7776 | /* TEST2: Test md_assemble() */ | |
36759679 NC |
7777 | /* Warning, this routine probably doesn't work anymore. */ |
7778 | int | |
31302357 | 7779 | main (void) |
252b5132 RH |
7780 | { |
7781 | struct m68k_it the_ins; | |
7782 | char buf[120]; | |
7783 | char *cp; | |
7784 | int n; | |
7785 | ||
7786 | m68k_ip_begin (); | |
7787 | for (;;) | |
7788 | { | |
7789 | if (!gets (buf) || !*buf) | |
7790 | break; | |
7791 | if (buf[0] == '|' || buf[1] == '.') | |
7792 | continue; | |
7793 | for (cp = buf; *cp; cp++) | |
7794 | if (*cp == '\t') | |
7795 | *cp = ' '; | |
7796 | if (is_label (buf)) | |
7797 | continue; | |
7798 | memset (&the_ins, '\0', sizeof (the_ins)); | |
7799 | m68k_ip (&the_ins, buf); | |
7800 | if (the_ins.error) | |
7801 | { | |
7802 | printf (_("Error %s in %s\n"), the_ins.error, buf); | |
7803 | } | |
7804 | else | |
7805 | { | |
7806 | printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); | |
7807 | for (n = 0; n < the_ins.numo; n++) | |
7808 | printf (" 0x%x", the_ins.opcode[n] & 0xffff); | |
7809 | printf (" "); | |
7810 | print_the_insn (&the_ins.opcode[0], stdout); | |
7811 | (void) putchar ('\n'); | |
7812 | } | |
7813 | for (n = 0; n < strlen (the_ins.args) / 2; n++) | |
7814 | { | |
7815 | if (the_ins.operands[n].error) | |
7816 | { | |
7817 | printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); | |
7818 | continue; | |
7819 | } | |
31302357 AS |
7820 | printf ("mode %d, reg %d, ", the_ins.operands[n].mode, |
7821 | the_ins.operands[n].reg); | |
252b5132 | 7822 | if (the_ins.operands[n].b_const) |
31302357 AS |
7823 | printf ("Constant: '%.*s', ", |
7824 | 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, | |
7825 | the_ins.operands[n].b_const); | |
7826 | printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, | |
7827 | the_ins.operands[n].isiz, the_ins.operands[n].imul); | |
252b5132 | 7828 | if (the_ins.operands[n].b_iadd) |
31302357 AS |
7829 | printf ("Iadd: '%.*s',", |
7830 | 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, | |
7831 | the_ins.operands[n].b_iadd); | |
7832 | putchar ('\n'); | |
252b5132 RH |
7833 | } |
7834 | } | |
7835 | m68k_ip_end (); | |
7836 | return 0; | |
7837 | } | |
7838 | ||
31302357 AS |
7839 | int |
7840 | is_label (char *str) | |
252b5132 RH |
7841 | { |
7842 | while (*str == ' ') | |
7843 | str++; | |
7844 | while (*str && *str != ' ') | |
7845 | str++; | |
7846 | if (str[-1] == ':' || str[1] == '=') | |
7847 | return 1; | |
7848 | return 0; | |
7849 | } | |
7850 | ||
7851 | #endif | |
7852 | ||
7853 | /* Possible states for relaxation: | |
7854 | ||
7855 | 0 0 branch offset byte (bra, etc) | |
7856 | 0 1 word | |
7857 | 0 2 long | |
7858 | ||
7859 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc | |
7860 | 1 1 word | |
7861 | 1 2 long | |
7862 | ||
7863 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc | |
7864 | 2 1 word-long | |
7865 | 2 2 long-word | |
7866 | 2 3 long-long | |
7867 | ||
7868 | */ | |
7869 | ||
7870 | /* We have no need to default values of symbols. */ | |
7871 | ||
252b5132 | 7872 | symbolS * |
31302357 | 7873 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
7874 | { |
7875 | return 0; | |
7876 | } | |
7877 | ||
7878 | /* Round up a section size to the appropriate boundary. */ | |
7879 | valueT | |
31302357 | 7880 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
7881 | { |
7882 | #ifdef OBJ_AOUT | |
252b5132 RH |
7883 | /* For a.out, force the section size to be aligned. If we don't do |
7884 | this, BFD will align it for us, but it will not write out the | |
7885 | final bytes of the section. This may be a bug in BFD, but it is | |
7886 | easier to fix it here since that is how the other a.out targets | |
7887 | work. */ | |
7888 | int align; | |
7889 | ||
7890 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 7891 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
252b5132 RH |
7892 | #endif |
7893 | ||
7894 | return size; | |
7895 | } | |
7896 | ||
7897 | /* Exactly what point is a PC-relative offset relative TO? | |
7898 | On the 68k, it is relative to the address of the first extension | |
7899 | word. The difference between the addresses of the offset and the | |
92774660 | 7900 | first extension word is stored in fx_pcrel_adjust. */ |
252b5132 | 7901 | long |
31302357 | 7902 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
7903 | { |
7904 | int adjust; | |
7905 | ||
552c607f | 7906 | adjust = fixP->fx_pcrel_adjust; |
252b5132 RH |
7907 | if (adjust == 64) |
7908 | adjust = -1; | |
7909 | return fixP->fx_where + fixP->fx_frag->fr_address - adjust; | |
7910 | } | |
7911 | ||
0d96863f | 7912 | #ifdef OBJ_ELF |
8a104df9 | 7913 | void |
31302357 | 7914 | m68k_elf_final_processing (void) |
0d96863f | 7915 | { |
266abb8f | 7916 | unsigned flags = 0; |
3739860c | 7917 | |
238d258f | 7918 | if (arch_coldfire_fpu (current_architecture)) |
266abb8f NS |
7919 | flags |= EF_M68K_CFV4E; |
7920 | /* Set file-specific flags if this is a cpu32 processor. */ | |
8a104df9 | 7921 | if (cpu_of_arch (current_architecture) & cpu32) |
3bdcfdf4 KH |
7922 | flags |= EF_M68K_CPU32; |
7923 | else if (cpu_of_arch (current_architecture) & fido_a) | |
7924 | flags |= EF_M68K_FIDO; | |
8a104df9 KH |
7925 | else if ((cpu_of_arch (current_architecture) & m68000up) |
7926 | && !(cpu_of_arch (current_architecture) & m68020up)) | |
266abb8f | 7927 | flags |= EF_M68K_M68000; |
3739860c | 7928 | |
266abb8f NS |
7929 | if (current_architecture & mcfisa_a) |
7930 | { | |
0b2e31dc NS |
7931 | static const unsigned isa_features[][2] = |
7932 | { | |
9a2e615a | 7933 | {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, |
c694fd50 | 7934 | {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, |
9a2e615a | 7935 | {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, |
c694fd50 KH |
7936 | {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, |
7937 | {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, | |
9a2e615a | 7938 | {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, |
8d100c32 | 7939 | {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, |
0b2e31dc NS |
7940 | {0,0}, |
7941 | }; | |
7942 | static const unsigned mac_features[][2] = | |
7943 | { | |
c694fd50 KH |
7944 | {EF_M68K_CF_MAC, mcfmac}, |
7945 | {EF_M68K_CF_EMAC, mcfemac}, | |
0b2e31dc NS |
7946 | {0,0}, |
7947 | }; | |
7948 | unsigned ix; | |
7949 | unsigned pattern; | |
3739860c | 7950 | |
0b2e31dc | 7951 | pattern = (current_architecture |
9a2e615a | 7952 | & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); |
0b2e31dc NS |
7953 | for (ix = 0; isa_features[ix][1]; ix++) |
7954 | { | |
7955 | if (pattern == isa_features[ix][1]) | |
7956 | { | |
7957 | flags |= isa_features[ix][0]; | |
7958 | break; | |
7959 | } | |
7960 | } | |
7961 | if (!isa_features[ix][1]) | |
7962 | { | |
7963 | cf_bad: | |
7964 | as_warn (_("Not a defined coldfire architecture")); | |
7965 | } | |
7966 | else | |
7967 | { | |
7968 | if (current_architecture & cfloat) | |
c694fd50 | 7969 | flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; |
266abb8f | 7970 | |
0b2e31dc NS |
7971 | pattern = current_architecture & (mcfmac|mcfemac); |
7972 | if (pattern) | |
7973 | { | |
7974 | for (ix = 0; mac_features[ix][1]; ix++) | |
7975 | { | |
7976 | if (pattern == mac_features[ix][1]) | |
7977 | { | |
7978 | flags |= mac_features[ix][0]; | |
7979 | break; | |
7980 | } | |
7981 | } | |
7982 | if (!mac_features[ix][1]) | |
7983 | goto cf_bad; | |
7984 | } | |
7985 | } | |
266abb8f NS |
7986 | } |
7987 | elf_elfheader (stdoutput)->e_flags |= flags; | |
0d96863f | 7988 | } |
cf869cce NC |
7989 | |
7990 | /* Parse @TLSLDO and return the desired relocation. */ | |
7991 | static bfd_reloc_code_real_type | |
7992 | m68k_elf_suffix (char **str_p, expressionS *exp_p) | |
7993 | { | |
7994 | char ident[20]; | |
7995 | char *str = *str_p; | |
7996 | char *str2; | |
7997 | int ch; | |
7998 | int len; | |
7999 | ||
8000 | if (*str++ != '@') | |
8001 | return BFD_RELOC_UNUSED; | |
8002 | ||
8003 | for (ch = *str, str2 = ident; | |
8004 | (str2 < ident + sizeof (ident) - 1 | |
8005 | && (ISALNUM (ch) || ch == '@')); | |
8006 | ch = *++str) | |
8007 | { | |
8008 | *str2++ = ch; | |
8009 | } | |
8010 | ||
8011 | *str2 = '\0'; | |
8012 | len = str2 - ident; | |
8013 | ||
8014 | if (strncmp (ident, "TLSLDO", 6) == 0 | |
8015 | && len == 6) | |
8016 | { | |
8017 | /* Now check for identifier@suffix+constant. */ | |
8018 | if (*str == '-' || *str == '+') | |
8019 | { | |
8020 | char *orig_line = input_line_pointer; | |
8021 | expressionS new_exp; | |
8022 | ||
8023 | input_line_pointer = str; | |
8024 | expression (&new_exp); | |
8025 | if (new_exp.X_op == O_constant) | |
8026 | { | |
8027 | exp_p->X_add_number += new_exp.X_add_number; | |
8028 | str = input_line_pointer; | |
8029 | } | |
8030 | ||
8031 | if (&input_line_pointer != str_p) | |
8032 | input_line_pointer = orig_line; | |
8033 | } | |
8034 | *str_p = str; | |
8035 | ||
8036 | return BFD_RELOC_68K_TLS_LDO32; | |
8037 | } | |
8038 | ||
8039 | return BFD_RELOC_UNUSED; | |
8040 | } | |
8041 | ||
8042 | /* Handles .long <tls_symbol>+0x8000 debug info. | |
8043 | Clobbers input_line_pointer, checks end-of-line. | |
8044 | Adapted from tc-ppc.c:ppc_elf_cons. */ | |
8045 | static void | |
8046 | m68k_elf_cons (int nbytes /* 4=.long */) | |
8047 | { | |
8048 | if (is_it_end_of_statement ()) | |
8049 | { | |
8050 | demand_empty_rest_of_line (); | |
8051 | return; | |
8052 | } | |
8053 | ||
8054 | do | |
8055 | { | |
8056 | expressionS exp; | |
8057 | bfd_reloc_code_real_type reloc; | |
8058 | ||
8059 | expression (&exp); | |
8060 | if (exp.X_op == O_symbol | |
8061 | && *input_line_pointer == '@' | |
8062 | && (reloc = m68k_elf_suffix (&input_line_pointer, | |
8063 | &exp)) != BFD_RELOC_UNUSED) | |
8064 | { | |
8065 | reloc_howto_type *reloc_howto; | |
8066 | int size; | |
8067 | ||
8068 | reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
8069 | size = bfd_get_reloc_size (reloc_howto); | |
8070 | ||
8071 | if (size > nbytes) | |
8072 | { | |
8073 | as_bad (_("%s relocations do not fit in %d bytes\n"), | |
8074 | reloc_howto->name, nbytes); | |
8075 | } | |
8076 | else | |
8077 | { | |
8078 | char *p; | |
8079 | int offset; | |
8080 | ||
8081 | p = frag_more (nbytes); | |
8082 | offset = 0; | |
8083 | if (target_big_endian) | |
8084 | offset = nbytes - size; | |
8085 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, | |
8086 | &exp, 0, reloc); | |
8087 | } | |
8088 | } | |
8089 | else | |
8090 | emit_expr (&exp, (unsigned int) nbytes); | |
8091 | } | |
8092 | while (*input_line_pointer++ == ','); | |
8093 | ||
8094 | /* Put terminator back into stream. */ | |
8095 | input_line_pointer--; | |
8096 | demand_empty_rest_of_line (); | |
8097 | } | |
0d96863f | 8098 | #endif |
c04898f8 AS |
8099 | |
8100 | int | |
1df69f4f | 8101 | tc_m68k_regname_to_dw2regnum (char *regname) |
c04898f8 AS |
8102 | { |
8103 | unsigned int regnum; | |
8104 | static const char *const regnames[] = | |
8105 | { | |
8106 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
8107 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", | |
8108 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", | |
8109 | "pc" | |
8110 | }; | |
8111 | ||
8112 | for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) | |
8113 | if (strcmp (regname, regnames[regnum]) == 0) | |
8114 | return regnum; | |
8115 | ||
8116 | return -1; | |
8117 | } | |
8118 | ||
8119 | void | |
8120 | tc_m68k_frame_initial_instructions (void) | |
8121 | { | |
8122 | static int sp_regno = -1; | |
8123 | ||
8124 | if (sp_regno < 0) | |
8125 | sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); | |
8126 | ||
8127 | cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); | |
8128 | cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); | |
8129 | } | |
909c7f9c NC |
8130 | |
8131 | /* Check and emit error if broken-word handling has failed to fix up a | |
8132 | case-table. This is called from write.c, after doing everything it | |
8133 | knows about how to handle broken words. */ | |
8134 | ||
8135 | void | |
8136 | tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) | |
8137 | { | |
8138 | if (new_offset > 32767 || new_offset < -32768) | |
8139 | as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, | |
8140 | _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."), | |
8141 | (long) new_offset); | |
8142 | } | |
8143 |