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2007-04-19 Paul Brook <paul@codesourcery.com>
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
266abb8f 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
2da12c60 179static const enum m68k_register mcf5208_ctrl[] = {
266abb8f
NS		 180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182};
96e0bbcc
NS		 183static const enum m68k_register mcf5210a_ctrl[] = {
184 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
185 0
186};
2da12c60 187static const enum m68k_register mcf5213_ctrl[] = {
266abb8f
NS		 188 VBR, RAMBAR, FLASHBAR,
189 0
190};
2da12c60
NS		 191static const enum m68k_register mcf5216_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
266abb8f
NS		 193 0
194};
96e0bbcc
NS		 195static const enum m68k_register mcf52235_ctrl[] = {
196 VBR, FLASHBAR, RAMBAR,
197 0
198};
199static const enum m68k_register mcf5225_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR,
201 0
202};
2da12c60
NS		 203static const enum m68k_register mcf5235_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
e80e0390
NC		 205 0
206};
2da12c60
NS		 207static const enum m68k_register mcf5249_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
3e602632
NC		 209 0
210};
2da12c60
NS		 211static const enum m68k_register mcf5250_ctrl[] = {
212 VBR,
213 0
214};
215static const enum m68k_register mcf5271_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR,
217 0
218};
219static const enum m68k_register mcf5272_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
221 0
222};
223static const enum m68k_register mcf5275_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226};
227static const enum m68k_register mcf5282_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
229 0
230};
231static const enum m68k_register mcf5329_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR,
233 0
234};
235static const enum m68k_register mcf5373_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR,
237 0
238};
239static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 240 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
241 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
242 MBAR, SECMBAR,
243 MPCR /* Multiprocessor Control register */,
244 EDRAMBAR /* Embedded DRAM Base Address Register */,
245 /* Permutation control registers. */
3e602632
NC		 246 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
247 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 248 /* Legacy names */
249 TC /* ASID */, BUSCR /* MMUBAR */,
250 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
251 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
252 ROMBAR /* ROMBAR0 */,
253 0
254};
255static const enum m68k_register mcf5475_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
258 /* Legacy names */
259 TC /* ASID */, BUSCR /* MMUBAR */,
260 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
261 MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
262 0
263};
264static const enum m68k_register mcf5485_ctrl[] = {
265 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
266 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
267 /* Legacy names */
268 TC /* ASID */, BUSCR /* MMUBAR */,
269 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
270 MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
3e602632
NC		 271 0
272};
f7ec513b
KH		 273static const enum m68k_register fido_ctrl[] = {
274 SFC, DFC, USP, VBR, CAC, MBB,
275 0
276};
2da12c60 277#define cpu32_ctrl m68010_ctrl
252b5132
RH		 278
279static const enum m68k_register *control_regs;
280
36759679 281/* Internal form of a 68020 instruction. */
252b5132
RH		 282struct m68k_it
283{
284 const char *error;
36759679 285 const char *args; /* List of opcode info. */
252b5132
RH		 286 int numargs;
287
36759679 288 int numo; /* Number of shorts in opcode. */
252b5132
RH		 289 short opcode[11];
290
291 struct m68k_op operands[6];
292
36759679 293 int nexp; /* Number of exprs in use. */
252b5132
RH		 294 struct m68k_exp exprs[4];
295
36759679 296 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 297 struct
298 {
36759679 299 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 300 symbolS *fadd;
301 offsetT foff;
302 int fragty;
303 }
304 fragb[4];
305
36759679 306 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 307 struct
308 {
309 int n;
310 expressionS exp;
311 char wid;
312 char pcrel;
313 /* In a pc relative address the difference between the address
314 of the offset and the address that the offset is relative
315 to. This depends on the addressing mode. Basically this
316 is the value to put in the offset field to address the
317 first byte of the offset, without regarding the special
318 significance of some values (in the branch instruction, for
319 example). */
320 int pcrel_fix;
321#ifdef OBJ_ELF
322 /* Whether this expression needs special pic relocation, and if
323 so, which. */
324 enum pic_relocation pic_reloc;
325#endif
326 }
36759679 327 reloc[5]; /* Five is enough??? */
252b5132
RH		 328};
329
9840d27e 330#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 331#define float_of_arch(x) ((x) & mfloat)
332#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 333#define arch_coldfire_p(x) ((x) & mcfisa_a)
334#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 335
36759679 336/* Macros for determining if cpu supports a specific addressing mode. */
d0e8669a 337#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
252b5132 338
36759679 339static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 340
341#define op(ex) ((ex)->exp.X_op)
342#define adds(ex) ((ex)->exp.X_add_symbol)
343#define subs(ex) ((ex)->exp.X_op_symbol)
344#define offs(ex) ((ex)->exp.X_add_number)
345
36759679 346/* Macros for adding things to the m68k_it struct. */
31302357 347#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 348
36759679
NC		 349/* Like addword, but goes BEFORE general operands. */
350
252b5132 351static void
31302357 352insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 353{
354 int z;
07726851 355 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 356 the_ins.opcode[z] = the_ins.opcode[z - 1];
357 for (z = 0; z < the_ins.nrel; z++)
358 the_ins.reloc[z].n += 2;
252b5132
RH		 359 for (z = 0; z < the_ins.nfrag; z++)
360 the_ins.fragb[z].fragoff++;
8a104df9 361 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 362 the_ins.numo++;
363}
364
365/* The numo+1 kludge is so we can hit the low order byte of the prev word.
366 Blecch. */
367static void
31302357 368add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 369{
31302357
AS		 370 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
371 ? the_ins.numo * 2 - 1
372 : (width == 'b'
373 ? the_ins.numo * 2 + 1
374 : the_ins.numo * 2));
252b5132
RH		 375 the_ins.reloc[the_ins.nrel].exp = exp->exp;
376 the_ins.reloc[the_ins.nrel].wid = width;
377 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
378#ifdef OBJ_ELF
379 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
380#endif
381 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
382}
383
384/* Cause an extra frag to be generated here, inserting up to 10 bytes
385 (that value is chosen in the frag_var call in md_assemble). TYPE
386 is the subtype of the frag to be generated; its primary type is
387 rs_machine_dependent.
388
389 The TYPE parameter is also used by md_convert_frag_1 and
390 md_estimate_size_before_relax. The appropriate type of fixup will
391 be emitted by md_convert_frag_1.
392
393 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
394static void
31302357 395add_frag (symbolS *add, offsetT off, int type)
252b5132 396{
8a104df9
KH		 397 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
398 the_ins.fragb[the_ins.nfrag].fadd = add;
399 the_ins.fragb[the_ins.nfrag].foff = off;
400 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 401}
402
403#define isvar(ex) \
404 (op (ex) != O_constant && op (ex) != O_big)
405
31302357
AS		 406static char *crack_operand (char *str, struct m68k_op *opP);
407static int get_num (struct m68k_exp *exp, int ok);
408static int reverse_16_bits (int in);
409static int reverse_8_bits (int in);
410static void install_gen_operand (int mode, int val);
411static void install_operand (int mode, int val);
412static void s_bss (int);
413static void s_data1 (int);
414static void s_data2 (int);
415static void s_even (int);
416static void s_proc (int);
417static void s_chip (int);
418static void s_fopt (int);
419static void s_opt (int);
420static void s_reg (int);
421static void s_restore (int);
422static void s_save (int);
423static void s_mri_if (int);
424static void s_mri_else (int);
425static void s_mri_endi (int);
426static void s_mri_break (int);
427static void s_mri_next (int);
428static void s_mri_for (int);
429static void s_mri_endf (int);
430static void s_mri_repeat (int);
431static void s_mri_until (int);
432static void s_mri_while (int);
433static void s_mri_endw (int);
266abb8f
NS		 434static void s_m68k_cpu (int);
435static void s_m68k_arch (int);
436
437struct m68k_cpu
438{
439 unsigned long arch; /* Architecture features. */
2da12c60 440 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 441 const char *name; /* Name */
0b2e31dc
NS		 442 int alias; /* Alias for a cannonical name. If 1, then
443 succeeds canonical name, if -1 then
444 succeeds canonical name, if <-1 ||>1 this is a
445 deprecated name, and the next/previous name
446 should be used. */
266abb8f 447};
252b5132 448
266abb8f
NS		 449/* We hold flags for features explicitly enabled and explicitly
450 disabled. */
252b5132 451static int current_architecture;
266abb8f 452static int not_current_architecture;
266abb8f
NS		 453static const struct m68k_cpu *selected_arch;
454static const struct m68k_cpu *selected_cpu;
455static int initialized;
252b5132 456
266abb8f
NS		 457/* Architecture models. */
458static const struct m68k_cpu m68k_archs[] =
459{
2da12c60
NS		 460 {m68000, m68000_ctrl, "68000", 0},
461 {m68010, m68010_ctrl, "68010", 0},
462 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
463 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
464 {m68040, m68040_ctrl, "68040", 0},
465 {m68060, m68060_ctrl, "68060", 0},
466 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 467 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 468 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
469 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
470 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
471 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
472 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 473 {0,0,NULL, 0}
474};
252b5132 475
0b2e31dc
NS		 476/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
477 for either. */
266abb8f
NS		 478static const struct m68k_cpu m68k_extensions[] =
479{
2da12c60
NS		 480 {m68851, NULL, "68851", -1},
481 {m68881, NULL, "68881", -1},
482 {m68881, NULL, "68882", -1},
0b2e31dc 483
2da12c60 484 {cfloat|m68881, NULL, "float", 0},
266abb8f 485
2da12c60
NS		 486 {mcfhwdiv, NULL, "div", 1},
487 {mcfusp, NULL, "usp", 1},
488 {mcfmac, NULL, "mac", 1},
489 {mcfemac, NULL, "emac", 1},
266abb8f 490
2da12c60 491 {0,NULL,NULL, 0}
266abb8f
NS		 492};
493
494/* Processor list */
495static const struct m68k_cpu m68k_cpus[] =
496{
2da12c60
NS		 497 {m68000, m68000_ctrl, "68000", 0},
498 {m68000, m68000_ctrl, "68ec000", 1},
499 {m68000, m68000_ctrl, "68hc000", 1},
500 {m68000, m68000_ctrl, "68hc001", 1},
501 {m68000, m68000_ctrl, "68008", 1},
502 {m68000, m68000_ctrl, "68302", 1},
503 {m68000, m68000_ctrl, "68306", 1},
504 {m68000, m68000_ctrl, "68307", 1},
505 {m68000, m68000_ctrl, "68322", 1},
506 {m68000, m68000_ctrl, "68356", 1},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
510 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
511 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
512 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
513 {m68040, m68040_ctrl, "68040", 0},
514 {m68040, m68040_ctrl, "68ec040", 1},
515 {m68060, m68060_ctrl, "68060", 0},
516 {m68060, m68060_ctrl, "68ec060", 1},
517
518 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
519 {cpu32|m68881, cpu32_ctrl, "68330", 1},
520 {cpu32|m68881, cpu32_ctrl, "68331", 1},
521 {cpu32|m68881, cpu32_ctrl, "68332", 1},
522 {cpu32|m68881, cpu32_ctrl, "68333", 1},
523 {cpu32|m68881, cpu32_ctrl, "68334", 1},
524 {cpu32|m68881, cpu32_ctrl, "68336", 1},
525 {cpu32|m68881, cpu32_ctrl, "68340", 1},
526 {cpu32|m68881, cpu32_ctrl, "68341", 1},
527 {cpu32|m68881, cpu32_ctrl, "68349", 1},
528 {cpu32|m68881, cpu32_ctrl, "68360", 1},
529
530 {mcfisa_a, mcf_ctrl, "5200", 0},
531 {mcfisa_a, mcf_ctrl, "5202", 1},
532 {mcfisa_a, mcf_ctrl, "5204", 1},
533 {mcfisa_a, mcf_ctrl, "5206", 1},
534
535 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
536
537 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
538 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
539
96e0bbcc
NS		 540 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
541 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
542
2da12c60
NS		 543 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
544 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
546
547 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
548 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
549 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
550
96e0bbcc
NS		 551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
552 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
554 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
555
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
558
2da12c60
NS		 559 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
562 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
563 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
564
565 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
566 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
567
568 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
569 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
570
571 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
572
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
579 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
580
581 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
582
583 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
587
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
591
592 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
593
a8e24a56
NS		 594 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
595 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
596 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
597 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
598 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
599 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
600 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 601
a8e24a56
NS		 602 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
603 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
604 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
605 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
606 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
607 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
608 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 609
b3768379 610 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 611 {fido_a, fido_ctrl, "fido", 1},
9840d27e 612
2da12c60 613 {0,NULL,NULL, 0}
dc84e067 614 };
252b5132 615
266abb8f
NS		 616static const struct m68k_cpu *m68k_lookup_cpu
617(const char *, const struct m68k_cpu *, int, int *);
618static int m68k_set_arch (const char *, int, int);
619static int m68k_set_cpu (const char *, int, int);
620static int m68k_set_extension (const char *, int, int);
621static void m68k_init_arch (void);
252b5132 622
151337e8
NC		 623/* This is the assembler relaxation table for m68k. m68k is a rich CISC
624 architecture and we have a lot of relaxation modes. */
252b5132 625
151337e8
NC		 626/* Macros used in the relaxation code. */
627#define TAB(x,y) (((x) << 2) + (y))
628#define TABTYPE(x) ((x) >> 2)
629
630/* Relaxation states. */
631#define BYTE 0
632#define SHORT 1
633#define LONG 2
634#define SZ_UNDEF 3
635
636/* Here are all the relaxation modes we support. First we can relax ordinary
637 branches. On 68020 and higher and on CPU32 all branch instructions take
638 three forms, so on these CPUs all branches always remain as such. When we
639 have to expand to the LONG form on a 68000, though, we substitute an
640 absolute jump instead. This is a direct replacement for unconditional
641 branches and a branch over a jump for conditional branches. However, if the
642 user requires PIC and disables this with --pcrel, we can only relax between
643 BYTE and SHORT forms, punting if that isn't enough. This gives us four
644 different relaxation modes for branches: */
645
36759679
NC		 646#define BRANCHBWL 0 /* Branch byte, word, or long. */
647#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
648#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
649#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 650
651/* We also relax coprocessor branches and DBcc's. All CPUs that support
652 coprocessor branches support them in word and long forms, so we have only
653 one relaxation mode for them. DBcc's are word only on all CPUs. We can
654 relax them to the LONG form with a branch-around sequence. This sequence
655 can use a long branch (if available) or an absolute jump (if acceptable).
656 This gives us two relaxation modes. If long branches are not available and
657 absolute jumps are not acceptable, we don't relax DBcc's. */
658
36759679
NC		 659#define FBRANCH 4 /* Coprocessor branch. */
660#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
661#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 662
663/* That's all for instruction relaxation. However, we also relax PC-relative
664 operands. Specifically, we have three operand relaxation modes. On the
665 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
666 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
667 two. Also PC+displacement+index operands in their simple form (with a non-
668 suppressed index without memory indirection) are supported on all CPUs, but
669 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
670 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
671 form of the PC+displacement+index operand. Finally, some absolute operands
672 can be relaxed down to 16-bit PC-relative. */
673
36759679
NC		 674#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
675#define PCINDEX 8 /* PC + displacement + index. */
676#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 677
678/* Note that calls to frag_var need to specify the maximum expansion
679 needed; this is currently 10 bytes for DBCC. */
680
681/* The fields are:
682 How far Forward this mode will reach:
683 How far Backward this mode will reach:
684 How many bytes this mode will add to the size of the frag
685 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 686
687 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 688relax_typeS md_relax_table[] =
689{
ac62c346
AM		 690 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
691 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
692 { 0, 0, 4, 0 },
693 { 1, 1, 0, 0 },
694
695 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
696 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
697 { 0, 0, 4, 0 },
698 { 1, 1, 0, 0 },
699
700 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
701 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
702 { 0, 0, 6, 0 },
703 { 1, 1, 0, 0 },
704
705 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
706 { 0, 0, 2, 0 },
707 { 1, 1, 0, 0 },
708 { 1, 1, 0, 0 },
709
36759679 710 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 711 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
712 { 0, 0, 4, 0 },
713 { 1, 1, 0, 0 },
714
36759679 715 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 716 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
717 { 0, 0, 10, 0 },
718 { 1, 1, 0, 0 },
719
36759679 720 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 721 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
722 { 0, 0, 10, 0 },
723 { 1, 1, 0, 0 },
724
36759679 725 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 726 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
727 { 0, 0, 6, 0 },
728 { 1, 1, 0, 0 },
729
730 { 125, -130, 0, TAB (PCINDEX, SHORT) },
731 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
732 { 0, 0, 4, 0 },
733 { 1, 1, 0, 0 },
734
36759679 735 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 736 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
737 { 0, 0, 4, 0 },
738 { 1, 1, 0, 0 },
252b5132
RH		 739};
740
741/* These are the machine dependent pseudo-ops. These are included so
742 the assembler can work on the output from the SUN C compiler, which
36759679 743 generates these. */
252b5132
RH		 744
745/* This table describes all the machine specific pseudo-ops the assembler
746 has to support. The fields are:
747 pseudo-op name without dot
748 function to call to execute this pseudo-op
36759679 749 Integer arg to pass to the function. */
252b5132
RH		 750const pseudo_typeS md_pseudo_table[] =
751{
752 {"data1", s_data1, 0},
753 {"data2", s_data2, 0},
754 {"bss", s_bss, 0},
755 {"even", s_even, 0},
756 {"skip", s_space, 0},
757 {"proc", s_proc, 0},
758#if defined (TE_SUN3) || defined (OBJ_ELF)
759 {"align", s_align_bytes, 0},
760#endif
761#ifdef OBJ_ELF
762 {"swbeg", s_ignore, 0},
763#endif
764 {"extend", float_cons, 'x'},
765 {"ldouble", float_cons, 'x'},
766
266abb8f
NS		 767 {"arch", s_m68k_arch, 0},
768 {"cpu", s_m68k_cpu, 0},
769
252b5132
RH		 770 /* The following pseudo-ops are supported for MRI compatibility. */
771 {"chip", s_chip, 0},
772 {"comline", s_space, 1},
773 {"fopt", s_fopt, 0},
774 {"mask2", s_ignore, 0},
775 {"opt", s_opt, 0},
776 {"reg", s_reg, 0},
777 {"restore", s_restore, 0},
778 {"save", s_save, 0},
779
780 {"if", s_mri_if, 0},
781 {"if.b", s_mri_if, 'b'},
782 {"if.w", s_mri_if, 'w'},
783 {"if.l", s_mri_if, 'l'},
784 {"else", s_mri_else, 0},
785 {"else.s", s_mri_else, 's'},
786 {"else.l", s_mri_else, 'l'},
787 {"endi", s_mri_endi, 0},
788 {"break", s_mri_break, 0},
789 {"break.s", s_mri_break, 's'},
790 {"break.l", s_mri_break, 'l'},
791 {"next", s_mri_next, 0},
792 {"next.s", s_mri_next, 's'},
793 {"next.l", s_mri_next, 'l'},
794 {"for", s_mri_for, 0},
795 {"for.b", s_mri_for, 'b'},
796 {"for.w", s_mri_for, 'w'},
797 {"for.l", s_mri_for, 'l'},
798 {"endf", s_mri_endf, 0},
799 {"repeat", s_mri_repeat, 0},
800 {"until", s_mri_until, 0},
801 {"until.b", s_mri_until, 'b'},
802 {"until.w", s_mri_until, 'w'},
803 {"until.l", s_mri_until, 'l'},
804 {"while", s_mri_while, 0},
805 {"while.b", s_mri_while, 'b'},
806 {"while.w", s_mri_while, 'w'},
807 {"while.l", s_mri_while, 'l'},
808 {"endw", s_mri_endw, 0},
809
810 {0, 0, 0}
811};
812
252b5132 813/* The mote pseudo ops are put into the opcode table, since they
31302357 814 don't start with a . they look like opcodes to gas. */
252b5132 815
5a38dc70 816const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 817{
818
819 {"dcl", cons, 4},
820 {"dc", cons, 2},
821 {"dcw", cons, 2},
822 {"dcb", cons, 1},
823
824 {"dsl", s_space, 4},
825 {"ds", s_space, 2},
826 {"dsw", s_space, 2},
827 {"dsb", s_space, 1},
828
829 {"xdef", s_globl, 0},
830#ifdef OBJ_ELF
831 {"align", s_align_bytes, 0},
832#else
833 {"align", s_align_ptwo, 0},
834#endif
835#ifdef M68KCOFF
836 {"sect", obj_coff_section, 0},
837 {"section", obj_coff_section, 0},
838#endif
839 {0, 0, 0}
840};
841
bd17c2c3
AM		 842/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
843 gives identical results to a 32-bit host. */
844#define TRUNC(X) ((valueT) (X) & 0xffffffff)
845#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
846
847#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
848#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
849#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
850#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
851
852#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
853#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 854#define islong(x) (1)
855
252b5132
RH		 856static char notend_table[256];
857static char alt_notend_table[256];
858#define notend(s) \
859 (! (notend_table[(unsigned char) *s] \
860 || (*s == ':' \
861 && alt_notend_table[(unsigned char) s[1]])))
862
252b5132
RH		 863#ifdef OBJ_ELF
864
c801568a
AM		 865/* Return zero if the reference to SYMBOL from within the same segment may
866 be relaxed. */
867
868/* On an ELF system, we can't relax an externally visible symbol,
869 because it may be overridden by a shared library. However, if
870 TARGET_OS is "elf", then we presume that we are assembling for an
871 embedded system, in which case we don't have to worry about shared
872 libraries, and we can relax any external sym. */
873
874#define relaxable_symbol(symbol) \
6358301e 875 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 876 || S_IS_WEAK (symbol)))
877
252b5132
RH		 878/* Compute the relocation code for a fixup of SIZE bytes, using pc
879 relative relocation if PCREL is non-zero. PIC says whether a special
880 pic relocation was requested. */
881
252b5132 882static bfd_reloc_code_real_type
31302357 883get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 884{
885 switch (pic)
886 {
887 case pic_got_pcrel:
888 switch (size)
889 {
890 case 1:
891 return BFD_RELOC_8_GOT_PCREL;
892 case 2:
893 return BFD_RELOC_16_GOT_PCREL;
894 case 4:
895 return BFD_RELOC_32_GOT_PCREL;
896 }
897 break;
898
899 case pic_got_off:
900 switch (size)
901 {
902 case 1:
903 return BFD_RELOC_8_GOTOFF;
904 case 2:
905 return BFD_RELOC_16_GOTOFF;
906 case 4:
907 return BFD_RELOC_32_GOTOFF;
908 }
909 break;
910
911 case pic_plt_pcrel:
912 switch (size)
913 {
914 case 1:
915 return BFD_RELOC_8_PLT_PCREL;
916 case 2:
917 return BFD_RELOC_16_PLT_PCREL;
918 case 4:
919 return BFD_RELOC_32_PLT_PCREL;
920 }
921 break;
922
923 case pic_plt_off:
924 switch (size)
925 {
926 case 1:
927 return BFD_RELOC_8_PLTOFF;
928 case 2:
929 return BFD_RELOC_16_PLTOFF;
930 case 4:
931 return BFD_RELOC_32_PLTOFF;
932 }
933 break;
934
935 case pic_none:
936 if (pcrel)
937 {
938 switch (size)
939 {
940 case 1:
941 return BFD_RELOC_8_PCREL;
942 case 2:
943 return BFD_RELOC_16_PCREL;
944 case 4:
945 return BFD_RELOC_32_PCREL;
946 }
947 }
948 else
949 {
950 switch (size)
951 {
952 case 1:
953 return BFD_RELOC_8;
954 case 2:
955 return BFD_RELOC_16;
956 case 4:
957 return BFD_RELOC_32;
958 }
959 }
960 }
961
962 if (pcrel)
963 {
964 if (pic == pic_none)
965 as_bad (_("Can not do %d byte pc-relative relocation"), size);
966 else
967 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
968 }
969 else
970 {
971 if (pic == pic_none)
972 as_bad (_("Can not do %d byte relocation"), size);
973 else
974 as_bad (_("Can not do %d byte pic relocation"), size);
975 }
976
977 return BFD_RELOC_NONE;
978}
979
980/* Here we decide which fixups can be adjusted to make them relative
981 to the beginning of the section instead of the symbol. Basically
982 we need to make sure that the dynamic relocations are done
983 correctly, so in some cases we force the original symbol to be
984 used. */
985int
31302357 986tc_m68k_fix_adjustable (fixS *fixP)
252b5132 987{
36759679 988 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 989 switch (fixP->fx_r_type)
990 {
991 case BFD_RELOC_8_GOT_PCREL:
992 case BFD_RELOC_16_GOT_PCREL:
993 case BFD_RELOC_32_GOT_PCREL:
994 case BFD_RELOC_8_GOTOFF:
995 case BFD_RELOC_16_GOTOFF:
996 case BFD_RELOC_32_GOTOFF:
997 case BFD_RELOC_8_PLT_PCREL:
998 case BFD_RELOC_16_PLT_PCREL:
999 case BFD_RELOC_32_PLT_PCREL:
1000 case BFD_RELOC_8_PLTOFF:
1001 case BFD_RELOC_16_PLTOFF:
1002 case BFD_RELOC_32_PLTOFF:
1003 return 0;
1004
1005 case BFD_RELOC_VTABLE_INHERIT:
1006 case BFD_RELOC_VTABLE_ENTRY:
1007 return 0;
1008
1009 default:
1010 return 1;
1011 }
1012}
1013
1014#else /* !OBJ_ELF */
1015
1016#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1017
c801568a
AM		 1018#define relaxable_symbol(symbol) 1
1019
252b5132
RH		 1020#endif /* OBJ_ELF */
1021
252b5132 1022arelent *
31302357 1023tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1024{
1025 arelent *reloc;
1026 bfd_reloc_code_real_type code;
1027
8ec6253e
NC		 1028 /* If the tcbit is set, then this was a fixup of a negative value
1029 that was never resolved. We do not have a reloc to handle this,
1030 so just return. We assume that other code will have detected this
1031 situation and produced a helpful error message, so we just tell the
1032 user that the reloc cannot be produced. */
252b5132 1033 if (fixp->fx_tcbit)
8ec6253e
NC		 1034 {
1035 if (fixp->fx_addsy)
b091f402
AM		 1036 as_bad_where (fixp->fx_file, fixp->fx_line,
1037 _("Unable to produce reloc against symbol '%s'"),
1038 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1039 return NULL;
1040 }
252b5132
RH		 1041
1042 if (fixp->fx_r_type != BFD_RELOC_NONE)
1043 {
1044 code = fixp->fx_r_type;
1045
1046 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1047 that fixup_segment converted a non-PC relative reloc into a
1048 PC relative reloc. In such a case, we need to convert the
1049 reloc code. */
1050 if (fixp->fx_pcrel)
1051 {
1052 switch (code)
1053 {
1054 case BFD_RELOC_8:
1055 code = BFD_RELOC_8_PCREL;
1056 break;
1057 case BFD_RELOC_16:
1058 code = BFD_RELOC_16_PCREL;
1059 break;
1060 case BFD_RELOC_32:
1061 code = BFD_RELOC_32_PCREL;
1062 break;
1063 case BFD_RELOC_8_PCREL:
1064 case BFD_RELOC_16_PCREL:
1065 case BFD_RELOC_32_PCREL:
1066 case BFD_RELOC_8_GOT_PCREL:
1067 case BFD_RELOC_16_GOT_PCREL:
1068 case BFD_RELOC_32_GOT_PCREL:
1069 case BFD_RELOC_8_GOTOFF:
1070 case BFD_RELOC_16_GOTOFF:
1071 case BFD_RELOC_32_GOTOFF:
1072 case BFD_RELOC_8_PLT_PCREL:
1073 case BFD_RELOC_16_PLT_PCREL:
1074 case BFD_RELOC_32_PLT_PCREL:
1075 case BFD_RELOC_8_PLTOFF:
1076 case BFD_RELOC_16_PLTOFF:
1077 case BFD_RELOC_32_PLTOFF:
1078 break;
1079 default:
1080 as_bad_where (fixp->fx_file, fixp->fx_line,
1081 _("Cannot make %s relocation PC relative"),
1082 bfd_get_reloc_code_name (code));
1083 }
1084 }
1085 }
1086 else
1087 {
1088#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1089 switch (F (fixp->fx_size, fixp->fx_pcrel))
1090 {
1091#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1092 MAP (1, 0, BFD_RELOC_8);
1093 MAP (2, 0, BFD_RELOC_16);
1094 MAP (4, 0, BFD_RELOC_32);
1095 MAP (1, 1, BFD_RELOC_8_PCREL);
1096 MAP (2, 1, BFD_RELOC_16_PCREL);
1097 MAP (4, 1, BFD_RELOC_32_PCREL);
1098 default:
1099 abort ();
1100 }
1101 }
1102#undef F
1103#undef MAP
1104
1105 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1106 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1107 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1108 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1109#ifndef OBJ_ELF
1110 if (fixp->fx_pcrel)
1111 reloc->addend = fixp->fx_addnumber;
1112 else
1113 reloc->addend = 0;
1114#else
1115 if (!fixp->fx_pcrel)
1116 reloc->addend = fixp->fx_addnumber;
1117 else
1118 reloc->addend = (section->vma
8390138c
AS		 1119 /* Explicit sign extension in case char is
1120 unsigned. */
1121 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1122 + fixp->fx_addnumber
1123 + md_pcrel_from (fixp));
1124#endif
1125
1126 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1127 assert (reloc->howto != 0);
1128
1129 return reloc;
1130}
1131
252b5132
RH		 1132/* Handle of the OPCODE hash table. NULL means any use before
1133 m68k_ip_begin() will crash. */
1134static struct hash_control *op_hash;
1135\f
1136/* Assemble an m68k instruction. */
1137
1138static void
31302357 1139m68k_ip (char *instring)
252b5132
RH		 1140{
1141 register char *p;
1142 register struct m68k_op *opP;
1143 register const struct m68k_incant *opcode;
1144 register const char *s;
1145 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1146 char *pdot, *pdotmove;
1147 enum m68k_size siz1, siz2;
1148 char c;
1149 int losing;
1150 int opsfound;
03b13e59 1151 struct m68k_op operands_backup[6];
252b5132
RH		 1152 LITTLENUM_TYPE words[6];
1153 LITTLENUM_TYPE *wordp;
1154 unsigned long ok_arch = 0;
1155
1156 if (*instring == ' ')
36759679 1157 instring++; /* Skip leading whitespace. */
252b5132
RH		 1158
1159 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1160 or exactly 1 space. */
252b5132
RH		 1161 pdot = 0;
1162 for (p = instring; *p != '\0'; p++)
1163 {
1164 if (*p == ' ')
1165 break;
1166 if (*p == '.')
1167 pdot = p;
1168 }
1169
1170 if (p == instring)
1171 {
1172 the_ins.error = _("No operator");
1173 return;
1174 }
1175
1176 /* p now points to the end of the opcode name, probably whitespace.
1177 Make sure the name is null terminated by clobbering the
1178 whitespace, look it up in the hash table, then fix it back.
1179 Remove a dot, first, since the opcode tables have none. */
1180 if (pdot != NULL)
1181 {
1182 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1183 *pdotmove = pdotmove[1];
1184 p--;
1185 }
1186
1187 c = *p;
1188 *p = '\0';
1189 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1190 *p = c;
1191
1192 if (pdot != NULL)
1193 {
1194 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1195 *pdotmove = pdotmove[-1];
1196 *pdot = '.';
1197 ++p;
1198 }
1199
1200 if (opcode == NULL)
1201 {
1202 the_ins.error = _("Unknown operator");
1203 return;
1204 }
1205
36759679 1206 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1207 while (*p == ' ')
1208 ++p;
1209
1210 if (opcode->m_operands == 0)
1211 {
1212 char *old = input_line_pointer;
1213 *old = '\n';
1214 input_line_pointer = p;
36759679 1215 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1216 mote_pseudo_table[opcode->m_opnum].poc_handler
1217 (mote_pseudo_table[opcode->m_opnum].poc_val);
1218 input_line_pointer = old;
1219 *old = 0;
1220
1221 return;
1222 }
1223
1224 if (flag_mri && opcode->m_opnum == 0)
1225 {
1226 /* In MRI mode, random garbage is allowed after an instruction
1227 which accepts no operands. */
1228 the_ins.args = opcode->m_operands;
1229 the_ins.numargs = opcode->m_opnum;
1230 the_ins.numo = opcode->m_codenum;
1231 the_ins.opcode[0] = getone (opcode);
1232 the_ins.opcode[1] = gettwo (opcode);
1233 return;
1234 }
1235
1236 for (opP = &the_ins.operands[0]; *p; opP++)
1237 {
1238 p = crack_operand (p, opP);
1239
1240 if (opP->error)
1241 {
1242 the_ins.error = opP->error;
1243 return;
1244 }
1245 }
1246
1247 opsfound = opP - &the_ins.operands[0];
1248
1249 /* This ugly hack is to support the floating pt opcodes in their
1250 standard form. Essentially, we fake a first enty of type COP#1 */
1251 if (opcode->m_operands[0] == 'I')
1252 {
1253 int n;
1254
1255 for (n = opsfound; n > 0; --n)
1256 the_ins.operands[n] = the_ins.operands[n - 1];
1257
31302357 1258 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1259 the_ins.operands[0].mode = CONTROL;
1260 the_ins.operands[0].reg = m68k_float_copnum;
1261 opsfound++;
1262 }
1263
36759679 1264 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1265 for (losing = 0;;)
1266 {
1267 /* If we didn't get the right number of ops, or we have no
92774660 1268 common model with this pattern then reject this pattern. */
252b5132
RH		 1269
1270 ok_arch |= opcode->m_arch;
1271 if (opsfound != opcode->m_opnum
1272 || ((opcode->m_arch & current_architecture) == 0))
1273 ++losing;
1274 else
1275 {
03b13e59
NC		 1276 int i;
1277
1278 /* Make a copy of the operands of this insn so that
1279 we can modify them safely, should we want to. */
1280 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1281 for (i = 0; i < opsfound; i++)
1282 operands_backup[i] = the_ins.operands[i];
1283
1284 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1285 *s && !losing;
1286 s += 2, opP++)
1287 {
1288 /* Warning: this switch is huge! */
1289 /* I've tried to organize the cases into this order:
1290 non-alpha first, then alpha by letter. Lower-case
1291 goes directly before uppercase counterpart. */
1292 /* Code with multiple case ...: gets sorted by the lowest
1293 case ... it belongs to. I hope this makes sense. */
1294 switch (*s)
1295 {
1296 case '!':
1297 switch (opP->mode)
1298 {
1299 case IMMED:
1300 case DREG:
1301 case AREG:
1302 case FPREG:
1303 case CONTROL:
1304 case AINC:
1305 case ADEC:
1306 case REGLST:
1307 losing++;
1308 break;
1309 default:
1310 break;
1311 }
1312 break;
1313
1314 case '<':
1315 switch (opP->mode)
1316 {
1317 case DREG:
1318 case AREG:
1319 case FPREG:
1320 case CONTROL:
1321 case IMMED:
1322 case ADEC:
1323 case REGLST:
1324 losing++;
1325 break;
1326 default:
1327 break;
1328 }
1329 break;
1330
1331 case '>':
1332 switch (opP->mode)
1333 {
1334 case DREG:
1335 case AREG:
1336 case FPREG:
1337 case CONTROL:
1338 case IMMED:
1339 case AINC:
1340 case REGLST:
1341 losing++;
1342 break;
1343 case ABSL:
1344 break;
1345 default:
1346 if (opP->reg == PC
1347 || opP->reg == ZPC)
1348 losing++;
1349 break;
1350 }
1351 break;
1352
1353 case 'm':
1354 switch (opP->mode)
1355 {
1356 case DREG:
1357 case AREG:
1358 case AINDR:
1359 case AINC:
1360 case ADEC:
1361 break;
1362 default:
1363 losing++;
1364 }
8a104df9 1365 break;
252b5132
RH		 1366
1367 case 'n':
1368 switch (opP->mode)
1369 {
1370 case DISP:
1371 break;
1372 default:
1373 losing++;
1374 }
8a104df9 1375 break;
252b5132
RH		 1376
1377 case 'o':
1378 switch (opP->mode)
1379 {
1380 case BASE:
1381 case ABSL:
1382 case IMMED:
1383 break;
1384 default:
1385 losing++;
1386 }
8a104df9 1387 break;
252b5132
RH		 1388
1389 case 'p':
1390 switch (opP->mode)
1391 {
1392 case DREG:
1393 case AREG:
1394 case AINDR:
1395 case AINC:
1396 case ADEC:
1397 break;
1398 case DISP:
1399 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1400 losing++;
252b5132
RH		 1401 break;
1402 default:
1403 losing++;
1404 }
8a104df9 1405 break;
252b5132
RH		 1406
1407 case 'q':
1408 switch (opP->mode)
1409 {
1410 case DREG:
1411 case AINDR:
1412 case AINC:
1413 case ADEC:
1414 break;
1415 case DISP:
1416 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1417 losing++;
252b5132
RH		 1418 break;
1419 default:
1420 losing++;
1421 break;
1422 }
8a104df9 1423 break;
252b5132
RH		 1424
1425 case 'v':
1426 switch (opP->mode)
1427 {
1428 case DREG:
1429 case AINDR:
1430 case AINC:
1431 case ADEC:
1432 case ABSL:
1433 break;
1434 case DISP:
1435 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1436 losing++;
252b5132
RH		 1437 break;
1438 default:
1439 losing++;
1440 break;
1441 }
1442 break;
1443
1444 case '#':
1445 if (opP->mode != IMMED)
1446 losing++;
1447 else if (s[1] == 'b'
1448 && ! isvar (&opP->disp)
1449 && (opP->disp.exp.X_op != O_constant
1450 || ! isbyte (opP->disp.exp.X_add_number)))
1451 losing++;
1452 else if (s[1] == 'B'
1453 && ! isvar (&opP->disp)
1454 && (opP->disp.exp.X_op != O_constant
1455 || ! issbyte (opP->disp.exp.X_add_number)))
1456 losing++;
1457 else if (s[1] == 'w'
1458 && ! isvar (&opP->disp)
1459 && (opP->disp.exp.X_op != O_constant
1460 || ! isword (opP->disp.exp.X_add_number)))
1461 losing++;
1462 else if (s[1] == 'W'
1463 && ! isvar (&opP->disp)
1464 && (opP->disp.exp.X_op != O_constant
1465 || ! issword (opP->disp.exp.X_add_number)))
1466 losing++;
1467 break;
1468
1469 case '^':
1470 case 'T':
1471 if (opP->mode != IMMED)
1472 losing++;
1473 break;
1474
1475 case '$':
1476 if (opP->mode == AREG
1477 || opP->mode == CONTROL
1478 || opP->mode == FPREG
1479 || opP->mode == IMMED
1480 || opP->mode == REGLST
1481 || (opP->mode != ABSL
1482 && (opP->reg == PC
1483 || opP->reg == ZPC)))
1484 losing++;
1485 break;
1486
1487 case '%':
1488 if (opP->mode == CONTROL
1489 || opP->mode == FPREG
1490 || opP->mode == REGLST
1491 || opP->mode == IMMED
1492 || (opP->mode != ABSL
1493 && (opP->reg == PC
1494 || opP->reg == ZPC)))
1495 losing++;
1496 break;
1497
1498 case '&':
1499 switch (opP->mode)
1500 {
1501 case DREG:
1502 case AREG:
1503 case FPREG:
1504 case CONTROL:
1505 case IMMED:
1506 case AINC:
1507 case ADEC:
1508 case REGLST:
1509 losing++;
1510 break;
1511 case ABSL:
1512 break;
1513 default:
1514 if (opP->reg == PC
1515 || opP->reg == ZPC)
1516 losing++;
1517 break;
1518 }
1519 break;
1520
1521 case '*':
1522 if (opP->mode == CONTROL
1523 || opP->mode == FPREG
1524 || opP->mode == REGLST)
1525 losing++;
1526 break;
1527
1528 case '+':
1529 if (opP->mode != AINC)
1530 losing++;
1531 break;
1532
1533 case '-':
1534 if (opP->mode != ADEC)
1535 losing++;
1536 break;
1537
1538 case '/':
1539 switch (opP->mode)
1540 {
1541 case AREG:
1542 case CONTROL:
1543 case FPREG:
1544 case AINC:
1545 case ADEC:
1546 case IMMED:
1547 case REGLST:
1548 losing++;
1549 break;
1550 default:
1551 break;
1552 }
1553 break;
1554
1555 case ';':
1556 switch (opP->mode)
1557 {
1558 case AREG:
1559 case CONTROL:
1560 case FPREG:
1561 case REGLST:
1562 losing++;
1563 break;
1564 default:
1565 break;
1566 }
1567 break;
1568
1569 case '?':
1570 switch (opP->mode)
1571 {
1572 case AREG:
1573 case CONTROL:
1574 case FPREG:
1575 case AINC:
1576 case ADEC:
1577 case IMMED:
1578 case REGLST:
1579 losing++;
1580 break;
1581 case ABSL:
1582 break;
1583 default:
1584 if (opP->reg == PC || opP->reg == ZPC)
1585 losing++;
1586 break;
1587 }
1588 break;
1589
1590 case '@':
1591 switch (opP->mode)
1592 {
1593 case AREG:
1594 case CONTROL:
1595 case FPREG:
1596 case IMMED:
1597 case REGLST:
1598 losing++;
1599 break;
1600 default:
1601 break;
1602 }
1603 break;
1604
1605 case '~': /* For now! (JF FOO is this right?) */
1606 switch (opP->mode)
1607 {
1608 case DREG:
1609 case AREG:
1610 case CONTROL:
1611 case FPREG:
1612 case IMMED:
1613 case REGLST:
1614 losing++;
1615 break;
1616 case ABSL:
1617 break;
1618 default:
1619 if (opP->reg == PC
1620 || opP->reg == ZPC)
1621 losing++;
1622 break;
1623 }
1624 break;
1625
1626 case '3':
1627 if (opP->mode != CONTROL
1628 || (opP->reg != TT0 && opP->reg != TT1))
1629 losing++;
1630 break;
1631
1632 case 'A':
1633 if (opP->mode != AREG)
1634 losing++;
1635 break;
1636
1637 case 'a':
1638 if (opP->mode != AINDR)
1639 ++losing;
1640 break;
1641
fd99574b
NC		 1642 case '4':
1643 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1644 && (opP->mode != DISP
1645 || opP->reg < ADDR0
1646 || opP->reg > ADDR7))
1647 ++losing;
1648 break;
1649
252b5132
RH		 1650 case 'B': /* FOO */
1651 if (opP->mode != ABSL
1652 || (flag_long_jumps
1653 && strncmp (instring, "jbsr", 4) == 0))
1654 losing++;
1655 break;
1656
3e602632
NC		 1657 case 'b':
1658 switch (opP->mode)
1659 {
1660 case IMMED:
1661 case ABSL:
1662 case AREG:
1663 case FPREG:
1664 case CONTROL:
1665 case POST:
1666 case PRE:
1667 case REGLST:
1668 losing++;
1669 break;
1670 default:
1671 break;
1672 }
1673 break;
1674
252b5132
RH		 1675 case 'C':
1676 if (opP->mode != CONTROL || opP->reg != CCR)
1677 losing++;
1678 break;
1679
1680 case 'd':
1681 if (opP->mode != DISP
1682 || opP->reg < ADDR0
1683 || opP->reg > ADDR7)
1684 losing++;
1685 break;
1686
1687 case 'D':
1688 if (opP->mode != DREG)
1689 losing++;
1690 break;
1691
6da466c7
ILT		 1692 case 'E':
1693 if (opP->reg != ACC)
1694 losing++;
1695 break;
1696
fd99574b
NC		 1697 case 'e':
1698 if (opP->reg != ACC && opP->reg != ACC1
1699 && opP->reg != ACC2 && opP->reg != ACC3)
1700 losing++;
1701 break;
1702
252b5132
RH		 1703 case 'F':
1704 if (opP->mode != FPREG)
1705 losing++;
1706 break;
1707
6da466c7
ILT		 1708 case 'G':
1709 if (opP->reg != MACSR)
1710 losing++;
1711 break;
1712
fd99574b
NC		 1713 case 'g':
1714 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1715 losing++;
1716 break;
1717
6da466c7
ILT		 1718 case 'H':
1719 if (opP->reg != MASK)
1720 losing++;
1721 break;
1722
252b5132
RH		 1723 case 'I':
1724 if (opP->mode != CONTROL
1725 || opP->reg < COP0
1726 || opP->reg > COP7)
1727 losing++;
1728 break;
1729
fd99574b
NC		 1730 case 'i':
1731 if (opP->mode != LSH && opP->mode != RSH)
1732 losing++;
1733 break;
1734
252b5132
RH		 1735 case 'J':
1736 if (opP->mode != CONTROL
1737 || opP->reg < USP
0b2e31dc
NS		 1738 || opP->reg > last_movec_reg
1739 || !control_regs)
252b5132
RH		 1740 losing++;
1741 else
1742 {
1743 const enum m68k_register *rp;
0b2e31dc 1744
252b5132
RH		 1745 for (rp = control_regs; *rp; rp++)
1746 if (*rp == opP->reg)
1747 break;
1748 if (*rp == 0)
1749 losing++;
1750 }
1751 break;
1752
1753 case 'k':
1754 if (opP->mode != IMMED)
1755 losing++;
1756 break;
1757
1758 case 'l':
1759 case 'L':
1760 if (opP->mode == DREG
1761 || opP->mode == AREG
1762 || opP->mode == FPREG)
1763 {
1764 if (s[1] == '8')
1765 losing++;
1766 else
1767 {
1768 switch (opP->mode)
1769 {
1770 case DREG:
1771 opP->mask = 1 << (opP->reg - DATA0);
1772 break;
1773 case AREG:
1774 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1775 break;
1776 case FPREG:
1777 opP->mask = 1 << (opP->reg - FP0 + 16);
1778 break;
1779 default:
1780 abort ();
1781 }
1782 opP->mode = REGLST;
1783 }
1784 }
1785 else if (opP->mode == CONTROL)
1786 {
1787 if (s[1] != '8')
1788 losing++;
1789 else
1790 {
1791 switch (opP->reg)
1792 {
1793 case FPI:
1794 opP->mask = 1 << 24;
1795 break;
1796 case FPS:
1797 opP->mask = 1 << 25;
1798 break;
1799 case FPC:
1800 opP->mask = 1 << 26;
1801 break;
1802 default:
1803 losing++;
1804 break;
1805 }
1806 opP->mode = REGLST;
1807 }
1808 }
1809 else if (opP->mode != REGLST)
1810 losing++;
1811 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1812 losing++;
1813 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1814 losing++;
1815 break;
1816
1817 case 'M':
1818 if (opP->mode != IMMED)
1819 losing++;
1820 else if (opP->disp.exp.X_op != O_constant
1821 || ! issbyte (opP->disp.exp.X_add_number))
1822 losing++;
1823 else if (! m68k_quick
1824 && instring[3] != 'q'
1825 && instring[4] != 'q')
1826 losing++;
1827 break;
1828
1829 case 'O':
1830 if (opP->mode != DREG
1831 && opP->mode != IMMED
1832 && opP->mode != ABSL)
1833 losing++;
1834 break;
1835
1836 case 'Q':
1837 if (opP->mode != IMMED)
1838 losing++;
1839 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1840 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1841 losing++;
1842 else if (! m68k_quick
1843 && (strncmp (instring, "add", 3) == 0
1844 || strncmp (instring, "sub", 3) == 0)
1845 && instring[3] != 'q')
1846 losing++;
1847 break;
1848
1849 case 'R':
1850 if (opP->mode != DREG && opP->mode != AREG)
1851 losing++;
1852 break;
1853
1854 case 'r':
1855 if (opP->mode != AINDR
1856 && (opP->mode != BASE
1857 || (opP->reg != 0
1858 && opP->reg != ZADDR0)
1859 || opP->disp.exp.X_op != O_absent
1860 || ((opP->index.reg < DATA0
1861 || opP->index.reg > DATA7)
1862 && (opP->index.reg < ADDR0
1863 || opP->index.reg > ADDR7))
1864 || opP->index.size != SIZE_UNSPEC
1865 || opP->index.scale != 1))
1866 losing++;
1867 break;
1868
1869 case 's':
1870 if (opP->mode != CONTROL
1871 || ! (opP->reg == FPI
1872 || opP->reg == FPS
1873 || opP->reg == FPC))
1874 losing++;
1875 break;
1876
1877 case 'S':
1878 if (opP->mode != CONTROL || opP->reg != SR)
1879 losing++;
1880 break;
1881
1882 case 't':
1883 if (opP->mode != IMMED)
1884 losing++;
1885 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1886 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1887 losing++;
1888 break;
1889
1890 case 'U':
1891 if (opP->mode != CONTROL || opP->reg != USP)
1892 losing++;
1893 break;
1894
3e602632
NC		 1895 case 'x':
1896 if (opP->mode != IMMED)
1897 losing++;
1898 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1899 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1900 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1901 losing++;
1902 break;
1903
252b5132
RH		 1904 /* JF these are out of order. We could put them
1905 in order if we were willing to put up with
1906 bunches of #ifdef m68851s in the code.
1907
1908 Don't forget that you need these operands
1909 to use 68030 MMU instructions. */
1910#ifndef NO_68851
36759679 1911 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1912 case '|':
1913 if (opP->mode == CONTROL
1914 || opP->mode == FPREG
1915 || opP->mode == DREG
1916 || opP->mode == AREG
1917 || opP->mode == REGLST)
1918 losing++;
1919 /* We should accept immediate operands, but they
1920 supposedly have to be quad word, and we don't
1921 handle that. I would like to see what a Motorola
1922 assembler does before doing something here. */
1923 if (opP->mode == IMMED)
1924 losing++;
1925 break;
1926
1927 case 'f':
1928 if (opP->mode != CONTROL
1929 || (opP->reg != SFC && opP->reg != DFC))
1930 losing++;
1931 break;
1932
1933 case '0':
1934 if (opP->mode != CONTROL || opP->reg != TC)
1935 losing++;
1936 break;
1937
1938 case '1':
1939 if (opP->mode != CONTROL || opP->reg != AC)
1940 losing++;
1941 break;
1942
1943 case '2':
1944 if (opP->mode != CONTROL
1945 || (opP->reg != CAL
1946 && opP->reg != VAL
1947 && opP->reg != SCC))
1948 losing++;
1949 break;
1950
1951 case 'V':
1952 if (opP->mode != CONTROL
1953 || opP->reg != VAL)
1954 losing++;
1955 break;
1956
1957 case 'W':
1958 if (opP->mode != CONTROL
1959 || (opP->reg != DRP
1960 && opP->reg != SRP
1961 && opP->reg != CRP))
1962 losing++;
1963 break;
1964
3e602632
NC		 1965 case 'w':
1966 switch (opP->mode)
1967 {
1968 case IMMED:
1969 case ABSL:
1970 case AREG:
1971 case DREG:
1972 case FPREG:
1973 case CONTROL:
1974 case POST:
1975 case PRE:
1976 case REGLST:
1977 losing++;
1978 break;
1979 default:
1980 break;
1981 }
1982 break;
1983
252b5132
RH		 1984 case 'X':
1985 if (opP->mode != CONTROL
1986 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1987 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1988 losing++;
1989 break;
1990
1991 case 'Y':
1992 if (opP->mode != CONTROL || opP->reg != PSR)
1993 losing++;
1994 break;
1995
1996 case 'Z':
1997 if (opP->mode != CONTROL || opP->reg != PCSR)
1998 losing++;
1999 break;
2000#endif
2001 case 'c':
2002 if (opP->mode != CONTROL
2003 || (opP->reg != NC
2004 && opP->reg != IC
2005 && opP->reg != DC
2006 && opP->reg != BC))
36759679 2007 losing++;
252b5132
RH		 2008 break;
2009
2010 case '_':
2011 if (opP->mode != ABSL)
2012 ++losing;
2013 break;
2014
6da466c7
ILT		 2015 case 'u':
2016 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2017 losing++;
2018 /* FIXME: kludge instead of fixing parser:
2019 upper/lower registers are *not* CONTROL
92774660 2020 registers, but ordinary ones. */
6da466c7
ILT		 2021 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2022 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2023 opP->mode = DREG;
2024 else
2025 opP->mode = AREG;
2026 break;
2027
3e602632
NC		 2028 case 'y':
2029 if (!(opP->mode == AINDR
31302357
AS		 2030 || (opP->mode == DISP
2031 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2032 losing++;
2033 break;
2034
2035 case 'z':
2036 if (!(opP->mode == AINDR || opP->mode == DISP))
2037 losing++;
2038 break;
2039
252b5132
RH		 2040 default:
2041 abort ();
36759679 2042 }
252b5132
RH		 2043
2044 if (losing)
2045 break;
36759679 2046 }
03b13e59
NC		 2047
2048 /* Since we have found the correct instruction, copy
2049 in the modifications that we may have made. */
2050 if (!losing)
2051 for (i = 0; i < opsfound; i++)
2052 the_ins.operands[i] = operands_backup[i];
36759679 2053 }
252b5132
RH		 2054
2055 if (!losing)
36759679 2056 break;
252b5132
RH		 2057
2058 opcode = opcode->m_next;
2059
2060 if (!opcode)
2061 {
2062 if (ok_arch
2063 && !(ok_arch & current_architecture))
2064 {
6d89cc8f
NS		 2065 const struct m68k_cpu *cpu;
2066 int any = 0;
2067 size_t space = 400;
2068 char *buf = xmalloc (space + 1);
2069 size_t len;
2070 int paren = 1;
2071
2072 the_ins.error = buf;
2073 /* Make sure there's a NUL at the end of the buffer -- strncpy
2074 won't write one when it runs out of buffer */
2075 buf[space] = 0;
2076#define APPEND(STRING) \
2077 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2078
2079 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2080 switch (ok_arch)
2081 {
6b6e92f4 2082 case mcfisa_a:
6d89cc8f 2083 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2084 break;
2085 case mcfhwdiv:
6d89cc8f 2086 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2087 break;
2088 case mcfisa_aa:
6d89cc8f 2089 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2090 break;
2091 case mcfisa_b:
6d89cc8f 2092 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2093 break;
3e602632 2094 case cfloat:
6d89cc8f 2095 APPEND (_("ColdFire fpu"));
3e602632 2096 break;
252b5132 2097 case mfloat:
6d89cc8f 2098 APPEND (_("M68K fpu"));
252b5132
RH		 2099 break;
2100 case mmmu:
6d89cc8f 2101 APPEND (_("M68K mmu"));
252b5132
RH		 2102 break;
2103 case m68020up:
6d89cc8f 2104 APPEND (_("68020 or higher"));
252b5132
RH		 2105 break;
2106 case m68000up:
6d89cc8f 2107 APPEND (_("68000 or higher"));
252b5132
RH		 2108 break;
2109 case m68010up:
6d89cc8f 2110 APPEND (_("68010 or higher"));
252b5132
RH		 2111 break;
2112 default:
6d89cc8f
NS		 2113 paren = 0;
2114 }
2115 if (paren)
2116 APPEND (" (");
6b6e92f4 2117
6d89cc8f
NS		 2118 for (cpu = m68k_cpus; cpu->name; cpu++)
2119 if (!cpu->alias && (cpu->arch & ok_arch))
2120 {
2121 const struct m68k_cpu *alias;
869ddf2a
NS		 2122 int seen_master = 0;
2123
6d89cc8f
NS		 2124 if (any)
2125 APPEND (", ");
2126 any = 0;
2127 APPEND (cpu->name);
869ddf2a
NS		 2128 for (alias = cpu; alias != m68k_cpus; alias--)
2129 if (alias[-1].alias >= 0)
2130 break;
2131 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2132 {
869ddf2a
NS		 2133 if (!alias->alias)
2134 seen_master = 1;
2135 else
2136 {
2137 if (any)
2138 APPEND (", ");
2139 else
2140 APPEND (" [");
2141 APPEND (alias->name);
2142 any = 1;
2143 }
6d89cc8f 2144 }
869ddf2a
NS		 2145 if (any)
2146 APPEND ("]");
6d89cc8f 2147 any = 1;
252b5132 2148 }
6d89cc8f
NS		 2149 if (paren)
2150 APPEND (")");
2151#undef APPEND
2152 if (!space)
2153 {
2154 /* we ran out of space, so replace the end of the list
2155 with ellipsis. */
2156 buf -= 4;
2157 while (*buf != ' ')
2158 buf--;
2159 strcpy (buf, " ...");
252b5132 2160 }
252b5132
RH		 2161 }
2162 else
2163 the_ins.error = _("operands mismatch");
2164 return;
36759679 2165 }
252b5132
RH		 2166
2167 losing = 0;
2168 }
2169
36759679 2170 /* Now assemble it. */
252b5132
RH		 2171 the_ins.args = opcode->m_operands;
2172 the_ins.numargs = opcode->m_opnum;
2173 the_ins.numo = opcode->m_codenum;
2174 the_ins.opcode[0] = getone (opcode);
2175 the_ins.opcode[1] = gettwo (opcode);
2176
2177 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2178 {
2179 /* This switch is a doozy.
31302357 2180 Watch the first step; its a big one! */
252b5132
RH		 2181 switch (s[0])
2182 {
2183
2184 case '*':
2185 case '~':
2186 case '%':
2187 case ';':
2188 case '@':
2189 case '!':
2190 case '&':
2191 case '$':
2192 case '?':
2193 case '/':
2194 case '<':
2195 case '>':
3e602632 2196 case 'b':
252b5132
RH		 2197 case 'm':
2198 case 'n':
2199 case 'o':
2200 case 'p':
2201 case 'q':
2202 case 'v':
3e602632
NC		 2203 case 'w':
2204 case 'y':
2205 case 'z':
fd99574b 2206 case '4':
252b5132
RH		 2207#ifndef NO_68851
2208 case '|':
2209#endif
2210 switch (opP->mode)
2211 {
2212 case IMMED:
2213 tmpreg = 0x3c; /* 7.4 */
2214 if (strchr ("bwl", s[1]))
3e602632 2215 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2216 else
2217 nextword = get_num (&opP->disp, 0);
2218 if (isvar (&opP->disp))
2219 add_fix (s[1], &opP->disp, 0, 0);
2220 switch (s[1])
2221 {
2222 case 'b':
2223 if (!isbyte (nextword))
2224 opP->error = _("operand out of range");
2225 addword (nextword);
2226 baseo = 0;
2227 break;
2228 case 'w':
2229 if (!isword (nextword))
2230 opP->error = _("operand out of range");
2231 addword (nextword);
2232 baseo = 0;
2233 break;
2234 case 'W':
2235 if (!issword (nextword))
2236 opP->error = _("operand out of range");
2237 addword (nextword);
2238 baseo = 0;
2239 break;
2240 case 'l':
2241 addword (nextword >> 16);
2242 addword (nextword);
2243 baseo = 0;
2244 break;
2245
2246 case 'f':
2247 baseo = 2;
2248 outro = 8;
2249 break;
2250 case 'F':
2251 baseo = 4;
2252 outro = 11;
2253 break;
2254 case 'x':
2255 baseo = 6;
2256 outro = 15;
2257 break;
2258 case 'p':
2259 baseo = 6;
2260 outro = -1;
2261 break;
2262 default:
2263 abort ();
2264 }
2265 if (!baseo)
2266 break;
2267
36759679 2268 /* We gotta put out some float. */
252b5132
RH		 2269 if (op (&opP->disp) != O_big)
2270 {
2271 valueT val;
2272 int gencnt;
2273
2274 /* Can other cases happen here? */
2275 if (op (&opP->disp) != O_constant)
2276 abort ();
2277
2278 val = (valueT) offs (&opP->disp);
2279 gencnt = 0;
2280 do
2281 {
2282 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2283 val >>= LITTLENUM_NUMBER_OF_BITS;
2284 ++gencnt;
2285 }
2286 while (val != 0);
2287 offs (&opP->disp) = gencnt;
2288 }
2289 if (offs (&opP->disp) > 0)
2290 {
2291 if (offs (&opP->disp) > baseo)
2292 {
2293 as_warn (_("Bignum too big for %c format; truncated"),
2294 s[1]);
2295 offs (&opP->disp) = baseo;
2296 }
2297 baseo -= offs (&opP->disp);
2298 while (baseo--)
2299 addword (0);
2300 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2301 offs (&opP->disp)--;
2302 --wordp)
2303 addword (*wordp);
2304 break;
2305 }
2306 gen_to_words (words, baseo, (long) outro);
2307 for (wordp = words; baseo--; wordp++)
2308 addword (*wordp);
2309 break;
2310 case DREG:
2311 tmpreg = opP->reg - DATA; /* 0.dreg */
2312 break;
2313 case AREG:
2314 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2315 break;
2316 case AINDR:
2317 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2318 break;
2319 case ADEC:
2320 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2321 break;
2322 case AINC:
2323 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2324 break;
2325 case DISP:
2326
3e602632 2327 nextword = get_num (&opP->disp, 90);
252b5132 2328
580b9172
NC		 2329 /* Convert mode 5 addressing with a zero offset into
2330 mode 2 addressing to reduce the instruction size by a
2331 word. */
2332 if (! isvar (&opP->disp)
2333 && (nextword == 0)
2334 && (opP->disp.size == SIZE_UNSPEC)
2335 && (opP->reg >= ADDR0)
2336 && (opP->reg <= ADDR7))
2337 {
2338 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2339 break;
2340 }
2341
252b5132
RH		 2342 if (opP->reg == PC
2343 && ! isvar (&opP->disp)
2344 && m68k_abspcadd)
2345 {
2346 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2347 opP->disp.exp.X_add_symbol =
2348 section_symbol (absolute_section);
252b5132
RH		 2349 }
2350
36759679 2351 /* Force into index mode. Hope this works. */
252b5132
RH		 2352
2353 /* We do the first bit for 32-bit displacements, and the
2354 second bit for 16 bit ones. It is possible that we
2355 should make the default be WORD instead of LONG, but
2356 I think that'd break GCC, so we put up with a little
2357 inefficiency for the sake of working output. */
2358
2359 if (!issword (nextword)
2360 || (isvar (&opP->disp)
2361 && ((opP->disp.size == SIZE_UNSPEC
2362 && flag_short_refs == 0
2363 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2364 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2365 || opP->disp.size == SIZE_LONG)))
2366 {
2367 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2368 || arch_coldfire_p (current_architecture))
252b5132
RH		 2369 opP->error =
2370 _("displacement too large for this architecture; needs 68020 or higher");
2371 if (opP->reg == PC)
2372 tmpreg = 0x3B; /* 7.3 */
2373 else
2374 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2375 if (isvar (&opP->disp))
2376 {
2377 if (opP->reg == PC)
2378 {
2379 if (opP->disp.size == SIZE_LONG
2380#ifdef OBJ_ELF
2381 /* If the displacement needs pic
2382 relocation it cannot be relaxed. */
2383 || opP->disp.pic_reloc != pic_none
2384#endif
2385 )
2386 {
2387 addword (0x0170);
2388 add_fix ('l', &opP->disp, 1, 2);
2389 }
2390 else
2391 {
2392 add_frag (adds (&opP->disp),
bd17c2c3 2393 SEXT (offs (&opP->disp)),
151337e8 2394 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2395 break;
2396 }
2397 }
2398 else
2399 {
2400 addword (0x0170);
2401 add_fix ('l', &opP->disp, 0, 0);
2402 }
2403 }
2404 else
2405 addword (0x0170);
2406 addword (nextword >> 16);
2407 }
2408 else
2409 {
2410 if (opP->reg == PC)
2411 tmpreg = 0x3A; /* 7.2 */
2412 else
2413 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2414
2415 if (isvar (&opP->disp))
2416 {
2417 if (opP->reg == PC)
2418 {
2419 add_fix ('w', &opP->disp, 1, 0);
2420 }
2421 else
2422 add_fix ('w', &opP->disp, 0, 0);
2423 }
2424 }
2425 addword (nextword);
2426 break;
2427
2428 case POST:
2429 case PRE:
2430 case BASE:
2431 nextword = 0;
3e602632 2432 baseo = get_num (&opP->disp, 90);
252b5132 2433 if (opP->mode == POST || opP->mode == PRE)
3e602632 2434 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2435 /* Figure out the `addressing mode'.
2436 Also turn on the BASE_DISABLE bit, if needed. */
2437 if (opP->reg == PC || opP->reg == ZPC)
2438 {
2439 tmpreg = 0x3b; /* 7.3 */
2440 if (opP->reg == ZPC)
2441 nextword |= 0x80;
2442 }
2443 else if (opP->reg == 0)
2444 {
2445 nextword |= 0x80;
2446 tmpreg = 0x30; /* 6.garbage */
2447 }
2448 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2449 {
2450 nextword |= 0x80;
2451 tmpreg = 0x30 + opP->reg - ZADDR0;
2452 }
2453 else
2454 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2455
2456 siz1 = opP->disp.size;
2457 if (opP->mode == POST || opP->mode == PRE)
2458 siz2 = opP->odisp.size;
2459 else
2460 siz2 = SIZE_UNSPEC;
2461
36759679 2462 /* Index register stuff. */
252b5132
RH		 2463 if (opP->index.reg != 0
2464 && opP->index.reg >= DATA
2465 && opP->index.reg <= ADDR7)
2466 {
2467 nextword |= (opP->index.reg - DATA) << 12;
2468
2469 if (opP->index.size == SIZE_LONG
2470 || (opP->index.size == SIZE_UNSPEC
2471 && m68k_index_width_default == SIZE_LONG))
2472 nextword |= 0x800;
2473
92774660 2474 if ((opP->index.scale != 1
252b5132 2475 && cpu_of_arch (current_architecture) < m68020)
92774660 2476 || (opP->index.scale == 8
3e602632 2477 && (arch_coldfire_p (current_architecture)
6b6e92f4 2478 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2479 {
2480 opP->error =
2481 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2482 }
2483
6da466c7
ILT		 2484 if (arch_coldfire_p (current_architecture)
2485 && opP->index.size == SIZE_WORD)
2486 opP->error = _("invalid index size for coldfire");
2487
252b5132
RH		 2488 switch (opP->index.scale)
2489 {
2490 case 1:
2491 break;
2492 case 2:
2493 nextword |= 0x200;
2494 break;
2495 case 4:
2496 nextword |= 0x400;
2497 break;
2498 case 8:
2499 nextword |= 0x600;
2500 break;
2501 default:
2502 abort ();
2503 }
2504 /* IF its simple,
2505 GET US OUT OF HERE! */
2506
2507 /* Must be INDEX, with an index register. Address
2508 register cannot be ZERO-PC, and either :b was
2509 forced, or we know it will fit. For a 68000 or
2510 68010, force this mode anyways, because the
2511 larger modes aren't supported. */
2512 if (opP->mode == BASE
2513 && ((opP->reg >= ADDR0
2514 && opP->reg <= ADDR7)
2515 || opP->reg == PC))
2516 {
2517 if (siz1 == SIZE_BYTE
2518 || cpu_of_arch (current_architecture) < m68020
6da466c7 2519 || arch_coldfire_p (current_architecture)
252b5132
RH		 2520 || (siz1 == SIZE_UNSPEC
2521 && ! isvar (&opP->disp)
2522 && issbyte (baseo)))
2523 {
2524 nextword += baseo & 0xff;
2525 addword (nextword);
2526 if (isvar (&opP->disp))
2527 {
2528 /* Do a byte relocation. If it doesn't
2529 fit (possible on m68000) let the
2530 fixup processing complain later. */
2531 if (opP->reg == PC)
2532 add_fix ('B', &opP->disp, 1, 1);
2533 else
2534 add_fix ('B', &opP->disp, 0, 0);
2535 }
2536 else if (siz1 != SIZE_BYTE)
2537 {
2538 if (siz1 != SIZE_UNSPEC)
2539 as_warn (_("Forcing byte displacement"));
2540 if (! issbyte (baseo))
2541 opP->error = _("byte displacement out of range");
2542 }
2543
2544 break;
2545 }
2546 else if (siz1 == SIZE_UNSPEC
2547 && opP->reg == PC
2548 && isvar (&opP->disp)
2549 && subs (&opP->disp) == NULL
2550#ifdef OBJ_ELF
2551 /* If the displacement needs pic
2552 relocation it cannot be relaxed. */
2553 && opP->disp.pic_reloc == pic_none
2554#endif
2555 )
2556 {
2557 /* The code in md_convert_frag_1 needs to be
2558 able to adjust nextword. Call frag_grow
2559 to ensure that we have enough space in
2560 the frag obstack to make all the bytes
2561 contiguous. */
2562 frag_grow (14);
8a104df9
KH		 2563 nextword += baseo & 0xff;
2564 addword (nextword);
bd17c2c3
AM		 2565 add_frag (adds (&opP->disp),
2566 SEXT (offs (&opP->disp)),
8a104df9 2567 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2568
2569 break;
8a104df9 2570 }
252b5132
RH		 2571 }
2572 }
2573 else
2574 {
36759679 2575 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2576 if (opP->index.reg >= ZDATA0
2577 && opP->index.reg <= ZDATA7)
2578 nextword |= (opP->index.reg - ZDATA0) << 12;
2579 else if (opP->index.reg >= ZADDR0
2580 || opP->index.reg <= ZADDR7)
2581 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2582 }
2583
2584 /* It isn't simple. */
2585
2586 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2587 || arch_coldfire_p (current_architecture))
252b5132
RH		 2588 opP->error =
2589 _("invalid operand mode for this architecture; needs 68020 or higher");
2590
2591 nextword |= 0x100;
2592 /* If the guy specified a width, we assume that it is
2593 wide enough. Maybe it isn't. If so, we lose. */
2594 switch (siz1)
2595 {
2596 case SIZE_UNSPEC:
2597 if (isvar (&opP->disp)
2598 ? m68k_rel32
2599 : ! issword (baseo))
2600 {
2601 siz1 = SIZE_LONG;
2602 nextword |= 0x30;
2603 }
2604 else if (! isvar (&opP->disp) && baseo == 0)
2605 nextword |= 0x10;
2606 else
2607 {
2608 nextword |= 0x20;
2609 siz1 = SIZE_WORD;
2610 }
2611 break;
2612 case SIZE_BYTE:
2613 as_warn (_(":b not permitted; defaulting to :w"));
2614 /* Fall through. */
2615 case SIZE_WORD:
2616 nextword |= 0x20;
2617 break;
2618 case SIZE_LONG:
2619 nextword |= 0x30;
2620 break;
2621 }
2622
67c1ffbe 2623 /* Figure out inner displacement stuff. */
252b5132
RH		 2624 if (opP->mode == POST || opP->mode == PRE)
2625 {
2626 if (cpu_of_arch (current_architecture) & cpu32)
2627 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2628 switch (siz2)
2629 {
2630 case SIZE_UNSPEC:
2631 if (isvar (&opP->odisp)
2632 ? m68k_rel32
2633 : ! issword (outro))
2634 {
2635 siz2 = SIZE_LONG;
2636 nextword |= 0x3;
2637 }
2638 else if (! isvar (&opP->odisp) && outro == 0)
2639 nextword |= 0x1;
2640 else
2641 {
2642 nextword |= 0x2;
2643 siz2 = SIZE_WORD;
2644 }
2645 break;
2646 case 1:
2647 as_warn (_(":b not permitted; defaulting to :w"));
2648 /* Fall through. */
2649 case 2:
2650 nextword |= 0x2;
2651 break;
2652 case 3:
2653 nextword |= 0x3;
2654 break;
2655 }
2656 if (opP->mode == POST
2657 && (nextword & 0x40) == 0)
2658 nextword |= 0x04;
2659 }
2660 addword (nextword);
2661
2662 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2663 {
2664 if (opP->reg == PC || opP->reg == ZPC)
2665 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2666 else
2667 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2668 }
2669 if (siz1 == SIZE_LONG)
2670 addword (baseo >> 16);
2671 if (siz1 != SIZE_UNSPEC)
2672 addword (baseo);
2673
2674 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2675 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2676 if (siz2 == SIZE_LONG)
2677 addword (outro >> 16);
2678 if (siz2 != SIZE_UNSPEC)
2679 addword (outro);
2680
2681 break;
2682
2683 case ABSL:
3e602632 2684 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2685 switch (opP->disp.size)
2686 {
2687 default:
2688 abort ();
2689 case SIZE_UNSPEC:
2690 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2691 {
2692 tmpreg = 0x38; /* 7.0 */
2693 addword (nextword);
2694 break;
2695 }
252b5132
RH		 2696 if (isvar (&opP->disp)
2697 && !subs (&opP->disp)
2698 && adds (&opP->disp)
2699#ifdef OBJ_ELF
2700 /* If the displacement needs pic relocation it
2701 cannot be relaxed. */
2702 && opP->disp.pic_reloc == pic_none
2703#endif
252b5132
RH		 2704 && !flag_long_jumps
2705 && !strchr ("~%&$?", s[0]))
2706 {
2707 tmpreg = 0x3A; /* 7.2 */
2708 add_frag (adds (&opP->disp),
bd17c2c3 2709 SEXT (offs (&opP->disp)),
151337e8 2710 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2711 break;
2712 }
36759679 2713 /* Fall through into long. */
252b5132
RH		 2714 case SIZE_LONG:
2715 if (isvar (&opP->disp))
2716 add_fix ('l', &opP->disp, 0, 0);
2717
2718 tmpreg = 0x39;/* 7.1 mode */
2719 addword (nextword >> 16);
2720 addword (nextword);
2721 break;
2722
2723 case SIZE_BYTE:
2724 as_bad (_("unsupported byte value; use a different suffix"));
2725 /* Fall through. */
36759679
NC		 2726
2727 case SIZE_WORD:
252b5132
RH		 2728 if (isvar (&opP->disp))
2729 add_fix ('w', &opP->disp, 0, 0);
2730
2731 tmpreg = 0x38;/* 7.0 mode */
2732 addword (nextword);
2733 break;
2734 }
2735 break;
2736 case CONTROL:
2737 case FPREG:
2738 default:
2739 as_bad (_("unknown/incorrect operand"));
bc805888 2740 /* abort (); */
252b5132 2741 }
fd99574b
NC		 2742
2743 /* If s[0] is '4', then this is for the mac instructions
2744 that can have a trailing_ampersand set. If so, set 0x100
2745 bit on tmpreg so install_gen_operand can check for it and
2746 set the appropriate bit (word2, bit 5). */
2747 if (s[0] == '4')
2748 {
2749 if (opP->trailing_ampersand)
2750 tmpreg |= 0x100;
2751 }
252b5132
RH		 2752 install_gen_operand (s[1], tmpreg);
2753 break;
2754
2755 case '#':
2756 case '^':
2757 switch (s[1])
2758 { /* JF: I hate floating point! */
2759 case 'j':
2760 tmpreg = 70;
2761 break;
2762 case '8':
2763 tmpreg = 20;
2764 break;
2765 case 'C':
2766 tmpreg = 50;
2767 break;
2768 case '3':
2769 default:
3e602632 2770 tmpreg = 90;
252b5132
RH		 2771 break;
2772 }
2773 tmpreg = get_num (&opP->disp, tmpreg);
2774 if (isvar (&opP->disp))
2775 add_fix (s[1], &opP->disp, 0, 0);
2776 switch (s[1])
2777 {
2778 case 'b': /* Danger: These do no check for
2779 certain types of overflow.
2780 user beware! */
2781 if (!isbyte (tmpreg))
2782 opP->error = _("out of range");
2783 insop (tmpreg, opcode);
2784 if (isvar (&opP->disp))
2785 the_ins.reloc[the_ins.nrel - 1].n =
2786 (opcode->m_codenum) * 2 + 1;
2787 break;
2788 case 'B':
2789 if (!issbyte (tmpreg))
2790 opP->error = _("out of range");
2791 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2792 if (isvar (&opP->disp))
2793 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2794 break;
2795 case 'w':
2796 if (!isword (tmpreg))
2797 opP->error = _("out of range");
2798 insop (tmpreg, opcode);
2799 if (isvar (&opP->disp))
2800 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2801 break;
2802 case 'W':
2803 if (!issword (tmpreg))
2804 opP->error = _("out of range");
2805 insop (tmpreg, opcode);
2806 if (isvar (&opP->disp))
2807 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2808 break;
2809 case 'l':
2810 /* Because of the way insop works, we put these two out
2811 backwards. */
2812 insop (tmpreg, opcode);
2813 insop (tmpreg >> 16, opcode);
2814 if (isvar (&opP->disp))
2815 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2816 break;
2817 case '3':
2818 tmpreg &= 0xFF;
2819 case '8':
2820 case 'C':
2821 case 'j':
2822 install_operand (s[1], tmpreg);
2823 break;
2824 default:
2825 abort ();
2826 }
2827 break;
2828
2829 case '+':
2830 case '-':
2831 case 'A':
2832 case 'a':
2833 install_operand (s[1], opP->reg - ADDR);
2834 break;
2835
2836 case 'B':
3e602632 2837 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2838 switch (s[1])
2839 {
2840 case 'B':
8390138c 2841 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2842 break;
2843 case 'W':
2844 add_fix ('w', &opP->disp, 1, 0);
2845 addword (0);
2846 break;
2847 case 'L':
2848 long_branch:
151337e8 2849 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2850 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2851 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2852 add_fix ('l', &opP->disp, 1, 0);
2853 addword (0);
2854 addword (0);
2855 break;
2856 case 'g':
36759679 2857 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2858 goto long_branch;
2859
2860#ifdef OBJ_ELF
2861 /* If the displacement needs pic relocation it cannot be
2862 relaxed. */
2863 if (opP->disp.pic_reloc != pic_none)
2864 goto long_branch;
2865#endif
252b5132 2866 /* This could either be a symbol, or an absolute
151337e8
NC		 2867 address. If it's an absolute address, turn it into
2868 an absolute jump right here and keep it out of the
2869 relaxer. */
2870 if (adds (&opP->disp) == 0)
2871 {
2872 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2873 the_ins.opcode[0] = 0x4EF9;
151337e8 2874 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2875 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2876 else /* jCC */
2877 {
2878 the_ins.opcode[0] ^= 0x0100;
2879 the_ins.opcode[0] |= 0x0006;
18566f55 2880 addword (0x4EF9);
151337e8
NC		 2881 }
2882 add_fix ('l', &opP->disp, 0, 0);
2883 addword (0);
2884 addword (0);
2885 break;
2886 }
2887
2888 /* Now we know it's going into the relaxer. Now figure
2889 out which mode. We try in this order of preference:
2890 long branch, absolute jump, byte/word branches only. */
2891 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2892 add_frag (adds (&opP->disp),
2893 SEXT (offs (&opP->disp)),
151337e8
NC		 2894 TAB (BRANCHBWL, SZ_UNDEF));
2895 else if (! flag_keep_pcrel)
2896 {
2897 if ((the_ins.opcode[0] == 0x6000)
2898 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2899 add_frag (adds (&opP->disp),
2900 SEXT (offs (&opP->disp)),
151337e8
NC		 2901 TAB (BRABSJUNC, SZ_UNDEF));
2902 else
bd17c2c3
AM		 2903 add_frag (adds (&opP->disp),
2904 SEXT (offs (&opP->disp)),
151337e8
NC		 2905 TAB (BRABSJCOND, SZ_UNDEF));
2906 }
252b5132 2907 else
bd17c2c3
AM		 2908 add_frag (adds (&opP->disp),
2909 SEXT (offs (&opP->disp)),
151337e8 2910 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2911 break;
2912 case 'w':
2913 if (isvar (&opP->disp))
2914 {
151337e8
NC		 2915 /* Check for DBcc instructions. We can relax them,
2916 but only if we have long branches and/or absolute
2917 jumps. */
2918 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2919 && (HAVE_LONG_BRANCH (current_architecture)
2920 || (! flag_keep_pcrel)))
252b5132 2921 {
151337e8 2922 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2923 add_frag (adds (&opP->disp),
2924 SEXT (offs (&opP->disp)),
151337e8
NC		 2925 TAB (DBCCLBR, SZ_UNDEF));
2926 else
bd17c2c3
AM		 2927 add_frag (adds (&opP->disp),
2928 SEXT (offs (&opP->disp)),
151337e8 2929 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2930 break;
2931 }
252b5132
RH		 2932 add_fix ('w', &opP->disp, 1, 0);
2933 }
2934 addword (0);
2935 break;
36759679 2936 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2937 add_fix ('l', &opP->disp, 1, 0);
2938 addword (0);
2939 addword (0);
2940 break;
36759679 2941 case 'c': /* Var size Coprocesssor branches. */
151337e8 2942 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2943 {
252b5132
RH		 2944 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2945 add_fix ('l', &opP->disp, 1, 0);
2946 addword (0);
2947 addword (0);
2948 }
151337e8 2949 else
bd17c2c3
AM		 2950 add_frag (adds (&opP->disp),
2951 SEXT (offs (&opP->disp)),
151337e8 2952 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2953 break;
2954 default:
2955 abort ();
2956 }
2957 break;
2958
36759679 2959 case 'C': /* Ignore it. */
252b5132
RH		 2960 break;
2961
36759679 2962 case 'd': /* JF this is a kludge. */
252b5132 2963 install_operand ('s', opP->reg - ADDR);
3e602632 2964 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2965 if (!issword (tmpreg))
2966 {
2967 as_warn (_("Expression out of range, using 0"));
2968 tmpreg = 0;
2969 }
2970 addword (tmpreg);
2971 break;
2972
2973 case 'D':
2974 install_operand (s[1], opP->reg - DATA);
2975 break;
2976
fd99574b
NC		 2977 case 'e': /* EMAC ACCx, reg/reg. */
2978 install_operand (s[1], opP->reg - ACC);
2979 break;
2980
36759679 2981 case 'E': /* Ignore it. */
6da466c7
ILT		 2982 break;
2983
252b5132
RH		 2984 case 'F':
2985 install_operand (s[1], opP->reg - FP0);
2986 break;
2987
fd99574b
NC		 2988 case 'g': /* EMAC ACCEXTx. */
2989 install_operand (s[1], opP->reg - ACCEXT01);
2990 break;
2991
36759679 2992 case 'G': /* Ignore it. */
6da466c7
ILT		 2993 case 'H':
2994 break;
2995
252b5132
RH		 2996 case 'I':
2997 tmpreg = opP->reg - COP0;
2998 install_operand (s[1], tmpreg);
2999 break;
3000
fd99574b
NC		 3001 case 'i': /* MAC/EMAC scale factor. */
3002 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3003 break;
3004
36759679 3005 case 'J': /* JF foo. */
252b5132
RH		 3006 switch (opP->reg)
3007 {
3008 case SFC:
3009 tmpreg = 0x000;
3010 break;
3011 case DFC:
3012 tmpreg = 0x001;
3013 break;
3014 case CACR:
3015 tmpreg = 0x002;
3016 break;
3017 case TC:
a8e24a56 3018 case ASID:
252b5132
RH		 3019 tmpreg = 0x003;
3020 break;
3e602632 3021 case ACR0:
252b5132
RH		 3022 case ITT0:
3023 tmpreg = 0x004;
3024 break;
3e602632 3025 case ACR1:
252b5132
RH		 3026 case ITT1:
3027 tmpreg = 0x005;
3028 break;
3e602632 3029 case ACR2:
252b5132
RH		 3030 case DTT0:
3031 tmpreg = 0x006;
3032 break;
3e602632 3033 case ACR3:
252b5132
RH		 3034 case DTT1:
3035 tmpreg = 0x007;
3036 break;
3037 case BUSCR:
a8e24a56 3038 case MMUBAR:
252b5132
RH		 3039 tmpreg = 0x008;
3040 break;
3041
3042 case USP:
3043 tmpreg = 0x800;
3044 break;
3045 case VBR:
3046 tmpreg = 0x801;
3047 break;
3048 case CAAR:
3049 tmpreg = 0x802;
3050 break;
3051 case MSP:
3052 tmpreg = 0x803;
3053 break;
3054 case ISP:
3055 tmpreg = 0x804;
3056 break;
3057 case MMUSR:
3058 tmpreg = 0x805;
3059 break;
3060 case URP:
3061 tmpreg = 0x806;
3062 break;
3063 case SRP:
3064 tmpreg = 0x807;
3065 break;
3066 case PCR:
3067 tmpreg = 0x808;
3068 break;
3069 case ROMBAR:
a8e24a56 3070 case ROMBAR0:
252b5132
RH		 3071 tmpreg = 0xC00;
3072 break;
3e602632
NC		 3073 case ROMBAR1:
3074 tmpreg = 0xC01;
3075 break;
3076 case FLASHBAR:
252b5132
RH		 3077 case RAMBAR0:
3078 tmpreg = 0xC04;
3079 break;
3e602632 3080 case RAMBAR:
252b5132
RH		 3081 case RAMBAR1:
3082 tmpreg = 0xC05;
3083 break;
3e602632
NC		 3084 case MPCR:
3085 tmpreg = 0xC0C;
3086 break;
3087 case EDRAMBAR:
3088 tmpreg = 0xC0D;
3089 break;
3090 case MBAR0:
e80e0390 3091 case MBAR2:
3e602632
NC		 3092 case SECMBAR:
3093 tmpreg = 0xC0E;
3094 break;
3095 case MBAR1:
252b5132
RH		 3096 case MBAR:
3097 tmpreg = 0xC0F;
3098 break;
3e602632
NC		 3099 case PCR1U0:
3100 tmpreg = 0xD02;
3101 break;
3102 case PCR1L0:
3103 tmpreg = 0xD03;
3104 break;
3105 case PCR2U0:
3106 tmpreg = 0xD04;
3107 break;
3108 case PCR2L0:
3109 tmpreg = 0xD05;
3110 break;
3111 case PCR3U0:
3112 tmpreg = 0xD06;
3113 break;
3114 case PCR3L0:
3115 tmpreg = 0xD07;
3116 break;
3117 case PCR1L1:
3118 tmpreg = 0xD0A;
3119 break;
3120 case PCR1U1:
3121 tmpreg = 0xD0B;
3122 break;
3123 case PCR2L1:
3124 tmpreg = 0xD0C;
3125 break;
3126 case PCR2U1:
3127 tmpreg = 0xD0D;
3128 break;
3129 case PCR3L1:
3130 tmpreg = 0xD0E;
3131 break;
3132 case PCR3U1:
3133 tmpreg = 0xD0F;
3134 break;
f7ec513b
KH		 3135 case CAC:
3136 tmpreg = 0xFFE;
3137 break;
3138 case MBB:
3139 tmpreg = 0xFFF;
3140 break;
252b5132
RH		 3141 default:
3142 abort ();
3143 }
3144 install_operand (s[1], tmpreg);
3145 break;
3146
3147 case 'k':
3148 tmpreg = get_num (&opP->disp, 55);
3149 install_operand (s[1], tmpreg & 0x7f);
3150 break;
3151
3152 case 'l':
3153 tmpreg = opP->mask;
3154 if (s[1] == 'w')
3155 {
3156 if (tmpreg & 0x7FF0000)
3157 as_bad (_("Floating point register in register list"));
3158 insop (reverse_16_bits (tmpreg), opcode);
3159 }
3160 else
3161 {
3162 if (tmpreg & 0x700FFFF)
3163 as_bad (_("Wrong register in floating-point reglist"));
3164 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3165 }
3166 break;
3167
3168 case 'L':
3169 tmpreg = opP->mask;
3170 if (s[1] == 'w')
3171 {
3172 if (tmpreg & 0x7FF0000)
3173 as_bad (_("Floating point register in register list"));
3174 insop (tmpreg, opcode);
3175 }
3176 else if (s[1] == '8')
3177 {
3178 if (tmpreg & 0x0FFFFFF)
3179 as_bad (_("incorrect register in reglist"));
3180 install_operand (s[1], tmpreg >> 24);
3181 }
3182 else
3183 {
3184 if (tmpreg & 0x700FFFF)
3185 as_bad (_("wrong register in floating-point reglist"));
3186 else
3187 install_operand (s[1], tmpreg >> 16);
3188 }
3189 break;
3190
3191 case 'M':
3192 install_operand (s[1], get_num (&opP->disp, 60));
3193 break;
3194
3195 case 'O':
3196 tmpreg = ((opP->mode == DREG)
8fce3f5e 3197 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3198 : (get_num (&opP->disp, 40) & 0x1F));
3199 install_operand (s[1], tmpreg);
3200 break;
3201
3202 case 'Q':
3203 tmpreg = get_num (&opP->disp, 10);
3204 if (tmpreg == 8)
3205 tmpreg = 0;
3206 install_operand (s[1], tmpreg);
3207 break;
3208
3209 case 'R':
3210 /* This depends on the fact that ADDR registers are eight
3211 more than their corresponding DATA regs, so the result
36759679 3212 will have the ADDR_REG bit set. */
252b5132
RH		 3213 install_operand (s[1], opP->reg - DATA);
3214 break;
3215
3216 case 'r':
3217 if (opP->mode == AINDR)
3218 install_operand (s[1], opP->reg - DATA);
3219 else
3220 install_operand (s[1], opP->index.reg - DATA);
3221 break;
3222
3223 case 's':
3224 if (opP->reg == FPI)
3225 tmpreg = 0x1;
3226 else if (opP->reg == FPS)
3227 tmpreg = 0x2;
3228 else if (opP->reg == FPC)
3229 tmpreg = 0x4;
3230 else
3231 abort ();
3232 install_operand (s[1], tmpreg);
3233 break;
3234
36759679 3235 case 'S': /* Ignore it. */
252b5132
RH		 3236 break;
3237
3238 case 'T':
3239 install_operand (s[1], get_num (&opP->disp, 30));
3240 break;
3241
36759679 3242 case 'U': /* Ignore it. */
252b5132
RH		 3243 break;
3244
3245 case 'c':
3246 switch (opP->reg)
3247 {
3248 case NC:
3249 tmpreg = 0;
3250 break;
3251 case DC:
3252 tmpreg = 1;
3253 break;
3254 case IC:
3255 tmpreg = 2;
3256 break;
3257 case BC:
3258 tmpreg = 3;
3259 break;
3260 default:
3261 as_fatal (_("failed sanity check"));
36759679 3262 } /* switch on cache token. */
252b5132
RH		 3263 install_operand (s[1], tmpreg);
3264 break;
3265#ifndef NO_68851
92774660 3266 /* JF: These are out of order, I fear. */
252b5132
RH		 3267 case 'f':
3268 switch (opP->reg)
3269 {
3270 case SFC:
3271 tmpreg = 0;
3272 break;
3273 case DFC:
3274 tmpreg = 1;
3275 break;
3276 default:
3277 abort ();
3278 }
3279 install_operand (s[1], tmpreg);
3280 break;
3281
3282 case '0':
3283 case '1':
3284 case '2':
3285 switch (opP->reg)
3286 {
3287 case TC:
3288 tmpreg = 0;
3289 break;
3290 case CAL:
3291 tmpreg = 4;
3292 break;
3293 case VAL:
3294 tmpreg = 5;
3295 break;
3296 case SCC:
3297 tmpreg = 6;
3298 break;
3299 case AC:
3300 tmpreg = 7;
3301 break;
3302 default:
3303 abort ();
3304 }
3305 install_operand (s[1], tmpreg);
3306 break;
3307
3308 case 'V':
3309 if (opP->reg == VAL)
3310 break;
3311 abort ();
3312
3313 case 'W':
3314 switch (opP->reg)
3315 {
3316 case DRP:
3317 tmpreg = 1;
3318 break;
3319 case SRP:
3320 tmpreg = 2;
3321 break;
3322 case CRP:
3323 tmpreg = 3;
3324 break;
3325 default:
3326 abort ();
3327 }
3328 install_operand (s[1], tmpreg);
3329 break;
3330
3331 case 'X':
3332 switch (opP->reg)
3333 {
3334 case BAD:
3335 case BAD + 1:
3336 case BAD + 2:
3337 case BAD + 3:
3338 case BAD + 4:
3339 case BAD + 5:
3340 case BAD + 6:
3341 case BAD + 7:
3342 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3343 break;
3344
3345 case BAC:
3346 case BAC + 1:
3347 case BAC + 2:
3348 case BAC + 3:
3349 case BAC + 4:
3350 case BAC + 5:
3351 case BAC + 6:
3352 case BAC + 7:
3353 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3354 break;
3355
3356 default:
3357 abort ();
3358 }
3359 install_operand (s[1], tmpreg);
3360 break;
3361 case 'Y':
3362 know (opP->reg == PSR);
3363 break;
3364 case 'Z':
3365 know (opP->reg == PCSR);
3366 break;
3367#endif /* m68851 */
3368 case '3':
3369 switch (opP->reg)
3370 {
3371 case TT0:
3372 tmpreg = 2;
3373 break;
3374 case TT1:
3375 tmpreg = 3;
3376 break;
3377 default:
3378 abort ();
3379 }
3380 install_operand (s[1], tmpreg);
3381 break;
3382 case 't':
3383 tmpreg = get_num (&opP->disp, 20);
3384 install_operand (s[1], tmpreg);
3385 break;
36759679 3386 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3387 if (isvar (&opP->disp))
3388 add_fix ('l', &opP->disp, 0, 0);
3e602632 3389 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3390 addword (tmpreg >> 16);
3391 addword (tmpreg & 0xFFFF);
3392 break;
6da466c7
ILT		 3393 case 'u':
3394 install_operand (s[1], opP->reg - DATA0L);
3395 opP->reg -= (DATA0L);
36759679 3396 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3397 break;
3e602632
NC		 3398 case 'x':
3399 tmpreg = get_num (&opP->disp, 80);
3400 if (tmpreg == -1)
3401 tmpreg = 0;
3402 install_operand (s[1], tmpreg);
3403 break;
252b5132
RH		 3404 default:
3405 abort ();
3406 }
3407 }
3408
3409 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3410 instruction, ready to be emitted. . . */
252b5132
RH		 3411}
3412
3413static int
31302357 3414reverse_16_bits (int in)
252b5132
RH		 3415{
3416 int out = 0;
3417 int n;
3418
3419 static int mask[16] =
3420 {
3421 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3422 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3423 };
3424 for (n = 0; n < 16; n++)
3425 {
3426 if (in & mask[n])
3427 out |= mask[15 - n];
3428 }
3429 return out;
3430} /* reverse_16_bits() */
3431
3432static int
31302357 3433reverse_8_bits (int in)
252b5132
RH		 3434{
3435 int out = 0;
3436 int n;
3437
3438 static int mask[8] =
3439 {
3440 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3441 };
3442
3443 for (n = 0; n < 8; n++)
3444 {
3445 if (in & mask[n])
3446 out |= mask[7 - n];
3447 }
3448 return out;
3449} /* reverse_8_bits() */
3450
3451/* Cause an extra frag to be generated here, inserting up to 10 bytes
3452 (that value is chosen in the frag_var call in md_assemble). TYPE
3453 is the subtype of the frag to be generated; its primary type is
3454 rs_machine_dependent.
3455
3456 The TYPE parameter is also used by md_convert_frag_1 and
3457 md_estimate_size_before_relax. The appropriate type of fixup will
3458 be emitted by md_convert_frag_1.
3459
3460 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3461static void
31302357 3462install_operand (int mode, int val)
252b5132
RH		 3463{
3464 switch (mode)
3465 {
3466 case 's':
36759679 3467 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3468 break;
3469 case 'd':
3470 the_ins.opcode[0] |= val << 9;
3471 break;
3472 case '1':
3473 the_ins.opcode[1] |= val << 12;
3474 break;
3475 case '2':
3476 the_ins.opcode[1] |= val << 6;
3477 break;
3478 case '3':
3479 the_ins.opcode[1] |= val;
3480 break;
3481 case '4':
3482 the_ins.opcode[2] |= val << 12;
3483 break;
3484 case '5':
3485 the_ins.opcode[2] |= val << 6;
3486 break;
3487 case '6':
3488 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3489 three words long! */
3490 the_ins.numo++;
3491 the_ins.opcode[2] |= val;
3492 break;
3493 case '7':
3494 the_ins.opcode[1] |= val << 7;
3495 break;
3496 case '8':
3497 the_ins.opcode[1] |= val << 10;
3498 break;
3499#ifndef NO_68851
3500 case '9':
3501 the_ins.opcode[1] |= val << 5;
3502 break;
3503#endif
3504
3505 case 't':
3506 the_ins.opcode[1] |= (val << 10) | (val << 7);
3507 break;
3508 case 'D':
3509 the_ins.opcode[1] |= (val << 12) | val;
3510 break;
3511 case 'g':
3512 the_ins.opcode[0] |= val = 0xff;
3513 break;
3514 case 'i':
3515 the_ins.opcode[0] |= val << 9;
3516 break;
3517 case 'C':
3518 the_ins.opcode[1] |= val;
3519 break;
3520 case 'j':
3521 the_ins.opcode[1] |= val;
36759679 3522 the_ins.numo++; /* What a hack. */
252b5132
RH		 3523 break;
3524 case 'k':
3525 the_ins.opcode[1] |= val << 4;
3526 break;
3527 case 'b':
3528 case 'w':
3529 case 'W':
3530 case 'l':
3531 break;
3532 case 'e':
3533 the_ins.opcode[0] |= (val << 6);
3534 break;
3535 case 'L':
3536 the_ins.opcode[1] = (val >> 16);
3537 the_ins.opcode[2] = val & 0xffff;
3538 break;
6da466c7
ILT		 3539 case 'm':
3540 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3541 the_ins.opcode[0] |= ((val & 0x7) << 9);
3542 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3543 break;
fd99574b 3544 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3545 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3546 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3547 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3548 break;
fd99574b 3549 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3550 the_ins.opcode[1] |= val << 12;
3551 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3552 break;
fd99574b 3553 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3554 the_ins.opcode[0] |= (val & 0xF);
3555 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3556 break;
fd99574b 3557 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3558 the_ins.opcode[1] |= (val & 0xF);
3559 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3560 break;
3561 case 'h':
3562 the_ins.opcode[1] |= ((val != 1) << 10);
3563 break;
fd99574b
NC		 3564 case 'F':
3565 the_ins.opcode[0] |= ((val & 0x3) << 9);
3566 break;
3567 case 'f':
3568 the_ins.opcode[0] |= ((val & 0x3) << 0);
3569 break;
be8c092b 3570 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3571 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3572 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3573 break;
be8c092b 3574 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3575 the_ins.opcode[0] |= ((val & 0x1) << 7);
3576 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3577 break;
3578 case 'I':
3579 the_ins.opcode[1] |= ((val & 0x3) << 9);
3580 break;
3581 case ']':
3582 the_ins.opcode[0] |= (val & 0x1) <<10;
3583 break;
252b5132
RH		 3584 case 'c':
3585 default:
3586 as_fatal (_("failed sanity check."));
3587 }
6b6e92f4 3588}
252b5132
RH		 3589
3590static void
31302357 3591install_gen_operand (int mode, int val)
252b5132
RH		 3592{
3593 switch (mode)
3594 {
fd99574b
NC		 3595 case '/': /* Special for mask loads for mac/msac insns with
3596 possible mask; trailing_ampersend set in bit 8. */
3597 the_ins.opcode[0] |= (val & 0x3f);
3598 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3599 break;
252b5132
RH		 3600 case 's':
3601 the_ins.opcode[0] |= val;
3602 break;
3603 case 'd':
3604 /* This is a kludge!!! */
3605 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3606 break;
3607 case 'b':
3608 case 'w':
3609 case 'l':
3610 case 'f':
3611 case 'F':
3612 case 'x':
3613 case 'p':
3614 the_ins.opcode[0] |= val;
3615 break;
36759679 3616 /* more stuff goes here. */
252b5132
RH		 3617 default:
3618 as_fatal (_("failed sanity check."));
3619 }
6b6e92f4 3620}
252b5132 3621
6b6e92f4
NC		 3622/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3623 then deal with the bitfield hack. */
252b5132
RH		 3624
3625static char *
31302357 3626crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3627{
3628 register int parens;
3629 register int c;
3630 register char *beg_str;
3631 int inquote = 0;
3632
3633 if (!str)
3634 {
3635 return str;
3636 }
3637 beg_str = str;
3638 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3639 {
3640 if (! inquote)
3641 {
3642 if (*str == '(')
3643 parens++;
3644 else if (*str == ')')
3645 {
3646 if (!parens)
36759679 3647 { /* ERROR. */
252b5132
RH		 3648 opP->error = _("Extra )");
3649 return str;
3650 }
3651 --parens;
3652 }
3653 }
3654 if (flag_mri && *str == '\'')
3655 inquote = ! inquote;
3656 }
3657 if (!*str && parens)
36759679 3658 { /* ERROR. */
252b5132
RH		 3659 opP->error = _("Missing )");
3660 return str;
3661 }
3662 c = *str;
3663 *str = '\0';
3664 if (m68k_ip_op (beg_str, opP) != 0)
3665 {
3666 *str = c;
3667 return str;
3668 }
3669 *str = c;
3670 if (c == '}')
36759679 3671 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3672 if (c)
3673 {
3674 c = *++str;
3675 if (!c)
3676 as_bad (_("Missing operand"));
3677 }
3678
3679 /* Detect MRI REG symbols and convert them to REGLSTs. */
3680 if (opP->mode == CONTROL && (int)opP->reg < 0)
3681 {
3682 opP->mode = REGLST;
3683 opP->mask = ~(int)opP->reg;
3684 opP->reg = 0;
3685 }
3686
3687 return str;
3688}
3689
3690/* This is the guts of the machine-dependent assembler. STR points to a
3691 machine dependent instruction. This function is supposed to emit
3692 the frags/bytes it assembles to.
3693 */
3694
3695static void
31302357 3696insert_reg (const char *regname, int regnum)
252b5132
RH		 3697{
3698 char buf[100];
3699 int i;
3700
3701#ifdef REGISTER_PREFIX
3702 if (!flag_reg_prefix_optional)
3703 {
3704 buf[0] = REGISTER_PREFIX;
3705 strcpy (buf + 1, regname);
3706 regname = buf;
3707 }
3708#endif
3709
3710 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3711 &zero_address_frag));
3712
3713 for (i = 0; regname[i]; i++)
3882b010 3714 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3715 buf[i] = '\0';
3716
3717 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3718 &zero_address_frag));
3719}
3720
3721struct init_entry
3722 {
3723 const char *name;
3724 int number;
3725 };
3726
3727static const struct init_entry init_table[] =
3728{
3729 { "d0", DATA0 },
3730 { "d1", DATA1 },
3731 { "d2", DATA2 },
3732 { "d3", DATA3 },
3733 { "d4", DATA4 },
3734 { "d5", DATA5 },
3735 { "d6", DATA6 },
3736 { "d7", DATA7 },
3737 { "a0", ADDR0 },
3738 { "a1", ADDR1 },
3739 { "a2", ADDR2 },
3740 { "a3", ADDR3 },
3741 { "a4", ADDR4 },
3742 { "a5", ADDR5 },
3743 { "a6", ADDR6 },
3744 { "fp", ADDR6 },
3745 { "a7", ADDR7 },
3746 { "sp", ADDR7 },
3747 { "ssp", ADDR7 },
3748 { "fp0", FP0 },
3749 { "fp1", FP1 },
3750 { "fp2", FP2 },
3751 { "fp3", FP3 },
3752 { "fp4", FP4 },
3753 { "fp5", FP5 },
3754 { "fp6", FP6 },
3755 { "fp7", FP7 },
3756 { "fpi", FPI },
3757 { "fpiar", FPI },
3758 { "fpc", FPI },
3759 { "fps", FPS },
3760 { "fpsr", FPS },
3761 { "fpc", FPC },
3762 { "fpcr", FPC },
3763 { "control", FPC },
3764 { "status", FPS },
3765 { "iaddr", FPI },
3766
3767 { "cop0", COP0 },
3768 { "cop1", COP1 },
3769 { "cop2", COP2 },
3770 { "cop3", COP3 },
3771 { "cop4", COP4 },
3772 { "cop5", COP5 },
3773 { "cop6", COP6 },
3774 { "cop7", COP7 },
3775 { "pc", PC },
3776 { "zpc", ZPC },
3777 { "sr", SR },
3778
3779 { "ccr", CCR },
3780 { "cc", CCR },
3781
6da466c7 3782 { "acc", ACC },
fd99574b
NC		 3783 { "acc0", ACC },
3784 { "acc1", ACC1 },
3785 { "acc2", ACC2 },
3786 { "acc3", ACC3 },
3787 { "accext01", ACCEXT01 },
3788 { "accext23", ACCEXT23 },
6da466c7
ILT		 3789 { "macsr", MACSR },
3790 { "mask", MASK },
3791
36759679
NC		 3792 /* Control registers. */
3793 { "sfc", SFC }, /* Source Function Code. */
252b5132 3794 { "sfcr", SFC },
36759679 3795 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3796 { "dfcr", DFC },
36759679
NC		 3797 { "cacr", CACR }, /* Cache Control Register. */
3798 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3799
36759679
NC		 3800 { "usp", USP }, /* User Stack Pointer. */
3801 { "vbr", VBR }, /* Vector Base Register. */
3802 { "msp", MSP }, /* Master Stack Pointer. */
3803 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3804
36759679
NC		 3805 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3806 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3807 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3808 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3809
3810 /* 68ec040 versions of same */
36759679
NC		 3811 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3812 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3813 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3814 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 3815
a8e24a56 3816 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 3817 manual indicated that the order is 2,3,0,1, but Ken Rose
3818 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3819 { "acr0", ACR0 }, /* Access Control Unit 0. */
3820 { "acr1", ACR1 }, /* Access Control Unit 1. */
3821 { "acr2", ACR2 }, /* Access Control Unit 2. */
3822 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3823
36759679 3824 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 3825 { "tcr", TC },
a8e24a56 3826 { "asid", ASID },
252b5132 3827
36759679
NC		 3828 { "mmusr", MMUSR }, /* MMU Status Register. */
3829 { "srp", SRP }, /* User Root Pointer. */
3830 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3831
3832 { "buscr", BUSCR },
a8e24a56 3833 { "mmubar", MMUBAR },
252b5132
RH		 3834 { "pcr", PCR },
3835
36759679
NC		 3836 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3837 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3838 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3839 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3840
3841 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3842 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 3843 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 3844 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3845 { "mpcr", MPCR }, /* mcfv4e registers. */
3846 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3847 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3848 { "asid", TC }, /* mcfv4e registers. */
3849 { "mmubar", BUSCR }, /* mcfv4e registers. */
3850 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3851 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3852 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3853 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3854 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3855 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3856 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3857 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3858 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3859 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3860 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3861 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3862
3863 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3864 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3865
3866 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 3867
3868 { "cac", CAC }, /* fido registers. */
3869 { "mbb", MBB }, /* fido registers. */
36759679 3870 /* End of control registers. */
252b5132
RH		 3871
3872 { "ac", AC },
3873 { "bc", BC },
3874 { "cal", CAL },
3875 { "crp", CRP },
3876 { "drp", DRP },
3877 { "pcsr", PCSR },
3878 { "psr", PSR },
3879 { "scc", SCC },
3880 { "val", VAL },
3881 { "bad0", BAD0 },
3882 { "bad1", BAD1 },
3883 { "bad2", BAD2 },
3884 { "bad3", BAD3 },
3885 { "bad4", BAD4 },
3886 { "bad5", BAD5 },
3887 { "bad6", BAD6 },
3888 { "bad7", BAD7 },
3889 { "bac0", BAC0 },
3890 { "bac1", BAC1 },
3891 { "bac2", BAC2 },
3892 { "bac3", BAC3 },
3893 { "bac4", BAC4 },
3894 { "bac5", BAC5 },
3895 { "bac6", BAC6 },
3896 { "bac7", BAC7 },
3897
3898 { "ic", IC },
3899 { "dc", DC },
3900 { "nc", NC },
3901
3902 { "tt0", TT0 },
3903 { "tt1", TT1 },
36759679 3904 /* 68ec030 versions of same. */
252b5132
RH		 3905 { "ac0", TT0 },
3906 { "ac1", TT1 },
36759679 3907 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3908 { "acusr", PSR },
3909
3910 /* Suppressed data and address registers. */
3911 { "zd0", ZDATA0 },
3912 { "zd1", ZDATA1 },
3913 { "zd2", ZDATA2 },
3914 { "zd3", ZDATA3 },
3915 { "zd4", ZDATA4 },
3916 { "zd5", ZDATA5 },
3917 { "zd6", ZDATA6 },
3918 { "zd7", ZDATA7 },
3919 { "za0", ZADDR0 },
3920 { "za1", ZADDR1 },
3921 { "za2", ZADDR2 },
3922 { "za3", ZADDR3 },
3923 { "za4", ZADDR4 },
3924 { "za5", ZADDR5 },
3925 { "za6", ZADDR6 },
3926 { "za7", ZADDR7 },
3927
92774660 3928 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3929 { "d0l", DATA0L },
3930 { "d1l", DATA1L },
3931 { "d2l", DATA2L },
3932 { "d3l", DATA3L },
3933 { "d4l", DATA4L },
3934 { "d5l", DATA5L },
3935 { "d6l", DATA6L },
3936 { "d7l", DATA7L },
3937
3938 { "a0l", ADDR0L },
3939 { "a1l", ADDR1L },
3940 { "a2l", ADDR2L },
3941 { "a3l", ADDR3L },
3942 { "a4l", ADDR4L },
3943 { "a5l", ADDR5L },
3944 { "a6l", ADDR6L },
3945 { "a7l", ADDR7L },
3946
3947 { "d0u", DATA0U },
3948 { "d1u", DATA1U },
3949 { "d2u", DATA2U },
3950 { "d3u", DATA3U },
3951 { "d4u", DATA4U },
3952 { "d5u", DATA5U },
3953 { "d6u", DATA6U },
3954 { "d7u", DATA7U },
3955
3956 { "a0u", ADDR0U },
3957 { "a1u", ADDR1U },
3958 { "a2u", ADDR2U },
3959 { "a3u", ADDR3U },
3960 { "a4u", ADDR4U },
3961 { "a5u", ADDR5U },
3962 { "a6u", ADDR6U },
3963 { "a7u", ADDR7U },
3964
252b5132
RH		 3965 { 0, 0 }
3966};
3967
3968static void
31302357 3969init_regtable (void)
252b5132
RH		 3970{
3971 int i;
3972 for (i = 0; init_table[i].name; i++)
3973 insert_reg (init_table[i].name, init_table[i].number);
3974}
3975
252b5132 3976void
31302357 3977md_assemble (char *str)
252b5132
RH		 3978{
3979 const char *er;
3980 short *fromP;
3981 char *toP = NULL;
3982 int m, n = 0;
3983 char *to_beg_P;
3984 int shorts_this_frag;
3985 fixS *fixP;
3986
266abb8f
NS		 3987 if (!selected_cpu && !selected_arch)
3988 {
3989 /* We've not selected an architecture yet. Set the default
3990 now. We do this lazily so that an initial .cpu or .arch directive
3991 can specify. */
3992 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3993 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3994 }
3995 if (!initialized)
3996 m68k_init_arch ();
3997
252b5132
RH		 3998 /* In MRI mode, the instruction and operands are separated by a
3999 space. Anything following the operands is a comment. The label
4000 has already been removed. */
4001 if (flag_mri)
4002 {
4003 char *s;
4004 int fields = 0;
4005 int infield = 0;
4006 int inquote = 0;
4007
4008 for (s = str; *s != '\0'; s++)
4009 {
4010 if ((*s == ' ' || *s == '\t') && ! inquote)
4011 {
4012 if (infield)
4013 {
4014 ++fields;
4015 if (fields >= 2)
4016 {
4017 *s = '\0';
4018 break;
4019 }
4020 infield = 0;
4021 }
4022 }
4023 else
4024 {
4025 if (! infield)
4026 infield = 1;
4027 if (*s == '\'')
4028 inquote = ! inquote;
4029 }
4030 }
4031 }
4032
31302357 4033 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4034 m68k_ip (str);
4035 er = the_ins.error;
4036 if (!er)
4037 {
4038 for (n = 0; n < the_ins.numargs; n++)
4039 if (the_ins.operands[n].error)
4040 {
4041 er = the_ins.operands[n].error;
4042 break;
4043 }
4044 }
4045 if (er)
4046 {
4047 as_bad (_("%s -- statement `%s' ignored"), er, str);
4048 return;
4049 }
4050
4051 /* If there is a current label, record that it marks an instruction. */
4052 if (current_label != NULL)
4053 {
4054 current_label->text = 1;
4055 current_label = NULL;
4056 }
4057
f27a3839
AS		 4058#ifdef OBJ_ELF
4059 /* Tie dwarf2 debug info to the address at the start of the insn. */
4060 dwarf2_emit_insn (0);
4061#endif
4062
252b5132
RH		 4063 if (the_ins.nfrag == 0)
4064 {
36759679 4065 /* No frag hacking involved; just put it out. */
252b5132
RH		 4066 toP = frag_more (2 * the_ins.numo);
4067 fromP = &the_ins.opcode[0];
4068 for (m = the_ins.numo; m; --m)
4069 {
4070 md_number_to_chars (toP, (long) (*fromP), 2);
4071 toP += 2;
4072 fromP++;
4073 }
36759679 4074 /* Put out symbol-dependent info. */
252b5132
RH		 4075 for (m = 0; m < the_ins.nrel; m++)
4076 {
4077 switch (the_ins.reloc[m].wid)
4078 {
4079 case 'B':
4080 n = 1;
4081 break;
4082 case 'b':
4083 n = 1;
4084 break;
4085 case '3':
4086 n = 1;
4087 break;
4088 case 'w':
4089 case 'W':
4090 n = 2;
4091 break;
4092 case 'l':
4093 n = 4;
4094 break;
4095 default:
4096 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4097 the_ins.reloc[m].wid);
4098 }
4099
4100 fixP = fix_new_exp (frag_now,
4101 ((toP - frag_now->fr_literal)
4102 - the_ins.numo * 2 + the_ins.reloc[m].n),
4103 n,
4104 &the_ins.reloc[m].exp,
4105 the_ins.reloc[m].pcrel,
4106 get_reloc_code (n, the_ins.reloc[m].pcrel,
4107 the_ins.reloc[m].pic_reloc));
4108 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4109 if (the_ins.reloc[m].wid == 'B')
4110 fixP->fx_signed = 1;
4111 }
4112 return;
4113 }
4114
36759679 4115 /* There's some frag hacking. */
fbe572f9
AM		 4116 {
4117 /* Calculate the max frag size. */
4118 int wid;
4119
4120 wid = 2 * the_ins.fragb[0].fragoff;
4121 for (n = 1; n < the_ins.nfrag; n++)
4122 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4123 /* frag_var part. */
4124 wid += 10;
4125 /* Make sure the whole insn fits in one chunk, in particular that
4126 the var part is attached, as we access one byte before the
4127 variable frag for byte branches. */
4128 frag_grow (wid);
4129 }
4130
252b5132
RH		 4131 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4132 {
4133 int wid;
4134
4135 if (n == 0)
4136 wid = 2 * the_ins.fragb[n].fragoff;
4137 else
4138 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4139 toP = frag_more (wid);
4140 to_beg_P = toP;
4141 shorts_this_frag = 0;
4142 for (m = wid / 2; m; --m)
4143 {
4144 md_number_to_chars (toP, (long) (*fromP), 2);
4145 toP += 2;
4146 fromP++;
4147 shorts_this_frag++;
4148 }
4149 for (m = 0; m < the_ins.nrel; m++)
4150 {
4151 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4152 {
4153 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4154 break;
4155 }
4156 wid = the_ins.reloc[m].wid;
4157 if (wid == 0)
4158 continue;
4159 the_ins.reloc[m].wid = 0;
4160 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4161
4162 fixP = fix_new_exp (frag_now,
4163 ((toP - frag_now->fr_literal)
4164 - the_ins.numo * 2 + the_ins.reloc[m].n),
4165 wid,
4166 &the_ins.reloc[m].exp,
4167 the_ins.reloc[m].pcrel,
4168 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4169 the_ins.reloc[m].pic_reloc));
4170 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4171 }
4172 (void) frag_var (rs_machine_dependent, 10, 0,
4173 (relax_substateT) (the_ins.fragb[n].fragty),
4174 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4175 }
4176 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4177 shorts_this_frag = 0;
4178 if (n)
4179 {
055d1eb0 4180 toP = frag_more (n * 2);
252b5132
RH		 4181 while (n--)
4182 {
4183 md_number_to_chars (toP, (long) (*fromP), 2);
4184 toP += 2;
4185 fromP++;
4186 shorts_this_frag++;
4187 }
4188 }
4189 for (m = 0; m < the_ins.nrel; m++)
4190 {
4191 int wid;
4192
4193 wid = the_ins.reloc[m].wid;
4194 if (wid == 0)
4195 continue;
4196 the_ins.reloc[m].wid = 0;
4197 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4198
4199 fixP = fix_new_exp (frag_now,
4200 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4201 - shorts_this_frag * 2),
4202 wid,
4203 &the_ins.reloc[m].exp,
4204 the_ins.reloc[m].pcrel,
4205 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4206 the_ins.reloc[m].pic_reloc));
4207 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4208 }
4209}
4210
60fed2d3
NC		 4211/* Comparison function used by qsort to rank the opcode entries by name. */
4212
4213static int
4214m68k_compare_opcode (const void * v1, const void * v2)
4215{
4216 struct m68k_opcode * op1, * op2;
4217 int ret;
4218
03b13e59
NC		 4219 if (v1 == v2)
4220 return 0;
4221
60fed2d3
NC		 4222 op1 = *(struct m68k_opcode **) v1;
4223 op2 = *(struct m68k_opcode **) v2;
4224
4225 /* Compare the two names. If different, return the comparison.
4226 If the same, return the order they are in the opcode table. */
4227 ret = strcmp (op1->name, op2->name);
4228 if (ret)
4229 return ret;
4230 if (op1 < op2)
4231 return -1;
03b13e59 4232 return 1;
60fed2d3
NC		 4233}
4234
252b5132 4235void
60fed2d3 4236md_begin (void)
252b5132 4237{
60fed2d3
NC		 4238 const struct m68k_opcode *ins;
4239 struct m68k_incant *hack, *slak;
4240 const char *retval = 0; /* Empty string, or error msg text. */
4241 int i;
4242
4243 /* Set up hash tables with 68000 instructions.
4244 similar to what the vax assembler does. */
252b5132
RH		 4245 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4246 a copy of it at runtime, adding in the information we want but isn't
4247 there. I think it'd be better to have an awk script hack the table
4248 at compile time. Or even just xstr the table and use it as-is. But
4249 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4250 names. */
4251
252b5132
RH		 4252 if (flag_mri)
4253 {
4254 flag_reg_prefix_optional = 1;
4255 m68k_abspcadd = 1;
4256 if (! m68k_rel32_from_cmdline)
4257 m68k_rel32 = 0;
4258 }
4259
60fed2d3
NC		 4260 /* First sort the opcode table into alphabetical order to seperate
4261 the order that the assembler wants to see the opcodes from the
4262 order that the disassembler wants to see them. */
4263 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4264 if (!m68k_sorted_opcodes)
4265 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4266 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4267
4268 for (i = m68k_numopcodes; i--;)
4269 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4270
4271 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4272 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4273
252b5132
RH		 4274 op_hash = hash_new ();
4275
4276 obstack_begin (&robyn, 4000);
4277 for (i = 0; i < m68k_numopcodes; i++)
4278 {
4279 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4280 do
4281 {
60fed2d3
NC		 4282 ins = m68k_sorted_opcodes[i];
4283
4284 /* We *could* ignore insns that don't match our
4285 arch here by just leaving them out of the hash. */
252b5132
RH		 4286 slak->m_operands = ins->args;
4287 slak->m_opnum = strlen (slak->m_operands) / 2;
4288 slak->m_arch = ins->arch;
4289 slak->m_opcode = ins->opcode;
36759679 4290 /* This is kludgey. */
252b5132
RH		 4291 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4292 if (i + 1 != m68k_numopcodes
60fed2d3 4293 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4294 {
60fed2d3 4295 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4296 i++;
4297 }
4298 else
4299 slak->m_next = 0;
4300 slak = slak->m_next;
4301 }
4302 while (slak);
4303
4304 retval = hash_insert (op_hash, ins->name, (char *) hack);
4305 if (retval)
4306 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4307 }
4308
4309 for (i = 0; i < m68k_numaliases; i++)
4310 {
4311 const char *name = m68k_opcode_aliases[i].primary;
4312 const char *alias = m68k_opcode_aliases[i].alias;
4313 PTR val = hash_find (op_hash, name);
60fed2d3 4314
252b5132
RH		 4315 if (!val)
4316 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4317 retval = hash_insert (op_hash, alias, val);
4318 if (retval)
4319 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4320 }
4321
4322 /* In MRI mode, all unsized branches are variable sized. Normally,
4323 they are word sized. */
4324 if (flag_mri)
4325 {
4326 static struct m68k_opcode_alias mri_aliases[] =
4327 {
4328 { "bhi", "jhi", },
4329 { "bls", "jls", },
4330 { "bcc", "jcc", },
4331 { "bcs", "jcs", },
4332 { "bne", "jne", },
4333 { "beq", "jeq", },
4334 { "bvc", "jvc", },
4335 { "bvs", "jvs", },
4336 { "bpl", "jpl", },
4337 { "bmi", "jmi", },
4338 { "bge", "jge", },
4339 { "blt", "jlt", },
4340 { "bgt", "jgt", },
4341 { "ble", "jle", },
4342 { "bra", "jra", },
4343 { "bsr", "jbsr", },
4344 };
4345
8fce3f5e
AM		 4346 for (i = 0;
4347 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4348 i++)
252b5132
RH		 4349 {
4350 const char *name = mri_aliases[i].primary;
4351 const char *alias = mri_aliases[i].alias;
4352 PTR val = hash_find (op_hash, name);
60fed2d3 4353
252b5132
RH		 4354 if (!val)
4355 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4356 retval = hash_jam (op_hash, alias, val);
4357 if (retval)
4358 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4359 }
4360 }
4361
8fce3f5e 4362 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4363 {
4364 notend_table[i] = 0;
4365 alt_notend_table[i] = 0;
4366 }
60fed2d3 4367
252b5132
RH		 4368 notend_table[','] = 1;
4369 notend_table['{'] = 1;
4370 notend_table['}'] = 1;
4371 alt_notend_table['a'] = 1;
4372 alt_notend_table['A'] = 1;
4373 alt_notend_table['d'] = 1;
4374 alt_notend_table['D'] = 1;
4375 alt_notend_table['#'] = 1;
4376 alt_notend_table['&'] = 1;
4377 alt_notend_table['f'] = 1;
4378 alt_notend_table['F'] = 1;
4379#ifdef REGISTER_PREFIX
4380 alt_notend_table[REGISTER_PREFIX] = 1;
4381#endif
4382
4383 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4384 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4385 alt_notend_table['('] = 1;
4386
4387 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4388 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4389 alt_notend_table['@'] = 1;
4390
4391 /* We need to put digits in alt_notend_table to handle
60fed2d3 4392 bfextu %d0{24:1},%d0 */
252b5132
RH		 4393 alt_notend_table['0'] = 1;
4394 alt_notend_table['1'] = 1;
4395 alt_notend_table['2'] = 1;
4396 alt_notend_table['3'] = 1;
4397 alt_notend_table['4'] = 1;
4398 alt_notend_table['5'] = 1;
4399 alt_notend_table['6'] = 1;
4400 alt_notend_table['7'] = 1;
4401 alt_notend_table['8'] = 1;
4402 alt_notend_table['9'] = 1;
4403
4404#ifndef MIT_SYNTAX_ONLY
4405 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4406 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4407 {
4408 int n = 0;
60fed2d3 4409
252b5132
RH		 4410 while (mote_pseudo_table[n].poc_name)
4411 {
60fed2d3 4412 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4413 hash_insert (op_hash,
4414 mote_pseudo_table[n].poc_name, (char *) hack);
4415 hack->m_operands = 0;
4416 hack->m_opnum = n;
4417 n++;
4418 }
4419 }
4420#endif
4421
4422 init_regtable ();
4423
4424#ifdef OBJ_ELF
4425 record_alignment (text_section, 2);
4426 record_alignment (data_section, 2);
4427 record_alignment (bss_section, 2);
4428#endif
4429}
4430
252b5132
RH		 4431\f
4432/* This is called when a label is defined. */
4433
4434void
31302357 4435m68k_frob_label (symbolS *sym)
252b5132
RH		 4436{
4437 struct label_line *n;
4438
4439 n = (struct label_line *) xmalloc (sizeof *n);
4440 n->next = labels;
4441 n->label = sym;
4442 as_where (&n->file, &n->line);
4443 n->text = 0;
4444 labels = n;
4445 current_label = n;
07a53e5c
RH		 4446
4447#ifdef OBJ_ELF
4448 dwarf2_emit_label (sym);
4449#endif
252b5132
RH		 4450}
4451
4452/* This is called when a value that is not an instruction is emitted. */
4453
4454void
31302357 4455m68k_flush_pending_output (void)
252b5132
RH		 4456{
4457 current_label = NULL;
4458}
4459
4460/* This is called at the end of the assembly, when the final value of
4461 the label is known. We warn if this is a text symbol aligned at an
4462 odd location. */
4463
4464void
31302357 4465m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4466{
4467 if (S_GET_SEGMENT (sym) == reg_section
4468 && (int) S_GET_VALUE (sym) < 0)
4469 {
4470 S_SET_SEGMENT (sym, absolute_section);
4471 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4472 }
4473 else if ((S_GET_VALUE (sym) & 1) != 0)
4474 {
4475 struct label_line *l;
4476
4477 for (l = labels; l != NULL; l = l->next)
4478 {
4479 if (l->label == sym)
4480 {
4481 if (l->text)
4482 as_warn_where (l->file, l->line,
4483 _("text label `%s' aligned to odd boundary"),
4484 S_GET_NAME (sym));
4485 break;
4486 }
4487 }
4488 }
4489}
4490\f
4491/* This is called if we go in or out of MRI mode because of the .mri
4492 pseudo-op. */
4493
4494void
31302357 4495m68k_mri_mode_change (int on)
252b5132
RH		 4496{
4497 if (on)
4498 {
4499 if (! flag_reg_prefix_optional)
4500 {
4501 flag_reg_prefix_optional = 1;
4502#ifdef REGISTER_PREFIX
4503 init_regtable ();
4504#endif
4505 }
4506 m68k_abspcadd = 1;
4507 if (! m68k_rel32_from_cmdline)
4508 m68k_rel32 = 0;
4509 }
4510 else
4511 {
4512 if (! reg_prefix_optional_seen)
4513 {
4514#ifdef REGISTER_PREFIX_OPTIONAL
4515 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4516#else
4517 flag_reg_prefix_optional = 0;
4518#endif
4519#ifdef REGISTER_PREFIX
4520 init_regtable ();
4521#endif
4522 }
4523 m68k_abspcadd = 0;
4524 if (! m68k_rel32_from_cmdline)
4525 m68k_rel32 = 1;
4526 }
4527}
4528
36759679 4529/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4530#define MAX_LITTLENUMS 6
4531
4532/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4533 of type TYPE, and store the appropriate bytes in *LITP. The number
4534 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4535 returned, or NULL on OK. */
4536
4537char *
31302357 4538md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4539{
4540 int prec;
4541 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4542 LITTLENUM_TYPE *wordP;
4543 char *t;
4544
4545 switch (type)
4546 {
4547 case 'f':
4548 case 'F':
4549 case 's':
4550 case 'S':
4551 prec = 2;
4552 break;
4553
4554 case 'd':
4555 case 'D':
4556 case 'r':
4557 case 'R':
4558 prec = 4;
4559 break;
4560
4561 case 'x':
4562 case 'X':
4563 prec = 6;
4564 break;
4565
4566 case 'p':
4567 case 'P':
4568 prec = 6;
4569 break;
4570
4571 default:
4572 *sizeP = 0;
4573 return _("Bad call to MD_ATOF()");
4574 }
4575 t = atof_ieee (input_line_pointer, type, words);
4576 if (t)
4577 input_line_pointer = t;
4578
4579 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4580 for (wordP = words; prec--;)
4581 {
4582 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4583 litP += sizeof (LITTLENUM_TYPE);
4584 }
4585 return 0;
4586}
4587
4588void
31302357 4589md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4590{
4591 number_to_chars_bigendian (buf, val, n);
4592}
4593
94f592af 4594void
55cf6793 4595md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4596{
bbe8ef22 4597 offsetT val = *valP;
252b5132
RH		 4598 addressT upper_limit;
4599 offsetT lower_limit;
4600
4601 /* This is unnecessary but it convinces the native rs6000 compiler
4602 to generate the code we want. */
4603 char *buf = fixP->fx_frag->fr_literal;
4604 buf += fixP->fx_where;
36759679 4605 /* End ibm compiler workaround. */
252b5132 4606
bd17c2c3 4607 val = SEXT (val);
252b5132 4608
94f592af
NC		 4609 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4610 fixP->fx_done = 1;
4611
252b5132
RH		 4612#ifdef OBJ_ELF
4613 if (fixP->fx_addsy)
4614 {
4615 memset (buf, 0, fixP->fx_size);
36759679 4616 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4617
4618 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4619 && !S_IS_DEFINED (fixP->fx_addsy)
4620 && !S_IS_WEAK (fixP->fx_addsy))
4621 S_SET_WEAK (fixP->fx_addsy);
4622 return;
4623 }
4624#endif
4625
252b5132
RH		 4626 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4628 return;
252b5132
RH		 4629
4630 switch (fixP->fx_size)
4631 {
94f592af
NC		 4632 /* The cast to offsetT below are necessary to make code
4633 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4634 case 1:
4635 *buf++ = val;
4636 upper_limit = 0x7f;
4637 lower_limit = - (offsetT) 0x80;
4638 break;
4639 case 2:
4640 *buf++ = (val >> 8);
4641 *buf++ = val;
4642 upper_limit = 0x7fff;
4643 lower_limit = - (offsetT) 0x8000;
4644 break;
4645 case 4:
4646 *buf++ = (val >> 24);
4647 *buf++ = (val >> 16);
4648 *buf++ = (val >> 8);
4649 *buf++ = val;
4650 upper_limit = 0x7fffffff;
36759679 4651 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4652 break;
4653 default:
4654 BAD_CASE (fixP->fx_size);
4655 }
4656
4657 /* Fix up a negative reloc. */
4658 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4659 {
4660 fixP->fx_addsy = fixP->fx_subsy;
4661 fixP->fx_subsy = NULL;
4662 fixP->fx_tcbit = 1;
4663 }
4664
4665 /* For non-pc-relative values, it's conceivable we might get something
4666 like "0xff" for a byte field. So extend the upper part of the range
4667 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4668 so that we can do any range checking at all. */
4669 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4670 upper_limit = upper_limit * 2 + 1;
4671
4672 if ((addressT) val > upper_limit
4673 && (val > 0 || val < lower_limit))
4674 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4675
4676 /* A one byte PC-relative reloc means a short branch. We can't use
4677 a short branch with a value of 0 or -1, because those indicate
4678 different opcodes (branches with longer offsets). fixup_segment
4679 in write.c may have clobbered fx_pcrel, so we need to examine the
4680 reloc type. */
4681 if ((fixP->fx_pcrel
7be1c489 4682 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4683 && fixP->fx_size == 1
4684 && (fixP->fx_addsy == NULL
4685 || S_IS_DEFINED (fixP->fx_addsy))
4686 && (val == 0 || val == -1))
4687 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4688}
4689
252b5132
RH		 4690/* *fragP has been relaxed to its final size, and now needs to have
4691 the bytes inside it modified to conform to the new size There is UGLY
4692 MAGIC here. ..
4693 */
4694static void
31302357 4695md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4696{
4697 long disp;
252b5132
RH		 4698 fixS *fixP;
4699
4700 /* Address in object code of the displacement. */
4701 register int object_address = fragP->fr_fix + fragP->fr_address;
4702
4703 /* Address in gas core of the place to store the displacement. */
4704 /* This convinces the native rs6000 compiler to generate the code we
92774660 4705 want. */
252b5132
RH		 4706 register char *buffer_address = fragP->fr_literal;
4707 buffer_address += fragP->fr_fix;
36759679 4708 /* End ibm compiler workaround. */
252b5132
RH		 4709
4710 /* The displacement of the address, from current location. */
4711 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4712 disp = (disp + fragP->fr_offset) - object_address;
4713
252b5132
RH		 4714 switch (fragP->fr_subtype)
4715 {
151337e8
NC		 4716 case TAB (BRANCHBWL, BYTE):
4717 case TAB (BRABSJUNC, BYTE):
4718 case TAB (BRABSJCOND, BYTE):
4719 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4720 know (issbyte (disp));
4721 if (disp == 0)
b091f402
AM		 4722 as_bad_where (fragP->fr_file, fragP->fr_line,
4723 _("short branch with zero offset: use :w"));
151337e8 4724 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4725 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4726 fixP->fx_pcrel_adjust = -1;
252b5132 4727 break;
151337e8
NC		 4728 case TAB (BRANCHBWL, SHORT):
4729 case TAB (BRABSJUNC, SHORT):
4730 case TAB (BRABSJCOND, SHORT):
4731 case TAB (BRANCHBW, SHORT):
252b5132 4732 fragP->fr_opcode[1] = 0x00;
151337e8 4733 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4734 1, RELAX_RELOC_PC16);
151337e8
NC		 4735 fragP->fr_fix += 2;
4736 break;
4737 case TAB (BRANCHBWL, LONG):
4738 fragP->fr_opcode[1] = (char) 0xFF;
4739 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4740 1, RELAX_RELOC_PC32);
151337e8 4741 fragP->fr_fix += 4;
252b5132 4742 break;
151337e8
NC		 4743 case TAB (BRABSJUNC, LONG):
4744 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4745 {
36759679 4746 if (flag_keep_pcrel)
6b6e92f4 4747 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4748 fragP->fr_opcode[0] = 0x4E;
36759679 4749 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4750 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4751 0, RELAX_RELOC_ABS32);
151337e8
NC		 4752 fragP->fr_fix += 4;
4753 }
4754 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4755 {
36759679 4756 if (flag_keep_pcrel)
6b6e92f4 4757 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4758 fragP->fr_opcode[0] = 0x4E;
36759679 4759 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4760 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4761 0, RELAX_RELOC_ABS32);
151337e8 4762 fragP->fr_fix += 4;
252b5132
RH		 4763 }
4764 else
4765 {
151337e8
NC		 4766 /* This cannot happen, because jbsr and jbra are the only two
4767 unconditional branches. */
4768 abort ();
252b5132
RH		 4769 }
4770 break;
151337e8 4771 case TAB (BRABSJCOND, LONG):
36759679 4772 if (flag_keep_pcrel)
6b6e92f4 4773 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4774
36759679
NC		 4775 /* Only Bcc 68000 instructions can come here
4776 Change bcc into b!cc/jmp absl long. */
4777 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4778 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4779
4780 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4781 different frag, in which case referring to them is a no-no.
92774660 4782 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4783 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4784 *buffer_address++ = (char) 0xf9;
36759679 4785 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4786 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4787 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4788 fragP->fr_fix += 4;
4789 break;
4790 case TAB (FBRANCH, SHORT):
4791 know ((fragP->fr_opcode[1] & 0x40) == 0);
4792 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4793 1, RELAX_RELOC_PC16);
151337e8
NC		 4794 fragP->fr_fix += 2;
4795 break;
4796 case TAB (FBRANCH, LONG):
36759679 4797 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4798 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4799 1, RELAX_RELOC_PC32);
252b5132 4800 fragP->fr_fix += 4;
252b5132 4801 break;
151337e8
NC		 4802 case TAB (DBCCLBR, SHORT):
4803 case TAB (DBCCABSJ, SHORT):
4804 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4805 1, RELAX_RELOC_PC16);
151337e8
NC		 4806 fragP->fr_fix += 2;
4807 break;
4808 case TAB (DBCCLBR, LONG):
36759679
NC		 4809 /* Only DBcc instructions can come here.
4810 Change dbcc into dbcc/bral.
4811 JF: these used to be fr_opcode[2-7], but that's wrong. */
4812 if (flag_keep_pcrel)
6b6e92f4 4813 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4814
36759679 4815 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4816 *buffer_address++ = 0x04;
36759679 4817 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4818 *buffer_address++ = 0x06;
151337e8
NC		 4819 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4820 *buffer_address++ = (char) 0xff;
252b5132 4821
36759679 4822 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4823 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4824 RELAX_RELOC_PC32);
252b5132 4825 fragP->fr_fix += 4;
252b5132 4826 break;
151337e8 4827 case TAB (DBCCABSJ, LONG):
36759679
NC		 4828 /* Only DBcc instructions can come here.
4829 Change dbcc into dbcc/jmp.
4830 JF: these used to be fr_opcode[2-7], but that's wrong. */
4831 if (flag_keep_pcrel)
6b6e92f4 4832 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4833
36759679 4834 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4835 *buffer_address++ = 0x04;
36759679 4836 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4837 *buffer_address++ = 0x06;
36759679 4838 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4839 *buffer_address++ = (char) 0xf9;
4840
36759679 4841 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4842 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4843 RELAX_RELOC_ABS32);
252b5132 4844 fragP->fr_fix += 4;
252b5132 4845 break;
151337e8 4846 case TAB (PCREL1632, SHORT):
252b5132
RH		 4847 fragP->fr_opcode[1] &= ~0x3F;
4848 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4849 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4850 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4851 fragP->fr_fix += 2;
252b5132 4852 break;
151337e8 4853 case TAB (PCREL1632, LONG):
252b5132
RH		 4854 /* Already set to mode 7.3; this indicates: PC indirect with
4855 suppressed index, 32-bit displacement. */
4856 *buffer_address++ = 0x01;
4857 *buffer_address++ = 0x70;
4858 fragP->fr_fix += 2;
151337e8 4859 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4860 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4861 fixP->fx_pcrel_adjust = 2;
4862 fragP->fr_fix += 4;
252b5132 4863 break;
252b5132 4864 case TAB (PCINDEX, BYTE):
252b5132
RH		 4865 assert (fragP->fr_fix >= 2);
4866 buffer_address[-2] &= ~1;
151337e8 4867 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4868 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4869 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4870 break;
4871 case TAB (PCINDEX, SHORT):
252b5132
RH		 4872 assert (fragP->fr_fix >= 2);
4873 buffer_address[-2] |= 0x1;
4874 buffer_address[-1] = 0x20;
4875 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4876 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4877 fixP->fx_pcrel_adjust = 2;
151337e8 4878 fragP->fr_fix += 2;
252b5132
RH		 4879 break;
4880 case TAB (PCINDEX, LONG):
252b5132
RH		 4881 assert (fragP->fr_fix >= 2);
4882 buffer_address[-2] |= 0x1;
4883 buffer_address[-1] = 0x30;
151337e8 4884 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4885 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4886 fixP->fx_pcrel_adjust = 2;
4887 fragP->fr_fix += 4;
4888 break;
4889 case TAB (ABSTOPCREL, SHORT):
4890 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4891 1, RELAX_RELOC_PC16);
151337e8
NC		 4892 fragP->fr_fix += 2;
4893 break;
4894 case TAB (ABSTOPCREL, LONG):
36759679 4895 if (flag_keep_pcrel)
6b6e92f4 4896 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4897 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4898 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4899 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4900 abort ();
4901 fragP->fr_opcode[1] &= ~0x3F;
4902 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4903 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4904 0, RELAX_RELOC_ABS32);
151337e8 4905 fragP->fr_fix += 4;
252b5132 4906 break;
252b5132
RH		 4907 }
4908}
4909
252b5132 4910void
31302357
AS		 4911md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4912 segT sec ATTRIBUTE_UNUSED,
4913 fragS *fragP)
252b5132
RH		 4914{
4915 md_convert_frag_1 (fragP);
4916}
252b5132
RH		 4917
4918/* Force truly undefined symbols to their maximum size, and generally set up
4919 the frag list to be relaxed
4920 */
4921int
31302357 4922md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4923{
151337e8 4924 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4925 switch (fragP->fr_subtype)
4926 {
151337e8
NC		 4927 case TAB (BRANCHBWL, SZ_UNDEF):
4928 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4929 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4930 {
151337e8
NC		 4931 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4932 && relaxable_symbol (fragP->fr_symbol))
252b5132 4933 {
151337e8
NC		 4934 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4935 }
4936 else if (flag_short_refs)
4937 {
4938 /* Symbol is undefined and we want short ref. */
4939 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4940 }
4941 else
4942 {
151337e8
NC		 4943 /* Symbol is still undefined. Make it LONG. */
4944 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4945 }
4946 break;
151337e8 4947 }
252b5132 4948
151337e8 4949 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4950 {
151337e8
NC		 4951 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4952 && relaxable_symbol (fragP->fr_symbol))
252b5132 4953 {
151337e8 4954 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4955 }
4956 else
4957 {
151337e8
NC		 4958 /* Symbol is undefined and we don't have long branches. */
4959 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4960 }
4961 break;
151337e8 4962 }
252b5132 4963
151337e8 4964 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4965 case TAB (DBCCLBR, SZ_UNDEF):
4966 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4967 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4968 {
8ec6253e
NC		 4969 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4970 && relaxable_symbol (fragP->fr_symbol))
151337e8 4971 || flag_short_refs)
252b5132 4972 {
151337e8 4973 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4974 }
4975 else
4976 {
151337e8 4977 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4978 }
4979 break;
151337e8 4980 }
81d4177b 4981
252b5132
RH		 4982 case TAB (PCINDEX, SZ_UNDEF):
4983 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4984 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4985 {
4986 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4987 }
4988 else
4989 {
4990 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4991 }
4992 break;
4993
151337e8
NC		 4994 case TAB (ABSTOPCREL, SZ_UNDEF):
4995 {
4996 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4997 && relaxable_symbol (fragP->fr_symbol)))
4998 {
4999 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5000 }
5001 else
5002 {
5003 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5004 }
5005 break;
5006 }
5007
252b5132
RH		 5008 default:
5009 break;
5010 }
5011
151337e8 5012 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5013 switch (fragP->fr_subtype)
5014 {
151337e8
NC		 5015 case TAB (BRANCHBWL, BYTE):
5016 case TAB (BRABSJUNC, BYTE):
5017 case TAB (BRABSJCOND, BYTE):
5018 case TAB (BRANCHBW, BYTE):
252b5132 5019 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5020 case we force word mode. If the symbol is at the start of a
5021 frag, and it is the next frag with any data in it (usually
5022 this is just the next frag, but assembler listings may
5023 introduce empty frags), we must use word mode. */
5024 if (fragP->fr_symbol)
252b5132 5025 {
ac62c346 5026 fragS *sym_frag;
252b5132 5027
ac62c346
AM		 5028 sym_frag = symbol_get_frag (fragP->fr_symbol);
5029 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5030 {
ac62c346
AM		 5031 fragS *l;
5032
23b7f870 5033 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5034 if (l->fr_fix != 0)
5035 break;
5036 if (l == sym_frag)
5037 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5038 }
5039 }
5040 break;
5041 default:
5042 break;
5043 }
ac62c346 5044 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5045}
5046
5047#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5048/* the bit-field entries in the relocation_info struct plays hell
5049 with the byte-order problems of cross-assembly. So as a hack,
5050 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5051 you there. -KWK */
252b5132
RH		 5052/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5053 are symbolnum, most sig. byte first. Last byte is broken up with
5054 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5055 nibble as nuthin. (on Sun 3 at least) */
5056/* Translate the internal relocation information into target-specific
92774660 5057 format. */
252b5132
RH		 5058#ifdef comment
5059void
31302357 5060md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5061{
36759679 5062 /* This is easy. */
252b5132 5063 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5064 /* Now the fun stuff. */
252b5132 5065 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5066 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5067 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5068 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5069 | ((ri->r_length << 5) & 0x60)
5070 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5071}
5072
36759679 5073#endif
252b5132 5074
252b5132
RH		 5075#endif /* OBJ_AOUT or OBJ_BOUT */
5076
5077#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5078int md_short_jump_size = 4;
5079int md_long_jump_size = 6;
252b5132
RH		 5080
5081void
31302357
AS		 5082md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5083 fragS *frag ATTRIBUTE_UNUSED,
5084 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5085{
5086 valueT offset;
5087
5088 offset = to_addr - (from_addr + 2);
5089
5090 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5091 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5092}
5093
5094void
31302357
AS		 5095md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5096 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5097{
5098 valueT offset;
5099
6b6e92f4 5100 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5101 {
36759679 5102 if (flag_keep_pcrel)
6b6e92f4 5103 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5104 offset = to_addr - S_GET_VALUE (to_symbol);
5105 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5106 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5107 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5108 0, NO_RELOC);
5109 }
5110 else
5111 {
5112 offset = to_addr - (from_addr + 2);
5113 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5114 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5115 }
5116}
5117
5118#endif
5119
5120/* Different values of OK tell what its OK to return. Things that
5121 aren't OK are an error (what a shock, no?)
5122
5123 0: Everything is OK
3e602632
NC		 5124 10: Absolute 1:8 only
5125 20: Absolute 0:7 only
5126 30: absolute 0:15 only
5127 40: Absolute 0:31 only
5128 50: absolute 0:127 only
252b5132 5129 55: absolute -64:63 only
3e602632
NC		 5130 60: absolute -128:127 only
5131 70: absolute 0:4095 only
5132 80: absolute -1, 1:7 only
5133 90: No bignums. */
252b5132
RH		 5134
5135static int
31302357 5136get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5137{
5138 if (exp->exp.X_op == O_absent)
5139 {
36759679 5140 /* Do the same thing the VAX asm does. */
252b5132
RH		 5141 op (exp) = O_constant;
5142 adds (exp) = 0;
5143 subs (exp) = 0;
5144 offs (exp) = 0;
5145 if (ok == 10)
5146 {
5147 as_warn (_("expression out of range: defaulting to 1"));
5148 offs (exp) = 1;
5149 }
5150 }
5151 else if (exp->exp.X_op == O_constant)
5152 {
5153 switch (ok)
5154 {
5155 case 10:
bd17c2c3 5156 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5157 {
5158 as_warn (_("expression out of range: defaulting to 1"));
5159 offs (exp) = 1;
5160 }
5161 break;
5162 case 20:
bd17c2c3 5163 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5164 goto outrange;
5165 break;
5166 case 30:
bd17c2c3 5167 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5168 goto outrange;
5169 break;
5170 case 40:
bd17c2c3 5171 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5172 goto outrange;
5173 break;
5174 case 50:
bd17c2c3 5175 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5176 goto outrange;
5177 break;
5178 case 55:
bd17c2c3 5179 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5180 goto outrange;
5181 break;
5182 case 60:
bd17c2c3 5183 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5184 goto outrange;
5185 break;
5186 case 70:
bd17c2c3 5187 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5188 {
5189 outrange:
5190 as_warn (_("expression out of range: defaulting to 0"));
5191 offs (exp) = 0;
5192 }
5193 break;
3e602632 5194 case 80:
bd17c2c3
AM		 5195 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5196 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5197 {
5198 as_warn (_("expression out of range: defaulting to 1"));
5199 offs (exp) = 1;
5200 }
5201 break;
252b5132
RH		 5202 default:
5203 break;
5204 }
5205 }
5206 else if (exp->exp.X_op == O_big)
5207 {
36759679 5208 if (offs (exp) <= 0 /* flonum. */
3e602632 5209 && (ok == 90 /* no bignums */
36759679 5210 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5211 /* If we have a flonum zero, a zero integer should
5212 do as well (e.g., in moveq). */
5213 && generic_floating_point_number.exponent == 0
5214 && generic_floating_point_number.low[0] == 0)))
5215 {
36759679 5216 /* HACK! Turn it into a long. */
252b5132
RH		 5217 LITTLENUM_TYPE words[6];
5218
36759679 5219 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5220 op (exp) = O_constant;
5221 adds (exp) = 0;
5222 subs (exp) = 0;
5223 offs (exp) = words[1] | (words[0] << 16);
5224 }
5225 else if (ok != 0)
5226 {
5227 op (exp) = O_constant;
5228 adds (exp) = 0;
5229 subs (exp) = 0;
5230 offs (exp) = (ok == 10) ? 1 : 0;
5231 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5232 (long) offs (exp));
252b5132
RH		 5233 }
5234 }
5235 else
5236 {
3e602632 5237 if (ok >= 10 && ok <= 80)
252b5132
RH		 5238 {
5239 op (exp) = O_constant;
5240 adds (exp) = 0;
5241 subs (exp) = 0;
5242 offs (exp) = (ok == 10) ? 1 : 0;
5243 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5244 (long) offs (exp));
252b5132
RH		 5245 }
5246 }
5247
5248 if (exp->size != SIZE_UNSPEC)
5249 {
5250 switch (exp->size)
5251 {
5252 case SIZE_UNSPEC:
5253 case SIZE_LONG:
5254 break;
5255 case SIZE_BYTE:
5256 if (!isbyte (offs (exp)))
5257 as_warn (_("expression doesn't fit in BYTE"));
5258 break;
5259 case SIZE_WORD:
5260 if (!isword (offs (exp)))
5261 as_warn (_("expression doesn't fit in WORD"));
5262 break;
5263 }
5264 }
5265
5266 return offs (exp);
5267}
5268
5269/* These are the back-ends for the various machine dependent pseudo-ops. */
5270
5271static void
31302357 5272s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5273{
5274 subseg_set (data_section, 1);
5275 demand_empty_rest_of_line ();
5276}
5277
5278static void
31302357 5279s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5280{
5281 subseg_set (data_section, 2);
5282 demand_empty_rest_of_line ();
5283}
5284
5285static void
31302357 5286s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5287{
5288 /* We don't support putting frags in the BSS segment, we fake it
5289 by marking in_bss, then looking at s_skip for clues. */
5290
5291 subseg_set (bss_section, 0);
5292 demand_empty_rest_of_line ();
5293}
5294
5295static void
31302357 5296s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5297{
5298 register int temp;
5299 register long temp_fill;
5300
5301 temp = 1; /* JF should be 2? */
5302 temp_fill = get_absolute_expression ();
92774660 5303 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5304 frag_align (temp, (int) temp_fill, 0);
5305 demand_empty_rest_of_line ();
5306 record_alignment (now_seg, temp);
5307}
5308
5309static void
31302357 5310s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5311{
5312 demand_empty_rest_of_line ();
5313}
5314\f
5315/* Pseudo-ops handled for MRI compatibility. */
5316
5317/* This function returns non-zero if the argument is a conditional
5318 pseudo-op. This is called when checking whether a pending
5319 alignment is needed. */
5320
5321int
31302357 5322m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5323{
5324 return (pop->poc_handler == s_mri_if
5325 || pop->poc_handler == s_mri_else);
5326}
5327
5328/* Handle an MRI style chip specification. */
5329
5330static void
31302357 5331mri_chip (void)
252b5132
RH		 5332{
5333 char *s;
5334 char c;
5335 int i;
5336
5337 s = input_line_pointer;
5338 /* We can't use get_symbol_end since the processor names are not proper
5339 symbols. */
5340 while (is_part_of_name (c = *input_line_pointer++))
5341 ;
5342 *--input_line_pointer = 0;
266abb8f
NS		 5343 for (i = 0; m68k_cpus[i].name; i++)
5344 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5345 break;
266abb8f 5346 if (!m68k_cpus[i].name)
252b5132
RH		 5347 {
5348 as_bad (_("%s: unrecognized processor name"), s);
5349 *input_line_pointer = c;
5350 ignore_rest_of_line ();
5351 return;
5352 }
5353 *input_line_pointer = c;
5354
5355 if (*input_line_pointer == '/')
5356 current_architecture = 0;
5357 else
5358 current_architecture &= m68881 | m68851;
266abb8f 5359 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5360 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5361
5362 while (*input_line_pointer == '/')
5363 {
5364 ++input_line_pointer;
5365 s = input_line_pointer;
5366 /* We can't use get_symbol_end since the processor names are not
5367 proper symbols. */
5368 while (is_part_of_name (c = *input_line_pointer++))
5369 ;
5370 *--input_line_pointer = 0;
5371 if (strcmp (s, "68881") == 0)
5372 current_architecture |= m68881;
5373 else if (strcmp (s, "68851") == 0)
5374 current_architecture |= m68851;
5375 *input_line_pointer = c;
5376 }
252b5132
RH		 5377}
5378
5379/* The MRI CHIP pseudo-op. */
5380
5381static void
31302357 5382s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5383{
5384 char *stop = NULL;
5385 char stopc;
5386
5387 if (flag_mri)
5388 stop = mri_comment_field (&stopc);
5389 mri_chip ();
5390 if (flag_mri)
5391 mri_comment_end (stop, stopc);
5392 demand_empty_rest_of_line ();
5393}
5394
5395/* The MRI FOPT pseudo-op. */
5396
5397static void
31302357 5398s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5399{
5400 SKIP_WHITESPACE ();
5401
5402 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5403 {
5404 int temp;
5405
5406 input_line_pointer += 3;
5407 temp = get_absolute_expression ();
5408 if (temp < 0 || temp > 7)
5409 as_bad (_("bad coprocessor id"));
5410 else
5411 m68k_float_copnum = COP0 + temp;
5412 }
5413 else
5414 {
5415 as_bad (_("unrecognized fopt option"));
5416 ignore_rest_of_line ();
5417 return;
5418 }
5419
5420 demand_empty_rest_of_line ();
5421}
5422
5423/* The structure used to handle the MRI OPT pseudo-op. */
5424
5425struct opt_action
5426{
5427 /* The name of the option. */
5428 const char *name;
5429
5430 /* If this is not NULL, just call this function. The first argument
5431 is the ARG field of this structure, the second argument is
5432 whether the option was negated. */
31302357 5433 void (*pfn) (int arg, int on);
252b5132
RH		 5434
5435 /* If this is not NULL, and the PFN field is NULL, set the variable
5436 this points to. Set it to the ARG field if the option was not
5437 negated, and the NOTARG field otherwise. */
5438 int *pvar;
5439
5440 /* The value to pass to PFN or to assign to *PVAR. */
5441 int arg;
5442
5443 /* The value to assign to *PVAR if the option is negated. If PFN is
5444 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5445 the option may not be negated. */
5446 int notarg;
5447};
5448
5449/* The table used to handle the MRI OPT pseudo-op. */
5450
31302357
AS		 5451static void skip_to_comma (int, int);
5452static void opt_nest (int, int);
5453static void opt_chip (int, int);
5454static void opt_list (int, int);
5455static void opt_list_symbols (int, int);
252b5132
RH		 5456
5457static const struct opt_action opt_table[] =
5458{
5459 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5460
5461 /* We do relaxing, so there is little use for these options. */
5462 { "b", 0, 0, 0, 0 },
5463 { "brs", 0, 0, 0, 0 },
5464 { "brb", 0, 0, 0, 0 },
5465 { "brl", 0, 0, 0, 0 },
5466 { "brw", 0, 0, 0, 0 },
5467
5468 { "c", 0, 0, 0, 0 },
5469 { "cex", 0, 0, 0, 0 },
5470 { "case", 0, &symbols_case_sensitive, 1, 0 },
5471 { "cl", 0, 0, 0, 0 },
5472 { "cre", 0, 0, 0, 0 },
5473 { "d", 0, &flag_keep_locals, 1, 0 },
5474 { "e", 0, 0, 0, 0 },
5475 { "f", 0, &flag_short_refs, 1, 0 },
5476 { "frs", 0, &flag_short_refs, 1, 0 },
5477 { "frl", 0, &flag_short_refs, 0, 1 },
5478 { "g", 0, 0, 0, 0 },
5479 { "i", 0, 0, 0, 0 },
5480 { "m", 0, 0, 0, 0 },
5481 { "mex", 0, 0, 0, 0 },
5482 { "mc", 0, 0, 0, 0 },
5483 { "md", 0, 0, 0, 0 },
5484 { "nest", opt_nest, 0, 0, 0 },
5485 { "next", skip_to_comma, 0, 0, 0 },
5486 { "o", 0, 0, 0, 0 },
5487 { "old", 0, 0, 0, 0 },
5488 { "op", skip_to_comma, 0, 0, 0 },
5489 { "pco", 0, 0, 0, 0 },
5490 { "p", opt_chip, 0, 0, 0 },
5491 { "pcr", 0, 0, 0, 0 },
5492 { "pcs", 0, 0, 0, 0 },
5493 { "r", 0, 0, 0, 0 },
5494 { "quick", 0, &m68k_quick, 1, 0 },
5495 { "rel32", 0, &m68k_rel32, 1, 0 },
5496 { "s", opt_list, 0, 0, 0 },
5497 { "t", opt_list_symbols, 0, 0, 0 },
5498 { "w", 0, &flag_no_warnings, 0, 1 },
5499 { "x", 0, 0, 0, 0 }
5500};
5501
8fce3f5e 5502#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5503
5504/* The MRI OPT pseudo-op. */
5505
5506static void
31302357 5507s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5508{
5509 do
5510 {
5511 int t;
5512 char *s;
5513 char c;
5514 int i;
5515 const struct opt_action *o;
5516
5517 SKIP_WHITESPACE ();
5518
5519 t = 1;
5520 if (*input_line_pointer == '-')
5521 {
5522 ++input_line_pointer;
5523 t = 0;
5524 }
5525 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5526 {
5527 input_line_pointer += 2;
5528 t = 0;
5529 }
5530
5531 s = input_line_pointer;
5532 c = get_symbol_end ();
5533
5534 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5535 {
5536 if (strcasecmp (s, o->name) == 0)
5537 {
5538 if (o->pfn)
5539 {
5540 /* Restore input_line_pointer now in case the option
5541 takes arguments. */
5542 *input_line_pointer = c;
5543 (*o->pfn) (o->arg, t);
5544 }
5545 else if (o->pvar != NULL)
5546 {
5547 if (! t && o->arg == o->notarg)
5548 as_bad (_("option `%s' may not be negated"), s);
5549 *input_line_pointer = c;
5550 *o->pvar = t ? o->arg : o->notarg;
5551 }
5552 else
5553 *input_line_pointer = c;
5554 break;
5555 }
5556 }
5557 if (i >= OPTCOUNT)
5558 {
5559 as_bad (_("option `%s' not recognized"), s);
5560 *input_line_pointer = c;
5561 }
5562 }
5563 while (*input_line_pointer++ == ',');
5564
5565 /* Move back to terminating character. */
5566 --input_line_pointer;
5567 demand_empty_rest_of_line ();
5568}
5569
5570/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5571 not support and which take arguments. */
252b5132
RH		 5572
5573static void
31302357 5574skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5575{
5576 while (*input_line_pointer != ','
5577 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5578 ++input_line_pointer;
5579}
5580
5581/* Handle the OPT NEST=depth option. */
5582
5583static void
31302357 5584opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5585{
5586 if (*input_line_pointer != '=')
5587 {
5588 as_bad (_("bad format of OPT NEST=depth"));
5589 return;
5590 }
5591
5592 ++input_line_pointer;
5593 max_macro_nest = get_absolute_expression ();
5594}
5595
5596/* Handle the OPT P=chip option. */
5597
5598static void
31302357 5599opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5600{
5601 if (*input_line_pointer != '=')
5602 {
5603 /* This is just OPT P, which we do not support. */
5604 return;
5605 }
5606
5607 ++input_line_pointer;
5608 mri_chip ();
5609}
5610
5611/* Handle the OPT S option. */
5612
5613static void
31302357 5614opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5615{
5616 listing_list (on);
5617}
5618
5619/* Handle the OPT T option. */
5620
5621static void
31302357 5622opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5623{
5624 if (on)
5625 listing |= LISTING_SYMBOLS;
5626 else
8a104df9 5627 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5628}
5629
5630/* Handle the MRI REG pseudo-op. */
5631
5632static void
31302357 5633s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5634{
5635 char *s;
5636 int c;
5637 struct m68k_op rop;
5638 int mask;
5639 char *stop = NULL;
5640 char stopc;
5641
5642 if (line_label == NULL)
5643 {
5644 as_bad (_("missing label"));
5645 ignore_rest_of_line ();
5646 return;
5647 }
5648
5649 if (flag_mri)
5650 stop = mri_comment_field (&stopc);
5651
5652 SKIP_WHITESPACE ();
5653
5654 s = input_line_pointer;
3882b010 5655 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5656#ifdef REGISTER_PREFIX
5657 || *input_line_pointer == REGISTER_PREFIX
5658#endif
5659 || *input_line_pointer == '/'
5660 || *input_line_pointer == '-')
5661 ++input_line_pointer;
5662 c = *input_line_pointer;
5663 *input_line_pointer = '\0';
5664
5665 if (m68k_ip_op (s, &rop) != 0)
5666 {
5667 if (rop.error == NULL)
5668 as_bad (_("bad register list"));
5669 else
5670 as_bad (_("bad register list: %s"), rop.error);
5671 *input_line_pointer = c;
5672 ignore_rest_of_line ();
5673 return;
5674 }
5675
5676 *input_line_pointer = c;
5677
5678 if (rop.mode == REGLST)
5679 mask = rop.mask;
5680 else if (rop.mode == DREG)
5681 mask = 1 << (rop.reg - DATA0);
5682 else if (rop.mode == AREG)
5683 mask = 1 << (rop.reg - ADDR0 + 8);
5684 else if (rop.mode == FPREG)
5685 mask = 1 << (rop.reg - FP0 + 16);
5686 else if (rop.mode == CONTROL
5687 && rop.reg == FPI)
5688 mask = 1 << 24;
5689 else if (rop.mode == CONTROL
5690 && rop.reg == FPS)
5691 mask = 1 << 25;
5692 else if (rop.mode == CONTROL
5693 && rop.reg == FPC)
5694 mask = 1 << 26;
5695 else
5696 {
5697 as_bad (_("bad register list"));
5698 ignore_rest_of_line ();
5699 return;
5700 }
5701
5702 S_SET_SEGMENT (line_label, reg_section);
5703 S_SET_VALUE (line_label, ~mask);
49309057 5704 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5705
5706 if (flag_mri)
5707 mri_comment_end (stop, stopc);
5708
5709 demand_empty_rest_of_line ();
5710}
5711
5712/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5713
5714struct save_opts
5715{
5716 struct save_opts *next;
5717 int abspcadd;
5718 int symbols_case_sensitive;
5719 int keep_locals;
5720 int short_refs;
5721 int architecture;
2da12c60 5722 const enum m68k_register *control_regs;
252b5132
RH		 5723 int quick;
5724 int rel32;
5725 int listing;
5726 int no_warnings;
5727 /* FIXME: We don't save OPT S. */
5728};
5729
5730/* This variable holds the stack of saved options. */
5731
5732static struct save_opts *save_stack;
5733
5734/* The MRI SAVE pseudo-op. */
5735
5736static void
31302357 5737s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5738{
5739 struct save_opts *s;
5740
5741 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5742 s->abspcadd = m68k_abspcadd;
5743 s->symbols_case_sensitive = symbols_case_sensitive;
5744 s->keep_locals = flag_keep_locals;
5745 s->short_refs = flag_short_refs;
5746 s->architecture = current_architecture;
2da12c60 5747 s->control_regs = control_regs;
252b5132
RH		 5748 s->quick = m68k_quick;
5749 s->rel32 = m68k_rel32;
5750 s->listing = listing;
5751 s->no_warnings = flag_no_warnings;
5752
5753 s->next = save_stack;
5754 save_stack = s;
5755
5756 demand_empty_rest_of_line ();
5757}
5758
5759/* The MRI RESTORE pseudo-op. */
5760
5761static void
31302357 5762s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5763{
5764 struct save_opts *s;
5765
5766 if (save_stack == NULL)
5767 {
5768 as_bad (_("restore without save"));
5769 ignore_rest_of_line ();
5770 return;
5771 }
5772
5773 s = save_stack;
5774 save_stack = s->next;
5775
5776 m68k_abspcadd = s->abspcadd;
5777 symbols_case_sensitive = s->symbols_case_sensitive;
5778 flag_keep_locals = s->keep_locals;
5779 flag_short_refs = s->short_refs;
5780 current_architecture = s->architecture;
2da12c60 5781 control_regs = s->control_regs;
252b5132
RH		 5782 m68k_quick = s->quick;
5783 m68k_rel32 = s->rel32;
5784 listing = s->listing;
5785 flag_no_warnings = s->no_warnings;
5786
5787 free (s);
5788
5789 demand_empty_rest_of_line ();
5790}
5791
5792/* Types of MRI structured control directives. */
5793
5794enum mri_control_type
5795{
5796 mri_for,
5797 mri_if,
5798 mri_repeat,
5799 mri_while
5800};
5801
5802/* This structure is used to stack the MRI structured control
5803 directives. */
5804
5805struct mri_control_info
5806{
5807 /* The directive within which this one is enclosed. */
5808 struct mri_control_info *outer;
5809
5810 /* The type of directive. */
5811 enum mri_control_type type;
5812
5813 /* Whether an ELSE has been in an IF. */
5814 int else_seen;
5815
5816 /* The add or sub statement at the end of a FOR. */
5817 char *incr;
5818
5819 /* The label of the top of a FOR or REPEAT loop. */
5820 char *top;
5821
5822 /* The label to jump to for the next iteration, or the else
5823 expression of a conditional. */
5824 char *next;
5825
5826 /* The label to jump to to break out of the loop, or the label past
5827 the end of a conditional. */
5828 char *bottom;
5829};
5830
5831/* The stack of MRI structured control directives. */
5832
5833static struct mri_control_info *mri_control_stack;
5834
5835/* The current MRI structured control directive index number, used to
5836 generate label names. */
5837
5838static int mri_control_index;
5839
252b5132
RH		 5840/* Assemble an instruction for an MRI structured control directive. */
5841
5842static void
31302357 5843mri_assemble (char *str)
252b5132
RH		 5844{
5845 char *s;
5846
5847 /* md_assemble expects the opcode to be in lower case. */
5848 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5849 *s = TOLOWER (*s);
252b5132
RH		 5850
5851 md_assemble (str);
5852}
5853
5854/* Generate a new MRI label structured control directive label name. */
5855
5856static char *
31302357 5857mri_control_label (void)
252b5132
RH		 5858{
5859 char *n;
5860
5861 n = (char *) xmalloc (20);
5862 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5863 ++mri_control_index;
5864 return n;
5865}
5866
5867/* Create a new MRI structured control directive. */
5868
5869static struct mri_control_info *
31302357 5870push_mri_control (enum mri_control_type type)
252b5132
RH		 5871{
5872 struct mri_control_info *n;
5873
5874 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5875
5876 n->type = type;
5877 n->else_seen = 0;
5878 if (type == mri_if || type == mri_while)
5879 n->top = NULL;
5880 else
5881 n->top = mri_control_label ();
5882 n->next = mri_control_label ();
5883 n->bottom = mri_control_label ();
5884
5885 n->outer = mri_control_stack;
5886 mri_control_stack = n;
5887
5888 return n;
5889}
5890
5891/* Pop off the stack of MRI structured control directives. */
5892
5893static void
31302357 5894pop_mri_control (void)
252b5132
RH		 5895{
5896 struct mri_control_info *n;
5897
5898 n = mri_control_stack;
5899 mri_control_stack = n->outer;
5900 if (n->top != NULL)
5901 free (n->top);
5902 free (n->next);
5903 free (n->bottom);
5904 free (n);
5905}
5906
5907/* Recognize a condition code in an MRI structured control expression. */
5908
5909static int
31302357 5910parse_mri_condition (int *pcc)
252b5132
RH		 5911{
5912 char c1, c2;
5913
5914 know (*input_line_pointer == '<');
5915
5916 ++input_line_pointer;
5917 c1 = *input_line_pointer++;
5918 c2 = *input_line_pointer++;
5919
5920 if (*input_line_pointer != '>')
5921 {
5922 as_bad (_("syntax error in structured control directive"));
5923 return 0;
5924 }
5925
5926 ++input_line_pointer;
5927 SKIP_WHITESPACE ();
5928
3882b010
L		 5929 c1 = TOLOWER (c1);
5930 c2 = TOLOWER (c2);
252b5132
RH		 5931
5932 *pcc = (c1 << 8) | c2;
5933
5934 return 1;
5935}
5936
5937/* Parse a single operand in an MRI structured control expression. */
5938
5939static int
31302357
AS		 5940parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5941 char **rightstart, char **rightstop)
252b5132
RH		 5942{
5943 char *s;
5944
5945 SKIP_WHITESPACE ();
5946
5947 *pcc = -1;
5948 *leftstart = NULL;
5949 *leftstop = NULL;
5950 *rightstart = NULL;
5951 *rightstop = NULL;
5952
5953 if (*input_line_pointer == '<')
5954 {
5955 /* It's just a condition code. */
5956 return parse_mri_condition (pcc);
5957 }
5958
5959 /* Look ahead for the condition code. */
5960 for (s = input_line_pointer; *s != '\0'; ++s)
5961 {
5962 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5963 break;
5964 }
5965 if (*s == '\0')
5966 {
5967 as_bad (_("missing condition code in structured control directive"));
5968 return 0;
5969 }
5970
5971 *leftstart = input_line_pointer;
5972 *leftstop = s;
5973 if (*leftstop > *leftstart
5974 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5975 --*leftstop;
5976
5977 input_line_pointer = s;
5978 if (! parse_mri_condition (pcc))
5979 return 0;
5980
5981 /* Look ahead for AND or OR or end of line. */
5982 for (s = input_line_pointer; *s != '\0'; ++s)
5983 {
e1f44d10
NC		 5984 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5985 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5986 ^^^ ^^ */
8a104df9
KH		 5987 if ((s == input_line_pointer
5988 || *(s-1) == ' '
5989 || *(s-1) == '\t')
5990 && ((strncasecmp (s, "AND", 3) == 0
5991 && (s[3] == '.' || ! is_part_of_name (s[3])))
5992 || (strncasecmp (s, "OR", 2) == 0
5993 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5994 break;
252b5132
RH		 5995 }
5996
5997 *rightstart = input_line_pointer;
5998 *rightstop = s;
5999 if (*rightstop > *rightstart
6000 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6001 --*rightstop;
6002
6003 input_line_pointer = s;
6004
6005 return 1;
6006}
6007
6008#define MCC(b1, b2) (((b1) << 8) | (b2))
6009
6010/* Swap the sense of a condition. This changes the condition so that
6011 it generates the same result when the operands are swapped. */
6012
6013static int
31302357 6014swap_mri_condition (int cc)
252b5132
RH		 6015{
6016 switch (cc)
6017 {
6018 case MCC ('h', 'i'): return MCC ('c', 's');
6019 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6020 /* <HS> is an alias for <CC>. */
e1f44d10 6021 case MCC ('h', 's'):
252b5132 6022 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6023 /* <LO> is an alias for <CS>. */
e1f44d10 6024 case MCC ('l', 'o'):
252b5132
RH		 6025 case MCC ('c', 's'): return MCC ('h', 'i');
6026 case MCC ('p', 'l'): return MCC ('m', 'i');
6027 case MCC ('m', 'i'): return MCC ('p', 'l');
6028 case MCC ('g', 'e'): return MCC ('l', 'e');
6029 case MCC ('l', 't'): return MCC ('g', 't');
6030 case MCC ('g', 't'): return MCC ('l', 't');
6031 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6032 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6033 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6034 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6035 case MCC ('v', 'c'):
6036 case MCC ('v', 's'):
6037 default :
6038 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6039 (char) (cc >> 8), (char) (cc));
6040 break;
252b5132
RH		 6041 }
6042 return cc;
6043}
6044
6045/* Reverse the sense of a condition. */
6046
6047static int
31302357 6048reverse_mri_condition (int cc)
252b5132
RH		 6049{
6050 switch (cc)
6051 {
6052 case MCC ('h', 'i'): return MCC ('l', 's');
6053 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6054 /* <HS> is an alias for <CC> */
6055 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6056 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6057 /* <LO> is an alias for <CS> */
6058 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6059 case MCC ('c', 's'): return MCC ('c', 'c');
6060 case MCC ('n', 'e'): return MCC ('e', 'q');
6061 case MCC ('e', 'q'): return MCC ('n', 'e');
6062 case MCC ('v', 'c'): return MCC ('v', 's');
6063 case MCC ('v', 's'): return MCC ('v', 'c');
6064 case MCC ('p', 'l'): return MCC ('m', 'i');
6065 case MCC ('m', 'i'): return MCC ('p', 'l');
6066 case MCC ('g', 'e'): return MCC ('l', 't');
6067 case MCC ('l', 't'): return MCC ('g', 'e');
6068 case MCC ('g', 't'): return MCC ('l', 'e');
6069 case MCC ('l', 'e'): return MCC ('g', 't');
6070 }
6071 return cc;
6072}
6073
6074/* Build an MRI structured control expression. This generates test
6075 and branch instructions. It goes to TRUELAB if the condition is
6076 true, and to FALSELAB if the condition is false. Exactly one of
6077 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6078 is the size qualifier for the expression. EXTENT is the size to
6079 use for the branch. */
6080
6081static void
31302357
AS		 6082build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6083 char *rightstart, char *rightstop,
6084 const char *truelab, const char *falselab,
6085 int extent)
252b5132
RH		 6086{
6087 char *buf;
6088 char *s;
6089
6090 if (leftstart != NULL)
6091 {
6092 struct m68k_op leftop, rightop;
6093 char c;
6094
6095 /* Swap the compare operands, if necessary, to produce a legal
6096 m68k compare instruction. Comparing a register operand with
6097 a non-register operand requires the register to be on the
6098 right (cmp, cmpa). Comparing an immediate value with
6099 anything requires the immediate value to be on the left
6100 (cmpi). */
6101
6102 c = *leftstop;
6103 *leftstop = '\0';
6104 (void) m68k_ip_op (leftstart, &leftop);
6105 *leftstop = c;
6106
6107 c = *rightstop;
6108 *rightstop = '\0';
6109 (void) m68k_ip_op (rightstart, &rightop);
6110 *rightstop = c;
6111
6112 if (rightop.mode == IMMED
6113 || ((leftop.mode == DREG || leftop.mode == AREG)
6114 && (rightop.mode != DREG && rightop.mode != AREG)))
6115 {
6116 char *temp;
6117
31302357
AS		 6118 /* Correct conditional handling:
6119 if #1 <lt> d0 then ;means if (1 < d0)
6120 ...
6121 endi
e1f44d10 6122
31302357 6123 should assemble to:
e1f44d10 6124
31302357
AS		 6125 cmp #1,d0 if we do *not* swap the operands
6126 bgt true we need the swapped condition!
6127 ble false
6128 true:
6129 ...
6130 false:
6131 */
252b5132
RH		 6132 temp = leftstart;
6133 leftstart = rightstart;
6134 rightstart = temp;
6135 temp = leftstop;
6136 leftstop = rightstop;
6137 rightstop = temp;
8a104df9
KH		 6138 }
6139 else
6140 {
e1f44d10 6141 cc = swap_mri_condition (cc);
252b5132
RH		 6142 }
6143 }
6144
6145 if (truelab == NULL)
6146 {
6147 cc = reverse_mri_condition (cc);
6148 truelab = falselab;
6149 }
92774660 6150
252b5132
RH		 6151 if (leftstart != NULL)
6152 {
6153 buf = (char *) xmalloc (20
6154 + (leftstop - leftstart)
6155 + (rightstop - rightstart));
6156 s = buf;
6157 *s++ = 'c';
6158 *s++ = 'm';
6159 *s++ = 'p';
6160 if (qual != '\0')
3882b010 6161 *s++ = TOLOWER (qual);
252b5132
RH		 6162 *s++ = ' ';
6163 memcpy (s, leftstart, leftstop - leftstart);
6164 s += leftstop - leftstart;
6165 *s++ = ',';
6166 memcpy (s, rightstart, rightstop - rightstart);
6167 s += rightstop - rightstart;
6168 *s = '\0';
6169 mri_assemble (buf);
6170 free (buf);
6171 }
92774660 6172
252b5132
RH		 6173 buf = (char *) xmalloc (20 + strlen (truelab));
6174 s = buf;
6175 *s++ = 'b';
6176 *s++ = cc >> 8;
6177 *s++ = cc & 0xff;
6178 if (extent != '\0')
3882b010 6179 *s++ = TOLOWER (extent);
252b5132
RH		 6180 *s++ = ' ';
6181 strcpy (s, truelab);
6182 mri_assemble (buf);
6183 free (buf);
6184}
6185
6186/* Parse an MRI structured control expression. This generates test
6187 and branch instructions. STOP is where the expression ends. It
6188 goes to TRUELAB if the condition is true, and to FALSELAB if the
6189 condition is false. Exactly one of TRUELAB and FALSELAB will be
6190 NULL, meaning to fall through. QUAL is the size qualifier for the
6191 expression. EXTENT is the size to use for the branch. */
6192
6193static void
31302357
AS		 6194parse_mri_control_expression (char *stop, int qual, const char *truelab,
6195 const char *falselab, int extent)
252b5132
RH		 6196{
6197 int c;
6198 int cc;
6199 char *leftstart;
6200 char *leftstop;
6201 char *rightstart;
6202 char *rightstop;
6203
6204 c = *stop;
6205 *stop = '\0';
6206
6207 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6208 &rightstart, &rightstop))
6209 {
6210 *stop = c;
6211 return;
6212 }
6213
6214 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6215 {
6216 const char *flab;
6217
6218 if (falselab != NULL)
6219 flab = falselab;
6220 else
6221 flab = mri_control_label ();
6222
6223 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6224 rightstop, (const char *) NULL, flab, extent);
6225
6226 input_line_pointer += 3;
6227 if (*input_line_pointer != '.'
6228 || input_line_pointer[1] == '\0')
6229 qual = '\0';
6230 else
6231 {
6232 qual = input_line_pointer[1];
6233 input_line_pointer += 2;
6234 }
6235
6236 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6237 &rightstart, &rightstop))
6238 {
6239 *stop = c;
6240 return;
6241 }
6242
6243 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6244 rightstop, truelab, falselab, extent);
6245
6246 if (falselab == NULL)
6247 colon (flab);
6248 }
6249 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6250 {
6251 const char *tlab;
6252
6253 if (truelab != NULL)
6254 tlab = truelab;
6255 else
6256 tlab = mri_control_label ();
6257
6258 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6259 rightstop, tlab, (const char *) NULL, extent);
6260
6261 input_line_pointer += 2;
6262 if (*input_line_pointer != '.'
6263 || input_line_pointer[1] == '\0')
6264 qual = '\0';
6265 else
6266 {
6267 qual = input_line_pointer[1];
6268 input_line_pointer += 2;
6269 }
6270
6271 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6272 &rightstart, &rightstop))
6273 {
6274 *stop = c;
6275 return;
6276 }
6277
6278 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6279 rightstop, truelab, falselab, extent);
6280
6281 if (truelab == NULL)
6282 colon (tlab);
6283 }
6284 else
6285 {
6286 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6287 rightstop, truelab, falselab, extent);
6288 }
6289
6290 *stop = c;
6291 if (input_line_pointer != stop)
6292 as_bad (_("syntax error in structured control directive"));
6293}
6294
6295/* Handle the MRI IF pseudo-op. This may be a structured control
6296 directive, or it may be a regular assembler conditional, depending
6297 on its operands. */
6298
6299static void
31302357 6300s_mri_if (int qual)
252b5132
RH		 6301{
6302 char *s;
6303 int c;
6304 struct mri_control_info *n;
6305
6306 /* A structured control directive must end with THEN with an
6307 optional qualifier. */
6308 s = input_line_pointer;
e1f44d10
NC		 6309 /* We only accept '*' as introduction of comments if preceded by white space
6310 or at first column of a line (I think this can't actually happen here?)
6311 This is important when assembling:
6312 if d0 <ne> 12(a0,d0*2) then
36759679 6313 if d0 <ne> #CONST*20 then. */
31302357
AS		 6314 while (! (is_end_of_line[(unsigned char) *s]
6315 || (flag_mri
6316 && *s == '*'
6317 && (s == input_line_pointer
6318 || *(s-1) == ' '
6319 || *(s-1) == '\t'))))
252b5132
RH		 6320 ++s;
6321 --s;
6322 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6323 --s;
6324
6325 if (s - input_line_pointer > 1
6326 && s[-1] == '.')
6327 s -= 2;
6328
6329 if (s - input_line_pointer < 3
6330 || strncasecmp (s - 3, "THEN", 4) != 0)
6331 {
6332 if (qual != '\0')
6333 {
6334 as_bad (_("missing then"));
6335 ignore_rest_of_line ();
6336 return;
6337 }
6338
6339 /* It's a conditional. */
6340 s_if (O_ne);
6341 return;
6342 }
6343
6344 /* Since this might be a conditional if, this pseudo-op will be
6345 called even if we are supported to be ignoring input. Double
6346 check now. Clobber *input_line_pointer so that ignore_input
6347 thinks that this is not a special pseudo-op. */
6348 c = *input_line_pointer;
6349 *input_line_pointer = 0;
6350 if (ignore_input ())
6351 {
6352 *input_line_pointer = c;
6353 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6354 ++input_line_pointer;
6355 demand_empty_rest_of_line ();
6356 return;
6357 }
6358 *input_line_pointer = c;
6359
6360 n = push_mri_control (mri_if);
6361
6362 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6363 n->next, s[1] == '.' ? s[2] : '\0');
6364
6365 if (s[1] == '.')
6366 input_line_pointer = s + 3;
6367 else
6368 input_line_pointer = s + 1;
6369
6370 if (flag_mri)
6371 {
6372 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6373 ++input_line_pointer;
6374 }
6375
6376 demand_empty_rest_of_line ();
6377}
6378
6379/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6380 structured IF, associate the ELSE with the IF. Otherwise, assume
6381 it is a conditional else. */
6382
6383static void
31302357 6384s_mri_else (int qual)
252b5132
RH		 6385{
6386 int c;
6387 char *buf;
6388 char q[2];
6389
6390 if (qual == '\0'
6391 && (mri_control_stack == NULL
6392 || mri_control_stack->type != mri_if
6393 || mri_control_stack->else_seen))
6394 {
6395 s_else (0);
6396 return;
6397 }
6398
6399 c = *input_line_pointer;
6400 *input_line_pointer = 0;
6401 if (ignore_input ())
6402 {
6403 *input_line_pointer = c;
6404 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6405 ++input_line_pointer;
6406 demand_empty_rest_of_line ();
6407 return;
6408 }
6409 *input_line_pointer = c;
6410
6411 if (mri_control_stack == NULL
6412 || mri_control_stack->type != mri_if
6413 || mri_control_stack->else_seen)
6414 {
6415 as_bad (_("else without matching if"));
6416 ignore_rest_of_line ();
6417 return;
6418 }
6419
6420 mri_control_stack->else_seen = 1;
6421
6422 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6423 q[0] = TOLOWER (qual);
252b5132
RH		 6424 q[1] = '\0';
6425 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6426 mri_assemble (buf);
6427 free (buf);
6428
6429 colon (mri_control_stack->next);
6430
6431 if (flag_mri)
6432 {
6433 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6434 ++input_line_pointer;
6435 }
6436
6437 demand_empty_rest_of_line ();
6438}
6439
6440/* Handle the MRI ENDI pseudo-op. */
6441
6442static void
31302357 6443s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6444{
6445 if (mri_control_stack == NULL
6446 || mri_control_stack->type != mri_if)
6447 {
6448 as_bad (_("endi without matching if"));
6449 ignore_rest_of_line ();
6450 return;
6451 }
6452
6453 /* ignore_input will not return true for ENDI, so we don't need to
6454 worry about checking it again here. */
6455
6456 if (! mri_control_stack->else_seen)
6457 colon (mri_control_stack->next);
6458 colon (mri_control_stack->bottom);
6459
6460 pop_mri_control ();
6461
6462 if (flag_mri)
6463 {
6464 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6465 ++input_line_pointer;
6466 }
6467
6468 demand_empty_rest_of_line ();
6469}
6470
6471/* Handle the MRI BREAK pseudo-op. */
6472
6473static void
31302357 6474s_mri_break (int extent)
252b5132
RH		 6475{
6476 struct mri_control_info *n;
6477 char *buf;
6478 char ex[2];
6479
6480 n = mri_control_stack;
6481 while (n != NULL
6482 && n->type != mri_for
6483 && n->type != mri_repeat
6484 && n->type != mri_while)
6485 n = n->outer;
6486 if (n == NULL)
6487 {
6488 as_bad (_("break outside of structured loop"));
6489 ignore_rest_of_line ();
6490 return;
6491 }
6492
6493 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6494 ex[0] = TOLOWER (extent);
252b5132
RH		 6495 ex[1] = '\0';
6496 sprintf (buf, "bra%s %s", ex, n->bottom);
6497 mri_assemble (buf);
6498 free (buf);
6499
6500 if (flag_mri)
6501 {
6502 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6503 ++input_line_pointer;
6504 }
6505
6506 demand_empty_rest_of_line ();
6507}
6508
6509/* Handle the MRI NEXT pseudo-op. */
6510
6511static void
31302357 6512s_mri_next (int extent)
252b5132
RH		 6513{
6514 struct mri_control_info *n;
6515 char *buf;
6516 char ex[2];
6517
6518 n = mri_control_stack;
6519 while (n != NULL
6520 && n->type != mri_for
6521 && n->type != mri_repeat
6522 && n->type != mri_while)
6523 n = n->outer;
6524 if (n == NULL)
6525 {
6526 as_bad (_("next outside of structured loop"));
6527 ignore_rest_of_line ();
6528 return;
6529 }
6530
6531 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6532 ex[0] = TOLOWER (extent);
252b5132
RH		 6533 ex[1] = '\0';
6534 sprintf (buf, "bra%s %s", ex, n->next);
6535 mri_assemble (buf);
6536 free (buf);
6537
6538 if (flag_mri)
6539 {
6540 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6541 ++input_line_pointer;
6542 }
6543
6544 demand_empty_rest_of_line ();
6545}
6546
6547/* Handle the MRI FOR pseudo-op. */
6548
6549static void
31302357 6550s_mri_for (int qual)
252b5132
RH		 6551{
6552 const char *varstart, *varstop;
6553 const char *initstart, *initstop;
6554 const char *endstart, *endstop;
6555 const char *bystart, *bystop;
6556 int up;
6557 int by;
6558 int extent;
6559 struct mri_control_info *n;
6560 char *buf;
6561 char *s;
6562 char ex[2];
6563
6564 /* The syntax is
6565 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6566 */
6567
6568 SKIP_WHITESPACE ();
6569 varstart = input_line_pointer;
6570
6571 /* Look for the '='. */
6572 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6573 && *input_line_pointer != '=')
6574 ++input_line_pointer;
6575 if (*input_line_pointer != '=')
6576 {
6577 as_bad (_("missing ="));
6578 ignore_rest_of_line ();
6579 return;
6580 }
6581
6582 varstop = input_line_pointer;
6583 if (varstop > varstart
6584 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6585 --varstop;
6586
6587 ++input_line_pointer;
6588
6589 initstart = input_line_pointer;
6590
6591 /* Look for TO or DOWNTO. */
6592 up = 1;
6593 initstop = NULL;
6594 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6595 {
6596 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6597 && ! is_part_of_name (input_line_pointer[2]))
6598 {
6599 initstop = input_line_pointer;
6600 input_line_pointer += 2;
6601 break;
6602 }
6603 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6604 && ! is_part_of_name (input_line_pointer[6]))
6605 {
6606 initstop = input_line_pointer;
6607 up = 0;
6608 input_line_pointer += 6;
6609 break;
6610 }
6611 ++input_line_pointer;
6612 }
6613 if (initstop == NULL)
6614 {
6615 as_bad (_("missing to or downto"));
6616 ignore_rest_of_line ();
6617 return;
6618 }
6619 if (initstop > initstart
6620 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6621 --initstop;
6622
6623 SKIP_WHITESPACE ();
6624 endstart = input_line_pointer;
6625
6626 /* Look for BY or DO. */
6627 by = 0;
6628 endstop = NULL;
6629 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6630 {
6631 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6632 && ! is_part_of_name (input_line_pointer[2]))
6633 {
6634 endstop = input_line_pointer;
6635 by = 1;
6636 input_line_pointer += 2;
6637 break;
6638 }
6639 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6640 && (input_line_pointer[2] == '.'
6641 || ! is_part_of_name (input_line_pointer[2])))
6642 {
6643 endstop = input_line_pointer;
6644 input_line_pointer += 2;
6645 break;
6646 }
6647 ++input_line_pointer;
6648 }
6649 if (endstop == NULL)
6650 {
6651 as_bad (_("missing do"));
6652 ignore_rest_of_line ();
6653 return;
6654 }
6655 if (endstop > endstart
6656 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6657 --endstop;
6658
6659 if (! by)
6660 {
6661 bystart = "#1";
6662 bystop = bystart + 2;
6663 }
6664 else
6665 {
6666 SKIP_WHITESPACE ();
6667 bystart = input_line_pointer;
6668
6669 /* Look for DO. */
6670 bystop = NULL;
6671 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6672 {
6673 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6674 && (input_line_pointer[2] == '.'
6675 || ! is_part_of_name (input_line_pointer[2])))
6676 {
6677 bystop = input_line_pointer;
6678 input_line_pointer += 2;
6679 break;
6680 }
6681 ++input_line_pointer;
6682 }
6683 if (bystop == NULL)
6684 {
6685 as_bad (_("missing do"));
6686 ignore_rest_of_line ();
6687 return;
6688 }
6689 if (bystop > bystart
6690 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6691 --bystop;
6692 }
6693
6694 if (*input_line_pointer != '.')
6695 extent = '\0';
6696 else
6697 {
6698 extent = input_line_pointer[1];
6699 input_line_pointer += 2;
6700 }
6701
6702 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6703 n = push_mri_control (mri_for);
6704
6705 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6706
36759679 6707 /* Move init,var. */
252b5132
RH		 6708 s = buf;
6709 *s++ = 'm';
6710 *s++ = 'o';
6711 *s++ = 'v';
6712 *s++ = 'e';
6713 if (qual != '\0')
3882b010 6714 *s++ = TOLOWER (qual);
252b5132
RH		 6715 *s++ = ' ';
6716 memcpy (s, initstart, initstop - initstart);
6717 s += initstop - initstart;
6718 *s++ = ',';
6719 memcpy (s, varstart, varstop - varstart);
6720 s += varstop - varstart;
6721 *s = '\0';
6722 mri_assemble (buf);
6723
6724 colon (n->top);
6725
36759679 6726 /* cmp end,var. */
252b5132
RH		 6727 s = buf;
6728 *s++ = 'c';
6729 *s++ = 'm';
6730 *s++ = 'p';
6731 if (qual != '\0')
3882b010 6732 *s++ = TOLOWER (qual);
252b5132
RH		 6733 *s++ = ' ';
6734 memcpy (s, endstart, endstop - endstart);
6735 s += endstop - endstart;
6736 *s++ = ',';
6737 memcpy (s, varstart, varstop - varstart);
6738 s += varstop - varstart;
6739 *s = '\0';
6740 mri_assemble (buf);
6741
36759679 6742 /* bcc bottom. */
3882b010 6743 ex[0] = TOLOWER (extent);
252b5132
RH		 6744 ex[1] = '\0';
6745 if (up)
6746 sprintf (buf, "blt%s %s", ex, n->bottom);
6747 else
6748 sprintf (buf, "bgt%s %s", ex, n->bottom);
6749 mri_assemble (buf);
6750
6751 /* Put together the add or sub instruction used by ENDF. */
6752 s = buf;
6753 if (up)
6754 strcpy (s, "add");
6755 else
6756 strcpy (s, "sub");
6757 s += 3;
6758 if (qual != '\0')
3882b010 6759 *s++ = TOLOWER (qual);
252b5132
RH		 6760 *s++ = ' ';
6761 memcpy (s, bystart, bystop - bystart);
6762 s += bystop - bystart;
6763 *s++ = ',';
6764 memcpy (s, varstart, varstop - varstart);
6765 s += varstop - varstart;
6766 *s = '\0';
6767 n->incr = buf;
6768
6769 if (flag_mri)
6770 {
6771 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6772 ++input_line_pointer;
6773 }
6774
6775 demand_empty_rest_of_line ();
6776}
6777
6778/* Handle the MRI ENDF pseudo-op. */
6779
6780static void
31302357 6781s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6782{
6783 if (mri_control_stack == NULL
6784 || mri_control_stack->type != mri_for)
6785 {
6786 as_bad (_("endf without for"));
6787 ignore_rest_of_line ();
6788 return;
6789 }
6790
6791 colon (mri_control_stack->next);
6792
6793 mri_assemble (mri_control_stack->incr);
6794
6795 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6796 mri_assemble (mri_control_stack->incr);
6797
6798 free (mri_control_stack->incr);
6799
6800 colon (mri_control_stack->bottom);
6801
6802 pop_mri_control ();
6803
6804 if (flag_mri)
6805 {
6806 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6807 ++input_line_pointer;
6808 }
6809
6810 demand_empty_rest_of_line ();
6811}
6812
6813/* Handle the MRI REPEAT pseudo-op. */
6814
6815static void
31302357 6816s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6817{
6818 struct mri_control_info *n;
6819
6820 n = push_mri_control (mri_repeat);
6821 colon (n->top);
6822 if (flag_mri)
6823 {
6824 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6825 ++input_line_pointer;
6826 }
6827 demand_empty_rest_of_line ();
6828}
6829
6830/* Handle the MRI UNTIL pseudo-op. */
6831
6832static void
31302357 6833s_mri_until (int qual)
252b5132
RH		 6834{
6835 char *s;
6836
6837 if (mri_control_stack == NULL
6838 || mri_control_stack->type != mri_repeat)
6839 {
6840 as_bad (_("until without repeat"));
6841 ignore_rest_of_line ();
6842 return;
6843 }
6844
6845 colon (mri_control_stack->next);
6846
6847 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6848 ;
6849
6850 parse_mri_control_expression (s, qual, (const char *) NULL,
6851 mri_control_stack->top, '\0');
6852
6853 colon (mri_control_stack->bottom);
6854
6855 input_line_pointer = s;
6856
6857 pop_mri_control ();
6858
6859 if (flag_mri)
6860 {
6861 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6862 ++input_line_pointer;
6863 }
6864
6865 demand_empty_rest_of_line ();
6866}
6867
6868/* Handle the MRI WHILE pseudo-op. */
6869
6870static void
31302357 6871s_mri_while (int qual)
252b5132
RH		 6872{
6873 char *s;
6874
6875 struct mri_control_info *n;
6876
6877 s = input_line_pointer;
e1f44d10
NC		 6878 /* We only accept '*' as introduction of comments if preceded by white space
6879 or at first column of a line (I think this can't actually happen here?)
6880 This is important when assembling:
6881 while d0 <ne> 12(a0,d0*2) do
36759679 6882 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6883 while (! (is_end_of_line[(unsigned char) *s]
6884 || (flag_mri
6885 && *s == '*'
6886 && (s == input_line_pointer
6887 || *(s-1) == ' '
6888 || *(s-1) == '\t'))))
252b5132
RH		 6889 s++;
6890 --s;
6891 while (*s == ' ' || *s == '\t')
6892 --s;
6893 if (s - input_line_pointer > 1
6894 && s[-1] == '.')
6895 s -= 2;
6896 if (s - input_line_pointer < 2
6897 || strncasecmp (s - 1, "DO", 2) != 0)
6898 {
6899 as_bad (_("missing do"));
6900 ignore_rest_of_line ();
6901 return;
6902 }
6903
6904 n = push_mri_control (mri_while);
6905
6906 colon (n->next);
6907
6908 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6909 s[1] == '.' ? s[2] : '\0');
6910
6911 input_line_pointer = s + 1;
6912 if (*input_line_pointer == '.')
6913 input_line_pointer += 2;
6914
6915 if (flag_mri)
6916 {
6917 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6918 ++input_line_pointer;
6919 }
6920
6921 demand_empty_rest_of_line ();
6922}
6923
6924/* Handle the MRI ENDW pseudo-op. */
6925
6926static void
31302357 6927s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6928{
6929 char *buf;
6930
6931 if (mri_control_stack == NULL
6932 || mri_control_stack->type != mri_while)
6933 {
6934 as_bad (_("endw without while"));
6935 ignore_rest_of_line ();
6936 return;
6937 }
6938
6939 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6940 sprintf (buf, "bra %s", mri_control_stack->next);
6941 mri_assemble (buf);
6942 free (buf);
6943
6944 colon (mri_control_stack->bottom);
6945
6946 pop_mri_control ();
6947
6948 if (flag_mri)
6949 {
6950 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6951 ++input_line_pointer;
6952 }
6953
6954 demand_empty_rest_of_line ();
6955}
6956\f
266abb8f
NS		 6957/* Parse a .cpu directive. */
6958
6959static void
6960s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6961{
6962 char saved_char;
6963 char *name;
6964
6965 if (initialized)
6966 {
6967 as_bad (_("already assembled instructions"));
6968 ignore_rest_of_line ();
6969 return;
6970 }
6971
6972 name = input_line_pointer;
6973 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6974 input_line_pointer++;
6975 saved_char = *input_line_pointer;
6976 *input_line_pointer = 0;
6977
6978 m68k_set_cpu (name, 1, 0);
6979
6980 *input_line_pointer = saved_char;
6981 demand_empty_rest_of_line ();
6982 return;
6983}
6984
6985/* Parse a .arch directive. */
6986
6987static void
6988s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6989{
6990 char saved_char;
6991 char *name;
6992
6993 if (initialized)
6994 {
6995 as_bad (_("already assembled instructions"));
6996 ignore_rest_of_line ();
6997 return;
6998 }
6999
7000 name = input_line_pointer;
7001 while (*input_line_pointer && *input_line_pointer != ','
7002 && !ISSPACE (*input_line_pointer))
7003 input_line_pointer++;
7004 saved_char = *input_line_pointer;
7005 *input_line_pointer = 0;
7006
7007 if (m68k_set_arch (name, 1, 0))
7008 {
7009 /* Scan extensions. */
7010 do
7011 {
7012 *input_line_pointer++ = saved_char;
7013 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7014 break;
7015 name = input_line_pointer;
7016 while (*input_line_pointer && *input_line_pointer != ','
7017 && !ISSPACE (*input_line_pointer))
7018 input_line_pointer++;
7019 saved_char = *input_line_pointer;
7020 *input_line_pointer = 0;
7021 }
7022 while (m68k_set_extension (name, 1, 0));
7023 }
7024
7025 *input_line_pointer = saved_char;
7026 demand_empty_rest_of_line ();
7027 return;
7028}
7029\f
7030/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7031 if none is found, the caller is responsible for emitting an error
7032 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7033 cpu name, if it begins with a '6' (possibly skipping an intervening
7034 'c'. We also allow a 'c' in the same place. if NEGATED is
7035 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7036 the option is indeed negated. */
7037
7038static const struct m68k_cpu *
7039m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7040 int allow_m, int *negated)
7041{
7042 /* allow negated value? */
7043 if (negated)
7044 {
7045 *negated = 0;
7046
7047 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7048 {
7049 arg += 3;
7050 *negated = 1;
7051 }
7052 }
7053
7054 /* Remove 'm' or 'mc' prefix from 68k variants. */
7055 if (allow_m)
7056 {
7057 if (arg[0] == 'm')
7058 {
7059 if (arg[1] == '6')
7060 arg += 1;
7061 else if (arg[1] == 'c' && arg[2] == '6')
7062 arg += 2;
7063 }
7064 }
7065 else if (arg[0] == 'c' && arg[1] == '6')
7066 arg += 1;
7067
7068 for (; table->name; table++)
7069 if (!strcmp (arg, table->name))
2da12c60
NS		 7070 {
7071 if (table->alias < -1 || table->alias > 1)
7072 as_bad (_("`%s' is deprecated, use `%s'"),
7073 table->name, table[table->alias < 0 ? 1 : -1].name);
7074 return table;
7075 }
266abb8f
NS		 7076 return 0;
7077}
7078
7079/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7080
7081static int
7082m68k_set_cpu (char const *name, int allow_m, int silent)
7083{
7084 const struct m68k_cpu *cpu;
7085
7086 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7087
7088 if (!cpu)
7089 {
7090 if (!silent)
7091 as_bad (_("cpu `%s' unrecognized"), name);
7092 return 0;
7093 }
7094
7095 if (selected_cpu && selected_cpu != cpu)
7096 {
7097 as_bad (_("already selected `%s' processor"),
7098 selected_cpu->name);
7099 return 0;
7100 }
7101 selected_cpu = cpu;
7102 return 1;
7103}
7104
7105/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7106
7107static int
7108m68k_set_arch (char const *name, int allow_m, int silent)
7109{
7110 const struct m68k_cpu *arch;
7111
7112 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7113
7114 if (!arch)
7115 {
7116 if (!silent)
7117 as_bad (_("architecture `%s' unrecognized"), name);
7118 return 0;
7119 }
7120
7121 if (selected_arch && selected_arch != arch)
7122 {
7123 as_bad (_("already selected `%s' architecture"),
7124 selected_arch->name);
7125 return 0;
7126 }
7127
7128 selected_arch = arch;
7129 return 1;
7130}
7131
7132/* Set the architecture extension, issuing errors if it is
7133 unrecognized, or invalid */
7134
7135static int
7136m68k_set_extension (char const *name, int allow_m, int silent)
7137{
7138 int negated;
7139 const struct m68k_cpu *ext;
7140
7141 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7142
7143 if (!ext)
7144 {
7145 if (!silent)
7146 as_bad (_("extension `%s' unrecognized"), name);
7147 return 0;
7148 }
7149
7150 if (negated)
7151 not_current_architecture |= ext->arch;
7152 else
7153 current_architecture |= ext->arch;
7154 return 1;
7155}
7156
31302357
AS		 7157/* md_parse_option
7158 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7159 */
252b5132
RH		 7160
7161#ifdef OBJ_ELF
5a38dc70 7162const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7163#else
5a38dc70 7164const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7165#endif
7166
7167struct option md_longopts[] = {
7168#define OPTION_PIC (OPTION_MD_BASE)
7169 {"pic", no_argument, NULL, OPTION_PIC},
7170#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7171 {"register-prefix-optional", no_argument, NULL,
7172 OPTION_REGISTER_PREFIX_OPTIONAL},
7173#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7174 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7175#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7176 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7177#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7178 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7179#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7180 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7181#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7182 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7183#define OPTION_PCREL (OPTION_MD_BASE + 7)
7184 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7185 {NULL, no_argument, NULL, 0}
7186};
bc805888 7187size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7188
7189int
31302357 7190md_parse_option (int c, char *arg)
252b5132
RH		 7191{
7192 switch (c)
7193 {
7194 case 'l': /* -l means keep external to 2 bit offset
36759679 7195 rather than 16 bit one. */
252b5132
RH		 7196 flag_short_refs = 1;
7197 break;
7198
7199 case 'S': /* -S means that jbsr's always turn into
7200 jsr's. */
7201 flag_long_jumps = 1;
7202 break;
7203
28e7409f
NC		 7204 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7205 branches into absolute jumps. */
7206 flag_keep_pcrel = 1;
7207 break;
7208
252b5132
RH		 7209 case OPTION_PIC:
7210 case 'k':
7211 flag_want_pic = 1;
36759679 7212 break; /* -pic, Position Independent Code. */
252b5132
RH		 7213
7214 case OPTION_REGISTER_PREFIX_OPTIONAL:
7215 flag_reg_prefix_optional = 1;
7216 reg_prefix_optional_seen = 1;
7217 break;
7218
7219 /* -V: SVR4 argument to print version ID. */
7220 case 'V':
7221 print_version_id ();
7222 break;
7223
7224 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7225 should be emitted or not. FIXME: Not implemented. */
7226 case 'Q':
7227 break;
7228
7229 case OPTION_BITWISE_OR:
7230 {
7231 char *n, *t;
7232 const char *s;
7233
7234 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7235 t = n;
7236 for (s = m68k_comment_chars; *s != '\0'; s++)
7237 if (*s != '|')
7238 *t++ = *s;
7239 *t = '\0';
7240 m68k_comment_chars = n;
7241 }
7242 break;
7243
7244 case OPTION_BASE_SIZE_DEFAULT_16:
7245 m68k_index_width_default = SIZE_WORD;
7246 break;
7247
7248 case OPTION_BASE_SIZE_DEFAULT_32:
7249 m68k_index_width_default = SIZE_LONG;
7250 break;
7251
7252 case OPTION_DISP_SIZE_DEFAULT_16:
7253 m68k_rel32 = 0;
7254 m68k_rel32_from_cmdline = 1;
7255 break;
7256
7257 case OPTION_DISP_SIZE_DEFAULT_32:
7258 m68k_rel32 = 1;
7259 m68k_rel32_from_cmdline = 1;
7260 break;
7261
266abb8f
NS		 7262 case 'A':
7263#if WARN_DEPRECATED
7264 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7265 arg, arg));
7266#endif
7267 /* Intentional fall-through. */
7268 case 'm':
7269 if (!strncmp (arg, "arch=", 5))
7270 m68k_set_arch (arg + 5, 1, 0);
7271 else if (!strncmp (arg, "cpu=", 4))
7272 m68k_set_cpu (arg + 4, 1, 0);
7273 else if (m68k_set_extension (arg, 0, 1))
7274 ;
0b2e31dc
NS		 7275 else if (m68k_set_arch (arg, 0, 1))
7276 ;
266abb8f
NS		 7277 else if (m68k_set_cpu (arg, 0, 1))
7278 ;
7279 else
7280 return 0;
7281 break;
7282
252b5132
RH		 7283 default:
7284 return 0;
7285 }
7286
7287 return 1;
7288}
7289
266abb8f
NS		 7290/* Setup tables from the selected arch and/or cpu */
7291
7292static void
7293m68k_init_arch (void)
7294{
266abb8f
NS		 7295 if (not_current_architecture & current_architecture)
7296 {
7297 as_bad (_("architecture features both enabled and disabled"));
7298 not_current_architecture &= ~current_architecture;
7299 }
7300 if (selected_arch)
2da12c60
NS		 7301 {
7302 current_architecture |= selected_arch->arch;
7303 control_regs = selected_arch->control_regs;
7304 }
0b2e31dc
NS		 7305 else
7306 current_architecture |= selected_cpu->arch;
0b2e31dc 7307
2da12c60
NS		 7308 current_architecture &= ~not_current_architecture;
7309
377260ba
NS		 7310 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7311 {
7312 /* Determine which float is really meant. */
7313 if (current_architecture & (m68k_mask & ~m68881))
7314 current_architecture ^= cfloat;
7315 else
7316 current_architecture ^= m68881;
7317 }
7318
0b2e31dc 7319 if (selected_cpu)
266abb8f 7320 {
2da12c60 7321 control_regs = selected_cpu->control_regs;
0b2e31dc 7322 if (current_architecture & ~selected_cpu->arch)
266abb8f 7323 {
0b2e31dc
NS		 7324 as_bad (_("selected processor does not have all features of selected architecture"));
7325 current_architecture
7326 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7327 }
7328 }
266abb8f 7329
266abb8f
NS		 7330 if ((current_architecture & m68k_mask)
7331 && (current_architecture & ~m68k_mask))
7332 {
7333 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7334 if (current_architecture & m68k_mask)
266abb8f
NS		 7335 current_architecture &= m68k_mask;
7336 else
7337 current_architecture &= ~m68k_mask;
7338 }
7339
7340 /* Permit m68881 specification with all cpus; those that can't work
7341 with a coprocessor could be doing emulation. */
7342 if (current_architecture & m68851)
7343 {
7344 if (current_architecture & m68040)
7345 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7346 }
7347 /* What other incompatibilities could we check for? */
7348
266abb8f
NS		 7349 if (cpu_of_arch (current_architecture) < m68020
7350 || arch_coldfire_p (current_architecture))
7351 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7352
7353 initialized = 1;
7354}
7355
252b5132 7356void
31302357 7357md_show_usage (FILE *stream)
252b5132 7358{
76f57f3a 7359 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7360 int i;
7361 unsigned int default_arch;
76f57f3a 7362
8a104df9 7363 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7364 if (*default_cpu == 'm')
7365 default_cpu++;
266abb8f 7366 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7367 {
266abb8f 7368 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7369 {
266abb8f 7370 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7371 while (m68k_cpus[i].alias > 0)
7372 i--;
7373 while (m68k_cpus[i].alias < 0)
7374 i++;
7375 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7376 }
7377 }
7378
bc805888 7379 fprintf (stream, _("\
266abb8f
NS		 7380-march=<arch> set architecture\n\
7381-mcpu=<cpu> set cpu [default %s]\n\
7382"), default_cpu);
7383 for (i = 0; m68k_extensions[i].name; i++)
7384 fprintf (stream, _("\
0b2e31dc
NS		 7385-m[no-]%-16s enable/disable%s architecture extension\n\
7386"), m68k_extensions[i].name,
7387 m68k_extensions[i].alias > 0 ? " ColdFire"
7388 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7389
bc805888 7390 fprintf (stream, _("\
266abb8f 7391-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7392-pic, -k generate position independent code\n\
7393-S turn jbsr into jsr\n\
28e7409f 7394--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7395--register-prefix-optional\n\
7396 recognize register names without prefix character\n\
266abb8f 7397--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7398--base-size-default-16 base reg without size is 16 bits\n\
7399--base-size-default-32 base reg without size is 32 bits (default)\n\
7400--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7401--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7402"));
7403
7404 fprintf (stream, _("Architecture variants are: "));
7405 for (i = 0; m68k_archs[i].name; i++)
7406 {
7407 if (i)
7408 fprintf (stream, " | ");
7409 fprintf (stream, m68k_archs[i].name);
7410 }
7411 fprintf (stream, "\n");
7412
7413 fprintf (stream, _("Processor variants are: "));
7414 for (i = 0; m68k_cpus[i].name; i++)
7415 {
7416 if (i)
7417 fprintf (stream, " | ");
7418 fprintf (stream, m68k_cpus[i].name);
7419 }
7420 fprintf (stream, _("\n"));
252b5132
RH		 7421}
7422\f
7423#ifdef TEST2
7424
7425/* TEST2: Test md_assemble() */
36759679
NC		 7426/* Warning, this routine probably doesn't work anymore. */
7427int
31302357 7428main (void)
252b5132
RH		 7429{
7430 struct m68k_it the_ins;
7431 char buf[120];
7432 char *cp;
7433 int n;
7434
7435 m68k_ip_begin ();
7436 for (;;)
7437 {
7438 if (!gets (buf) || !*buf)
7439 break;
7440 if (buf[0] == '|' || buf[1] == '.')
7441 continue;
7442 for (cp = buf; *cp; cp++)
7443 if (*cp == '\t')
7444 *cp = ' ';
7445 if (is_label (buf))
7446 continue;
7447 memset (&the_ins, '\0', sizeof (the_ins));
7448 m68k_ip (&the_ins, buf);
7449 if (the_ins.error)
7450 {
7451 printf (_("Error %s in %s\n"), the_ins.error, buf);
7452 }
7453 else
7454 {
7455 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7456 for (n = 0; n < the_ins.numo; n++)
7457 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7458 printf (" ");
7459 print_the_insn (&the_ins.opcode[0], stdout);
7460 (void) putchar ('\n');
7461 }
7462 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7463 {
7464 if (the_ins.operands[n].error)
7465 {
7466 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7467 continue;
7468 }
31302357
AS		 7469 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7470 the_ins.operands[n].reg);
252b5132 7471 if (the_ins.operands[n].b_const)
31302357
AS		 7472 printf ("Constant: '%.*s', ",
7473 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7474 the_ins.operands[n].b_const);
7475 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7476 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7477 if (the_ins.operands[n].b_iadd)
31302357
AS		 7478 printf ("Iadd: '%.*s',",
7479 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7480 the_ins.operands[n].b_iadd);
7481 putchar ('\n');
252b5132
RH		 7482 }
7483 }
7484 m68k_ip_end ();
7485 return 0;
7486}
7487
31302357
AS		 7488int
7489is_label (char *str)
252b5132
RH		 7490{
7491 while (*str == ' ')
7492 str++;
7493 while (*str && *str != ' ')
7494 str++;
7495 if (str[-1] == ':' || str[1] == '=')
7496 return 1;
7497 return 0;
7498}
7499
7500#endif
7501
7502/* Possible states for relaxation:
7503
7504 0 0 branch offset byte (bra, etc)
7505 0 1 word
7506 0 2 long
7507
7508 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7509 1 1 word
7510 1 2 long
7511
7512 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7513 2 1 word-long
7514 2 2 long-word
7515 2 3 long-long
7516
7517 */
7518
7519/* We have no need to default values of symbols. */
7520
252b5132 7521symbolS *
31302357 7522md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7523{
7524 return 0;
7525}
7526
7527/* Round up a section size to the appropriate boundary. */
7528valueT
31302357 7529md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7530{
7531#ifdef OBJ_AOUT
252b5132
RH		 7532 /* For a.out, force the section size to be aligned. If we don't do
7533 this, BFD will align it for us, but it will not write out the
7534 final bytes of the section. This may be a bug in BFD, but it is
7535 easier to fix it here since that is how the other a.out targets
7536 work. */
7537 int align;
7538
7539 align = bfd_get_section_alignment (stdoutput, segment);
7540 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7541#endif
7542
7543 return size;
7544}
7545
7546/* Exactly what point is a PC-relative offset relative TO?
7547 On the 68k, it is relative to the address of the first extension
7548 word. The difference between the addresses of the offset and the
92774660 7549 first extension word is stored in fx_pcrel_adjust. */
252b5132 7550long
31302357 7551md_pcrel_from (fixS *fixP)
252b5132
RH		 7552{
7553 int adjust;
7554
8390138c
AS		 7555 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7556 sign extend the value here. */
7557 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7558 if (adjust == 64)
7559 adjust = -1;
7560 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7561}
7562
0d96863f 7563#ifdef OBJ_ELF
8a104df9 7564void
31302357 7565m68k_elf_final_processing (void)
0d96863f 7566{
266abb8f
NS		 7567 unsigned flags = 0;
7568
238d258f 7569 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7570 flags |= EF_M68K_CFV4E;
7571 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7572 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7573 flags |= EF_M68K_CPU32;
7574 else if (cpu_of_arch (current_architecture) & fido_a)
7575 flags |= EF_M68K_FIDO;
8a104df9
KH		 7576 else if ((cpu_of_arch (current_architecture) & m68000up)
7577 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7578 flags |= EF_M68K_M68000;
7579
7580 if (current_architecture & mcfisa_a)
7581 {
0b2e31dc
NS		 7582 static const unsigned isa_features[][2] =
7583 {
c694fd50
KH		 7584 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7585 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7586 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7587 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7588 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7589 {0,0},
7590 };
7591 static const unsigned mac_features[][2] =
7592 {
c694fd50
KH		 7593 {EF_M68K_CF_MAC, mcfmac},
7594 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7595 {0,0},
7596 };
7597 unsigned ix;
7598 unsigned pattern;
266abb8f 7599
0b2e31dc
NS		 7600 pattern = (current_architecture
7601 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7602 for (ix = 0; isa_features[ix][1]; ix++)
7603 {
7604 if (pattern == isa_features[ix][1])
7605 {
7606 flags |= isa_features[ix][0];
7607 break;
7608 }
7609 }
7610 if (!isa_features[ix][1])
7611 {
7612 cf_bad:
7613 as_warn (_("Not a defined coldfire architecture"));
7614 }
7615 else
7616 {
7617 if (current_architecture & cfloat)
c694fd50 7618 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7619
0b2e31dc
NS		 7620 pattern = current_architecture & (mcfmac|mcfemac);
7621 if (pattern)
7622 {
7623 for (ix = 0; mac_features[ix][1]; ix++)
7624 {
7625 if (pattern == mac_features[ix][1])
7626 {
7627 flags |= mac_features[ix][0];
7628 break;
7629 }
7630 }
7631 if (!mac_features[ix][1])
7632 goto cf_bad;
7633 }
7634 }
266abb8f
NS		 7635 }
7636 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7637}
7638#endif
c04898f8
AS		 7639
7640int
1df69f4f 7641tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7642{
7643 unsigned int regnum;
7644 static const char *const regnames[] =
7645 {
7646 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7647 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7648 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7649 "pc"
7650 };
7651
7652 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7653 if (strcmp (regname, regnames[regnum]) == 0)
7654 return regnum;
7655
7656 return -1;
7657}
7658
7659void
7660tc_m68k_frame_initial_instructions (void)
7661{
7662 static int sp_regno = -1;
7663
7664 if (sp_regno < 0)
7665 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7666
7667 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7668 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7669}
GDB Binutils - Deliverables
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