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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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a87b3269 1/* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
fecd2382 2 slow to compile, easy to find file.
6d27d3a2 3
a87b3269 4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
6d27d3a2 5
a39116f1 6 This file is part of GAS, the GNU Assembler.
6d27d3a2 7
a39116f1
RP		 8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
6d27d3a2 12
a39116f1
RP		 13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
6d27d3a2 17
a39116f1
RP		 18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
fecd2382
RP		 21
22#include <ctype.h>
f8701a3f 23#define NO_RELOC 0
fecd2382 24#include "as.h"
3ad9ec6a 25#include "read.h"
fecd2382
RP		 26
27#include "obstack.h"
28
a39116f1 29/* note that this file includes real declarations and thus can only be included by one source file per executable. */
e0982afe 30#include "opcode/m68k.h"
3ad9ec6a 31
f6e504fe
RP		 32#ifdef TE_SUN
33/* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
36
355afbcd 37long omagic = 2 << 16 | OMAGIC; /* Magic byte for header file */
f6e504fe
RP		 38#else
39long omagic = OMAGIC;
40#endif
fecd2382
RP		 41
42/* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44const char comment_chars[] = "|";
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
53const char line_comment_chars[] = "#";
54
587c4264
ILT		 55const char line_separator_chars[] = "";
56
fecd2382
RP		 57/* Chars that can be used to separate mant from exp in floating point nums */
58const char EXP_CHARS[] = "eE";
59
60/* Chars that mean this number is a floating point constant */
61/* As in 0f12.456 */
62/* or 0d1.2345e12 */
63
64const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65
66/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here.
a39116f1 69 */
fecd2382
RP		 70
71int md_reloc_size = 8; /* Size of relocation record */
72
73/* Its an arbitrary name: This means I don't approve of it */
74/* See flames below */
75static struct obstack robyn;
76
77#define TAB(x,y) (((x)<<2)+(y))
78#define TABTYPE(xy) ((xy) >> 2)
79#define BYTE 0
80#define SHORT 1
81#define LONG 2
82#define SZ_UNDEF 3
3ad9ec6a
ILT		 83#undef BRANCH
84#define ABRANCH 1
fecd2382
RP		 85#define FBRANCH 2
86#define PCREL 3
87#define BCC68000 4
88#define DBCC 5
89#define PCLEA 6
90
f6e504fe 91/* Operands we can parse: (And associated modes)
6d27d3a2 92
a39116f1
RP		 93 numb: 8 bit num
94 numw: 16 bit num
95 numl: 32 bit num
96 dreg: data reg 0-7
97 reg: address or data register
98 areg: address register
99 apc: address register, PC, ZPC or empty string
100 num: 16 or 32 bit num
101 num2: like num
102 sz: w or l if omitted, l assumed
103 scale: 1 2 4 or 8 if omitted, 1 assumed
6d27d3a2 104
a39116f1
RP		 105 7.4 IMMED #num --> NUM
106 0.? DREG dreg --> dreg
107 1.? AREG areg --> areg
108 2.? AINDR areg@ --> *(areg)
109 3.? AINC areg@+ --> *(areg++)
110 4.? ADEC areg@- --> *(--areg)
111 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
112 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
113 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
114 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
115 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
116 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
117 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
118 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
119 7.0 ABSL num:sz --> *(num)
120 num --> *(num) (sz L assumed)
121 *** MSCR otherreg --> Magic
122 With -l option
123 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
c50140c8 124 ?.? DINDR dreg@ --> (dreg) -- cas2 only
6d27d3a2 125
a39116f1
RP		 126 examples:
127 #foo #0x35 #12
128 d2
129 a4
130 a3@
131 a5@+
132 a6@-
133 a2@(12) pc@(14)
134 a1@(5,d2:w:1) @(45,d6:l:4)
135 pc@(a2) @(d4)
136 etc . . .
6d27d3a2
KR		 137
138
a39116f1
RP		 139 #name@(numw) -->turn into PC rel mode
140 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
6d27d3a2 141
a39116f1 142 */
f6e504fe 143
355afbcd
KR		 144enum operand_type
145 {
146 IMMED = 1,
147 DREG,
148 AREG,
149 AINDR,
150 ADEC,
151 AINC,
152 AOFF,
153 AINDX,
154 APODX,
155 AMIND,
156 APRDX,
157 ABSL,
158 MSCR,
159 REGLST,
160 DINDR
161 };
162
163
164struct m68k_exp
165 {
166 char *e_beg;
167 char *e_end;
168 expressionS e_exp;
169 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
170 };
fecd2382 171
7c15cbe8
RP		 172/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
173 8-15==addr reg for operands that take both types */
174
355afbcd
KR		 175enum _register
176 {
177 DATA = 1, /* 1- 8 == data registers 0-7 */
178 DATA0 = DATA,
179 DATA1,
180 DATA2,
181 DATA3,
182 DATA4,
183 DATA5,
184 DATA6,
185 DATA7,
186
187 ADDR,
188 ADDR0 = ADDR,
189 ADDR1,
190 ADDR2,
191 ADDR3,
192 ADDR4,
193 ADDR5,
194 ADDR6,
195 ADDR7,
196
197 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
198 /* I think. . . */
199
200 SP = ADDR7,
201
202 FPREG, /* Eight FP registers */
203 FP0 = FPREG,
204 FP1,
205 FP2,
206 FP3,
207 FP4,
208 FP5,
209 FP6,
210 FP7,
211 COPNUM = (FPREG + 8), /* Co-processor #1-#8 */
212 COP0 = COPNUM,
213 COP1,
214 COP2,
215 COP3,
216 COP4,
217 COP5,
218 COP6,
219 COP7,
220 PC, /* Program counter */
221 ZPC, /* Hack for Program space, but 0 addressing */
222 SR, /* Status Reg */
223 CCR, /* Condition code Reg */
224
225 /* These have to be in order for the movec instruction to work. */
226 USP, /* User Stack Pointer */
227 ISP, /* Interrupt stack pointer */
228 SFC,
229 DFC,
230 CACR,
231 VBR,
232 CAAR,
233 MSP,
234 ITT0,
235 ITT1,
236 DTT0,
237 DTT1,
238 MMUSR,
239 TC,
240 SRP,
241 URP,
242 /* end of movec ordering constraints */
243
244 FPI,
245 FPS,
246 FPC,
247
248 DRP, /* 68851 or 68030 MMU regs */
249 CRP,
250 CAL,
251 VAL,
252 SCC,
253 AC,
254 BAD,
255 BAD0 = BAD,
256 BAD1,
257 BAD2,
258 BAD3,
259 BAD4,
260 BAD5,
261 BAD6,
262 BAD7,
263 BAC,
264 BAC0 = BAC,
265 BAC1,
266 BAC2,
267 BAC3,
268 BAC4,
269 BAC5,
270 BAC6,
271 BAC7,
272 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
4134a793 273 and ACUSR on 68ec030 */
355afbcd 274 PCSR,
6d27d3a2 275
355afbcd
KR		 276 IC, /* instruction cache token */
277 DC, /* data cache token */
278 NC, /* no cache token */
279 BC, /* both caches token */
6d27d3a2 280
355afbcd
KR		 281 TT0, /* 68030 access control unit regs */
282 TT1,
283 };
7c15cbe8 284
fecd2382 285/* Internal form of an operand. */
355afbcd
KR		 286struct m68k_op
287 {
288 char *error; /* Couldn't parse it */
289 enum operand_type mode; /* What mode this instruction is in. */
290 enum _register reg; /* Base register */
291 struct m68k_exp *con1;
292 int ireg; /* Index register */
293 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
294 int imul; /* Multipy ireg by this (1,2,4,or 8) */
295 struct m68k_exp *con2;
296 };
fecd2382
RP		 297
298/* internal form of a 68020 instruction */
355afbcd
KR		 299struct m68k_it
300 {
301 char *error;
302 char *args; /* list of opcode info */
303 int numargs;
304
305 int numo; /* Number of shorts in opcode */
306 short opcode[11];
307
308 struct m68k_op operands[6];
309
310 int nexp; /* number of exprs in use */
311 struct m68k_exp exprs[4];
312
313 int nfrag; /* Number of frags we have to produce */
314 struct
315 {
316 int fragoff; /* Where in the current opcode[] the frag ends */
317 symbolS *fadd;
318 long foff;
319 int fragty;
320 }
321 fragb[4];
322
323 int nrel; /* Num of reloc strucs in use */
324 struct
325 {
326 int n;
327 symbolS *add, *sub;
328 long off;
329 char wid;
330 char pcrel;
331 }
332 reloc[5]; /* Five is enough??? */
333 };
fecd2382 334
865a2edf
MT		 335#define cpu_of_arch(x) ((x) & m68000up)
336#define float_of_arch(x) ((x) & mfloat)
337#define mmu_of_arch(x) ((x) & mmmu)
338
355afbcd 339static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 340
7c15cbe8 341/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 342
343#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
344
345/* Like addword, but goes BEFORE general operands */
346#define insop(w) {int z;\
a39116f1
RP		 347 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
348 the_ins.opcode[z]=the_ins.opcode[z-1];\
349 for(z=0;z<the_ins.nrel;z++)\
350 the_ins.reloc[z].n+=2;\
351 the_ins.opcode[opcode->m_codenum]=w;\
352 the_ins.numo++;\
f8701a3f 353 }
fecd2382
RP		 354
355
356#define add_exp(beg,end) (\
a39116f1
RP		 357 the_ins.exprs[the_ins.nexp].e_beg=beg,\
358 the_ins.exprs[the_ins.nexp].e_end=end,\
359 &the_ins.exprs[the_ins.nexp++]\
360 )
fecd2382
RP		 361
362
363/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
364#define add_fix(width,exp,pc_rel) {\
a39116f1
RP		 365 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
366 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
367 the_ins.reloc[the_ins.nrel].add=adds((exp));\
368 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
369 the_ins.reloc[the_ins.nrel].off=offs((exp));\
370 the_ins.reloc[the_ins.nrel].wid=width;\
371 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
f8701a3f 372 }
fecd2382
RP		 373
374#define add_frag(add,off,type) {\
a39116f1
RP		 375 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
376 the_ins.fragb[the_ins.nfrag].fadd=add;\
377 the_ins.fragb[the_ins.nfrag].foff=off;\
378 the_ins.fragb[the_ins.nfrag++].fragty=type;\
f8701a3f 379 }
fecd2382
RP		 380
381#define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
382
383#define seg(exp) ((exp)->e_exp.X_seg)
384#define adds(exp) ((exp)->e_exp.X_add_symbol)
385#define subs(exp) ((exp)->e_exp.X_subtract_symbol)
386#define offs(exp) ((exp)->e_exp.X_add_number)
387
388
355afbcd
KR		 389struct m68k_incant
390 {
391 char *m_operands;
392 unsigned long m_opcode;
393 short m_opnum;
394 short m_codenum;
395 int m_arch;
396 struct m68k_incant *m_next;
397 };
fecd2382 398
3ad9ec6a
ILT		 399
400
fecd2382
RP		 401#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
402#define gettwo(x) (((x)->m_opcode)&0xffff)
403
404
a87b3269 405#if __STDC__ == 1
fecd2382 406
355afbcd
KR		 407static char *crack_operand (char *str, struct m68k_op *opP);
408static int get_num (struct m68k_exp *exp, int ok);
409static int get_regs (int i, char *str, struct m68k_op *opP);
410static int reverse_16_bits (int in);
411static int reverse_8_bits (int in);
412static int try_index (char **s, struct m68k_op *opP);
413static void install_gen_operand (int mode, int val);
414static void install_operand (int mode, int val);
415static void s_bss (void);
416static void s_data1 (void);
417static void s_data2 (void);
418static void s_even (void);
419static void s_proc (void);
fecd2382 420
a87b3269 421#else /* not __STDC__ */
fecd2382 422
355afbcd
KR		 423static char *crack_operand ();
424static int get_num ();
425static int get_regs ();
426static int reverse_16_bits ();
427static int reverse_8_bits ();
428static int try_index ();
429static void install_gen_operand ();
430static void install_operand ();
431static void s_bss ();
432void s_align_bytes ();
433static void s_data1 ();
434static void s_data2 ();
435static void s_even ();
436static void s_proc ();
fecd2382 437
a87b3269 438#endif /* not __STDC__ */
fecd2382 439
df3768fb 440static int current_architecture = 0;
7c15cbe8 441
fecd2382
RP		 442/* BCC68000 is for patching in an extra jmp instruction for long offsets
443 on the 68000. The 68000 doesn't support long branches with branchs */
444
445/* This table desribes how you change sizes for the various types of variable
446 size expressions. This version only supports two kinds. */
447
448/* Note that calls to frag_var need to specify the maximum expansion needed */
449/* This is currently 10 bytes for DBCC */
450
451/* The fields are:
a39116f1
RP		 452 How far Forward this mode will reach:
453 How far Backward this mode will reach:
454 How many bytes this mode will add to the size of the frag
455 Which mode to go to if the offset won't fit in this one
456 */
fecd2382 457const relax_typeS
355afbcd
KR		 458 md_relax_table[] =
459{
460 {1, 1, 0, 0}, /* First entries aren't used */
461 {1, 1, 0, 0}, /* For no good reason except */
462 {1, 1, 0, 0}, /* that the VAX doesn't either */
463 {1, 1, 0, 0},
464
465 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
466 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
467 {0, 0, 4, 0},
468 {1, 1, 0, 0},
469
470 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
471 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
472 {0, 0, 4, 0},
473 {1, 1, 0, 0},
474
475 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
476 {(32767), (-32768), 2, TAB (PCREL, LONG)},
477 {0, 0, 4, 0},
478 {1, 1, 0, 0},
479
480 {(127), (-128), 0, TAB (BCC68000, SHORT)},
481 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
482 {0, 0, 6, 0}, /* jmp long space */
483 {1, 1, 0, 0},
484
485 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
486 {(32767), (-32768), 2, TAB (DBCC, LONG)},
487 {0, 0, 10, 0}, /* bra/jmp long space */
488 {1, 1, 0, 0},
489
490 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
491 {32767, -32768, 2, TAB (PCLEA, LONG)},
492 {0, 0, 6, 0},
493 {1, 1, 0, 0},
494
495};
fecd2382
RP		 496
497/* These are the machine dependent pseudo-ops. These are included so
498 the assembler can work on the output from the SUN C compiler, which
499 generates these.
a39116f1 500 */
fecd2382
RP		 501
502/* This table describes all the machine specific pseudo-ops the assembler
503 has to support. The fields are:
a39116f1
RP		 504 pseudo-op name without dot
505 function to call to execute this pseudo-op
506 Integer arg to pass to the function
507 */
355afbcd
KR		 508const pseudo_typeS md_pseudo_table[] =
509{
510 {"data1", s_data1, 0},
511 {"data2", s_data2, 0},
512 {"bss", s_bss, 0},
513 {"even", s_even, 0},
514 {"skip", s_space, 0},
515 {"proc", s_proc, 0},
bec66218 516#ifdef TE_SUN3
355afbcd 517 {"align", s_align_bytes, 0},
bec66218 518#endif
355afbcd 519 {0, 0, 0}
fecd2382
RP		 520};
521
522
3ad9ec6a 523/* The mote pseudo ops are put into the opcode table, since they
355afbcd 524 don't start with a . they look like opcodes to gas.
3ad9ec6a 525 */
355afbcd 526extern void obj_coff_section ();
3ad9ec6a
ILT		 527
528const pseudo_typeS mote_pseudo_table[] =
529{
530
355afbcd
KR		 531 {"dc.l", cons, 4},
532 {"dc", cons, 2},
533 {"dc.w", cons, 2},
534 {"dc.b", cons, 1},
3ad9ec6a 535
355afbcd
KR		 536 {"ds.l", s_space, 4},
537 {"ds", s_space, 2},
538 {"ds.w", s_space, 2},
539 {"ds.b", s_space, 1},
3ad9ec6a 540
355afbcd
KR		 541 {"xdef", s_globl, 0},
542 {"align", s_align_ptwo, 0},
3ad9ec6a 543#ifdef M68KCOFF
355afbcd
KR		 544 {"sect", obj_coff_section, 0},
545 {"section", obj_coff_section, 0},
3ad9ec6a
ILT		 546#endif
547 0,
548};
549
fecd2382
RP		 550/* #define isbyte(x) ((x)>=-128 && (x)<=127) */
551/* #define isword(x) ((x)>=-32768 && (x)<=32767) */
552
553#define issbyte(x) ((x)>=-128 && (x)<=127)
554#define isubyte(x) ((x)>=0 && (x)<=255)
555#define issword(x) ((x)>=-32768 && (x)<=32767)
556#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 557
fecd2382
RP		 558#define isbyte(x) ((x)>=-128 && (x)<=255)
559#define isword(x) ((x)>=-32768 && (x)<=65535)
560#define islong(x) (1)
f8701a3f
SC		 561
562extern char *input_line_pointer;
fecd2382 563
355afbcd
KR		 564enum
565 {
566 FAIL = 0,
567 OK = 1,
568 };
fecd2382
RP		 569
570/* JF these tables here are for speed at the expense of size */
571/* You can replace them with the #if 0 versions if you really
572 need space and don't mind it running a bit slower */
573
574static char mklower_table[256];
575#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 576static char notend_table[256];
fecd2382
RP		 577static char alt_notend_table[256];
578#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
a39116f1 579 alt_notend_table[(unsigned char)(s[1])])))
fecd2382
RP		 580
581#if 0
582#define mklower(c) (isupper(c) ? tolower(c) : c)
583#endif
f8701a3f
SC		 584
585
586/* JF modified this to handle cases where the first part of a symbol name
587 looks like a register */
588
589/*
590 * m68k_reg_parse() := if it looks like a register, return it's token &
591 * advance the pointer.
592 */
593
355afbcd
KR		 594enum _register
595m68k_reg_parse (ccp)
596 register char **ccp;
fecd2382 597{
f8701a3f 598 char *start = *ccp;
0069b1f6
ILT		 599 char c;
600 char *p;
601 symbolS *symbolP;
f8701a3f 602
587c4264 603#ifdef REGISTER_PREFIX
0069b1f6
ILT		 604 if (*start != REGISTER_PREFIX)
605 return FAIL;
606 p = start + 1;
607#else
608 p = start;
609 if (*p == OPTIONAL_REGISTER_PREFIX)
610 p++, start++;
587c4264 611#endif
0069b1f6
ILT		 612 if (!isalpha (*p) || !is_name_beginner (*p))
613 return FAIL;
587c4264 614
0069b1f6 615 c = *p++;
355afbcd 616 while (isalpha (c) || isdigit (c) || c == '_')
0069b1f6
ILT		 617 {
618 c = *p++;
619 }
3ad9ec6a 620
355afbcd
KR		 621 *--p = 0;
622 symbolP = symbol_find (start);
623 *p = c;
f8701a3f 624
355afbcd 625 if (symbolP && S_GET_SEGMENT (symbolP) == SEG_REGISTER)
a39116f1 626 {
f8701a3f 627 *ccp = p;
355afbcd 628 return S_GET_VALUE (symbolP);
a39116f1 629 }
f8701a3f 630
0069b1f6 631 return FAIL;
fecd2382
RP		 632}
633
634#define SKIP_WHITE() { str++; if(*str==' ') str++;}
3ad9ec6a
ILT		 635#define SKIP_W() { ss++; if(*ss==' ') ss++;}
636
637/* Parse an index specification using Motorola syntax. */
638
639static int
355afbcd
KR		 640try_moto_index (s, opP)
641 char **s;
642 struct m68k_op *opP;
3ad9ec6a 643{
355afbcd
KR		 644 register int i;
645 char *ss;
646
647 ss = *s;
648 /* SKIP_W(); */
649 if (*ss == ' ')
650 ss++;
651 i = m68k_reg_parse (&ss);
652 if (!(i >= DATA + 0 && i <= ADDR + 7))
653 { /* if i is not DATA or ADDR reg */
654 opP->error = "Invalid index register";
655 *s = ss;
656 return FAIL;
657 }
658 opP->ireg = i;
659 /* SKIP_W(); */
660 if (*ss == ')')
661 {
662 opP->isiz = 0;
663 opP->imul = 1;
664 SKIP_W ();
665 *s = ss;
666 return OK;
667 }
668 if (*ss != '.')
669 {
670 opP->error = "Missing . in index register";
671 *s = ss;
672 return FAIL;
673 }
674 SKIP_W ();
675 if (mklower (*ss) == 'w')
676 opP->isiz = 2;
677 else if (mklower (*ss) == 'l')
678 opP->isiz = 3;
679 else
680 {
681 opP->error = "Size spec not .W or .L";
682 *s = ss;
683 return FAIL;
684 }
685 SKIP_W ();
686 if (*ss == '.' || *ss == '*')
687 {
688 SKIP_W ();
689 switch (*ss)
690 {
691 case '1':
692 case '2':
693 case '4':
694 case '8':
695 opP->imul = *ss - '0';
696 break;
697 default:
698 opP->error = "index multiplier not 1, 2, 4 or 8";
699 *s = ss;
700 return FAIL;
3ad9ec6a 701 }
355afbcd
KR		 702 SKIP_W ();
703 }
704 else
705 opP->imul = 1;
706 if (*ss != ')')
707 {
708 opP->error = "Missing )";
709 *s = ss;
710 return FAIL;
711 }
712 SKIP_W ();
713 *s = ss;
714 return OK;
3ad9ec6a 715}
fecd2382 716
7c15cbe8 717/*
3ad9ec6a
ILT		 718 *
719 * try_index := data_or_address_register + ')' + SKIP_W
720 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
721 *
722 * multiplier := <empty>
723 * | ':' + multiplier_number
7c15cbe8 724 * ;
6d27d3a2 725 *
3ad9ec6a 726 * multiplier_number := '1' | '2' | '4' | '8' ;
7c15cbe8 727 *
3ad9ec6a
ILT		 728 * size_spec := 'l' | 'L' | 'w' | 'W' ;
729 *
730 * SKIP_W := <empty> | ' ' ;
7c15cbe8
RP		 731 *
732 */
733
355afbcd
KR		 734static int
735try_index (s, opP)
736 char **s;
737 struct m68k_op *opP;
3ad9ec6a 738{
355afbcd
KR		 739 register int i;
740 char *ss;
741
742 ss = *s;
743 /* SKIP_W(); */
744 i = m68k_reg_parse (&ss);
745 if (!(i >= DATA + 0 && i <= ADDR + 7))
746 { /* if i is not DATA or ADDR reg */
747 *s = ss;
748 return FAIL;
749 }
750 opP->ireg = i;
751 /* SKIP_W(); */
752 if (*ss == ')')
753 {
754 opP->isiz = 0;
755 opP->imul = 1;
756 SKIP_W ();
757 *s = ss;
758 return OK;
759 }
760 if (*ss != ':')
761 {
762 opP->error = "Missing : in index register";
763 *s = ss;
764 return FAIL;
765 }
766 SKIP_W ();
767 switch (*ss)
768 {
769 case 'w':
770 case 'W':
771 opP->isiz = 2;
772 break;
773 case 'l':
774 case 'L':
775 opP->isiz = 3;
776 break;
777 default:
778 opP->error = "Index register size spec not :w or :l";
779 *s = ss;
780 return FAIL;
781 }
782 SKIP_W ();
783 if (*ss == ':')
784 {
785 SKIP_W ();
786 switch (*ss)
787 {
788 case '1':
789 case '2':
790 case '4':
791 case '8':
792 if (cpu_of_arch (current_architecture) < m68020)
793 {
794 opP->error = "no index scaling in pre-68020's";
795 *s = ss;
796 return FAIL;
797 }
798 opP->imul = *ss - '0';
799 break;
3ad9ec6a 800 default:
355afbcd
KR		 801 opP->error = "index multiplier not 1, 2, 4 or 8";
802 *s = ss;
803 return FAIL;
3ad9ec6a 804 }
355afbcd
KR		 805 SKIP_W ();
806 }
807 else
808 opP->imul = 1;
809 if (*ss != ')')
810 {
811 opP->error = "Missing )";
812 *s = ss;
813 return FAIL;
814 }
815 SKIP_W ();
816 *s = ss;
817 return OK;
818} /* try_index() */
3ad9ec6a
ILT		 819
820/* Ian Taylor expanded this function to accept both MIT and Motorola
821 syntax. I removed the old comment, since it was wrong. The syntax
822 this accepted even before my changes was complex and undocumented.
823 I mainly added a large case when the operand string does not
824 contain an '@', since the Motorola syntax does not use the '@'
825 character. */
826
fecd2382 827int
355afbcd
KR		 828m68k_ip_op (str, opP)
829 char *str;
830 register struct m68k_op *opP;
fecd2382 831{
355afbcd
KR		 832 char *strend;
833 long i;
834 char *parse_index ();
835 int needp;
3ad9ec6a 836
355afbcd
KR		 837 if (*str == ' ')
838 {
839 str++;
840 } /* Find the beginning of the string */
6d27d3a2 841
355afbcd
KR		 842 if (!*str)
843 {
844 opP->error = "Missing operand";
845 return FAIL;
846 } /* Out of gas */
6d27d3a2 847
355afbcd
KR		 848 for (strend = str; *strend; strend++)
849 ;
850 --strend;
6d27d3a2 851
355afbcd
KR		 852 if (*str == '#')
853 {
854 str++;
855 opP->con1 = add_exp (str, strend);
856 opP->mode = IMMED;
857 return OK;
858 } /* Guess what: A constant. Shar and enjoy */
6d27d3a2 859
355afbcd 860 i = m68k_reg_parse (&str);
6d27d3a2 861
355afbcd
KR		 862 if (i != FAIL)
863 {
864 if (*str == '/' || *str == '-')
865 {
866 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
867 opP->mode = REGLST;
868 return get_regs (i, str, opP);
869 }
870 if (*str == '\0')
871 {
872 opP->reg = i;
873 /* "Rn" Register Direct mode */
874 if (i >= DATA + 0 && i <= DATA + 7)
875 opP->mode = DREG;
876 else if (i >= ADDR + 0 && i <= ADDR + 7)
877 opP->mode = AREG;
878 else
879 opP->mode = MSCR;
880 return OK;
881 }
882 }
6d27d3a2 883
355afbcd
KR		 884 if (*str != '@')
885 {
886 char *stmp;
6d27d3a2 887
355afbcd
KR		 888 if ((stmp = strchr (str, '@')) != 0)
889 {
890 opP->con1 = add_exp (str, stmp - 1);
891 if (stmp == strend)
892 {
893 opP->mode = AINDX;
894 return (OK);
895 }
6d27d3a2 896
355afbcd
KR		 897 if ((current_architecture & m68020up) == 0)
898 {
899 return (FAIL);
900 } /* if target is not a '20 or better */
6d27d3a2 901
355afbcd
KR		 902 stmp++;
903 if (*stmp++ != '(' || *strend-- != ')')
904 {
905 opP->error = "Malformed operand";
906 return (FAIL);
907 }
908 i = try_index (&stmp, opP);
909 opP->con2 = add_exp (stmp, strend);
6d27d3a2 910
355afbcd
KR		 911 if (i == FAIL)
912 {
913 opP->mode = AMIND;
914 }
915 else
916 {
917 opP->mode = APODX;
918 }
919 return (OK);
920 } /* if there's an '@' */
6d27d3a2 921
3ad9ec6a 922#ifndef MIT_SYNTAX_ONLY
355afbcd 923 /* The operand has no '@'. Try to parse it using
3ad9ec6a 924 Motorola syntax. */
355afbcd 925 /* Logic of the parsing switch(*str):
3ad9ec6a
ILT		 926 case opP->mode =
927 ---- -----------
928 #anything IMMED 1
929 REG AREG or DREG or MSCR 3 or 2 or 13
930 REG- or REG/ REGLST 14
931 (REG) AINDR 4
932 (REG)+ AINC 6
933 (REG,INDX) AINDX 8
934 (EXPR,REG) AOFF 7
935 (EXPR,REG,INDX) AINDX 8
936 -(REG) ADEC 5
937 EXP2(REG) AOFF 7
938 EXP2(REG,INDX) AINDX 8
939 EXP2 ABSL 12
940
941 REG means truth(m68k_reg_parse(&str))
942 INDX means truth(try_moto_index(&str,opP))
943 EXPR means not REG
944 EXP2 means not REG and not '(' and not '-('
945 */
946
355afbcd
KR		 947 if (*str == '(')
948 {
949 str++;
950 i = m68k_reg_parse (&str);
951 if ((i < ADDR + 0 || i > ADDR + 7)
952 && (i < DATA + 0 || i > DATA + 7
953 || *str != ')' || str[1] != '0')
954 && i != PC && i != ZPC && i != FAIL)
955 {
956 /* Can't indirect off non address regs */
957 opP->error = "Invalid indirect register";
958 return FAIL;
959 }
960 if (i != FAIL)
961 {
962 opP->reg = i;
963 if (*str == ')')
964 {
965 str++;
966 if (*str == '\0')
967 {
968 /* "(An)" Address Register Indirect mode
3ad9ec6a 969 or "(Dn)" for cas2. */
355afbcd
KR		 970 if (i >= DATA + 0 && i <= DATA + 7)
971 opP->mode = DINDR;
972 else
973 opP->mode = AINDR;
974 return OK;
975 }
976 if (*str == '+')
977 {
978 if (str[1] == '\0')
979 {
980 /* "(An)+" Register Indirect w Postincrement */
981 opP->mode = AINC;
982 return OK;
983 }
984 }
985 opP->error = "Junk after indirect";
986 return FAIL;
987 }
988 if (*str == ',')
989 {
990 str++;
991 i = try_moto_index (&str, opP);
992 if (i == FAIL)
993 return FAIL;
994 /* "(An,Rn)" Register Indirect with Index mode*/
995 opP->mode = AINDX;
996 return OK;
997 }
998 else
999 {
1000 opP->error = "Bad indirect syntax";
1001 return FAIL;
1002 }
1003 }
1004 else
1005 {
1006 /* "(EXPR,..." , a displacement */
1007 char *stmp;
1008 char *index ();
1009
1010 if (stmp = index (str, ','))
1011 {
1012 opP->con1 = add_exp (str, stmp - 1);
1013 str = stmp;
1014 SKIP_WHITE ();
1015 i = m68k_reg_parse (&str);
1016 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1017 {
1018 /* Can't indirect off non address regs */
1019 opP->error = "Invalid indirect register";
1020 return FAIL;
1021 }
1022 if (i != FAIL)
1023 {
1024 opP->reg = i;
1025 if (*str == ')')
1026 {
1027 /* "(d,An)" Register Indirect w Displacement */
1028 opP->mode = AOFF;
1029 return OK;
1030 }
1031 if (*str == ',')
1032 {
1033 str++;
1034 i = try_moto_index (&str, opP);
1035 if (i == FAIL)
1036 return FAIL;
1037 /* "(d,An,Rn)" Register Indirect with Index */
1038 opP->mode = AINDX;
1039 return OK;
1040 }
1041 else
1042 {
1043 opP->error = "Bad indirect syntax";
1044 return FAIL;
1045 }
1046 }
1047 else
1048 {
1049 opP->error = "Invalid register";
1050 return FAIL;
1051 }
1052 }
1053 else
1054 {
1055 opP->mode = ABSL;
1056 opP->con1 = add_exp (str - 1, strend);
1057 return OK;
1058 }
1059 }
1060 }
6d27d3a2 1061
355afbcd
KR		 1062 if (*str == '-')
1063 {
1064 if (str[1] == '(')
1065 {
1066 str = str + 2;
1067 i = m68k_reg_parse (&str);
1068 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1069 {
1070 /* Can't indirect off non address regs */
1071 opP->error = "Invalid indirect register";
1072 return FAIL;
1073 }
1074 if (i != FAIL)
1075 {
1076 opP->reg = i;
1077 if (*str == ')')
1078 {
1079 str++;
1080 if (*str == '\0')
1081 {
1082 /* "-(An)" Register Indirect with Predecrement */
1083 opP->mode = ADEC;
1084 return OK;
1085 }
1086 opP->error = "Junk after indirect";
1087 return FAIL;
1088 }
1089 opP->error = "Bad indirect syntax";
1090 return FAIL;
1091 }
1092 opP->mode = ABSL;
1093 opP->con1 = add_exp (str - 2, strend);
1094 return OK;
1095 }
1096 /* if '-' but not "-(', do nothing */
1097 }
1098
1099 /* whether *str=='-' or not */
1100 {
1101 /* "EXP2" or "EXP2(REG..." */
1102 char *stmp;
1103 char *index ();
1104 if (stmp = index (str, '('))
1105 {
1106 char *ostr = str;
3ad9ec6a 1107
355afbcd
KR		 1108 opP->con1 = add_exp (str, stmp - 1);
1109 str = stmp + 1;
1110 i = m68k_reg_parse (&str);
1111 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1112 && i != ZPC && i != FAIL)
1113 {
1114 /* Can't indirect off non address regs */
1115 opP->error = "Invalid indirect register";
1116 return FAIL;
1117 }
1118 if (i != FAIL)
1119 {
1120 opP->reg = i;
1121 if (*str == ')')
3ad9ec6a 1122 {
355afbcd
KR		 1123 /* "d(An)" Register Indirect w Displacement */
1124 opP->mode = AOFF;
1125 return OK;
3ad9ec6a 1126 }
355afbcd
KR		 1127 if (*str == ',')
1128 {
1129 str++;
1130 i = try_moto_index (&str, opP);
1131 if (i == FAIL)
1132 return FAIL;
1133 /* "d(An,Rn)" Register Indirect with Index */
1134 opP->mode = AINDX;
1135 return OK;
1136 }
1137 else
1138 {
1139 opP->error = "Bad indirect syntax";
1140 return FAIL;
1141 }
1142 }
1143 else
1144 {
1145 opP->mode = ABSL;
1146 opP->con1 = add_exp (ostr, strend);
f8701a3f 1147 return OK;
3ad9ec6a 1148 }
355afbcd
KR		 1149 }
1150 else
1151 {
1152 /* "EXP2" Absolute */
1153 opP->mode = ABSL;
1154 opP->isiz = 0;
1155 if (strend[-1] == '.' || strend[-1] == ':')
1156 {
1157 /* mode ==foo.[wl] */
1158 switch (*strend)
1159 {
1160 case 'w':
1161 case 'W':
1162 opP->isiz = 2;
1163 strend -= 2;
1164 break;
1165 case 'l':
1166 case 'L':
1167 opP->isiz = 3;
1168 strend -= 2;
1169 break;
1170 }
1171 }
1172 opP->con1 = add_exp (str, strend);
1173 return OK;
1174 }
1175 }
1176 /*NOTREACHED*/
1177#else /* defined (MIT_SYNTAX_ONLY) */
1178 opP->mode = ABSL;
1179 opP->con1 = add_exp (str, strend);
1180 return OK;
1181#endif /* defined (MIT_SYNTAX_ONLY) */
1182 }
3ad9ec6a 1183
355afbcd 1184 opP->reg = i;
6d27d3a2 1185
355afbcd
KR		 1186 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1187 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1188 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1189 {
1190 opP->error = "Invalid indirect register";
1191 return FAIL;
1192 }
1193 know (*str == '@');
6d27d3a2 1194
355afbcd
KR		 1195 str++;
1196 switch (*str)
1197 {
1198 case '\0':
1199 if (i < DATA + 0 || i > DATA + 7)
1200 opP->mode = AINDR;
1201 else
1202 opP->mode = DINDR;
1203 return OK;
1204 case '-':
1205 opP->mode = ADEC;
1206 return OK;
1207 case '+':
1208 opP->mode = AINC;
1209 return OK;
1210 case '(':
1211 str++;
1212 break;
1213 default:
1214 opP->error = "Junk after indirect";
1215 return FAIL;
1216 }
1217 /* Some kind of indexing involved. Lets find out how bad it is */
1218 i = try_index (&str, opP);
1219 /* Didn't start with an index reg, maybe its offset or offset,reg */
1220 if (i == FAIL)
1221 {
1222 char *beg_str;
1223
1224 beg_str = str;
1225 for (i = 1; i;)
1226 {
1227 switch (*str++)
1228 {
1229 case '\0':
1230 opP->error = "Missing )";
1231 return FAIL;
1232 case ',':
1233 i = 0;
1234 break;
1235 case '(':
1236 i++;
1237 break;
1238 case ')':
1239 --i;
1240 break;
1241 }
fecd2382 1242 }
355afbcd 1243 /* if(str[-3]==':') {
f8701a3f 1244 int siz;
6d27d3a2 1245
f8701a3f
SC		 1246 switch(str[-2]) {
1247 case 'b':
1248 case 'B':
1249 siz=1;
1250 break;
1251 case 'w':
1252 case 'W':
1253 siz=2;
1254 break;
1255 case 'l':
1256 case 'L':
1257 siz=3;
1258 break;
1259 default:
1260 opP->error="Specified size isn't :w or :l";
1261 return FAIL;
1262 }
1263 opP->con1=add_exp(beg_str,str-4);
1264 opP->con1->e_siz=siz;
1265 } else */
355afbcd
KR		 1266 opP->con1 = add_exp (beg_str, str - 2);
1267 /* Should be offset,reg */
1268 if (str[-1] == ',')
1269 {
1270 i = try_index (&str, opP);
1271 if (i == FAIL)
1272 {
1273 opP->error = "Malformed index reg";
1274 return FAIL;
1275 }
f8701a3f 1276 }
355afbcd
KR		 1277 }
1278 /* We've now got offset) offset,reg) or reg) */
1279
1280 if (*str == '\0')
1281 {
1282 /* Th-the-thats all folks */
1283 if (opP->reg == FAIL)
1284 opP->mode = AINDX; /* Other form of indirect */
1285 else if (opP->ireg == FAIL)
1286 opP->mode = AOFF;
1287 else
1288 opP->mode = AINDX;
1289 return (OK);
1290 }
1291 /* Next thing had better be another @ */
1292 if (*str == '@')
1293 {
1294 if (str[1] == '(')
1295 {
1296 needp = 1;
1297 str += 2;
f8701a3f 1298 }
355afbcd
KR		 1299 else
1300 {
1301 needp = 0;
1302 str++;
fecd2382 1303 }
355afbcd 1304 }
6d27d3a2 1305
355afbcd
KR		 1306 if ((current_architecture & m68020up) == 0)
1307 {
1308 return (FAIL);
1309 } /* if target is not a '20 or better */
6d27d3a2
KR		 1310
1311
355afbcd
KR		 1312 if (opP->ireg != FAIL)
1313 {
1314 opP->mode = APRDX;
6d27d3a2 1315
355afbcd
KR		 1316 i = try_index (&str, opP);
1317 if (i != FAIL)
1318 {
1319 opP->error = "Two index registers! not allowed!";
1320 return (FAIL);
865a2edf 1321 }
355afbcd
KR		 1322 }
1323 else
1324 {
1325 i = try_index (&str, opP);
1326 }
6d27d3a2 1327
355afbcd
KR		 1328 if (i == FAIL)
1329 {
1330 char *beg_str;
6d27d3a2 1331
355afbcd 1332 beg_str = str;
6d27d3a2 1333
355afbcd
KR		 1334 for (i = 1; i;)
1335 {
1336 switch (*str++)
1337 {
1338 case '\0':
1339 if (needp)
1340 opP->error = "Missing )";
1341 return (FAIL);
1342 break;
1343 case ',':
1344 i = 0;
1345 break;
1346 case '(':
1347 i++;
1348 break;
1349 case ')':
1350 --i;
1351 break;
1352 }
1353 }
6d27d3a2 1354
355afbcd 1355 opP->con2 = add_exp (beg_str, str - 2);
6d27d3a2 1356
355afbcd
KR		 1357 if (str[-1] == ',')
1358 {
1359 if (opP->ireg != FAIL)
1360 {
1361 opP->error = "Can't have two index regs";
1362 return (FAIL);
1363 }
6d27d3a2 1364
355afbcd 1365 i = try_index (&str, opP);
6d27d3a2 1366
355afbcd
KR		 1367 if (i == FAIL)
1368 {
1369 opP->error = "malformed index reg";
1370 return (FAIL);
1371 }
6d27d3a2 1372
355afbcd 1373 opP->mode = APODX;
f8701a3f 1374 }
355afbcd
KR		 1375 else if (opP->ireg != FAIL)
1376 {
1377 opP->mode = APRDX;
1378 }
1379 else
1380 {
1381 opP->mode = AMIND;
f8701a3f 1382 }
355afbcd
KR		 1383 }
1384 else
1385 {
1386 opP->mode = APODX;
1387 }
1388
1389 if (*str != '\0')
1390 {
1391 opP->error = "Junk after indirect";
1392 return FAIL;
1393 }
1394 return (OK);
1395} /* m68k_ip_op() */
fecd2382 1396
7c15cbe8 1397
3ad9ec6a
ILT		 1398#ifdef M68KCOFF
1399
355afbcd
KR		 1400short
1401tc_coff_fix2rtype (fixP)
1402 fixS *fixP;
fecd2382 1403{
355afbcd
KR		 1404 return (fixP->fx_pcrel ?
1405 (fixP->fx_size == 1 ? R_PCRBYTE :
1406 fixP->fx_size == 2 ? R_PCRWORD :
1407 R_PCRLONG) :
1408 (fixP->fx_size == 1 ? R_RELBYTE :
1409 fixP->fx_size == 2 ? R_RELWORD :
1410 R_RELLONG));
6d27d3a2 1411
3ad9ec6a
ILT		 1412
1413}
1414
1415#endif
fecd2382 1416
355afbcd
KR		 1417#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1418main ()
fecd2382 1419{
355afbcd
KR		 1420 char buf[128];
1421 struct m68k_op thark;
6d27d3a2 1422
355afbcd
KR		 1423 for (;;)
1424 {
1425 if (!gets (buf))
1426 break;
1427 memset (&thark, '\0', sizeof (thark));
1428 if (!m68k_ip_op (buf, &thark))
1429 printf ("FAIL:");
1430 if (thark.error)
1431 printf ("op1 error %s in %s\n", thark.error, buf);
1432 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1433 if (thark.b_const)
1434 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1435 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1436 if (thark.b_iadd)
1437 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1438 printf ("\n");
1439 }
1440 exit (0);
fecd2382
RP		 1441}
1442
1443#endif
1444
1445
355afbcd 1446static struct hash_control *op_hash = NULL; /* handle of the OPCODE hash table
a39116f1
RP		 1447 NULL means any use before m68k_ip_begin()
1448 will crash */
fecd2382 1449\f
355afbcd 1450
fecd2382 1451/*
7c15cbe8 1452 * m 6 8 k _ i p ( )
fecd2382
RP		 1453 *
1454 * This converts a string into a 68k instruction.
1455 * The string must be a bare single instruction in sun format
1456 * with RMS-style 68020 indirects
1457 * (example: )
1458 *
1459 * It provides some error messages: at most one fatal error message (which
1460 * stops the scan) and at most one warning message for each operand.
1461 * The 68k instruction is returned in exploded form, since we have no
1462 * knowledge of how you parse (or evaluate) your expressions.
1463 * We do however strip off and decode addressing modes and operation
1464 * mnemonic.
1465 *
1466 * This function's value is a string. If it is not "" then an internal
1467 * logic error was found: read this code to assign meaning to the string.
1468 * No argument string should generate such an error string:
1469 * it means a bug in our code, not in the user's text.
1470 *
7c15cbe8 1471 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
fecd2382
RP		 1472 * this function.
1473 */
1474
1475/* JF this function no longer returns a useful value. Sorry */
355afbcd
KR		 1476void
1477m68k_ip (instring)
6d27d3a2 1478 char *instring;
fecd2382 1479{
6d27d3a2
KR		 1480 register char *p;
1481 register struct m68k_op *opP;
1482 register struct m68k_incant *opcode;
1483 register char *s;
1484 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 1485 char *pdot, *pdotmove;
6d27d3a2 1486 int siz1, siz2;
355afbcd
KR		 1487 char c;
1488 int losing;
1489 int opsfound;
1490 char *crack_operand ();
6d27d3a2
KR		 1491 LITTLENUM_TYPE words[6];
1492 LITTLENUM_TYPE *wordp;
8be74775 1493 unsigned long ok_arch = 0;
6d27d3a2
KR		 1494
1495 if (*instring == ' ')
1496 instring++; /* skip leading whitespace */
1497
1498 /* Scan up to end of operation-code, which MUST end in end-of-string
1499 or exactly 1 space. */
3ad9ec6a 1500 pdot = 0;
355afbcd
KR		 1501 for (p = instring; *p != '\0'; p++)
1502 {
1503 if (*p == ' ')
1504 break;
1505 if (*p == '.')
1506 pdot = p;
1507 }
6d27d3a2 1508
355afbcd
KR		 1509 if (p == instring)
1510 {
1511 the_ins.error = "No operator";
1512 the_ins.opcode[0] = NULL;
1513 /* the_ins.numo=1; */
1514 return;
1515 }
6d27d3a2
KR		 1516
1517 /* p now points to the end of the opcode name, probably whitespace.
1518 make sure the name is null terminated by clobbering the whitespace,
3ad9ec6a
ILT		 1519 look it up in the hash table, then fix it back.
1520 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 1521 if (pdot != NULL)
1522 {
1523 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1524 *pdotmove = pdotmove[1];
1525 p--;
1526 }
3ad9ec6a 1527
6d27d3a2
KR		 1528 c = *p;
1529 *p = '\0';
355afbcd 1530 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 1531 *p = c;
1532
355afbcd
KR		 1533 if (pdot != NULL)
1534 {
1535 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1536 *pdotmove = pdotmove[-1];
1537 *pdot = '.';
1538 ++p;
1539 }
3ad9ec6a 1540
355afbcd
KR		 1541 if (opcode == NULL)
1542 {
1543 the_ins.error = "Unknown operator";
1544 the_ins.opcode[0] = NULL;
1545 /* the_ins.numo=1; */
1546 return;
1547 }
6d27d3a2
KR		 1548
1549 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 1550 while (*p == ' ')
1551 ++p;
6d27d3a2 1552
3ad9ec6a 1553
355afbcd
KR		 1554 if (opcode->m_operands == 0)
1555 {
1556 char *old = input_line_pointer;
1557 *old = '\n';
1558 input_line_pointer = p;
1559 /* Ahh - it's a motorola style psuedo op */
1560 mote_pseudo_table[opcode->m_opnum].poc_handler
1561 (mote_pseudo_table[opcode->m_opnum].poc_val);
1562 input_line_pointer = old;
1563 *old = 0;
3ad9ec6a 1564
355afbcd
KR		 1565 return;
1566 }
3ad9ec6a 1567
355afbcd
KR		 1568 for (opP = &the_ins.operands[0]; *p; opP++)
1569 {
6d27d3a2 1570
355afbcd 1571 p = crack_operand (p, opP);
6d27d3a2 1572
355afbcd
KR		 1573 if (opP->error)
1574 {
1575 the_ins.error = opP->error;
1576 return;
1577 }
6d27d3a2 1578 }
6d27d3a2
KR		 1579
1580 opsfound = opP - &the_ins.operands[0];
1581
1582 /* This ugly hack is to support the floating pt opcodes in their standard form */
1583 /* Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 1584 if (opcode->m_operands[0] == 'I')
1585 {
1586 int n;
6d27d3a2 1587
355afbcd
KR		 1588 for (n = opsfound; n > 0; --n)
1589 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 1590
355afbcd
KR		 1591 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1592 the_ins.operands[0].mode = MSCR;
1593 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1594 opsfound++;
1595 }
6d27d3a2
KR		 1596
1597 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 1598 for (losing = 0;;)
1599 {
1600 /* if we didn't get the right number of ops,
6d27d3a2
KR		 1601 or we have no common model with this pattern
1602 then reject this pattern. */
1603
355afbcd
KR		 1604 if (opsfound != opcode->m_opnum
1605 || ((opcode->m_arch & current_architecture) == 0))
1606 {
1607 ++losing;
1608 ok_arch |= opcode->m_arch;
1609 }
1610 else
1611 {
1612 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1613 {
1614 /* Warning: this switch is huge! */
1615 /* I've tried to organize the cases into this order:
8be74775
KR		 1616 non-alpha first, then alpha by letter. lower-case goes directly
1617 before uppercase counterpart. */
355afbcd 1618 /* Code with multiple case ...: gets sorted by the lowest case ...
8be74775 1619 it belongs to. I hope this makes sense. */
355afbcd
KR		 1620 switch (*s)
1621 {
1622 case '!':
1623 if (opP->mode == MSCR || opP->mode == IMMED
1624 || opP->mode == DREG || opP->mode == AREG
1625 || opP->mode == AINC || opP->mode == ADEC
1626 || opP->mode == REGLST)
1627 losing++;
1628 break;
1629
1630 case '`':
1631 switch (opP->mode)
1632 {
1633 case MSCR:
1634 case IMMED:
1635 case DREG:
1636 case AREG:
1637 case AINC:
1638 case REGLST:
1639 case AINDR:
1640 losing++;
1641 }
1642 break;
8be74775 1643
355afbcd
KR		 1644 case '#':
1645 if (opP->mode != IMMED)
1646 losing++;
1647 else
1648 {
1649 long t;
1650
1651 t = get_num (opP->con1, 80);
1652 if (s[1] == 'b' && !isbyte (t))
1653 losing++;
1654 else if (s[1] == 'w' && !isword (t))
1655 losing++;
1656 }
1657 break;
1658
1659 case '^':
1660 case 'T':
1661 if (opP->mode != IMMED)
1662 losing++;
1663 break;
1664
1665 case '$':
1666 if (opP->mode == MSCR || opP->mode == AREG ||
1667 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1668 losing++;
1669 break;
1670
1671 case '%':
1672 if (opP->mode == MSCR || opP->reg == PC ||
1673 opP->reg == ZPC || opP->mode == REGLST)
1674 losing++;
1675 break;
1676
1677
1678 case '&':
1679 if (opP->mode == MSCR || opP->mode == DREG ||
1680 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1681 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1682 losing++;
1683 break;
1684
1685 case '*':
1686 if (opP->mode == MSCR || opP->mode == REGLST)
1687 losing++;
1688 break;
1689
1690 case '+':
1691 if (opP->mode != AINC)
1692 losing++;
1693 break;
1694
1695 case '-':
1696 if (opP->mode != ADEC)
1697 losing++;
1698 break;
1699
1700 case '/':
1701 if (opP->mode == MSCR || opP->mode == AREG ||
1702 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1703 losing++;
1704 break;
1705
1706 case ';':
1707 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1708 losing++;
1709 break;
1710
1711 case '?':
1712 if (opP->mode == MSCR || opP->mode == AREG ||
1713 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1714 opP->reg == ZPC || opP->mode == REGLST)
1715 losing++;
1716 break;
1717
1718 case '@':
1719 if (opP->mode == MSCR || opP->mode == AREG ||
1720 opP->mode == IMMED || opP->mode == REGLST)
1721 losing++;
1722 break;
1723
1724 case '~': /* For now! (JF FOO is this right?) */
1725 if (opP->mode == MSCR || opP->mode == DREG ||
1726 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1727 losing++;
1728 break;
1729
1730 case '3':
1731 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1732 losing++;
1733 break;
1734
1735 case 'A':
1736 if (opP->mode != AREG)
1737 losing++;
1738 break;
1739 case 'a':
1740 if (opP->mode != AINDR)
1741 {
1742 ++losing;
1743 } /* if not address register indirect */
1744 break;
1745 case 'B': /* FOO */
1746 if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j'
1747 && instring[1] == 'b'
1748 && instring[2] == 's'
1749 && instring[3] == 'r'))
1750 losing++;
1751 break;
1752
1753 case 'C':
1754 if (opP->mode != MSCR || opP->reg != CCR)
1755 losing++;
1756 break;
1757
1758 case 'd': /* FOO This mode is a KLUDGE!! */
1759 if (opP->mode != AOFF && (opP->mode != ABSL ||
1760 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1761 losing++;
1762 break;
1763
1764 case 'D':
1765 if (opP->mode != DREG)
1766 losing++;
1767 break;
1768
1769 case 'F':
1770 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1771 losing++;
1772 break;
1773
1774 case 'I':
1775 if (opP->mode != MSCR || opP->reg < COPNUM ||
1776 opP->reg >= COPNUM + 7)
1777 losing++;
1778 break;
1779
1780 case 'J':
1781 if (opP->mode != MSCR
1782 || opP->reg < USP
1783 || opP->reg > URP
1784 || cpu_of_arch (current_architecture) < m68010 /* before 68010 had none */
1785 || (cpu_of_arch (current_architecture) < m68020
1786 && opP->reg != SFC
1787 && opP->reg != DFC
1788 && opP->reg != USP
1789 && opP->reg != VBR) /* 68010's had only these */
1790 || (cpu_of_arch (current_architecture) < m68040
1791 && opP->reg != SFC
1792 && opP->reg != DFC
1793 && opP->reg != USP
1794 && opP->reg != VBR
1795 && opP->reg != CACR
1796 && opP->reg != CAAR
1797 && opP->reg != MSP
1798 && opP->reg != ISP) /* 680[23]0's have only these */
1799 || (cpu_of_arch (current_architecture) == m68040 /* 68040 has all but this */
1800 && opP->reg == CAAR))
1801 {
1802 losing++;
1803 } /* doesn't cut it */
1804 break;
1805
1806 case 'k':
1807 if (opP->mode != IMMED)
1808 losing++;
1809 break;
8be74775 1810
355afbcd
KR		 1811 case 'l':
1812 case 'L':
1813 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1814 {
1815 if (s[1] == '8')
1816 losing++;
1817 else
1818 {
1819 opP->mode = REGLST;
1820 opP->reg = 1 << (opP->reg - DATA);
1821 }
1822 }
1823 else if (opP->mode != REGLST)
1824 {
1825 losing++;
1826 }
1827 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1828 losing++;
1829 else if (s[1] == '3' && opP->reg & 0x7000000)
1830 losing++;
1831 break;
1832
1833 case 'M':
1834 if (opP->mode != IMMED)
1835 losing++;
1836 else
1837 {
1838 long t;
6d27d3a2 1839
355afbcd
KR		 1840 t = get_num (opP->con1, 80);
1841 if (!issbyte (t) || isvar (opP->con1))
1842 losing++;
1843 }
1844 break;
8be74775 1845
355afbcd
KR		 1846 case 'O':
1847 if (opP->mode != DREG && opP->mode != IMMED)
1848 losing++;
1849 break;
6d27d3a2 1850
355afbcd
KR		 1851 case 'Q':
1852 if (opP->mode != IMMED)
1853 losing++;
1854 else
1855 {
1856 long t;
6d27d3a2 1857
355afbcd
KR		 1858 t = get_num (opP->con1, 80);
1859 if (t < 1 || t > 8 || isvar (opP->con1))
1860 losing++;
1861 }
1862 break;
8be74775 1863
355afbcd
KR		 1864 case 'R':
1865 if (opP->mode != DREG && opP->mode != AREG)
1866 losing++;
1867 break;
8be74775 1868
355afbcd
KR		 1869 case 'r':
1870 if (opP->mode != AINDR && opP->mode != DINDR)
1871 losing++;
1872 break;
c50140c8 1873
355afbcd
KR		 1874 case 's':
1875 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1876 losing++;
1877 break;
8be74775 1878
355afbcd
KR		 1879 case 'S':
1880 if (opP->mode != MSCR || opP->reg != SR)
1881 losing++;
1882 break;
8be74775 1883
355afbcd
KR		 1884 case 't':
1885 if (opP->mode != IMMED)
1886 losing++;
1887 else
1888 {
1889 long t = get_num (opP->con1, 80);
1890 if (t < 0 || t > 7 || isvar (opP->con1))
1891 losing++;
1892 }
1893 break;
4134a793 1894
355afbcd
KR		 1895 case 'U':
1896 if (opP->mode != MSCR || opP->reg != USP)
1897 losing++;
1898 break;
8be74775 1899
355afbcd 1900 /* JF these are out of order. We could put them
8be74775 1901 in order if we were willing to put up with
4134a793
KR		 1902 bunches of #ifdef m68851s in the code.
1903
1904 Don't forget that you need these operands
1905 to use 68030 MMU instructions. */
f8701a3f 1906#ifndef NO_68851
355afbcd
KR		 1907 /* Memory addressing mode used by pflushr */
1908 case '|':
1909 if (opP->mode == MSCR || opP->mode == DREG ||
1910 opP->mode == AREG || opP->mode == REGLST)
1911 losing++;
1912 break;
1913
1914 case 'f':
1915 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1916 losing++;
1917 break;
1918
1919 case 'P':
1920 if (opP->mode != MSCR
1921 || (opP->reg != TC && opP->reg != CAL
1922 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1923 losing++;
1924 break;
1925
1926 case 'V':
1927 if (opP->reg != VAL)
1928 losing++;
1929 break;
8be74775 1930
355afbcd
KR		 1931 case 'W':
1932 if (opP->mode != MSCR
1933 || (opP->reg != DRP && opP->reg != SRP
1934 && opP->reg != CRP))
1935 losing++;
1936 break;
1937
1938 case 'X':
1939 if (opP->mode != MSCR ||
1940 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
1941 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1942 losing++;
1943 break;
1944
1945 case 'Y':
1946 if (opP->reg != PSR)
1947 losing++;
1948 break;
1949
1950 case 'Z':
1951 if (opP->reg != PCSR)
1952 losing++;
1953 break;
f8701a3f 1954#endif
355afbcd
KR		 1955 case 'c':
1956 if (opP->reg != NC
1957 && opP->reg != IC
1958 && opP->reg != DC
1959 && opP->reg != BC)
1960 {
1961 losing++;
1962 } /* not a cache specifier. */
1963 break;
1964
1965 case '_':
1966 if (opP->mode != ABSL)
1967 {
1968 ++losing;
1969 } /* not absolute */
1970 break;
8be74775 1971
355afbcd
KR		 1972 default:
1973 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
1974 *s, __LINE__, __FILE__);
1975 } /* switch on type of operand */
6d27d3a2 1976
355afbcd
KR		 1977 if (losing)
1978 break;
1979 } /* for each operand */
1980 } /* if immediately wrong */
6d27d3a2 1981
355afbcd
KR		 1982 if (!losing)
1983 {
8be74775 1984 break;
355afbcd 1985 } /* got it. */
6d27d3a2 1986
355afbcd 1987 opcode = opcode->m_next;
6d27d3a2 1988
355afbcd 1989 if (!opcode)
8be74775 1990 {
355afbcd
KR		 1991 if (ok_arch
1992 && !(ok_arch & current_architecture))
8be74775 1993 {
355afbcd
KR		 1994 char buf[200], *cp;
1995 int len;
1996 strcpy (buf, "invalid instruction for this architecture; needs ");
1997 cp = buf + strlen (buf);
1998 switch (ok_arch)
1999 {
2000 case mfloat:
2001 strcpy (cp, "fpu (68040 or 68881/68882)");
2002 break;
2003 case mmmu:
2004 strcpy (cp, "mmu (68030 or 68851)");
2005 break;
2006 case m68020up:
2007 strcpy (cp, "68020 or higher");
2008 break;
2009 case m68000up:
2010 strcpy (cp, "68000 or higher");
2011 break;
2012 case m68010up:
2013 strcpy (cp, "68010 or higher");
2014 break;
2015 default:
8be74775 2016 {
355afbcd
KR		 2017 int got_one = 0, idx;
2018 const static struct
2019 {
2020 int arch;
2021 const char *name;
2022 }
2023 archs[] =
2024 {
2025 m68000, "68000",
2026 m68010, "68010",
2027 m68020, "68020",
2028 m68030, "68030",
2029 m68040, "68040",
2030 cpu32, "cpu32",
2031 m68881, "68881",
2032 m68851, "68851",
2033 };
2034 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
8be74775 2035 {
355afbcd 2036 if (archs[idx].arch & ok_arch)
8be74775 2037 {
355afbcd
KR		 2038 if (got_one)
2039 {
2040 strcpy (cp, " or ");
2041 cp += strlen (cp);
2042 }
2043 got_one = 1;
2044 strcpy (cp, archs[idx].name);
8be74775
KR		 2045 cp += strlen (cp);
2046 }
8be74775
KR		 2047 }
2048 }
355afbcd
KR		 2049 }
2050 len = cp - buf + 1;
2051 cp = malloc (len);
2052 strcpy (cp, buf);
2053 the_ins.error = cp;
8be74775 2054 }
355afbcd
KR		 2055 else
2056 the_ins.error = "operands mismatch";
2057 return;
2058 } /* Fell off the end */
6d27d3a2 2059
355afbcd
KR		 2060 losing = 0;
2061 }
6d27d3a2
KR		 2062
2063 /* now assemble it */
2064
355afbcd
KR		 2065 the_ins.args = opcode->m_operands;
2066 the_ins.numargs = opcode->m_opnum;
2067 the_ins.numo = opcode->m_codenum;
2068 the_ins.opcode[0] = getone (opcode);
2069 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 2070
355afbcd
KR		 2071 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2072 {
2073 /* This switch is a doozy.
6d27d3a2 2074 Watch the first step; its a big one! */
355afbcd
KR		 2075 switch (s[0])
2076 {
6d27d3a2 2077
355afbcd
KR		 2078 case '*':
2079 case '~':
2080 case '%':
2081 case ';':
2082 case '@':
2083 case '!':
2084 case '&':
2085 case '$':
2086 case '?':
2087 case '/':
2088 case '`':
2089#ifndef NO_68851
2090 case '|':
2091#endif
2092 switch (opP->mode)
2093 {
2094 case IMMED:
2095 tmpreg = 0x3c; /* 7.4 */
2096 if (strchr ("bwl", s[1]))
2097 nextword = get_num (opP->con1, 80);
2098 else
2099 nextword = nextword = get_num (opP->con1, 0);
2100 if (isvar (opP->con1))
2101 add_fix (s[1], opP->con1, 0);
2102 switch (s[1])
2103 {
2104 case 'b':
2105 if (!isbyte (nextword))
2106 opP->error = "operand out of range";
2107 addword (nextword);
2108 baseo = 0;
2109 break;
2110 case 'w':
2111 if (!isword (nextword))
2112 opP->error = "operand out of range";
2113 addword (nextword);
2114 baseo = 0;
2115 break;
2116 case 'l':
2117 addword (nextword >> 16);
2118 addword (nextword);
2119 baseo = 0;
2120 break;
2121
2122 case 'f':
2123 baseo = 2;
2124 outro = 8;
2125 break;
2126 case 'F':
2127 baseo = 4;
2128 outro = 11;
2129 break;
2130 case 'x':
2131 baseo = 6;
2132 outro = 15;
2133 break;
2134 case 'p':
2135 baseo = 6;
2136 outro = -1;
2137 break;
2138 default:
2139 as_fatal ("Internal error: Can't decode %c%c in line %s of file \"%s\"",
2140 *s, s[1], __LINE__, __FILE__);
2141 }
2142 if (!baseo)
2143 break;
6d27d3a2 2144
355afbcd
KR		 2145 /* We gotta put out some float */
2146#if 0
2147 if (seg (opP->con1) != SEG_BIG)
2148 {
2149 int_to_gen (nextword);
2150 gen_to_words (words, baseo, (long int) outro);
2151 for (wordp = words; baseo--; wordp++)
2152 addword (*wordp);
2153 break;
2154 } /* Its BIG */
2155#else
2156 if (seg (opP->con1) != SEG_BIG)
2157 {
2158 abort ();
2159 }
2160#endif
2161 if (offs (opP->con1) > 0)
2162 {
2163 if (offs (opP->con1) > baseo)
2164 {
2165 as_warn ("Bignum too big for %c format; truncated", s[1]);
2166 offs (opP->con1) = baseo;
2167 }
2168 baseo -= offs (opP->con1);
2169 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2170 addword (*wordp);
2171 while (baseo--)
2172 addword (0);
2173 break;
2174 }
2175 gen_to_words (words, baseo, (long) outro);
2176 for (wordp = words; baseo--; wordp++)
2177 addword (*wordp);
2178 break;
2179 case DREG:
2180 tmpreg = opP->reg - DATA; /* 0.dreg */
2181 break;
2182 case AREG:
2183 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2184 break;
2185 case AINDR:
2186 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2187 break;
2188 case ADEC:
2189 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2190 break;
2191 case AINC:
2192 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2193 break;
2194 case AOFF:
6d27d3a2 2195
355afbcd
KR		 2196 nextword = get_num (opP->con1, 80);
2197 /* Force into index mode. Hope this works */
6d27d3a2 2198
355afbcd 2199 /* We do the first bit for 32-bit displacements,
6d27d3a2
KR		 2200 and the second bit for 16 bit ones. It is
2201 possible that we should make the default be
2202 WORD instead of LONG, but I think that'd
2203 break GCC, so we put up with a little
2204 inefficiency for the sake of working output.
2205 */
2206
355afbcd
KR		 2207 if (!issword (nextword)
2208 || (isvar (opP->con1)
2209 && ((opP->con1->e_siz == 0
2210 && flagseen['l'] == 0)
2211 || opP->con1->e_siz == 3)))
2212 {
6d27d3a2 2213
355afbcd
KR		 2214 if (opP->reg == PC)
2215 tmpreg = 0x3B; /* 7.3 */
2216 else
2217 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2218 if (isvar (opP->con1))
2219 {
2220 if (opP->reg == PC)
2221 {
2222 add_frag (adds (opP->con1),
2223 offs (opP->con1),
2224 TAB (PCLEA, SZ_UNDEF));
2225 break;
2226 }
2227 else
2228 {
2229 addword (0x0170);
2230 add_fix ('l', opP->con1, 0);
2231 }
2232 }
2233 else
2234 addword (0x0170);
2235 addword (nextword >> 16);
2236 }
2237 else
2238 {
2239 if (opP->reg == PC)
2240 tmpreg = 0x3A; /* 7.2 */
2241 else
2242 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2243
2244 if (isvar (opP->con1))
2245 {
2246 if (opP->reg == PC)
2247 {
2248 add_fix ('w', opP->con1, 1);
2249 }
2250 else
2251 add_fix ('w', opP->con1, 0);
2252 }
2253 }
2254 addword (nextword);
6d27d3a2 2255 break;
6d27d3a2 2256
355afbcd
KR		 2257 case APODX:
2258 case AMIND:
2259 case APRDX:
2260 know (current_architecture & m68020up);
2261 /* intentional fall-through */
2262 case AINDX:
2263 nextword = 0;
2264 baseo = get_num (opP->con1, 80);
2265 outro = get_num (opP->con2, 80);
2266 /* Figure out the 'addressing mode' */
2267 /* Also turn on the BASE_DISABLE bit, if needed */
2268 if (opP->reg == PC || opP->reg == ZPC)
2269 {
2270 tmpreg = 0x3b;/* 7.3 */
2271 if (opP->reg == ZPC)
2272 nextword |= 0x80;
2273 }
2274 else if (opP->reg == FAIL)
2275 {
2276 nextword |= 0x80;
2277 tmpreg = 0x30;/* 6.garbage */
2278 }
2279 else
2280 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2281
2282 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2283 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2284
2285 /* Index register stuff */
2286 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2287 {
2288 nextword |= (opP->ireg - DATA) << 12;
2289
2290 if (opP->isiz == 0 || opP->isiz == 3)
2291 nextword |= 0x800;
2292 switch (opP->imul)
2293 {
2294 case 1:
2295 break;
2296 case 2:
2297 nextword |= 0x200;
2298 break;
2299 case 4:
2300 nextword |= 0x400;
2301 break;
2302 case 8:
2303 nextword |= 0x600;
2304 break;
2305 default:
2306 as_fatal ("failed sanity check.");
2307 }
2308 /* IF its simple,
6d27d3a2
KR		 2309 GET US OUT OF HERE! */
2310
355afbcd 2311 /* Must be INDEX, with an index
6d27d3a2
KR		 2312 register. Address register
2313 cannot be ZERO-PC, and either
2314 :b was forced, or we know
2315 it will fit */
355afbcd
KR		 2316 if (opP->mode == AINDX
2317 && opP->reg != FAIL
2318 && opP->reg != ZPC
2319 && (siz1 == 1
2320 || (issbyte (baseo)
2321 && !isvar (opP->con1))))
2322 {
2323 nextword += baseo & 0xff;
2324 addword (nextword);
2325 if (isvar (opP->con1))
2326 add_fix ('B', opP->con1, 0);
2327 break;
2328 }
2329 }
2330 else
2331 nextword |= 0x40; /* No index reg */
6d27d3a2 2332
355afbcd
KR		 2333 /* It aint simple */
2334 nextword |= 0x100;
2335 /* If the guy specified a width, we assume that
6d27d3a2
KR		 2336 it is wide enough. Maybe it isn't. If so, we lose
2337 */
355afbcd
KR		 2338 switch (siz1)
2339 {
2340 case 0:
2341 if (isvar (opP->con1) || !issword (baseo))
2342 {
2343 siz1 = 3;
2344 nextword |= 0x30;
2345 }
2346 else if (baseo == 0)
2347 nextword |= 0x10;
2348 else
2349 {
2350 nextword |= 0x20;
2351 siz1 = 2;
2352 }
2353 break;
2354 case 1:
2355 as_warn ("Byte dispacement won't work. Defaulting to :w");
2356 case 2:
2357 nextword |= 0x20;
2358 break;
2359 case 3:
2360 nextword |= 0x30;
2361 break;
2362 }
6d27d3a2 2363
355afbcd
KR		 2364 /* Figure out innner displacement stuff */
2365 if (opP->mode != AINDX)
2366 {
2367 switch (siz2)
2368 {
2369 case 0:
2370 if (isvar (opP->con2) || !issword (outro))
2371 {
2372 siz2 = 3;
2373 nextword |= 0x3;
2374 }
2375 else if (outro == 0)
2376 nextword |= 0x1;
2377 else
2378 {
2379 nextword |= 0x2;
2380 siz2 = 2;
2381 }
2382 break;
2383 case 1:
2384 as_warn ("Byte dispacement won't work. Defaulting to :w");
2385 case 2:
2386 nextword |= 0x2;
2387 break;
2388 case 3:
2389 nextword |= 0x3;
2390 break;
2391 }
2392 if (opP->mode == APODX)
2393 nextword |= 0x04;
2394 else if (opP->mode == AMIND)
2395 nextword |= 0x40;
2396 }
2397 addword (nextword);
2398
2399 if (isvar (opP->con1))
2400 {
2401 if (opP->reg == PC || opP->reg == ZPC)
2402 {
2403 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
2404 opP->con1->e_exp.X_add_number += 6;
2405 }
2406 else
2407 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2408 }
2409 if (siz1 == 3)
2410 addword (baseo >> 16);
2411 if (siz1)
2412 addword (baseo);
2413
2414 if (isvar (opP->con2))
2415 {
2416 if (opP->reg == PC || opP->reg == ZPC)
2417 {
2418 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
2419 opP->con1->e_exp.X_add_number += 6;
2420 }
2421 else
2422 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2423 }
2424 if (siz2 == 3)
2425 addword (outro >> 16);
2426 if (siz2)
2427 addword (outro);
6d27d3a2 2428
355afbcd 2429 break;
6d27d3a2 2430
355afbcd
KR		 2431 case ABSL:
2432 nextword = get_num (opP->con1, 80);
2433 switch (opP->con1->e_siz)
2434 {
2435 default:
2436 as_warn ("Unknown size for absolute reference");
2437 case 0:
2438 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2439 {
2440 tmpreg = 0x38; /* 7.0 */
2441 addword (nextword);
2442 break;
2443 }
2444 /* Don't generate pc relative code
6d27d3a2 2445 on 68010 and 68000 */
355afbcd
KR		 2446 if (isvar (opP->con1)
2447 && !subs (opP->con1)
2448 && seg (opP->con1) == SEG_TEXT
2449 && now_seg == SEG_TEXT
2450 && cpu_of_arch (current_architecture) >= m68020
2451 && !flagseen['S']
2452 && !strchr ("~%&$?", s[0]))
2453 {
2454 tmpreg = 0x3A; /* 7.2 */
2455 add_frag (adds (opP->con1),
2456 offs (opP->con1),
2457 TAB (PCREL, SZ_UNDEF));
2458 break;
2459 }
2460 case 3: /* Fall through into long */
2461 if (isvar (opP->con1))
2462 add_fix ('l', opP->con1, 0);
2463
2464 tmpreg = 0x39;/* 7.1 mode */
2465 addword (nextword >> 16);
2466 addword (nextword);
2467 break;
2468
2469 case 2: /* Word */
2470 if (isvar (opP->con1))
2471 add_fix ('w', opP->con1, 0);
2472
2473 tmpreg = 0x38;/* 7.0 mode */
2474 addword (nextword);
2475 break;
2476 }
2477 break;
2478 case DINDR:
2479 as_bad ("invalid indirect register");
2480 break;
2481 case MSCR:
2482 default:
2483 as_bad ("unknown/incorrect operand");
2484 /* abort(); */
2485 }
2486 install_gen_operand (s[1], tmpreg);
6d27d3a2 2487 break;
6d27d3a2 2488
355afbcd
KR		 2489 case '#':
2490 case '^':
2491 switch (s[1])
2492 { /* JF: I hate floating point! */
2493 case 'j':
2494 tmpreg = 70;
2495 break;
2496 case '8':
2497 tmpreg = 20;
2498 break;
2499 case 'C':
2500 tmpreg = 50;
2501 break;
2502 case '3':
2503 default:
2504 tmpreg = 80;
2505 break;
2506 }
2507 tmpreg = get_num (opP->con1, tmpreg);
2508 if (isvar (opP->con1))
2509 add_fix (s[1], opP->con1, 0);
2510 switch (s[1])
2511 {
2512 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 2513 certain types of overflow.
2514 user beware! */
355afbcd
KR		 2515 if (!isbyte (tmpreg))
2516 opP->error = "out of range";
2517 insop (tmpreg);
2518 if (isvar (opP->con1))
2519 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2520 break;
2521 case 'w':
2522 if (!isword (tmpreg))
2523 opP->error = "out of range";
2524 insop (tmpreg);
2525 if (isvar (opP->con1))
2526 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2527 break;
2528 case 'l':
2529 insop (tmpreg); /* Because of the way insop works, we put these two out backwards */
2530 insop (tmpreg >> 16);
2531 if (isvar (opP->con1))
2532 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2533 break;
2534 case '3':
2535 tmpreg &= 0xFF;
2536 case '8':
2537 case 'C':
2538 install_operand (s[1], tmpreg);
2539 break;
2540 default:
2541 as_fatal ("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2542 }
2543 break;
6d27d3a2 2544
355afbcd
KR		 2545 case '+':
2546 case '-':
2547 case 'A':
2548 case 'a':
2549 install_operand (s[1], opP->reg - ADDR);
2550 break;
6d27d3a2 2551
355afbcd
KR		 2552 case 'B':
2553 tmpreg = get_num (opP->con1, 80);
2554 switch (s[1])
2555 {
2556 case 'B':
2557 /* Needs no offsetting */
2558 add_fix ('B', opP->con1, 1);
2559 break;
2560 case 'W':
2561 /* Offset the displacement to be relative to byte disp location */
2562 opP->con1->e_exp.X_add_number += 2;
2563 add_fix ('w', opP->con1, 1);
2564 addword (0);
2565 break;
2566 case 'L':
2567 long_branch:
2568 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2569 as_warn ("Can't use long branches on 68000/68010");
2570 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2571 /* Offset the displacement to be relative to byte disp location */
2572 opP->con1->e_exp.X_add_number += 4;
2573 add_fix ('l', opP->con1, 1);
2574 addword (0);
2575 addword (0);
2576 break;
2577 case 'g':
2578 if (subs (opP->con1)) /* We can't relax it */
2579 goto long_branch;
6d27d3a2 2580
355afbcd 2581 /* This could either be a symbol, or an
6d27d3a2
KR		 2582 absolute address. No matter, the
2583 frag hacking will finger it out.
2584 Not quite: it can't switch from
2585 BRANCH to BCC68000 for the case
2586 where opnd is absolute (it needs
2587 to use the 68000 hack since no
2588 conditional abs jumps). */
355afbcd
KR		 2589 if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1)))
2590 && (the_ins.opcode[0] >= 0x6200)
2591 && (the_ins.opcode[0] <= 0x6f00))
2592 {
2593 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2594 }
2595 else
2596 {
2597 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2598 }
2599 break;
2600 case 'w':
2601 if (isvar (opP->con1))
2602 {
2603 /* check for DBcc instruction */
2604 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2605 {
2606 /* size varies if patch */
2607 /* needed for long form */
2608 add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF));
2609 break;
2610 }
6d27d3a2 2611
355afbcd
KR		 2612 /* Don't ask! */
2613 opP->con1->e_exp.X_add_number += 2;
2614 add_fix ('w', opP->con1, 1);
2615 }
2616 addword (0);
2617 break;
2618 case 'C': /* Fixed size LONG coproc branches */
2619 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2620 /* Offset the displacement to be relative to byte disp location */
2621 /* Coproc branches don't have a byte disp option, but they are
6d27d3a2 2622 compatible with the ordinary branches, which do... */
355afbcd
KR		 2623 opP->con1->e_exp.X_add_number += 4;
2624 add_fix ('l', opP->con1, 1);
2625 addword (0);
2626 addword (0);
2627 break;
2628 case 'c': /* Var size Coprocesssor branches */
2629 if (subs (opP->con1))
2630 {
2631 add_fix ('l', opP->con1, 1);
2632 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2633 }
2634 else if (adds (opP->con1))
2635 {
2636 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2637 }
2638 else
2639 {
2640 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2641 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2642 add_fix ('l', opP->con1, 1);
2643 addword (0);
2644 addword (4);
2645 }
2646 break;
2647 default:
2648 as_fatal ("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2649 s[1], __LINE__, __FILE__);
2650 }
2651 break;
6d27d3a2 2652
355afbcd
KR		 2653 case 'C': /* Ignore it */
2654 break;
6d27d3a2 2655
355afbcd
KR		 2656 case 'd': /* JF this is a kludge */
2657 if (opP->mode == AOFF)
2658 {
2659 install_operand ('s', opP->reg - ADDR);
2660 }
2661 else
2662 {
2663 char *tmpP;
2664
2665 tmpP = opP->con1->e_end - 2;
2666 opP->con1->e_beg++;
2667 opP->con1->e_end -= 4; /* point to the , */
2668 baseo = m68k_reg_parse (&tmpP);
2669 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2670 {
2671 as_bad ("Unknown address reg, using A0");
2672 baseo = 0;
2673 }
2674 else
2675 baseo -= ADDR;
2676 install_operand ('s', baseo);
2677 }
2678 tmpreg = get_num (opP->con1, 80);
2679 if (!issword (tmpreg))
2680 {
2681 as_warn ("Expression out of range, using 0");
2682 tmpreg = 0;
2683 }
2684 addword (tmpreg);
2685 break;
6d27d3a2 2686
355afbcd
KR		 2687 case 'D':
2688 install_operand (s[1], opP->reg - DATA);
2689 break;
6d27d3a2 2690
355afbcd
KR		 2691 case 'F':
2692 install_operand (s[1], opP->reg - FPREG);
2693 break;
6d27d3a2 2694
355afbcd
KR		 2695 case 'I':
2696 tmpreg = 1 + opP->reg - COPNUM;
2697 if (tmpreg == 8)
2698 tmpreg = 0;
2699 install_operand (s[1], tmpreg);
2700 break;
6d27d3a2 2701
355afbcd
KR		 2702 case 'J': /* JF foo */
2703 switch (opP->reg)
2704 {
2705 case SFC:
2706 tmpreg = 0x000;
2707 break;
2708 case DFC:
2709 tmpreg = 0x001;
2710 break;
2711 case CACR:
2712 tmpreg = 0x002;
2713 break;
2714 case TC:
2715 tmpreg = 0x003;
2716 break;
2717 case ITT0:
2718 tmpreg = 0x004;
2719 break;
2720 case ITT1:
2721 tmpreg = 0x005;
2722 break;
2723 case DTT0:
2724 tmpreg = 0x006;
2725 break;
2726 case DTT1:
2727 tmpreg = 0x007;
2728 break;
6d27d3a2 2729
355afbcd
KR		 2730 case USP:
2731 tmpreg = 0x800;
2732 break;
2733 case VBR:
2734 tmpreg = 0x801;
2735 break;
2736 case CAAR:
2737 tmpreg = 0x802;
2738 break;
2739 case MSP:
2740 tmpreg = 0x803;
2741 break;
2742 case ISP:
2743 tmpreg = 0x804;
2744 break;
2745 case MMUSR:
2746 tmpreg = 0x805;
2747 break;
2748 case URP:
2749 tmpreg = 0x806;
2750 break;
2751 case SRP:
2752 tmpreg = 0x807;
2753 break;
2754 default:
2755 as_fatal ("failed sanity check.");
2756 }
2757 install_operand (s[1], tmpreg);
2758 break;
6d27d3a2 2759
355afbcd
KR		 2760 case 'k':
2761 tmpreg = get_num (opP->con1, 55);
2762 install_operand (s[1], tmpreg & 0x7f);
2763 break;
6d27d3a2 2764
355afbcd
KR		 2765 case 'l':
2766 tmpreg = opP->reg;
2767 if (s[1] == 'w')
2768 {
2769 if (tmpreg & 0x7FF0000)
2770 as_bad ("Floating point register in register list");
2771 insop (reverse_16_bits (tmpreg));
2772 }
2773 else
2774 {
2775 if (tmpreg & 0x700FFFF)
2776 as_bad ("Wrong register in floating-point reglist");
2777 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2778 }
2779 break;
6d27d3a2 2780
355afbcd
KR		 2781 case 'L':
2782 tmpreg = opP->reg;
2783 if (s[1] == 'w')
2784 {
2785 if (tmpreg & 0x7FF0000)
2786 as_bad ("Floating point register in register list");
2787 insop (tmpreg);
2788 }
2789 else if (s[1] == '8')
2790 {
2791 if (tmpreg & 0x0FFFFFF)
2792 as_bad ("incorrect register in reglist");
2793 install_operand (s[1], tmpreg >> 24);
2794 }
2795 else
2796 {
2797 if (tmpreg & 0x700FFFF)
2798 as_bad ("wrong register in floating-point reglist");
2799 else
2800 install_operand (s[1], tmpreg >> 16);
2801 }
2802 break;
6d27d3a2 2803
355afbcd
KR		 2804 case 'M':
2805 install_operand (s[1], get_num (opP->con1, 60));
2806 break;
6d27d3a2 2807
355afbcd
KR		 2808 case 'O':
2809 tmpreg = (opP->mode == DREG)
2810 ? 0x20 + opP->reg - DATA
2811 : (get_num (opP->con1, 40) & 0x1F);
2812 install_operand (s[1], tmpreg);
2813 break;
6d27d3a2 2814
355afbcd
KR		 2815 case 'Q':
2816 tmpreg = get_num (opP->con1, 10);
2817 if (tmpreg == 8)
2818 tmpreg = 0;
2819 install_operand (s[1], tmpreg);
2820 break;
2821
2822 case 'R':
2823 case 'r':
2824 /* This depends on the fact that ADDR registers are
6d27d3a2
KR		 2825 eight more than their corresponding DATA regs, so
2826 the result will have the ADDR_REG bit set */
355afbcd
KR		 2827 install_operand (s[1], opP->reg - DATA);
2828 break;
6d27d3a2 2829
355afbcd
KR		 2830 case 's':
2831 if (opP->reg == FPI)
2832 tmpreg = 0x1;
2833 else if (opP->reg == FPS)
2834 tmpreg = 0x2;
2835 else if (opP->reg == FPC)
2836 tmpreg = 0x4;
2837 else
2838 as_fatal ("failed sanity check.");
2839 install_operand (s[1], tmpreg);
2840 break;
6d27d3a2 2841
355afbcd
KR		 2842 case 'S': /* Ignore it */
2843 break;
6d27d3a2 2844
355afbcd
KR		 2845 case 'T':
2846 install_operand (s[1], get_num (opP->con1, 30));
2847 break;
6d27d3a2 2848
355afbcd
KR		 2849 case 'U': /* Ignore it */
2850 break;
6d27d3a2 2851
355afbcd
KR		 2852 case 'c':
2853 switch (opP->reg)
2854 {
2855 case NC:
2856 tmpreg = 0;
2857 break;
2858 case DC:
2859 tmpreg = 1;
2860 break;
2861 case IC:
2862 tmpreg = 2;
2863 break;
2864 case BC:
2865 tmpreg = 3;
2866 break;
2867 default:
2868 as_fatal ("failed sanity check");
2869 } /* switch on cache token */
2870 install_operand (s[1], tmpreg);
2871 break;
a39116f1 2872#ifndef NO_68851
355afbcd
KR		 2873 /* JF: These are out of order, I fear. */
2874 case 'f':
2875 switch (opP->reg)
2876 {
2877 case SFC:
2878 tmpreg = 0;
2879 break;
2880 case DFC:
2881 tmpreg = 1;
2882 break;
2883 default:
2884 as_fatal ("failed sanity check.");
2885 }
2886 install_operand (s[1], tmpreg);
2887 break;
6d27d3a2 2888
355afbcd
KR		 2889 case 'P':
2890 switch (opP->reg)
2891 {
2892 case TC:
2893 tmpreg = 0;
2894 break;
2895 case CAL:
2896 tmpreg = 4;
2897 break;
2898 case VAL:
2899 tmpreg = 5;
2900 break;
2901 case SCC:
2902 tmpreg = 6;
2903 break;
2904 case AC:
2905 tmpreg = 7;
2906 break;
2907 default:
2908 as_fatal ("failed sanity check.");
2909 }
2910 install_operand (s[1], tmpreg);
2911 break;
6d27d3a2 2912
355afbcd
KR		 2913 case 'V':
2914 if (opP->reg == VAL)
2915 break;
2916 as_fatal ("failed sanity check.");
6d27d3a2 2917
355afbcd
KR		 2918 case 'W':
2919 switch (opP->reg)
2920 {
6d27d3a2 2921
355afbcd
KR		 2922 case DRP:
2923 tmpreg = 1;
2924 break;
2925 case SRP:
2926 tmpreg = 2;
2927 break;
2928 case CRP:
2929 tmpreg = 3;
2930 break;
2931 default:
2932 as_fatal ("failed sanity check.");
2933 }
2934 install_operand (s[1], tmpreg);
2935 break;
6d27d3a2 2936
355afbcd
KR		 2937 case 'X':
2938 switch (opP->reg)
2939 {
2940 case BAD:
2941 case BAD + 1:
2942 case BAD + 2:
2943 case BAD + 3:
2944 case BAD + 4:
2945 case BAD + 5:
2946 case BAD + 6:
2947 case BAD + 7:
2948 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2949 break;
6d27d3a2 2950
355afbcd
KR		 2951 case BAC:
2952 case BAC + 1:
2953 case BAC + 2:
2954 case BAC + 3:
2955 case BAC + 4:
2956 case BAC + 5:
2957 case BAC + 6:
2958 case BAC + 7:
2959 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2960 break;
6d27d3a2 2961
355afbcd
KR		 2962 default:
2963 as_fatal ("failed sanity check.");
2964 }
2965 install_operand (s[1], tmpreg);
2966 break;
2967 case 'Y':
2968 know (opP->reg == PSR);
2969 break;
2970 case 'Z':
2971 know (opP->reg == PCSR);
2972 break;
f8701a3f 2973#endif /* m68851 */
355afbcd
KR		 2974 case '3':
2975 switch (opP->reg)
2976 {
2977 case TT0:
2978 tmpreg = 2;
2979 break;
2980 case TT1:
2981 tmpreg = 3;
2982 break;
2983 default:
2984 as_fatal ("failed sanity check");
2985 }
2986 install_operand (s[1], tmpreg);
2987 break;
2988 case 't':
2989 tmpreg = get_num (opP->con1, 20);
2990 install_operand (s[1], tmpreg);
4134a793 2991 break;
355afbcd
KR		 2992 case '_': /* used only for move16 absolute 32-bit address */
2993 tmpreg = get_num (opP->con1, 80);
2994 addword (tmpreg >> 16);
2995 addword (tmpreg & 0xFFFF);
4134a793
KR		 2996 break;
2997 default:
355afbcd
KR		 2998 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2999 s[0], __LINE__, __FILE__);
4134a793 3000 }
6d27d3a2 3001 }
3ad9ec6a 3002
6d27d3a2
KR		 3003 /* By the time whe get here (FINALLY) the_ins contains the complete
3004 instruction, ready to be emitted. . . */
355afbcd 3005} /* m68k_ip() */
7c15cbe8
RP		 3006
3007/*
3008 * get_regs := '/' + ?
3009 * | '-' + <register>
3010 * | '-' + <register> + ?
3011 * | <empty>
3012 * ;
3013 *
6d27d3a2 3014
7c15cbe8
RP		 3015 * The idea here must be to scan in a set of registers but I don't
3016 * understand it. Looks awfully sloppy to me but I don't have any doc on
3017 * this format so...
6d27d3a2
KR		 3018
3019 *
7c15cbe8
RP		 3020 *
3021 */
fecd2382 3022
355afbcd
KR		 3023static int
3024get_regs (i, str, opP)
3025 int i;
3026 struct m68k_op *opP;
3027 char *str;
fecd2382 3028{
355afbcd
KR		 3029 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3030 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3031 unsigned long cur_regs = 0;
3032 int reg1, reg2;
6d27d3a2 3033
fecd2382 3034#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
a39116f1
RP		 3035else if(x==FPS) cur_regs|=(1<<25);\
3036else if(x==FPC) cur_regs|=(1<<26);\
3037else cur_regs|=(1<<(x-1)); }
6d27d3a2 3038
355afbcd
KR		 3039 reg1 = i;
3040 for (;;)
3041 {
3042 if (*str == '/')
3043 {
3044 ADD_REG (reg1);
3045 str++;
3046 }
3047 else if (*str == '-')
3048 {
3049 str++;
3050 reg2 = m68k_reg_parse (&str);
3051 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3052 {
3053 opP->error = "unknown register in register list";
3054 return FAIL;
3055 }
3056 while (reg1 <= reg2)
3057 {
3058 ADD_REG (reg1);
3059 reg1++;
3060 }
3061 if (*str == '\0')
3062 break;
3063 }
3064 else if (*str == '\0')
3065 {
3066 ADD_REG (reg1);
3067 break;
3068 }
3069 else
3070 {
3071 opP->error = "unknow character in register list";
3072 return FAIL;
3073 }
3074 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3075 if (*str == '/')
3076 str++;
3077 reg1 = m68k_reg_parse (&str);
3078 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3079 {
3080 opP->error = "unknown register in register list";
3081 return FAIL;
a39116f1 3082 }
355afbcd
KR		 3083 }
3084 opP->reg = cur_regs;
3085 return OK;
3086} /* get_regs() */
fecd2382 3087
355afbcd
KR		 3088static int
3089reverse_16_bits (in)
3090 int in;
fecd2382 3091{
355afbcd
KR		 3092 int out = 0;
3093 int n;
6d27d3a2 3094
355afbcd
KR		 3095 static int mask[16] =
3096 {
3097 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3098 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3099 };
3100 for (n = 0; n < 16; n++)
3101 {
3102 if (in & mask[n])
3103 out |= mask[15 - n];
3104 }
3105 return out;
3106} /* reverse_16_bits() */
fecd2382 3107
355afbcd
KR		 3108static int
3109reverse_8_bits (in)
3110 int in;
fecd2382 3111{
355afbcd
KR		 3112 int out = 0;
3113 int n;
6d27d3a2 3114
355afbcd
KR		 3115 static int mask[8] =
3116 {
3117 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3118 };
6d27d3a2 3119
355afbcd
KR		 3120 for (n = 0; n < 8; n++)
3121 {
3122 if (in & mask[n])
3123 out |= mask[7 - n];
3124 }
3125 return out;
3126} /* reverse_8_bits() */
fecd2382 3127
355afbcd
KR		 3128static void
3129install_operand (mode, val)
3130 int mode;
3131 int val;
fecd2382 3132{
355afbcd
KR		 3133 switch (mode)
3134 {
3135 case 's':
3136 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3137 break;
3138 case 'd':
3139 the_ins.opcode[0] |= val << 9;
3140 break;
3141 case '1':
3142 the_ins.opcode[1] |= val << 12;
3143 break;
3144 case '2':
3145 the_ins.opcode[1] |= val << 6;
3146 break;
3147 case '3':
3148 the_ins.opcode[1] |= val;
3149 break;
3150 case '4':
3151 the_ins.opcode[2] |= val << 12;
3152 break;
3153 case '5':
3154 the_ins.opcode[2] |= val << 6;
3155 break;
3156 case '6':
3157 /* DANGER! This is a hack to force cas2l and cas2w cmds
f8701a3f 3158 to be three words long! */
355afbcd
KR		 3159 the_ins.numo++;
3160 the_ins.opcode[2] |= val;
3161 break;
3162 case '7':
3163 the_ins.opcode[1] |= val << 7;
3164 break;
3165 case '8':
3166 the_ins.opcode[1] |= val << 10;
3167 break;
f8701a3f 3168#ifndef NO_68851
355afbcd
KR		 3169 case '9':
3170 the_ins.opcode[1] |= val << 5;
3171 break;
f8701a3f 3172#endif
6d27d3a2 3173
355afbcd
KR		 3174 case 't':
3175 the_ins.opcode[1] |= (val << 10) | (val << 7);
3176 break;
3177 case 'D':
3178 the_ins.opcode[1] |= (val << 12) | val;
3179 break;
3180 case 'g':
3181 the_ins.opcode[0] |= val = 0xff;
3182 break;
3183 case 'i':
3184 the_ins.opcode[0] |= val << 9;
3185 break;
3186 case 'C':
3187 the_ins.opcode[1] |= val;
3188 break;
3189 case 'j':
3190 the_ins.opcode[1] |= val;
3191 the_ins.numo++; /* What a hack */
3192 break;
3193 case 'k':
3194 the_ins.opcode[1] |= val << 4;
3195 break;
3196 case 'b':
3197 case 'w':
3198 case 'l':
3199 break;
3200 case 'e':
3201 the_ins.opcode[0] |= (val << 6);
3202 break;
3203 case 'L':
3204 the_ins.opcode[1] = (val >> 16);
3205 the_ins.opcode[2] = val & 0xffff;
3206 break;
3207 case 'c':
3208 default:
3209 as_fatal ("failed sanity check.");
3210 }
3211} /* install_operand() */
fecd2382 3212
355afbcd
KR		 3213static void
3214install_gen_operand (mode, val)
3215 int mode;
3216 int val;
fecd2382 3217{
355afbcd
KR		 3218 switch (mode)
3219 {
3220 case 's':
3221 the_ins.opcode[0] |= val;
3222 break;
3223 case 'd':
3224 /* This is a kludge!!! */
3225 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3226 break;
3227 case 'b':
3228 case 'w':
3229 case 'l':
3230 case 'f':
3231 case 'F':
3232 case 'x':
3233 case 'p':
3234 the_ins.opcode[0] |= val;
3235 break;
3236 /* more stuff goes here */
3237 default:
3238 as_fatal ("failed sanity check.");
3239 }
3240} /* install_gen_operand() */
fecd2382 3241
7c15cbe8
RP		 3242/*
3243 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3244 * then deal with the bitfield hack.
3245 */
3246
355afbcd
KR		 3247static char *
3248crack_operand (str, opP)
3249 register char *str;
3250 register struct m68k_op *opP;
fecd2382 3251{
355afbcd
KR		 3252 register int parens;
3253 register int c;
3254 register char *beg_str;
6d27d3a2 3255
355afbcd
KR		 3256 if (!str)
3257 {
3258 return str;
3259 }
3260 beg_str = str;
3261 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3262 {
3263 if (*str == '(')
3264 parens++;
3265 else if (*str == ')')
3266 {
3267 if (!parens)
3268 { /* ERROR */
3269 opP->error = "Extra )";
3270 return str;
3271 }
3272 --parens;
f8701a3f 3273 }
355afbcd
KR		 3274 }
3275 if (!*str && parens)
3276 { /* ERROR */
3277 opP->error = "Missing )";
3278 return str;
3279 }
3280 c = *str;
3281 *str = '\0';
3282 if (m68k_ip_op (beg_str, opP) == FAIL)
3283 {
3284 *str = c;
3285 return str;
3286 }
3287 *str = c;
3288 if (c == '}')
3289 c = *++str; /* JF bitfield hack */
3290 if (c)
3291 {
3292 c = *++str;
3293 if (!c)
3294 as_bad ("Missing operand");
3295 }
3296 return str;
fecd2382
RP		 3297}
3298
3299/* See the comment up above where the #define notend(... is */
3300#if 0
355afbcd
KR		 3301notend (s)
3302 char *s;
fecd2382 3303{
355afbcd
KR		 3304 if (*s == ',')
3305 return 0;
3306 if (*s == '{' || *s == '}')
3307 return 0;
3308 if (*s != ':')
3309 return 1;
3310 /* This kludge here is for the division cmd, which is a kludge */
3311 if (index ("aAdD#", s[1]))
3312 return 0;
3313 return 1;
fecd2382 3314}
355afbcd 3315
fecd2382
RP		 3316#endif
3317
3318/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 3319 machine dependent instruction. This function is supposed to emit
fecd2382 3320 the frags/bytes it assembles to.
a39116f1 3321 */
a933d598
SC		 3322
3323void
355afbcd
KR		 3324insert_reg (regname, regnum)
3325 char *regname;
3326 int regnum;
a933d598
SC		 3327{
3328 char buf[100];
3329 int i;
355afbcd
KR		 3330
3331#ifdef REGISTER_PREFIX
3332 buf[0] = REGISTER_PREFIX;
3333 strcpy (buf + 1, regname);
3334 regname = buf;
3335#endif
3336
3337 symbol_table_insert (symbol_new (regname, SEG_REGISTER, regnum, &zero_address_frag));
a933d598
SC		 3338
3339 for (i = 0; regname[i]; i++)
355afbcd 3340 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 3341 buf[i] = '\0';
6d27d3a2 3342
355afbcd 3343 symbol_table_insert (symbol_new (buf, SEG_REGISTER, regnum, &zero_address_frag));
a933d598
SC		 3344}
3345
355afbcd
KR		 3346static const struct
3347 {
3348 char *name;
3349 int number;
3350 }
3351
3352init_table[] =
3353{
3354 "d0", DATA0,
3355 "d1", DATA1,
3356 "d2", DATA2,
3357 "d3", DATA3,
3358 "d4", DATA4,
3359 "d5", DATA5,
3360 "d6", DATA6,
3361 "d7", DATA7,
3362 "a0", ADDR0,
3363 "a1", ADDR1,
3364 "a2", ADDR2,
3365 "a3", ADDR3,
3366 "a4", ADDR4,
3367 "a5", ADDR5,
3368 "a6", ADDR6,
3369 "fp", ADDR6,
3370 "a7", ADDR7,
3371 "sp", ADDR7,
3372 "fp0", FP0,
3373 "fp1", FP1,
3374 "fp2", FP2,
3375 "fp3", FP3,
3376 "fp4", FP4,
3377 "fp5", FP5,
3378 "fp6", FP6,
3379 "fp7", FP7,
3380 "fpi", FPI,
3381 "fpiar", FPI,
3382 "fpc", FPI,
3383 "fps", FPS,
3384 "fpsr", FPS,
3385 "fpc", FPC,
3386 "fpcr", FPC,
3387
3388 "cop0", COP0,
3389 "cop1", COP1,
3390 "cop2", COP2,
3391 "cop3", COP3,
3392 "cop4", COP4,
3393 "cop5", COP5,
3394 "cop6", COP6,
3395 "cop7", COP7,
3396 "pc", PC,
3397 "zpc", ZPC,
3398 "sr", SR,
3399
3400 "ccr", CCR,
3401 "cc", CCR,
3402
3403 "usp", USP,
3404 "isp", ISP,
3405 "sfc", SFC,
3406 "dfc", DFC,
3407 "cacr", CACR,
3408 "caar", CAAR,
3409
3410 "vbr", VBR,
3411
3412 "msp", MSP,
3413 "itt0", ITT0,
3414 "itt1", ITT1,
3415 "dtt0", DTT0,
3416 "dtt1", DTT1,
3417 "mmusr", MMUSR,
3418 "tc", TC,
3419 "srp", SRP,
3420 "urp", URP,
3421
3422 "ac", AC,
3423 "bc", BC,
3424 "cal", CAL,
3425 "crp", CRP,
3426 "drp", DRP,
3427 "pcsr", PCSR,
3428 "psr", PSR,
3429 "scc", SCC,
3430 "val", VAL,
3431 "bad0", BAD0,
3432 "bad1", BAD1,
3433 "bad2", BAD2,
3434 "bad3", BAD3,
3435 "bad4", BAD4,
3436 "bad5", BAD5,
3437 "bad6", BAD6,
3438 "bad7", BAD7,
3439 "bac0", BAC0,
3440 "bac1", BAC1,
3441 "bac2", BAC2,
3442 "bac3", BAC3,
3443 "bac4", BAC4,
3444 "bac5", BAC5,
3445 "bac6", BAC6,
3446 "bac7", BAC7,
3447
3448 "ic", IC,
3449 "dc", DC,
3450 "nc", NC,
3451
3452 "tt0", TT0,
3453 "tt1", TT1,
4134a793 3454 /* 68ec030 versions of same */
355afbcd
KR		 3455 "ac0", TT0,
3456 "ac1", TT1,
4134a793 3457 /* 68ec030 access control unit, identical to 030 MMU status reg */
355afbcd 3458 "acusr", PSR,
4134a793 3459
a933d598
SC		 3460 0,
3461
3462};
3463
3464
3465void
355afbcd 3466init_regtable ()
a933d598
SC		 3467{
3468 int i;
6d27d3a2 3469 for (i = 0; init_table[i].name; i++)
355afbcd 3470 insert_reg (init_table[i].name, init_table[i].number);
a933d598 3471}
6d27d3a2 3472
df3768fb 3473static int no_68851, no_68881;
a933d598 3474
fecd2382 3475void
355afbcd 3476md_assemble (str)
6d27d3a2 3477 char *str;
fecd2382 3478{
355afbcd
KR		 3479 char *er;
3480 short *fromP;
3481 char *toP = NULL;
3482 int m, n = 0;
3483 char *to_beg_P;
3484 int shorts_this_frag;
3485 static int done_first_time;
3486
3487 if (!done_first_time)
3488 {
3489 done_first_time = 1;
4134a793 3490
355afbcd
KR		 3491 if (cpu_of_arch (current_architecture) == 0)
3492 {
3493 int cpu_type;
148eb5dd
ILT		 3494
3495#ifndef TARGET_CPU
355afbcd 3496 cpu_type = m68020;
148eb5dd 3497#else
355afbcd
KR		 3498 if (strcmp (TARGET_CPU, "m68000") == 0)
3499 cpu_type = m68000;
3500 else if (strcmp (TARGET_CPU, "m68010") == 0)
3501 cpu_type = m68010;
3502 else if (strcmp (TARGET_CPU, "m68020") == 0
3503 || strcmp (TARGET_CPU, "m68k") == 0)
3504 cpu_type = m68020;
3505 else if (strcmp (TARGET_CPU, "m68030") == 0)
3506 cpu_type = m68030;
3507 else if (strcmp (TARGET_CPU, "m68040") == 0)
3508 cpu_type = m68040;
3509 else if (strcmp (TARGET_CPU, "cpu32") == 0)
3510 cpu_type = cpu32;
3511 else
3512 cpu_type = m68020;
148eb5dd
ILT		 3513#endif
3514
355afbcd
KR		 3515 current_architecture |= cpu_type;
3516 }
3517#if 0 /* Could be doing emulation. */
3518 if (current_architecture & m68881)
3519 {
3520 if (current_architecture & m68000)
3521 as_bad ("incompatible processors 68000 and 68881/2 specified");
3522 if (current_architecture & m68010)
3523 as_bad ("incompatible processors 68010 and 68881/2 specified");
3524 if (current_architecture & m68040)
3525 as_bad ("incompatible processors 68040 and 68881/2 specified");
3526 }
3527#endif
3528 /* What other incompatibilities could we check for? */
6d27d3a2 3529
355afbcd
KR		 3530 /* Toss in some default assumptions about coprocessors. */
3531 if (!no_68881
3532 && (cpu_of_arch (current_architecture)
3533 /* Can CPU32 have a 68881 coprocessor?? */
3534 & (m68020 | m68030 | cpu32)))
3535 {
3536 current_architecture |= m68881;
fecd2382 3537 }
355afbcd
KR		 3538 if (!no_68851
3539 && (cpu_of_arch (current_architecture) & m68020up) != 0)
3540 {
3541 current_architecture |= m68851;
fecd2382 3542 }
355afbcd
KR		 3543 if (no_68881 && (current_architecture & m68881))
3544 as_bad ("options for 68881 and no-68881 both given");
3545 if (no_68851 && (current_architecture & m68851))
3546 as_bad ("options for 68851 and no-68851 both given");
3547 done_first_time = 1;
3548 }
6d27d3a2 3549
355afbcd
KR		 3550 memset ((char *) (&the_ins), '\0', sizeof (the_ins)); /* JF for paranoia sake */
3551 m68k_ip (str);
3552 er = the_ins.error;
3553 if (!er)
3554 {
3555 for (n = the_ins.numargs; n; --n)
3556 if (the_ins.operands[n].error)
3557 {
3558 er = the_ins.operands[n].error;
3559 break;
3560 }
3561 }
3562 if (er)
3563 {
3564 as_bad ("%s -- statement `%s' ignored", er, str);
3565 return;
3566 }
6d27d3a2 3567
355afbcd
KR		 3568 if (the_ins.nfrag == 0)
3569 { /* No frag hacking involved; just put it out */
3570 toP = frag_more (2 * the_ins.numo);
3571 fromP = &the_ins.opcode[0];
3572 for (m = the_ins.numo; m; --m)
3573 {
3574 md_number_to_chars (toP, (long) (*fromP), 2);
3575 toP += 2;
3576 fromP++;
f8701a3f 3577 }
355afbcd
KR		 3578 /* put out symbol-dependent info */
3579 for (m = 0; m < the_ins.nrel; m++)
3580 {
3581 switch (the_ins.reloc[m].wid)
3582 {
3583 case 'B':
3584 n = 1;
3585 break;
3586 case 'b':
3587 n = 1;
3588 break;
3589 case '3':
3590 n = 2;
3591 break;
3592 case 'w':
3593 n = 2;
3594 break;
3595 case 'l':
3596 n = 4;
3597 break;
3598 default:
3599 as_fatal ("Don't know how to figure width of %c in md_assemble()", the_ins.reloc[m].wid);
3600 }
6d27d3a2 3601
355afbcd
KR		 3602 fix_new (frag_now,
3603 (toP - frag_now->fr_literal) - the_ins.numo * 2 + the_ins.reloc[m].n,
3604 n,
3605 the_ins.reloc[m].add,
3606 the_ins.reloc[m].sub,
3607 the_ins.reloc[m].off,
3608 the_ins.reloc[m].pcrel,
3609 NO_RELOC);
f8701a3f 3610 }
355afbcd
KR		 3611 return;
3612 }
3613
3614 /* There's some frag hacking */
3615 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3616 {
3617 int wid;
3618
3619 if (n == 0)
3620 wid = 2 * the_ins.fragb[n].fragoff;
3621 else
3622 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3623 toP = frag_more (wid);
3624 to_beg_P = toP;
3625 shorts_this_frag = 0;
3626 for (m = wid / 2; m; --m)
3627 {
3628 md_number_to_chars (toP, (long) (*fromP), 2);
3629 toP += 2;
3630 fromP++;
3631 shorts_this_frag++;
3632 }
3633 for (m = 0; m < the_ins.nrel; m++)
3634 {
3635 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag /* 2*the_ins.fragb[n].fragoff */ )
3636 {
3637 the_ins.reloc[m].n -= 2 * shorts_this_frag /* 2*the_ins.fragb[n].fragoff */ ;
3638 break;
3639 }
3640 wid = the_ins.reloc[m].wid;
3641 if (wid == 0)
3642 continue;
3643 the_ins.reloc[m].wid = 0;
3644 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3645
3646 fix_new (frag_now,
3647 (toP - frag_now->fr_literal) - the_ins.numo * 2 + the_ins.reloc[m].n,
3648 wid,
3649 the_ins.reloc[m].add,
3650 the_ins.reloc[m].sub,
3651 the_ins.reloc[m].off,
3652 the_ins.reloc[m].pcrel,
3653 NO_RELOC);
fecd2382 3654 }
355afbcd
KR		 3655 /* know(the_ins.fragb[n].fadd); */
3656 (void) frag_var (rs_machine_dependent, 10, 0, (relax_substateT) (the_ins.fragb[n].fragty),
3657 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3658 }
3659 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3660 shorts_this_frag = 0;
3661 if (n)
3662 {
3663 toP = frag_more (n * sizeof (short));
3664 while (n--)
3665 {
3666 md_number_to_chars (toP, (long) (*fromP), 2);
3667 toP += 2;
3668 fromP++;
3669 shorts_this_frag++;
fecd2382 3670 }
355afbcd
KR		 3671 }
3672 for (m = 0; m < the_ins.nrel; m++)
3673 {
3674 int wid;
3675
3676 wid = the_ins.reloc[m].wid;
3677 if (wid == 0)
3678 continue;
3679 the_ins.reloc[m].wid = 0;
3680 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3681
3682 fix_new (frag_now,
3683 (the_ins.reloc[m].n + toP - frag_now->fr_literal) - /* the_ins.numo */ shorts_this_frag * 2,
3684 wid,
3685 the_ins.reloc[m].add,
3686 the_ins.reloc[m].sub,
3687 the_ins.reloc[m].off,
3688 the_ins.reloc[m].pcrel,
3689 NO_RELOC);
3690 }
fecd2382
RP		 3691}
3692
f8701a3f 3693
f8701a3f 3694
fecd2382 3695void
355afbcd 3696md_begin ()
fecd2382 3697{
355afbcd 3698 /*
f8701a3f
SC		 3699 * md_begin -- set up hash tables with 68000 instructions.
3700 * similar to what the vax assembler does. ---phr
3701 */
355afbcd 3702 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
f8701a3f
SC		 3703 a copy of it at runtime, adding in the information we want but isn't
3704 there. I think it'd be better to have an awk script hack the table
3705 at compile time. Or even just xstr the table and use it as-is. But
3706 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3707 names. */
6d27d3a2 3708
355afbcd
KR		 3709 register const struct m68k_opcode *ins;
3710 register struct m68k_incant *hack, *slak;
3711 register char *retval = 0; /* empty string, or error msg text */
3712 register unsigned int i;
3713 register char c;
3714
3715 if ((op_hash = hash_new ()) == NULL)
3716 as_fatal ("Virtual memory exhausted");
3717
3718 obstack_begin (&robyn, 4000);
3719 for (ins = m68k_opcodes; ins < endop; ins++)
3720 {
3721 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3722 do
3723 {
3724 /* we *could* ignore insns that don't match our
f8701a3f
SC		 3725 arch here but just leaving them out of the
3726 hash. */
355afbcd
KR		 3727 slak->m_operands = ins->args;
3728 slak->m_opnum = strlen (slak->m_operands) / 2;
3729 slak->m_arch = ins->arch;
3730 slak->m_opcode = ins->opcode;
3731 /* This is kludgey */
3732 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3733 if ((ins + 1) != endop && !strcmp (ins->name, (ins + 1)->name))
3734 {
3735 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3736 ins++;
3737 }
3738 else
3739 slak->m_next = 0;
3740 slak = slak->m_next;
f8701a3f 3741 }
355afbcd
KR		 3742 while (slak);
3743
3744 retval = hash_insert (op_hash, ins->name, (char *) hack);
3745 /* Didn't his mommy tell him about null pointers? */
3746 if (retval && *retval)
3747 as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval);
3748 }
6d27d3a2 3749
355afbcd
KR		 3750 for (i = 0; i < sizeof (mklower_table); i++)
3751 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3752
355afbcd
KR		 3753 for (i = 0; i < sizeof (notend_table); i++)
3754 {
3755 notend_table[i] = 0;
3756 alt_notend_table[i] = 0;
3757 }
3758 notend_table[','] = 1;
3759 notend_table['{'] = 1;
3760 notend_table['}'] = 1;
3761 alt_notend_table['a'] = 1;
3762 alt_notend_table['A'] = 1;
3763 alt_notend_table['d'] = 1;
3764 alt_notend_table['D'] = 1;
3765 alt_notend_table['#'] = 1;
3766 alt_notend_table['f'] = 1;
3767 alt_notend_table['F'] = 1;
fecd2382 3768#ifdef REGISTER_PREFIX
355afbcd 3769 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3770#endif
0069b1f6 3771#ifdef OPTIONAL_REGISTER_PREFIX
355afbcd 3772 alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1;
0069b1f6 3773#endif
f8701a3f 3774
3ad9ec6a 3775#ifndef MIT_SYNTAX_ONLY
355afbcd 3776 /* Insert pseudo ops, these have to go into the opcode table since
3ad9ec6a 3777 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3778 {
3779 int n = 0;
3780 while (mote_pseudo_table[n].poc_name)
3781 {
3782 hack = (struct m68k_incant *)
3783 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3784 hash_insert (op_hash,
3785 mote_pseudo_table[n].poc_name, (char *) hack);
3786 hack->m_operands = 0;
3787 hack->m_opnum = n;
3788 n++;
3789 }
3790 }
3ad9ec6a
ILT		 3791#endif
3792
355afbcd 3793 init_regtable ();
fecd2382
RP		 3794}
3795
3796#if 0
3797#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
a39116f1
RP		 3798 || (*s == ':' && strchr("aAdD#", s[1]))) \
3799 ? 0 : 1)
fecd2382
RP		 3800#endif
3801
3802/* This funciton is called once, before the assembler exits. It is
3803 supposed to do any final cleanup for this part of the assembler.
a39116f1 3804 */
fecd2382 3805void
355afbcd 3806md_end ()
fecd2382
RP		 3807{
3808}
3809
3810/* Equal to MAX_PRECISION in atof-ieee.c */
3811#define MAX_LITTLENUMS 6
3812
3813/* Turn a string in input_line_pointer into a floating point constant of type
3814 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3815 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
a39116f1 3816 */
fecd2382 3817char *
355afbcd
KR		 3818md_atof (type, litP, sizeP)
3819 char type;
3820 char *litP;
3821 int *sizeP;
fecd2382 3822{
355afbcd
KR		 3823 int prec;
3824 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3825 LITTLENUM_TYPE *wordP;
3826 char *t;
3827 char *atof_ieee ();
6d27d3a2 3828
355afbcd
KR		 3829 switch (type)
3830 {
3831 case 'f':
3832 case 'F':
3833 case 's':
3834 case 'S':
3835 prec = 2;
3836 break;
6d27d3a2 3837
355afbcd
KR		 3838 case 'd':
3839 case 'D':
3840 case 'r':
3841 case 'R':
3842 prec = 4;
3843 break;
6d27d3a2 3844
355afbcd
KR		 3845 case 'x':
3846 case 'X':
3847 prec = 6;
3848 break;
6d27d3a2 3849
355afbcd
KR		 3850 case 'p':
3851 case 'P':
3852 prec = 6;
3853 break;
6d27d3a2 3854
355afbcd
KR		 3855 default:
3856 *sizeP = 0;
3857 return "Bad call to MD_ATOF()";
3858 }
3859 t = atof_ieee (input_line_pointer, type, words);
3860 if (t)
3861 input_line_pointer = t;
3862
3863 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3864 for (wordP = words; prec--;)
3865 {
3866 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3867 litP += sizeof (LITTLENUM_TYPE);
3868 }
3869 return ""; /* Someone should teach Dean about null pointers */
fecd2382
RP		 3870}
3871
3872/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3873 for use in the a.out file, and stores them in the array pointed to by buf.
3874 This knows about the endian-ness of the target machine and does
3875 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3876 2 (short) and 4 (long) Floating numbers are put out as a series of
3877 LITTLENUMS (shorts, here at least)
a39116f1 3878 */
fecd2382 3879void
355afbcd
KR		 3880md_number_to_chars (buf, val, n)
3881 char *buf;
3882 long val;
3883 int n;
fecd2382 3884{
355afbcd
KR		 3885 switch (n)
3886 {
3887 case 1:
3888 *buf++ = val;
3889 break;
3890 case 2:
3891 *buf++ = (val >> 8);
3892 *buf++ = val;
3893 break;
3894 case 4:
3895 *buf++ = (val >> 24);
3896 *buf++ = (val >> 16);
3897 *buf++ = (val >> 8);
3898 *buf++ = val;
3899 break;
3900 default:
3901 as_fatal ("failed sanity check.");
3902 }
fecd2382
RP		 3903}
3904
3905void
355afbcd
KR		 3906md_apply_fix (fixP, val)
3907 fixS *fixP;
3908 long val;
fecd2382 3909{
587c4264 3910#ifdef IBM_COMPILER_SUX
355afbcd 3911 /* This is unnecessary but it convinces the native rs6000
587c4264 3912 compiler to generate the code we want. */
355afbcd
KR		 3913 char *buf = fixP->fx_frag->fr_literal;
3914 buf += fixP->fx_where;
587c4264 3915#else /* IBM_COMPILER_SUX */
355afbcd 3916 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
587c4264 3917#endif /* IBM_COMPILER_SUX */
6d27d3a2 3918
355afbcd
KR		 3919 switch (fixP->fx_size)
3920 {
3921 case 1:
3922 *buf++ = val;
3923 break;
3924 case 2:
3925 *buf++ = (val >> 8);
3926 *buf++ = val;
3927 break;
3928 case 4:
3929 *buf++ = (val >> 24);
3930 *buf++ = (val >> 16);
3931 *buf++ = (val >> 8);
3932 *buf++ = val;
3933 break;
3934 default:
3935 BAD_CASE (fixP->fx_size);
3936 }
fecd2382
RP		 3937}
3938
3939
3940/* *fragP has been relaxed to its final size, and now needs to have
3941 the bytes inside it modified to conform to the new size There is UGLY
3942 MAGIC here. ..
a39116f1 3943 */
fecd2382 3944void
355afbcd
KR		 3945md_convert_frag (headers, fragP)
3946 object_headers *headers;
3947 register fragS *fragP;
fecd2382 3948{
355afbcd
KR		 3949 long disp;
3950 long ext = 0;
6d27d3a2 3951
355afbcd
KR		 3952 /* Address in object code of the displacement. */
3953 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 3954
f6e504fe 3955#ifdef IBM_COMPILER_SUX
355afbcd 3956 /* This is wrong but it convinces the native rs6000 compiler to
f8701a3f 3957 generate the code we want. */
355afbcd
KR		 3958 register char *buffer_address = fragP->fr_literal;
3959 buffer_address += fragP->fr_fix;
f6e504fe 3960#else /* IBM_COMPILER_SUX */
355afbcd
KR		 3961 /* Address in gas core of the place to store the displacement. */
3962 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
f6e504fe 3963#endif /* IBM_COMPILER_SUX */
6d27d3a2 3964
355afbcd 3965 /* No longer true: know(fragP->fr_symbol); */
6d27d3a2 3966
355afbcd
KR		 3967 /* The displacement of the address, from current location. */
3968 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3969 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 3970
355afbcd
KR		 3971 switch (fragP->fr_subtype)
3972 {
3973 case TAB (BCC68000, BYTE):
3974 case TAB (ABRANCH, BYTE):
3975 know (issbyte (disp));
3976 if (disp == 0)
3977 as_bad ("short branch with zero offset: use :w");
3978 fragP->fr_opcode[1] = disp;
3979 ext = 0;
3980 break;
3981 case TAB (DBCC, SHORT):
3982 know (issword (disp));
3983 ext = 2;
3984 break;
3985 case TAB (BCC68000, SHORT):
3986 case TAB (ABRANCH, SHORT):
3987 know (issword (disp));
3988 fragP->fr_opcode[1] = 0x00;
3989 ext = 2;
3990 break;
3991 case TAB (ABRANCH, LONG):
3992 if (cpu_of_arch (current_architecture) < m68020)
3993 {
3994 if (fragP->fr_opcode[0] == 0x61)
3995 {
3996 fragP->fr_opcode[0] = 0x4E;
3997 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */
3998 subseg_change (SEG_TEXT, 0);
3999
4000 fix_new (fragP,
4001 fragP->fr_fix,
4002 4,
4003 fragP->fr_symbol,
4004 0,
4005 fragP->fr_offset,
4006 0,
4007 NO_RELOC);
4008
4009 fragP->fr_fix += 4;
4010 ext = 0;
4011 }
4012 else if (fragP->fr_opcode[0] == 0x60)
4013 {
4014 fragP->fr_opcode[0] = 0x4E;
4015 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */
4016 subseg_change (SEG_TEXT, 0);
4017 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0,
4018 NO_RELOC);
4019 fragP->fr_fix += 4;
4020 ext = 0;
4021 }
4022 else
4023 {
4024 as_bad ("Long branch offset not supported.");
4025 }
4026 }
4027 else
4028 {
4029 fragP->fr_opcode[1] = 0xff;
4030 ext = 4;
4031 }
4032 break;
4033 case TAB (BCC68000, LONG):
4034 /* only Bcc 68000 instructions can come here */
4035 /* change bcc into b!cc/jmp absl long */
4036 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4037 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 4038
355afbcd 4039 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 4040 different frag, in which case refering to them is a no-no.
4041 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd
KR		 4042 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4043 *buffer_address++ = 0xf9;
4044 fragP->fr_fix += 2; /* account for jmp instruction */
4045 subseg_change (SEG_TEXT, 0);
4046 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4047 fragP->fr_offset, 0,
4048 NO_RELOC);
4049 fragP->fr_fix += 4;
4050 ext = 0;
4051 break;
4052 case TAB (DBCC, LONG):
4053 /* only DBcc 68000 instructions can come here */
4054 /* change dbcc into dbcc/jmp absl long */
4055 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4056 *buffer_address++ = 0x00; /* branch offset = 4 */
4057 *buffer_address++ = 0x04;
4058 *buffer_address++ = 0x60; /* put in bra pc+6 */
4059 *buffer_address++ = 0x06;
4060 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4061 *buffer_address++ = 0xf9;
4062
4063 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4064 subseg_change (SEG_TEXT, 0);
4065 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4066 fragP->fr_offset, 0,
4067 NO_RELOC);
4068 fragP->fr_fix += 4;
4069 ext = 0;
4070 break;
4071 case TAB (FBRANCH, SHORT):
4072 know ((fragP->fr_opcode[1] & 0x40) == 0);
4073 ext = 2;
4074 break;
4075 case TAB (FBRANCH, LONG):
4076 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4077 ext = 4;
4078 break;
4079 case TAB (PCREL, SHORT):
4080 ext = 2;
4081 break;
4082 case TAB (PCREL, LONG):
4083 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 4084 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd
KR		 4085 /* JF FOO This code has not been tested */
4086 subseg_change (SEG_TEXT, 0);
4087 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4088 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4089 as_bad ("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
4090 fragP->fr_opcode[0], fragP->fr_address);
4091 fragP->fr_opcode[1] &= ~0x3F;
4092 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4093 fragP->fr_fix += 4;
4094 /* md_number_to_chars(buffer_address,
a39116f1
RP		 4095 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
4096 4); */
355afbcd
KR		 4097 ext = 0;
4098 break;
4099 case TAB (PCLEA, SHORT):
4100 subseg_change (SEG_TEXT, 0);
4101 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, (symbolS *) 0, fragP->fr_offset, 1,
4102 NO_RELOC);
4103 fragP->fr_opcode[1] &= ~0x3F;
4104 fragP->fr_opcode[1] |= 0x3A;
4105 ext = 2;
4106 break;
4107 case TAB (PCLEA, LONG):
4108 subseg_change (SEG_TEXT, 0);
4109 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol, (symbolS *) 0, fragP->fr_offset + 2, 1,
4110 NO_RELOC);
4111 *buffer_address++ = 0x01;
4112 *buffer_address++ = 0x70;
4113 fragP->fr_fix += 2;
4114 /* buffer_address+=2; */
4115 ext = 4;
4116 break;
4117
4118 } /* switch on subtype */
4119
4120 if (ext)
4121 {
4122 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4123 fragP->fr_fix += ext;
4124 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
4125 } /* if extending */
4126
4127 return;
4128} /* md_convert_frag() */
4129
4130/* Force truly undefined symbols to their maximum size, and generally set up
4131 the frag list to be relaxed
4132 */
4133int
4134md_estimate_size_before_relax (fragP, segment)
4135 register fragS *fragP;
4136 segT segment;
4137{
4138 int old_fix;
4139 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4140
4141 old_fix = fragP->fr_fix;
4142
4143 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4144 switch (fragP->fr_subtype)
4145 {
4146
4147 case TAB (ABRANCH, SZ_UNDEF):
4148 {
4149 if ((fragP->fr_symbol != NULL) /* Not absolute */
4150 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4151 {
4152 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4153 break;
4154 }
4155 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4156 {
4157 /* On 68000, or for absolute value, switch to abs long */
4158 /* FIXME, we should check abs val, pick short or long */
4159 if (fragP->fr_opcode[0] == 0x61)
4160 {
4161 fragP->fr_opcode[0] = 0x4E;
4162 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */
4163 subseg_change (SEG_TEXT, 0);
4164 fix_new (fragP, fragP->fr_fix, 4,
4165 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4166 fragP->fr_fix += 4;
4167 frag_wane (fragP);
4168 }
4169 else if (fragP->fr_opcode[0] == 0x60)
4170 {
4171 fragP->fr_opcode[0] = 0x4E;
4172 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */
4173 subseg_change (SEG_TEXT, 0);
4174 fix_new (fragP, fragP->fr_fix, 4,
4175 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4176 fragP->fr_fix += 4;
4177 frag_wane (fragP);
4178 }
4179 else
4180 {
4181 as_warn ("Long branch offset to extern symbol not supported.");
4182 }
4183 }
4184 else
4185 { /* Symbol is still undefined. Make it simple */
4186 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4187 (symbolS *) 0, fragP->fr_offset + 4, 1, NO_RELOC);
4188 fragP->fr_fix += 4;
4189 fragP->fr_opcode[1] = 0xff;
4190 frag_wane (fragP);
4191 break;
4192 }
4193
a39116f1 4194 break;
355afbcd 4195 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 4196
355afbcd
KR		 4197 case TAB (FBRANCH, SZ_UNDEF):
4198 {
4199 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4200 {
4201 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4202 fragP->fr_var += 2;
4203 }
4204 else
4205 {
4206 fragP->fr_subtype = TAB (FBRANCH, LONG);
4207 fragP->fr_var += 4;
4208 }
4209 break;
4210 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 4211
355afbcd
KR		 4212 case TAB (PCREL, SZ_UNDEF):
4213 {
4214 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4215 {
4216 fragP->fr_subtype = TAB (PCREL, SHORT);
4217 fragP->fr_var += 2;
4218 }
4219 else
4220 {
4221 fragP->fr_subtype = TAB (PCREL, LONG);
4222 fragP->fr_var += 4;
4223 }
4224 break;
4225 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 4226
355afbcd
KR		 4227 case TAB (BCC68000, SZ_UNDEF):
4228 {
4229 if ((fragP->fr_symbol != NULL)
4230 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4231 {
4232 fragP->fr_subtype = TAB (BCC68000, BYTE);
4233 break;
4234 }
4235 /* only Bcc 68000 instructions can come here */
4236 /* change bcc into b!cc/jmp absl long */
4237 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4238 if (flagseen['l'])
4239 {
4240 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4241 /* JF: these were fr_opcode[2,3] */
4242 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4243 buffer_address[1] = 0xf8;
4244 fragP->fr_fix += 2; /* account for jmp instruction */
4245 subseg_change (SEG_TEXT, 0);
4246 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
4247 fragP->fr_offset, 0, NO_RELOC);
4248 fragP->fr_fix += 2;
4249 }
4250 else
4251 {
4252 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4253 /* JF: these were fr_opcode[2,3] */
4254 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4255 buffer_address[1] = 0xf9;
4256 fragP->fr_fix += 2; /* account for jmp instruction */
4257 subseg_change (SEG_TEXT, 0);
4258 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4259 fragP->fr_offset, 0, NO_RELOC);
4260 fragP->fr_fix += 4;
4261 }
4262 frag_wane (fragP);
4263 break;
4264 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 4265
355afbcd
KR		 4266 case TAB (DBCC, SZ_UNDEF):
4267 {
4268 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4269 {
4270 fragP->fr_subtype = TAB (DBCC, SHORT);
4271 fragP->fr_var += 2;
4272 break;
4273 }
4274 /* only DBcc 68000 instructions can come here */
4275 /* change dbcc into dbcc/jmp absl long */
4276 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4277 buffer_address[0] = 0x00; /* branch offset = 4 */
4278 buffer_address[1] = 0x04;
4279 buffer_address[2] = 0x60; /* put in bra pc + ... */
4280
4281 if (flagseen['l'])
4282 {
4283 /* JF: these were fr_opcode[5-7] */
4284 buffer_address[3] = 0x04; /* plus 4 */
4285 buffer_address[4] = 0x4e; /* Put in Jump Word */
4286 buffer_address[5] = 0xf8;
4287 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4288 subseg_change (SEG_TEXT, 0);
4289 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
6d27d3a2 4290
6d27d3a2 4291
355afbcd
KR		 4292 fragP->fr_offset, 0, NO_RELOC);
4293 fragP->fr_fix += 2;
4294 }
4295 else
4296 {
4297 /* JF: these were fr_opcode[5-7] */
4298 buffer_address[3] = 0x06; /* Plus 6 */
4299 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4300 buffer_address[5] = 0xf9;
4301 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4302 subseg_change (SEG_TEXT, 0);
4303 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4304 fragP->fr_offset, 0, NO_RELOC);
4305 fragP->fr_fix += 4;
4306 }
6d27d3a2 4307
355afbcd
KR		 4308 frag_wane (fragP);
4309 break;
4310 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 4311
355afbcd
KR		 4312 case TAB (PCLEA, SZ_UNDEF):
4313 {
4314 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l'])
4315 {
4316 fragP->fr_subtype = TAB (PCLEA, SHORT);
4317 fragP->fr_var += 2;
4318 }
4319 else
4320 {
4321 fragP->fr_subtype = TAB (PCLEA, LONG);
4322 fragP->fr_var += 6;
4323 }
4324 break;
4325 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 4326
355afbcd
KR		 4327 default:
4328 break;
6d27d3a2 4329
355afbcd 4330 } /* switch on subtype looking for SZ_UNDEF's. */
6d27d3a2 4331
355afbcd
KR		 4332 /* now that SZ_UNDEF are taken care of, check others */
4333 switch (fragP->fr_subtype)
4334 {
4335 case TAB (BCC68000, BYTE):
4336 case TAB (ABRANCH, BYTE):
4337 /* We can't do a short jump to the next instruction,
a39116f1 4338 so we force word mode. */
355afbcd
KR		 4339 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4340 fragP->fr_symbol->sy_frag == fragP->fr_next)
4341 {
4342 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4343 fragP->fr_var += 2;
fecd2382 4344 }
355afbcd
KR		 4345 break;
4346 default:
4347 break;
4348 }
4349 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 4350}
4351
4352#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 4353/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 4354 with the byte-order problems of cross-assembly. So as a hack,
4355 I added this mach. dependent ri twiddler. Ugly, but it gets
4356 you there. -KWK */
4357/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 4358 are symbolnum, most sig. byte first. Last byte is broken up with
4359 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4360 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 4361/* Translate the internal relocation information into target-specific
4362 format. */
a79c6033 4363#ifdef comment
fecd2382 4364void
355afbcd
KR		 4365md_ri_to_chars (the_bytes, ri)
4366 char *the_bytes;
4367 struct reloc_info_generic *ri;
fecd2382 4368{
355afbcd
KR		 4369 /* this is easy */
4370 md_number_to_chars (the_bytes, ri->r_address, 4);
4371 /* now the fun stuff */
4372 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4373 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4374 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4375 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4376 ((ri->r_extern << 4) & 0x10));
fecd2382 4377}
355afbcd 4378
a79c6033
RP		 4379#endif /* comment */
4380
355afbcd
KR		 4381void
4382tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4383 char *where;
4384 fixS *fixP;
4385 relax_addressT segment_address_in_file;
a79c6033 4386{
355afbcd 4387 /*
f8701a3f
SC		 4388 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4389 * Out: GNU LD relocation length code: 0, 1, or 2.
4390 */
6d27d3a2 4391
355afbcd
KR		 4392 static unsigned char nbytes_r_length[] =
4393 {42, 0, 1, 42, 2};
4394 long r_symbolnum;
6d27d3a2 4395
355afbcd 4396 know (fixP->fx_addsy != NULL);
6d27d3a2 4397
355afbcd
KR		 4398 md_number_to_chars (where,
4399 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4400 4);
6d27d3a2 4401
355afbcd
KR		 4402 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4403 ? S_GET_TYPE (fixP->fx_addsy)
4404 : fixP->fx_addsy->sy_number);
6d27d3a2 4405
355afbcd
KR		 4406 where[4] = (r_symbolnum >> 16) & 0x0ff;
4407 where[5] = (r_symbolnum >> 8) & 0x0ff;
4408 where[6] = r_symbolnum & 0x0ff;
4409 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4410 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
6d27d3a2 4411
355afbcd
KR		 4412 return;
4413} /* tc_aout_fix_to_chars() */
a79c6033 4414
fecd2382
RP		 4415#endif /* OBJ_AOUT or OBJ_BOUT */
4416
4417#ifndef WORKING_DOT_WORD
4418const int md_short_jump_size = 4;
4419const int md_long_jump_size = 6;
4420
4421void
355afbcd
KR		 4422md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4423 char *ptr;
4424 long from_addr, to_addr;
4425 fragS *frag;
4426 symbolS *to_symbol;
fecd2382 4427{
355afbcd 4428 long offset;
6d27d3a2 4429
355afbcd 4430 offset = to_addr - (from_addr + 2);
6d27d3a2 4431
355afbcd
KR		 4432 md_number_to_chars (ptr, (long) 0x6000, 2);
4433 md_number_to_chars (ptr + 2, (long) offset, 2);
fecd2382
RP		 4434}
4435
4436void
355afbcd
KR		 4437md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4438 char *ptr;
4439 long from_addr, to_addr;
4440 fragS *frag;
4441 symbolS *to_symbol;
fecd2382 4442{
355afbcd
KR		 4443 long offset;
4444
4445 if (cpu_of_arch (current_architecture) < m68020)
4446 {
4447 offset = to_addr - S_GET_VALUE (to_symbol);
4448 md_number_to_chars (ptr, (long) 0x4EF9, 2);
4449 md_number_to_chars (ptr + 2, (long) offset, 4);
4450 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (symbolS *) 0, (long) 0, 0,
4451 NO_RELOC);
4452 }
4453 else
4454 {
4455 offset = to_addr - (from_addr + 2);
4456 md_number_to_chars (ptr, (long) 0x60ff, 2);
4457 md_number_to_chars (ptr + 2, (long) offset, 4);
4458 }
fecd2382
RP		 4459}
4460
4461#endif
4462/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
6d27d3a2 4463
a39116f1
RP		 4464 0: Everything is OK
4465 10: Absolute 1:8 only
4466 20: Absolute 0:7 only
4467 30: absolute 0:15 only
4468 40: Absolute 0:31 only
4469 50: absolute 0:127 only
4470 55: absolute -64:63 only
4471 60: absolute -128:127 only
4472 70: absolute 0:4095 only
4473 80: No bignums
6d27d3a2 4474
a39116f1 4475 */
fecd2382 4476
355afbcd
KR		 4477static int
4478get_num (exp, ok)
4479 struct m68k_exp *exp;
4480 int ok;
fecd2382
RP		 4481{
4482#ifdef TEST2
355afbcd 4483 long l = 0;
6d27d3a2 4484
355afbcd
KR		 4485 if (!exp->e_beg)
4486 return 0;
4487 if (*exp->e_beg == '0')
4488 {
4489 if (exp->e_beg[1] == 'x')
4490 sscanf (exp->e_beg + 2, "%x", &l);
4491 else
4492 sscanf (exp->e_beg + 1, "%O", &l);
4493 return l;
4494 }
4495 return atol (exp->e_beg);
fecd2382 4496#else
355afbcd
KR		 4497 char *save_in;
4498 char c_save;
6d27d3a2 4499
355afbcd
KR		 4500 if (!exp)
4501 {
4502 /* Can't do anything */
4503 return 0;
4504 }
4505 if (!exp->e_beg || !exp->e_end)
4506 {
4507 seg (exp) = SEG_ABSOLUTE;
4508 adds (exp) = 0;
4509 subs (exp) = 0;
4510 offs (exp) = (ok == 10) ? 1 : 0;
4511 as_warn ("Null expression defaults to %ld", offs (exp));
4512 return 0;
4513 }
6d27d3a2 4514
355afbcd
KR		 4515 exp->e_siz = 0;
4516 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4517 && (exp->e_end - exp->e_beg) >= 2)
4518 {
4519 switch (exp->e_end[0])
4520 {
4521 case 's':
4522 case 'S':
4523 case 'b':
4524 case 'B':
4525 exp->e_siz = 1;
4526 exp->e_end -= 2;
4527 break;
4528 case 'w':
4529 case 'W':
4530 exp->e_siz = 2;
4531 exp->e_end -= 2;
4532 break;
4533 case 'l':
4534 case 'L':
4535 exp->e_siz = 3;
4536 exp->e_end -= 2;
4537 break;
4538 default:
4539 if (exp->e_end[-1] == ':')
4540 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4541 break;
fecd2382 4542 }
355afbcd
KR		 4543 }
4544 c_save = exp->e_end[1];
4545 exp->e_end[1] = '\0';
4546 save_in = input_line_pointer;
4547 input_line_pointer = exp->e_beg;
4548 switch (expression (&(exp->e_exp)))
4549 {
4550 case SEG_PASS1:
4551 seg (exp) = SEG_ABSOLUTE;
4552 adds (exp) = 0;
4553 subs (exp) = 0;
4554 offs (exp) = (ok == 10) ? 1 : 0;
4555 as_warn ("Unknown expression: '%s' defaulting to %d", exp->e_beg, offs (exp));
4556 break;
6d27d3a2 4557
355afbcd
KR		 4558 case SEG_ABSENT:
4559 /* Do the same thing the VAX asm does */
4560 seg (exp) = SEG_ABSOLUTE;
4561 adds (exp) = 0;
4562 subs (exp) = 0;
4563 offs (exp) = 0;
4564 if (ok == 10)
4565 {
4566 as_warn ("expression out of range: defaulting to 1");
4567 offs (exp) = 1;
4568 }
4569 break;
4570 case SEG_ABSOLUTE:
4571 switch (ok)
4572 {
4573 case 10:
4574 if (offs (exp) < 1 || offs (exp) > 8)
4575 {
4576 as_warn ("expression out of range: defaulting to 1");
4577 offs (exp) = 1;
4578 }
4579 break;
4580 case 20:
4581 if (offs (exp) < 0 || offs (exp) > 7)
4582 goto outrange;
4583 break;
4584 case 30:
4585 if (offs (exp) < 0 || offs (exp) > 15)
4586 goto outrange;
4587 break;
4588 case 40:
4589 if (offs (exp) < 0 || offs (exp) > 32)
4590 goto outrange;
4591 break;
4592 case 50:
4593 if (offs (exp) < 0 || offs (exp) > 127)
4594 goto outrange;
4595 break;
4596 case 55:
4597 if (offs (exp) < -64 || offs (exp) > 63)
4598 goto outrange;
4599 break;
4600 case 60:
4601 if (offs (exp) < -128 || offs (exp) > 127)
4602 goto outrange;
4603 break;
4604 case 70:
4605 if (offs (exp) < 0 || offs (exp) > 4095)
4606 {
4607 outrange:
4608 as_warn ("expression out of range: defaulting to 0");
4609 offs (exp) = 0;
4610 }
4611 break;
fecd2382 4612 default:
355afbcd
KR		 4613 break;
4614 }
4615 break;
4616 case SEG_BIG:
4617 if (offs (exp) < 0 /* flonum */
4618 && (ok == 80 /* no bignums */
4619 || (ok > 10 /* small-int ranges including 0 ok */
4620 /* If we have a flonum zero, a zero integer should
4621 do as well (e.g., in moveq). */
4622 && generic_floating_point_number.exponent == 0
4623 && generic_floating_point_number.low[0] == 0)))
4624 {
4625 /* HACK! Turn it into a long */
4626 LITTLENUM_TYPE words[6];
4627
4628 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4629 seg (exp) = SEG_ABSOLUTE;
4630 adds (exp) = 0;
4631 subs (exp) = 0;
4632 offs (exp) = words[1] | (words[0] << 16);
4633 }
4634 else if (ok != 0)
4635 {
4636 seg (exp) = SEG_ABSOLUTE;
4637 adds (exp) = 0;
4638 subs (exp) = 0;
4639 offs (exp) = (ok == 10) ? 1 : 0;
4640 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4641 }
4642 break;
4643 default:
4644 case SEG_TEXT:
4645 case SEG_DATA:
4646 case SEG_BSS:
4647 case SEG_UNKNOWN:
4648 case SEG_DIFFERENCE:
4649 if (ok >= 10 && ok <= 70)
4650 {
4651 seg (exp) = SEG_ABSOLUTE;
4652 adds (exp) = 0;
4653 subs (exp) = 0;
4654 offs (exp) = (ok == 10) ? 1 : 0;
4655 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4656 }
4657 break;
587c4264
ILT		 4658
4659
355afbcd
KR		 4660 }
4661 if (input_line_pointer != exp->e_end + 1)
4662 as_bad ("Ignoring junk after expression");
4663 exp->e_end[1] = c_save;
4664 input_line_pointer = save_in;
4665 if (exp->e_siz)
4666 {
4667 switch (exp->e_siz)
4668 {
4669 case 1:
4670 if (!isbyte (offs (exp)))
4671 as_warn ("expression doesn't fit in BYTE");
4672 break;
4673 case 2:
4674 if (!isword (offs (exp)))
4675 as_warn ("expression doesn't fit in WORD");
4676 break;
a39116f1 4677 }
355afbcd
KR		 4678 }
4679 return offs (exp);
fecd2382 4680#endif
355afbcd 4681} /* get_num() */
fecd2382
RP		 4682
4683/* These are the back-ends for the various machine dependent pseudo-ops. */
355afbcd 4684void demand_empty_rest_of_line (); /* Hate those extra verbose names */
fecd2382 4685
355afbcd
KR		 4686static void
4687s_data1 ()
4688{
4689 subseg_new (SEG_DATA, 1);
4690 demand_empty_rest_of_line ();
4691} /* s_data1() */
fecd2382 4692
355afbcd
KR		 4693static void
4694s_data2 ()
4695{
4696 subseg_new (SEG_DATA, 2);
4697 demand_empty_rest_of_line ();
4698} /* s_data2() */
fecd2382 4699
355afbcd
KR		 4700static void
4701s_bss ()
a1765cf0 4702{
355afbcd 4703 /* We don't support putting frags in the BSS segment, we fake it
a1765cf0
SC		 4704 by marking in_bss, then looking at s_skip for clues */
4705
355afbcd
KR		 4706 subseg_new (SEG_BSS, 0);
4707 demand_empty_rest_of_line ();
4708} /* s_bss() */
6d27d3a2 4709
355afbcd
KR		 4710static void
4711s_even ()
4712{
4713 register int temp;
4714 register long temp_fill;
4715
4716 temp = 1; /* JF should be 2? */
4717 temp_fill = get_absolute_expression ();
4718 if (!need_pass_2) /* Never make frag if expect extra pass. */
4719 frag_align (temp, (int) temp_fill);
4720 demand_empty_rest_of_line ();
4721} /* s_even() */
4722
4723static void
4724s_proc ()
4725{
4726 demand_empty_rest_of_line ();
4727} /* s_proc() */
fecd2382
RP		 4728
4729/* s_space is defined in read.c .skip is simply an alias to it. */
4730
7c15cbe8
RP		 4731/*
4732 * md_parse_option
4733 * Invocation line includes a switch not recognized by the base assembler.
4734 * See if it's a processor-specific option. These are:
4735 *
4736 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4737 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4738 * Select the architecture. Instructions or features not
4739 * supported by the selected architecture cause fatal
4740 * errors. More than one may be specified. The default is
4741 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4742 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 4743 * -[A]m[c]no-68851, -[A]m[c]no-68881
4744 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4745 * so don't use or document it, but that's the way the parsing
4746 * works).
7c15cbe8 4747 *
a39116f1
RP		 4748 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4749 * (e.g. m68020) also requests that float instructions be included. This
4750 * is the default setup, mostly to avoid hassling users. A better
4751 * rearrangement of this structure would be to add an option to DENY
4752 * floating point opcodes, for people who want to really know there's none
4753 * of that funny floaty stuff going on. FIXME-later.
7c15cbe8 4754 */
a39116f1 4755#ifndef MAYBE_FLOAT_TOO
355afbcd 4756#define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
a39116f1 4757#endif
7c15cbe8 4758
355afbcd
KR		 4759int
4760md_parse_option (argP, cntP, vecP)
4761 char **argP;
4762 int *cntP;
4763 char ***vecP;
fecd2382 4764{
355afbcd
KR		 4765 switch (**argP)
4766 {
4767 case 'l': /* -l means keep external to 2 bit offset
f8701a3f 4768 rather than 16 bit one */
355afbcd 4769 break;
6d27d3a2 4770
355afbcd
KR		 4771 case 'S': /* -S means that jbsr's always turn into jsr's. */
4772 break;
6d27d3a2 4773
355afbcd
KR		 4774 case 'A':
4775 (*argP)++;
4776 /* intentional fall-through */
4777 case 'm':
4778 (*argP)++;
4779
4780 if (**argP == 'c')
4781 {
4782 (*argP)++;
4783 } /* allow an optional "c" */
4784
4785 if (!strcmp (*argP, "68000")
4786 || !strcmp (*argP, "68008"))
4787 {
4788 current_architecture |= m68000;
4789 }
4790 else if (!strcmp (*argP, "68010"))
4791 {
fecd2382 4792#ifdef TE_SUN
355afbcd 4793 omagic = 1 << 16 | OMAGIC;
fecd2382 4794#endif
355afbcd 4795 current_architecture |= m68010;
6d27d3a2 4796
355afbcd
KR		 4797 }
4798 else if (!strcmp (*argP, "68020"))
4799 {
4800 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
6d27d3a2 4801
355afbcd
KR		 4802 }
4803 else if (!strcmp (*argP, "68030"))
4804 {
4805 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
6d27d3a2 4806
355afbcd
KR		 4807 }
4808 else if (!strcmp (*argP, "68040"))
4809 {
4810 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
6d27d3a2 4811
7c15cbe8 4812#ifndef NO_68881
355afbcd
KR		 4813 }
4814 else if (!strcmp (*argP, "68881"))
4815 {
4816 current_architecture |= m68881;
6d27d3a2 4817
355afbcd
KR		 4818 }
4819 else if (!strcmp (*argP, "68882"))
4820 {
4821 current_architecture |= m68882;
7c15cbe8 4822#endif /* NO_68881 */
355afbcd 4823 /* Even if we aren't configured to support the processor,
df3768fb
KR		 4824 it should still be possible to assert that the user
4825 doesn't have it... */
355afbcd
KR		 4826 }
4827 else if (!strcmp (*argP, "no-68881")
4828 || !strcmp (*argP, "no-68882"))
4829 {
4830 no_68881 = 1;
7c15cbe8 4831#ifndef NO_68851
355afbcd
KR		 4832 }
4833 else if (!strcmp (*argP, "68851"))
4834 {
4835 current_architecture |= m68851;
7c15cbe8 4836#endif /* NO_68851 */
355afbcd
KR		 4837 }
4838 else if (!strcmp (*argP, "no-68851"))
4839 {
4840 no_68851 = 1;
4841 }
4842 else if (!strcmp (*argP, "pu32"))
4843 { /* "-mcpu32" */
4844 current_architecture |= cpu32;
4845 }
4846 else
4847 {
4848 as_warn ("Unknown architecture, \"%s\". option ignored", *argP);
4849 } /* switch on architecture */
6d27d3a2 4850
355afbcd
KR		 4851 while (**argP)
4852 (*argP)++;
6d27d3a2 4853
355afbcd 4854 break;
6d27d3a2 4855
355afbcd
KR		 4856 case 'p':
4857 if (!strcmp (*argP, "pic"))
4858 {
4859 (*argP) += 3;
4860 break; /* -pic, Position Independent Code */
f8701a3f 4861 }
355afbcd
KR		 4862 else
4863 {
4864 return (0);
4865 } /* pic or not */
4866
4867 default:
4868 return 0;
4869 }
4870 return 1;
fecd2382
RP		 4871}
4872
4873
4874#ifdef TEST2
4875
4876/* TEST2: Test md_assemble() */
4877/* Warning, this routine probably doesn't work anymore */
4878
355afbcd 4879main ()
fecd2382 4880{
355afbcd
KR		 4881 struct m68k_it the_ins;
4882 char buf[120];
4883 char *cp;
4884 int n;
4885
4886 m68k_ip_begin ();
4887 for (;;)
4888 {
4889 if (!gets (buf) || !*buf)
4890 break;
4891 if (buf[0] == '|' || buf[1] == '.')
4892 continue;
4893 for (cp = buf; *cp; cp++)
4894 if (*cp == '\t')
4895 *cp = ' ';
4896 if (is_label (buf))
4897 continue;
4898 memset (&the_ins, '\0', sizeof (the_ins));
4899 m68k_ip (&the_ins, buf);
4900 if (the_ins.error)
4901 {
4902 printf ("Error %s in %s\n", the_ins.error, buf);
4903 }
4904 else
4905 {
4906 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4907 for (n = 0; n < the_ins.numo; n++)
4908 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4909 printf (" ");
4910 print_the_insn (&the_ins.opcode[0], stdout);
4911 (void) putchar ('\n');
4912 }
4913 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4914 {
4915 if (the_ins.operands[n].error)
4916 {
4917 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4918 continue;
4919 }
4920 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4921 if (the_ins.operands[n].b_const)
4922 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4923 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4924 if (the_ins.operands[n].b_iadd)
4925 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4926 (void) putchar ('\n');
a39116f1 4927 }
355afbcd
KR		 4928 }
4929 m68k_ip_end ();
4930 return 0;
fecd2382
RP		 4931}
4932
355afbcd
KR		 4933is_label (str)
4934 char *str;
fecd2382 4935{
355afbcd
KR		 4936 while (*str == ' ')
4937 str++;
4938 while (*str && *str != ' ')
4939 str++;
4940 if (str[-1] == ':' || str[1] == '=')
4941 return 1;
4942 return 0;
fecd2382
RP		 4943}
4944
4945#endif
4946
4947/* Possible states for relaxation:
6d27d3a2 4948
a39116f1
RP		 4949 0 0 branch offset byte (bra, etc)
4950 0 1 word
4951 0 2 long
6d27d3a2 4952
a39116f1
RP		 4953 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4954 1 1 word
4955 1 2 long
6d27d3a2 4956
a39116f1
RP		 4957 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4958 2 1 word-long
4959 2 2 long-word
4960 2 3 long-long
6d27d3a2 4961
a39116f1 4962 */
fecd2382
RP		 4963
4964
4965
4966#ifdef DONTDEF
355afbcd 4967abort ()
fecd2382 4968{
355afbcd
KR		 4969 printf ("ABORT!\n");
4970 exit (12);
fecd2382
RP		 4971}
4972
355afbcd 4973print_frags ()
fecd2382 4974{
355afbcd
KR		 4975 fragS *fragP;
4976 extern fragS *text_frag_root;
6d27d3a2 4977
355afbcd
KR		 4978 for (fragP = text_frag_root; fragP; fragP = fragP->fr_next)
4979 {
4980 printf ("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4981 fragP->fr_address, fragP->fr_next, fragP->fr_fix, fragP->fr_var, fragP->fr_symbol, fragP->fr_offset);
4982 printf ("opcode 0x%x type %d subtype %d\n\n", fragP->fr_opcode, fragP->fr_type, fragP->fr_subtype);
4983 }
4984 fflush (stdout);
4985 return 0;
fecd2382 4986}
355afbcd 4987
fecd2382
RP		 4988#endif
4989
4990#ifdef DONTDEF
4991/*VARARGS1*/
355afbcd
KR		 4992panic (format, args)
4993 char *format;
fecd2382 4994{
355afbcd
KR		 4995 fputs ("Internal error:", stderr);
4996 _doprnt (format, &args, stderr);
4997 (void) putc ('\n', stderr);
4998 as_where ();
4999 abort ();
fecd2382 5000}
355afbcd 5001
fecd2382
RP		 5002#endif
5003
5004/* We have no need to default values of symbols. */
5005
5006/* ARGSUSED */
5007symbolS *
355afbcd
KR		 5008md_undefined_symbol (name)
5009 char *name;
fecd2382 5010{
355afbcd 5011 return 0;
fecd2382
RP		 5012}
5013
6d27d3a2 5014/* Parse an operand that is machine-specific.
fecd2382
RP		 5015 We just return without modifying the expression if we have nothing
5016 to do. */
5017
5018/* ARGSUSED */
5019void
355afbcd
KR		 5020md_operand (expressionP)
5021 expressionS *expressionP;
fecd2382
RP		 5022{
5023}
5024
5025/* Round up a section size to the appropriate boundary. */
5026long
355afbcd
KR		 5027md_section_align (segment, size)
5028 segT segment;
5029 long size;
fecd2382 5030{
355afbcd 5031 return size; /* Byte alignment is fine */
fecd2382
RP		 5032}
5033
5034/* Exactly what point is a PC-relative offset relative TO?
5035 On the 68k, they're relative to the address of the offset, plus
5036 its size. (??? Is this right? FIXME-SOON!) */
5037long
355afbcd
KR		 5038md_pcrel_from (fixP)
5039 fixS *fixP;
fecd2382 5040{
355afbcd 5041 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
fecd2382
RP		 5042}
5043
355afbcd 5044void
3ad9ec6a
ILT		 5045tc_coff_symbol_emit_hook ()
5046{
5047}
5048
355afbcd
KR		 5049int
5050tc_coff_sizemachdep (frag)
5051 fragS *frag;
3ad9ec6a 5052{
355afbcd
KR		 5053 switch (frag->fr_subtype & 0x3)
5054 {
5055 case BYTE:
5056 return 1;
5057 case SHORT:
5058 return 2;
5059 case LONG:
5060 return 4;
5061 default:
5062 abort ();
5063 }
3ad9ec6a
ILT		 5064
5065}
355afbcd 5066
fecd2382
RP		 5067/*
5068 * Local Variables:
5069 * comment-column: 0
5070 * fill-column: 131
5071 * End:
5072 */
5073
5074/* end of tc-m68k.c */
GDB Binutils - Deliverables
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