Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-m68k.c -- Assemble for the m68k family |
f7e42eb4 | 2 | Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
cf869cce | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
5a49b8ac | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
252b5132 RH |
25 | #include "obstack.h" |
26 | #include "subsegs.h" | |
f27a3839 | 27 | #include "dwarf2dbg.h" |
c04898f8 | 28 | #include "dw2gencfi.h" |
252b5132 RH |
29 | |
30 | #include "opcode/m68k.h" | |
31 | #include "m68k-parse.h" | |
32 | ||
0d96863f CM |
33 | #if defined (OBJ_ELF) |
34 | #include "elf/m68k.h" | |
35 | #endif | |
36 | ||
31302357 AS |
37 | #ifdef M68KCOFF |
38 | #include "obj-coff.h" | |
39 | #endif | |
40 | ||
cf869cce NC |
41 | #ifdef OBJ_ELF |
42 | static void m68k_elf_cons (int); | |
43 | #endif | |
44 | ||
252b5132 RH |
45 | /* This string holds the chars that always start a comment. If the |
46 | pre-processor is disabled, these aren't very useful. The macro | |
47 | tc_comment_chars points to this. We use this, rather than the | |
48 | usual comment_chars, so that the --bitwise-or option will work. */ | |
49 | #if defined (TE_SVR4) || defined (TE_DELTA) | |
50 | const char *m68k_comment_chars = "|#"; | |
51 | #else | |
52 | const char *m68k_comment_chars = "|"; | |
53 | #endif | |
54 | ||
55 | /* This array holds the chars that only start a comment at the beginning of | |
56 | a line. If the line seems to have the form '# 123 filename' | |
57 | .line and .file directives will appear in the pre-processed output */ | |
58 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
59 | first line of the input file. This is because the compiler outputs | |
92774660 KH |
60 | #NO_APP at the beginning of its output. */ |
61 | /* Also note that comments like this one will always work. */ | |
252b5132 RH |
62 | const char line_comment_chars[] = "#*"; |
63 | ||
63a0b638 | 64 | const char line_separator_chars[] = ";"; |
252b5132 | 65 | |
36759679 | 66 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
5a38dc70 | 67 | const char EXP_CHARS[] = "eE"; |
252b5132 RH |
68 | |
69 | /* Chars that mean this number is a floating point constant, as | |
70 | in "0f12.456" or "0d1.2345e12". */ | |
71 | ||
5a38dc70 | 72 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
252b5132 RH |
73 | |
74 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
75 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
76 | but nothing is ideal around here. */ | |
77 | ||
252b5132 RH |
78 | /* Are we trying to generate PIC code? If so, absolute references |
79 | ought to be made into linkage table references or pc-relative | |
92774660 | 80 | references. Not implemented. For ELF there are other means |
252b5132 RH |
81 | to denote pic relocations. */ |
82 | int flag_want_pic; | |
83 | ||
36759679 NC |
84 | static int flag_short_refs; /* -l option. */ |
85 | static int flag_long_jumps; /* -S option. */ | |
28e7409f | 86 | static int flag_keep_pcrel; /* --pcrel option. */ |
252b5132 RH |
87 | |
88 | #ifdef REGISTER_PREFIX_OPTIONAL | |
89 | int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
90 | #else | |
91 | int flag_reg_prefix_optional; | |
92 | #endif | |
93 | ||
94 | /* Whether --register-prefix-optional was used on the command line. */ | |
95 | static int reg_prefix_optional_seen; | |
96 | ||
97 | /* The floating point coprocessor to use by default. */ | |
98 | static enum m68k_register m68k_float_copnum = COP1; | |
99 | ||
100 | /* If this is non-zero, then references to number(%pc) will be taken | |
101 | to refer to number, rather than to %pc + number. */ | |
102 | static int m68k_abspcadd; | |
103 | ||
104 | /* If this is non-zero, then the quick forms of the move, add, and sub | |
105 | instructions are used when possible. */ | |
106 | static int m68k_quick = 1; | |
107 | ||
108 | /* If this is non-zero, then if the size is not specified for a base | |
109 | or outer displacement, the assembler assumes that the size should | |
110 | be 32 bits. */ | |
111 | static int m68k_rel32 = 1; | |
112 | ||
113 | /* This is non-zero if m68k_rel32 was set from the command line. */ | |
114 | static int m68k_rel32_from_cmdline; | |
115 | ||
116 | /* The default width to use for an index register when using a base | |
117 | displacement. */ | |
118 | static enum m68k_size m68k_index_width_default = SIZE_LONG; | |
119 | ||
120 | /* We want to warn if any text labels are misaligned. In order to get | |
121 | the right line number, we need to record the line number for each | |
122 | label. */ | |
252b5132 RH |
123 | struct label_line |
124 | { | |
125 | struct label_line *next; | |
126 | symbolS *label; | |
127 | char *file; | |
128 | unsigned int line; | |
129 | int text; | |
130 | }; | |
131 | ||
132 | /* The list of labels. */ | |
133 | ||
134 | static struct label_line *labels; | |
135 | ||
136 | /* The current label. */ | |
137 | ||
138 | static struct label_line *current_label; | |
139 | ||
60fed2d3 NC |
140 | /* Pointer to list holding the opcodes sorted by name. */ |
141 | static struct m68k_opcode const ** m68k_sorted_opcodes; | |
142 | ||
36759679 NC |
143 | /* Its an arbitrary name: This means I don't approve of it. |
144 | See flames below. */ | |
252b5132 RH |
145 | static struct obstack robyn; |
146 | ||
252b5132 RH |
147 | struct m68k_incant |
148 | { | |
149 | const char *m_operands; | |
150 | unsigned long m_opcode; | |
151 | short m_opnum; | |
152 | short m_codenum; | |
153 | int m_arch; | |
154 | struct m68k_incant *m_next; | |
155 | }; | |
156 | ||
157 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
158 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
159 | ||
2da12c60 NS |
160 | static const enum m68k_register m68000_ctrl[] = { 0 }; |
161 | static const enum m68k_register m68010_ctrl[] = { | |
252b5132 RH |
162 | SFC, DFC, USP, VBR, |
163 | 0 | |
164 | }; | |
2da12c60 | 165 | static const enum m68k_register m68020_ctrl[] = { |
252b5132 RH |
166 | SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, |
167 | 0 | |
168 | }; | |
2da12c60 | 169 | static const enum m68k_register m68040_ctrl[] = { |
252b5132 RH |
170 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, |
171 | USP, VBR, MSP, ISP, MMUSR, URP, SRP, | |
172 | 0 | |
173 | }; | |
2da12c60 | 174 | static const enum m68k_register m68060_ctrl[] = { |
252b5132 RH |
175 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, |
176 | USP, VBR, URP, SRP, PCR, | |
177 | 0 | |
178 | }; | |
2da12c60 | 179 | static const enum m68k_register mcf_ctrl[] = { |
3e602632 | 180 | CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, |
78336706 NS |
181 | RAMBAR0, RAMBAR1, RAMBAR, MBAR, |
182 | 0 | |
183 | }; | |
87298967 NS |
184 | static const enum m68k_register mcf51_ctrl[] = { |
185 | VBR, CPUCR, | |
f75192f2 KH |
186 | 0 |
187 | }; | |
78336706 NS |
188 | static const enum m68k_register mcf5206_ctrl[] = { |
189 | CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, | |
252b5132 RH |
190 | 0 |
191 | }; | |
2da12c60 | 192 | static const enum m68k_register mcf5208_ctrl[] = { |
78336706 | 193 | CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, |
266abb8f NS |
194 | 0 |
195 | }; | |
96e0bbcc | 196 | static const enum m68k_register mcf5210a_ctrl[] = { |
78336706 | 197 | VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, |
96e0bbcc NS |
198 | 0 |
199 | }; | |
2da12c60 | 200 | static const enum m68k_register mcf5213_ctrl[] = { |
78336706 | 201 | VBR, RAMBAR, RAMBAR1, FLASHBAR, |
266abb8f NS |
202 | 0 |
203 | }; | |
2da12c60 | 204 | static const enum m68k_register mcf5216_ctrl[] = { |
78336706 | 205 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
266abb8f NS |
206 | 0 |
207 | }; | |
d5be9593 NS |
208 | static const enum m68k_register mcf52223_ctrl[] = { |
209 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, | |
210 | 0 | |
211 | }; | |
96e0bbcc | 212 | static const enum m68k_register mcf52235_ctrl[] = { |
def8fc92 | 213 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
96e0bbcc NS |
214 | 0 |
215 | }; | |
216 | static const enum m68k_register mcf5225_ctrl[] = { | |
78336706 | 217 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, |
96e0bbcc NS |
218 | 0 |
219 | }; | |
87298967 NS |
220 | static const enum m68k_register mcf52259_ctrl[] = { |
221 | VBR, FLASHBAR, RAMBAR, RAMBAR1, | |
222 | 0 | |
223 | }; | |
224 | static const enum m68k_register mcf52277_ctrl[] = { | |
225 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, | |
226 | 0 | |
227 | }; | |
2da12c60 | 228 | static const enum m68k_register mcf5235_ctrl[] = { |
78336706 | 229 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
e80e0390 NC |
230 | 0 |
231 | }; | |
2da12c60 | 232 | static const enum m68k_register mcf5249_ctrl[] = { |
78336706 | 233 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, |
3e602632 NC |
234 | 0 |
235 | }; | |
2da12c60 NS |
236 | static const enum m68k_register mcf5250_ctrl[] = { |
237 | VBR, | |
238 | 0 | |
239 | }; | |
d5be9593 | 240 | static const enum m68k_register mcf5253_ctrl[] = { |
def8fc92 | 241 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, |
d5be9593 NS |
242 | 0 |
243 | }; | |
2da12c60 | 244 | static const enum m68k_register mcf5271_ctrl[] = { |
78336706 | 245 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
246 | 0 |
247 | }; | |
248 | static const enum m68k_register mcf5272_ctrl[] = { | |
78336706 | 249 | VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, |
2da12c60 NS |
250 | 0 |
251 | }; | |
252 | static const enum m68k_register mcf5275_ctrl[] = { | |
78336706 | 253 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
254 | 0 |
255 | }; | |
256 | static const enum m68k_register mcf5282_ctrl[] = { | |
78336706 NS |
257 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
258 | 0 | |
259 | }; | |
87298967 NS |
260 | static const enum m68k_register mcf53017_ctrl[] = { |
261 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR, | |
262 | 0 | |
263 | }; | |
78336706 | 264 | static const enum m68k_register mcf5307_ctrl[] = { |
87298967 | 265 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, |
2da12c60 NS |
266 | 0 |
267 | }; | |
268 | static const enum m68k_register mcf5329_ctrl[] = { | |
78336706 | 269 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
270 | 0 |
271 | }; | |
272 | static const enum m68k_register mcf5373_ctrl[] = { | |
78336706 | 273 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
274 | 0 |
275 | }; | |
276 | static const enum m68k_register mcfv4e_ctrl[] = { | |
a8e24a56 NS |
277 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, |
278 | VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, | |
279 | MBAR, SECMBAR, | |
280 | MPCR /* Multiprocessor Control register */, | |
281 | EDRAMBAR /* Embedded DRAM Base Address Register */, | |
282 | /* Permutation control registers. */ | |
3e602632 NC |
283 | PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, |
284 | PCR3U0, PCR3L0, PCR3U1, PCR3L1, | |
a8e24a56 NS |
285 | /* Legacy names */ |
286 | TC /* ASID */, BUSCR /* MMUBAR */, | |
287 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
288 | MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, | |
78336706 | 289 | ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, |
a8e24a56 NS |
290 | 0 |
291 | }; | |
def8fc92 KH |
292 | static const enum m68k_register mcf5407_ctrl[] = { |
293 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, | |
294 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
295 | /* Legacy names */ | |
296 | TC /* ASID */, | |
297 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
298 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, | |
299 | 0 | |
300 | }; | |
9a2e615a NS |
301 | static const enum m68k_register mcf54455_ctrl[] = { |
302 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
303 | VBR, PC, RAMBAR1, MBAR, | |
304 | /* Legacy names */ | |
305 | TC /* ASID */, BUSCR /* MMUBAR */, | |
306 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
307 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, | |
308 | 0 | |
309 | }; | |
a8e24a56 NS |
310 | static const enum m68k_register mcf5475_ctrl[] = { |
311 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
312 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
313 | /* Legacy names */ | |
314 | TC /* ASID */, BUSCR /* MMUBAR */, | |
315 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
78336706 | 316 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, |
a8e24a56 NS |
317 | 0 |
318 | }; | |
319 | static const enum m68k_register mcf5485_ctrl[] = { | |
320 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
321 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
322 | /* Legacy names */ | |
323 | TC /* ASID */, BUSCR /* MMUBAR */, | |
324 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
78336706 | 325 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, |
3e602632 NC |
326 | 0 |
327 | }; | |
f7ec513b | 328 | static const enum m68k_register fido_ctrl[] = { |
d0fa1372 | 329 | SFC, DFC, USP, VBR, CAC, MBO, |
f7ec513b KH |
330 | 0 |
331 | }; | |
2da12c60 | 332 | #define cpu32_ctrl m68010_ctrl |
252b5132 RH |
333 | |
334 | static const enum m68k_register *control_regs; | |
335 | ||
36759679 | 336 | /* Internal form of a 68020 instruction. */ |
252b5132 RH |
337 | struct m68k_it |
338 | { | |
339 | const char *error; | |
36759679 | 340 | const char *args; /* List of opcode info. */ |
252b5132 RH |
341 | int numargs; |
342 | ||
36759679 | 343 | int numo; /* Number of shorts in opcode. */ |
252b5132 RH |
344 | short opcode[11]; |
345 | ||
346 | struct m68k_op operands[6]; | |
347 | ||
36759679 | 348 | int nexp; /* Number of exprs in use. */ |
252b5132 RH |
349 | struct m68k_exp exprs[4]; |
350 | ||
36759679 | 351 | int nfrag; /* Number of frags we have to produce. */ |
252b5132 RH |
352 | struct |
353 | { | |
36759679 | 354 | int fragoff; /* Where in the current opcode the frag ends. */ |
252b5132 RH |
355 | symbolS *fadd; |
356 | offsetT foff; | |
357 | int fragty; | |
358 | } | |
359 | fragb[4]; | |
360 | ||
36759679 | 361 | int nrel; /* Num of reloc strucs in use. */ |
252b5132 RH |
362 | struct |
363 | { | |
364 | int n; | |
365 | expressionS exp; | |
366 | char wid; | |
367 | char pcrel; | |
368 | /* In a pc relative address the difference between the address | |
369 | of the offset and the address that the offset is relative | |
370 | to. This depends on the addressing mode. Basically this | |
371 | is the value to put in the offset field to address the | |
372 | first byte of the offset, without regarding the special | |
373 | significance of some values (in the branch instruction, for | |
374 | example). */ | |
375 | int pcrel_fix; | |
376 | #ifdef OBJ_ELF | |
377 | /* Whether this expression needs special pic relocation, and if | |
378 | so, which. */ | |
379 | enum pic_relocation pic_reloc; | |
380 | #endif | |
381 | } | |
36759679 | 382 | reloc[5]; /* Five is enough??? */ |
252b5132 RH |
383 | }; |
384 | ||
9840d27e | 385 | #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) |
252b5132 RH |
386 | #define float_of_arch(x) ((x) & mfloat) |
387 | #define mmu_of_arch(x) ((x) & mmmu) | |
6b6e92f4 NC |
388 | #define arch_coldfire_p(x) ((x) & mcfisa_a) |
389 | #define arch_coldfire_fpu(x) ((x) & cfloat) | |
252b5132 | 390 | |
36759679 | 391 | /* Macros for determining if cpu supports a specific addressing mode. */ |
9a2e615a NS |
392 | #define HAVE_LONG_DISP(x) \ |
393 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
394 | #define HAVE_LONG_CALL(x) \ | |
395 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
396 | #define HAVE_LONG_COND(x) \ | |
397 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
398 | #define HAVE_LONG_BRANCH(x) \ | |
399 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) | |
cac27205 | 400 | #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) |
252b5132 | 401 | |
36759679 | 402 | static struct m68k_it the_ins; /* The instruction being assembled. */ |
252b5132 RH |
403 | |
404 | #define op(ex) ((ex)->exp.X_op) | |
405 | #define adds(ex) ((ex)->exp.X_add_symbol) | |
406 | #define subs(ex) ((ex)->exp.X_op_symbol) | |
407 | #define offs(ex) ((ex)->exp.X_add_number) | |
408 | ||
36759679 | 409 | /* Macros for adding things to the m68k_it struct. */ |
31302357 | 410 | #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) |
252b5132 | 411 | |
36759679 NC |
412 | /* Like addword, but goes BEFORE general operands. */ |
413 | ||
252b5132 | 414 | static void |
31302357 | 415 | insop (int w, const struct m68k_incant *opcode) |
252b5132 RH |
416 | { |
417 | int z; | |
07726851 | 418 | for (z = the_ins.numo; z > opcode->m_codenum; --z) |
8a104df9 KH |
419 | the_ins.opcode[z] = the_ins.opcode[z - 1]; |
420 | for (z = 0; z < the_ins.nrel; z++) | |
421 | the_ins.reloc[z].n += 2; | |
252b5132 RH |
422 | for (z = 0; z < the_ins.nfrag; z++) |
423 | the_ins.fragb[z].fragoff++; | |
8a104df9 | 424 | the_ins.opcode[opcode->m_codenum] = w; |
252b5132 RH |
425 | the_ins.numo++; |
426 | } | |
427 | ||
428 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. | |
429 | Blecch. */ | |
430 | static void | |
31302357 | 431 | add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) |
252b5132 | 432 | { |
31302357 AS |
433 | the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' |
434 | ? the_ins.numo * 2 - 1 | |
435 | : (width == 'b' | |
436 | ? the_ins.numo * 2 + 1 | |
437 | : the_ins.numo * 2)); | |
252b5132 RH |
438 | the_ins.reloc[the_ins.nrel].exp = exp->exp; |
439 | the_ins.reloc[the_ins.nrel].wid = width; | |
440 | the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; | |
441 | #ifdef OBJ_ELF | |
442 | the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; | |
443 | #endif | |
444 | the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; | |
445 | } | |
446 | ||
447 | /* Cause an extra frag to be generated here, inserting up to 10 bytes | |
448 | (that value is chosen in the frag_var call in md_assemble). TYPE | |
449 | is the subtype of the frag to be generated; its primary type is | |
450 | rs_machine_dependent. | |
451 | ||
452 | The TYPE parameter is also used by md_convert_frag_1 and | |
453 | md_estimate_size_before_relax. The appropriate type of fixup will | |
454 | be emitted by md_convert_frag_1. | |
455 | ||
456 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
457 | static void | |
31302357 | 458 | add_frag (symbolS *add, offsetT off, int type) |
252b5132 | 459 | { |
8a104df9 KH |
460 | the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; |
461 | the_ins.fragb[the_ins.nfrag].fadd = add; | |
462 | the_ins.fragb[the_ins.nfrag].foff = off; | |
463 | the_ins.fragb[the_ins.nfrag++].fragty = type; | |
252b5132 RH |
464 | } |
465 | ||
466 | #define isvar(ex) \ | |
467 | (op (ex) != O_constant && op (ex) != O_big) | |
468 | ||
31302357 AS |
469 | static char *crack_operand (char *str, struct m68k_op *opP); |
470 | static int get_num (struct m68k_exp *exp, int ok); | |
471 | static int reverse_16_bits (int in); | |
472 | static int reverse_8_bits (int in); | |
473 | static void install_gen_operand (int mode, int val); | |
474 | static void install_operand (int mode, int val); | |
475 | static void s_bss (int); | |
476 | static void s_data1 (int); | |
477 | static void s_data2 (int); | |
478 | static void s_even (int); | |
479 | static void s_proc (int); | |
480 | static void s_chip (int); | |
481 | static void s_fopt (int); | |
482 | static void s_opt (int); | |
483 | static void s_reg (int); | |
484 | static void s_restore (int); | |
485 | static void s_save (int); | |
486 | static void s_mri_if (int); | |
487 | static void s_mri_else (int); | |
488 | static void s_mri_endi (int); | |
489 | static void s_mri_break (int); | |
490 | static void s_mri_next (int); | |
491 | static void s_mri_for (int); | |
492 | static void s_mri_endf (int); | |
493 | static void s_mri_repeat (int); | |
494 | static void s_mri_until (int); | |
495 | static void s_mri_while (int); | |
496 | static void s_mri_endw (int); | |
266abb8f NS |
497 | static void s_m68k_cpu (int); |
498 | static void s_m68k_arch (int); | |
499 | ||
500 | struct m68k_cpu | |
501 | { | |
502 | unsigned long arch; /* Architecture features. */ | |
2da12c60 | 503 | const enum m68k_register *control_regs; /* Control regs on chip */ |
266abb8f | 504 | const char *name; /* Name */ |
0b2e31dc NS |
505 | int alias; /* Alias for a cannonical name. If 1, then |
506 | succeeds canonical name, if -1 then | |
507 | succeeds canonical name, if <-1 ||>1 this is a | |
508 | deprecated name, and the next/previous name | |
509 | should be used. */ | |
266abb8f | 510 | }; |
252b5132 | 511 | |
266abb8f NS |
512 | /* We hold flags for features explicitly enabled and explicitly |
513 | disabled. */ | |
252b5132 | 514 | static int current_architecture; |
266abb8f | 515 | static int not_current_architecture; |
266abb8f NS |
516 | static const struct m68k_cpu *selected_arch; |
517 | static const struct m68k_cpu *selected_cpu; | |
518 | static int initialized; | |
252b5132 | 519 | |
266abb8f NS |
520 | /* Architecture models. */ |
521 | static const struct m68k_cpu m68k_archs[] = | |
522 | { | |
2da12c60 NS |
523 | {m68000, m68000_ctrl, "68000", 0}, |
524 | {m68010, m68010_ctrl, "68010", 0}, | |
525 | {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, | |
526 | {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, | |
527 | {m68040, m68040_ctrl, "68040", 0}, | |
528 | {m68060, m68060_ctrl, "68060", 0}, | |
529 | {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, | |
3bdcfdf4 | 530 | {fido_a, fido_ctrl, "fidoa", 0}, |
2da12c60 NS |
531 | {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, |
532 | {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, | |
533 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, | |
9a2e615a | 534 | {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, |
2da12c60 NS |
535 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, |
536 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, | |
266abb8f NS |
537 | {0,0,NULL, 0} |
538 | }; | |
252b5132 | 539 | |
87298967 NS |
540 | /* For -mno-mac we want to turn off all types of mac. */ |
541 | static const unsigned no_mac = mcfmac | mcfemac; | |
542 | ||
0b2e31dc NS |
543 | /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 |
544 | for either. */ | |
266abb8f NS |
545 | static const struct m68k_cpu m68k_extensions[] = |
546 | { | |
2da12c60 NS |
547 | {m68851, NULL, "68851", -1}, |
548 | {m68881, NULL, "68881", -1}, | |
549 | {m68881, NULL, "68882", -1}, | |
cf869cce | 550 | |
2da12c60 | 551 | {cfloat|m68881, NULL, "float", 0}, |
cf869cce | 552 | |
2da12c60 NS |
553 | {mcfhwdiv, NULL, "div", 1}, |
554 | {mcfusp, NULL, "usp", 1}, | |
87298967 | 555 | {mcfmac, (void *)&no_mac, "mac", 1}, |
2da12c60 | 556 | {mcfemac, NULL, "emac", 1}, |
cf869cce | 557 | |
2da12c60 | 558 | {0,NULL,NULL, 0} |
266abb8f NS |
559 | }; |
560 | ||
561 | /* Processor list */ | |
562 | static const struct m68k_cpu m68k_cpus[] = | |
563 | { | |
2da12c60 NS |
564 | {m68000, m68000_ctrl, "68000", 0}, |
565 | {m68000, m68000_ctrl, "68ec000", 1}, | |
566 | {m68000, m68000_ctrl, "68hc000", 1}, | |
567 | {m68000, m68000_ctrl, "68hc001", 1}, | |
568 | {m68000, m68000_ctrl, "68008", 1}, | |
569 | {m68000, m68000_ctrl, "68302", 1}, | |
570 | {m68000, m68000_ctrl, "68306", 1}, | |
571 | {m68000, m68000_ctrl, "68307", 1}, | |
572 | {m68000, m68000_ctrl, "68322", 1}, | |
573 | {m68000, m68000_ctrl, "68356", 1}, | |
574 | {m68010, m68010_ctrl, "68010", 0}, | |
575 | {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, | |
576 | {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, | |
577 | {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, | |
578 | {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, | |
579 | {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, | |
580 | {m68040, m68040_ctrl, "68040", 0}, | |
581 | {m68040, m68040_ctrl, "68ec040", 1}, | |
582 | {m68060, m68060_ctrl, "68060", 0}, | |
583 | {m68060, m68060_ctrl, "68ec060", 1}, | |
cf869cce | 584 | |
2da12c60 NS |
585 | {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, |
586 | {cpu32|m68881, cpu32_ctrl, "68330", 1}, | |
587 | {cpu32|m68881, cpu32_ctrl, "68331", 1}, | |
588 | {cpu32|m68881, cpu32_ctrl, "68332", 1}, | |
589 | {cpu32|m68881, cpu32_ctrl, "68333", 1}, | |
590 | {cpu32|m68881, cpu32_ctrl, "68334", 1}, | |
591 | {cpu32|m68881, cpu32_ctrl, "68336", 1}, | |
592 | {cpu32|m68881, cpu32_ctrl, "68340", 1}, | |
593 | {cpu32|m68881, cpu32_ctrl, "68341", 1}, | |
594 | {cpu32|m68881, cpu32_ctrl, "68349", 1}, | |
595 | {cpu32|m68881, cpu32_ctrl, "68360", 1}, | |
f75192f2 | 596 | |
87298967 NS |
597 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, |
598 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, | |
599 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, | |
600 | {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, | |
601 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, | |
602 | {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, | |
cf869cce | 603 | |
2da12c60 NS |
604 | {mcfisa_a, mcf_ctrl, "5200", 0}, |
605 | {mcfisa_a, mcf_ctrl, "5202", 1}, | |
606 | {mcfisa_a, mcf_ctrl, "5204", 1}, | |
78336706 | 607 | {mcfisa_a, mcf5206_ctrl, "5206", 1}, |
cf869cce | 608 | |
78336706 | 609 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, |
cf869cce | 610 | |
2da12c60 NS |
611 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, |
612 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, | |
cf869cce | 613 | |
96e0bbcc NS |
614 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, |
615 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, | |
cf869cce | 616 | |
2da12c60 NS |
617 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, |
618 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, | |
619 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, | |
cf869cce | 620 | |
2da12c60 NS |
621 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, |
622 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, | |
623 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, | |
624 | ||
d5be9593 NS |
625 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, |
626 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, | |
627 | ||
96e0bbcc NS |
628 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, |
629 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, | |
630 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, | |
631 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, | |
cf869cce | 632 | |
96e0bbcc NS |
633 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, |
634 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, | |
cf869cce | 635 | |
87298967 NS |
636 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, |
637 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, | |
638 | ||
2da12c60 NS |
639 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, |
640 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, | |
641 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, | |
642 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, | |
643 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, | |
644 | ||
645 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, | |
646 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, | |
d5be9593 | 647 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, |
87298967 NS |
648 | |
649 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, | |
650 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, | |
651 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, | |
652 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, | |
653 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, | |
654 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, | |
655 | ||
2da12c60 NS |
656 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, |
657 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, | |
658 | ||
659 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, | |
660 | ||
661 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, | |
662 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, | |
663 | ||
664 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, | |
665 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, | |
666 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, | |
667 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, | |
668 | ||
87298967 NS |
669 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, |
670 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, | |
671 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, | |
672 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, | |
673 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, | |
674 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, | |
675 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, | |
676 | ||
78336706 | 677 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, |
2da12c60 NS |
678 | |
679 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, | |
680 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, | |
681 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, | |
682 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, | |
683 | ||
684 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, | |
685 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, | |
686 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, | |
687 | ||
def8fc92 | 688 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, |
9a2e615a NS |
689 | |
690 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, | |
691 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, | |
692 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, | |
693 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, | |
694 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, | |
695 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, | |
2da12c60 | 696 | |
a8e24a56 NS |
697 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, |
698 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, | |
699 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, | |
700 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, | |
701 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, | |
702 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, | |
703 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, | |
2da12c60 | 704 | |
a8e24a56 NS |
705 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, |
706 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, | |
707 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, | |
708 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, | |
709 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, | |
710 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, | |
711 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, | |
2da12c60 | 712 | |
b3768379 | 713 | {fido_a, fido_ctrl, "fidoa", 0}, |
3bdcfdf4 | 714 | {fido_a, fido_ctrl, "fido", 1}, |
9840d27e | 715 | |
2da12c60 | 716 | {0,NULL,NULL, 0} |
dc84e067 | 717 | }; |
252b5132 | 718 | |
266abb8f NS |
719 | static const struct m68k_cpu *m68k_lookup_cpu |
720 | (const char *, const struct m68k_cpu *, int, int *); | |
721 | static int m68k_set_arch (const char *, int, int); | |
722 | static int m68k_set_cpu (const char *, int, int); | |
723 | static int m68k_set_extension (const char *, int, int); | |
724 | static void m68k_init_arch (void); | |
252b5132 | 725 | |
151337e8 NC |
726 | /* This is the assembler relaxation table for m68k. m68k is a rich CISC |
727 | architecture and we have a lot of relaxation modes. */ | |
252b5132 | 728 | |
151337e8 NC |
729 | /* Macros used in the relaxation code. */ |
730 | #define TAB(x,y) (((x) << 2) + (y)) | |
731 | #define TABTYPE(x) ((x) >> 2) | |
732 | ||
733 | /* Relaxation states. */ | |
734 | #define BYTE 0 | |
735 | #define SHORT 1 | |
736 | #define LONG 2 | |
737 | #define SZ_UNDEF 3 | |
738 | ||
739 | /* Here are all the relaxation modes we support. First we can relax ordinary | |
740 | branches. On 68020 and higher and on CPU32 all branch instructions take | |
741 | three forms, so on these CPUs all branches always remain as such. When we | |
742 | have to expand to the LONG form on a 68000, though, we substitute an | |
743 | absolute jump instead. This is a direct replacement for unconditional | |
744 | branches and a branch over a jump for conditional branches. However, if the | |
745 | user requires PIC and disables this with --pcrel, we can only relax between | |
746 | BYTE and SHORT forms, punting if that isn't enough. This gives us four | |
747 | different relaxation modes for branches: */ | |
748 | ||
36759679 NC |
749 | #define BRANCHBWL 0 /* Branch byte, word, or long. */ |
750 | #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ | |
751 | #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ | |
752 | #define BRANCHBW 3 /* Branch byte or word. */ | |
151337e8 NC |
753 | |
754 | /* We also relax coprocessor branches and DBcc's. All CPUs that support | |
755 | coprocessor branches support them in word and long forms, so we have only | |
756 | one relaxation mode for them. DBcc's are word only on all CPUs. We can | |
757 | relax them to the LONG form with a branch-around sequence. This sequence | |
758 | can use a long branch (if available) or an absolute jump (if acceptable). | |
759 | This gives us two relaxation modes. If long branches are not available and | |
760 | absolute jumps are not acceptable, we don't relax DBcc's. */ | |
761 | ||
36759679 NC |
762 | #define FBRANCH 4 /* Coprocessor branch. */ |
763 | #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ | |
764 | #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ | |
151337e8 NC |
765 | |
766 | /* That's all for instruction relaxation. However, we also relax PC-relative | |
767 | operands. Specifically, we have three operand relaxation modes. On the | |
768 | 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and | |
769 | on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the | |
770 | two. Also PC+displacement+index operands in their simple form (with a non- | |
771 | suppressed index without memory indirection) are supported on all CPUs, but | |
772 | on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher | |
773 | and on CPU32 we relax it to SHORT and LONG forms as well using the extended | |
774 | form of the PC+displacement+index operand. Finally, some absolute operands | |
775 | can be relaxed down to 16-bit PC-relative. */ | |
776 | ||
36759679 NC |
777 | #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ |
778 | #define PCINDEX 8 /* PC + displacement + index. */ | |
779 | #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ | |
252b5132 | 780 | |
cac27205 NC |
781 | /* This relaxation is required for branches where there is no long |
782 | branch and we are in pcrel mode. We generate a bne/beq pair. */ | |
783 | #define BRANCHBWPL 10 /* Branch byte, word or pair of longs | |
784 | */ | |
785 | ||
252b5132 | 786 | /* Note that calls to frag_var need to specify the maximum expansion |
cac27205 NC |
787 | needed; this is currently 12 bytes for bne/beq pair. */ |
788 | #define FRAG_VAR_SIZE 12 | |
252b5132 RH |
789 | |
790 | /* The fields are: | |
791 | How far Forward this mode will reach: | |
792 | How far Backward this mode will reach: | |
793 | How many bytes this mode will add to the size of the frag | |
794 | Which mode to go to if the offset won't fit in this one | |
d7861ad2 AM |
795 | |
796 | Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ | |
252b5132 RH |
797 | relax_typeS md_relax_table[] = |
798 | { | |
ac62c346 AM |
799 | { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, |
800 | { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, | |
801 | { 0, 0, 4, 0 }, | |
802 | { 1, 1, 0, 0 }, | |
803 | ||
804 | { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, | |
805 | { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, | |
806 | { 0, 0, 4, 0 }, | |
807 | { 1, 1, 0, 0 }, | |
808 | ||
809 | { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, | |
810 | { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, | |
811 | { 0, 0, 6, 0 }, | |
812 | { 1, 1, 0, 0 }, | |
813 | ||
814 | { 127, -128, 0, TAB (BRANCHBW, SHORT) }, | |
815 | { 0, 0, 2, 0 }, | |
816 | { 1, 1, 0, 0 }, | |
817 | { 1, 1, 0, 0 }, | |
818 | ||
36759679 | 819 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ |
ac62c346 AM |
820 | { 32767, -32768, 2, TAB (FBRANCH, LONG) }, |
821 | { 0, 0, 4, 0 }, | |
822 | { 1, 1, 0, 0 }, | |
823 | ||
36759679 | 824 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
825 | { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, |
826 | { 0, 0, 10, 0 }, | |
827 | { 1, 1, 0, 0 }, | |
828 | ||
36759679 | 829 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
830 | { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, |
831 | { 0, 0, 10, 0 }, | |
832 | { 1, 1, 0, 0 }, | |
833 | ||
36759679 | 834 | { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ |
ac62c346 AM |
835 | { 32767, -32768, 2, TAB (PCREL1632, LONG) }, |
836 | { 0, 0, 6, 0 }, | |
837 | { 1, 1, 0, 0 }, | |
838 | ||
839 | { 125, -130, 0, TAB (PCINDEX, SHORT) }, | |
840 | { 32765, -32770, 2, TAB (PCINDEX, LONG) }, | |
841 | { 0, 0, 4, 0 }, | |
842 | { 1, 1, 0, 0 }, | |
843 | ||
36759679 | 844 | { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ |
ac62c346 AM |
845 | { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, |
846 | { 0, 0, 4, 0 }, | |
847 | { 1, 1, 0, 0 }, | |
cac27205 NC |
848 | |
849 | { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, | |
850 | { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, | |
851 | { 0, 0, 10, 0 }, | |
852 | { 1, 1, 0, 0 }, | |
252b5132 RH |
853 | }; |
854 | ||
855 | /* These are the machine dependent pseudo-ops. These are included so | |
856 | the assembler can work on the output from the SUN C compiler, which | |
36759679 | 857 | generates these. */ |
252b5132 RH |
858 | |
859 | /* This table describes all the machine specific pseudo-ops the assembler | |
860 | has to support. The fields are: | |
861 | pseudo-op name without dot | |
862 | function to call to execute this pseudo-op | |
36759679 | 863 | Integer arg to pass to the function. */ |
252b5132 RH |
864 | const pseudo_typeS md_pseudo_table[] = |
865 | { | |
866 | {"data1", s_data1, 0}, | |
867 | {"data2", s_data2, 0}, | |
868 | {"bss", s_bss, 0}, | |
869 | {"even", s_even, 0}, | |
870 | {"skip", s_space, 0}, | |
871 | {"proc", s_proc, 0}, | |
872 | #if defined (TE_SUN3) || defined (OBJ_ELF) | |
873 | {"align", s_align_bytes, 0}, | |
874 | #endif | |
875 | #ifdef OBJ_ELF | |
876 | {"swbeg", s_ignore, 0}, | |
cf869cce | 877 | {"long", m68k_elf_cons, 4}, |
252b5132 RH |
878 | #endif |
879 | {"extend", float_cons, 'x'}, | |
880 | {"ldouble", float_cons, 'x'}, | |
881 | ||
266abb8f NS |
882 | {"arch", s_m68k_arch, 0}, |
883 | {"cpu", s_m68k_cpu, 0}, | |
884 | ||
252b5132 RH |
885 | /* The following pseudo-ops are supported for MRI compatibility. */ |
886 | {"chip", s_chip, 0}, | |
887 | {"comline", s_space, 1}, | |
888 | {"fopt", s_fopt, 0}, | |
889 | {"mask2", s_ignore, 0}, | |
890 | {"opt", s_opt, 0}, | |
891 | {"reg", s_reg, 0}, | |
892 | {"restore", s_restore, 0}, | |
893 | {"save", s_save, 0}, | |
894 | ||
895 | {"if", s_mri_if, 0}, | |
896 | {"if.b", s_mri_if, 'b'}, | |
897 | {"if.w", s_mri_if, 'w'}, | |
898 | {"if.l", s_mri_if, 'l'}, | |
899 | {"else", s_mri_else, 0}, | |
900 | {"else.s", s_mri_else, 's'}, | |
901 | {"else.l", s_mri_else, 'l'}, | |
902 | {"endi", s_mri_endi, 0}, | |
903 | {"break", s_mri_break, 0}, | |
904 | {"break.s", s_mri_break, 's'}, | |
905 | {"break.l", s_mri_break, 'l'}, | |
906 | {"next", s_mri_next, 0}, | |
907 | {"next.s", s_mri_next, 's'}, | |
908 | {"next.l", s_mri_next, 'l'}, | |
909 | {"for", s_mri_for, 0}, | |
910 | {"for.b", s_mri_for, 'b'}, | |
911 | {"for.w", s_mri_for, 'w'}, | |
912 | {"for.l", s_mri_for, 'l'}, | |
913 | {"endf", s_mri_endf, 0}, | |
914 | {"repeat", s_mri_repeat, 0}, | |
915 | {"until", s_mri_until, 0}, | |
916 | {"until.b", s_mri_until, 'b'}, | |
917 | {"until.w", s_mri_until, 'w'}, | |
918 | {"until.l", s_mri_until, 'l'}, | |
919 | {"while", s_mri_while, 0}, | |
920 | {"while.b", s_mri_while, 'b'}, | |
921 | {"while.w", s_mri_while, 'w'}, | |
922 | {"while.l", s_mri_while, 'l'}, | |
923 | {"endw", s_mri_endw, 0}, | |
924 | ||
925 | {0, 0, 0} | |
926 | }; | |
927 | ||
252b5132 | 928 | /* The mote pseudo ops are put into the opcode table, since they |
31302357 | 929 | don't start with a . they look like opcodes to gas. */ |
252b5132 | 930 | |
5a38dc70 | 931 | const pseudo_typeS mote_pseudo_table[] = |
252b5132 RH |
932 | { |
933 | ||
934 | {"dcl", cons, 4}, | |
935 | {"dc", cons, 2}, | |
936 | {"dcw", cons, 2}, | |
937 | {"dcb", cons, 1}, | |
938 | ||
939 | {"dsl", s_space, 4}, | |
940 | {"ds", s_space, 2}, | |
941 | {"dsw", s_space, 2}, | |
942 | {"dsb", s_space, 1}, | |
943 | ||
944 | {"xdef", s_globl, 0}, | |
945 | #ifdef OBJ_ELF | |
946 | {"align", s_align_bytes, 0}, | |
947 | #else | |
948 | {"align", s_align_ptwo, 0}, | |
949 | #endif | |
950 | #ifdef M68KCOFF | |
951 | {"sect", obj_coff_section, 0}, | |
952 | {"section", obj_coff_section, 0}, | |
953 | #endif | |
954 | {0, 0, 0} | |
955 | }; | |
956 | ||
bd17c2c3 AM |
957 | /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host |
958 | gives identical results to a 32-bit host. */ | |
959 | #define TRUNC(X) ((valueT) (X) & 0xffffffff) | |
960 | #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) | |
961 | ||
962 | #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) | |
963 | #define isubyte(x) ((valueT) TRUNC (x) < 0x100) | |
964 | #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) | |
965 | #define isuword(x) ((valueT) TRUNC (x) < 0x10000) | |
966 | ||
967 | #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) | |
968 | #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) | |
252b5132 RH |
969 | #define islong(x) (1) |
970 | ||
252b5132 RH |
971 | static char notend_table[256]; |
972 | static char alt_notend_table[256]; | |
973 | #define notend(s) \ | |
974 | (! (notend_table[(unsigned char) *s] \ | |
975 | || (*s == ':' \ | |
976 | && alt_notend_table[(unsigned char) s[1]]))) | |
977 | ||
252b5132 RH |
978 | #ifdef OBJ_ELF |
979 | ||
c801568a AM |
980 | /* Return zero if the reference to SYMBOL from within the same segment may |
981 | be relaxed. */ | |
982 | ||
983 | /* On an ELF system, we can't relax an externally visible symbol, | |
984 | because it may be overridden by a shared library. However, if | |
985 | TARGET_OS is "elf", then we presume that we are assembling for an | |
986 | embedded system, in which case we don't have to worry about shared | |
987 | libraries, and we can relax any external sym. */ | |
988 | ||
989 | #define relaxable_symbol(symbol) \ | |
6358301e | 990 | (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ |
c801568a AM |
991 | || S_IS_WEAK (symbol))) |
992 | ||
252b5132 RH |
993 | /* Compute the relocation code for a fixup of SIZE bytes, using pc |
994 | relative relocation if PCREL is non-zero. PIC says whether a special | |
995 | pic relocation was requested. */ | |
996 | ||
252b5132 | 997 | static bfd_reloc_code_real_type |
31302357 | 998 | get_reloc_code (int size, int pcrel, enum pic_relocation pic) |
252b5132 RH |
999 | { |
1000 | switch (pic) | |
1001 | { | |
1002 | case pic_got_pcrel: | |
1003 | switch (size) | |
1004 | { | |
1005 | case 1: | |
1006 | return BFD_RELOC_8_GOT_PCREL; | |
1007 | case 2: | |
1008 | return BFD_RELOC_16_GOT_PCREL; | |
1009 | case 4: | |
1010 | return BFD_RELOC_32_GOT_PCREL; | |
1011 | } | |
1012 | break; | |
1013 | ||
1014 | case pic_got_off: | |
1015 | switch (size) | |
1016 | { | |
1017 | case 1: | |
1018 | return BFD_RELOC_8_GOTOFF; | |
1019 | case 2: | |
1020 | return BFD_RELOC_16_GOTOFF; | |
1021 | case 4: | |
1022 | return BFD_RELOC_32_GOTOFF; | |
1023 | } | |
1024 | break; | |
1025 | ||
1026 | case pic_plt_pcrel: | |
1027 | switch (size) | |
1028 | { | |
1029 | case 1: | |
1030 | return BFD_RELOC_8_PLT_PCREL; | |
1031 | case 2: | |
1032 | return BFD_RELOC_16_PLT_PCREL; | |
1033 | case 4: | |
1034 | return BFD_RELOC_32_PLT_PCREL; | |
1035 | } | |
1036 | break; | |
1037 | ||
1038 | case pic_plt_off: | |
1039 | switch (size) | |
1040 | { | |
1041 | case 1: | |
1042 | return BFD_RELOC_8_PLTOFF; | |
1043 | case 2: | |
1044 | return BFD_RELOC_16_PLTOFF; | |
1045 | case 4: | |
1046 | return BFD_RELOC_32_PLTOFF; | |
1047 | } | |
1048 | break; | |
1049 | ||
cf869cce NC |
1050 | case pic_tls_gd: |
1051 | switch (size) | |
1052 | { | |
1053 | case 1: | |
1054 | return BFD_RELOC_68K_TLS_GD8; | |
1055 | case 2: | |
1056 | return BFD_RELOC_68K_TLS_GD16; | |
1057 | case 4: | |
1058 | return BFD_RELOC_68K_TLS_GD32; | |
1059 | } | |
1060 | break; | |
1061 | ||
1062 | case pic_tls_ldm: | |
1063 | switch (size) | |
1064 | { | |
1065 | case 1: | |
1066 | return BFD_RELOC_68K_TLS_LDM8; | |
1067 | case 2: | |
1068 | return BFD_RELOC_68K_TLS_LDM16; | |
1069 | case 4: | |
1070 | return BFD_RELOC_68K_TLS_LDM32; | |
1071 | } | |
1072 | break; | |
1073 | ||
1074 | case pic_tls_ldo: | |
1075 | switch (size) | |
1076 | { | |
1077 | case 1: | |
1078 | return BFD_RELOC_68K_TLS_LDO8; | |
1079 | case 2: | |
1080 | return BFD_RELOC_68K_TLS_LDO16; | |
1081 | case 4: | |
1082 | return BFD_RELOC_68K_TLS_LDO32; | |
1083 | } | |
1084 | break; | |
1085 | ||
1086 | case pic_tls_ie: | |
1087 | switch (size) | |
1088 | { | |
1089 | case 1: | |
1090 | return BFD_RELOC_68K_TLS_IE8; | |
1091 | case 2: | |
1092 | return BFD_RELOC_68K_TLS_IE16; | |
1093 | case 4: | |
1094 | return BFD_RELOC_68K_TLS_IE32; | |
1095 | } | |
1096 | break; | |
1097 | ||
1098 | case pic_tls_le: | |
1099 | switch (size) | |
1100 | { | |
1101 | case 1: | |
1102 | return BFD_RELOC_68K_TLS_LE8; | |
1103 | case 2: | |
1104 | return BFD_RELOC_68K_TLS_LE16; | |
1105 | case 4: | |
1106 | return BFD_RELOC_68K_TLS_LE32; | |
1107 | } | |
1108 | break; | |
1109 | ||
252b5132 RH |
1110 | case pic_none: |
1111 | if (pcrel) | |
1112 | { | |
1113 | switch (size) | |
1114 | { | |
1115 | case 1: | |
1116 | return BFD_RELOC_8_PCREL; | |
1117 | case 2: | |
1118 | return BFD_RELOC_16_PCREL; | |
1119 | case 4: | |
1120 | return BFD_RELOC_32_PCREL; | |
1121 | } | |
1122 | } | |
1123 | else | |
1124 | { | |
1125 | switch (size) | |
1126 | { | |
1127 | case 1: | |
1128 | return BFD_RELOC_8; | |
1129 | case 2: | |
1130 | return BFD_RELOC_16; | |
1131 | case 4: | |
1132 | return BFD_RELOC_32; | |
1133 | } | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | if (pcrel) | |
1138 | { | |
1139 | if (pic == pic_none) | |
1140 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
1141 | else | |
1142 | as_bad (_("Can not do %d byte pc-relative pic relocation"), size); | |
1143 | } | |
1144 | else | |
1145 | { | |
1146 | if (pic == pic_none) | |
1147 | as_bad (_("Can not do %d byte relocation"), size); | |
1148 | else | |
1149 | as_bad (_("Can not do %d byte pic relocation"), size); | |
1150 | } | |
1151 | ||
1152 | return BFD_RELOC_NONE; | |
1153 | } | |
1154 | ||
1155 | /* Here we decide which fixups can be adjusted to make them relative | |
1156 | to the beginning of the section instead of the symbol. Basically | |
1157 | we need to make sure that the dynamic relocations are done | |
1158 | correctly, so in some cases we force the original symbol to be | |
1159 | used. */ | |
1160 | int | |
31302357 | 1161 | tc_m68k_fix_adjustable (fixS *fixP) |
252b5132 | 1162 | { |
36759679 | 1163 | /* Adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1164 | switch (fixP->fx_r_type) |
1165 | { | |
1166 | case BFD_RELOC_8_GOT_PCREL: | |
1167 | case BFD_RELOC_16_GOT_PCREL: | |
1168 | case BFD_RELOC_32_GOT_PCREL: | |
1169 | case BFD_RELOC_8_GOTOFF: | |
1170 | case BFD_RELOC_16_GOTOFF: | |
1171 | case BFD_RELOC_32_GOTOFF: | |
1172 | case BFD_RELOC_8_PLT_PCREL: | |
1173 | case BFD_RELOC_16_PLT_PCREL: | |
1174 | case BFD_RELOC_32_PLT_PCREL: | |
1175 | case BFD_RELOC_8_PLTOFF: | |
1176 | case BFD_RELOC_16_PLTOFF: | |
1177 | case BFD_RELOC_32_PLTOFF: | |
cf869cce NC |
1178 | case BFD_RELOC_68K_TLS_GD32: |
1179 | case BFD_RELOC_68K_TLS_GD16: | |
1180 | case BFD_RELOC_68K_TLS_GD8: | |
1181 | case BFD_RELOC_68K_TLS_LDM32: | |
1182 | case BFD_RELOC_68K_TLS_LDM16: | |
1183 | case BFD_RELOC_68K_TLS_LDM8: | |
1184 | case BFD_RELOC_68K_TLS_LDO32: | |
1185 | case BFD_RELOC_68K_TLS_LDO16: | |
1186 | case BFD_RELOC_68K_TLS_LDO8: | |
1187 | case BFD_RELOC_68K_TLS_IE32: | |
1188 | case BFD_RELOC_68K_TLS_IE16: | |
1189 | case BFD_RELOC_68K_TLS_IE8: | |
1190 | case BFD_RELOC_68K_TLS_LE32: | |
1191 | case BFD_RELOC_68K_TLS_LE16: | |
1192 | case BFD_RELOC_68K_TLS_LE8: | |
252b5132 RH |
1193 | return 0; |
1194 | ||
1195 | case BFD_RELOC_VTABLE_INHERIT: | |
1196 | case BFD_RELOC_VTABLE_ENTRY: | |
1197 | return 0; | |
1198 | ||
1199 | default: | |
1200 | return 1; | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | #else /* !OBJ_ELF */ | |
1205 | ||
1206 | #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC | |
1207 | ||
22184a77 NC |
1208 | /* PR gas/3041 Weak symbols are not relaxable |
1209 | because they must be treated as extern. */ | |
1210 | #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol))) | |
c801568a | 1211 | |
252b5132 RH |
1212 | #endif /* OBJ_ELF */ |
1213 | ||
252b5132 | 1214 | arelent * |
31302357 | 1215 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
1216 | { |
1217 | arelent *reloc; | |
1218 | bfd_reloc_code_real_type code; | |
1219 | ||
8ec6253e NC |
1220 | /* If the tcbit is set, then this was a fixup of a negative value |
1221 | that was never resolved. We do not have a reloc to handle this, | |
1222 | so just return. We assume that other code will have detected this | |
1223 | situation and produced a helpful error message, so we just tell the | |
1224 | user that the reloc cannot be produced. */ | |
252b5132 | 1225 | if (fixp->fx_tcbit) |
8ec6253e NC |
1226 | { |
1227 | if (fixp->fx_addsy) | |
b091f402 AM |
1228 | as_bad_where (fixp->fx_file, fixp->fx_line, |
1229 | _("Unable to produce reloc against symbol '%s'"), | |
1230 | S_GET_NAME (fixp->fx_addsy)); | |
8ec6253e NC |
1231 | return NULL; |
1232 | } | |
252b5132 RH |
1233 | |
1234 | if (fixp->fx_r_type != BFD_RELOC_NONE) | |
1235 | { | |
1236 | code = fixp->fx_r_type; | |
1237 | ||
1238 | /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible | |
1239 | that fixup_segment converted a non-PC relative reloc into a | |
1240 | PC relative reloc. In such a case, we need to convert the | |
1241 | reloc code. */ | |
1242 | if (fixp->fx_pcrel) | |
1243 | { | |
1244 | switch (code) | |
1245 | { | |
1246 | case BFD_RELOC_8: | |
1247 | code = BFD_RELOC_8_PCREL; | |
1248 | break; | |
1249 | case BFD_RELOC_16: | |
1250 | code = BFD_RELOC_16_PCREL; | |
1251 | break; | |
1252 | case BFD_RELOC_32: | |
1253 | code = BFD_RELOC_32_PCREL; | |
1254 | break; | |
1255 | case BFD_RELOC_8_PCREL: | |
1256 | case BFD_RELOC_16_PCREL: | |
1257 | case BFD_RELOC_32_PCREL: | |
1258 | case BFD_RELOC_8_GOT_PCREL: | |
1259 | case BFD_RELOC_16_GOT_PCREL: | |
1260 | case BFD_RELOC_32_GOT_PCREL: | |
1261 | case BFD_RELOC_8_GOTOFF: | |
1262 | case BFD_RELOC_16_GOTOFF: | |
1263 | case BFD_RELOC_32_GOTOFF: | |
1264 | case BFD_RELOC_8_PLT_PCREL: | |
1265 | case BFD_RELOC_16_PLT_PCREL: | |
1266 | case BFD_RELOC_32_PLT_PCREL: | |
1267 | case BFD_RELOC_8_PLTOFF: | |
1268 | case BFD_RELOC_16_PLTOFF: | |
1269 | case BFD_RELOC_32_PLTOFF: | |
cf869cce NC |
1270 | case BFD_RELOC_68K_TLS_GD32: |
1271 | case BFD_RELOC_68K_TLS_GD16: | |
1272 | case BFD_RELOC_68K_TLS_GD8: | |
1273 | case BFD_RELOC_68K_TLS_LDM32: | |
1274 | case BFD_RELOC_68K_TLS_LDM16: | |
1275 | case BFD_RELOC_68K_TLS_LDM8: | |
1276 | case BFD_RELOC_68K_TLS_LDO32: | |
1277 | case BFD_RELOC_68K_TLS_LDO16: | |
1278 | case BFD_RELOC_68K_TLS_LDO8: | |
1279 | case BFD_RELOC_68K_TLS_IE32: | |
1280 | case BFD_RELOC_68K_TLS_IE16: | |
1281 | case BFD_RELOC_68K_TLS_IE8: | |
1282 | case BFD_RELOC_68K_TLS_LE32: | |
1283 | case BFD_RELOC_68K_TLS_LE16: | |
1284 | case BFD_RELOC_68K_TLS_LE8: | |
252b5132 RH |
1285 | break; |
1286 | default: | |
1287 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1288 | _("Cannot make %s relocation PC relative"), | |
1289 | bfd_get_reloc_code_name (code)); | |
1290 | } | |
1291 | } | |
1292 | } | |
1293 | else | |
1294 | { | |
1295 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) | |
1296 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
1297 | { | |
1298 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
1299 | MAP (1, 0, BFD_RELOC_8); | |
1300 | MAP (2, 0, BFD_RELOC_16); | |
1301 | MAP (4, 0, BFD_RELOC_32); | |
1302 | MAP (1, 1, BFD_RELOC_8_PCREL); | |
1303 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
1304 | MAP (4, 1, BFD_RELOC_32_PCREL); | |
1305 | default: | |
1306 | abort (); | |
1307 | } | |
1308 | } | |
1309 | #undef F | |
1310 | #undef MAP | |
1311 | ||
1312 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
1313 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1314 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1315 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1316 | #ifndef OBJ_ELF | |
1317 | if (fixp->fx_pcrel) | |
1318 | reloc->addend = fixp->fx_addnumber; | |
22184a77 NC |
1319 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
1320 | && fixp->fx_addsy | |
1321 | && S_IS_WEAK (fixp->fx_addsy) | |
1322 | && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy))) | |
1323 | /* PR gas/3041 Adjust addend in order to force bfd_install_relocation() | |
1c3f20b4 NC |
1324 | to put the symbol offset into frags referencing a weak symbol. */ |
1325 | reloc->addend = fixp->fx_addnumber | |
1326 | - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
252b5132 RH |
1327 | else |
1328 | reloc->addend = 0; | |
1329 | #else | |
1330 | if (!fixp->fx_pcrel) | |
1331 | reloc->addend = fixp->fx_addnumber; | |
1332 | else | |
1333 | reloc->addend = (section->vma | |
8390138c AS |
1334 | /* Explicit sign extension in case char is |
1335 | unsigned. */ | |
1336 | + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80 | |
252b5132 RH |
1337 | + fixp->fx_addnumber |
1338 | + md_pcrel_from (fixp)); | |
1339 | #endif | |
1340 | ||
1341 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
9c2799c2 | 1342 | gas_assert (reloc->howto != 0); |
252b5132 RH |
1343 | |
1344 | return reloc; | |
1345 | } | |
1346 | ||
252b5132 RH |
1347 | /* Handle of the OPCODE hash table. NULL means any use before |
1348 | m68k_ip_begin() will crash. */ | |
1349 | static struct hash_control *op_hash; | |
1350 | \f | |
1351 | /* Assemble an m68k instruction. */ | |
1352 | ||
1353 | static void | |
31302357 | 1354 | m68k_ip (char *instring) |
252b5132 RH |
1355 | { |
1356 | register char *p; | |
1357 | register struct m68k_op *opP; | |
1358 | register const struct m68k_incant *opcode; | |
1359 | register const char *s; | |
1360 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
1361 | char *pdot, *pdotmove; | |
1362 | enum m68k_size siz1, siz2; | |
1363 | char c; | |
1364 | int losing; | |
1365 | int opsfound; | |
03b13e59 | 1366 | struct m68k_op operands_backup[6]; |
252b5132 RH |
1367 | LITTLENUM_TYPE words[6]; |
1368 | LITTLENUM_TYPE *wordp; | |
1369 | unsigned long ok_arch = 0; | |
1370 | ||
1371 | if (*instring == ' ') | |
36759679 | 1372 | instring++; /* Skip leading whitespace. */ |
252b5132 RH |
1373 | |
1374 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
92774660 | 1375 | or exactly 1 space. */ |
252b5132 RH |
1376 | pdot = 0; |
1377 | for (p = instring; *p != '\0'; p++) | |
1378 | { | |
1379 | if (*p == ' ') | |
1380 | break; | |
1381 | if (*p == '.') | |
1382 | pdot = p; | |
1383 | } | |
1384 | ||
1385 | if (p == instring) | |
1386 | { | |
1387 | the_ins.error = _("No operator"); | |
1388 | return; | |
1389 | } | |
1390 | ||
1391 | /* p now points to the end of the opcode name, probably whitespace. | |
1392 | Make sure the name is null terminated by clobbering the | |
1393 | whitespace, look it up in the hash table, then fix it back. | |
1394 | Remove a dot, first, since the opcode tables have none. */ | |
1395 | if (pdot != NULL) | |
1396 | { | |
1397 | for (pdotmove = pdot; pdotmove < p; pdotmove++) | |
1398 | *pdotmove = pdotmove[1]; | |
1399 | p--; | |
1400 | } | |
1401 | ||
1402 | c = *p; | |
1403 | *p = '\0'; | |
1404 | opcode = (const struct m68k_incant *) hash_find (op_hash, instring); | |
1405 | *p = c; | |
1406 | ||
1407 | if (pdot != NULL) | |
1408 | { | |
1409 | for (pdotmove = p; pdotmove > pdot; pdotmove--) | |
1410 | *pdotmove = pdotmove[-1]; | |
1411 | *pdot = '.'; | |
1412 | ++p; | |
1413 | } | |
1414 | ||
1415 | if (opcode == NULL) | |
1416 | { | |
1417 | the_ins.error = _("Unknown operator"); | |
1418 | return; | |
1419 | } | |
1420 | ||
36759679 | 1421 | /* Found a legitimate opcode, start matching operands. */ |
252b5132 RH |
1422 | while (*p == ' ') |
1423 | ++p; | |
1424 | ||
1425 | if (opcode->m_operands == 0) | |
1426 | { | |
1427 | char *old = input_line_pointer; | |
1428 | *old = '\n'; | |
1429 | input_line_pointer = p; | |
36759679 | 1430 | /* Ahh - it's a motorola style psuedo op. */ |
252b5132 RH |
1431 | mote_pseudo_table[opcode->m_opnum].poc_handler |
1432 | (mote_pseudo_table[opcode->m_opnum].poc_val); | |
1433 | input_line_pointer = old; | |
1434 | *old = 0; | |
1435 | ||
1436 | return; | |
1437 | } | |
1438 | ||
1439 | if (flag_mri && opcode->m_opnum == 0) | |
1440 | { | |
1441 | /* In MRI mode, random garbage is allowed after an instruction | |
1442 | which accepts no operands. */ | |
1443 | the_ins.args = opcode->m_operands; | |
1444 | the_ins.numargs = opcode->m_opnum; | |
1445 | the_ins.numo = opcode->m_codenum; | |
1446 | the_ins.opcode[0] = getone (opcode); | |
1447 | the_ins.opcode[1] = gettwo (opcode); | |
1448 | return; | |
1449 | } | |
1450 | ||
1451 | for (opP = &the_ins.operands[0]; *p; opP++) | |
1452 | { | |
1453 | p = crack_operand (p, opP); | |
1454 | ||
1455 | if (opP->error) | |
1456 | { | |
1457 | the_ins.error = opP->error; | |
1458 | return; | |
1459 | } | |
1460 | } | |
1461 | ||
1462 | opsfound = opP - &the_ins.operands[0]; | |
1463 | ||
1464 | /* This ugly hack is to support the floating pt opcodes in their | |
1465 | standard form. Essentially, we fake a first enty of type COP#1 */ | |
1466 | if (opcode->m_operands[0] == 'I') | |
1467 | { | |
1468 | int n; | |
1469 | ||
1470 | for (n = opsfound; n > 0; --n) | |
1471 | the_ins.operands[n] = the_ins.operands[n - 1]; | |
1472 | ||
31302357 | 1473 | memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); |
252b5132 RH |
1474 | the_ins.operands[0].mode = CONTROL; |
1475 | the_ins.operands[0].reg = m68k_float_copnum; | |
1476 | opsfound++; | |
1477 | } | |
1478 | ||
36759679 | 1479 | /* We've got the operands. Find an opcode that'll accept them. */ |
252b5132 RH |
1480 | for (losing = 0;;) |
1481 | { | |
1482 | /* If we didn't get the right number of ops, or we have no | |
92774660 | 1483 | common model with this pattern then reject this pattern. */ |
252b5132 RH |
1484 | |
1485 | ok_arch |= opcode->m_arch; | |
1486 | if (opsfound != opcode->m_opnum | |
1487 | || ((opcode->m_arch & current_architecture) == 0)) | |
1488 | ++losing; | |
1489 | else | |
1490 | { | |
03b13e59 NC |
1491 | int i; |
1492 | ||
1493 | /* Make a copy of the operands of this insn so that | |
1494 | we can modify them safely, should we want to. */ | |
9c2799c2 | 1495 | gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); |
03b13e59 NC |
1496 | for (i = 0; i < opsfound; i++) |
1497 | operands_backup[i] = the_ins.operands[i]; | |
1498 | ||
1499 | for (s = opcode->m_operands, opP = &operands_backup[0]; | |
252b5132 RH |
1500 | *s && !losing; |
1501 | s += 2, opP++) | |
1502 | { | |
1503 | /* Warning: this switch is huge! */ | |
1504 | /* I've tried to organize the cases into this order: | |
1505 | non-alpha first, then alpha by letter. Lower-case | |
1506 | goes directly before uppercase counterpart. */ | |
1507 | /* Code with multiple case ...: gets sorted by the lowest | |
1508 | case ... it belongs to. I hope this makes sense. */ | |
1509 | switch (*s) | |
1510 | { | |
1511 | case '!': | |
1512 | switch (opP->mode) | |
1513 | { | |
1514 | case IMMED: | |
1515 | case DREG: | |
1516 | case AREG: | |
1517 | case FPREG: | |
1518 | case CONTROL: | |
1519 | case AINC: | |
1520 | case ADEC: | |
1521 | case REGLST: | |
1522 | losing++; | |
1523 | break; | |
1524 | default: | |
1525 | break; | |
1526 | } | |
1527 | break; | |
1528 | ||
1529 | case '<': | |
1530 | switch (opP->mode) | |
1531 | { | |
1532 | case DREG: | |
1533 | case AREG: | |
1534 | case FPREG: | |
1535 | case CONTROL: | |
1536 | case IMMED: | |
1537 | case ADEC: | |
1538 | case REGLST: | |
1539 | losing++; | |
1540 | break; | |
1541 | default: | |
1542 | break; | |
1543 | } | |
1544 | break; | |
1545 | ||
1546 | case '>': | |
1547 | switch (opP->mode) | |
1548 | { | |
1549 | case DREG: | |
1550 | case AREG: | |
1551 | case FPREG: | |
1552 | case CONTROL: | |
1553 | case IMMED: | |
1554 | case AINC: | |
1555 | case REGLST: | |
1556 | losing++; | |
1557 | break; | |
1558 | case ABSL: | |
1559 | break; | |
1560 | default: | |
1561 | if (opP->reg == PC | |
1562 | || opP->reg == ZPC) | |
1563 | losing++; | |
1564 | break; | |
1565 | } | |
1566 | break; | |
1567 | ||
1568 | case 'm': | |
1569 | switch (opP->mode) | |
1570 | { | |
1571 | case DREG: | |
1572 | case AREG: | |
1573 | case AINDR: | |
1574 | case AINC: | |
1575 | case ADEC: | |
1576 | break; | |
1577 | default: | |
1578 | losing++; | |
1579 | } | |
8a104df9 | 1580 | break; |
252b5132 RH |
1581 | |
1582 | case 'n': | |
1583 | switch (opP->mode) | |
1584 | { | |
1585 | case DISP: | |
1586 | break; | |
1587 | default: | |
1588 | losing++; | |
1589 | } | |
8a104df9 | 1590 | break; |
252b5132 RH |
1591 | |
1592 | case 'o': | |
1593 | switch (opP->mode) | |
1594 | { | |
1595 | case BASE: | |
1596 | case ABSL: | |
1597 | case IMMED: | |
1598 | break; | |
1599 | default: | |
1600 | losing++; | |
1601 | } | |
8a104df9 | 1602 | break; |
252b5132 RH |
1603 | |
1604 | case 'p': | |
1605 | switch (opP->mode) | |
1606 | { | |
1607 | case DREG: | |
1608 | case AREG: | |
1609 | case AINDR: | |
1610 | case AINC: | |
1611 | case ADEC: | |
1612 | break; | |
1613 | case DISP: | |
1614 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1615 | losing++; |
252b5132 RH |
1616 | break; |
1617 | default: | |
1618 | losing++; | |
1619 | } | |
8a104df9 | 1620 | break; |
252b5132 RH |
1621 | |
1622 | case 'q': | |
1623 | switch (opP->mode) | |
1624 | { | |
1625 | case DREG: | |
1626 | case AINDR: | |
1627 | case AINC: | |
1628 | case ADEC: | |
1629 | break; | |
1630 | case DISP: | |
1631 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1632 | losing++; |
252b5132 RH |
1633 | break; |
1634 | default: | |
1635 | losing++; | |
1636 | break; | |
1637 | } | |
8a104df9 | 1638 | break; |
252b5132 RH |
1639 | |
1640 | case 'v': | |
1641 | switch (opP->mode) | |
1642 | { | |
1643 | case DREG: | |
1644 | case AINDR: | |
1645 | case AINC: | |
1646 | case ADEC: | |
1647 | case ABSL: | |
1648 | break; | |
1649 | case DISP: | |
1650 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1651 | losing++; |
252b5132 RH |
1652 | break; |
1653 | default: | |
1654 | losing++; | |
1655 | break; | |
1656 | } | |
1657 | break; | |
1658 | ||
1659 | case '#': | |
1660 | if (opP->mode != IMMED) | |
1661 | losing++; | |
1662 | else if (s[1] == 'b' | |
1663 | && ! isvar (&opP->disp) | |
1664 | && (opP->disp.exp.X_op != O_constant | |
1665 | || ! isbyte (opP->disp.exp.X_add_number))) | |
1666 | losing++; | |
1667 | else if (s[1] == 'B' | |
1668 | && ! isvar (&opP->disp) | |
1669 | && (opP->disp.exp.X_op != O_constant | |
1670 | || ! issbyte (opP->disp.exp.X_add_number))) | |
1671 | losing++; | |
1672 | else if (s[1] == 'w' | |
1673 | && ! isvar (&opP->disp) | |
1674 | && (opP->disp.exp.X_op != O_constant | |
1675 | || ! isword (opP->disp.exp.X_add_number))) | |
1676 | losing++; | |
1677 | else if (s[1] == 'W' | |
1678 | && ! isvar (&opP->disp) | |
1679 | && (opP->disp.exp.X_op != O_constant | |
1680 | || ! issword (opP->disp.exp.X_add_number))) | |
1681 | losing++; | |
1682 | break; | |
1683 | ||
1684 | case '^': | |
1685 | case 'T': | |
1686 | if (opP->mode != IMMED) | |
1687 | losing++; | |
1688 | break; | |
1689 | ||
1690 | case '$': | |
1691 | if (opP->mode == AREG | |
1692 | || opP->mode == CONTROL | |
1693 | || opP->mode == FPREG | |
1694 | || opP->mode == IMMED | |
1695 | || opP->mode == REGLST | |
1696 | || (opP->mode != ABSL | |
1697 | && (opP->reg == PC | |
1698 | || opP->reg == ZPC))) | |
1699 | losing++; | |
1700 | break; | |
1701 | ||
1702 | case '%': | |
1703 | if (opP->mode == CONTROL | |
1704 | || opP->mode == FPREG | |
1705 | || opP->mode == REGLST | |
1706 | || opP->mode == IMMED | |
1707 | || (opP->mode != ABSL | |
1708 | && (opP->reg == PC | |
1709 | || opP->reg == ZPC))) | |
1710 | losing++; | |
1711 | break; | |
1712 | ||
1713 | case '&': | |
1714 | switch (opP->mode) | |
1715 | { | |
1716 | case DREG: | |
1717 | case AREG: | |
1718 | case FPREG: | |
1719 | case CONTROL: | |
1720 | case IMMED: | |
1721 | case AINC: | |
1722 | case ADEC: | |
1723 | case REGLST: | |
1724 | losing++; | |
1725 | break; | |
1726 | case ABSL: | |
1727 | break; | |
1728 | default: | |
1729 | if (opP->reg == PC | |
1730 | || opP->reg == ZPC) | |
1731 | losing++; | |
1732 | break; | |
1733 | } | |
1734 | break; | |
1735 | ||
1736 | case '*': | |
1737 | if (opP->mode == CONTROL | |
1738 | || opP->mode == FPREG | |
1739 | || opP->mode == REGLST) | |
1740 | losing++; | |
1741 | break; | |
1742 | ||
1743 | case '+': | |
1744 | if (opP->mode != AINC) | |
1745 | losing++; | |
1746 | break; | |
1747 | ||
1748 | case '-': | |
1749 | if (opP->mode != ADEC) | |
1750 | losing++; | |
1751 | break; | |
1752 | ||
1753 | case '/': | |
1754 | switch (opP->mode) | |
1755 | { | |
1756 | case AREG: | |
1757 | case CONTROL: | |
1758 | case FPREG: | |
1759 | case AINC: | |
1760 | case ADEC: | |
1761 | case IMMED: | |
1762 | case REGLST: | |
1763 | losing++; | |
1764 | break; | |
1765 | default: | |
1766 | break; | |
1767 | } | |
1768 | break; | |
1769 | ||
1770 | case ';': | |
1771 | switch (opP->mode) | |
1772 | { | |
1773 | case AREG: | |
1774 | case CONTROL: | |
1775 | case FPREG: | |
1776 | case REGLST: | |
1777 | losing++; | |
1778 | break; | |
1779 | default: | |
1780 | break; | |
1781 | } | |
1782 | break; | |
1783 | ||
1784 | case '?': | |
1785 | switch (opP->mode) | |
1786 | { | |
1787 | case AREG: | |
1788 | case CONTROL: | |
1789 | case FPREG: | |
1790 | case AINC: | |
1791 | case ADEC: | |
1792 | case IMMED: | |
1793 | case REGLST: | |
1794 | losing++; | |
1795 | break; | |
1796 | case ABSL: | |
1797 | break; | |
1798 | default: | |
1799 | if (opP->reg == PC || opP->reg == ZPC) | |
1800 | losing++; | |
1801 | break; | |
1802 | } | |
1803 | break; | |
1804 | ||
1805 | case '@': | |
1806 | switch (opP->mode) | |
1807 | { | |
1808 | case AREG: | |
1809 | case CONTROL: | |
1810 | case FPREG: | |
1811 | case IMMED: | |
1812 | case REGLST: | |
1813 | losing++; | |
1814 | break; | |
1815 | default: | |
1816 | break; | |
1817 | } | |
1818 | break; | |
1819 | ||
1820 | case '~': /* For now! (JF FOO is this right?) */ | |
1821 | switch (opP->mode) | |
1822 | { | |
1823 | case DREG: | |
1824 | case AREG: | |
1825 | case CONTROL: | |
1826 | case FPREG: | |
1827 | case IMMED: | |
1828 | case REGLST: | |
1829 | losing++; | |
1830 | break; | |
1831 | case ABSL: | |
1832 | break; | |
1833 | default: | |
1834 | if (opP->reg == PC | |
1835 | || opP->reg == ZPC) | |
1836 | losing++; | |
1837 | break; | |
1838 | } | |
1839 | break; | |
1840 | ||
1841 | case '3': | |
1842 | if (opP->mode != CONTROL | |
1843 | || (opP->reg != TT0 && opP->reg != TT1)) | |
1844 | losing++; | |
1845 | break; | |
1846 | ||
1847 | case 'A': | |
1848 | if (opP->mode != AREG) | |
1849 | losing++; | |
1850 | break; | |
1851 | ||
1852 | case 'a': | |
1853 | if (opP->mode != AINDR) | |
1854 | ++losing; | |
1855 | break; | |
1856 | ||
fd99574b NC |
1857 | case '4': |
1858 | if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC | |
1859 | && (opP->mode != DISP | |
1860 | || opP->reg < ADDR0 | |
1861 | || opP->reg > ADDR7)) | |
1862 | ++losing; | |
1863 | break; | |
1864 | ||
252b5132 RH |
1865 | case 'B': /* FOO */ |
1866 | if (opP->mode != ABSL | |
1867 | || (flag_long_jumps | |
1868 | && strncmp (instring, "jbsr", 4) == 0)) | |
1869 | losing++; | |
1870 | break; | |
1871 | ||
3e602632 NC |
1872 | case 'b': |
1873 | switch (opP->mode) | |
1874 | { | |
1875 | case IMMED: | |
1876 | case ABSL: | |
1877 | case AREG: | |
1878 | case FPREG: | |
1879 | case CONTROL: | |
1880 | case POST: | |
1881 | case PRE: | |
1882 | case REGLST: | |
1883 | losing++; | |
1884 | break; | |
1885 | default: | |
1886 | break; | |
1887 | } | |
1888 | break; | |
1889 | ||
252b5132 RH |
1890 | case 'C': |
1891 | if (opP->mode != CONTROL || opP->reg != CCR) | |
1892 | losing++; | |
1893 | break; | |
1894 | ||
1895 | case 'd': | |
1896 | if (opP->mode != DISP | |
1897 | || opP->reg < ADDR0 | |
1898 | || opP->reg > ADDR7) | |
1899 | losing++; | |
1900 | break; | |
1901 | ||
1902 | case 'D': | |
1903 | if (opP->mode != DREG) | |
1904 | losing++; | |
1905 | break; | |
1906 | ||
6da466c7 ILT |
1907 | case 'E': |
1908 | if (opP->reg != ACC) | |
1909 | losing++; | |
1910 | break; | |
1911 | ||
fd99574b NC |
1912 | case 'e': |
1913 | if (opP->reg != ACC && opP->reg != ACC1 | |
1914 | && opP->reg != ACC2 && opP->reg != ACC3) | |
1915 | losing++; | |
1916 | break; | |
1917 | ||
252b5132 RH |
1918 | case 'F': |
1919 | if (opP->mode != FPREG) | |
1920 | losing++; | |
1921 | break; | |
1922 | ||
6da466c7 ILT |
1923 | case 'G': |
1924 | if (opP->reg != MACSR) | |
1925 | losing++; | |
1926 | break; | |
1927 | ||
fd99574b NC |
1928 | case 'g': |
1929 | if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) | |
1930 | losing++; | |
1931 | break; | |
1932 | ||
6da466c7 ILT |
1933 | case 'H': |
1934 | if (opP->reg != MASK) | |
1935 | losing++; | |
1936 | break; | |
1937 | ||
252b5132 RH |
1938 | case 'I': |
1939 | if (opP->mode != CONTROL | |
1940 | || opP->reg < COP0 | |
1941 | || opP->reg > COP7) | |
1942 | losing++; | |
1943 | break; | |
1944 | ||
fd99574b NC |
1945 | case 'i': |
1946 | if (opP->mode != LSH && opP->mode != RSH) | |
1947 | losing++; | |
1948 | break; | |
1949 | ||
252b5132 RH |
1950 | case 'J': |
1951 | if (opP->mode != CONTROL | |
1952 | || opP->reg < USP | |
0b2e31dc NS |
1953 | || opP->reg > last_movec_reg |
1954 | || !control_regs) | |
252b5132 RH |
1955 | losing++; |
1956 | else | |
1957 | { | |
1958 | const enum m68k_register *rp; | |
0b2e31dc | 1959 | |
252b5132 | 1960 | for (rp = control_regs; *rp; rp++) |
78336706 NS |
1961 | { |
1962 | if (*rp == opP->reg) | |
1963 | break; | |
1964 | /* In most CPUs RAMBAR refers to control reg | |
1965 | c05 (RAMBAR1), but a few CPUs have it | |
1966 | refer to c04 (RAMBAR0). */ | |
1967 | else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) | |
1968 | { | |
1969 | opP->reg = RAMBAR_ALT; | |
1970 | break; | |
1971 | } | |
1972 | } | |
252b5132 RH |
1973 | if (*rp == 0) |
1974 | losing++; | |
1975 | } | |
1976 | break; | |
1977 | ||
1978 | case 'k': | |
1979 | if (opP->mode != IMMED) | |
1980 | losing++; | |
1981 | break; | |
1982 | ||
1983 | case 'l': | |
1984 | case 'L': | |
1985 | if (opP->mode == DREG | |
1986 | || opP->mode == AREG | |
1987 | || opP->mode == FPREG) | |
1988 | { | |
1989 | if (s[1] == '8') | |
1990 | losing++; | |
1991 | else | |
1992 | { | |
1993 | switch (opP->mode) | |
1994 | { | |
1995 | case DREG: | |
1996 | opP->mask = 1 << (opP->reg - DATA0); | |
1997 | break; | |
1998 | case AREG: | |
1999 | opP->mask = 1 << (opP->reg - ADDR0 + 8); | |
2000 | break; | |
2001 | case FPREG: | |
2002 | opP->mask = 1 << (opP->reg - FP0 + 16); | |
2003 | break; | |
2004 | default: | |
2005 | abort (); | |
2006 | } | |
2007 | opP->mode = REGLST; | |
2008 | } | |
2009 | } | |
2010 | else if (opP->mode == CONTROL) | |
2011 | { | |
2012 | if (s[1] != '8') | |
2013 | losing++; | |
2014 | else | |
2015 | { | |
2016 | switch (opP->reg) | |
2017 | { | |
2018 | case FPI: | |
2019 | opP->mask = 1 << 24; | |
2020 | break; | |
2021 | case FPS: | |
2022 | opP->mask = 1 << 25; | |
2023 | break; | |
2024 | case FPC: | |
2025 | opP->mask = 1 << 26; | |
2026 | break; | |
2027 | default: | |
2028 | losing++; | |
2029 | break; | |
2030 | } | |
2031 | opP->mode = REGLST; | |
2032 | } | |
2033 | } | |
2034 | else if (opP->mode != REGLST) | |
2035 | losing++; | |
2036 | else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) | |
2037 | losing++; | |
2038 | else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) | |
2039 | losing++; | |
2040 | break; | |
2041 | ||
2042 | case 'M': | |
2043 | if (opP->mode != IMMED) | |
2044 | losing++; | |
2045 | else if (opP->disp.exp.X_op != O_constant | |
2046 | || ! issbyte (opP->disp.exp.X_add_number)) | |
2047 | losing++; | |
2048 | else if (! m68k_quick | |
2049 | && instring[3] != 'q' | |
2050 | && instring[4] != 'q') | |
2051 | losing++; | |
2052 | break; | |
2053 | ||
2054 | case 'O': | |
2055 | if (opP->mode != DREG | |
2056 | && opP->mode != IMMED | |
2057 | && opP->mode != ABSL) | |
2058 | losing++; | |
2059 | break; | |
2060 | ||
2061 | case 'Q': | |
2062 | if (opP->mode != IMMED) | |
2063 | losing++; | |
2064 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 | 2065 | || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) |
252b5132 RH |
2066 | losing++; |
2067 | else if (! m68k_quick | |
2068 | && (strncmp (instring, "add", 3) == 0 | |
2069 | || strncmp (instring, "sub", 3) == 0) | |
2070 | && instring[3] != 'q') | |
2071 | losing++; | |
2072 | break; | |
2073 | ||
2074 | case 'R': | |
2075 | if (opP->mode != DREG && opP->mode != AREG) | |
2076 | losing++; | |
2077 | break; | |
2078 | ||
2079 | case 'r': | |
2080 | if (opP->mode != AINDR | |
2081 | && (opP->mode != BASE | |
2082 | || (opP->reg != 0 | |
2083 | && opP->reg != ZADDR0) | |
2084 | || opP->disp.exp.X_op != O_absent | |
2085 | || ((opP->index.reg < DATA0 | |
2086 | || opP->index.reg > DATA7) | |
2087 | && (opP->index.reg < ADDR0 | |
2088 | || opP->index.reg > ADDR7)) | |
2089 | || opP->index.size != SIZE_UNSPEC | |
2090 | || opP->index.scale != 1)) | |
2091 | losing++; | |
2092 | break; | |
2093 | ||
2094 | case 's': | |
2095 | if (opP->mode != CONTROL | |
2096 | || ! (opP->reg == FPI | |
2097 | || opP->reg == FPS | |
2098 | || opP->reg == FPC)) | |
2099 | losing++; | |
2100 | break; | |
2101 | ||
2102 | case 'S': | |
2103 | if (opP->mode != CONTROL || opP->reg != SR) | |
2104 | losing++; | |
2105 | break; | |
2106 | ||
2107 | case 't': | |
2108 | if (opP->mode != IMMED) | |
2109 | losing++; | |
2110 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 | 2111 | || TRUNC (opP->disp.exp.X_add_number) > 7) |
252b5132 RH |
2112 | losing++; |
2113 | break; | |
2114 | ||
2115 | case 'U': | |
2116 | if (opP->mode != CONTROL || opP->reg != USP) | |
2117 | losing++; | |
2118 | break; | |
2119 | ||
3e602632 NC |
2120 | case 'x': |
2121 | if (opP->mode != IMMED) | |
2122 | losing++; | |
2123 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 AM |
2124 | || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff |
2125 | && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) | |
3e602632 NC |
2126 | losing++; |
2127 | break; | |
2128 | ||
afa2158f NS |
2129 | case 'j': |
2130 | if (opP->mode != IMMED) | |
2131 | losing++; | |
2132 | else if (opP->disp.exp.X_op != O_constant | |
2133 | || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) | |
2134 | losing++; | |
2135 | break; | |
2136 | ||
2137 | case 'K': | |
2138 | if (opP->mode != IMMED) | |
2139 | losing++; | |
2140 | else if (opP->disp.exp.X_op != O_constant | |
2141 | || TRUNC (opP->disp.exp.X_add_number) > 511) | |
2142 | losing++; | |
2143 | break; | |
2144 | ||
252b5132 RH |
2145 | /* JF these are out of order. We could put them |
2146 | in order if we were willing to put up with | |
2147 | bunches of #ifdef m68851s in the code. | |
2148 | ||
2149 | Don't forget that you need these operands | |
2150 | to use 68030 MMU instructions. */ | |
2151 | #ifndef NO_68851 | |
36759679 | 2152 | /* Memory addressing mode used by pflushr. */ |
252b5132 RH |
2153 | case '|': |
2154 | if (opP->mode == CONTROL | |
2155 | || opP->mode == FPREG | |
2156 | || opP->mode == DREG | |
2157 | || opP->mode == AREG | |
2158 | || opP->mode == REGLST) | |
2159 | losing++; | |
2160 | /* We should accept immediate operands, but they | |
2161 | supposedly have to be quad word, and we don't | |
2162 | handle that. I would like to see what a Motorola | |
2163 | assembler does before doing something here. */ | |
2164 | if (opP->mode == IMMED) | |
2165 | losing++; | |
2166 | break; | |
2167 | ||
2168 | case 'f': | |
2169 | if (opP->mode != CONTROL | |
2170 | || (opP->reg != SFC && opP->reg != DFC)) | |
2171 | losing++; | |
2172 | break; | |
2173 | ||
2174 | case '0': | |
2175 | if (opP->mode != CONTROL || opP->reg != TC) | |
2176 | losing++; | |
2177 | break; | |
2178 | ||
2179 | case '1': | |
2180 | if (opP->mode != CONTROL || opP->reg != AC) | |
2181 | losing++; | |
2182 | break; | |
2183 | ||
2184 | case '2': | |
2185 | if (opP->mode != CONTROL | |
2186 | || (opP->reg != CAL | |
2187 | && opP->reg != VAL | |
2188 | && opP->reg != SCC)) | |
2189 | losing++; | |
2190 | break; | |
2191 | ||
2192 | case 'V': | |
2193 | if (opP->mode != CONTROL | |
2194 | || opP->reg != VAL) | |
2195 | losing++; | |
2196 | break; | |
2197 | ||
2198 | case 'W': | |
2199 | if (opP->mode != CONTROL | |
2200 | || (opP->reg != DRP | |
2201 | && opP->reg != SRP | |
2202 | && opP->reg != CRP)) | |
2203 | losing++; | |
2204 | break; | |
2205 | ||
3e602632 NC |
2206 | case 'w': |
2207 | switch (opP->mode) | |
2208 | { | |
2209 | case IMMED: | |
2210 | case ABSL: | |
2211 | case AREG: | |
2212 | case DREG: | |
2213 | case FPREG: | |
2214 | case CONTROL: | |
2215 | case POST: | |
2216 | case PRE: | |
2217 | case REGLST: | |
2218 | losing++; | |
2219 | break; | |
2220 | default: | |
2221 | break; | |
2222 | } | |
2223 | break; | |
2224 | ||
252b5132 RH |
2225 | case 'X': |
2226 | if (opP->mode != CONTROL | |
2227 | || (!(opP->reg >= BAD && opP->reg <= BAD + 7) | |
2228 | && !(opP->reg >= BAC && opP->reg <= BAC + 7))) | |
2229 | losing++; | |
2230 | break; | |
2231 | ||
2232 | case 'Y': | |
2233 | if (opP->mode != CONTROL || opP->reg != PSR) | |
2234 | losing++; | |
2235 | break; | |
2236 | ||
2237 | case 'Z': | |
2238 | if (opP->mode != CONTROL || opP->reg != PCSR) | |
2239 | losing++; | |
2240 | break; | |
2241 | #endif | |
2242 | case 'c': | |
2243 | if (opP->mode != CONTROL | |
2244 | || (opP->reg != NC | |
2245 | && opP->reg != IC | |
2246 | && opP->reg != DC | |
2247 | && opP->reg != BC)) | |
36759679 | 2248 | losing++; |
252b5132 RH |
2249 | break; |
2250 | ||
2251 | case '_': | |
2252 | if (opP->mode != ABSL) | |
2253 | ++losing; | |
2254 | break; | |
2255 | ||
6da466c7 ILT |
2256 | case 'u': |
2257 | if (opP->reg < DATA0L || opP->reg > ADDR7U) | |
2258 | losing++; | |
2259 | /* FIXME: kludge instead of fixing parser: | |
2260 | upper/lower registers are *not* CONTROL | |
92774660 | 2261 | registers, but ordinary ones. */ |
6da466c7 ILT |
2262 | if ((opP->reg >= DATA0L && opP->reg <= DATA7L) |
2263 | || (opP->reg >= DATA0U && opP->reg <= DATA7U)) | |
2264 | opP->mode = DREG; | |
2265 | else | |
2266 | opP->mode = AREG; | |
2267 | break; | |
2268 | ||
3e602632 NC |
2269 | case 'y': |
2270 | if (!(opP->mode == AINDR | |
31302357 AS |
2271 | || (opP->mode == DISP |
2272 | && !(opP->reg == PC || opP->reg == ZPC)))) | |
3e602632 NC |
2273 | losing++; |
2274 | break; | |
2275 | ||
2276 | case 'z': | |
2277 | if (!(opP->mode == AINDR || opP->mode == DISP)) | |
2278 | losing++; | |
2279 | break; | |
2280 | ||
252b5132 RH |
2281 | default: |
2282 | abort (); | |
36759679 | 2283 | } |
252b5132 RH |
2284 | |
2285 | if (losing) | |
2286 | break; | |
36759679 | 2287 | } |
03b13e59 NC |
2288 | |
2289 | /* Since we have found the correct instruction, copy | |
2290 | in the modifications that we may have made. */ | |
2291 | if (!losing) | |
2292 | for (i = 0; i < opsfound; i++) | |
2293 | the_ins.operands[i] = operands_backup[i]; | |
36759679 | 2294 | } |
252b5132 RH |
2295 | |
2296 | if (!losing) | |
36759679 | 2297 | break; |
252b5132 RH |
2298 | |
2299 | opcode = opcode->m_next; | |
2300 | ||
2301 | if (!opcode) | |
2302 | { | |
2303 | if (ok_arch | |
2304 | && !(ok_arch & current_architecture)) | |
2305 | { | |
6d89cc8f NS |
2306 | const struct m68k_cpu *cpu; |
2307 | int any = 0; | |
2308 | size_t space = 400; | |
2309 | char *buf = xmalloc (space + 1); | |
2310 | size_t len; | |
2311 | int paren = 1; | |
2312 | ||
2313 | the_ins.error = buf; | |
2314 | /* Make sure there's a NUL at the end of the buffer -- strncpy | |
b2f58c0c | 2315 | won't write one when it runs out of buffer. */ |
6d89cc8f NS |
2316 | buf[space] = 0; |
2317 | #define APPEND(STRING) \ | |
2318 | (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) | |
2319 | ||
2320 | APPEND (_("invalid instruction for this architecture; needs ")); | |
252b5132 RH |
2321 | switch (ok_arch) |
2322 | { | |
6b6e92f4 | 2323 | case mcfisa_a: |
b2f58c0c | 2324 | APPEND ("ColdFire ISA_A"); |
6b6e92f4 NC |
2325 | break; |
2326 | case mcfhwdiv: | |
b2f58c0c NC |
2327 | APPEND ("ColdFire "); |
2328 | APPEND (_("hardware divide")); | |
6b6e92f4 NC |
2329 | break; |
2330 | case mcfisa_aa: | |
b2f58c0c | 2331 | APPEND ("ColdFire ISA_A+"); |
6b6e92f4 NC |
2332 | break; |
2333 | case mcfisa_b: | |
b2f58c0c | 2334 | APPEND ("ColdFire ISA_B"); |
6b6e92f4 | 2335 | break; |
8d100c32 | 2336 | case mcfisa_c: |
b2f58c0c | 2337 | APPEND ("ColdFire ISA_C"); |
8d100c32 | 2338 | break; |
3e602632 | 2339 | case cfloat: |
b2f58c0c | 2340 | APPEND ("ColdFire fpu"); |
3e602632 | 2341 | break; |
252b5132 | 2342 | case mfloat: |
b2f58c0c | 2343 | APPEND ("M68K fpu"); |
252b5132 RH |
2344 | break; |
2345 | case mmmu: | |
b2f58c0c | 2346 | APPEND ("M68K mmu"); |
252b5132 RH |
2347 | break; |
2348 | case m68020up: | |
b2f58c0c NC |
2349 | APPEND ("68020 "); |
2350 | APPEND (_("or higher")); | |
252b5132 RH |
2351 | break; |
2352 | case m68000up: | |
b2f58c0c NC |
2353 | APPEND ("68000 "); |
2354 | APPEND (_("or higher")); | |
252b5132 RH |
2355 | break; |
2356 | case m68010up: | |
b2f58c0c NC |
2357 | APPEND ("68010 "); |
2358 | APPEND (_("or higher")); | |
252b5132 RH |
2359 | break; |
2360 | default: | |
6d89cc8f NS |
2361 | paren = 0; |
2362 | } | |
2363 | if (paren) | |
2364 | APPEND (" ("); | |
6b6e92f4 | 2365 | |
6d89cc8f NS |
2366 | for (cpu = m68k_cpus; cpu->name; cpu++) |
2367 | if (!cpu->alias && (cpu->arch & ok_arch)) | |
2368 | { | |
2369 | const struct m68k_cpu *alias; | |
869ddf2a NS |
2370 | int seen_master = 0; |
2371 | ||
6d89cc8f NS |
2372 | if (any) |
2373 | APPEND (", "); | |
2374 | any = 0; | |
2375 | APPEND (cpu->name); | |
869ddf2a NS |
2376 | for (alias = cpu; alias != m68k_cpus; alias--) |
2377 | if (alias[-1].alias >= 0) | |
2378 | break; | |
2379 | for (; !seen_master || alias->alias > 0; alias++) | |
6d89cc8f | 2380 | { |
869ddf2a NS |
2381 | if (!alias->alias) |
2382 | seen_master = 1; | |
2383 | else | |
2384 | { | |
2385 | if (any) | |
2386 | APPEND (", "); | |
2387 | else | |
2388 | APPEND (" ["); | |
2389 | APPEND (alias->name); | |
2390 | any = 1; | |
2391 | } | |
6d89cc8f | 2392 | } |
869ddf2a NS |
2393 | if (any) |
2394 | APPEND ("]"); | |
6d89cc8f | 2395 | any = 1; |
252b5132 | 2396 | } |
6d89cc8f NS |
2397 | if (paren) |
2398 | APPEND (")"); | |
2399 | #undef APPEND | |
2400 | if (!space) | |
2401 | { | |
b2f58c0c | 2402 | /* We ran out of space, so replace the end of the list |
6d89cc8f NS |
2403 | with ellipsis. */ |
2404 | buf -= 4; | |
2405 | while (*buf != ' ') | |
2406 | buf--; | |
2407 | strcpy (buf, " ..."); | |
252b5132 | 2408 | } |
252b5132 RH |
2409 | } |
2410 | else | |
2411 | the_ins.error = _("operands mismatch"); | |
2412 | return; | |
36759679 | 2413 | } |
252b5132 RH |
2414 | |
2415 | losing = 0; | |
2416 | } | |
2417 | ||
36759679 | 2418 | /* Now assemble it. */ |
252b5132 RH |
2419 | the_ins.args = opcode->m_operands; |
2420 | the_ins.numargs = opcode->m_opnum; | |
2421 | the_ins.numo = opcode->m_codenum; | |
2422 | the_ins.opcode[0] = getone (opcode); | |
2423 | the_ins.opcode[1] = gettwo (opcode); | |
2424 | ||
2425 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) | |
2426 | { | |
9a2e615a | 2427 | int have_disp = 0; |
cac27205 | 2428 | int use_pl = 0; |
9a2e615a | 2429 | |
252b5132 | 2430 | /* This switch is a doozy. |
31302357 | 2431 | Watch the first step; its a big one! */ |
252b5132 RH |
2432 | switch (s[0]) |
2433 | { | |
2434 | ||
2435 | case '*': | |
2436 | case '~': | |
2437 | case '%': | |
2438 | case ';': | |
2439 | case '@': | |
2440 | case '!': | |
2441 | case '&': | |
2442 | case '$': | |
2443 | case '?': | |
2444 | case '/': | |
2445 | case '<': | |
2446 | case '>': | |
3e602632 | 2447 | case 'b': |
252b5132 RH |
2448 | case 'm': |
2449 | case 'n': | |
2450 | case 'o': | |
2451 | case 'p': | |
2452 | case 'q': | |
2453 | case 'v': | |
3e602632 NC |
2454 | case 'w': |
2455 | case 'y': | |
2456 | case 'z': | |
fd99574b | 2457 | case '4': |
252b5132 RH |
2458 | #ifndef NO_68851 |
2459 | case '|': | |
2460 | #endif | |
2461 | switch (opP->mode) | |
2462 | { | |
2463 | case IMMED: | |
2464 | tmpreg = 0x3c; /* 7.4 */ | |
2465 | if (strchr ("bwl", s[1])) | |
3e602632 | 2466 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2467 | else |
2468 | nextword = get_num (&opP->disp, 0); | |
2469 | if (isvar (&opP->disp)) | |
2470 | add_fix (s[1], &opP->disp, 0, 0); | |
2471 | switch (s[1]) | |
2472 | { | |
2473 | case 'b': | |
2474 | if (!isbyte (nextword)) | |
2475 | opP->error = _("operand out of range"); | |
2476 | addword (nextword); | |
2477 | baseo = 0; | |
2478 | break; | |
2479 | case 'w': | |
2480 | if (!isword (nextword)) | |
2481 | opP->error = _("operand out of range"); | |
2482 | addword (nextword); | |
2483 | baseo = 0; | |
2484 | break; | |
2485 | case 'W': | |
2486 | if (!issword (nextword)) | |
2487 | opP->error = _("operand out of range"); | |
2488 | addword (nextword); | |
2489 | baseo = 0; | |
2490 | break; | |
2491 | case 'l': | |
2492 | addword (nextword >> 16); | |
2493 | addword (nextword); | |
2494 | baseo = 0; | |
2495 | break; | |
2496 | ||
2497 | case 'f': | |
2498 | baseo = 2; | |
2499 | outro = 8; | |
2500 | break; | |
2501 | case 'F': | |
2502 | baseo = 4; | |
2503 | outro = 11; | |
2504 | break; | |
2505 | case 'x': | |
2506 | baseo = 6; | |
2507 | outro = 15; | |
2508 | break; | |
2509 | case 'p': | |
2510 | baseo = 6; | |
2511 | outro = -1; | |
2512 | break; | |
2513 | default: | |
2514 | abort (); | |
2515 | } | |
2516 | if (!baseo) | |
2517 | break; | |
2518 | ||
36759679 | 2519 | /* We gotta put out some float. */ |
252b5132 RH |
2520 | if (op (&opP->disp) != O_big) |
2521 | { | |
2522 | valueT val; | |
2523 | int gencnt; | |
2524 | ||
2525 | /* Can other cases happen here? */ | |
2526 | if (op (&opP->disp) != O_constant) | |
2527 | abort (); | |
2528 | ||
2529 | val = (valueT) offs (&opP->disp); | |
2530 | gencnt = 0; | |
2531 | do | |
2532 | { | |
2533 | generic_bignum[gencnt] = (LITTLENUM_TYPE) val; | |
2534 | val >>= LITTLENUM_NUMBER_OF_BITS; | |
2535 | ++gencnt; | |
2536 | } | |
2537 | while (val != 0); | |
2538 | offs (&opP->disp) = gencnt; | |
2539 | } | |
2540 | if (offs (&opP->disp) > 0) | |
2541 | { | |
2542 | if (offs (&opP->disp) > baseo) | |
2543 | { | |
2544 | as_warn (_("Bignum too big for %c format; truncated"), | |
2545 | s[1]); | |
2546 | offs (&opP->disp) = baseo; | |
2547 | } | |
2548 | baseo -= offs (&opP->disp); | |
2549 | while (baseo--) | |
2550 | addword (0); | |
2551 | for (wordp = generic_bignum + offs (&opP->disp) - 1; | |
2552 | offs (&opP->disp)--; | |
2553 | --wordp) | |
2554 | addword (*wordp); | |
2555 | break; | |
2556 | } | |
2557 | gen_to_words (words, baseo, (long) outro); | |
2558 | for (wordp = words; baseo--; wordp++) | |
2559 | addword (*wordp); | |
2560 | break; | |
2561 | case DREG: | |
2562 | tmpreg = opP->reg - DATA; /* 0.dreg */ | |
2563 | break; | |
2564 | case AREG: | |
2565 | tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ | |
2566 | break; | |
2567 | case AINDR: | |
2568 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2569 | break; | |
2570 | case ADEC: | |
2571 | tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ | |
2572 | break; | |
2573 | case AINC: | |
2574 | tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ | |
2575 | break; | |
2576 | case DISP: | |
2577 | ||
3e602632 | 2578 | nextword = get_num (&opP->disp, 90); |
252b5132 | 2579 | |
580b9172 NC |
2580 | /* Convert mode 5 addressing with a zero offset into |
2581 | mode 2 addressing to reduce the instruction size by a | |
2582 | word. */ | |
2583 | if (! isvar (&opP->disp) | |
2584 | && (nextword == 0) | |
2585 | && (opP->disp.size == SIZE_UNSPEC) | |
2586 | && (opP->reg >= ADDR0) | |
2587 | && (opP->reg <= ADDR7)) | |
2588 | { | |
2589 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2590 | break; | |
2591 | } | |
2592 | ||
252b5132 RH |
2593 | if (opP->reg == PC |
2594 | && ! isvar (&opP->disp) | |
2595 | && m68k_abspcadd) | |
2596 | { | |
2597 | opP->disp.exp.X_op = O_symbol; | |
252b5132 RH |
2598 | opP->disp.exp.X_add_symbol = |
2599 | section_symbol (absolute_section); | |
252b5132 RH |
2600 | } |
2601 | ||
36759679 | 2602 | /* Force into index mode. Hope this works. */ |
252b5132 RH |
2603 | |
2604 | /* We do the first bit for 32-bit displacements, and the | |
2605 | second bit for 16 bit ones. It is possible that we | |
2606 | should make the default be WORD instead of LONG, but | |
2607 | I think that'd break GCC, so we put up with a little | |
2608 | inefficiency for the sake of working output. */ | |
2609 | ||
2610 | if (!issword (nextword) | |
2611 | || (isvar (&opP->disp) | |
2612 | && ((opP->disp.size == SIZE_UNSPEC | |
2613 | && flag_short_refs == 0 | |
2614 | && cpu_of_arch (current_architecture) >= m68020 | |
6da466c7 | 2615 | && ! arch_coldfire_p (current_architecture)) |
252b5132 RH |
2616 | || opP->disp.size == SIZE_LONG))) |
2617 | { | |
2618 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2619 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2620 | opP->error = |
2621 | _("displacement too large for this architecture; needs 68020 or higher"); | |
2622 | if (opP->reg == PC) | |
2623 | tmpreg = 0x3B; /* 7.3 */ | |
2624 | else | |
2625 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2626 | if (isvar (&opP->disp)) | |
2627 | { | |
2628 | if (opP->reg == PC) | |
2629 | { | |
2630 | if (opP->disp.size == SIZE_LONG | |
2631 | #ifdef OBJ_ELF | |
2632 | /* If the displacement needs pic | |
2633 | relocation it cannot be relaxed. */ | |
2634 | || opP->disp.pic_reloc != pic_none | |
2635 | #endif | |
2636 | ) | |
2637 | { | |
2638 | addword (0x0170); | |
2639 | add_fix ('l', &opP->disp, 1, 2); | |
2640 | } | |
2641 | else | |
2642 | { | |
2643 | add_frag (adds (&opP->disp), | |
bd17c2c3 | 2644 | SEXT (offs (&opP->disp)), |
151337e8 | 2645 | TAB (PCREL1632, SZ_UNDEF)); |
252b5132 RH |
2646 | break; |
2647 | } | |
2648 | } | |
2649 | else | |
2650 | { | |
2651 | addword (0x0170); | |
2652 | add_fix ('l', &opP->disp, 0, 0); | |
2653 | } | |
2654 | } | |
2655 | else | |
2656 | addword (0x0170); | |
2657 | addword (nextword >> 16); | |
2658 | } | |
2659 | else | |
2660 | { | |
2661 | if (opP->reg == PC) | |
2662 | tmpreg = 0x3A; /* 7.2 */ | |
2663 | else | |
2664 | tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ | |
2665 | ||
2666 | if (isvar (&opP->disp)) | |
2667 | { | |
2668 | if (opP->reg == PC) | |
2669 | { | |
2670 | add_fix ('w', &opP->disp, 1, 0); | |
2671 | } | |
2672 | else | |
2673 | add_fix ('w', &opP->disp, 0, 0); | |
2674 | } | |
2675 | } | |
2676 | addword (nextword); | |
2677 | break; | |
2678 | ||
2679 | case POST: | |
2680 | case PRE: | |
2681 | case BASE: | |
2682 | nextword = 0; | |
3e602632 | 2683 | baseo = get_num (&opP->disp, 90); |
252b5132 | 2684 | if (opP->mode == POST || opP->mode == PRE) |
3e602632 | 2685 | outro = get_num (&opP->odisp, 90); |
252b5132 RH |
2686 | /* Figure out the `addressing mode'. |
2687 | Also turn on the BASE_DISABLE bit, if needed. */ | |
2688 | if (opP->reg == PC || opP->reg == ZPC) | |
2689 | { | |
2690 | tmpreg = 0x3b; /* 7.3 */ | |
2691 | if (opP->reg == ZPC) | |
2692 | nextword |= 0x80; | |
2693 | } | |
2694 | else if (opP->reg == 0) | |
2695 | { | |
2696 | nextword |= 0x80; | |
2697 | tmpreg = 0x30; /* 6.garbage */ | |
2698 | } | |
2699 | else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) | |
2700 | { | |
2701 | nextword |= 0x80; | |
2702 | tmpreg = 0x30 + opP->reg - ZADDR0; | |
2703 | } | |
2704 | else | |
2705 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2706 | ||
2707 | siz1 = opP->disp.size; | |
2708 | if (opP->mode == POST || opP->mode == PRE) | |
2709 | siz2 = opP->odisp.size; | |
2710 | else | |
2711 | siz2 = SIZE_UNSPEC; | |
2712 | ||
36759679 | 2713 | /* Index register stuff. */ |
252b5132 RH |
2714 | if (opP->index.reg != 0 |
2715 | && opP->index.reg >= DATA | |
2716 | && opP->index.reg <= ADDR7) | |
2717 | { | |
2718 | nextword |= (opP->index.reg - DATA) << 12; | |
2719 | ||
2720 | if (opP->index.size == SIZE_LONG | |
2721 | || (opP->index.size == SIZE_UNSPEC | |
2722 | && m68k_index_width_default == SIZE_LONG)) | |
2723 | nextword |= 0x800; | |
2724 | ||
92774660 | 2725 | if ((opP->index.scale != 1 |
252b5132 | 2726 | && cpu_of_arch (current_architecture) < m68020) |
92774660 | 2727 | || (opP->index.scale == 8 |
3e602632 | 2728 | && (arch_coldfire_p (current_architecture) |
6b6e92f4 | 2729 | && !arch_coldfire_fpu (current_architecture)))) |
252b5132 RH |
2730 | { |
2731 | opP->error = | |
2732 | _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); | |
2733 | } | |
2734 | ||
6da466c7 ILT |
2735 | if (arch_coldfire_p (current_architecture) |
2736 | && opP->index.size == SIZE_WORD) | |
2737 | opP->error = _("invalid index size for coldfire"); | |
2738 | ||
252b5132 RH |
2739 | switch (opP->index.scale) |
2740 | { | |
2741 | case 1: | |
2742 | break; | |
2743 | case 2: | |
2744 | nextword |= 0x200; | |
2745 | break; | |
2746 | case 4: | |
2747 | nextword |= 0x400; | |
2748 | break; | |
2749 | case 8: | |
2750 | nextword |= 0x600; | |
2751 | break; | |
2752 | default: | |
2753 | abort (); | |
2754 | } | |
2755 | /* IF its simple, | |
2756 | GET US OUT OF HERE! */ | |
2757 | ||
2758 | /* Must be INDEX, with an index register. Address | |
2759 | register cannot be ZERO-PC, and either :b was | |
2760 | forced, or we know it will fit. For a 68000 or | |
2761 | 68010, force this mode anyways, because the | |
2762 | larger modes aren't supported. */ | |
2763 | if (opP->mode == BASE | |
2764 | && ((opP->reg >= ADDR0 | |
2765 | && opP->reg <= ADDR7) | |
2766 | || opP->reg == PC)) | |
2767 | { | |
2768 | if (siz1 == SIZE_BYTE | |
2769 | || cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2770 | || arch_coldfire_p (current_architecture) |
252b5132 RH |
2771 | || (siz1 == SIZE_UNSPEC |
2772 | && ! isvar (&opP->disp) | |
2773 | && issbyte (baseo))) | |
2774 | { | |
2775 | nextword += baseo & 0xff; | |
2776 | addword (nextword); | |
2777 | if (isvar (&opP->disp)) | |
2778 | { | |
2779 | /* Do a byte relocation. If it doesn't | |
2780 | fit (possible on m68000) let the | |
2781 | fixup processing complain later. */ | |
2782 | if (opP->reg == PC) | |
2783 | add_fix ('B', &opP->disp, 1, 1); | |
2784 | else | |
2785 | add_fix ('B', &opP->disp, 0, 0); | |
2786 | } | |
2787 | else if (siz1 != SIZE_BYTE) | |
2788 | { | |
2789 | if (siz1 != SIZE_UNSPEC) | |
2790 | as_warn (_("Forcing byte displacement")); | |
2791 | if (! issbyte (baseo)) | |
2792 | opP->error = _("byte displacement out of range"); | |
2793 | } | |
2794 | ||
2795 | break; | |
2796 | } | |
2797 | else if (siz1 == SIZE_UNSPEC | |
2798 | && opP->reg == PC | |
2799 | && isvar (&opP->disp) | |
2800 | && subs (&opP->disp) == NULL | |
2801 | #ifdef OBJ_ELF | |
2802 | /* If the displacement needs pic | |
2803 | relocation it cannot be relaxed. */ | |
2804 | && opP->disp.pic_reloc == pic_none | |
2805 | #endif | |
2806 | ) | |
2807 | { | |
2808 | /* The code in md_convert_frag_1 needs to be | |
2809 | able to adjust nextword. Call frag_grow | |
2810 | to ensure that we have enough space in | |
2811 | the frag obstack to make all the bytes | |
2812 | contiguous. */ | |
2813 | frag_grow (14); | |
8a104df9 KH |
2814 | nextword += baseo & 0xff; |
2815 | addword (nextword); | |
bd17c2c3 AM |
2816 | add_frag (adds (&opP->disp), |
2817 | SEXT (offs (&opP->disp)), | |
8a104df9 | 2818 | TAB (PCINDEX, SZ_UNDEF)); |
252b5132 RH |
2819 | |
2820 | break; | |
8a104df9 | 2821 | } |
252b5132 RH |
2822 | } |
2823 | } | |
2824 | else | |
2825 | { | |
36759679 | 2826 | nextword |= 0x40; /* No index reg. */ |
252b5132 RH |
2827 | if (opP->index.reg >= ZDATA0 |
2828 | && opP->index.reg <= ZDATA7) | |
2829 | nextword |= (opP->index.reg - ZDATA0) << 12; | |
2830 | else if (opP->index.reg >= ZADDR0 | |
2831 | || opP->index.reg <= ZADDR7) | |
2832 | nextword |= (opP->index.reg - ZADDR0 + 8) << 12; | |
2833 | } | |
2834 | ||
2835 | /* It isn't simple. */ | |
2836 | ||
2837 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2838 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2839 | opP->error = |
2840 | _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2841 | ||
2842 | nextword |= 0x100; | |
2843 | /* If the guy specified a width, we assume that it is | |
2844 | wide enough. Maybe it isn't. If so, we lose. */ | |
2845 | switch (siz1) | |
2846 | { | |
2847 | case SIZE_UNSPEC: | |
2848 | if (isvar (&opP->disp) | |
2849 | ? m68k_rel32 | |
2850 | : ! issword (baseo)) | |
2851 | { | |
2852 | siz1 = SIZE_LONG; | |
2853 | nextword |= 0x30; | |
2854 | } | |
2855 | else if (! isvar (&opP->disp) && baseo == 0) | |
2856 | nextword |= 0x10; | |
2857 | else | |
2858 | { | |
2859 | nextword |= 0x20; | |
2860 | siz1 = SIZE_WORD; | |
2861 | } | |
2862 | break; | |
2863 | case SIZE_BYTE: | |
2864 | as_warn (_(":b not permitted; defaulting to :w")); | |
2865 | /* Fall through. */ | |
2866 | case SIZE_WORD: | |
2867 | nextword |= 0x20; | |
2868 | break; | |
2869 | case SIZE_LONG: | |
2870 | nextword |= 0x30; | |
2871 | break; | |
2872 | } | |
2873 | ||
67c1ffbe | 2874 | /* Figure out inner displacement stuff. */ |
252b5132 RH |
2875 | if (opP->mode == POST || opP->mode == PRE) |
2876 | { | |
2877 | if (cpu_of_arch (current_architecture) & cpu32) | |
2878 | opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2879 | switch (siz2) | |
2880 | { | |
2881 | case SIZE_UNSPEC: | |
2882 | if (isvar (&opP->odisp) | |
2883 | ? m68k_rel32 | |
2884 | : ! issword (outro)) | |
2885 | { | |
2886 | siz2 = SIZE_LONG; | |
2887 | nextword |= 0x3; | |
2888 | } | |
2889 | else if (! isvar (&opP->odisp) && outro == 0) | |
2890 | nextword |= 0x1; | |
2891 | else | |
2892 | { | |
2893 | nextword |= 0x2; | |
2894 | siz2 = SIZE_WORD; | |
2895 | } | |
2896 | break; | |
2897 | case 1: | |
2898 | as_warn (_(":b not permitted; defaulting to :w")); | |
2899 | /* Fall through. */ | |
2900 | case 2: | |
2901 | nextword |= 0x2; | |
2902 | break; | |
2903 | case 3: | |
2904 | nextword |= 0x3; | |
2905 | break; | |
2906 | } | |
2907 | if (opP->mode == POST | |
2908 | && (nextword & 0x40) == 0) | |
2909 | nextword |= 0x04; | |
2910 | } | |
2911 | addword (nextword); | |
2912 | ||
2913 | if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) | |
2914 | { | |
2915 | if (opP->reg == PC || opP->reg == ZPC) | |
2916 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); | |
2917 | else | |
2918 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); | |
2919 | } | |
2920 | if (siz1 == SIZE_LONG) | |
2921 | addword (baseo >> 16); | |
2922 | if (siz1 != SIZE_UNSPEC) | |
2923 | addword (baseo); | |
2924 | ||
2925 | if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) | |
2926 | add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); | |
2927 | if (siz2 == SIZE_LONG) | |
2928 | addword (outro >> 16); | |
2929 | if (siz2 != SIZE_UNSPEC) | |
2930 | addword (outro); | |
2931 | ||
2932 | break; | |
2933 | ||
2934 | case ABSL: | |
3e602632 | 2935 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2936 | switch (opP->disp.size) |
2937 | { | |
2938 | default: | |
2939 | abort (); | |
2940 | case SIZE_UNSPEC: | |
2941 | if (!isvar (&opP->disp) && issword (offs (&opP->disp))) | |
2942 | { | |
2943 | tmpreg = 0x38; /* 7.0 */ | |
2944 | addword (nextword); | |
2945 | break; | |
2946 | } | |
252b5132 RH |
2947 | if (isvar (&opP->disp) |
2948 | && !subs (&opP->disp) | |
2949 | && adds (&opP->disp) | |
2950 | #ifdef OBJ_ELF | |
2951 | /* If the displacement needs pic relocation it | |
2952 | cannot be relaxed. */ | |
2953 | && opP->disp.pic_reloc == pic_none | |
2954 | #endif | |
252b5132 RH |
2955 | && !flag_long_jumps |
2956 | && !strchr ("~%&$?", s[0])) | |
2957 | { | |
2958 | tmpreg = 0x3A; /* 7.2 */ | |
2959 | add_frag (adds (&opP->disp), | |
bd17c2c3 | 2960 | SEXT (offs (&opP->disp)), |
151337e8 | 2961 | TAB (ABSTOPCREL, SZ_UNDEF)); |
252b5132 RH |
2962 | break; |
2963 | } | |
36759679 | 2964 | /* Fall through into long. */ |
252b5132 RH |
2965 | case SIZE_LONG: |
2966 | if (isvar (&opP->disp)) | |
2967 | add_fix ('l', &opP->disp, 0, 0); | |
2968 | ||
2969 | tmpreg = 0x39;/* 7.1 mode */ | |
2970 | addword (nextword >> 16); | |
2971 | addword (nextword); | |
2972 | break; | |
2973 | ||
2974 | case SIZE_BYTE: | |
2975 | as_bad (_("unsupported byte value; use a different suffix")); | |
2976 | /* Fall through. */ | |
36759679 NC |
2977 | |
2978 | case SIZE_WORD: | |
252b5132 RH |
2979 | if (isvar (&opP->disp)) |
2980 | add_fix ('w', &opP->disp, 0, 0); | |
2981 | ||
2982 | tmpreg = 0x38;/* 7.0 mode */ | |
2983 | addword (nextword); | |
2984 | break; | |
2985 | } | |
2986 | break; | |
2987 | case CONTROL: | |
2988 | case FPREG: | |
2989 | default: | |
2990 | as_bad (_("unknown/incorrect operand")); | |
bc805888 | 2991 | /* abort (); */ |
252b5132 | 2992 | } |
fd99574b NC |
2993 | |
2994 | /* If s[0] is '4', then this is for the mac instructions | |
2995 | that can have a trailing_ampersand set. If so, set 0x100 | |
2996 | bit on tmpreg so install_gen_operand can check for it and | |
2997 | set the appropriate bit (word2, bit 5). */ | |
2998 | if (s[0] == '4') | |
2999 | { | |
3000 | if (opP->trailing_ampersand) | |
3001 | tmpreg |= 0x100; | |
3002 | } | |
252b5132 RH |
3003 | install_gen_operand (s[1], tmpreg); |
3004 | break; | |
3005 | ||
3006 | case '#': | |
3007 | case '^': | |
3008 | switch (s[1]) | |
3009 | { /* JF: I hate floating point! */ | |
3010 | case 'j': | |
3011 | tmpreg = 70; | |
3012 | break; | |
3013 | case '8': | |
3014 | tmpreg = 20; | |
3015 | break; | |
3016 | case 'C': | |
3017 | tmpreg = 50; | |
3018 | break; | |
3019 | case '3': | |
3020 | default: | |
3e602632 | 3021 | tmpreg = 90; |
252b5132 RH |
3022 | break; |
3023 | } | |
3024 | tmpreg = get_num (&opP->disp, tmpreg); | |
3025 | if (isvar (&opP->disp)) | |
3026 | add_fix (s[1], &opP->disp, 0, 0); | |
3027 | switch (s[1]) | |
3028 | { | |
3029 | case 'b': /* Danger: These do no check for | |
3030 | certain types of overflow. | |
3031 | user beware! */ | |
3032 | if (!isbyte (tmpreg)) | |
3033 | opP->error = _("out of range"); | |
3034 | insop (tmpreg, opcode); | |
3035 | if (isvar (&opP->disp)) | |
3036 | the_ins.reloc[the_ins.nrel - 1].n = | |
3037 | (opcode->m_codenum) * 2 + 1; | |
3038 | break; | |
3039 | case 'B': | |
3040 | if (!issbyte (tmpreg)) | |
3041 | opP->error = _("out of range"); | |
3042 | the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; | |
3043 | if (isvar (&opP->disp)) | |
3044 | the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; | |
3045 | break; | |
3046 | case 'w': | |
3047 | if (!isword (tmpreg)) | |
3048 | opP->error = _("out of range"); | |
3049 | insop (tmpreg, opcode); | |
3050 | if (isvar (&opP->disp)) | |
3051 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
3052 | break; | |
3053 | case 'W': | |
3054 | if (!issword (tmpreg)) | |
3055 | opP->error = _("out of range"); | |
3056 | insop (tmpreg, opcode); | |
3057 | if (isvar (&opP->disp)) | |
3058 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
3059 | break; | |
3060 | case 'l': | |
3061 | /* Because of the way insop works, we put these two out | |
3062 | backwards. */ | |
3063 | insop (tmpreg, opcode); | |
3064 | insop (tmpreg >> 16, opcode); | |
3065 | if (isvar (&opP->disp)) | |
3066 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
3067 | break; | |
3068 | case '3': | |
3069 | tmpreg &= 0xFF; | |
3070 | case '8': | |
3071 | case 'C': | |
3072 | case 'j': | |
3073 | install_operand (s[1], tmpreg); | |
3074 | break; | |
3075 | default: | |
3076 | abort (); | |
3077 | } | |
3078 | break; | |
3079 | ||
3080 | case '+': | |
3081 | case '-': | |
3082 | case 'A': | |
3083 | case 'a': | |
3084 | install_operand (s[1], opP->reg - ADDR); | |
3085 | break; | |
3086 | ||
3087 | case 'B': | |
3e602632 | 3088 | tmpreg = get_num (&opP->disp, 90); |
9a2e615a | 3089 | |
252b5132 RH |
3090 | switch (s[1]) |
3091 | { | |
3092 | case 'B': | |
8390138c | 3093 | add_fix ('B', &opP->disp, 1, -1); |
252b5132 RH |
3094 | break; |
3095 | case 'W': | |
3096 | add_fix ('w', &opP->disp, 1, 0); | |
3097 | addword (0); | |
3098 | break; | |
3099 | case 'L': | |
3100 | long_branch: | |
151337e8 | 3101 | the_ins.opcode[0] |= 0xff; |
252b5132 RH |
3102 | add_fix ('l', &opP->disp, 1, 0); |
3103 | addword (0); | |
3104 | addword (0); | |
3105 | break; | |
9a2e615a NS |
3106 | case 'g': /* Conditional branch */ |
3107 | have_disp = HAVE_LONG_CALL (current_architecture); | |
3108 | goto var_branch; | |
3109 | ||
3110 | case 'b': /* Unconditional branch */ | |
3111 | have_disp = HAVE_LONG_BRANCH (current_architecture); | |
cac27205 | 3112 | use_pl = LONG_BRANCH_VIA_COND (current_architecture); |
9a2e615a NS |
3113 | goto var_branch; |
3114 | ||
3115 | case 's': /* Unconditional subroutine */ | |
3116 | have_disp = HAVE_LONG_CALL (current_architecture); | |
3117 | ||
3118 | var_branch: | |
3119 | if (subs (&opP->disp) /* We can't relax it. */ | |
252b5132 | 3120 | #ifdef OBJ_ELF |
9a2e615a NS |
3121 | /* If the displacement needs pic relocation it cannot be |
3122 | relaxed. */ | |
3123 | || opP->disp.pic_reloc != pic_none | |
252b5132 | 3124 | #endif |
9a2e615a NS |
3125 | || 0) |
3126 | { | |
3127 | if (!have_disp) | |
3128 | as_warn (_("Can't use long branches on this architecture")); | |
3129 | goto long_branch; | |
3130 | } | |
3131 | ||
252b5132 | 3132 | /* This could either be a symbol, or an absolute |
151337e8 NC |
3133 | address. If it's an absolute address, turn it into |
3134 | an absolute jump right here and keep it out of the | |
3135 | relaxer. */ | |
3136 | if (adds (&opP->disp) == 0) | |
3137 | { | |
3138 | if (the_ins.opcode[0] == 0x6000) /* jbra */ | |
18566f55 | 3139 | the_ins.opcode[0] = 0x4EF9; |
151337e8 | 3140 | else if (the_ins.opcode[0] == 0x6100) /* jbsr */ |
18566f55 | 3141 | the_ins.opcode[0] = 0x4EB9; |
151337e8 NC |
3142 | else /* jCC */ |
3143 | { | |
3144 | the_ins.opcode[0] ^= 0x0100; | |
3145 | the_ins.opcode[0] |= 0x0006; | |
18566f55 | 3146 | addword (0x4EF9); |
151337e8 NC |
3147 | } |
3148 | add_fix ('l', &opP->disp, 0, 0); | |
3149 | addword (0); | |
3150 | addword (0); | |
3151 | break; | |
3152 | } | |
3153 | ||
3154 | /* Now we know it's going into the relaxer. Now figure | |
3155 | out which mode. We try in this order of preference: | |
3156 | long branch, absolute jump, byte/word branches only. */ | |
9a2e615a | 3157 | if (have_disp) |
bd17c2c3 AM |
3158 | add_frag (adds (&opP->disp), |
3159 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3160 | TAB (BRANCHBWL, SZ_UNDEF)); |
3161 | else if (! flag_keep_pcrel) | |
3162 | { | |
3163 | if ((the_ins.opcode[0] == 0x6000) | |
3164 | || (the_ins.opcode[0] == 0x6100)) | |
bd17c2c3 AM |
3165 | add_frag (adds (&opP->disp), |
3166 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3167 | TAB (BRABSJUNC, SZ_UNDEF)); |
3168 | else | |
bd17c2c3 AM |
3169 | add_frag (adds (&opP->disp), |
3170 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3171 | TAB (BRABSJCOND, SZ_UNDEF)); |
3172 | } | |
252b5132 | 3173 | else |
bd17c2c3 AM |
3174 | add_frag (adds (&opP->disp), |
3175 | SEXT (offs (&opP->disp)), | |
cac27205 NC |
3176 | (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) |
3177 | : TAB (BRANCHBW, SZ_UNDEF))); | |
252b5132 RH |
3178 | break; |
3179 | case 'w': | |
3180 | if (isvar (&opP->disp)) | |
3181 | { | |
151337e8 NC |
3182 | /* Check for DBcc instructions. We can relax them, |
3183 | but only if we have long branches and/or absolute | |
3184 | jumps. */ | |
3185 | if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) | |
3186 | && (HAVE_LONG_BRANCH (current_architecture) | |
9a2e615a | 3187 | || ! flag_keep_pcrel)) |
252b5132 | 3188 | { |
151337e8 | 3189 | if (HAVE_LONG_BRANCH (current_architecture)) |
bd17c2c3 AM |
3190 | add_frag (adds (&opP->disp), |
3191 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3192 | TAB (DBCCLBR, SZ_UNDEF)); |
3193 | else | |
bd17c2c3 AM |
3194 | add_frag (adds (&opP->disp), |
3195 | SEXT (offs (&opP->disp)), | |
151337e8 | 3196 | TAB (DBCCABSJ, SZ_UNDEF)); |
252b5132 RH |
3197 | break; |
3198 | } | |
252b5132 RH |
3199 | add_fix ('w', &opP->disp, 1, 0); |
3200 | } | |
3201 | addword (0); | |
3202 | break; | |
36759679 | 3203 | case 'C': /* Fixed size LONG coproc branches. */ |
252b5132 RH |
3204 | add_fix ('l', &opP->disp, 1, 0); |
3205 | addword (0); | |
3206 | addword (0); | |
3207 | break; | |
36759679 | 3208 | case 'c': /* Var size Coprocesssor branches. */ |
151337e8 | 3209 | if (subs (&opP->disp) || (adds (&opP->disp) == 0)) |
252b5132 | 3210 | { |
252b5132 RH |
3211 | the_ins.opcode[the_ins.numo - 1] |= 0x40; |
3212 | add_fix ('l', &opP->disp, 1, 0); | |
3213 | addword (0); | |
3214 | addword (0); | |
3215 | } | |
151337e8 | 3216 | else |
bd17c2c3 AM |
3217 | add_frag (adds (&opP->disp), |
3218 | SEXT (offs (&opP->disp)), | |
151337e8 | 3219 | TAB (FBRANCH, SZ_UNDEF)); |
252b5132 RH |
3220 | break; |
3221 | default: | |
3222 | abort (); | |
3223 | } | |
3224 | break; | |
3225 | ||
36759679 | 3226 | case 'C': /* Ignore it. */ |
252b5132 RH |
3227 | break; |
3228 | ||
36759679 | 3229 | case 'd': /* JF this is a kludge. */ |
252b5132 | 3230 | install_operand ('s', opP->reg - ADDR); |
3e602632 | 3231 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3232 | if (!issword (tmpreg)) |
3233 | { | |
3234 | as_warn (_("Expression out of range, using 0")); | |
3235 | tmpreg = 0; | |
3236 | } | |
3237 | addword (tmpreg); | |
3238 | break; | |
3239 | ||
3240 | case 'D': | |
3241 | install_operand (s[1], opP->reg - DATA); | |
3242 | break; | |
3243 | ||
fd99574b NC |
3244 | case 'e': /* EMAC ACCx, reg/reg. */ |
3245 | install_operand (s[1], opP->reg - ACC); | |
3246 | break; | |
3247 | ||
36759679 | 3248 | case 'E': /* Ignore it. */ |
6da466c7 ILT |
3249 | break; |
3250 | ||
252b5132 RH |
3251 | case 'F': |
3252 | install_operand (s[1], opP->reg - FP0); | |
3253 | break; | |
3254 | ||
fd99574b NC |
3255 | case 'g': /* EMAC ACCEXTx. */ |
3256 | install_operand (s[1], opP->reg - ACCEXT01); | |
3257 | break; | |
3258 | ||
36759679 | 3259 | case 'G': /* Ignore it. */ |
6da466c7 ILT |
3260 | case 'H': |
3261 | break; | |
3262 | ||
252b5132 RH |
3263 | case 'I': |
3264 | tmpreg = opP->reg - COP0; | |
3265 | install_operand (s[1], tmpreg); | |
3266 | break; | |
3267 | ||
fd99574b NC |
3268 | case 'i': /* MAC/EMAC scale factor. */ |
3269 | install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); | |
3270 | break; | |
3271 | ||
36759679 | 3272 | case 'J': /* JF foo. */ |
252b5132 RH |
3273 | switch (opP->reg) |
3274 | { | |
3275 | case SFC: | |
3276 | tmpreg = 0x000; | |
3277 | break; | |
3278 | case DFC: | |
3279 | tmpreg = 0x001; | |
3280 | break; | |
3281 | case CACR: | |
3282 | tmpreg = 0x002; | |
3283 | break; | |
3284 | case TC: | |
a8e24a56 | 3285 | case ASID: |
252b5132 RH |
3286 | tmpreg = 0x003; |
3287 | break; | |
3e602632 | 3288 | case ACR0: |
252b5132 RH |
3289 | case ITT0: |
3290 | tmpreg = 0x004; | |
3291 | break; | |
3e602632 | 3292 | case ACR1: |
252b5132 RH |
3293 | case ITT1: |
3294 | tmpreg = 0x005; | |
3295 | break; | |
3e602632 | 3296 | case ACR2: |
252b5132 RH |
3297 | case DTT0: |
3298 | tmpreg = 0x006; | |
3299 | break; | |
3e602632 | 3300 | case ACR3: |
252b5132 RH |
3301 | case DTT1: |
3302 | tmpreg = 0x007; | |
3303 | break; | |
3304 | case BUSCR: | |
a8e24a56 | 3305 | case MMUBAR: |
252b5132 RH |
3306 | tmpreg = 0x008; |
3307 | break; | |
3308 | ||
3309 | case USP: | |
3310 | tmpreg = 0x800; | |
3311 | break; | |
3312 | case VBR: | |
3313 | tmpreg = 0x801; | |
3314 | break; | |
3315 | case CAAR: | |
87298967 | 3316 | case CPUCR: |
252b5132 RH |
3317 | tmpreg = 0x802; |
3318 | break; | |
3319 | case MSP: | |
3320 | tmpreg = 0x803; | |
3321 | break; | |
3322 | case ISP: | |
3323 | tmpreg = 0x804; | |
3324 | break; | |
3325 | case MMUSR: | |
3326 | tmpreg = 0x805; | |
3327 | break; | |
3328 | case URP: | |
3329 | tmpreg = 0x806; | |
3330 | break; | |
3331 | case SRP: | |
3332 | tmpreg = 0x807; | |
3333 | break; | |
3334 | case PCR: | |
3335 | tmpreg = 0x808; | |
3336 | break; | |
3337 | case ROMBAR: | |
a8e24a56 | 3338 | case ROMBAR0: |
252b5132 RH |
3339 | tmpreg = 0xC00; |
3340 | break; | |
3e602632 NC |
3341 | case ROMBAR1: |
3342 | tmpreg = 0xC01; | |
3343 | break; | |
3344 | case FLASHBAR: | |
252b5132 | 3345 | case RAMBAR0: |
78336706 | 3346 | case RAMBAR_ALT: |
252b5132 RH |
3347 | tmpreg = 0xC04; |
3348 | break; | |
3e602632 | 3349 | case RAMBAR: |
252b5132 RH |
3350 | case RAMBAR1: |
3351 | tmpreg = 0xC05; | |
3352 | break; | |
3e602632 NC |
3353 | case MPCR: |
3354 | tmpreg = 0xC0C; | |
3355 | break; | |
3356 | case EDRAMBAR: | |
3357 | tmpreg = 0xC0D; | |
3358 | break; | |
3359 | case MBAR0: | |
e80e0390 | 3360 | case MBAR2: |
3e602632 NC |
3361 | case SECMBAR: |
3362 | tmpreg = 0xC0E; | |
3363 | break; | |
3364 | case MBAR1: | |
252b5132 RH |
3365 | case MBAR: |
3366 | tmpreg = 0xC0F; | |
3367 | break; | |
3e602632 NC |
3368 | case PCR1U0: |
3369 | tmpreg = 0xD02; | |
3370 | break; | |
3371 | case PCR1L0: | |
3372 | tmpreg = 0xD03; | |
3373 | break; | |
3374 | case PCR2U0: | |
3375 | tmpreg = 0xD04; | |
3376 | break; | |
3377 | case PCR2L0: | |
3378 | tmpreg = 0xD05; | |
3379 | break; | |
3380 | case PCR3U0: | |
3381 | tmpreg = 0xD06; | |
3382 | break; | |
3383 | case PCR3L0: | |
3384 | tmpreg = 0xD07; | |
3385 | break; | |
3386 | case PCR1L1: | |
3387 | tmpreg = 0xD0A; | |
3388 | break; | |
3389 | case PCR1U1: | |
3390 | tmpreg = 0xD0B; | |
3391 | break; | |
3392 | case PCR2L1: | |
3393 | tmpreg = 0xD0C; | |
3394 | break; | |
3395 | case PCR2U1: | |
3396 | tmpreg = 0xD0D; | |
3397 | break; | |
3398 | case PCR3L1: | |
3399 | tmpreg = 0xD0E; | |
3400 | break; | |
3401 | case PCR3U1: | |
3402 | tmpreg = 0xD0F; | |
3403 | break; | |
f7ec513b KH |
3404 | case CAC: |
3405 | tmpreg = 0xFFE; | |
3406 | break; | |
d0fa1372 | 3407 | case MBO: |
f7ec513b KH |
3408 | tmpreg = 0xFFF; |
3409 | break; | |
252b5132 RH |
3410 | default: |
3411 | abort (); | |
3412 | } | |
3413 | install_operand (s[1], tmpreg); | |
3414 | break; | |
3415 | ||
3416 | case 'k': | |
3417 | tmpreg = get_num (&opP->disp, 55); | |
3418 | install_operand (s[1], tmpreg & 0x7f); | |
3419 | break; | |
3420 | ||
3421 | case 'l': | |
3422 | tmpreg = opP->mask; | |
3423 | if (s[1] == 'w') | |
3424 | { | |
3425 | if (tmpreg & 0x7FF0000) | |
3426 | as_bad (_("Floating point register in register list")); | |
3427 | insop (reverse_16_bits (tmpreg), opcode); | |
3428 | } | |
3429 | else | |
3430 | { | |
3431 | if (tmpreg & 0x700FFFF) | |
3432 | as_bad (_("Wrong register in floating-point reglist")); | |
3433 | install_operand (s[1], reverse_8_bits (tmpreg >> 16)); | |
3434 | } | |
3435 | break; | |
3436 | ||
3437 | case 'L': | |
3438 | tmpreg = opP->mask; | |
3439 | if (s[1] == 'w') | |
3440 | { | |
3441 | if (tmpreg & 0x7FF0000) | |
3442 | as_bad (_("Floating point register in register list")); | |
3443 | insop (tmpreg, opcode); | |
3444 | } | |
3445 | else if (s[1] == '8') | |
3446 | { | |
3447 | if (tmpreg & 0x0FFFFFF) | |
3448 | as_bad (_("incorrect register in reglist")); | |
3449 | install_operand (s[1], tmpreg >> 24); | |
3450 | } | |
3451 | else | |
3452 | { | |
3453 | if (tmpreg & 0x700FFFF) | |
3454 | as_bad (_("wrong register in floating-point reglist")); | |
3455 | else | |
3456 | install_operand (s[1], tmpreg >> 16); | |
3457 | } | |
3458 | break; | |
3459 | ||
3460 | case 'M': | |
3461 | install_operand (s[1], get_num (&opP->disp, 60)); | |
3462 | break; | |
3463 | ||
3464 | case 'O': | |
3465 | tmpreg = ((opP->mode == DREG) | |
8fce3f5e | 3466 | ? 0x20 + (int) (opP->reg - DATA) |
252b5132 RH |
3467 | : (get_num (&opP->disp, 40) & 0x1F)); |
3468 | install_operand (s[1], tmpreg); | |
3469 | break; | |
3470 | ||
3471 | case 'Q': | |
3472 | tmpreg = get_num (&opP->disp, 10); | |
3473 | if (tmpreg == 8) | |
3474 | tmpreg = 0; | |
3475 | install_operand (s[1], tmpreg); | |
3476 | break; | |
3477 | ||
3478 | case 'R': | |
3479 | /* This depends on the fact that ADDR registers are eight | |
3480 | more than their corresponding DATA regs, so the result | |
36759679 | 3481 | will have the ADDR_REG bit set. */ |
252b5132 RH |
3482 | install_operand (s[1], opP->reg - DATA); |
3483 | break; | |
3484 | ||
3485 | case 'r': | |
3486 | if (opP->mode == AINDR) | |
3487 | install_operand (s[1], opP->reg - DATA); | |
3488 | else | |
3489 | install_operand (s[1], opP->index.reg - DATA); | |
3490 | break; | |
3491 | ||
3492 | case 's': | |
3493 | if (opP->reg == FPI) | |
3494 | tmpreg = 0x1; | |
3495 | else if (opP->reg == FPS) | |
3496 | tmpreg = 0x2; | |
3497 | else if (opP->reg == FPC) | |
3498 | tmpreg = 0x4; | |
3499 | else | |
3500 | abort (); | |
3501 | install_operand (s[1], tmpreg); | |
3502 | break; | |
3503 | ||
36759679 | 3504 | case 'S': /* Ignore it. */ |
252b5132 RH |
3505 | break; |
3506 | ||
3507 | case 'T': | |
3508 | install_operand (s[1], get_num (&opP->disp, 30)); | |
3509 | break; | |
3510 | ||
36759679 | 3511 | case 'U': /* Ignore it. */ |
252b5132 RH |
3512 | break; |
3513 | ||
3514 | case 'c': | |
3515 | switch (opP->reg) | |
3516 | { | |
3517 | case NC: | |
3518 | tmpreg = 0; | |
3519 | break; | |
3520 | case DC: | |
3521 | tmpreg = 1; | |
3522 | break; | |
3523 | case IC: | |
3524 | tmpreg = 2; | |
3525 | break; | |
3526 | case BC: | |
3527 | tmpreg = 3; | |
3528 | break; | |
3529 | default: | |
3530 | as_fatal (_("failed sanity check")); | |
36759679 | 3531 | } /* switch on cache token. */ |
252b5132 RH |
3532 | install_operand (s[1], tmpreg); |
3533 | break; | |
3534 | #ifndef NO_68851 | |
92774660 | 3535 | /* JF: These are out of order, I fear. */ |
252b5132 RH |
3536 | case 'f': |
3537 | switch (opP->reg) | |
3538 | { | |
3539 | case SFC: | |
3540 | tmpreg = 0; | |
3541 | break; | |
3542 | case DFC: | |
3543 | tmpreg = 1; | |
3544 | break; | |
3545 | default: | |
3546 | abort (); | |
3547 | } | |
3548 | install_operand (s[1], tmpreg); | |
3549 | break; | |
3550 | ||
3551 | case '0': | |
3552 | case '1': | |
3553 | case '2': | |
3554 | switch (opP->reg) | |
3555 | { | |
3556 | case TC: | |
3557 | tmpreg = 0; | |
3558 | break; | |
3559 | case CAL: | |
3560 | tmpreg = 4; | |
3561 | break; | |
3562 | case VAL: | |
3563 | tmpreg = 5; | |
3564 | break; | |
3565 | case SCC: | |
3566 | tmpreg = 6; | |
3567 | break; | |
3568 | case AC: | |
3569 | tmpreg = 7; | |
3570 | break; | |
3571 | default: | |
3572 | abort (); | |
3573 | } | |
3574 | install_operand (s[1], tmpreg); | |
3575 | break; | |
3576 | ||
3577 | case 'V': | |
3578 | if (opP->reg == VAL) | |
3579 | break; | |
3580 | abort (); | |
3581 | ||
3582 | case 'W': | |
3583 | switch (opP->reg) | |
3584 | { | |
3585 | case DRP: | |
3586 | tmpreg = 1; | |
3587 | break; | |
3588 | case SRP: | |
3589 | tmpreg = 2; | |
3590 | break; | |
3591 | case CRP: | |
3592 | tmpreg = 3; | |
3593 | break; | |
3594 | default: | |
3595 | abort (); | |
3596 | } | |
3597 | install_operand (s[1], tmpreg); | |
3598 | break; | |
3599 | ||
3600 | case 'X': | |
3601 | switch (opP->reg) | |
3602 | { | |
3603 | case BAD: | |
3604 | case BAD + 1: | |
3605 | case BAD + 2: | |
3606 | case BAD + 3: | |
3607 | case BAD + 4: | |
3608 | case BAD + 5: | |
3609 | case BAD + 6: | |
3610 | case BAD + 7: | |
3611 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
3612 | break; | |
3613 | ||
3614 | case BAC: | |
3615 | case BAC + 1: | |
3616 | case BAC + 2: | |
3617 | case BAC + 3: | |
3618 | case BAC + 4: | |
3619 | case BAC + 5: | |
3620 | case BAC + 6: | |
3621 | case BAC + 7: | |
3622 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
3623 | break; | |
3624 | ||
3625 | default: | |
3626 | abort (); | |
3627 | } | |
3628 | install_operand (s[1], tmpreg); | |
3629 | break; | |
3630 | case 'Y': | |
3631 | know (opP->reg == PSR); | |
3632 | break; | |
3633 | case 'Z': | |
3634 | know (opP->reg == PCSR); | |
3635 | break; | |
3636 | #endif /* m68851 */ | |
3637 | case '3': | |
3638 | switch (opP->reg) | |
3639 | { | |
3640 | case TT0: | |
3641 | tmpreg = 2; | |
3642 | break; | |
3643 | case TT1: | |
3644 | tmpreg = 3; | |
3645 | break; | |
3646 | default: | |
3647 | abort (); | |
3648 | } | |
3649 | install_operand (s[1], tmpreg); | |
3650 | break; | |
3651 | case 't': | |
3652 | tmpreg = get_num (&opP->disp, 20); | |
3653 | install_operand (s[1], tmpreg); | |
3654 | break; | |
36759679 | 3655 | case '_': /* used only for move16 absolute 32-bit address. */ |
252b5132 RH |
3656 | if (isvar (&opP->disp)) |
3657 | add_fix ('l', &opP->disp, 0, 0); | |
3e602632 | 3658 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3659 | addword (tmpreg >> 16); |
3660 | addword (tmpreg & 0xFFFF); | |
3661 | break; | |
6da466c7 ILT |
3662 | case 'u': |
3663 | install_operand (s[1], opP->reg - DATA0L); | |
3664 | opP->reg -= (DATA0L); | |
36759679 | 3665 | opP->reg &= 0x0F; /* remove upper/lower bit. */ |
6da466c7 | 3666 | break; |
3e602632 NC |
3667 | case 'x': |
3668 | tmpreg = get_num (&opP->disp, 80); | |
3669 | if (tmpreg == -1) | |
3670 | tmpreg = 0; | |
3671 | install_operand (s[1], tmpreg); | |
3672 | break; | |
afa2158f NS |
3673 | case 'j': |
3674 | tmpreg = get_num (&opP->disp, 10); | |
3675 | install_operand (s[1], tmpreg - 1); | |
3676 | break; | |
3677 | case 'K': | |
3678 | tmpreg = get_num (&opP->disp, 65); | |
3679 | install_operand (s[1], tmpreg); | |
3680 | break; | |
252b5132 RH |
3681 | default: |
3682 | abort (); | |
3683 | } | |
3684 | } | |
3685 | ||
3686 | /* By the time whe get here (FINALLY) the_ins contains the complete | |
92774660 | 3687 | instruction, ready to be emitted. . . */ |
252b5132 RH |
3688 | } |
3689 | ||
3690 | static int | |
31302357 | 3691 | reverse_16_bits (int in) |
252b5132 RH |
3692 | { |
3693 | int out = 0; | |
3694 | int n; | |
3695 | ||
3696 | static int mask[16] = | |
3697 | { | |
3698 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3699 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 | |
3700 | }; | |
3701 | for (n = 0; n < 16; n++) | |
3702 | { | |
3703 | if (in & mask[n]) | |
3704 | out |= mask[15 - n]; | |
3705 | } | |
3706 | return out; | |
3707 | } /* reverse_16_bits() */ | |
3708 | ||
3709 | static int | |
31302357 | 3710 | reverse_8_bits (int in) |
252b5132 RH |
3711 | { |
3712 | int out = 0; | |
3713 | int n; | |
3714 | ||
3715 | static int mask[8] = | |
3716 | { | |
3717 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3718 | }; | |
3719 | ||
3720 | for (n = 0; n < 8; n++) | |
3721 | { | |
3722 | if (in & mask[n]) | |
3723 | out |= mask[7 - n]; | |
3724 | } | |
3725 | return out; | |
3726 | } /* reverse_8_bits() */ | |
3727 | ||
cac27205 NC |
3728 | /* Cause an extra frag to be generated here, inserting up to |
3729 | FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be | |
3730 | generated; its primary type is rs_machine_dependent. | |
252b5132 RH |
3731 | |
3732 | The TYPE parameter is also used by md_convert_frag_1 and | |
3733 | md_estimate_size_before_relax. The appropriate type of fixup will | |
3734 | be emitted by md_convert_frag_1. | |
3735 | ||
3736 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
3737 | static void | |
31302357 | 3738 | install_operand (int mode, int val) |
252b5132 RH |
3739 | { |
3740 | switch (mode) | |
3741 | { | |
3742 | case 's': | |
36759679 | 3743 | the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ |
252b5132 RH |
3744 | break; |
3745 | case 'd': | |
3746 | the_ins.opcode[0] |= val << 9; | |
3747 | break; | |
afa2158f NS |
3748 | case 'E': |
3749 | the_ins.opcode[1] |= val << 9; | |
3750 | break; | |
252b5132 RH |
3751 | case '1': |
3752 | the_ins.opcode[1] |= val << 12; | |
3753 | break; | |
3754 | case '2': | |
3755 | the_ins.opcode[1] |= val << 6; | |
3756 | break; | |
3757 | case '3': | |
3758 | the_ins.opcode[1] |= val; | |
3759 | break; | |
3760 | case '4': | |
3761 | the_ins.opcode[2] |= val << 12; | |
3762 | break; | |
3763 | case '5': | |
3764 | the_ins.opcode[2] |= val << 6; | |
3765 | break; | |
3766 | case '6': | |
3767 | /* DANGER! This is a hack to force cas2l and cas2w cmds to be | |
3768 | three words long! */ | |
3769 | the_ins.numo++; | |
3770 | the_ins.opcode[2] |= val; | |
3771 | break; | |
3772 | case '7': | |
3773 | the_ins.opcode[1] |= val << 7; | |
3774 | break; | |
3775 | case '8': | |
3776 | the_ins.opcode[1] |= val << 10; | |
3777 | break; | |
3778 | #ifndef NO_68851 | |
3779 | case '9': | |
3780 | the_ins.opcode[1] |= val << 5; | |
3781 | break; | |
3782 | #endif | |
3783 | ||
3784 | case 't': | |
3785 | the_ins.opcode[1] |= (val << 10) | (val << 7); | |
3786 | break; | |
3787 | case 'D': | |
3788 | the_ins.opcode[1] |= (val << 12) | val; | |
3789 | break; | |
3790 | case 'g': | |
3791 | the_ins.opcode[0] |= val = 0xff; | |
3792 | break; | |
3793 | case 'i': | |
3794 | the_ins.opcode[0] |= val << 9; | |
3795 | break; | |
3796 | case 'C': | |
3797 | the_ins.opcode[1] |= val; | |
3798 | break; | |
3799 | case 'j': | |
3800 | the_ins.opcode[1] |= val; | |
36759679 | 3801 | the_ins.numo++; /* What a hack. */ |
252b5132 RH |
3802 | break; |
3803 | case 'k': | |
3804 | the_ins.opcode[1] |= val << 4; | |
3805 | break; | |
3806 | case 'b': | |
3807 | case 'w': | |
3808 | case 'W': | |
3809 | case 'l': | |
3810 | break; | |
3811 | case 'e': | |
3812 | the_ins.opcode[0] |= (val << 6); | |
3813 | break; | |
3814 | case 'L': | |
3815 | the_ins.opcode[1] = (val >> 16); | |
3816 | the_ins.opcode[2] = val & 0xffff; | |
3817 | break; | |
6da466c7 ILT |
3818 | case 'm': |
3819 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); | |
3820 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
3821 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3822 | break; | |
fd99574b | 3823 | case 'n': /* MAC/EMAC Rx on !load. */ |
6da466c7 ILT |
3824 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); |
3825 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
fd99574b | 3826 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); |
6da466c7 | 3827 | break; |
fd99574b | 3828 | case 'o': /* MAC/EMAC Rx on load. */ |
6da466c7 ILT |
3829 | the_ins.opcode[1] |= val << 12; |
3830 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3831 | break; | |
fd99574b | 3832 | case 'M': /* MAC/EMAC Ry on !load. */ |
6da466c7 ILT |
3833 | the_ins.opcode[0] |= (val & 0xF); |
3834 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3835 | break; | |
fd99574b | 3836 | case 'N': /* MAC/EMAC Ry on load. */ |
6da466c7 ILT |
3837 | the_ins.opcode[1] |= (val & 0xF); |
3838 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3839 | break; | |
3840 | case 'h': | |
3841 | the_ins.opcode[1] |= ((val != 1) << 10); | |
3842 | break; | |
fd99574b NC |
3843 | case 'F': |
3844 | the_ins.opcode[0] |= ((val & 0x3) << 9); | |
3845 | break; | |
3846 | case 'f': | |
3847 | the_ins.opcode[0] |= ((val & 0x3) << 0); | |
3848 | break; | |
be8c092b | 3849 | case 'G': /* EMAC accumulator in a EMAC load instruction. */ |
fd99574b NC |
3850 | the_ins.opcode[0] |= ((~val & 0x1) << 7); |
3851 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3852 | break; | |
be8c092b | 3853 | case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ |
fd99574b NC |
3854 | the_ins.opcode[0] |= ((val & 0x1) << 7); |
3855 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3856 | break; | |
3857 | case 'I': | |
3858 | the_ins.opcode[1] |= ((val & 0x3) << 9); | |
3859 | break; | |
3860 | case ']': | |
3861 | the_ins.opcode[0] |= (val & 0x1) <<10; | |
3862 | break; | |
252b5132 RH |
3863 | case 'c': |
3864 | default: | |
3865 | as_fatal (_("failed sanity check.")); | |
3866 | } | |
6b6e92f4 | 3867 | } |
252b5132 RH |
3868 | |
3869 | static void | |
31302357 | 3870 | install_gen_operand (int mode, int val) |
252b5132 RH |
3871 | { |
3872 | switch (mode) | |
3873 | { | |
fd99574b NC |
3874 | case '/': /* Special for mask loads for mac/msac insns with |
3875 | possible mask; trailing_ampersend set in bit 8. */ | |
3876 | the_ins.opcode[0] |= (val & 0x3f); | |
3877 | the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); | |
3878 | break; | |
252b5132 RH |
3879 | case 's': |
3880 | the_ins.opcode[0] |= val; | |
3881 | break; | |
3882 | case 'd': | |
3883 | /* This is a kludge!!! */ | |
3884 | the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; | |
3885 | break; | |
3886 | case 'b': | |
3887 | case 'w': | |
3888 | case 'l': | |
3889 | case 'f': | |
3890 | case 'F': | |
3891 | case 'x': | |
3892 | case 'p': | |
3893 | the_ins.opcode[0] |= val; | |
3894 | break; | |
36759679 | 3895 | /* more stuff goes here. */ |
252b5132 RH |
3896 | default: |
3897 | as_fatal (_("failed sanity check.")); | |
3898 | } | |
6b6e92f4 | 3899 | } |
252b5132 | 3900 | |
6b6e92f4 NC |
3901 | /* Verify that we have some number of paren pairs, do m68k_ip_op(), and |
3902 | then deal with the bitfield hack. */ | |
252b5132 RH |
3903 | |
3904 | static char * | |
31302357 | 3905 | crack_operand (char *str, struct m68k_op *opP) |
252b5132 RH |
3906 | { |
3907 | register int parens; | |
3908 | register int c; | |
3909 | register char *beg_str; | |
3910 | int inquote = 0; | |
3911 | ||
3912 | if (!str) | |
3913 | { | |
3914 | return str; | |
3915 | } | |
3916 | beg_str = str; | |
3917 | for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) | |
3918 | { | |
3919 | if (! inquote) | |
3920 | { | |
3921 | if (*str == '(') | |
3922 | parens++; | |
3923 | else if (*str == ')') | |
3924 | { | |
3925 | if (!parens) | |
36759679 | 3926 | { /* ERROR. */ |
252b5132 RH |
3927 | opP->error = _("Extra )"); |
3928 | return str; | |
3929 | } | |
3930 | --parens; | |
3931 | } | |
3932 | } | |
3933 | if (flag_mri && *str == '\'') | |
3934 | inquote = ! inquote; | |
3935 | } | |
3936 | if (!*str && parens) | |
36759679 | 3937 | { /* ERROR. */ |
252b5132 RH |
3938 | opP->error = _("Missing )"); |
3939 | return str; | |
3940 | } | |
3941 | c = *str; | |
3942 | *str = '\0'; | |
3943 | if (m68k_ip_op (beg_str, opP) != 0) | |
3944 | { | |
3945 | *str = c; | |
3946 | return str; | |
3947 | } | |
3948 | *str = c; | |
3949 | if (c == '}') | |
36759679 | 3950 | c = *++str; /* JF bitfield hack. */ |
252b5132 RH |
3951 | if (c) |
3952 | { | |
3953 | c = *++str; | |
3954 | if (!c) | |
3955 | as_bad (_("Missing operand")); | |
3956 | } | |
3957 | ||
3958 | /* Detect MRI REG symbols and convert them to REGLSTs. */ | |
3959 | if (opP->mode == CONTROL && (int)opP->reg < 0) | |
3960 | { | |
3961 | opP->mode = REGLST; | |
3962 | opP->mask = ~(int)opP->reg; | |
3963 | opP->reg = 0; | |
3964 | } | |
3965 | ||
3966 | return str; | |
3967 | } | |
3968 | ||
3969 | /* This is the guts of the machine-dependent assembler. STR points to a | |
3970 | machine dependent instruction. This function is supposed to emit | |
3971 | the frags/bytes it assembles to. | |
3972 | */ | |
3973 | ||
3974 | static void | |
31302357 | 3975 | insert_reg (const char *regname, int regnum) |
252b5132 RH |
3976 | { |
3977 | char buf[100]; | |
3978 | int i; | |
3979 | ||
3980 | #ifdef REGISTER_PREFIX | |
3981 | if (!flag_reg_prefix_optional) | |
3982 | { | |
3983 | buf[0] = REGISTER_PREFIX; | |
3984 | strcpy (buf + 1, regname); | |
3985 | regname = buf; | |
3986 | } | |
3987 | #endif | |
3988 | ||
3989 | symbol_table_insert (symbol_new (regname, reg_section, regnum, | |
3990 | &zero_address_frag)); | |
3991 | ||
3992 | for (i = 0; regname[i]; i++) | |
3882b010 | 3993 | buf[i] = TOUPPER (regname[i]); |
252b5132 RH |
3994 | buf[i] = '\0'; |
3995 | ||
3996 | symbol_table_insert (symbol_new (buf, reg_section, regnum, | |
3997 | &zero_address_frag)); | |
3998 | } | |
3999 | ||
4000 | struct init_entry | |
4001 | { | |
4002 | const char *name; | |
4003 | int number; | |
4004 | }; | |
4005 | ||
4006 | static const struct init_entry init_table[] = | |
4007 | { | |
4008 | { "d0", DATA0 }, | |
4009 | { "d1", DATA1 }, | |
4010 | { "d2", DATA2 }, | |
4011 | { "d3", DATA3 }, | |
4012 | { "d4", DATA4 }, | |
4013 | { "d5", DATA5 }, | |
4014 | { "d6", DATA6 }, | |
4015 | { "d7", DATA7 }, | |
4016 | { "a0", ADDR0 }, | |
4017 | { "a1", ADDR1 }, | |
4018 | { "a2", ADDR2 }, | |
4019 | { "a3", ADDR3 }, | |
4020 | { "a4", ADDR4 }, | |
4021 | { "a5", ADDR5 }, | |
4022 | { "a6", ADDR6 }, | |
4023 | { "fp", ADDR6 }, | |
4024 | { "a7", ADDR7 }, | |
4025 | { "sp", ADDR7 }, | |
4026 | { "ssp", ADDR7 }, | |
4027 | { "fp0", FP0 }, | |
4028 | { "fp1", FP1 }, | |
4029 | { "fp2", FP2 }, | |
4030 | { "fp3", FP3 }, | |
4031 | { "fp4", FP4 }, | |
4032 | { "fp5", FP5 }, | |
4033 | { "fp6", FP6 }, | |
4034 | { "fp7", FP7 }, | |
4035 | { "fpi", FPI }, | |
4036 | { "fpiar", FPI }, | |
4037 | { "fpc", FPI }, | |
4038 | { "fps", FPS }, | |
4039 | { "fpsr", FPS }, | |
4040 | { "fpc", FPC }, | |
4041 | { "fpcr", FPC }, | |
4042 | { "control", FPC }, | |
4043 | { "status", FPS }, | |
4044 | { "iaddr", FPI }, | |
4045 | ||
4046 | { "cop0", COP0 }, | |
4047 | { "cop1", COP1 }, | |
4048 | { "cop2", COP2 }, | |
4049 | { "cop3", COP3 }, | |
4050 | { "cop4", COP4 }, | |
4051 | { "cop5", COP5 }, | |
4052 | { "cop6", COP6 }, | |
4053 | { "cop7", COP7 }, | |
4054 | { "pc", PC }, | |
4055 | { "zpc", ZPC }, | |
4056 | { "sr", SR }, | |
4057 | ||
4058 | { "ccr", CCR }, | |
4059 | { "cc", CCR }, | |
4060 | ||
6da466c7 | 4061 | { "acc", ACC }, |
fd99574b NC |
4062 | { "acc0", ACC }, |
4063 | { "acc1", ACC1 }, | |
4064 | { "acc2", ACC2 }, | |
4065 | { "acc3", ACC3 }, | |
4066 | { "accext01", ACCEXT01 }, | |
4067 | { "accext23", ACCEXT23 }, | |
6da466c7 ILT |
4068 | { "macsr", MACSR }, |
4069 | { "mask", MASK }, | |
4070 | ||
36759679 NC |
4071 | /* Control registers. */ |
4072 | { "sfc", SFC }, /* Source Function Code. */ | |
252b5132 | 4073 | { "sfcr", SFC }, |
36759679 | 4074 | { "dfc", DFC }, /* Destination Function Code. */ |
252b5132 | 4075 | { "dfcr", DFC }, |
36759679 NC |
4076 | { "cacr", CACR }, /* Cache Control Register. */ |
4077 | { "caar", CAAR }, /* Cache Address Register. */ | |
87298967 | 4078 | { "cpucr", CPUCR }, /* CPU Control Register. */ |
252b5132 | 4079 | |
36759679 NC |
4080 | { "usp", USP }, /* User Stack Pointer. */ |
4081 | { "vbr", VBR }, /* Vector Base Register. */ | |
4082 | { "msp", MSP }, /* Master Stack Pointer. */ | |
4083 | { "isp", ISP }, /* Interrupt Stack Pointer. */ | |
252b5132 | 4084 | |
36759679 NC |
4085 | { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ |
4086 | { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ | |
4087 | { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ | |
4088 | { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ | |
252b5132 RH |
4089 | |
4090 | /* 68ec040 versions of same */ | |
36759679 NC |
4091 | { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ |
4092 | { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ | |
4093 | { "dacr0", DTT0 }, /* Data Access Control Register 0. */ | |
4094 | { "dacr1", DTT1 }, /* Data Access Control Register 0. */ | |
252b5132 | 4095 | |
a8e24a56 | 4096 | /* Coldfire versions of same. The ColdFire programmer's reference |
252b5132 RH |
4097 | manual indicated that the order is 2,3,0,1, but Ken Rose |
4098 | <rose@netcom.com> says that 0,1,2,3 is the correct order. */ | |
3e602632 NC |
4099 | { "acr0", ACR0 }, /* Access Control Unit 0. */ |
4100 | { "acr1", ACR1 }, /* Access Control Unit 1. */ | |
4101 | { "acr2", ACR2 }, /* Access Control Unit 2. */ | |
4102 | { "acr3", ACR3 }, /* Access Control Unit 3. */ | |
252b5132 | 4103 | |
36759679 | 4104 | { "tc", TC }, /* MMU Translation Control Register. */ |
252b5132 | 4105 | { "tcr", TC }, |
a8e24a56 | 4106 | { "asid", ASID }, |
252b5132 | 4107 | |
36759679 NC |
4108 | { "mmusr", MMUSR }, /* MMU Status Register. */ |
4109 | { "srp", SRP }, /* User Root Pointer. */ | |
4110 | { "urp", URP }, /* Supervisor Root Pointer. */ | |
252b5132 RH |
4111 | |
4112 | { "buscr", BUSCR }, | |
a8e24a56 | 4113 | { "mmubar", MMUBAR }, |
252b5132 RH |
4114 | { "pcr", PCR }, |
4115 | ||
36759679 NC |
4116 | { "rombar", ROMBAR }, /* ROM Base Address Register. */ |
4117 | { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ | |
4118 | { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ | |
4119 | { "mbar", MBAR }, /* Module Base Address Register. */ | |
3e602632 NC |
4120 | |
4121 | { "mbar0", MBAR0 }, /* mcfv4e registers. */ | |
4122 | { "mbar1", MBAR1 }, /* mcfv4e registers. */ | |
a8e24a56 | 4123 | { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ |
3e602632 NC |
4124 | { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ |
4125 | { "mpcr", MPCR }, /* mcfv4e registers. */ | |
4126 | { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ | |
4127 | { "secmbar", SECMBAR }, /* mcfv4e registers. */ | |
4128 | { "asid", TC }, /* mcfv4e registers. */ | |
4129 | { "mmubar", BUSCR }, /* mcfv4e registers. */ | |
4130 | { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ | |
4131 | { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ | |
4132 | { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ | |
4133 | { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ | |
4134 | { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ | |
4135 | { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ | |
4136 | { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ | |
4137 | { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ | |
4138 | { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ | |
4139 | { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ | |
4140 | { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ | |
4141 | { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ | |
4142 | ||
4143 | { "flashbar", FLASHBAR }, /* mcf528x registers. */ | |
4144 | { "rambar", RAMBAR }, /* mcf528x registers. */ | |
e80e0390 NC |
4145 | |
4146 | { "mbar2", MBAR2 }, /* mcf5249 registers. */ | |
f7ec513b KH |
4147 | |
4148 | { "cac", CAC }, /* fido registers. */ | |
d0fa1372 KH |
4149 | { "mbb", MBO }, /* fido registers (obsolete). */ |
4150 | { "mbo", MBO }, /* fido registers. */ | |
36759679 | 4151 | /* End of control registers. */ |
252b5132 RH |
4152 | |
4153 | { "ac", AC }, | |
4154 | { "bc", BC }, | |
4155 | { "cal", CAL }, | |
4156 | { "crp", CRP }, | |
4157 | { "drp", DRP }, | |
4158 | { "pcsr", PCSR }, | |
4159 | { "psr", PSR }, | |
4160 | { "scc", SCC }, | |
4161 | { "val", VAL }, | |
4162 | { "bad0", BAD0 }, | |
4163 | { "bad1", BAD1 }, | |
4164 | { "bad2", BAD2 }, | |
4165 | { "bad3", BAD3 }, | |
4166 | { "bad4", BAD4 }, | |
4167 | { "bad5", BAD5 }, | |
4168 | { "bad6", BAD6 }, | |
4169 | { "bad7", BAD7 }, | |
4170 | { "bac0", BAC0 }, | |
4171 | { "bac1", BAC1 }, | |
4172 | { "bac2", BAC2 }, | |
4173 | { "bac3", BAC3 }, | |
4174 | { "bac4", BAC4 }, | |
4175 | { "bac5", BAC5 }, | |
4176 | { "bac6", BAC6 }, | |
4177 | { "bac7", BAC7 }, | |
4178 | ||
4179 | { "ic", IC }, | |
4180 | { "dc", DC }, | |
4181 | { "nc", NC }, | |
4182 | ||
4183 | { "tt0", TT0 }, | |
4184 | { "tt1", TT1 }, | |
36759679 | 4185 | /* 68ec030 versions of same. */ |
252b5132 RH |
4186 | { "ac0", TT0 }, |
4187 | { "ac1", TT1 }, | |
36759679 | 4188 | /* 68ec030 access control unit, identical to 030 MMU status reg. */ |
252b5132 RH |
4189 | { "acusr", PSR }, |
4190 | ||
4191 | /* Suppressed data and address registers. */ | |
4192 | { "zd0", ZDATA0 }, | |
4193 | { "zd1", ZDATA1 }, | |
4194 | { "zd2", ZDATA2 }, | |
4195 | { "zd3", ZDATA3 }, | |
4196 | { "zd4", ZDATA4 }, | |
4197 | { "zd5", ZDATA5 }, | |
4198 | { "zd6", ZDATA6 }, | |
4199 | { "zd7", ZDATA7 }, | |
4200 | { "za0", ZADDR0 }, | |
4201 | { "za1", ZADDR1 }, | |
4202 | { "za2", ZADDR2 }, | |
4203 | { "za3", ZADDR3 }, | |
4204 | { "za4", ZADDR4 }, | |
4205 | { "za5", ZADDR5 }, | |
4206 | { "za6", ZADDR6 }, | |
4207 | { "za7", ZADDR7 }, | |
4208 | ||
92774660 | 4209 | /* Upper and lower data and address registers, used by macw and msacw. */ |
6da466c7 ILT |
4210 | { "d0l", DATA0L }, |
4211 | { "d1l", DATA1L }, | |
4212 | { "d2l", DATA2L }, | |
4213 | { "d3l", DATA3L }, | |
4214 | { "d4l", DATA4L }, | |
4215 | { "d5l", DATA5L }, | |
4216 | { "d6l", DATA6L }, | |
4217 | { "d7l", DATA7L }, | |
4218 | ||
4219 | { "a0l", ADDR0L }, | |
4220 | { "a1l", ADDR1L }, | |
4221 | { "a2l", ADDR2L }, | |
4222 | { "a3l", ADDR3L }, | |
4223 | { "a4l", ADDR4L }, | |
4224 | { "a5l", ADDR5L }, | |
4225 | { "a6l", ADDR6L }, | |
4226 | { "a7l", ADDR7L }, | |
4227 | ||
4228 | { "d0u", DATA0U }, | |
4229 | { "d1u", DATA1U }, | |
4230 | { "d2u", DATA2U }, | |
4231 | { "d3u", DATA3U }, | |
4232 | { "d4u", DATA4U }, | |
4233 | { "d5u", DATA5U }, | |
4234 | { "d6u", DATA6U }, | |
4235 | { "d7u", DATA7U }, | |
4236 | ||
4237 | { "a0u", ADDR0U }, | |
4238 | { "a1u", ADDR1U }, | |
4239 | { "a2u", ADDR2U }, | |
4240 | { "a3u", ADDR3U }, | |
4241 | { "a4u", ADDR4U }, | |
4242 | { "a5u", ADDR5U }, | |
4243 | { "a6u", ADDR6U }, | |
4244 | { "a7u", ADDR7U }, | |
4245 | ||
252b5132 RH |
4246 | { 0, 0 } |
4247 | }; | |
4248 | ||
4249 | static void | |
31302357 | 4250 | init_regtable (void) |
252b5132 RH |
4251 | { |
4252 | int i; | |
4253 | for (i = 0; init_table[i].name; i++) | |
4254 | insert_reg (init_table[i].name, init_table[i].number); | |
4255 | } | |
4256 | ||
252b5132 | 4257 | void |
31302357 | 4258 | md_assemble (char *str) |
252b5132 RH |
4259 | { |
4260 | const char *er; | |
4261 | short *fromP; | |
4262 | char *toP = NULL; | |
4263 | int m, n = 0; | |
4264 | char *to_beg_P; | |
4265 | int shorts_this_frag; | |
4266 | fixS *fixP; | |
4267 | ||
266abb8f NS |
4268 | if (!selected_cpu && !selected_arch) |
4269 | { | |
4270 | /* We've not selected an architecture yet. Set the default | |
4271 | now. We do this lazily so that an initial .cpu or .arch directive | |
4272 | can specify. */ | |
4273 | if (!m68k_set_cpu (TARGET_CPU, 1, 1)) | |
4274 | as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); | |
4275 | } | |
4276 | if (!initialized) | |
4277 | m68k_init_arch (); | |
4278 | ||
252b5132 RH |
4279 | /* In MRI mode, the instruction and operands are separated by a |
4280 | space. Anything following the operands is a comment. The label | |
4281 | has already been removed. */ | |
4282 | if (flag_mri) | |
4283 | { | |
4284 | char *s; | |
4285 | int fields = 0; | |
4286 | int infield = 0; | |
4287 | int inquote = 0; | |
4288 | ||
4289 | for (s = str; *s != '\0'; s++) | |
4290 | { | |
4291 | if ((*s == ' ' || *s == '\t') && ! inquote) | |
4292 | { | |
4293 | if (infield) | |
4294 | { | |
4295 | ++fields; | |
4296 | if (fields >= 2) | |
4297 | { | |
4298 | *s = '\0'; | |
4299 | break; | |
4300 | } | |
4301 | infield = 0; | |
4302 | } | |
4303 | } | |
4304 | else | |
4305 | { | |
4306 | if (! infield) | |
4307 | infield = 1; | |
4308 | if (*s == '\'') | |
4309 | inquote = ! inquote; | |
4310 | } | |
4311 | } | |
4312 | } | |
4313 | ||
31302357 | 4314 | memset (&the_ins, '\0', sizeof (the_ins)); |
252b5132 RH |
4315 | m68k_ip (str); |
4316 | er = the_ins.error; | |
4317 | if (!er) | |
4318 | { | |
4319 | for (n = 0; n < the_ins.numargs; n++) | |
4320 | if (the_ins.operands[n].error) | |
4321 | { | |
4322 | er = the_ins.operands[n].error; | |
4323 | break; | |
4324 | } | |
4325 | } | |
4326 | if (er) | |
4327 | { | |
4328 | as_bad (_("%s -- statement `%s' ignored"), er, str); | |
4329 | return; | |
4330 | } | |
4331 | ||
4332 | /* If there is a current label, record that it marks an instruction. */ | |
4333 | if (current_label != NULL) | |
4334 | { | |
4335 | current_label->text = 1; | |
4336 | current_label = NULL; | |
4337 | } | |
4338 | ||
f27a3839 AS |
4339 | #ifdef OBJ_ELF |
4340 | /* Tie dwarf2 debug info to the address at the start of the insn. */ | |
4341 | dwarf2_emit_insn (0); | |
4342 | #endif | |
4343 | ||
252b5132 RH |
4344 | if (the_ins.nfrag == 0) |
4345 | { | |
36759679 | 4346 | /* No frag hacking involved; just put it out. */ |
252b5132 RH |
4347 | toP = frag_more (2 * the_ins.numo); |
4348 | fromP = &the_ins.opcode[0]; | |
4349 | for (m = the_ins.numo; m; --m) | |
4350 | { | |
4351 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4352 | toP += 2; | |
4353 | fromP++; | |
4354 | } | |
36759679 | 4355 | /* Put out symbol-dependent info. */ |
252b5132 RH |
4356 | for (m = 0; m < the_ins.nrel; m++) |
4357 | { | |
4358 | switch (the_ins.reloc[m].wid) | |
4359 | { | |
4360 | case 'B': | |
4361 | n = 1; | |
4362 | break; | |
4363 | case 'b': | |
4364 | n = 1; | |
4365 | break; | |
4366 | case '3': | |
4367 | n = 1; | |
4368 | break; | |
4369 | case 'w': | |
4370 | case 'W': | |
4371 | n = 2; | |
4372 | break; | |
4373 | case 'l': | |
4374 | n = 4; | |
4375 | break; | |
4376 | default: | |
4377 | as_fatal (_("Don't know how to figure width of %c in md_assemble()"), | |
4378 | the_ins.reloc[m].wid); | |
4379 | } | |
4380 | ||
4381 | fixP = fix_new_exp (frag_now, | |
4382 | ((toP - frag_now->fr_literal) | |
4383 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4384 | n, | |
4385 | &the_ins.reloc[m].exp, | |
4386 | the_ins.reloc[m].pcrel, | |
4387 | get_reloc_code (n, the_ins.reloc[m].pcrel, | |
4388 | the_ins.reloc[m].pic_reloc)); | |
4389 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4390 | if (the_ins.reloc[m].wid == 'B') | |
4391 | fixP->fx_signed = 1; | |
4392 | } | |
4393 | return; | |
4394 | } | |
4395 | ||
36759679 | 4396 | /* There's some frag hacking. */ |
fbe572f9 AM |
4397 | { |
4398 | /* Calculate the max frag size. */ | |
4399 | int wid; | |
4400 | ||
4401 | wid = 2 * the_ins.fragb[0].fragoff; | |
4402 | for (n = 1; n < the_ins.nfrag; n++) | |
4403 | wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4404 | /* frag_var part. */ | |
cac27205 | 4405 | wid += FRAG_VAR_SIZE; |
fbe572f9 AM |
4406 | /* Make sure the whole insn fits in one chunk, in particular that |
4407 | the var part is attached, as we access one byte before the | |
4408 | variable frag for byte branches. */ | |
4409 | frag_grow (wid); | |
4410 | } | |
4411 | ||
252b5132 RH |
4412 | for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) |
4413 | { | |
4414 | int wid; | |
4415 | ||
4416 | if (n == 0) | |
4417 | wid = 2 * the_ins.fragb[n].fragoff; | |
4418 | else | |
4419 | wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4420 | toP = frag_more (wid); | |
4421 | to_beg_P = toP; | |
4422 | shorts_this_frag = 0; | |
4423 | for (m = wid / 2; m; --m) | |
4424 | { | |
4425 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4426 | toP += 2; | |
4427 | fromP++; | |
4428 | shorts_this_frag++; | |
4429 | } | |
4430 | for (m = 0; m < the_ins.nrel; m++) | |
4431 | { | |
4432 | if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) | |
4433 | { | |
4434 | the_ins.reloc[m].n -= 2 * shorts_this_frag; | |
4435 | break; | |
4436 | } | |
4437 | wid = the_ins.reloc[m].wid; | |
4438 | if (wid == 0) | |
4439 | continue; | |
4440 | the_ins.reloc[m].wid = 0; | |
4441 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4442 | ||
4443 | fixP = fix_new_exp (frag_now, | |
4444 | ((toP - frag_now->fr_literal) | |
4445 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4446 | wid, | |
4447 | &the_ins.reloc[m].exp, | |
4448 | the_ins.reloc[m].pcrel, | |
4449 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4450 | the_ins.reloc[m].pic_reloc)); | |
4451 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4452 | } | |
cac27205 | 4453 | (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, |
252b5132 RH |
4454 | (relax_substateT) (the_ins.fragb[n].fragty), |
4455 | the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); | |
4456 | } | |
4457 | n = (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4458 | shorts_this_frag = 0; | |
4459 | if (n) | |
4460 | { | |
055d1eb0 | 4461 | toP = frag_more (n * 2); |
252b5132 RH |
4462 | while (n--) |
4463 | { | |
4464 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4465 | toP += 2; | |
4466 | fromP++; | |
4467 | shorts_this_frag++; | |
4468 | } | |
4469 | } | |
4470 | for (m = 0; m < the_ins.nrel; m++) | |
4471 | { | |
4472 | int wid; | |
4473 | ||
4474 | wid = the_ins.reloc[m].wid; | |
4475 | if (wid == 0) | |
4476 | continue; | |
4477 | the_ins.reloc[m].wid = 0; | |
4478 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4479 | ||
4480 | fixP = fix_new_exp (frag_now, | |
4481 | ((the_ins.reloc[m].n + toP - frag_now->fr_literal) | |
4482 | - shorts_this_frag * 2), | |
4483 | wid, | |
4484 | &the_ins.reloc[m].exp, | |
4485 | the_ins.reloc[m].pcrel, | |
4486 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4487 | the_ins.reloc[m].pic_reloc)); | |
4488 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4489 | } | |
4490 | } | |
4491 | ||
60fed2d3 NC |
4492 | /* Comparison function used by qsort to rank the opcode entries by name. */ |
4493 | ||
4494 | static int | |
4495 | m68k_compare_opcode (const void * v1, const void * v2) | |
4496 | { | |
4497 | struct m68k_opcode * op1, * op2; | |
4498 | int ret; | |
4499 | ||
03b13e59 NC |
4500 | if (v1 == v2) |
4501 | return 0; | |
4502 | ||
60fed2d3 NC |
4503 | op1 = *(struct m68k_opcode **) v1; |
4504 | op2 = *(struct m68k_opcode **) v2; | |
4505 | ||
4506 | /* Compare the two names. If different, return the comparison. | |
4507 | If the same, return the order they are in the opcode table. */ | |
4508 | ret = strcmp (op1->name, op2->name); | |
4509 | if (ret) | |
4510 | return ret; | |
4511 | if (op1 < op2) | |
4512 | return -1; | |
03b13e59 | 4513 | return 1; |
60fed2d3 NC |
4514 | } |
4515 | ||
252b5132 | 4516 | void |
60fed2d3 | 4517 | md_begin (void) |
252b5132 | 4518 | { |
60fed2d3 NC |
4519 | const struct m68k_opcode *ins; |
4520 | struct m68k_incant *hack, *slak; | |
4521 | const char *retval = 0; /* Empty string, or error msg text. */ | |
4522 | int i; | |
4523 | ||
4524 | /* Set up hash tables with 68000 instructions. | |
4525 | similar to what the vax assembler does. */ | |
252b5132 RH |
4526 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make |
4527 | a copy of it at runtime, adding in the information we want but isn't | |
4528 | there. I think it'd be better to have an awk script hack the table | |
4529 | at compile time. Or even just xstr the table and use it as-is. But | |
4530 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
4531 | names. */ | |
4532 | ||
252b5132 RH |
4533 | if (flag_mri) |
4534 | { | |
4535 | flag_reg_prefix_optional = 1; | |
4536 | m68k_abspcadd = 1; | |
4537 | if (! m68k_rel32_from_cmdline) | |
4538 | m68k_rel32 = 0; | |
4539 | } | |
4540 | ||
60fed2d3 NC |
4541 | /* First sort the opcode table into alphabetical order to seperate |
4542 | the order that the assembler wants to see the opcodes from the | |
4543 | order that the disassembler wants to see them. */ | |
4544 | m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); | |
4545 | if (!m68k_sorted_opcodes) | |
4546 | as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"), | |
045b540e | 4547 | m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes))); |
60fed2d3 NC |
4548 | |
4549 | for (i = m68k_numopcodes; i--;) | |
4550 | m68k_sorted_opcodes[i] = m68k_opcodes + i; | |
4551 | ||
4552 | qsort (m68k_sorted_opcodes, m68k_numopcodes, | |
4553 | sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); | |
4554 | ||
252b5132 RH |
4555 | op_hash = hash_new (); |
4556 | ||
4557 | obstack_begin (&robyn, 4000); | |
4558 | for (i = 0; i < m68k_numopcodes; i++) | |
4559 | { | |
78aff5a5 | 4560 | hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4561 | do |
4562 | { | |
60fed2d3 NC |
4563 | ins = m68k_sorted_opcodes[i]; |
4564 | ||
afa2158f NS |
4565 | /* We must enter all insns into the table, because .arch and |
4566 | .cpu directives can change things. */ | |
252b5132 | 4567 | slak->m_operands = ins->args; |
252b5132 RH |
4568 | slak->m_arch = ins->arch; |
4569 | slak->m_opcode = ins->opcode; | |
afa2158f NS |
4570 | |
4571 | /* In most cases we can determine the number of opcode words | |
4572 | by checking the second word of the mask. Unfortunately | |
4573 | some instructions have 2 opcode words, but no fixed bits | |
4574 | in the second word. A leading dot in the operands | |
4575 | string also indicates 2 opcodes. */ | |
4576 | if (*slak->m_operands == '.') | |
4577 | { | |
4578 | slak->m_operands++; | |
4579 | slak->m_codenum = 2; | |
4580 | } | |
4581 | else if (ins->match & 0xffffL) | |
4582 | slak->m_codenum = 2; | |
4583 | else | |
4584 | slak->m_codenum = 1; | |
4585 | slak->m_opnum = strlen (slak->m_operands) / 2; | |
4586 | ||
252b5132 | 4587 | if (i + 1 != m68k_numopcodes |
60fed2d3 | 4588 | && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) |
252b5132 | 4589 | { |
60fed2d3 | 4590 | slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4591 | i++; |
4592 | } | |
4593 | else | |
4594 | slak->m_next = 0; | |
4595 | slak = slak->m_next; | |
4596 | } | |
4597 | while (slak); | |
4598 | ||
4599 | retval = hash_insert (op_hash, ins->name, (char *) hack); | |
4600 | if (retval) | |
4601 | as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); | |
4602 | } | |
4603 | ||
4604 | for (i = 0; i < m68k_numaliases; i++) | |
4605 | { | |
4606 | const char *name = m68k_opcode_aliases[i].primary; | |
4607 | const char *alias = m68k_opcode_aliases[i].alias; | |
5a49b8ac | 4608 | void *val = hash_find (op_hash, name); |
60fed2d3 | 4609 | |
252b5132 RH |
4610 | if (!val) |
4611 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4612 | retval = hash_insert (op_hash, alias, val); | |
4613 | if (retval) | |
4614 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4615 | } | |
4616 | ||
4617 | /* In MRI mode, all unsized branches are variable sized. Normally, | |
4618 | they are word sized. */ | |
4619 | if (flag_mri) | |
4620 | { | |
4621 | static struct m68k_opcode_alias mri_aliases[] = | |
4622 | { | |
4623 | { "bhi", "jhi", }, | |
4624 | { "bls", "jls", }, | |
4625 | { "bcc", "jcc", }, | |
4626 | { "bcs", "jcs", }, | |
4627 | { "bne", "jne", }, | |
4628 | { "beq", "jeq", }, | |
4629 | { "bvc", "jvc", }, | |
4630 | { "bvs", "jvs", }, | |
4631 | { "bpl", "jpl", }, | |
4632 | { "bmi", "jmi", }, | |
4633 | { "bge", "jge", }, | |
4634 | { "blt", "jlt", }, | |
4635 | { "bgt", "jgt", }, | |
4636 | { "ble", "jle", }, | |
4637 | { "bra", "jra", }, | |
4638 | { "bsr", "jbsr", }, | |
4639 | }; | |
4640 | ||
8fce3f5e AM |
4641 | for (i = 0; |
4642 | i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); | |
4643 | i++) | |
252b5132 RH |
4644 | { |
4645 | const char *name = mri_aliases[i].primary; | |
4646 | const char *alias = mri_aliases[i].alias; | |
5a49b8ac | 4647 | void *val = hash_find (op_hash, name); |
60fed2d3 | 4648 | |
252b5132 RH |
4649 | if (!val) |
4650 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4651 | retval = hash_jam (op_hash, alias, val); | |
4652 | if (retval) | |
4653 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4654 | } | |
4655 | } | |
4656 | ||
8fce3f5e | 4657 | for (i = 0; i < (int) sizeof (notend_table); i++) |
252b5132 RH |
4658 | { |
4659 | notend_table[i] = 0; | |
4660 | alt_notend_table[i] = 0; | |
4661 | } | |
60fed2d3 | 4662 | |
252b5132 RH |
4663 | notend_table[','] = 1; |
4664 | notend_table['{'] = 1; | |
4665 | notend_table['}'] = 1; | |
4666 | alt_notend_table['a'] = 1; | |
4667 | alt_notend_table['A'] = 1; | |
4668 | alt_notend_table['d'] = 1; | |
4669 | alt_notend_table['D'] = 1; | |
4670 | alt_notend_table['#'] = 1; | |
4671 | alt_notend_table['&'] = 1; | |
4672 | alt_notend_table['f'] = 1; | |
4673 | alt_notend_table['F'] = 1; | |
4674 | #ifdef REGISTER_PREFIX | |
4675 | alt_notend_table[REGISTER_PREFIX] = 1; | |
4676 | #endif | |
4677 | ||
4678 | /* We need to put '(' in alt_notend_table to handle | |
60fed2d3 | 4679 | cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ |
252b5132 RH |
4680 | alt_notend_table['('] = 1; |
4681 | ||
4682 | /* We need to put '@' in alt_notend_table to handle | |
60fed2d3 | 4683 | cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ |
252b5132 RH |
4684 | alt_notend_table['@'] = 1; |
4685 | ||
4686 | /* We need to put digits in alt_notend_table to handle | |
60fed2d3 | 4687 | bfextu %d0{24:1},%d0 */ |
252b5132 RH |
4688 | alt_notend_table['0'] = 1; |
4689 | alt_notend_table['1'] = 1; | |
4690 | alt_notend_table['2'] = 1; | |
4691 | alt_notend_table['3'] = 1; | |
4692 | alt_notend_table['4'] = 1; | |
4693 | alt_notend_table['5'] = 1; | |
4694 | alt_notend_table['6'] = 1; | |
4695 | alt_notend_table['7'] = 1; | |
4696 | alt_notend_table['8'] = 1; | |
4697 | alt_notend_table['9'] = 1; | |
4698 | ||
4699 | #ifndef MIT_SYNTAX_ONLY | |
4700 | /* Insert pseudo ops, these have to go into the opcode table since | |
36759679 | 4701 | gas expects pseudo ops to start with a dot. */ |
252b5132 RH |
4702 | { |
4703 | int n = 0; | |
60fed2d3 | 4704 | |
252b5132 RH |
4705 | while (mote_pseudo_table[n].poc_name) |
4706 | { | |
60fed2d3 | 4707 | hack = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4708 | hash_insert (op_hash, |
4709 | mote_pseudo_table[n].poc_name, (char *) hack); | |
4710 | hack->m_operands = 0; | |
4711 | hack->m_opnum = n; | |
4712 | n++; | |
4713 | } | |
4714 | } | |
4715 | #endif | |
4716 | ||
4717 | init_regtable (); | |
4718 | ||
4719 | #ifdef OBJ_ELF | |
4720 | record_alignment (text_section, 2); | |
4721 | record_alignment (data_section, 2); | |
4722 | record_alignment (bss_section, 2); | |
4723 | #endif | |
4724 | } | |
4725 | ||
252b5132 RH |
4726 | \f |
4727 | /* This is called when a label is defined. */ | |
4728 | ||
4729 | void | |
31302357 | 4730 | m68k_frob_label (symbolS *sym) |
252b5132 RH |
4731 | { |
4732 | struct label_line *n; | |
4733 | ||
4734 | n = (struct label_line *) xmalloc (sizeof *n); | |
4735 | n->next = labels; | |
4736 | n->label = sym; | |
4737 | as_where (&n->file, &n->line); | |
4738 | n->text = 0; | |
4739 | labels = n; | |
4740 | current_label = n; | |
07a53e5c RH |
4741 | |
4742 | #ifdef OBJ_ELF | |
4743 | dwarf2_emit_label (sym); | |
4744 | #endif | |
252b5132 RH |
4745 | } |
4746 | ||
4747 | /* This is called when a value that is not an instruction is emitted. */ | |
4748 | ||
4749 | void | |
31302357 | 4750 | m68k_flush_pending_output (void) |
252b5132 RH |
4751 | { |
4752 | current_label = NULL; | |
4753 | } | |
4754 | ||
4755 | /* This is called at the end of the assembly, when the final value of | |
4756 | the label is known. We warn if this is a text symbol aligned at an | |
4757 | odd location. */ | |
4758 | ||
4759 | void | |
31302357 | 4760 | m68k_frob_symbol (symbolS *sym) |
252b5132 RH |
4761 | { |
4762 | if (S_GET_SEGMENT (sym) == reg_section | |
4763 | && (int) S_GET_VALUE (sym) < 0) | |
4764 | { | |
4765 | S_SET_SEGMENT (sym, absolute_section); | |
4766 | S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); | |
4767 | } | |
4768 | else if ((S_GET_VALUE (sym) & 1) != 0) | |
4769 | { | |
4770 | struct label_line *l; | |
4771 | ||
4772 | for (l = labels; l != NULL; l = l->next) | |
4773 | { | |
4774 | if (l->label == sym) | |
4775 | { | |
4776 | if (l->text) | |
4777 | as_warn_where (l->file, l->line, | |
4778 | _("text label `%s' aligned to odd boundary"), | |
4779 | S_GET_NAME (sym)); | |
4780 | break; | |
4781 | } | |
4782 | } | |
4783 | } | |
4784 | } | |
4785 | \f | |
4786 | /* This is called if we go in or out of MRI mode because of the .mri | |
4787 | pseudo-op. */ | |
4788 | ||
4789 | void | |
31302357 | 4790 | m68k_mri_mode_change (int on) |
252b5132 RH |
4791 | { |
4792 | if (on) | |
4793 | { | |
4794 | if (! flag_reg_prefix_optional) | |
4795 | { | |
4796 | flag_reg_prefix_optional = 1; | |
4797 | #ifdef REGISTER_PREFIX | |
4798 | init_regtable (); | |
4799 | #endif | |
4800 | } | |
4801 | m68k_abspcadd = 1; | |
4802 | if (! m68k_rel32_from_cmdline) | |
4803 | m68k_rel32 = 0; | |
4804 | } | |
4805 | else | |
4806 | { | |
4807 | if (! reg_prefix_optional_seen) | |
4808 | { | |
4809 | #ifdef REGISTER_PREFIX_OPTIONAL | |
4810 | flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
4811 | #else | |
4812 | flag_reg_prefix_optional = 0; | |
4813 | #endif | |
4814 | #ifdef REGISTER_PREFIX | |
4815 | init_regtable (); | |
4816 | #endif | |
4817 | } | |
4818 | m68k_abspcadd = 0; | |
4819 | if (! m68k_rel32_from_cmdline) | |
4820 | m68k_rel32 = 1; | |
4821 | } | |
4822 | } | |
4823 | ||
252b5132 | 4824 | char * |
31302357 | 4825 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 4826 | { |
499ac353 | 4827 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
4828 | } |
4829 | ||
4830 | void | |
31302357 | 4831 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
4832 | { |
4833 | number_to_chars_bigendian (buf, val, n); | |
4834 | } | |
4835 | ||
94f592af | 4836 | void |
55cf6793 | 4837 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 4838 | { |
bbe8ef22 | 4839 | offsetT val = *valP; |
252b5132 RH |
4840 | addressT upper_limit; |
4841 | offsetT lower_limit; | |
4842 | ||
4843 | /* This is unnecessary but it convinces the native rs6000 compiler | |
4844 | to generate the code we want. */ | |
4845 | char *buf = fixP->fx_frag->fr_literal; | |
4846 | buf += fixP->fx_where; | |
36759679 | 4847 | /* End ibm compiler workaround. */ |
252b5132 | 4848 | |
bd17c2c3 | 4849 | val = SEXT (val); |
252b5132 | 4850 | |
94f592af NC |
4851 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
4852 | fixP->fx_done = 1; | |
4853 | ||
252b5132 RH |
4854 | #ifdef OBJ_ELF |
4855 | if (fixP->fx_addsy) | |
4856 | { | |
4857 | memset (buf, 0, fixP->fx_size); | |
36759679 | 4858 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
4859 | |
4860 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4861 | && !S_IS_DEFINED (fixP->fx_addsy) | |
4862 | && !S_IS_WEAK (fixP->fx_addsy)) | |
4863 | S_SET_WEAK (fixP->fx_addsy); | |
cf869cce NC |
4864 | |
4865 | switch (fixP->fx_r_type) | |
4866 | { | |
4867 | case BFD_RELOC_68K_TLS_GD32: | |
4868 | case BFD_RELOC_68K_TLS_GD16: | |
4869 | case BFD_RELOC_68K_TLS_GD8: | |
4870 | case BFD_RELOC_68K_TLS_LDM32: | |
4871 | case BFD_RELOC_68K_TLS_LDM16: | |
4872 | case BFD_RELOC_68K_TLS_LDM8: | |
4873 | case BFD_RELOC_68K_TLS_LDO32: | |
4874 | case BFD_RELOC_68K_TLS_LDO16: | |
4875 | case BFD_RELOC_68K_TLS_LDO8: | |
4876 | case BFD_RELOC_68K_TLS_IE32: | |
4877 | case BFD_RELOC_68K_TLS_IE16: | |
4878 | case BFD_RELOC_68K_TLS_IE8: | |
4879 | case BFD_RELOC_68K_TLS_LE32: | |
4880 | case BFD_RELOC_68K_TLS_LE16: | |
4881 | case BFD_RELOC_68K_TLS_LE8: | |
4882 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4883 | break; | |
4884 | ||
4885 | default: | |
4886 | break; | |
4887 | } | |
4888 | ||
252b5132 RH |
4889 | return; |
4890 | } | |
22184a77 | 4891 | #elif defined(OBJ_AOUT) |
1c3f20b4 | 4892 | /* PR gas/3041 Do not fix frags referencing a weak symbol. */ |
22184a77 NC |
4893 | if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)) |
4894 | { | |
4895 | memset (buf, 0, fixP->fx_size); | |
1c3f20b4 | 4896 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
22184a77 NC |
4897 | return; |
4898 | } | |
252b5132 RH |
4899 | #endif |
4900 | ||
252b5132 RH |
4901 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
4902 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4903 | return; | |
252b5132 RH |
4904 | |
4905 | switch (fixP->fx_size) | |
4906 | { | |
94f592af NC |
4907 | /* The cast to offsetT below are necessary to make code |
4908 | correct for machines where ints are smaller than offsetT. */ | |
252b5132 RH |
4909 | case 1: |
4910 | *buf++ = val; | |
4911 | upper_limit = 0x7f; | |
4912 | lower_limit = - (offsetT) 0x80; | |
4913 | break; | |
4914 | case 2: | |
4915 | *buf++ = (val >> 8); | |
4916 | *buf++ = val; | |
4917 | upper_limit = 0x7fff; | |
4918 | lower_limit = - (offsetT) 0x8000; | |
4919 | break; | |
4920 | case 4: | |
4921 | *buf++ = (val >> 24); | |
4922 | *buf++ = (val >> 16); | |
4923 | *buf++ = (val >> 8); | |
4924 | *buf++ = val; | |
4925 | upper_limit = 0x7fffffff; | |
36759679 | 4926 | lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ |
252b5132 RH |
4927 | break; |
4928 | default: | |
4929 | BAD_CASE (fixP->fx_size); | |
4930 | } | |
4931 | ||
4932 | /* Fix up a negative reloc. */ | |
4933 | if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) | |
4934 | { | |
4935 | fixP->fx_addsy = fixP->fx_subsy; | |
4936 | fixP->fx_subsy = NULL; | |
4937 | fixP->fx_tcbit = 1; | |
4938 | } | |
4939 | ||
4940 | /* For non-pc-relative values, it's conceivable we might get something | |
4941 | like "0xff" for a byte field. So extend the upper part of the range | |
4942 | to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", | |
4943 | so that we can do any range checking at all. */ | |
4944 | if (! fixP->fx_pcrel && ! fixP->fx_signed) | |
4945 | upper_limit = upper_limit * 2 + 1; | |
4946 | ||
4947 | if ((addressT) val > upper_limit | |
4948 | && (val > 0 || val < lower_limit)) | |
2b878742 NS |
4949 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4950 | _("value %ld out of range"), (long)val); | |
252b5132 RH |
4951 | |
4952 | /* A one byte PC-relative reloc means a short branch. We can't use | |
4953 | a short branch with a value of 0 or -1, because those indicate | |
4954 | different opcodes (branches with longer offsets). fixup_segment | |
4955 | in write.c may have clobbered fx_pcrel, so we need to examine the | |
4956 | reloc type. */ | |
4957 | if ((fixP->fx_pcrel | |
7be1c489 | 4958 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
252b5132 RH |
4959 | && fixP->fx_size == 1 |
4960 | && (fixP->fx_addsy == NULL | |
4961 | || S_IS_DEFINED (fixP->fx_addsy)) | |
4962 | && (val == 0 || val == -1)) | |
2b878742 NS |
4963 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4964 | _("invalid byte branch offset")); | |
252b5132 RH |
4965 | } |
4966 | ||
252b5132 RH |
4967 | /* *fragP has been relaxed to its final size, and now needs to have |
4968 | the bytes inside it modified to conform to the new size There is UGLY | |
4969 | MAGIC here. .. | |
4970 | */ | |
4971 | static void | |
31302357 | 4972 | md_convert_frag_1 (fragS *fragP) |
252b5132 RH |
4973 | { |
4974 | long disp; | |
2b878742 | 4975 | fixS *fixP = NULL; |
252b5132 RH |
4976 | |
4977 | /* Address in object code of the displacement. */ | |
4978 | register int object_address = fragP->fr_fix + fragP->fr_address; | |
4979 | ||
4980 | /* Address in gas core of the place to store the displacement. */ | |
4981 | /* This convinces the native rs6000 compiler to generate the code we | |
92774660 | 4982 | want. */ |
252b5132 RH |
4983 | register char *buffer_address = fragP->fr_literal; |
4984 | buffer_address += fragP->fr_fix; | |
36759679 | 4985 | /* End ibm compiler workaround. */ |
252b5132 RH |
4986 | |
4987 | /* The displacement of the address, from current location. */ | |
4988 | disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; | |
4989 | disp = (disp + fragP->fr_offset) - object_address; | |
4990 | ||
252b5132 RH |
4991 | switch (fragP->fr_subtype) |
4992 | { | |
151337e8 NC |
4993 | case TAB (BRANCHBWL, BYTE): |
4994 | case TAB (BRABSJUNC, BYTE): | |
4995 | case TAB (BRABSJCOND, BYTE): | |
4996 | case TAB (BRANCHBW, BYTE): | |
cac27205 | 4997 | case TAB (BRANCHBWPL, BYTE): |
252b5132 RH |
4998 | know (issbyte (disp)); |
4999 | if (disp == 0) | |
b091f402 AM |
5000 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5001 | _("short branch with zero offset: use :w")); | |
151337e8 | 5002 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 5003 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 5004 | fixP->fx_pcrel_adjust = -1; |
252b5132 | 5005 | break; |
151337e8 NC |
5006 | case TAB (BRANCHBWL, SHORT): |
5007 | case TAB (BRABSJUNC, SHORT): | |
5008 | case TAB (BRABSJCOND, SHORT): | |
5009 | case TAB (BRANCHBW, SHORT): | |
cac27205 | 5010 | case TAB (BRANCHBWPL, SHORT): |
252b5132 | 5011 | fragP->fr_opcode[1] = 0x00; |
2b878742 NS |
5012 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5013 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5014 | fragP->fr_fix += 2; |
5015 | break; | |
5016 | case TAB (BRANCHBWL, LONG): | |
5017 | fragP->fr_opcode[1] = (char) 0xFF; | |
2b878742 NS |
5018 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5019 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
151337e8 | 5020 | fragP->fr_fix += 4; |
252b5132 | 5021 | break; |
cac27205 NC |
5022 | case TAB (BRANCHBWPL, LONG): |
5023 | /* Here we are converting an unconditional branch into a pair of | |
5024 | conditional branches, in order to get the range. */ | |
5025 | fragP->fr_opcode[0] = 0x66; /* bne */ | |
5026 | fragP->fr_opcode[1] = 0xFF; | |
5027 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
5028 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
5029 | fixP->fx_file = fragP->fr_file; | |
5030 | fixP->fx_line = fragP->fr_line; | |
5031 | fragP->fr_fix += 4; /* Skip first offset */ | |
5032 | buffer_address += 4; | |
5033 | *buffer_address++ = 0x67; /* beq */ | |
5034 | *buffer_address++ = 0xff; | |
5035 | fragP->fr_fix += 2; /* Skip second branch opcode */ | |
5036 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
5037 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
5038 | fragP->fr_fix += 4; | |
5039 | break; | |
151337e8 NC |
5040 | case TAB (BRABSJUNC, LONG): |
5041 | if (fragP->fr_opcode[0] == 0x61) /* jbsr */ | |
252b5132 | 5042 | { |
36759679 | 5043 | if (flag_keep_pcrel) |
2b878742 NS |
5044 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5045 | _("Conversion of PC relative BSR to absolute JSR")); | |
151337e8 | 5046 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 5047 | fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ |
2b878742 NS |
5048 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5049 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 NC |
5050 | fragP->fr_fix += 4; |
5051 | } | |
5052 | else if (fragP->fr_opcode[0] == 0x60) /* jbra */ | |
5053 | { | |
36759679 | 5054 | if (flag_keep_pcrel) |
2b878742 NS |
5055 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5056 | _("Conversion of PC relative branch to absolute jump")); | |
151337e8 | 5057 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 5058 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ |
2b878742 NS |
5059 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5060 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 | 5061 | fragP->fr_fix += 4; |
252b5132 RH |
5062 | } |
5063 | else | |
5064 | { | |
151337e8 NC |
5065 | /* This cannot happen, because jbsr and jbra are the only two |
5066 | unconditional branches. */ | |
5067 | abort (); | |
252b5132 RH |
5068 | } |
5069 | break; | |
151337e8 | 5070 | case TAB (BRABSJCOND, LONG): |
36759679 | 5071 | if (flag_keep_pcrel) |
2b878742 NS |
5072 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5073 | _("Conversion of PC relative conditional branch to absolute jump")); | |
92774660 | 5074 | |
36759679 NC |
5075 | /* Only Bcc 68000 instructions can come here |
5076 | Change bcc into b!cc/jmp absl long. */ | |
5077 | fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ | |
5078 | fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ | |
252b5132 RH |
5079 | |
5080 | /* JF: these used to be fr_opcode[2,3], but they may be in a | |
67c1ffbe | 5081 | different frag, in which case referring to them is a no-no. |
92774660 | 5082 | Only fr_opcode[0,1] are guaranteed to work. */ |
252b5132 RH |
5083 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
5084 | *buffer_address++ = (char) 0xf9; | |
36759679 | 5085 | fragP->fr_fix += 2; /* Account for jmp instruction. */ |
2b878742 NS |
5086 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5087 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 NC |
5088 | fragP->fr_fix += 4; |
5089 | break; | |
5090 | case TAB (FBRANCH, SHORT): | |
5091 | know ((fragP->fr_opcode[1] & 0x40) == 0); | |
2b878742 NS |
5092 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5093 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5094 | fragP->fr_fix += 2; |
5095 | break; | |
5096 | case TAB (FBRANCH, LONG): | |
36759679 | 5097 | fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ |
2b878742 NS |
5098 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5099 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
252b5132 | 5100 | fragP->fr_fix += 4; |
252b5132 | 5101 | break; |
151337e8 NC |
5102 | case TAB (DBCCLBR, SHORT): |
5103 | case TAB (DBCCABSJ, SHORT): | |
2b878742 NS |
5104 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5105 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5106 | fragP->fr_fix += 2; |
5107 | break; | |
5108 | case TAB (DBCCLBR, LONG): | |
36759679 NC |
5109 | /* Only DBcc instructions can come here. |
5110 | Change dbcc into dbcc/bral. | |
5111 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
5112 | if (flag_keep_pcrel) | |
2b878742 NS |
5113 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5114 | _("Conversion of DBcc to absolute jump")); | |
28e7409f | 5115 | |
36759679 | 5116 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
252b5132 | 5117 | *buffer_address++ = 0x04; |
36759679 | 5118 | *buffer_address++ = 0x60; /* Put in bra pc+6. */ |
252b5132 | 5119 | *buffer_address++ = 0x06; |
151337e8 NC |
5120 | *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ |
5121 | *buffer_address++ = (char) 0xff; | |
252b5132 | 5122 | |
36759679 | 5123 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
2b878742 NS |
5124 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5125 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
252b5132 | 5126 | fragP->fr_fix += 4; |
252b5132 | 5127 | break; |
151337e8 | 5128 | case TAB (DBCCABSJ, LONG): |
36759679 NC |
5129 | /* Only DBcc instructions can come here. |
5130 | Change dbcc into dbcc/jmp. | |
5131 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
5132 | if (flag_keep_pcrel) | |
2b878742 NS |
5133 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5134 | _("Conversion of PC relative conditional branch to absolute jump")); | |
151337e8 | 5135 | |
36759679 | 5136 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
151337e8 | 5137 | *buffer_address++ = 0x04; |
36759679 | 5138 | *buffer_address++ = 0x60; /* Put in bra pc + 6. */ |
151337e8 | 5139 | *buffer_address++ = 0x06; |
36759679 | 5140 | *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ |
151337e8 NC |
5141 | *buffer_address++ = (char) 0xf9; |
5142 | ||
36759679 | 5143 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
2b878742 NS |
5144 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5145 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
252b5132 | 5146 | fragP->fr_fix += 4; |
252b5132 | 5147 | break; |
151337e8 | 5148 | case TAB (PCREL1632, SHORT): |
252b5132 RH |
5149 | fragP->fr_opcode[1] &= ~0x3F; |
5150 | fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ | |
2b878742 NS |
5151 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, |
5152 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 | 5153 | fragP->fr_fix += 2; |
252b5132 | 5154 | break; |
151337e8 | 5155 | case TAB (PCREL1632, LONG): |
252b5132 RH |
5156 | /* Already set to mode 7.3; this indicates: PC indirect with |
5157 | suppressed index, 32-bit displacement. */ | |
5158 | *buffer_address++ = 0x01; | |
5159 | *buffer_address++ = 0x70; | |
5160 | fragP->fr_fix += 2; | |
151337e8 | 5161 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 5162 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
5163 | fixP->fx_pcrel_adjust = 2; |
5164 | fragP->fr_fix += 4; | |
252b5132 | 5165 | break; |
252b5132 | 5166 | case TAB (PCINDEX, BYTE): |
9c2799c2 | 5167 | gas_assert (fragP->fr_fix >= 2); |
252b5132 | 5168 | buffer_address[-2] &= ~1; |
151337e8 | 5169 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 5170 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 5171 | fixP->fx_pcrel_adjust = 1; |
252b5132 RH |
5172 | break; |
5173 | case TAB (PCINDEX, SHORT): | |
9c2799c2 | 5174 | gas_assert (fragP->fr_fix >= 2); |
252b5132 RH |
5175 | buffer_address[-2] |= 0x1; |
5176 | buffer_address[-1] = 0x20; | |
5177 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, | |
5cbdaa77 | 5178 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
252b5132 | 5179 | fixP->fx_pcrel_adjust = 2; |
151337e8 | 5180 | fragP->fr_fix += 2; |
252b5132 RH |
5181 | break; |
5182 | case TAB (PCINDEX, LONG): | |
9c2799c2 | 5183 | gas_assert (fragP->fr_fix >= 2); |
252b5132 RH |
5184 | buffer_address[-2] |= 0x1; |
5185 | buffer_address[-1] = 0x30; | |
151337e8 | 5186 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 5187 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
5188 | fixP->fx_pcrel_adjust = 2; |
5189 | fragP->fr_fix += 4; | |
5190 | break; | |
5191 | case TAB (ABSTOPCREL, SHORT): | |
2b878742 NS |
5192 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5193 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5194 | fragP->fr_fix += 2; |
5195 | break; | |
5196 | case TAB (ABSTOPCREL, LONG): | |
36759679 | 5197 | if (flag_keep_pcrel) |
025987ea NS |
5198 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5199 | _("Conversion of PC relative displacement to absolute")); | |
151337e8 | 5200 | /* The thing to do here is force it to ABSOLUTE LONG, since |
36759679 | 5201 | ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ |
151337e8 NC |
5202 | if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) |
5203 | abort (); | |
5204 | fragP->fr_opcode[1] &= ~0x3F; | |
5205 | fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ | |
2b878742 NS |
5206 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5207 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 | 5208 | fragP->fr_fix += 4; |
252b5132 | 5209 | break; |
252b5132 | 5210 | } |
2b878742 NS |
5211 | if (fixP) |
5212 | { | |
5213 | fixP->fx_file = fragP->fr_file; | |
5214 | fixP->fx_line = fragP->fr_line; | |
5215 | } | |
252b5132 RH |
5216 | } |
5217 | ||
252b5132 | 5218 | void |
31302357 AS |
5219 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
5220 | segT sec ATTRIBUTE_UNUSED, | |
5221 | fragS *fragP) | |
252b5132 RH |
5222 | { |
5223 | md_convert_frag_1 (fragP); | |
5224 | } | |
252b5132 RH |
5225 | |
5226 | /* Force truly undefined symbols to their maximum size, and generally set up | |
5227 | the frag list to be relaxed | |
5228 | */ | |
5229 | int | |
31302357 | 5230 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 5231 | { |
151337e8 | 5232 | /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ |
252b5132 RH |
5233 | switch (fragP->fr_subtype) |
5234 | { | |
151337e8 | 5235 | case TAB (BRANCHBWL, SZ_UNDEF): |
cac27205 | 5236 | case TAB (BRANCHBWPL, SZ_UNDEF): |
151337e8 | 5237 | case TAB (BRABSJUNC, SZ_UNDEF): |
151337e8 | 5238 | case TAB (BRABSJCOND, SZ_UNDEF): |
252b5132 | 5239 | { |
151337e8 NC |
5240 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
5241 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 5242 | { |
151337e8 NC |
5243 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
5244 | } | |
5245 | else if (flag_short_refs) | |
5246 | { | |
5247 | /* Symbol is undefined and we want short ref. */ | |
5248 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5249 | } |
5250 | else | |
5251 | { | |
151337e8 NC |
5252 | /* Symbol is still undefined. Make it LONG. */ |
5253 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); | |
252b5132 RH |
5254 | } |
5255 | break; | |
151337e8 | 5256 | } |
252b5132 | 5257 | |
151337e8 | 5258 | case TAB (BRANCHBW, SZ_UNDEF): |
252b5132 | 5259 | { |
151337e8 NC |
5260 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
5261 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 5262 | { |
151337e8 | 5263 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
252b5132 RH |
5264 | } |
5265 | else | |
5266 | { | |
151337e8 NC |
5267 | /* Symbol is undefined and we don't have long branches. */ |
5268 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5269 | } |
5270 | break; | |
151337e8 | 5271 | } |
252b5132 | 5272 | |
151337e8 | 5273 | case TAB (FBRANCH, SZ_UNDEF): |
151337e8 NC |
5274 | case TAB (DBCCLBR, SZ_UNDEF): |
5275 | case TAB (DBCCABSJ, SZ_UNDEF): | |
5c65dbc1 | 5276 | case TAB (PCREL1632, SZ_UNDEF): |
252b5132 | 5277 | { |
8ec6253e NC |
5278 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
5279 | && relaxable_symbol (fragP->fr_symbol)) | |
151337e8 | 5280 | || flag_short_refs) |
252b5132 | 5281 | { |
151337e8 | 5282 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
252b5132 RH |
5283 | } |
5284 | else | |
5285 | { | |
151337e8 | 5286 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); |
252b5132 RH |
5287 | } |
5288 | break; | |
151337e8 | 5289 | } |
81d4177b | 5290 | |
252b5132 RH |
5291 | case TAB (PCINDEX, SZ_UNDEF): |
5292 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
151337e8 | 5293 | && relaxable_symbol (fragP->fr_symbol))) |
252b5132 RH |
5294 | { |
5295 | fragP->fr_subtype = TAB (PCINDEX, BYTE); | |
5296 | } | |
5297 | else | |
5298 | { | |
5299 | fragP->fr_subtype = TAB (PCINDEX, LONG); | |
252b5132 RH |
5300 | } |
5301 | break; | |
5302 | ||
151337e8 NC |
5303 | case TAB (ABSTOPCREL, SZ_UNDEF): |
5304 | { | |
5305 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
5306 | && relaxable_symbol (fragP->fr_symbol))) | |
5307 | { | |
5308 | fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); | |
151337e8 NC |
5309 | } |
5310 | else | |
5311 | { | |
5312 | fragP->fr_subtype = TAB (ABSTOPCREL, LONG); | |
151337e8 NC |
5313 | } |
5314 | break; | |
5315 | } | |
5316 | ||
252b5132 RH |
5317 | default: |
5318 | break; | |
5319 | } | |
5320 | ||
151337e8 | 5321 | /* Now that SZ_UNDEF are taken care of, check others. */ |
252b5132 RH |
5322 | switch (fragP->fr_subtype) |
5323 | { | |
151337e8 NC |
5324 | case TAB (BRANCHBWL, BYTE): |
5325 | case TAB (BRABSJUNC, BYTE): | |
5326 | case TAB (BRABSJCOND, BYTE): | |
5327 | case TAB (BRANCHBW, BYTE): | |
252b5132 | 5328 | /* We can't do a short jump to the next instruction, so in that |
ac62c346 AM |
5329 | case we force word mode. If the symbol is at the start of a |
5330 | frag, and it is the next frag with any data in it (usually | |
5331 | this is just the next frag, but assembler listings may | |
5332 | introduce empty frags), we must use word mode. */ | |
5333 | if (fragP->fr_symbol) | |
252b5132 | 5334 | { |
ac62c346 | 5335 | fragS *sym_frag; |
252b5132 | 5336 | |
ac62c346 AM |
5337 | sym_frag = symbol_get_frag (fragP->fr_symbol); |
5338 | if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) | |
252b5132 | 5339 | { |
ac62c346 AM |
5340 | fragS *l; |
5341 | ||
23b7f870 | 5342 | for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) |
ac62c346 AM |
5343 | if (l->fr_fix != 0) |
5344 | break; | |
5345 | if (l == sym_frag) | |
5346 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5347 | } |
5348 | } | |
5349 | break; | |
5350 | default: | |
5351 | break; | |
5352 | } | |
ac62c346 | 5353 | return md_relax_table[fragP->fr_subtype].rlx_length; |
252b5132 RH |
5354 | } |
5355 | ||
5356 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
5357 | /* the bit-field entries in the relocation_info struct plays hell | |
5358 | with the byte-order problems of cross-assembly. So as a hack, | |
5359 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
36759679 | 5360 | you there. -KWK */ |
252b5132 RH |
5361 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes |
5362 | are symbolnum, most sig. byte first. Last byte is broken up with | |
5363 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
5364 | nibble as nuthin. (on Sun 3 at least) */ | |
5365 | /* Translate the internal relocation information into target-specific | |
92774660 | 5366 | format. */ |
252b5132 RH |
5367 | #ifdef comment |
5368 | void | |
31302357 | 5369 | md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) |
252b5132 | 5370 | { |
36759679 | 5371 | /* This is easy. */ |
252b5132 | 5372 | md_number_to_chars (the_bytes, ri->r_address, 4); |
36759679 | 5373 | /* Now the fun stuff. */ |
252b5132 | 5374 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; |
36759679 NC |
5375 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; |
5376 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
31302357 AS |
5377 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) |
5378 | | ((ri->r_length << 5) & 0x60) | |
5379 | | ((ri->r_extern << 4) & 0x10)); | |
252b5132 RH |
5380 | } |
5381 | ||
36759679 | 5382 | #endif |
252b5132 | 5383 | |
252b5132 RH |
5384 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
5385 | ||
5386 | #ifndef WORKING_DOT_WORD | |
2b4f075a HPN |
5387 | int md_short_jump_size = 4; |
5388 | int md_long_jump_size = 6; | |
252b5132 RH |
5389 | |
5390 | void | |
31302357 AS |
5391 | md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, |
5392 | fragS *frag ATTRIBUTE_UNUSED, | |
5393 | symbolS *to_symbol ATTRIBUTE_UNUSED) | |
252b5132 RH |
5394 | { |
5395 | valueT offset; | |
5396 | ||
5397 | offset = to_addr - (from_addr + 2); | |
5398 | ||
5399 | md_number_to_chars (ptr, (valueT) 0x6000, 2); | |
5400 | md_number_to_chars (ptr + 2, (valueT) offset, 2); | |
5401 | } | |
5402 | ||
5403 | void | |
31302357 AS |
5404 | md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, |
5405 | fragS *frag, symbolS *to_symbol) | |
252b5132 RH |
5406 | { |
5407 | valueT offset; | |
5408 | ||
6b6e92f4 | 5409 | if (!HAVE_LONG_BRANCH (current_architecture)) |
252b5132 | 5410 | { |
36759679 | 5411 | if (flag_keep_pcrel) |
6b6e92f4 | 5412 | as_fatal (_("Tried to convert PC relative branch to absolute jump")); |
252b5132 RH |
5413 | offset = to_addr - S_GET_VALUE (to_symbol); |
5414 | md_number_to_chars (ptr, (valueT) 0x4EF9, 2); | |
5415 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5416 | fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, | |
5417 | 0, NO_RELOC); | |
5418 | } | |
5419 | else | |
5420 | { | |
5421 | offset = to_addr - (from_addr + 2); | |
5422 | md_number_to_chars (ptr, (valueT) 0x60ff, 2); | |
5423 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5424 | } | |
5425 | } | |
5426 | ||
5427 | #endif | |
5428 | ||
5429 | /* Different values of OK tell what its OK to return. Things that | |
5430 | aren't OK are an error (what a shock, no?) | |
5431 | ||
5432 | 0: Everything is OK | |
3e602632 NC |
5433 | 10: Absolute 1:8 only |
5434 | 20: Absolute 0:7 only | |
5435 | 30: absolute 0:15 only | |
5436 | 40: Absolute 0:31 only | |
5437 | 50: absolute 0:127 only | |
252b5132 | 5438 | 55: absolute -64:63 only |
3e602632 | 5439 | 60: absolute -128:127 only |
afa2158f | 5440 | 65: absolute 0:511 only |
3e602632 NC |
5441 | 70: absolute 0:4095 only |
5442 | 80: absolute -1, 1:7 only | |
5443 | 90: No bignums. */ | |
252b5132 RH |
5444 | |
5445 | static int | |
31302357 | 5446 | get_num (struct m68k_exp *exp, int ok) |
252b5132 RH |
5447 | { |
5448 | if (exp->exp.X_op == O_absent) | |
5449 | { | |
36759679 | 5450 | /* Do the same thing the VAX asm does. */ |
252b5132 RH |
5451 | op (exp) = O_constant; |
5452 | adds (exp) = 0; | |
5453 | subs (exp) = 0; | |
5454 | offs (exp) = 0; | |
5455 | if (ok == 10) | |
5456 | { | |
5457 | as_warn (_("expression out of range: defaulting to 1")); | |
5458 | offs (exp) = 1; | |
5459 | } | |
5460 | } | |
5461 | else if (exp->exp.X_op == O_constant) | |
5462 | { | |
5463 | switch (ok) | |
5464 | { | |
5465 | case 10: | |
bd17c2c3 | 5466 | if ((valueT) TRUNC (offs (exp)) - 1 > 7) |
252b5132 RH |
5467 | { |
5468 | as_warn (_("expression out of range: defaulting to 1")); | |
5469 | offs (exp) = 1; | |
5470 | } | |
5471 | break; | |
5472 | case 20: | |
bd17c2c3 | 5473 | if ((valueT) TRUNC (offs (exp)) > 7) |
252b5132 RH |
5474 | goto outrange; |
5475 | break; | |
5476 | case 30: | |
bd17c2c3 | 5477 | if ((valueT) TRUNC (offs (exp)) > 15) |
252b5132 RH |
5478 | goto outrange; |
5479 | break; | |
5480 | case 40: | |
bd17c2c3 | 5481 | if ((valueT) TRUNC (offs (exp)) > 32) |
252b5132 RH |
5482 | goto outrange; |
5483 | break; | |
5484 | case 50: | |
bd17c2c3 | 5485 | if ((valueT) TRUNC (offs (exp)) > 127) |
252b5132 RH |
5486 | goto outrange; |
5487 | break; | |
5488 | case 55: | |
bd17c2c3 | 5489 | if ((valueT) SEXT (offs (exp)) + 64 > 127) |
252b5132 RH |
5490 | goto outrange; |
5491 | break; | |
5492 | case 60: | |
bd17c2c3 | 5493 | if ((valueT) SEXT (offs (exp)) + 128 > 255) |
252b5132 | 5494 | goto outrange; |
afa2158f NS |
5495 | break; |
5496 | case 65: | |
5497 | if ((valueT) TRUNC (offs (exp)) > 511) | |
5498 | goto outrange; | |
252b5132 RH |
5499 | break; |
5500 | case 70: | |
bd17c2c3 | 5501 | if ((valueT) TRUNC (offs (exp)) > 4095) |
252b5132 RH |
5502 | { |
5503 | outrange: | |
5504 | as_warn (_("expression out of range: defaulting to 0")); | |
5505 | offs (exp) = 0; | |
5506 | } | |
5507 | break; | |
3e602632 | 5508 | case 80: |
bd17c2c3 AM |
5509 | if ((valueT) TRUNC (offs (exp)) != 0xffffffff |
5510 | && (valueT) TRUNC (offs (exp)) - 1 > 6) | |
3e602632 NC |
5511 | { |
5512 | as_warn (_("expression out of range: defaulting to 1")); | |
5513 | offs (exp) = 1; | |
5514 | } | |
5515 | break; | |
252b5132 RH |
5516 | default: |
5517 | break; | |
5518 | } | |
5519 | } | |
5520 | else if (exp->exp.X_op == O_big) | |
5521 | { | |
36759679 | 5522 | if (offs (exp) <= 0 /* flonum. */ |
3e602632 | 5523 | && (ok == 90 /* no bignums */ |
36759679 | 5524 | || (ok > 10 /* Small-int ranges including 0 ok. */ |
252b5132 RH |
5525 | /* If we have a flonum zero, a zero integer should |
5526 | do as well (e.g., in moveq). */ | |
5527 | && generic_floating_point_number.exponent == 0 | |
5528 | && generic_floating_point_number.low[0] == 0))) | |
5529 | { | |
36759679 | 5530 | /* HACK! Turn it into a long. */ |
252b5132 RH |
5531 | LITTLENUM_TYPE words[6]; |
5532 | ||
36759679 | 5533 | gen_to_words (words, 2, 8L); /* These numbers are magic! */ |
252b5132 RH |
5534 | op (exp) = O_constant; |
5535 | adds (exp) = 0; | |
5536 | subs (exp) = 0; | |
5537 | offs (exp) = words[1] | (words[0] << 16); | |
5538 | } | |
5539 | else if (ok != 0) | |
5540 | { | |
5541 | op (exp) = O_constant; | |
5542 | adds (exp) = 0; | |
5543 | subs (exp) = 0; | |
5544 | offs (exp) = (ok == 10) ? 1 : 0; | |
5545 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
045b540e | 5546 | (long) offs (exp)); |
252b5132 RH |
5547 | } |
5548 | } | |
5549 | else | |
5550 | { | |
3e602632 | 5551 | if (ok >= 10 && ok <= 80) |
252b5132 RH |
5552 | { |
5553 | op (exp) = O_constant; | |
5554 | adds (exp) = 0; | |
5555 | subs (exp) = 0; | |
5556 | offs (exp) = (ok == 10) ? 1 : 0; | |
5557 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
045b540e | 5558 | (long) offs (exp)); |
252b5132 RH |
5559 | } |
5560 | } | |
5561 | ||
5562 | if (exp->size != SIZE_UNSPEC) | |
5563 | { | |
5564 | switch (exp->size) | |
5565 | { | |
5566 | case SIZE_UNSPEC: | |
5567 | case SIZE_LONG: | |
5568 | break; | |
5569 | case SIZE_BYTE: | |
5570 | if (!isbyte (offs (exp))) | |
5571 | as_warn (_("expression doesn't fit in BYTE")); | |
5572 | break; | |
5573 | case SIZE_WORD: | |
5574 | if (!isword (offs (exp))) | |
5575 | as_warn (_("expression doesn't fit in WORD")); | |
5576 | break; | |
5577 | } | |
5578 | } | |
5579 | ||
5580 | return offs (exp); | |
5581 | } | |
5582 | ||
5583 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
5584 | ||
5585 | static void | |
31302357 | 5586 | s_data1 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5587 | { |
5588 | subseg_set (data_section, 1); | |
5589 | demand_empty_rest_of_line (); | |
5590 | } | |
5591 | ||
5592 | static void | |
31302357 | 5593 | s_data2 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5594 | { |
5595 | subseg_set (data_section, 2); | |
5596 | demand_empty_rest_of_line (); | |
5597 | } | |
5598 | ||
5599 | static void | |
31302357 | 5600 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5601 | { |
5602 | /* We don't support putting frags in the BSS segment, we fake it | |
5603 | by marking in_bss, then looking at s_skip for clues. */ | |
5604 | ||
5605 | subseg_set (bss_section, 0); | |
5606 | demand_empty_rest_of_line (); | |
5607 | } | |
5608 | ||
5609 | static void | |
31302357 | 5610 | s_even (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5611 | { |
5612 | register int temp; | |
5613 | register long temp_fill; | |
5614 | ||
5615 | temp = 1; /* JF should be 2? */ | |
5616 | temp_fill = get_absolute_expression (); | |
92774660 | 5617 | if (!need_pass_2) /* Never make frag if expect extra pass. */ |
252b5132 RH |
5618 | frag_align (temp, (int) temp_fill, 0); |
5619 | demand_empty_rest_of_line (); | |
5620 | record_alignment (now_seg, temp); | |
5621 | } | |
5622 | ||
5623 | static void | |
31302357 | 5624 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5625 | { |
5626 | demand_empty_rest_of_line (); | |
5627 | } | |
5628 | \f | |
5629 | /* Pseudo-ops handled for MRI compatibility. */ | |
5630 | ||
5631 | /* This function returns non-zero if the argument is a conditional | |
5632 | pseudo-op. This is called when checking whether a pending | |
5633 | alignment is needed. */ | |
5634 | ||
5635 | int | |
31302357 | 5636 | m68k_conditional_pseudoop (pseudo_typeS *pop) |
252b5132 RH |
5637 | { |
5638 | return (pop->poc_handler == s_mri_if | |
5639 | || pop->poc_handler == s_mri_else); | |
5640 | } | |
5641 | ||
5642 | /* Handle an MRI style chip specification. */ | |
5643 | ||
5644 | static void | |
31302357 | 5645 | mri_chip (void) |
252b5132 RH |
5646 | { |
5647 | char *s; | |
5648 | char c; | |
5649 | int i; | |
5650 | ||
5651 | s = input_line_pointer; | |
5652 | /* We can't use get_symbol_end since the processor names are not proper | |
5653 | symbols. */ | |
5654 | while (is_part_of_name (c = *input_line_pointer++)) | |
5655 | ; | |
5656 | *--input_line_pointer = 0; | |
266abb8f NS |
5657 | for (i = 0; m68k_cpus[i].name; i++) |
5658 | if (strcasecmp (s, m68k_cpus[i].name) == 0) | |
252b5132 | 5659 | break; |
266abb8f | 5660 | if (!m68k_cpus[i].name) |
252b5132 RH |
5661 | { |
5662 | as_bad (_("%s: unrecognized processor name"), s); | |
5663 | *input_line_pointer = c; | |
5664 | ignore_rest_of_line (); | |
5665 | return; | |
5666 | } | |
5667 | *input_line_pointer = c; | |
5668 | ||
5669 | if (*input_line_pointer == '/') | |
5670 | current_architecture = 0; | |
5671 | else | |
5672 | current_architecture &= m68881 | m68851; | |
266abb8f | 5673 | current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); |
2da12c60 | 5674 | control_regs = m68k_cpus[i].control_regs; |
252b5132 RH |
5675 | |
5676 | while (*input_line_pointer == '/') | |
5677 | { | |
5678 | ++input_line_pointer; | |
5679 | s = input_line_pointer; | |
5680 | /* We can't use get_symbol_end since the processor names are not | |
5681 | proper symbols. */ | |
5682 | while (is_part_of_name (c = *input_line_pointer++)) | |
5683 | ; | |
5684 | *--input_line_pointer = 0; | |
5685 | if (strcmp (s, "68881") == 0) | |
5686 | current_architecture |= m68881; | |
5687 | else if (strcmp (s, "68851") == 0) | |
5688 | current_architecture |= m68851; | |
5689 | *input_line_pointer = c; | |
5690 | } | |
252b5132 RH |
5691 | } |
5692 | ||
5693 | /* The MRI CHIP pseudo-op. */ | |
5694 | ||
5695 | static void | |
31302357 | 5696 | s_chip (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5697 | { |
5698 | char *stop = NULL; | |
5699 | char stopc; | |
5700 | ||
5701 | if (flag_mri) | |
5702 | stop = mri_comment_field (&stopc); | |
5703 | mri_chip (); | |
5704 | if (flag_mri) | |
5705 | mri_comment_end (stop, stopc); | |
5706 | demand_empty_rest_of_line (); | |
5707 | } | |
5708 | ||
5709 | /* The MRI FOPT pseudo-op. */ | |
5710 | ||
5711 | static void | |
31302357 | 5712 | s_fopt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5713 | { |
5714 | SKIP_WHITESPACE (); | |
5715 | ||
5716 | if (strncasecmp (input_line_pointer, "ID=", 3) == 0) | |
5717 | { | |
5718 | int temp; | |
5719 | ||
5720 | input_line_pointer += 3; | |
5721 | temp = get_absolute_expression (); | |
5722 | if (temp < 0 || temp > 7) | |
5723 | as_bad (_("bad coprocessor id")); | |
5724 | else | |
5725 | m68k_float_copnum = COP0 + temp; | |
5726 | } | |
5727 | else | |
5728 | { | |
5729 | as_bad (_("unrecognized fopt option")); | |
5730 | ignore_rest_of_line (); | |
5731 | return; | |
5732 | } | |
5733 | ||
5734 | demand_empty_rest_of_line (); | |
5735 | } | |
5736 | ||
5737 | /* The structure used to handle the MRI OPT pseudo-op. */ | |
5738 | ||
5739 | struct opt_action | |
5740 | { | |
5741 | /* The name of the option. */ | |
5742 | const char *name; | |
5743 | ||
5744 | /* If this is not NULL, just call this function. The first argument | |
5745 | is the ARG field of this structure, the second argument is | |
5746 | whether the option was negated. */ | |
31302357 | 5747 | void (*pfn) (int arg, int on); |
252b5132 RH |
5748 | |
5749 | /* If this is not NULL, and the PFN field is NULL, set the variable | |
5750 | this points to. Set it to the ARG field if the option was not | |
5751 | negated, and the NOTARG field otherwise. */ | |
5752 | int *pvar; | |
5753 | ||
5754 | /* The value to pass to PFN or to assign to *PVAR. */ | |
5755 | int arg; | |
5756 | ||
5757 | /* The value to assign to *PVAR if the option is negated. If PFN is | |
5758 | NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then | |
5759 | the option may not be negated. */ | |
5760 | int notarg; | |
5761 | }; | |
5762 | ||
5763 | /* The table used to handle the MRI OPT pseudo-op. */ | |
5764 | ||
31302357 AS |
5765 | static void skip_to_comma (int, int); |
5766 | static void opt_nest (int, int); | |
5767 | static void opt_chip (int, int); | |
5768 | static void opt_list (int, int); | |
5769 | static void opt_list_symbols (int, int); | |
252b5132 RH |
5770 | |
5771 | static const struct opt_action opt_table[] = | |
5772 | { | |
5773 | { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, | |
5774 | ||
5775 | /* We do relaxing, so there is little use for these options. */ | |
5776 | { "b", 0, 0, 0, 0 }, | |
5777 | { "brs", 0, 0, 0, 0 }, | |
5778 | { "brb", 0, 0, 0, 0 }, | |
5779 | { "brl", 0, 0, 0, 0 }, | |
5780 | { "brw", 0, 0, 0, 0 }, | |
5781 | ||
5782 | { "c", 0, 0, 0, 0 }, | |
5783 | { "cex", 0, 0, 0, 0 }, | |
5784 | { "case", 0, &symbols_case_sensitive, 1, 0 }, | |
5785 | { "cl", 0, 0, 0, 0 }, | |
5786 | { "cre", 0, 0, 0, 0 }, | |
5787 | { "d", 0, &flag_keep_locals, 1, 0 }, | |
5788 | { "e", 0, 0, 0, 0 }, | |
5789 | { "f", 0, &flag_short_refs, 1, 0 }, | |
5790 | { "frs", 0, &flag_short_refs, 1, 0 }, | |
5791 | { "frl", 0, &flag_short_refs, 0, 1 }, | |
5792 | { "g", 0, 0, 0, 0 }, | |
5793 | { "i", 0, 0, 0, 0 }, | |
5794 | { "m", 0, 0, 0, 0 }, | |
5795 | { "mex", 0, 0, 0, 0 }, | |
5796 | { "mc", 0, 0, 0, 0 }, | |
5797 | { "md", 0, 0, 0, 0 }, | |
5798 | { "nest", opt_nest, 0, 0, 0 }, | |
5799 | { "next", skip_to_comma, 0, 0, 0 }, | |
5800 | { "o", 0, 0, 0, 0 }, | |
5801 | { "old", 0, 0, 0, 0 }, | |
5802 | { "op", skip_to_comma, 0, 0, 0 }, | |
5803 | { "pco", 0, 0, 0, 0 }, | |
5804 | { "p", opt_chip, 0, 0, 0 }, | |
5805 | { "pcr", 0, 0, 0, 0 }, | |
5806 | { "pcs", 0, 0, 0, 0 }, | |
5807 | { "r", 0, 0, 0, 0 }, | |
5808 | { "quick", 0, &m68k_quick, 1, 0 }, | |
5809 | { "rel32", 0, &m68k_rel32, 1, 0 }, | |
5810 | { "s", opt_list, 0, 0, 0 }, | |
5811 | { "t", opt_list_symbols, 0, 0, 0 }, | |
5812 | { "w", 0, &flag_no_warnings, 0, 1 }, | |
5813 | { "x", 0, 0, 0, 0 } | |
5814 | }; | |
5815 | ||
8fce3f5e | 5816 | #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) |
252b5132 RH |
5817 | |
5818 | /* The MRI OPT pseudo-op. */ | |
5819 | ||
5820 | static void | |
31302357 | 5821 | s_opt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5822 | { |
5823 | do | |
5824 | { | |
5825 | int t; | |
5826 | char *s; | |
5827 | char c; | |
5828 | int i; | |
5829 | const struct opt_action *o; | |
5830 | ||
5831 | SKIP_WHITESPACE (); | |
5832 | ||
5833 | t = 1; | |
5834 | if (*input_line_pointer == '-') | |
5835 | { | |
5836 | ++input_line_pointer; | |
5837 | t = 0; | |
5838 | } | |
5839 | else if (strncasecmp (input_line_pointer, "NO", 2) == 0) | |
5840 | { | |
5841 | input_line_pointer += 2; | |
5842 | t = 0; | |
5843 | } | |
5844 | ||
5845 | s = input_line_pointer; | |
5846 | c = get_symbol_end (); | |
5847 | ||
5848 | for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) | |
5849 | { | |
5850 | if (strcasecmp (s, o->name) == 0) | |
5851 | { | |
5852 | if (o->pfn) | |
5853 | { | |
5854 | /* Restore input_line_pointer now in case the option | |
5855 | takes arguments. */ | |
5856 | *input_line_pointer = c; | |
5857 | (*o->pfn) (o->arg, t); | |
5858 | } | |
5859 | else if (o->pvar != NULL) | |
5860 | { | |
5861 | if (! t && o->arg == o->notarg) | |
5862 | as_bad (_("option `%s' may not be negated"), s); | |
5863 | *input_line_pointer = c; | |
5864 | *o->pvar = t ? o->arg : o->notarg; | |
5865 | } | |
5866 | else | |
5867 | *input_line_pointer = c; | |
5868 | break; | |
5869 | } | |
5870 | } | |
5871 | if (i >= OPTCOUNT) | |
5872 | { | |
5873 | as_bad (_("option `%s' not recognized"), s); | |
5874 | *input_line_pointer = c; | |
5875 | } | |
5876 | } | |
5877 | while (*input_line_pointer++ == ','); | |
5878 | ||
5879 | /* Move back to terminating character. */ | |
5880 | --input_line_pointer; | |
5881 | demand_empty_rest_of_line (); | |
5882 | } | |
5883 | ||
5884 | /* Skip ahead to a comma. This is used for OPT options which we do | |
67c1ffbe | 5885 | not support and which take arguments. */ |
252b5132 RH |
5886 | |
5887 | static void | |
31302357 | 5888 | skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5889 | { |
5890 | while (*input_line_pointer != ',' | |
5891 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5892 | ++input_line_pointer; | |
5893 | } | |
5894 | ||
5895 | /* Handle the OPT NEST=depth option. */ | |
5896 | ||
5897 | static void | |
31302357 | 5898 | opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5899 | { |
5900 | if (*input_line_pointer != '=') | |
5901 | { | |
5902 | as_bad (_("bad format of OPT NEST=depth")); | |
5903 | return; | |
5904 | } | |
5905 | ||
5906 | ++input_line_pointer; | |
5907 | max_macro_nest = get_absolute_expression (); | |
5908 | } | |
5909 | ||
5910 | /* Handle the OPT P=chip option. */ | |
5911 | ||
5912 | static void | |
31302357 | 5913 | opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5914 | { |
5915 | if (*input_line_pointer != '=') | |
5916 | { | |
5917 | /* This is just OPT P, which we do not support. */ | |
5918 | return; | |
5919 | } | |
5920 | ||
5921 | ++input_line_pointer; | |
5922 | mri_chip (); | |
5923 | } | |
5924 | ||
5925 | /* Handle the OPT S option. */ | |
5926 | ||
5927 | static void | |
31302357 | 5928 | opt_list (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5929 | { |
5930 | listing_list (on); | |
5931 | } | |
5932 | ||
5933 | /* Handle the OPT T option. */ | |
5934 | ||
5935 | static void | |
31302357 | 5936 | opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5937 | { |
5938 | if (on) | |
5939 | listing |= LISTING_SYMBOLS; | |
5940 | else | |
8a104df9 | 5941 | listing &= ~LISTING_SYMBOLS; |
252b5132 RH |
5942 | } |
5943 | ||
5944 | /* Handle the MRI REG pseudo-op. */ | |
5945 | ||
5946 | static void | |
31302357 | 5947 | s_reg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5948 | { |
5949 | char *s; | |
5950 | int c; | |
5951 | struct m68k_op rop; | |
5952 | int mask; | |
5953 | char *stop = NULL; | |
5954 | char stopc; | |
5955 | ||
5956 | if (line_label == NULL) | |
5957 | { | |
5958 | as_bad (_("missing label")); | |
5959 | ignore_rest_of_line (); | |
5960 | return; | |
5961 | } | |
5962 | ||
5963 | if (flag_mri) | |
5964 | stop = mri_comment_field (&stopc); | |
5965 | ||
5966 | SKIP_WHITESPACE (); | |
5967 | ||
5968 | s = input_line_pointer; | |
3882b010 | 5969 | while (ISALNUM (*input_line_pointer) |
252b5132 RH |
5970 | #ifdef REGISTER_PREFIX |
5971 | || *input_line_pointer == REGISTER_PREFIX | |
5972 | #endif | |
5973 | || *input_line_pointer == '/' | |
5974 | || *input_line_pointer == '-') | |
5975 | ++input_line_pointer; | |
5976 | c = *input_line_pointer; | |
5977 | *input_line_pointer = '\0'; | |
5978 | ||
5979 | if (m68k_ip_op (s, &rop) != 0) | |
5980 | { | |
5981 | if (rop.error == NULL) | |
5982 | as_bad (_("bad register list")); | |
5983 | else | |
5984 | as_bad (_("bad register list: %s"), rop.error); | |
5985 | *input_line_pointer = c; | |
5986 | ignore_rest_of_line (); | |
5987 | return; | |
5988 | } | |
5989 | ||
5990 | *input_line_pointer = c; | |
5991 | ||
5992 | if (rop.mode == REGLST) | |
5993 | mask = rop.mask; | |
5994 | else if (rop.mode == DREG) | |
5995 | mask = 1 << (rop.reg - DATA0); | |
5996 | else if (rop.mode == AREG) | |
5997 | mask = 1 << (rop.reg - ADDR0 + 8); | |
5998 | else if (rop.mode == FPREG) | |
5999 | mask = 1 << (rop.reg - FP0 + 16); | |
6000 | else if (rop.mode == CONTROL | |
6001 | && rop.reg == FPI) | |
6002 | mask = 1 << 24; | |
6003 | else if (rop.mode == CONTROL | |
6004 | && rop.reg == FPS) | |
6005 | mask = 1 << 25; | |
6006 | else if (rop.mode == CONTROL | |
6007 | && rop.reg == FPC) | |
6008 | mask = 1 << 26; | |
6009 | else | |
6010 | { | |
6011 | as_bad (_("bad register list")); | |
6012 | ignore_rest_of_line (); | |
6013 | return; | |
6014 | } | |
6015 | ||
6016 | S_SET_SEGMENT (line_label, reg_section); | |
6017 | S_SET_VALUE (line_label, ~mask); | |
49309057 | 6018 | symbol_set_frag (line_label, &zero_address_frag); |
252b5132 RH |
6019 | |
6020 | if (flag_mri) | |
6021 | mri_comment_end (stop, stopc); | |
6022 | ||
6023 | demand_empty_rest_of_line (); | |
6024 | } | |
6025 | ||
6026 | /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ | |
6027 | ||
6028 | struct save_opts | |
6029 | { | |
6030 | struct save_opts *next; | |
6031 | int abspcadd; | |
6032 | int symbols_case_sensitive; | |
6033 | int keep_locals; | |
6034 | int short_refs; | |
6035 | int architecture; | |
2da12c60 | 6036 | const enum m68k_register *control_regs; |
252b5132 RH |
6037 | int quick; |
6038 | int rel32; | |
6039 | int listing; | |
6040 | int no_warnings; | |
6041 | /* FIXME: We don't save OPT S. */ | |
6042 | }; | |
6043 | ||
6044 | /* This variable holds the stack of saved options. */ | |
6045 | ||
6046 | static struct save_opts *save_stack; | |
6047 | ||
6048 | /* The MRI SAVE pseudo-op. */ | |
6049 | ||
6050 | static void | |
31302357 | 6051 | s_save (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6052 | { |
6053 | struct save_opts *s; | |
6054 | ||
6055 | s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); | |
6056 | s->abspcadd = m68k_abspcadd; | |
6057 | s->symbols_case_sensitive = symbols_case_sensitive; | |
6058 | s->keep_locals = flag_keep_locals; | |
6059 | s->short_refs = flag_short_refs; | |
6060 | s->architecture = current_architecture; | |
2da12c60 | 6061 | s->control_regs = control_regs; |
252b5132 RH |
6062 | s->quick = m68k_quick; |
6063 | s->rel32 = m68k_rel32; | |
6064 | s->listing = listing; | |
6065 | s->no_warnings = flag_no_warnings; | |
6066 | ||
6067 | s->next = save_stack; | |
6068 | save_stack = s; | |
6069 | ||
6070 | demand_empty_rest_of_line (); | |
6071 | } | |
6072 | ||
6073 | /* The MRI RESTORE pseudo-op. */ | |
6074 | ||
6075 | static void | |
31302357 | 6076 | s_restore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6077 | { |
6078 | struct save_opts *s; | |
6079 | ||
6080 | if (save_stack == NULL) | |
6081 | { | |
6082 | as_bad (_("restore without save")); | |
6083 | ignore_rest_of_line (); | |
6084 | return; | |
6085 | } | |
6086 | ||
6087 | s = save_stack; | |
6088 | save_stack = s->next; | |
6089 | ||
6090 | m68k_abspcadd = s->abspcadd; | |
6091 | symbols_case_sensitive = s->symbols_case_sensitive; | |
6092 | flag_keep_locals = s->keep_locals; | |
6093 | flag_short_refs = s->short_refs; | |
6094 | current_architecture = s->architecture; | |
2da12c60 | 6095 | control_regs = s->control_regs; |
252b5132 RH |
6096 | m68k_quick = s->quick; |
6097 | m68k_rel32 = s->rel32; | |
6098 | listing = s->listing; | |
6099 | flag_no_warnings = s->no_warnings; | |
6100 | ||
6101 | free (s); | |
6102 | ||
6103 | demand_empty_rest_of_line (); | |
6104 | } | |
6105 | ||
6106 | /* Types of MRI structured control directives. */ | |
6107 | ||
6108 | enum mri_control_type | |
6109 | { | |
6110 | mri_for, | |
6111 | mri_if, | |
6112 | mri_repeat, | |
6113 | mri_while | |
6114 | }; | |
6115 | ||
6116 | /* This structure is used to stack the MRI structured control | |
6117 | directives. */ | |
6118 | ||
6119 | struct mri_control_info | |
6120 | { | |
6121 | /* The directive within which this one is enclosed. */ | |
6122 | struct mri_control_info *outer; | |
6123 | ||
6124 | /* The type of directive. */ | |
6125 | enum mri_control_type type; | |
6126 | ||
6127 | /* Whether an ELSE has been in an IF. */ | |
6128 | int else_seen; | |
6129 | ||
6130 | /* The add or sub statement at the end of a FOR. */ | |
6131 | char *incr; | |
6132 | ||
6133 | /* The label of the top of a FOR or REPEAT loop. */ | |
6134 | char *top; | |
6135 | ||
6136 | /* The label to jump to for the next iteration, or the else | |
6137 | expression of a conditional. */ | |
6138 | char *next; | |
6139 | ||
6140 | /* The label to jump to to break out of the loop, or the label past | |
6141 | the end of a conditional. */ | |
6142 | char *bottom; | |
6143 | }; | |
6144 | ||
6145 | /* The stack of MRI structured control directives. */ | |
6146 | ||
6147 | static struct mri_control_info *mri_control_stack; | |
6148 | ||
6149 | /* The current MRI structured control directive index number, used to | |
6150 | generate label names. */ | |
6151 | ||
6152 | static int mri_control_index; | |
6153 | ||
252b5132 RH |
6154 | /* Assemble an instruction for an MRI structured control directive. */ |
6155 | ||
6156 | static void | |
31302357 | 6157 | mri_assemble (char *str) |
252b5132 RH |
6158 | { |
6159 | char *s; | |
6160 | ||
6161 | /* md_assemble expects the opcode to be in lower case. */ | |
6162 | for (s = str; *s != ' ' && *s != '\0'; s++) | |
3882b010 | 6163 | *s = TOLOWER (*s); |
252b5132 RH |
6164 | |
6165 | md_assemble (str); | |
6166 | } | |
6167 | ||
6168 | /* Generate a new MRI label structured control directive label name. */ | |
6169 | ||
6170 | static char * | |
31302357 | 6171 | mri_control_label (void) |
252b5132 RH |
6172 | { |
6173 | char *n; | |
6174 | ||
6175 | n = (char *) xmalloc (20); | |
6176 | sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); | |
6177 | ++mri_control_index; | |
6178 | return n; | |
6179 | } | |
6180 | ||
6181 | /* Create a new MRI structured control directive. */ | |
6182 | ||
6183 | static struct mri_control_info * | |
31302357 | 6184 | push_mri_control (enum mri_control_type type) |
252b5132 RH |
6185 | { |
6186 | struct mri_control_info *n; | |
6187 | ||
6188 | n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); | |
6189 | ||
6190 | n->type = type; | |
6191 | n->else_seen = 0; | |
6192 | if (type == mri_if || type == mri_while) | |
6193 | n->top = NULL; | |
6194 | else | |
6195 | n->top = mri_control_label (); | |
6196 | n->next = mri_control_label (); | |
6197 | n->bottom = mri_control_label (); | |
6198 | ||
6199 | n->outer = mri_control_stack; | |
6200 | mri_control_stack = n; | |
6201 | ||
6202 | return n; | |
6203 | } | |
6204 | ||
6205 | /* Pop off the stack of MRI structured control directives. */ | |
6206 | ||
6207 | static void | |
31302357 | 6208 | pop_mri_control (void) |
252b5132 RH |
6209 | { |
6210 | struct mri_control_info *n; | |
6211 | ||
6212 | n = mri_control_stack; | |
6213 | mri_control_stack = n->outer; | |
6214 | if (n->top != NULL) | |
6215 | free (n->top); | |
6216 | free (n->next); | |
6217 | free (n->bottom); | |
6218 | free (n); | |
6219 | } | |
6220 | ||
6221 | /* Recognize a condition code in an MRI structured control expression. */ | |
6222 | ||
6223 | static int | |
31302357 | 6224 | parse_mri_condition (int *pcc) |
252b5132 RH |
6225 | { |
6226 | char c1, c2; | |
6227 | ||
6228 | know (*input_line_pointer == '<'); | |
6229 | ||
6230 | ++input_line_pointer; | |
6231 | c1 = *input_line_pointer++; | |
6232 | c2 = *input_line_pointer++; | |
6233 | ||
6234 | if (*input_line_pointer != '>') | |
6235 | { | |
6236 | as_bad (_("syntax error in structured control directive")); | |
6237 | return 0; | |
6238 | } | |
6239 | ||
6240 | ++input_line_pointer; | |
6241 | SKIP_WHITESPACE (); | |
6242 | ||
3882b010 L |
6243 | c1 = TOLOWER (c1); |
6244 | c2 = TOLOWER (c2); | |
252b5132 RH |
6245 | |
6246 | *pcc = (c1 << 8) | c2; | |
6247 | ||
6248 | return 1; | |
6249 | } | |
6250 | ||
6251 | /* Parse a single operand in an MRI structured control expression. */ | |
6252 | ||
6253 | static int | |
31302357 AS |
6254 | parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, |
6255 | char **rightstart, char **rightstop) | |
252b5132 RH |
6256 | { |
6257 | char *s; | |
6258 | ||
6259 | SKIP_WHITESPACE (); | |
6260 | ||
6261 | *pcc = -1; | |
6262 | *leftstart = NULL; | |
6263 | *leftstop = NULL; | |
6264 | *rightstart = NULL; | |
6265 | *rightstop = NULL; | |
6266 | ||
6267 | if (*input_line_pointer == '<') | |
6268 | { | |
6269 | /* It's just a condition code. */ | |
6270 | return parse_mri_condition (pcc); | |
6271 | } | |
6272 | ||
6273 | /* Look ahead for the condition code. */ | |
6274 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6275 | { | |
6276 | if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') | |
6277 | break; | |
6278 | } | |
6279 | if (*s == '\0') | |
6280 | { | |
6281 | as_bad (_("missing condition code in structured control directive")); | |
6282 | return 0; | |
6283 | } | |
6284 | ||
6285 | *leftstart = input_line_pointer; | |
6286 | *leftstop = s; | |
6287 | if (*leftstop > *leftstart | |
6288 | && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) | |
6289 | --*leftstop; | |
6290 | ||
6291 | input_line_pointer = s; | |
6292 | if (! parse_mri_condition (pcc)) | |
6293 | return 0; | |
6294 | ||
6295 | /* Look ahead for AND or OR or end of line. */ | |
6296 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6297 | { | |
e1f44d10 NC |
6298 | /* We must make sure we don't misinterpret AND/OR at the end of labels! |
6299 | if d0 <eq> #FOOAND and d1 <ne> #BAROR then | |
6300 | ^^^ ^^ */ | |
8a104df9 KH |
6301 | if ((s == input_line_pointer |
6302 | || *(s-1) == ' ' | |
6303 | || *(s-1) == '\t') | |
6304 | && ((strncasecmp (s, "AND", 3) == 0 | |
6305 | && (s[3] == '.' || ! is_part_of_name (s[3]))) | |
6306 | || (strncasecmp (s, "OR", 2) == 0 | |
6307 | && (s[2] == '.' || ! is_part_of_name (s[2]))))) | |
6308 | break; | |
252b5132 RH |
6309 | } |
6310 | ||
6311 | *rightstart = input_line_pointer; | |
6312 | *rightstop = s; | |
6313 | if (*rightstop > *rightstart | |
6314 | && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) | |
6315 | --*rightstop; | |
6316 | ||
6317 | input_line_pointer = s; | |
6318 | ||
6319 | return 1; | |
6320 | } | |
6321 | ||
6322 | #define MCC(b1, b2) (((b1) << 8) | (b2)) | |
6323 | ||
6324 | /* Swap the sense of a condition. This changes the condition so that | |
6325 | it generates the same result when the operands are swapped. */ | |
6326 | ||
6327 | static int | |
31302357 | 6328 | swap_mri_condition (int cc) |
252b5132 RH |
6329 | { |
6330 | switch (cc) | |
6331 | { | |
6332 | case MCC ('h', 'i'): return MCC ('c', 's'); | |
6333 | case MCC ('l', 's'): return MCC ('c', 'c'); | |
36759679 | 6334 | /* <HS> is an alias for <CC>. */ |
e1f44d10 | 6335 | case MCC ('h', 's'): |
252b5132 | 6336 | case MCC ('c', 'c'): return MCC ('l', 's'); |
36759679 | 6337 | /* <LO> is an alias for <CS>. */ |
e1f44d10 | 6338 | case MCC ('l', 'o'): |
252b5132 RH |
6339 | case MCC ('c', 's'): return MCC ('h', 'i'); |
6340 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6341 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6342 | case MCC ('g', 'e'): return MCC ('l', 'e'); | |
6343 | case MCC ('l', 't'): return MCC ('g', 't'); | |
6344 | case MCC ('g', 't'): return MCC ('l', 't'); | |
6345 | case MCC ('l', 'e'): return MCC ('g', 'e'); | |
36759679 | 6346 | /* Issue a warning for conditions we can not swap. */ |
8fc4ee9b AM |
6347 | case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ |
6348 | case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ | |
e1f44d10 NC |
6349 | case MCC ('v', 'c'): |
6350 | case MCC ('v', 's'): | |
6351 | default : | |
6352 | as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), | |
6353 | (char) (cc >> 8), (char) (cc)); | |
6354 | break; | |
252b5132 RH |
6355 | } |
6356 | return cc; | |
6357 | } | |
6358 | ||
6359 | /* Reverse the sense of a condition. */ | |
6360 | ||
6361 | static int | |
31302357 | 6362 | reverse_mri_condition (int cc) |
252b5132 RH |
6363 | { |
6364 | switch (cc) | |
6365 | { | |
6366 | case MCC ('h', 'i'): return MCC ('l', 's'); | |
6367 | case MCC ('l', 's'): return MCC ('h', 'i'); | |
e1f44d10 NC |
6368 | /* <HS> is an alias for <CC> */ |
6369 | case MCC ('h', 's'): return MCC ('l', 'o'); | |
252b5132 | 6370 | case MCC ('c', 'c'): return MCC ('c', 's'); |
e1f44d10 NC |
6371 | /* <LO> is an alias for <CS> */ |
6372 | case MCC ('l', 'o'): return MCC ('h', 's'); | |
252b5132 RH |
6373 | case MCC ('c', 's'): return MCC ('c', 'c'); |
6374 | case MCC ('n', 'e'): return MCC ('e', 'q'); | |
6375 | case MCC ('e', 'q'): return MCC ('n', 'e'); | |
6376 | case MCC ('v', 'c'): return MCC ('v', 's'); | |
6377 | case MCC ('v', 's'): return MCC ('v', 'c'); | |
6378 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6379 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6380 | case MCC ('g', 'e'): return MCC ('l', 't'); | |
6381 | case MCC ('l', 't'): return MCC ('g', 'e'); | |
6382 | case MCC ('g', 't'): return MCC ('l', 'e'); | |
6383 | case MCC ('l', 'e'): return MCC ('g', 't'); | |
6384 | } | |
6385 | return cc; | |
6386 | } | |
6387 | ||
6388 | /* Build an MRI structured control expression. This generates test | |
6389 | and branch instructions. It goes to TRUELAB if the condition is | |
6390 | true, and to FALSELAB if the condition is false. Exactly one of | |
6391 | TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL | |
6392 | is the size qualifier for the expression. EXTENT is the size to | |
6393 | use for the branch. */ | |
6394 | ||
6395 | static void | |
31302357 AS |
6396 | build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, |
6397 | char *rightstart, char *rightstop, | |
6398 | const char *truelab, const char *falselab, | |
6399 | int extent) | |
252b5132 RH |
6400 | { |
6401 | char *buf; | |
6402 | char *s; | |
6403 | ||
6404 | if (leftstart != NULL) | |
6405 | { | |
6406 | struct m68k_op leftop, rightop; | |
6407 | char c; | |
6408 | ||
6409 | /* Swap the compare operands, if necessary, to produce a legal | |
6410 | m68k compare instruction. Comparing a register operand with | |
6411 | a non-register operand requires the register to be on the | |
6412 | right (cmp, cmpa). Comparing an immediate value with | |
6413 | anything requires the immediate value to be on the left | |
6414 | (cmpi). */ | |
6415 | ||
6416 | c = *leftstop; | |
6417 | *leftstop = '\0'; | |
6418 | (void) m68k_ip_op (leftstart, &leftop); | |
6419 | *leftstop = c; | |
6420 | ||
6421 | c = *rightstop; | |
6422 | *rightstop = '\0'; | |
6423 | (void) m68k_ip_op (rightstart, &rightop); | |
6424 | *rightstop = c; | |
6425 | ||
6426 | if (rightop.mode == IMMED | |
6427 | || ((leftop.mode == DREG || leftop.mode == AREG) | |
6428 | && (rightop.mode != DREG && rightop.mode != AREG))) | |
6429 | { | |
6430 | char *temp; | |
6431 | ||
31302357 AS |
6432 | /* Correct conditional handling: |
6433 | if #1 <lt> d0 then ;means if (1 < d0) | |
6434 | ... | |
6435 | endi | |
e1f44d10 | 6436 | |
31302357 | 6437 | should assemble to: |
e1f44d10 | 6438 | |
31302357 AS |
6439 | cmp #1,d0 if we do *not* swap the operands |
6440 | bgt true we need the swapped condition! | |
6441 | ble false | |
6442 | true: | |
6443 | ... | |
6444 | false: | |
6445 | */ | |
252b5132 RH |
6446 | temp = leftstart; |
6447 | leftstart = rightstart; | |
6448 | rightstart = temp; | |
6449 | temp = leftstop; | |
6450 | leftstop = rightstop; | |
6451 | rightstop = temp; | |
8a104df9 KH |
6452 | } |
6453 | else | |
6454 | { | |
e1f44d10 | 6455 | cc = swap_mri_condition (cc); |
252b5132 RH |
6456 | } |
6457 | } | |
6458 | ||
6459 | if (truelab == NULL) | |
6460 | { | |
6461 | cc = reverse_mri_condition (cc); | |
6462 | truelab = falselab; | |
6463 | } | |
92774660 | 6464 | |
252b5132 RH |
6465 | if (leftstart != NULL) |
6466 | { | |
6467 | buf = (char *) xmalloc (20 | |
6468 | + (leftstop - leftstart) | |
6469 | + (rightstop - rightstart)); | |
6470 | s = buf; | |
6471 | *s++ = 'c'; | |
6472 | *s++ = 'm'; | |
6473 | *s++ = 'p'; | |
6474 | if (qual != '\0') | |
3882b010 | 6475 | *s++ = TOLOWER (qual); |
252b5132 RH |
6476 | *s++ = ' '; |
6477 | memcpy (s, leftstart, leftstop - leftstart); | |
6478 | s += leftstop - leftstart; | |
6479 | *s++ = ','; | |
6480 | memcpy (s, rightstart, rightstop - rightstart); | |
6481 | s += rightstop - rightstart; | |
6482 | *s = '\0'; | |
6483 | mri_assemble (buf); | |
6484 | free (buf); | |
6485 | } | |
92774660 | 6486 | |
252b5132 RH |
6487 | buf = (char *) xmalloc (20 + strlen (truelab)); |
6488 | s = buf; | |
6489 | *s++ = 'b'; | |
6490 | *s++ = cc >> 8; | |
6491 | *s++ = cc & 0xff; | |
6492 | if (extent != '\0') | |
3882b010 | 6493 | *s++ = TOLOWER (extent); |
252b5132 RH |
6494 | *s++ = ' '; |
6495 | strcpy (s, truelab); | |
6496 | mri_assemble (buf); | |
6497 | free (buf); | |
6498 | } | |
6499 | ||
6500 | /* Parse an MRI structured control expression. This generates test | |
6501 | and branch instructions. STOP is where the expression ends. It | |
6502 | goes to TRUELAB if the condition is true, and to FALSELAB if the | |
6503 | condition is false. Exactly one of TRUELAB and FALSELAB will be | |
6504 | NULL, meaning to fall through. QUAL is the size qualifier for the | |
6505 | expression. EXTENT is the size to use for the branch. */ | |
6506 | ||
6507 | static void | |
31302357 AS |
6508 | parse_mri_control_expression (char *stop, int qual, const char *truelab, |
6509 | const char *falselab, int extent) | |
252b5132 RH |
6510 | { |
6511 | int c; | |
6512 | int cc; | |
6513 | char *leftstart; | |
6514 | char *leftstop; | |
6515 | char *rightstart; | |
6516 | char *rightstop; | |
6517 | ||
6518 | c = *stop; | |
6519 | *stop = '\0'; | |
6520 | ||
6521 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6522 | &rightstart, &rightstop)) | |
6523 | { | |
6524 | *stop = c; | |
6525 | return; | |
6526 | } | |
6527 | ||
6528 | if (strncasecmp (input_line_pointer, "AND", 3) == 0) | |
6529 | { | |
6530 | const char *flab; | |
6531 | ||
6532 | if (falselab != NULL) | |
6533 | flab = falselab; | |
6534 | else | |
6535 | flab = mri_control_label (); | |
6536 | ||
6537 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6538 | rightstop, (const char *) NULL, flab, extent); | |
6539 | ||
6540 | input_line_pointer += 3; | |
6541 | if (*input_line_pointer != '.' | |
6542 | || input_line_pointer[1] == '\0') | |
6543 | qual = '\0'; | |
6544 | else | |
6545 | { | |
6546 | qual = input_line_pointer[1]; | |
6547 | input_line_pointer += 2; | |
6548 | } | |
6549 | ||
6550 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6551 | &rightstart, &rightstop)) | |
6552 | { | |
6553 | *stop = c; | |
6554 | return; | |
6555 | } | |
6556 | ||
6557 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6558 | rightstop, truelab, falselab, extent); | |
6559 | ||
6560 | if (falselab == NULL) | |
6561 | colon (flab); | |
6562 | } | |
6563 | else if (strncasecmp (input_line_pointer, "OR", 2) == 0) | |
6564 | { | |
6565 | const char *tlab; | |
6566 | ||
6567 | if (truelab != NULL) | |
6568 | tlab = truelab; | |
6569 | else | |
6570 | tlab = mri_control_label (); | |
6571 | ||
6572 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6573 | rightstop, tlab, (const char *) NULL, extent); | |
6574 | ||
6575 | input_line_pointer += 2; | |
6576 | if (*input_line_pointer != '.' | |
6577 | || input_line_pointer[1] == '\0') | |
6578 | qual = '\0'; | |
6579 | else | |
6580 | { | |
6581 | qual = input_line_pointer[1]; | |
6582 | input_line_pointer += 2; | |
6583 | } | |
6584 | ||
6585 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6586 | &rightstart, &rightstop)) | |
6587 | { | |
6588 | *stop = c; | |
6589 | return; | |
6590 | } | |
6591 | ||
6592 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6593 | rightstop, truelab, falselab, extent); | |
6594 | ||
6595 | if (truelab == NULL) | |
6596 | colon (tlab); | |
6597 | } | |
6598 | else | |
6599 | { | |
6600 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6601 | rightstop, truelab, falselab, extent); | |
6602 | } | |
6603 | ||
6604 | *stop = c; | |
6605 | if (input_line_pointer != stop) | |
6606 | as_bad (_("syntax error in structured control directive")); | |
6607 | } | |
6608 | ||
6609 | /* Handle the MRI IF pseudo-op. This may be a structured control | |
6610 | directive, or it may be a regular assembler conditional, depending | |
6611 | on its operands. */ | |
6612 | ||
6613 | static void | |
31302357 | 6614 | s_mri_if (int qual) |
252b5132 RH |
6615 | { |
6616 | char *s; | |
6617 | int c; | |
6618 | struct mri_control_info *n; | |
6619 | ||
6620 | /* A structured control directive must end with THEN with an | |
6621 | optional qualifier. */ | |
6622 | s = input_line_pointer; | |
e1f44d10 NC |
6623 | /* We only accept '*' as introduction of comments if preceded by white space |
6624 | or at first column of a line (I think this can't actually happen here?) | |
6625 | This is important when assembling: | |
6626 | if d0 <ne> 12(a0,d0*2) then | |
36759679 | 6627 | if d0 <ne> #CONST*20 then. */ |
31302357 AS |
6628 | while (! (is_end_of_line[(unsigned char) *s] |
6629 | || (flag_mri | |
6630 | && *s == '*' | |
6631 | && (s == input_line_pointer | |
6632 | || *(s-1) == ' ' | |
6633 | || *(s-1) == '\t')))) | |
252b5132 RH |
6634 | ++s; |
6635 | --s; | |
6636 | while (s > input_line_pointer && (*s == ' ' || *s == '\t')) | |
6637 | --s; | |
6638 | ||
6639 | if (s - input_line_pointer > 1 | |
6640 | && s[-1] == '.') | |
6641 | s -= 2; | |
6642 | ||
6643 | if (s - input_line_pointer < 3 | |
6644 | || strncasecmp (s - 3, "THEN", 4) != 0) | |
6645 | { | |
6646 | if (qual != '\0') | |
6647 | { | |
6648 | as_bad (_("missing then")); | |
6649 | ignore_rest_of_line (); | |
6650 | return; | |
6651 | } | |
6652 | ||
6653 | /* It's a conditional. */ | |
6654 | s_if (O_ne); | |
6655 | return; | |
6656 | } | |
6657 | ||
6658 | /* Since this might be a conditional if, this pseudo-op will be | |
6659 | called even if we are supported to be ignoring input. Double | |
6660 | check now. Clobber *input_line_pointer so that ignore_input | |
6661 | thinks that this is not a special pseudo-op. */ | |
6662 | c = *input_line_pointer; | |
6663 | *input_line_pointer = 0; | |
6664 | if (ignore_input ()) | |
6665 | { | |
6666 | *input_line_pointer = c; | |
6667 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6668 | ++input_line_pointer; | |
6669 | demand_empty_rest_of_line (); | |
6670 | return; | |
6671 | } | |
6672 | *input_line_pointer = c; | |
6673 | ||
6674 | n = push_mri_control (mri_if); | |
6675 | ||
6676 | parse_mri_control_expression (s - 3, qual, (const char *) NULL, | |
6677 | n->next, s[1] == '.' ? s[2] : '\0'); | |
6678 | ||
6679 | if (s[1] == '.') | |
6680 | input_line_pointer = s + 3; | |
6681 | else | |
6682 | input_line_pointer = s + 1; | |
6683 | ||
6684 | if (flag_mri) | |
6685 | { | |
6686 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6687 | ++input_line_pointer; | |
6688 | } | |
6689 | ||
6690 | demand_empty_rest_of_line (); | |
6691 | } | |
6692 | ||
6693 | /* Handle the MRI else pseudo-op. If we are currently doing an MRI | |
6694 | structured IF, associate the ELSE with the IF. Otherwise, assume | |
6695 | it is a conditional else. */ | |
6696 | ||
6697 | static void | |
31302357 | 6698 | s_mri_else (int qual) |
252b5132 RH |
6699 | { |
6700 | int c; | |
6701 | char *buf; | |
6702 | char q[2]; | |
6703 | ||
6704 | if (qual == '\0' | |
6705 | && (mri_control_stack == NULL | |
6706 | || mri_control_stack->type != mri_if | |
6707 | || mri_control_stack->else_seen)) | |
6708 | { | |
6709 | s_else (0); | |
6710 | return; | |
6711 | } | |
6712 | ||
6713 | c = *input_line_pointer; | |
6714 | *input_line_pointer = 0; | |
6715 | if (ignore_input ()) | |
6716 | { | |
6717 | *input_line_pointer = c; | |
6718 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6719 | ++input_line_pointer; | |
6720 | demand_empty_rest_of_line (); | |
6721 | return; | |
6722 | } | |
6723 | *input_line_pointer = c; | |
6724 | ||
6725 | if (mri_control_stack == NULL | |
6726 | || mri_control_stack->type != mri_if | |
6727 | || mri_control_stack->else_seen) | |
6728 | { | |
6729 | as_bad (_("else without matching if")); | |
6730 | ignore_rest_of_line (); | |
6731 | return; | |
6732 | } | |
6733 | ||
6734 | mri_control_stack->else_seen = 1; | |
6735 | ||
6736 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); | |
3882b010 | 6737 | q[0] = TOLOWER (qual); |
252b5132 RH |
6738 | q[1] = '\0'; |
6739 | sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); | |
6740 | mri_assemble (buf); | |
6741 | free (buf); | |
6742 | ||
6743 | colon (mri_control_stack->next); | |
6744 | ||
6745 | if (flag_mri) | |
6746 | { | |
6747 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6748 | ++input_line_pointer; | |
6749 | } | |
6750 | ||
6751 | demand_empty_rest_of_line (); | |
6752 | } | |
6753 | ||
6754 | /* Handle the MRI ENDI pseudo-op. */ | |
6755 | ||
6756 | static void | |
31302357 | 6757 | s_mri_endi (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6758 | { |
6759 | if (mri_control_stack == NULL | |
6760 | || mri_control_stack->type != mri_if) | |
6761 | { | |
6762 | as_bad (_("endi without matching if")); | |
6763 | ignore_rest_of_line (); | |
6764 | return; | |
6765 | } | |
6766 | ||
6767 | /* ignore_input will not return true for ENDI, so we don't need to | |
6768 | worry about checking it again here. */ | |
6769 | ||
6770 | if (! mri_control_stack->else_seen) | |
6771 | colon (mri_control_stack->next); | |
6772 | colon (mri_control_stack->bottom); | |
6773 | ||
6774 | pop_mri_control (); | |
6775 | ||
6776 | if (flag_mri) | |
6777 | { | |
6778 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6779 | ++input_line_pointer; | |
6780 | } | |
6781 | ||
6782 | demand_empty_rest_of_line (); | |
6783 | } | |
6784 | ||
6785 | /* Handle the MRI BREAK pseudo-op. */ | |
6786 | ||
6787 | static void | |
31302357 | 6788 | s_mri_break (int extent) |
252b5132 RH |
6789 | { |
6790 | struct mri_control_info *n; | |
6791 | char *buf; | |
6792 | char ex[2]; | |
6793 | ||
6794 | n = mri_control_stack; | |
6795 | while (n != NULL | |
6796 | && n->type != mri_for | |
6797 | && n->type != mri_repeat | |
6798 | && n->type != mri_while) | |
6799 | n = n->outer; | |
6800 | if (n == NULL) | |
6801 | { | |
6802 | as_bad (_("break outside of structured loop")); | |
6803 | ignore_rest_of_line (); | |
6804 | return; | |
6805 | } | |
6806 | ||
6807 | buf = (char *) xmalloc (20 + strlen (n->bottom)); | |
3882b010 | 6808 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6809 | ex[1] = '\0'; |
6810 | sprintf (buf, "bra%s %s", ex, n->bottom); | |
6811 | mri_assemble (buf); | |
6812 | free (buf); | |
6813 | ||
6814 | if (flag_mri) | |
6815 | { | |
6816 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6817 | ++input_line_pointer; | |
6818 | } | |
6819 | ||
6820 | demand_empty_rest_of_line (); | |
6821 | } | |
6822 | ||
6823 | /* Handle the MRI NEXT pseudo-op. */ | |
6824 | ||
6825 | static void | |
31302357 | 6826 | s_mri_next (int extent) |
252b5132 RH |
6827 | { |
6828 | struct mri_control_info *n; | |
6829 | char *buf; | |
6830 | char ex[2]; | |
6831 | ||
6832 | n = mri_control_stack; | |
6833 | while (n != NULL | |
6834 | && n->type != mri_for | |
6835 | && n->type != mri_repeat | |
6836 | && n->type != mri_while) | |
6837 | n = n->outer; | |
6838 | if (n == NULL) | |
6839 | { | |
6840 | as_bad (_("next outside of structured loop")); | |
6841 | ignore_rest_of_line (); | |
6842 | return; | |
6843 | } | |
6844 | ||
6845 | buf = (char *) xmalloc (20 + strlen (n->next)); | |
3882b010 | 6846 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6847 | ex[1] = '\0'; |
6848 | sprintf (buf, "bra%s %s", ex, n->next); | |
6849 | mri_assemble (buf); | |
6850 | free (buf); | |
6851 | ||
6852 | if (flag_mri) | |
6853 | { | |
6854 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6855 | ++input_line_pointer; | |
6856 | } | |
6857 | ||
6858 | demand_empty_rest_of_line (); | |
6859 | } | |
6860 | ||
6861 | /* Handle the MRI FOR pseudo-op. */ | |
6862 | ||
6863 | static void | |
31302357 | 6864 | s_mri_for (int qual) |
252b5132 RH |
6865 | { |
6866 | const char *varstart, *varstop; | |
6867 | const char *initstart, *initstop; | |
6868 | const char *endstart, *endstop; | |
6869 | const char *bystart, *bystop; | |
6870 | int up; | |
6871 | int by; | |
6872 | int extent; | |
6873 | struct mri_control_info *n; | |
6874 | char *buf; | |
6875 | char *s; | |
6876 | char ex[2]; | |
6877 | ||
6878 | /* The syntax is | |
6879 | FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e | |
6880 | */ | |
6881 | ||
6882 | SKIP_WHITESPACE (); | |
6883 | varstart = input_line_pointer; | |
6884 | ||
6885 | /* Look for the '='. */ | |
6886 | while (! is_end_of_line[(unsigned char) *input_line_pointer] | |
6887 | && *input_line_pointer != '=') | |
6888 | ++input_line_pointer; | |
6889 | if (*input_line_pointer != '=') | |
6890 | { | |
6891 | as_bad (_("missing =")); | |
6892 | ignore_rest_of_line (); | |
6893 | return; | |
6894 | } | |
6895 | ||
6896 | varstop = input_line_pointer; | |
6897 | if (varstop > varstart | |
6898 | && (varstop[-1] == ' ' || varstop[-1] == '\t')) | |
6899 | --varstop; | |
6900 | ||
6901 | ++input_line_pointer; | |
6902 | ||
6903 | initstart = input_line_pointer; | |
6904 | ||
6905 | /* Look for TO or DOWNTO. */ | |
6906 | up = 1; | |
6907 | initstop = NULL; | |
6908 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6909 | { | |
6910 | if (strncasecmp (input_line_pointer, "TO", 2) == 0 | |
6911 | && ! is_part_of_name (input_line_pointer[2])) | |
6912 | { | |
6913 | initstop = input_line_pointer; | |
6914 | input_line_pointer += 2; | |
6915 | break; | |
6916 | } | |
6917 | if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 | |
6918 | && ! is_part_of_name (input_line_pointer[6])) | |
6919 | { | |
6920 | initstop = input_line_pointer; | |
6921 | up = 0; | |
6922 | input_line_pointer += 6; | |
6923 | break; | |
6924 | } | |
6925 | ++input_line_pointer; | |
6926 | } | |
6927 | if (initstop == NULL) | |
6928 | { | |
6929 | as_bad (_("missing to or downto")); | |
6930 | ignore_rest_of_line (); | |
6931 | return; | |
6932 | } | |
6933 | if (initstop > initstart | |
6934 | && (initstop[-1] == ' ' || initstop[-1] == '\t')) | |
6935 | --initstop; | |
6936 | ||
6937 | SKIP_WHITESPACE (); | |
6938 | endstart = input_line_pointer; | |
6939 | ||
6940 | /* Look for BY or DO. */ | |
6941 | by = 0; | |
6942 | endstop = NULL; | |
6943 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6944 | { | |
6945 | if (strncasecmp (input_line_pointer, "BY", 2) == 0 | |
6946 | && ! is_part_of_name (input_line_pointer[2])) | |
6947 | { | |
6948 | endstop = input_line_pointer; | |
6949 | by = 1; | |
6950 | input_line_pointer += 2; | |
6951 | break; | |
6952 | } | |
6953 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
6954 | && (input_line_pointer[2] == '.' | |
6955 | || ! is_part_of_name (input_line_pointer[2]))) | |
6956 | { | |
6957 | endstop = input_line_pointer; | |
6958 | input_line_pointer += 2; | |
6959 | break; | |
6960 | } | |
6961 | ++input_line_pointer; | |
6962 | } | |
6963 | if (endstop == NULL) | |
6964 | { | |
6965 | as_bad (_("missing do")); | |
6966 | ignore_rest_of_line (); | |
6967 | return; | |
6968 | } | |
6969 | if (endstop > endstart | |
6970 | && (endstop[-1] == ' ' || endstop[-1] == '\t')) | |
6971 | --endstop; | |
6972 | ||
6973 | if (! by) | |
6974 | { | |
6975 | bystart = "#1"; | |
6976 | bystop = bystart + 2; | |
6977 | } | |
6978 | else | |
6979 | { | |
6980 | SKIP_WHITESPACE (); | |
6981 | bystart = input_line_pointer; | |
6982 | ||
6983 | /* Look for DO. */ | |
6984 | bystop = NULL; | |
6985 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6986 | { | |
6987 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
6988 | && (input_line_pointer[2] == '.' | |
6989 | || ! is_part_of_name (input_line_pointer[2]))) | |
6990 | { | |
6991 | bystop = input_line_pointer; | |
6992 | input_line_pointer += 2; | |
6993 | break; | |
6994 | } | |
6995 | ++input_line_pointer; | |
6996 | } | |
6997 | if (bystop == NULL) | |
6998 | { | |
6999 | as_bad (_("missing do")); | |
7000 | ignore_rest_of_line (); | |
7001 | return; | |
7002 | } | |
7003 | if (bystop > bystart | |
7004 | && (bystop[-1] == ' ' || bystop[-1] == '\t')) | |
7005 | --bystop; | |
7006 | } | |
7007 | ||
7008 | if (*input_line_pointer != '.') | |
7009 | extent = '\0'; | |
7010 | else | |
7011 | { | |
7012 | extent = input_line_pointer[1]; | |
7013 | input_line_pointer += 2; | |
7014 | } | |
7015 | ||
7016 | /* We have fully parsed the FOR operands. Now build the loop. */ | |
252b5132 RH |
7017 | n = push_mri_control (mri_for); |
7018 | ||
7019 | buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); | |
7020 | ||
36759679 | 7021 | /* Move init,var. */ |
252b5132 RH |
7022 | s = buf; |
7023 | *s++ = 'm'; | |
7024 | *s++ = 'o'; | |
7025 | *s++ = 'v'; | |
7026 | *s++ = 'e'; | |
7027 | if (qual != '\0') | |
3882b010 | 7028 | *s++ = TOLOWER (qual); |
252b5132 RH |
7029 | *s++ = ' '; |
7030 | memcpy (s, initstart, initstop - initstart); | |
7031 | s += initstop - initstart; | |
7032 | *s++ = ','; | |
7033 | memcpy (s, varstart, varstop - varstart); | |
7034 | s += varstop - varstart; | |
7035 | *s = '\0'; | |
7036 | mri_assemble (buf); | |
7037 | ||
7038 | colon (n->top); | |
7039 | ||
36759679 | 7040 | /* cmp end,var. */ |
252b5132 RH |
7041 | s = buf; |
7042 | *s++ = 'c'; | |
7043 | *s++ = 'm'; | |
7044 | *s++ = 'p'; | |
7045 | if (qual != '\0') | |
3882b010 | 7046 | *s++ = TOLOWER (qual); |
252b5132 RH |
7047 | *s++ = ' '; |
7048 | memcpy (s, endstart, endstop - endstart); | |
7049 | s += endstop - endstart; | |
7050 | *s++ = ','; | |
7051 | memcpy (s, varstart, varstop - varstart); | |
7052 | s += varstop - varstart; | |
7053 | *s = '\0'; | |
7054 | mri_assemble (buf); | |
7055 | ||
36759679 | 7056 | /* bcc bottom. */ |
3882b010 | 7057 | ex[0] = TOLOWER (extent); |
252b5132 RH |
7058 | ex[1] = '\0'; |
7059 | if (up) | |
7060 | sprintf (buf, "blt%s %s", ex, n->bottom); | |
7061 | else | |
7062 | sprintf (buf, "bgt%s %s", ex, n->bottom); | |
7063 | mri_assemble (buf); | |
7064 | ||
7065 | /* Put together the add or sub instruction used by ENDF. */ | |
7066 | s = buf; | |
7067 | if (up) | |
7068 | strcpy (s, "add"); | |
7069 | else | |
7070 | strcpy (s, "sub"); | |
7071 | s += 3; | |
7072 | if (qual != '\0') | |
3882b010 | 7073 | *s++ = TOLOWER (qual); |
252b5132 RH |
7074 | *s++ = ' '; |
7075 | memcpy (s, bystart, bystop - bystart); | |
7076 | s += bystop - bystart; | |
7077 | *s++ = ','; | |
7078 | memcpy (s, varstart, varstop - varstart); | |
7079 | s += varstop - varstart; | |
7080 | *s = '\0'; | |
7081 | n->incr = buf; | |
7082 | ||
7083 | if (flag_mri) | |
7084 | { | |
7085 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7086 | ++input_line_pointer; | |
7087 | } | |
7088 | ||
7089 | demand_empty_rest_of_line (); | |
7090 | } | |
7091 | ||
7092 | /* Handle the MRI ENDF pseudo-op. */ | |
7093 | ||
7094 | static void | |
31302357 | 7095 | s_mri_endf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7096 | { |
7097 | if (mri_control_stack == NULL | |
7098 | || mri_control_stack->type != mri_for) | |
7099 | { | |
7100 | as_bad (_("endf without for")); | |
7101 | ignore_rest_of_line (); | |
7102 | return; | |
7103 | } | |
7104 | ||
7105 | colon (mri_control_stack->next); | |
7106 | ||
7107 | mri_assemble (mri_control_stack->incr); | |
7108 | ||
7109 | sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); | |
7110 | mri_assemble (mri_control_stack->incr); | |
7111 | ||
7112 | free (mri_control_stack->incr); | |
7113 | ||
7114 | colon (mri_control_stack->bottom); | |
7115 | ||
7116 | pop_mri_control (); | |
7117 | ||
7118 | if (flag_mri) | |
7119 | { | |
7120 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7121 | ++input_line_pointer; | |
7122 | } | |
7123 | ||
7124 | demand_empty_rest_of_line (); | |
7125 | } | |
7126 | ||
7127 | /* Handle the MRI REPEAT pseudo-op. */ | |
7128 | ||
7129 | static void | |
31302357 | 7130 | s_mri_repeat (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7131 | { |
7132 | struct mri_control_info *n; | |
7133 | ||
7134 | n = push_mri_control (mri_repeat); | |
7135 | colon (n->top); | |
7136 | if (flag_mri) | |
7137 | { | |
7138 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7139 | ++input_line_pointer; | |
7140 | } | |
7141 | demand_empty_rest_of_line (); | |
7142 | } | |
7143 | ||
7144 | /* Handle the MRI UNTIL pseudo-op. */ | |
7145 | ||
7146 | static void | |
31302357 | 7147 | s_mri_until (int qual) |
252b5132 RH |
7148 | { |
7149 | char *s; | |
7150 | ||
7151 | if (mri_control_stack == NULL | |
7152 | || mri_control_stack->type != mri_repeat) | |
7153 | { | |
7154 | as_bad (_("until without repeat")); | |
7155 | ignore_rest_of_line (); | |
7156 | return; | |
7157 | } | |
7158 | ||
7159 | colon (mri_control_stack->next); | |
7160 | ||
7161 | for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) | |
7162 | ; | |
7163 | ||
7164 | parse_mri_control_expression (s, qual, (const char *) NULL, | |
7165 | mri_control_stack->top, '\0'); | |
7166 | ||
7167 | colon (mri_control_stack->bottom); | |
7168 | ||
7169 | input_line_pointer = s; | |
7170 | ||
7171 | pop_mri_control (); | |
7172 | ||
7173 | if (flag_mri) | |
7174 | { | |
7175 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7176 | ++input_line_pointer; | |
7177 | } | |
7178 | ||
7179 | demand_empty_rest_of_line (); | |
7180 | } | |
7181 | ||
7182 | /* Handle the MRI WHILE pseudo-op. */ | |
7183 | ||
7184 | static void | |
31302357 | 7185 | s_mri_while (int qual) |
252b5132 RH |
7186 | { |
7187 | char *s; | |
7188 | ||
7189 | struct mri_control_info *n; | |
7190 | ||
7191 | s = input_line_pointer; | |
e1f44d10 NC |
7192 | /* We only accept '*' as introduction of comments if preceded by white space |
7193 | or at first column of a line (I think this can't actually happen here?) | |
7194 | This is important when assembling: | |
7195 | while d0 <ne> 12(a0,d0*2) do | |
36759679 | 7196 | while d0 <ne> #CONST*20 do. */ |
8a104df9 KH |
7197 | while (! (is_end_of_line[(unsigned char) *s] |
7198 | || (flag_mri | |
7199 | && *s == '*' | |
7200 | && (s == input_line_pointer | |
7201 | || *(s-1) == ' ' | |
7202 | || *(s-1) == '\t')))) | |
252b5132 RH |
7203 | s++; |
7204 | --s; | |
7205 | while (*s == ' ' || *s == '\t') | |
7206 | --s; | |
7207 | if (s - input_line_pointer > 1 | |
7208 | && s[-1] == '.') | |
7209 | s -= 2; | |
7210 | if (s - input_line_pointer < 2 | |
7211 | || strncasecmp (s - 1, "DO", 2) != 0) | |
7212 | { | |
7213 | as_bad (_("missing do")); | |
7214 | ignore_rest_of_line (); | |
7215 | return; | |
7216 | } | |
7217 | ||
7218 | n = push_mri_control (mri_while); | |
7219 | ||
7220 | colon (n->next); | |
7221 | ||
7222 | parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, | |
7223 | s[1] == '.' ? s[2] : '\0'); | |
7224 | ||
7225 | input_line_pointer = s + 1; | |
7226 | if (*input_line_pointer == '.') | |
7227 | input_line_pointer += 2; | |
7228 | ||
7229 | if (flag_mri) | |
7230 | { | |
7231 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7232 | ++input_line_pointer; | |
7233 | } | |
7234 | ||
7235 | demand_empty_rest_of_line (); | |
7236 | } | |
7237 | ||
7238 | /* Handle the MRI ENDW pseudo-op. */ | |
7239 | ||
7240 | static void | |
31302357 | 7241 | s_mri_endw (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7242 | { |
7243 | char *buf; | |
7244 | ||
7245 | if (mri_control_stack == NULL | |
7246 | || mri_control_stack->type != mri_while) | |
7247 | { | |
7248 | as_bad (_("endw without while")); | |
7249 | ignore_rest_of_line (); | |
7250 | return; | |
7251 | } | |
7252 | ||
7253 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); | |
7254 | sprintf (buf, "bra %s", mri_control_stack->next); | |
7255 | mri_assemble (buf); | |
7256 | free (buf); | |
7257 | ||
7258 | colon (mri_control_stack->bottom); | |
7259 | ||
7260 | pop_mri_control (); | |
7261 | ||
7262 | if (flag_mri) | |
7263 | { | |
7264 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7265 | ++input_line_pointer; | |
7266 | } | |
7267 | ||
7268 | demand_empty_rest_of_line (); | |
7269 | } | |
7270 | \f | |
266abb8f NS |
7271 | /* Parse a .cpu directive. */ |
7272 | ||
7273 | static void | |
7274 | s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) | |
7275 | { | |
7276 | char saved_char; | |
7277 | char *name; | |
7278 | ||
7279 | if (initialized) | |
7280 | { | |
7281 | as_bad (_("already assembled instructions")); | |
7282 | ignore_rest_of_line (); | |
7283 | return; | |
7284 | } | |
7285 | ||
7286 | name = input_line_pointer; | |
7287 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
7288 | input_line_pointer++; | |
7289 | saved_char = *input_line_pointer; | |
7290 | *input_line_pointer = 0; | |
7291 | ||
7292 | m68k_set_cpu (name, 1, 0); | |
7293 | ||
7294 | *input_line_pointer = saved_char; | |
7295 | demand_empty_rest_of_line (); | |
7296 | return; | |
7297 | } | |
7298 | ||
7299 | /* Parse a .arch directive. */ | |
7300 | ||
7301 | static void | |
7302 | s_m68k_arch (int ignored ATTRIBUTE_UNUSED) | |
7303 | { | |
7304 | char saved_char; | |
7305 | char *name; | |
7306 | ||
7307 | if (initialized) | |
7308 | { | |
7309 | as_bad (_("already assembled instructions")); | |
7310 | ignore_rest_of_line (); | |
7311 | return; | |
7312 | } | |
7313 | ||
7314 | name = input_line_pointer; | |
7315 | while (*input_line_pointer && *input_line_pointer != ',' | |
7316 | && !ISSPACE (*input_line_pointer)) | |
7317 | input_line_pointer++; | |
7318 | saved_char = *input_line_pointer; | |
7319 | *input_line_pointer = 0; | |
7320 | ||
7321 | if (m68k_set_arch (name, 1, 0)) | |
7322 | { | |
7323 | /* Scan extensions. */ | |
7324 | do | |
7325 | { | |
7326 | *input_line_pointer++ = saved_char; | |
7327 | if (!*input_line_pointer || ISSPACE (*input_line_pointer)) | |
7328 | break; | |
7329 | name = input_line_pointer; | |
7330 | while (*input_line_pointer && *input_line_pointer != ',' | |
7331 | && !ISSPACE (*input_line_pointer)) | |
7332 | input_line_pointer++; | |
7333 | saved_char = *input_line_pointer; | |
7334 | *input_line_pointer = 0; | |
7335 | } | |
7336 | while (m68k_set_extension (name, 1, 0)); | |
7337 | } | |
7338 | ||
7339 | *input_line_pointer = saved_char; | |
7340 | demand_empty_rest_of_line (); | |
7341 | return; | |
7342 | } | |
7343 | \f | |
7344 | /* Lookup a cpu name in TABLE and return the slot found. Return NULL | |
7345 | if none is found, the caller is responsible for emitting an error | |
7346 | message. If ALLOW_M is non-zero, we allow an initial 'm' on the | |
7347 | cpu name, if it begins with a '6' (possibly skipping an intervening | |
7348 | 'c'. We also allow a 'c' in the same place. if NEGATED is | |
7349 | non-zero, we accept a leading 'no-' and *NEGATED is set to true, if | |
7350 | the option is indeed negated. */ | |
7351 | ||
7352 | static const struct m68k_cpu * | |
7353 | m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, | |
7354 | int allow_m, int *negated) | |
7355 | { | |
7356 | /* allow negated value? */ | |
7357 | if (negated) | |
7358 | { | |
7359 | *negated = 0; | |
7360 | ||
7361 | if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') | |
7362 | { | |
7363 | arg += 3; | |
7364 | *negated = 1; | |
7365 | } | |
7366 | } | |
7367 | ||
7368 | /* Remove 'm' or 'mc' prefix from 68k variants. */ | |
7369 | if (allow_m) | |
7370 | { | |
7371 | if (arg[0] == 'm') | |
7372 | { | |
7373 | if (arg[1] == '6') | |
7374 | arg += 1; | |
7375 | else if (arg[1] == 'c' && arg[2] == '6') | |
7376 | arg += 2; | |
7377 | } | |
7378 | } | |
7379 | else if (arg[0] == 'c' && arg[1] == '6') | |
7380 | arg += 1; | |
7381 | ||
7382 | for (; table->name; table++) | |
7383 | if (!strcmp (arg, table->name)) | |
2da12c60 NS |
7384 | { |
7385 | if (table->alias < -1 || table->alias > 1) | |
7386 | as_bad (_("`%s' is deprecated, use `%s'"), | |
7387 | table->name, table[table->alias < 0 ? 1 : -1].name); | |
7388 | return table; | |
7389 | } | |
266abb8f NS |
7390 | return 0; |
7391 | } | |
7392 | ||
bfbba8e4 | 7393 | /* Set the cpu, issuing errors if it is unrecognized. */ |
266abb8f NS |
7394 | |
7395 | static int | |
7396 | m68k_set_cpu (char const *name, int allow_m, int silent) | |
7397 | { | |
7398 | const struct m68k_cpu *cpu; | |
7399 | ||
7400 | cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); | |
7401 | ||
7402 | if (!cpu) | |
7403 | { | |
7404 | if (!silent) | |
7405 | as_bad (_("cpu `%s' unrecognized"), name); | |
7406 | return 0; | |
7407 | } | |
266abb8f NS |
7408 | selected_cpu = cpu; |
7409 | return 1; | |
7410 | } | |
7411 | ||
bfbba8e4 | 7412 | /* Set the architecture, issuing errors if it is unrecognized. */ |
266abb8f NS |
7413 | |
7414 | static int | |
7415 | m68k_set_arch (char const *name, int allow_m, int silent) | |
7416 | { | |
7417 | const struct m68k_cpu *arch; | |
7418 | ||
7419 | arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); | |
7420 | ||
7421 | if (!arch) | |
7422 | { | |
7423 | if (!silent) | |
7424 | as_bad (_("architecture `%s' unrecognized"), name); | |
7425 | return 0; | |
7426 | } | |
266abb8f NS |
7427 | selected_arch = arch; |
7428 | return 1; | |
7429 | } | |
7430 | ||
7431 | /* Set the architecture extension, issuing errors if it is | |
7432 | unrecognized, or invalid */ | |
7433 | ||
7434 | static int | |
7435 | m68k_set_extension (char const *name, int allow_m, int silent) | |
7436 | { | |
7437 | int negated; | |
7438 | const struct m68k_cpu *ext; | |
7439 | ||
7440 | ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); | |
7441 | ||
7442 | if (!ext) | |
7443 | { | |
7444 | if (!silent) | |
7445 | as_bad (_("extension `%s' unrecognized"), name); | |
7446 | return 0; | |
7447 | } | |
7448 | ||
7449 | if (negated) | |
87298967 NS |
7450 | not_current_architecture |= (ext->control_regs |
7451 | ? *(unsigned *)ext->control_regs: ext->arch); | |
266abb8f NS |
7452 | else |
7453 | current_architecture |= ext->arch; | |
7454 | return 1; | |
7455 | } | |
7456 | ||
31302357 AS |
7457 | /* md_parse_option |
7458 | Invocation line includes a switch not recognized by the base assembler. | |
266abb8f | 7459 | */ |
252b5132 RH |
7460 | |
7461 | #ifdef OBJ_ELF | |
5a38dc70 | 7462 | const char *md_shortopts = "lSA:m:kQ:V"; |
252b5132 | 7463 | #else |
5a38dc70 | 7464 | const char *md_shortopts = "lSA:m:k"; |
252b5132 RH |
7465 | #endif |
7466 | ||
7467 | struct option md_longopts[] = { | |
7468 | #define OPTION_PIC (OPTION_MD_BASE) | |
7469 | {"pic", no_argument, NULL, OPTION_PIC}, | |
7470 | #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) | |
7471 | {"register-prefix-optional", no_argument, NULL, | |
7472 | OPTION_REGISTER_PREFIX_OPTIONAL}, | |
7473 | #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) | |
7474 | {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, | |
7475 | #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) | |
7476 | {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, | |
7477 | #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) | |
7478 | {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, | |
7479 | #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) | |
7480 | {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, | |
7481 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) | |
7482 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, | |
28e7409f NC |
7483 | #define OPTION_PCREL (OPTION_MD_BASE + 7) |
7484 | {"pcrel", no_argument, NULL, OPTION_PCREL}, | |
252b5132 RH |
7485 | {NULL, no_argument, NULL, 0} |
7486 | }; | |
bc805888 | 7487 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
7488 | |
7489 | int | |
31302357 | 7490 | md_parse_option (int c, char *arg) |
252b5132 RH |
7491 | { |
7492 | switch (c) | |
7493 | { | |
7494 | case 'l': /* -l means keep external to 2 bit offset | |
36759679 | 7495 | rather than 16 bit one. */ |
252b5132 RH |
7496 | flag_short_refs = 1; |
7497 | break; | |
7498 | ||
7499 | case 'S': /* -S means that jbsr's always turn into | |
7500 | jsr's. */ | |
7501 | flag_long_jumps = 1; | |
7502 | break; | |
7503 | ||
28e7409f NC |
7504 | case OPTION_PCREL: /* --pcrel means never turn PC-relative |
7505 | branches into absolute jumps. */ | |
7506 | flag_keep_pcrel = 1; | |
7507 | break; | |
7508 | ||
252b5132 RH |
7509 | case OPTION_PIC: |
7510 | case 'k': | |
7511 | flag_want_pic = 1; | |
36759679 | 7512 | break; /* -pic, Position Independent Code. */ |
252b5132 RH |
7513 | |
7514 | case OPTION_REGISTER_PREFIX_OPTIONAL: | |
7515 | flag_reg_prefix_optional = 1; | |
7516 | reg_prefix_optional_seen = 1; | |
7517 | break; | |
7518 | ||
7519 | /* -V: SVR4 argument to print version ID. */ | |
7520 | case 'V': | |
7521 | print_version_id (); | |
7522 | break; | |
7523 | ||
7524 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
7525 | should be emitted or not. FIXME: Not implemented. */ | |
7526 | case 'Q': | |
7527 | break; | |
7528 | ||
7529 | case OPTION_BITWISE_OR: | |
7530 | { | |
7531 | char *n, *t; | |
7532 | const char *s; | |
7533 | ||
7534 | n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); | |
7535 | t = n; | |
7536 | for (s = m68k_comment_chars; *s != '\0'; s++) | |
7537 | if (*s != '|') | |
7538 | *t++ = *s; | |
7539 | *t = '\0'; | |
7540 | m68k_comment_chars = n; | |
7541 | } | |
7542 | break; | |
7543 | ||
7544 | case OPTION_BASE_SIZE_DEFAULT_16: | |
7545 | m68k_index_width_default = SIZE_WORD; | |
7546 | break; | |
7547 | ||
7548 | case OPTION_BASE_SIZE_DEFAULT_32: | |
7549 | m68k_index_width_default = SIZE_LONG; | |
7550 | break; | |
7551 | ||
7552 | case OPTION_DISP_SIZE_DEFAULT_16: | |
7553 | m68k_rel32 = 0; | |
7554 | m68k_rel32_from_cmdline = 1; | |
7555 | break; | |
7556 | ||
7557 | case OPTION_DISP_SIZE_DEFAULT_32: | |
7558 | m68k_rel32 = 1; | |
7559 | m68k_rel32_from_cmdline = 1; | |
7560 | break; | |
7561 | ||
266abb8f NS |
7562 | case 'A': |
7563 | #if WARN_DEPRECATED | |
7564 | as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", | |
7565 | arg, arg)); | |
7566 | #endif | |
7567 | /* Intentional fall-through. */ | |
7568 | case 'm': | |
7569 | if (!strncmp (arg, "arch=", 5)) | |
7570 | m68k_set_arch (arg + 5, 1, 0); | |
7571 | else if (!strncmp (arg, "cpu=", 4)) | |
7572 | m68k_set_cpu (arg + 4, 1, 0); | |
7573 | else if (m68k_set_extension (arg, 0, 1)) | |
7574 | ; | |
0b2e31dc NS |
7575 | else if (m68k_set_arch (arg, 0, 1)) |
7576 | ; | |
266abb8f NS |
7577 | else if (m68k_set_cpu (arg, 0, 1)) |
7578 | ; | |
7579 | else | |
7580 | return 0; | |
7581 | break; | |
7582 | ||
252b5132 RH |
7583 | default: |
7584 | return 0; | |
7585 | } | |
7586 | ||
7587 | return 1; | |
7588 | } | |
7589 | ||
266abb8f NS |
7590 | /* Setup tables from the selected arch and/or cpu */ |
7591 | ||
7592 | static void | |
7593 | m68k_init_arch (void) | |
7594 | { | |
266abb8f NS |
7595 | if (not_current_architecture & current_architecture) |
7596 | { | |
7597 | as_bad (_("architecture features both enabled and disabled")); | |
7598 | not_current_architecture &= ~current_architecture; | |
7599 | } | |
7600 | if (selected_arch) | |
2da12c60 NS |
7601 | { |
7602 | current_architecture |= selected_arch->arch; | |
7603 | control_regs = selected_arch->control_regs; | |
7604 | } | |
0b2e31dc NS |
7605 | else |
7606 | current_architecture |= selected_cpu->arch; | |
0b2e31dc | 7607 | |
2da12c60 NS |
7608 | current_architecture &= ~not_current_architecture; |
7609 | ||
377260ba NS |
7610 | if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) |
7611 | { | |
7612 | /* Determine which float is really meant. */ | |
7613 | if (current_architecture & (m68k_mask & ~m68881)) | |
7614 | current_architecture ^= cfloat; | |
7615 | else | |
7616 | current_architecture ^= m68881; | |
7617 | } | |
7618 | ||
0b2e31dc | 7619 | if (selected_cpu) |
266abb8f | 7620 | { |
2da12c60 | 7621 | control_regs = selected_cpu->control_regs; |
0b2e31dc | 7622 | if (current_architecture & ~selected_cpu->arch) |
266abb8f | 7623 | { |
0b2e31dc NS |
7624 | as_bad (_("selected processor does not have all features of selected architecture")); |
7625 | current_architecture | |
7626 | = selected_cpu->arch & ~not_current_architecture; | |
266abb8f NS |
7627 | } |
7628 | } | |
266abb8f | 7629 | |
266abb8f NS |
7630 | if ((current_architecture & m68k_mask) |
7631 | && (current_architecture & ~m68k_mask)) | |
7632 | { | |
7633 | as_bad (_ ("m68k and cf features both selected")); | |
0b2e31dc | 7634 | if (current_architecture & m68k_mask) |
266abb8f NS |
7635 | current_architecture &= m68k_mask; |
7636 | else | |
7637 | current_architecture &= ~m68k_mask; | |
7638 | } | |
7639 | ||
7640 | /* Permit m68881 specification with all cpus; those that can't work | |
7641 | with a coprocessor could be doing emulation. */ | |
7642 | if (current_architecture & m68851) | |
7643 | { | |
7644 | if (current_architecture & m68040) | |
7645 | as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); | |
7646 | } | |
7647 | /* What other incompatibilities could we check for? */ | |
7648 | ||
266abb8f NS |
7649 | if (cpu_of_arch (current_architecture) < m68020 |
7650 | || arch_coldfire_p (current_architecture)) | |
7651 | md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; | |
7652 | ||
7653 | initialized = 1; | |
7654 | } | |
7655 | ||
252b5132 | 7656 | void |
31302357 | 7657 | md_show_usage (FILE *stream) |
252b5132 | 7658 | { |
76f57f3a | 7659 | const char *default_cpu = TARGET_CPU; |
f1f5ef86 AM |
7660 | int i; |
7661 | unsigned int default_arch; | |
76f57f3a | 7662 | |
8a104df9 | 7663 | /* Get the canonical name for the default target CPU. */ |
76f57f3a JT |
7664 | if (*default_cpu == 'm') |
7665 | default_cpu++; | |
266abb8f | 7666 | for (i = 0; m68k_cpus[i].name; i++) |
76f57f3a | 7667 | { |
266abb8f | 7668 | if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) |
76f57f3a | 7669 | { |
266abb8f | 7670 | default_arch = m68k_cpus[i].arch; |
2da12c60 NS |
7671 | while (m68k_cpus[i].alias > 0) |
7672 | i--; | |
7673 | while (m68k_cpus[i].alias < 0) | |
7674 | i++; | |
7675 | default_cpu = m68k_cpus[i].name; | |
76f57f3a JT |
7676 | } |
7677 | } | |
7678 | ||
bc805888 | 7679 | fprintf (stream, _("\ |
266abb8f NS |
7680 | -march=<arch> set architecture\n\ |
7681 | -mcpu=<cpu> set cpu [default %s]\n\ | |
7682 | "), default_cpu); | |
7683 | for (i = 0; m68k_extensions[i].name; i++) | |
7684 | fprintf (stream, _("\ | |
0b2e31dc NS |
7685 | -m[no-]%-16s enable/disable%s architecture extension\n\ |
7686 | "), m68k_extensions[i].name, | |
7687 | m68k_extensions[i].alias > 0 ? " ColdFire" | |
7688 | : m68k_extensions[i].alias < 0 ? " m68k" : ""); | |
266abb8f | 7689 | |
bc805888 | 7690 | fprintf (stream, _("\ |
266abb8f | 7691 | -l use 1 word for refs to undefined symbols [default 2]\n\ |
252b5132 RH |
7692 | -pic, -k generate position independent code\n\ |
7693 | -S turn jbsr into jsr\n\ | |
28e7409f | 7694 | --pcrel never turn PC-relative branches into absolute jumps\n\ |
252b5132 RH |
7695 | --register-prefix-optional\n\ |
7696 | recognize register names without prefix character\n\ | |
266abb8f | 7697 | --bitwise-or do not treat `|' as a comment character\n\ |
252b5132 RH |
7698 | --base-size-default-16 base reg without size is 16 bits\n\ |
7699 | --base-size-default-32 base reg without size is 32 bits (default)\n\ | |
7700 | --disp-size-default-16 displacement with unknown size is 16 bits\n\ | |
266abb8f NS |
7701 | --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ |
7702 | ")); | |
7703 | ||
7704 | fprintf (stream, _("Architecture variants are: ")); | |
7705 | for (i = 0; m68k_archs[i].name; i++) | |
7706 | { | |
7707 | if (i) | |
7708 | fprintf (stream, " | "); | |
87298967 | 7709 | fprintf (stream, "%s", m68k_archs[i].name); |
266abb8f NS |
7710 | } |
7711 | fprintf (stream, "\n"); | |
7712 | ||
7713 | fprintf (stream, _("Processor variants are: ")); | |
7714 | for (i = 0; m68k_cpus[i].name; i++) | |
7715 | { | |
7716 | if (i) | |
7717 | fprintf (stream, " | "); | |
87298967 | 7718 | fprintf (stream, "%s", m68k_cpus[i].name); |
266abb8f NS |
7719 | } |
7720 | fprintf (stream, _("\n")); | |
252b5132 RH |
7721 | } |
7722 | \f | |
7723 | #ifdef TEST2 | |
7724 | ||
7725 | /* TEST2: Test md_assemble() */ | |
36759679 NC |
7726 | /* Warning, this routine probably doesn't work anymore. */ |
7727 | int | |
31302357 | 7728 | main (void) |
252b5132 RH |
7729 | { |
7730 | struct m68k_it the_ins; | |
7731 | char buf[120]; | |
7732 | char *cp; | |
7733 | int n; | |
7734 | ||
7735 | m68k_ip_begin (); | |
7736 | for (;;) | |
7737 | { | |
7738 | if (!gets (buf) || !*buf) | |
7739 | break; | |
7740 | if (buf[0] == '|' || buf[1] == '.') | |
7741 | continue; | |
7742 | for (cp = buf; *cp; cp++) | |
7743 | if (*cp == '\t') | |
7744 | *cp = ' '; | |
7745 | if (is_label (buf)) | |
7746 | continue; | |
7747 | memset (&the_ins, '\0', sizeof (the_ins)); | |
7748 | m68k_ip (&the_ins, buf); | |
7749 | if (the_ins.error) | |
7750 | { | |
7751 | printf (_("Error %s in %s\n"), the_ins.error, buf); | |
7752 | } | |
7753 | else | |
7754 | { | |
7755 | printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); | |
7756 | for (n = 0; n < the_ins.numo; n++) | |
7757 | printf (" 0x%x", the_ins.opcode[n] & 0xffff); | |
7758 | printf (" "); | |
7759 | print_the_insn (&the_ins.opcode[0], stdout); | |
7760 | (void) putchar ('\n'); | |
7761 | } | |
7762 | for (n = 0; n < strlen (the_ins.args) / 2; n++) | |
7763 | { | |
7764 | if (the_ins.operands[n].error) | |
7765 | { | |
7766 | printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); | |
7767 | continue; | |
7768 | } | |
31302357 AS |
7769 | printf ("mode %d, reg %d, ", the_ins.operands[n].mode, |
7770 | the_ins.operands[n].reg); | |
252b5132 | 7771 | if (the_ins.operands[n].b_const) |
31302357 AS |
7772 | printf ("Constant: '%.*s', ", |
7773 | 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, | |
7774 | the_ins.operands[n].b_const); | |
7775 | printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, | |
7776 | the_ins.operands[n].isiz, the_ins.operands[n].imul); | |
252b5132 | 7777 | if (the_ins.operands[n].b_iadd) |
31302357 AS |
7778 | printf ("Iadd: '%.*s',", |
7779 | 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, | |
7780 | the_ins.operands[n].b_iadd); | |
7781 | putchar ('\n'); | |
252b5132 RH |
7782 | } |
7783 | } | |
7784 | m68k_ip_end (); | |
7785 | return 0; | |
7786 | } | |
7787 | ||
31302357 AS |
7788 | int |
7789 | is_label (char *str) | |
252b5132 RH |
7790 | { |
7791 | while (*str == ' ') | |
7792 | str++; | |
7793 | while (*str && *str != ' ') | |
7794 | str++; | |
7795 | if (str[-1] == ':' || str[1] == '=') | |
7796 | return 1; | |
7797 | return 0; | |
7798 | } | |
7799 | ||
7800 | #endif | |
7801 | ||
7802 | /* Possible states for relaxation: | |
7803 | ||
7804 | 0 0 branch offset byte (bra, etc) | |
7805 | 0 1 word | |
7806 | 0 2 long | |
7807 | ||
7808 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc | |
7809 | 1 1 word | |
7810 | 1 2 long | |
7811 | ||
7812 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc | |
7813 | 2 1 word-long | |
7814 | 2 2 long-word | |
7815 | 2 3 long-long | |
7816 | ||
7817 | */ | |
7818 | ||
7819 | /* We have no need to default values of symbols. */ | |
7820 | ||
252b5132 | 7821 | symbolS * |
31302357 | 7822 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
7823 | { |
7824 | return 0; | |
7825 | } | |
7826 | ||
7827 | /* Round up a section size to the appropriate boundary. */ | |
7828 | valueT | |
31302357 | 7829 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
7830 | { |
7831 | #ifdef OBJ_AOUT | |
252b5132 RH |
7832 | /* For a.out, force the section size to be aligned. If we don't do |
7833 | this, BFD will align it for us, but it will not write out the | |
7834 | final bytes of the section. This may be a bug in BFD, but it is | |
7835 | easier to fix it here since that is how the other a.out targets | |
7836 | work. */ | |
7837 | int align; | |
7838 | ||
7839 | align = bfd_get_section_alignment (stdoutput, segment); | |
7840 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
252b5132 RH |
7841 | #endif |
7842 | ||
7843 | return size; | |
7844 | } | |
7845 | ||
7846 | /* Exactly what point is a PC-relative offset relative TO? | |
7847 | On the 68k, it is relative to the address of the first extension | |
7848 | word. The difference between the addresses of the offset and the | |
92774660 | 7849 | first extension word is stored in fx_pcrel_adjust. */ |
252b5132 | 7850 | long |
31302357 | 7851 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
7852 | { |
7853 | int adjust; | |
7854 | ||
8390138c AS |
7855 | /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly |
7856 | sign extend the value here. */ | |
7857 | adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80; | |
252b5132 RH |
7858 | if (adjust == 64) |
7859 | adjust = -1; | |
7860 | return fixP->fx_where + fixP->fx_frag->fr_address - adjust; | |
7861 | } | |
7862 | ||
0d96863f | 7863 | #ifdef OBJ_ELF |
8a104df9 | 7864 | void |
31302357 | 7865 | m68k_elf_final_processing (void) |
0d96863f | 7866 | { |
266abb8f NS |
7867 | unsigned flags = 0; |
7868 | ||
238d258f | 7869 | if (arch_coldfire_fpu (current_architecture)) |
266abb8f NS |
7870 | flags |= EF_M68K_CFV4E; |
7871 | /* Set file-specific flags if this is a cpu32 processor. */ | |
8a104df9 | 7872 | if (cpu_of_arch (current_architecture) & cpu32) |
3bdcfdf4 KH |
7873 | flags |= EF_M68K_CPU32; |
7874 | else if (cpu_of_arch (current_architecture) & fido_a) | |
7875 | flags |= EF_M68K_FIDO; | |
8a104df9 KH |
7876 | else if ((cpu_of_arch (current_architecture) & m68000up) |
7877 | && !(cpu_of_arch (current_architecture) & m68020up)) | |
266abb8f NS |
7878 | flags |= EF_M68K_M68000; |
7879 | ||
7880 | if (current_architecture & mcfisa_a) | |
7881 | { | |
0b2e31dc NS |
7882 | static const unsigned isa_features[][2] = |
7883 | { | |
9a2e615a | 7884 | {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, |
c694fd50 | 7885 | {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, |
9a2e615a | 7886 | {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, |
c694fd50 KH |
7887 | {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, |
7888 | {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, | |
9a2e615a | 7889 | {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, |
8d100c32 | 7890 | {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, |
0b2e31dc NS |
7891 | {0,0}, |
7892 | }; | |
7893 | static const unsigned mac_features[][2] = | |
7894 | { | |
c694fd50 KH |
7895 | {EF_M68K_CF_MAC, mcfmac}, |
7896 | {EF_M68K_CF_EMAC, mcfemac}, | |
0b2e31dc NS |
7897 | {0,0}, |
7898 | }; | |
7899 | unsigned ix; | |
7900 | unsigned pattern; | |
266abb8f | 7901 | |
0b2e31dc | 7902 | pattern = (current_architecture |
9a2e615a | 7903 | & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); |
0b2e31dc NS |
7904 | for (ix = 0; isa_features[ix][1]; ix++) |
7905 | { | |
7906 | if (pattern == isa_features[ix][1]) | |
7907 | { | |
7908 | flags |= isa_features[ix][0]; | |
7909 | break; | |
7910 | } | |
7911 | } | |
7912 | if (!isa_features[ix][1]) | |
7913 | { | |
7914 | cf_bad: | |
7915 | as_warn (_("Not a defined coldfire architecture")); | |
7916 | } | |
7917 | else | |
7918 | { | |
7919 | if (current_architecture & cfloat) | |
c694fd50 | 7920 | flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; |
266abb8f | 7921 | |
0b2e31dc NS |
7922 | pattern = current_architecture & (mcfmac|mcfemac); |
7923 | if (pattern) | |
7924 | { | |
7925 | for (ix = 0; mac_features[ix][1]; ix++) | |
7926 | { | |
7927 | if (pattern == mac_features[ix][1]) | |
7928 | { | |
7929 | flags |= mac_features[ix][0]; | |
7930 | break; | |
7931 | } | |
7932 | } | |
7933 | if (!mac_features[ix][1]) | |
7934 | goto cf_bad; | |
7935 | } | |
7936 | } | |
266abb8f NS |
7937 | } |
7938 | elf_elfheader (stdoutput)->e_flags |= flags; | |
0d96863f | 7939 | } |
cf869cce NC |
7940 | |
7941 | /* Parse @TLSLDO and return the desired relocation. */ | |
7942 | static bfd_reloc_code_real_type | |
7943 | m68k_elf_suffix (char **str_p, expressionS *exp_p) | |
7944 | { | |
7945 | char ident[20]; | |
7946 | char *str = *str_p; | |
7947 | char *str2; | |
7948 | int ch; | |
7949 | int len; | |
7950 | ||
7951 | if (*str++ != '@') | |
7952 | return BFD_RELOC_UNUSED; | |
7953 | ||
7954 | for (ch = *str, str2 = ident; | |
7955 | (str2 < ident + sizeof (ident) - 1 | |
7956 | && (ISALNUM (ch) || ch == '@')); | |
7957 | ch = *++str) | |
7958 | { | |
7959 | *str2++ = ch; | |
7960 | } | |
7961 | ||
7962 | *str2 = '\0'; | |
7963 | len = str2 - ident; | |
7964 | ||
7965 | if (strncmp (ident, "TLSLDO", 6) == 0 | |
7966 | && len == 6) | |
7967 | { | |
7968 | /* Now check for identifier@suffix+constant. */ | |
7969 | if (*str == '-' || *str == '+') | |
7970 | { | |
7971 | char *orig_line = input_line_pointer; | |
7972 | expressionS new_exp; | |
7973 | ||
7974 | input_line_pointer = str; | |
7975 | expression (&new_exp); | |
7976 | if (new_exp.X_op == O_constant) | |
7977 | { | |
7978 | exp_p->X_add_number += new_exp.X_add_number; | |
7979 | str = input_line_pointer; | |
7980 | } | |
7981 | ||
7982 | if (&input_line_pointer != str_p) | |
7983 | input_line_pointer = orig_line; | |
7984 | } | |
7985 | *str_p = str; | |
7986 | ||
7987 | return BFD_RELOC_68K_TLS_LDO32; | |
7988 | } | |
7989 | ||
7990 | return BFD_RELOC_UNUSED; | |
7991 | } | |
7992 | ||
7993 | /* Handles .long <tls_symbol>+0x8000 debug info. | |
7994 | Clobbers input_line_pointer, checks end-of-line. | |
7995 | Adapted from tc-ppc.c:ppc_elf_cons. */ | |
7996 | static void | |
7997 | m68k_elf_cons (int nbytes /* 4=.long */) | |
7998 | { | |
7999 | if (is_it_end_of_statement ()) | |
8000 | { | |
8001 | demand_empty_rest_of_line (); | |
8002 | return; | |
8003 | } | |
8004 | ||
8005 | do | |
8006 | { | |
8007 | expressionS exp; | |
8008 | bfd_reloc_code_real_type reloc; | |
8009 | ||
8010 | expression (&exp); | |
8011 | if (exp.X_op == O_symbol | |
8012 | && *input_line_pointer == '@' | |
8013 | && (reloc = m68k_elf_suffix (&input_line_pointer, | |
8014 | &exp)) != BFD_RELOC_UNUSED) | |
8015 | { | |
8016 | reloc_howto_type *reloc_howto; | |
8017 | int size; | |
8018 | ||
8019 | reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
8020 | size = bfd_get_reloc_size (reloc_howto); | |
8021 | ||
8022 | if (size > nbytes) | |
8023 | { | |
8024 | as_bad (_("%s relocations do not fit in %d bytes\n"), | |
8025 | reloc_howto->name, nbytes); | |
8026 | } | |
8027 | else | |
8028 | { | |
8029 | char *p; | |
8030 | int offset; | |
8031 | ||
8032 | p = frag_more (nbytes); | |
8033 | offset = 0; | |
8034 | if (target_big_endian) | |
8035 | offset = nbytes - size; | |
8036 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, | |
8037 | &exp, 0, reloc); | |
8038 | } | |
8039 | } | |
8040 | else | |
8041 | emit_expr (&exp, (unsigned int) nbytes); | |
8042 | } | |
8043 | while (*input_line_pointer++ == ','); | |
8044 | ||
8045 | /* Put terminator back into stream. */ | |
8046 | input_line_pointer--; | |
8047 | demand_empty_rest_of_line (); | |
8048 | } | |
0d96863f | 8049 | #endif |
c04898f8 AS |
8050 | |
8051 | int | |
1df69f4f | 8052 | tc_m68k_regname_to_dw2regnum (char *regname) |
c04898f8 AS |
8053 | { |
8054 | unsigned int regnum; | |
8055 | static const char *const regnames[] = | |
8056 | { | |
8057 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
8058 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", | |
8059 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", | |
8060 | "pc" | |
8061 | }; | |
8062 | ||
8063 | for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) | |
8064 | if (strcmp (regname, regnames[regnum]) == 0) | |
8065 | return regnum; | |
8066 | ||
8067 | return -1; | |
8068 | } | |
8069 | ||
8070 | void | |
8071 | tc_m68k_frame_initial_instructions (void) | |
8072 | { | |
8073 | static int sp_regno = -1; | |
8074 | ||
8075 | if (sp_regno < 0) | |
8076 | sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); | |
8077 | ||
8078 | cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); | |
8079 | cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); | |
8080 | } |