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Add code to support FR30 instrucitons which contain a colon in their mnemonic
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a1c7c0f3 1/* tc-m68k.c -- Assemble for the m68k family
48401fcf 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
b4d51f3d 3 Free Software Foundation, Inc.
6d27d3a2 4
a39116f1 5 This file is part of GAS, the GNU Assembler.
6d27d3a2 6
a39116f1
RP		 7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
6d27d3a2 11
a39116f1
RP		 12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
6d27d3a2 16
a39116f1 17 You should have received a copy of the GNU General Public License
a1c7c0f3
ILT		 18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
fecd2382
RP		 21
22#include <ctype.h>
fecd2382 23#include "as.h"
fecd2382 24#include "obstack.h"
b4ec75e0 25#include "subsegs.h"
fecd2382 26
e0982afe 27#include "opcode/m68k.h"
a1c7c0f3 28#include "m68k-parse.h"
3ad9ec6a 29
8d20a0a8
C		 30/* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
fee3e248 34#if defined (TE_SVR4) || defined (TE_DELTA)
8d20a0a8 35const char *m68k_comment_chars = "|#";
5f8cb05e 36#else
8d20a0a8 37const char *m68k_comment_chars = "|";
5f8cb05e 38#endif
fecd2382
RP		 39
40/* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43/* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46/* Also note that comments like this one will always work. */
590c50d8 47const char line_comment_chars[] = "#*";
fecd2382 48
326b087c 49const char line_separator_chars[] = "";
587c4264 50
fecd2382 51/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 52CONST char EXP_CHARS[] = "eE";
fecd2382 53
49864cfa
KR		 54/* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
fecd2382 56
49864cfa 57CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 58
59/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 61 but nothing is ideal around here. */
fecd2382 62
49864cfa 63const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 64
b80d39a0 65/* Are we trying to generate PIC code? If so, absolute references
dff60b7d 66 ought to be made into linkage table references or pc-relative
a043f579
ILT		 67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
b80d39a0
KR		 69int flag_want_pic;
70
9ad5755f
KR		 71static int flag_short_refs; /* -l option */
72static int flag_long_jumps; /* -S option */
73
82489ea0
KR		 74#ifdef REGISTER_PREFIX_OPTIONAL
75int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76#else
77int flag_reg_prefix_optional;
78#endif
79
20710f1c
ILT		 80/* Whether --register-prefix-optional was used on the command line. */
81static int reg_prefix_optional_seen;
82
27a53b88
ILT		 83/* The floating point coprocessor to use by default. */
84static enum m68k_register m68k_float_copnum = COP1;
85
6700d36e
ILT		 86/* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88static int m68k_abspcadd;
89
90/* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92static int m68k_quick = 1;
93
94/* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97static int m68k_rel32 = 1;
98
924160b0
ILT		 99/* This is non-zero if m68k_rel32 was set from the command line. */
100static int m68k_rel32_from_cmdline;
101
b4d51f3d
ILT		 102/* The default width to use for an index register when using a base
103 displacement. */
104static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
d703b5a7
ILT		 106/* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110struct label_line
111{
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117};
118
119/* The list of labels. */
120
121static struct label_line *labels;
122
123/* The current label. */
124
125static struct label_line *current_label;
126
fecd2382
RP		 127/* Its an arbitrary name: This means I don't approve of it */
128/* See flames below */
129static struct obstack robyn;
130
131#define TAB(x,y) (((x)<<2)+(y))
132#define TABTYPE(xy) ((xy) >> 2)
133#define BYTE 0
134#define SHORT 1
135#define LONG 2
136#define SZ_UNDEF 3
3ad9ec6a 137#undef BRANCH
04ef74bb 138/* Case `g' except when BCC68000 is applicable. */
3ad9ec6a 139#define ABRANCH 1
04ef74bb 140/* Coprocessor branches. */
fecd2382 141#define FBRANCH 2
04ef74bb
KR		 142/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
fecd2382 144#define PCREL 3
04ef74bb
KR		 145/* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
fecd2382 150#define BCC68000 4
04ef74bb
KR		 151/* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
fecd2382 153#define DBCC 5
04ef74bb 154/* Not currently used? */
fecd2382 155#define PCLEA 6
04ef74bb
KR		 156/* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158#define PCINDEX 7
fecd2382 159
bcb8dff8
KR		 160struct m68k_incant
161 {
a1c7c0f3 162 const char *m_operands;
bcb8dff8
KR		 163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171#define gettwo(x) (((x)->m_opcode)&0xffff)
172
a1c7c0f3
ILT		 173static const enum m68k_register m68000_control_regs[] = { 0 };
174static const enum m68k_register m68010_control_regs[] = {
82489ea0
KR		 175 SFC, DFC, USP, VBR,
176 0
177};
a1c7c0f3 178static const enum m68k_register m68020_control_regs[] = {
82489ea0
KR		 179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181};
a1c7c0f3 182static const enum m68k_register m68040_control_regs[] = {
82489ea0
KR		 183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186};
a1c7c0f3 187static const enum m68k_register m68060_control_regs[] = {
82489ea0
KR		 188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191};
8d20a0a8
C		 192static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196};
b79de3a1 197#define cpu32_control_regs m68010_control_regs
82489ea0 198
a1c7c0f3 199static const enum m68k_register *control_regs;
fecd2382
RP		 200
201/* internal form of a 68020 instruction */
355afbcd 202struct m68k_it
a1c7c0f3
ILT		 203{
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
355afbcd 207
a1c7c0f3
ILT		 208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
355afbcd 210
a1c7c0f3 211 struct m68k_op operands[6];
355afbcd 212
a1c7c0f3
ILT		 213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
355afbcd 215
a1c7c0f3
ILT		 216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
f59fb6ca 221 offsetT foff;
a1c7c0f3
ILT		 222 int fragty;
223 }
224 fragb[4];
355afbcd 225
a1c7c0f3
ILT		 226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
a043f579
ILT		 241#ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245#endif
a1c7c0f3
ILT		 246 }
247 reloc[5]; /* Five is enough??? */
248};
fecd2382 249
8d20a0a8 250#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
865a2edf
MT		 251#define float_of_arch(x) ((x) & mfloat)
252#define mmu_of_arch(x) ((x) & mmmu)
253
ffecfc8b
C		 254/* Macros for determining if cpu supports a specific addressing mode */
255#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
355afbcd 257static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 258
a1c7c0f3
ILT		 259#define op(ex) ((ex)->exp.X_op)
260#define adds(ex) ((ex)->exp.X_add_symbol)
261#define subs(ex) ((ex)->exp.X_op_symbol)
262#define offs(ex) ((ex)->exp.X_add_number)
49864cfa 263
7c15cbe8 264/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 265
266#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
f59fb6ca
ILT		 268/* Static functions. */
269
48401fcf 270static void insop PARAMS ((int, const struct m68k_incant *));
f59fb6ca
ILT		 271static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272static void add_frag PARAMS ((symbolS *, offsetT, int));
273
fecd2382 274/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 275static void
276insop (w, opcode)
277 int w;
48401fcf 278 const struct m68k_incant *opcode;
bcb8dff8
KR		 279{
280 int z;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
5f8cb05e
ILT		 285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
bcb8dff8
KR		 287 the_ins.opcode[opcode->m_codenum]=w;
288 the_ins.numo++;
289}
fecd2382 290
1404ef23
KR		 291/* The numo+1 kludge is so we can hit the low order byte of the prev word.
292 Blecch. */
49864cfa 293static void
5f8cb05e 294add_fix (width, exp, pc_rel, pc_fix)
f59fb6ca 295 int width;
49864cfa
KR		 296 struct m68k_exp *exp;
297 int pc_rel;
5f8cb05e 298 int pc_fix;
49864cfa 299{
0b810a6e 300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
49864cfa
KR		 301 ? (the_ins.numo*2-1)
302 : (((width)=='b')
5f8cb05e 303 ? (the_ins.numo*2+1)
49864cfa 304 : (the_ins.numo*2)));
a1c7c0f3 305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
49864cfa 306 the_ins.reloc[the_ins.nrel].wid = width;
5f8cb05e 307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
a043f579
ILT		 308#ifdef OBJ_ELF
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
310#endif
49864cfa 311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 312}
313
5f8cb05e
ILT		 314/* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
318
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
322
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
49864cfa 324static void
f59fb6ca 325add_frag (add, off, type)
49864cfa 326 symbolS *add;
f59fb6ca 327 offsetT off;
49864cfa
KR		 328 int type;
329{
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 334}
fecd2382 335
a1c7c0f3
ILT		 336#define isvar(ex) \
337 (op (ex) != O_constant && op (ex) != O_big)
fecd2382 338
49864cfa
KR		 339static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340static int get_num PARAMS ((struct m68k_exp *exp, int ok));
f59fb6ca
ILT		 341static void m68k_ip PARAMS ((char *));
342static void insert_reg PARAMS ((const char *, int));
343static void select_control_regs PARAMS ((void));
344static void init_regtable PARAMS ((void));
49864cfa
KR		 345static int reverse_16_bits PARAMS ((int in));
346static int reverse_8_bits PARAMS ((int in));
49864cfa
KR		 347static void install_gen_operand PARAMS ((int mode, int val));
348static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 349static void s_bss PARAMS ((int));
350static void s_data1 PARAMS ((int));
351static void s_data2 PARAMS ((int));
352static void s_even PARAMS ((int));
353static void s_proc PARAMS ((int));
e9bb39b4
ILT		 354static void mri_chip PARAMS ((void));
355static void s_chip PARAMS ((int));
27a53b88 356static void s_fopt PARAMS ((int));
6700d36e
ILT		 357static void s_opt PARAMS ((int));
358static void s_reg PARAMS ((int));
e14994d9
ILT		 359static void s_restore PARAMS ((int));
360static void s_save PARAMS ((int));
b4ec75e0
ILT		 361static void s_mri_if PARAMS ((int));
362static void s_mri_else PARAMS ((int));
363static void s_mri_endi PARAMS ((int));
364static void s_mri_break PARAMS ((int));
365static void s_mri_next PARAMS ((int));
366static void s_mri_for PARAMS ((int));
367static void s_mri_endf PARAMS ((int));
368static void s_mri_repeat PARAMS ((int));
369static void s_mri_until PARAMS ((int));
370static void s_mri_while PARAMS ((int));
371static void s_mri_endw PARAMS ((int));
f59fb6ca
ILT		 372static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373static void md_convert_frag_1 PARAMS ((fragS *));
49864cfa
KR		 374
375static int current_architecture;
7c15cbe8 376
b79de3a1
KR		 377struct m68k_cpu {
378 unsigned long arch;
379 const char *name;
9e64486e 380 int alias;
b79de3a1
KR		 381};
382
383static const struct m68k_cpu archs[] = {
9e64486e
ILT		 384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
8d20a0a8 393 { mcf5200, "5200", 0 },
b79de3a1
KR		 394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
9e64486e 396 { m68020, "68k", 1 },
9e64486e 397 { m68000, "68008", 1 },
15ab76e5
ILT		 398 { m68000, "68302", 1 },
399 { m68000, "68306", 1 },
400 { m68000, "68307", 1 },
401 { m68000, "68322", 1 },
402 { m68000, "68356", 1 },
9e64486e
ILT		 403 { m68000, "68ec000", 1 },
404 { m68000, "68hc000", 1 },
405 { m68000, "68hc001", 1 },
406 { m68020, "68ec020", 1 },
407 { m68030, "68ec030", 1 },
408 { m68040, "68ec040", 1 },
8d20a0a8 409 { m68060, "68ec060", 1 },
9e64486e
ILT		 410 { cpu32, "68330", 1 },
411 { cpu32, "68331", 1 },
412 { cpu32, "68332", 1 },
413 { cpu32, "68333", 1 },
15ab76e5
ILT		 414 { cpu32, "68334", 1 },
415 { cpu32, "68336", 1 },
9e64486e 416 { cpu32, "68340", 1 },
15ab76e5
ILT		 417 { cpu32, "68341", 1 },
418 { cpu32, "68349", 1 },
9e64486e
ILT		 419 { cpu32, "68360", 1 },
420 { m68881, "68882", 1 },
b79de3a1
KR		 421};
422
423static const int n_archs = sizeof (archs) / sizeof (archs[0]);
424
fecd2382
RP		 425/* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
427
428/* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
430
49864cfa
KR		 431/* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 433
434/* The fields are:
a39116f1
RP		 435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
439 */
04ef74bb 440relax_typeS md_relax_table[] =
355afbcd
KR		 441{
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
445 {1, 1, 0, 0},
446
447 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
448 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
449 {0, 0, 4, 0},
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
454 {0, 0, 4, 0},
455 {1, 1, 0, 0},
456
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL, LONG)},
459 {0, 0, 4, 0},
460 {1, 1, 0, 0},
461
462 {(127), (-128), 0, TAB (BCC68000, SHORT)},
463 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
464 {0, 0, 6, 0}, /* jmp long space */
465 {1, 1, 0, 0},
466
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC, LONG)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
470 {1, 1, 0, 0},
471
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA, LONG)},
474 {0, 0, 6, 0},
475 {1, 1, 0, 0},
476
04ef74bb
KR		 477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX, SHORT)},
479 {32765, -32770, 2, TAB (PCINDEX, LONG)},
480 {0, 0, 4, 0},
481 {1, 1, 0, 0},
355afbcd 482};
fecd2382
RP		 483
484/* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
486 generates these.
a39116f1 487 */
fecd2382
RP		 488
489/* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
a39116f1
RP		 491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
494 */
326b087c 495const pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 496{
497 {"data1", s_data1, 0},
498 {"data2", s_data2, 0},
499 {"bss", s_bss, 0},
500 {"even", s_even, 0},
501 {"skip", s_space, 0},
502 {"proc", s_proc, 0},
a043f579 503#if defined (TE_SUN3) || defined (OBJ_ELF)
355afbcd 504 {"align", s_align_bytes, 0},
5f8cb05e
ILT		 505#endif
506#ifdef OBJ_ELF
507 {"swbeg", s_ignore, 0},
bec66218 508#endif
9e64486e
ILT		 509 {"extend", float_cons, 'x'},
510 {"ldouble", float_cons, 'x'},
e9bb39b4
ILT		 511
512 /* The following pseudo-ops are supported for MRI compatibility. */
513 {"chip", s_chip, 0},
514 {"comline", s_space, 1},
27a53b88
ILT		 515 {"fopt", s_fopt, 0},
516 {"mask2", s_ignore, 0},
6700d36e
ILT		 517 {"opt", s_opt, 0},
518 {"reg", s_reg, 0},
e14994d9
ILT		 519 {"restore", s_restore, 0},
520 {"save", s_save, 0},
e9bb39b4 521
b4ec75e0
ILT		 522 {"if", s_mri_if, 0},
523 {"if.b", s_mri_if, 'b'},
524 {"if.w", s_mri_if, 'w'},
525 {"if.l", s_mri_if, 'l'},
526 {"else", s_mri_else, 0},
527 {"else.s", s_mri_else, 's'},
528 {"else.l", s_mri_else, 'l'},
529 {"endi", s_mri_endi, 0},
530 {"break", s_mri_break, 0},
531 {"break.s", s_mri_break, 's'},
532 {"break.l", s_mri_break, 'l'},
533 {"next", s_mri_next, 0},
534 {"next.s", s_mri_next, 's'},
535 {"next.l", s_mri_next, 'l'},
536 {"for", s_mri_for, 0},
537 {"for.b", s_mri_for, 'b'},
538 {"for.w", s_mri_for, 'w'},
539 {"for.l", s_mri_for, 'l'},
540 {"endf", s_mri_endf, 0},
541 {"repeat", s_mri_repeat, 0},
542 {"until", s_mri_until, 0},
543 {"until.b", s_mri_until, 'b'},
544 {"until.w", s_mri_until, 'w'},
545 {"until.l", s_mri_until, 'l'},
546 {"while", s_mri_while, 0},
547 {"while.b", s_mri_while, 'b'},
548 {"while.w", s_mri_while, 'w'},
549 {"while.l", s_mri_while, 'l'},
550 {"endw", s_mri_endw, 0},
551
355afbcd 552 {0, 0, 0}
fecd2382
RP		 553};
554
555
3ad9ec6a 556/* The mote pseudo ops are put into the opcode table, since they
355afbcd 557 don't start with a . they look like opcodes to gas.
3ad9ec6a 558 */
f59fb6ca
ILT		 559
560#ifdef M68KCOFF
561extern void obj_coff_section PARAMS ((int));
562#endif
3ad9ec6a 563
49864cfa 564CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 565{
566
b79de3a1 567 {"dcl", cons, 4},
355afbcd 568 {"dc", cons, 2},
b79de3a1
KR		 569 {"dcw", cons, 2},
570 {"dcb", cons, 1},
3ad9ec6a 571
b79de3a1 572 {"dsl", s_space, 4},
355afbcd 573 {"ds", s_space, 2},
b79de3a1
KR		 574 {"dsw", s_space, 2},
575 {"dsb", s_space, 1},
3ad9ec6a 576
355afbcd 577 {"xdef", s_globl, 0},
a043f579
ILT		 578#ifdef OBJ_ELF
579 {"align", s_align_bytes, 0},
580#else
355afbcd 581 {"align", s_align_ptwo, 0},
a043f579 582#endif
3ad9ec6a 583#ifdef M68KCOFF
355afbcd
KR		 584 {"sect", obj_coff_section, 0},
585 {"section", obj_coff_section, 0},
3ad9ec6a 586#endif
bcb8dff8 587 {0, 0, 0}
3ad9ec6a
ILT		 588};
589
fecd2382
RP		 590#define issbyte(x) ((x)>=-128 && (x)<=127)
591#define isubyte(x) ((x)>=0 && (x)<=255)
592#define issword(x) ((x)>=-32768 && (x)<=32767)
593#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 594
e284846a 595#define isbyte(x) ((x)>= -255 && (x)<=255)
a7512014 596#define isword(x) ((x)>=-65536 && (x)<=65535)
fecd2382 597#define islong(x) (1)
f8701a3f
SC		 598
599extern char *input_line_pointer;
fecd2382 600
fecd2382
RP		 601static char mklower_table[256];
602#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 603static char notend_table[256];
fecd2382 604static char alt_notend_table[256];
a1c7c0f3
ILT		 605#define notend(s) \
606 (! (notend_table[(unsigned char) *s] \
607 || (*s == ':' \
608 && alt_notend_table[(unsigned char) s[1]])))
7c15cbe8 609
49864cfa 610#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 611
82489ea0
KR		 612#ifdef NO_PCREL_RELOCS
613
614int
615make_pcrel_absolute(fixP, add_number)
616 fixS *fixP;
617 long *add_number;
618{
619 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
620
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
624 */
625 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
626 {
627 opcode[0] = 0x4e;
628 opcode[1] = 0xf9;
629 }
630 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
631 {
632 opcode[0] = 0x4e;
633 opcode[1] = 0xb9;
634 }
635 else
48401fcf 636 as_fatal (_("Unknown PC relative instruction"));
82489ea0
KR		 637 *add_number -= 4;
638 return 0;
639}
640
641#endif /* NO_PCREL_RELOCS */
642
355afbcd
KR		 643short
644tc_coff_fix2rtype (fixP)
645 fixS *fixP;
fecd2382 646{
3b06beb7
ILT		 647 if (fixP->fx_tcbit && fixP->fx_size == 4)
648 return R_RELLONG_NEG;
82489ea0
KR		 649#ifdef NO_PCREL_RELOCS
650 know (fixP->fx_pcrel == 0);
651 return (fixP->fx_size == 1 ? R_RELBYTE
652 : fixP->fx_size == 2 ? R_DIR16
653 : R_DIR32);
654#else
355afbcd
KR		 655 return (fixP->fx_pcrel ?
656 (fixP->fx_size == 1 ? R_PCRBYTE :
657 fixP->fx_size == 2 ? R_PCRWORD :
658 R_PCRLONG) :
659 (fixP->fx_size == 1 ? R_RELBYTE :
660 fixP->fx_size == 2 ? R_RELWORD :
661 R_RELLONG));
82489ea0 662#endif
3ad9ec6a
ILT		 663}
664
665#endif
fecd2382 666
a043f579
ILT		 667#ifdef OBJ_ELF
668
669/* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
672
673static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation));
675
676static bfd_reloc_code_real_type
677get_reloc_code (size, pcrel, pic)
678 int size;
679 int pcrel;
680 enum pic_relocation pic;
681{
682 switch (pic)
683 {
684 case pic_got_pcrel:
685 switch (size)
686 {
687 case 1:
688 return BFD_RELOC_8_GOT_PCREL;
689 case 2:
690 return BFD_RELOC_16_GOT_PCREL;
691 case 4:
692 return BFD_RELOC_32_GOT_PCREL;
693 }
694 break;
695
696 case pic_got_off:
697 switch (size)
698 {
699 case 1:
700 return BFD_RELOC_8_GOTOFF;
701 case 2:
702 return BFD_RELOC_16_GOTOFF;
703 case 4:
704 return BFD_RELOC_32_GOTOFF;
705 }
706 break;
707
708 case pic_plt_pcrel:
709 switch (size)
710 {
711 case 1:
712 return BFD_RELOC_8_PLT_PCREL;
713 case 2:
714 return BFD_RELOC_16_PLT_PCREL;
715 case 4:
716 return BFD_RELOC_32_PLT_PCREL;
717 }
718 break;
719
720 case pic_plt_off:
721 switch (size)
722 {
723 case 1:
724 return BFD_RELOC_8_PLTOFF;
725 case 2:
726 return BFD_RELOC_16_PLTOFF;
727 case 4:
728 return BFD_RELOC_32_PLTOFF;
729 }
730 break;
731
732 case pic_none:
733 if (pcrel)
734 {
735 switch (size)
736 {
737 case 1:
738 return BFD_RELOC_8_PCREL;
739 case 2:
740 return BFD_RELOC_16_PCREL;
741 case 4:
742 return BFD_RELOC_32_PCREL;
743 }
744 }
745 else
746 {
747 switch (size)
748 {
749 case 1:
750 return BFD_RELOC_8;
751 case 2:
752 return BFD_RELOC_16;
753 case 4:
754 return BFD_RELOC_32;
755 }
756 }
757 }
758
48401fcf
TT		 759 if (pcrel)
760 {
761 if (pic == pic_none)
762 as_bad (_("Can not do %d byte pc-relative relocation"), size);
763 else
764 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
765 }
766 else
767 {
768 if (pic == pic_none)
769 as_bad (_("Can not do %d byte relocation"), size);
770 else
771 as_bad (_("Can not do %d byte pic relocation"), size);
772 }
773
a043f579
ILT		 774 return BFD_RELOC_NONE;
775}
776
777/* Here we decide which fixups can be adjusted to make them relative
778 to the beginning of the section instead of the symbol. Basically
779 we need to make sure that the dynamic relocations are done
780 correctly, so in some cases we force the original symbol to be
781 used. */
782int
783tc_m68k_fix_adjustable (fixP)
784 fixS *fixP;
785{
786 /* Prevent all adjustments to global symbols. */
dcb76edb
ILT		 787 if (S_IS_EXTERNAL (fixP->fx_addsy)
788 || S_IS_WEAK (fixP->fx_addsy))
a043f579
ILT		 789 return 0;
790
791 /* adjust_reloc_syms doesn't know about the GOT */
792 switch (fixP->fx_r_type)
793 {
794 case BFD_RELOC_8_GOT_PCREL:
795 case BFD_RELOC_16_GOT_PCREL:
796 case BFD_RELOC_32_GOT_PCREL:
797 case BFD_RELOC_8_GOTOFF:
798 case BFD_RELOC_16_GOTOFF:
799 case BFD_RELOC_32_GOTOFF:
800 case BFD_RELOC_8_PLT_PCREL:
801 case BFD_RELOC_16_PLT_PCREL:
802 case BFD_RELOC_32_PLT_PCREL:
803 case BFD_RELOC_8_PLTOFF:
804 case BFD_RELOC_16_PLTOFF:
805 case BFD_RELOC_32_PLTOFF:
806 return 0;
807
808 default:
809 return 1;
810 }
811}
812
813#else /* !OBJ_ELF */
814
815#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
816
817#endif /* OBJ_ELF */
818
49864cfa
KR		 819#ifdef BFD_ASSEMBLER
820
821arelent *
822tc_gen_reloc (section, fixp)
823 asection *section;
824 fixS *fixp;
825{
826 arelent *reloc;
827 bfd_reloc_code_real_type code;
828
9e64486e 829 if (fixp->fx_tcbit)
3b06beb7
ILT		 830 abort ();
831
a043f579 832 if (fixp->fx_r_type != BFD_RELOC_NONE)
7f003b7f
ILT		 833 {
834 code = fixp->fx_r_type;
835
836 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
837 that fixup_segment converted a non-PC relative reloc into a
838 PC relative reloc. In such a case, we need to convert the
839 reloc code. */
840 if (fixp->fx_pcrel)
841 {
842 switch (code)
843 {
844 case BFD_RELOC_8:
845 code = BFD_RELOC_8_PCREL;
846 break;
847 case BFD_RELOC_16:
848 code = BFD_RELOC_16_PCREL;
849 break;
850 case BFD_RELOC_32:
851 code = BFD_RELOC_32_PCREL;
852 break;
853 case BFD_RELOC_8_PCREL:
854 case BFD_RELOC_16_PCREL:
855 case BFD_RELOC_32_PCREL:
856 case BFD_RELOC_8_GOT_PCREL:
857 case BFD_RELOC_16_GOT_PCREL:
858 case BFD_RELOC_32_GOT_PCREL:
859 case BFD_RELOC_8_GOTOFF:
860 case BFD_RELOC_16_GOTOFF:
861 case BFD_RELOC_32_GOTOFF:
862 case BFD_RELOC_8_PLT_PCREL:
863 case BFD_RELOC_16_PLT_PCREL:
864 case BFD_RELOC_32_PLT_PCREL:
865 case BFD_RELOC_8_PLTOFF:
866 case BFD_RELOC_16_PLTOFF:
867 case BFD_RELOC_32_PLTOFF:
868 break;
869 default:
870 as_bad_where (fixp->fx_file, fixp->fx_line,
48401fcf 871 _("Cannot make %s relocation PC relative"),
7f003b7f
ILT		 872 bfd_get_reloc_code_name (code));
873 }
874 }
875 }
a043f579 876 else
49864cfa 877 {
a043f579
ILT		 878#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
879 switch (F (fixp->fx_size, fixp->fx_pcrel))
880 {
49864cfa 881#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
a043f579
ILT		 882 MAP (1, 0, BFD_RELOC_8);
883 MAP (2, 0, BFD_RELOC_16);
884 MAP (4, 0, BFD_RELOC_32);
885 MAP (1, 1, BFD_RELOC_8_PCREL);
886 MAP (2, 1, BFD_RELOC_16_PCREL);
887 MAP (4, 1, BFD_RELOC_32_PCREL);
888 default:
889 abort ();
890 }
49864cfa 891 }
a043f579
ILT		 892#undef F
893#undef MAP
49864cfa 894
590c50d8 895 reloc = (arelent *) xmalloc (sizeof (arelent));
49864cfa
KR		 896 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
897 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a043f579 898#ifndef OBJ_ELF
49864cfa
KR		 899 if (fixp->fx_pcrel)
900 reloc->addend = fixp->fx_addnumber;
901 else
902 reloc->addend = 0;
a043f579
ILT		 903#else
904 if (!fixp->fx_pcrel)
905 reloc->addend = fixp->fx_addnumber;
7f003b7f 906 else
a043f579
ILT		 907 reloc->addend = (section->vma
908 + (fixp->fx_pcrel_adjust == 64
909 ? -1 : fixp->fx_pcrel_adjust)
910 + fixp->fx_addnumber
911 + md_pcrel_from (fixp));
a043f579 912#endif
49864cfa
KR		 913
914 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
915 assert (reloc->howto != 0);
916
917 return reloc;
918}
919
920#endif /* BFD_ASSEMBLER */
921
dcb76edb
ILT		 922/* Return zero if the reference to SYMBOL from within the same segment may
923 be relaxed. */
924#ifdef OBJ_ELF
925
926#define relaxable_symbol(symbol) \
927 (! S_IS_EXTERNAL (symbol) && ! S_IS_WEAK (symbol))
928
929#else
930
931#define relaxable_symbol(symbol) 1
932
933#endif
934
49864cfa
KR		 935/* Handle of the OPCODE hash table. NULL means any use before
936 m68k_ip_begin() will crash. */
937static struct hash_control *op_hash;
fecd2382 938\f
a1c7c0f3 939/* Assemble an m68k instruction. */
355afbcd 940
0917e2cb 941static void
355afbcd 942m68k_ip (instring)
6d27d3a2 943 char *instring;
fecd2382 944{
6d27d3a2
KR		 945 register char *p;
946 register struct m68k_op *opP;
48401fcf 947 register const struct m68k_incant *opcode;
a1c7c0f3 948 register const char *s;
6d27d3a2 949 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 950 char *pdot, *pdotmove;
a1c7c0f3 951 enum m68k_size siz1, siz2;
355afbcd
KR		 952 char c;
953 int losing;
954 int opsfound;
6d27d3a2
KR		 955 LITTLENUM_TYPE words[6];
956 LITTLENUM_TYPE *wordp;
8be74775 957 unsigned long ok_arch = 0;
6d27d3a2
KR		 958
959 if (*instring == ' ')
960 instring++; /* skip leading whitespace */
961
962 /* Scan up to end of operation-code, which MUST end in end-of-string
963 or exactly 1 space. */
3ad9ec6a 964 pdot = 0;
355afbcd
KR		 965 for (p = instring; *p != '\0'; p++)
966 {
967 if (*p == ' ')
968 break;
969 if (*p == '.')
970 pdot = p;
971 }
6d27d3a2 972
355afbcd
KR		 973 if (p == instring)
974 {
48401fcf 975 the_ins.error = _("No operator");
355afbcd
KR		 976 return;
977 }
6d27d3a2
KR		 978
979 /* p now points to the end of the opcode name, probably whitespace.
a1c7c0f3
ILT		 980 Make sure the name is null terminated by clobbering the
981 whitespace, look it up in the hash table, then fix it back.
3ad9ec6a 982 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 983 if (pdot != NULL)
984 {
985 for (pdotmove = pdot; pdotmove < p; pdotmove++)
986 *pdotmove = pdotmove[1];
987 p--;
988 }
3ad9ec6a 989
6d27d3a2
KR		 990 c = *p;
991 *p = '\0';
48401fcf 992 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 993 *p = c;
994
355afbcd
KR		 995 if (pdot != NULL)
996 {
997 for (pdotmove = p; pdotmove > pdot; pdotmove--)
998 *pdotmove = pdotmove[-1];
999 *pdot = '.';
1000 ++p;
1001 }
3ad9ec6a 1002
355afbcd
KR		 1003 if (opcode == NULL)
1004 {
48401fcf 1005 the_ins.error = _("Unknown operator");
355afbcd
KR		 1006 return;
1007 }
6d27d3a2
KR		 1008
1009 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 1010 while (*p == ' ')
1011 ++p;
6d27d3a2 1012
355afbcd
KR		 1013 if (opcode->m_operands == 0)
1014 {
1015 char *old = input_line_pointer;
1016 *old = '\n';
1017 input_line_pointer = p;
1018 /* Ahh - it's a motorola style psuedo op */
1019 mote_pseudo_table[opcode->m_opnum].poc_handler
1020 (mote_pseudo_table[opcode->m_opnum].poc_val);
1021 input_line_pointer = old;
1022 *old = 0;
3ad9ec6a 1023
355afbcd
KR		 1024 return;
1025 }
3ad9ec6a 1026
92a25e12
ILT		 1027 if (flag_mri && opcode->m_opnum == 0)
1028 {
1029 /* In MRI mode, random garbage is allowed after an instruction
1030 which accepts no operands. */
1031 the_ins.args = opcode->m_operands;
1032 the_ins.numargs = opcode->m_opnum;
1033 the_ins.numo = opcode->m_codenum;
1034 the_ins.opcode[0] = getone (opcode);
1035 the_ins.opcode[1] = gettwo (opcode);
1036 return;
1037 }
1038
355afbcd
KR		 1039 for (opP = &the_ins.operands[0]; *p; opP++)
1040 {
355afbcd 1041 p = crack_operand (p, opP);
6d27d3a2 1042
355afbcd
KR		 1043 if (opP->error)
1044 {
1045 the_ins.error = opP->error;
1046 return;
1047 }
6d27d3a2 1048 }
6d27d3a2
KR		 1049
1050 opsfound = opP - &the_ins.operands[0];
1051
a1c7c0f3
ILT		 1052 /* This ugly hack is to support the floating pt opcodes in their
1053 standard form. Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 1054 if (opcode->m_operands[0] == 'I')
1055 {
1056 int n;
6d27d3a2 1057
355afbcd
KR		 1058 for (n = opsfound; n > 0; --n)
1059 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 1060
a1c7c0f3
ILT		 1061 memset ((char *) (&the_ins.operands[0]), '\0',
1062 sizeof (the_ins.operands[0]));
1063 the_ins.operands[0].mode = CONTROL;
27a53b88 1064 the_ins.operands[0].reg = m68k_float_copnum;
355afbcd
KR		 1065 opsfound++;
1066 }
6d27d3a2
KR		 1067
1068 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 1069 for (losing = 0;;)
1070 {
49864cfa
KR		 1071 /* If we didn't get the right number of ops, or we have no
1072 common model with this pattern then reject this pattern. */
6d27d3a2 1073
0b810a6e 1074 ok_arch |= opcode->m_arch;
355afbcd
KR		 1075 if (opsfound != opcode->m_opnum
1076 || ((opcode->m_arch & current_architecture) == 0))
0b810a6e 1077 ++losing;
355afbcd
KR		 1078 else
1079 {
a1c7c0f3
ILT		 1080 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1081 *s && !losing;
1082 s += 2, opP++)
355afbcd
KR		 1083 {
1084 /* Warning: this switch is huge! */
49864cfa
KR		 1085 /* I've tried to organize the cases into this order:
1086 non-alpha first, then alpha by letter. Lower-case
1087 goes directly before uppercase counterpart. */
1088 /* Code with multiple case ...: gets sorted by the lowest
1089 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 1090 switch (*s)
1091 {
a1c7c0f3
ILT		 1092 case '!':
1093 switch (opP->mode)
1094 {
1095 case IMMED:
1096 case DREG:
1097 case AREG:
1098 case FPREG:
1099 case CONTROL:
1100 case AINC:
1101 case ADEC:
1102 case REGLST:
1103 losing++;
1104 break;
1105 default:
1106 break;
1107 }
355afbcd
KR		 1108 break;
1109
b4d51f3d
ILT		 1110 case '<':
1111 switch (opP->mode)
1112 {
1113 case DREG:
1114 case AREG:
1115 case FPREG:
1116 case CONTROL:
1117 case IMMED:
1118 case ADEC:
1119 case REGLST:
1120 losing++;
1121 break;
1122 default:
1123 break;
1124 }
1125 break;
1126
1127 case '>':
1128 switch (opP->mode)
1129 {
1130 case DREG:
1131 case AREG:
1132 case FPREG:
1133 case CONTROL:
1134 case IMMED:
1135 case AINC:
1136 case REGLST:
1137 losing++;
1138 break;
1139 case ABSL:
1140 break;
1141 default:
1142 if (opP->reg == PC
1143 || opP->reg == ZPC)
1144 losing++;
1145 break;
1146 }
1147 break;
1148
1149 case 'm':
1150 switch (opP->mode)
1151 {
1152 case DREG:
1153 case AREG:
1154 case AINDR:
1155 case AINC:
1156 case ADEC:
1157 break;
1158 default:
1159 losing++;
1160 }
1161 break;
1162
1163 case 'n':
1164 switch (opP->mode)
1165 {
1166 case DISP:
1167 break;
1168 default:
1169 losing++;
1170 }
1171 break;
1172
1173 case 'o':
1174 switch (opP->mode)
1175 {
1176 case BASE:
1177 case ABSL:
1178 case IMMED:
1179 break;
1180 default:
1181 losing++;
1182 }
1183 break;
1184
1185 case 'p':
1186 switch (opP->mode)
1187 {
1188 case DREG:
1189 case AREG:
1190 case AINDR:
1191 case AINC:
1192 case ADEC:
fee3e248 1193 break;
b4d51f3d 1194 case DISP:
fee3e248
ILT		 1195 if (opP->reg == PC || opP->reg == ZPC)
1196 losing++;
b4d51f3d
ILT		 1197 break;
1198 default:
1199 losing++;
1200 }
1201 break;
1202
469adf23
ILT		 1203 case 'q':
1204 switch (opP->mode)
1205 {
1206 case DREG:
1207 case AINDR:
1208 case AINC:
1209 case ADEC:
1210 break;
1211 case DISP:
1212 if (opP->reg == PC || opP->reg == ZPC)
1213 losing++;
1214 break;
1215 default:
1216 losing++;
1217 break;
1218 }
1219 break;
1220
1221 case 'v':
1222 switch (opP->mode)
1223 {
1224 case DREG:
1225 case AINDR:
1226 case AINC:
1227 case ADEC:
1228 case ABSL:
1229 break;
1230 case DISP:
1231 if (opP->reg == PC || opP->reg == ZPC)
1232 losing++;
1233 break;
1234 default:
1235 losing++;
1236 break;
1237 }
1238 break;
1239
355afbcd
KR		 1240 case '#':
1241 if (opP->mode != IMMED)
1242 losing++;
a1c7c0f3
ILT		 1243 else if (s[1] == 'b'
1244 && ! isvar (&opP->disp)
336435bc
ILT		 1245 && (opP->disp.exp.X_op != O_constant
1246 || ! isbyte (opP->disp.exp.X_add_number)))
a1c7c0f3 1247 losing++;
a78bc551
ILT		 1248 else if (s[1] == 'B'
1249 && ! isvar (&opP->disp)
1250 && (opP->disp.exp.X_op != O_constant
1251 || ! issbyte (opP->disp.exp.X_add_number)))
1252 losing++;
a1c7c0f3
ILT		 1253 else if (s[1] == 'w'
1254 && ! isvar (&opP->disp)
336435bc
ILT		 1255 && (opP->disp.exp.X_op != O_constant
1256 || ! isword (opP->disp.exp.X_add_number)))
a1c7c0f3 1257 losing++;
9e64486e
ILT		 1258 else if (s[1] == 'W'
1259 && ! isvar (&opP->disp)
1260 && (opP->disp.exp.X_op != O_constant
1261 || ! issword (opP->disp.exp.X_add_number)))
1262 losing++;
355afbcd
KR		 1263 break;
1264
1265 case '^':
1266 case 'T':
1267 if (opP->mode != IMMED)
1268 losing++;
1269 break;
1270
1271 case '$':
a1c7c0f3
ILT		 1272 if (opP->mode == AREG
1273 || opP->mode == CONTROL
1274 || opP->mode == FPREG
1275 || opP->mode == IMMED
1276 || opP->mode == REGLST
1277 || (opP->mode != ABSL
1278 && (opP->reg == PC
1279 || opP->reg == ZPC)))
355afbcd
KR		 1280 losing++;
1281 break;
1282
1283 case '%':
a1c7c0f3
ILT		 1284 if (opP->mode == CONTROL
1285 || opP->mode == FPREG
1286 || opP->mode == REGLST
a7512014 1287 || opP->mode == IMMED
a1c7c0f3 1288 || (opP->mode != ABSL
a1c7c0f3
ILT		 1289 && (opP->reg == PC
1290 || opP->reg == ZPC)))
355afbcd
KR		 1291 losing++;
1292 break;
1293
355afbcd 1294 case '&':
a1c7c0f3
ILT		 1295 switch (opP->mode)
1296 {
1297 case DREG:
1298 case AREG:
1299 case FPREG:
1300 case CONTROL:
1301 case IMMED:
1302 case AINC:
1303 case ADEC:
1304 case REGLST:
1305 losing++;
1306 break;
1307 case ABSL:
1308 break;
1309 default:
1310 if (opP->reg == PC
1311 || opP->reg == ZPC)
1312 losing++;
1313 break;
1314 }
355afbcd
KR		 1315 break;
1316
1317 case '*':
a1c7c0f3
ILT		 1318 if (opP->mode == CONTROL
1319 || opP->mode == FPREG
1320 || opP->mode == REGLST)
355afbcd
KR		 1321 losing++;
1322 break;
1323
1324 case '+':
1325 if (opP->mode != AINC)
1326 losing++;
1327 break;
1328
1329 case '-':
1330 if (opP->mode != ADEC)
1331 losing++;
1332 break;
1333
1334 case '/':
a1c7c0f3
ILT		 1335 switch (opP->mode)
1336 {
1337 case AREG:
1338 case CONTROL:
1339 case FPREG:
1340 case AINC:
1341 case ADEC:
1342 case IMMED:
1343 case REGLST:
1344 losing++;
1345 break;
1346 default:
1347 break;
1348 }
355afbcd
KR		 1349 break;
1350
1351 case ';':
a1c7c0f3
ILT		 1352 switch (opP->mode)
1353 {
1354 case AREG:
1355 case CONTROL:
1356 case FPREG:
1357 case REGLST:
1358 losing++;
1359 break;
1360 default:
1361 break;
1362 }
355afbcd
KR		 1363 break;
1364
1365 case '?':
a1c7c0f3
ILT		 1366 switch (opP->mode)
1367 {
1368 case AREG:
1369 case CONTROL:
1370 case FPREG:
1371 case AINC:
1372 case ADEC:
1373 case IMMED:
1374 case REGLST:
1375 losing++;
1376 break;
1377 case ABSL:
1378 break;
1379 default:
1380 if (opP->reg == PC || opP->reg == ZPC)
1381 losing++;
1382 break;
1383 }
355afbcd
KR		 1384 break;
1385
1386 case '@':
a1c7c0f3
ILT		 1387 switch (opP->mode)
1388 {
1389 case AREG:
1390 case CONTROL:
1391 case FPREG:
1392 case IMMED:
1393 case REGLST:
1394 losing++;
1395 break;
1396 default:
1397 break;
1398 }
355afbcd
KR		 1399 break;
1400
1401 case '~': /* For now! (JF FOO is this right?) */
a1c7c0f3
ILT		 1402 switch (opP->mode)
1403 {
1404 case DREG:
1405 case AREG:
1406 case CONTROL:
1407 case FPREG:
1408 case IMMED:
1409 case REGLST:
1410 losing++;
1411 break;
1412 case ABSL:
1413 break;
1414 default:
1415 if (opP->reg == PC
1416 || opP->reg == ZPC)
1417 losing++;
1418 break;
1419 }
355afbcd
KR		 1420 break;
1421
1422 case '3':
a1c7c0f3
ILT		 1423 if (opP->mode != CONTROL
1424 || (opP->reg != TT0 && opP->reg != TT1))
355afbcd
KR		 1425 losing++;
1426 break;
1427
1428 case 'A':
1429 if (opP->mode != AREG)
1430 losing++;
1431 break;
a1c7c0f3 1432
355afbcd
KR		 1433 case 'a':
1434 if (opP->mode != AINDR)
a1c7c0f3 1435 ++losing;
355afbcd 1436 break;
a1c7c0f3 1437
355afbcd 1438 case 'B': /* FOO */
a1c7c0f3
ILT		 1439 if (opP->mode != ABSL
1440 || (flag_long_jumps
1441 && strncmp (instring, "jbsr", 4) == 0))
355afbcd
KR		 1442 losing++;
1443 break;
1444
1445 case 'C':
a1c7c0f3 1446 if (opP->mode != CONTROL || opP->reg != CCR)
355afbcd
KR		 1447 losing++;
1448 break;
1449
a1c7c0f3
ILT		 1450 case 'd':
1451 if (opP->mode != DISP
1452 || opP->reg < ADDR0
1453 || opP->reg > ADDR7)
355afbcd
KR		 1454 losing++;
1455 break;
1456
1457 case 'D':
1458 if (opP->mode != DREG)
1459 losing++;
1460 break;
1461
1462 case 'F':
a1c7c0f3 1463 if (opP->mode != FPREG)
355afbcd
KR		 1464 losing++;
1465 break;
1466
1467 case 'I':
a1c7c0f3 1468 if (opP->mode != CONTROL
27a53b88
ILT		 1469 || opP->reg < COP0
1470 || opP->reg > COP7)
355afbcd
KR		 1471 losing++;
1472 break;
1473
1474 case 'J':
a1c7c0f3 1475 if (opP->mode != CONTROL
355afbcd 1476 || opP->reg < USP
82489ea0
KR		 1477 || opP->reg > last_movec_reg)
1478 losing++;
1479 else
355afbcd 1480 {
a1c7c0f3 1481 const enum m68k_register *rp;
82489ea0
KR		 1482 for (rp = control_regs; *rp; rp++)
1483 if (*rp == opP->reg)
1484 break;
1485 if (*rp == 0)
1486 losing++;
1487 }
355afbcd
KR		 1488 break;
1489
1490 case 'k':
1491 if (opP->mode != IMMED)
1492 losing++;
1493 break;
8be74775 1494
355afbcd
KR		 1495 case 'l':
1496 case 'L':
a1c7c0f3
ILT		 1497 if (opP->mode == DREG
1498 || opP->mode == AREG
1499 || opP->mode == FPREG)
355afbcd
KR		 1500 {
1501 if (s[1] == '8')
1502 losing++;
1503 else
1504 {
a1c7c0f3
ILT		 1505 switch (opP->mode)
1506 {
1507 case DREG:
1508 opP->mask = 1 << (opP->reg - DATA0);
1509 break;
1510 case AREG:
1511 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1512 break;
1513 case FPREG:
1514 opP->mask = 1 << (opP->reg - FP0 + 16);
1515 break;
1516 default:
1517 abort ();
1518 }
355afbcd 1519 opP->mode = REGLST;
355afbcd
KR		 1520 }
1521 }
a1c7c0f3 1522 else if (opP->mode == CONTROL)
355afbcd 1523 {
a1c7c0f3
ILT		 1524 if (s[1] != '8')
1525 losing++;
1526 else
1527 {
1528 switch (opP->reg)
1529 {
1530 case FPI:
1531 opP->mask = 1 << 24;
1532 break;
1533 case FPS:
1534 opP->mask = 1 << 25;
1535 break;
1536 case FPC:
1537 opP->mask = 1 << 26;
1538 break;
1539 default:
1540 losing++;
1541 break;
1542 }
1543 opP->mode = REGLST;
1544 }
355afbcd 1545 }
a1c7c0f3 1546 else if (opP->mode != REGLST)
355afbcd 1547 losing++;
a1c7c0f3
ILT		 1548 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1549 losing++;
1550 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
355afbcd
KR		 1551 losing++;
1552 break;
1553
1554 case 'M':
1555 if (opP->mode != IMMED)
1556 losing++;
336435bc
ILT		 1557 else if (opP->disp.exp.X_op != O_constant
1558 || ! issbyte (opP->disp.exp.X_add_number))
a1c7c0f3 1559 losing++;
6700d36e
ILT		 1560 else if (! m68k_quick
1561 && instring[3] != 'q'
1562 && instring[4] != 'q')
1563 losing++;
355afbcd 1564 break;
8be74775 1565
355afbcd 1566 case 'O':
8d20a0a8
C		 1567 if (opP->mode != DREG
1568 && opP->mode != IMMED
1569 && opP->mode != ABSL)
355afbcd
KR		 1570 losing++;
1571 break;
6d27d3a2 1572
355afbcd
KR		 1573 case 'Q':
1574 if (opP->mode != IMMED)
1575 losing++;
336435bc 1576 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1577 || opP->disp.exp.X_add_number < 1
1578 || opP->disp.exp.X_add_number > 8)
1579 losing++;
6700d36e
ILT		 1580 else if (! m68k_quick
1581 && (strncmp (instring, "add", 3) == 0
1582 || strncmp (instring, "sub", 3) == 0)
1583 && instring[3] != 'q')
1584 losing++;
355afbcd 1585 break;
8be74775 1586
355afbcd
KR		 1587 case 'R':
1588 if (opP->mode != DREG && opP->mode != AREG)
1589 losing++;
1590 break;
8be74775 1591
355afbcd 1592 case 'r':
a1c7c0f3
ILT		 1593 if (opP->mode != AINDR
1594 && (opP->mode != BASE
1595 || (opP->reg != 0
1596 && opP->reg != ZADDR0)
1597 || opP->disp.exp.X_op != O_absent
1598 || ((opP->index.reg < DATA0
1599 || opP->index.reg > DATA7)
1600 && (opP->index.reg < ADDR0
1601 || opP->index.reg > ADDR7))
1602 || opP->index.size != SIZE_UNSPEC
1603 || opP->index.scale != 1))
355afbcd
KR		 1604 losing++;
1605 break;
c50140c8 1606
355afbcd 1607 case 's':
a1c7c0f3
ILT		 1608 if (opP->mode != CONTROL
1609 || ! (opP->reg == FPI
1610 || opP->reg == FPS
1611 || opP->reg == FPC))
355afbcd
KR		 1612 losing++;
1613 break;
8be74775 1614
355afbcd 1615 case 'S':
a1c7c0f3 1616 if (opP->mode != CONTROL || opP->reg != SR)
355afbcd
KR		 1617 losing++;
1618 break;
8be74775 1619
355afbcd
KR		 1620 case 't':
1621 if (opP->mode != IMMED)
1622 losing++;
336435bc 1623 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1624 || opP->disp.exp.X_add_number < 0
1625 || opP->disp.exp.X_add_number > 7)
1626 losing++;
355afbcd 1627 break;
4134a793 1628
355afbcd 1629 case 'U':
a1c7c0f3 1630 if (opP->mode != CONTROL || opP->reg != USP)
355afbcd
KR		 1631 losing++;
1632 break;
8be74775 1633
355afbcd 1634 /* JF these are out of order. We could put them
1404ef23
KR		 1635 in order if we were willing to put up with
1636 bunches of #ifdef m68851s in the code.
4134a793 1637
1404ef23
KR		 1638 Don't forget that you need these operands
1639 to use 68030 MMU instructions. */
f8701a3f 1640#ifndef NO_68851
355afbcd
KR		 1641 /* Memory addressing mode used by pflushr */
1642 case '|':
a1c7c0f3
ILT		 1643 if (opP->mode == CONTROL
1644 || opP->mode == FPREG
1645 || opP->mode == DREG
1646 || opP->mode == AREG
1647 || opP->mode == REGLST)
355afbcd 1648 losing++;
9adcd781
ILT		 1649 /* We should accept immediate operands, but they
1650 supposedly have to be quad word, and we don't
1651 handle that. I would like to see what a Motorola
1652 assembler does before doing something here. */
1653 if (opP->mode == IMMED)
1654 losing++;
355afbcd
KR		 1655 break;
1656
1657 case 'f':
a1c7c0f3
ILT		 1658 if (opP->mode != CONTROL
1659 || (opP->reg != SFC && opP->reg != DFC))
355afbcd
KR		 1660 losing++;
1661 break;
1662
9adcd781
ILT		 1663 case '0':
1664 if (opP->mode != CONTROL || opP->reg != TC)
1665 losing++;
1666 break;
1667
1668 case '1':
1669 if (opP->mode != CONTROL || opP->reg != AC)
1670 losing++;
1671 break;
1672
1673 case '2':
a1c7c0f3 1674 if (opP->mode != CONTROL
9adcd781 1675 || (opP->reg != CAL
a1c7c0f3 1676 && opP->reg != VAL
9adcd781 1677 && opP->reg != SCC))
355afbcd
KR		 1678 losing++;
1679 break;
1680
1681 case 'V':
a1c7c0f3
ILT		 1682 if (opP->mode != CONTROL
1683 || opP->reg != VAL)
355afbcd
KR		 1684 losing++;
1685 break;
8be74775 1686
355afbcd 1687 case 'W':
a1c7c0f3
ILT		 1688 if (opP->mode != CONTROL
1689 || (opP->reg != DRP
1690 && opP->reg != SRP
355afbcd
KR		 1691 && opP->reg != CRP))
1692 losing++;
1693 break;
1694
1695 case 'X':
a1c7c0f3
ILT		 1696 if (opP->mode != CONTROL
1697 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1698 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
355afbcd
KR		 1699 losing++;
1700 break;
1701
1702 case 'Y':
a1c7c0f3 1703 if (opP->mode != CONTROL || opP->reg != PSR)
355afbcd
KR		 1704 losing++;
1705 break;
1706
1707 case 'Z':
a1c7c0f3 1708 if (opP->mode != CONTROL || opP->reg != PCSR)
355afbcd
KR		 1709 losing++;
1710 break;
f8701a3f 1711#endif
355afbcd 1712 case 'c':
a1c7c0f3
ILT		 1713 if (opP->mode != CONTROL
1714 || (opP->reg != NC
1715 && opP->reg != IC
1716 && opP->reg != DC
1717 && opP->reg != BC))
355afbcd
KR		 1718 {
1719 losing++;
1720 } /* not a cache specifier. */
1721 break;
1722
1723 case '_':
1724 if (opP->mode != ABSL)
a1c7c0f3 1725 ++losing;
355afbcd 1726 break;
8be74775 1727
355afbcd 1728 default:
a1c7c0f3 1729 abort ();
355afbcd 1730 } /* switch on type of operand */
6d27d3a2 1731
355afbcd
KR		 1732 if (losing)
1733 break;
1734 } /* for each operand */
1735 } /* if immediately wrong */
6d27d3a2 1736
355afbcd
KR		 1737 if (!losing)
1738 {
8be74775 1739 break;
355afbcd 1740 } /* got it. */
6d27d3a2 1741
355afbcd 1742 opcode = opcode->m_next;
6d27d3a2 1743
355afbcd 1744 if (!opcode)
8be74775 1745 {
355afbcd
KR		 1746 if (ok_arch
1747 && !(ok_arch & current_architecture))
8be74775 1748 {
355afbcd 1749 char buf[200], *cp;
091221ce 1750
a1c7c0f3 1751 strcpy (buf,
48401fcf 1752 _("invalid instruction for this architecture; needs "));
355afbcd
KR		 1753 cp = buf + strlen (buf);
1754 switch (ok_arch)
1755 {
1756 case mfloat:
48401fcf 1757 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
355afbcd
KR		 1758 break;
1759 case mmmu:
48401fcf 1760 strcpy (cp, _("mmu (68030 or 68851)"));
355afbcd
KR		 1761 break;
1762 case m68020up:
48401fcf 1763 strcpy (cp, _("68020 or higher"));
355afbcd
KR		 1764 break;
1765 case m68000up:
48401fcf 1766 strcpy (cp, _("68000 or higher"));
355afbcd
KR		 1767 break;
1768 case m68010up:
48401fcf 1769 strcpy (cp, _("68010 or higher"));
355afbcd
KR		 1770 break;
1771 default:
8be74775 1772 {
355afbcd 1773 int got_one = 0, idx;
a1c7c0f3
ILT		 1774 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1775 idx++)
8be74775 1776 {
9e64486e
ILT		 1777 if ((archs[idx].arch & ok_arch)
1778 && ! archs[idx].alias)
8be74775 1779 {
355afbcd
KR		 1780 if (got_one)
1781 {
1782 strcpy (cp, " or ");
1783 cp += strlen (cp);
1784 }
1785 got_one = 1;
1786 strcpy (cp, archs[idx].name);
8be74775
KR		 1787 cp += strlen (cp);
1788 }
8be74775
KR		 1789 }
1790 }
355afbcd 1791 }
091221ce 1792 cp = xmalloc (strlen (buf) + 1);
355afbcd
KR		 1793 strcpy (cp, buf);
1794 the_ins.error = cp;
8be74775 1795 }
355afbcd 1796 else
48401fcf 1797 the_ins.error = _("operands mismatch");
355afbcd
KR		 1798 return;
1799 } /* Fell off the end */
6d27d3a2 1800
355afbcd
KR		 1801 losing = 0;
1802 }
6d27d3a2
KR		 1803
1804 /* now assemble it */
1805
355afbcd
KR		 1806 the_ins.args = opcode->m_operands;
1807 the_ins.numargs = opcode->m_opnum;
1808 the_ins.numo = opcode->m_codenum;
1809 the_ins.opcode[0] = getone (opcode);
1810 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 1811
355afbcd
KR		 1812 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1813 {
1814 /* This switch is a doozy.
6d27d3a2 1815 Watch the first step; its a big one! */
355afbcd
KR		 1816 switch (s[0])
1817 {
6d27d3a2 1818
355afbcd
KR		 1819 case '*':
1820 case '~':
1821 case '%':
1822 case ';':
1823 case '@':
1824 case '!':
1825 case '&':
1826 case '$':
1827 case '?':
1828 case '/':
b4d51f3d
ILT		 1829 case '<':
1830 case '>':
1831 case 'm':
1832 case 'n':
1833 case 'o':
1834 case 'p':
469adf23
ILT		 1835 case 'q':
1836 case 'v':
355afbcd
KR		 1837#ifndef NO_68851
1838 case '|':
1839#endif
1840 switch (opP->mode)
1841 {
1842 case IMMED:
1843 tmpreg = 0x3c; /* 7.4 */
1844 if (strchr ("bwl", s[1]))
a1c7c0f3 1845 nextword = get_num (&opP->disp, 80);
355afbcd 1846 else
a1c7c0f3
ILT		 1847 nextword = get_num (&opP->disp, 0);
1848 if (isvar (&opP->disp))
1849 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1850 switch (s[1])
1851 {
1852 case 'b':
1853 if (!isbyte (nextword))
48401fcf 1854 opP->error = _("operand out of range");
355afbcd
KR		 1855 addword (nextword);
1856 baseo = 0;
1857 break;
1858 case 'w':
1859 if (!isword (nextword))
48401fcf 1860 opP->error = _("operand out of range");
355afbcd
KR		 1861 addword (nextword);
1862 baseo = 0;
1863 break;
9e64486e
ILT		 1864 case 'W':
1865 if (!issword (nextword))
48401fcf 1866 opP->error = _("operand out of range");
9e64486e
ILT		 1867 addword (nextword);
1868 baseo = 0;
1869 break;
355afbcd
KR		 1870 case 'l':
1871 addword (nextword >> 16);
1872 addword (nextword);
1873 baseo = 0;
1874 break;
1875
1876 case 'f':
1877 baseo = 2;
1878 outro = 8;
1879 break;
1880 case 'F':
1881 baseo = 4;
1882 outro = 11;
1883 break;
1884 case 'x':
1885 baseo = 6;
1886 outro = 15;
1887 break;
1888 case 'p':
1889 baseo = 6;
1890 outro = -1;
1891 break;
1892 default:
a1c7c0f3 1893 abort ();
355afbcd
KR		 1894 }
1895 if (!baseo)
1896 break;
6d27d3a2 1897
355afbcd 1898 /* We gotta put out some float */
a1c7c0f3 1899 if (op (&opP->disp) != O_big)
355afbcd 1900 {
bcb8dff8
KR		 1901 valueT val;
1902 int gencnt;
1903
1904 /* Can other cases happen here? */
a1c7c0f3 1905 if (op (&opP->disp) != O_constant)
bcb8dff8 1906 abort ();
82489ea0 1907
a1c7c0f3 1908 val = (valueT) offs (&opP->disp);
bcb8dff8
KR		 1909 gencnt = 0;
1910 do
1911 {
1912 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1913 val >>= LITTLENUM_NUMBER_OF_BITS;
1914 ++gencnt;
1915 }
1916 while (val != 0);
a1c7c0f3 1917 offs (&opP->disp) = gencnt;
355afbcd 1918 }
a1c7c0f3 1919 if (offs (&opP->disp) > 0)
355afbcd 1920 {
a1c7c0f3 1921 if (offs (&opP->disp) > baseo)
355afbcd 1922 {
48401fcf 1923 as_warn (_("Bignum too big for %c format; truncated"),
a1c7c0f3
ILT		 1924 s[1]);
1925 offs (&opP->disp) = baseo;
355afbcd 1926 }
a1c7c0f3 1927 baseo -= offs (&opP->disp);
355afbcd
KR		 1928 while (baseo--)
1929 addword (0);
a1c7c0f3
ILT		 1930 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1931 offs (&opP->disp)--;
1932 --wordp)
bcb8dff8 1933 addword (*wordp);
355afbcd
KR		 1934 break;
1935 }
1936 gen_to_words (words, baseo, (long) outro);
1937 for (wordp = words; baseo--; wordp++)
1938 addword (*wordp);
1939 break;
1940 case DREG:
1941 tmpreg = opP->reg - DATA; /* 0.dreg */
1942 break;
1943 case AREG:
1944 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1945 break;
1946 case AINDR:
1947 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1948 break;
1949 case ADEC:
1950 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1951 break;
1952 case AINC:
1953 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1954 break;
a1c7c0f3 1955 case DISP:
6d27d3a2 1956
a1c7c0f3 1957 nextword = get_num (&opP->disp, 80);
6700d36e
ILT		 1958
1959 if (opP->reg == PC
1960 && ! isvar (&opP->disp)
1961 && m68k_abspcadd)
1962 {
1963 opP->disp.exp.X_op = O_symbol;
1964#ifndef BFD_ASSEMBLER
1965 opP->disp.exp.X_add_symbol = &abs_symbol;
1966#else
1967 opP->disp.exp.X_add_symbol =
1968 section_symbol (absolute_section);
1969#endif
1970 }
1971
355afbcd 1972 /* Force into index mode. Hope this works */
6d27d3a2 1973
1404ef23
KR		 1974 /* We do the first bit for 32-bit displacements, and the
1975 second bit for 16 bit ones. It is possible that we
1976 should make the default be WORD instead of LONG, but
1977 I think that'd break GCC, so we put up with a little
1978 inefficiency for the sake of working output. */
6d27d3a2 1979
355afbcd 1980 if (!issword (nextword)
a1c7c0f3
ILT		 1981 || (isvar (&opP->disp)
1982 && ((opP->disp.size == SIZE_UNSPEC
b79de3a1 1983 && flag_short_refs == 0
48401fcf
TT		 1984 && cpu_of_arch (current_architecture) >= m68020
1985 && cpu_of_arch (current_architecture) != mcf5200)
a1c7c0f3 1986 || opP->disp.size == SIZE_LONG)))
355afbcd 1987 {
48401fcf
TT		 1988 if (cpu_of_arch (current_architecture) < m68020
1989 || cpu_of_arch (current_architecture) == mcf5200)
912e4245 1990 opP->error =
48401fcf 1991 _("displacement too large for this architecture; needs 68020 or higher");
355afbcd
KR		 1992 if (opP->reg == PC)
1993 tmpreg = 0x3B; /* 7.3 */
1994 else
1995 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
a1c7c0f3 1996 if (isvar (&opP->disp))
355afbcd
KR		 1997 {
1998 if (opP->reg == PC)
1999 {
a043f579
ILT		 2000 if (opP->disp.size == SIZE_LONG
2001#ifdef OBJ_ELF
2002 /* If the displacement needs pic
2003 relocation it cannot be relaxed. */
2004 || opP->disp.pic_reloc != pic_none
04ef74bb 2005#endif
a043f579
ILT		 2006 )
2007 {
2008 addword (0x0170);
2009 add_fix ('l', &opP->disp, 1, 2);
2010 }
2011 else
2012 {
2013 add_frag (adds (&opP->disp),
2014 offs (&opP->disp),
2015 TAB (PCLEA, SZ_UNDEF));
2016 break;
2017 }
355afbcd
KR		 2018 }
2019 else
2020 {
2021 addword (0x0170);
a1c7c0f3 2022 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 2023 }
2024 }
2025 else
2026 addword (0x0170);
2027 addword (nextword >> 16);
2028 }
2029 else
2030 {
2031 if (opP->reg == PC)
2032 tmpreg = 0x3A; /* 7.2 */
2033 else
2034 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2035
a1c7c0f3 2036 if (isvar (&opP->disp))
355afbcd
KR		 2037 {
2038 if (opP->reg == PC)
2039 {
a1c7c0f3 2040 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2041 }
2042 else
a1c7c0f3 2043 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 2044 }
2045 }
2046 addword (nextword);
6d27d3a2 2047 break;
6d27d3a2 2048
a1c7c0f3
ILT		 2049 case POST:
2050 case PRE:
2051 case BASE:
355afbcd 2052 nextword = 0;
a1c7c0f3
ILT		 2053 baseo = get_num (&opP->disp, 80);
2054 if (opP->mode == POST || opP->mode == PRE)
2055 outro = get_num (&opP->odisp, 80);
49864cfa
KR		 2056 /* Figure out the `addressing mode'.
2057 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 2058 if (opP->reg == PC || opP->reg == ZPC)
2059 {
a1c7c0f3 2060 tmpreg = 0x3b; /* 7.3 */
355afbcd
KR		 2061 if (opP->reg == ZPC)
2062 nextword |= 0x80;
2063 }
a1c7c0f3
ILT		 2064 else if (opP->reg == 0)
2065 {
2066 nextword |= 0x80;
2067 tmpreg = 0x30; /* 6.garbage */
2068 }
2069 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
355afbcd
KR		 2070 {
2071 nextword |= 0x80;
a1c7c0f3 2072 tmpreg = 0x30 + opP->reg - ZADDR0;
355afbcd
KR		 2073 }
2074 else
2075 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2076
a1c7c0f3
ILT		 2077 siz1 = opP->disp.size;
2078 if (opP->mode == POST || opP->mode == PRE)
2079 siz2 = opP->odisp.size;
2080 else
2081 siz2 = SIZE_UNSPEC;
355afbcd
KR		 2082
2083 /* Index register stuff */
a1c7c0f3
ILT		 2084 if (opP->index.reg != 0
2085 && opP->index.reg >= DATA
2086 && opP->index.reg <= ADDR7)
355afbcd 2087 {
a1c7c0f3 2088 nextword |= (opP->index.reg - DATA) << 12;
355afbcd 2089
b4d51f3d
ILT		 2090 if (opP->index.size == SIZE_LONG
2091 || (opP->index.size == SIZE_UNSPEC
2092 && m68k_index_width_default == SIZE_LONG))
355afbcd 2093 nextword |= 0x800;
a1c7c0f3 2094
8d20a0a8
C		 2095 if ((opP->index.scale != 1
2096 && cpu_of_arch (current_architecture) < m68020)
2097 || (opP->index.scale == 8
2098 && current_architecture == mcf5200))
a1c7c0f3 2099 {
8d20a0a8 2100 opP->error =
48401fcf 2101 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
a1c7c0f3
ILT		 2102 }
2103
2104 switch (opP->index.scale)
355afbcd
KR		 2105 {
2106 case 1:
2107 break;
2108 case 2:
2109 nextword |= 0x200;
2110 break;
2111 case 4:
2112 nextword |= 0x400;
2113 break;
2114 case 8:
2115 nextword |= 0x600;
2116 break;
2117 default:
a1c7c0f3 2118 abort ();
355afbcd
KR		 2119 }
2120 /* IF its simple,
49864cfa 2121 GET US OUT OF HERE! */
6d27d3a2 2122
04ef74bb
KR		 2123 /* Must be INDEX, with an index register. Address
2124 register cannot be ZERO-PC, and either :b was
2125 forced, or we know it will fit. For a 68000 or
2126 68010, force this mode anyways, because the
2127 larger modes aren't supported. */
a1c7c0f3
ILT		 2128 if (opP->mode == BASE
2129 && ((opP->reg >= ADDR0
2130 && opP->reg <= ADDR7)
2131 || opP->reg == PC))
355afbcd 2132 {
a1c7c0f3
ILT		 2133 if (siz1 == SIZE_BYTE
2134 || cpu_of_arch (current_architecture) < m68020
48401fcf 2135 || cpu_of_arch (current_architecture) == mcf5200
a1c7c0f3
ILT		 2136 || (siz1 == SIZE_UNSPEC
2137 && ! isvar (&opP->disp)
2138 && issbyte (baseo)))
2139 {
5f8cb05e
ILT		 2140 nextword += baseo & 0xff;
2141 addword (nextword);
a1c7c0f3 2142 if (isvar (&opP->disp))
04ef74bb 2143 {
a1c7c0f3
ILT		 2144 /* Do a byte relocation. If it doesn't
2145 fit (possible on m68000) let the
2146 fixup processing complain later. */
5f8cb05e 2147 if (opP->reg == PC)
a1c7c0f3 2148 add_fix ('B', &opP->disp, 1, 1);
5f8cb05e 2149 else
a1c7c0f3 2150 add_fix ('B', &opP->disp, 0, 0);
04ef74bb 2151 }
a1c7c0f3
ILT		 2152 else if (siz1 != SIZE_BYTE)
2153 {
2154 if (siz1 != SIZE_UNSPEC)
48401fcf 2155 as_warn (_("Forcing byte displacement"));
a1c7c0f3 2156 if (! issbyte (baseo))
48401fcf 2157 opP->error = _("byte displacement out of range");
a1c7c0f3
ILT		 2158 }
2159
2160 break;
2161 }
2162 else if (siz1 == SIZE_UNSPEC
2163 && opP->reg == PC
2164 && isvar (&opP->disp)
a043f579
ILT		 2165 && subs (&opP->disp) == NULL
2166#ifdef OBJ_ELF
2167 /* If the displacement needs pic
2168 relocation it cannot be relaxed. */
2169 && opP->disp.pic_reloc == pic_none
2170#endif
2171 )
a1c7c0f3 2172 {
2156d0d7
ILT		 2173 /* The code in md_convert_frag_1 needs to be
2174 able to adjust nextword. Call frag_grow
2175 to ensure that we have enough space in
2176 the frag obstack to make all the bytes
2177 contiguous. */
2178 frag_grow (14);
5f8cb05e
ILT		 2179 nextword += baseo & 0xff;
2180 addword (nextword);
a1c7c0f3 2181 add_frag (adds (&opP->disp), offs (&opP->disp),
5f8cb05e 2182 TAB (PCINDEX, SZ_UNDEF));
a1c7c0f3
ILT		 2183
2184 break;
5f8cb05e 2185 }
355afbcd
KR		 2186 }
2187 }
2188 else
a1c7c0f3
ILT		 2189 {
2190 nextword |= 0x40; /* No index reg */
2191 if (opP->index.reg >= ZDATA0
2192 && opP->index.reg <= ZDATA7)
2193 nextword |= (opP->index.reg - ZDATA0) << 12;
2194 else if (opP->index.reg >= ZADDR0
2195 || opP->index.reg <= ZADDR7)
2196 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2197 }
6d27d3a2 2198
49864cfa 2199 /* It isn't simple. */
a1c7c0f3 2200
48401fcf
TT		 2201 if (cpu_of_arch (current_architecture) < m68020
2202 || cpu_of_arch (current_architecture) == mcf5200)
a1c7c0f3 2203 opP->error =
48401fcf 2204 _("invalid operand mode for this architecture; needs 68020 or higher");
a1c7c0f3 2205
355afbcd 2206 nextword |= 0x100;
49864cfa
KR		 2207 /* If the guy specified a width, we assume that it is
2208 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 2209 switch (siz1)
2210 {
a1c7c0f3 2211 case SIZE_UNSPEC:
6700d36e
ILT		 2212 if (isvar (&opP->disp)
2213 ? m68k_rel32
2214 : ! issword (baseo))
355afbcd 2215 {
a1c7c0f3 2216 siz1 = SIZE_LONG;
355afbcd
KR		 2217 nextword |= 0x30;
2218 }
6700d36e 2219 else if (! isvar (&opP->disp) && baseo == 0)
355afbcd
KR		 2220 nextword |= 0x10;
2221 else
2222 {
2223 nextword |= 0x20;
a1c7c0f3 2224 siz1 = SIZE_WORD;
355afbcd
KR		 2225 }
2226 break;
a1c7c0f3 2227 case SIZE_BYTE:
48401fcf 2228 as_warn (_(":b not permitted; defaulting to :w"));
a1c7c0f3
ILT		 2229 /* Fall through. */
2230 case SIZE_WORD:
355afbcd
KR		 2231 nextword |= 0x20;
2232 break;
a1c7c0f3 2233 case SIZE_LONG:
355afbcd
KR		 2234 nextword |= 0x30;
2235 break;
2236 }
6d27d3a2 2237
355afbcd 2238 /* Figure out innner displacement stuff */
a1c7c0f3 2239 if (opP->mode == POST || opP->mode == PRE)
355afbcd 2240 {
8d20a0a8 2241 if (cpu_of_arch (current_architecture) & cpu32)
48401fcf 2242 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
355afbcd
KR		 2243 switch (siz2)
2244 {
a1c7c0f3 2245 case SIZE_UNSPEC:
6700d36e
ILT		 2246 if (isvar (&opP->odisp)
2247 ? m68k_rel32
2248 : ! issword (outro))
355afbcd 2249 {
a1c7c0f3 2250 siz2 = SIZE_LONG;
355afbcd
KR		 2251 nextword |= 0x3;
2252 }
92a25e12 2253 else if (! isvar (&opP->odisp) && outro == 0)
355afbcd
KR		 2254 nextword |= 0x1;
2255 else
2256 {
2257 nextword |= 0x2;
a1c7c0f3 2258 siz2 = SIZE_WORD;
355afbcd
KR		 2259 }
2260 break;
2261 case 1:
48401fcf 2262 as_warn (_(":b not permitted; defaulting to :w"));
a1c7c0f3 2263 /* Fall through. */
355afbcd
KR		 2264 case 2:
2265 nextword |= 0x2;
2266 break;
2267 case 3:
2268 nextword |= 0x3;
2269 break;
2270 }
92a25e12
ILT		 2271 if (opP->mode == POST
2272 && (nextword & 0x40) == 0)
355afbcd 2273 nextword |= 0x04;
355afbcd
KR		 2274 }
2275 addword (nextword);
2276
a1c7c0f3 2277 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
355afbcd
KR		 2278 {
2279 if (opP->reg == PC || opP->reg == ZPC)
a1c7c0f3 2280 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
355afbcd 2281 else
a1c7c0f3 2282 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
355afbcd 2283 }
a1c7c0f3 2284 if (siz1 == SIZE_LONG)
355afbcd 2285 addword (baseo >> 16);
a1c7c0f3 2286 if (siz1 != SIZE_UNSPEC)
355afbcd
KR		 2287 addword (baseo);
2288
a1c7c0f3
ILT		 2289 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2290 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2291 if (siz2 == SIZE_LONG)
355afbcd 2292 addword (outro >> 16);
a1c7c0f3 2293 if (siz2 != SIZE_UNSPEC)
355afbcd 2294 addword (outro);
6d27d3a2 2295
355afbcd 2296 break;
6d27d3a2 2297
355afbcd 2298 case ABSL:
a1c7c0f3
ILT		 2299 nextword = get_num (&opP->disp, 80);
2300 switch (opP->disp.size)
355afbcd
KR		 2301 {
2302 default:
a1c7c0f3
ILT		 2303 abort ();
2304 case SIZE_UNSPEC:
2305 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
355afbcd
KR		 2306 {
2307 tmpreg = 0x38; /* 7.0 */
2308 addword (nextword);
2309 break;
2310 }
bcb8dff8
KR		 2311 /* Don't generate pc relative code on 68010 and
2312 68000. */
a1c7c0f3
ILT		 2313 if (isvar (&opP->disp)
2314 && !subs (&opP->disp)
2315 && adds (&opP->disp)
a043f579
ILT		 2316#ifdef OBJ_ELF
2317 /* If the displacement needs pic relocation it
2318 cannot be relaxed. */
2319 && opP->disp.pic_reloc == pic_none
2320#endif
f00f5ecd 2321 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
dcb76edb 2322 && relaxable_symbol (adds (&opP->disp))
ffecfc8b 2323 && HAVE_LONG_BRANCH(current_architecture)
9ad5755f 2324 && !flag_long_jumps
355afbcd
KR		 2325 && !strchr ("~%&$?", s[0]))
2326 {
2327 tmpreg = 0x3A; /* 7.2 */
a1c7c0f3
ILT		 2328 add_frag (adds (&opP->disp),
2329 offs (&opP->disp),
355afbcd
KR		 2330 TAB (PCREL, SZ_UNDEF));
2331 break;
2332 }
04ef74bb 2333 /* Fall through into long */
a1c7c0f3
ILT		 2334 case SIZE_LONG:
2335 if (isvar (&opP->disp))
2336 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 2337
2338 tmpreg = 0x39;/* 7.1 mode */
2339 addword (nextword >> 16);
2340 addword (nextword);
2341 break;
2342
469adf23 2343 case SIZE_BYTE:
48401fcf 2344 as_bad (_("unsupported byte value; use a different suffix"));
469adf23 2345 /* Fall through. */
a1c7c0f3
ILT		 2346 case SIZE_WORD: /* Word */
2347 if (isvar (&opP->disp))
2348 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 2349
2350 tmpreg = 0x38;/* 7.0 mode */
2351 addword (nextword);
2352 break;
2353 }
2354 break;
a1c7c0f3
ILT		 2355 case CONTROL:
2356 case FPREG:
355afbcd 2357 default:
48401fcf 2358 as_bad (_("unknown/incorrect operand"));
355afbcd
KR		 2359 /* abort(); */
2360 }
2361 install_gen_operand (s[1], tmpreg);
6d27d3a2 2362 break;
6d27d3a2 2363
355afbcd
KR		 2364 case '#':
2365 case '^':
2366 switch (s[1])
2367 { /* JF: I hate floating point! */
2368 case 'j':
2369 tmpreg = 70;
2370 break;
2371 case '8':
2372 tmpreg = 20;
2373 break;
2374 case 'C':
2375 tmpreg = 50;
2376 break;
2377 case '3':
2378 default:
2379 tmpreg = 80;
2380 break;
2381 }
a1c7c0f3
ILT		 2382 tmpreg = get_num (&opP->disp, tmpreg);
2383 if (isvar (&opP->disp))
2384 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 2385 switch (s[1])
2386 {
2387 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 2388 certain types of overflow.
2389 user beware! */
355afbcd 2390 if (!isbyte (tmpreg))
48401fcf 2391 opP->error = _("out of range");
bcb8dff8 2392 insop (tmpreg, opcode);
a1c7c0f3 2393 if (isvar (&opP->disp))
d9396c16
ILT		 2394 the_ins.reloc[the_ins.nrel - 1].n =
2395 (opcode->m_codenum) * 2 + 1;
355afbcd 2396 break;
a78bc551
ILT		 2397 case 'B':
2398 if (!issbyte (tmpreg))
48401fcf
TT		 2399 opP->error = _("out of range");
2400 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
a78bc551
ILT		 2401 if (isvar (&opP->disp))
2402 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2403 break;
355afbcd
KR		 2404 case 'w':
2405 if (!isword (tmpreg))
48401fcf 2406 opP->error = _("out of range");
bcb8dff8 2407 insop (tmpreg, opcode);
a1c7c0f3 2408 if (isvar (&opP->disp))
355afbcd
KR		 2409 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2410 break;
9e64486e
ILT		 2411 case 'W':
2412 if (!issword (tmpreg))
48401fcf 2413 opP->error = _("out of range");
9e64486e
ILT		 2414 insop (tmpreg, opcode);
2415 if (isvar (&opP->disp))
2416 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2417 break;
355afbcd 2418 case 'l':
bcb8dff8
KR		 2419 /* Because of the way insop works, we put these two out
2420 backwards. */
2421 insop (tmpreg, opcode);
2422 insop (tmpreg >> 16, opcode);
a1c7c0f3 2423 if (isvar (&opP->disp))
355afbcd
KR		 2424 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2425 break;
2426 case '3':
2427 tmpreg &= 0xFF;
2428 case '8':
2429 case 'C':
af438bdb 2430 case 'j':
355afbcd
KR		 2431 install_operand (s[1], tmpreg);
2432 break;
2433 default:
a1c7c0f3 2434 abort ();
355afbcd
KR		 2435 }
2436 break;
6d27d3a2 2437
355afbcd
KR		 2438 case '+':
2439 case '-':
2440 case 'A':
2441 case 'a':
2442 install_operand (s[1], opP->reg - ADDR);
2443 break;
6d27d3a2 2444
355afbcd 2445 case 'B':
a1c7c0f3 2446 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2447 switch (s[1])
2448 {
2449 case 'B':
b4ec75e0
ILT		 2450 /* The pc_fix argument winds up in fx_pcrel_adjust,
2451 which is a char, and may therefore be unsigned. We
2452 want to pass -1, but we pass 64 instead, and convert
2453 back in md_pcrel_from. */
2454 add_fix ('B', &opP->disp, 1, 64);
355afbcd
KR		 2455 break;
2456 case 'W':
a1c7c0f3 2457 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2458 addword (0);
2459 break;
2460 case 'L':
2461 long_branch:
ffecfc8b 2462 if (!HAVE_LONG_BRANCH(current_architecture))
48401fcf 2463 as_warn (_("Can't use long branches on 68000/68010/5200"));
355afbcd 2464 the_ins.opcode[the_ins.numo - 1] |= 0xff;
a1c7c0f3 2465 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2466 addword (0);
2467 addword (0);
2468 break;
2469 case 'g':
a1c7c0f3 2470 if (subs (&opP->disp)) /* We can't relax it */
355afbcd 2471 goto long_branch;
6d27d3a2 2472
a043f579
ILT		 2473#ifdef OBJ_ELF
2474 /* If the displacement needs pic relocation it cannot be
2475 relaxed. */
2476 if (opP->disp.pic_reloc != pic_none)
2477 goto long_branch;
2478#endif
2479
a1c7c0f3
ILT		 2480 /* This could either be a symbol, or an absolute
2481 address. No matter, the frag hacking will finger it
2482 out. Not quite: it can't switch from BRANCH to
2483 BCC68000 for the case where opnd is absolute (it
2484 needs to use the 68000 hack since no conditional abs
2485 jumps). */
ffecfc8b 2486 if (( !HAVE_LONG_BRANCH(current_architecture)
a1c7c0f3 2487 || (0 == adds (&opP->disp)))
355afbcd
KR		 2488 && (the_ins.opcode[0] >= 0x6200)
2489 && (the_ins.opcode[0] <= 0x6f00))
a1c7c0f3
ILT		 2490 add_frag (adds (&opP->disp), offs (&opP->disp),
2491 TAB (BCC68000, SZ_UNDEF));
355afbcd 2492 else
a1c7c0f3
ILT		 2493 add_frag (adds (&opP->disp), offs (&opP->disp),
2494 TAB (ABRANCH, SZ_UNDEF));
355afbcd
KR		 2495 break;
2496 case 'w':
a1c7c0f3 2497 if (isvar (&opP->disp))
355afbcd 2498 {
49864cfa 2499#if 1
355afbcd
KR		 2500 /* check for DBcc instruction */
2501 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2502 {
2503 /* size varies if patch */
2504 /* needed for long form */
a1c7c0f3 2505 add_frag (adds (&opP->disp), offs (&opP->disp),
b79de3a1 2506 TAB (DBCC, SZ_UNDEF));
355afbcd
KR		 2507 break;
2508 }
49864cfa 2509#endif
a1c7c0f3 2510 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2511 }
2512 addword (0);
2513 break;
2514 case 'C': /* Fixed size LONG coproc branches */
a1c7c0f3 2515 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2516 addword (0);
2517 addword (0);
2518 break;
2519 case 'c': /* Var size Coprocesssor branches */
a1c7c0f3 2520 if (subs (&opP->disp))
355afbcd 2521 {
a1c7c0f3 2522 add_fix ('l', &opP->disp, 1, 0);
f59fb6ca 2523 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
355afbcd 2524 }
a1c7c0f3
ILT		 2525 else if (adds (&opP->disp))
2526 add_frag (adds (&opP->disp), offs (&opP->disp),
2527 TAB (FBRANCH, SZ_UNDEF));
355afbcd
KR		 2528 else
2529 {
f59fb6ca
ILT		 2530 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2531 TAB(FBRANCH,SHORT)); */
355afbcd 2532 the_ins.opcode[the_ins.numo - 1] |= 0x40;
a1c7c0f3 2533 add_fix ('l', &opP->disp, 1, 0);
5f8cb05e 2534 addword (0);
355afbcd 2535 addword (0);
355afbcd
KR		 2536 }
2537 break;
2538 default:
a1c7c0f3 2539 abort ();
355afbcd
KR		 2540 }
2541 break;
6d27d3a2 2542
355afbcd
KR		 2543 case 'C': /* Ignore it */
2544 break;
6d27d3a2 2545
355afbcd 2546 case 'd': /* JF this is a kludge */
a1c7c0f3
ILT		 2547 install_operand ('s', opP->reg - ADDR);
2548 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2549 if (!issword (tmpreg))
2550 {
48401fcf 2551 as_warn (_("Expression out of range, using 0"));
355afbcd
KR		 2552 tmpreg = 0;
2553 }
2554 addword (tmpreg);
2555 break;
6d27d3a2 2556
355afbcd
KR		 2557 case 'D':
2558 install_operand (s[1], opP->reg - DATA);
2559 break;
6d27d3a2 2560
355afbcd 2561 case 'F':
a1c7c0f3 2562 install_operand (s[1], opP->reg - FP0);
355afbcd 2563 break;
6d27d3a2 2564
355afbcd 2565 case 'I':
27a53b88 2566 tmpreg = opP->reg - COP0;
355afbcd
KR		 2567 install_operand (s[1], tmpreg);
2568 break;
6d27d3a2 2569
355afbcd
KR		 2570 case 'J': /* JF foo */
2571 switch (opP->reg)
2572 {
2573 case SFC:
2574 tmpreg = 0x000;
2575 break;
2576 case DFC:
2577 tmpreg = 0x001;
2578 break;
2579 case CACR:
2580 tmpreg = 0x002;
2581 break;
2582 case TC:
2583 tmpreg = 0x003;
2584 break;
2585 case ITT0:
2586 tmpreg = 0x004;
2587 break;
2588 case ITT1:
2589 tmpreg = 0x005;
2590 break;
2591 case DTT0:
2592 tmpreg = 0x006;
2593 break;
2594 case DTT1:
2595 tmpreg = 0x007;
2596 break;
9ad5755f
KR		 2597 case BUSCR:
2598 tmpreg = 0x008;
2599 break;
6d27d3a2 2600
355afbcd
KR		 2601 case USP:
2602 tmpreg = 0x800;
2603 break;
2604 case VBR:
2605 tmpreg = 0x801;
2606 break;
2607 case CAAR:
2608 tmpreg = 0x802;
2609 break;
2610 case MSP:
2611 tmpreg = 0x803;
2612 break;
2613 case ISP:
2614 tmpreg = 0x804;
2615 break;
2616 case MMUSR:
2617 tmpreg = 0x805;
2618 break;
2619 case URP:
2620 tmpreg = 0x806;
2621 break;
2622 case SRP:
2623 tmpreg = 0x807;
2624 break;
9ad5755f
KR		 2625 case PCR:
2626 tmpreg = 0x808;
2627 break;
8d20a0a8
C		 2628 case ROMBAR:
2629 tmpreg = 0xC00;
2630 break;
2631 case RAMBAR0:
2632 tmpreg = 0xC04;
2633 break;
2634 case RAMBAR1:
2635 tmpreg = 0xC05;
2636 break;
2637 case MBAR:
2638 tmpreg = 0xC0F;
2639 break;
355afbcd 2640 default:
a1c7c0f3 2641 abort ();
355afbcd
KR		 2642 }
2643 install_operand (s[1], tmpreg);
2644 break;
6d27d3a2 2645
355afbcd 2646 case 'k':
a1c7c0f3 2647 tmpreg = get_num (&opP->disp, 55);
355afbcd
KR		 2648 install_operand (s[1], tmpreg & 0x7f);
2649 break;
6d27d3a2 2650
355afbcd 2651 case 'l':
a1c7c0f3 2652 tmpreg = opP->mask;
355afbcd
KR		 2653 if (s[1] == 'w')
2654 {
2655 if (tmpreg & 0x7FF0000)
48401fcf 2656 as_bad (_("Floating point register in register list"));
bcb8dff8 2657 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 2658 }
2659 else
2660 {
2661 if (tmpreg & 0x700FFFF)
48401fcf 2662 as_bad (_("Wrong register in floating-point reglist"));
355afbcd
KR		 2663 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2664 }
2665 break;
6d27d3a2 2666
355afbcd 2667 case 'L':
a1c7c0f3 2668 tmpreg = opP->mask;
355afbcd
KR		 2669 if (s[1] == 'w')
2670 {
2671 if (tmpreg & 0x7FF0000)
48401fcf 2672 as_bad (_("Floating point register in register list"));
bcb8dff8 2673 insop (tmpreg, opcode);
355afbcd
KR		 2674 }
2675 else if (s[1] == '8')
2676 {
2677 if (tmpreg & 0x0FFFFFF)
48401fcf 2678 as_bad (_("incorrect register in reglist"));
355afbcd
KR		 2679 install_operand (s[1], tmpreg >> 24);
2680 }
2681 else
2682 {
2683 if (tmpreg & 0x700FFFF)
48401fcf 2684 as_bad (_("wrong register in floating-point reglist"));
355afbcd
KR		 2685 else
2686 install_operand (s[1], tmpreg >> 16);
2687 }
2688 break;
6d27d3a2 2689
355afbcd 2690 case 'M':
a1c7c0f3 2691 install_operand (s[1], get_num (&opP->disp, 60));
355afbcd 2692 break;
6d27d3a2 2693
355afbcd 2694 case 'O':
a1c7c0f3
ILT		 2695 tmpreg = ((opP->mode == DREG)
2696 ? 0x20 + opP->reg - DATA
2697 : (get_num (&opP->disp, 40) & 0x1F));
355afbcd
KR		 2698 install_operand (s[1], tmpreg);
2699 break;
6d27d3a2 2700
355afbcd 2701 case 'Q':
a1c7c0f3 2702 tmpreg = get_num (&opP->disp, 10);
355afbcd
KR		 2703 if (tmpreg == 8)
2704 tmpreg = 0;
2705 install_operand (s[1], tmpreg);
2706 break;
2707
2708 case 'R':
a1c7c0f3
ILT		 2709 /* This depends on the fact that ADDR registers are eight
2710 more than their corresponding DATA regs, so the result
2711 will have the ADDR_REG bit set */
355afbcd
KR		 2712 install_operand (s[1], opP->reg - DATA);
2713 break;
6d27d3a2 2714
a1c7c0f3
ILT		 2715 case 'r':
2716 if (opP->mode == AINDR)
2717 install_operand (s[1], opP->reg - DATA);
2718 else
2719 install_operand (s[1], opP->index.reg - DATA);
2720 break;
2721
355afbcd
KR		 2722 case 's':
2723 if (opP->reg == FPI)
2724 tmpreg = 0x1;
2725 else if (opP->reg == FPS)
2726 tmpreg = 0x2;
2727 else if (opP->reg == FPC)
2728 tmpreg = 0x4;
2729 else
a1c7c0f3 2730 abort ();
355afbcd
KR		 2731 install_operand (s[1], tmpreg);
2732 break;
6d27d3a2 2733
355afbcd
KR		 2734 case 'S': /* Ignore it */
2735 break;
6d27d3a2 2736
355afbcd 2737 case 'T':
a1c7c0f3 2738 install_operand (s[1], get_num (&opP->disp, 30));
355afbcd 2739 break;
6d27d3a2 2740
355afbcd
KR		 2741 case 'U': /* Ignore it */
2742 break;
6d27d3a2 2743
355afbcd
KR		 2744 case 'c':
2745 switch (opP->reg)
2746 {
2747 case NC:
2748 tmpreg = 0;
2749 break;
2750 case DC:
2751 tmpreg = 1;
2752 break;
2753 case IC:
2754 tmpreg = 2;
2755 break;
2756 case BC:
2757 tmpreg = 3;
2758 break;
2759 default:
48401fcf 2760 as_fatal (_("failed sanity check"));
355afbcd
KR		 2761 } /* switch on cache token */
2762 install_operand (s[1], tmpreg);
2763 break;
a39116f1 2764#ifndef NO_68851
355afbcd
KR		 2765 /* JF: These are out of order, I fear. */
2766 case 'f':
2767 switch (opP->reg)
2768 {
2769 case SFC:
2770 tmpreg = 0;
2771 break;
2772 case DFC:
2773 tmpreg = 1;
2774 break;
2775 default:
a1c7c0f3 2776 abort ();
355afbcd
KR		 2777 }
2778 install_operand (s[1], tmpreg);
2779 break;
6d27d3a2 2780
9adcd781
ILT		 2781 case '0':
2782 case '1':
2783 case '2':
355afbcd
KR		 2784 switch (opP->reg)
2785 {
2786 case TC:
2787 tmpreg = 0;
2788 break;
2789 case CAL:
2790 tmpreg = 4;
2791 break;
2792 case VAL:
2793 tmpreg = 5;
2794 break;
2795 case SCC:
2796 tmpreg = 6;
2797 break;
2798 case AC:
2799 tmpreg = 7;
2800 break;
2801 default:
a1c7c0f3 2802 abort ();
355afbcd
KR		 2803 }
2804 install_operand (s[1], tmpreg);
2805 break;
6d27d3a2 2806
355afbcd
KR		 2807 case 'V':
2808 if (opP->reg == VAL)
2809 break;
a1c7c0f3 2810 abort ();
6d27d3a2 2811
355afbcd
KR		 2812 case 'W':
2813 switch (opP->reg)
2814 {
355afbcd
KR		 2815 case DRP:
2816 tmpreg = 1;
2817 break;
2818 case SRP:
2819 tmpreg = 2;
2820 break;
2821 case CRP:
2822 tmpreg = 3;
2823 break;
2824 default:
a1c7c0f3 2825 abort ();
355afbcd
KR		 2826 }
2827 install_operand (s[1], tmpreg);
2828 break;
6d27d3a2 2829
355afbcd
KR		 2830 case 'X':
2831 switch (opP->reg)
2832 {
2833 case BAD:
2834 case BAD + 1:
2835 case BAD + 2:
2836 case BAD + 3:
2837 case BAD + 4:
2838 case BAD + 5:
2839 case BAD + 6:
2840 case BAD + 7:
2841 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2842 break;
6d27d3a2 2843
355afbcd
KR		 2844 case BAC:
2845 case BAC + 1:
2846 case BAC + 2:
2847 case BAC + 3:
2848 case BAC + 4:
2849 case BAC + 5:
2850 case BAC + 6:
2851 case BAC + 7:
2852 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2853 break;
6d27d3a2 2854
355afbcd 2855 default:
a1c7c0f3 2856 abort ();
355afbcd
KR		 2857 }
2858 install_operand (s[1], tmpreg);
2859 break;
2860 case 'Y':
2861 know (opP->reg == PSR);
2862 break;
2863 case 'Z':
2864 know (opP->reg == PCSR);
2865 break;
f8701a3f 2866#endif /* m68851 */
355afbcd
KR		 2867 case '3':
2868 switch (opP->reg)
2869 {
2870 case TT0:
2871 tmpreg = 2;
2872 break;
2873 case TT1:
2874 tmpreg = 3;
2875 break;
2876 default:
a1c7c0f3 2877 abort ();
355afbcd
KR		 2878 }
2879 install_operand (s[1], tmpreg);
2880 break;
2881 case 't':
a1c7c0f3 2882 tmpreg = get_num (&opP->disp, 20);
355afbcd 2883 install_operand (s[1], tmpreg);
4134a793 2884 break;
a1c7c0f3 2885 case '_': /* used only for move16 absolute 32-bit address */
48401fcf
TT		 2886 if (isvar (&opP->disp))
2887 add_fix ('l', &opP->disp, 0, 0);
a1c7c0f3 2888 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2889 addword (tmpreg >> 16);
2890 addword (tmpreg & 0xFFFF);
4134a793
KR		 2891 break;
2892 default:
a1c7c0f3 2893 abort ();
4134a793 2894 }
6d27d3a2 2895 }
3ad9ec6a 2896
6d27d3a2
KR		 2897 /* By the time whe get here (FINALLY) the_ins contains the complete
2898 instruction, ready to be emitted. . . */
a1c7c0f3 2899}
fecd2382 2900
355afbcd
KR		 2901static int
2902reverse_16_bits (in)
2903 int in;
fecd2382 2904{
355afbcd
KR		 2905 int out = 0;
2906 int n;
6d27d3a2 2907
355afbcd
KR		 2908 static int mask[16] =
2909 {
2910 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2911 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2912 };
2913 for (n = 0; n < 16; n++)
2914 {
2915 if (in & mask[n])
2916 out |= mask[15 - n];
2917 }
2918 return out;
2919} /* reverse_16_bits() */
fecd2382 2920
355afbcd
KR		 2921static int
2922reverse_8_bits (in)
2923 int in;
fecd2382 2924{
355afbcd
KR		 2925 int out = 0;
2926 int n;
6d27d3a2 2927
355afbcd
KR		 2928 static int mask[8] =
2929 {
2930 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2931 };
6d27d3a2 2932
355afbcd
KR		 2933 for (n = 0; n < 8; n++)
2934 {
2935 if (in & mask[n])
2936 out |= mask[7 - n];
2937 }
2938 return out;
2939} /* reverse_8_bits() */
fecd2382 2940
04ef74bb
KR		 2941/* Cause an extra frag to be generated here, inserting up to 10 bytes
2942 (that value is chosen in the frag_var call in md_assemble). TYPE
2943 is the subtype of the frag to be generated; its primary type is
2944 rs_machine_dependent.
2945
2946 The TYPE parameter is also used by md_convert_frag_1 and
2947 md_estimate_size_before_relax. The appropriate type of fixup will
2948 be emitted by md_convert_frag_1.
2949
2950 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355afbcd
KR		 2951static void
2952install_operand (mode, val)
2953 int mode;
2954 int val;
fecd2382 2955{
355afbcd
KR		 2956 switch (mode)
2957 {
2958 case 's':
2959 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2960 break;
2961 case 'd':
2962 the_ins.opcode[0] |= val << 9;
2963 break;
2964 case '1':
2965 the_ins.opcode[1] |= val << 12;
2966 break;
2967 case '2':
2968 the_ins.opcode[1] |= val << 6;
2969 break;
2970 case '3':
2971 the_ins.opcode[1] |= val;
2972 break;
2973 case '4':
2974 the_ins.opcode[2] |= val << 12;
2975 break;
2976 case '5':
2977 the_ins.opcode[2] |= val << 6;
2978 break;
2979 case '6':
bcb8dff8
KR		 2980 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2981 three words long! */
355afbcd
KR		 2982 the_ins.numo++;
2983 the_ins.opcode[2] |= val;
2984 break;
2985 case '7':
2986 the_ins.opcode[1] |= val << 7;
2987 break;
2988 case '8':
2989 the_ins.opcode[1] |= val << 10;
2990 break;
f8701a3f 2991#ifndef NO_68851
355afbcd
KR		 2992 case '9':
2993 the_ins.opcode[1] |= val << 5;
2994 break;
f8701a3f 2995#endif
6d27d3a2 2996
355afbcd
KR		 2997 case 't':
2998 the_ins.opcode[1] |= (val << 10) | (val << 7);
2999 break;
3000 case 'D':
3001 the_ins.opcode[1] |= (val << 12) | val;
3002 break;
3003 case 'g':
3004 the_ins.opcode[0] |= val = 0xff;
3005 break;
3006 case 'i':
3007 the_ins.opcode[0] |= val << 9;
3008 break;
3009 case 'C':
3010 the_ins.opcode[1] |= val;
3011 break;
3012 case 'j':
3013 the_ins.opcode[1] |= val;
3014 the_ins.numo++; /* What a hack */
3015 break;
3016 case 'k':
3017 the_ins.opcode[1] |= val << 4;
3018 break;
3019 case 'b':
3020 case 'w':
9e64486e 3021 case 'W':
355afbcd
KR		 3022 case 'l':
3023 break;
3024 case 'e':
3025 the_ins.opcode[0] |= (val << 6);
3026 break;
3027 case 'L':
3028 the_ins.opcode[1] = (val >> 16);
3029 the_ins.opcode[2] = val & 0xffff;
3030 break;
3031 case 'c':
3032 default:
48401fcf 3033 as_fatal (_("failed sanity check."));
355afbcd
KR		 3034 }
3035} /* install_operand() */
fecd2382 3036
355afbcd
KR		 3037static void
3038install_gen_operand (mode, val)
3039 int mode;
3040 int val;
fecd2382 3041{
355afbcd
KR		 3042 switch (mode)
3043 {
3044 case 's':
3045 the_ins.opcode[0] |= val;
3046 break;
3047 case 'd':
3048 /* This is a kludge!!! */
3049 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3050 break;
3051 case 'b':
3052 case 'w':
3053 case 'l':
3054 case 'f':
3055 case 'F':
3056 case 'x':
3057 case 'p':
3058 the_ins.opcode[0] |= val;
3059 break;
3060 /* more stuff goes here */
3061 default:
48401fcf 3062 as_fatal (_("failed sanity check."));
355afbcd
KR		 3063 }
3064} /* install_gen_operand() */
fecd2382 3065
7c15cbe8
RP		 3066/*
3067 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3068 * then deal with the bitfield hack.
3069 */
3070
355afbcd
KR		 3071static char *
3072crack_operand (str, opP)
3073 register char *str;
3074 register struct m68k_op *opP;
fecd2382 3075{
355afbcd
KR		 3076 register int parens;
3077 register int c;
3078 register char *beg_str;
4026c122 3079 int inquote = 0;
6d27d3a2 3080
355afbcd
KR		 3081 if (!str)
3082 {
3083 return str;
3084 }
3085 beg_str = str;
4026c122 3086 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
355afbcd 3087 {
4026c122 3088 if (! inquote)
355afbcd 3089 {
4026c122
ILT		 3090 if (*str == '(')
3091 parens++;
3092 else if (*str == ')')
3093 {
3094 if (!parens)
3095 { /* ERROR */
48401fcf 3096 opP->error = _("Extra )");
4026c122
ILT		 3097 return str;
3098 }
3099 --parens;
355afbcd 3100 }
f8701a3f 3101 }
4026c122
ILT		 3102 if (flag_mri && *str == '\'')
3103 inquote = ! inquote;
355afbcd
KR		 3104 }
3105 if (!*str && parens)
3106 { /* ERROR */
48401fcf 3107 opP->error = _("Missing )");
355afbcd
KR		 3108 return str;
3109 }
3110 c = *str;
3111 *str = '\0';
a1c7c0f3 3112 if (m68k_ip_op (beg_str, opP) != 0)
355afbcd
KR		 3113 {
3114 *str = c;
3115 return str;
3116 }
3117 *str = c;
3118 if (c == '}')
3119 c = *++str; /* JF bitfield hack */
3120 if (c)
3121 {
3122 c = *++str;
3123 if (!c)
48401fcf
TT		 3124 as_bad (_("Missing operand"));
3125 }
3126
3127 /* Detect MRI REG symbols and convert them to REGLSTs. */
3128 if (opP->mode == CONTROL && (int)opP->reg < 0)
3129 {
3130 opP->mode = REGLST;
3131 opP->mask = ~(int)opP->reg;
3132 opP->reg = 0;
355afbcd 3133 }
48401fcf 3134
355afbcd 3135 return str;
fecd2382
RP		 3136}
3137
fecd2382 3138/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 3139 machine dependent instruction. This function is supposed to emit
fecd2382 3140 the frags/bytes it assembles to.
a39116f1 3141 */
a933d598 3142
0917e2cb 3143static void
355afbcd 3144insert_reg (regname, regnum)
f59fb6ca 3145 const char *regname;
355afbcd 3146 int regnum;
a933d598
SC		 3147{
3148 char buf[100];
3149 int i;
355afbcd
KR		 3150
3151#ifdef REGISTER_PREFIX
82489ea0
KR		 3152 if (!flag_reg_prefix_optional)
3153 {
3154 buf[0] = REGISTER_PREFIX;
3155 strcpy (buf + 1, regname);
3156 regname = buf;
3157 }
355afbcd
KR		 3158#endif
3159
82489ea0
KR		 3160 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3161 &zero_address_frag));
a933d598
SC		 3162
3163 for (i = 0; regname[i]; i++)
355afbcd 3164 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 3165 buf[i] = '\0';
6d27d3a2 3166
82489ea0
KR		 3167 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3168 &zero_address_frag));
a933d598
SC		 3169}
3170
49864cfa 3171struct init_entry
355afbcd 3172 {
bcb8dff8 3173 const char *name;
355afbcd 3174 int number;
49864cfa 3175 };
355afbcd 3176
bcb8dff8 3177static const struct init_entry init_table[] =
355afbcd 3178{
bcb8dff8
KR		 3179 { "d0", DATA0 },
3180 { "d1", DATA1 },
3181 { "d2", DATA2 },
3182 { "d3", DATA3 },
3183 { "d4", DATA4 },
3184 { "d5", DATA5 },
3185 { "d6", DATA6 },
3186 { "d7", DATA7 },
3187 { "a0", ADDR0 },
3188 { "a1", ADDR1 },
3189 { "a2", ADDR2 },
3190 { "a3", ADDR3 },
3191 { "a4", ADDR4 },
3192 { "a5", ADDR5 },
3193 { "a6", ADDR6 },
3194 { "fp", ADDR6 },
3195 { "a7", ADDR7 },
3196 { "sp", ADDR7 },
a1c7c0f3 3197 { "ssp", ADDR7 },
bcb8dff8
KR		 3198 { "fp0", FP0 },
3199 { "fp1", FP1 },
3200 { "fp2", FP2 },
3201 { "fp3", FP3 },
3202 { "fp4", FP4 },
3203 { "fp5", FP5 },
3204 { "fp6", FP6 },
3205 { "fp7", FP7 },
3206 { "fpi", FPI },
3207 { "fpiar", FPI },
3208 { "fpc", FPI },
3209 { "fps", FPS },
3210 { "fpsr", FPS },
3211 { "fpc", FPC },
3212 { "fpcr", FPC },
064ba683
ILT		 3213 { "control", FPC },
3214 { "status", FPS },
3215 { "iaddr", FPI },
bcb8dff8
KR		 3216
3217 { "cop0", COP0 },
3218 { "cop1", COP1 },
3219 { "cop2", COP2 },
3220 { "cop3", COP3 },
3221 { "cop4", COP4 },
3222 { "cop5", COP5 },
3223 { "cop6", COP6 },
3224 { "cop7", COP7 },
3225 { "pc", PC },
3226 { "zpc", ZPC },
3227 { "sr", SR },
3228
3229 { "ccr", CCR },
3230 { "cc", CCR },
3231
8d20a0a8
C		 3232 /* control registers */
3233 { "sfc", SFC }, /* Source Function Code */
064ba683 3234 { "sfcr", SFC },
8d20a0a8 3235 { "dfc", DFC }, /* Destination Function Code */
064ba683 3236 { "dfcr", DFC },
8d20a0a8
C		 3237 { "cacr", CACR }, /* Cache Control Register */
3238 { "caar", CAAR }, /* Cache Address Register */
3239
3240 { "usp", USP }, /* User Stack Pointer */
3241 { "vbr", VBR }, /* Vector Base Register */
3242 { "msp", MSP }, /* Master Stack Pointer */
3243 { "isp", ISP }, /* Interrupt Stack Pointer */
3244
3245 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3246 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3247 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3248 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3249
3250 /* 68ec040 versions of same */
3251 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3252 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3253 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3254 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3255
0b810a6e
ILT		 3256 /* mcf5200 versions of same. The ColdFire programmer's reference
3257 manual indicated that the order is 2,3,0,1, but Ken Rose
3258 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3259 { "acr0", ITT0 }, /* Access Control Unit 0 */
3260 { "acr1", ITT1 }, /* Access Control Unit 1 */
3261 { "acr2", DTT0 }, /* Access Control Unit 2 */
3262 { "acr3", DTT1 }, /* Access Control Unit 3 */
8d20a0a8
C		 3263
3264 { "tc", TC }, /* MMU Translation Control Register */
3265 { "tcr", TC },
3266
3267 { "mmusr", MMUSR }, /* MMU Status Register */
3268 { "srp", SRP }, /* User Root Pointer */
3269 { "urp", URP }, /* Supervisor Root Pointer */
3270
9ad5755f
KR		 3271 { "buscr", BUSCR },
3272 { "pcr", PCR },
bcb8dff8 3273
8d20a0a8
C		 3274 { "rombar", ROMBAR }, /* ROM Base Address Register */
3275 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3276 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3277 { "mbar", MBAR }, /* Module Base Address Register */
3278 /* end of control registers */
3279
bcb8dff8
KR		 3280 { "ac", AC },
3281 { "bc", BC },
3282 { "cal", CAL },
3283 { "crp", CRP },
3284 { "drp", DRP },
3285 { "pcsr", PCSR },
3286 { "psr", PSR },
3287 { "scc", SCC },
3288 { "val", VAL },
3289 { "bad0", BAD0 },
3290 { "bad1", BAD1 },
3291 { "bad2", BAD2 },
3292 { "bad3", BAD3 },
3293 { "bad4", BAD4 },
3294 { "bad5", BAD5 },
3295 { "bad6", BAD6 },
3296 { "bad7", BAD7 },
3297 { "bac0", BAC0 },
3298 { "bac1", BAC1 },
3299 { "bac2", BAC2 },
3300 { "bac3", BAC3 },
3301 { "bac4", BAC4 },
3302 { "bac5", BAC5 },
3303 { "bac6", BAC6 },
3304 { "bac7", BAC7 },
3305
3306 { "ic", IC },
3307 { "dc", DC },
3308 { "nc", NC },
3309
3310 { "tt0", TT0 },
3311 { "tt1", TT1 },
4134a793 3312 /* 68ec030 versions of same */
bcb8dff8
KR		 3313 { "ac0", TT0 },
3314 { "ac1", TT1 },
4134a793 3315 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 3316 { "acusr", PSR },
a933d598 3317
a1c7c0f3
ILT		 3318 /* Suppressed data and address registers. */
3319 { "zd0", ZDATA0 },
3320 { "zd1", ZDATA1 },
3321 { "zd2", ZDATA2 },
3322 { "zd3", ZDATA3 },
3323 { "zd4", ZDATA4 },
3324 { "zd5", ZDATA5 },
3325 { "zd6", ZDATA6 },
3326 { "zd7", ZDATA7 },
3327 { "za0", ZADDR0 },
3328 { "za1", ZADDR1 },
3329 { "za2", ZADDR2 },
3330 { "za3", ZADDR3 },
3331 { "za4", ZADDR4 },
3332 { "za5", ZADDR5 },
3333 { "za6", ZADDR6 },
3334 { "za7", ZADDR7 },
3335
bcb8dff8 3336 { 0, 0 }
a933d598
SC		 3337};
3338
0917e2cb 3339static void
355afbcd 3340init_regtable ()
a933d598
SC		 3341{
3342 int i;
6d27d3a2 3343 for (i = 0; init_table[i].name; i++)
355afbcd 3344 insert_reg (init_table[i].name, init_table[i].number);
a933d598 3345}
6d27d3a2 3346
df3768fb 3347static int no_68851, no_68881;
a933d598 3348
dff60b7d
ILT		 3349#ifdef OBJ_AOUT
3350/* a.out machine type. Default to 68020. */
3351int m68k_aout_machtype = 2;
3352#endif
3353
fecd2382 3354void
355afbcd 3355md_assemble (str)
6d27d3a2 3356 char *str;
fecd2382 3357{
a1c7c0f3 3358 const char *er;
355afbcd
KR		 3359 short *fromP;
3360 char *toP = NULL;
3361 int m, n = 0;
3362 char *to_beg_P;
3363 int shorts_this_frag;
5f8cb05e 3364 fixS *fixP;
6d27d3a2 3365
4026c122
ILT		 3366 /* In MRI mode, the instruction and operands are separated by a
3367 space. Anything following the operands is a comment. The label
3368 has already been removed. */
3369 if (flag_mri)
3370 {
3371 char *s;
3372 int fields = 0;
3373 int infield = 0;
3374 int inquote = 0;
3375
3376 for (s = str; *s != '\0'; s++)
3377 {
3378 if ((*s == ' ' || *s == '\t') && ! inquote)
3379 {
3380 if (infield)
3381 {
3382 ++fields;
3383 if (fields >= 2)
3384 {
3385 *s = '\0';
3386 break;
3387 }
3388 infield = 0;
3389 }
3390 }
3391 else
3392 {
3393 if (! infield)
3394 infield = 1;
3395 if (*s == '\'')
3396 inquote = ! inquote;
3397 }
3398 }
3399 }
3400
e284846a 3401 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 3402 m68k_ip (str);
3403 er = the_ins.error;
3404 if (!er)
3405 {
a1c7c0f3 3406 for (n = 0; n < the_ins.numargs; n++)
355afbcd
KR		 3407 if (the_ins.operands[n].error)
3408 {
3409 er = the_ins.operands[n].error;
3410 break;
3411 }
3412 }
3413 if (er)
3414 {
48401fcf 3415 as_bad (_("%s -- statement `%s' ignored"), er, str);
355afbcd
KR		 3416 return;
3417 }
6d27d3a2 3418
d703b5a7
ILT		 3419 /* If there is a current label, record that it marks an instruction. */
3420 if (current_label != NULL)
3421 {
3422 current_label->text = 1;
3423 current_label = NULL;
3424 }
3425
355afbcd 3426 if (the_ins.nfrag == 0)
49864cfa
KR		 3427 {
3428 /* No frag hacking involved; just put it out */
355afbcd
KR		 3429 toP = frag_more (2 * the_ins.numo);
3430 fromP = &the_ins.opcode[0];
3431 for (m = the_ins.numo; m; --m)
3432 {
3433 md_number_to_chars (toP, (long) (*fromP), 2);
3434 toP += 2;
3435 fromP++;
f8701a3f 3436 }
355afbcd
KR		 3437 /* put out symbol-dependent info */
3438 for (m = 0; m < the_ins.nrel; m++)
3439 {
3440 switch (the_ins.reloc[m].wid)
3441 {
3442 case 'B':
3443 n = 1;
3444 break;
3445 case 'b':
3446 n = 1;
3447 break;
3448 case '3':
0b810a6e 3449 n = 1;
355afbcd
KR		 3450 break;
3451 case 'w':
590c50d8 3452 case 'W':
355afbcd
KR		 3453 n = 2;
3454 break;
3455 case 'l':
3456 n = 4;
3457 break;
3458 default:
48401fcf 3459 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
49864cfa 3460 the_ins.reloc[m].wid);
355afbcd 3461 }
6d27d3a2 3462
5f8cb05e
ILT		 3463 fixP = fix_new_exp (frag_now,
3464 ((toP - frag_now->fr_literal)
3465 - the_ins.numo * 2 + the_ins.reloc[m].n),
3466 n,
3467 &the_ins.reloc[m].exp,
3468 the_ins.reloc[m].pcrel,
a043f579
ILT		 3469 get_reloc_code (n, the_ins.reloc[m].pcrel,
3470 the_ins.reloc[m].pic_reloc));
5f8cb05e 3471 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
a78bc551
ILT		 3472 if (the_ins.reloc[m].wid == 'B')
3473 fixP->fx_signed = 1;
f8701a3f 3474 }
355afbcd
KR		 3475 return;
3476 }
3477
3478 /* There's some frag hacking */
3479 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3480 {
3481 int wid;
3482
3483 if (n == 0)
3484 wid = 2 * the_ins.fragb[n].fragoff;
3485 else
3486 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3487 toP = frag_more (wid);
3488 to_beg_P = toP;
3489 shorts_this_frag = 0;
3490 for (m = wid / 2; m; --m)
3491 {
3492 md_number_to_chars (toP, (long) (*fromP), 2);
3493 toP += 2;
3494 fromP++;
3495 shorts_this_frag++;
3496 }
3497 for (m = 0; m < the_ins.nrel; m++)
3498 {
49864cfa 3499 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 3500 {
49864cfa 3501 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 3502 break;
3503 }
3504 wid = the_ins.reloc[m].wid;
3505 if (wid == 0)
3506 continue;
3507 the_ins.reloc[m].wid = 0;
3508 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3509
5f8cb05e
ILT		 3510 fixP = fix_new_exp (frag_now,
3511 ((toP - frag_now->fr_literal)
3512 - the_ins.numo * 2 + the_ins.reloc[m].n),
3513 wid,
3514 &the_ins.reloc[m].exp,
3515 the_ins.reloc[m].pcrel,
a043f579
ILT		 3516 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3517 the_ins.reloc[m].pic_reloc));
5f8cb05e 3518 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
fecd2382 3519 }
49864cfa
KR		 3520 (void) frag_var (rs_machine_dependent, 10, 0,
3521 (relax_substateT) (the_ins.fragb[n].fragty),
3522 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 3523 }
3524 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3525 shorts_this_frag = 0;
3526 if (n)
3527 {
3528 toP = frag_more (n * sizeof (short));
3529 while (n--)
3530 {
3531 md_number_to_chars (toP, (long) (*fromP), 2);
3532 toP += 2;
3533 fromP++;
3534 shorts_this_frag++;
fecd2382 3535 }
355afbcd
KR		 3536 }
3537 for (m = 0; m < the_ins.nrel; m++)
3538 {
3539 int wid;
3540
3541 wid = the_ins.reloc[m].wid;
3542 if (wid == 0)
3543 continue;
3544 the_ins.reloc[m].wid = 0;
3545 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3546
5f8cb05e
ILT		 3547 fixP = fix_new_exp (frag_now,
3548 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3549 - shorts_this_frag * 2),
3550 wid,
3551 &the_ins.reloc[m].exp,
3552 the_ins.reloc[m].pcrel,
a043f579
ILT		 3553 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3554 the_ins.reloc[m].pic_reloc));
5f8cb05e 3555 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
355afbcd 3556 }
fecd2382
RP		 3557}
3558
fecd2382 3559void
355afbcd 3560md_begin ()
fecd2382 3561{
355afbcd 3562 /*
e284846a
KR		 3563 * md_begin -- set up hash tables with 68000 instructions.
3564 * similar to what the vax assembler does. ---phr
3565 */
355afbcd 3566 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 3567 a copy of it at runtime, adding in the information we want but isn't
3568 there. I think it'd be better to have an awk script hack the table
3569 at compile time. Or even just xstr the table and use it as-is. But
3570 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3571 names. */
6d27d3a2 3572
b79de3a1 3573 register const struct m68k_opcode *ins;
355afbcd 3574 register struct m68k_incant *hack, *slak;
bcb8dff8 3575 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 3576 register unsigned int i;
3577 register char c;
3578
064ba683 3579 if (flag_mri)
6700d36e
ILT		 3580 {
3581 flag_reg_prefix_optional = 1;
3582 m68k_abspcadd = 1;
924160b0
ILT		 3583 if (! m68k_rel32_from_cmdline)
3584 m68k_rel32 = 0;
6700d36e 3585 }
064ba683 3586
82489ea0 3587 op_hash = hash_new ();
355afbcd
KR		 3588
3589 obstack_begin (&robyn, 4000);
a1c7c0f3 3590 for (i = 0; i < m68k_numopcodes; i++)
355afbcd
KR		 3591 {
3592 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3593 do
3594 {
a1c7c0f3 3595 ins = &m68k_opcodes[i];
e284846a
KR		 3596 /* We *could* ignore insns that don't match our arch here
3597 but just leaving them out of the hash. */
355afbcd
KR		 3598 slak->m_operands = ins->args;
3599 slak->m_opnum = strlen (slak->m_operands) / 2;
3600 slak->m_arch = ins->arch;
3601 slak->m_opcode = ins->opcode;
3602 /* This is kludgey */
3603 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
a1c7c0f3
ILT		 3604 if (i + 1 != m68k_numopcodes
3605 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
355afbcd
KR		 3606 {
3607 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 3608 i++;
355afbcd
KR		 3609 }
3610 else
3611 slak->m_next = 0;
3612 slak = slak->m_next;
f8701a3f 3613 }
355afbcd
KR		 3614 while (slak);
3615
3616 retval = hash_insert (op_hash, ins->name, (char *) hack);
dff60b7d 3617 if (retval)
48401fcf 3618 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
b79de3a1
KR		 3619 }
3620
a1c7c0f3 3621 for (i = 0; i < m68k_numaliases; i++)
b79de3a1
KR		 3622 {
3623 const char *name = m68k_opcode_aliases[i].primary;
3624 const char *alias = m68k_opcode_aliases[i].alias;
3625 PTR val = hash_find (op_hash, name);
3626 if (!val)
48401fcf 3627 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
b79de3a1
KR		 3628 retval = hash_insert (op_hash, alias, val);
3629 if (retval)
48401fcf 3630 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
355afbcd 3631 }
6d27d3a2 3632
6700d36e
ILT		 3633 /* In MRI mode, all unsized branches are variable sized. Normally,
3634 they are word sized. */
3635 if (flag_mri)
3636 {
3637 static struct m68k_opcode_alias mri_aliases[] =
3638 {
3639 { "bhi", "jhi", },
3640 { "bls", "jls", },
3641 { "bcc", "jcc", },
3642 { "bcs", "jcs", },
3643 { "bne", "jne", },
3644 { "beq", "jeq", },
3645 { "bvc", "jvc", },
3646 { "bvs", "jvs", },
3647 { "bpl", "jpl", },
3648 { "bmi", "jmi", },
3649 { "bge", "jge", },
3650 { "blt", "jlt", },
3651 { "bgt", "jgt", },
3652 { "ble", "jle", },
3653 { "bra", "jra", },
3654 { "bsr", "jbsr", },
3655 };
3656
3657 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3658 {
3659 const char *name = mri_aliases[i].primary;
3660 const char *alias = mri_aliases[i].alias;
3661 PTR val = hash_find (op_hash, name);
3662 if (!val)
48401fcf 3663 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
6700d36e
ILT		 3664 retval = hash_jam (op_hash, alias, val);
3665 if (retval)
48401fcf 3666 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
6700d36e
ILT		 3667 }
3668 }
3669
355afbcd
KR		 3670 for (i = 0; i < sizeof (mklower_table); i++)
3671 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3672
355afbcd
KR		 3673 for (i = 0; i < sizeof (notend_table); i++)
3674 {
3675 notend_table[i] = 0;
3676 alt_notend_table[i] = 0;
3677 }
3678 notend_table[','] = 1;
3679 notend_table['{'] = 1;
3680 notend_table['}'] = 1;
3681 alt_notend_table['a'] = 1;
3682 alt_notend_table['A'] = 1;
3683 alt_notend_table['d'] = 1;
3684 alt_notend_table['D'] = 1;
3685 alt_notend_table['#'] = 1;
5f8cb05e 3686 alt_notend_table['&'] = 1;
355afbcd
KR		 3687 alt_notend_table['f'] = 1;
3688 alt_notend_table['F'] = 1;
fecd2382 3689#ifdef REGISTER_PREFIX
355afbcd 3690 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3691#endif
f8701a3f 3692
a1c7c0f3
ILT		 3693 /* We need to put '(' in alt_notend_table to handle
3694 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3695 */
3696 alt_notend_table['('] = 1;
3697
3698 /* We need to put '@' in alt_notend_table to handle
3699 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3700 */
3701 alt_notend_table['@'] = 1;
3702
8d20a0a8
C		 3703 /* We need to put digits in alt_notend_table to handle
3704 bfextu %d0{24:1},%d0
3705 */
3706 alt_notend_table['0'] = 1;
3707 alt_notend_table['1'] = 1;
3708 alt_notend_table['2'] = 1;
3709 alt_notend_table['3'] = 1;
3710 alt_notend_table['4'] = 1;
3711 alt_notend_table['5'] = 1;
3712 alt_notend_table['6'] = 1;
3713 alt_notend_table['7'] = 1;
3714 alt_notend_table['8'] = 1;
3715 alt_notend_table['9'] = 1;
3716
3ad9ec6a 3717#ifndef MIT_SYNTAX_ONLY
355afbcd 3718 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 3719 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3720 {
3721 int n = 0;
3722 while (mote_pseudo_table[n].poc_name)
3723 {
3724 hack = (struct m68k_incant *)
3725 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3726 hash_insert (op_hash,
3727 mote_pseudo_table[n].poc_name, (char *) hack);
3728 hack->m_operands = 0;
3729 hack->m_opnum = n;
3730 n++;
3731 }
3732 }
3ad9ec6a
ILT		 3733#endif
3734
355afbcd 3735 init_regtable ();
a043f579
ILT		 3736
3737#ifdef OBJ_ELF
3738 record_alignment (text_section, 2);
3739 record_alignment (data_section, 2);
3740 record_alignment (bss_section, 2);
3741#endif
fecd2382
RP		 3742}
3743
b4d51f3d
ILT		 3744static void
3745select_control_regs ()
3746{
3747 /* Note which set of "movec" control registers is available. */
3748 switch (cpu_of_arch (current_architecture))
3749 {
3750 case m68000:
3751 control_regs = m68000_control_regs;
3752 break;
3753 case m68010:
3754 control_regs = m68010_control_regs;
3755 break;
3756 case m68020:
3757 case m68030:
3758 control_regs = m68020_control_regs;
3759 break;
3760 case m68040:
3761 control_regs = m68040_control_regs;
3762 break;
3763 case m68060:
3764 control_regs = m68060_control_regs;
3765 break;
3766 case cpu32:
3767 control_regs = cpu32_control_regs;
3768 break;
3769 case mcf5200:
3770 control_regs = mcf5200_control_regs;
3771 break;
3772 default:
3773 abort ();
3774 }
3775}
3776
82489ea0
KR		 3777void
3778m68k_init_after_args ()
3779{
3780 if (cpu_of_arch (current_architecture) == 0)
3781 {
064ba683 3782 int i;
b79de3a1 3783 const char *default_cpu = TARGET_CPU;
82489ea0 3784
b79de3a1
KR		 3785 if (*default_cpu == 'm')
3786 default_cpu++;
3787 for (i = 0; i < n_archs; i++)
e9bb39b4 3788 if (strcasecmp (default_cpu, archs[i].name) == 0)
b79de3a1
KR		 3789 break;
3790 if (i == n_archs)
3791 {
48401fcf 3792 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
b79de3a1
KR		 3793 current_architecture |= m68020;
3794 }
3795 else
3796 current_architecture |= archs[i].arch;
82489ea0 3797 }
b79de3a1
KR		 3798 /* Permit m68881 specification with all cpus; those that can't work
3799 with a coprocessor could be doing emulation. */
82489ea0
KR		 3800 if (current_architecture & m68851)
3801 {
3802 if (current_architecture & m68040)
3803 {
48401fcf 3804 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
82489ea0
KR		 3805 }
3806 }
3807 /* What other incompatibilities could we check for? */
3808
3809 /* Toss in some default assumptions about coprocessors. */
3810 if (!no_68881
3811 && (cpu_of_arch (current_architecture)
3812 /* Can CPU32 have a 68881 coprocessor?? */
3813 & (m68020 | m68030 | cpu32)))
3814 {
3815 current_architecture |= m68881;
3816 }
3817 if (!no_68851
3818 && (cpu_of_arch (current_architecture) & m68020up) != 0
3819 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3820 {
3821 current_architecture |= m68851;
3822 }
3823 if (no_68881 && (current_architecture & m68881))
48401fcf 3824 as_bad (_("options for 68881 and no-68881 both given"));
82489ea0 3825 if (no_68851 && (current_architecture & m68851))
48401fcf 3826 as_bad (_("options for 68851 and no-68851 both given"));
82489ea0
KR		 3827
3828#ifdef OBJ_AOUT
3829 /* Work out the magic number. This isn't very general. */
3830 if (current_architecture & m68000)
3831 m68k_aout_machtype = 0;
3832 else if (current_architecture & m68010)
3833 m68k_aout_machtype = 1;
3834 else if (current_architecture & m68020)
3835 m68k_aout_machtype = 2;
3836 else
3837 m68k_aout_machtype = 2;
3838#endif
3839
3840 /* Note which set of "movec" control registers is available. */
b4d51f3d 3841 select_control_regs ();
04ef74bb 3842
48401fcf
TT		 3843 if (cpu_of_arch (current_architecture) < m68020
3844 || cpu_of_arch (current_architecture) == mcf5200)
04ef74bb 3845 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
82489ea0 3846}
d703b5a7
ILT		 3847\f
3848/* This is called when a label is defined. */
3849
3850void
3851m68k_frob_label (sym)
3852 symbolS *sym;
3853{
3854 struct label_line *n;
3855
3856 n = (struct label_line *) xmalloc (sizeof *n);
3857 n->next = labels;
3858 n->label = sym;
3859 as_where (&n->file, &n->line);
ffecfc8b 3860 n->text = 0;
d703b5a7
ILT		 3861 labels = n;
3862 current_label = n;
3863}
3864
3865/* This is called when a value that is not an instruction is emitted. */
3866
3867void
3868m68k_flush_pending_output ()
3869{
3870 current_label = NULL;
3871}
3872
3873/* This is called at the end of the assembly, when the final value of
3874 the label is known. We warn if this is a text symbol aligned at an
3875 odd location. */
3876
3877void
3878m68k_frob_symbol (sym)
3879 symbolS *sym;
3880{
48401fcf
TT		 3881 if (S_GET_SEGMENT (sym) == reg_section
3882 && (int) S_GET_VALUE (sym) < 0)
3883 {
3884 S_SET_SEGMENT (sym, absolute_section);
3885 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
3886 }
3887 else if ((S_GET_VALUE (sym) & 1) != 0)
d703b5a7
ILT		 3888 {
3889 struct label_line *l;
82489ea0 3890
d703b5a7
ILT		 3891 for (l = labels; l != NULL; l = l->next)
3892 {
3893 if (l->label == sym)
3894 {
3895 if (l->text)
3896 as_warn_where (l->file, l->line,
48401fcf 3897 _("text label `%s' aligned to odd boundary"),
d703b5a7
ILT		 3898 S_GET_NAME (sym));
3899 break;
3900 }
3901 }
3902 }
3903}
3904\f
20710f1c
ILT		 3905/* This is called if we go in or out of MRI mode because of the .mri
3906 pseudo-op. */
3907
3908void
3909m68k_mri_mode_change (on)
3910 int on;
3911{
3912 if (on)
3913 {
3914 if (! flag_reg_prefix_optional)
3915 {
3916 flag_reg_prefix_optional = 1;
3917#ifdef REGISTER_PREFIX
3918 init_regtable ();
3919#endif
3920 }
3921 m68k_abspcadd = 1;
924160b0
ILT		 3922 if (! m68k_rel32_from_cmdline)
3923 m68k_rel32 = 0;
20710f1c
ILT		 3924 }
3925 else
3926 {
3927 if (! reg_prefix_optional_seen)
3928 {
3929#ifdef REGISTER_PREFIX_OPTIONAL
3930 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3931#else
3932 flag_reg_prefix_optional = 0;
3933#endif
3934#ifdef REGISTER_PREFIX
3935 init_regtable ();
3936#endif
3937 }
3938 m68k_abspcadd = 0;
924160b0
ILT		 3939 if (! m68k_rel32_from_cmdline)
3940 m68k_rel32 = 1;
20710f1c
ILT		 3941 }
3942}
3943
fecd2382
RP		 3944/* Equal to MAX_PRECISION in atof-ieee.c */
3945#define MAX_LITTLENUMS 6
3946
a1c7c0f3
ILT		 3947/* Turn a string in input_line_pointer into a floating point constant
3948 of type type, and store the appropriate bytes in *litP. The number
3949 of LITTLENUMS emitted is stored in *sizeP . An error message is
3950 returned, or NULL on OK. */
3951
fecd2382 3952char *
355afbcd
KR		 3953md_atof (type, litP, sizeP)
3954 char type;
3955 char *litP;
3956 int *sizeP;
fecd2382 3957{
355afbcd
KR		 3958 int prec;
3959 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3960 LITTLENUM_TYPE *wordP;
3961 char *t;
6d27d3a2 3962
355afbcd
KR		 3963 switch (type)
3964 {
3965 case 'f':
3966 case 'F':
3967 case 's':
3968 case 'S':
3969 prec = 2;
3970 break;
6d27d3a2 3971
355afbcd
KR		 3972 case 'd':
3973 case 'D':
3974 case 'r':
3975 case 'R':
3976 prec = 4;
3977 break;
6d27d3a2 3978
355afbcd
KR		 3979 case 'x':
3980 case 'X':
3981 prec = 6;
3982 break;
6d27d3a2 3983
355afbcd
KR		 3984 case 'p':
3985 case 'P':
3986 prec = 6;
3987 break;
6d27d3a2 3988
355afbcd
KR		 3989 default:
3990 *sizeP = 0;
48401fcf 3991 return _("Bad call to MD_ATOF()");
355afbcd
KR		 3992 }
3993 t = atof_ieee (input_line_pointer, type, words);
3994 if (t)
3995 input_line_pointer = t;
3996
3997 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3998 for (wordP = words; prec--;)
3999 {
4000 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4001 litP += sizeof (LITTLENUM_TYPE);
4002 }
49864cfa 4003 return 0;
fecd2382
RP		 4004}
4005
fecd2382 4006void
355afbcd
KR		 4007md_number_to_chars (buf, val, n)
4008 char *buf;
025b0302 4009 valueT val;
355afbcd 4010 int n;
fecd2382 4011{
82489ea0 4012 number_to_chars_bigendian (buf, val, n);
fecd2382
RP		 4013}
4014
49864cfa
KR		 4015static void
4016md_apply_fix_2 (fixP, val)
355afbcd 4017 fixS *fixP;
9ad5755f 4018 offsetT val;
fecd2382 4019{
9ad5755f
KR		 4020 addressT upper_limit;
4021 offsetT lower_limit;
49864cfa 4022
9ad5755f
KR		 4023 /* This is unnecessary but it convinces the native rs6000 compiler
4024 to generate the code we want. */
355afbcd
KR		 4025 char *buf = fixP->fx_frag->fr_literal;
4026 buf += fixP->fx_where;
9ad5755f
KR		 4027 /* end ibm compiler workaround */
4028
4029 if (val & 0x80000000)
4030 val |= ~(addressT)0x7fffffff;
4031 else
4032 val &= 0x7fffffff;
6d27d3a2 4033
a043f579
ILT		 4034#ifdef OBJ_ELF
4035 if (fixP->fx_addsy)
4036 {
4037 memset (buf, 0, fixP->fx_size);
4038 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4039 return;
4040 }
4041#endif
4042
355afbcd
KR		 4043 switch (fixP->fx_size)
4044 {
b79de3a1
KR		 4045 /* The cast to offsetT below are necessary to make code correct for
4046 machines where ints are smaller than offsetT */
355afbcd
KR		 4047 case 1:
4048 *buf++ = val;
49864cfa 4049 upper_limit = 0x7f;
b79de3a1 4050 lower_limit = - (offsetT) 0x80;
355afbcd
KR		 4051 break;
4052 case 2:
4053 *buf++ = (val >> 8);
4054 *buf++ = val;
49864cfa 4055 upper_limit = 0x7fff;
b79de3a1 4056 lower_limit = - (offsetT) 0x8000;
355afbcd
KR		 4057 break;
4058 case 4:
4059 *buf++ = (val >> 24);
4060 *buf++ = (val >> 16);
4061 *buf++ = (val >> 8);
4062 *buf++ = val;
49864cfa 4063 upper_limit = 0x7fffffff;
b79de3a1 4064 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
355afbcd
KR		 4065 break;
4066 default:
4067 BAD_CASE (fixP->fx_size);
4068 }
49864cfa 4069
3b06beb7
ILT		 4070 /* Fix up a negative reloc. */
4071 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4072 {
4073 fixP->fx_addsy = fixP->fx_subsy;
4074 fixP->fx_subsy = NULL;
4075 fixP->fx_tcbit = 1;
4076 }
4077
49864cfa
KR		 4078 /* For non-pc-relative values, it's conceivable we might get something
4079 like "0xff" for a byte field. So extend the upper part of the range
4080 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4081 so that we can do any range checking at all. */
a78bc551 4082 if (! fixP->fx_pcrel && ! fixP->fx_signed)
49864cfa
KR		 4083 upper_limit = upper_limit * 2 + 1;
4084
9ad5755f
KR		 4085 if ((addressT) val > upper_limit
4086 && (val > 0 || val < lower_limit))
48401fcf 4087 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
f3751617
ILT		 4088
4089 /* A one byte PC-relative reloc means a short branch. We can't use
4090 a short branch with a value of 0 or -1, because those indicate
469adf23
ILT		 4091 different opcodes (branches with longer offsets). fixup_segment
4092 in write.c may have clobbered fx_pcrel, so we need to examine the
4093 reloc type. */
4094 if ((fixP->fx_pcrel
4095#ifdef BFD_ASSEMBLER
4096 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4097#endif
4098 )
f3751617
ILT		 4099 && fixP->fx_size == 1
4100 && (fixP->fx_addsy == NULL
4101 || S_IS_DEFINED (fixP->fx_addsy))
4102 && (val == 0 || val == -1))
48401fcf 4103 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
fecd2382
RP		 4104}
4105
49864cfa
KR		 4106#ifdef BFD_ASSEMBLER
4107int
4108md_apply_fix (fixP, valp)
4109 fixS *fixP;
5f8cb05e 4110 valueT *valp;
49864cfa 4111{
9ad5755f 4112 md_apply_fix_2 (fixP, (addressT) *valp);
49864cfa
KR		 4113 return 1;
4114}
4115#else
4116void md_apply_fix (fixP, val)
4117 fixS *fixP;
4118 long val;
4119{
9ad5755f 4120 md_apply_fix_2 (fixP, (addressT) val);
49864cfa
KR		 4121}
4122#endif
fecd2382
RP		 4123
4124/* *fragP has been relaxed to its final size, and now needs to have
4125 the bytes inside it modified to conform to the new size There is UGLY
4126 MAGIC here. ..
a39116f1 4127 */
0917e2cb 4128static void
49864cfa 4129md_convert_frag_1 (fragP)
355afbcd 4130 register fragS *fragP;
fecd2382 4131{
355afbcd
KR		 4132 long disp;
4133 long ext = 0;
5f8cb05e 4134 fixS *fixP;
6d27d3a2 4135
355afbcd
KR		 4136 /* Address in object code of the displacement. */
4137 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 4138
9ad5755f
KR		 4139 /* Address in gas core of the place to store the displacement. */
4140 /* This convinces the native rs6000 compiler to generate the code we
4141 want. */
355afbcd
KR		 4142 register char *buffer_address = fragP->fr_literal;
4143 buffer_address += fragP->fr_fix;
9ad5755f 4144 /* end ibm compiler workaround */
6d27d3a2 4145
355afbcd
KR		 4146 /* The displacement of the address, from current location. */
4147 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4148 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 4149
5f8cb05e
ILT		 4150#ifdef BFD_ASSEMBLER
4151 disp += fragP->fr_symbol->sy_frag->fr_address;
4152#endif
4153
355afbcd
KR		 4154 switch (fragP->fr_subtype)
4155 {
4156 case TAB (BCC68000, BYTE):
4157 case TAB (ABRANCH, BYTE):
4158 know (issbyte (disp));
4159 if (disp == 0)
48401fcf 4160 as_bad (_("short branch with zero offset: use :w"));
355afbcd
KR		 4161 fragP->fr_opcode[1] = disp;
4162 ext = 0;
4163 break;
4164 case TAB (DBCC, SHORT):
4165 know (issword (disp));
4166 ext = 2;
4167 break;
4168 case TAB (BCC68000, SHORT):
4169 case TAB (ABRANCH, SHORT):
4170 know (issword (disp));
4171 fragP->fr_opcode[1] = 0x00;
4172 ext = 2;
4173 break;
4174 case TAB (ABRANCH, LONG):
ffecfc8b 4175 if (!HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4176 {
4177 if (fragP->fr_opcode[0] == 0x61)
04ef74bb 4178 /* BSR */
355afbcd
KR		 4179 {
4180 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4181 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd
KR		 4182
4183 fix_new (fragP,
4184 fragP->fr_fix,
4185 4,
4186 fragP->fr_symbol,
355afbcd
KR		 4187 fragP->fr_offset,
4188 0,
4189 NO_RELOC);
4190
4191 fragP->fr_fix += 4;
4192 ext = 0;
4193 }
04ef74bb 4194 /* BRA */
355afbcd
KR		 4195 else if (fragP->fr_opcode[0] == 0x60)
4196 {
4197 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4198 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
bcb8dff8
KR		 4199 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4200 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4201 fragP->fr_fix += 4;
4202 ext = 0;
4203 }
4204 else
4205 {
48401fcf 4206 as_bad (_("Long branch offset not supported."));
355afbcd
KR		 4207 }
4208 }
4209 else
4210 {
bcb8dff8 4211 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4212 ext = 4;
4213 }
4214 break;
4215 case TAB (BCC68000, LONG):
4216 /* only Bcc 68000 instructions can come here */
4217 /* change bcc into b!cc/jmp absl long */
4218 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4219 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 4220
355afbcd 4221 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 4222 different frag, in which case refering to them is a no-no.
4223 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 4224 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4225 *buffer_address++ = (char) 0xf9;
355afbcd 4226 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8
KR		 4227 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4228 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4229 fragP->fr_fix += 4;
4230 ext = 0;
4231 break;
4232 case TAB (DBCC, LONG):
4233 /* only DBcc 68000 instructions can come here */
4234 /* change dbcc into dbcc/jmp absl long */
4235 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4236 *buffer_address++ = 0x00; /* branch offset = 4 */
4237 *buffer_address++ = 0x04;
4238 *buffer_address++ = 0x60; /* put in bra pc+6 */
4239 *buffer_address++ = 0x06;
4240 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4241 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 4242
4243 fragP->fr_fix += 6; /* account for bra/jmp instructions */
bcb8dff8 4244 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 4245 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4246 fragP->fr_fix += 4;
4247 ext = 0;
4248 break;
4249 case TAB (FBRANCH, SHORT):
4250 know ((fragP->fr_opcode[1] & 0x40) == 0);
4251 ext = 2;
4252 break;
4253 case TAB (FBRANCH, LONG):
4254 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4255 ext = 4;
4256 break;
4257 case TAB (PCREL, SHORT):
4258 ext = 2;
4259 break;
4260 case TAB (PCREL, LONG):
4261 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 4262 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 4263 /* JF FOO This code has not been tested */
bcb8dff8 4264 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 4265 0, NO_RELOC);
355afbcd 4266 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
48401fcf 4267 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
bcb8dff8
KR		 4268 (unsigned) fragP->fr_opcode[0],
4269 (unsigned long) fragP->fr_address);
355afbcd
KR		 4270 fragP->fr_opcode[1] &= ~0x3F;
4271 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4272 fragP->fr_fix += 4;
355afbcd
KR		 4273 ext = 0;
4274 break;
4275 case TAB (PCLEA, SHORT):
49864cfa 4276 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 4277 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4278 fragP->fr_opcode[1] &= ~0x3F;
04ef74bb 4279 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
355afbcd
KR		 4280 ext = 2;
4281 break;
4282 case TAB (PCLEA, LONG):
5f8cb05e
ILT		 4283 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4284 fragP->fr_offset, 1, NO_RELOC);
4285 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4286 /* Already set to mode 7.3; this indicates: PC indirect with
4287 suppressed index, 32-bit displacement. */
355afbcd
KR		 4288 *buffer_address++ = 0x01;
4289 *buffer_address++ = 0x70;
4290 fragP->fr_fix += 2;
355afbcd
KR		 4291 ext = 4;
4292 break;
04ef74bb
KR		 4293
4294 case TAB (PCINDEX, BYTE):
4295 disp += 2;
4296 if (!issbyte (disp))
4297 {
48401fcf 4298 as_bad (_("displacement doesn't fit in one byte"));
04ef74bb
KR		 4299 disp = 0;
4300 }
5f8cb05e
ILT		 4301 assert (fragP->fr_fix >= 2);
4302 buffer_address[-2] &= ~1;
4303 buffer_address[-1] = disp;
04ef74bb
KR		 4304 ext = 0;
4305 break;
4306 case TAB (PCINDEX, SHORT):
04ef74bb
KR		 4307 disp += 2;
4308 assert (issword (disp));
5f8cb05e
ILT		 4309 assert (fragP->fr_fix >= 2);
4310 buffer_address[-2] |= 0x1;
4311 buffer_address[-1] = 0x20;
4312 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4313 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4314 NO_RELOC);
4315 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4316 ext = 2;
4317 break;
4318 case TAB (PCINDEX, LONG):
04ef74bb 4319 disp += 2;
5f8cb05e
ILT		 4320 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4321 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4322 NO_RELOC);
4323 fixP->fx_pcrel_adjust = 2;
4324 assert (fragP->fr_fix >= 2);
4325 buffer_address[-2] |= 0x1;
4326 buffer_address[-1] = 0x30;
04ef74bb
KR		 4327 ext = 4;
4328 break;
49864cfa 4329 }
355afbcd
KR		 4330
4331 if (ext)
4332 {
4333 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4334 fragP->fr_fix += ext;
49864cfa
KR		 4335 }
4336}
355afbcd 4337
49864cfa
KR		 4338#ifndef BFD_ASSEMBLER
4339
4340void
064ba683 4341md_convert_frag (headers, sec, fragP)
49864cfa 4342 object_headers *headers;
064ba683 4343 segT sec;
49864cfa
KR		 4344 fragS *fragP;
4345{
4346 md_convert_frag_1 (fragP);
4347}
4348
4349#else
4350
4351void
4352md_convert_frag (abfd, sec, fragP)
4353 bfd *abfd;
5f8cb05e 4354 segT sec;
49864cfa
KR		 4355 fragS *fragP;
4356{
4357 md_convert_frag_1 (fragP);
4358}
4359#endif
355afbcd
KR		 4360
4361/* Force truly undefined symbols to their maximum size, and generally set up
4362 the frag list to be relaxed
4363 */
4364int
4365md_estimate_size_before_relax (fragP, segment)
4366 register fragS *fragP;
4367 segT segment;
4368{
4369 int old_fix;
4370 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4371
4372 old_fix = fragP->fr_fix;
4373
4374 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4375 switch (fragP->fr_subtype)
4376 {
4377
4378 case TAB (ABRANCH, SZ_UNDEF):
4379 {
4380 if ((fragP->fr_symbol != NULL) /* Not absolute */
4381 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4382 {
4383 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4384 break;
4385 }
ffecfc8b 4386 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4387 {
4388 /* On 68000, or for absolute value, switch to abs long */
4389 /* FIXME, we should check abs val, pick short or long */
4390 if (fragP->fr_opcode[0] == 0x61)
4391 {
4392 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4393 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd 4394 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4395 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4396 fragP->fr_fix += 4;
4397 frag_wane (fragP);
4398 }
4399 else if (fragP->fr_opcode[0] == 0x60)
4400 {
4401 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4402 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
355afbcd 4403 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4404 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4405 fragP->fr_fix += 4;
4406 frag_wane (fragP);
4407 }
4408 else
4409 {
48401fcf 4410 as_warn (_("Long branch offset to extern symbol not supported."));
355afbcd
KR		 4411 }
4412 }
4413 else
4414 { /* Symbol is still undefined. Make it simple */
4415 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5f8cb05e 4416 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4417 fragP->fr_fix += 4;
bcb8dff8 4418 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4419 frag_wane (fragP);
4420 break;
4421 }
4422
a39116f1 4423 break;
355afbcd 4424 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 4425
355afbcd
KR		 4426 case TAB (FBRANCH, SZ_UNDEF):
4427 {
9ad5755f 4428 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
355afbcd
KR		 4429 {
4430 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4431 fragP->fr_var += 2;
4432 }
4433 else
4434 {
5f8cb05e
ILT		 4435 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4436 fragP->fr_offset, 1, NO_RELOC);
4437 fragP->fr_fix += 4;
4438 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4439 frag_wane (fragP);
355afbcd
KR		 4440 }
4441 break;
4442 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 4443
355afbcd
KR		 4444 case TAB (PCREL, SZ_UNDEF):
4445 {
dcb76edb
ILT		 4446 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4447 && relaxable_symbol (fragP->fr_symbol))
b79de3a1 4448 || flag_short_refs
48401fcf
TT		 4449 || cpu_of_arch (current_architecture) < m68020
4450 || cpu_of_arch (current_architecture) == mcf5200)
355afbcd
KR		 4451 {
4452 fragP->fr_subtype = TAB (PCREL, SHORT);
4453 fragP->fr_var += 2;
4454 }
4455 else
4456 {
4457 fragP->fr_subtype = TAB (PCREL, LONG);
4458 fragP->fr_var += 4;
4459 }
4460 break;
4461 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 4462
355afbcd
KR		 4463 case TAB (BCC68000, SZ_UNDEF):
4464 {
4465 if ((fragP->fr_symbol != NULL)
4466 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4467 {
4468 fragP->fr_subtype = TAB (BCC68000, BYTE);
4469 break;
4470 }
4471 /* only Bcc 68000 instructions can come here */
4472 /* change bcc into b!cc/jmp absl long */
4473 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
9ad5755f 4474 if (flag_short_refs)
355afbcd
KR		 4475 {
4476 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4477 /* JF: these were fr_opcode[2,3] */
4478 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4479 buffer_address[1] = (char) 0xf8;
355afbcd 4480 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4481 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4482 fragP->fr_offset, 0, NO_RELOC);
4483 fragP->fr_fix += 2;
4484 }
4485 else
4486 {
4487 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4488 /* JF: these were fr_opcode[2,3] */
4489 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4490 buffer_address[1] = (char) 0xf9;
355afbcd 4491 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4492 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4493 fragP->fr_offset, 0, NO_RELOC);
4494 fragP->fr_fix += 4;
4495 }
4496 frag_wane (fragP);
4497 break;
4498 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 4499
355afbcd
KR		 4500 case TAB (DBCC, SZ_UNDEF):
4501 {
4502 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4503 {
4504 fragP->fr_subtype = TAB (DBCC, SHORT);
4505 fragP->fr_var += 2;
4506 break;
4507 }
4508 /* only DBcc 68000 instructions can come here */
4509 /* change dbcc into dbcc/jmp absl long */
4510 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4511 buffer_address[0] = 0x00; /* branch offset = 4 */
4512 buffer_address[1] = 0x04;
4513 buffer_address[2] = 0x60; /* put in bra pc + ... */
4514
9ad5755f 4515 if (flag_short_refs)
355afbcd
KR		 4516 {
4517 /* JF: these were fr_opcode[5-7] */
4518 buffer_address[3] = 0x04; /* plus 4 */
4519 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 4520 buffer_address[5] = (char) 0xf8;
355afbcd 4521 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4522 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4523 fragP->fr_offset, 0, NO_RELOC);
4524 fragP->fr_fix += 2;
4525 }
4526 else
4527 {
4528 /* JF: these were fr_opcode[5-7] */
4529 buffer_address[3] = 0x06; /* Plus 6 */
4530 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4531 buffer_address[5] = (char) 0xf9;
355afbcd 4532 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4533 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4534 fragP->fr_offset, 0, NO_RELOC);
4535 fragP->fr_fix += 4;
4536 }
6d27d3a2 4537
355afbcd
KR		 4538 frag_wane (fragP);
4539 break;
4540 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 4541
355afbcd
KR		 4542 case TAB (PCLEA, SZ_UNDEF):
4543 {
dcb76edb
ILT		 4544 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4545 && relaxable_symbol (fragP->fr_symbol))
b79de3a1 4546 || flag_short_refs
48401fcf
TT		 4547 || cpu_of_arch (current_architecture) < m68020
4548 || cpu_of_arch (current_architecture) == mcf5200)
355afbcd
KR		 4549 {
4550 fragP->fr_subtype = TAB (PCLEA, SHORT);
4551 fragP->fr_var += 2;
4552 }
4553 else
4554 {
4555 fragP->fr_subtype = TAB (PCLEA, LONG);
4556 fragP->fr_var += 6;
4557 }
4558 break;
4559 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 4560
04ef74bb 4561 case TAB (PCINDEX, SZ_UNDEF):
dcb76edb
ILT		 4562 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4563 && relaxable_symbol (fragP->fr_symbol))
48401fcf
TT		 4564 || cpu_of_arch (current_architecture) < m68020
4565 || cpu_of_arch (current_architecture) == mcf5200)
04ef74bb
KR		 4566 {
4567 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4568 }
4569 else
4570 {
4571 fragP->fr_subtype = TAB (PCINDEX, LONG);
5f8cb05e 4572 fragP->fr_var += 4;
04ef74bb 4573 }
355afbcd 4574 break;
6d27d3a2 4575
04ef74bb
KR		 4576 default:
4577 break;
4578 }
6d27d3a2 4579
355afbcd
KR		 4580 /* now that SZ_UNDEF are taken care of, check others */
4581 switch (fragP->fr_subtype)
4582 {
4583 case TAB (BCC68000, BYTE):
4584 case TAB (ABRANCH, BYTE):
024e1779
ILT		 4585 /* We can't do a short jump to the next instruction, so in that
4586 case we force word mode. At this point S_GET_VALUE should
4587 return the offset of the symbol within its frag. If the
4588 symbol is at the start of a frag, and it is the next frag
4589 with any data in it (usually this is just the next frag, but
4590 assembler listings may introduce empty frags), we must use
4591 word mode. */
65feb78d 4592 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
355afbcd 4593 {
65feb78d
ILT		 4594 fragS *l;
4595
4596 for (l = fragP->fr_next;
4597 l != fragP->fr_symbol->sy_frag;
4598 l = l->fr_next)
4599 if (l->fr_fix + l->fr_var != 0)
4600 break;
4601 if (l == fragP->fr_symbol->sy_frag)
4602 {
4603 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4604 fragP->fr_var += 2;
4605 }
fecd2382 4606 }
355afbcd
KR		 4607 break;
4608 default:
4609 break;
4610 }
4611 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 4612}
4613
4614#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 4615/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 4616 with the byte-order problems of cross-assembly. So as a hack,
4617 I added this mach. dependent ri twiddler. Ugly, but it gets
4618 you there. -KWK */
4619/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 4620 are symbolnum, most sig. byte first. Last byte is broken up with
4621 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4622 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 4623/* Translate the internal relocation information into target-specific
4624 format. */
a79c6033 4625#ifdef comment
fecd2382 4626void
355afbcd
KR		 4627md_ri_to_chars (the_bytes, ri)
4628 char *the_bytes;
4629 struct reloc_info_generic *ri;
fecd2382 4630{
355afbcd
KR		 4631 /* this is easy */
4632 md_number_to_chars (the_bytes, ri->r_address, 4);
4633 /* now the fun stuff */
4634 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4635 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4636 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4637 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4638 ((ri->r_extern << 4) & 0x10));
fecd2382 4639}
355afbcd 4640
a79c6033
RP		 4641#endif /* comment */
4642
49864cfa 4643#ifndef BFD_ASSEMBLER
355afbcd
KR		 4644void
4645tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4646 char *where;
4647 fixS *fixP;
4648 relax_addressT segment_address_in_file;
a79c6033 4649{
355afbcd 4650 /*
1404ef23
KR		 4651 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4652 * Out: GNU LD relocation length code: 0, 1, or 2.
4653 */
6d27d3a2 4654
82489ea0 4655 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
355afbcd 4656 long r_symbolnum;
6d27d3a2 4657
355afbcd 4658 know (fixP->fx_addsy != NULL);
6d27d3a2 4659
355afbcd
KR		 4660 md_number_to_chars (where,
4661 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4662 4);
6d27d3a2 4663
355afbcd
KR		 4664 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4665 ? S_GET_TYPE (fixP->fx_addsy)
4666 : fixP->fx_addsy->sy_number);
6d27d3a2 4667
355afbcd
KR		 4668 where[4] = (r_symbolnum >> 16) & 0x0ff;
4669 where[5] = (r_symbolnum >> 8) & 0x0ff;
4670 where[6] = r_symbolnum & 0x0ff;
4671 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4672 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
49864cfa
KR		 4673}
4674#endif
a79c6033 4675
fecd2382
RP		 4676#endif /* OBJ_AOUT or OBJ_BOUT */
4677
4678#ifndef WORKING_DOT_WORD
49864cfa
KR		 4679CONST int md_short_jump_size = 4;
4680CONST int md_long_jump_size = 6;
fecd2382
RP		 4681
4682void
355afbcd
KR		 4683md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4684 char *ptr;
025b0302 4685 addressT from_addr, to_addr;
355afbcd
KR		 4686 fragS *frag;
4687 symbolS *to_symbol;
fecd2382 4688{
025b0302 4689 valueT offset;
6d27d3a2 4690
355afbcd 4691 offset = to_addr - (from_addr + 2);
6d27d3a2 4692
025b0302
ME		 4693 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4694 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 4695}
4696
4697void
355afbcd
KR		 4698md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4699 char *ptr;
025b0302 4700 addressT from_addr, to_addr;
355afbcd
KR		 4701 fragS *frag;
4702 symbolS *to_symbol;
fecd2382 4703{
025b0302 4704 valueT offset;
355afbcd 4705
ffecfc8b 4706 if (!HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4707 {
4708 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 4709 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4710 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 4711 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4712 0, NO_RELOC);
355afbcd
KR		 4713 }
4714 else
4715 {
4716 offset = to_addr - (from_addr + 2);
025b0302
ME		 4717 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4718 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 4719 }
fecd2382
RP		 4720}
4721
4722#endif
a1c7c0f3
ILT		 4723
4724/* Different values of OK tell what its OK to return. Things that
4725 aren't OK are an error (what a shock, no?)
6d27d3a2 4726
a39116f1
RP		 4727 0: Everything is OK
4728 10: Absolute 1:8 only
4729 20: Absolute 0:7 only
4730 30: absolute 0:15 only
4731 40: Absolute 0:31 only
4732 50: absolute 0:127 only
4733 55: absolute -64:63 only
4734 60: absolute -128:127 only
4735 70: absolute 0:4095 only
4736 80: No bignums
6d27d3a2 4737
a39116f1 4738 */
fecd2382 4739
355afbcd
KR		 4740static int
4741get_num (exp, ok)
4742 struct m68k_exp *exp;
4743 int ok;
fecd2382 4744{
a1c7c0f3 4745 if (exp->exp.X_op == O_absent)
49864cfa 4746 {
355afbcd 4747 /* Do the same thing the VAX asm does */
bcb8dff8 4748 op (exp) = O_constant;
355afbcd
KR		 4749 adds (exp) = 0;
4750 subs (exp) = 0;
4751 offs (exp) = 0;
4752 if (ok == 10)
4753 {
48401fcf 4754 as_warn (_("expression out of range: defaulting to 1"));
355afbcd
KR		 4755 offs (exp) = 1;
4756 }
49864cfa 4757 }
a1c7c0f3 4758 else if (exp->exp.X_op == O_constant)
49864cfa 4759 {
355afbcd
KR		 4760 switch (ok)
4761 {
4762 case 10:
4763 if (offs (exp) < 1 || offs (exp) > 8)
4764 {
48401fcf 4765 as_warn (_("expression out of range: defaulting to 1"));
355afbcd
KR		 4766 offs (exp) = 1;
4767 }
4768 break;
4769 case 20:
4770 if (offs (exp) < 0 || offs (exp) > 7)
4771 goto outrange;
4772 break;
4773 case 30:
4774 if (offs (exp) < 0 || offs (exp) > 15)
4775 goto outrange;
4776 break;
4777 case 40:
4778 if (offs (exp) < 0 || offs (exp) > 32)
4779 goto outrange;
4780 break;
4781 case 50:
4782 if (offs (exp) < 0 || offs (exp) > 127)
4783 goto outrange;
4784 break;
4785 case 55:
4786 if (offs (exp) < -64 || offs (exp) > 63)
4787 goto outrange;
4788 break;
4789 case 60:
4790 if (offs (exp) < -128 || offs (exp) > 127)
4791 goto outrange;
4792 break;
4793 case 70:
4794 if (offs (exp) < 0 || offs (exp) > 4095)
4795 {
4796 outrange:
48401fcf 4797 as_warn (_("expression out of range: defaulting to 0"));
355afbcd
KR		 4798 offs (exp) = 0;
4799 }
4800 break;
fecd2382 4801 default:
355afbcd
KR		 4802 break;
4803 }
49864cfa 4804 }
a1c7c0f3 4805 else if (exp->exp.X_op == O_big)
49864cfa 4806 {
bcb8dff8 4807 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 4808 && (ok == 80 /* no bignums */
4809 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 4810 /* If we have a flonum zero, a zero integer should
4811 do as well (e.g., in moveq). */
355afbcd
KR		 4812 && generic_floating_point_number.exponent == 0
4813 && generic_floating_point_number.low[0] == 0)))
4814 {
4815 /* HACK! Turn it into a long */
4816 LITTLENUM_TYPE words[6];
4817
4818 gen_to_words (words, 2, 8L); /* These numbers are magic! */
bcb8dff8 4819 op (exp) = O_constant;
355afbcd
KR		 4820 adds (exp) = 0;
4821 subs (exp) = 0;
4822 offs (exp) = words[1] | (words[0] << 16);
4823 }
4824 else if (ok != 0)
4825 {
bcb8dff8 4826 op (exp) = O_constant;
355afbcd
KR		 4827 adds (exp) = 0;
4828 subs (exp) = 0;
4829 offs (exp) = (ok == 10) ? 1 : 0;
48401fcf 4830 as_warn (_("Can't deal with expression; defaulting to %ld"),
a1c7c0f3 4831 offs (exp));
355afbcd 4832 }
49864cfa
KR		 4833 }
4834 else
4835 {
355afbcd
KR		 4836 if (ok >= 10 && ok <= 70)
4837 {
bcb8dff8 4838 op (exp) = O_constant;
355afbcd
KR		 4839 adds (exp) = 0;
4840 subs (exp) = 0;
4841 offs (exp) = (ok == 10) ? 1 : 0;
48401fcf 4842 as_warn (_("Can't deal with expression; defaulting to %ld"),
a1c7c0f3 4843 offs (exp));
355afbcd 4844 }
355afbcd 4845 }
49864cfa 4846
a1c7c0f3 4847 if (exp->size != SIZE_UNSPEC)
355afbcd 4848 {
a1c7c0f3 4849 switch (exp->size)
355afbcd 4850 {
a1c7c0f3
ILT		 4851 case SIZE_UNSPEC:
4852 case SIZE_LONG:
4853 break;
4854 case SIZE_BYTE:
355afbcd 4855 if (!isbyte (offs (exp)))
48401fcf 4856 as_warn (_("expression doesn't fit in BYTE"));
355afbcd 4857 break;
a1c7c0f3 4858 case SIZE_WORD:
355afbcd 4859 if (!isword (offs (exp)))
48401fcf 4860 as_warn (_("expression doesn't fit in WORD"));
355afbcd 4861 break;
a39116f1 4862 }
355afbcd 4863 }
a1c7c0f3 4864
355afbcd 4865 return offs (exp);
49864cfa 4866}
fecd2382
RP		 4867
4868/* These are the back-ends for the various machine dependent pseudo-ops. */
4869
355afbcd 4870static void
bcb8dff8
KR		 4871s_data1 (ignore)
4872 int ignore;
355afbcd 4873{
bcb8dff8 4874 subseg_set (data_section, 1);
355afbcd 4875 demand_empty_rest_of_line ();
49864cfa 4876}
fecd2382 4877
355afbcd 4878static void
bcb8dff8
KR		 4879s_data2 (ignore)
4880 int ignore;
355afbcd 4881{
bcb8dff8 4882 subseg_set (data_section, 2);
355afbcd 4883 demand_empty_rest_of_line ();
49864cfa 4884}
fecd2382 4885
355afbcd 4886static void
bcb8dff8
KR		 4887s_bss (ignore)
4888 int ignore;
a1765cf0 4889{
355afbcd 4890 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 4891 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 4892
bcb8dff8 4893 subseg_set (bss_section, 0);
355afbcd 4894 demand_empty_rest_of_line ();
49864cfa 4895}
6d27d3a2 4896
355afbcd 4897static void
bcb8dff8
KR		 4898s_even (ignore)
4899 int ignore;
355afbcd
KR		 4900{
4901 register int temp;
4902 register long temp_fill;
4903
4904 temp = 1; /* JF should be 2? */
4905 temp_fill = get_absolute_expression ();
4906 if (!need_pass_2) /* Never make frag if expect extra pass. */
fee3e248 4907 frag_align (temp, (int) temp_fill, 0);
355afbcd 4908 demand_empty_rest_of_line ();
79811f6f 4909 record_alignment (now_seg, temp);
49864cfa 4910}
355afbcd
KR		 4911
4912static void
bcb8dff8
KR		 4913s_proc (ignore)
4914 int ignore;
355afbcd
KR		 4915{
4916 demand_empty_rest_of_line ();
49864cfa 4917}
e9bb39b4
ILT		 4918\f
4919/* Pseudo-ops handled for MRI compatibility. */
4920
a986926b
ILT		 4921/* This function returns non-zero if the argument is a conditional
4922 pseudo-op. This is called when checking whether a pending
4923 alignment is needed. */
4924
4925int
4926m68k_conditional_pseudoop (pop)
4927 pseudo_typeS *pop;
4928{
4929 return (pop->poc_handler == s_mri_if
4930 || pop->poc_handler == s_mri_else);
4931}
4932
e9bb39b4 4933/* Handle an MRI style chip specification. */
fecd2382 4934
e9bb39b4
ILT		 4935static void
4936mri_chip ()
4937{
4938 char *s;
4939 char c;
4940 int i;
4941
4942 s = input_line_pointer;
af438bdb
ILT		 4943 /* We can't use get_symbol_end since the processor names are not proper
4944 symbols. */
4945 while (is_part_of_name (c = *input_line_pointer++))
4946 ;
4947 *--input_line_pointer = 0;
e9bb39b4
ILT		 4948 for (i = 0; i < n_archs; i++)
4949 if (strcasecmp (s, archs[i].name) == 0)
4950 break;
4951 if (i >= n_archs)
4952 {
48401fcf 4953 as_bad (_("%s: unrecognized processor name"), s);
e9bb39b4
ILT		 4954 *input_line_pointer = c;
4955 ignore_rest_of_line ();
4956 return;
4957 }
4958 *input_line_pointer = c;
fecd2382 4959
e9bb39b4
ILT		 4960 if (*input_line_pointer == '/')
4961 current_architecture = 0;
4962 else
4963 current_architecture &= m68881 | m68851;
4964 current_architecture |= archs[i].arch;
4965
4966 while (*input_line_pointer == '/')
4967 {
4968 ++input_line_pointer;
4969 s = input_line_pointer;
af438bdb
ILT		 4970 /* We can't use get_symbol_end since the processor names are not
4971 proper symbols. */
4972 while (is_part_of_name (c = *input_line_pointer++))
4973 ;
4974 *--input_line_pointer = 0;
e9bb39b4
ILT		 4975 if (strcmp (s, "68881") == 0)
4976 current_architecture |= m68881;
4977 else if (strcmp (s, "68851") == 0)
4978 current_architecture |= m68851;
4979 *input_line_pointer = c;
4980 }
b4d51f3d
ILT		 4981
4982 /* Update info about available control registers. */
4983 select_control_regs ();
e9bb39b4
ILT		 4984}
4985
4986/* The MRI CHIP pseudo-op. */
4987
4988static void
4989s_chip (ignore)
4990 int ignore;
4991{
f9680a05
ILT		 4992 char *stop = NULL;
4993 char stopc;
4994
4995 if (flag_mri)
4996 stop = mri_comment_field (&stopc);
e9bb39b4 4997 mri_chip ();
f9680a05
ILT		 4998 if (flag_mri)
4999 mri_comment_end (stop, stopc);
e9bb39b4
ILT		 5000 demand_empty_rest_of_line ();
5001}
27a53b88
ILT		 5002
5003/* The MRI FOPT pseudo-op. */
5004
5005static void
5006s_fopt (ignore)
5007 int ignore;
5008{
5009 SKIP_WHITESPACE ();
5010
5011 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5012 {
5013 int temp;
5014
5015 input_line_pointer += 3;
5016 temp = get_absolute_expression ();
5017 if (temp < 0 || temp > 7)
48401fcf 5018 as_bad (_("bad coprocessor id"));
27a53b88
ILT		 5019 else
5020 m68k_float_copnum = COP0 + temp;
5021 }
5022 else
5023 {
48401fcf 5024 as_bad (_("unrecognized fopt option"));
27a53b88
ILT		 5025 ignore_rest_of_line ();
5026 return;
5027 }
5028
5029 demand_empty_rest_of_line ();
5030}
6700d36e
ILT		 5031
5032/* The structure used to handle the MRI OPT pseudo-op. */
5033
5034struct opt_action
5035{
5036 /* The name of the option. */
5037 const char *name;
5038
5039 /* If this is not NULL, just call this function. The first argument
5040 is the ARG field of this structure, the second argument is
5041 whether the option was negated. */
5042 void (*pfn) PARAMS ((int arg, int on));
5043
5044 /* If this is not NULL, and the PFN field is NULL, set the variable
5045 this points to. Set it to the ARG field if the option was not
5046 negated, and the NOTARG field otherwise. */
5047 int *pvar;
5048
5049 /* The value to pass to PFN or to assign to *PVAR. */
5050 int arg;
5051
5052 /* The value to assign to *PVAR if the option is negated. If PFN is
5053 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5054 the option may not be negated. */
5055 int notarg;
5056};
5057
5058/* The table used to handle the MRI OPT pseudo-op. */
5059
5060static void skip_to_comma PARAMS ((int, int));
7e047ac2 5061static void opt_nest PARAMS ((int, int));
6700d36e
ILT		 5062static void opt_chip PARAMS ((int, int));
5063static void opt_list PARAMS ((int, int));
5064static void opt_list_symbols PARAMS ((int, int));
5065
5066static const struct opt_action opt_table[] =
5067{
5068 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5069
5070 /* We do relaxing, so there is little use for these options. */
5071 { "b", 0, 0, 0, 0 },
5072 { "brs", 0, 0, 0, 0 },
5073 { "brb", 0, 0, 0, 0 },
5074 { "brl", 0, 0, 0, 0 },
5075 { "brw", 0, 0, 0, 0 },
5076
5077 { "c", 0, 0, 0, 0 },
5078 { "cex", 0, 0, 0, 0 },
5079 { "case", 0, &symbols_case_sensitive, 1, 0 },
5080 { "cl", 0, 0, 0, 0 },
5081 { "cre", 0, 0, 0, 0 },
5082 { "d", 0, &flag_keep_locals, 1, 0 },
5083 { "e", 0, 0, 0, 0 },
5084 { "f", 0, &flag_short_refs, 1, 0 },
5085 { "frs", 0, &flag_short_refs, 1, 0 },
5086 { "frl", 0, &flag_short_refs, 0, 1 },
5087 { "g", 0, 0, 0, 0 },
5088 { "i", 0, 0, 0, 0 },
5089 { "m", 0, 0, 0, 0 },
5090 { "mex", 0, 0, 0, 0 },
5091 { "mc", 0, 0, 0, 0 },
5092 { "md", 0, 0, 0, 0 },
7e047ac2 5093 { "nest", opt_nest, 0, 0, 0 },
6700d36e
ILT		 5094 { "next", skip_to_comma, 0, 0, 0 },
5095 { "o", 0, 0, 0, 0 },
5096 { "old", 0, 0, 0, 0 },
5097 { "op", skip_to_comma, 0, 0, 0 },
5098 { "pco", 0, 0, 0, 0 },
5099 { "p", opt_chip, 0, 0, 0 },
5100 { "pcr", 0, 0, 0, 0 },
5101 { "pcs", 0, 0, 0, 0 },
5102 { "r", 0, 0, 0, 0 },
5103 { "quick", 0, &m68k_quick, 1, 0 },
5104 { "rel32", 0, &m68k_rel32, 1, 0 },
5105 { "s", opt_list, 0, 0, 0 },
5106 { "t", opt_list_symbols, 0, 0, 0 },
5107 { "w", 0, &flag_no_warnings, 0, 1 },
5108 { "x", 0, 0, 0, 0 }
5109};
5110
5111#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5112
5113/* The MRI OPT pseudo-op. */
5114
5115static void
5116s_opt (ignore)
5117 int ignore;
5118{
5119 do
5120 {
5121 int t;
5122 char *s;
5123 char c;
5124 int i;
5125 const struct opt_action *o;
5126
5127 SKIP_WHITESPACE ();
5128
5129 t = 1;
5130 if (*input_line_pointer == '-')
5131 {
5132 ++input_line_pointer;
5133 t = 0;
5134 }
5135 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5136 {
5137 input_line_pointer += 2;
5138 t = 0;
5139 }
5140
5141 s = input_line_pointer;
5142 c = get_symbol_end ();
5143
5144 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5145 {
5146 if (strcasecmp (s, o->name) == 0)
5147 {
5148 if (o->pfn)
5149 {
5150 /* Restore input_line_pointer now in case the option
5151 takes arguments. */
5152 *input_line_pointer = c;
5153 (*o->pfn) (o->arg, t);
5154 }
5155 else if (o->pvar != NULL)
5156 {
5157 if (! t && o->arg == o->notarg)
48401fcf 5158 as_bad (_("option `%s' may not be negated"), s);
6700d36e
ILT		 5159 *input_line_pointer = c;
5160 *o->pvar = t ? o->arg : o->notarg;
5161 }
9bef2324
ILT		 5162 else
5163 *input_line_pointer = c;
6700d36e
ILT		 5164 break;
5165 }
5166 }
5167 if (i >= OPTCOUNT)
5168 {
48401fcf 5169 as_bad (_("option `%s' not recognized"), s);
6700d36e
ILT		 5170 *input_line_pointer = c;
5171 }
5172 }
5173 while (*input_line_pointer++ == ',');
5174
5175 /* Move back to terminating character. */
5176 --input_line_pointer;
5177 demand_empty_rest_of_line ();
5178}
5179
5180/* Skip ahead to a comma. This is used for OPT options which we do
5181 not suppor tand which take arguments. */
5182
5183static void
5184skip_to_comma (arg, on)
5185 int arg;
5186 int on;
5187{
5188 while (*input_line_pointer != ','
5189 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5190 ++input_line_pointer;
5191}
5192
7e047ac2
ILT		 5193/* Handle the OPT NEST=depth option. */
5194
5195static void
5196opt_nest (arg, on)
5197 int arg;
5198 int on;
5199{
5200 if (*input_line_pointer != '=')
5201 {
48401fcf 5202 as_bad (_("bad format of OPT NEST=depth"));
7e047ac2
ILT		 5203 return;
5204 }
5205
5206 ++input_line_pointer;
5207 max_macro_nest = get_absolute_expression ();
5208}
5209
6700d36e
ILT		 5210/* Handle the OPT P=chip option. */
5211
5212static void
5213opt_chip (arg, on)
5214 int arg;
5215 int on;
5216{
5217 if (*input_line_pointer != '=')
5218 {
5219 /* This is just OPT P, which we do not support. */
5220 return;
5221 }
5222
5223 ++input_line_pointer;
5224 mri_chip ();
5225}
5226
5227/* Handle the OPT S option. */
5228
5229static void
5230opt_list (arg, on)
5231 int arg;
5232 int on;
5233{
5234 listing_list (on);
5235}
5236
5237/* Handle the OPT T option. */
5238
5239static void
5240opt_list_symbols (arg, on)
5241 int arg;
5242 int on;
5243{
5244 if (on)
5245 listing |= LISTING_SYMBOLS;
5246 else
5247 listing &=~ LISTING_SYMBOLS;
5248}
5249
5250/* Handle the MRI REG pseudo-op. */
5251
5252static void
5253s_reg (ignore)
5254 int ignore;
5255{
5256 char *s;
5257 int c;
8e11ad0a 5258 struct m68k_op rop;
48401fcf 5259 int mask;
f9680a05
ILT		 5260 char *stop = NULL;
5261 char stopc;
6700d36e 5262
7e047ac2 5263 if (line_label == NULL)
6700d36e 5264 {
48401fcf 5265 as_bad (_("missing label"));
6700d36e
ILT		 5266 ignore_rest_of_line ();
5267 return;
5268 }
5269
f9680a05
ILT		 5270 if (flag_mri)
5271 stop = mri_comment_field (&stopc);
5272
6700d36e
ILT		 5273 SKIP_WHITESPACE ();
5274
5275 s = input_line_pointer;
5276 while (isalnum ((unsigned char) *input_line_pointer)
5277#ifdef REGISTER_PREFIX
5278 || *input_line_pointer == REGISTER_PREFIX
5279#endif
5280 || *input_line_pointer == '/'
5281 || *input_line_pointer == '-')
5282 ++input_line_pointer;
5283 c = *input_line_pointer;
5284 *input_line_pointer = '\0';
5285
8e11ad0a 5286 if (m68k_ip_op (s, &rop) != 0)
6700d36e 5287 {
8e11ad0a 5288 if (rop.error == NULL)
48401fcf 5289 as_bad (_("bad register list"));
6700d36e 5290 else
48401fcf 5291 as_bad (_("bad register list: %s"), rop.error);
6700d36e
ILT		 5292 *input_line_pointer = c;
5293 ignore_rest_of_line ();
5294 return;
5295 }
5296
5297 *input_line_pointer = c;
5298
8e11ad0a
ILT		 5299 if (rop.mode == REGLST)
5300 mask = rop.mask;
5301 else if (rop.mode == DREG)
5302 mask = 1 << (rop.reg - DATA0);
5303 else if (rop.mode == AREG)
5304 mask = 1 << (rop.reg - ADDR0 + 8);
5305 else if (rop.mode == FPREG)
5306 mask = 1 << (rop.reg - FP0 + 16);
5307 else if (rop.mode == CONTROL
5308 && rop.reg == FPI)
6700d36e 5309 mask = 1 << 24;
8e11ad0a
ILT		 5310 else if (rop.mode == CONTROL
5311 && rop.reg == FPS)
6700d36e 5312 mask = 1 << 25;
8e11ad0a
ILT		 5313 else if (rop.mode == CONTROL
5314 && rop.reg == FPC)
6700d36e
ILT		 5315 mask = 1 << 26;
5316 else
5317 {
48401fcf 5318 as_bad (_("bad register list"));
6700d36e
ILT		 5319 ignore_rest_of_line ();
5320 return;
5321 }
5322
48401fcf
TT		 5323 S_SET_SEGMENT (line_label, reg_section);
5324 S_SET_VALUE (line_label, ~mask);
7e047ac2 5325 line_label->sy_frag = &zero_address_frag;
6700d36e 5326
85f34122 5327 if (flag_mri)
f9680a05 5328 mri_comment_end (stop, stopc);
85f34122 5329
6700d36e
ILT		 5330 demand_empty_rest_of_line ();
5331}
e14994d9
ILT		 5332
5333/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5334
5335struct save_opts
5336{
5337 struct save_opts *next;
5338 int abspcadd;
5339 int symbols_case_sensitive;
5340 int keep_locals;
5341 int short_refs;
5342 int architecture;
5343 int quick;
5344 int rel32;
5345 int listing;
5346 int no_warnings;
5347 /* FIXME: We don't save OPT S. */
5348};
5349
5350/* This variable holds the stack of saved options. */
5351
5352static struct save_opts *save_stack;
5353
5354/* The MRI SAVE pseudo-op. */
5355
5356static void
5357s_save (ignore)
5358 int ignore;
5359{
5360 struct save_opts *s;
5361
5362 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5363 s->abspcadd = m68k_abspcadd;
5364 s->symbols_case_sensitive = symbols_case_sensitive;
5365 s->keep_locals = flag_keep_locals;
5366 s->short_refs = flag_short_refs;
5367 s->architecture = current_architecture;
5368 s->quick = m68k_quick;
5369 s->rel32 = m68k_rel32;
5370 s->listing = listing;
5371 s->no_warnings = flag_no_warnings;
5372
5373 s->next = save_stack;
5374 save_stack = s;
5375
5376 demand_empty_rest_of_line ();
5377}
5378
5379/* The MRI RESTORE pseudo-op. */
5380
5381static void
5382s_restore (ignore)
5383 int ignore;
5384{
5385 struct save_opts *s;
5386
5387 if (save_stack == NULL)
5388 {
48401fcf 5389 as_bad (_("restore without save"));
e14994d9
ILT		 5390 ignore_rest_of_line ();
5391 return;
5392 }
5393
5394 s = save_stack;
5395 save_stack = s->next;
5396
5397 m68k_abspcadd = s->abspcadd;
5398 symbols_case_sensitive = s->symbols_case_sensitive;
5399 flag_keep_locals = s->keep_locals;
5400 flag_short_refs = s->short_refs;
5401 current_architecture = s->architecture;
5402 m68k_quick = s->quick;
5403 m68k_rel32 = s->rel32;
5404 listing = s->listing;
5405 flag_no_warnings = s->no_warnings;
5406
5407 free (s);
5408
5409 demand_empty_rest_of_line ();
5410}
b4ec75e0
ILT		 5411
5412/* Types of MRI structured control directives. */
5413
5414enum mri_control_type
5415{
5416 mri_for,
5417 mri_if,
5418 mri_repeat,
5419 mri_while
5420};
5421
5422/* This structure is used to stack the MRI structured control
5423 directives. */
5424
5425struct mri_control_info
5426{
5427 /* The directive within which this one is enclosed. */
5428 struct mri_control_info *outer;
5429
5430 /* The type of directive. */
5431 enum mri_control_type type;
5432
5433 /* Whether an ELSE has been in an IF. */
5434 int else_seen;
5435
5436 /* The add or sub statement at the end of a FOR. */
5437 char *incr;
5438
5439 /* The label of the top of a FOR or REPEAT loop. */
5440 char *top;
5441
5442 /* The label to jump to for the next iteration, or the else
5443 expression of a conditional. */
5444 char *next;
5445
5446 /* The label to jump to to break out of the loop, or the label past
5447 the end of a conditional. */
5448 char *bottom;
5449};
5450
5451/* The stack of MRI structured control directives. */
5452
5453static struct mri_control_info *mri_control_stack;
5454
5455/* The current MRI structured control directive index number, used to
5456 generate label names. */
5457
5458static int mri_control_index;
5459
5460/* Some function prototypes. */
5461
dcb76edb 5462static void mri_assemble PARAMS ((char *));
b4ec75e0
ILT		 5463static char *mri_control_label PARAMS ((void));
5464static struct mri_control_info *push_mri_control
5465 PARAMS ((enum mri_control_type));
5466static void pop_mri_control PARAMS ((void));
5467static int parse_mri_condition PARAMS ((int *));
5468static int parse_mri_control_operand
e1c0287d 5469 PARAMS ((int *, char **, char **, char **, char **));
b4ec75e0
ILT		 5470static int swap_mri_condition PARAMS ((int));
5471static int reverse_mri_condition PARAMS ((int));
5472static void build_mri_control_operand
e1c0287d
ILT		 5473 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5474 const char *, int));
b4ec75e0
ILT		 5475static void parse_mri_control_expression
5476 PARAMS ((char *, int, const char *, const char *, int));
5477
dcb76edb
ILT		 5478/* Assemble an instruction for an MRI structured control directive. */
5479
5480static void
5481mri_assemble (str)
5482 char *str;
5483{
5484 char *s;
5485
5486 /* md_assemble expects the opcode to be in lower case. */
5487 for (s = str; *s != ' ' && *s != '\0'; s++)
5488 {
5489 if (isupper ((unsigned char) *s))
5490 *s = tolower ((unsigned char) *s);
5491 }
5492
5493 md_assemble (str);
5494}
5495
b4ec75e0
ILT		 5496/* Generate a new MRI label structured control directive label name. */
5497
5498static char *
5499mri_control_label ()
5500{
5501 char *n;
5502
5503 n = (char *) xmalloc (20);
5504 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5505 ++mri_control_index;
5506 return n;
5507}
5508
5509/* Create a new MRI structured control directive. */
5510
5511static struct mri_control_info *
5512push_mri_control (type)
5513 enum mri_control_type type;
5514{
5515 struct mri_control_info *n;
5516
5517 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5518
5519 n->type = type;
5520 n->else_seen = 0;
5521 if (type == mri_if || type == mri_while)
5522 n->top = NULL;
5523 else
5524 n->top = mri_control_label ();
5525 n->next = mri_control_label ();
5526 n->bottom = mri_control_label ();
5527
5528 n->outer = mri_control_stack;
5529 mri_control_stack = n;
5530
5531 return n;
5532}
5533
5534/* Pop off the stack of MRI structured control directives. */
5535
5536static void
5537pop_mri_control ()
5538{
5539 struct mri_control_info *n;
5540
5541 n = mri_control_stack;
5542 mri_control_stack = n->outer;
5543 if (n->top != NULL)
5544 free (n->top);
5545 free (n->next);
5546 free (n->bottom);
5547 free (n);
5548}
5549
5550/* Recognize a condition code in an MRI structured control expression. */
5551
5552static int
5553parse_mri_condition (pcc)
5554 int *pcc;
5555{
5556 char c1, c2;
5557
5558 know (*input_line_pointer == '<');
5559
5560 ++input_line_pointer;
5561 c1 = *input_line_pointer++;
5562 c2 = *input_line_pointer++;
5563
5564 if (*input_line_pointer != '>')
5565 {
48401fcf 5566 as_bad (_("syntax error in structured control directive"));
b4ec75e0
ILT		 5567 return 0;
5568 }
5569
5570 ++input_line_pointer;
5571 SKIP_WHITESPACE ();
5572
5573 if (isupper (c1))
5574 c1 = tolower (c1);
5575 if (isupper (c2))
5576 c2 = tolower (c2);
5577
5578 *pcc = (c1 << 8) | c2;
5579
5580 return 1;
5581}
5582
5583/* Parse a single operand in an MRI structured control expression. */
5584
5585static int
5586parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5587 int *pcc;
b3625fe6 5588 char **leftstart;
e1c0287d 5589 char **leftstop;
b3625fe6 5590 char **rightstart;
e1c0287d 5591 char **rightstop;
b4ec75e0
ILT		 5592{
5593 char *s;
5594
5595 SKIP_WHITESPACE ();
5596
5597 *pcc = -1;
5598 *leftstart = NULL;
5599 *leftstop = NULL;
5600 *rightstart = NULL;
5601 *rightstop = NULL;
5602
5603 if (*input_line_pointer == '<')
5604 {
5605 /* It's just a condition code. */
5606 return parse_mri_condition (pcc);
5607 }
5608
5609 /* Look ahead for the condition code. */
5610 for (s = input_line_pointer; *s != '\0'; ++s)
5611 {
5612 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5613 break;
5614 }
5615 if (*s == '\0')
5616 {
48401fcf 5617 as_bad (_("missing condition code in structured control directive"));
b4ec75e0
ILT		 5618 return 0;
5619 }
5620
5621 *leftstart = input_line_pointer;
5622 *leftstop = s;
4026c122
ILT		 5623 if (*leftstop > *leftstart
5624 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5625 --*leftstop;
b4ec75e0
ILT		 5626
5627 input_line_pointer = s;
5628 if (! parse_mri_condition (pcc))
5629 return 0;
5630
5631 /* Look ahead for AND or OR or end of line. */
5632 for (s = input_line_pointer; *s != '\0'; ++s)
5633 {
5634 if ((strncasecmp (s, "AND", 3) == 0
5635 && (s[3] == '.' || ! is_part_of_name (s[3])))
5636 || (strncasecmp (s, "OR", 2) == 0
5637 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5638 break;
5639 }
5640
5641 *rightstart = input_line_pointer;
5642 *rightstop = s;
4026c122
ILT		 5643 if (*rightstop > *rightstart
5644 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5645 --*rightstop;
b4ec75e0
ILT		 5646
5647 input_line_pointer = s;
5648
5649 return 1;
5650}
5651
5652#define MCC(b1, b2) (((b1) << 8) | (b2))
5653
5654/* Swap the sense of a condition. This changes the condition so that
5655 it generates the same result when the operands are swapped. */
5656
5657static int
5658swap_mri_condition (cc)
5659 int cc;
5660{
5661 switch (cc)
5662 {
5663 case MCC ('h', 'i'): return MCC ('c', 's');
5664 case MCC ('l', 's'): return MCC ('c', 'c');
5665 case MCC ('c', 'c'): return MCC ('l', 's');
5666 case MCC ('c', 's'): return MCC ('h', 'i');
5667 case MCC ('p', 'l'): return MCC ('m', 'i');
5668 case MCC ('m', 'i'): return MCC ('p', 'l');
5669 case MCC ('g', 'e'): return MCC ('l', 'e');
5670 case MCC ('l', 't'): return MCC ('g', 't');
5671 case MCC ('g', 't'): return MCC ('l', 't');
5672 case MCC ('l', 'e'): return MCC ('g', 'e');
5673 }
5674 return cc;
5675}
5676
5677/* Reverse the sense of a condition. */
5678
5679static int
5680reverse_mri_condition (cc)
5681 int cc;
5682{
5683 switch (cc)
5684 {
5685 case MCC ('h', 'i'): return MCC ('l', 's');
5686 case MCC ('l', 's'): return MCC ('h', 'i');
5687 case MCC ('c', 'c'): return MCC ('c', 's');
5688 case MCC ('c', 's'): return MCC ('c', 'c');
5689 case MCC ('n', 'e'): return MCC ('e', 'q');
5690 case MCC ('e', 'q'): return MCC ('n', 'e');
5691 case MCC ('v', 'c'): return MCC ('v', 's');
5692 case MCC ('v', 's'): return MCC ('v', 'c');
5693 case MCC ('p', 'l'): return MCC ('m', 'i');
5694 case MCC ('m', 'i'): return MCC ('p', 'l');
5695 case MCC ('g', 'e'): return MCC ('l', 't');
5696 case MCC ('l', 't'): return MCC ('g', 'e');
5697 case MCC ('g', 't'): return MCC ('l', 'e');
5698 case MCC ('l', 'e'): return MCC ('g', 't');
5699 }
5700 return cc;
5701}
5702
5703/* Build an MRI structured control expression. This generates test
5704 and branch instructions. It goes to TRUELAB if the condition is
5705 true, and to FALSELAB if the condition is false. Exactly one of
5706 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5707 is the size qualifier for the expression. EXTENT is the size to
5708 use for the branch. */
5709
5710static void
5711build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5712 rightstop, truelab, falselab, extent)
5713 int qual;
5714 int cc;
b3625fe6 5715 char *leftstart;
e1c0287d 5716 char *leftstop;
b3625fe6 5717 char *rightstart;
e1c0287d 5718 char *rightstop;
b4ec75e0
ILT		 5719 const char *truelab;
5720 const char *falselab;
5721 int extent;
5722{
5723 char *buf;
5724 char *s;
5725
e1c0287d 5726 if (leftstart != NULL)
b3625fe6 5727 {
e1c0287d
ILT		 5728 struct m68k_op leftop, rightop;
5729 char c;
b3625fe6 5730
e1c0287d
ILT		 5731 /* Swap the compare operands, if necessary, to produce a legal
5732 m68k compare instruction. Comparing a register operand with
5733 a non-register operand requires the register to be on the
5734 right (cmp, cmpa). Comparing an immediate value with
5735 anything requires the immediate value to be on the left
5736 (cmpi). */
5737
5738 c = *leftstop;
5739 *leftstop = '\0';
5740 (void) m68k_ip_op (leftstart, &leftop);
5741 *leftstop = c;
5742
5743 c = *rightstop;
5744 *rightstop = '\0';
5745 (void) m68k_ip_op (rightstart, &rightop);
5746 *rightstop = c;
5747
5748 if (rightop.mode == IMMED
5749 || ((leftop.mode == DREG || leftop.mode == AREG)
5750 && (rightop.mode != DREG && rightop.mode != AREG)))
5751 {
5752 char *temp;
5753
5754 cc = swap_mri_condition (cc);
5755 temp = leftstart;
5756 leftstart = rightstart;
5757 rightstart = temp;
5758 temp = leftstop;
5759 leftstop = rightstop;
5760 rightstop = temp;
5761 }
b4ec75e0
ILT		 5762 }
5763
5764 if (truelab == NULL)
5765 {
5766 cc = reverse_mri_condition (cc);
5767 truelab = falselab;
5768 }
5769
5770 if (leftstart != NULL)
5771 {
5772 buf = (char *) xmalloc (20
5773 + (leftstop - leftstart)
5774 + (rightstop - rightstart));
5775 s = buf;
5776 *s++ = 'c';
5777 *s++ = 'm';
5778 *s++ = 'p';
5779 if (qual != '\0')
5780 *s++ = qual;
5781 *s++ = ' ';
5782 memcpy (s, leftstart, leftstop - leftstart);
5783 s += leftstop - leftstart;
5784 *s++ = ',';
5785 memcpy (s, rightstart, rightstop - rightstart);
5786 s += rightstop - rightstart;
5787 *s = '\0';
dcb76edb 5788 mri_assemble (buf);
b4ec75e0
ILT		 5789 free (buf);
5790 }
5791
5792 buf = (char *) xmalloc (20 + strlen (truelab));
5793 s = buf;
5794 *s++ = 'b';
5795 *s++ = cc >> 8;
5796 *s++ = cc & 0xff;
5797 if (extent != '\0')
5798 *s++ = extent;
5799 *s++ = ' ';
5800 strcpy (s, truelab);
dcb76edb 5801 mri_assemble (buf);
b4ec75e0
ILT		 5802 free (buf);
5803}
5804
5805/* Parse an MRI structured control expression. This generates test
5806 and branch instructions. STOP is where the expression ends. It
5807 goes to TRUELAB if the condition is true, and to FALSELAB if the
5808 condition is false. Exactly one of TRUELAB and FALSELAB will be
5809 NULL, meaning to fall through. QUAL is the size qualifier for the
5810 expression. EXTENT is the size to use for the branch. */
5811
5812static void
5813parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5814 char *stop;
5815 int qual;
5816 const char *truelab;
5817 const char *falselab;
5818 int extent;
5819{
5820 int c;
5821 int cc;
b3625fe6 5822 char *leftstart;
e1c0287d 5823 char *leftstop;
b3625fe6 5824 char *rightstart;
e1c0287d 5825 char *rightstop;
b4ec75e0
ILT		 5826
5827 c = *stop;
5828 *stop = '\0';
5829
5830 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5831 &rightstart, &rightstop))
5832 {
5833 *stop = c;
5834 return;
5835 }
5836
5837 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5838 {
5839 const char *flab;
5840
5841 if (falselab != NULL)
5842 flab = falselab;
5843 else
5844 flab = mri_control_label ();
5845
5846 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5847 rightstop, (const char *) NULL, flab, extent);
5848
5849 input_line_pointer += 3;
5850 if (*input_line_pointer != '.'
5851 || input_line_pointer[1] == '\0')
5852 qual = '\0';
5853 else
5854 {
5855 qual = input_line_pointer[1];
5856 input_line_pointer += 2;
5857 }
5858
5859 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5860 &rightstart, &rightstop))
5861 {
5862 *stop = c;
5863 return;
5864 }
5865
5866 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5867 rightstop, truelab, falselab, extent);
5868
5869 if (falselab == NULL)
5870 colon (flab);
5871 }
5872 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5873 {
5874 const char *tlab;
5875
5876 if (truelab != NULL)
5877 tlab = truelab;
5878 else
5879 tlab = mri_control_label ();
5880
5881 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5882 rightstop, tlab, (const char *) NULL, extent);
5883
5884 input_line_pointer += 2;
5885 if (*input_line_pointer != '.'
5886 || input_line_pointer[1] == '\0')
5887 qual = '\0';
5888 else
5889 {
5890 qual = input_line_pointer[1];
5891 input_line_pointer += 2;
5892 }
5893
5894 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5895 &rightstart, &rightstop))
5896 {
5897 *stop = c;
5898 return;
5899 }
5900
5901 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5902 rightstop, truelab, falselab, extent);
5903
5904 if (truelab == NULL)
5905 colon (tlab);
5906 }
5907 else
5908 {
5909 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5910 rightstop, truelab, falselab, extent);
5911 }
5912
5913 *stop = c;
5914 if (input_line_pointer != stop)
48401fcf 5915 as_bad (_("syntax error in structured control directive"));
b4ec75e0
ILT		 5916}
5917
5918/* Handle the MRI IF pseudo-op. This may be a structured control
5919 directive, or it may be a regular assembler conditional, depending
5920 on its operands. */
5921
5922static void
5923s_mri_if (qual)
5924 int qual;
5925{
5926 char *s;
5927 int c;
5928 struct mri_control_info *n;
5929
5930 /* A structured control directive must end with THEN with an
5931 optional qualifier. */
5932 s = input_line_pointer;
e1c0287d
ILT		 5933 while (! is_end_of_line[(unsigned char) *s]
5934 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 5935 ++s;
5936 --s;
5937 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5938 --s;
5939
5940 if (s - input_line_pointer > 1
5941 && s[-1] == '.')
5942 s -= 2;
5943
5944 if (s - input_line_pointer < 3
5945 || strncasecmp (s - 3, "THEN", 4) != 0)
5946 {
5947 if (qual != '\0')
5948 {
48401fcf 5949 as_bad (_("missing then"));
b4ec75e0
ILT		 5950 ignore_rest_of_line ();
5951 return;
5952 }
5953
5954 /* It's a conditional. */
5955 s_if (O_ne);
5956 return;
5957 }
5958
5959 /* Since this might be a conditional if, this pseudo-op will be
5960 called even if we are supported to be ignoring input. Double
5961 check now. Clobber *input_line_pointer so that ignore_input
5962 thinks that this is not a special pseudo-op. */
5963 c = *input_line_pointer;
5964 *input_line_pointer = 0;
5965 if (ignore_input ())
5966 {
5967 *input_line_pointer = c;
5968 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5969 ++input_line_pointer;
5970 demand_empty_rest_of_line ();
5971 return;
5972 }
5973 *input_line_pointer = c;
5974
5975 n = push_mri_control (mri_if);
5976
5977 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5978 n->next, s[1] == '.' ? s[2] : '\0');
5979
5980 if (s[1] == '.')
5981 input_line_pointer = s + 3;
5982 else
5983 input_line_pointer = s + 1;
5984
e1c0287d
ILT		 5985 if (flag_mri)
5986 {
5987 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5988 ++input_line_pointer;
5989 }
5990
b4ec75e0
ILT		 5991 demand_empty_rest_of_line ();
5992}
5993
5994/* Handle the MRI else pseudo-op. If we are currently doing an MRI
5995 structured IF, associate the ELSE with the IF. Otherwise, assume
5996 it is a conditional else. */
5997
5998static void
5999s_mri_else (qual)
6000 int qual;
6001{
6002 int c;
6003 char *buf;
6004 char q[2];
6005
6006 if (qual == '\0'
6007 && (mri_control_stack == NULL
6008 || mri_control_stack->type != mri_if
6009 || mri_control_stack->else_seen))
6010 {
6011 s_else (0);
6012 return;
6013 }
6014
6015 c = *input_line_pointer;
6016 *input_line_pointer = 0;
6017 if (ignore_input ())
6018 {
6019 *input_line_pointer = c;
6020 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6021 ++input_line_pointer;
6022 demand_empty_rest_of_line ();
6023 return;
6024 }
6025 *input_line_pointer = c;
6026
6027 if (mri_control_stack == NULL
6028 || mri_control_stack->type != mri_if
6029 || mri_control_stack->else_seen)
6030 {
48401fcf 6031 as_bad (_("else without matching if"));
b4ec75e0
ILT		 6032 ignore_rest_of_line ();
6033 return;
6034 }
6035
6036 mri_control_stack->else_seen = 1;
6037
6038 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6039 q[0] = qual;
6040 q[1] = '\0';
6041 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
dcb76edb 6042 mri_assemble (buf);
b4ec75e0
ILT		 6043 free (buf);
6044
6045 colon (mri_control_stack->next);
6046
e1c0287d
ILT		 6047 if (flag_mri)
6048 {
6049 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6050 ++input_line_pointer;
6051 }
6052
b4ec75e0
ILT		 6053 demand_empty_rest_of_line ();
6054}
6055
6056/* Handle the MRI ENDI pseudo-op. */
6057
6058static void
6059s_mri_endi (ignore)
6060 int ignore;
6061{
6062 if (mri_control_stack == NULL
6063 || mri_control_stack->type != mri_if)
6064 {
48401fcf 6065 as_bad (_("endi without matching if"));
b4ec75e0
ILT		 6066 ignore_rest_of_line ();
6067 return;
6068 }
6069
6070 /* ignore_input will not return true for ENDI, so we don't need to
6071 worry about checking it again here. */
6072
6073 if (! mri_control_stack->else_seen)
6074 colon (mri_control_stack->next);
6075 colon (mri_control_stack->bottom);
6076
6077 pop_mri_control ();
6078
e1c0287d
ILT		 6079 if (flag_mri)
6080 {
6081 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6082 ++input_line_pointer;
6083 }
6084
b4ec75e0
ILT		 6085 demand_empty_rest_of_line ();
6086}
6087
6088/* Handle the MRI BREAK pseudo-op. */
6089
6090static void
6091s_mri_break (extent)
6092 int extent;
6093{
6094 struct mri_control_info *n;
6095 char *buf;
6096 char ex[2];
6097
6098 n = mri_control_stack;
6099 while (n != NULL
6100 && n->type != mri_for
6101 && n->type != mri_repeat
6102 && n->type != mri_while)
6103 n = n->outer;
6104 if (n == NULL)
6105 {
48401fcf 6106 as_bad (_("break outside of structured loop"));
b4ec75e0
ILT		 6107 ignore_rest_of_line ();
6108 return;
6109 }
6110
6111 buf = (char *) xmalloc (20 + strlen (n->bottom));
6112 ex[0] = extent;
6113 ex[1] = '\0';
6114 sprintf (buf, "bra%s %s", ex, n->bottom);
dcb76edb 6115 mri_assemble (buf);
b4ec75e0
ILT		 6116 free (buf);
6117
e1c0287d
ILT		 6118 if (flag_mri)
6119 {
6120 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6121 ++input_line_pointer;
6122 }
6123
b4ec75e0
ILT		 6124 demand_empty_rest_of_line ();
6125}
6126
6127/* Handle the MRI NEXT pseudo-op. */
6128
6129static void
6130s_mri_next (extent)
6131 int extent;
6132{
6133 struct mri_control_info *n;
6134 char *buf;
6135 char ex[2];
6136
6137 n = mri_control_stack;
6138 while (n != NULL
6139 && n->type != mri_for
6140 && n->type != mri_repeat
6141 && n->type != mri_while)
6142 n = n->outer;
6143 if (n == NULL)
6144 {
48401fcf 6145 as_bad (_("next outside of structured loop"));
b4ec75e0
ILT		 6146 ignore_rest_of_line ();
6147 return;
6148 }
6149
6150 buf = (char *) xmalloc (20 + strlen (n->next));
6151 ex[0] = extent;
6152 ex[1] = '\0';
6153 sprintf (buf, "bra%s %s", ex, n->next);
dcb76edb 6154 mri_assemble (buf);
b4ec75e0
ILT		 6155 free (buf);
6156
e1c0287d
ILT		 6157 if (flag_mri)
6158 {
6159 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6160 ++input_line_pointer;
6161 }
6162
b4ec75e0
ILT		 6163 demand_empty_rest_of_line ();
6164}
6165
6166/* Handle the MRI FOR pseudo-op. */
6167
6168static void
6169s_mri_for (qual)
6170 int qual;
6171{
6172 const char *varstart, *varstop;
6173 const char *initstart, *initstop;
6174 const char *endstart, *endstop;
6175 const char *bystart, *bystop;
6176 int up;
6177 int by;
6178 int extent;
6179 struct mri_control_info *n;
6180 char *buf;
6181 char *s;
6182 char ex[2];
6183
6184 /* The syntax is
6185 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6186 */
6187
4026c122 6188 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6189 varstart = input_line_pointer;
6190
6191 /* Look for the '='. */
6192 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6193 && *input_line_pointer != '=')
6194 ++input_line_pointer;
6195 if (*input_line_pointer != '=')
6196 {
48401fcf 6197 as_bad (_("missing ="));
b4ec75e0
ILT		 6198 ignore_rest_of_line ();
6199 return;
6200 }
6201
6202 varstop = input_line_pointer;
4026c122
ILT		 6203 if (varstop > varstart
6204 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6205 --varstop;
b4ec75e0
ILT		 6206
6207 ++input_line_pointer;
6208
6209 initstart = input_line_pointer;
6210
6211 /* Look for TO or DOWNTO. */
6212 up = 1;
6213 initstop = NULL;
6214 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6215 {
6216 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6217 && ! is_part_of_name (input_line_pointer[2]))
6218 {
6219 initstop = input_line_pointer;
6220 input_line_pointer += 2;
6221 break;
6222 }
6223 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6224 && ! is_part_of_name (input_line_pointer[6]))
6225 {
6226 initstop = input_line_pointer;
6227 up = 0;
6228 input_line_pointer += 6;
6229 break;
6230 }
6231 ++input_line_pointer;
6232 }
6233 if (initstop == NULL)
6234 {
48401fcf 6235 as_bad (_("missing to or downto"));
b4ec75e0
ILT		 6236 ignore_rest_of_line ();
6237 return;
6238 }
4026c122
ILT		 6239 if (initstop > initstart
6240 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6241 --initstop;
b4ec75e0 6242
4026c122 6243 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6244 endstart = input_line_pointer;
6245
6246 /* Look for BY or DO. */
6247 by = 0;
6248 endstop = NULL;
6249 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6250 {
6251 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6252 && ! is_part_of_name (input_line_pointer[2]))
6253 {
6254 endstop = input_line_pointer;
6255 by = 1;
6256 input_line_pointer += 2;
6257 break;
6258 }
6259 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6260 && (input_line_pointer[2] == '.'
6261 || ! is_part_of_name (input_line_pointer[2])))
6262 {
6263 endstop = input_line_pointer;
6264 input_line_pointer += 2;
6265 break;
6266 }
6267 ++input_line_pointer;
6268 }
6269 if (endstop == NULL)
6270 {
48401fcf 6271 as_bad (_("missing do"));
b4ec75e0
ILT		 6272 ignore_rest_of_line ();
6273 return;
6274 }
4026c122
ILT		 6275 if (endstop > endstart
6276 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6277 --endstop;
b4ec75e0
ILT		 6278
6279 if (! by)
6280 {
6281 bystart = "#1";
6282 bystop = bystart + 2;
6283 }
6284 else
6285 {
4026c122 6286 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6287 bystart = input_line_pointer;
6288
6289 /* Look for DO. */
6290 bystop = NULL;
6291 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6292 {
6293 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6294 && (input_line_pointer[2] == '.'
6295 || ! is_part_of_name (input_line_pointer[2])))
6296 {
6297 bystop = input_line_pointer;
6298 input_line_pointer += 2;
6299 break;
6300 }
6301 ++input_line_pointer;
6302 }
6303 if (bystop == NULL)
6304 {
48401fcf 6305 as_bad (_("missing do"));
b4ec75e0
ILT		 6306 ignore_rest_of_line ();
6307 return;
6308 }
4026c122
ILT		 6309 if (bystop > bystart
6310 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6311 --bystop;
b4ec75e0
ILT		 6312 }
6313
6314 if (*input_line_pointer != '.')
6315 extent = '\0';
6316 else
6317 {
6318 extent = input_line_pointer[1];
6319 input_line_pointer += 2;
6320 }
6321
6322 /* We have fully parsed the FOR operands. Now build the loop. */
6323
6324 n = push_mri_control (mri_for);
6325
6326 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6327
6328 /* move init,var */
6329 s = buf;
6330 *s++ = 'm';
6331 *s++ = 'o';
6332 *s++ = 'v';
6333 *s++ = 'e';
6334 if (qual != '\0')
6335 *s++ = qual;
6336 *s++ = ' ';
6337 memcpy (s, initstart, initstop - initstart);
6338 s += initstop - initstart;
6339 *s++ = ',';
6340 memcpy (s, varstart, varstop - varstart);
6341 s += varstop - varstart;
6342 *s = '\0';
dcb76edb 6343 mri_assemble (buf);
b4ec75e0
ILT		 6344
6345 colon (n->top);
6346
6347 /* cmp end,var */
6348 s = buf;
6349 *s++ = 'c';
6350 *s++ = 'm';
6351 *s++ = 'p';
6352 if (qual != '\0')
6353 *s++ = qual;
6354 *s++ = ' ';
6355 memcpy (s, endstart, endstop - endstart);
6356 s += endstop - endstart;
6357 *s++ = ',';
6358 memcpy (s, varstart, varstop - varstart);
6359 s += varstop - varstart;
6360 *s = '\0';
dcb76edb 6361 mri_assemble (buf);
b4ec75e0
ILT		 6362
6363 /* bcc bottom */
6364 ex[0] = extent;
6365 ex[1] = '\0';
6366 if (up)
6367 sprintf (buf, "blt%s %s", ex, n->bottom);
6368 else
6369 sprintf (buf, "bgt%s %s", ex, n->bottom);
dcb76edb 6370 mri_assemble (buf);
b4ec75e0
ILT		 6371
6372 /* Put together the add or sub instruction used by ENDF. */
6373 s = buf;
6374 if (up)
6375 strcpy (s, "add");
6376 else
6377 strcpy (s, "sub");
6378 s += 3;
6379 if (qual != '\0')
6380 *s++ = qual;
6381 *s++ = ' ';
6382 memcpy (s, bystart, bystop - bystart);
6383 s += bystop - bystart;
6384 *s++ = ',';
6385 memcpy (s, varstart, varstop - varstart);
6386 s += varstop - varstart;
6387 *s = '\0';
6388 n->incr = buf;
6389
e1c0287d
ILT		 6390 if (flag_mri)
6391 {
6392 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6393 ++input_line_pointer;
6394 }
6395
b4ec75e0
ILT		 6396 demand_empty_rest_of_line ();
6397}
6398
6399/* Handle the MRI ENDF pseudo-op. */
6400
6401static void
6402s_mri_endf (ignore)
6403 int ignore;
6404{
6405 if (mri_control_stack == NULL
6406 || mri_control_stack->type != mri_for)
6407 {
48401fcf 6408 as_bad (_("endf without for"));
b4ec75e0
ILT		 6409 ignore_rest_of_line ();
6410 return;
6411 }
6412
6413 colon (mri_control_stack->next);
6414
dcb76edb 6415 mri_assemble (mri_control_stack->incr);
b4ec75e0
ILT		 6416
6417 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
dcb76edb 6418 mri_assemble (mri_control_stack->incr);
b4ec75e0
ILT		 6419
6420 free (mri_control_stack->incr);
6421
6422 colon (mri_control_stack->bottom);
6423
6424 pop_mri_control ();
6425
e1c0287d
ILT		 6426 if (flag_mri)
6427 {
6428 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6429 ++input_line_pointer;
6430 }
6431
b4ec75e0
ILT		 6432 demand_empty_rest_of_line ();
6433}
6434
6435/* Handle the MRI REPEAT pseudo-op. */
6436
6437static void
6438s_mri_repeat (ignore)
6439 int ignore;
6440{
6441 struct mri_control_info *n;
6442
6443 n = push_mri_control (mri_repeat);
6444 colon (n->top);
e1c0287d
ILT		 6445 if (flag_mri)
6446 {
6447 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6448 ++input_line_pointer;
6449 }
b4ec75e0
ILT		 6450 demand_empty_rest_of_line ();
6451}
6452
6453/* Handle the MRI UNTIL pseudo-op. */
6454
6455static void
6456s_mri_until (qual)
6457 int qual;
6458{
6459 char *s;
6460
6461 if (mri_control_stack == NULL
6462 || mri_control_stack->type != mri_repeat)
6463 {
48401fcf 6464 as_bad (_("until without repeat"));
b4ec75e0
ILT		 6465 ignore_rest_of_line ();
6466 return;
6467 }
6468
6469 colon (mri_control_stack->next);
6470
6471 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6472 ;
6473
6474 parse_mri_control_expression (s, qual, (const char *) NULL,
6475 mri_control_stack->top, '\0');
6476
6477 colon (mri_control_stack->bottom);
6478
6479 input_line_pointer = s;
6480
9e64486e
ILT		 6481 pop_mri_control ();
6482
e1c0287d
ILT		 6483 if (flag_mri)
6484 {
6485 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6486 ++input_line_pointer;
6487 }
6488
b4ec75e0
ILT		 6489 demand_empty_rest_of_line ();
6490}
6491
6492/* Handle the MRI WHILE pseudo-op. */
6493
6494static void
6495s_mri_while (qual)
6496 int qual;
6497{
6498 char *s;
6499
6500 struct mri_control_info *n;
6501
6502 s = input_line_pointer;
e1c0287d
ILT		 6503 while (! is_end_of_line[(unsigned char) *s]
6504 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 6505 s++;
6506 --s;
6507 while (*s == ' ' || *s == '\t')
6508 --s;
6509 if (s - input_line_pointer > 1
6510 && s[-1] == '.')
6511 s -= 2;
6512 if (s - input_line_pointer < 2
6513 || strncasecmp (s - 1, "DO", 2) != 0)
6514 {
48401fcf 6515 as_bad (_("missing do"));
b4ec75e0
ILT		 6516 ignore_rest_of_line ();
6517 return;
6518 }
6519
6520 n = push_mri_control (mri_while);
6521
6522 colon (n->next);
6523
6524 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6525 s[1] == '.' ? s[2] : '\0');
6526
6527 input_line_pointer = s + 1;
6528 if (*input_line_pointer == '.')
6529 input_line_pointer += 2;
6530
e1c0287d
ILT		 6531 if (flag_mri)
6532 {
6533 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6534 ++input_line_pointer;
6535 }
6536
b4ec75e0
ILT		 6537 demand_empty_rest_of_line ();
6538}
6539
6540/* Handle the MRI ENDW pseudo-op. */
6541
6542static void
6543s_mri_endw (ignore)
6544 int ignore;
6545{
6546 char *buf;
6547
6548 if (mri_control_stack == NULL
6549 || mri_control_stack->type != mri_while)
6550 {
48401fcf 6551 as_bad (_("endw without while"));
b4ec75e0
ILT		 6552 ignore_rest_of_line ();
6553 return;
6554 }
6555
6556 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6557 sprintf (buf, "bra %s", mri_control_stack->next);
dcb76edb 6558 mri_assemble (buf);
b4ec75e0
ILT		 6559 free (buf);
6560
6561 colon (mri_control_stack->bottom);
6562
6563 pop_mri_control ();
6564
e1c0287d
ILT		 6565 if (flag_mri)
6566 {
6567 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6568 ++input_line_pointer;
6569 }
6570
b4ec75e0
ILT		 6571 demand_empty_rest_of_line ();
6572}
f3d817d8 6573\f
7c15cbe8
RP		 6574/*
6575 * md_parse_option
6576 * Invocation line includes a switch not recognized by the base assembler.
6577 * See if it's a processor-specific option. These are:
6578 *
6579 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6580 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6581 * Select the architecture. Instructions or features not
6582 * supported by the selected architecture cause fatal
6583 * errors. More than one may be specified. The default is
6584 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6585 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 6586 * -[A]m[c]no-68851, -[A]m[c]no-68881
6587 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6588 * so don't use or document it, but that's the way the parsing
6589 * works).
7c15cbe8 6590 *
dff60b7d
ILT		 6591 * -pic Indicates PIC.
6592 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 6593 *
8d20a0a8
C		 6594 * --bitwise-or
6595 * Permit `|' to be used in expressions.
6596 *
7c15cbe8
RP		 6597 */
6598
5f8cb05e
ILT		 6599#ifdef OBJ_ELF
6600CONST char *md_shortopts = "lSA:m:kQ:V";
6601#else
f3d817d8 6602CONST char *md_shortopts = "lSA:m:k";
5f8cb05e
ILT		 6603#endif
6604
f3d817d8
DM		 6605struct option md_longopts[] = {
6606#define OPTION_PIC (OPTION_MD_BASE)
6607 {"pic", no_argument, NULL, OPTION_PIC},
6608#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6609 {"register-prefix-optional", no_argument, NULL,
6610 OPTION_REGISTER_PREFIX_OPTIONAL},
8d20a0a8
C		 6611#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6612 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
b4d51f3d
ILT		 6613#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6614 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6615#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6616 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
924160b0
ILT		 6617#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6618 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6619#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6620 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
f3d817d8
DM		 6621 {NULL, no_argument, NULL, 0}
6622};
6623size_t md_longopts_size = sizeof(md_longopts);
82489ea0 6624
355afbcd 6625int
f3d817d8
DM		 6626md_parse_option (c, arg)
6627 int c;
6628 char *arg;
fecd2382 6629{
f3d817d8 6630 switch (c)
355afbcd
KR		 6631 {
6632 case 'l': /* -l means keep external to 2 bit offset
e284846a 6633 rather than 16 bit one */
9ad5755f 6634 flag_short_refs = 1;
355afbcd 6635 break;
6d27d3a2 6636
e284846a
KR		 6637 case 'S': /* -S means that jbsr's always turn into
6638 jsr's. */
9ad5755f 6639 flag_long_jumps = 1;
355afbcd 6640 break;
6d27d3a2 6641
355afbcd 6642 case 'A':
f3d817d8
DM		 6643 if (*arg == 'm')
6644 arg++;
355afbcd
KR		 6645 /* intentional fall-through */
6646 case 'm':
355afbcd 6647
b79de3a1 6648 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
e284846a 6649 {
064ba683
ILT		 6650 int i;
6651 unsigned long arch;
b79de3a1
KR		 6652 const char *oarg = arg;
6653
6654 arg += 3;
6655 if (*arg == 'm')
6656 {
6657 arg++;
6658 if (arg[0] == 'c' && arg[1] == '6')
6659 arg++;
6660 }
6661 for (i = 0; i < n_archs; i++)
6662 if (!strcmp (arg, archs[i].name))
6663 break;
6664 if (i == n_archs)
6665 {
6666 unknown:
48401fcf 6667 as_bad (_("unrecognized option `%s'"), oarg);
b79de3a1
KR		 6668 return 0;
6669 }
6670 arch = archs[i].arch;
6671 if (arch == m68881)
6672 no_68881 = 1;
6673 else if (arch == m68851)
6674 no_68851 = 1;
6675 else
6676 goto unknown;
355afbcd
KR		 6677 }
6678 else
6679 {
b79de3a1
KR		 6680 int i;
6681
6682 if (arg[0] == 'c' && arg[1] == '6')
6683 arg++;
6684
6685 for (i = 0; i < n_archs; i++)
6686 if (!strcmp (arg, archs[i].name))
6687 {
6688 unsigned long arch = archs[i].arch;
6689 if (cpu_of_arch (arch))
6690 /* It's a cpu spec. */
6691 {
6692 current_architecture &= ~m68000up;
6693 current_architecture |= arch;
6694 }
6695 else if (arch == m68881)
6696 {
6697 current_architecture |= m68881;
6698 no_68881 = 0;
6699 }
6700 else if (arch == m68851)
6701 {
6702 current_architecture |= m68851;
6703 no_68851 = 0;
6704 }
6705 else
6706 /* ??? */
6707 abort ();
6708 break;
6709 }
6710 if (i == n_archs)
6711 {
48401fcf 6712 as_bad (_("unrecognized architecture specification `%s'"), arg);
b79de3a1
KR		 6713 return 0;
6714 }
f8701a3f 6715 }
f3d817d8 6716 break;
dff60b7d 6717
f3d817d8 6718 case OPTION_PIC:
dff60b7d
ILT		 6719 case 'k':
6720 flag_want_pic = 1;
f3d817d8
DM		 6721 break; /* -pic, Position Independent Code */
6722
6723 case OPTION_REGISTER_PREFIX_OPTIONAL:
6724 flag_reg_prefix_optional = 1;
20710f1c 6725 reg_prefix_optional_seen = 1;
dff60b7d 6726 break;
355afbcd 6727
a043f579 6728 /* -V: SVR4 argument to print version ID. */
5f8cb05e 6729 case 'V':
a043f579
ILT		 6730 print_version_id ();
6731 break;
6732
6733 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6734 should be emitted or not. FIXME: Not implemented. */
6735 case 'Q':
5f8cb05e
ILT		 6736 break;
6737
8d20a0a8
C		 6738 case OPTION_BITWISE_OR:
6739 {
6740 char *n, *t;
6741 const char *s;
6742
6743 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6744 t = n;
6745 for (s = m68k_comment_chars; *s != '\0'; s++)
6746 if (*s != '|')
6747 *t++ = *s;
6748 *t = '\0';
6749 m68k_comment_chars = n;
6750 }
6751 break;
6752
b4d51f3d
ILT		 6753 case OPTION_BASE_SIZE_DEFAULT_16:
6754 m68k_index_width_default = SIZE_WORD;
6755 break;
6756
6757 case OPTION_BASE_SIZE_DEFAULT_32:
6758 m68k_index_width_default = SIZE_LONG;
6759 break;
6760
924160b0
ILT		 6761 case OPTION_DISP_SIZE_DEFAULT_16:
6762 m68k_rel32 = 0;
6763 m68k_rel32_from_cmdline = 1;
6764 break;
6765
6766 case OPTION_DISP_SIZE_DEFAULT_32:
6767 m68k_rel32 = 1;
6768 m68k_rel32_from_cmdline = 1;
6769 break;
6770
355afbcd
KR		 6771 default:
6772 return 0;
6773 }
f3d817d8 6774
355afbcd 6775 return 1;
fecd2382
RP		 6776}
6777
f3d817d8
DM		 6778void
6779md_show_usage (stream)
6780 FILE *stream;
6781{
48401fcf 6782 fprintf(stream, _("\
f3d817d8
DM		 6783680X0 options:\n\
6784-l use 1 word for refs to undefined symbols [default 2]\n\
5f8cb05e
ILT		 6785-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6786 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
7f003b7f 6787 | -mcpu32 | -m5200\n\
f3d817d8
DM		 6788 specify variant of 680X0 architecture [default 68020]\n\
6789-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6790 target has/lacks floating-point coprocessor\n\
48401fcf
TT		 6791 [default yes for 68020, 68030, and cpu32]\n"));
6792 fprintf(stream, _("\
f3d817d8
DM		 6793-m68851 | -mno-68851\n\
6794 target has/lacks memory-management unit coprocessor\n\
6795 [default yes for 68020 and up]\n\
6796-pic, -k generate position independent code\n\
6797-S turn jbsr into jsr\n\
6798--register-prefix-optional\n\
8d20a0a8 6799 recognize register names without prefix character\n\
48401fcf
TT		 6800--bitwise-or do not treat `|' as a comment character\n"));
6801 fprintf (stream, _("\
b4d51f3d 6802--base-size-default-16 base reg without size is 16 bits\n\
924160b0
ILT		 6803--base-size-default-32 base reg without size is 32 bits (default)\n\
6804--disp-size-default-16 displacement with unknown size is 16 bits\n\
48401fcf 6805--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
f3d817d8
DM		 6806}
6807\f
fecd2382
RP		 6808#ifdef TEST2
6809
6810/* TEST2: Test md_assemble() */
6811/* Warning, this routine probably doesn't work anymore */
6812
355afbcd 6813main ()
fecd2382 6814{
355afbcd
KR		 6815 struct m68k_it the_ins;
6816 char buf[120];
6817 char *cp;
6818 int n;
6819
6820 m68k_ip_begin ();
6821 for (;;)
6822 {
6823 if (!gets (buf) || !*buf)
6824 break;
6825 if (buf[0] == '|' || buf[1] == '.')
6826 continue;
6827 for (cp = buf; *cp; cp++)
6828 if (*cp == '\t')
6829 *cp = ' ';
6830 if (is_label (buf))
6831 continue;
6832 memset (&the_ins, '\0', sizeof (the_ins));
6833 m68k_ip (&the_ins, buf);
6834 if (the_ins.error)
6835 {
48401fcf 6836 printf (_("Error %s in %s\n"), the_ins.error, buf);
355afbcd
KR		 6837 }
6838 else
6839 {
48401fcf 6840 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
355afbcd
KR		 6841 for (n = 0; n < the_ins.numo; n++)
6842 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6843 printf (" ");
6844 print_the_insn (&the_ins.opcode[0], stdout);
6845 (void) putchar ('\n');
6846 }
6847 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6848 {
6849 if (the_ins.operands[n].error)
6850 {
6851 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6852 continue;
6853 }
6854 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6855 if (the_ins.operands[n].b_const)
6856 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6857 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6858 if (the_ins.operands[n].b_iadd)
6859 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6860 (void) putchar ('\n');
a39116f1 6861 }
355afbcd
KR		 6862 }
6863 m68k_ip_end ();
6864 return 0;
fecd2382
RP		 6865}
6866
355afbcd
KR		 6867is_label (str)
6868 char *str;
fecd2382 6869{
355afbcd
KR		 6870 while (*str == ' ')
6871 str++;
6872 while (*str && *str != ' ')
6873 str++;
6874 if (str[-1] == ':' || str[1] == '=')
6875 return 1;
6876 return 0;
fecd2382
RP		 6877}
6878
6879#endif
6880
6881/* Possible states for relaxation:
6d27d3a2 6882
a39116f1
RP		 6883 0 0 branch offset byte (bra, etc)
6884 0 1 word
6885 0 2 long
6d27d3a2 6886
a39116f1
RP		 6887 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6888 1 1 word
6889 1 2 long
6d27d3a2 6890
a39116f1
RP		 6891 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6892 2 1 word-long
6893 2 2 long-word
6894 2 3 long-long
6d27d3a2 6895
a39116f1 6896 */
fecd2382 6897
fecd2382
RP		 6898/* We have no need to default values of symbols. */
6899
6900/* ARGSUSED */
6901symbolS *
355afbcd
KR		 6902md_undefined_symbol (name)
6903 char *name;
fecd2382 6904{
355afbcd 6905 return 0;
fecd2382
RP		 6906}
6907
fecd2382 6908/* Round up a section size to the appropriate boundary. */
025b0302 6909valueT
355afbcd
KR		 6910md_section_align (segment, size)
6911 segT segment;
025b0302 6912 valueT size;
fecd2382 6913{
af438bdb
ILT		 6914#ifdef OBJ_AOUT
6915#ifdef BFD_ASSEMBLER
6916 /* For a.out, force the section size to be aligned. If we don't do
6917 this, BFD will align it for us, but it will not write out the
6918 final bytes of the section. This may be a bug in BFD, but it is
6919 easier to fix it here since that is how the other a.out targets
6920 work. */
6921 int align;
6922
6923 align = bfd_get_section_alignment (stdoutput, segment);
6924 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6925#endif
6926#endif
6927
6928 return size;
fecd2382
RP		 6929}
6930
6931/* Exactly what point is a PC-relative offset relative TO?
5f8cb05e
ILT		 6932 On the 68k, it is relative to the address of the first extension
6933 word. The difference between the addresses of the offset and the
6934 first extension word is stored in fx_pcrel_adjust. */
fecd2382 6935long
355afbcd
KR		 6936md_pcrel_from (fixP)
6937 fixS *fixP;
fecd2382 6938{
b4ec75e0
ILT		 6939 int adjust;
6940
6941 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6942 -1 as 64. */
6943 adjust = fixP->fx_pcrel_adjust;
6944 if (adjust == 64)
6945 adjust = -1;
6946 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
fecd2382
RP		 6947}
6948
49864cfa 6949#ifndef BFD_ASSEMBLER
af438bdb
ILT		 6950#ifdef OBJ_COFF
6951
9ad5755f 6952/*ARGSUSED*/
355afbcd 6953void
9ad5755f
KR		 6954tc_coff_symbol_emit_hook (ignore)
6955 symbolS *ignore;
3ad9ec6a
ILT		 6956{
6957}
6958
355afbcd
KR		 6959int
6960tc_coff_sizemachdep (frag)
6961 fragS *frag;
3ad9ec6a 6962{
355afbcd
KR		 6963 switch (frag->fr_subtype & 0x3)
6964 {
6965 case BYTE:
6966 return 1;
6967 case SHORT:
6968 return 2;
6969 case LONG:
6970 return 4;
6971 default:
6972 abort ();
064ba683 6973 return 0;
355afbcd 6974 }
3ad9ec6a 6975}
af438bdb
ILT		 6976
6977#endif
49864cfa 6978#endif
355afbcd 6979
fecd2382 6980/* end of tc-m68k.c */
GDB Binutils - Deliverables
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